Physics-based process modeling, reliability prediction, and design guidelines for flip-chip devices

NASA Astrophysics Data System (ADS)

Michaelides, Stylianos

Flip Chip on Board (FCOB) and Chip-Scale Packages (CSPs) are relatively new technologies that are being increasingly used in the electronic packaging industry. Compared to the more widely used face-up wirebonding and TAB technologies, flip-chips and most CSPs provide the shortest possible leads, lower inductance, higher frequency, better noise control, higher density, greater input/output (I/O), smaller device footprint and lower profile. However, due to the short history and due to the introduction of several new electronic materials, designs, and processing conditions, very limited work has been done to understand the role of material, geometry, and processing parameters on the reliability of flip-chip devices. Also, with the ever-increasing complexity of semiconductor packages and with the continued reduction in time to market, it is too costly to wait until the later stages of design and testing to discover that the reliability is not satisfactory. The objective of the research is to develop integrated process-reliability models that will take into consideration the mechanics of assembly processes to be able to determine the reliability of face-down devices under thermal cycling and long-term temperature dwelling. The models incorporate the time and temperature-dependent constitutive behavior of various materials in the assembly to be able to predict failure modes such as die cracking and solder cracking. In addition, the models account for process-induced defects and macro-micro features of the assembly. Creep-fatigue and continuum-damage mechanics models for the solder interconnects and fracture-mechanics models for the die have been used to determine the reliability of the devices. The results predicted by the models have been successfully validated against experimental data. The validated models have been used to develop qualification and test procedures for implantable medical devices. In addition, the research has helped develop innovative face-down devices without the underfill, based on the thorough understanding of the failure modes. Also, practical design guidelines for material, geometry and process parameters for reliable flip-chip devices have been developed.

High-sensitivity low-noise miniature fluxgate magnetometers using a flip chip conceptual design.

PubMed

Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

2014-07-30

This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current "flip chip" concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or "responsivity" for magnetometers) and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz) magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz(1/2) at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market.

Broad Frequency LTCC Vertical Interconnect Transition for Multichip Modules and System on Package Applications

NASA Technical Reports Server (NTRS)

Decrossas, Emmanuel; Glover, Michael D.; Porter, Kaoru; Cannon, Tom; Mantooth, H. Alan; Hamilton, M. C.

2013-01-01

Various stripline structures and flip chip interconnect designs for high-speed digital communication systems implemented in low temperature co-fired ceramic (LTCC) substrates are studied in this paper. Specifically, two different transition designs from edge launch 2.4 millimeter connectors to stripline transmission lines embedded in LTCC are discussed. After characterizing the DuPont (sup trademark) 9K7 green tape, different designs are proposed to improve signal integrity for high-speed digital data. The full-wave simulations and experimental data validate the presented designs over a broad frequency band from Direct Current to 50 gigahertz and beyond.

Detection of solder bump defects on a flip chip using vibration analysis

NASA Astrophysics Data System (ADS)

Liu, Junchao; Shi, Tielin; Xia, Qi; Liao, Guanglan

2012-03-01

Flip chips are widely used in microelectronics packaging owing to the high demand of integration in IC fabrication. Solder bump defects on flip chips are difficult to detect, because the solder bumps are obscured by the chip and substrate. In this paper a nondestructive detection method combining ultrasonic excitation with vibration analysis is presented for detecting missing solder bumps, which is a typical defect in flip chip packaging. The flip chip analytical model is revised by considering the influence of spring mass on mechanical energy of the system. This revised model is then applied to estimate the flip chip resonance frequencies. We use an integrated signal generator and power amplifier together with an air-coupled ultrasonic transducer to excite the flip chips. The vibrations are measured by a laser scanning vibrometer to detect the resonance frequencies. A sensitivity coefficient is proposed to select the sensitive resonance frequency order for defect detection. Finite element simulation is also implemented for further investigation. The results of analytical computation, experiment, and simulation prove the efficacy of the revised flip chip analytical model and verify the effectiveness of this detection method. Therefore, it may provide a guide for the improvement and innovation of the flip chip on-line inspection systems.

Flip-chip light emitting diode with resonant optical microcavity

DOEpatents

Gee, James M.; Bogart, Katherine H.A.; Fischer, Arthur J.

2005-11-29

A flip-chip light emitting diode with enhanced efficiency. The device structure employs a microcavity structure in a flip-chip configuration. The microcavity enhances the light emission in vertical modes, which are readily extracted from the device. Most of the rest of the light is emitted into waveguided lateral modes. Flip-chip configuration is advantageous for light emitting diodes (LEDs) grown on dielectric substrates (e.g., gallium nitride LEDs grown on sapphire substrates) in general due to better thermal dissipation and lower series resistance. Flip-chip configuration is advantageous for microcavity LEDs in particular because (a) one of the reflectors is a high-reflectivity metal ohmic contact that is already part of the flip-chip configuration, and (b) current conduction is only required through a single distributed Bragg reflector. Some of the waveguided lateral modes can also be extracted with angled sidewalls used for the interdigitated contacts in the flip-chip configuration.

Identifying Professional Competencies of the Flip-Chip Packaging Engineer in Taiwan

ERIC Educational Resources Information Center

Guu, Y. H.; Lin, Kuen-Yi; Lee, Lung-Sheng

2014-01-01

This study employed a literature review, expert interviews, and a questionnaire survey to construct a set of two-tier competencies for a flip-chip packaging engineer. The fuzzy Delphi questionnaire was sent to 12 flip-chip engineering experts to identify professional competencies that a flip-chip packaging engineer must have. Four competencies,…

High-Sensitivity Low-Noise Miniature Fluxgate Magnetometers Using a Flip Chip Conceptual Design

PubMed Central

Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

2014-01-01

This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current “flip chip” concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or “responsivity” for magnetometers) and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz) magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz1/2 at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market. PMID:25196107

Fabrication of five-level ultraplanar micromirror arrays by flip-chip assembly

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper reports a detailed study of the fabrication of various piston, torsion, and cantilever style micromirror arrays using a novel, simple, and inexpensive flip-chip assembly technique. Several rectangular and polar arrays were commercially prefabricated in the MUMPs process and then flip-chip bonded to form advanced micromirror arrays where adverse effects typically associated with surface micromachining were removed. These arrays were bonded by directly fusing the MUMPs gold layers with no complex preprocessing. The modules were assembled using a computer-controlled, custom-built flip-chip bonding machine. Topographically opposed bond pads were designed to correct for slight misalignment errors during bonding and typically result in less than 2 micrometers of lateral alignment error. Although flip-chip micromirror performance is briefly discussed, the means used to create these arrays is the focus of the paper. A detailed study of flip-chip process yield is presented which describes the primary failure mechanisms for flip-chip bonding. Studies of alignment tolerance, bonding force, stress concentration, module planarity, bonding machine calibration techniques, prefabrication errors, and release procedures are presented in relation to specific observations in process yield. Ultimately, the standard thermo-compression flip-chip assembly process remains a viable technique to develop highly complex prototypes of advanced micromirror arrays.

Polarity effect of electromigration on mechanical properties of lead-free solder joints

NASA Astrophysics Data System (ADS)

Ren, Fei

The trend of electronic packaging is to package the chips and the associated interconnections in a compact way that allows high speed operation; that allows for sufficient heat removal; that can withstand the thermal cycling associated with the turning on and turning off of the circuits; and that protects the circuits from environmental attack. These goals require that flip chip solder joints have higher resistance to electromigration, stronger mechanical property to sustain thermal mechanical stress, and are lead-free materials to satisfy environment and health concern. With lots of work on chemical reaction, electromigration and mechanical study in flip chip solder joints, however, the interaction between different driving forces is still little known. As a matter of fact, the combination study of chemical, electrical and mechanical is more and more significant to the understanding of the behavior of flip chip solder joints. In this dissertation, I developed one dimensional Cu (wire)-eutectic SnAgCu(ball)-Cu(wire) structure to investigate the interaction between electrical and mechanical force in lead-free solder joints. Electromigration was first conducted. The mechanical behaviors of solder joints before, after, and during electromigration were examined. Electrical current and mechanical stress were applied either in serial or in parallel to the solder joints. Tensile, creep, and drop tests, combined with different electrical current densities (1˜5x10 3A/cm2) and different stressing time (3˜144 hours), have been performed to study the effect of electromigration on the mechanical behavior of solder joints. Nano-indentation test was conducted to study the localized mechanical property of IMC at both interfaces in nanometer scale. Fracture images help analyze the failure mechanism of solder joints driven by both electrical and mechanical forces. The combination study shows a strain build-up during electromigration. Furthermore, a ductile-to-brittle transition in flip chip solder joints induced by electromigration is observed, in which the fracture position migrates from the middle to the cathode interface of the joint with increasing current density and time. The transition is explained by the polarity effect of electromigration, particular due to the accumulation of vacancies at the cathode interface.

Flip-chip assembly and reliability using gold/tin solder bumps

NASA Astrophysics Data System (ADS)

Oppermann, Hermann; Hutter, Matthias; Klein, Matthias; Reichl, Herbert

2004-09-01

Au/Sn solder bumps are commonly used for flip chip assembly of optoelectronic and RF devices. They allow a fluxless assembly which is required to avoid contamination at optical interfaces. Flip chip assembly experiments were carried out using as plated Au/Sn bumps without prior bump reflow. An RF and reliability test vehicles comprise a GaAs chip which was flip chip soldered on a silicon substrate. Temperature cycling tests with and without underfiller were performed and the results are presented. The different failure modes for underfilled and non-underfilled samples were discussed and compared. Additional reliability tests were performed with flip chip bonding by gold thermocompression for comparison. The test results and the failure modes are discussed in detail.

1.65 mm diameter forward-viewing confocal endomicroscopic catheter using a flip-chip bonded electrothermal MEMS fiber scanner.

PubMed

Seo, Yeong-Hyeon; Hwang, Kyungmin; Jeong, Ki-Hun

2018-02-19

We report a 1.65 mm diameter forward-viewing confocal endomicroscopic catheter using a flip-chip bonded electrothermal MEMS fiber scanner. Lissajous scanning was implemented by the electrothermal MEMS fiber scanner. The Lissajous scanned MEMS fiber scanner was precisely fabricated to facilitate flip-chip connection, and bonded with a printed circuit board. The scanner was successfully combined with a fiber-based confocal imaging system. A two-dimensional reflectance image of the metal pattern 'OPTICS' was successfully obtained with the scanner. The flip-chip bonded scanner minimizes electrical packaging dimensions. The inner diameter of the flip-chip bonded MEMS fiber scanner is 1.3 mm. The flip-chip bonded MEMS fiber scanner is fully packaged with a 1.65 mm diameter housing tube, 1 mm diameter GRIN lens, and a single mode optical fiber. The packaged confocal endomicroscopic catheter can provide a new breakthrough for diverse in-vivo endomicroscopic applications.

Defect Inspection of Flip Chip Solder Bumps Using an Ultrasonic Transducer

PubMed Central

Su, Lei; Shi, Tielin; Xu, Zhensong; Lu, Xiangning; Liao, Guanglan

2013-01-01

Surface mount technology has spurred a rapid decrease in the size of electronic packages, where solder bump inspection of surface mount packages is crucial in the electronics manufacturing industry. In this study we demonstrate the feasibility of using a 230 MHz ultrasonic transducer for nondestructive flip chip testing. The reflected time domain signal was captured when the transducer scanning the flip chip, and the image of the flip chip was generated by scanning acoustic microscopy. Normalized cross-correlation was used to locate the center of solder bumps for segmenting the flip chip image. Then five features were extracted from the signals and images. The support vector machine was adopted to process the five features for classification and recognition. The results show the feasibility of this approach with high recognition rate, proving that defect inspection of flip chip solder bumps using the ultrasonic transducer has high potential in microelectronics packaging.

Flexible packaging of solid-state integrated circuit chips with elastomeric microfluidics

PubMed Central

Zhang, Bowei; Dong, Quan; Korman, Can E.; Li, Zhenyu; Zaghloul, Mona E.

2013-01-01

A flexible technology is proposed to integrate smart electronics and microfluidics all embedded in an elastomer package. The microfluidic channels are used to deliver both liquid samples and liquid metals to the integrated circuits (ICs). The liquid metals are used to realize electrical interconnects to the IC chip. This avoids the traditional IC packaging challenges, such as wire-bonding and flip-chip bonding, which are not compatible with current microfluidic technologies. As a demonstration we integrated a CMOS magnetic sensor chip and associate microfluidic channels on a polydimethylsiloxane (PDMS) substrate that allows precise delivery of small liquid samples to the sensor. Furthermore, the packaged system is fully functional under bending curvature radius of one centimetre and uniaxial strain of 15%. The flexible integration of solid-state ICs with microfluidics enables compact flexible electronic and lab-on-a-chip systems, which hold great potential for wearable health monitoring, point-of-care diagnostics and environmental sensing among many other applications.

Oxide-confined 2D VCSEL arrays for high-density inter/intra-chip interconnects

NASA Astrophysics Data System (ADS)

King, Roger; Michalzik, Rainer; Jung, Christian; Grabherr, Martin; Eberhard, Franz; Jaeger, Roland; Schnitzer, Peter; Ebeling, Karl J.

1998-04-01

We have designed and fabricated 4 X 8 vertical-cavity surface-emitting laser (VCSEL) arrays intended to be used as transmitters in short-distance parallel optical interconnects. In order to meet the requirements of 2D, high-speed optical links, each of the 32 laser diodes is supplied with two individual top contacts. The metallization scheme allows flip-chip mounting of the array modules junction-side down on silicon complementary metal oxide semiconductor (CMOS) chips. The optical and electrical characteristics across the arrays with device pitch of 250 micrometers are quite homogeneous. Arrays with 3 micrometers , 6 micrometers and 10 micrometers active diameter lasers have been investigated. The small devices show threshold currents of 600 (mu) A, single-mode output powers as high as 3 mW and maximum wavelength deviations of only 3 nm. The driving characteristics of all arrays are fully compatible to advanced 3.3 V CMOS technology. Using these arrays, we have measured small-signal modulation bandwidths exceeding 10 GHz and transmitted pseudo random data at 8 Gbit/s channel over 500 m graded index multimode fiber. This corresponds to a data transmission rate of 256 Gbit/s per array of 1 X 2 mm2 footprint area.

PbS-PbSe IR detector arrays

NASA Technical Reports Server (NTRS)

Barrett, John R. (Inventor)

1986-01-01

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chipping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

NASA Astrophysics Data System (ADS)

Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

2003-06-01

We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

Hybridization of active and passive elements for planar photonic components and interconnects

NASA Astrophysics Data System (ADS)

Pearson, M.; Bidnyk, S.; Balakrishnan, A.

2007-02-01

The deployment of Passive Optical Networks (PON) for Fiber-to-the-Home (FTTH) applications currently represents the fastest growing sector of the telecommunication industry. Traditionally, FTTH transceivers have been manufactured using commodity bulk optics subcomponents, such as thin film filters (TFFs), micro-optic collimating lenses, TO-packaged lasers, and photodetectors. Assembling these subcomponents into a single housing requires active alignment and labor-intensive techniques. Today, the majority of cost reducing strategies using bulk subcomponents has been implemented making future reductions in the price of manufacturing FTTH transceivers unlikely. Future success of large scale deployments of FTTH depends on further cost reductions of transceivers. Realizing the necessity of a radically new packaging approach for assembly of photonic components and interconnects, we designed a novel way of hybridizing active and passive elements into a planar lightwave circuit (PLC) platform. In our approach, all the filtering components were monolithically integrated into the chip using advancements in planar reflective gratings. Subsequently, active components were passively hybridized with the chip using fully-automated high-capacity flip-chip bonders. In this approach, the assembly of the transceiver package required no active alignment and was readily suitable for large-scale production. This paper describes the monolithic integration of filters and hybridization of active components in both silica-on-silicon and silicon-on-insulator PLCs.

Experiences in flip chip production of radiation detectors

NASA Astrophysics Data System (ADS)

Savolainen-Pulli, Satu; Salonen, Jaakko; Salmi, Jorma; Vähänen, Sami

2006-09-01

Modern imaging devices often require heterogeneous integration of different materials and technologies. Because of yield considerations, material availability, and various technological limitations, an extremely fine pitch is necessary to realize high-resolution images. Thus, there is a need for a hybridization technology that is able to join together readout amplifiers and pixel detectors at a very fine pitch. This paper describes radiation detector flip chip production at VTT. Our flip chip technology utilizes 25-μm diameter tin-lead solder bumps at a 50-μm pitch and is based on flux-free bonding. When preprocessed wafers are used, as is the case here, the total yield is defined only partly by the flip chip process. Wafer preprocessing done by a third-party silicon foundry and the flip chip process create different process defects. Wafer-level yield maps (based on probing) provided by the customer are used to select good readout chips for assembly. Wafer probing is often done outside of a real clean room environment, resulting in particle contamination and/or scratches on the wafers. Factors affecting the total yield of flip chip bonded detectors are discussed, and some yield numbers of the process are given. Ways to improve yield are considered, and finally guidelines for process planning and device design with respect to yield optimization are given.

Enabling Large Focal Plane Arrays Through Mosaic Hybridization

NASA Technical Reports Server (NTRS)

Miller, TImothy M.; Jhabvala, Christine A.; Leong, Edward; Costen, Nicholas P.; Sharp, Elmer; Adachi, Tomoko; Benford, Dominic

2012-01-01

We have demonstrated advances in mosaic hybridization that will enable very large format far-infrared detectors. Specifically we have produced electrical detector models via mosaic hybridization yielding superconducting circuit paths by hybridizing separately fabricated sub-units onto a single detector unit. The detector model was made on a 100mm diameter wafer while four model readout quadrant chips were made from a separate 100mm wafer. The individually fabricated parts were hybridized using a flip-chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the model mosaic-hybrid detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently available.

Enabling Large Focal Plane Arrays through Mosaic Hybridization

NASA Technical Reports Server (NTRS)

Miller, Timothy M.; Jhabvala, Christine A.; Costen, Nick; Benford, Dominic J.

2012-01-01

We have demonstrated the hybridization of large mosaics of far-infrared detectors, joining separately fabricated sub-units into a single unit on a single, large substrate. We produced a single detector mockup on a 100mm diameter wafer and four mockup readout quadrant chips from a separate 100mm wafer. The individually fabricated parts were hybridized using a Suss FC150 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion (CTE) match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the mockup mosaic-hybridized detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently demonstrated.

Silver free III-nitride flip chip light-emitting-diode with wall plug efficiency over 70% utilizing a GaN tunnel junction

NASA Astrophysics Data System (ADS)

Yonkee, B. P.; Young, E. C.; DenBaars, S. P.; Nakamura, S.; Speck, J. S.

2016-11-01

A molecular beam epitaxy regrowth technique was demonstrated on standard industrial patterned sapphire substrate light-emitting diode (LED) epitaxial wafers emitting at 455 nm to form a GaN tunnel junction. By using an HF pretreatment on the wafers before regrowth, a voltage of 3.08 V at 20 A/cm2 was achieved on small area devices. A high extraction package was developed for comparison with flip chip devices which utilize an LED floating in silicone over a BaSO4 coated header and produced a peak external quantum efficiency (EQE) of 78%. A high reflectivity mirror was designed using a seven-layer dielectric coating backed by aluminum which has a calculated angular averaged reflectivity over 98% between 400 and 500 nm. This was utilized to fabricate a flip chip LED which had a peak EQE and wall plug efficiency of 76% and 73%, respectively. This flip chip could increase light extraction over a traditional flip chip LED due to the increased reflectivity of the dielectric based mirror.

Effects of PCB Pad Metal Finishes on the Cu-Pillar/Sn-Ag Micro Bump Joint Reliability of Chip-on-Board (COB) Assembly

NASA Astrophysics Data System (ADS)

Kim, Youngsoon; Lee, Seyong; Shin, Ji-won; Paik, Kyung-Wook

2016-06-01

While solder bumps have been used as the bump structure to form the interconnection during the last few decades, the continuing scaling down of devices has led to a change in the bump structure to Cu-pillar/Sn-Ag micro-bumps. Cu-pillar/Sn-Ag micro-bump interconnections differ from conventional solder bump interconnections in terms of their assembly processing and reliability. A thermo-compression bonding method with pre-applied b-stage non-conductive films has been adopted to form solder joints between Cu pillar/Sn-Ag micro bumps and printed circuit board vehicles, using various pad metal finishes. As a result, various interfacial inter-metallic compounds (IMCs) reactions and stress concentrations occur at the Cu pillar/Sn-Ag micro bumps joints. Therefore, it is necessary to investigate the influence of pad metal finishes on the structural reliability of fine pitch Cu pillar/Sn-Ag micro bumps flip chip packaging. In this study, four different pad surface finishes (Thin Ni ENEPIG, OSP, ENEPIG, ENIG) were evaluated in terms of their interconnection reliability by thermal cycle (T/C) test up to 2000 cycles at temperatures ranging from -55°C to 125°C and high-temperature storage test up to 1000 h at 150°C. The contact resistances of the Cu pillar/Sn-Ag micro bump showed significant differences after the T/C reliability test in the following order: thin Ni ENEPIG > OSP > ENEPIG where the thin Ni ENEPIG pad metal finish provided the best Cu pillar/Sn-Ag micro bump interconnection in terms of bump joint reliability. Various IMCs formed between the bump joint areas can account for the main failure mechanism.

Biwavelength transceiver module for parallel simultaneous bidirectional optical interconnections

NASA Astrophysics Data System (ADS)

Nguyen, Nga T. H.; Ukaegbu, Ikechi A.; Sangirov, Jamshid; Cho, Mu-Hee; Lee, Tae-Woo; Park, Hyo-Hoon

2013-12-01

The design of a biwavelength transceiver (TRx) module for parallel simultaneous bidirectional optical interconnects is described. The TRx module has been implemented using two different wavelengths, 850 and 1060 nm, to send and receive signals simultaneously through a common optical interface while optimizing cost and performance. Filtering mirrors are formed in the optical fibers which are embedded on a V-grooved silicon substrate for reflecting and filtering optical signals from/to vertical-cavity surface-emitting laser (VCSEL)/photodiode (PD). The VCSEL and PD are flip-chip bonded on individual silicon optical benches, which are attached on the silicon substrate for optical signal coupling from the VCSEL to fiber and from fiber to the PD. A high-speed and low-loss ceramic printed circuit board, which has a compact size of 0.033 cc, has been designed to carry transmitter and receiver chips for easy packaging of the TRx module. Applied for quad small form-factor pluggable applications at 40-Gbps operation, the four-channel biwavelength TRx module showed clear eye diagrams with a bit error rate (BER) of 10-12 at input powers of -5 and -5.8 dBm for 1060 and 850 nm operation modes, respectively.

Hybrid integration of VCSELs onto a silicon photonic platform for biosensing application

NASA Astrophysics Data System (ADS)

Lu, Huihui; Lee, Jun Su; Zhao, Yan; Cardile, Paolo; Daly, Aidan; Carroll, Lee; O'Brien, Peter

2017-02-01

This paper presents a technology of hybrid integration vertical cavity surface emitting lasers (VCSELs) directly on silicon photonics chip. By controlling the reflow of the solder balls used for electrical and mechanical bonding, the VCSELs were bonded at 10 degree to achieve the optimum angle-of-incidence to the planar grating coupler through vision based flip-chip techniques. The 1 dB discrepancy between optical loss values of flip-chip passive assembly and active alignment confirmed that the general purpose of the flip-chip design concept is achieved. This hybrid approach of integrating a miniaturized light source on chip opens the possibly of highly compact sensor system, which enable future portable and wearable diagnostics devices.

Photodiodes integration on a suspended ridge structure VOA using 2-step flip-chip bonding method

NASA Astrophysics Data System (ADS)

Kim, Seon Hoon; Kim, Tae Un; Ki, Hyun Chul; Kim, Doo Gun; Kim, Hwe Jong; Lim, Jung Woon; Lee, Dong Yeol; Park, Chul Hee

2015-01-01

In this works, we have demonstrated a VOA integrated with mPDs, based on silica-on-silicon PLC and flip-chip bonding technologies. The suspended ridge structure was applied to reduce the power consumption. It achieves the attenuation of 30dB in open loop operation with the power consumption of below 30W. We have applied two-step flipchip bonding method using passive alignment to perform high density multi-chip integration on a VOA with eutectic AuSn solder bumps. The average bonding strength of the two-step flip-chip bonding method was about 90gf.

Thermoelectric Coolers with Sintered Silver Interconnects

NASA Astrophysics Data System (ADS)

Kähler, Julian; Stranz, Andrej; Waag, Andreas; Peiner, Erwin

2014-06-01

The fabrication and performance of a sintered Peltier cooler (SPC) based on bismuth telluride with sintered silver interconnects are described. Miniature SPC modules with a footprint of 20 mm2 were assembled using pick-and-place pressure-assisted silver sintering at low pressure (5.5 N/mm2) and moderate temperature (250°C to 270°C). A modified flip-chip bonder combined with screen/stencil printing for paste transfer was used for the pick-and-place process, enabling high positioning accuracy, easy handling of the tiny bismuth telluride pellets, and immediate visual process control. A specific contact resistance of (1.4 ± 0.1) × 10-5 Ω cm2 was found, which is in the range of values reported for high-temperature solder interconnects of bismuth telluride pellets. The realized SPCs were evaluated from room temperature to 300°C, considerably outperforming the operating temperature range of standard commercial Peltier coolers. Temperature cycling capability was investigated from 100°C to 235°C over more than 200 h, i.e., 850 cycles, during which no degradation of module resistance or cooling performance occurred.

Molded underfill (MUF) encapsulation for flip-chip package: A numerical investigation

NASA Astrophysics Data System (ADS)

Azmi, M. A.; Abdullah, M. K.; Abdullah, M. Z.; Ariff, Z. M.; Saad, Abdullah Aziz; Hamid, M. F.; Ismail, M. A.

2017-07-01

This paper presents the numerical simulation of epoxy molding compound (EMC) filling in multi flip-chip packages during encapsulation process. The empty and a group flip chip packages were considered in the mold cavity in order to study the flow profile of the EMC. SOLIDWORKS software was used for three-dimensional modeling and it was incorporated into fluid analysis software namely as ANSYS FLUENT. The volume of fluid (VOF) technique was used for capturing the flow front profiles and Power Law model was applied for its rheology model. The numerical result are compared and discussed with previous experimental and it was shown a good conformity for model validation. The prediction of flow front was observed and analyzed at different filling time. The possibility and visual of void formation in the package is captured and the number of flip-chip is one factor that contributed to the void formation.

Super-Lattice Light Emitting Diodes (SLEDS) on GaAs

DTIC Science & Technology

2016-03-31

Super-Lattice Light Emitting Diodes (SLEDS) on GaAs Kassem Nabha1, Russel Ricker2, Rodney McGee1, Nick Waite1, John Prineas2, Sydney Provence2...infrared light emitting diodes (LEDs). Typically, the LED arrays are mated with CMOS read-in integrated circuit (RIIC) chips using flip-chip bonding. In...circuit (RIIC) chips using flip-chip bonding. This established technology is called Hybrid-super-lattice light emitting diodes (Hybrid- SLEDS). In

3D printed high density, reversible, chip-to-chip microfluidic interconnects.

PubMed

Gong, Hua; Woolley, Adam T; Nordin, Gregory P

2018-02-13

Our latest developments in miniaturizing 3D printed microfluidics [Gong et al., Lab Chip, 2016, 16, 2450; Gong et al., Lab Chip, 2017, 17, 2899] offer the opportunity to fabricate highly integrated chips that measure only a few mm on a side. For such small chips, an interconnection method is needed to provide the necessary world-to-chip reagent and pneumatic connections. In this paper, we introduce simple integrated microgaskets (SIMs) and controlled-compression integrated microgaskets (CCIMs) to connect a small device chip to a larger interface chip that implements world-to-chip connections. SIMs or CCIMs are directly 3D printed as part of the device chip, and therefore no additional materials or components are required to make the connection to the larger 3D printed interface chip. We demonstrate 121 chip-to-chip interconnections in an 11 × 11 array for both SIMs and CCIMs with an areal density of 53 interconnections per mm 2 and show that they withstand fluid pressures of 50 psi. We further demonstrate their reusability by testing the devices 100 times without seal failure. Scaling experiments show that 20 × 20 interconnection arrays are feasible and that the CCIM areal density can be increased to 88 interconnections per mm 2 . We then show the utility of spatially distributed discrete CCIMs by using an interconnection chip with 28 chip-to-world interconnects to test 45 3D printed valves in a 9 × 5 array. Each valve is only 300 μm in diameter (the smallest yet reported for 3D printed valves). Every row of 5 valves is tested to at least 10 000 actuations, with one row tested to 1 000 000 actuations. In all cases, there is no sign of valve failure, and the CCIM interconnections prove an effective means of using a single interface chip to test a series of valve array chips.

Enabling Large Focal Plane Arrays Through Mosaic Hybridization

NASA Technical Reports Server (NTRS)

Miller, Timothy M.; Jhabvala, Christine A.; Leong, Edward; Costen, Nick P.; Sharp, Elmer; Adachi, Tomoko; Benford, Dominic J.

2012-01-01

We have demonstrated advances in mosaic hybridization that will enable very large format far-infrared detectors. Specifically we have produced electrical detector models via mosaic hybridization yielding superconducting circuit patbs by hybridizing separately fabricated sub-units onto a single detector unit. The detector model was made on a 100mm diameter wafer while four model readout quadrant chips were made from a separate 100mm wafer. The individually fabric.ted parts were hybridized using a Suss FCI50 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the model mosaic-hybrid detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently available.

Thermal cycling reliability of Cu/SnAg double-bump flip chip assemblies for 100 μm pitch applications

NASA Astrophysics Data System (ADS)

Son, Ho-Young; Kim, Ilho; Lee, Soon-Bok; Jung, Gi-Jo; Park, Byung-Jin; Paik, Kyung-Wook

2009-01-01

A thick Cu column based double-bump flip chip structure is one of the promising alternatives for fine pitch flip chip applications. In this study, the thermal cycling (T/C) reliability of Cu/SnAg double-bump flip chip assemblies was investigated, and the failure mechanism was analyzed through the correlation of T/C test and the finite element analysis (FEA) results. After 1000 thermal cycles, T/C failures occurred at some Cu/SnAg bumps located at the edge and corner of chips. Scanning acoustic microscope analysis and scanning electron microscope observations indicated that the failure site was the Cu column/Si chip interface. It was identified by a FEA where the maximum stress concentration was located during T/C. During T/C, the Al pad between the Si chip and a Cu column bump was displaced due to thermomechanical stress. Based on the low cycle fatigue model, the accumulation of equivalent plastic strain resulted in thermal fatigue deformation of the Cu column bumps and ultimately reduced the thermal cycling lifetime. The maximum equivalent plastic strains of some bumps at the chip edge increased with an increased number of thermal cycles. However, equivalent plastic strains of the inner bumps did not increase regardless of the number of thermal cycles. In addition, the z-directional normal plastic strain ɛ22 was determined to be compressive and was a dominant component causing the plastic deformation of Cu/SnAg double bumps. As the number of thermal cycles increased, normal plastic strains in the perpendicular direction to the Si chip and shear strains were accumulated on the Cu column bumps at the chip edge at low temperature region. Thus it was found that the Al pad at the Si chip/Cu column interface underwent thermal fatigue deformation by compressive normal strain and the contact loss by displacement failure of the Al pad, the main T/C failure mode of the Cu/SnAg flip chip assembly, then occurred at the Si chip/Cu column interface shear strain deformation during T/C.

Life test of the InGaAs focal plane arrays detector for space applications

NASA Astrophysics Data System (ADS)

Zhu, Xian-Liang; Zhang, Hai-Yan; Li, Xue; Huang, Zhang-Cheng; Gong, Hai-Mei

2017-08-01

The short-wavelength infrared (SWIR) InGaAs focal plane array (FPA) detector consists of infrared detector chip, readout integrated circuit (ROIC), and flip-chip bonding interconnection by Indium bump. In order to satisfy space application requirements for failure rates or Mean Time to Failure (MTTF), which can only be demonstrated with the large number of detectors manufactured, the single pixel in InGaAs FPAs was chosen as the research object in this paper. The constant-stress accelerated life tests were carried out at 70°C 80°C 90°C and100°C. The failed pixels increased gradually during more than 14000 hours at each elevated temperatures. From the random failure data the activation energy was estimated to be 0.46eV, and the average lifetime of a single pixel in InGaAs FPAs was estimated to be longer than 1E+7h at the practical operating temperature (5°C).

AIN-Based Packaging for SiC High-Temperature Electronics

NASA Technical Reports Server (NTRS)

Savrun, Ender

2004-01-01

Packaging made primarily of aluminum nitride has been developed to enclose silicon carbide-based integrated circuits (ICs), including circuits containing SiC-based power diodes, that are capable of operation under conditions more severe than can be withstood by silicon-based integrated circuits. A major objective of this development was to enable packaged SiC electronic circuits to operate continuously at temperatures up to 500 C. AlN-packaged SiC electronic circuits have commercial potential for incorporation into high-power electronic equipment and into sensors that must withstand high temperatures and/or high pressures in diverse applications that include exploration in outer space, well logging, and monitoring of nuclear power systems. This packaging embodies concepts drawn from flip-chip packaging of silicon-based integrated circuits. One or more SiC-based circuit chips are mounted on an aluminum nitride package substrate or sandwiched between two such substrates. Intimate electrical connections between metal conductors on the chip(s) and the metal conductors on external circuits are made by direct bonding to interconnections on the package substrate(s) and/or by use of holes through the package substrate(s). This approach eliminates the need for wire bonds, which have been the most vulnerable links in conventional electronic circuitry in hostile environments. Moreover, the elimination of wire bonds makes it possible to pack chips more densely than was previously possible.

Hybrid UV Imager Containing Face-Up AlGaN/GaN Photodiodes

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Pain, Bedabrata

2005-01-01

A proposed hybrid ultraviolet (UV) image sensor would comprise a planar membrane array of face-up AlGaN/GaN photodiodes integrated with a complementary metal oxide/semiconductor (CMOS) readout-circuit chip. Each pixel in the hybrid image sensor would contain a UV photodiode on the AlGaN/GaN membrane, metal oxide/semiconductor field-effect transistor (MOSFET) readout circuitry on the CMOS chip underneath the photodiode, and a metal via connection between the photodiode and the readout circuitry (see figure). The proposed sensor design would offer all the advantages of comparable prior CMOS active-pixel sensors and AlGaN UV detectors while overcoming some of the limitations of prior (AlGaN/sapphire)/CMOS hybrid image sensors that have been designed and fabricated according to the methodology of flip-chip integration. AlGaN is a nearly ideal UV-detector material because its bandgap is wide and adjustable and it offers the potential to attain extremely low dark current. Integration of AlGaN with CMOS is necessary because at present there are no practical means of realizing readout circuitry in the AlGaN/GaN material system, whereas the means of realizing readout circuitry in CMOS are well established. In one variant of the flip-chip approach to integration, an AlGaN chip on a sapphire substrate is inverted (flipped) and then bump-bonded to a CMOS readout circuit chip; this variant results in poor quantum efficiency. In another variant of the flip-chip approach, an AlGaN chip on a crystalline AlN substrate would be bonded to a CMOS readout circuit chip; this variant is expected to result in narrow spectral response, which would be undesirable in many applications. Two other major disadvantages of flip-chip integration are large pixel size (a consequence of the need to devote sufficient area to each bump bond) and severe restriction on the photodetector structure. The membrane array of AlGaN/GaN photodiodes and the CMOS readout circuit for the proposed image sensor would be fabricated separately.

Fabrication of a novel gigabit/second free-space optical interconnect - photodetector characterization and testing and system development

NASA Technical Reports Server (NTRS)

Savich, Gregory R.

2004-01-01

The time when computing power is limited by the copper wire inherent in the computer system and not the speed of the microprocessor is rapidly approaching. With constant advances in computer technology, many researchers believe that in only a few years, optical interconnects will begin to replace copper wires in your Central Processing Unit (CPU). On a more macroscopic scale, the telecommunications industry has already made the switch to optical data transmission as, to date, fiber optic technology is the only reasonable method of reliable, long range data transmission. Within the span of a decade, we will see optical technologies move from the macroscopic world of the telecommunications industry to the microscopic world of the computer chip. Already, the communications industry is marketing commercially available optical links to connect two personal computers, thereby eliminating the need for standard and comparatively slow wired and wireless Ethernet transfers and greatly increasing the distance the computers can be separated. As processing demands continue to increase, the realm of optical communications will continue to move closer to the microprocessor and quite possibly onto the microprocessor itself. A day may come when copper connections are used only to supply power, not transfer data. This summer s work marks some of the beginning stages of a 5 to 10 year, long-term research project to create and study a free-space, 1 Gigabit/sec optical interconnect. The research will result in a novel fabricated, chip-to-chip interconnect consisting of a Vertical Cavity Surface Emitting Laser (VCSEL) Diode linked through free space to a Metal- Semiconductor-Metal (MSM) Photodetector with the possible integration of microlenses for signal focusing and Micro-Electromechanical Systems (MEMS) devices for optical signal steering. The advantages, disadvantages, and practicality of incorporating flip-chip mounting technologies will also be addressed. My work began with the design and construction of a test setup for the experiment and then appropriate characterization of the test system. Specifically, I am involved in the characterization of a commercially available 1550nm wavelength, 5mW diode laser and a study of its modulation bandwidth. Commercially produced photodetectors as well as the incorporation of microwave technology, in the form of RF input and output, are used in the characterization procedure. The next stage involves the use of a probe station and network analyzer to characterize and test a series of photodetectors fabricated on a 2 inch, Indium Gallium Arsenide (InGaAs) wafer in the Branch s microlithography lab. Other project responsibilities include, but are not limited to the incorporation of a transimpedance amplifier to the photodetector circuit; a study of VCSEL technology; bit error rate analysis of an optical interconnect system; and analysis of free space divergence of the VCSEL, optical path length of the interconnect; and any other pertinent optical properties of the one gigabit per second interconnect for fabrication and testing.

Flip Chip on Organic Substrates: A Feasibility Study for Space Applications

DTIC Science & Technology

2017-03-01

scheme, a 1752 I/O land grid array (LGA) package with decoupling capacitors, heat sink and optional column attach [1] as shown in Figure 1...investigated the effect of moisture and current loading on the Class Y flip chip on ceramic reliability [ 2 ]. The UT1752FC Class Y technology has...chip assembly to ceramic test substrates, the FA10 die are assembled to build-up organic test substrates as shown in Figure 2 . These assemblies

Wireless Interconnects for Intra-chip & Inter-chip Transmission

NASA Astrophysics Data System (ADS)

Narde, Rounak Singh

With the emergence of Internet of Things and information revolution, the demand of high performance computing systems is increasing. The copper interconnects inside the computing chips have evolved into a sophisticated network of interconnects known as Network on Chip (NoC) comprising of routers, switches, repeaters, just like computer networks. When network on chip is implemented on a large scale like in Multicore Multichip (MCMC) systems for High Performance Computing (HPC) systems, length of interconnects increases and so are the problems like power dissipation, interconnect delays, clock synchronization and electrical noise. In this thesis, wireless interconnects are chosen as the substitute for wired copper interconnects. Wireless interconnects offer easy integration with CMOS fabrication and chip packaging. Using wireless interconnects working at unlicensed mm-wave band (57-64GHz), high data rate of Gbps can be achieved. This thesis presents study of transmission between zigzag antennas as wireless interconnects for Multichip multicores (MCMC) systems and 3D IC. For MCMC systems, a four-chips 16-cores model is analyzed with only four wireless interconnects in three configurations with different antenna orientations and locations. Return loss and transmission coefficients are simulated in ANSYS HFSS. Moreover, wireless interconnects are designed, fabricated and tested on a 6'' silicon wafer with resistivity of 55O-cm using a basic standard CMOS process. Wireless interconnect are designed to work at 30GHz using ANSYS HFSS. The fabricated antennas are resonating around 20GHz with a return loss of less than -10dB. The transmission coefficients between antenna pair within a 20mm x 20mm silicon die is found to be varying between -45dB to -55dB. Furthermore, wireless interconnect approach is extended for 3D IC. Wireless interconnects are implemented as zigzag antenna. This thesis extends the work of analyzing the wireless interconnects in 3D IC with different configurations of antenna orientations and coolants. The return loss and transmission coefficients are simulated using ANSYS HFSS.

Three dimensional, multi-chip module

DOEpatents

Bernhardt, A.F.; Petersen, R.W.

1993-08-31

A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow dummy chips'' are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned on the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

Three dimensional, multi-chip module

DOEpatents

Bernhardt, Anthony F.; Petersen, Robert W.

1993-01-01

A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow "dummy chips" are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned o the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

Process for 3D chip stacking

DOEpatents

Malba, V.

1998-11-10

A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: (1) holding individual chips for batch processing, (2) depositing a dielectric passivation layer on the top and sidewalls of the chips, (3) opening vias in the dielectric, (4) forming the interconnects by laser pantography, and (5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume. 3 figs.

Process for 3D chip stacking

DOEpatents

Malba, Vincent

1998-01-01

A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: 1) holding individual chips for batch processing, 2) depositing a dielectric passivation layer on the top and sidewalls of the chips, 3) opening vias in the dielectric, 4) forming the interconnects by laser pantography, and 5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume.

New Failure Mode of Flip-Chip Solder Joints Related to the Metallization of an Organic Substrate

NASA Astrophysics Data System (ADS)

Jang, J. W.; Yoo, S. J.; Hwang, H. I.; Yuk, S. Y.; Kim, C. K.; Kim, S. J.; Han, J. S.; An, S. H.

2015-10-01

We report a new failure phenomenon during flip-chip die attach. After reflow, flip-chip bumps were separated between the Al and Ti layers on the Si die side. This was mainly observed at the Si die corner. Transmission electron microscopy images revealed corrosion of the Al layer at the edge of the solder bump metallization. The corrosion at the metallization edge exhibited a notch shape with high stress concentration factor. The organic substrate had Cu metallization with an organic solderable preservative (OSP) coating layer, where a small amount of Cl ions were detected. A solder bump separation mechanism is suggested based on the reaction between Al and Cl, related to the flow of soldering flux. During reflow, the flux will dissolve the Cl-containing OSP layer and flow up to the Al layer on the Si die side. Then, the Cl-dissolved flux will actively react with Al, forming AlCl3. During cooling, solder bumps at the Si die corner will separate through the location of Al corrosion. This demonstrated that the chemistry of the substrate metallization can affect the thermomechanical reliability of flip-chip solder joints.

Chip-scale integrated optical interconnects: a key enabler for future high-performance computing

NASA Astrophysics Data System (ADS)

Haney, Michael; Nair, Rohit; Gu, Tian

2012-01-01

High Performance Computing (HPC) systems are putting ever-increasing demands on the throughput efficiency of their interconnection fabrics. In this paper, the limits of conventional metal trace-based inter-chip interconnect fabrics are examined in the context of state-of-the-art HPC systems, which currently operate near the 1 GFLOPS/W level. The analysis suggests that conventional metal trace interconnects will limit performance to approximately 6 GFLOPS/W in larger HPC systems that require many computer chips to be interconnected in parallel processing architectures. As the HPC communications bottlenecks push closer to the processing chips, integrated Optical Interconnect (OI) technology may provide the ultra-high bandwidths needed at the inter- and intra-chip levels. With inter-chip photonic link energies projected to be less than 1 pJ/bit, integrated OI is projected to enable HPC architecture scaling to the 50 GFLOPS/W level and beyond - providing a path to Peta-FLOPS-level HPC within a single rack, and potentially even Exa-FLOPSlevel HPC for large systems. A new hybrid integrated chip-scale OI approach is described and evaluated. The concept integrates a high-density polymer waveguide fabric directly on top of a multiple quantum well (MQW) modulator array that is area-bonded to the Silicon computing chip. Grayscale lithography is used to fabricate 5 μm x 5 μm polymer waveguides and associated novel small-footprint total internal reflection-based vertical input/output couplers directly onto a layer containing an array of GaAs MQW devices configured to be either absorption modulators or photodetectors. An external continuous wave optical "power supply" is coupled into the waveguide links. Contrast ratios were measured using a test rider chip in place of a Silicon processing chip. The results suggest that sub-pJ/b chip-scale communication is achievable with this concept. When integrated into high-density integrated optical interconnect fabrics, it could provide a seamless interconnect fabric spanning the intra-

3D integrated superconducting qubits

NASA Astrophysics Data System (ADS)

Rosenberg, D.; Kim, D.; Das, R.; Yost, D.; Gustavsson, S.; Hover, D.; Krantz, P.; Melville, A.; Racz, L.; Samach, G. O.; Weber, S. J.; Yan, F.; Yoder, J. L.; Kerman, A. J.; Oliver, W. D.

2017-10-01

As the field of quantum computing advances from the few-qubit stage to larger-scale processors, qubit addressability and extensibility will necessitate the use of 3D integration and packaging. While 3D integration is well-developed for commercial electronics, relatively little work has been performed to determine its compatibility with high-coherence solid-state qubits. Of particular concern, qubit coherence times can be suppressed by the requisite processing steps and close proximity of another chip. In this work, we use a flip-chip process to bond a chip with superconducting flux qubits to another chip containing structures for qubit readout and control. We demonstrate that high qubit coherence (T1, T2,echo > 20 μs) is maintained in a flip-chip geometry in the presence of galvanic, capacitive, and inductive coupling between the chips.

Fundamental study of microelectronic chip response under laser ultrasonic-interferometric inspection using C-scan method

NASA Astrophysics Data System (ADS)

Yang, Lei; Gong, Jie; Ume, I. Charles

2014-02-01

In modern surface mount packaging technologies, such as flip chips, chip scale packages, and ball grid arrays(BGA), chips are attached to the substrates/printed wiring board (PWB) using solder bump interconnections. The quality of solder bumps between the chips and the substrate/board is difficult to inspect. Laser ultrasonic-interferometric technique was proved to be a promising approach for solder bump inspection because of its noncontact and nondestructive characteristics. Different indicators extracted from received signals have been used to predict the potential defects, such as correlation coefficient, error ratio, frequency shifting, etc. However, the fundamental understanding of the chip behavior under laser ultrasonic inspection is still missing. Specifically, it is not sure whether the laser interferometer detected out-of-plane displacements were due to wave propagation or structural vibration when the chip was excited by pulsed laser. Plus, it is found that the received signals are chip dependent. Both challenges impede the interpretation of acquired signals. In this paper, a C-scan method was proposed to study the underlying phenomenon during laser ultrasonic inspection. The full chip was inspected. The response of the chip under laser excitation was visualized in a movie resulted from acquired signals. Specifically, a BGA chip was investigated to demonstrate the effectiveness of this method. By characterizing signals using discrete wavelet transform(DWT), both ultrasonic wave propagation and vibration were observed. Separation of them was successfully achieved using ideal band-pass filter and visualized in resultant movies, too. The observed ultrasonic waves were characterized and their respective speeds were measured by applying 2-D FFT. The C-scan method, combined with different digital signal processing techniques, was proved to be an very effective methodology to learn the behavior of chips under laser excitation. This general procedure can be applied to any unknown chip before inspection. A wealth of information can be provided by this learning procedure, which greatly benefits the interpretation of inspection signals afterwards.

Survey of critical failure events in on-chip interconnect by fault tree analysis

NASA Astrophysics Data System (ADS)

Yokogawa, Shinji; Kunii, Kyousuke

2018-07-01

In this paper, a framework based on reliability physics is proposed for adopting fault tree analysis (FTA) to the on-chip interconnect system of a semiconductor. By integrating expert knowledge and experience regarding the possibilities of failure on basic events, critical issues of on-chip interconnect reliability will be evaluated by FTA. In particular, FTA is used to identify the minimal cut sets with high risk priority. Critical events affecting the on-chip interconnect reliability are identified and discussed from the viewpoint of long-term reliability assessment. The moisture impact is evaluated as an external event.

Method of fabricating a PbS-PbSe IR detector array

NASA Technical Reports Server (NTRS)

Barrett, John R. (Inventor)

1987-01-01

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chiping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

Evaluation of the thermal conductance of flip-chip bonding structure utilizing the measurement based on Fourier's law of heat conduction at steady-state

NASA Astrophysics Data System (ADS)

Wu, Chia-Yu; Huang, Yin-Hsien; Wu, Hsin-Han; Hsieh, Tsung-Eong

2018-06-01

Fourier's law of heat conduction at steady-state was adopted to establish a measurement method utilizing platinum (Pt) thin-film electrodes as the heater and the temperature sensor. The thermal conductivities (κ's) of Pyrex glass, an epoxy resin and a commercial underfill for flip-chip devices were measured and a good agreement with previously reported values was obtained. The thermal boundary resistances (RTBR's) of Pt/sample interfaces were also extracted for discussing their influence on the thermal conduction of samples. Afterward, the flip-chip samples with 2×2 solder joint array utilizing Si wafers as the die and the substrate, without and with the underfills, were prepared and their thermal conductance were measured. For the sample without underfill, the air presenting in the gap of die and the substrate led to the poor thermal conductance of sample. With the insertion of underfills, the thermal conductance of flip-chip samples improved. The resistance to heat transfer across Si/underfill interfaces was also suppressed and to promote the thermal conductance of samples. The thermal properties of underfill and RTBR at Si/underfill interface were further implanted in the calculation of thermal conductance of flip-chip samples containing various solder joint arrays. The increasing number of solder joints diminished the influence of thermal conduction of underfill and RTBR of Si/underfill interface on the thermal conductance of samples. The insertion of underfill with high-κ value might promote the heat conductance of samples containing low-density solder joint arrays; however, it became insignificant in improving the heat conductance of samples containing high-density solder joint arrays.

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

NASA Astrophysics Data System (ADS)

Bartelink, Dirk J.

1998-11-01

The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must recognize—test is also performed using IC's. A system interconnection is proposed using multiple chips fabricated with conventional silicon processes, including MEMS technology. The system resembles an MCM that can be joined without committing to final assembly to perform at-speed testing. 50-Ohm test probes never load the circuit; only intended neighboring chips are ever connected. A `back-plane' chip provides the connection layers for both inter- and intra-chip signals and also serves as the probe card, in analogy with membrane probes now used for single-chip testing. Intra-chip connections, which require complicated connections during test that exactly match the product, are then properly made and all waveforms and loading conditions under test will be identical to those of the product. The major benefit is that all front-end chip technologies can be merged—logic, memory, RF, even passives. ESD protection is required only on external system connections. Manufacturing test information will accurately characterize process faults and thus avoid the Known-Good-Die problem that has slowed the arrival of conventional MCM's.

Flip-chip integration of tilted VCSELs onto a silicon photonic integrated circuit.

PubMed

Lu, Huihui; Lee, Jun Su; Zhao, Yan; Scarcella, Carmelo; Cardile, Paolo; Daly, Aidan; Ortsiefer, Markus; Carroll, Lee; O'Brien, Peter

2016-07-25

In this article we describe a cost-effective approach for hybrid laser integration, in which vertical cavity surface emitting lasers (VCSELs) are passively-aligned and flip-chip bonded to a Si photonic integrated circuit (PIC), with a tilt-angle optimized for optical-insertion into standard grating-couplers. A tilt-angle of 10° is achieved by controlling the reflow of the solder ball deposition used for the electrical-contacting and mechanical-bonding of the VCSEL to the PIC. After flip-chip integration, the VCSEL-to-PIC insertion loss is -11.8 dB, indicating an excess coupling penalty of -5.9 dB, compared to Fibre-to-PIC coupling. Finite difference time domain simulations indicate that the penalty arises from the relatively poor match between the VCSEL mode and the grating-coupler.

Development and Industrialization of InGaN/GaN LEDs on Patterned Sapphire Substrates for Low Cost Emitter Architecture

DOE Office of Scientific and Technical Information (OSTI.GOV)

Flemish, Joseph; Soer, Wouter

2015-11-30

Patterned sapphire substrate (PSS) technology has proven to be an effective approach to improve efficacy and reduce cost of light-emitting diodes (LEDs). The volume emission from the transparent substrate leads to high package efficiency, while the simple and robust architecture of PSS-based LEDs enables low cost. PSS substrates have gained wide use in mid-power LEDs over the past years. In this project, Lumileds has developed and industrialized PSS and epitaxy technology for high- power flip-chip LEDs to bring these benefits to a broader range of applications and accelerate the adoption of energy-efficient solid-state lighting (SSL). PSS geometries were designed formore » highly efficient light extraction in a flip-chip architecture and high-volume manufacturability, and corresponding sapphire patterning and epitaxy manufacturing processes were integrally developed. Concurrently, device and package architectures were developed to take advantage of the PSS flip-chip die in different types of products that meet application needs. The developed PSS and epitaxy technology has been fully implemented in manufacturing at Lumileds’ San Jose, CA location, and incorporated in illumination-grade LED products that have been successfully introduced to the market, including LUXEON Q and LUXEON FlipChip White.« less

A novel model for simulating the racing effect in capillary-driven underfill process in flip chip

NASA Astrophysics Data System (ADS)

Zhu, Wenhui; Wang, Kanglun; Wang, Yan

2018-04-01

Underfill is typically applied in flip chips to increase the reliability of the electronic packagings. In this paper, the evolution of the melt-front shape of the capillary-driven underfill flow is studied through 3D numerical analysis. Two different models, the prevailing surface force model and the capillary model based on the wetted wall boundary condition, are introduced to test their applicability, where level set method is used to track the interface of the two phase flow. The comparison between the simulation results and experimental data indicates that, the surface force model produces better prediction on the melt-front shape, especially in the central area of the flip chip. Nevertheless, the two above models cannot simulate properly the racing effect phenomenon that appears during underfill encapsulation. A novel ‘dynamic pressure boundary condition’ method is proposed based on the validated surface force model. Utilizing this approach, the racing effect phenomenon is simulated with high precision. In addition, a linear relationship is derived from this model between the flow front location at the edge of the flip chip and the filling time. Using the proposed approach, the impact of the underfill-dispensing length on the melt-front shape is also studied.

Fluxless Bonding Processes Using Silver-Indium System for High Temperature Electronics and Silver Flip-Chip Interconnect Technology

NASA Astrophysics Data System (ADS)

Wu, Yuan-Yun

In this dissertation, fluxless silver (Ag)-indium (In) binary system bonding and Ag solid-state bonding are used between different bonded pairs which have large thermal expansion coefficient (CTE) mismatch and flip-chip interconnect bonding application. In contrast to the conventional soldering process, fluxless bonding technique eliminates contamination and reliability problems caused by flux to fabricate high quality joints. There are two section are reported. In the first section, the reactions of Ag-In binary system are presented. In the second section, the high melting temperature, thermal and electrical conductivity joint materials bonding by either Ag-In binary system bonding or solid-state bonding processes for different bonded pairs and flip-chip application are designed, developed, and reported. Our group have studied Ag-In system for several years and developed the bonding processes successfully. However, the detailed reactions of Ag and In were seldom studied. To design a proper bonding structure, it is necessary to understand the reaction between Ag and In. The systematic experiments were performed to investigate these reactions. A 40 um Ag layer was electroplated on copper (Cu) substrates, followed by indium layers of 1, 3, 5, 10, and 15 um, respectively. The samples were annealed at 180 °C in 0.1 torr vacuum. For samples with In thickness less than 5 mum, the joint compositions are Ag2In only (1 um) or AgIn2, Ag2In, and Ag solid solution (Ag) after annealing. No indium is identified. For 10 and 15 um thick In samples, In covers almost over the entire sample surface after annealing. Later, an Ag layer was annealed at 450 °C for 3 hours to grow Ag grains, followed by plating 10 um In and annealing at 180 °C. By annealing Ag before plating In, more In is kept in the structure during annealing at 180 °C. Based on above results, for those designs with In thinner than 5 um, the Ag layer needs to be annealed, prior to In plating in order to make a successful bonding. In this section, we further studied the Ag-In bonding and solid-state bonding for different bonded pairs and flip-chip application. For the silicon (Si) and aluminum (Al) pair, Al has been used as the material for interconnect pads on the ICs. However, its high CTE (23 x 10-6/°C) and non-solderable property limit its applications in electronic products. To overcome these problems, a fluxless Ag-In bonding was developed. Al was deposited Cr/Cu layer on the surface by E-beam evaporator to make it solderable. 15 um of Ag and 8 um of In were sequentially plated on the Al substrates and 15 um of Ag was on Si chips with Cr/Au coating layer. The bonding was performed at 180 °C in 0.1 torr vacuum. The joint consists of Ag/(Ag)/Ag2In/(Ag)/Ag. The joint can achieve a solidus temperature of beyond 600 °C. From shear test results, the shear strengths far exceed the requirement in MIL-STD-883H. Al is not considered as a favorable substrate material because it is not solderable and has a high CTE. The new method presented in this thesis seems to have surmounted these two challenges. Since Ag2In is weak inside the joint in Ag-In system, an annealed process was used to convert the joints into Ag solid solution (Ag) to increase the joint strength and ductility. Two copper (Cu) substrates were bonded at 180 °C without flux. Bonding samples were annealed at 200 °C for 1,000 hours (first design) and at 250 °C for 350 hours (second design), respectively. Scanning electron microscope with energy dispersive X-ray (EDX) analysis results indicate that the joint of the first design is an alloy of mostly (Ag) with micron-size Ag2In and Ag3In regions, and that of second design has converted to a single (Ag) phase. Shear test results show that the breaking forces far exceed the requirement in MIL-STD-883H. The joint solidus temperatures are 600 °C and 800 °C for the first and second designs, respectively. The research results have shown that high-strength and high temperature joints can be manufactured using fluxless low temperature processes with the Ag-In system and are valuable in developing high temperature package. (Abstract shortened by UMI.).

Effects of Solder Volume and Reflow Conditions on Self-Alignment Accuracy for Fan-Out Package Applications

NASA Astrophysics Data System (ADS)

Park, Hwan-Pil; Seo, Gwancheol; Kim, Sungchul; Kim, Young-Ho

2018-01-01

The effects of solder volume and reaction time between molten solder and a metal pad at the peak temperature of reflow on the self-alignment effect have been investigated in flip chip bonding. A glass die with two different pad designs and a flame retardant-4 (FR-4) organic substrate were used. Sn-3.0Ag-0.5Cu and Sn-3.5Ag solders were formed on Cu-organic solderability preservation (Cu-OSP) and electroless nickel electroless palladium immersion gold (ENEPIG) pads on FR-4 substrates using the stencil printing method. To assess the effect of solder volume, the thickness and opening size of the stencil mask were controlled. Reflow experiments were performed at 250°C with wetting times of 40 s, 55 s, 65 s, and 75 s. After flip chip reflow soldering, the bonding areas were cross-sectioned to inspect the shape of the interconnected solder using scanning electron microscopy. The results revealed that using an insufficient solder volume on the pad was responsible for die shifts larger than 1 μm, while a sufficient solder volume on the pad and a stable solder joint shape could ensure misalignment less than 1 μm. The Sn-3.0Ag-0.5Cu solder showed a lower die shift value than the Sn-3.5Ag solder because the Sn-3.0Ag-0.5Cu solder has stronger surface tension than the Sn-3.5Ag solder. Using a longer wetting time between the solder and the pad at the peak temperature also improved the die shift value because the increased reaction time changed the interconnected solder shape between the die and substrate from concave to convex, moving the die to a more accurate position. Furthermore, the restoring forces on die self-alignment influenced the die shift value. A stronger solder surface tension and a larger volume of solder on the pad produced stronger restoring forces for die self-alignment, thereby improving the die shift value.

Chip-scale white flip-chip light-emitting diode containing indium phosphide/zinc selenide quantum dots

NASA Astrophysics Data System (ADS)

Fan, Bingfeng; Yan, Linchao; Lao, Yuqin; Ma, Yanfei; Chen, Zimin; Ma, Xuejin; Zhuo, Yi; Pei, Yanli; Wang, Gang

2017-08-01

A method for preparing a quantum dot (QD)-white light-emitting diode (WLED) is reported. Holes were etched in the SiO2 layer deposited on the sapphire substrate of the flip-chip LED by inductively coupled plasma, and these holes were then filled with QDs. An ultraviolet-curable resin was then spin-coated on top of the QD-containing SiO2 layer, and the resin was cured to act as a protecting layer. The reflective sidewall structure minimized sidelight leakage. The fabrication of the QD-WLED is simple in preparation and compatible with traditional LED processes, which was the minimum size of the WLED chip-scale integrated package. InP/ZnS core-shell QDs were used as the converter in the WLED. A blue light-emitting diode with a flip-chip structure was used as the excitation source. The QD-WLED exhibited color temperatures from 5900 to 6400 K and Commission Internationale De L'Elcairage color coordinates from (0.315, 0.325) to (0.325, 0.317), under drive currents from 100 to 400 mA. The QD-WLED exhibited stable optoelectronic properties.

Decapsulation Method for Flip Chips with Ceramics in Microelectronic Packaging

NASA Astrophysics Data System (ADS)

Shih, T. I.; Duh, J. G.

2008-06-01

The decapsulation of flip chips bonded to ceramic substrates is a challenging task in the packaging industry owing to the vulnerability of the chip surface during the process. In conventional methods, such as manual grinding and polishing, the solder bumps are easily damaged during the removal of underfill, and the thin chip may even be crushed due to mechanical stress. An efficient and reliable decapsulation method consisting of thermal and chemical processes was developed in this study. The surface quality of chips after solder removal is satisfactory for the existing solder rework procedure as well as for die-level failure analysis. The innovative processes included heat-sink and ceramic substrate removal, solder bump separation, and solder residue cleaning from the chip surface. In the last stage, particular temperatures were selected for the removal of eutectic Pb-Sn, high-lead, and lead-free solders considering their respective melting points.

Electromigration induced high fraction of compound formation in SnAgCu flip chip solder joints with copper column

NASA Astrophysics Data System (ADS)

Xu, Luhua; Han, Jung-Kyu; Liang, Jarrett Jun; Tu, K. N.; Lai, Yi-Shao

2008-06-01

To overcome the effect of current crowding on electromigration-induced pancake-type void formation in flip chip solder joints, two types of Cu column in 90μm flip chip SnAgCu solder joints have been studied. They were (1) the solder contacts the Cu column at bottom and side walls and (2) the solder wets only the bottom surface of the copper column. With a current density of 1.6×104A/cm2 at 135°C, no failure was detected after 1290h. However, the resistance increased by about 10% due to the formation of a large fraction of intermetallic compounds. We found that electromigration has accelerated the consumption rate of copper column and converted almost the entire solder joint into intermetallic compound. Mechanically, drop impact test indicates a brittle fracture failure in the intermetallic. The electromigration critical product for the intermetallic is discussed.

3-D integrated heterogeneous intra-chip free-space optical interconnect.

PubMed

Ciftcioglu, Berkehan; Berman, Rebecca; Wang, Shang; Hu, Jianyun; Savidis, Ioannis; Jain, Manish; Moore, Duncan; Huang, Michael; Friedman, Eby G; Wicks, Gary; Wu, Hui

2012-02-13

This paper presents the first chip-scale demonstration of an intra-chip free-space optical interconnect (FSOI) we recently proposed. This interconnect system provides point-to-point free-space optical links between any two communication nodes, and hence constructs an all-to-all intra-chip communication fabric, which can be extended for inter-chip communications as well. Unlike electrical and other waveguide-based optical interconnects, FSOI exhibits low latency, high energy efficiency, and large bandwidth density, and hence can significantly improve the performance of future many-core chips. In this paper, we evaluate the performance of the proposed FSOI interconnect, and compare it to a waveguide-based optical interconnect with wavelength division multiplexing (WDM). It shows that the FSOI system can achieve significantly lower loss and higher energy efficiency than the WDM system, even with optimistic assumptions for the latter. A 1×1-cm2 chip prototype is fabricated on a germanium substrate with integrated photodetectors. Commercial 850-nm GaAs vertical-cavity-surface-emitting-lasers (VCSELs) and fabricated fused silica microlenses are 3-D integrated on top of the substrate. At 1.4-cm distance, the measured optical transmission loss is 5 dB, the crosstalk is less than -20 dB, and the electrical-to-electrical bandwidth is 3.3 GHz. The latter is mainly limited by the 5-GHz VCSEL.

276 nm Substrate-Free Flip-Chip AlGaN Light-Emitting Diodes

NASA Astrophysics Data System (ADS)

Hwang, Seongmo; Morgan, Daniel; Kesler, Amanda; Lachab, Mohamed; Zhang, Bin; Heidari, Ahmad; Nazir, Haseeb; Ahmad, Iftikhar; Dion, Joe; Fareed, Qhalid; Adivarahan, Vinod; Islam, Monirul; Khan, Asif

2011-03-01

Lateral-conduction, substrate-free flip-chip (SFFC) light-emitting diodes (LEDs) with peak emission at 276 nm are demonstrated for the first time. The AlGaN multiple quantum well LED structures were grown by metal-organic chemical vapor deposition (MOCVD) on thick-AlN laterally overgrown on sapphire substrates. To fabricate the SFFC LEDs, a newly-developed laser-assisted ablation process was employed to separate the substrate from the LED chips. The chips had physical dimensions of 1100×900 µm2, and were comprised of four devices each with a 100×100 µm2 junction area. Electrical and optical characterization of the devices revealed no noticeable degradation to their performance due to the laser-lift-off process.

Aeroflex Technology as Class-Y Demonstrator

NASA Technical Reports Server (NTRS)

Suh, Jong-ook; Agarwal, Shri; Popelar, Scott

2014-01-01

Modern space field programmable gate array (FPGA) devices with increased functional density and operational frequency, such as Xilinx Virtex 4 (V4) and S (V5), are packaged in non-hermetic ceramic flip chip forms. These next generation space parts were not qualified to the MIL-PRF-38535 Qualified Manufacturer Listing (QML) class-V when they were released because class-V was only intended for hermetic parts. In order to bring Xilinx V5 type packages into the QML system, it was suggested that class-Y be set up as a new category. From 2010 through 2014, a JEDEC G12 task group developed screening and qualification requirements for Class-Y products. The Document Standardization Division of the Defense Logistics Agency (DLA) has completed an engineering practice study. In parallel with the class-Y efforts, the NASA Electronic Parts and Packaging (NEPP) program has funded JPL to study potential reliability issues of the class-Y products. The major hurdle of this task was the absence of adequate research samples. Figure 1-1 shows schematic diagrams of typical structures of class-Y type products. Typically, class-Y products are either in ceramic flip chip column grid array (CGA) or land grid array (LGA) form. In class-Y packages, underfill and heat spread adhesive materials are directly exposed to the spacecraft environment due to their non-hermeticity. One of the concerns originally raised was that the underfill material could degrade due to the spacecraft environment and negatively impact the reliability of the package. In order to study such issues, it was necessary to use ceramic daisy chain flip chip package samples so that continuity of flip chip solder bumps could be monitored during the reliability tests. However, none of the commercially available class-Y daisy chain parts had electrical connections through flip chip solder bumps; only solder columns were daisy chained, which made it impossible to test continuity of flip chip solder bumps without using extremely costly functional parts. Among space parts manufacturers who were interested in producing class-Y products, Aeroflex Microelectronic Solutions-HiRel had been developing assembly processes using their internal R&D classy type samples. In early 2012, JPL and Aeroflex initiated a collaboration to study reliability of the Aeroflex technology as a class-Y demonstrator.

Repairable chip bonding/interconnect process

DOEpatents

Bernhardt, Anthony F.; Contolini, Robert J.; Malba, Vincent; Riddle, Robert A.

1997-01-01

A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.

Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications.

PubMed

Kirk, Andrew G; Plant, David V; Szymanski, Ted H; Vranesic, Zvonko G; Tooley, Frank A P; Rolston, David R; Ayliffe, Michael H; Lacroix, Frederic K; Robertson, Brian; Bernier, Eric; Brosseau, Daniel F

2003-05-10

Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.

Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications

NASA Astrophysics Data System (ADS)

Kirk, Andrew G.; Plant, David V.; Szymanski, Ted H.; Vranesic, Zvonko G.; Tooley, Frank A. P.; Rolston, David R.; Ayliffe, Michael H.; Lacroix, Frederic K.; Robertson, Brian; Bernier, Eric; Brosseau, Daniel F.

2003-05-01

Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.

Methods for Trustworthy Design of On-Chip Bus Interconnect for General-Purpose Processors

DTIC Science & Technology

2012-03-01

Technology Andrew Huang, was able to test the security properties of HyperTransport bus protocol on an Xbox [20]. In his research, he was able to...TRUSTWORTHY DESIGN OF ON -CHIP BUS INTERCONNECT FOR GENERAL-PURPOSE PROCESSORS by Jay F. Elson March 2012 Thesis Advisor: Ted Huffmire Second...AND DATES COVERED Master’s Thesis 4. TITLE AND SUBTITLE Methods for Trustworthy Design of On -Chip Bus Interconnect for General-Purpose Processors 5

Spatial redistribution of radiation in flip-chip photodiodes based on InAsSbP/InAs double heterostructures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zakgeim, A. L.; Il’inskaya, N. D.; Karandashev, S. A.

2017-02-15

The spatial distribution of equilibrium and nonequilibrium (including luminescent) IR (infrared) radiation in flip-chip photodiodes based on InAsSbP/InAs double heterostructures (λ{sub max} = 3.4 μm) is measured and analyzed; the structural features of the photodiodes, including the reflective properties of the ohmic contacts, are taken into account. Optical area enhancement due to multiple internal reflection in photodiodes with different geometric characteristics is estimated.

Flip Chip Bonding of 68 x 68 MWIR LED Arrays

DTIC Science & Technology

2009-01-01

transmission of IR light through GaSb material varies between 5%–30% and depends on the type of substrate dopants (n- or p-type). Hence, for bottom...emission regions (8.9/16 monolayer’s (ml) InAs/GaSb) separated by (n InAs/GaSb super lattice grade)/(p+ GaSb) tunnel junctions. Graded super lattices were...flip chip bonding process. Besides four corner LED test pads, there are 296 bonding pads in the CMOS driver to bias each LED pixel independently. The

Repairable chip bonding/interconnect process

DOEpatents

Bernhardt, A.F.; Contolini, R.J.; Malba, V.; Riddle, R.A.

1997-08-05

A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules is disclosed. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder. 10 figs.

WDM mid-board optics for chip-to-chip wavelength routing interconnects in the H2020 ICT-STREAMS

NASA Astrophysics Data System (ADS)

Kanellos, G. T.; Pleros, N.

2017-02-01

Multi-socket server boards have emerged to increase the processing power density on the board level and further flatten the data center networks beyond leaf-spine architectures. Scaling however the number of processors per board puts current electronic technologies into challenge, as it requires high bandwidth interconnects and high throughput switches with increased number of ports that are currently unavailable. On-board optical interconnection has proved the potential to efficiently satisfy the bandwidth needs, but their use has been limited to parallel links without performing any smart routing functionality. With CWDM optical interconnects already a commodity, cyclical wavelength routing proposed to fit the datacom for rack-to-rack and board-to-board communication now becomes a promising on-board routing platform. ICT-STREAMS is a European research project that aims to combine WDM parallel on-board transceivers with a cyclical AWGR, in order to create a new board-level, chip-to-chip interconnection paradigm that will leverage WDM parallel transmission to a powerful wavelength routing platform capable to interconnect multiple processors with unprecedented bandwidth and throughput capacity. Direct, any-to-any, on-board interconnection of multiple processors will significantly contribute to further flatten the data centers and facilitate east-west communication. In the present communication, we present ICT-STREAMS on-board wavelength routing architecture for multiple chip-to-chip interconnections and evaluate the overall system performance in terms of throughput and latency for several schemes and traffic profiles. We also review recent advances of the ICT-STREAMS platform key-enabling technologies that span from Si in-plane lasers and polymer based electro-optical circuit boards to silicon photonics transceivers and photonic-crystal amplifiers.

Flip-chip replacement within the constraints imposed by multilayer ceramic (MLC) modules

NASA Astrophysics Data System (ADS)

Puttlitz, Karl J.

1984-01-01

Economics often dictates that suitable module rework procedures be established to replace solder bump devices (flip chips) reflowed to multichip carriers. These operations are complicated, owing to various constraints such as the substrate's physical and mechanical properties, close proximity of surface features, etc. This paper describes the constraints and the methods to circumvent them. An order of preference based upon the degree of constraint is recommended to achieve device removal and subsequent site dress of the residual solder left on the substrate. It has been determined that rework (device replacement) can be successfully achieved in even highly constricted situations. This is illustrated by the example of utilizing a localized heating technique, hot gas, to remove solder from microsockets from which chips were previously removed. Microsockets are areas to which chips are reflowed to the top surface of IBM's densely populated multilayer ceramic (MLC) modules, thus forming the so-called controlled collapse chip connection or C-4. The microsocket patterns are thus identical to the chip footprint.

Cost-effective parallel optical interconnection module based on fully passive-alignment process

NASA Astrophysics Data System (ADS)

Son, Dong Hoon; Heo, Young Soon; Park, Hyoung-Jun; Kang, Hyun Seo; Kim, Sung Chang

2017-11-01

In optical interconnection technology, high-speed and large data transitions with low error rate and cost reduction are key issues for the upcoming 8K media era. The researchers present notable types of optical manufacturing structures of a four-channel parallel optical module by fully passive alignment, which are able to reduce manufacturing time and cost. Each of the components, such as vertical-cavity surface laser/positive-intrinsic negative-photodiode array, microlens array, fiber array, and receiver (RX)/transmitter (TX) integrated circuit, is integrated successfully using flip-chip bonding, die bonding, and passive alignment with a microscope. Clear eye diagrams are obtained by 25.78-Gb/s (for TX) and 25.7-Gb/s (for RX) nonreturn-to-zero signals of pseudorandom binary sequence with a pattern length of 231 to 1. The measured responsivity and minimum sensitivity of the RX are about 0.5 A/W and ≤-6.5 dBm at a bit error rate (BER) of 10-12, respectively. The optical power margin at a BER of 10-12 is 7.5 dB, and cross talk by the adjacent channel is ≤1 dB.

Development of advanced micromirror arrays by flip-chip assembly

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper presents the design, commercial prefabrication, modeling and testing of advanced micromirror arrays fabricated using a novel, simple and inexpensive flip-chip assembly technique. Several polar piston arrays and rectangular cantilever arrays were fabricated using flip-chip assembly by which the upper layers of the array are fabricated on a separate chip and then transferred to a receiving module containing the lower layers. Typical polar piston arrays boast 98.3% active surface area, highly planarized surfaces, low address potentials compatible with CMOS electronics, highly standardized actuation between devices, and complex segmentation of mirror surfaces which allows for custom aberration configurations. Typical cantilever arrays boast large angles of rotation as well as an average surface planarity of only 1.779 nm of RMS roughness across 100 +m mirrors. Continuous torsion devices offer stable operation through as much as six degrees of rotation while binary operation devices offer stable activated positions with as much as 20 degrees of rotation. All arrays have desirable features of costly fabrication services like five structural layers and planarized mirror surfaces, but are prefabricated in the less costly MUMPs process. Models are developed for all devices and used to compare empirical data.

Multi-scale reflection modulator-based optical interconnects

NASA Astrophysics Data System (ADS)

Nair, Rohit

This dissertation describes the design, analysis, and experimental validation of micro- and macro-optical components for implementing optical interconnects at multiple scales for varied applications. Three distance scales are explored: millimeter, centimeter, and meter-scales. At the millimeter-scale, we propose the use of optical interconnects at the intra-chip level. With the rapid scaling down of CMOS critical dimensions in accordance to Moore's law, the bandwidth requirements of global interconnects in microprocessors has exceeded the capabilities of metal links. These are the wires that connect the most remote parts of the chip and are disproportionately problematic in terms of chip area and power consumption. Consequently, in the mid-2000s, we saw a shift in the chip architecture: a move towards multicore designs. However, this only delays the inevitable communication bottleneck between cores. To satisfy this bandwidth, we propose to replace the global metal interconnects with optical interconnects. We propose to use the hybrid integration of silicon with GaAs/AlAs-based multiple quantum well devices as optical modulators and photodetectors along with polymeric waveguides to transport the light. We use grayscale lithography to fabricate curved facets into the waveguides to couple light into the modulators and photodetectors. Next, at the chip-to-chip level in high-performance multiprocessor computing systems, communication distances vary from a few centimeters to tens of centimeters. An optical design for coupling light from off-chip lasers to on-chip surface-normal modulators is proposed in order to implement chip-to-chip free-space optical interconnects. The method uses a dual-prism module constructed from prisms made of two different glasses. The various alignment tolerances of the proposed system are investigated and found to be well within pick-and-place accuracies. For the off-chip lasers, vertical cavity surface emitting lasers (VCSELs) are proposed. The rationale behind using on-chip modulators rather than VCSELs is to avoid VCSEL thermal loads on chip, and because of higher reliability of modulators than VCSELs. Particularly above 10Gbps, an empirical model developed shows the rapid decrease of VCSEL median time to failure vs. data rate. Thus the proposed interconnect scheme which utilizes continuous wave VCSELs that are externally modulated by on-chip multiple quantum well modulators is applicable for chip-to-chip optical interconnects at 20Gbps and higher line data rates. Finally, for applications such as remote telemetry, where the interrogation distances can vary from a few meters to tens or even hundreds of meters we demonstrate a modulated retroreflector that utilizes InGaAs/InAlAs-based large-area multiple quantum well modulators on all three faces of a retroreflector. The large-area devices, fabricated by metalorganic chemical vapor deposition, are characterized in terms of the yield and leakage currents. A yield higher than that achieved previously using devices fabricated by molecular beam epitaxy is observed. The retroreflector module is constructed using standard FR4 printed circuit boards, thereby simplifying the wiring issue. A high optical contrast ratio of 8.23dB is observed for a drive of 20V. A free-standing PCB retroreflector is explored and found to have insufficient angular tolerances (+/-0.5 degrees). We show that the angular errors in the corner-cube construction can be corrected for using off-the-shelf optical components as opposed to mounting the PCBs on a precision corner cube, as has been done previously.

Miniaturized tool for optogenetics based on an LED and an optical fiber interfaced by a silicon housing.

PubMed

Schwaerzle, M; Elmlinger, P; Paul, O; Ruther, P

2014-01-01

This paper reports on the design, simulation, fabrication and characterization of a tool for optogenetic experiments based on a light emitting diode (LED). A minimized silicon (Si) interface houses the LED and aligns it to an optical fiber. With a Si housing size of 550×500×380 μm(3) and an electrical interconnection of the LED by a highly flexible polyimide (PI) ribbon cable is the system very variable. PI cables and Si housings are fabricated using established microsystem technologies. A 270×220×50 μm(3) bare LED chip is flip-chip-bonded onto the PI cable. The Si housing is adhesively attached to the PI cable, thereby hosting the LED in a recess. An opposite recess guides the optical fiber with a diameter of 125 μm. An aperture in-between restricts the emitted LED light to the fiber core. The optical fiber is adhesively fixed into the Si housing recess. An optical output intensity at the fiber end facet of 1.71 mW/mm(2) was achieved at a duty cycle of 10 % and a driving current of 30 mA.

AE (Acoustic Emission) for Flip-Chip CGA/FCBGA Defect Detection

NASA Technical Reports Server (NTRS)

Ghaffarian, Reza

2014-01-01

C-mode scanning acoustic microscopy (C-SAM) is a nondestructive inspection technique that uses ultrasound to show the internal feature of a specimen. A very high or ultra-high-frequency ultrasound passes through a specimen to produce a visible acoustic microimage (AMI) of its inner features. As ultrasound travels into a specimen, the wave is absorbed, scattered or reflected. The response is highly sensitive to the elastic properties of the materials and is especially sensitive to air gaps. This specific characteristic makes AMI the preferred method for finding "air gaps" such as delamination, cracks, voids, and porosity. C-SAM analysis, which is a type of AMI, was widely used in the past for evaluation of plastic microelectronic circuits, especially for detecting delamination of direct die bonding. With the introduction of the flip-chip die attachment in a package; its use has been expanded to nondestructive characterization of the flip-chip solder bumps and underfill. Figure 1.1 compares visual and C-SAM inspection approaches for defect detection, especially for solder joint interconnections and hidden defects. C-SAM is specifically useful for package features like internal cracks and delamination. C-SAM not only allows for the visualization of the interior features, it has the ability to produce images on layer-by-layer basis. Visual inspection; however, is only superior to C-SAM for the exposed features including solder dewetting, microcracks, and contamination. Ideally, a combination of various inspection techniques - visual, optical and SEM microscopy, C-SAM, and X-ray - need to be performed in order to assure quality at part, package, and system levels. This reports presents evaluations performed on various advanced packages/assemblies, especially the flip-chip die version of ball grid array/column grid array (BGA/CGA) using C-SAM equipment. Both external and internal equipment was used for evaluation. The outside facility provided images of the key features that could be detected using the most advanced C-SAM equipment with a skilled operator. Investigation continued using in-house equipment with its limitations. For comparison, representative X-rays of the assemblies were also gathered to show key defect detection features of these non-destructive techniques. Key images gathered and compared are: Compared the images of 2D X-ray and C-SAM for a plastic LGA assembly showing features that could be detected by either NDE technique. For this specific case, X-ray was a clear winner. Evaluated flip-chip CGA and FCBGA assemblies with and without heat sink by C-SAM. Only the FCCGA package that had no heat sink could be fully analyzed for underfill and bump quality. Cross-sectional microscopy did not revealed peripheral delamination features detected by C-SAM. Analyzed a number of fine pitch PBGA assemblies by C-SAM. Even though the internal features of the package assemblies could be detected, C-SAM was unable to detect solder joint failure at either the package or board level. Twenty times touch ups by solder iron with 700degF tip temperature, each with about 5 second duration, did not induce defects to be detected by C-SAM images. Other techniques need to be considered to induce known defects for characterization. Given NASA's emphasis on the use of microelectronic packages and assemblies and quality assurance on workmanship defect detection, understanding key features of various inspection systems that detect defects in the early stages of package and assembly is critical to developing approaches that will minimize future failures. Additional specific, tailored non-destructive inspection approaches could enable low-risk insertion of these advanced electronic packages having hidden and fine features.

A new Cu(GeNx) alloy film for industrial applications

NASA Astrophysics Data System (ADS)

Lin, Chon-Hsin

2014-11-01

In this study, a copper alloy [Cu(GeNx)] film is developed for industrial applications by cosputtering Cu and Ge targets on a barrierless Si substrate within a vacuum chamber sparsely filled with N2 gas. Through extensive tests conducted in this study, the alloy film shows good thermal stability and adhesion to the substrate with no noticeable interactions between the film and the substrate after annealing at 720 °C for 1 h. The new Cu(GeNx) alloy film also renders adequate wetting for solders, shows good solderability, and has a dissolution rate lower than pure Cu by at least one order of magnitude, in addition to having a comparable consumption rate to Ni. The alloy film seems suitable for industrial applications in, e.g., barrierless Si metallization, interconnect manufacture and, the replacement of the wetting and diffusion layers for flip-chip solder joints in conventional metallurgy.

Adaptive Code Division Multiple Access Protocol for Wireless Network-on-Chip Architectures

NASA Astrophysics Data System (ADS)

Vijayakumaran, Vineeth

Massive levels of integration following Moore's Law ushered in a paradigm shift in the way on-chip interconnections were designed. With higher and higher number of cores on the same die traditional bus based interconnections are no longer a scalable communication infrastructure. On-chip networks were proposed enabled a scalable plug-and-play mechanism for interconnecting hundreds of cores on the same chip. Wired interconnects between the cores in a traditional Network-on-Chip (NoC) system, becomes a bottleneck with increase in the number of cores thereby increasing the latency and energy to transmit signals over them. Hence, there has been many alternative emerging interconnect technologies proposed, namely, 3D, photonic and multi-band RF interconnects. Although they provide better connectivity, higher speed and higher bandwidth compared to wired interconnects; they also face challenges with heat dissipation and manufacturing difficulties. On-chip wireless interconnects is one other alternative proposed which doesn't need physical interconnection layout as data travels over the wireless medium. They are integrated into a hybrid NOC architecture consisting of both wired and wireless links, which provides higher bandwidth, lower latency, lesser area overhead and reduced energy dissipation in communication. However, as the bandwidth of the wireless channels is limited, an efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. This thesis proposes using a multiple access mechanism such as Code Division Multiple Access (CDMA) to enable multiple transmitter-receiver pairs to send data over the wireless channel simultaneously. It will be shown that such a hybrid wireless NoC with an efficient CDMA based MAC protocol can significantly increase the performance of the system while lowering the energy dissipation in data transfer. In this work it is shown that the wireless NoC with the proposed CDMA based MAC protocol outperformed the wired counterparts and several other wireless architectures proposed in literature in terms of bandwidth and packet energy dissipation. Significant gains were observed in packet energy dissipation and bandwidth even with scaling the system to higher number of cores. Non-uniform traffic simulations showed that the proposed CDMA-WiNoC was consistent in bandwidth across all traffic patterns. It is also shown that the CDMA based MAC scheme does not introduce additional reliability concerns in data transfer over the on-chip wireless interconnects.

Single-chip photonic transceiver based on bulk-silicon, as a chip-level photonic I/O platform for optical interconnects.

PubMed

Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Kim, In Gyoo; Oh, Jin Hyuk; Kim, Sun Ae; Park, Jaegyu; Kim, Sanggi

2015-06-10

When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube, and LAN, SAN, data center and network applications.

A crunch on thermocompression flip chip bonding

NASA Astrophysics Data System (ADS)

Suppiah, Sarveshvaran; Ong, Nestor Rubio; Sauli, Zaliman; Sarukunaselan, Karunavani; Alcain, Jesselyn Barro; Mahmed, Norsuria; Retnasamy, Vithyacharan

2017-09-01

This study discussed the evolution and important findings, critical technical challenges, solutions and bonding equipment of flip chip thermo compression bonding (TCB). The bonding force, temperature and time were the key bonding parameters that need to be tweaked based on the researches done by others. TCB technology worked well with both pre-applied underfill and flux (still under development). Lower throughput coupled with higher processing costs was example of challenges in the TCB technology. The paper is concluded with a brief description of the current equipment used in thermo compression process.

Comparison of microrings and microdisks for high-speed optical modulation in silicon photonics

NASA Astrophysics Data System (ADS)

Ying, Zhoufeng; Wang, Zheng; Zhao, Zheng; Dhar, Shounak; Pan, David Z.; Soref, Richard; Chen, Ray T.

2018-03-01

The past several decades have witnessed the gradual transition from electrical to optical interconnects, ranging from long-haul telecommunication to chip-to-chip interconnects. As one type of key component in integrated optical interconnect and high-performance computing, optical modulators have been well developed these past few years, including ultrahigh-speed microring and microdisk modulators. In this paper, a comparison between microring and microdisk modulators is well analyzed in terms of dimensions, static and dynamic power consumption, and fabrication tolerance. The results show that microdisks have advantages over microrings in these aspects, which gives instructions to the chip design of high-density integrated systems for optical interconnects and optical computing.

Optical Interconnections for VLSI Computational Systems Using Computer-Generated Holography.

NASA Astrophysics Data System (ADS)

Feldman, Michael Robert

Optical interconnects for VLSI computational systems using computer generated holograms are evaluated in theory and experiment. It is shown that by replacing particular electronic connections with free-space optical communication paths, connection of devices on a single chip or wafer and between chips or modules can be improved. Optical and electrical interconnects are compared in terms of power dissipation, communication bandwidth, and connection density. Conditions are determined for which optical interconnects are advantageous. Based on this analysis, it is shown that by applying computer generated holographic optical interconnects to wafer scale fine grain parallel processing systems, dramatic increases in system performance can be expected. Some new interconnection networks, designed to take full advantage of optical interconnect technology, have been developed. Experimental Computer Generated Holograms (CGH's) have been designed, fabricated and subsequently tested in prototype optical interconnected computational systems. Several new CGH encoding methods have been developed to provide efficient high performance CGH's. One CGH was used to decrease the access time of a 1 kilobit CMOS RAM chip. Another was produced to implement the inter-processor communication paths in a shared memory SIMD parallel processor array.

Thin-film chip-to-substrate interconnect and methods for making same

DOEpatents

Tuckerman, D.B.

1988-06-06

Integrated circuit chips are electrically connected to a silicon wafer interconnection substrate. Thin film wiring is fabricated down bevelled edges of the chips. A subtractive wire fabrication method uses a series of masks and etching steps to form wires in a metal layer. An additive method direct laser writes or deposits very thin lines which can then be plated up to form wires. A quasi-additive or subtractive/additive method forms a pattern of trenches to expose a metal surface which can nucleate subsequent electrolytic deposition of wires. Low inductance interconnections on a 25 micron pitch (1600 wires on a 1 cm square chip) can be produced. The thin film hybrid interconnect eliminates solder joints or welds, and minimizes the levels of metallization. Advantages include good electrical properties, very high wiring density, excellent backside contact, compactness, and high thermal and mechanical reliability. 6 figs.

Thin-film chip-to-substrate interconnect and methods for making same

DOEpatents

Tuckerman, David B.

1991-01-01

Integrated circuit chips are electrically connected to a silica wafer interconnection substrate. Thin film wiring is fabricated down bevelled edges of the chips. A subtractive wire fabrication method uses a series of masks and etching steps to form wires in a metal layer. An additive method direct laser writes or deposits very thin metal lines which can then be plated up to form wires. A quasi-additive or subtractive/additive method forms a pattern of trenches to expose a metal surface which can nucleate subsequent electrolytic deposition of wires. Low inductance interconnections on a 25 micron pitch (1600 wires on a 1 cm square chip) can be produced. The thin film hybrid interconnect eliminates solder joints or welds, and minimizes the levels of metallization. Advantages include good electrical properties, very high wiring density, excellent backside contact, compactness, and high thermal and mechanical reliability.

Low-power chip-level optical interconnects based on bulk-silicon single-chip photonic transceivers

NASA Astrophysics Data System (ADS)

Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Kim, In Gyoo; Kim, Sun Ae; Oh, Jin Hyuk; Park, Jaegyu; Kim, Sanggi

2016-03-01

We present new scheme for chip-level photonic I/Os, based on monolithically integrated vertical photonic devices on bulk silicon, which increases the integration level of PICs to a complete photonic transceiver (TRx) including chip-level light source. A prototype of the single-chip photonic TRx based on a bulk silicon substrate demonstrated 20 Gb/s low power chip-level optical interconnects between fabricated chips, proving that this scheme can offer compact low-cost chip-level I/O solutions and have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, 3D-IC, and LAN/SAN/data-center and network applications.

Numerical simulation of CTE mismatch and thermal-structural stresses in the design of interconnects

NASA Astrophysics Data System (ADS)

Peter, Geoffrey John M.

With the ever-increasing chip complexity, interconnects have to be designed to meet the new challenges. Advances in optical lithography have made chip feature sizes available today at 70 nm dimensions. With advances in Extreme Ultraviolet Lithography, X-ray Lithography, and Ion Projection Lithography it is expected that the line width will further decrease to 20 nm or less. With the decrease in feature size, the number of active devices on the chip increases. With higher levels of circuit integration, the challenge is to dissipate the increased heat flux from the chip surface area. Thermal management considerations include coefficient of thermal expansion (CTE) matching to prevent failure between the chip and the board. This in turn calls for improved system performance and reliability of the electronic structural systems. Experience has shown that in most electronic systems, failures are mostly due to CTE mismatch between the chip, board, and the solder joint (solder interconnect). The resulting high thermal-structural stress and strain due to CTE mismatch produces cracks in the solder joints with eventual failure of the electronic component. In order to reduce the thermal stress between the chip, board, and the solder joint, this dissertation examines the effect of inserting wire bundle (wire interconnect) between the chip and the board. The flexibility of the wires or fibers would reduce the stress at the rigid joints. Numerical simulations of two, and three-dimensional models of the solder and wire interconnects are examined. The numerical simulation is linear in nature and is based on linear isotropic material properties. The effect of different wire material properties is examined. The effect of varying the wire diameter is studied by changing the wire diameter. A major cause of electronic equipment failure is due to fatigue failure caused by thermal cycling, and vibrations. A two-dimensional modal and harmonic analysis was simulated for the wire interconnect and the solder interconnect. The numerical model simulated using ANSYS program was validated with the numerical/experimental results of other published researchers. In addition the results were cross-checked by IDEAS program. A prototype non-working wire interconnect is proposed to emphasize practical application. The numerical analysis, in this dissertation is based on a U.S. Patent granted to G. Peter(42).

Light-extraction enhancement of GaN-based 395  nm flip-chip light-emitting diodes by an Al-doped ITO transparent conductive electrode.

PubMed

Xu, Jin; Zhang, Wei; Peng, Meng; Dai, Jiangnan; Chen, Changqing

2018-06-01

The distinct ultraviolet (UV) light absorption of indium tin oxide (ITO) limits the performance of GaN-based near-UV light-emitting diodes (LEDs). Herein, we report an Al-doped ITO with enhanced UV transmittance and low sheet resistance as the transparent conductive electrode for GaN-based 395 nm flip-chip near-UV LEDs. The thickness dependence of optical and electrical properties of Al-doped ITO films is investigated. The optimal Al-doped ITO film exhibited a transmittance of 93.2% at 395 nm and an average sheet resistance of 30.1  Ω/sq. Meanwhile, at an injection current of 300 mA, the forward voltage decreased from 3.14 to 3.11 V, and the light output power increased by 13% for the 395 nm near-UV flip-chip LEDs with the optimal Al-doped ITO over those with pure ITO. This Letter provides a simple and repeatable approach to further improve the light extraction efficiency of GaN-based near-UV LEDs.

Sparsely-Bonded CMOS Hybrid Imager

NASA Technical Reports Server (NTRS)

Sun, Chao (Inventor); Jones, Todd J. (Inventor); Nikzad, Shouleh (Inventor); Newton, Kenneth W. (Inventor); Cunningham, Thomas J. (Inventor); Hancock, Bruce R. (Inventor); Dickie, Matthew R. (Inventor); Hoenk, Michael E. (Inventor); Wrigley, Christopher J. (Inventor); Pain, Bedabrata (Inventor)

2015-01-01

A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.

Single-chip photonic transceiver based on bulk-silicon, as a chip-level photonic I/O platform for optical interconnects

PubMed Central

Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Gyoo Kim, In; Hyuk Oh, Jin; Ae Kim, Sun; Park, Jaegyu; Kim, Sanggi

2015-01-01

When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube, and LAN, SAN, data center and network applications. PMID:26061463

A 16K-bit static IIL RAM with 25-ns access time

NASA Astrophysics Data System (ADS)

Inabe, Y.; Hayashi, T.; Kawarada, K.; Miwa, H.; Ogiue, K.

1982-04-01

A 16,384 x 1-bit RAM with 25-ns access time, 600-mW power dissipation, and 33 sq mm chip size has been developed. Excellent speed-power performance with high packing density has been achieved by an oxide isolation technology in conjunction with novel ECL circuit techniques and IIL flip-flop memory cells, 980 sq microns (35 x 28 microns) in cell size. Development results have shown that IIL flip-flop memory cell is a trump card for assuring achievement of a high-performance large-capacity bipolar RAM, in the above 16K-bit/chip area.

Low-power, transparent optical network interface for high bandwidth off-chip interconnects.

PubMed

Liboiron-Ladouceur, Odile; Wang, Howard; Garg, Ajay S; Bergman, Keren

2009-04-13

The recent emergence of multicore architectures and chip multiprocessors (CMPs) has accelerated the bandwidth requirements in high-performance processors for both on-chip and off-chip interconnects. For next generation computing clusters, the delivery of scalable power efficient off-chip communications to each compute node has emerged as a key bottleneck to realizing the full computational performance of these systems. The power dissipation is dominated by the off-chip interface and the necessity to drive high-speed signals over long distances. We present a scalable photonic network interface approach that fully exploits the bandwidth capacity offered by optical interconnects while offering significant power savings over traditional E/O and O/E approaches. The power-efficient interface optically aggregates electronic serial data streams into a multiple WDM channel packet structure at time-of-flight latencies. We demonstrate a scalable optical network interface with 70% improvement in power efficiency for a complete end-to-end PCI Express data transfer.

Optical computing research

NASA Astrophysics Data System (ADS)

Goodman, Joseph W.

1987-10-01

Work Accomplished: OPTICAL INTERCONNECTIONS - the powerful interconnect abilities of optical beams have led much optimism about the possible roles for optics in solving interconnect problems at various levels of computer architecture. Examined were the powerful requirements of optical interconnects at the gate-to-gate and chip-to-chip levels. OPTICAL NEUTRAL NETWORKS - basic studies of the convergence properties on the Holfield model, based on mathematical approach - graph theory. OPTICS AND ARTIFICIAL INTELLIGENCE - review the field of optical processing and artificial intelligence, with the aim of finding areas that might be particularly attractive for future investigation(s).

Quantifying the benefits of improved rolling of chip seals : final report, June 2008.

DOT National Transportation Integrated Search

2008-06-01

This report presents an improvement in the rolling protocol for chip seals based on an evaluation of aggregate : retention performance and aggregate embedment depth. The flip-over test (FOT), Vialit test, modified sand circle : test, digital image pr...

Optical interconnection networks for high-performance computing systems

NASA Astrophysics Data System (ADS)

Biberman, Aleksandr; Bergman, Keren

2012-04-01

Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. Chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, offer unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of our work, we demonstrate such feasibility of waveguides, modulators, switches and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. We propose novel silicon photonic devices, subsystems, network topologies and architectures to enable unprecedented performance of these photonic interconnection networks. Furthermore, the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers.

Architecture for VLSI design of Reed-Solomon encoders

NASA Technical Reports Server (NTRS)

Liu, K. Y.

1981-01-01

The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255,223) RD encoder requiring around 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring less power and having a higher reliability.

Mean-time-to-failure study of flip chip solder joints on Cu/Ni(V)/Al thin-film under-bump-metallization

NASA Astrophysics Data System (ADS)

Choi, W. J.; Yeh, E. C. C.; Tu, K. N.

2003-11-01

Electromigration of eutectic SnPb flip chip solder joints and their mean-time-to-failure (MTTF) have been studied in the temperature range of 100 to 140 °C with current densities of 1.9 to 2.75×104 A/cm2. In these joints, the under-bump-metallization (UBM) on the chip side is a multilayer thin film of Al/Ni(V)/Cu, and the metallic bond-pad on the substrate side is a very thick, electroless Ni layer covered with 30 nm of Au. When stressed at the higher current densities, the MTTF was found to decrease much faster than what is expected from the published Black's equation. The failure occurred by interfacial void propagation at the cathode side, and it is due to current crowding near the contact interface between the solder bump and the thin-film UBM. The current crowding is confirmed by a simulation of current distribution in the solder joint. Besides the interfacial void formation, the intermetallic compounds formed on the UBM as well as the Ni(V) film in the UBM have been found to dissolve completely into the solder bump during electromigration. Therefore, the electromigation failure is a combination of the interfacial void formation and the loss of UBM. Similar findings in eutectic SnAgCu flip chip solder joints have also been obtained and compared.

A low-cost, manufacturable method for fabricating capillary and optical fiber interconnects for microfluidic devices.

PubMed

Hartmann, Daniel M; Nevill, J Tanner; Pettigrew, Kenneth I; Votaw, Gregory; Kung, Pang-Jen; Crenshaw, Hugh C

2008-04-01

Microfluidic chips require connections to larger macroscopic components, such as light sources, light detectors, and reagent reservoirs. In this article, we present novel methods for integrating capillaries, optical fibers, and wires with the channels of microfluidic chips. The method consists of forming planar interconnect channels in microfluidic chips and inserting capillaries, optical fibers, or wires into these channels. UV light is manually directed onto the ends of the interconnects using a microscope. UV-curable glue is then allowed to wick to the end of the capillaries, fibers, or wires, where it is cured to form rigid, liquid-tight connections. In a variant of this technique, used with light-guiding capillaries and optical fibers, the UV light is directed into the capillaries or fibers, and the UV-glue is cured by the cone of light emerging from the end of each capillary or fiber. This technique is fully self-aligned, greatly improves both the quality and the manufacturability of the interconnects, and has the potential to enable the fabrication of interconnects in a fully automated fashion. Using these methods, including a semi-automated implementation of the second technique, over 10,000 interconnects have been formed in almost 2000 microfluidic chips made of a variety of rigid materials. The resulting interconnects withstand pressures up to at least 800psi, have unswept volumes estimated to be less than 10 femtoliters, and have dead volumes defined only by the length of the capillary.

Time-domain finite-difference based analysis of induced crosstalk in multiwall carbon nanotube interconnects

NASA Astrophysics Data System (ADS)

Kumar, Amit; Nehra, Vikas; Kaushik, Brajesh Kumar

2017-08-01

Graphene rolled-up cylindrical sheets i.e. carbon nanotubes (CNTs) is one of the finest and emerging research area. This paper presents the investigation of induced crosstalk in coupled on-chip multiwalled carbon nanotube (MWCNT) interconnects using finite-difference analysis (FDA) in time-domain i.e. the finite-difference time-domain (FDTD) method. The exceptional properties of versatile MWCNTs profess their candidacy to replace conventional on-chip copper interconnects. Time delay and crosstalk noise have been evaluated for coupled on-chip MWCNT interconnects. With a decrease in CNT length, the obtained results for an MWCNT shows that transmission performance improves as the number of shells increases. It has been observed that the obtained results using the finite-difference time domain (FDTD) technique shows a very close match with the HSPICE simulated results.

Development of n+-in-p planar pixel quadsensor flip-chipped with FE-I4 readout ASICs

NASA Astrophysics Data System (ADS)

Unno, Y.; Kamada, S.; Yamamura, K.; Yamamoto, H.; Hanagaki, K.; Hori, R.; Ikegami, Y.; Nakamura, K.; Takubo, Y.; Takashima, R.; Tojo, J.; Kono, T.; Nagai, R.; Saito, S.; Sugibayashi, K.; Hirose, M.; Jinnouchi, O.; Sato, S.; Sawai, H.; Hara, K.; Sato, Kz.; Sato, Kj.; Iwabuchi, S.; Suzuki, J.

2017-01-01

We have developed flip-chip modules applicable to the pixel detector for the HL-LHC. New radiation-tolerant n+-in-p planar pixel sensors of a size of four FE-I4 application-specific integrated circuits (ASICs) are laid out in a 6-in wafer. Variation in readout connection for the pixels at the boundary of ASICs is implemented in the design of quadsensors. Bump bonding technology is developed for four ASICs onto one quadsensor. Both sensors and ASICs are thinned to 150 μm before bump bonding, and are held flat with vacuum chucks. Using lead-free SnAg solder bumps, we encounter deficiency with large areas of disconnected bumps after thermal stress treatment, including irradiation. Surface oxidation of the solder bumps is identified as a critical source of this deficiency after bump bonding trials, using SnAg bumps with solder flux, indium bumps, and SnAg bumps with a newly-introduced hydrogen-reflow process. With hydrogen-reflow, we establish flux-less bump bonding technology with SnAg bumps, appropriate for mass production of the flip-chip modules with thin sensors and thin ASICs.

Embeded photonic crystal at the interface of p-GaN and Ag reflector to improve light extraction of GaN-based flip-chip light-emitting diode

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhen, Aigong; Ma, Ping, E-mail: maping@semi.ac.cn; Zhang, Yonghui

2014-12-22

In this experiment, a flip-chip light-emitting diode with photonic crystal was fabricated at the interface of p-GaN and Ag reflector via nanospheres lithography technique. In this structure, photonic crystal could couple with the guide-light efficiently by reason of the little distance between photonic crystal and active region. The light output power of light emitting diode with embedded photonic crystal was 1.42 times larger than that of planar flip-chip light-emitting diode. Moreover, the embedded photonic crystal structure makes the far-field divergence angle decreased by 18° without spectra shift. The three-dimensional finite difference time domain simulation results show that photonic crystal couldmore » improve the light extraction, and enhance the light absorption caused by Ag reflector simultaneously, because of the roughed surface. The depth of photonic crystal is the key parameter affecting the light extraction and absorption. Light extraction efficiency increases with the depth photonic crystal structure rapidly, and reaches the maximum at the depth 80 nm, beyond which light extraction decrease drastically.« less

Electronic Switch Arrays for Managing Microbattery Arrays

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Alahmad, Mahmoud; Sukumar, Vinesh; Zghoul, Fadi; Buck, Kevin; Hess, Herbert; Li, Harry; Cox, David

2008-01-01

Integrated circuits have been invented for managing the charging and discharging of such advanced miniature energy-storage devices as planar arrays of microscopic energy-storage elements [typically, microscopic electrochemical cells (microbatteries) or microcapacitors]. The architecture of these circuits enables implementation of the following energy-management options: dynamic configuration of the elements of an array into a series or parallel combination of banks (subarrarys), each array comprising a series of parallel combination of elements; direct addressing of individual banks for charging/or discharging; and, disconnection of defective elements and corresponding reconfiguration of the rest of the array to utilize the remaining functional elements to obtain the desited voltage and current performance. An integrated circuit according to the invention consists partly of a planar array of field-effect transistors that function as switches for routing electric power among the energy-storage elements, the power source, and the load. To connect the energy-storage elements to the power source for charging, a specific subset of switches is closed; to connect the energy-storage elements to the load for discharging, a different specific set of switches is closed. Also included in the integrated circuit is circuitry for monitoring and controlling charging and discharging. The control and monitoring circuitry, the switching transistors, and interconnecting metal lines are laid out on the integrated-circuit chip in a pattern that registers with the array of energy-storage elements. There is a design option to either (1) fabricate the energy-storage elements in the corresponding locations on, and as an integral part of, this integrated circuit; or (2) following a flip-chip approach, fabricate the array of energy-storage elements on a separate integrated-circuit chip and then align and bond the two chips together.

Optical interconnection for a polymeric PLC device using simple positional alignment.

PubMed

Ryu, Jin Hwa; Kim, Po Jin; Cho, Cheon Soo; Lee, El-Hang; Kim, Chang-Seok; Jeong, Myung Yung

2011-04-25

This study proposes a simple cost-effective method of optical interconnection between a planar lightwave circuit (PLC) device chip and an optical fiber. It was conducted to minimize and overcome the coupling loss caused by lateral offset which is due to the process tolerance and the dimensional limitation existing between PLC device chips and fiber array blocks with groove structures. A PLC device chip and a fiber array block were simultaneously fabricated in a series of polymer replication processes using the original master. The dimensions (i.e., width and thickness) of the under-clad of the PLC device chip were identical to those of the fiber array block. The PLC device chip and optical fiber were aligned by simple positional control for the vertical direction of the PLC device chip under a particular condition. The insertion loss of the proposed 1 x 2 multimode optical splitter device interconnection was 4.0 dB at 850 nm and the coupling loss was below 0.1 dB compared with single-fiber based active alignment.

Scaling induced performance challenges/limitations of on-chip metal interconnects and comparisons with optical interconnects

NASA Astrophysics Data System (ADS)

Kapur, Pawan

The miniaturization paradigm for silicon integrated circuits has resulted in a tremendous cost and performance advantage. Aggressive shrinking of devices provides faster transistors and a greater functionality for circuit design. However, scaling induced smaller wire cross-sections coupled with longer lengths owing to larger chip areas, result in a steady deterioration of interconnects. This degradation in interconnect trends threatens to slow down the rapid growth along Moore's law. This work predicts that the situation is worse than anticipated. It shows that in the light of technology and reliability constraints, scaling induced increase in electron surface scattering, fractional cross section area occupied by the highly resistive barrier, and realistic interconnect operation temperature will lead to a significant rise in effective resistivity of modern copper based interconnects. We start by discussing various technology factors affecting copper resistivity. We, next, develop simulation tools to model these effects. Using these tools, we quantify the increase in realistic copper resistivity as a function of future technology nodes, under various technology assumptions. Subsequently, we evaluate the impact of these technology effects on delay and power dissipation of global signaling interconnects. Modern long on-chip wires use repeaters, which dramatically improves their delay and bandwidth. We quantify the repeated wire delays and power dissipation using realistic resistance trends at future nodes. With the motivation of reducing power, we formalize a methodology, which trades power with delay very efficiently for repeated wires. Using this method, we find that although the repeater power comes down, the total power dissipation due to wires is still found to be very large at future nodes. Finally, we explore optical interconnects as a possible substitute, for specific interconnect applications. We model an optical receiver and waveguides. Using this we assess future optical system performance. Finally, we compare the delay and power of future metal interconnects with that of optical interconnects for global signaling application. We also compare the power dissipation of the two approaches for an upper level clock distribution application. We find that for long on-chip communication links, optical interconnects have lower latencies than future metal interconnects at comparable levels of power dissipation.

Monolithically mode division multiplexing photonic integrated circuit for large-capacity optical interconnection.

PubMed

Chen, Guanyu; Yu, Yu; Zhang, Xinliang

2016-08-01

We propose and fabricate an on-chip mode division multiplexed (MDM) photonic interconnection system. Such a monolithically photonic integrated circuit (PIC) is composed of a grating coupler, two micro-ring modulators, mode multiplexer/demultiplexer, and two germanium photodetectors. The signals' generation, multiplexing, transmission, demultiplexing, and detection are successfully demonstrated on the same chip. Twenty Gb/s MDM signals are successfully processed with clear and open eye diagrams, validating the feasibility of the proposed circuit. The measured power penalties show a good performance of the MDM link. The proposed on-chip MDM system can be potentially used for large-capacity optical interconnection in future high-performance computers and big data centers.

Stochastic architecture for Hopfield neural nets

NASA Technical Reports Server (NTRS)

Pavel, Sandy

1992-01-01

An expandable stochastic digital architecture for recurrent (Hopfield like) neural networks is proposed. The main features and basic principles of stochastic processing are presented. The stochastic digital architecture is based on a chip with n full interconnected neurons with a pipeline, bit processing structure. For large applications, a flexible way to interconnect many such chips is provided.

Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments.

PubMed

Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

2015-08-18

In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a "one-sensor-one-packaging_technology" concept. The second one uses a standard flip-chip bonding technique. The first sensor is a "floating-concept", capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not "floating" but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

Reliability and Qualification of Hardware to Enhance the Mission Assurance of JPL/NASA Projects

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni

2010-01-01

Packaging Qualification and Verification (PQV) and life testing of advanced electronic packaging, mechanical assemblies (motors/actuators), and interconnect technologies (flip-chip), platinum temperature thermometer attachment processes, and various other types of hardware for Mars Exploration Rover (MER)/Mars Science Laboratory (MSL), and JUNO flight projects was performed to enhance the mission assurance. The qualification of hardware under extreme cold to hot temperatures was performed with reference to various project requirements. The flight like packages, assemblies, test coupons, and subassemblies were selected for the study to survive three times the total number of expected temperature cycles resulting from all environmental and operational exposures occurring over the life of the flight hardware including all relevant manufacturing, ground operations, and mission phases. Qualification/life testing was performed by subjecting flight-like qualification hardware to the environmental temperature extremes and assessing any structural failures, mechanical failures or degradation in electrical performance due to either overstress or thermal cycle fatigue. Experimental flight qualification test results will be described in this presentation.

Multigigabit optical transceivers for high-data rate military applications

NASA Astrophysics Data System (ADS)

Catanzaro, Brian E.; Kuznia, Charlie

2012-01-01

Avionics has experienced an ever increasing demand for processing power and communication bandwidth. Currently deployed avionics systems require gigabit communication using opto-electronic transceivers connected with parallel optical fiber. Ultra Communications has developed a series of transceiver solutions combining ASIC technology with flip-chip bonding and advanced opto-mechanical molded optics. Ultra Communications custom high speed ASIC chips are developed using an SoS (silicon on sapphire) process. These circuits are flip chip bonded with sources (VCSEL arrays) and detectors (PIN diodes) to create an Opto-Electronic Integrated Circuit (OEIC). These have been combined with micro-optics assemblies to create transceivers with interfaces to standard fiber array (MT) cabling technology. We present an overview of the demands for transceivers in military applications and how new generation transceivers leverage both previous generation military optical transceivers as well as commercial high performance computing optical transceivers.

Improved light extraction efficiency of GaN-based flip-chip light-emitting diodes with an antireflective interface layer

NASA Astrophysics Data System (ADS)

Wu, Dongxue; Ma, Ping; Liu, Boting; Zhang, Shuo; Wang, Junxi; Li, Jinmin

2016-05-01

GaN-based flip-chip light-emitting diodes (FC-LEDs) grown on nanopatterned sapphire substrates (NPSS) are fabricated using self-assembled SiO2 nanospheres as masks during inductively coupled plasma etching. By controlling the pattern spacing, epitaxial GaN can be grown from the top or bottom of patterns to obtain two different GaN/substrate interfaces. The optoelectronic characteristics of FC-LED chips with different GaN/sapphire interfaces are studied. The FC-LED with an antireflective interface layer consisting of a NPSS with GaN in the pattern spacings demonstrates better optical properties than the FC-LED with an interface embedded with air voids. Our study indicates that the two types of FC-LEDs grown on NPSS show higher crystal quality and improved electrical and optical characteristics compared with those of FC-LEDs grown on conventional planar sapphire substrates.

Optimization of Indium Bump Morphology for Improved Flip Chip Devices

NASA Technical Reports Server (NTRS)

Jones, Todd J.; Nikzad, Shouleh; Cunningham, Thomas J.; Blazejewski, Edward; Dickie, Matthew R.; Hoenk, Michael E.; Greer, Harold F.

2011-01-01

Flip-chip hybridization, also known as bump bonding, is a packaging technique for microelectronic devices that directly connects an active element or detector to a substrate readout face-to-face, eliminating the need for wire bonding. In order to make conductive links between the two parts, a solder material is used between the bond pads on each side. Solder bumps, composed of indium metal, are typically deposited by thermal evaporation onto the active regions of the device and substrate. While indium bump technology has been a part of the electronic interconnect process field for many years and has been extensively employed in the infrared imager industry, obtaining a reliable, high-yield process for high-density patterns of bumps can be quite difficult. Under the right conditions, a moderate hydrogen plasma exposure can raise the temperature of the indium bump to the point where it can flow. This flow can result in a desirable shape where indium will efficiently wet the metal contact pad to provide good electrical contact to the underlying readout or imager circuit. However, it is extremely important to carefully control this process as the intensity of the hydrogen plasma treatment dramatically affects the indium bump morphology. To ensure the fine-tuning of this reflow process, it is necessary to have realtime feedback on the status of the bumps. With an appropriately placed viewport in a plasma chamber, one can image a small field (a square of approximately 5 millimeters on each side) of the bumps (10-20 microns in size) during the hydrogen plasma reflow process. By monitoring the shape of the bumps in real time using a video camera mounted to a telescoping 12 magnifying zoom lens and associated optical elements, an engineer can precisely determine when the reflow of the bumps has occurred, and can shut off the plasma before evaporation or de-wetting takes place.

MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems

PubMed Central

Pannuto, Pat; Lee, Yoonmyung; Kuo, Ye-Sheng; Foo, ZhiYoong; Kempke, Benjamin; Kim, Gyouho; Dreslinski, Ronald G.; Blaauw, David; Dutta, Prabal

2015-01-01

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized—yet reusable—components with an interconnect that permits tiny, ultra-low power systems. In contrast to today’s interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two “shoot-through” rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient’s power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom chips from three different semiconductor processes. A three-chip, 2.2 mm3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/chip for communication. This is the lowest power for any system bus with MBus’s feature set. PMID:26855555

MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems.

PubMed

Pannuto, Pat; Lee, Yoonmyung; Kuo, Ye-Sheng; Foo, ZhiYoong; Kempke, Benjamin; Kim, Gyouho; Dreslinski, Ronald G; Blaauw, David; Dutta, Prabal

2015-06-01

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus , a new 4-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom chips from three different semiconductor processes. A three-chip, 2.2 mm 3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/chip for communication. This is the lowest power for any system bus with MBus's feature set.

Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s.

PubMed

Kim, Gyungock; Park, Jeong Woo; Kim, In Gyoo; Kim, Sanghoon; Kim, Sanggi; Lee, Jong Moo; Park, Gun Sik; Joo, Jiho; Jang, Ki-Seok; Oh, Jin Hyuk; Kim, Sun Ae; Kim, Jong Hoon; Lee, Jun Young; Park, Jong Moon; Kim, Do-Won; Jeong, Deog-Kyoon; Hwang, Moon-Sang; Kim, Jeong-Kyoum; Park, Kyu-Sang; Chi, Han-Kyu; Kim, Hyun-Chang; Kim, Dong-Wook; Cho, Mu Hee

2011-12-19

We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PIC(off-chip) for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the integrated 1 mm-phase-shifter modulator in the PIC(off-chip) demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of V(π)L(π) ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at -1V. The fabricated silicon PIC(intra-chip) for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. We also report the performance of the hybrid silicon electronic-photonic IC (EPIC), where a PIC(intra-chip) chip and 0.13μm CMOS interface IC chips were hybrid-integrated.

Chip-to-chip interconnects based on 3D stacking of optoelectrical dies on Si

NASA Astrophysics Data System (ADS)

Duan, P.; Raz, O.; Smalbrugge, B. E.; Duis, J.; Dorren, H. J. S.

2012-01-01

We demonstrate a new approach to increase the optical interconnection bandwidth density by stacking the opto-electrical dies directly on the CMOS driver. The suggested implementation is aiming to provide a wafer scale process which will make the use of wire bonding redundant and will allow for impedance matched metallic wiring between the electronic driving circuit and its opto-electronic counter part. We suggest the use of a thick photoresist ramp between CMOS driver and opto-electrical dies surface as the bridge for supporting co-plannar waveguides (CPW) electrically plated with lithographic accuracy. In this way all three dimensions of the interconnecting metal layer, width, length and thickness can be completely controlled. In this 1st demonstration all processing is done on commercially available devices and products, and is compatible with CMOS processing technology. To test the applicability of CPW instead of wire bonds for interconnecting the CMOS circuit and opto-electronic chips, we have made test samples and tested their performance at speeds up to 10 Gbps. In this demonstration, a silicon substrate was used on which we evaporated gold co-planar waveguides (CPW) to mimic a wire on the driver. An optical link consisting of a VCSEL chip and a photodiode chip has been assembled and fully characterized using optical coupling into and out of a multimode fiber (MMF). A 10 Gb/s 27-1 NRZ PRBS signal transmitted from one chip to another chip was detected error free. A 4 dB receiver sensitivity penalty is measured for the integrated device compared to a commercial link.

4-GHz counters bring synthesizers up to speed

NASA Astrophysics Data System (ADS)

Lee, F.; Miller, R.

1984-06-01

The availability of digital IC counters built on GaAs makes direct frequency division in microwave synthesizers possible. Four GHz is the highest clock rate achievable in production designs. These devices have the ability to drive TTL/CMOS logic, and the counter can be connected directly to single-chip frequency synthesizers controllers. A complete microwave sythesizer is formed by two chips and a voltage-controlled oscillator (VCO). The advantages of GaAs are discussed along with flip-flop basics, aspects of device fabrication, and the characteristics of GaAs MESAFETs. Attention is given to a GaAs prescaler usable for direct conversion, four kinds of flip-flops in a divide-by-two mode, and seven-stage binary ripple counters.

A short review on thermosonic flip chip bonding

NASA Astrophysics Data System (ADS)

Suppiah, Sarveshvaran; Ong, Nestor Rubio; Sauli, Zaliman; Sarukunaselan, Karunavani; Alcain, Jesselyn Barro; Shahimin, Mukhzeer Mohamad; Retnasamy, Vithyacharan

2017-09-01

This review is to study the evolution and key findings, critical technical challenges, solutions and bonding equipment of thermosonic flip chip bonding. Based on the review done, it was found that ultrasonic power, bonding time and force are the three main critical parameters need to be optimized in order to achieve sound and reliable bonding between the die and substrate. A close monitoring of the ultrasonic power helped to prevent over bonding phenomena on flexible substrate. Gold stud bumping is commonly used in thermosonic bonding compared to solder due to its better reliability obtained in the LED and optoelectronic packages. The review comprised short details on the available thermosonic bonding equipment in the semiconductor industry as well.

All-optical SR flip-flop based on SOA-MZI switches monolithically integrated on a generic InP platform

NASA Astrophysics Data System (ADS)

Pitris, St.; Vagionas, Ch.; Kanellos, G. T.; Kisacik, R.; Tekin, T.; Broeke, R.; Pleros, N.

2016-03-01

At the dawning of the exaflop era, High Performance Computers are foreseen to exploit integrated all-optical elements, to overcome the speed limitations imposed by electronic counterparts. Drawing from the well-known Memory Wall limitation, imposing a performance gap between processor and memory speeds, research has focused on developing ultra-fast latching devices and all-optical memory elements capable of delivering buffering and switching functionalities at unprecedented bit-rates. Following the master-slave configuration of electronic Flip-Flops, coupled SOA-MZI based switches have been theoretically investigated to exceed 40 Gb/s operation, provided a short coupling waveguide. However, this flip-flop architecture has been only hybridly integrated with silica-on-silicon integration technology exhibiting a total footprint of 45x12 mm2 and intra-Flip-Flop coupling waveguide of 2.5cm, limited at 5 Gb/s operation. Monolithic integration offers the possibility to fabricate multiple active and passive photonic components on a single chip at a close proximity towards, bearing promises for fast all-optical memories. Here, we present for the first time a monolithically integrated all-optical SR Flip-Flop with coupled master-slave SOA-MZI switches. The photonic chip is integrated on a 6x2 mm2 die as a part of a multi-project wafer run using library based components of a generic InP platform, fiber-pigtailed and fully packaged on a temperature controlled ceramic submount module with electrical contacts. The intra Flip-Flop coupling waveguide is 5 mm long, reducing the total footprint by two orders of magnitude. Successful flip flop functionality is evaluated at 10 Gb/s with clear open eye diagram, achieving error free operation with a power penalty of 4dB.

Sense and nonsense of logic-level optical interconnect: reflections on an experiment

NASA Astrophysics Data System (ADS)

Van Campenhout, Jan M.; Brunfaut, Marnik; Meeus, Wim; Dambre, Joni; De Wilde, Michiel

2001-12-01

Centimeter-range high-density optical interconnect between chips is coming into reach with current optical interconnect technology. Many theoretical studies have identified several good reasons why to use such types of interconnect as a replacement of various layers of the traditional electronic interconnect hierarchy. However, the true feasibility and usefulness of optical interconnects can only be established by actually building and evaluating them in a real system setting. This contribution reports on our experience in using short-range high-density optical inter-chip interconnects. It is based on the design and construction of a fully functional optoelectronic demonstrator system. We discuss the rationale for building the demonstrator in the first place, the implications of using many low-level optical interconnections in electronic systems, and the degree to which our expectations have been fulfilled by the demonstrator. The detailed description of the architecture, design and implementation of the demonstrator is not presented here, but can be found elsewhere in this issue.

Electro-optic techniques for VLSI interconnect

NASA Astrophysics Data System (ADS)

Neff, J. A.

1985-03-01

A major limitation to achieving significant speed increases in very large scale integration (VLSI) lies in the metallic interconnects. They are costly not only from the charge transport standpoint but also from capacitive loading effects. The Defense Advanced Research Projects Agency, in pursuit of the fifth generation supercomputer, is investigating alternatives to the VLSI metallic interconnects, especially the use of optical techniques to transport the information either inter or intrachip. As the on chip performance of VLSI continues to improve via the scale down of the logic elements, the problems associated with transferring data off and onto the chip become more severe. The use of optical carriers to transfer the information within the computer is very appealing from several viewpoints. Besides the potential for gigabit propagation rates, the conversion from electronics to optics conveniently provides a decoupling of the various circuits from one another. Significant gains will also be realized in reducing cross talk between the metallic routings, and the interconnects need no longer be constrained to the plane of a thin film on the VLSI chip. In addition, optics can offer an increased programming flexibility for restructuring the interconnect network.

Laser-induced forward transfer for flip-chip packaging of single dies.

PubMed

Kaur, Kamal S; Van Steenberge, Geert

2015-03-20

Flip-chip (FC) packaging is a key technology for realizing high performance, ultra-miniaturized and high-density circuits in the micro-electronics industry. In this technique the chip and/or the substrate is bumped and the two are bonded via these conductive bumps. Many bumping techniques have been developed and intensively investigated since the introduction of the FC technology in 1960(1) such as stencil printing, stud bumping, evaporation and electroless/electroplating2. Despite the progress that these methods have made they all suffer from one or more than one drawbacks that need to be addressed such as cost, complex processing steps, high processing temperatures, manufacturing time and most importantly the lack of flexibility. In this paper, we demonstrate a simple and cost-effective laser-based bump forming technique known as Laser-induced Forward Transfer (LIFT)3. Using the LIFT technique a wide range of bump materials can be printed in a single-step with great flexibility, high speed and accuracy at RT. In addition, LIFT enables the bumping and bonding down to chip-scale, which is critical for fabricating ultra-miniature circuitry.

Read disturb errors in a CMOS static RAM chip. [radiation hardened for spacedraft

NASA Technical Reports Server (NTRS)

Wood, Steven H.; Marr, James C., IV; Nguyen, Tien T.; Padgett, Dwayne J.; Tran, Joe C.; Griswold, Thomas W.; Lebowitz, Daniel C.

1989-01-01

Results are reported from an extensive investigation into pattern-sensitive soft errors (read disturb errors) in the TCC244 CMOS static RAM chip. The TCC244, also known as the SA2838, is a radiation-hard single-event-upset-resistant 4 x 256 memory chip. This device is being used by the Jet Propulsion Laboratory in the Galileo and Magellan spacecraft, which will have encounters with Jupiter and Venus, respectively. Two aspects of the part's design are shown to result in the occurrence of read disturb errors: the transparence of the signal path from the address pins to the array of cells, and the large resistance in the Vdd and Vss lines of the cells in the center of the array. Probe measurements taken during a read disturb failure illustrate how address skews and the data pattern in the chip combine to produce a bit flip. A capacitive charge pump formed by the individual cell capacitances and the resistance in the supply lines pumps down both the internal cell voltage and the local supply voltage until a bit flip occurs.

Heterogeneously integrated microsystem-on-a-chip

DOEpatents

Chanchani, Rajen [Albuquerque, NM

2008-02-26

A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.

Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments

PubMed Central

Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

2015-01-01

In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a “one-sensor-one-packaging_technology” concept. The second one uses a standard flip-chip bonding technique. The first sensor is a “floating-concept”, capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not “floating” but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA. PMID:26295235

Optomechanical Design and Characterization of a Printed-Circuit-Board-Based Free-Space Optical Interconnect Package

NASA Astrophysics Data System (ADS)

Zheng, Xuezhe; Marchand, Philippe J.; Huang, Dawei; Kibar, Osman; Ozkan, Nur S. E.; Esener, Sadik C.

1999-09-01

We present a proof of concept and a feasibility demonstration of a practical packaging approach in which free-space optical interconnects (FSOI s) can be integrated simply on electronic multichip modules (MCM s) for intra-MCM board interconnects. Our system-level packaging architecture is based on a modified folded 4 f imaging system that has been implemented with only off-the-shelf optics, conventional electronic packaging, and passive-assembly techniques to yield a potentially low-cost and manufacturable packaging solution. The prototypical system as built supports 48 independent FSOI channels with 8 separate laser and detector chips, for which each chip consists of a one-dimensional array of 12 devices. All the chips are assembled on a single substrate that consists of a printed circuit board or a ceramic MCM. Optical link channel efficiencies of greater than 90% and interchannel cross talk of less than 20 dB at low frequency have been measured. The system is compact at only 10 in. 3 (25.4 cm 3 ) and is scalable, as it can easily accommodate additional chips as well as two-dimensional optoelectronic device arrays for increased interconnection density.

High Coherence Qubit packaging

NASA Astrophysics Data System (ADS)

Pappas, David P.; Wu, Xian; Olivadese, Salvatore B.; Adiga, V. P.; Hertzberg, Jared B.; Bronn, Nicholas T.; Chow, Jerry M.; NIST Team; IBM Team

Development of sockets and associated interconnects for multi-qubit chips is presented. Considerations include thermalization, RF hygiene, non-magnetic environment, and self-alignment of the chips to allow for rapid testing, scalable integration, and high coherence operation. The sockets include wirebond free, vertical take-off launches with pogopins. This allows for high interconnectivity to non-trivial topology of qubits. Furthermore, vertical grounding is accomplished to reduce chip modes and suppress box modes. Low energy loss and high phase coherence is observed using this paradigm. We acknowledge support from IARPA, LPS, and the NIST Quantum Based Metrology Initiative.

Current crowding and self-heating effects in AlGaN-based flip-chip deep-ultraviolet light-emitting diodes

NASA Astrophysics Data System (ADS)

Hao, Guo-Dong; Taniguchi, Manabu; Tamari, Naoki; Inoue, Shin-ichiro

2018-01-01

We thoroughly explored the physical origin of the efficiency decrease with increasing injection current and current crowding effect in 280 nm AlGaN-based flip-chip deep-ultraviolet (DUV) light-emitting diodes (LEDs). The current spreading length was experimentally determined to be much smaller in DUV LEDs than that in conventional InGaN-based visible LEDs. The severe self-heating caused by the low power conversion efficiency of DUV LEDs should be mainly responsible for the considerable decrease of efficiency when current crowding is present. The wall-plug efficiency of the DUV LEDs was markedly enhanced by using a well-designed p-electrode pattern to improve the current distribution.

Effect of Al-trace dimension on Joule heating and current crowding in flip-chip solder joints under accelerated electromigration

NASA Astrophysics Data System (ADS)

Liang, S. W.; Chang, Y. W.; Chen, Chih

2006-04-01

Three-dimensional thermoelectrical simulation was conducted to investigate the influence of Al-trace dimension on Joule heating and current crowding in flip-chip solder joints. It is found that the dimension of the Al-trace effects significantly on the Joule heating, and thus directly determines the mean time to failure (MTTF). Simulated at a stressing current of 0.6A at 70°C, we estimate that the MTTF of the joints with Al traces in 100μm width was 6.1 times longer than that of joints with Al traces in 34μm width. Lower current crowding effect and reduced hot-spot temperature are responsible for the improved MTTF.

Chip-package nano-structured copper and nickel interconnections with metallic and polymeric bonding interfaces

NASA Astrophysics Data System (ADS)

Aggarwal, Ankur

With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 that support computing speed in terabits per second, with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Decreasing I/O pitch together with low cost, high electrical performance and high reliability are the key technological challenges identified by the 2005 International Technology Roadmap for Semiconductors (ITRS). Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. In addition, the materials must be environmentally-friendly, corrosion resistant, thermally stable over a long time, and resistant to electro-migration. A major challenge is also to develop economic processes that can be integrated into back end of the wafer foundry, i.e. with wafer level packaging. Device-to-system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches of the order of 30 microns and less. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. A novel chip-package interconnection technology is developed to address the IC packaging requirements beyond the ITRS projections and to introduce innovative design and fabrication concepts that will further advance the performance of the chip, the package, and the system board. The nano-structured interconnect technology simultaneously packages all the ICs intact in wafer form with quantum jump in the number of interconnections with the lowest electrical parasitics. The intrinsic properties of nano materials also enable several orders of magnitude higher interconnect densities with the best mechanical properties for the highest reliability and yet provide higher current and heat transfer densities. Nano-structured interconnects provides the ability to assemble the packaged parts on the system board without the use of underfill materials and to enable advanced analog/digital testing, reliability testing, and burn-in at wafer level. This thesis investigates the electrical and mechanical performance of nanostructured interconnections through modeling and test vehicle fabrication. The analytical models evaluate the performance improvements over solder and compliant interconnections. Test vehicles with nano-interconnections were fabricated using low cost electro-deposition techniques and assembled with various bonding interfaces. Interconnections were fabricated at 200 micron pitch to compare with the existing solder joints and at 50 micron pitch to demonstrate fabrication processes at fine pitches. Experimental and modeling results show that the proposed nano-interconnections could enhance the reliability and potentially meet all the system performance requirements for the emerging micro/nano-systems.

Pressure-Sensor Assembly Technique

NASA Technical Reports Server (NTRS)

Pruzan, Daniel A.

2003-01-01

Nielsen Engineering & Research (NEAR) recently developed an ultrathin data acquisition system for use in turbomachinery testing at NASA Glenn Research Center. This system integrates a microelectromechanical- systems- (MEMS-) based absolute pressure sensor [0 to 50 psia (0 to 345 kPa)], temperature sensor, signal-conditioning application-specific integrated circuit (ASIC), microprocessor, and digital memory into a package which is roughly 2.8 in. (7.1 cm) long by 0.75 in. (1.9 cm) wide. Each of these components is flip-chip attached to a thin, flexible circuit board and subsequently ground and polished to achieve a total system thickness of 0.006 in. (0.15 mm). Because this instrument is so thin, it can be quickly adhered to any surface of interest where data can be collected without disrupting the flow being investigated. One issue in the development of the ultrathin data acquisition system was how to attach the MEMS pressure sensor to the circuit board in a manner which allowed the sensor s diaphragm to communicate with the ambient fluid while providing enough support for the chip to survive the grinding and polishing operations. The technique, developed by NEAR and Jabil Technology Services Group (San Jose, CA), is described below. In the approach developed, the sensor is attached to the specially designed circuit board, see Figure 1, using a modified flip-chip technique. The circular diaphragm on the left side of the sensor is used to actively measure the ambient pressure, while the diaphragm on the right is used to compensate for changes in output due to temperature variations. The circuit board is fabricated with an access hole through it so that when the completed system is installed onto a wind tunnel model (chip side down), the active diaphragm is exposed to the environment. After the sensor is flip-chip attached to the circuit board, the die is underfilled to support the chip during the subsequent grinding and polishing operations. To prevent this underfill material from getting onto the sensor s diaphragms, the circuit board is fabricated with two 25- micrometer-tall polymer rings, sized so that the diaphragms fit inside the rings once the chip is attached.

Using Ant Colony Optimization for Routing in VLSI Chips

NASA Astrophysics Data System (ADS)

Arora, Tamanna; Moses, Melanie

2009-04-01

Rapid advances in VLSI technology have increased the number of transistors that fit on a single chip to about two billion. A frequent problem in the design of such high performance and high density VLSI layouts is that of routing wires that connect such large numbers of components. Most wire-routing problems are computationally hard. The quality of any routing algorithm is judged by the extent to which it satisfies routing constraints and design objectives. Some of the broader design objectives include minimizing total routed wire length, and minimizing total capacitance induced in the chip, both of which serve to minimize power consumed by the chip. Ant Colony Optimization algorithms (ACO) provide a multi-agent framework for combinatorial optimization by combining memory, stochastic decision and strategies of collective and distributed learning by ant-like agents. This paper applies ACO to the NP-hard problem of finding optimal routes for interconnect routing on VLSI chips. The constraints on interconnect routing are used by ants as heuristics which guide their search process. We found that ACO algorithms were able to successfully incorporate multiple constraints and route interconnects on suite of benchmark chips. On an average, the algorithm routed with total wire length 5.5% less than other established routing algorithms.

Flip-chip fabrication of integrated micromirror arrays using a novel latching off-chip hinge mechanism

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper presents the design, fabrication, modeling, and testing of various arrays of cantilever micromirror devices integrated atop CMOS control electronics. The upper layers of the arrays are prefabricated in the MUMPs process and then flip-chip transferred to CMOS receiving modules using a novel latching off-chip hinge mechanism. This mechanism allows the micromirror arrays to be released, rotated off the edge of the host module and then bonded to the receiving module using a standard probe station. The hinge mechanism supports the arrays by tethers that are severed to free the arrays once bonded. The resulting devices are inherently planarized since the bottom of the first releasable MUMPs layer becomes the surface of the integrated mirror. The working devices are formed by mirror surfaces bonded to address electrodes fabricated above static memory cells on the CMOS module. These arrays demonstrate highly desirable features such as compatible address potentials, less than 2 nm of RMS roughness, approximately 1 micrometers of lateral position accuracy and the unique ability to metallize reflective surfaces without masking. Ultimately, the off-chip hinge mechanism enables very low-cost, simple, reliable, repeatable and accurate assembly of advanced MEMS and integrated microsystems without specialized equipment or complex procedures.

Integrated Flexible Electronic Devices Based on Passive Alignment for Physiological Measurement

PubMed Central

Ryu, Jin Hwa; Byun, Sangwon; Baek, In-Bok; Lee, Bong Kuk; Jang, Won Ick; Jang, Eun-Hye; Kim, Ah-Yung; Yu, Han Yung

2017-01-01

This study proposes a simple method of fabricating flexible electronic devices using a metal template for passive alignment between chip components and an interconnect layer, which enabled efficient alignment with high accuracy. An electrocardiogram (ECG) sensor was fabricated using 20 µm thick polyimide (PI) film as a flexible substrate to demonstrate the feasibility of the proposed method. The interconnect layer was fabricated by a two-step photolithography process and evaporation. After applying solder paste, the metal template was placed on top of the interconnect layer. The metal template had rectangular holes at the same position as the chip components on the interconnect layer. Rectangular hole sizes were designed to account for alignment tolerance of the chips. Passive alignment was performed by simply inserting the components in the holes of the template, which resulted in accurate alignment with positional tolerance of less than 10 µm based on the structural design, suggesting that our method can efficiently perform chip mounting with precision. Furthermore, a fabricated flexible ECG sensor was easily attachable to the curved skin surface and able to measure ECG signals from a human subject. These results suggest that the proposed method can be used to fabricate epidermal sensors, which are mounted on the skin to measure various physiological signals. PMID:28420219

Flexible Chip Scale Package and Interconnect for Implantable MEMS Movable Microelectrodes for the Brain

PubMed Central

Jackson, Nathan; Muthuswamy, Jit

2009-01-01

We report here a novel approach called MEMS microflex interconnect (MMFI) technology for packaging a new generation of Bio-MEMS devices that involve movable microelectrodes implanted in brain tissue. MMFI addresses the need for (i) operating space for movable parts and (ii) flexible interconnects for mechanical isolation. We fabricated a thin polyimide substrate with embedded bond-pads, vias, and conducting traces for the interconnect with a backside dry etch, so that the flexible substrate can act as a thin-film cap for the MEMS package. A double gold stud bump rivet bonding mechanism was used to form electrical connections to the chip and also to provide a spacing of approximately 15–20 µm for the movable parts. The MMFI approach achieved a chip scale package (CSP) that is lightweight, biocompatible, having flexible interconnects, without an underfill. Reliability tests demonstrated minimal increases of 0.35 mΩ, 0.23 mΩ and 0.15 mΩ in mean contact resistances under high humidity, thermal cycling, and thermal shock conditions respectively. High temperature tests resulted in an increase in resistance of > 90 mΩ when aluminum bond pads were used, but an increase of ~ 4.2 mΩ with gold bond pads. The mean-time-to-failure (MTTF) was estimated to be at least one year under physiological conditions. We conclude that MMFI technology is a feasible and reliable approach for packaging and interconnecting Bio-MEMS devices. PMID:20160981

A review on solder reflow and flux application for flip chip

NASA Astrophysics Data System (ADS)

Suppiah, Sarveshvaran; Ong, Nestor Rubio; Sauli, Zaliman; Sarukunaselan, Karunavani; Alcain, Jesselyn Barro; Visvanathan, Susthitha Menon; Retnasamy, Vithyacharan

2017-09-01

This paper encompassed of the evolution and key findings, critical technical challenges, solutions and bonding equipment of solder reflow in flip chip bonding. Upon scrutinizing researches done by others, it can be deduced that peak temperature, time above liquidus, soak temperature, soak time, cooling rate and reflow environment played a vital role in achieving the desired bonding profile. In addition, flux is also needed with the purpose of removing oxides/contaminations on bump surface as well as to promote wetting of solder balls. Electromigration and warpage are the two main challenges faced by solder reflow process which can be overcome by the advancement in under bump metallization (UBM) and substrate technology. The review is ended with a brief description of the current equipment used in solder reflow process.

Designing an Electronics Data Package for Printed Circuit Boards (PCBs)

DTIC Science & Technology

2013-08-01

finished PCB flatness deviation should be less than 0.010 inches per inch. 4  The minimum copper wall thickness of plated-thru holes should be...Memory Card International Association)  IPC-6015 MCM-L (Multi-Chip Module – Laminated )  IPC-6016 HDI (High Density Interconnect)  IPC-6018...Interconnect ICT In Circuit Tester IPC Association Connecting Electronics Industries MCM-L Multi-Chip Module – Laminated MIL Military NEMA National

Applications of SPICE for modeling miniaturized biomedical sensor systems

NASA Technical Reports Server (NTRS)

Mundt, C. W.; Nagle, H. T.

2000-01-01

This paper proposes a model for a miniaturized signal conditioning system for biopotential and ion-selective electrode arrays. The system consists of three main components: sensors, interconnections, and signal conditioning chip. The model for this system is based on SPICE. Transmission-line based equivalent circuits are used to represent the sensors, lumped resistance-capacitance circuits describe the interconnections, and a model for the signal conditioning chip is extracted from its layout. A system for measurements of biopotentials and ionic activities can be miniaturized and optimized for cardiovascular applications based on the development of an integrated SPICE system model of its electrochemical, interconnection, and electronic components.

Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

PubMed

Shen, Wen-Wei; Lin, Yu-Min; Wu, Sheng-Tsai; Lee, Chia-Hsin; Huang, Shin-Yi; Chang, Hsiang-Hung; Chang, Tao-Chih; Chen, Kuan-Neng

2018-08-01

In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

Impact of Data Transmission over 10 Gbps on High-Density and Low-Cost Optoelectronic Module with Polynorbornene Waveguides

NASA Astrophysics Data System (ADS)

Ito, Yuka; Terada, Shinsuke; Arai, Shinya; Fujiwara, Makoto; Mori, Tetsuya; Choki, Koji; Fukushima, Takafumi; Koyanagi, Mitsumasa

2012-04-01

We proposed a rigid/flex optoelectronic (O/E) module with 48-channel polymeric waveguides for short-distance board-level optical interconnection. A flexible O/E test module was fabricated in the following two steps by using standard packaging processes. First, two vertical cavity surface emitting laser diodes (VCSELs) and one VCSEL driver (VD) were flip-chip bonded to a completed flexible printed circuit board (PCB), and two photodiodes (PDs) and one transimpedance amplifier/limiting amplifier (TIA/LA) to another flexible PCB. Second, the two flexible PCBs were attached with a polynorbornene (PNB) sheet in which high-density PNB waveguides were formed by UV exposure. Active areas of VCSELs and PDs on the flexible PCBs were aligned to micromirrors of the waveguides with -6 µm offset toward the signal propagation direction. We successfully demonstrated data transmission over 10 Gbps and low inter-channel crosstalk of less than -20 dB was achieved in the flexible O/E test module with 120-mm-long and 62.5-µm-pitch waveguides.

High performance low cost interconnections for flip chip attachment with electrically conductive adhesive. Final report

DOE Office of Scientific and Technical Information (OSTI.GOV)

NONE

1998-05-01

This final report is a compilation of final reports from each of the groups participating in the program. The main three groups involved in this effort are the Thomas J. Watson Research Center of IBM Corporation in Yorktown Heights, New York, Assembly Process Design of IBM Corporation in Endicott, New York, and SMT Laboratory of Universal Instruments Corporation in Binghamton, New York. The group at the research center focused on the conductive adhesive materials development and characterization. The group in process development focused on processing of the Polymer-Metal-Solvent Paste (PMSP) to form conductive adhesive bumps, formation of the Polymer-Metal Compositemore » (PMC) on semiconductor devices and study of the bonding process to circuitized organic carriers, and the long term durability and reliability of joints formed using the process. The group at Universal Instruments focused on development of an equipment set and bonding parameters for the equipment to produce bond assembly tooling. Reports of each of these individual groups are presented here reviewing their technical efforts and achievements.« less

Optical wireless link between a nanoscale antenna and a transducing rectenna.

PubMed

Dasgupta, Arindam; Mennemanteuil, Marie-Maxime; Buret, Mickaël; Cazier, Nicolas; Colas-des-Francs, Gérard; Bouhelier, Alexandre

2018-05-18

Initiated as a cable-replacement solution, short-range wireless power transfer has rapidly become ubiquitous in the development of modern high-data throughput networking in centimeter to meter accessibility range. Wireless technology is now penetrating a higher level of system integration for chip-to-chip and on-chip radiofrequency interconnects. However, standard CMOS integrated millimeter-wave antennas have typical size commensurable with the operating wavelength, and are thus an unrealistic solution for downsizing transmitters and receivers to the micrometer and nanometer scale. Herein, we demonstrate a light-in and electrical signal-out, on-chip wireless near-infrared link between a 220 nm optical antenna and a sub-nanometer rectifying antenna converting the transmitted optical energy into direct electrical current. The co-integration of subwavelength optical functional devices with electronic transduction offers a disruptive solution to interface photons and electrons at the nanoscale for on-chip wireless optical interconnects.

Construction of large scale switch matrix by interconnecting integrated optical switch chips with EDFAs

NASA Astrophysics Data System (ADS)

Liao, Mingle; Wu, Baojian; Hou, Jianhong; Qiu, Kun

2018-03-01

Large scale optical switches are essential components in optical communication network. We aim to build up a large scale optical switch matrix by the interconnection of silicon-based optical switch chips using 3-stage CLOS structure, where EDFAs are needed to compensate for the insertion loss of the chips. The optical signal-to-noise ratio (OSNR) performance of the resulting large scale optical switch matrix is investigated for TE-mode light and the experimental results are in agreement with the theoretical analysis. We build up a 64 ×64 switch matrix by use of 16 ×16 optical switch chips and the OSNR and receiver sensibility can respectively be improved by 0.6 dB and 0.2 dB by optimizing the gain configuration of the EDFAs.

Method of fabricating a microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2003-01-01

A method of fabricating a microelectronic device package with an integral window for providing optical access through an aperture in the package. The package is made of a multilayered insulating material, e.g., a low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC). The window is inserted in-between personalized layers of ceramic green tape during stackup and registration. Then, during baking and firing, the integral window is simultaneously bonded to the sintered ceramic layers of the densified package. Next, the microelectronic device is flip-chip bonded to cofired thick-film metallized traces on the package, where the light-sensitive side is optically accessible through the window. Finally, a cover lid is attached to the opposite side of the package. The result is a compact, low-profile package, flip-chip bonded, hermetically-sealed package having an integral window.

PICSiP: new system-in-package technology using a high bandwidth photonic interconnection layer for converged microsystems

NASA Astrophysics Data System (ADS)

Tekin, Tolga; Töpper, Michael; Reichl, Herbert

2009-05-01

Technological frontiers between semiconductor technology, packaging, and system design are disappearing. Scaling down geometries [1] alone does not provide improvement of performance, less power, smaller size, and lower cost. It will require "More than Moore" [2] through the tighter integration of system level components at the package level. System-in-Package (SiP) will deliver the efficient use of three dimensions (3D) through innovation in packaging and interconnect technology. A key bottleneck to the implementation of high-performance microelectronic systems, including SiP, is the lack of lowlatency, high-bandwidth, and high density off-chip interconnects. Some of the challenges in achieving high-bandwidth chip-to-chip communication using electrical interconnects include the high losses in the substrate dielectric, reflections and impedance discontinuities, and susceptibility to crosstalk [3]. Obviously, the incentive for the use of photonics to overcome the challenges and leverage low-latency and highbandwidth communication will enable the vision of optical computing within next generation architectures. Supercomputers of today offer sustained performance of more than petaflops, which can be increased by utilizing optical interconnects. Next generation computing architectures are needed with ultra low power consumption; ultra high performance with novel interconnection technologies. In this paper we will discuss a CMOS compatible underlying technology to enable next generation optical computing architectures. By introducing a new optical layer within the 3D SiP, the development of converged microsystems, deployment for next generation optical computing architecture will be leveraged.

Flexible Chip Scale Package and Interconnect for Implantable MEMS Movable Microelectrodes for the Brain.

PubMed

Jackson, Nathan; Muthuswamy, Jit

2009-04-01

We report here a novel approach called MEMS microflex interconnect (MMFI) technology for packaging a new generation of Bio-MEMS devices that involve movable microelectrodes implanted in brain tissue. MMFI addresses the need for (i) operating space for movable parts and (ii) flexible interconnects for mechanical isolation. We fabricated a thin polyimide substrate with embedded bond-pads, vias, and conducting traces for the interconnect with a backside dry etch, so that the flexible substrate can act as a thin-film cap for the MEMS package. A double gold stud bump rivet bonding mechanism was used to form electrical connections to the chip and also to provide a spacing of approximately 15-20 µm for the movable parts. The MMFI approach achieved a chip scale package (CSP) that is lightweight, biocompatible, having flexible interconnects, without an underfill. Reliability tests demonstrated minimal increases of 0.35 mΩ, 0.23 mΩ and 0.15 mΩ in mean contact resistances under high humidity, thermal cycling, and thermal shock conditions respectively. High temperature tests resulted in an increase in resistance of > 90 mΩ when aluminum bond pads were used, but an increase of ~ 4.2 mΩ with gold bond pads. The mean-time-to-failure (MTTF) was estimated to be at least one year under physiological conditions. We conclude that MMFI technology is a feasible and reliable approach for packaging and interconnecting Bio-MEMS devices.

Single-mode glass waveguide technology for optical interchip communication on board level

NASA Astrophysics Data System (ADS)

Brusberg, Lars; Neitz, Marcel; Schröder, Henning

2012-01-01

The large bandwidth demand in long-distance telecom networks lead to single-mode fiber interconnects as result of low dispersion, low loss and dense wavelength multiplexing possibilities. In contrast, multi-mode interconnects are suitable for much shorter lengths up to 300 meters and are promising for optical links between racks and on board level. Active optical cables based on multi-mode fiber links are at the market and research in multi-mode waveguide integration on board level is still going on. Compared to multi-mode, a single-mode waveguide has much more integration potential because of core diameters of around 20% of a multi-mode waveguide by a much larger bandwidth. But light coupling in single-mode waveguides is much more challenging because of lower coupling tolerances. Together with the silicon photonics technology, a single-mode waveguide technology on board-level will be the straight forward development goal for chip-to-chip optical interconnects integration. Such a hybrid packaging platform providing 3D optical single-mode links bridges the gap between novel photonic integrated circuits and the glass fiber based long-distance telecom networks. Following we introduce our 3D photonic packaging approach based on thin glass substrates with planar integrated optical single-mode waveguides for fiber-to-chip and chip-to-chip interconnects. This novel packaging approach merges micro-system packaging and glass integrated optics. It consists of a thin glass substrate with planar integrated singlemode waveguide circuits, optical mirrors and lenses providing an integration platform for photonic IC assembly and optical fiber interconnect. Thin glass is commercially available in panel and wafer formats and characterizes excellent optical and high-frequency properties. That makes it perfect for microsystem packaging. The paper presents recent results in single-mode waveguide technology on wafer level and waveguide characterization. Furthermore the integration in a hybrid packaging process and design issues are discussed.

A novel miniaturized PCR multi-reactor array fabricated using flip-chip bonding techniques

NASA Astrophysics Data System (ADS)

Zou, Zhi-Qing; Chen, Xiang; Jin, Qing-Hui; Yang, Meng-Su; Zhao, Jian-Long

2005-08-01

This paper describes a novel miniaturized multi-chamber array capable of high throughput polymerase chain reaction (PCR). The structure of the proposed device is verified by using finite element analysis (FEA) to optimize the thermal performance, and then implemented on a glass-silicon substrate using a standard MEMS process and post-processing. Thermal analysis simulation and verification of each reactor cell is equipped with integrated Pt temperature sensors and heaters at the bottom of the reaction chamber for real-time accurate temperature sensing and control. The micro-chambers are thermally separated from each other, and can be controlled independently. The multi-chip array was packaged on a printed circuit board (PCB) substrate using a conductive polymer flip-chip bonding technique, which enables effective heat dissipation and suppresses thermal crosstalk between the chambers. The designed system has successfully demonstrated a temperature fluctuation of ±0.5 °C during thermal multiplexing of up to 2 × 2 chambers, a full speed of 30 min for 30 cycle PCR, as well as the capability of controlling each chamber digitally and independently.

Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chiang, Patrick

2014-01-31

The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

Ultrafast all-optical flip-flop based on passive micro Sagnac waveguide ring with photonic crystal fiber.

PubMed

Xu, Ming; Yang, Wan; Hong, Tao; Kang, TangZhen; Ji, JianHua; Wang, Ke

2017-06-01

Ultrafast all-optical flip-flop based on a passive micro Sagnac waveguide ring is studied through theoretical analysis and numerical simulation in this paper. The types of D, R-S, J-K, and T flip-flop are designed by controlling the cross-phase modulation effect of lights in this special microring. The high nonlinearity of the hollow-core photonic crystal fiber is implanted on a chip to shorten the length of the ring and reduce input power. By sensible management, the pulse width ratio of the input and the control signal, problems of pulse narrowing, and residual pedestal at the out port are solved. The parameters affecting the performance of flip-flops are optimized. The results show that the all-optical flip-flops have stable performance, low power consumption, high transmission rate (up to 100  Gb/s), and response time in picosecond order. The small size microwaveguide structure is suitable for photonic integration.

Architecture for VLSI design of Reed-Solomon encoders

NASA Technical Reports Server (NTRS)

Liu, K. Y.

1982-01-01

A description is given of the logic structure of the universal VLSI symbol-slice Reed-Solomon (RS) encoder chip, from a group of which an RS encoder may be constructed through cascading and proper interconnection. As a design example, it is shown that an RS encoder presently requiring approximately 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical, interconnected VLSI RS encoder chips, offering in addition to greater compactness both a lower power requirement and greater reliability.

Architecture for VLSI design of Reed-Solomon encoders

NASA Astrophysics Data System (ADS)

Liu, K. Y.

1982-02-01

A description is given of the logic structure of the universal VLSI symbol-slice Reed-Solomon (RS) encoder chip, from a group of which an RS encoder may be constructed through cascading and proper interconnection. As a design example, it is shown that an RS encoder presently requiring approximately 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical, interconnected VLSI RS encoder chips, offering in addition to greater compactness both a lower power requirement and greater reliability.

Bi-level multilayered microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2002-01-01

A bi-level, multilayered package with an integral window for housing a microelectronic device. The device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The multilayered package can be formed of a low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the window being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. The microelectronic device can be flip-chip bonded and oriented so that the light-sensitive side is optically accessible through the window. A second chip can be bonded to the backside of the first chip, with the second chip being wirebonded to the second level of the bi-level package. The result is a compact, low-profile package, having an integral window that can be hermetically-sealed.

Chip design for thin-film deep ultraviolet LEDs fabricated by laser lift-off of the sapphire substrate

NASA Astrophysics Data System (ADS)

Cho, H. K.; Krüger, O.; Külberg, A.; Rass, J.; Zeimer, U.; Kolbe, T.; Knauer, A.; Einfeldt, S.; Weyers, M.; Kneissl, M.

2017-12-01

We report on a chip design which allows the laser lift-off (LLO) of the sapphire substrate sustaining the epitaxial film of flip-chip mounted deep ultraviolet light emitting diodes. A nanosecond pulsed excimer laser with a wavelength of 248 nm was used for the LLO. A mechanically stable chip design was found to be the key to prevent crack formation in the epitaxial layers and material chipping during the LLO process. Stabilization was achieved by introducing a Ti/Au leveling layer that mechanically supports the fragile epitaxial film. The electrical and optical characterization of devices before and after the LLO process shows that the device performance did not degrade by the LLO.

Sealed symmetric multilayered microelectronic device package with integral windows

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2002-01-01

A sealed symmetric multilayered package with integral windows for housing one or more microelectronic devices. The devices can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The multilayered package can be formed of a low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the windows being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. The microelectronic devices can be flip-chip bonded and oriented so that the light-sensitive sides are optically accessible through the windows. The result is a compact, low-profile, sealed symmetric package, having integral windows that can be hermetically-sealed.

Mechanical flip-chip for ultra-high electron mobility devices

DOE PAGES

Bennaceur, Keyan; Schmidt, Benjamin A.; Gaucher, Samuel; ...

2015-09-22

In this study, electrostatic gates are of paramount importance for the physics of devices based on high-mobility two-dimensional electron gas (2DEG) since they allow depletion of electrons in selected areas. This field-effect gating enables the fabrication of a wide range of devices such as, for example, quantum point contacts (QPC), electron interferometers and quantum dots. To fabricate these gates, processing is usually performed on the 2DEG material, which is in many cases detrimental to its electron mobility. Here we propose an alternative process which does not require any processing of the 2DEG material other than for the ohmic contacts. Thismore » approach relies on processing a separate wafer that is then mechanically mounted on the 2DEG material in a flip-chip fashion. This technique proved successful to fabricate quantum point contacts on both GaAs/AlGaAs materials with both moderate and ultra-high electron mobility.« less

Nanoparticle embedded p-type electrodes for GaN-based flip-chip light emitting diodes.

PubMed

Kwak, Joon Seop; Song, J O; Seong, T Y; Kim, B I; Cho, J; Sone, C; Park, Y

2006-11-01

We have investigated high-quality ohmic contacts for flip-chip light emitting diodes using Zn-Ni nanoparticles/Ag schemes. The Zn-Ni nanoparticles/Ag contacts produce specific contact resistances of 10(-5)-10(-6) omegacm2 when annealed at temperatures of 330-530 degrees C for 1 min in air ambient, which are much better than those obtained from the Ag contacts. It is shown that blue InGaN/GaN multi-quantum well light emitting diodes fabricated with the annealed Zn-Ni nanoparticles/Ag contacts give much lower forward-bias voltages at 20 mA compared with those of the multi-quantum well light emitting diodes made with the as-deposited Ag contacts. It is further presented that the multi-quantum well light emitting diodes made with the Zn-Ni nanoparticles/Ag contacts show similar output power compared to those fabricated with the Ag contact layers.

Flip-chip integrated silicon Mach-Zehnder modulator with a 28nm fully depleted silicon-on-insulator CMOS driver.

PubMed

Yong, Zheng; Shopov, Stefan; Mikkelsen, Jared C; Mallard, Robert; Mak, Jason C C; Voinigescu, Sorin P; Poon, Joyce K S

2017-03-20

We present a silicon electro-optic transmitter consisting of a 28nm ultra-thin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) CMOS driver flip-chip integrated onto a Mach-Zehnder modulator. The Mach-Zehnder silicon optical modulator was optimized to have a 3dB bandwidth of around 25 GHz at -1V bias and a 50 Ω impedance. The UTBB FD-SOI CMOS driver provided a large output voltage swing around 5 V_pp to enable a high dynamic extinction ratio and a low device insertion loss. At 44 Gbps, the transmitter achieved a high extinction ratio of 6.4 dB at the modulator quadrature operation point. This result shows open eye diagrams at the highest bit rates and with the largest extinction ratios for silicon electro-optic transmitter using a CMOS driver.

Effect of current crowding on whisker growth at the anode in flip chip solder joints

NASA Astrophysics Data System (ADS)

Ouyang, Fan-Yi; Chen, Kai; Tu, K. N.; Lai, Yi-Shao

2007-12-01

Owing to the line-to-bump configuration in flip chip solder joints, current crowding occurs when electrons enter into or exit from the solder bump. At the cathode contact, where electrons enter into the bump, current crowding induced pancake-type void formation has now been observed widely. At the anode contact, where electrons exit from the bump, we report here that whisker is formed. Results of both eutectic SnPb and SnAgCu solder joints are presented and compared. The cross-sectioned surface in SnPb showed dimple and bulge after electromigration, while that of SnAgCu remained flat. The difference is due to a larger back stress in the SnAgCu, consequently, electromigration in SnAgCu is slower than that in SnPb. Nanoindentation markers were used to measure the combined atomic fluxes of back stress and electromigration.

Microcircuit Device Reliability Digital Detailed Data

DTIC Science & Technology

1976-01-01

TYPE s No. FUNCTION A LASS PINS TEMP. TYPE CLASS LEVEL I eFAILED 8 NO. CHIP TEST APPL. TEST PAR1 t T AGATES PROTECT. DATE E:V. D TYPE HOURST :708 FLIP...LEVEL # EFAILED s a NO. t CHIP i TEST 3 APPL. a TEST I PAR! 3 a GATES s PROTECT. a DATE 3 ENV. t TYPE I 3 -OUHb s 354H0( 3 GATE C-I CDIP 14 150C :11.A

Towards energy-efficient photonic interconnects

NASA Astrophysics Data System (ADS)

Demir, Yigit; Hardavellas, Nikos

2015-03-01

Silicon photonics have emerged as a promising solution to meet the growing demand for high-bandwidth, low-latency, and energy-efficient on-chip and off-chip communication in many-core processors. However, current silicon-photonic interconnect designs for many-core processors waste a significant amount of power because (a) lasers are always on, even during periods of interconnect inactivity, and (b) microring resonators employ heaters which consume a significant amount of power just to overcome thermal variations and maintain communication on the photonic links, especially in a 3D-stacked design. The problem of high laser power consumption is particularly important as lasers typically have very low energy efficiency, and photonic interconnects often remain underutilized both in scientific computing (compute-intensive execution phases underutilize the interconnect), and in server computing (servers in Google-scale datacenters have a typical utilization of less than 30%). We address the high laser power consumption by proposing EcoLaser+, which is a laser control scheme that saves energy by predicting the interconnect activity and opportunistically turning the on-chip laser off when possible, and also by scaling the width of the communication link based on a runtime prediction of the expected message length. Our laser control scheme can save up to 62 - 92% of the laser energy, and improve the energy efficiency of a manycore processor with negligible performance penalty. We address the high trimming (heating) power consumption of the microrings by proposing insulation methods that reduce the impact of localized heating induced by highly-active components on the 3D-stacked logic die.

Development of phased twin flip-flop jets

NASA Technical Reports Server (NTRS)

Raman, Ganesh; Rice, Edward J.

1993-01-01

The flip-flop nozzle is a device that can produce an oscillating jet flow without any moving parts. There is now a renewed interest in such nozzles due to their potential for use as excitation devices in practical applications. An experiment aimed at developing twin flip-flop jets that operate at prescribed frequencies and phase differences was performed. The phasing was achieved using two different nozzle interconnection schemes. In one configuration the two jets flapped in-phase and in another they flapped out-of-phase with respect to each other. In either configuration the frequencies of oscillation of both jets were equal. When one of the jets was run at a constant high velocity and the velocity of the second jet was increased gradually, the higher velocity jet determined the frequency of oscillation of both jets. The two flip-flop jet configurations described could be used to excite a primary jet flow in either an anti-symmetric (sinuous) or a symmetric (varicose) mode.

Solid state lighting component

DOEpatents

Yuan, Thomas; Keller, Bernd; Ibbetson, James; Tarsa, Eric; Negley, Gerald

2010-10-26

An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in a series circuit. A lens is included over the LED chips. Other embodiments can comprise thermal spreading structures included integral to the submount and arranged to dissipate heat from the LED chips.

Solid state lighting component

DOEpatents

Yuan, Thomas; Keller, Bernd; Ibbetson, James; Tarsa, Eric; Negley, Gerald

2015-07-07

An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in a series circuit. A lens is included over the LED chips. Other embodiments can comprise thermal spreading structures included integral to the submount and arranged to dissipate heat from the LED chips.

Solid state lighting component

DOEpatents

Keller, Bernd; Ibbetson, James; Tarsa, Eric; Negley, Gerald; Yuan, Thomas

2012-07-10

An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in a series circuit. A lens is included over the LED chips. Other embodiments can comprise thermal spreading structures included integral to the submount and arranged to dissipate heat from the LED chips.

Trinary flip-flops using Savart plate and spatial light modulator for optical computation in multivalued logic

NASA Astrophysics Data System (ADS)

Ghosh, Amal K.; Basuray, Amitabha

2008-11-01

The memory devices in multi-valued logic are of most significance in modern research. This paper deals with the implementation of basic memory devices in multi-valued logic using Savart plate and spatial light modulator (SLM) based optoelectronic circuits. Photons are used here as the carrier to speed up the operations. Optical tree architecture (OTA) has been also utilized in the optical interconnection network. We have exploited the advantages of Savart plates, SLMs and OTA and proposed the SLM based high speed JK, D-type and T-type flip-flops in a trinary system.

An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging.

PubMed

Wygant, Ira O; Jamal, Nafis S; Lee, Hyunjoo J; Nikoozadeh, Amin; Oralkan, Omer; Karaman, Mustafa; Khuri-Yakub, Butrus T

2009-10-01

State-of-the-art 3-D medical ultrasound imaging requires transmitting and receiving ultrasound using a 2-D array of ultrasound transducers with hundreds or thousands of elements. A tight combination of the transducer array with integrated circuitry eliminates bulky cables connecting the elements of the transducer array to a separate system of electronics. Furthermore, preamplifiers located close to the array can lead to improved receive sensitivity. A combined IC and transducer array can lead to a portable, high-performance, and inexpensive 3-D ultrasound imaging system. This paper presents an IC flip-chip bonded to a 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array for 3-D ultrasound imaging. The IC includes a transmit beamformer that generates 25-V unipolar pulses with programmable focusing delays to 224 of the 256 transducer elements. One-shot circuits allow adjustment of the pulse widths for different ultrasound transducer center frequencies. For receiving reflected ultrasound signals, the IC uses the 32-elements along the array diagonals. The IC provides each receiving element with a low-noise 25-MHz-bandwidth transimpedance amplifier. Using a field-programmable gate array (FPGA) clocked at 100 MHz to operate the IC, the IC generated properly timed transmit pulses with 5-ns accuracy. With the IC flip-chip bonded to a CMUT array, we show that the IC can produce steered and focused ultrasound beams. We present 2-D and 3-D images of a wire phantom and 2-D orthogonal cross-sectional images (Bscans) of a latex heart phantom.

Multilayered Microelectronic Device Package With An Integral Window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2004-10-26

A microelectronic package with an integral window mounted in a recessed lip for housing a microelectronic device. The device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The package can be formed of a low temperature co-fired ceramic (LTCC) or high temperature cofired ceramic (HTCC) multilayered material, with the integral window being simultaneously joined (e.g. co-fired) to the package body during LTCC or HTCC processing. The microelectronic device can be flip-chip bonded and oriented so that a light-sensitive side is optically accessible through the window. The result is a compact, low profile package, having an integral window mounted in a recessed lip, that can be hermetically sealed.

C-MOS array design techniques

NASA Technical Reports Server (NTRS)

Feller, A.

1978-01-01

The entire complement of standard cells and components, except for the set-reset flip-flop, was completed. Two levels of checking were performed on each device. Logic cells and topological layout are described. All the related computer programs were coded and one level of debugging was completed. The logic for the test chip was modified and updated. This test chip served as the first test vehicle to exercise the standard cell complementary MOS(C-MOS) automatic artwork generation capability.

Quantifying Electromigration Processes in Sn-0.7Cu Solder with Lab-Scale X-Ray Computed Micro-Tomography

NASA Astrophysics Data System (ADS)

Mertens, James Charles Edwin

For decades, microelectronics manufacturing has been concerned with failures related to electromigration phenomena in conductors experiencing high current densities. The influence of interconnect microstructure on device failures related to electromigration in BGA and flip chip solder interconnects has become a significant interest with reduced individual solder interconnect volumes. A survey indicates that x-ray computed micro-tomography (muXCT) is an emerging, novel means for characterizing the microstructures' role in governing electromigration failures. This work details the design and construction of a lab-scale muXCT system to characterize electromigration in the Sn-0.7Cu lead-free solder system by leveraging in situ imaging. In order to enhance the attenuation contrast observed in multi-phase material systems, a modeling approach has been developed to predict settings for the controllable imaging parameters which yield relatively high detection rates over the range of x-ray energies for which maximum attenuation contrast is expected in the polychromatic x-ray imaging system. In order to develop this predictive tool, a model has been constructed for the Bremsstrahlung spectrum of an x-ray tube, and calculations for the detector's efficiency over the relevant range of x-ray energies have been made, and the product of emitted and detected spectra has been used to calculate the effective x-ray imaging spectrum. An approach has also been established for filtering 'zinger' noise in x-ray radiographs, which has proven problematic at high x-ray energies used for solder imaging. The performance of this filter has been compared with a known existing method and the results indicate a significant increase in the accuracy of zinger filtered radiographs. The obtained results indicate the conception of a powerful means for the study of failure causing processes in solder systems used as interconnects in microelectronic packaging devices. These results include the volumetric quantification of parameters which are indicative of both electromigration tolerance of solders and the dominant mechanisms for atomic migration in response to current stressing. This work is aimed to further the community's understanding of failure-causing electromigration processes in industrially relevant material systems for microelectronic interconnect applications and to advance the capability of available characterization techniques for their interrogation.

4 channel × 10 Gb/s bidirectional optical subassembly using silicon optical bench with precise passive optical alignment.

PubMed

Kang, Eun Kyu; Lee, Yong Woo; Ravindran, Sooraj; Lee, Jun Ki; Choi, Hee Ju; Ju, Gun Wu; Min, Jung Wook; Song, Young Min; Sohn, Ik-Bu; Lee, Yong Tak

2016-05-16

We demonstrate an advanced structure for optical interconnect consisting of 4 channel × 10 Gb/s bidirectional optical subassembly (BOSA) formed using silicon optical bench (SiOB) with tapered fiber guiding holes (TFGHs) for precise and passive optical alignment of vertical-cavity surface-emitting laser (VCSEL)-to-multi mode fiber (MMF) and MMF-to-photodiode (PD). The co-planar waveguide (CPW) transmission line (Tline) was formed on the backside of silicon substrate to reduce the insertion loss of electrical data signal. The 4 channel VCSEL and PD array are attached at the end of CPW Tline using a flip-chip bonder and solder pad. The 12-channel ribbon fiber is simply inserted into the TFGHs of SiOB and is passively aligned to the VCSEL and PD in which no additional coupling optics are required. The fabricated BOSA shows high coupling efficiency and good performance with the clearly open eye patterns and a very low bit error rate of less than 10^-12 order at a data rate of 10 Gb/s with a PRBS pattern of 2³¹-1.

Light coupling for on-chip optical interconnects

NASA Astrophysics Data System (ADS)

Gao, Xumin; Yuan, Jialei; Yang, Yongchao; Li, Yuanhang; Cai, Wei; Li, Xin; Wang, Yongjin

2017-12-01

An on-chip optical interconnect of a light emitter, waveguide and photodetector based on p-n junction InGaN/GaN multiple quantum wells (MQWs) is fabricated to investigate the light coupling efficiency of suspended waveguides connecting the light emitter and photodetector. Optical characterizations indicate that the photocurrent of the photodetector is mainly induced by the emitted light that is transmitted through the waveguides. Suspended waveguides with and without air gaps are reported in this paper. A 1 mA current injection into the light emitter induces a photocurrent of 17.3 nA and 205.5 nA for the photodetector connected to the waveguides that with 10 μm air gaps and without air gaps, respectively. Finite-difference time-domain simulations are performed to analyze the gap effect on the coupling efficiency of the light transmission. Both the gap distance and the index variation of the gap materials are analyzed to verify the potential optical sensing functions of the on-chip optical interconnect. A possible strategy for increasing the light coupling efficiency is proven by simulations.

L-connect routing of die surface pads to the die edge for stacking in a 3D array

DOEpatents

Petersen, Robert W.

2000-01-01

Integrated circuit chips and method of routing the interface pads from the face of the chip or die to one or more sidewall surfaces of the die. The interconnection is routed from the face of the die to one or more edges of the die, then routed over the edge of the die and onto the side surface. A new pad is then formed on the sidewall surface, which allows multiple die or chips to be stacked in a three-dimensional array, while enabling follow-on signal routing from the sidewall pads. The routing of the interconnects and formation of the sidewall pads can be carried out in an L-connect or L-shaped routing configuration, using a metalization process such as laser pantography.

Electromigration Critical Product to Measure Effect of Underfill Material in Suppressing Bi Segregation in Sn-58Bi Solder

NASA Astrophysics Data System (ADS)

Zhao, Xu; Takaya, Satoshi; Muraoka, Mikio

2017-08-01

Recently, we detected length-dependent electromigration (EM) behavior in Sn-58Bi (SB) solder and revealed the existence of Bi back-flow, which retards EM-induced Bi segregation and is dependent on solder length. The cause of the back-flow is attributed to an oxide layer formed on the SB solder. At present, underfill (UF) material is commonly used in flip-chip packaging as filler between chip and substrate to surround solder bumps. In this study, we quantitatively investigated the effect of UF material as a passivation layer on EM in SB solder strips. EM tests on SB solder strips with length of 50 μm, 100 μm, and 150 μm were conducted simultaneously. Some samples were coated with commercial thermosetting epoxy UF material, which acted as a passivation layer on the Cu-SB-Cu interconnections. The value of the critical product for SB solder was estimated to be 38 A/cm to 43 A/cm at 353 K to 373 K without UF coating and 59 A/cm at 373 K with UF coating. The UF material acting as a passivation layer suppressed EM-induced Bi segregation and increased the threshold current density by 37% to 55%. However, at very high current density, this effect became very slight. In addition, Bi atoms can diffuse to the anode side through the Sn phase, hence addition of microelements to the Sn phase to form obstacles, such as intermetallic compounds, may retard Bi segregation in SB solder.

Microfabricated Electrical Connector for Atomic Force Microscopy Probes with Integrated Sensor/Actuator

NASA Astrophysics Data System (ADS)

Akiyama, Terunobu; Staufer, Urs; Rooij, Nico F. de

2002-06-01

A microfabricated, electrical connector is proposed for facilitating the mounting of atomic force microscopy (AFM) probes, which have an integrated sensor and/or actuator. Only a base chip, which acts as a socket, is permanently fixed onto a printed circuit board and electronically connected by standard wire bonding. The AFM chip, the “plug”, is flipped onto the base chip and pressed from the backside by a spring. Electrical contact with the eventual stress sensors, capacitive or piezoelectric sensor/actuators, is provided by contact bumps. These bumps of about 8 μm height are placed onto the base chip. They touch the pads on the AFM chip that were originally foreseen to be for wire bonding and thus provide the electrical contact. This connector schema was successfully used to register AFM images with piezoresistive cantilevers.

Three Dimensional Integration and On-Wafer Packaging for Heterogeneous Wafer-Scale Circuit Architectures

DTIC Science & Technology

2006-11-01

Chip Level CMOS Chip High resistivity Si Metal Interconnect 25μm 24GHz fully integrated receiver CMOS transimpedance Amplifier (13GHz BW, 52dBΩ...power of a high-resistivity SiGe power amplifier chip with the wide operating frequency range and compactness of a CMOS mixed signal chip operating...With good RF channel selectivity, system specifications such as the linearity of the low noise amplifier (LNA), the phase noise of the voltage

The use of hybrid integrated circuit techniques in biotelemetry applications

NASA Technical Reports Server (NTRS)

Fryer, T. B.

1977-01-01

A review is presented of some features of hybrid integrated circuits that make their use advantageous in miniature biotelemetry applications. The various techniques for fabricating resistors, capacitors and interconnections by both thin film and thick film technology are discussed. The use of chip capacitors, resistors, and especially standard IC chips on substrates with fired-on interconnection patterns is emphasized. The review is designed primarily to acquaint biotelemetry users and designers with an overview of this fabrication technique so that they can better communicate their needs with an understanding of its limitations and advantages to facilities specializing in hybrid construction.

Surface and buried interfacial structures of epoxy resins used as underfills studied by sum frequency generation vibrational spectroscopy.

PubMed

Vázquez, Anne V; Holden, Brad; Kristalyn, Cornelius; Fuller, Mike; Wilkerson, Brett; Chen, Zhan

2011-05-01

Flip chip technology has greatly improved the performance of semiconductor devices, but relies heavily on the performance of epoxy underfill adhesives. Because epoxy underfills are cured in situ in flip chip semiconductor devices, understanding their surface and interfacial structures is critical for understanding their adhesion to various substrates. Here, sum frequency generation (SFG) vibrational spectroscopy was used to study surface and buried interfacial structures of two model epoxy resins used as underfills in flip chip devices, bisphenol A digylcidyl ether (BADGE) and 1,4-butanediol diglycidyl ether (BDDGE). The surface structures of these epoxies were compared before and after cure, and the orientations of their surface functional groups were deduced to understand how surface structural changes during cure may affect adhesion properties. Further, the effect of moisture exposure, a known cause of adhesion failure, on surface structures was studied. It was found that the BADGE surface significantly restructured upon moisture exposure while the BDDGE surface did not, showing that BADGE adhesives may be more prone to moisture-induced delamination. Lastly, although surface structure can give some insight into adhesion, buried interfacial structures more directly correspond to adhesion properties of polymers. SFG was used to study buried interfaces between deuterated polystyrene (d-PS) and the epoxies before and after moisture exposure. It was shown that moisture exposure acted to disorder the buried interfaces, most likely due to swelling. These results correlated with lap shear adhesion testing showing a decrease in adhesion strength after moisture exposure. The presented work showed that surface and interfacial structures can be correlated to adhesive strength and may be helpful in understanding and designing optimized epoxy underfill adhesives.

Hardware Trust Implications of 3-D Integration

DTIC Science & Technology

2010-12-01

between two points of the combined circuit, allowing more transistors to be placed closer to each other. The reduced global interconnect length, and the...Scandiuzzo, S. Cani, L. Perugini, E. Franchi , R. Canegallo, and R. Guerrieri. Chip-to-chip communication based on capacitive coupling. In Proceedings

A Robust Strategy for Total Ionizing Dose Testing of Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Wilcox, Edward; Berg, Melanie; Friendlich, Mark; Lakeman, Joseph; KIm, Hak; Pellish, Jonathan; LaBel, Kenneth

2012-01-01

We present a novel method of FPGA TID testing that measures propagation delay between flip-flops operating at maximum speed. Measurement is performed on-chip at-speed and provides a key design metric when building system-critical synchronous designs.

Mechanism of Void Prediction in Flip Chip Packages with Molded Underfill

NASA Astrophysics Data System (ADS)

Wu, Kuo-Tsai; Hwang, Sheng-Jye; Lee, Huei-Huang

2017-08-01

Voids have always been present using the molded underfill (MUF) package process, which is a problem that needs further investigation. In this study, the process was studied using the Moldex3D numerical analysis software. The effects of gas (air vent effect) on the overall melt front were also considered. In this isothermal process containing two fluids, the gas and melt colloid interact in the mold cavity. Simulation enabled an appropriate understanding of the actual situation to be gained, and, through analysis, the void region and exact location of voids were predicted. First, the global flow end area was observed to predict the void movement trend, and then the local flow ends were observed to predict the location and size of voids. In the MUF 518 case study, simulations predicted the void region as well as the location and size of the voids. The void phenomenon in a flip chip ball grid array underfill is discussed as part of the study.

Numerical analysis of light extraction enhancement of GaN-based thin-film flip-chip light-emitting diodes with high-refractive-index buckling nanostructures

NASA Astrophysics Data System (ADS)

Yue, Qing-Yang; Yang, Yang; Cheng, Zhen-Jia; Guo, Cheng-Shan

2018-06-01

In this work, the light extraction efficiency enhancement of GaN-based thin-film flip-chip (TFFC) light-emitting diodes (LEDs) with high-refractive-index (TiO2) buckling nanostructures was studied using the three-dimensional finite difference time domain method. Compared with 2-D photonic crystals, the buckling structures have the advantages of a random directionality and a broad distribution in periodicity, which can effectively extract the guided light propagating in all azimuthal directions over a wide spectrum. Numerical studies revealed that the light extraction efficiency of buckling-structured LEDs reaches 1.1 times that of triangular lattice photonic crystals. The effects of the buckling structure feature sizes and the thickness of the N-GaN layer on the light extraction efficiency for TFFC LEDs were also investigated systematically. With optimized structural parameters, a significant light extraction enhancement of about 2.6 times was achieved for TiO2 buckling-structured TFFC LEDs compared with planar LEDs.

Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip

NASA Technical Reports Server (NTRS)

Carson, John C. (Inventor); Indin, Ronald J. (Inventor); Shanken, Stuart N. (Inventor)

1994-01-01

A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.

MO detector (MOD): a dual-function optical modulator-detector for on-chip communication

NASA Astrophysics Data System (ADS)

Sun, Shuai; Zhang, Ruoyu; Peng, Jiaxin; Narayana, Vikram K.; Dalir, Hamed; El-Ghazawi, Tarek; Sorger, Volker J.

2018-04-01

Physical challenges at the device and interconnect level limit both network and computing energy efficiency. While photonics is being considered to address interconnect bottlenecks, optical routing is still limited by electronic circuitry, requiring substantial overhead for optical-electrical-optical conversion. Here we show a novel design of an integrated broadband photonic-plasmonic hybrid device termed MODetector featuring dual light modulation and detection function to act as an optical transceiver in the photonic network-on-chip. With over 10 dB extinction ratio and 0.8 dB insertion loss at the modulation state, this MODetector provides 0.7 W/A responsivity in the detection state with 36 ps response time. This multi-functional device: (i) eliminates OEO conversion, (ii) reduces optical losses from photodetectors when not needed, and (iii) enables cognitive routing strategies for network-on-chips.

High-speed highly temperature stable 980 nm VCSELs operating at 25 Gb/s at up to 85 °C for short reach optical interconnects

NASA Astrophysics Data System (ADS)

Mutig, Alex; Lott, James A.; Blokhin, Sergey A.; Moser, Philip; Wolf, Philip; Hofmann, Werner; Nadtochiy, Alexey M.; Bimberg, Dieter

2011-03-01

The progressive penetration of optical communication links into traditional copper interconnect markets greatly expands the applications of vertical cavity surface emitting lasers (VCSELs) for the next-generation of board-to-board, moduleto- module, chip-to-chip, and on-chip optical interconnects. Stability of the VCSEL parameters at high temperatures is indispensable for such applications, since these lasers typically reside directly on or near integrated circuit chips. Here we present 980 nm oxide-confined VCSELs operating error-free at bit rates up to 25 Gbit/s at temperatures as high as 85 °C without adjustment of the drive current and peak-to-peak modulation voltage. The driver design is therefore simplified and the power consumption of the driver electronics is lowered, reducing the production and operational costs. Small and large signal modulation experiments at various temperatures from 20 up to 85 °C for lasers with different oxide aperture diameters are presented in order to analyze the physical processes controlling the performance of the VCSELs. Temperature insensitive maximum -3 dB bandwidths of around 13-15 GHz for VCSELs with aperture diameters of 10 μm and corresponding parasitic cut-off frequencies exceeding 22 GHz are observed. Presented results demonstrate the suitability of our VCSELs for practical high speed and high temperature stable short-reach optical links.

Design and fabrication of a multilayered polymer microfluidic chip with nanofluidic interconnects via adhesive contact printing.

PubMed

Flachsbart, Bruce R; Wong, Kachuen; Iannacone, Jamie M; Abante, Edward N; Vlach, Robert L; Rauchfuss, Peter A; Bohn, Paul W; Sweedler, Jonathan V; Shannon, Mark A

2006-05-01

The design and fabrication of a multilayered polymer micro-nanofluidic chip is described that consists of poly(methylmethacrylate) (PMMA) layers that contain microfluidic channels separated in the vertical direction by polycarbonate (PC) membranes that incorporate an array of nanometre diameter cylindrical pores. The materials are optically transparent to allow inspection of the fluids within the channels in the near UV and visible spectrum. The design architecture enables nanofluidic interconnections to be placed in the vertical direction between microfluidic channels. Such an architecture allows microchannel separations within the chip, as well as allowing unique operations that utilize nanocapillary interconnects: the separation of analytes based on molecular size, channel isolation, enhanced mixing, and sample concentration. Device fabrication is made possible by a transfer process of labile membranes and the development of a contact printing method for a thermally curable epoxy based adhesive. This adhesive is shown to have bond strengths that prevent leakage and delamination and channel rupture tests exceed 6 atm (0.6 MPa) under applied pressure. Channels 100 microm in width and 20 microm in depth are contact printed without the adhesive entering the microchannel. The chip is characterized in terms of resistivity measurements along the microfluidic channels, electroosmotic flow (EOF) measurements at different pH values and laser-induced-fluorescence (LIF) detection of green-fluorescent protein (GFP) plugs injected across the nanocapillary membrane and into a microfluidic channel. The results indicate that the mixed polymer micro-nanofluidic multilayer chip has electrical characteristics needed for use in microanalytical systems.

High reliable and chromaticity-tunable flip-chip w-LEDs with Ce:YAG glass-ceramics phosphor for long-lifetime automotive headlights applications

NASA Astrophysics Data System (ADS)

Ma, Chaoyang; Cao, Yongge; Shen, Xiaofei; Wen, Zicheng; Ma, Ran; Long, Jiaqi; Yuan, Xuanyi

2017-07-01

Nowadays, major commercial w-LEDs fabricated by the traditionally gold-wire-welding packaging technology have undergone considerable development as indoor/outdoor lighting sources due to its high-energy utilization efficiency, long service life, environmental friendliness, and excellent chromatic stability. While, new generation applications in projections, automotive lighting, street lighting, plaza lighting, and high-end general lighting need further improvements in power handling and light extraction. Herein, transparent Ce:YAG glass-ceramics (GCs) phosphor was prepared by low-temperature co-sintering polycrystalline Ce:YAG phosphor powder and home-made PbO-B2O3-ZnO-SiO2 glass powder. Thereafter, the flip-chip (FC) w-LEDs were fabricated with the GCs phosphor plates and FC blue chips. The GCs-based FC w-LEDs show not only excellent heat- and humidity-resistance characteristics, but also superior optical performances with an LE of 112.8 lm/W, a CRI of 71.2, a CCT of 6103 K as well as a chromaticity coordinate of (0.3202, 0.3298), under a high operation current of 400 mA. The technology route will open a practically commercial feasible approach to achieve excellent performances for advanced high-power FC w-LEDs.

Optical-fiber-to-waveguide coupling using carbon-dioxide-laser-induced long-period fiber gratings.

PubMed

Bachim, Brent L; Ogunsola, Oluwafemi O; Gaylord, Thomas K

2005-08-15

Optical fibers are expected to play a role in chip-level and board-level optical interconnects because of limitations on the bandwidth and level of integration of electrical interconnects. Therefore, methods are needed to couple optical fibers directly to waveguides on chips and on boards. We demonstrate optical-fiber-to-waveguide coupling using carbon-dioxide laser-induced long-period fiber gratings (LPFGs). Such gratings can be written in standard fiber and offer wavelength multiplexing-demultiplexing performance. The coupler fabrication process and the characterization apparatus are presented. The operation and the wavelength response of a LPFG-based optical-fiber-to-waveguide directional coupler are demonstrated.

WDM package enabling high-bandwidth optical intrasystem interconnects for high-performance computer systems

NASA Astrophysics Data System (ADS)

Schrage, J.; Soenmez, Y.; Happel, T.; Gubler, U.; Lukowicz, P.; Mrozynski, G.

2006-02-01

From long haul, metro access and intersystem links the trend goes to applying optical interconnection technology at increasingly shorter distances. Intrasystem interconnects such as data busses between microprocessors and memory blocks are still based on copper interconnects today. This causes a bottleneck in computer systems since the achievable bandwidth of electrical interconnects is limited through the underlying physical properties. Approaches to solve this problem by embedding optical multimode polymer waveguides into the board (electro-optical circuit board technology, EOCB) have been reported earlier. The principle feasibility of optical interconnection technology in chip-to-chip applications has been validated in a number of projects. For reasons of cost considerations waveguides with large cross sections are used in order to relax alignment requirements and to allow automatic placement and assembly without any active alignment of components necessary. On the other hand the bandwidth of these highly multimodal waveguides is restricted due to mode dispersion. The advance of WDM technology towards intrasystem applications will provide sufficiently high bandwidth which is required for future high-performance computer systems: Assuming that, for example, 8 wavelength-channels with 12Gbps (SDR1) each are given, then optical on-board interconnects with data rates a magnitude higher than the data rates of electrical interconnects for distances typically found at today's computer boards and backplanes can be realized. The data rate will be twice as much, if DDR2 technology is considered towards the optical signals as well. In this paper we discuss an approach for a hybrid integrated optoelectronic WDM package which might enable the application of WDM technology to EOCB.

Optoelectronic interconnects for 3D wafer stacks

NASA Astrophysics Data System (ADS)

Ludwig, David E.; Carson, John C.; Lome, Louis S.

1996-01-01

Wafer and chip stacking are envisioned as a means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper provides definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies are discussed.

Optoelectronic interconnects for 3D wafer stacks

NASA Astrophysics Data System (ADS)

Ludwig, David; Carson, John C.; Lome, Louis S.

1996-01-01

Wafer and chip stacking are envisioned as means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper will provide definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies will be discussed.

Manufacturability of the X Architecture at the 90-nm technology node

NASA Astrophysics Data System (ADS)

Smayling, Michael C.; Sarma, Robin C.; Nagata, Toshiyuki; Arora, Narain; Duane, Michael P.; Oemardani, Shiany; Shah, Santosh

2004-05-01

In this paper, we discuss the results from a test chip that demonstrate the manufacturability and integration-worthiness of the X Architecture at the 90-nm technology node. We discuss how a collaborative effort between the design and chip making communities used the current generation of mask, lithography, wafer processing, inspection and metrology equipment to create 45 degree wires in typical metal pitches for the upper layers on a 90-nm device in a production environment. Cadence Design Systems created the test structure design and chip validation tools for the project. Canon"s KrF ES3 and ArF AS2 scanners were used for the lithography. Applied Materials used its interconnect fabrication technologies to produce the multilayer copper, low-k interconnect on 300-mm wafers. The results were confirmed for critical dimension and defect levels using Applied Materials" wafer inspection and metrology systems.

A 30 GHz monolithic receive module technology assessment

NASA Technical Reports Server (NTRS)

Geddes, J.; Sokolov, V.; Bauhahn, P.; Contolatis, T.

1988-01-01

This report is a technology assessment relevant to the 30 GHz Monolithic Receive Module development. It is based on results obtained on the present NASA Contract (NAS3-23356) as well as on information gathered from literature and other industry sources. To date the on-going Honeywell program has concentrated on demonstrating the so-called interconnected receive module which consists of four monolithic chips - the low noise front-end amplifier (LNA), the five bit phase shifter (PS), the gain control amplifier (GC), and the RF to IF downconverter (RF/IF). Results on all four individual chips have been obtained and interconnection of the first three functions has been accomplished. Future work on this contract is aimed at a higher level of integration, i.e., integration of the first three functions (LNA + PS + GC) on a single GaAs chip. The report presents the status of this technology and projections of its future directions.

Leadless Chip Carrier Packaging and CAD/CAM-Supported Wire Wrap Interconnect Technology for Subnanosecond ECL.

DTIC Science & Technology

1981-11-01

Showing Wire . 99 Impregnanted Silicone Rubber Contacts, Chip Carrier, ard Lid 35. Technit Connector For 68-Pad JEDEC Type A Leadless . . 100 Chip Carrier...Points of Various . . . . 124 Solders 4. Composition of Alloys Employed in Dual-In-Line . . . . 128 Package Pins and Plating by Mass Spectrographic...swings, and subnanosecond gate delays and risetimes. Presently, emitter coupled logic (ECL) and current mode logic (CML), both fabricated with silicon tech

Design, processing and testing of LSI arrays, hybrid microelectronics task

NASA Technical Reports Server (NTRS)

Himmel, R. P.; Stuhlbarg, S. M.; Ravetti, R. G.; Zulueta, P. J.; Rothrock, C. W.

1979-01-01

Mathematical cost models previously developed for hybrid microelectronic subsystems were refined and expanded. Rework terms related to substrate fabrication, nonrecurring developmental and manufacturing operations, and prototype production are included. Sample computer programs were written to demonstrate hybrid microelectric applications of these cost models. Computer programs were generated to calculate and analyze values for the total microelectronics costs. Large scale integrated (LST) chips utilizing tape chip carrier technology were studied. The feasibility of interconnecting arrays of LSU chips utilizing tape chip carrier and semiautomatic wire bonding technology was demonstrated.

Silicon Carbide Integrated Circuit Chip

NASA Image and Video Library

2015-02-17

A multilevel interconnect silicon carbide integrated circuit chip with co-fired ceramic package and circuit board recently developed at the NASA GRC Smart Sensors and Electronics Systems Branch for high temperature applications. High temperature silicon carbide electronics and compatible packaging technologies are elements of instrumentation for aerospace engine control and long term inner-solar planet explorations.

Neural dynamics in reconfigurable silicon.

PubMed

Basu, A; Ramakrishnan, S; Petre, C; Koziol, S; Brink, S; Hasler, P E

2010-10-01

A neuromorphic analog chip is presented that is capable of implementing massively parallel neural computations while retaining the programmability of digital systems. We show measurements from neurons with Hopf bifurcations and integrate and fire neurons, excitatory and inhibitory synapses, passive dendrite cables, coupled spiking neurons, and central pattern generators implemented on the chip. This chip provides a platform for not only simulating detailed neuron dynamics but also uses the same to interface with actual cells in applications such as a dynamic clamp. There are 28 computational analog blocks (CAB), each consisting of ion channels with tunable parameters, synapses, winner-take-all elements, current sources, transconductance amplifiers, and capacitors. There are four other CABs which have programmable bias generators. The programmability is achieved using floating gate transistors with on-chip programming control. The switch matrix for interconnecting the components in CABs also consists of floating-gate transistors. Emphasis is placed on replicating the detailed dynamics of computational neural models. Massive computational area efficiency is obtained by using the reconfigurable interconnect as synaptic weights, resulting in more than 50 000 possible 9-b accurate synapses in 9 mm(2).

Fabrication of Fresnel micro lens array in borosilicate glass by F2-laser ablation for glass interposer application

NASA Astrophysics Data System (ADS)

Brusberg, Lars; Neitz, Marcel; Schröder, Henning; Fricke-Begemann, Thomas; Ihlemann, Jürgen

2014-03-01

The future need for more bandwidth forces the development of optical transmission solutions for rack-to-rack, boardto- board and chip-to-chip interconnects. The goals are significant reduction of power consumption, highest density and potential for bandwidth scalability to overcome the limitations of the systems today with mostly copper based interconnects. For system integration the enabling of thin glass as a substrate material for electro-optical components with integrated micro-optics for efficient light coupling to integrated optical waveguides or fibers is becoming important. Our glass based packaging approach merges micro-system packaging and glass integrated optics. This kind of packaging consists of a thin glass substrate with integrated micro lenses providing a platform for photonic component assembly and optical fiber or waveguide interconnection. Thin glass is commercially available in panel and wafer size and characterizes excellent optical and high frequency properties. That makes it perfect for microsystem packaging. A suitable micro lens approach has to be comparable with different commercial glasses and withstand post-processing like soldering. A benefit of using laser ablated Fresnel lenses is the planar integration capability in the substrate for highest integration density. In the paper we introduce our glass based packaging concept and the Fresnel lens design for different scenarios like chip-to-fiber, chip-to-optical-printed-circuit-board coupling. Based on the design the Fresnel lenses were fabricated by using a 157 nm fluorine laser ablation system.

Synthesis and interface characterization of CNTs on graphene

NASA Astrophysics Data System (ADS)

Zhou, Changjian; Senegor, Richard; Baron, Zachary; Chen, Yihan; Raju, Salahuddin; Vyas, Anshul A.; Chan, Mansun; Chai, Yang; Yang, Cary Y.

2017-02-01

Carbon nanotubes (CNTs) and graphene are potential candidates for future interconnect materials. CNTs are promising on-chip via interconnect materials due to their readily formed vertical structures, their current-carrying capacity, which is much larger than existing on-chip interconnect materials such as copper and tungsten, and their demonstrated ability to grow in patterned vias with sub-50 nm widths; meanwhile, graphene is suitable for horizontal interconnects. However, they both present the challenge of having high-resistance contacts with other conductors. An all-carbon structure is proposed in this paper, which can be formed using the same chemical vapor deposition method for both CNTs and graphene. Vertically aligned CNTs are grown directly on graphene with an Fe or Ni catalyst. The structural characteristics of the graphene and the grown CNTs are analyzed using Raman spectroscopy and electron microscopy techniques. The CNT-graphene interface is studied in detail using transmission electron microscopic analysis of the CNT-graphene heterostructure, which suggests C-C bonding between the two materials. Electrical measurement results confirm the existence of both a lateral conduction path within graphene and a vertical conduction path in the CNT-graphene heterostructure, giving further support to the C-C bonding at the CNT-graphene interface and resulting in potential applications for all-carbon interconnects.

Synthesis and interface characterization of CNTs on graphene.

PubMed

Zhou, Changjian; Senegor, Richard; Baron, Zachary; Chen, Yihan; Raju, Salahuddin; Vyas, Anshul A; Chan, Mansun; Chai, Yang; Yang, Cary Y

2017-02-03

Carbon nanotubes (CNTs) and graphene are potential candidates for future interconnect materials. CNTs are promising on-chip via interconnect materials due to their readily formed vertical structures, their current-carrying capacity, which is much larger than existing on-chip interconnect materials such as copper and tungsten, and their demonstrated ability to grow in patterned vias with sub-50 nm widths; meanwhile, graphene is suitable for horizontal interconnects. However, they both present the challenge of having high-resistance contacts with other conductors. An all-carbon structure is proposed in this paper, which can be formed using the same chemical vapor deposition method for both CNTs and graphene. Vertically aligned CNTs are grown directly on graphene with an Fe or Ni catalyst. The structural characteristics of the graphene and the grown CNTs are analyzed using Raman spectroscopy and electron microscopy techniques. The CNT-graphene interface is studied in detail using transmission electron microscopic analysis of the CNT-graphene heterostructure, which suggests C-C bonding between the two materials. Electrical measurement results confirm the existence of both a lateral conduction path within graphene and a vertical conduction path in the CNT-graphene heterostructure, giving further support to the C-C bonding at the CNT-graphene interface and resulting in potential applications for all-carbon interconnects.

Thermal conductivity on stud bump interconnection of high power COB LED

NASA Astrophysics Data System (ADS)

Sarukunaselan, K.; Ong, N. R.; Sauli, Z.; Mahmed, N.; Kirtsaeng, S.; Sakuntasathien, S.; Suppiah, S.; Alcain, J. B.; Retnasamy, V.

2017-09-01

In this paper, the impacts of bump dimensions and material conductivity on the thermal performances of a high power chip on board (COB) LED package were investigated using open source software, Elmer. The stud bump acted as interconnection join which has an extra role in dissipating heat generated by the chip to the ambience. Simulation data showed that for a bump with a fixed contact length of 1mm, the most suitable height was 171 µm with material conductivity of 238W/mK or 319W/mK. Materials with thermal conductivity of lower than 20W/mK, had the poorest heat dissipation irrespective of the height.

Fluxless flip-chip bonding using a lead-free solder bumping technique

NASA Astrophysics Data System (ADS)

Hansen, K.; Kousar, S.; Pitzl, D.; Arab, S.

2017-09-01

With the LHC exceeding the nominal instantaneous luminosity, the current barrel pixel detector (BPIX) of the CMS experiment at CERN will reach its performance limits and undergo significant radiation damage. In order to improve detector performance in high luminosity conditions, the entire BPIX is replaced with an upgraded version containing an additional detection layer. Half of the modules comprising this additional layer are produced at DESY using fluxless and lead-free bumping and bonding techniques. Sequential solder-jetting technique is utilized to wet 40-μm SAC305 solder spheres on the silicon-sensor pads with electroless Ni, Pd and immersion Au (ENEPIG) under-bump metallization (UBM). The bumped sensors are flip-chip assembled with readout chips (ROCs) and then reflowed using a flux-less bonding facility. The challenges for jetting low solder volume have been analyzed and will be presented in this paper. An average speed of 3.4 balls per second is obtained to jet about 67 thousand solder balls on a single chip. On average, 7 modules have been produced per week. The bump-bond quality is evaluated in terms of electrical and mechanical properties. The peak-bump resistance is about 17.5 mΩ. The cross-section study revealed different types of intermetallic compounds (IMC) as a result of interfacial reactions between UBM and solder material. The effect of crystalline phases on the mechanical properties of the joint is discussed. The mean shear strength per bump after the final module reflow is about 16 cN. The results and sources of yield loss of module production are reported. The achieved yield is 95%.

Effect of surface finish on the failure mechanisms of flip-chip solder joints under electromigration

NASA Astrophysics Data System (ADS)

Lin, Y. L.; Lai, Y. S.; Tsai, C. M.; Kao, C. R.

2006-12-01

Two substrate surface finishes, Au/Ni and organic solderable preservative (OSP), were used to study the effect of the surface finish on the reliability of flip-chip solder joints under electromigration at 150°C ambient temperature. The solder used was eutectic PbSn, and the applied current density was 5×103 A/cm2 at the contact window of the chip. The under bump metallurgy (UBM) on the chip was sputtered Cu/Ni. It was found that the mean-time-to-failure (MTTF) of the OSP joints was six times better than that of the Au/Ni joints (3080 h vs. 500 h). Microstructure examinations uncovered that the combined effect of current crowding and the accompanying local Joule heating accelerated the local Ni UBM consumption near the point of electron entrance. Once Ni was depleted at a certain region, this region became nonconductive, and the flow of the electrons was diverted to the neighboring region. This neighboring region then became the place where electrons entered the joint, and the local Ni UBM consumption was accelerated. This process repeated itself, and the Ni-depleted region extended further on, creating an ever-larger nonconductive region. The solder joint eventually, failed when the nonconductive region became too large, making the effective current density very high. Accordingly, the key factor determining the MTTF was the Ni consumption rate. The joints with the OSP surface finish had a longer MTTF because Cu released from the substrate was able to reduce the Ni consumption rate.

Circuit-Switched Memory Access in Photonic Interconnection Networks for High-Performance Embedded Computing

DTIC Science & Technology

2010-07-22

dependent , providing a natural bandwidth match between compute cores and the memory subsystem. • High Bandwidth Dcnsity. Waveguides crossing the chip...simulate this memory access architecture on a 2S6-core chip with a concentrated 64-node network lIsing detailed traces of high-performance embedded...memory modulcs, wc placc memory access poi nts (MAPs) around the pcriphery of the chip connected to thc nctwork. These MAPs, shown in Figure 4, contain

Chip packaging technique

NASA Technical Reports Server (NTRS)

Jayaraj, Kumaraswamy (Inventor); Noll, Thomas E. (Inventor); Lockwood, Harry F. (Inventor)

2001-01-01

A hermetically sealed package for at least one semiconductor chip is provided which is formed of a substrate having electrical interconnects thereon to which the semiconductor chips are selectively bonded, and a lid which preferably functions as a heat sink, with a hermetic seal being formed around the chips between the substrate and the heat sink. The substrate is either formed of or includes a layer of a thermoplastic material having low moisture permeability which material is preferably a liquid crystal polymer (LCP) and is a multiaxially oriented LCP material for preferred embodiments. Where the lid is a heat sink, the heat sink is formed of a material having high thermal conductivity and preferably a coefficient of thermal expansion which substantially matches that of the chip. A hermetic bond is formed between the side of each chip opposite that connected to the substrate and the heat sink. The thermal bond between the substrate and the lid/heat sink may be a pinched seal or may be provided, for example by an LCP frame which is hermetically bonded or sealed on one side to the substrate and on the other side to the lid/heat sink. The chips may operate in the RF or microwave bands with suitable interconnects on the substrate and the chips may also include optical components with optical fibers being sealed into the substrate and aligned with corresponding optical components to transmit light in at least one direction. A plurality of packages may be physically and electrically connected together in a stack to form a 3D array.

A modular microfluidic architecture for integrated biochemical analysis.

PubMed

Shaikh, Kashan A; Ryu, Kee Suk; Goluch, Edgar D; Nam, Jwa-Min; Liu, Juewen; Thaxton, C Shad; Chiesl, Thomas N; Barron, Annelise E; Lu, Yi; Mirkin, Chad A; Liu, Chang

2005-07-12

Microfluidic laboratory-on-a-chip (LOC) systems based on a modular architecture are presented. The architecture is conceptualized on two levels: a single-chip level and a multiple-chip module (MCM) system level. At the individual chip level, a multilayer approach segregates components belonging to two fundamental categories: passive fluidic components (channels and reaction chambers) and active electromechanical control structures (sensors and actuators). This distinction is explicitly made to simplify the development process and minimize cost. Components belonging to these two categories are built separately on different physical layers and can communicate fluidically via cross-layer interconnects. The chip that hosts the electromechanical control structures is called the microfluidic breadboard (FBB). A single LOC module is constructed by attaching a chip comprised of a custom arrangement of fluid routing channels and reactors (passive chip) to the FBB. Many different LOC functions can be achieved by using different passive chips on an FBB with a standard resource configuration. Multiple modules can be interconnected to form a larger LOC system (MCM level). We demonstrated the utility of this architecture by developing systems for two separate biochemical applications: one for detection of protein markers of cancer and another for detection of metal ions. In the first case, free prostate-specific antigen was detected at 500 aM concentration by using a nanoparticle-based bio-bar-code protocol on a parallel MCM system. In the second case, we used a DNAzyme-based biosensor to identify the presence of Pb(2+) (lead) at a sensitivity of 500 nM in <1 nl of solution.

Two-Step Plasma Process for Cleaning Indium Bonding Bumps

NASA Technical Reports Server (NTRS)

Greer, Harold F.; Vasquez, Richard P.; Jones, Todd J.; Hoenk, Michael E.; Dickie, Matthew R.; Nikzad, Shouleh

2009-01-01

A two-step plasma process has been developed as a means of removing surface oxide layers from indium bumps used in flip-chip hybridization (bump bonding) of integrated circuits. The two-step plasma process makes it possible to remove surface indium oxide, without incurring the adverse effects of the acid etching process.

High-Modulation-Speed LEDs Based on III-Nitride

NASA Astrophysics Data System (ADS)

Chen, Hong

III-nitride InGaN light-emitting diodes (LEDs) enable wide range of applications in solid-state lighting, full-color displays, and high-speed visible-light communication. Conventional InGaN quantum well LEDs grown on polar c-plane substrate suffer from quantum confined Stark effect due to the large internal polarization-related fields, leading to a reduced radiative recombination rate and device efficiency, which limits the performance of InGaN LEDs in high-speed communication applications. To circumvent these negative effects, non-trivial-cavity designs such as flip-chip LEDs, metallic grating coated LEDs are proposed. This oral defense will show the works on the high-modulation-speed LEDs from basic ideas to applications. Fundamental principles such as rate equations for LEDs/laser diodes (LDs), plasmonic effects, Purcell effects will be briefly introduced. For applications, the modal properties of flip-chip LEDs are solved by implementing finite difference method in order to study the modulation response. The emission properties of highly polarized InGaN LEDs coated by metallic gratings are also investigated by finite difference time domain method.

Neighbour-die effect on the measurement of wafer-level flip-chip LED dies in production lines

NASA Astrophysics Data System (ADS)

Chen, Tengfei; Wan, Zirui; Li, Bin

2017-11-01

The light from the side surfaces of the test flip-chip light-emitting diode (FCLED) dies is reflected, refracted or absorbed by neighbour dies during the measurement of wafer-level FCLED dies in production lines. A notable measurement deviation is caused by the neighbour-die effect, which is not considered in current industry practice. In this paper, Monte Carlo ray-tracing simulations are used to study the measurement deviations caused by the neighbour-die effect and extension ratios of the film. The simulation results show that the maximal deviation of radiant flux impinging the photodiode can reach 5.5%, if the die is tested without any neighbour dies, or is surrounded by a set of neighbour dies at an extension ratio of 1.1. Moreover, the dependence between the measurement results and neighbour cases for different extension ratios is also investigated. Then, a modified calibration method is proposed and studied. The proposed technique can be used to improve the calibration and measurement accuracy of the test equipment used for measurement of wafer-level FCLED dies in production lines.

Aging Studies of Cu-Sn Intermetallics in Cu Micropillars Used in Flip Chip Attachment onto Cu Lead Frames

NASA Astrophysics Data System (ADS)

Roma, Maria Penafrancia C.; Kudtarkar, Santosh; Kierse, Oliver; Sengupta, Dipak; Cho, Junghyun

2018-02-01

Copper micropillars plated onto a silicon die and soldered with Sn-Ag solder to a copper lead frame in a flip chip on lead package have been subjected to high-temperature storage at 150°C and 175°C for 500 h, 1000 h, and 1500 h. Cu6Sn5 and Cu3Sn intermetallic compounds were found on both sides of the solder, but the growth rates were not the same as evidenced by different values of the growth exponent n. Cu and Sn diffusion controlled the Cu3Sn growth in the Cu pillar interface ( n ≈ 0.5), while interface reactions controlled the growth in the Cu lead frame interface ( n ≈ 0.8). Increasing the aging temperature increased the growth of Cu3Sn as well as the presence of microvoids in the Cu lead frame side. Adding Ni as a barrier layer on the Cu pillar prevented the growth of Cu3Sn in the Cu pillar interface and reduced its growth rate on the lead frame side, even at higher aging temperatures.

CSP Manufacturing Challenges and Assembly Reliability

NASA Technical Reports Server (NTRS)

Ghaffarian, Reza

2000-01-01

Although the expression of CSP is widely used by industry from suppliers to users, its implied definition had evolved as the technology has matured. There are "expert definition"- package that is up to 1.5 time die- or "interim definition". CSPs are miniature new packages that industry is starting to implement and there are many unresolved technical issues associated with their implementation. For example, in early 1997, packages with 1 mm pitch and lower were the dominant CSPs, whereas in early 1998 packages with 0.8 mm and lower became the norm for CSPs. Other changes included the use of flip chip die rather than wire bond in CSP. Nonetheless the emerging CSPs are competing with bare die assemblies and are becoming the package of choice for size reduction applications. These packages provide the benefits of small size and performance of the bare die or flip chip, with the advantage of standard die packages. The JPL-led MicrotypeBGA Consortium of enterprises representing government agencies and private companies have jointed together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. This talk will cover specifically the experience of our consortium on technology implementation challenges, including design and build of both standard and microvia boards, assembly of two types of test vehicles, and the most current environmental thermal cycling test results.

Low temperature co-fired ceramic packaging of CMOS capacitive sensor chip towards cell viability monitoring.

PubMed

Halonen, Niina; Kilpijärvi, Joni; Sobocinski, Maciej; Datta-Chaudhuri, Timir; Hassinen, Antti; Prakash, Someshekar B; Möller, Peter; Abshire, Pamela; Kellokumpu, Sakari; Lloyd Spetz, Anita

2016-01-01

Cell viability monitoring is an important part of biosafety evaluation for the detection of toxic effects on cells caused by nanomaterials, preferably by label-free, noninvasive, fast, and cost effective methods. These requirements can be met by monitoring cell viability with a capacitance-sensing integrated circuit (IC) microchip. The capacitance provides a measurement of the surface attachment of adherent cells as an indication of their health status. However, the moist, warm, and corrosive biological environment requires reliable packaging of the sensor chip. In this work, a second generation of low temperature co-fired ceramic (LTCC) technology was combined with flip-chip bonding to provide a durable package compatible with cell culture. The LTCC-packaged sensor chip was integrated with a printed circuit board, data acquisition device, and measurement-controlling software. The packaged sensor chip functioned well in the presence of cell medium and cells, with output voltages depending on the medium above the capacitors. Moreover, the manufacturing of microfluidic channels in the LTCC package was demonstrated.

On-chip detection of non-classical light by scalable integration of single-photon detectors

PubMed Central

Najafi, Faraz; Mower, Jacob; Harris, Nicholas C.; Bellei, Francesco; Dane, Andrew; Lee, Catherine; Hu, Xiaolong; Kharel, Prashanta; Marsili, Francesco; Assefa, Solomon; Berggren, Karl K.; Englund, Dirk

2015-01-01

Photonic-integrated circuits have emerged as a scalable platform for complex quantum systems. A central goal is to integrate single-photon detectors to reduce optical losses, latency and wiring complexity associated with off-chip detectors. Superconducting nanowire single-photon detectors (SNSPDs) are particularly attractive because of high detection efficiency, sub-50-ps jitter and nanosecond-scale reset time. However, while single detectors have been incorporated into individual waveguides, the system detection efficiency of multiple SNSPDs in one photonic circuit—required for scalable quantum photonic circuits—has been limited to <0.2%. Here we introduce a micrometer-scale flip-chip process that enables scalable integration of SNSPDs on a range of photonic circuits. Ten low-jitter detectors are integrated on one circuit with 100% device yield. With an average system detection efficiency beyond 10%, and estimated on-chip detection efficiency of 14–52% for four detectors operated simultaneously, we demonstrate, to the best of our knowledge, the first on-chip photon correlation measurements of non-classical light. PMID:25575346

Electromigration and solid state aging of flip chip solder joints and analysis of tin whisker on lead-frame

NASA Astrophysics Data System (ADS)

Lee, Taekyeong

Electromigration and solid state aging in flip chip joint, and whisker on lead frame of Pb-containing (eutectic SnPb) and Pb-free solders (SnAg 3.5, SnAg3.8Cu0.7, and SnCu0.7), have been studied systematically, using Scanning Electron Microscopy (SEM), Energy Dispersive X-ray Analysis (EDX), and synchrotron radiation. The high current density in flip chip joint drives the diffusion of atoms of eutectic SnPb and SnAgCu. A marker is used to measure the diffusion flux in a half cross-sectioned solder joint. SnAgCu shows higher resistance against electromigration than eutectic SnPb. In the half cross-sectioned solder joint, void growth is the dominant failure mechanism. However, the whole solder balls in the underfill show that the failure mechanism is a result from the dissolution of electroless Ni under bump metallization (UBM) of about 10 mum thickness. The growth rate between intermetallic compounds in molten and solid solders differed by four orders of magnitude. In liquid solder, the growth rate is about 1 mum/min; the growth rate in solid solder is only about 10 -4 mum/min. The difference is not resulting from factors of thermodynamics, which is the change of Gibbs free energy before and after intermetallic compound formation, but from kinetic factors, which is the rate of change of Gibbs free energy. Even though the difference in growth rate between eutectic SnPb and Pb-free solders during solid state aging was found, the reason behind such difference shown is unclear. The orientation and stress levels of whiskers are measured by white X-ray of synchrotron radiation. The growth direction is nearly parallel to one of the principal axes of tin. The compressive stress level is quite low because the residual stress is relaxed by the whisker growth.

Programmable on-chip and off-chip network architecture on demand for flexible optical intra-datacenters.

PubMed

Rofoee, Bijan Rahimzadeh; Zervas, Georgios; Yan, Yan; Amaya, Norberto; Qin, Yixuan; Simeonidou, Dimitra

2013-03-11

The paper presents a novel network architecture on demand approach using on-chip and-off chip implementations, enabling programmable, highly efficient and transparent networking, well suited for intra-datacenter communications. The implemented FPGA-based adaptable line-card with on-chip design along with an architecture on demand (AoD) based off-chip flexible switching node, deliver single chip dual L2-Packet/L1-time shared optical network (TSON) server Network Interface Cards (NIC) interconnected through transparent AoD based switch. It enables hitless adaptation between Ethernet over wavelength switched network (EoWSON), and TSON based sub-wavelength switching, providing flexible bitrates, while meeting strict bandwidth, QoS requirements. The on and off-chip performance results show high throughput (9.86Ethernet, 8.68Gbps TSON), high QoS, as well as hitless switch-over.

Backside contacted field effect transistor array for extracellular signal recording.

PubMed

Ingebrandt, S; Yeung, C K; Staab, W; Zetterer, T; Offenhäusser, A

2003-04-01

A new approach to the design of field-effect transistor (FET) sensors and the use of these FETs in detecting extracellular electrophysiological recordings is reported. Backside contacts were engineered by deep reactive ion etching and a gas phase boron doping process of the holes using planar diffusion sources. The metal contacts were designed to fit on top of the bonding pads of a standard industrial 22-pin DIL (dual inline) chip carrier. To minimise contact resistance, the metal backside contacts of the chips were electroless plated with gold. The chips were mounted on top of the bonding pads using a standard flip-chip process and a fineplacer unit previously described. Rat embryonic myocytes were cultured on these new devices (effective growth area 6 x 6 mm(2)) in order to confirm their validity in electrophysiological recording. Copyright 2003 Elsevier Science B.V.

Broadband and scalable optical coupling for silicon photonics using polymer waveguides

NASA Astrophysics Data System (ADS)

La Porta, Antonio; Weiss, Jonas; Dangel, Roger; Jubin, Daniel; Meier, Norbert; Horst, Folkert; Offrein, Bert Jan

2018-04-01

We present optical coupling schemes for silicon integrated photonics circuits that account for the challenges in large-scale data processing systems such as those used for emerging big data workloads. Our waveguide based approach allows to optimally exploit the on-chip optical feature size, and chip- and package real-estate. It further scales well to high numbers of channels and is compatible with state-of-the-art flip-chip die packaging. We demonstrate silicon waveguide to polymer waveguide coupling losses below 1.5 dB for both the O- and C-bands with a polarisation dependent loss of <1 dB. Over 100 optical silicon waveguide to polymer waveguide interfaces were assembled within a single alignment step, resulting in a physical I/O channel density of up to 13 waveguides per millimetre along the chip-edge, with an average coupling loss of below 3.4 dB measured at 1310 nm.

Design and Training of Limited-Interconnect Architectures

DTIC Science & Technology

1991-07-16

and signal processing. Neuromorphic (brain like) models, allow an alternative for achieving real-time operation tor such tasks, while having a...compact and robust architecture. Neuromorphic models consist of interconnections of simple computational nodes. In this approach, each node computes a...operational performance. I1. Research Objectives The research objectives were: 1. Development of on- chip local training rules specifically designed for

NEXUS Scalable and Distributed Next-Generation Avionics Bus for Space Missions

NASA Technical Reports Server (NTRS)

He, Yutao; Shalom, Eddy; Chau, Savio N.; Some, Raphael R.; Bolotin, Gary S.

2011-01-01

A paper discusses NEXUS, a common, next-generation avionics interconnect that is transparently compatible with wired, fiber-optic, and RF physical layers; provides a flexible, scalable, packet switched topology; is fault-tolerant with sub-microsecond detection/recovery latency; has scalable bandwidth from 1 Kbps to 10 Gbps; has guaranteed real-time determinism with sub-microsecond latency/jitter; has built-in testability; features low power consumption (< 100 mW per Gbps); is lightweight with about a 5,000-logic-gate footprint; and is implemented in a small Bus Interface Unit (BIU) with reconfigurable back-end providing interface to legacy subsystems. NEXUS enhances a commercial interconnect standard, Serial RapidIO, to meet avionics interconnect requirements without breaking the standard. This unified interconnect technology can be used to meet performance, power, size, and reliability requirements of all ranges of equipment, sensors, and actuators at chip-to-chip, board-to-board, or box-to-box boundary. Early results from in-house modeling activity of Serial RapidIO using VisualSim indicate that the use of a switched, high-performance avionics network will provide a quantum leap in spacecraft onboard science and autonomy capability for science and exploration missions.

Monolithic integration of a silica AWG and Ge photodiodes on Si photonic platform for one-chip WDM receiver.

PubMed

Nishi, Hidetaka; Tsuchizawa, Tai; Kou, Rai; Shinojima, Hiroyuki; Yamada, Takashi; Kimura, Hideaki; Ishikawa, Yasuhiko; Wada, Kazumi; Yamada, Koji

2012-04-09

On the silicon (Si) photonic platform, we monolithically integrated a silica-based arrayed-waveguide grating (AWG) and germanium (Ge) photodiodes (PDs) using low-temperature fabrication technology. We confirmed demultiplexing by the AWG, optical-electrical signal conversion by Ge PDs, and high-speed signal detection at all channels. In addition, we mounted a multichannel transimpedance amplifier/limiting amplifier (TIA/LA) circuit on the fabricated AWG-PD device using flip-chip bonding technology. The results show the promising potential of our Si photonic platform as a photonics-electronics convergence.

Plastic straw: future of high-speed signaling

NASA Astrophysics Data System (ADS)

Song, Ha Il; Jin, Huxian; Bae, Hyeon-Min

2015-11-01

The ever-increasing demand for bandwidth triggered by mobile and video Internet traffic requires advanced interconnect solutions satisfying functional and economic constraints. A new interconnect called E-TUBE is proposed as a cost-and-power-effective all-electrical-domain wideband waveguide solution for high-speed high-volume short-reach communication links. The E-TUBE achieves an unprecedented level of performance in terms of bandwidth-per-carrier frequency, power, and density without requiring a precision manufacturing process unlike conventional optical/waveguide solutions. The E-TUBE exhibits a frequency-independent loss-profile of 4 dB/m and has nearly 20-GHz bandwidth over the V band. A single-sideband signal transmission enabled by the inherent frequency response of the E-TUBE renders two-times data throughput without any physical overhead compared to conventional radio frequency communication technologies. This new interconnect scheme would be attractive to parties interested in high throughput links, including but not limited to, 100/400 Gbps chip-to-chip communications.

Planned development of a 3D computer based on free-space optical interconnects

NASA Astrophysics Data System (ADS)

Neff, John A.; Guarino, David R.

1994-05-01

Free-space optical interconnection has the potential to provide upwards of a million data channels between planes of electronic circuits. This may result in the planar board and backplane structures of today giving away to 3-D stacks of wafers or multi-chip modules interconnected via channels running perpendicular to the processor planes, thereby eliminating much of the packaging overhead. Three-dimensional packaging is very appealing for tightly coupled fine-grained parallel computing where the need for massive numbers of interconnections is severely taxing the capabilities of the planar structures. This paper describes a coordinated effort by four research organizations to demonstrate an operational fine-grained parallel computer that achieves global connectivity through the use of free space optical interconnects.

Radiometer on a Chip

NASA Technical Reports Server (NTRS)

Chattopadhyay, Goutam; Gill, John J.; Mehdi, Imran; Lee, Choonsup; Schlecht, Erich T.; Skalare, Anders; Ward, John S.; Siegel, Peter H.; Thomas, Bertrand C.

2009-01-01

The radiometer on a chip (ROC) integrates whole wafers together to p rovide a robust, extremely powerful way of making submillimeter rece ivers that provide vertically integrated functionality. By integratin g at the wafer level, customizing the interconnects, and planarizing the transmission media, it is possible to create a lightweight asse mbly performing the function of several pieces in a more conventiona l radiometer.

Modular microfluidic systems using reversibly attached PDMS fluid control modules

NASA Astrophysics Data System (ADS)

Skafte-Pedersen, Peder; Sip, Christopher G.; Folch, Albert; Dufva, Martin

2013-05-01

The use of soft lithography-based poly(dimethylsiloxane) (PDMS) valve systems is the dominating approach for high-density microscale fluidic control. Integrated systems enable complex flow control and large-scale integration, but lack modularity. In contrast, modular systems are attractive alternatives to integration because they can be tailored for different applications piecewise and without redesigning every element of the system. We present a method for reversibly coupling hard materials to soft lithography defined systems through self-aligning O-ring features thereby enabling easy interfacing of complex-valve-based systems with simpler detachable units. Using this scheme, we demonstrate the seamless interfacing of a PDMS-based fluid control module with hard polymer chips. In our system, 32 self-aligning O-ring features protruding from the PDMS fluid control module form chip-to-control module interconnections which are sealed by tightening four screws. The interconnection method is robust and supports complex fluidic operations in the reversibly attached passive chip. In addition, we developed a double-sided molding method for fabricating PDMS devices with integrated through-holes. The versatile system facilitates a wide range of applications due to the modular approach, where application specific passive chips can be readily attached to the flow control module.

Development of chip passivated monolithic complementary MISFET circuits with beam leads

NASA Technical Reports Server (NTRS)

Ragonese, L. J.; Kim, M. J.; Corrie, B. L.; Brouillette, J. W.; Warr, R. E.

1972-01-01

The results are presented of a program to demonstrate the processes for fabricating complementary MISFET beam-leaded circuits, which, potentially, are comparable in quality to available bipolar beam-lead chips that use silicon nitride passivation in conjunction with a platinum-titanium-gold metal system. Materials and techniques, different from the bipolar case, were used in order to be more compatible with the special requirements of fully passivated complementary MISFET devices. Two types of circuits were designed and fabricated, a D-flip-flop and a three-input NOR/NAND gate. Fifty beam-leaded chips of each type were constructed. A quality and reliability assurance program was performed to identify failure mechanisms. Sample tests and inspections (including destructive) were developed to measure the physical characteristics of the circuits.

Vertical integration of array-type miniature interferometers at wafer level by using multistack anodic bonding

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Wiemer, Maik; Froemel, Joerg; Enderlein, Tom; Gessner, Thomas; Lullin, Justine; Bargiel, Sylwester; Passilly, Nicolas; Albero, Jorge; Gorecki, Christophe

2016-04-01

In this work, vertical integration of miniaturized array-type Mirau interferometers at wafer level by using multi-stack anodic bonding is presented. Mirau interferometer is suitable for MEMS metrology and for medical imaging according to its vertical-, lateral- resolutions and working distances. Miniaturized Mirau interferometer can be a promising candidate as a key component of an optical coherence tomography (OCT) system. The miniaturized array-type interferometer consists of a microlens doublet, a Si-based MEMS Z scanner, a spacer for focus-adjustment and a beam splitter. Therefore, bonding technologies which are suitable for heterogeneous substrates are of high interest and necessary for the integration of MEMS/MOEMS devices. Multi-stack anodic bonding, which meets the optical and mechanical requirements of the MOEMS device, is adopted to integrate the array-type interferometers. First, the spacer and the beam splitter are bonded, followed by bonding of the MEMS Z scanner. In the meanwhile, two microlenses, which are composed of Si and glass wafers, are anodically bonded to form a microlens doublet. Then, the microlens doublet is aligned and bonded with the scanner/spacer/beam splitter stack. The bonded array-type interferometer is a 7- wafer stack and the thickness is approximately 5mm. To separate such a thick wafer stack with various substrates, 2-step laser cutting is used to dice the bonded stack into Mirau chips. To simplify fabrication process of each component, electrical connections are created at the last step by mounting a Mirau chip onto a flip chip PCB instead of through wafer vias. Stability of Au/Ti films on the MEMS Z scanner after anodic bonding, laser cutting and flip chip bonding are discussed as well.

Additive manufacturing and analysis of high frequency interconnects for microwave devices

NASA Astrophysics Data System (ADS)

Harper, Elicia K.

Wire bond interconnects have been the main approach to interconnecting microelectronic devices within a package. Conventional wirebonding however offers little control of the impedance of the interconnect and also introduces parasitic inductance that can degrade performance at microwave frequencies. The size and compactness of microchips is often an issue when it comes to attaching wirebonds to the microchip or other components within a microwave module. This work demonstrates the use of additive manufacturing for printing interconnects directly between bare die microchips and other components within a microwave module. A test structure was developed consisting of a GaAs microchip sandwiched between two alumina blocks patterned with coplanar waveguides (CPW). A printed dielectric ink is used to fill the gap between the alumina CPW blocks and the GaAs chip. Conductive interconnects are printed on top of the dielectric bridge material to connect the CPW traces to the bonding pads on the GaAs microchip. Simulations of these structures were modeled in the electromagnetics simulation tool by ANSYS, high frequency structure simulation (HFSS), to optimize the printed interconnects at 1-40 GHz (ANSYS Inc., Canonsburg, PA). The dielectric constant and loss tangent of the simulated dielectric was varied along with the dimensions of the conductive interconnects. The best combination of dielectric properties and interconnect dimensions was chosen for impedance matching by analyzing the insertion losses and return losses. A dielectric ink, which was chosen based on the simulated results, was experimentally printed between the two CPW blocks and the GaAs chip and subsequently cured. The conductive interconnects were then printed with an aerosol jet printer, connecting the CPW traces to the bonding pads on the GaAs microchip. The experimental prototype was then measured with a network analyzer and the measured data were compared to simulations. Results show good agreement between the simulated and measured S-parameters. This work demonstrates the potential for using additive manufacturing technology to create impedance- matched interconnects between high frequency ICs and other module components such as high frequency CPW transmission lines.

Upset due to a single particle caused propagated transients in a bulk CMOS microprocessor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Leavy, J.F.; Hoffmann, L.F.; Shoran, R.W.

1991-12-01

This paper reports on data pattern advances observed in preset, single event upset (SEU) hardened clocked flip-flops, during static Cf-252 exposures on a bulk CMOS microprocessor, that were attributable to particle caused anomalous clock signals, or propagated transients. SPICE simulations established that particle strikes in the output nodes of a clock control logic flip-flop could produce transients of sufficient amplitude and duration to be accepted as legitimate pulses by clock buffers fed by the flip-flop's output nodes. The buffers would then output false clock pulses, thereby advancing the state of the present flip-flops. Masking the clock logic on one ofmore » the test chips made the flip-flop data advance cease, confirming the clock logic as the source of the SEU. By introducing N{sub 2} gas, at reduced pressures, into the SEU test chamber to attenuate Cf-252 particle LET's, a 24-26 MeV-cm{sup 2}/mg LET threshold was deduced. Subsequent tests, at the 88-inch cyclotron at Berkeley, established an LET threshold of 30 MeV-cm{sup 2}/mg (283 MeV Cu at 0{degrees}) for the generation of false clocks. Cyclotron SEU tests are considered definitive, while Cf-252 data usually is not. However, in this instance Cf-252 tests proved analytically useful, providing SEU characterization data that was both timely and inexpensive.« less

Optical RAM-enabled cache memory and optical routing for chip multiprocessors: technologies and architectures

NASA Astrophysics Data System (ADS)

Pleros, Nikos; Maniotis, Pavlos; Alexoudi, Theonitsa; Fitsios, Dimitris; Vagionas, Christos; Papaioannou, Sotiris; Vyrsokinos, K.; Kanellos, George T.

2014-03-01

The processor-memory performance gap, commonly referred to as "Memory Wall" problem, owes to the speed mismatch between processor and electronic RAM clock frequencies, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In this article, we present our recent work spanning from Si-based integrated optical RAM cell architectures up to complete optical cache memory architectures for Chip Multiprocessor configurations. Moreover, we discuss on e/o router subsystems with up to Tb/s routing capacity for cache interconnection purposes within CMP configurations, currently pursued within the FP7 PhoxTrot project.

A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors.

PubMed

Close, Gael F; Yasuda, Shinichi; Paul, Bipul; Fujita, Shinobu; Wong, H-S Philip

2008-02-01

Due to their excellent electrical properties, metallic carbon nanotubes are promising materials for interconnect wires in future integrated circuits. Simulations have shown that the use of metallic carbon nanotube interconnects could yield more energy efficient and faster integrated circuits. The next step is to build an experimental prototype integrated circuit using carbon nanotube interconnects operating at high speed. Here, we report the fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz. In addition to setting a milestone by operating above 1 GHz, this prototype is also a tool to investigate carbon nanotubes on a silicon-based platform at high frequencies, paving the way for future multi-GHz nanoelectronics.

Battery tester

DOE Office of Scientific and Technical Information (OSTI.GOV)

Poljak, M.D.

1985-08-12

This abstract discloses an improved battery tester for determining the acceptability of a Lithium Sulfur Dioxide (LiSO/sub 2/) storage battery at a given temperature and with one or more cells therein. The tester is generally made up of a first-comparison circuit having a series of series-interconnected components, namely a comparator, first and second flip-flops, and an AND gate. A first resistor is parallel connected to the first-comparison circuit. A second comparison circuit is also parallel connected to the first-comparison circuit and is generally made up of series-interconnected components, namely a second resistor, a capacitor, a buffer, and a second-comparator. Amore » first switch is connected to the first resistor and a second switch is parallel connected to the second-comparison circuit between the capacitor and the buffer. A logic control arrangement controls the operation of both switches, both comparators, and both flip-flops for testing a battery as to its start-up voltage and performance voltage characteristics all in a relatively short time period. In another embodiment of the tester, it is provided with an analog-to-digital converter, a memory, and a sensor arrangement for enhancing the versatility and reliability of the tester in determining the acceptability of a LiSO/sub 2/ battery.« less

A new on-chip all-digital three-phase full-bridge dc/ac power inverter with feedforward and frequency control techniques.

PubMed

Chen, Jiann-Jong; Kung, Che-Min

2010-09-01

The communication speed between components is far from satisfactory. To achieve high speed, simple control system configuration, and low cost, a new on-chip all-digital three-phase dc/ac power inverter using feedforward and frequency control techniques is proposed. The controller of the proposed power inverter, called the shift register, consists of six-stage D-latch flip-flops with a goal of achieving low-power consumption and area efficiency. Variable frequency is achieved by controlling the clocks of the shift register. One advantage regarding the data signal (D) and the common clock (CK) is that, regardless of the phase difference between the two, all of the D-latch flip-flops are capable of delaying data by one CK period. To ensure stability, the frequency of CK must be six times higher than that of D. The operation frequency of the proposed power inverter ranges from 10 Hz to 2 MHz, and the maximum output loading current is 0.8 A. The prototype of the proposed circuit has been fabricated with TSMC 0.35 μm 2P4M CMOS processes. The total chip area is 2.333 x 1.698 mm2. The three-phase dc/ac power inverter is applicable in uninterrupted power supplies, cold cathode fluorescent lamps, and motors, because of its ability to convert the dc supply voltage into the three-phase ac power sources.

Polymer waveguides for electro-optical integration in data centers and high-performance computers.

PubMed

Dangel, Roger; Hofrichter, Jens; Horst, Folkert; Jubin, Daniel; La Porta, Antonio; Meier, Norbert; Soganci, Ibrahim Murat; Weiss, Jonas; Offrein, Bert Jan

2015-02-23

To satisfy the intra- and inter-system bandwidth requirements of future data centers and high-performance computers, low-cost low-power high-throughput optical interconnects will become a key enabling technology. To tightly integrate optics with the computing hardware, particularly in the context of CMOS-compatible silicon photonics, optical printed circuit boards using polymer waveguides are considered as a formidable platform. IBM Research has already demonstrated the essential silicon photonics and interconnection building blocks. A remaining challenge is electro-optical packaging, i.e., the connection of the silicon photonics chips with the system. In this paper, we present a new single-mode polymer waveguide technology and a scalable method for building the optical interface between silicon photonics chips and single-mode polymer waveguides.

Engineering anastomosis between living capillary networks and endothelial cell-lined microfluidic channels.

PubMed

Wang, Xiaolin; Phan, Duc T T; Sobrino, Agua; George, Steven C; Hughes, Christopher C W; Lee, Abraham P

2016-01-21

This paper reports a method for generating an intact and perfusable microvascular network that connects to microfluidic channels without appreciable leakage. This platform incorporates different stages of vascular development including vasculogenesis, endothelial cell (EC) lining, sprouting angiogenesis, and anastomosis in sequential order. After formation of a capillary network inside the tissue chamber via vasculogenesis, the adjacent microfluidic channels are lined with a monolayer of ECs, which then serve as the high-pressure input ("artery") and low pressure output ("vein") conduits. To promote a tight interconnection between the artery/vein and the capillary network, sprouting angiogenesis is induced, which promotes anastomosis of the vasculature inside the tissue chamber with the EC lining along the microfluidic channels. Flow of fluorescent microparticles confirms the perfusability of the lumenized microvascular network, and minimal leakage of 70 kDa FITC-dextran confirms physiologic tightness of the EC junctions and completeness of the interconnections between artery/vein and the capillary network. This versatile device design and its robust construction methodology establish a physiological transport model of interconnected perfused vessels from artery to vascularized tissue to vein. The system has utility in a wide range of organ-on-a-chip applications as it enables the physiological vascular interconnection of multiple on-chip tissue constructs that can serve as disease models for drug screening.

Comparative experimental and simulation studies of high-power AlGaN-based 353 nm ultraviolet flip-chip and top-emitting LEDs

NASA Astrophysics Data System (ADS)

Liu, Mengling; Zhou, Shengjun; Liu, Xingtong; Gao, Yilin; Ding, Xinghuo

2018-03-01

Experimental and simulation studies of high-power AlGaN-based 353 nm ultraviolet (UV) flip-chip (FC) and top-emitting (TE) light-emitting diodes (LEDs) are performed here. To improve the optical and electrical properties of ultraviolet LEDs, we fabricate high-power FC-UV LEDs with Ta2O5/SiO2 distributed Bragg reflectors (DBRs) and a strip-shaped SiO2 current blocking layer (CBL). The reflectance of fourteen pairs of Ta2O5/SiO2 DBRs is 96.4% at 353 nm. The strip-shaped SiO2 CBL underneath the strip-shaped p-electrode can prevent the current concentrating in regions immediately adjacent to the p-electrode where the overlying opaque p-electrode metal layer absorbs the emitted UV light. Moreover, two-level metallization electrodes are used to improve current spreading. Our numerical results show that FC-UV LED has a more favorable current spreading uniformity than TE-UV LED. The light output power of 353 nm FC-UV LED was 23.22 mW at 350 mA, which is 24.7% higher than that of TE-UV LED.

Nucleation rates of Sn in undercooled Sn-Ag-Cu flip-chip solder joints

NASA Astrophysics Data System (ADS)

Arfaei, B.; Benedict, M.; Cotts, E. J.

2013-11-01

The nucleation of Sn from the melt in commercial SnAgCu flip chip solder joints was monitored at a number of different temperatures. Nucleation rates were estimated from measurements of nucleation times for 440 solder balls after one reflow and were found to be well epitomized by the expression I = 2 × 109 exp[(-1.6 × 105)/(T × (ΔT)2)] m-3 s-1, as per classical nucleation theory. After an additional reflow, the nucleation rates of the same 440 samples were observed to increase to I = 2 × 109 exp[(-8.9 × 104)/(T × (ΔT)2)] m-3 s-1. Thus it was shown that the expressions of classical nucleation theory well characterize nucleation kinetics for this system. These changes in nucleation kinetics were correlated with continued dissolution of Al and Ni in to the SnAgCu melt. Such increases in nucleation rates meant increases in the average solidification temperatures of the solder balls after reflow. Variations in the Sn grain morphology of the solder joints were correlated with these changes in solidification temperature, with larger Sn grains (beach ball Sn grain morphology) observed at higher solidification temperatures.

CMOS chip planarization by chemical mechanical polishing for a vertically stacked metal MEMS integration

NASA Astrophysics Data System (ADS)

Lee, Hocheol; Miller, Michele H.; Bifano, Thomas G.

2004-01-01

In this paper we present the planarization process of a CMOS chip for the integration of a microelectromechanical systems (MEMS) metal mirror array. The CMOS chip, which comes from a commercial foundry, has a bumpy passivation layer due to an underlying aluminum interconnect pattern (1.8 µm high), which is used for addressing individual micromirror array elements. To overcome the tendency for tilt error in the CMOS chip planarization, the approach is to sputter a thick layer of silicon nitride at low temperature and to surround the CMOS chip with dummy silicon pieces that define a polishing plane. The dummy pieces are first lapped down to the height of the CMOS chip, and then all pieces are polished. This process produced a chip surface with a root-mean-square flatness error of less than 100 nm, including tilt and curvature errors.

Novel Highly Parallel and Systolic Architectures Using Quantum Dot-Based Hardware

NASA Technical Reports Server (NTRS)

Fijany, Amir; Toomarian, Benny N.; Spotnitz, Matthew

1997-01-01

VLSI technology has made possible the integration of massive number of components (processors, memory, etc.) into a single chip. In VLSI design, memory and processing power are relatively cheap and the main emphasis of the design is on reducing the overall interconnection complexity since data routing costs dominate the power, time, and area required to implement a computation. Communication is costly because wires occupy the most space on a circuit and it can also degrade clock time. In fact, much of the complexity (and hence the cost) of VLSI design results from minimization of data routing. The main difficulty in VLSI routing is due to the fact that crossing of the lines carrying data, instruction, control, etc. is not possible in a plane. Thus, in order to meet this constraint, the VLSI design aims at keeping the architecture highly regular with local and short interconnection. As a result, while the high level of integration has opened the way for massively parallel computation, practical and full exploitation of such a capability in many applications of interest has been hindered by the constraints on interconnection pattern. More precisely. the use of only localized communication significantly simplifies the design of interconnection architecture but at the expense of somewhat restricted class of applications. For example, there are currently commercially available products integrating; hundreds of simple processor elements within a single chip. However, the lack of adequate interconnection pattern among these processing elements make them inefficient for exploiting a large degree of parallelism in many applications.

Silicon photonics for high-performance interconnection networks

NASA Astrophysics Data System (ADS)

Biberman, Aleksandr

2011-12-01

We assert in the course of this work that silicon photonics has the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems, and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. This work showcases that chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, enable unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of this work, we demonstrate such feasibility of waveguides, modulators, switches, and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. Furthermore, we leverage the unique properties of available silicon photonic materials to create novel silicon photonic devices, subsystems, network topologies, and architectures to enable unprecedented performance of these photonic interconnection networks and computing systems. We show that the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers. Furthermore, we explore the immense potential of all-optical functionalities implemented using parametric processing in the silicon platform, demonstrating unique methods that have the ability to revolutionize computation and communication. Silicon photonics enables new sets of opportunities that we can leverage for performance gains, as well as new sets of challenges that we must solve. Leveraging its inherent compatibility with standard fabrication techniques of the semiconductor industry, combined with its capability of dense integration with advanced microelectronics, silicon photonics also offers a clear path toward commercialization through low-cost mass-volume production. Combining empirical validations of feasibility, demonstrations of massive performance gains in large-scale systems, and the potential for commercial penetration of silicon photonics, the impact of this work will become evident in the many decades that follow.

Thin glass based packaging and photonic single-mode waveguide integration by ion-exchange technology on board and module level

NASA Astrophysics Data System (ADS)

Brusberg, Lars; Lang, Günter; Schröder, Henning

2011-01-01

The proposed novel packaging approach merges micro-system packaging and glass integrated optics. It provides 3D optical single-mode intra system links to bridge the gap between novel photonic integrated circuits and the glass fibers for inter system interconnects. We introduce our hybrid 3D photonic packaging approach based on thin glass substrates with planar integrated optical single-mode waveguides for fiber-to-chip and chip-to-chip links. Optical mirrors and lenses provide optical mode matching for photonic IC assemblies and optical fiber interconnects. Thin glass is commercially available in panel and wafer formats and characterizes excellent optical and high-frequency properties as reviewed in the paper. That makes it perfect for micro-system packaging. The adopted planar waveguide process based on ion-exchange technology is capable for high-volume manufacturing. This ion-exchange process and the optical propagation are described in detail for thin glass substrates. An extensive characterization of all basic circuit elements like straight and curved waveguides, couplers and crosses proves the low attenuation of the optical circuit elements.

Comment on "Enhancement of flip-chip white light-emitting diodes with a one-dimensional photonic crystal".

PubMed

Liu, Zong-Yuan; Liu, Sheng; Wang, Kai; Luo, Xiao-Bing

2010-06-01

We show that research presented in Opt. Lett.34, 301 (2009)OPLEDP0146-959210.1364/OL.34.000301 applied questionable phosphor definitions and a questionable simulation procedure for light-emitting diodes. Our simulation indicates that a one-dimensional photonic crystal is beneficial for color control but cannot improve the light extraction as asserted in that Letter.

Adaptive Optoelectronic Eyes: Hybrid Sensor/Processor Architectures

DTIC Science & Technology

2006-11-13

corresponding calculated data. The width of the mirror stopband is proportional to the refractive index difference between the high and low index materials ...Silicon VLSI Neuron Unit Arrays 56 Development of a Single-Sided Flip-Chip Bonding Process 65 Development of High Refractive Index Diffractive Optical ...Elements (DOEs) 68 Development of High-Performance Antireflection Coatings for High Refractive Index DOEs 69 Design and Fabrication of Low Threshold

DOE Office of Scientific and Technical Information (OSTI.GOV)

McAdams, Brian J.; Pearson, Raymond A.

With the continuing trend of decreasing feature sizes in flip-chip assemblies, the reliability tolerance to interfacial flaws is also decreasing. Small-scale disbonds will become more of a concern, pointing to the need for a better understanding of the initiation stage of interfacial delamination. With most accepted adhesion metric methodologies tailored to predict failure under the prior existence of a disbond, the study of the initiation phenomenon is open to development and standardization of new testing procedures. Traditional fracture mechanics approaches are not suitable, as the mathematics assume failure to originate at a disbond or crack tip. Disbond initiation is believedmore » to first occur at free edges and corners, which act as high stress concentration sites and exhibit singular stresses similar to a crack tip, though less severe in intensity. As such, a 'fracture mechanics-like' approach may be employed which defines a material parameter--a critical stress intensity factor (K{sub c})--that can be used to predict when initiation of a disbond at an interface will occur. The factors affecting the adhesion of underfill/polyimide interfaces relevant to flip-chip assemblies were investigated in this study. The study consisted of two distinct parts: a comparison of the initiation and propagation phenomena and a comparison of the relationship between sub-critical and critical initiation of interfacial failure. The initiation of underfill interfacial failure was studied by characterizing failure at a free-edge with a critical stress intensity factor. In comparison with the interfacial fracture toughness testing, it was shown that a good correlation exists between the initiation and propagation of interfacial failures. Such a correlation justifies the continuing use of fracture mechanics to predict the reliability of flip-chip packages. The second aspect of the research involved fatigue testing of tensile butt joint specimens to determine lifetimes at sub-critical load levels. The results display an interfacial strength ranking similar to that observed during monotonic testing. The fatigue results indicate that monotonic fracture mechanics testing may be an adequate screening tool to help predict cyclic underfill failure; however lifetime data is required to predict reliability.« less

A non-volatile flip-flop based on diode-selected PCM for ultra-low power systems

NASA Astrophysics Data System (ADS)

Ye, Yong; Du, Yuan; Gao, Dan; Kang, Yong; Song, Zhitang; Chen, Bomy

2016-10-01

As the process technology is continuously shrinking, low power consumption is a major issue in VLSI Systems-on-Chip (SoCs), especially for standby-power-critical applications. Recently, the emerging CMOS-compatible non-volatile memories (NVMs), such as Phase Change Memory (PCM), have been used as on-chip storage elements, which can obtain non-volatile processing, nearly-zero standby power and instant-on capability. PCM has been considered as the best candidate for the next generation of NVMs for its low cost, high density and high resistance transformation ratio. In this paper, for the first time, we present a diode-selected PCM based non-volatile flip-flop (NVFF) which is optimized for better power consumption and process variation tolerance. With dual trench isolation process, the diode-selected PCM realizes ultra small area, which is very suitable for multi-context configuration and large scale flip-flops matrix. Since the MOS-selected PCM is hard to shrink further due to large amount of PCM write current, the proposed NVFF achieves higher power efficiency without loss of current driving capability. Using the 40nm manufacturing process, the area of the cell (1D1R) is as small as 0.016 μm2. Simulation results show that the energy consumption during the recall operation is 62 fJ with 1.1 standard supply voltage, which is reduced by 54.9% compared to the previous 2T2R based NVFF. When the supply voltage reduces to 0.7 V, the recall energy is as low as 17 fJ. With the great advantages in cell size and energy, the proposed diode-selected NVFF is very applicable and cost-effective for ULP systems.

Ultra-compact 32 × 32 strictly-non-blocking Si-wire optical switch with fan-out LGA interposer.

PubMed

Tanizawa, Ken; Suzuki, Keijiro; Toyama, Munehiro; Ohtsuka, Minoru; Yokoyama, Nobuyuki; Matsumaro, Kazuyuki; Seki, Miyoshi; Koshino, Keiji; Sugaya, Toshio; Suda, Satoshi; Cong, Guangwei; Kimura, Toshio; Ikeda, Kazuhiro; Namiki, Shu; Kawashima, Hitoshi

2015-06-29

We demonstrate a 32 × 32 path-independent-insertion-loss optical path switch that integrates 1024 thermooptic Mach-Zehnder switches and 961 intersections on a small, 11 × 25 mm2 die. The switch is fabricated on a 300-mm-diameter silicon-on-insulator wafer by a complementary metal-oxide semiconductor-compatible process with advanced ArF immersion lithography. For reliable electrical packaging, the switch chip is flip-chip bonded to a ceramic interposer that arranges the electrodes in a 0.5-mm pitch land grid array. The on-chip loss is measured to be 15.8 ± 1.0 dB, and successful switching is demonstrated for digital-coherent 43-Gb/s QPSK signals. The total crosstalk of the switch is estimated to be less than -20 dB at the center wavelength of 1545 nm. The bandwidth narrowing caused by dimensional errors that arise during fabrication is discussed.

Electrically-pumped compact hybrid silicon microring lasers for optical interconnects.

PubMed

Liang, Di; Fiorentino, Marco; Okumura, Tadashi; Chang, Hsu-Hao; Spencer, Daryl T; Kuo, Ying-Hao; Fang, Alexander W; Dai, Daoxin; Beausoleil, Raymond G; Bowers, John E

2009-10-26

We demonstrate an electrically-pumped hybrid silicon microring laser fabricated by a self-aligned process. The compact structure (D = 50 microm) and small electrical and optical losses result in lasing threshold as low as 5.4 mA and up to 65 degrees C operation temperature in continuous-wave (cw) mode. The spectrum is single mode with large extinction ratio and small linewidth observed. Application as on-chip optical interconnects is discussed from a system perspective.

Accelerated Thermal Cycling and Failure Mechanisms

NASA Technical Reports Server (NTRS)

Ghaffarian, R.

1999-01-01

This paper reviews the accelerated thermal cycling test methods that are currently used by industry to characterize the interconnect reliability of commercial-off-the-shelf (COTS) ball grid array (BGA) and chip scale package (CSP) assemblies.

Mega-pixel PQR laser chips for interconnect, display ITS, and biocell-tweezers OEIC

NASA Astrophysics Data System (ADS)

Kwon, O'Dae; Yoon, J. H.; Kim, D. K.; Kim, Y. C.; Lee, S. E.; Kim, S. S.

2008-02-01

We describe a photonic quantum ring (PQR) laser device of three dimensional toroidal whispering gallery cavity. We have succeeded in fabricating the first genuine mega-pixel laser chips via regular semiconductor technology. This has been realized since the present injection laser emitting surface-normal dominant 3D whispering gallery modes (WGMs) can be operated CW with extremely low operating currents (μA-nA per pixel), together with the lasing temperature stabilities well above 140 deg C with minimal redshifts, which solves the well-known integration problems facing the conventional VCSEL. Such properties unusual for quantum well lasers become usual because the active region, involving vertically confining DBR structure in addition to the 2D concave WGM geometry, induces a 'photonic quantum ring (PQR)-like' carrier distribution through a photonic quantum corral effect. A few applications of such mega-pixel PQR chips are explained as follows: (A) Next-generation 3D semiconductor technologies demand a strategy on the inter-chip and intra-chip optical interconnect schemes with a key to the high-density emitter array. (B) Due to mounting traffic problems and fatalities ITS technology today is looking for a revolutionary change in the technology. We will thus outline how 'SLEEP-ITS' can emerge with the PQR's position-sensing capability. (C) We describe a recent PQR 'hole' laser of convex WGM: Mega-pixel PQR 'hole' laser chips are even easier to fabricate than PQR 'mesa' lasers. Genuine Laguerre-Gaussian (LG) beam patterns of PQR holes are very promising for biocell manipulations like sorting mouse myeloid leukemia (M1s) cells. (D) Energy saving and 3D speckle-free POR laser can outdo LEDs in view of red GaAs and blue GaN devices fabricated recently.

Scalable Motion Estimation Processor Core for Multimedia System-on-Chip Applications

NASA Astrophysics Data System (ADS)

Lai, Yeong-Kang; Hsieh, Tian-En; Chen, Lien-Fei

2007-04-01

In this paper, we describe a high-throughput and scalable motion estimation processor architecture for multimedia system-on-chip applications. The number of processing elements (PEs) is scalable according to the variable algorithm parameters and the performance required for different applications. Using the PE rings efficiently and an intelligent memory-interleaving organization, the efficiency of the architecture can be increased. Moreover, using efficient on-chip memories and a data management technique can effectively decrease the power consumption and memory bandwidth. Techniques for reducing the number of interconnections and external memory accesses are also presented. Our results demonstrate that the proposed scalable PE-ringed architecture is a flexible and high-performance processor core in multimedia system-on-chip applications.

On-chip spin-controlled orbital angular momentum directional coupling

NASA Astrophysics Data System (ADS)

Xie, Zhenwei; Lei, Ting; Si, Guangyuan; Du, Luping; Lin, Jiao; Min, Changjun; Yuan, Xiaocong

2018-01-01

Optical vortex beams have many potential applications in the particle trapping, quantum encoding, optical orbital angular momentum (OAM) communications and interconnects. However, the on-chip compact OAM detection is still a big challenge. Based on a holographic configuration and a spin-dependent structure design, we propose and demonstrate an on-chip spin-controlled OAM-mode directional coupler, which can couple the OAM signal to different directions due to its topological charge. While the directional coupling function can be switched on/off by altering the spin of incident beam. Both simulation and experimental measurements verify the validity of the proposed approach. This work would benefit the on-chip OAM devices for optical communications and high dimensional quantum coding/decoding in the future.

Phosphor-Free InGaN White Light Emitting Diodes Using Flip-Chip Technology

PubMed Central

Li, Ying-Chang; Chang, Liann-Be; Chen, Hou-Jen; Yen, Chia-Yi; Pan, Ke-Wei; Huang, Bohr-Ran; Kuo, Wen-Yu; Chow, Lee; Zhou, Dan; Popko, Ewa

2017-01-01

Monolithic phosphor-free two-color gallium nitride (GaN)-based white light emitting diodes (LED) have the potential to replace current phosphor-based GaN white LEDs due to their low cost and long life cycle. Unfortunately, the growth of high indium content indium gallium nitride (InGaN)/GaN quantum dot and reported LED’s color rendering index (CRI) are still problematic. Here, we use flip-chip technology to fabricate an upside down monolithic two-color phosphor-free LED with four grown layers of high indium quantum dots on top of the three grown layers of lower indium quantum wells separated by a GaN tunneling barrier layer. The photoluminescence (PL) and electroluminescence (EL) spectra of this white LED reveal a broad spectrum ranging from 475 to 675 nm which is close to an ideal white-light source. The corresponding color temperature and color rendering index (CRI) of the fabricated white LED, operated at 350, 500, and 750 mA, are comparable to that of the conventional phosphor-based LEDs. Insights of the epitaxial structure and the transport mechanism were revealed through the TEM and temperature dependent PL and EL measurements. Our results show true potential in the Epi-ready GaN white LEDs for future solid state lighting applications. PMID:28772792

Analysis of light extraction efficiency enhancement for thin-film-flip-chip InGaN quantum wells light-emitting diodes with GaN micro-domes.

PubMed

Zhao, Peng; Zhao, Hongping

2012-09-10

The enhancement of light extraction efficiency for thin-film flip-chip (TFFC) InGaN quantum wells (QWs) light-emitting diodes (LEDs) with GaN micro-domes on n-GaN layer was studied. The light extraction efficiency of TFFC InGaN QWs LEDs with GaN micro-domes were calculated and compared to that of the conventional TFFC InGaN QWs LEDs with flat surface. The three dimensional finite difference time domain (3D-FDTD) method was used to calculate the light extraction efficiency for the InGaN QWs LEDs emitting at 460nm and 550 nm, respectively. The effects of the GaN micro-dome feature size and the p-GaN layer thickness on the light extraction efficiency were studied systematically. Studies indicate that the p-GaN layer thickness is critical for optimizing the TFFC LED light extraction efficiency. Significant enhancement of the light extraction efficiency (2.5-2.7 times for λ(peak) = 460nm and 2.7-2.8 times for λ(peak) = 550nm) is achievable from TFFC InGaN QWs LEDs with optimized GaN micro-dome diameter and height.

Thermal Design and Characterization of Heterogeneously Integrated InGaP/GaAs HBTs

DOE PAGES

Choi, Sukwon; Peake, Gregory M.; Keeler, Gordon A.; ...

2016-04-21

Flip-chip heterogeneously integrated n-p-n InGaP/GaAs heterojunction bipolar transistors (HBTs) with integrated thermal management on wide-bandgap AlN substrates followed by GaAs substrate removal are demonstrated. Without thermal management, substrate removal after integration significantly aggravates self-heating effects, causing poor I–V characteristics due to excessive device self-heating. An electrothermal codesign scheme is demonstrated that involves simulation (design), thermal characterization, fabrication, and evaluation. Thermoreflectance thermal imaging, electrical-temperature sensitive parameter-based thermometry, and infrared thermography were utilized to assess the junction temperature rise in HBTs under diverse configurations. In order to reduce the thermal resistance of integrated devices, passive cooling schemes assisted by structural modification, i.e.,more » positioning indium bump heat sinks between the devices and the carrier, were employed. By implementing thermal heat sinks in close proximity to the active region of flip-chip integrated HBTs, the junction-to-baseplate thermal resistance was reduced over a factor of two, as revealed by junction temperature measurements and improvement of electrical performance. In conclusion, the suggested heterogeneous integration method accounts for not only electrical but also thermal requirements providing insight into realization of advanced and robust III–V/Si heterogeneously integrated electronics.« less

Microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2002-01-01

An apparatus for packaging of microelectronic devices, including an integral window. The microelectronic device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The package can include a cofired ceramic frame or body. The package can have an internal stepped structure made of one or more plates, with apertures, which are patterned with metallized conductive circuit traces. The microelectronic device can be flip-chip bonded on the plate to these traces, and oriented so that the light-sensitive side is optically accessible through the window. A cover lid can be attached to the opposite side of the package. The result is a compact, low-profile package, having an integral window that can be hermetically-sealed. The package body can be formed by low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the window being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. Multiple chips can be located within a single package. The cover lid can include a window. The apparatus is particularly suited for packaging of MEMS devices, since the number of handling steps is greatly reduced, thereby reducing the potential for contamination.

White light emitting diode based on InGaN chip with core/shell quantum dots

NASA Astrophysics Data System (ADS)

Shen, Changyu; Hong, Yan; Ma, Jiandong; Ming, Jiangzhou

2009-08-01

Quantum dots have many applications in optoelectronic device such as LEDs for its many superior properties resulting from the three-dimensional confinement effect of its carrier. In this paper, single chip white light-emitting diodes (WLEDs) were fabricated by combining blue InGaN chip with luminescent colloidal quantum dots (QDs). Two kinds of QDs of core/shell CdSe /ZnS and core/shell/shell CdSe /ZnS /CdS nanocrystals were synthesized by thermal deposition using cadmium oxide and selenium as precursors in a hot lauric acid and hexadecylamine trioctylphosphine oxide hybrid. This two kinds of QDs exhibited high photoluminescence efficiency with a quantum yield more than 41%, and size-tunable emission wavelengths from 500 to 620 nm. The QDs LED mainly consists of flip luminescent InGaN chip, glass ceramic protective coating, glisten cup, QDs using as the photoluminescence material, pyroceram, gold line, electric layer, dielectric layer, silicon gel and bottom layer for welding. The WLEDs had the CIE coordinates of (0.319, 0.32). The InGaN chip white-light-emitting diodes with quantum dots as the emitting layer are potentially useful in illumination and display applications.

Chip-to-chip optical link by using optical wiring method

NASA Astrophysics Data System (ADS)

Cho, In-Kui; Ahn, Seoung Ho; Jeong, Myung-Yung; Rho, Byung Sup; Park, Hyo Hoon

2008-01-01

A practical optical link system was prepared with a transmitter (Tx) and receiver (Rx). The optical TRx module consisted of a metal optical bench, a module printed circuit board (PCB), a driver/receiver IC, a VCSEL/PD array, and an optical link block composed of plastic optical fiber (POF). For the optical interconnection between the light-sources and detectors, an optical wiring method has been proposed to enable easy assembly. This paper provides a method for optical interconnection between an optical Tx and an optical Rx, comprising the following steps: (a) forming a light source device, an optical detection device, and an optical transmission unit on a substrate (metal optical bench (MOB)); (b) preparing a flexible optical transmission-connection medium (optical wiring link) to optically connect the light source device formed on the substrate with the optical detection device; and (c) directly connecting one end of the surface-finished optical transmission connection medium with the light source device and the other end with the optical detection device. A chip-to-chip optical link system constructed with TRx modules was fabricated and the optical characteristics were measured. The results clearly demonstrate that the use of an optical wiring method can provide robust and cost-effective assembly for vertical-cavity surface-emitting lasers (VCSELs) and photodiodes (PDs). We successfully achieved a 5 Gb/s data transmission rate with this optical link.

Nanofiber Anisotropic Conductive Films (ACF) for Ultra-Fine-Pitch Chip-on-Glass (COG) Interconnections

NASA Astrophysics Data System (ADS)

Lee, Sang-Hoon; Kim, Tae-Wan; Suk, Kyung-Lim; Paik, Kyung-Wook

2015-11-01

Nanofiber anisotropic conductive films (ACF) were invented, by adapting nanofiber technology to ACF materials, to overcome the limitations of ultra-fine-pitch interconnection packaging, i.e. shorts and open circuits as a result of the narrow space between bumps and electrodes. For nanofiber ACF, poly(vinylidene fluoride) (PVDF) and poly(butylene succinate) (PBS) polymers were used as nanofiber polymer materials. For PVDF and PBS nanofiber ACF, conductive particles of diameter 3.5 μm were incorporated into nanofibers by electrospinning. In ultra-fine-pitch chip-on-glass assembly, insulation was significantly improved by using nanofiber ACF, because nanofibers inside the ACF suppressed the mobility of conductive particles, preventing them from flowing out during the bonding process. Capture of conductive particles was increased from 31% (conventional ACF) to 65%, and stable electrical properties and reliability were achieved by use of nanofiber ACF.

Monolithic optoelectronic integrated broadband optical receiver with graphene photodetectors

NASA Astrophysics Data System (ADS)

Cheng, Chuantong; Huang, Beiju; Mao, Xurui; Zhang, Zanyun; Zhang, Zan; Geng, Zhaoxin; Xue, Ping; Chen, Hongda

2017-07-01

Optical receivers with potentially high operation bandwidth and low cost have received considerable interest due to rapidly growing data traffic and potential Tb/s optical interconnect requirements. Experimental realization of 65 GHz optical signal detection and 262 GHz intrinsic operation speed reveals the significance role of graphene photodetectors (PDs) in optical interconnect domains. In this work, a novel complementary metal oxide semiconductor post-backend process has been developed for integrating graphene PDs onto silicon integrated circuit chips. A prototype monolithic optoelectronic integrated optical receiver has been successfully demonstrated for the first time. Moreover, this is a firstly reported broadband optical receiver benefiting from natural broadband light absorption features of graphene material. This work is a perfect exhibition of the concept of monolithic optoelectronic integration and will pave way to monolithically integrated graphene optoelectronic devices with silicon ICs for three-dimensional optoelectronic integrated circuit chips.

System architecture of a gallium arsenide one-gigahertz digital IC tester

NASA Technical Reports Server (NTRS)

Fouts, Douglas J.; Johnson, John M.; Butner, Steven E.; Long, Stephen I.

1987-01-01

The design for a 1-GHz digital integrated circuit tester for the evaluation of custom GaAs chips and subsystems is discussed. Technology-related problems affecting the design of a GaAs computer are discussed, with emphasis on the problems introduced by long printed-circuit-board interconnect. High-speed interface modules provide a link between the low-speed microprocessor and the chip under test. Memory-multiplexer and memory-shift register architectures for the storage of test vectors are described in addition to an architecture for local data storage consisting of a long chain of GaAs shift registers. The tester is constructed around a VME system card cage and backplane, and very little high-speed interconnect exists between boards. The tester has a three part self-test consisting of a CPU board confidence test, a main memory confidence test, and a high-speed interface module functional test.

Mode selecting switch using multimode interference for on-chip optical interconnects.

PubMed

Priti, Rubana B; Pishvai Bazargani, Hamed; Xiong, Yule; Liboiron-Ladouceur, Odile

2017-10-15

A novel mode selecting switch (MSS) is experimentally demonstrated for on-chip mode-division multiplexing (MDM) optical interconnects. The MSS consists of a Mach-Zehnder interferometer with tapered multi-mode interference couplers and TiN thermo-optic phase shifters for conversion and switching between the optical data encoded on the fundamental and first-order quasi-transverse electric (TE) modes. The C-band MSS exhibits a >25  dB switching extinction ratio and < -12 dB crosstalk. We validate the dynamic switching with a 25.8 kHz gating signal measuring switching times for both TE0 and TE1 modes of <10.9  μs. All channels exhibit less than 1.7 dB power penalty at a 10 -12 bit error rate, while switching the non-return-to-zero PRBS-31 data signals at 10  Gb/s.

Semiconductor lasers for versatile applications from global communications to on-chip interconnects

NASA Astrophysics Data System (ADS)

Arai, Shigehisa

2015-01-01

Since semiconductor lasers were realized in 1962, various efforts have been made to enrich human life thorough novel equipments and services. Among them optical fiber communications in global communications have brought out marvelous information technology age represented by the internet. In this paper, emerging topics made on GaInAsP/InP based long-wavelength lasers toward ultra-low power consumption semiconductor lasers for optical interconnects in supercomputers as well as in future LSIs are presented.

Research on Optical Transmitter and Receiver Module Used for High-Speed Interconnection between CPU and Memory

NASA Astrophysics Data System (ADS)

He, Huimin; Liu, Fengman; Li, Baoxia; Xue, Haiyun; Wang, Haidong; Qiu, Delong; Zhou, Yunyan; Cao, Liqiang

2016-11-01

With the development of the multicore processor, the bandwidth and capacity of the memory, rather than the memory area, are the key factors in server performance. At present, however, the new architectures, such as fully buffered DIMM (FBDIMM), hybrid memory cube (HMC), and high bandwidth memory (HBM), cannot be commercially applied in the server. Therefore, a new architecture for the server is proposed. CPU and memory are separated onto different boards, and optical interconnection is used for the communication between them. Each optical module corresponds to each dual inline memory module (DIMM) with 64 channels. Compared to the previous technology, not only can the architecture realize high-capacity and wide-bandwidth memory, it also can reduce power consumption and cost, and be compatible with the existing dynamic random access memory (DRAM). In this article, the proposed module with system-in-package (SiP) integration is demonstrated. In the optical module, the silicon photonic chip is included, which is a promising technology to be applied in the next-generation data exchanging centers. And due to the bandwidth-distance performance of the optical interconnection, SerDes chips are introduced to convert the 64-bit data at 800 Mbps from/to 4-channel data at 12.8 Gbps after/before they are transmitted though optical fiber. All the devices are packaged on cheap organic substrates. To ensure the performance of the whole system, several optimization efforts have been performed on the two modules. High-speed interconnection traces have been designed and simulated with electromagnetic simulation software. Steady-state thermal characteristics of the transceiver module have been evaluated by ANSYS APLD based on finite-element methodology (FEM). Heat sinks are placed at the hotspot area to ensure the reliability of all working chips. Finally, this transceiver system based on silicon photonics is measured, and the eye diagrams of data and clock signals are verified.

Attachment method for stacked integrated circuit (IC) chips

DOEpatents

Bernhardt, Anthony F.; Malba, Vincent

1999-01-01

An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM.

Fabrication of Quench Condensed Thin Films Using an Integrated MEMS Fab on a Chip

NASA Astrophysics Data System (ADS)

Lally, Richard; Reeves, Jeremy; Stark, Thomas; Barrett, Lawrence; Bishop, David

Atomic calligraphy is a microelectromechanical systems (MEMS)-based dynamic stencil nanolithography technique. Integrating MEMS devices into a bonded stacked array of three die provides a unique platform for conducting quench condensed thin film mesoscopic experiments. The atomic calligraphy Fab on a Chip process incorporates metal film sources, electrostatic comb driven stencil plate, mass sensor, temperature sensor, and target surface into one multi-die assembly. Three separate die are created using the PolyMUMPs process and are flip-chip bonded together. A die containing joule heated sources must be prepared with metal for evaporation prior to assembly. A backside etch of the middle/central die exposes the moveable stencil plate allowing the flux to pass through the stencil from the source die to the target die. The chip assembly is mounted in a cryogenic system at ultra-high vacuum for depositing extremely thin films down to single layers of atoms across targeted electrodes. Experiments such as the effect of thin film alloys or added impurities on their superconductivity can be measured in situ with this process.

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2015-01-01

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

A Highly Functional Decision Paradigm Based on Nonlinear Adaptive Genetic Algorithm

DTIC Science & Technology

1997-10-07

significant speedup. p£ lC <$jALTnimm SCTED & 14. SUBJECT TERMS Network Topology Optimization, Mathlink, Mathematica Plug-In, GA Route Optimizer, DSP...operations per second 2.4 Gbytes/second sustainable on-chip data transfer rate 400 Mb/s off-chip peak transfer rate Layer-to-layer interconnection...SecondHighestDist# = DistanceArray%(IndexList%(ChromeGene%(i%, 1) -1), IndexList%( Chrom eGene%(i%, 2) - 1)) For j% = 1 To StrandLength% - 1 ’If highest distance

Chip-To-Chip Optical Interconnection Using MEMS Mirrors

DTIC Science & Technology

2009-03-26

the Figure 2.3: SEM of a 2D micromirror with embedded polysilicon circuit paths within the frame structures which drives individual thermal actuation...single-crystal silicon micromirror for large bi-directional 2d scanning applications,” Sens. and Actuators, A, vol. 130-131, pp. 454–460, 8/14 2006. 14...thesis (m.s.), AFIT, Mar 2008. AFIT/GEO/ENP/08-03. 17. B. McCarthy, V. M. Bright, and J. A. Neff, “A multi-component solder self- assembled micromirror

Hybrid-integrated coherent receiver using silica-based planar lightwave circuit technology

NASA Astrophysics Data System (ADS)

Kim, Jong-Hoi; Choe, Joong-Seon; Choi, Kwang-Seong; Youn, Chun-Ju; Kim, Duk-Jun; Jang, Sun-Hyok; Kwon, Yong-Hwan; Nam, Eun-Soo

2011-12-01

A hybrid-integrated coherent receiver module has been achieved using flip-chip bonding technology, consisting of a silica-based 90°-hybrid planar lightwave circuit (PLC) platform, a spot-size converter integrated waveguide photodiode (SSC-WG-PD), and a dual-channel transimpedance amplifier (TIA). The receiver module shows error-free operation up to 40Gb/s and OSNR sensitivity of 11.5 dB for BER = 10-3 at 25 Gb/s.

Identification of Bacterial Factors Involved in Type 1 Fimbria Expression using an Escherichia coli K12 Proteome Chip*

PubMed Central

Chen, Yi-Wen; Teng, Ching-Hao; Ho, Yu-Hsuan; Jessica Ho, Tien Yu; Huang, Wen-Chun; Hashimoto, Masayuki; Chiang, I-Yuan; Chen, Chien-Sheng

2014-01-01

Type 1 fimbriae are filamentous structures on Escherichia coli. These structures are important adherence factors. Because binding to the host cells is the first step of infection, type 1 fimbria is an important virulence factor of pathogenic E. coli. Expression of type 1 fimbria is regulated by a phase variation in which each individual bacterium can alternate between fimbriated (phase-ON) and nonfimbriated (phase-OFF) states. The phase variation is regulated by the flipping of the 314-bp fimS fragment, which contains the promoter driving the expression of the genes required for the synthesis of type 1 fimbria. Thus, the bacterial proteins able to interact with fimS are likely to be involved in regulating the expression of type 1 fimbria. To identify novel type 1 fimbria-regulating factors, we used an E. coli K12 proteome chip to screen for the bacterial factors able to interact with a 602-bp DNA fragment containing fimS and its adjacent regions. The Spr protein was identified by the proteome chip-based screening and further confirmed to be able to interact with fimS by electrophoretic mobility shift assay. Deletion of spr in the neonatal meningitis E. coli strain RS218 significantly increased the ratio of the bacterial colonies that contained the type 1 fimbria phase-ON cells on agar plates. In addition, Spr interfered with the interactions of fimS with the site-specific recombinases, FimB and FimE, which are responsible for mediating the flipping of fimS. These results suggest that Spr is involved in the regulation of type 1 fimbria expression through direct interaction with the invertible element fimS. These findings facilitate our understanding of the regulation of type 1 fimbria. PMID:24692643

Attachment method for stacked integrated circuit (IC) chips

DOEpatents

Bernhardt, A.F.; Malba, V.

1999-08-03

An attachment method for stacked integrated circuit (IC) chips is disclosed. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM. 12 figs.

Realization of optical multimode TSV waveguides for Si-Interposer in 3D-chip-stacks

NASA Astrophysics Data System (ADS)

Killge, S.; Charania, S.; Richter, K.; Neumann, N.; Al-Husseini, Z.; Plettemeier, D.; Bartha, J. W.

2017-05-01

Optical connectivity has the potential to outperform copper-based TSVs in terms of bandwidth at the cost of more complexity due to the required electro-optical and opto-electrical conversion. The continuously increasing demand for higher bandwidth pushes the breakeven point for a profitable operation to shorter distances. To integrate an optical communication network in a 3D-chip-stack optical through-silicon vertical VIAs (TSV) are required. While the necessary effort for the electrical/optical and vice versa conversion makes it hard to envision an on-chip optical interconnect, a chip-to-chip optical link appears practicable. In general, the interposer offers the potential advantage to realize electro-optical transceivers on affordable expense by specific, but not necessarily CMOS technology. We investigated the realization and characterization of optical interconnects as a polymer based waveguide in high aspect ratio (HAR) TSVs proved on waferlevel. To guide the optical field inside a TSV as optical-waveguide or fiber, its core has to have a higher refractive index than the surrounding material. Comparing different material / technology options it turned out that thermal grown silicon dioxide (SiO2) is a perfect candidate for the cladding (nSiO2 = 1.4525 at 850 nm). In combination with SiO2 as the adjacent polymer layer, the negative resist SU-8 is very well suited as waveguide material (nSU-8 = 1.56) for the core. Here, we present the fabrication of an optical polymer based multimode waveguide in TSVs proved on waferlevel using SU-8 as core and SiO2 as cladding. The process resulted in a defect-free filling of waveguide TSVs with SU-8 core and SiO2 cladding up to aspect ratio (AR) 20:1 and losses less than 3 dB.

Novel optical interconnect devices and coupling methods applying self-written waveguide technology

NASA Astrophysics Data System (ADS)

Nakama, Kenichi; Mikami, Osamu

2011-05-01

For the use in cost-effective optical interconnection of opt-electronic printed wiring boards (OE-PWBs), we have developed novel optical interconnect devices and coupling methods simplifying board to board optical interconnect. All these are based on the self-written waveguide (SWW) technology by the mask-transfer method with light-curable resin. This method enables fabrication of arrayed M × N optical channels at one shot of UV light. Very precise patterns, as an example, optical rod with diameters of 50μm to 500μm, can be easily fabricated. The length of the fabricated patterns ,, typically up to about 1000μm , can be controlled by a spacer placed between the photomask and the substrate. Using these technologies, several new optical interfaces have been demonstrated. These are a chip VCSEL with an optical output rod and new coupling methods of "plug-in" alignment and "optical socket" based on SWW.

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2015-01-01

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

Dose-dependent X-ray measurements using a 64×64 hybrid GaAs pixel detector with photon counting

NASA Astrophysics Data System (ADS)

Schwarz, C.; Campbell, M.; Goeppert, R.; Ludwig, J.; Mikulec, B.; Rogalla, M.; Runge, K.; Soeldner-Rembold, A.; Smith, K. M.; Snoeys, W.; Watt, J.

2001-03-01

New developments in medical imaging head towards semiconductor detectors flip-chip bonded to CMOS readout chips. In this work, detectors fabricated on SI-GaAs bulk material were bonded to Photon Counting Chips. This PCC consists of a matrix of 64×64 identical square pixels (170 μm×170 μm) with a 15-bit counter in each cell. We investigated the imaging properties of these detector systems under exposure of a dental X-ray tube. First, a dose calibration of the X-ray tube was performed. Fixed pattern noise in flood exposure images was determined for a fixed dose and an image correction method, which uses a gain map, was applied. For characterising the imaging properties, the signal-to-noise ratio (SNR) was calculated as function of exposure dose. Finally, the dynamic range of the system was estimated. Developed in the framework of the MEDIPIX collaboration: CERN, Universities of Freiburg, Glasgow, Naples and Pisa.

Development of non-destructive evaluation system using an HTS-SQUID gradiometer for magnetized materials

NASA Astrophysics Data System (ADS)

Kawano, J.; Tsukamoto, A.; Adachi, S.; Oshikubo, Y.; Hato, T.; Tanabe, K.; Okamura, T.

We have developed a new eddy-current non-destructive evaluation (NDE) system using an HTS SQUID gradiometer with the aim of applying it to practical materials with magnetization. The new NDE system employs a LN2-cooled external Cu pickup coil and an HTS SQUID chip placed in a magnetic shield made of HTS material. The HTS SQUID chip consists of an HTS planar gradiometer manufactured by using a ramp-edge junction technology and a multi-turn HTS thin film input coil coupled with the flip-chip configuration. The first-order coaxial gradiometric Cu pickup coil with a diameter of 16 mm and the baseline of 5.6 mm was used in the present NDE experiments. By using this NDE system, we could observe defect-induced magnetic signals without an appreciable influence of magnetization up to 10 mT. We also examined the ability of detecting deep-lying defects and compared with the results obtained using our previous NDE system.

Multimode fiber for high-density optical interconnects

NASA Astrophysics Data System (ADS)

Bickham, Scott R.; Ripumaree, Radawan; Chalk, Julie A.; Paap, Mark T.; Hurley, William C.; McClure, Randy L.

2017-02-01

Data centers (DCs) are facing the challenge of delivering more capacity over longer distances. As line rates increase to 25 Gb/s and higher, DCs are being challenged with signal integrity issues due to the long electrical traces that require retiming. In addition, the density of interconnects on the front panel is limited by the size and power dissipation requirements of the pluggable modules. One proposal to overcome these issues is to use embedded optical transceivers in which optical fibers are used to transport data to and from the front panel. These embedded modules will utilize arrays of VCSEL or silicon-photonic transceivers, and in both cases, the capacity may be limited by the density of the optical connections on the chip. To address this constraint, we have prototyped optical fibers in which the glass and coating diameters are reduced to 80 and 125 microns, respectively. These smaller diameters enable twice as many optical interconnects in the same footprint, and this in turn will allow the transceiver arrays to be collinearly located on small chips with dimensions on the order of (5x5mm2)1,2. We have also incorporated these reduced diameter fibers into small, flexible 8-fiber ribbon cables which can simplify routing constraints inside modules and optical backplanes.

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

PubMed

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

Statistical metrology—measurement and modeling of variation for advanced process development and design rule generation

NASA Astrophysics Data System (ADS)

Boning, Duane S.; Chung, James E.

1998-11-01

Advanced process technology will require more detailed understanding and tighter control of variation in devices and interconnects. The purpose of statistical metrology is to provide methods to measure and characterize variation, to model systematic and random components of that variation, and to understand the impact of variation on both yield and performance of advanced circuits. Of particular concern are spatial or pattern-dependencies within individual chips; such systematic variation within the chip can have a much larger impact on performance than wafer-level random variation. Statistical metrology methods will play an important role in the creation of design rules for advanced technologies. For example, a key issue in multilayer interconnect is the uniformity of interlevel dielectric (ILD) thickness within the chip. For the case of ILD thickness, we describe phases of statistical metrology development and application to understanding and modeling thickness variation arising from chemical-mechanical polishing (CMP). These phases include screening experiments including design of test structures and test masks to gather electrical or optical data, techniques for statistical decomposition and analysis of the data, and approaches to calibrating empirical and physical variation models. These models can be integrated with circuit CAD tools to evaluate different process integration or design rule strategies. One focus for the generation of interconnect design rules are guidelines for the use of "dummy fill" or "metal fill" to improve the uniformity of underlying metal density and thus improve the uniformity of oxide thickness within the die. Trade-offs that can be evaluated via statistical metrology include the improvements to uniformity possible versus the effect of increased capacitance due to additional metal.

Innovative materials tailored for advanced micro-optic applications

NASA Astrophysics Data System (ADS)

Himmelhuber, Roland; Fink, Marion; Pfeiffer, Karl; Ostrzinski, Ute; Klukowska, Anna; Gruetzner, Gabi; Houbertz, Ruth; Wolter, Herbert

2007-02-01

The handling of a continuously increasing amount of data leads to a strong need for high-speed short-range connections. Conventional Cu technology between chips on a board is limited. Optical interconnects will dominate the market, since they can overcome the limitations. One of the issues for materials used, e.g., for waveguides embedded in printed circuit boards (PCBs) is the compatibility with standard epoxies used for PCBs during the entire board fabrication process. Materials applied for optical interconnects should be mechanically and optically reliable, and also allow low-cost production. From the material production side, the process should be easy to up-scale. Therefore, anticipatory research strategy and suitable tailoring is asked for. The handling of light in the UV and visible range often requires the use of specially designed materials. Most polymer materials show an increased yellowing effect upon being exposed to shorter wavelength light. The major influence on the absorption in the UV and visible range of a UV curable material is related to the UV initiator, beside any other chromophores formed mainly during the exposure. Different material approaches will be presented which fulfil the requirements for highly sophisticated applications in optics / optical packaging technology. Firstly, an epoxy-based material system for optical chip-to-chip interconnection will be introduced. Secondly, the adaptation of a UV patternable inorganic-organic hybrid material (ORMOCER ®) originally developed for waveguide applications in the data and telecom regime, will be discussed with respect to applications in the visible regime. Spectroscopy and UV-DSC measurements were carried out to investigate the influence of standard photoinitiators on the optical properties for an ORMOCER ® system suitable for microoptic applications. The results show that the resulting material properties were significantly improved by exchange of the initiators compared to the originally incorporated one.

Phase Equilibria of the Sn-Ni-Si Ternary System and Interfacial Reactions in Sn-(Cu)/Ni-Si Couples

NASA Astrophysics Data System (ADS)

Fang, Gu; Chen, Chih-chi

2015-07-01

Interfacial reactions in Sn/Ni-4.5 wt.%Si and Sn-Cu/Ni-4.5 wt.%Si couples at 250°C, and Sn-Ni-Si ternary phase equilibria at 250°C were investigated in this study. Ni-Si alloys, which are nonmagnetic, can be regarded as a diffusion barrier layer material in flip chip packaging. Solder/Ni-4.5 wt.%Si interfacial reactions are crucial to the reliability of soldered joints. Phase equilibria information is essential for development of solder/Ni-Si materials. No ternary compound is present in the Sn-Ni-Si ternary system at 250°C. Extended solubility of Si in the phases Ni3Sn2 and Ni3Sn is 3.8 and 6.1 at.%, respectively. As more Si dissolves in these phases their lattice constants decrease. No noticeable ternary solubility is observed for the other intermetallics. Interfacial reactions in solder/Ni-4.5 wt.%Si are similar to those for solder/Ni. Si does not alter the reaction phases. No Si solubility in the reaction phases was detected, although rates of growth of the reaction phases were reduced. Because the alloy Ni-4.5 wt.%Si reacts more slowly with solders than pure Ni, the Ni-4.5 wt.%Si alloy could be a potential new diffusion barrier layer material for flip chip packaging.

White thin-film flip-chip LEDs with uniform color temperature using laser lift-off and conformal phosphor coating technologies.

PubMed

Lin, Huan-Ting; Tien, Ching-Ho; Hsu, Chen-Peng; Horng, Ray-Hua

2014-12-29

We fabricated a phosphor-conversion white light emitting diode (PC-WLED) using a thin-film flip-chip GaN LED with a roughened u-GaN surface (TFFC-SR-LED) that emits blue light at 450 nm wavelength with a conformal phosphor coating that converts the blue light into yellow light. It was found that the TFFC-SR-LED with the thin-film substrate removal process and surface roughening exhibits a power enhancement of 16.1% when compared with the TFFC-LED without a sapphire substrate. When a TFFC-SR-LED with phosphors on a Cu-metal packaging-base (TFFC-SR-Cu-WLED) was operated at a forward-bias current of 350 mA, luminous flux and luminous efficacy were increased by 17.8 and 11.9%, compared to a TFFC-SR-LED on a Cup-shaped packaging-base (TFFC-SR-Cup-WLED). The angular correlated color temperature (CCT) deviation of a TFFC-SR-Cu-WLED reaches 77 K in the range of -70° to + 70° when the average CCT of white LEDs is around 4300 K. Consequently, the TFFC-SR-LED in a conformal coating phosphor structure on a Cu packaging-base could not only increase the luminous flux output, but also improve the angular-dependent CCT uniformity, thereby reducing the yellow ring effect.

40-Gb/s directly-modulated photonic crystal lasers under optical injection-locking

NASA Astrophysics Data System (ADS)

Chen, Chin-Hui; Takeda, Koji; Shinya, Akihiko; Nozaki, Kengo; Sato, Tomonari; Kawaguchi, Yoshihiro; Notomi, Masaya; Matsuo, Shinji

2011-08-01

CMOS integrated circuits (IC) usually requires high data bandwidth for off-chip input/output (I/O) data transport with sufficiently low power consumption in order to overcome pin-count limitation. In order to meet future requirements of photonic network interconnect, we propose an optical output device based on an optical injection-locked photonic crystal (PhC) laser to realize low-power and high-speed off-chip interconnects. This device enables ultralow-power operation and is suitable for highly integrated photonic circuits because of its strong light-matter interaction in the PhC nanocavity and ultra-compact size. High-speed operation is achieved by using the optical injection-locking (OIL) technique, which has been shown as an effective means to enhance modulation bandwidth beyond the relaxation resonance frequency limit. In this paper, we report experimental results of the OIL-PhC laser under various injection conditions and also demonstrate 40-Gb/s large-signal direct modulation with an ultralow energy consumption of 6.6 fJ/bit.

Application of quantum-dot multi-wavelength lasers and silicon photonic ring resonators to data-center optical interconnects

NASA Astrophysics Data System (ADS)

Beckett, Douglas J. S.; Hickey, Ryan; Logan, Dylan F.; Knights, Andrew P.; Chen, Rong; Cao, Bin; Wheeldon, Jeffery F.

2018-02-01

Quantum dot comb sources integrated with silicon photonic ring-resonator filters and modulators enable the realization of optical sub-components and modules for both inter- and intra-data-center applications. Low-noise, multi-wavelength, single-chip, laser sources, PAM4 modulation and direct detection allow a practical, scalable, architecture for applications beyond 400 Gb/s. Multi-wavelength, single-chip light sources are essential for reducing power dissipation, space and cost, while silicon photonic ring resonators offer high-performance with space and power efficiency.

Integrated Microfluidic Gas Sensors for Water Monitoring

NASA Technical Reports Server (NTRS)

Zhu, L.; Sniadecki, N.; DeVoe, D. L.; Beamesderfer, M.; Semancik, S.; DeVoe, D. L.

2003-01-01

A silicon-based microhotplate tin oxide (SnO2) gas sensor integrated into a polymer-based microfluidic system for monitoring of contaminants in water systems is presented. This device is designed to sample a water source, control the sample vapor pressure within a microchannel using integrated resistive heaters, and direct the vapor past the integrated gas sensor for analysis. The sensor platform takes advantage of novel technology allowing direct integration of discrete silicon chips into a larger polymer microfluidic substrate, including seamless fluidic and electrical interconnects between the substrate and silicon chip.

Real-Time Reed-Solomon Decoder

NASA Technical Reports Server (NTRS)

Maki, Gary K.; Cameron, Kelly B.; Owsley, Patrick A.

1994-01-01

Generic Reed-Solomon decoder fast enough to correct errors in real time in practical applications designed to be implemented in fewer and smaller very-large-scale integrated, VLSI, circuit chips. Configured to operate in pipelined manner. One outstanding aspect of decoder design is that Euclid multiplier and divider modules contain Galoisfield multipliers configured as combinational-logic cells. Operates at speeds greater than older multipliers. Cellular configuration highly regular and requires little interconnection area, making it ideal for implementation in extraordinarily dense VLSI circuitry. Flight electronics single chip version of this technology implemented and available.

Insulator photocurrents: Application to dose rate hardening of CMOS/SOI integrated circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dupont-Nivet, E.; Coiec, Y.M.; Flament, O.

1998-06-01

Irradiation of insulators with a pulse of high energy x-rays can induce photocurrents in the interconnections of integrated circuits. The authors present, here, a new method to measure and analyze this effect together with a simple model. They also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. They show that it explains some of the upsets observed in a SRAM embedded in an ASIC.

Misalignment corrections in optical interconnects

NASA Astrophysics Data System (ADS)

Song, Deqiang

Optical interconnects are considered a promising solution for long distance and high bitrate data transmissions, outperforming electrical interconnects in terms of loss and dispersion. Due to the bandwidth and distance advantage of optical interconnects, longer links have been implemented with optics. Recent studies show that optical interconnects have clear advantages even at very short distances---intra system interconnects. The biggest challenge for such optical interconnects is the alignment tolerance. Many free space optical components require very precise assembly and installation, and therefore the overall cost could be increased. This thesis studied the misalignment tolerance and possible alignment correction solutions for optical interconnects at backplane or board level. First the alignment tolerance for free space couplers was simulated and the result indicated the most critical alignments occur between the VCSEL, waveguide and microlens arrays. An in-situ microlens array fabrication method was designed and experimentally demonstrated, with no observable misalignment with the waveguide array. At the receiver side, conical lens arrays were proposed to replace simple microlens arrays for a larger angular alignment tolerance. Multilayer simulation models in CodeV were built to optimized the refractive index and shape profiles of the conical lens arrays. Conical lenses fabricated with micro injection molding machine and fiber etching were characterized. Active component VCSOA was used to correct misalignment in optical connectors between the board and backplane. The alignment correction capability were characterized for both DC and AC (1GHz) optical signal. The speed and bandwidth of the VCSOA was measured and compared with a same structure VCSEL. Based on the optical inverter being studied in our lab, an all-optical flip-flop was demonstrated using a pair of VCSOAs. This memory cell with random access ability can store one bit optical signal with set or reset beam. The operating conditions were studied to generate two stable states between the VCSOA pair. The entire functionality test was implemented with free space optical components.

Modular cryogenic interconnects for multi-qubit devices.

PubMed

Colless, J I; Reilly, D J

2014-11-01

We have developed a modular interconnect platform for the control and readout of multiple solid-state qubits at cryogenic temperatures. The setup provides 74 filtered dc-bias connections, 32 control and readout connections with -3 dB frequency above 5 GHz, and 4 microwave feed lines that allow low loss (less than 3 dB) transmission 10 GHz. The incorporation of a radio-frequency interposer enables the platform to be separated into two printed circuit boards, decoupling the simple board that is bonded to the qubit chip from the multilayer board that incorporates expensive connectors and components. This modular approach lifts the burden of duplicating complex interconnect circuits for every prototype device. We report the performance of this platform at milli-Kelvin temperatures, including signal transmission and crosstalk measurements.

Chip-to-chip SnO2 nanowire network sensors for room temperature H2 detection

NASA Astrophysics Data System (ADS)

Köck, A.; Brunet, E.; Mutinati, G. C.; Maier, T.; Steinhauer, S.

2012-06-01

The employment of nanowires is a very powerful strategy to improve gas sensor performance. We demonstrate a gas sensor device, which is based on silicon chip-to-chip synthesis of ultralong tin oxide (SnO2) nanowires. The sensor device employs an interconnected SnO2 nanowire network configuration, which exhibits a huge surface-to-volume ratio and provides full access of the target gas to the nanowires. The chip-to-chip SnO2 nanowire device is able to detect a H2 concentration of only 20 ppm in synthetic air with ~ 60% relative humidity at room temperature. At an operating temperature of 300°C a concentration of 50 ppm H2 results in a sensitivity of 5%. At this elevated temperature the sensor shows a linear response in a concentration range between 10 ppm and 100 ppm H2. The SnO2-nanowire fabrication procedure based on spray pyrolysis and subsequent annealing is performed at atmospheric pressure, requires no vacuum and allows upscale of the substrate to a wafer size. 3D-integration with CMOS chips is proposed as viable way for practical realization of smart nanowire based gas sensor devices for the consumer market.

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

1989-01-01

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

High-Temperature High-Power Packaging Techniques for HEV Traction Applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Elshabini, Aicha; Barlow, Fred D.

A key issue associated with the wider adoption of hybrid-electric vehicles (HEV) and plug in hybrid-electric vehicles (PHEV) is the implementation of the power electronic systems that are required in these products. One of the primary industry goals is the reduction in the price of these vehicles relative to the cost of traditional gasoline powered vehicles. Today these systems, such as the Prius, utilize one coolant loop for the engine at approximately 100 C coolant temperatures, and a second coolant loop for the inverter at 65 C. One way in which significant cost reduction of these systems could be achievedmore » is through the use of a single coolant loop for both the power electronics as well as the internal combustion engine (ICE). This change in coolant temperature significantly increases the junction temperatures of the devices and creates a number of challenges for both device fabrication and the assembly of these devices into inverters and converters for HEV and PHEV applications. Traditional power modules and the state-of-the-art inverters in the current HEV products, are based on chip and wire assembly and direct bond copper (DBC) on ceramic substrates. While a shift to silicon carbide (SiC) devices from silicon (Si) devices would allow the higher operating temperatures required for a single coolant loop, it also creates a number of challenges for the assembly of these devices into power inverters. While this traditional packaging technology can be extended to higher temperatures, the key issues are the substrate material and conductor stability, die bonding material, wire bonds, and bond metallurgy reliability as well as encapsulation materials that are stable at high operating temperatures. The larger temperature differential during power cycling, which would be created by higher coolant temperatures, places tremendous stress on traditional aluminum wire bonds that are used to interconnect power devices. Selection of the bond metallurgy and wire bond geometry can play a key role in mitigating this stress. An alternative solution would be to eliminate the wire bonds completely through a fundamentally different method of forming a reliable top side interconnect. Similarly, the solders used in most power modules exhibit too low of a liquidus to be viable solutions for maximum junction temperatures of 200 C. Commonly used encapsulation materials, such as silicone gels, also suffer from an inability to operate at 200 C for extended periods of time. Possible solutions to these problems exist in most cases but require changes to the traditional manufacturing process used in these modules. In addition, a number of emerging technologies such as Si nitride, flip-chip assembly methods, and the elimination of base-plates would allow reliable module development for operation of HEV and PHEV inverters at elevated junction temperatures.« less

Prototype readout electronics and silicon strip detector study for the silicon tracking system at compressed baryonic matter experiment

NASA Astrophysics Data System (ADS)

Kasiński, Krzysztof; Szczygieł, Robert; Gryboś, Paweł

2011-10-01

This paper presents the prototype detector readout electronics for the STS (Silicon Tracking System) at CBM (Compressed Baryonic Matter) experiment at FAIR, GSI (Helmholtzzentrum fuer Schwerionenforschung GmbH) in Germany. The emphasis has been put on the strip detector readout chip and its interconnectivity with detector. Paper discusses the impact of the silicon strip detector and interconnection cable construction on the overall noise of the system and architecture of the TOT02 readout ASIC. The idea and problems of the double-sided silicon detector usage are also presented.

Pressure driven digital logic in PDMS based microfluidic devices fabricated by multilayer soft lithography.

PubMed

Devaraju, Naga Sai Gopi K; Unger, Marc A

2012-11-21

Advances in microfluidics now allow an unprecedented level of parallelization and integration of biochemical reactions. However, one challenge still faced by the field has been the complexity and cost of the control hardware: one external pressure signal has been required for each independently actuated set of valves on chip. Using a simple post-modification to the multilayer soft lithography fabrication process, we present a new implementation of digital fluidic logic fully analogous to electronic logic with significant performance advances over the previous implementations. We demonstrate a novel normally closed static gain valve capable of modulating pressure signals in a fashion analogous to an electronic transistor. We utilize these valves to build complex fluidic logic circuits capable of arbitrary control of flows by processing binary input signals (pressure (1) and atmosphere (0)). We demonstrate logic gates and devices including NOT, NAND and NOR gates, bi-stable flip-flops, gated flip-flops (latches), oscillators, self-driven peristaltic pumps, delay flip-flops, and a 12-bit shift register built using static gain valves. This fluidic logic shows cascade-ability, feedback, programmability, bi-stability, and autonomous control capability. This implementation of fluidic logic yields significantly smaller devices, higher clock rates, simple designs, easy fabrication, and integration into MSL microfluidics.

Consortia for Known Good Die (KGD), phase 1

NASA Astrophysics Data System (ADS)

Andrews, Marshall; Carey, David; Fellows, Mary M.; Gilg, Larry; Murphy, Cindy; Noddings, Chad; Pitts, Greg; Rathmell, Claude; Spooner, Charles

1994-02-01

This report describes the results of Phase 1 of the Infrastructure for KGD program at MCC. The objective of the work is to resolve the issues for supplying and procuring Known Good Die (KGD) in a way that fosters industry acceptance and confidence in Application Specific Electronic Modules (ASEM's for military systems) and MultiChip Modules (MCM's for commercial systems). This report is divided into four sections. Section 1 describes the technical assessment of proposed industry approaches to KGD implementation. Section 2 of the report contains an outline for the plan for industry and government cooperation for the demonstration, validation, and implementation of KGD methodologies identified in this Phase 1 study. Section 3 of the report contains the industry-generated requirements for KGD implementation. Section IV of the report contains the KGD specifications for TAB and flip chip IC's.

Intra-Chip Free-Space Optical Interconnect: System, Device, Integration and Prototyping

NASA Astrophysics Data System (ADS)

Ciftcioglu, Berkehan

Currently, on-chip optical interconnect schemes already proposed utilize circuit switching using wavelength division multiplexing (WDM) or all-optical packet switching, all based on planar optical waveguides and related photonic devices such as microrings. These proposed approaches pose significant challenges in latency, energy efficiency, integration, and scalability. This thesis presents a new alternative approach by utilizing free-space optics. This 3-D integrated intra-chip free-space optical interconnect (FSOI) leverages mature photonic devices such as integrated lasers, photodiodes, microlenses and mirrors. It takes full advantages of the latest developments in 3-D integration technologies. This interconnect system provides point-to-point free-space optical links between any two communication nodes to construct an all-to-all intra-chip communication network with little or no arbitration. Therefore, it has significant networking advantages over conventional electrical and waveguide-based optical interconnects. An FSOI system is evaluated based on the real device parameters, predictive technology models and International Roadmap of Semiconductor's predictions. A single FSOI link achieves 10-Gbps data rate with 0.5-pJ/bit energy efficiency and less than 10--12 bit-error-rate (BER). A system using this individual link can provide scalability up to 36 nodes, providing 10-Tbps aggregate bandwidth. A comparison analysis performed between a WDM-based waveguide interconnect system and the proposed FSOI system shows that FSOI achieves better energy efficiency than the WDM one as the technology scales. Similarly, network simulation on a 16-core microprocessor using the proposed FSOI system instead of mesh networks has been shown to speed up the system by 12% and reduce the energy consumption by 33%. As a part of the development of a 3-D integrated FSOI system, operating at 850 nm with a 10-Gbps data rate per optical link, the photonics devices and optical components are individually designed and fabricated. The photodiodes (PDs) are designed to have large area for efficient light coupling and low capacitance to achieve large bandwidth, while achieving reasonably high responsivity. A metal-semiconductor-metal (MSM) structure is chosen over p-i-n ones to reduce parasitic capacitance per area, to allow less stringent microlens-to-PD alignment for efficient light coupling with a large bandwidth. A novel MSM germanium PD is implemented using an amorphous silicon (a-Si) layer on top of the undoped germanium substrate, serving as a barrier enhancement layer, mitigating the low Schottky barrier height for holes due to fermi level pinning and a surface passivation layer, preventing charge accumulation and image force lowering of the barrier. Therefore, the dark current is reduced and low-frequency gain is eliminated. The PDs achieve a 13-GHz bandwidth with a 0.315-A/W responsivity and a 1.7-nAmum² dark current density. The microlenses are fabricated on a fused silica substrate based on the photoresist melt-and-reflow technique, followed by dry etching into fused silica substrate. The measured focal length of a 220-mum aperture size microlens is 350-mum away from the backside of the substrate. The vertical-cavity surface-emitting lasers (VCSELs) are fabricated on a commercial molecular beam epitaxially (MBE) grown GaAs wafer. The fabricated 8-mum aperture size VCSEL can achieve 0.65-mW optical power at a 1.5-mA forward bias current with a threshold current of 0.48 mA and a 0.67-A/W slope efficiency. Three prototypes are implemented via integrating the individually fabricated components using non-conductive epoxy and wirebonding. The first prototype, built on a printed circuit board (PCB) using commercial VCSEL arrays, achieves a 5-dB transmission loss and less than -30-dB crosstalk at 1-cm distance with a small-signal bandwidth of 10 GHz, limited by the VCSEL. The second board-level prototype uses all fabricated components integrated on a PCB. The prototype achieves a 9-dB transmission loss at 3-cm distance and a 4.4-GHz bandwidth. The chip-level prototype is built on a germanium carrier with integrated MSM Ge PDs, microlenses on fused silica and VCSEL chip on GaAs substrates. The prototype achieves 4-dB transmission loss at 1 cm and 3.3-GHz bandwidth, limited by commercial VCSEL bandwidth. (Abstract shortened by UMI.)

Optical interconnection using polyimide waveguide for multichip module

NASA Astrophysics Data System (ADS)

Koyanagi, Mitsumasa

1996-01-01

We have developed a parallel processor system with 152 RISC processor chips specific for Monte-Carlo analysis. This system has the ring-bus architecture. The performance of several Gflops is expected in this system according to the computer simulation. However, it was revealed that the data transfer speed of the bus has to be increased more dramatically in order to further increase the performance. Then, we propose to introduce the optical interconnection into the parallel processor system to increase the data transfer speed of the buses. The double ringbus architecture is employed in this new parallel processor system with optical interconnection. The free-space optical interconnection arid the optical waveguide are used for the optical ring-bus. Thin polyimide film was used to form the optical waveguide. A relatively low propagation loss was achieved in the polyimide optical waveguide. In addition, it was confirmed that the propagation direction of signal light can be easily changed by using a micro-mirror.

Optical interconnection using polyimide waveguide for multichip module

NASA Astrophysics Data System (ADS)

Koyanagi, Mitsumasa

1996-01-01

We have developed a parallel processor system with 152 RISC processor chips specific for Monte-Carlo analysis. This system has the ring-bus architecture. The performance of several Gflops is expected in this system according to the computer simulation. However, it was revealed that the data transfer speed of the bus has to be increased more dramatically in order to further increase the performance. Then, we propose to introduce the optical interconnection into the parallel processor system to increase the data transfer speed of the buses. The double ring-bus architecture is employed in this new parallel processor system with optical interconnection. The free-space optical interconnection and the optical waveguide are used for the optical ring-bus. Thin polyimide film was used to form the optical waveguide. A relatively low propagation loss was achieved in the polyimide optical waveguide. In addition, it was confirmed that the propagation direction of signal light can be easily changed by using a micro-mirror.

Gigascale Silicon Photonic Transmitters Integrating HBT-based Carrier-injection Electroabsorption Modulator Structures

NASA Astrophysics Data System (ADS)

Fu, Enjin

Demand for more bandwidth is rapidly increasing, which is driven by data intensive applications such as high-definition (HD) video streaming, cloud storage, and terascale computing applications. Next-generation high-performance computing systems require power efficient chip-to-chip and intra-chip interconnect yielding densities on the order of 1Tbps/cm2. The performance requirements of such system are the driving force behind the development of silicon integrated optical interconnect, providing a cost-effective solution for fully integrated optical interconnect systems on a single substrate. Compared to conventional electrical interconnect, optical interconnects have several advantages, including frequency independent insertion loss resulting in ultra wide bandwidth and link latency reduction. For high-speed optical transmitter modules, the optical modulator is a key component of the optical I/O channel. This thesis presents a silicon integrated optical transmitter module design based on a novel silicon HBT-based carrier injection electroabsorption modulator (EAM), which has the merits of wide optical bandwidth, high speed, low power, low drive voltage, small footprint, and high modulation efficiency. The structure, mechanism, and fabrication of the modulator structure will be discussed which is followed by the electrical modeling of the post-processed modulator device. The design and realization of a 10Gbps monolithic optical transmitter module integrating the driver circuit architecture and the HBT-based EAM device in a 130nm BiCMOS process is discussed. For high power efficiency, a 6Gbps ultra-low power driver IC implemented in a 130nm BiCMOS process is presented. The driver IC incorporates an integrated 27-1 pseudo-random bit sequence (PRBS) generator for reliable high-speed testing, and a driver circuit featuring digitally-tuned pre-emphasis signal strength. With outstanding drive capability, the driver module can be applied to a wide range of carrier injection modulators and light-emitting diodes (LED) with drive voltage requirements below 1.5V. Measurement results show an optical link based on a 70MHz red LED work well at 300Mbps by using the pre-emphasis driver module. A traveling wave electrode (TWE) modulator structure is presented, including a novel design methodology to address process limitations imposed by a commercial silicon fabrication technology. Results from 3D full wave EM simulation demonstrate the application of the design methodology to achieve specifications, including phase velocity matching, insertion loss, and impedance matching. Results show the HBT-based TWE-EAM system has the bandwidth higher than 60GHz.

GaN-based flip-chip LEDs with highly reflective ITO/DBR p-type and via hole-based n-type contacts for enhanced current spreading and light extraction

NASA Astrophysics Data System (ADS)

Zhou, Shengjun; Zheng, Chenju; Lv, Jiajiang; Gao, Yilin; Wang, Ruiqing; Liu, Sheng

2017-07-01

We demonstrate GaN-based double-layer electrode flip-chip light-emitting diodes (DLE-FCLED) with highly reflective indium-tin oxide (ITO)/distributed bragg reflector (DBR) p-type contact and via hole-based n-type contacts. Transparent thin ITO in combination with TiO2/SiO2 DBR is used for reflective p-type ohmic contact, resulting in a significant reduction in absorption of light by opaque metal electrodes. The finely distributed via hole-based n-type contacts are formed on the n-GaN layer by etching via holes through p-GaN and multiple quantum well (MQW) active layer, leading to reduced lateral current spreading length, and hence alleviated current crowding effect. The forward voltage of the DLE-FCLED is 0.31 V lower than that of the top-emitting LED at 90 mA. The light output power of DLE-FCLED is 15.7% and 80.8% higher than that of top-emitting LED at 90 mA and 300 mA, respectively. Compared to top- emitting LED, the external quantum efficiency (EQE) of DLE-FCLED is enhanced by 15.4% and 132% at 90 mA and 300 mA, respectively. The maximum light output power of the DLE-FCLED obtained at 195.6 A/cm2 is 1.33 times larger than that of the top-emitting LED obtained at 93 A/cm2.

Numerical and experimental investigation of GaN-based flip-chip light-emitting diodes with highly reflective Ag/TiW and ITO/DBR Ohmic contacts.

PubMed

Zhou, Shengjun; Liu, Xingtong; Gao, Yilin; Liu, Yingce; Liu, Mengling; Liu, Zongyuan; Gui, Chengqun; Liu, Sheng

2017-10-30

We demonstrate two types of GaN-based flip-chip light-emitting diodes (FCLEDs) with highly reflective Ag/TiW and indium-tin oxide (ITO)/distributed Bragg reflector (DBR) p-type Ohmic contacts. We show that a direct Ohmic contact to p-GaN layer using pure Ag is obtained when annealed at 600°C in N 2 ambient. A TiW diffusion barrier layer covered onto Ag is used to suppress the agglomeration of Ag and thus maintain high reflectance of Ag during high temperature annealing process. We develop a strip-shaped SiO 2 current blocking layer beneath the ITO/DBR to alleviate current crowding occurring in FCLED with ITO/DBR. Owing to negligibly small spreading resistance of Ag, however, our combined numerical and experimental results show that the FCLED with Ag/TiW has a more favorable current spreading uniformity in comparison to the FCLED with ITO/DBR. As a result, the light output power of FCLED with Ag/TiW is 7.5% higher than that of FCLED with ITO/DBR at 350 mA. The maximum output power of the FCLED with Ag/TiW obtained at 305.6 A/cm 2 is 29.3% larger than that of the FCLED with ITO/DBR obtained at 278.9 A/cm 2 . The improvement appears to be due to the enhanced current spreading and higher optical reflectance provided by the Ag/TiW.

Nanoantenna couplers for metal-insulator-metal waveguide interconnects

NASA Astrophysics Data System (ADS)

Onbasli, M. Cengiz; Okyay, Ali K.

2010-08-01

State-of-the-art copper interconnects suffer from increasing spatial power dissipation due to chip downscaling and RC delays reducing operation bandwidth. Wide bandwidth, minimized Ohmic loss, deep sub-wavelength confinement and high integration density are key features that make metal-insulator-metal waveguides (MIM) utilizing plasmonic modes attractive for applications in on-chip optical signal processing. Size-mismatch between two fundamental components (micron-size fibers and a few hundred nanometers wide waveguides) demands compact coupling methods for implementation of large scale on-chip optoelectronic device integration. Existing solutions use waveguide tapering, which requires more than 4λ-long taper distances. We demonstrate that nanoantennas can be integrated with MIM for enhancing coupling into MIM plasmonic modes. Two-dimensional finite-difference time domain simulations of antennawaveguide structures for TE and TM incident plane waves ranging from λ = 1300 to 1600 nm were done. The same MIM (100-nm-wide Ag/100-nm-wide SiO2/100-nm-wide Ag) was used for each case, while antenna dimensions were systematically varied. For nanoantennas disconnected from the MIM; field is strongly confined inside MIM-antenna gap region due to Fabry-Perot resonances. Major fraction of incident energy was not transferred into plasmonic modes. When the nanoantennas are connected to the MIM, stronger coupling is observed and E-field intensity at outer end of core is enhanced more than 70 times.

Electro-optical line cards with multimode polymer waveguides for chip-to-chip interconnects

NASA Astrophysics Data System (ADS)

Zhu, Long Xiu; Immonen, Marika; Wu, Jinhua; Yan, Hui Juan; Shi, Ruizhi; Chen, Peifeng; Rapala-Virtanen, Tarja

2014-10-01

In this paper, we report developments of electro-optical PCBs (EO-PCB) with low-loss (<0.05dB/cm) polymer waveguides. Our results shows successful fabrication of complex waveguide structures part of hybrid EO-PCBs utilizing production scale process on standard board panels. Test patterns include 90° bends of varying radii (40mm - 2mm), waveguide crossing with varied crossing angles (90°-20°), cascaded bends with varying radii, splitters and tapered waveguides. Full ranges of geometric configurations are required to meet practical optical routing functions and layouts. Moreover, we report results obtained to realize structures to integrate optical connectors with waveguides. Experimental results are shown for MT in-plane and 90° out-of-plane optical connectors realized with coupling loss < 2dB and < 2.5 dB, respectively. These connectors are crucial to realize efficient light coupling from/to TX/RX chip-to-waveguide and within waveguide-to-fiber connections in practical optical PCBs. Furthermore, we show results for fabricating electrical interconnect structures e.g. tracing layers, vias, plated vias top/bottom and through optical layers. Process compatibility with accepted practices and production scale up for high volumes are key concerns to meet the yield target and cost efficiency. Results include waveguide characterization, transmission loss, misalignment tolerance, and effect of lamination. Critical link metrics are reported.

A compact multi-bit flip-flop with smaller height implementation and metal-less intra-cell routing

NASA Astrophysics Data System (ADS)

Seo, Jaewoo; Jung, Jinwook; Shin, Youngsoo

2018-03-01

Multi-bit flip-ops (MBFFs) are widely used in modern circuit designs because of their lower power consumption and smaller footprint. However, conventional MBFFs have routability issues due to the dense intra-cell connections. Since many horizontal connections are populated in the typical MBFF layouts, metal-2 (M2) tracks are highly occupied inside the cell. Accordingly, routers cannot leverage the M2 tracks for inter-cell connections. The conventional MBFFs also show a limited impact on the cell area reduction. Since the cell area saving of an MBFF mainly comes from the clock driver sharing, the layouts of other ip-op modules remain almost the same. In this paper, we propose a compact MBFF with metal-less clock routing and smaller height implementation. To achieve a sparse population of M2 routing tracks, we vertically place MBFF modules and interconnect them using the poly layer. As a result, the wire length of M2 layer inside a cell is significantly reduced. We also propose the smaller cell height implementation for compact MBFF layouts. Assuming the default standard cell height of 9 tracks, we present a 6-track MBFF implementation and the glue logic which makes legal cell placement with the 9-track logic cells. Experiments with a few test circuits show that the number of routing grids having congestion overflow is reduced by 16% and 73%, on average, compared to the single-bit flip-op and conventional MBFF based designs, respectively. Total cell area is also reduced by 8% and 2%, on average, compared to the single-bit flip-op and conventional MBFF based designs, respectively.

Artificial brains. A million spiking-neuron integrated circuit with a scalable communication network and interface.

PubMed

Merolla, Paul A; Arthur, John V; Alvarez-Icaza, Rodrigo; Cassidy, Andrew S; Sawada, Jun; Akopyan, Filipp; Jackson, Bryan L; Imam, Nabil; Guo, Chen; Nakamura, Yutaka; Brezzo, Bernard; Vo, Ivan; Esser, Steven K; Appuswamy, Rathinakumar; Taba, Brian; Amir, Arnon; Flickner, Myron D; Risk, William P; Manohar, Rajit; Modha, Dharmendra S

2014-08-08

Inspired by the brain's structure, we have developed an efficient, scalable, and flexible non-von Neumann architecture that leverages contemporary silicon technology. To demonstrate, we built a 5.4-billion-transistor chip with 4096 neurosynaptic cores interconnected via an intrachip network that integrates 1 million programmable spiking neurons and 256 million configurable synapses. Chips can be tiled in two dimensions via an interchip communication interface, seamlessly scaling the architecture to a cortexlike sheet of arbitrary size. The architecture is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification. With 400-pixel-by-240-pixel video input at 30 frames per second, the chip consumes 63 milliwatts. Copyright © 2014, American Association for the Advancement of Science.

Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers.

PubMed

Carrillo, Snaider; Harkin, Jim; McDaid, Liam; Pande, Sandeep; Cawley, Seamus; McGinley, Brian; Morgan, Fearghal

2012-09-01

The brain is highly efficient in how it processes information and tolerates faults. Arguably, the basic processing units are neurons and synapses that are interconnected in a complex pattern. Computer scientists and engineers aim to harness this efficiency and build artificial neural systems that can emulate the key information processing principles of the brain. However, existing approaches cannot provide the dense interconnect for the billions of neurons and synapses that are required. Recently a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an efficient, robust computing platform. However, the use of the NoC as an interconnection fabric for large-scale SNNs demands a good trade-off between scalability, throughput, neuron/synapse ratio and power consumption. This paper presents a novel traffic-aware, adaptive NoC router, which forms part of a proposed embedded mixed-signal SNN architecture called EMBRACE (EMulating Biologically-inspiRed ArChitectures in hardwarE). The proposed adaptive NoC router provides the inter-neuron connectivity for EMBRACE, maintaining router communication and avoiding dropped router packets by adapting to router traffic congestion. Results are presented on throughput, power and area performance analysis of the adaptive router using a 90 nm CMOS technology which outperforms existing NoCs in this domain. The adaptive behaviour of the router is also verified on a Stratix II FPGA implementation of a 4 × 2 router array with real-time traffic congestion. The presented results demonstrate the feasibility of using the proposed adaptive NoC router within the EMBRACE architecture to realise large-scale SNNs on embedded hardware. Copyright © 2012 Elsevier Ltd. All rights reserved.

Electromigration Failure Mechanism in Sn-Cu Solder Alloys with OSP Cu Surface Finish

NASA Astrophysics Data System (ADS)

Chu, Ming-Hui; Liang, S. W.; Chen, Chih; Huang, Annie T.

2012-09-01

Organic solderable preservative (OSP) has been adopted as the Cu substrate surface finish in flip-chip solder joints for many years. In this study, the electromigration behavior of lead-free Sn-Cu solder alloys with thin-film under bump metallization and OSP surface finish was investigated. The results showed that severe damage occurred on the substrate side (cathode side), whereas the damage on the chip side (cathode side) was not severe. The damage on the substrate side included void formation, copper dissolution, and formation of intermetallic compounds (IMCs). The OSP Cu interface on the substrate side became the weakest point in the solder joint even when thin-film metallization was used on the chip side. Three-dimensional simulations were employed to investigate the current density distribution in the area between the OSP Cu surface finish and the solder. The results indicated that the current density was higher along the periphery of the bonding area between the solder and the Cu pad, consistent with the area of IMC and void formation in our experimental results.

Preparation of a YAG:Ce phosphor glass by screen-printing technology and its application in LED packaging.

PubMed

Yang, Liang; Chen, Mingxiang; Lv, Zhicheng; Wang, Simin; Liu, Xiaogang; Liu, Sheng

2013-07-01

A simple and practical method for preparing phosphor glass is proposed. Phosphor distribution and element analysis are investigated by optical microscope and field emission scanning electron microscope (FE-SEM). The phosphor particles dispersed in the matrix are vividly observed, and their distributions are uniform. Spectrum distribution and color coordinates dependent on the thickness of the screen-printed phosphor layer coupled with a blue light emitting diode (LED) chip are studied. The luminous efficacy of the 75 μm printed phosphor-layer phosphor glass packaged white LED is 81.24 lm/W at 350 mA. This study opens up many possibilities for applications using the phosphor glass on a selected chip in which emission is well absorbed by all phosphors. The screen-printing technique also offers possibilities for the design and engineering of complex phosphor layers on glass substrates. Phosphor screen-printing technology allows the realization of high stability and thermal conductivity for the phosphor layer. This phosphor glass method provides many possibilities for LED packing, including thin-film flip chip and remote phosphor technology.

Ten-channel InP-based large-scale photonic integrated transmitter fabricated by SAG technology

NASA Astrophysics Data System (ADS)

Zhang, Can; Zhu, Hongliang; Liang, Song; Cui, Xiao; Wang, Huitao; Zhao, Lingjuan; Wang, Wei

2014-12-01

A 10-channel InP-based large-scale photonic integrated transmitter was fabricated by selective area growth (SAG) technology combined with butt-joint regrowth (BJR) technology. The SAG technology was utilized to fabricate the electroabsorption modulated distributed feedback (DFB) laser (EML) arrays at the same time. The design of coplanar electrodes for electroabsorption modulator (EAM) was used for the flip-chip bonding package. The lasing wavelength of DFB laser could be tuned by the integrated micro-heater to match the ITU grids, which only needs one electrode pad. The average output power of each channel is 250 μW with an injection current of 200 mA. The static extinction ratios of the EAMs for 10 channels tested are ranged from 15 to 27 dB with a reverse bias of 6 V. The frequencies of 3 dB bandwidth of the chip for each channel are around 14 GHz. The novel design and simple fabrication process show its enormous potential in reducing the cost of large-scale photonic integrated circuit (LS-PIC) transmitter with high chip yields.

Trade-offs between lens complexity and real estate utilization in a free-space multichip global interconnection module.

PubMed

Milojkovic, Predrag; Christensen, Marc P; Haney, Michael W

2006-07-01

The FAST-Net (Free-space Accelerator for Switching Terabit Networks) concept uses an array of wide-field-of-view imaging lenses to realize a high-density shuffle interconnect pattern across an array of smart-pixel integrated circuits. To simplify the optics we evaluated the efficiency gained in replacing spherical surfaces with aspherical surfaces by exploiting the large disparity between narrow vertical cavity surface emitting laser (VCSEL) beams and the wide field of view of the imaging optics. We then analyzed trade-offs between lens complexity and chip real estate utilization and determined that there exists an optimal numerical aperture for VCSELs that maximizes their area density. The results provide a general framework for the design of wide-field-of-view free-space interconnection systems that incorporate high-density VCSEL arrays.

Test Structures for Rapid Prototyping of Gas and Pressure Sensors

NASA Technical Reports Server (NTRS)

Buehler, M.; Cheng, L. J.; Martin, D.

1996-01-01

A multi-project ceramic substrate was used in developing a gas sensor and pressure sensor. The ceramic substrate cantained 36 chips with six variants including sensors, process control monitors, and an interconnect ship. Tha gas sensor is being developed as an air quality monitor and the pressure gauge as a barometer.

FPGA-Based Laboratory Assignments for NoC-Based Manycore Systems

ERIC Educational Resources Information Center

Ttofis, C.; Theocharides, T.; Michael, M. K.

2012-01-01

Manycore systems have emerged as being one of the dominant architectural trends in next-generation computer systems. These highly parallel systems are expected to be interconnected via packet-based networks-on-chip (NoC). The complexity of such systems poses novel and exciting challenges in academia, as teaching their design requires the students…

Hybrid Silicon Photonic Integration using Quantum Well Intermixing

NASA Astrophysics Data System (ADS)

Jain, Siddharth R.

With the push for faster data transfer across all domains of telecommunication, optical interconnects are transitioning into shorter range applications such as in data centers and personal computing. Silicon photonics, with its economic advantages of leveraging well-established silicon manufacturing facilities, is considered the most promising approach to further scale down the cost and size of optical interconnects for chip-to-chip communication. Intrinsic properties of silicon however limit its ability to generate and modulate light, both of which are key to realizing on-chip optical data transfer. The hybrid silicon approach directly addresses this problem by using molecularly bonded III-V epitaxial layers on silicon for optical gain and absorption. This technology includes direct transfer of III-V wafer to a pre-patterned silicon-on-insulator wafer. Several discrete devices for light generation, modulation, amplification and detection have already been demonstrated on this platform. As in the case of electronics, multiple photonic elements can be integrated on a single chip to improve performance and functionality. However, scalable photonic integration requires the ability to control the bandgap for individual devices along with design changes to simplify fabrication. In the research presented here, quantum well intermixing is used as a technique to define multiple bandgaps for integration on the hybrid silicon platform. Implantation enhanced disordering is used to generate four bandgaps spread over 120+ nm. By combining these selectively intermixed III-V layers with pre-defined gratings and waveguides on silicon, we fabricate distributed feedback, distributed Bragg reflector, Fabry-Perot and mode-locked lasers along with photodetectors, electro-absorption modulators and other test structures, all on a single chip. We demonstrate a broadband laser source with continuous-wave operational lasers over a 200 nm bandwidth. Some of these lasers are integrated with modulators with a 3-dB bandwidth above 25 GHz, thus demonstrating coarse wavelength division multiplexing transmitter on silicon.

High-speed and on-chip graphene blackbody emitters for optical communications by remote heat transfer.

PubMed

Miyoshi, Yusuke; Fukazawa, Yusuke; Amasaka, Yuya; Reckmann, Robin; Yokoi, Tomoya; Ishida, Kazuki; Kawahara, Kenji; Ago, Hiroki; Maki, Hideyuki

2018-03-29

High-speed light emitters integrated on silicon chips can enable novel architectures for silicon-based optoelectronics, such as on-chip optical interconnects, and silicon photonics. However, conventional light sources based on compound semiconductors face major challenges for their integration with a silicon-based platform because of their difficulty of direct growth on a silicon substrate. Here we report ultra-high-speed (100-ps response time), highly integrated graphene-based on-silicon-chip blackbody emitters in the near-infrared region including telecommunication wavelength. Their emission responses are strongly affected by the graphene contact with the substrate depending on the number of graphene layers. The ultra-high-speed emission can be understood by remote quantum thermal transport via surface polar phonons of the substrates. We demonstrated real-time optical communications, integrated two-dimensional array emitters, capped emitters operable in air, and the direct coupling of optical fibers to the emitters. These emitters can open new routes to on-Si-chip, small footprint, and high-speed emitters for highly integrated optoelectronics and silicon photonics.

Packaging Technologies for High Temperature Electronics and Sensors

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Spry, David J.; Meredith, Roger D.

2013-01-01

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500 C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550 C. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500 C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500 C are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

PECVD based silicon oxynitride thin films for nano photonic on chip interconnects applications.

PubMed

Sharma, Satinder K; Barthwal, Sumit; Singh, Vikram; Kumar, Anuj; Dwivedi, Prabhat K; Prasad, B; Kumar, Dinesh

2013-01-01

Thin silicon oxynitride (SiO(x)N(y)) films were deposited by low temperature (~300°C) plasma enhanced chemical vapour deposition (PECVD), using SiH(4), N(2)O, NH(3) precursor of the flow rate 25, 100, 30 sccm and subjected to the post deposition annealing (PDA) treatment at 400°C and 600°C for nano optical/photonics on chip interconnects applications. AFM result reveals the variation of roughness from 60.9 Å to 23.4 Å after PDA treatment with respect to the as-deposited films, favourable surface topography for integrated waveguide applications. A model of decrease in island height with the effect of PDA treatment is proposed in support of AFM results. Raman spectroscopy and FTIR measurements are performed in order to define the change in crystallite and chemical bonding of as-deposited as well as PDA treated samples. These outcomes endorsed to the densification of SiO(x)N(y) thin films, due to decrease in Si-N and Si-O bonds strain, as well the O-H, N-H bonds with in oxynitride network. The increase in refractive index and PL intensity of as deposited SiO(x)N(y) thin films to the PDA treated films at 400°C and 600°C are observed. The significant shift of PL spectra peak positions indicate the change in cluster size as the result of PDA treatment, which influence the optical properties of thin films. It might be due to out diffusion of hydrogen containing species from silicon oxynitride films after PDA treatment. In this way, the structural and optical, feasibility of SiO(x)N(y) films are demonstrated in order to obtain high quality thin films for nano optical/photonics on chip interconnects applications. Copyright © 2012 Elsevier Ltd. All rights reserved.

Automated Absorber Attachment for X-ray Microcalorimeter Arrays

NASA Technical Reports Server (NTRS)

Moseley, S.; Allen, Christine; Kilbourne, Caroline; Miller, Timothy M.; Costen, Nick; Schulte, Eric; Moseley, Samuel J.

2007-01-01

Our goal is to develop a method for the automated attachment of large numbers of absorber tiles to large format detector arrays. This development includes the fabrication of high quality, closely spaced HgTe absorber tiles that are properly positioned for pick-and-place by our FC150 flip chip bonder. The FC150 also transfers the appropriate minute amount of epoxy to the detectors for permanent attachment of the absorbers. The success of this development will replace an arduous, risky and highly manual task with a reliable, high-precision automated process.

Nanohole Array-directed Trapping of Mammalian Mitochondria Enabling Single Organelle Analysis

PubMed Central

Kumar, Shailabh; Wolken, Gregory G.; Wittenberg, Nathan J.; Arriaga, Edgar A.; Oh, Sang-Hyun

2016-01-01

We present periodic nanohole arrays fabricated in free-standing metal-coated nitride films as a platform for trapping and analyzing single organelles. When a microliter-scale droplet containing mitochondria is dispensed above the nanohole array, the combination of evaporation and capillary flow directs individual mitochondria to the nanoholes. Mammalian mitochondria arrays were rapidly formed on chip using this technique without any surface modification steps, microfluidic interconnects or external power sources. The trapped mitochondria were depolarized on chip using an ionophore with results showing that the organelle viability and behavior were preserved during the on-chip assembly process. Fluorescence signal related to mitochondrial membrane potential was obtained from single mitochondria trapped in individual nanoholes revealing statistical differences between the behavior of polarized vs. depolarized mammalian mitochondria. This technique provides a fast and stable route for droplet-based directed localization of organelles-on-a-chip with minimal limitations and complexity, as well as promotes integration with other optical or electrochemical detection techniques. PMID:26593329

Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors

PubMed Central

Huang, Yue; Mason, Andrew J.

2013-01-01

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Lab-on-CMOS integration of microfluidics and electrochemical sensors.

PubMed

Huang, Yue; Mason, Andrew J

2013-10-07

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms.

Ice-assisted transfer of carbon nanotube arrays.

PubMed

Wei, Haoming; Wei, Yang; Lin, Xiaoyang; Liu, Peng; Fan, Shoushan; Jiang, Kaili

2015-03-11

Decoupling the growth and the application of nanomaterials by transfer is an important issue in nanotechnology. Here, we developed an efficient transfer technique for carbon nanotube (CNT) arrays by using ice as a binder to temporarily bond the CNT array and the target substrate. Ice makes it an ultraclean transfer because the evaporation of ice ensures that no contaminants are introduced. The transferred superaligned carbon nanotube (SACNT) arrays not only keep their original appearance and initial alignment but also inherit their spinnability, which is the most desirable feature. The transfer-then-spin strategy can be employed to fabricate patterned CNT arrays, which can act as 3-dimensional electrodes in CNT thermoacoustic chips. Besides, the flip-chipped CNTs are promising field electron emitters. Furthermore, the ice-assisted transfer technique provides a cost-effective solution for mass production of SACNTs, giving CNT technologies a competitive edge, and this method may inspire new ways to transfer other nanomaterials.

Integrated microsystems packaging approach with LCP

NASA Astrophysics Data System (ADS)

Jaynes, Paul; Shacklette, Lawrence W.

2006-05-01

Within the government communication market there is an increasing push to further miniaturize systems with the use of chip-scale packages, flip-chip bonding, and other advances over traditional packaging techniques. Harris' approach to miniaturization includes these traditional packaging advances, but goes beyond this level of miniaturization by combining the functional and structural elements of a system, thus creating a Multi-Functional Structural Circuit (MFSC). An emerging high-frequency, near hermetic, thermoplastic electronic substrate material, Liquid Crystal Polymer (LCP), is the material that will enable the combination of the electronic circuit and the physical structure of the system. The first embodiment of this vision for Harris is the development of a battlefield acoustic sensor module. This paper will introduce LCP and its advantages for MFSC, present an example of the work that Harris has performed, and speak to LCP MFSCs' potential benefits to miniature communications modules and sensor platforms.

Silicon quantum processor with robust long-distance qubit couplings

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tosi, Guilherme; Mohiyaddin, Fahd A.; Schmitt, Vivien

Practical quantum computers require a large network of highly coherent qubits, interconnected in a design robust against errors. Donor spins in silicon provide state-of-the-art coherence and quantum gate fidelities, in a platform adapted from industrial semiconductor processing. Here we present a scalable design for a silicon quantum processor that does not require precise donor placement and leaves ample space for the routing of interconnects and readout devices. We introduce the flip-flop qubit, a combination of the electron-nuclear spin states of a phosphorus donor that can be controlled by microwave electric fields. Two-qubit gates exploit a second-order electric dipole-dipole interaction, allowingmore » selective coupling beyond the nearest-neighbor, at separations of hundreds of nanometers, while microwave resonators can extend the entanglement to macroscopic distances. We predict gate fidelities within fault-tolerance thresholds using realistic noise models. This design provides a realizable blueprint for scalable spin-based quantum computers in silicon.« less

Distributed and Lumped Parameter Models for the Characterization of High Throughput Bioreactors

PubMed Central

Conoscenti, Gioacchino; Cutrì, Elena; Tuan, Rocky S.; Raimondi, Manuela T.; Gottardi, Riccardo

2016-01-01

Next generation bioreactors are being developed to generate multiple human cell-based tissue analogs within the same fluidic system, to better recapitulate the complexity and interconnection of human physiology [1, 2]. The effective development of these devices requires a solid understanding of their interconnected fluidics, to predict the transport of nutrients and waste through the constructs and improve the design accordingly. In this work, we focus on a specific model of bioreactor, with multiple input/outputs, aimed at generating osteochondral constructs, i.e., a biphasic construct in which one side is cartilaginous in nature, while the other is osseous. We next develop a general computational approach to model the microfluidics of a multi-chamber, interconnected system that may be applied to human-on-chip devices. This objective requires overcoming several challenges at the level of computational modeling. The main one consists of addressing the multi-physics nature of the problem that combines free flow in channels with hindered flow in porous media. Fluid dynamics is also coupled with advection-diffusion-reaction equations that model the transport of biomolecules throughout the system and their interaction with living tissues and C constructs. Ultimately, we aim at providing a predictive approach useful for the general organ-on-chip community. To this end, we have developed a lumped parameter approach that allows us to analyze the behavior of multi-unit bioreactor systems with modest computational effort, provided that the behavior of a single unit can be fully characterized. PMID:27669413

Distributed and Lumped Parameter Models for the Characterization of High Throughput Bioreactors.

PubMed

Iannetti, Laura; D'Urso, Giovanna; Conoscenti, Gioacchino; Cutrì, Elena; Tuan, Rocky S; Raimondi, Manuela T; Gottardi, Riccardo; Zunino, Paolo

Next generation bioreactors are being developed to generate multiple human cell-based tissue analogs within the same fluidic system, to better recapitulate the complexity and interconnection of human physiology [1, 2]. The effective development of these devices requires a solid understanding of their interconnected fluidics, to predict the transport of nutrients and waste through the constructs and improve the design accordingly. In this work, we focus on a specific model of bioreactor, with multiple input/outputs, aimed at generating osteochondral constructs, i.e., a biphasic construct in which one side is cartilaginous in nature, while the other is osseous. We next develop a general computational approach to model the microfluidics of a multi-chamber, interconnected system that may be applied to human-on-chip devices. This objective requires overcoming several challenges at the level of computational modeling. The main one consists of addressing the multi-physics nature of the problem that combines free flow in channels with hindered flow in porous media. Fluid dynamics is also coupled with advection-diffusion-reaction equations that model the transport of biomolecules throughout the system and their interaction with living tissues and C constructs. Ultimately, we aim at providing a predictive approach useful for the general organ-on-chip community. To this end, we have developed a lumped parameter approach that allows us to analyze the behavior of multi-unit bioreactor systems with modest computational effort, provided that the behavior of a single unit can be fully characterized.

Smart and functional polymer materials for smart and functional microfluidic instruments

NASA Astrophysics Data System (ADS)

Gray, Bonnie L.

2014-04-01

As microfluidic systems evolve from "chip-in-the-lab" to true portable lab-on-a-chip (LoC) or lab-in-a-package (LiP) microinstrumentation, there is a need for increasingly miniaturized sensors, actuators, and integration/interconnect technologies with high levels of functionality and self-direction. Furthermore, as microfluidic instruments are increasingly realized in polymer-based rather than glass- or silicon- based platforms, there is a need to realize these highly functional components in materials that are polymer-compatible. Polymers that are altered to possess basic functionality, and even higher-functioning "smart" polymer materials, may help to realize high-functioning and selfdirecting portable microinstrumentation. Stimuli-responsive hydrogels have been recognized for over a decade as beneficial to the development of smart microfluidics systems and instrumentation. In addition, functional materials such as conductive and magnetic composite polymers are being increasingly employed to push microfluidics systems to greater degrees of functionality, portability, and/or flexibility for wearable/implantable systems. Functional and smart polymer materials can be employed to realize electrodes, electronic routing, heaters, mixers, valves, pumps, sensors, and interconnect structures in polymer-based microfluidic systems. Stimuli for such materials can be located on-chip or in a small package, thus greatly increasing the degree of portability and the potential for mechanical flexibility of such systems. This paper will examine the application of functional polymer materials to the development of high-functioning microfluidics instruments with a goal towards self-direction.

Continuous epitaxial growth of extremely strong Cu6Sn5 textures at liquid-Sn/(111)Cu interface under temperature gradient

NASA Astrophysics Data System (ADS)

Zhong, Y.; Zhao, N.; Liu, C. Y.; Dong, W.; Qiao, Y. Y.; Wang, Y. P.; Ma, H. T.

2017-11-01

As the diameter of solder interconnects in three-dimensional integrated circuits (3D ICs) downsizes to several microns, how to achieve a uniform microstructure with thousands of interconnects on stacking chips becomes a critical issue in 3D IC manufacturing. We report a promising way for fabricating fully intermetallic interconnects with a regular grain morphology and a strong texture feature by soldering single crystal (111) Cu/Sn/polycrystalline Cu interconnects under the temperature gradient. Continuous epitaxial growth of η-Cu6Sn5 at cold end liquid-Sn/(111)Cu interfaces has been demonstrated. The resultant η-Cu6Sn5 grains show faceted prism textures with an intersecting angle of 60° and highly preferred orientation with their ⟨ 11 2 ¯ 0 ⟩ directions nearly paralleling to the direction of the temperature gradient. These desirable textures are maintained even after soldering for 120 min. The results pave the way for controlling the morphology and orientation of interfacial intermetallics in 3D packaging technologies.

Numerical simulation and experimental investigation of GaN-based flip-chip LEDs and top-emitting LEDs.

PubMed

Liu, Xingtong; Zhou, Shengjun; Gao, Yilin; Hu, Hongpo; Liu, Yingce; Gui, Chengqun; Liu, Sheng

2017-12-01

We demonstrate a GaN-based flip-chip LED (FC-LED) with a highly reflective indium-tin oxide (ITO)/distributed Bragg reflector (DBR) ohmic contact. A transparent ITO current spreading layer combined with Ta 2 O 5 /SiO 2 double DBR stacks is used as a reflective p-type ohmic contact in the FC-LED. We develop a strip-shaped SiO 2 current blocking layer, which is well aligned with a p-electrode, to prevent the current from crowding around the p-electrode. Our combined numerical simulation and experimental results revealed that the FC-LED with ITO/DBR has advantages of better current spreading and superior heat dissipation performance compared to top-emitting LEDs (TE-LEDs). As a result, the light output power (LOP) of the FC-LED with ITO/DBR was 7.6% higher than that of the TE-LED at 150 mA, and the light output saturation current was shifted from 130.9  A/cm 2 for the TE-LED to 273.8  A/cm 2 for the FC-LED with ITO/DBR. Owing to the high reflectance of the ITO/DBR ohmic contact, the LOP of the FC-LED with ITO/DBR was 13.0% higher than that of a conventional FC-LED with Ni/Ag at 150 mA. However, because of the better heat dissipation of the Ni/Ag ohmic contact, the conventional FC-LED with Ni/Ag exhibited higher light output saturation current compared to the FC-LED with ITO/DBR.

NSC 800, 8-bit CMOS microprocessor

NASA Technical Reports Server (NTRS)

Suszko, S. F.

1984-01-01

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Li, K.; Shih, Y. C.

1992-01-01

Packaging schemes were developed that provide low-loss, hermetic enclosure for advanced monolithic microwave and millimeter-wave integrated circuits (MMICs). The package designs are based on a fused quartz substrate material that offers improved radio frequency (RF) performance through 44 gigahertz (GHz). The small size and weight of the packages make them appropriate for a variety of applications, including phased array antenna systems. Packages were designed in two forms; one for housing a single MMIC chip, the second in the form of a multi-chip phased array module. The single chip array module was developed in three separate sizes, for chips of different geometry and frequency requirements. The phased array module was developed to address packaging directly for antenna applications, and includes transmission line and interconnect structures to support multi-element operation. All packages are fabricated using fused quartz substrate materials. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices. The package and test fixture designs were both developed in a generic sense, optimizing performance for a wide range of possible applications and devices.

Towards co-packaging of photonics and microelectronics in existing manufacturing facilities

NASA Astrophysics Data System (ADS)

Janta-Polczynski, Alexander; Cyr, Elaine; Bougie, Jerome; Drouin, Alain; Langlois, Richard; Childers, Darrell; Takenobu, Shotaro; Taira, Yoichi; Lichoulas, Ted W.; Kamlapurkar, Swetha; Engelmann, Sebastian; Fortier, Paul; Boyer, Nicolas; Barwicz, Tymon

2018-02-01

The impact of integrated photonics on optical interconnects is currently muted by challenges in photonic packaging and in the dense integration of photonic modules with microelectronic components on printed circuit boards. Single mode optics requires tight alignment tolerance for optical coupling and maintaining this alignment in a cost-efficient package can be challenging during thermal excursions arising from downstream microelectronic assembly processes. In addition, the form factor of typical fiber connectors is incompatible with the dense module integration expected on printed circuit boards. We have implemented novel approaches to interfacing photonic chips to standard optical fibers. These leverage standard high throughput microelectronic assembly tooling and self-alignment techniques resulting in photonic packaging that is scalable in manufacturing volume and in the number of optical IOs per chip. In addition, using dense optical fiber connectors with space-efficient latching of fiber patch cables results in compact module size and efficient board integration, bringing the optics closer to the logic chip to alleviate bandwidth bottlenecks. This packaging direction is also well suited for embedding optics in multi-chip modules, including both photonic and microelectronic chips. We discuss the challenges and rewards in this type of configuration such as thermal management and signal integrity.

An Implantable Neural Sensing Microsystem with Fiber-Optic Data Transmission and Power Delivery

PubMed Central

Park, Sunmee; Borton, David A.; Kang, Mingyu; Nurmikko, Arto V.; Song, Yoon-Kyu

2013-01-01

We have developed a prototype cortical neural sensing microsystem for brain implantable neuroengineering applications. Its key feature is that both the transmission of broadband, multichannel neural data and power required for the embedded microelectronics are provided by optical fiber access. The fiber-optic system is aimed at enabling neural recording from rodents and primates by converting cortical signals to a digital stream of infrared light pulses. In the full microsystem whose performance is summarized in this paper, an analog-to-digital converter and a low power digital controller IC have been integrated with a low threshold, semiconductor laser to extract the digitized neural signals optically from the implantable unit. The microsystem also acquires electrical power and synchronization clocks via optical fibers from an external laser by using a highly efficient photovoltaic cell on board. The implantable unit employs a flexible polymer substrate to integrate analog and digital microelectronics and on-chip optoelectronic components, while adapting to the anatomical and physiological constraints of the environment. A low power analog CMOS chip, which includes preamplifier and multiplexing circuitry, is directly flip-chip bonded to the microelectrode array to form the cortical neurosensor device. PMID:23666130

Cell Patterning Chip for Controlling the Stem Cell Microenvironment

PubMed Central

Rosenthal, Adam; Macdonald, Alice; Voldman, Joel

2007-01-01

Cell-cell signaling is an important component of the stem cell microenvironment, affecting both differentiation and self-renewal. However, traditional cell-culture techniques do not provide precise control over cell-cell interactions, while existing cell patterning technologies are limited when used with proliferating or motile cells. To address these limitations, we created the Bio Flip Chip (BFC), a microfabricated polymer chip containing thousands of microwells, each sized to trap down to a single stem cell. We have demonstrated the functionality of the BFC by patterning a 50×50 grid of murine embryonic stem cells (mESCs), with patterning efficiencies > 75%, onto a variety of substrates – a cell-culture dish patterned with gelatin, a 3-D substrate, and even another layer of cells. We also used the BFC to pattern small groups of cells, with and without cell-cell contact, allowing incremental and independent control of contact-mediated signaling. We present quantitative evidence that cell-cell contact plays an important role in depressing mESC colony formation, and show that E-cadherin is involved in this negative regulatory pathway. Thus, by allowing exquisite control of the cellular microenvironment, we provide a technology that enables new applications in tissue engineering and regenerative medicine. PMID:17434582

Low power laser driver design in 28nm CMOS for on-chip and chip-to-chip optical interconnect

NASA Astrophysics Data System (ADS)

Belfiore, Guido; Szilagyi, Laszlo; Henker, Ronny; Ellinger, Frank

2015-09-01

This paper discusses the challenges and the trade-offs in the design of laser drivers for very-short distance optical communications. A prototype integrated circuit is designed and fabricated in 28 nm super-low-power CMOS technology. The power consumption of the transmitter is 17.2 mW excluding the VCSEL that in our test has a DC power consumption of 10 mW. The active area of the driver is only 0.0045 mm2. The driver can achieve an error-free (BER < 10 -12) electrical data-rate of 25 Gbit/s using a pseudo random bit sequence of 27 -1. When the driver is connected to the VCSEL module an open optical eye is reported at 15 Gbit/s. In the tested bias point the VCSEL module has a measured bandwidth of 10.7 GHz.

Sparse matrix-vector multiplication on network-on-chip

NASA Astrophysics Data System (ADS)

Sun, C.-C.; Götze, J.; Jheng, H.-Y.; Ruan, S.-J.

2010-12-01

In this paper, we present an idea for performing matrix-vector multiplication by using Network-on-Chip (NoC) architecture. In traditional IC design on-chip communications have been designed with dedicated point-to-point interconnections. Therefore, regular local data transfer is the major concept of many parallel implementations. However, when dealing with the parallel implementation of sparse matrix-vector multiplication (SMVM), which is the main step of all iterative algorithms for solving systems of linear equation, the required data transfers depend on the sparsity structure of the matrix and can be extremely irregular. Using the NoC architecture makes it possible to deal with arbitrary structure of the data transfers; i.e. with the irregular structure of the sparse matrices. So far, we have already implemented the proposed SMVM-NoC architecture with the size 4×4 and 5×5 in IEEE 754 single float point precision using FPGA.

Three-mode all-optical (de)multiplexing on a SOI chip

NASA Astrophysics Data System (ADS)

Le, Yan-Si; Wang, Zhi; Li, Zhi-Yong; Li, Ying; Li, Qiang; Cui, Can; Wu, Chong-Qing

2018-01-01

An on-chip three-mode division multiplexing circuit using a simple ADC-based TE0 & TE1 & TE2 (de)multiplexer is demonstrated to improve the link capacity of on-chip optical interconnects. The proposed (de)multiplexer does not contain any tapered waveguide which is different from the previous mode (de)multiplexer based on ADCs. Here, we choose multimode waveguide width first and then confirm corresponding width of the other two waveguides. Thus the bus waveguide without any tapers can not only reduce complexity of (de)multiplexer but also reduce difficulty of the fabrication. Our simulation results show that the hybrid multiplexer has relatively low loss and low crosstalk about -40 dB, -26.99 dB and -28.72 dB for each mode around 1550 nm with a width-variation w =± 25 nm. These properties make the proposed mode-(de)multiplexer suitable for application in high-capacity data transmission.

Multilayered microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2003-01-01

An apparatus for packaging of microelectronic devices is disclosed, wherein the package includes an integral window. The microelectronic device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The package can comprise, for example, a cofired ceramic frame or body. The package has an internal stepped structure made of a plurality of plates, with apertures, which are patterned with metallized conductive circuit traces. The microelectronic device can be flip-chip bonded on the plate to these traces, and oriented so that the light-sensitive side is optically accessible through the window. A cover lid can be attached to the opposite side of the package. The result is a compact, low-profile package, having an integral window that can be hermetically-sealed. The package body can be formed by low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the window being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. Multiple chips can be located within a single package, according to some embodiments. The cover lid can include a window. The apparatus is particularly suited for packaging of MEMS devices, since the number of handling steps is greatly reduced, thereby reducing the potential for contamination. The integral window can further include a lens for optically transforming light passing through the window. The package can include an array of binary optic lenslets made integral with the window. The package can include an electrically-switched optical modulator, such as a lithium niobate window attached to the package, for providing a very fast electrically-operated shutter.

Investigation Of The Effects Of Reflow Profile Parameters On Lead-free Solder Bump Volumes And Joint Integrity

NASA Astrophysics Data System (ADS)

Amalu, E. H.; Lui, Y. T.; Ekere, N. N.; Bhatti, R. S.; Takyi, G.

2011-01-01

The electronics manufacturing industry was quick to adopt and use the Surface Mount Technology (SMT) assembly technique on realization of its huge potentials in achieving smaller, lighter and low cost product implementations. Increasing global customer demand for miniaturized electronic products is a key driver in the design, development and wide application of high-density area array package format. Electronic components and their associated solder joints have reduced in size as the miniaturization trend in packaging continues to be challenged by printing through very small stencil apertures required for fine pitch flip-chip applications. At very narrow aperture sizes, solder paste rheology becomes crucial for consistent paste withdrawal. The deposition of consistent volume of solder from pad-to-pad is fundamental to minimizing surface mount assembly defects. This study investigates the relationship between volume of solder paste deposit (VSPD) and the volume of solder bump formed (VSBF) after reflow, and the effect of reflow profile parameters on lead-free solder bump formation and the associated solder joint integrity. The study uses a fractional factorial design (FFD) of 24-1 Ramp-Soak-Spike reflow profile, with all main effects and two-way interactions estimable to determine the optimal factorial combination. The results from the study show that the percentage change in the VSPD depends on the combination of the process parameters and reliability issues could become critical as the size of solder joints soldered on the same board assembly vary greatly. Mathematical models describe the relationships among VSPD, VSBF and theoretical volume of solder paste. Some factors have main effects across the volumes and a number of interactions exist among them. These results would be useful for R&D personnel in designing and implementing newer applications with finer-pitch interconnect.

Improving yield and reliability of FIB modifications using electrical testing

NASA Astrophysics Data System (ADS)

Desplats, Romain; Benbrik, Jamel; Benteo, Bruno; Perdu, Philippe

1998-08-01

Focused Ion Beam technology has two main areas of application for ICs: modification and preparation for technological analysis. The most solicited area is modification. This involves physically modifying a circuit by cutting lines and creating new ones in order to change the electrical function of the circuit. IC planar technologies have an increasing number of metal interconnections making FIB modifications more complex and decreasing their changes of success. The yield of FIB operations on ICs reflects a downward trend that imposes a greater number of circuits to be modified in order to successfully correct a small number of them. This requires extended duration, which is not compatible with production line turn around times. To respond to this problem, two solutions can be defined: either, reducing the duration of each FIB operation or increasing the success rate of FIB modifications. Since reducing the time depends mainly on FIB operator experience, insuring a higher success rate represents a more crucial aspect as both experienced and novice operators could benefit from this improvement. In order to insure successful modifications, it is necessary to control each step of a FIB operation. To do this, we have developed a new method using in situ electrical testing which has a direct impact on the yield of FIB modifications. We will present this innovative development through a real case study of a CMOS ASIC for high-speed communications. Monitoring the electrical behavior at each step in a FIB operation makes it possible to reduce the number of circuits to be modified and consequently reduces system costs thanks to better yield control. Knowing the internal electrical behavior also gives us indications about the impact on reliability of FIB modified circuits. Finally, this approach can be applied to failure analysis and FIB operations on flip chip circuits.

Advanced Interconnect Roadmap for Space Applications

NASA Technical Reports Server (NTRS)

Galbraith, Lissa

1999-01-01

This paper presents the NASA electronic parts and packaging program for space applications. The topics include: 1) Forecasts; 2) Technology Challenges; 3) Research Directions; 4) Research Directions for Chip on Board (COB); 5) Research Directions for HDPs: Multichip Modules (MCMs); 6) Research Directions for Microelectromechanical systems (MEMS); 7) Research Directions for Photonics; and 8) Research Directions for Materials. This paper is presented in viewgraph form.

Phase change material based tunable reflectarray for free-space optical inter/intra chip interconnects.

PubMed

Zou, Longfang; Cryan, Martin; Klemm, Maciej

2014-10-06

The concept of phase change material (PCM) based optical antennas and antenna arrays is proposed for dynamic beam shaping and steering utilized in free-space optical inter/intra chip interconnects. The essence of this concept lies in the fact that the behaviour of PCM based optical antennas will change due to the different optical properties of the amorphous and crystalline state of the PCM. By engineering optical antennas or antenna arrays, it is feasible to design dynamic optical links in a desired manner. In order to illustrate this concept, a PCM based tunable reflectarray is proposed for a scenario of a dynamic optical link between a source and two receivers. The designed reflectarray is able to switch the optical link between two receivers by switching the two states of the PCM. Two types of antennas are employed in the proposed tunable reflectarray to achieve full control of the wavefront of the reflected beam. Numerical studies show the expected binary beam steering at the optical communication wavelength of 1.55 μm. This study suggests a new research area of PCM based optical antennas and antenna arrays for dynamic optical switching and routing.

Electrically driven monolithic subwavelength plasmonic interconnect circuits

PubMed Central

Liu, Yang; Zhang, Jiasen; Liu, Huaping; Wang, Sheng; Peng, Lian-Mao

2017-01-01

In the post-Moore era, an electrically driven monolithic optoelectronic integrated circuit (OEIC) fabricated from a single material is pursued globally to enable the construction of wafer-scale compact computing systems with powerful processing capabilities and low-power consumption. We report a monolithic plasmonic interconnect circuit (PIC) consisting of a photovoltaic (PV) cascading detector, Au-strip waveguides, and electrically driven surface plasmon polariton (SPP) sources. These components are fabricated from carbon nanotubes (CNTs) via a CMOS (complementary metal-oxide semiconductor)–compatible doping-free technique in the same feature size, which can be reduced to deep-subwavelength scale (~λ/7 to λ/95, λ = 1340 nm) compared with the 14-nm technique node. An OEIC could potentially be configured as a repeater for data transport because of its “photovoltaic” operation mode to transform SPP energy directly into electricity to drive subsequent electronic circuits. Moreover, chip-scale throughput capability has also been demonstrated by fabricating a 20 × 20 PIC array on a 10 mm × 10 mm wafer. Tailoring photonics for monolithic integration with electronics beyond the diffraction limit opens a new era of chip-level nanoscale electronic-photonic systems, introducing a new path to innovate toward much faster, smaller, and cheaper computing frameworks. PMID:29062890

Single-chip microprocessor that communicates directly using light

NASA Astrophysics Data System (ADS)

Sun, Chen; Wade, Mark T.; Lee, Yunsup; Orcutt, Jason S.; Alloatti, Luca; Georgas, Michael S.; Waterman, Andrew S.; Shainline, Jeffrey M.; Avizienis, Rimas R.; Lin, Sen; Moss, Benjamin R.; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H.; Cook, Henry M.; Ou, Albert J.; Leu, Jonathan C.; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J.; Popović, Miloš A.; Stojanović, Vladimir M.

2015-12-01

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Single-chip microprocessor that communicates directly using light.

PubMed

Sun, Chen; Wade, Mark T; Lee, Yunsup; Orcutt, Jason S; Alloatti, Luca; Georgas, Michael S; Waterman, Andrew S; Shainline, Jeffrey M; Avizienis, Rimas R; Lin, Sen; Moss, Benjamin R; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H; Cook, Henry M; Ou, Albert J; Leu, Jonathan C; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J; Popović, Miloš A; Stojanović, Vladimir M

2015-12-24

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Roll up nanowire battery from silicon chips

PubMed Central

Vlad, Alexandru; Reddy, Arava Leela Mohana; Ajayan, Anakha; Singh, Neelam; Gohy, Jean-François; Melinte, Sorin; Ajayan, Pulickel M.

2012-01-01

Here we report an approach to roll out Li-ion battery components from silicon chips by a continuous and repeatable etch-infiltrate-peel cycle. Vertically aligned silicon nanowires etched from recycled silicon wafers are captured in a polymer matrix that operates as Li+ gel-electrolyte and electrode separator and peeled off to make multiple battery devices out of a single wafer. Porous, electrically interconnected copper nanoshells are conformally deposited around the silicon nanowires to stabilize the electrodes over extended cycles and provide efficient current collection. Using the above developed process we demonstrate an operational full cell 3.4 V lithium-polymer silicon nanowire (LIPOSIL) battery which is mechanically flexible and scalable to large dimensions. PMID:22949696

Testing interconnected VLSI circuits in the Big Viterbi Decoder

NASA Technical Reports Server (NTRS)

Onyszchuk, I. M.

1991-01-01

The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

Two-Volt Josephson Arbitrary Waveform Synthesizer Using Wilkinson Dividers.

PubMed

Flowers-Jacobs, Nathan E; Fox, Anna E; Dresselhaus, Paul D; Schwall, Robert E; Benz, Samuel P

2016-09-01

The root-mean-square (rms) output voltage of the NIST Josephson arbitrary waveform synthesizer (JAWS) has been doubled from 1 V to a record 2 V by combining two new 1 V chips on a cryocooler. This higher voltage will improve calibrations of ac thermal voltage converters and precision voltage measurements that require state-of-the-art quantum accuracy, stability, and signal-to-noise ratio. We achieved this increase in output voltage by using four on-chip Wilkinson dividers and eight inner-outer dc blocks, which enable biasing of eight Josephson junction (JJ) arrays with high-speed inputs from only four high-speed pulse generator channels. This approach halves the number of pulse generator channels required in future JAWS systems. We also implemented on-chip superconducting interconnects between JJ arrays, which reduces systematic errors and enables a new modular chip package. Finally, we demonstrate a new technique for measuring and visualizing the operating current range that reduces the measurement time by almost two orders of magnitude and reveals the relationship between distortion in the output spectrum and output pulse sequence errors.

A portable pressure pump for microfluidic lab-on-a-chip systems using a porous polydimethylsiloxane (PDMS) sponge.

PubMed

Cha, Kyoung Je; Kim, Dong Sung

2011-10-01

In this paper, we propose a novel portable and disposable pressure pump using a porous polydimethylsiloxane (PDMS) sponge and demonstrate its application to a microfluidic lab-on-a-chip. The porous PDMS sponge was simply fabricated by a sugar leaching technique based on capillary suction of pre-cured PDMS into lumps of sugar, thereby enabling us to achieve the porous PDMS sponge composed of interconnected micropores. To indicate the characteristics of the porous PDMS sponge and pump, we measured the average porosities of them whose values were 0.64 and 0.34, respectively. A stress-strain relationship of the fabricated portable pressure pump represented a linear behavior in the compressive strain range of 0 to 20%. Within this range, a pumping volume of the pressure pump could be linearly controlled by the compressed strain. Finally, the fabricated porous PDMS pump was successfully demonstrated as a portable pressure pump for a disposable microfluidic lab-on-a-chip for efficient detection of agglutination. The proposed portable pressure pump can be potentially applicable to various disposable microfluidic lab-on-a-chip systems.

Reliability assessment of Multichip Module technologies via the Triservice/NASA RELTECH program

NASA Astrophysics Data System (ADS)

Fayette, Daniel F.

1994-10-01

Multichip Module (MCM) packaging/interconnect technologies have seen increased emphasis from both the commercial and military communities as a means of increasing capability and performance while providing a vehicle for reducing cost, power and weight of the end item electronic application. This is accomplished through three basic Multichip module technologies, MCM-L that are laminates, MCM-C that are ceramic type substrates and MCM-D that are deposited substrates (e.g., polymer dielectric with thin film metals). Three types of interconnect structures are also used with these substrates and include, wire bond, Tape Automated Bonds (TAB) and flip chip ball bonds. Application, cost, producibility and reliability are the drivers that will determine which MCM technology will best fit a respective need or requirement. With all the benefits and technologies cited, it would be expected that the use of, or the planned use of, MCM's would be more extensive in both military and commercial applications. However, two significant roadblocks exist to implementation of these new technologies: the absence of reliability data and a single national standard for the procurement of reliable/quality MCM's. To address the preceding issues, the Reliability Technology to Achieve Insertion of Advanced Packaging (RELTECH) program has been established. This program, which began in May 1992, has endeavored to evaluate a cross section of MCM technologies covering all classes of MCM's previously cited. NASA and the Tri-Services (Air Force Rome Laboratory, Naval Surface Warfare Center, Crane IN and Army Research Laboratory) have teamed together with sponsorship from ARPA to evaluate the performance, reliability and producibility of MCM's for both military and commercial usage. This is done in close cooperation with our industry partners whose support is critical to the goals of the program. Several tasks are being performed by the RELTECH program and data from this effort, in conjunction with information from our industry partners as well as discussions with industry organizations (IPC, EIA, ISHM, etc.) are being used to develop the qualification and screening requirements for MCM's. Specific tasks being performed by the RELTECH program include technical assessments, product evaluations, reliability modeling, environmental testing, and failure analysis. This paper will describe the various tasks associated with the RELTECH program, status, progress and a description of the national dual use specification being developed for MCM technologies.

Encapsulation of Fluidic Tubing and Microelectrodes in Microfluidic Devices: Integrating Off-Chip Process and Coupling Conventional Capillary Electrophoresis with Electrochemical Detection

PubMed Central

Becirovic, Vedada; Doonan, Steven R.; Martin, R. Scott

2013-01-01

In this paper, an approach to fabricate epoxy or polystyrene microdevices with encapsulated tubing and electrodes is described. Key features of this approach include a fixed alignment between the fluidic tubing and electrodes, the ability to polish the device when desired, and the low dead volume nature of the fluidic interconnects. It is shown that a variety of tubing can be encapsulated with this approach, including fused silica capillary, polyetheretherketone (PEEK), and perfluoroalkoxy (PFA), with the resulting tubing/microchip interface not leading to significant band broadening or plug dilution. The applicability of the devices with embedded tubing is demonstrated by integrating several off-chip analytical methods to the microchip. This includes droplet transfer, droplet desegmentation, and microchip-based flow injection analysis. Off-chip generated droplets can be transferred to the microchip with minimal coalescence, while flow injection studies showed improved peak shape and sensitivity when compared to the use of fluidic interconnects with an appreciable dead volume. Importantly, it is shown that this low dead volume approach can be extended to also enable the integration of conventional capillary electrophoresis (CE) with electrochemical detection. This is accomplished by embedding fused silica capillary along with palladium (for grounding the electrophoresis voltage) and platinum (for detection) electrodes. With this approach, up to 128,000 theoretical plates for dopamine was possible. In all cases, the tubing and electrodes are housed in a rigid base; this results in extremely robust devices that will be of interest to researchers wanting to develop microchips for use by non-experts. PMID:24159363

Encapsulation of Fluidic Tubing and Microelectrodes in Microfluidic Devices: Integrating Off-Chip Process and Coupling Conventional Capillary Electrophoresis with Electrochemical Detection.

PubMed

Becirovic, Vedada; Doonan, Steven R; Martin, R Scott

2013-08-21

In this paper, an approach to fabricate epoxy or polystyrene microdevices with encapsulated tubing and electrodes is described. Key features of this approach include a fixed alignment between the fluidic tubing and electrodes, the ability to polish the device when desired, and the low dead volume nature of the fluidic interconnects. It is shown that a variety of tubing can be encapsulated with this approach, including fused silica capillary, polyetheretherketone (PEEK), and perfluoroalkoxy (PFA), with the resulting tubing/microchip interface not leading to significant band broadening or plug dilution. The applicability of the devices with embedded tubing is demonstrated by integrating several off-chip analytical methods to the microchip. This includes droplet transfer, droplet desegmentation, and microchip-based flow injection analysis. Off-chip generated droplets can be transferred to the microchip with minimal coalescence, while flow injection studies showed improved peak shape and sensitivity when compared to the use of fluidic interconnects with an appreciable dead volume. Importantly, it is shown that this low dead volume approach can be extended to also enable the integration of conventional capillary electrophoresis (CE) with electrochemical detection. This is accomplished by embedding fused silica capillary along with palladium (for grounding the electrophoresis voltage) and platinum (for detection) electrodes. With this approach, up to 128,000 theoretical plates for dopamine was possible. In all cases, the tubing and electrodes are housed in a rigid base; this results in extremely robust devices that will be of interest to researchers wanting to develop microchips for use by non-experts.

Silicon Photonics: Challenges and Future

DTIC Science & Technology

2007-01-01

process or phonon assisted. It directly impacts the internal quantum efficiency through the relationship : ηi = (1+ (τrad/τ non-rad ))-1 There are...linear cavity approach, the reported differential quantum efficiency is currently low. The measured characteristic temperature (To), is lower than...rule changes • package design 4.1.2 Inter-chip interconnects There is a requirement on the circuit card to transfer data more efficiently between

Compact holographic optical neural network system for real-time pattern recognition

NASA Astrophysics Data System (ADS)

Lu, Taiwei; Mintzer, David T.; Kostrzewski, Andrew A.; Lin, Freddie S.

1996-08-01

One of the important characteristics of artificial neural networks is their capability for massive interconnection and parallel processing. Recently, specialized electronic neural network processors and VLSI neural chips have been introduced in the commercial market. The number of parallel channels they can handle is limited because of the limited parallel interconnections that can be implemented with 1D electronic wires. High-resolution pattern recognition problems can require a large number of neurons for parallel processing of an image. This paper describes a holographic optical neural network (HONN) that is based on high- resolution volume holographic materials and is capable of performing massive 3D parallel interconnection of tens of thousands of neurons. A HONN with more than 16,000 neurons packaged in an attache case has been developed. Rotation- shift-scale-invariant pattern recognition operations have been demonstrated with this system. System parameters such as the signal-to-noise ratio, dynamic range, and processing speed are discussed.

The Unification of Space Qualified Integrated Circuits by Example of International Space Project GAMMA-400

NASA Astrophysics Data System (ADS)

Bobkov, S. G.; Serdin, O. V.; Arkhangelskiy, A. I.; Arkhangelskaja, I. V.; Suchkov, S. I.; Topchiev, N. P.

The problem of electronic component unification at the different levels (circuits, interfaces, hardware and software) used in space industry is considered. The task of computer systems for space purposes developing is discussed by example of scientific data acquisition system for space project GAMMA-400. The basic characteristics of high reliable and fault tolerant chips developed by SRISA RAS for space applicable computational systems are given. To reduce power consumption and enhance data reliability, embedded system interconnect made hierarchical: upper level is Serial RapidIO 1x or 4x with rate transfer 1.25 Gbaud; next level - SpaceWire with rate transfer up to 400 Mbaud and lower level - MIL-STD-1553B and RS232/RS485. The Ethernet 10/100 is technology interface and provided connection with the previously released modules too. Systems interconnection allows creating different redundancy systems. Designers can develop heterogeneous systems that employ the peer-to-peer networking performance of Serial RapidIO using multiprocessor clusters interconnected by SpaceWire.

Conductive contact area estimation for carbon nanotube via interconnects using secondary-electron imaging

NASA Astrophysics Data System (ADS)

Abe, Yusuke; Suzuki, Makoto; Vyas, Anshul; Yang, Cary Y.

2018-01-01

A major challenge for carbon nanotube (CNT) to become a viable replacement of copper and tungsten in the next-generation on-chip via interconnects is the high contact resistance between CNT and metal electrodes. A first step in meeting this challenge is an accurate characterization of via contact resistance. In this paper, the scanning electron microscope (SEM) image contrast at low landing energy is employed to estimate the conductive CNT area inside vias. The total conductive CNT area inside each via is deduced using SEM image with 0.1 keV landing energy and a specified threshold brightness, yielding via resistance versus CNT area behavior, which correlates well with electrical nanoprobing measurements of via resistance. Monte Carlo simulation of secondary electron generation lends further support for our analysis and suggests that the residue covering the CNT does not affect the conduction across the contact for residue thickness below 1 nm. This imaging and analysis technique can add much value to CNT via interconnect contact characterization.

Socket with built-in valves for the interconnection of microfluidic chips to macro constituents.

PubMed

Yang, Zhen; Maeda, Ryutaro

2003-09-26

This paper reports a prototype for a standard connector between a microfluidic chip and the macro world. This prototype demonstrate a fully functioning socket for a microchip to access the outside world by means of fluids, data signals and energy supply. It supports up to 10 channels for the input and output of liquids or gases, as well as compressed air or vacuum lines for pneumatic power lines. The socket has built-in valves for each flow channel. It also contains 28 pins for the connection of electrical signals and power. Built-in valves make it possible to control the flow in each channel independently. A chip ( 11.0 x 11.0 x 0.9 mm) can be mounted into or dismounted from the socket with one touch. The fluidic connectors of the socket are designed to contact vertically on the top of chip. And the electrical connectors (the spring array) of that physically support the chip and contact lead pads at the bottom of chip. No adhesives or solders are used at any contact points. The pressure limit for the connection of working fluids was 0.2 MPa and the current limit for the electrical connections was 1 A. This socket supports both serial and parallel processing applications. It exhibits great potential for developing microfluidic systems efficiently.

Toward more efficient fabrication of high-density 2-D VCSEL arrays for spatial redundancy and/or multi-level signal communication

NASA Astrophysics Data System (ADS)

Roscher, Hendrik; Gerlach, Philipp; Khan, Faisal Nadeem; Kroner, Andrea; Stach, Martin; Weigl, Alexander; Michalzik, Rainer

2006-04-01

We present flip-chip attached high-speed VCSELs in 2-D arrays with record-high intra-cell packing densities. The advances of VCSEL array technology toward improved thermal performance and more efficient fabrication are reviewed, and the introduction of self-aligned features to these devices is pointed out. The structure of close-spaced wedge-shaped VCSELs is discussed and their static and dynamic characteristics are presented including an examination of the modal structure by near-field measurements. The lasers flip-chip bonded to a silicon-based test platform exhibit 3-dB and 10-dB bandwidths of 7.7 GHz and 9.8 GHz, respectively. Open 12.5 Gbit/s two-level eye patterns are demonstrated. We discuss the uses of high packing densities for the increase of the total amount of data throughput an array can deliver in the course of its life. One such approach is to provide up to two backup VCSELs per fiber channel that can extend the lifetimes of parallel transmitters through redundancy of light sources. Another is to increase the information density by using multiple VCSELs per 50 μm core diameter multimode fiber to generate more complex signals. A novel scheme using three butt-coupled VCSELs per fiber for the generation of four-level signals in the optical domain is proposed. First experiments are demonstrated using two VCSELs butt-coupled to the same standard glass fiber, each modulated with two-level signals to produce four-level signals at the photoreceiver. A four-level direct modulation of one VCSEL within a triple of devices produced first 20.6 Gbit/s (10.3 Gsymbols/s) four-level eyes, leaving two VCSELs as backup sources.

Vertically Integrated MEMS SOI Composite Porous Silicon-Crystalline Silicon Cantilever-Array Sensors: Concept for Continuous Sensing of Explosives and Warfare Agents

NASA Astrophysics Data System (ADS)

Stolyarova, Sara; Shemesh, Ariel; Aharon, Oren; Cohen, Omer; Gal, Lior; Eichen, Yoav; Nemirovsky, Yael

This study focuses on arrays of cantilevers made of crystalline silicon (c-Si), using SOI wafers as the starting material and using bulk micromachining. The arrays are subsequently transformed into composite porous silicon-crystalline silicon cantilevers, using a unique vapor phase process tailored for providing a thin surface layer of porous silicon on one side only. This results in asymmetric cantilever arrays, with one side providing nano-structured porous large surface, which can be further coated with polymers, thus providing additional sensing capabilities and enhanced sensing. The c-Si cantilevers are vertically integrated with a bottom silicon die with electrodes allowing electrostatic actuation. Flip Chip bonding is used for the vertical integration. The readout is provided by a sensitive Capacitance to Digital Converter. The fabrication, processing and characterization results are reported. The reported study is aimed towards achieving miniature cantilever chips with integrated readout for sensing explosives and chemical warfare agents in the field.

Miniaturized force/torque sensor for in vivo measurements of tissue characteristics.

PubMed

Hessinger, M; Pilic, T; Werthschutzky, R; Pott, P P

2016-08-01

This paper presents the development of a surgical instrument to measure interaction forces/torques with organic tissue during operation. The focus is on the design progress of the sensor element, consisting of a spoke wheel deformation element with a diameter of 12 mm and eight inhomogeneous doped piezoresistive silicon strain gauges on an integrated full-bridge assembly with an edge length of 500 μm. The silicon chips are contacted to flex-circuits via flip chip and bonded on the substrate with a single component adhesive. A signal processing board with an 18 bit serial A/D converter is integrated into the sensor. The design concept of the handheld surgical sensor device consists of an instrument coupling, the six-axis sensor, a wireless communication interface and battery. The nominal force of the sensing element is 10 N and the nominal torque is 1 N-m in all spatial directions. A first characterization of the force sensor results in a maximal systematic error of 4.92 % and random error of 1.13 %.

Fitting tissue chips and microphysiological systems into the grand scheme of medicine, biology, pharmacology, and toxicology.

PubMed

Watson, David E; Hunziker, Rosemarie; Wikswo, John P

2017-10-01

Microphysiological systems (MPS), which include engineered organoids (EOs), single organ/tissue chips (TCs), and multiple organs interconnected to create miniature in vitro models of human physiological systems, are rapidly becoming effective tools for drug development and the mechanistic understanding of tissue physiology and pathophysiology. The second MPS thematic issue of Experimental Biology and Medicine comprises 15 articles by scientists and engineers from the National Institutes of Health, the IQ Consortium, the Food and Drug Administration, and Environmental Protection Agency, an MPS company, and academia. Topics include the progress, challenges, and future of organs-on-chips, dissemination of TCs into Pharma, children's health protection, liver zonation, liver chips and their coupling to interconnected systems, gastrointestinal MPS, maturation of immature cardiomyocytes in a heart-on-a-chip, coculture of multiple cell types in a human skin construct, use of synthetic hydrogels to create EOs that form neural tissue models, the blood-brain barrier-on-a-chip, MPS models of coupled female reproductive organs, coupling MPS devices to create a body-on-a-chip, and the use of a microformulator to recapitulate endocrine circadian rhythms. While MPS hardware has been relatively stable since the last MPS thematic issue, there have been significant advances in cell sourcing, with increased reliance on human-induced pluripotent stem cells, and in characterization of the genetic and functional cell state in MPS bioreactors. There is growing appreciation of the need to minimize perfusate-to-cell-volume ratios and respect physiological scaling of coupled TCs. Questions asked by drug developers are followed by an analysis of the potential value, costs, and needs of Pharma. Of highest value and lowest switching costs may be the development of MPS disease models to aid in the discovery of disease mechanisms; novel compounds including probes, leads, and clinical candidates; and mechanism of action of drug candidates. Impact statement Microphysiological systems (MPS), which include engineered organoids and both individual and coupled organs-on-chips and tissue chips, are a rapidly growing topic of research that addresses the known limitations of conventional cellular monoculture on flat plastic - a well-perfected set of techniques that produces reliable, statistically significant results that may not adequately represent human biology and disease. As reviewed in this article and the others in this thematic issue, MPS research has made notable progress in the past three years in both cell sourcing and characterization. As the field matures, currently identified challenges are being addressed, and new ones are being recognized. Building upon investments by the Defense Advanced Research Projects Agency, National Institutes of Health, Food and Drug Administration, Defense Threat Reduction Agency, and Environmental Protection Agency of more than $200 million since 2012 and sizable corporate spending, academic and commercial players in the MPS community are demonstrating their ability to meet the translational challenges required to apply MPS technologies to accelerate drug development and advance toxicology.

Fabrication of multijunction high voltage concentrator solar cells by integrated circuit technology

NASA Technical Reports Server (NTRS)

Valco, G. J.; Kapoor, V. J.; Evans, J. C., Jr.; Chai, A.-T.

1981-01-01

Standard integrated circuit technology has been developed for the design and fabrication of planar multijunction (PMJ) solar cell chips. Each 1 cm x 1 cm solar chip consisted of six n(+)/p, back contacted, internally series interconnected unit cells. These high open circuit voltage solar cells were fabricated on 2 ohm-cm, p-type 75 microns thick, silicon substrates. A five photomask level process employing contact photolithography was used to pattern for boron diffusions, phorphorus diffusions, and contact metallization. Fabricated devices demonstrated an open circuit voltage of 3.6 volts and a short circuit current of 90 mA at 80 AMl suns. An equivalent circuit model of the planar multi-junction solar cell was developed.

An analog VLSI chip emulating polarization vision of Octopus retina.

PubMed

Momeni, Massoud; Titus, Albert H

2006-01-01

Biological systems provide a wealth of information which form the basis for human-made artificial systems. In this work, the visual system of Octopus is investigated and its polarization sensitivity mimicked. While in actual Octopus retina, polarization vision is mainly based on the orthogonal arrangement of its photoreceptors, our implementation uses a birefringent micropolarizer made of YVO4 and mounted on a CMOS chip with neuromorphic circuitry to process linearly polarized light. Arranged in an 8 x 5 array with two photodiodes per pixel, each consuming typically 10 microW, this circuitry mimics both the functionality of individual Octopus retina cells by computing the state of polarization and the interconnection of these cells through a bias-controllable resistive network.

Fabrication of a Silicon Backshort Assembly for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

Radiation hardness and timing studies of a monolithic TowerJazz pixel design for the new ATLAS Inner Tracker

NASA Astrophysics Data System (ADS)

Riegel, C.; Backhaus, M.; Van Hoorne, J. W.; Kugathasan, T.; Musa, L.; Pernegger, H.; Riedler, P.; Schaefer, D.; Snoeys, W.; Wagner, W.

2017-01-01

A part of the upcoming HL-LHC upgrade of the ATLAS Detector is the construction of a new Inner Tracker. This upgrade opens new possibilities, but also presents challenges in terms of occupancy and radiation tolerance. For the pixel detector inside the inner tracker, hybrid modules containing passive silicon sensors and connected readout chips are presently used, but require expensive assembly techniques like fine-pitch bump bonding. Silicon devices fabricated in standard commercial CMOS technologies, which include part or all of the readout chain, are also investigated offering a reduced cost as they are cheaper per unit area than traditional silicon detectors. If they contain the full readout chain, as for a fully monolithic approach, there is no need for the expensive flip-chip assembly, resulting in a further cost reduction and material savings. In the outer pixel layers of the ATLAS Inner Tracker, the pixel sensors must withstand non-ionising energy losses of up to 1015 n/cm2 and offer a timing resolution of 25 ns or less. This paper presents test results obtained on a monolithic test chip, the TowerJazz 180nm Investigator, towards these specifications. The presented program of radiation hardness and timing studies has been launched to investigate this technology's potential for the new ATLAS Inner Tracker.

Modeling, Simulation and Design of Plasmonic Interconnects for On-Chip Signal Processing

DTIC Science & Technology

2011-02-14

integration and computation can be achieved by using the photonic detection devices such as the ultrafast photodectors and nanowire field transistors... infrared to optical frequencies, and their FDTD simulation results are shown in the middle diagram. In the right most diagram, the HSPICE simulation...FDTD simulation. The results tally very well to affirm that plasmonic nanowires can be simulated using circuit simulators like HSPICE to combine the

Monolithically Integrated High-β Nanowire Lasers on Silicon.

PubMed

Mayer, B; Janker, L; Loitsch, B; Treu, J; Kostenbader, T; Lichtmannecker, S; Reichert, T; Morkötter, S; Kaniber, M; Abstreiter, G; Gies, C; Koblmüller, G; Finley, J J

2016-01-13

Reliable technologies for the monolithic integration of lasers onto silicon represent the holy grail for chip-level optical interconnects. In this context, nanowires (NWs) fabricated using III-V semiconductors are of strong interest since they can be grown site-selectively on silicon using conventional epitaxial approaches. Their unique one-dimensional structure and high refractive index naturally facilitate low loss optical waveguiding and optical recirculation in the active NW-core region. However, lasing from NWs on silicon has not been achieved to date, due to the poor modal reflectivity at the NW-silicon interface. We demonstrate how, by inserting a tailored dielectric interlayer at the NW-Si interface, low-threshold single mode lasing can be achieved in vertical-cavity GaAs-AlGaAs core-shell NW lasers on silicon as measured at low temperature. By exploring the output characteristics along a detection direction parallel to the NW-axis, we measure very high spontaneous emission factors comparable to nanocavity lasers (β = 0.2) and achieve ultralow threshold pump energies ≤11 pJ/pulse. Analysis of the input-output characteristics of the NW lasers and the power dependence of the lasing emission line width demonstrate the potential for high pulsation rates ≥250 GHz. Such highly efficient nanolasers grown monolithically on silicon are highly promising for the realization of chip-level optical interconnects.

Design and fabrication of a foldable 3D silicon based package for solid state lighting applications

NASA Astrophysics Data System (ADS)

Sokolovskij, R.; Liu, P.; van Zeijl, H. W.; Mimoun, B.; Zhang, G. Q.

2015-05-01

Miniaturization of solid state lighting (SSL) luminaires as well as reduction of packaging and assembly costs are of prime interest for the SSL lighting industry. A novel silicon based LED package for lighting applications is presented in this paper. The proposed design consists of 5 rigid Si tiles connected by flexible polyimide hinges with embedded interconnects (ICs). Electrical, optical and thermal characteristics were taken into consideration during design. The fabrication process involved polyimide (PI) application and patterning, aluminium interconnect integration in the flexible hinge, LED reflector cavity formation and metalization followed by through wafer DRIE etching for chip formation and release. A method to connect chip front to backside without TSVs was also integrated into the process. Post-fabrication wafer level assembly included LED mounting and wirebond, phosphor-based colour conversion and silicone encapsulation. The package formation was finalized by vacuum assisted wrapping around an assembly structure to form a 3D geometry, which is beneficial for omnidirectional lighting. Bending tests were performed on the flexible ICs and optical performance at different temperatures was evaluated. It is suggested that 3D packages can be expanded to platforms for miniaturized luminaire applications by combining monolithic silicon integration and system-in-package (SiP) technologies.

Hot Chips and Hot Interconnects for High End Computing Systems

NASA Technical Reports Server (NTRS)

Saini, Subhash

2005-01-01

I will discuss several processors: 1. The Cray proprietary processor used in the Cray X1; 2. The IBM Power 3 and Power 4 used in an IBM SP 3 and IBM SP 4 systems; 3. The Intel Itanium and Xeon, used in the SGI Altix systems and clusters respectively; 4. IBM System-on-a-Chip used in IBM BlueGene/L; 5. HP Alpha EV68 processor used in DOE ASCI Q cluster; 6. SPARC64 V processor, which is used in the Fujitsu PRIMEPOWER HPC2500; 7. An NEC proprietary processor, which is used in NEC SX-6/7; 8. Power 4+ processor, which is used in Hitachi SR11000; 9. NEC proprietary processor, which is used in Earth Simulator. The IBM POWER5 and Red Storm Computing Systems will also be discussed. The architectures of these processors will first be presented, followed by interconnection networks and a description of high-end computer systems based on these processors and networks. The performance of various hardware/programming model combinations will then be compared, based on latest NAS Parallel Benchmark results (MPI, OpenMP/HPF and hybrid (MPI + OpenMP). The tutorial will conclude with a discussion of general trends in the field of high performance computing, (quantum computing, DNA computing, cellular engineering, and neural networks).

A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits.

PubMed

Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

2017-12-01

One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe 2 , a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

Spaceborne Processor Array

NASA Technical Reports Server (NTRS)

Chow, Edward T.; Schatzel, Donald V.; Whitaker, William D.; Sterling, Thomas

2008-01-01

A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.

A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits

NASA Astrophysics Data System (ADS)

Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M.; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K.; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

2017-12-01

One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe2, a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

Advanced packaging for Integrated Micro-Instruments

NASA Technical Reports Server (NTRS)

Lyke, James L.

1995-01-01

The relationship between packaging, microelectronics, and micro-electrical-mechanical systems (MEMS) is an important one, particularly when the edges of performance boundaries are pressed, as in the case of miniaturized systems. Packaging is a sort of physical backbone that enables the maximum performance of these systems to be realized, and the penalties imposed by conventional packing approaches is particularly limiting for MEMS devices. As such, advanced packaging approaches, such as multi-chip modules (MCM's) have been touted as a true means of electronic 'enablement' for a variety of application domains. Realizing an optimum system of packaging, however, in not as simple as replacing a set of single chip packages with a substrate of interconnections. Research at Phillips Laboratory has turned up a number of integrating options in the two- and three-dimensional rending of miniature systems with physical interconnection structures with intrinsically high performance. Not only do these structures motivate the redesign of integrated circuits (IC's) for lower power, but they possess interesting features that provide a framework for the direct integration of MEMS devices. Cost remains a barrier to the application of MEMS devices, even in space systems. Several innovations are suggested that will result in lower cost and more rapid cycle time. First, the novelty of a 'constant floor plan' MCM which encapsulates a variety of commonly used components into a stockable, easily customized assembly is discussed. Next, the use of low-cost substrates is examined. The anticipated advent of ultra-high density interconnect (UHDI) is suggested as the limit argument of advanced packaging. Finally, the concept of a heterogeneous 3-D MCM system is outlined that allows for the combination of different compatible packaging approaches into a uniformly dense structure that could also include MEMS-based sensors.

Design, fabrication, and characterization of high density silicon photonic components

NASA Astrophysics Data System (ADS)

Jones, Adam Michael

Our burgeoning appetite for data relentlessly demands exponential scaling of computing and communications resources leading to an overbearing and ever-present drive to improve eciency while reducing on-chip area even as photonic components expand to ll application spaces no longer satised by their electronic counterparts. With a high index contrast, low optical loss, and compatibility with the CMOS fabrication infrastructure, silicon-on-insulator technology delivers a mechanism by which ecient, sub-micron waveguides can be fabricated while enabling monolithic integration of photonic components and their associated electronic infrastructure. The result is a solution leveraging the superior bandwidth of optical signaling on a platform capable of delivering the optical analogue to Moore's Law scaling of transistor density. Device size is expected to end Moore's Law scaling in photonics as Maxwell's equations limit the extent to which this parameter may be reduced. The focus of the work presented here surrounds photonic device miniaturization and the development of 3D optical interconnects as approaches to optimize performance in densely integrated optical interconnects. In this dissertation, several technological barriers inhibiting widespread adoption of photonics in data communications and telecommunications are explored. First, examination of loss and crosstalk performance in silicon nitride over SOI waveguide crossings yields insight into the feasibility of 3D optical interconnects with the rst experimental analysis of such a structure presented herein. A novel measurement platform utilizing a modied racetrack resonator is then presented enabling extraction of insertion loss data for highly ecient structures while requiring minimal on-chip area. Finally, pioneering work in understanding the statistical nature of doublet formation in microphotonic resonators is delivered with the resulting impact on resonant device design detailed.

Optical interconnects for satellite payloads: overview of the state-of-the-art

NASA Astrophysics Data System (ADS)

Vervaeke, Michael; Debaes, Christof; Van Erps, Jürgen; Karppinen, Mikko; Tanskanen, Antti; Aalto, Timo; Harjanne, Mikko; Thienpont, Hugo

2010-05-01

The increased demand of broadband communication services like High Definition Television, Video On Demand, Triple Play, fuels the technologies to enhance the bandwidth of individual users towards service providers and hence the increase of aggregate bandwidths on terrestial networks. Optical solutions clearly leverage the bandwidth appetite easily whereas electrical interconnection schemes require an ever-increasing effort to counteract signal distortions at higher bitrates. Dense wavelength division multiplexing and all-optical signal regeneration and switching solve the bandwidth demands of network trunks. Fiber-to-the-home, and fiber-to-the-desk are trends towards providing individual users with greatly increased bandwidth. Operators in the satellite telecommunication sector face similar challenges fuelled by the same demands as for their terrestial counterparts. Moreover, the limited number of orbital positions for new satellites set the trend for an increase in payload datacommunication capacity using an ever-increasing number of complex multi-beam active antennas and a larger aggregate bandwidth. Only satellites with very large capacity, high computational density and flexible, transparent fully digital payload solutions achieve affordable communication prices. To keep pace with the bandwidth and flexibility requirements, designers have to come up with systems requiring a total digital througput of a few Tb/s resulting in a high power consuming satellite payload. An estimated 90 % of the total power consumption per chip is used for the off-chip communication lines. We have undertaken a study to assess the viability of optical datacommunication solutions to alleviate the demands regarding power consumption and aggregate bandwidth imposed on future satellite communication payloads. The review on optical interconnects given here is especially focussed on the demands of the satellite communication business and the particular environment in which the optics have to perform their functionality: space.

Thermo-mechanical properties and integrity of metallic interconnects in microelectronics

NASA Astrophysics Data System (ADS)

Ege, Efe Sinan

In this dissertation, combined numerical (Finite Element Method) and experimental efforts were undertaken to study thermo-mechanical behavior in microelectronic devices. Interconnects, including chip-level metallization and package-level solder joints, are used to join many of the circuit parts in modern equipment. The dissertation is structured into six independent studies after the introductory chapter. The first two studies focus on thermo-mechanical fatigue of solder joints. Thermo-mechanical fatigue, in the form of damage along a microstructurally coarsened region in tin-lead solder, is analyzed along with the effects of intermetallic morphology. Also, lap-shear testing is modeled to characterize the joint and to investigate the validity of experimental data from different solder and substrate geometries. In the third study, the effects of pre-machined holes on strain localization and overall ductility in bulk eutectic tin-lead alloy is examined. Finite element analyses, taking into account the viscoplastic response, were carried out to provide a mechanistic rationale to corroborate the experimental findings. The fourth study concerns chip-level copper interconnects. Various combinations of oxide and polymer-based low-k dielectric schemes, with and without the thin barrier layers surrounding the Cu line, are considered. Attention is devoted to the thermal stress and strain fields and their dependency on material properties, geometry, and modeling details. This study is followed by a chapter on atomistics of interface-mediated plasticity in thin metallic films. The objective is to gain fundamental insight into the underlying mechanisms affecting the mechanical response of nanoscale thin films. The final study investigates the effect of microstructural heterogeneity on indentation response, for the purpose of raising awareness of the uncertainties involved in applying indentation techniques in probing mechanical properties of miniaturized devices.

Design Fabrication and Characterization of High Density Silicon Photonic Components

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jones, Adam

2015-02-01

Our burgeoning appetite for data relentlessly demands exponential scaling of computing and communications resources leading to an overbearing and ever-present drive to improve e ciency while reducing on-chip area even as photonic components expand to ll application spaces no longer satis ed by their electronic counterparts. With a high index contrast, low optical loss, and compatibility with the CMOS fabrication infrastructure, silicon-on-insulator technology delivers a mechanism by which e cient, sub-micron waveguides can be fabricated while enabling monolithic integration of photonic components and their associated electronic infrastructure. The result is a solution leveraging the superior bandwidth of optical signaling onmore » a platform capable of delivering the optical analogue to Moore's Law scaling of transistor density. Device size is expected to end Moore's Law scaling in photonics as Maxwell's equations limit the extent to which this parameter may be reduced. The focus of the work presented here surrounds photonic device miniaturization and the development of 3D optical interconnects as approaches to optimize performance in densely integrated optical interconnects. In this dissertation, several technological barriers inhibiting widespread adoption of photonics in data communications and telecommunications are explored. First, examination of loss and crosstalk performance in silicon nitride over SOI waveguide crossings yields insight into the feasibility of 3D optical interconnects with the rst experimental analysis of such a structure presented herein. A novel measurement platform utilizing a modi ed racetrack resonator is then presented enabling extraction of insertion loss data for highly e cient structures while requiring minimal on-chip area. Finally, pioneering work in understanding the statistical nature of doublet formation in microphotonic resonators is delivered with the resulting impact on resonant device design detailed.« less

Reliability and Characteristics of Wafer-Level Chip-Scale Packages under Current Stress

NASA Astrophysics Data System (ADS)

Chen, Po-Ying; Kung, Heng-Yu; Lai, Yi-Shao; Hsiung Tsai, Ming; Yeh, Wen-Kuan

2008-02-01

In this work, we present a novel approach and method for elucidating the characteristics of wafer-level chip-scale packages (WLCSPs) for electromigration (EM) tests. The die in WLCSP was directly attached to the substrate via a soldered interconnect. The shrinking of the area of the die that is available for power, and the solder bump also shrinks the volume and increases the density of electrons for interconnect efficiency. The bump current density now approaches to 106 A/cm2, at which point the EM becomes a significant reliability issue. As known, the EM failure depends on numerous factors, including the working temperature and the under bump metallization (UBM) thickness. A new interconnection geometry is adopted extensively with moderate success in overcoming larger mismatches between the displacements of components during current and temperature changes. Both environments and testing parameters for WLCSP are increasingly demanded. Although failure mechanisms are considered to have been eliminated or at least made manageable, new package technologies are again challenging its process, integrity and reliability. WLCSP technology was developed to eliminate the need for encapsulation to ensure compatibility with smart-mount technology (SMT). The package has good handing properties but is now facing serious reliability problems. In this work, we investigated the reliability of a WLCSP subjected to different accelerated current stressing conditions at a fixed ambient temperature of 125 °C. A very strong correlation exists between the mean time to failure (MTTF) of the WLCSP test vehicle and the mean current density that is carried by a solder joint. A series of current densities were applied to the WLCSP architecture; Black's power law was employed in a failure mode simulation. Additionally, scanning electron microscopy (SEM) was adopted to determine the differences existing between high- and low-current-density failure modes.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

Off-line, built-in test techniques for VLSI circuits

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Sievers, M. W.

1982-01-01

It is shown that the use of redundant on-chip circuitry improves the testability of an entire VLSI circuit. In the study described here, five techniques applied to a two-bit ripple carry adder are compared. The techniques considered are self-oscillation, self-comparison, partition, scan path, and built-in logic block observer. It is noted that both classical stuck-at faults and nonclassical faults, such as bridging faults (shorts), stuck-on x faults where x may be 0, 1, or vary between the two, and parasitic flip-flop faults occur in IC structures. To simplify the analysis of the testing techniques, however, a stuck-at fault model is assumed.

Research on defects inspection of solder balls based on eddy current pulsed thermography.

PubMed

Zhou, Xiuyun; Zhou, Jinlong; Tian, Guiyun; Wang, Yizhe

2015-10-13

In order to solve tiny defect detection for solder balls in high-density flip-chip, this paper proposed feasibility study on the effect of detectability as well as classification based on eddy current pulsed thermography (ECPT). Specifically, numerical analysis of 3D finite element inductive heat model is generated to investigate disturbance on the temperature field for different kind of defects such as cracks, voids, etc. The temperature variation between defective and non-defective solder balls is monitored for defects identification and classification. Finally, experimental study is carried on the diameter 1mm tiny solder balls by using ECPT and verify the efficacy of the technique.

Cu Pillar Low Temperature Bonding and Interconnection Technology of for 3D RF Microsystem

NASA Astrophysics Data System (ADS)

Shi, G. X.; Qian, K. Q.; Huang, M.; Yu, Y. W.; Zhu, J.

2018-03-01

In this paper 3D interconnects technologies used Cu pillars are discussed with respect to RF microsystem. While 2.5D Si interposer and 3D packaging seem to rely to cu pillars for the coming years, RF microsystem used the heterogeneous chip such as GaAs integration with Si interposers should be at low temperature. The pillars were constituted by Cu (2 micron) -Ni (2 micron) -Cu (3 micron) -Sn (1 micron) multilayer metal and total height is 8 micron on the front-side of the wafer by using electroplating. The wafer backside Cu pillar is obtained by temporary bonding, thinning and silicon surface etching. The RF interposers are stacked by Cu-Sn eutectic bonding at 260 °C. Analyzed the reliability of different pillar bonding structure.

3D interconnect metrology in CMS/ITRI

NASA Astrophysics Data System (ADS)

Ku, Y. S.; Shyu, D. M.; Hsu, W. T.; Chang, P. Y.; Chen, Y. C.; Pang, H. L.

2011-05-01

Semiconductor device packaging technology is rapidly advancing, in response to the demand for thinner and smaller electronic devices. Three-dimensional chip/wafer stacking that uses through-silicon vias (TSV) is a key technical focus area, and the continuous development of this novel technology has created a need for non-contact characterization. Many of these challenges are novel to the industry due to the relatively large variety of via sizes and density, and new processes such as wafer thinning and stacked wafer bonding. This paper summarizes the developing metrology that has been used during via-middle & via-last TSV process development at EOL/ITRI. While there is a variety of metrology and inspection applications for 3D interconnect processing, the main topics covered here are via CD/depth measurement, thinned wafer inspection and wafer warpage measurement.

Packaging Technologies for High Temperature Electronics and Sensors

NASA Technical Reports Server (NTRS)

Chen, Liangyu; Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Spry, David J.; Meredith, Roger D.

2013-01-01

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Photonic crystal lasers using wavelength-scale embedded active region

NASA Astrophysics Data System (ADS)

Matsuo, Shinji; Sato, Tomonari; Takeda, Koji; Shinya, Akihiko; Nozaki, Kengo; Kuramochi, Eiichi; Taniyama, Hideaki; Notomi, Masaya; Fujii, Takuro; Hasebe, Koichi; Kakitsuka, Takaaki

2014-01-01

Lasers with ultra-low operating energy are desired for use in chip-to-chip and on-chip optical interconnects. If we are to reduce the operating energy, we must reduce the active volume. Therefore, a photonic crystal (PhC) laser with a wavelength-scale cavity has attracted a lot of attention because a PhC provides a large Q-factor with a small volume. To improve this device's performance, we employ an embedded active region structure in which the wavelength-scale active region is buried with an InP PhC slab. This structure enables us to achieve effective confinement of both carriers and photons, and to improve the thermal resistance of the device. Thus, we have obtained a large external differential quantum efficiency of 55% and an output power of -10 dBm by optical pumping. For electrical pumping, we use a lateral p-i-n structure that employs Zn diffusion and Si ion implantation for p-type and n-type doping, respectively. We have achieved room-temperature continuous-wave operation with a threshold current of 7.8 µA and a maximum 3 dB bandwidth of 16.2 GHz. The results of an experimental bit error rate measurement with a 10 Gbit s-1 NRZ signal reveal the minimum operating energy for transferring a single bit of 5.5 fJ. These results show the potential of this laser to be used for very short reach interconnects. We also describe the optimal design of cavity quality (Q) factor in terms of achieving a large output power with a low operating energy using a calculation based on rate equations. When we assume an internal absorption loss of 20 cm-1, the optimized coupling Q-factor is 2000.

Graphene-Boron Nitride Heterostructure Based Optoelectronic Devices for On-Chip Optical Interconnects

NASA Astrophysics Data System (ADS)

Gao, Yuanda

Graphene has emerged as an appealing material for a variety of optoelectronic applications due to its unique electrical and optical characteristics. In this thesis, I will present recent advances in integrating graphene and graphene-boron nitride (BN) heterostructures with confined optical architectures, e.g. planar photonic crystal (PPC) nanocavities and silicon channel waveguides, to make this otherwise weakly absorbing material optically opaque. Based on these integrations, I will further demonstrate the resulting chip-integrated optoelectronic devices for optical interconnects. After transferring a layer of graphene onto PPC nanocavities, spectral selectivity at the resonance frequency and orders-of-magnitude enhancement of optical coupling with graphene have been observed in infrared spectrum. By applying electrostatic potential to graphene, electro-optic modulation of the cavity reflection is possible with contrast in excess of 10 dB. And furthermore, a novel and complex modulator device structure based on the cavity-coupled and BN-encapsulated dual-layer graphene capacitor is demonstrated to operate at a speed of 1.2 GHz. On the other hand, an enhanced broad-spectrum light-graphene interaction coupled with silicon channel waveguides is also demonstrated with ?0.1 dB/?m transmission attenuation due to graphene absorption. A waveguide-integrated graphene photodetector is fabricated and shown 0.1 A/W photoresponsivity and 20 GHz operation speed. An improved version of a similar photodetector using graphene-BN heterostructure exhibits 0.36 A/W photoresponsivity and 42 GHz response speed. The integration of graphene and graphene-BN heterostructures with nanophotonic architectures promises a new generation of compact, energy-efficient, high-speed optoelectronic device concepts for on-chip optical communications that are not yet feasible or very difficult to realize using traditional bulk semiconductors.

Organs-on-a-chip: Current applications and consideration points for in vitro ADME-Tox studies.

PubMed

Ishida, Seiichi

2018-02-01

Assay systems using in vitro cultured cells are increasingly applied for evaluation of the efficacy, safety, and toxicity of drug candidates. In vitro cell-based assays have two main applications in the drug discovery process: searching for a compound that is effective against the target disease (seed investigation) and confirmation of safety during use of the identified compounds (safety assessment). Currently available in vitro cell-based assays have been designed to evaluate the efficacy and toxicity in single organs, but the in vivo pharmacokinetics and pharmacodynamics of the administered drug candidates have not been considered. Thus, an evaluation system that interconnects cell culture units, one of which has appropriate drug metabolism activities and the other assesses the efficacy and toxicity of compounds, is needed. Accordingly, the in vitro ADME-Tox culture system known as organs-on-a-chip has been proposed. In this review, after introducing the organs-on-a-chip system, the evaluation of enterohepatic circulation and the gut-liver axis relationship will be presented as an example of the application of the organs-on-a-chip system for ADME studies based on inter-organ network. Additionally, the functions required for the organs-on-a-chip system and the necessity of standardization of cells mounted on the chip system will be discussed. Copyright © 2018 The Japanese Society for the Study of Xenobiotics. Published by Elsevier Ltd. All rights reserved.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Technical Reports Server (NTRS)

Sewell, James S.; Bozada, Christopher A.

1994-01-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Astrophysics Data System (ADS)

Sewell, James S.; Bozada, Christopher A.

1994-02-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Polarized electroluminescence from edge-emission organic light emitting devices

NASA Astrophysics Data System (ADS)

Ran, G. Z.; Jiang, D. F.

2011-01-01

We report the experimental observation and measurement of the polarized electroluminescence from an edge-emission Si based- organic light emitting device (OLED) with a Sm/Au or Sm/Ag cathode. Light collected from the OLED edge comes from the scattering of the surface plasmon polaritons (SPPs) at the device boundary. This experiment shows that such Si-OLED can be an electrically excited SPP source on a silicon chip for optical interconnect based on SPPs.

Nanotubes May Break Through "Chip Wall"

NASA Technical Reports Server (NTRS)

Laufenberg, Larry

2003-01-01

In 1965, just four years after the first planar integrated circuit (IC) was discovered, Cordon Moore observed that the number of transistors per integrated circuit had grown exponentially. He predicted that this would continue, and the media soon began to call his prophesy "Moore's Law" For nearly forty years, Moore's Law has been validated by the technological progress achieved in the semiconductor industry. Now, however, industry experts are warning of a "Red Brick Wall" that may soon block the continued scaling predicted by by Moore's Law. The "red bricks" in the wall are those areas of technical challenge for which no known manufacturable solution exists. One such "brick" is the challenge of finding a new material and processing technology to replace the metals used today to interconnect transistors on a chip.

Ge-Photodetectors for Si-Based Optoelectronic Integration

PubMed Central

Wang, Jian; Lee, Sungjoo

2011-01-01

High speed photodetectors are a key building block, which allow a large wavelength range of detection from 850 nm to telecommunication standards at optical fiber band passes of 1.3–1.55 μm. Such devices are key components in several applications such as local area networks, board to board, chip to chip and intrachip interconnects. Recent technological achievements in growth of high quality SiGe/Ge films on Si wafers have opened up the possibility of low cost Ge-based photodetectors for near infrared communication bands and high resolution spectral imaging with high quantum efficiencies. In this review article, the recent progress in the development and integration of Ge-photodetectors on Si-based photonics will be comprehensively reviewed, along with remaining technological issues to be overcome and future research trends. PMID:22346598

Evaluation of hybrid polymers for high-precision manufacturing of 3D optical interconnects by two-photon absorption lithography

NASA Astrophysics Data System (ADS)

Schleunitz, A.; Klein, J. J.; Krupp, A.; Stender, B.; Houbertz, R.; Gruetzner, G.

2017-02-01

The fabrication of optical interconnects has been widely investigated for the generation of optical circuit boards. Twophoton absorption (TPA) lithography (or high-precision 3D printing) as an innovative production method for direct manufacture of individual 3D photonic structures gains more and more attention when optical polymers are employed. In this regard, we have evaluated novel ORMOCER-based hybrid polymers tailored for the manufacture of optical waveguides by means of high-precision 3D printing. In order to facilitate future industrial implementation, the processability was evaluated and the optical performance of embedded waveguides was assessed. The results illustrate that hybrid polymers are not only viable consumables for industrial manufacture of polymeric micro-optics using generic processes such as UV molding. They also are potential candidates to fabricate optical waveguide systems down to the chip level where TPA-based emerging manufacturing techniques are engaged. Hence, it is shown that hybrid polymers continue to meet the increasing expectations of dynamically growing markets of micro-optics and optical interconnects due to the flexibility of the employed polymer material concept.

Silicon quantum processor with robust long-distance qubit couplings.

PubMed

Tosi, Guilherme; Mohiyaddin, Fahd A; Schmitt, Vivien; Tenberg, Stefanie; Rahman, Rajib; Klimeck, Gerhard; Morello, Andrea

2017-09-06

Practical quantum computers require a large network of highly coherent qubits, interconnected in a design robust against errors. Donor spins in silicon provide state-of-the-art coherence and quantum gate fidelities, in a platform adapted from industrial semiconductor processing. Here we present a scalable design for a silicon quantum processor that does not require precise donor placement and leaves ample space for the routing of interconnects and readout devices. We introduce the flip-flop qubit, a combination of the electron-nuclear spin states of a phosphorus donor that can be controlled by microwave electric fields. Two-qubit gates exploit a second-order electric dipole-dipole interaction, allowing selective coupling beyond the nearest-neighbor, at separations of hundreds of nanometers, while microwave resonators can extend the entanglement to macroscopic distances. We predict gate fidelities within fault-tolerance thresholds using realistic noise models. This design provides a realizable blueprint for scalable spin-based quantum computers in silicon.Quantum computers will require a large network of coherent qubits, connected in a noise-resilient way. Tosi et al. present a design for a quantum processor based on electron-nuclear spins in silicon, with electrical control and coupling schemes that simplify qubit fabrication and operation.

The Use of Metal Filled Via Holes for Improving Isolation in LTCC RF and Wireless Multichip Packages

NASA Technical Reports Server (NTRS)

Ponchak, George E.; Chun, Donghoon; Yook, Jong-Gwan; Katehi, Linda P. B.

1999-01-01

LTCC MCMs (Low Temperature Cofired Ceramic MultiChip Module) for RF and wireless systems often use metal filled via holes to improve isolation between the stripline and microstrip interconnects. In this paper, results from a 3D-FEM electromagnetic characterization of microstrip and stripline interconnects with metal filled via fences for isolation are presented. It is shown that placement of a via hole fence closer than three times the substrate height to the transmission lines increases radiation and coupling. Radiation loss and reflections are increased when a short via fence is used in areas suspected of having high radiation. Also, via posts should not be separated by more than three times the substrate height for low radiation loss, coupling, and suppression of higher order modes in a package.

A flexible skin patch for continuous physiological monitoring of mental disorders

NASA Astrophysics Data System (ADS)

Jang, Won Ick; Lee, Bong Kuk; Ryu, Jin Hwa; Baek, In-Bok; Yu, Han Young; Kim, Seunghwan

2017-10-01

In this study, we have newly developed a flexible adhesive skin patch of electrocardiogram (ECG) device for continuous physiological monitoring of mental disorders. In addition, this flexible patch did not cause any damage to the skin even after 24 hours attachment. We have also suggested the possibility of novel interconnection for copper film on polyimide and polydimethylsiloxane (PDMS) layers of the flexible patch. Self-align and soldering of IC chips such as resistor between metal pads on flexible skin patch have also successfully fabricated for 5 min at 180 °C in vacuum oven. Low temperature interconnection technology based on a Sn42/Bi58 solder was also developed for flexible ECG devices. As a result, we can monitor the mental health status through a comprehensive analysis of biological signals from flexible ECG devices.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bauer, R.; Ebersberger, B.; Kupfer, C.

SnAg solder bump is one bump type which is used to replace eutectic SnPb bumps. In this work tests have been done to characterize the reliability properties of this bump type. Electromigration (EM) tests, which were accelerated by high current and high temperature and high temperature storage (HTS) tests were performed. It was found that the reliability properties are sensitive to the material combinations in the interconnect stack. The interconnect stack includes substrate pad, pad finish, bump, underbump metallization (UBM) and the chip pad. Therefore separate test groups for SnAg bumps on Cu substrate pads with organic solderability preservative (OSP)more » finish and the identical bumps on pads with Ni/Au finish were used. In this paper the reliability test results and the corresponding failure analysis are presented. Some explanations about the differences in formation of intermetallic compounds (IMCs) are given.« less

Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays.

PubMed

Ciçek, Ihsan; Bozkurt, Ayhan; Karaman, Mustafa

2005-12-01

Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMUT element, we developed an electrical CMUT model with parameters derived through finite element analysis, and performed both the pre- and postlayout verification. An experimental chip consisting of 4 X 4 array of the designed circuit cells, each cell occupying a 200 X 200 microm2 area, was formed for the initial test studies and scheduled for fabrication in 0.8 microm, 50 V CMOS technology. The designed circuit is suitable for integration with CMUT arrays through flip-chip bonding and the CMUT-on-CMOS process.

Subwavelength engineered fiber-to-chip silicon-on-sapphire interconnects for mid-infrared applications (Conference Presentation)

NASA Astrophysics Data System (ADS)

Alonso-Ramos, Carlos; Han, Zhaohong; Le Roux, Xavier; Lin, Hongtao; Singh, Vivek; Lin, Pao Tai; Tan, Dawn; Cassan, Eric; Marris-Morini, Delphine; Vivien, Laurent; Wada, Kazumi; Hu, Juejun; Agarwal, Anuradha; Kimerling, Lionel C.

2016-05-01

The mid-Infrared wavelength range (2-20 µm), so-called fingerprint region, contains the very sharp vibrational and rotational resonances of many chemical and biological substances. Thereby, on-chip absorption-spectrometry-based sensors operating in the mid-Infrared (mid-IR) have the potential to perform high-precision, label-free, real-time detection of multiple target molecules within a single sensor, which makes them an ideal technology for the implementation of lab-on-a-chip devices. Benefiting from the great development realized in the telecom field, silicon photonics is poised to deliver ultra-compact efficient and cost-effective devices fabricated at mass scale. In addition, Si is transparent up to 8 µm wavelength, making it an ideal material for the implementation of high-performance mid-IR photonic circuits. The silicon-on-insulator (SOI) technology, typically used in telecom applications, relies on silicon dioxide as bottom insulator. Unfortunately, silicon dioxide absorbs light beyond 3.6 µm, limiting the usability range of the SOI platform for the mid-IR. Silicon-on-sapphire (SOS) has been proposed as an alternative solution that extends the operability region up to 6 µm (sapphire absorption), while providing a high-index contrast. In this context, surface grating couplers have been proved as an efficient means of injecting and extracting light from mid-IR SOS circuits that obviate the need of cleaving sapphire. However, grating couplers typically have a reduced bandwidth, compared with facet coupling solutions such as inverse or sub-wavelength tapers. This feature limits their feasibility for absorption spectroscopy applications that may require monitoring wide wavelength ranges. Interestingly, sub-wavelength engineering can be used to substantially improve grating coupler bandwidth, as demonstrated in devices operating at telecom wavelengths. Here, we report on the development of fiber-to-chip interconnects to ZrF4 optical fibers and integrated SOS circuits with 500 nm thick Si, operating around 3.8 µm wavelength. Results on facet coupling and sub-wavelength engineered grating coupler solutions in the mid-IR regime will be compared.

Silicon-based products and solutions

NASA Astrophysics Data System (ADS)

Painchaud, Y.; Poulin, M.; Pelletier, F.; Latrasse, C.; Gagné, J.-F.; Savard, S.; Robidoux, G.; Picard, M.-.; Paquet, S.; Davidson, C.-.; Pelletier, M.; Cyr, M.; Paquet, C.; Guy, M.; Morsy-Osman, M.; Chagnon, M.; Plant, D. V.

2014-03-01

TeraXion started silicon photonics activities aiming at developing building blocks for new products and customized solutions. Passive and active devices have been developed including MMI couplers, power splitters, Bragg grating filters, high responsivity photodetectors, high speed modulators and variable optical attenuators. Packaging solutions including fiber attachment and hybrid integration using flip-chip were also developed. More specifically, a compact packaged integrated coherent receiver has been realized. Good performances were obtained as demonstrated by our system tests results showing transmission up to 4800 km with BER below hard FEC threshold. The package size is small but still limited by the electrical interface. Migrating to more compact RF interface would allow realizing the full benefit of this technology.

Large Area MEMS Based Ultrasound Device for Cancer Detection.

PubMed

Wodnicki, Robert; Thomenius, Kai; Hooi, Fong Ming; Sinha, Sumedha P; Carson, Paul L; Lin, Der-Song; Zhuang, Xuefeng; Khuri-Yakub, Pierre; Woychik, Charles

2011-08-21

We present image results obtained using a prototype ultrasound array which demonstrates the fundamental architecture for a large area MEMS based ultrasound device for detection of breast cancer. The prototype array consists of a tiling of capacitive Micro-Machined Ultrasound Transducers (cMUTs) which have been flip-chip attached to a rigid organic substrate. The pitch on the cMUT elements is 185 um and the operating frequency is nominally 9 MHz. The spatial resolution of the new probe is comparable to production PZT probes, however the sensitivity is reduced by conditions that should be correctable. Simulated opposed-view image registration and Speed of Sound volume reconstruction results for ultrasound in the mammographic geometry are also presented.

Physics of Failure Analysis of Xilinx Flip Chip CCGA Packages: Effects of Mission Environments on Properties of LP2 Underfill and ATI Lid Adhesive Materials

NASA Technical Reports Server (NTRS)

Suh, Jong-ook

2013-01-01

The Xilinx Virtex 4QV and 5QV (V4 and V5) are next-generation field-programmable gate arrays (FPGAs) for space applications. However, there have been concerns within the space community regarding the non-hermeticity of V4/V5 packages; polymeric materials such as the underfill and lid adhesive will be directly exposed to the space environment. In this study, reliability concerns associated with the non-hermeticity of V4/V5 packages were investigated by studying properties and behavior of the underfill and the lid adhesvie materials used in V4/V5 packages.

Method to Improve Indium Bump Bonding via Indium Oxide Removal Using a Multi-Step Plasma Process

NASA Technical Reports Server (NTRS)

Dickie, Matthew R. (Inventor); Nikzad, Shouleh (Inventor); Greer, H. Frank (Inventor); Jones, Todd J. (Inventor); Vasquez, Richard P. (Inventor); Hoenk, Michael E. (Inventor)

2012-01-01

A process for removing indium oxide from indium bumps in a flip-chip structure to reduce contact resistance, by a multi-step plasma treatment. A first plasma treatment of the indium bumps with an argon, methane and hydrogen plasma reduces indium oxide, and a second plasma treatment with an argon and hydrogen plasma removes residual organics. The multi-step plasma process for removing indium oxide from the indium bumps is more effective in reducing the oxide, and yet does not require the use of halogens, does not change the bump morphology, does not attack the bond pad material or under-bump metallization layers, and creates no new mechanisms for open circuits.

Development of a RadFET Linear Array for Intracavitary in vivo Dosimetry During External Beam Radiotherapy and Brachytherapy

NASA Astrophysics Data System (ADS)

Price, R. A.; Benson, C.; Joyce, M. J.; Rodgers, K.

2004-08-01

We present the details of a new linear array dosimeter consisting of a chain of semiconductors mounted on an ultra-thin (50 /spl mu/m thick) flexible substrate and housed in an intracavitary catheter. The semiconductors, manufactured by NMRC Cork, have not been packaging and incorporate a passivation layer that allows them to be mounted on the substrate using flip-chip-bonding. This paper reports, for the first time, the construction of a multiple (ten) detector array suited to in vivo dosimetry in the rectum, esophagus and vagina during external beam radiotherapy, as well as being adaptable to in vivo dosimetry during brachytherapy and diagnostic radiology.

Platform technologies for hybrid optoelectronic integration and packaging

NASA Astrophysics Data System (ADS)

Datta, Madhumita

In order to bring fiber-optics closer to individual home and business services, the optical network components have to be inexpensive and reliable. Integration and packaging of optoelectronic devices holds the key to high-volume low-cost component manufacturing. The goal of this dissertation is to propose, study, and demonstrate various ways to integrate optoelectronic devices on a packaging platform to implement cost-effective, functional optical modules. Two types of hybrid integration techniques have been proposed: flip-chip solder bump bonding for high-density two-dimensional array packaging of surface-emitting devices, and solder preform bonding for fiber-coupled edge-emitting semiconductor devices. For flip-chip solder bump bonding, we developed a simple, inexpensive remetallization process called "electroless plating", which converts the aluminum bond pads of foundry-made complementary metal oxide semiconductor (CMOS) chips into solder-bondable and wire-bondable gold surfaces. We have applied for a patent on this remetallization technique. For fiber-pigtailed edge-emitting laser modules, we have studied the coupling characteristics of different types of lensed single-mode fibers including semispherically lensed fiber, cylindrically lensed fiber and conically lensed fiber. We have experimentally demonstrated 66% coupling efficiency with semispherically lensed fiber and 50% efficiency with conically lensed fibers. We have proposed and designed a packaging platform on which lensed fibers can be actively aligned to a laser and solder-attached reliably to the platform so that the alignment is retained. We have designed thin-film nichrome heaters on fused quartz platforms as local heat source to facilitate on-board solder alignment and attachment of fiber. The thermal performance of the heaters was simulated using finite element analysis tool ANSYS prior to fabrication. Using the heater's reworkability advantage, we have estimated the shift of the fiber due to solder shrinkage and introduced a pre-correction in the alignment process to restore optimum coupling efficiency close to 50% with conically lensed fibers. We have applied for a patent on this unique active alignment method through the University of Maryland's Technology Commercialization Office. Although we have mostly concentrated on active alignment platforms, we have proposed the idea of combining the passive alignment advantages of silicon optical benches to the on-board heater-assisted active alignment technique. This passive-active alignment process has the potential of cost-effective array packaging of edge-emitting devices.

Technology Description Sheets form the AMC 1990 Technology Expo Held in Aberdeen Proving Ground, Maryland on 1-4 October 1990

DTIC Science & Technology

1990-10-04

emission signals) " Compactness (can be hand-held). The ISOPADS was demonstrated to troop units at the Army Training Command, Grafenwoehr , West...To be controlled, the microwave chips and modules must be interconnected with remotely located components and subsystems. Utilizing metallic cables...forward observer systcm being developed for use in situations too dangerous for soldiers. such as nuclear- contaminated areas or in support of a minefield

A Boundary Scan Test Vehicle for Direct Chip Attach Testing

NASA Technical Reports Server (NTRS)

Parsons, Heather A.; DAgostino, Saverio; Arakaki, Genji

2000-01-01

To facilitate the new faster, better and cheaper spacecraft designs, smaller more mass efficient avionics and instruments are using higher density electronic packaging technologies such as direct chip attach (DCA). For space flight applications, these technologies need to have demonstrated reliability and reasonably well defined fabrication and assembly processes before they will be accepted as baseline designs in new missions. As electronics shrink in size, not only can repair be more difficult, but 49 probing" circuitry can be very risky and it becomes increasingly more difficult to identify the specific source of a problem. To test and monitor these new technologies, the Direct Chip Attach Task, under NASA's Electronic Parts and Packaging Program (NEPP), chose the test methodology of boundary scan testing. The boundary scan methodology was developed for interconnect integrity and functional testing at hard to access electrical nodes. With boundary scan testing, active devices are used and failures can be identified to the specific device and lead. This technology permits the incorporation of "built in test" into almost any circuit and thus gives detailed test access to the highly integrated electronic assemblies. This presentation will describe boundary scan, discuss the development of the boundary scan test vehicle for DCA and current plans for testing of direct chip attach configurations.

Gbps wireless transceivers for high bandwidth interconnections in distributed cyber physical systems

NASA Astrophysics Data System (ADS)

Saponara, Sergio; Neri, Bruno

2015-05-01

In Cyber Physical Systems there is a growing use of high speed sensors like photo and video camera, radio and light detection and ranging (Radar/Lidar) sensors. Hence Cyber Physical Systems can benefit from the high communication data rate, several Gbps, that can be provided by mm-wave wireless transceivers. At such high frequency the wavelength is few mm and hence the whole transceiver including the antenna can be integrated in a single chip. To this aim this paper presents the design of 60 GHz transceiver architecture to ensure connection distances up to 10 m and data rate up to 4 Gbps. At 60 GHz there are more than 7 GHz of unlicensed bandwidth (available for free for development of new services). By using a CMOS SOI technology RF, analog and digital baseband circuitry can be integrated in the same chip minimizing noise coupling. Even the antenna is integrated on chip reducing cost and size vs. classic off-chip antenna solutions. Therefore the proposed transceiver can enable at physical layer the implementation of low cost nodes for a Cyber Physical System with data rates of several Gbps and with a communication distance suitable for home/office scenarios, or on-board vehicles such as cars, trains, ships, airplanes

High-resolution non-destructive three-dimensional imaging of integrated circuits

NASA Astrophysics Data System (ADS)

Holler, Mirko; Guizar-Sicairos, Manuel; Tsai, Esther H. R.; Dinapoli, Roberto; Müller, Elisabeth; Bunk, Oliver; Raabe, Jörg; Aeppli, Gabriel

2017-03-01

Modern nanoelectronics has advanced to a point at which it is impossible to image entire devices and their interconnections non-destructively because of their small feature sizes and the complex three-dimensional structures resulting from their integration on a chip. This metrology gap implies a lack of direct feedback between design and manufacturing processes, and hampers quality control during production, shipment and use. Here we demonstrate that X-ray ptychography—a high-resolution coherent diffractive imaging technique—can create three-dimensional images of integrated circuits of known and unknown designs with a lateral resolution in all directions down to 14.6 nanometres. We obtained detailed device geometries and corresponding elemental maps, and show how the devices are integrated with each other to form the chip. Our experiments represent a major advance in chip inspection and reverse engineering over the traditional destructive electron microscopy and ion milling techniques. Foreseeable developments in X-ray sources, optics and detectors, as well as adoption of an instrument geometry optimized for planar rather than cylindrical samples, could lead to a thousand-fold increase in efficiency, with concomitant reductions in scan times and voxel sizes.

GaAs VLSI for aerospace electronics

NASA Technical Reports Server (NTRS)

Larue, G.; Chan, P.

1990-01-01

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

Implementation of neuromorphic systems: from discrete components to analog VLSI chips (testing and communication issues).

PubMed

Dante, V; Del Giudice, P; Mattia, M

2001-01-01

We review a series of implementations of electronic devices aiming at imitating to some extent structure and function of simple neural systems, with particular emphasis on communication issues. We first provide a short overview of general features of such "neuromorphic" devices and the implications of setting up "tests" for them. We then review the developments directly related to our work at the Istituto Superiore di Sanità (ISS): a pilot electronic neural network implementing a simple classifier, autonomously developing internal representations of incoming stimuli; an output network, collecting information from the previous classifier and extracting the relevant part to be forwarded to the observer; an analog, VLSI (very large scale integration) neural chip implementing a recurrent network of spiking neurons and plastic synapses, and the test setup for it; a board designed to interface the standard PCI (peripheral component interconnect) bus of a PC with a special purpose, asynchronous bus for communication among neuromorphic chips; a short and preliminary account of an application-oriented device, taking advantage of the above communication infrastructure.

High-resolution non-destructive three-dimensional imaging of integrated circuits.

PubMed

Holler, Mirko; Guizar-Sicairos, Manuel; Tsai, Esther H R; Dinapoli, Roberto; Müller, Elisabeth; Bunk, Oliver; Raabe, Jörg; Aeppli, Gabriel

2017-03-15

Modern nanoelectronics has advanced to a point at which it is impossible to image entire devices and their interconnections non-destructively because of their small feature sizes and the complex three-dimensional structures resulting from their integration on a chip. This metrology gap implies a lack of direct feedback between design and manufacturing processes, and hampers quality control during production, shipment and use. Here we demonstrate that X-ray ptychography-a high-resolution coherent diffractive imaging technique-can create three-dimensional images of integrated circuits of known and unknown designs with a lateral resolution in all directions down to 14.6 nanometres. We obtained detailed device geometries and corresponding elemental maps, and show how the devices are integrated with each other to form the chip. Our experiments represent a major advance in chip inspection and reverse engineering over the traditional destructive electron microscopy and ion milling techniques. Foreseeable developments in X-ray sources, optics and detectors, as well as adoption of an instrument geometry optimized for planar rather than cylindrical samples, could lead to a thousand-fold increase in efficiency, with concomitant reductions in scan times and voxel sizes.

5-Gb/s 0.18-μm CMOS 2:1 multiplexer with integrated clock extraction

NASA Astrophysics Data System (ADS)

Changchun, Zhang; Zhigong, Wang; Si, Shi; Peng, Miao; Ling, Tian

2009-09-01

A 5-Gb/s 2:1 MUX (multiplexer) with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment (APA), has been designed and fabricated in SMIC's 0.18 μm CMOS technology. The chip area is 670 × 780 μm2. At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system.

Design and realization of 144 x 7 TDI ROIC with hybrid integrated test structure

NASA Astrophysics Data System (ADS)

Ceylan, Omer; Kayahan, Huseyin; Yazici, Melik; Baran, Muhammet Burak; Gurbuz, Yasar

2012-06-01

Design and realization of a 144x7 silicon readout integrated circuit (ROIC) based on switched capacitor TDI for MCT LWIR scanning type focal plane arrays (FPAs) and its corresponding hybrid integrated test circuits are presented. TDI operation with 7 detectors improves the SNR of the system by a factor of √7, while oversampling rate of 3 improves the spatial resolution of the system. ROIC supports bidirectional scan, 5 adjustable gain settings, bypass operation, automatic gain adjustment in case of mulfunctioning pixels and pixel select/deselect properties. Integration time of the system can be determined by the help of an external clock. Programming of ROIC can be done in parallel or serial mode according to the needs of the system. All properties except pixel select/deselect property can be performed in parallel mode, while pixel select/deselect property can be performed only in serial mode. ROIC can handle up to 3.75V dynamic range with a load of 25pF and output settling time of 80ns. Input referred noise of the ROIC is less than 750 rms electrons, while the power consumption is less than 100mW. To test ROIC in absence of detector array, a process and temperature compensated current reference array, which supplies uniform input current in range of 1-50nA to ROIC, is designed and measured both in room and cryogenic (77ºK) temperatures. Standard deviations of current reference arrays are measured 3.26% for 1nA and 0.99% for 50nA. ROIC and current reference array are fabricated seperately, and then flip-chip bonded for the test of the system. Flip-chip bonded system including ROIC and current reference test array is successfully measured both in room and cryogenic temperatures, and measurement results are presented. The manufacturing technology is 0.35μm, double poly-Si, four metal, 5V CMOS process.

On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS

PubMed Central

Liang, Yuan; Yu, Hao; Wen, Jincai; Apriyana, Anak Agung Alit; Li, Nan; Luo, Yu; Sun, Lingling

2016-01-01

An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<−9 dB) with excellent transmission efficiency (averagely −1.9 dB) from 110 GHz–325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author’s knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology. PMID:27444782

Self-priming compartmentalization digital LAMP for point-of-care.

PubMed

Zhu, Qiangyuan; Gao, Yibo; Yu, Bingwen; Ren, Hao; Qiu, Lin; Han, Sihai; Jin, Wei; Jin, Qinhan; Mu, Ying

2012-11-21

Digital nucleic acid amplification provides unprecedented opportunities for absolute nucleic acid quantification by counting of single molecules. This technique is useful for molecular genetic analysis in cancer, stem cell, bacterial, non-invasive prenatal diagnosis in which many biologists are interested. This paper describes a self-priming compartmentalization (SPC) microfluidic chip platform for performing digital loop-mediated amplification (LAMP). The energy for the pumping is pre-stored in the degassed bulk PDMS by exploiting the high gas solubility of PDMS; therefore, no additional structures other than channels and reservoirs are required. The sample and oil are sequentially sucked into the channels, and the pressure difference of gas dissolved in PDMS allows sample self-compartmentalization without the need for further chip manipulation such as with pneumatic microvalves and control systems, and so on. The SPC digital LAMP chip can be used like a 384-well plate, so, the world-to-chip fluidic interconnections are avoided. The microfluidic chip contains 4 separate panels, each panel contains 1200 independent 6 nL chambers and can be used to detect 4 samples simultaneously. Digital LAMP on the microfluidic chip was tested quantitatively by using β-actin DNA from humans. The self-priming compartmentalization behavior is roughly predictable using a two-dimensional model. The uniformity of compartmentalization was analyzed by fluorescent intensity and fraction of volume. The results showed that the feasibility and flexibility of the microfluidic chip platform for amplifying single nucleic acid molecules in different chambers made by diluting and distributing sample solutions. The SPC chip has the potential to meet the requirements of a general laboratory: power-free, valve-free, operating at isothermal temperature, inexpensive, sensitive, economizing labour time and reagents. The disposable analytical devices with appropriate air-tight packaging should be useful for point-of-care, and enabling it to become one of the common tools for biology research, especially, in point-of-care testing.

An Embedded Fusion Processor

DTIC Science & Technology

2000-10-01

available from rooksj~,rl.af.mil [4] J. Lyke and G. Forman "Microengineering Aerospace Systems" H . Helvajian editor, The Aerospace Press 1999, Chapter 8...e h I O iinterface chip, and Synchronous Dynamic Random 1K-byte. The only consequence is that after the FIFO is Access Memory (SDRAM). Each interface...shown in figure 4a, that will be used for the 1/O interconnects in place of the perimeter bond pads used in the MCM3A. The 6’ h layer is used to

Western Fisheries Research Center--Forage fish studies in Puget Sound

USGS Publications Warehouse

Liedtke, Theresa L.

2012-01-01

Researchers at the Western Fisheries Research Center are working with other U.S. Geological Survey (USGS) Centers to better understand the interconnected roles of forage fishes throughout the ecosystem of Puget Sound, Washington. Support for these studies primarily is from the USGS Coastal Habitats in Puget Sound (CHIPS) program, which supports studies of the nearshore areas of Puget Sound. Human perturbations in the nearshore area such as shoreline armoring or urban development can affect the nearshore habitats critical to forage fish.

High density electronic circuit and process for making

DOEpatents

Morgan, William P.

1999-01-01

High density circuits with posts that protrude beyond one surface of a substrate to provide easy mounting of devices such as integrated circuits. The posts also provide stress relief to accommodate differential thermal expansion. The process allows high interconnect density with fewer alignment restrictions and less wasted circuit area than previous processes. The resulting substrates can be test platforms for die testing and for multi-chip module substrate testing. The test platform can contain active components and emulate realistic operational conditions, replacing shorts/opens net testing.

Vertical cavity surface emitting lasers based on InP and related compounds -- Bottleneck and corkscrew

DOE Office of Scientific and Technical Information (OSTI.GOV)

Iga, K.

1996-12-31

Vertical optical interconnects of LSI chips and circuit boards and multiple fiber systems may be the most interesting field related to SE lasers. From this point of view, the device should be small as possible. The future process technology for it including epitaxy and etching will drastically change the situation of SE lasers. Dome optical technologies are already introduced in various subsystems, but the arrayed microoptic technology would be very helpful for advanced systems.

Opportunities and challenges in the wider adoption of liver and interconnected microphysiological systems

PubMed Central

Kostrzewski, Tomasz; Sceats, Emma L

2017-01-01

Liver disease represents a growing global health burden. The development of in vitro liver models which allow the study of disease and the prediction of metabolism and drug-induced liver injury in humans remains a challenge. The maintenance of functional primary hepatocytes cultures, the parenchymal cell of the liver, has historically been difficult with dedifferentiation and the consequent loss of hepatic function limiting utility. The desire for longer term functional liver cultures sparked the development of numerous systems, including collagen sandwiches, spheroids, micropatterned co-cultures and liver microphysiological systems. This review will focus on liver microphysiological systems, often referred to as liver-on-a-chip, and broaden to include platforms with interconnected microphysiological systems or multi-organ-chips. The interconnection of microphysiological systems presents the opportunity to explore system level effects, investigate organ cross talk, and address questions which were previously the preserve of animal experimentation. As a field, microphysiological systems have reached a level of maturity suitable for commercialization and consequent evaluation by a wider community of users, in academia and the pharmaceutical industry. Here scientific, operational, and organizational considerations relevant to the wider adoption of microphysiological systems will be discussed. Applications in which microphysiological systems might offer unique scientific insights or enable studies currently feasible only with animal models are described, and challenges which might be addressed to enable wider adoption of the technologies are highlighted. A path forward which envisions the development of microphysiological systems in partnerships between academia, vendors and industry, is proposed. Impact statement Microphysiological systems are in vitro models of human tissues and organs. These systems have advanced rapidly in recent years and are now being commercialized. To achieve wide adoption in the biological and pharmaceutical research communities, microphysiological systems must provide unique insights which translate to humans. This will be achieved by identifying key applications and making microphysiological systems intuitive to use. PMID:28504617

Opportunities and challenges in the wider adoption of liver and interconnected microphysiological systems.

PubMed

Hughes, David J; Kostrzewski, Tomasz; Sceats, Emma L

2017-10-01

Liver disease represents a growing global health burden. The development of in vitro liver models which allow the study of disease and the prediction of metabolism and drug-induced liver injury in humans remains a challenge. The maintenance of functional primary hepatocytes cultures, the parenchymal cell of the liver, has historically been difficult with dedifferentiation and the consequent loss of hepatic function limiting utility. The desire for longer term functional liver cultures sparked the development of numerous systems, including collagen sandwiches, spheroids, micropatterned co-cultures and liver microphysiological systems. This review will focus on liver microphysiological systems, often referred to as liver-on-a-chip, and broaden to include platforms with interconnected microphysiological systems or multi-organ-chips. The interconnection of microphysiological systems presents the opportunity to explore system level effects, investigate organ cross talk, and address questions which were previously the preserve of animal experimentation. As a field, microphysiological systems have reached a level of maturity suitable for commercialization and consequent evaluation by a wider community of users, in academia and the pharmaceutical industry. Here scientific, operational, and organizational considerations relevant to the wider adoption of microphysiological systems will be discussed. Applications in which microphysiological systems might offer unique scientific insights or enable studies currently feasible only with animal models are described, and challenges which might be addressed to enable wider adoption of the technologies are highlighted. A path forward which envisions the development of microphysiological systems in partnerships between academia, vendors and industry, is proposed. Impact statement Microphysiological systems are in vitro models of human tissues and organs. These systems have advanced rapidly in recent years and are now being commercialized. To achieve wide adoption in the biological and pharmaceutical research communities, microphysiological systems must provide unique insights which translate to humans. This will be achieved by identifying key applications and making microphysiological systems intuitive to use.

An analysis of the pull strength behaviors of fine-pitch, flip chip solder interconnections using a Au-Pt-Pd thick film conductor on Low-Temperature, Co-fired Ceramic (LTCC) substrates.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Uribe, Fernando R.; Kilgo, Alice C.; Grazier, John Mark

2008-09-01

The assembly of the BDYE detector requires the attachment of sixteen silicon (Si) processor dice (eight on the top side; eight on the bottom side) onto a low-temperature, co-fired ceramic (LTCC) substrate using 63Sn-37Pb (wt.%, Sn-Pb) in a double-reflow soldering process (nitrogen). There are 132 solder joints per die. The bond pads were gold-platinum-palladium (71Au-26Pt-3Pd, wt.%) thick film layers fired onto the LTCC in a post-process sequence. The pull strength and failure modes provided the quality metrics for the Sn-Pb solder joints. Pull strengths were measured in both the as-fabricated condition and after exposure to thermal cycling (-55/125 C; 15more » min hold times; 20 cycles). Extremely low pull strengths--referred to as the low pull strength phenomenon--were observed intermittently throughout the product build, resulting in added program costs, schedule delays, and a long-term reliability concern for the detector. There was no statistically significant correlation between the low pull strength phenomenon and (1) the LTCC 'sub-floor' lot; (2) grit blasting the LTCC surfaces prior to the post-process steps; (3) the post-process parameters; (4) the conductor pad height (thickness); (5) the dice soldering assembly sequence; or (5) the dice pull test sequence. Formation of an intermetallic compound (IMC)/LTCC interface caused by thick film consumption during either the soldering process or by solid-state IMC formation was not directly responsible for the low-strength phenomenon. Metallographic cross sections of solder joints from dice that exhibited the low pull strength behavior, revealed the presence of a reaction layer resulting from an interaction between Sn from the molten Sn-Pb and the glassy phase at the TKN/LTCC interface. The thick film porosity did not contribute, explicitly, to the occurrence of reaction layer. Rather, the process of printing the very thin conductor pads was too sensitive to minor thixotropic changes to ink, which resulted in inconsistent proportions of metal and glassy phase particles present during the subsequent firing process. The consequences were subtle, intermittent changes to the thick film microstructure that gave rise to the reaction layer and, thus, the low pull strength phenomenon. A mitigation strategy would be the use of physical vapor deposition (PVD) techniques to create thin film bond pads; this is multi-chip module, deposited (MCM-D) technology.« less

A macrochip interconnection network enabled by silicon nanophotonic devices.

PubMed

Zheng, Xuezhe; Cunningham, John E; Koka, Pranay; Schwetman, Herb; Lexau, Jon; Ho, Ron; Shubin, Ivan; Krishnamoorthy, Ashok V; Yao, Jin; Mekis, Attila; Pinguet, Thierry

2010-03-01

We present an advanced wavelength-division multiplexing point-to-point network enabled by silicon nanophotonic devices. This network offers strictly non-blocking all-to-all connectivity while maximizing bisection bandwidth, making it ideal for multi-core and multi-processor interconnections. We introduce one of the key components, the nanophotonic grating coupler, and discuss, for the first time, how this device can be useful for practical implementations of the wavelength-division multiplexing network using optical proximity communications. Finite difference time-domain simulation of the nanophotonic grating coupler device indicates that it can be made compact (20 microm x 50 microm), low loss (3.8 dB), and broadband (100 nm). These couplers require subwavelength material modulation at the nanoscale to achieve the desired functionality. We show that optical proximity communication provides unmatched optical I/O bandwidth density to electrical chips, which enables the application of wavelength-division multiplexing point-to-point network in macrochip with unprecedented bandwidth-density. The envisioned physical implementation is discussed. The benefits of such an interconnect network include a 5-6x improvement in latency when compared to a purely electronic implementation. Performance analysis shows that the wavelength-division multiplexing point-to-point network offers better overall performance over other optical network architectures.

3D packaging of a microfluidic system with sensory applications

NASA Astrophysics Data System (ADS)

Morrissey, Anthony; Kelly, Gerard; Alderman, John C.

1997-09-01

Among the main benefits of microsystem technology are its contributions to cost reductio, reliability and improved performance. however, the packaging of microsystems, and particularly microsensor, has proven to be one of the biggest limitations to their commercialization and the packaging of silicon sensor devices can be the most costly part of their fabrication. This paper describes the integration of 3D packaging of a microsystem. Central to the operation of the 3D demonstrator is a micromachined silicon membrane pump to supply fluids to a sensing chamber constructed about the active area of a sensor chip. This chip carries ISFET based chemical sensors, pressure sensors and thermal sensors. The electronics required for controlling and regulating the activity of the various sensors ar also available on this chip and as other chips in the 3D assembly. The demonstrator also contains a power supply module with optical fiber interconnections. All of these modules are integrated into a single plastic- encapsulated 3D vertical multichip module. The reliability of such a structure, initially proposed by Val was demonstrated by Barrett et al. An additional module available for inclusion in some of our assemblies is a test chip capable of measuring the packaging-induced stress experienced during and after assembly. The packaging process described produces a module with very high density and utilizes standard off-the-shelf components to minimize costs. As the sensor chip and micropump include micromachined silicon membranes and microvalves, the packaging of such structures has to allow consideration for the minimization of the packaging-induced stresses. With this in mind, low stress techniques, including the use of soft glob-top materials, were employed.

Realization of 10 GHz minus 30dB on-chip micro-optical links with Si-Ge RF bi-polar technology

NASA Astrophysics Data System (ADS)

Ogudo, Kingsley A.; Snyman, Lukas W.; Polleux, Jean-Luc; Viana, Carlos; Tegegne, Zerihun

2014-06-01

Si Avalanche based LEDs technology has been developed in the 650 -850nm wavelength regime [1, 2]. Correspondingly, small micro-dimensioned detectors with pW/μm2 sensitivity have been developed for the same wavelength range utilizing Si-Ge detector technology with detection efficiencies of up to 0.85, and with a transition frequencies of up to 80 GHz [3] A series of on-chip optical links of 50 micron length, utilizing 650 - 850 nm propagation wavelength have been designed and realized, utilizing a Si Ge radio frequency bipolar process. Micron dimensioned optical sources, waveguides and detectors were all integrated on the same chip to form a complete optical link on-chip. Avalanche based Si LEDs (Si Av LEDs), Schottky contacting, TEOS densification strategies, silicon nitride based waveguides, and state of the art Si-Ge bipolar detector technologies were used as key design strategies. Best performances show optical coupling from source to detector of up to 10GHz and - 40dBm total optical link budget loss with a potential transition frequency coupling of up to 40GHz utilizing Si Ge based LEDs. The technology is particularly suitable for application as on-chip optical links, optical MEMS and MOEMS, as well as for optical interconnects utilizing low loss, side surface, waveguide- to-optical fiber coupling. Most particularly is one of our designed waveguide which have a good core axis alignment with the optical source and yield 10GHz -30dB on-chip micro-optical links as shown in Fig 9 (c). The technology as developed has been appropriately IP protected.

High-frequency ultrasonic wire bonding systems

PubMed

Tsujino; Yoshihara; Sano; Ihara

2000-03-01

The vibration characteristics of longitudinal-complex transverse vibration systems with multiple resonance frequencies of 350-980 kHz for ultrasonic wire bonding of IC, LSI or electronic devices were studied. The complex vibration systems can be applied for direct welding of semiconductor tips (face-down bonding, flip-chip bonding) and packaging of electronic devices. A longitudinal-complex transverse vibration bonding system consists of a complex transverse vibration rod, two driving longitudinal transducers 7.0 mm in diameter and a transverse vibration welding tip. The vibration distributions along ceramic and stainless-steel welding tips were measured at up to 980 kHz. A high-frequency vibration system with a height of 20.7 mm and a weight of less than 15 g was obtained.

Ultra-thin ohmic contacts for p-type nitride light emitting devices

DOEpatents

Raffetto, Mark; Bharathan, Jayesh; Haberern, Kevin; Bergmann, Michael; Emerson, David; Ibbetson, James; Li, Ting

2014-06-24

A flip-chip semiconductor based Light Emitting Device (LED) can include an n-type semiconductor substrate and an n-type GaN epi-layer on the substrate. A p-type GaN epi-layer can be on the n-type GaN epi-layer and a metal ohmic contact p-electrode can be on the p-type GaN epi-layer, where the metal ohmic contact p-electrode can have an average thickness less than about 25 .ANG.. A reflector can be on the metal ohmic contact p-electrode and a metal stack can be on the reflector. An n-electrode can be on the substrate opposite the n-type GaN epi-layer and a bonding pad can be on the n-electrode.

Large area MEMS based ultrasound device for cancer detection

NASA Astrophysics Data System (ADS)

Wodnicki, Robert; Thomenius, Kai; Ming Hooi, Fong; Sinha, Sumedha P.; Carson, Paul L.; Lin, Der-Song; Zhuang, Xuefeng; Khuri-Yakub, Pierre; Woychik, Charles

2011-08-01

We present image results obtained using a prototype ultrasound array that demonstrates the fundamental architecture for a large area MEMS based ultrasound device for detection of breast cancer. The prototype array consists of a tiling of capacitive Micromachined Ultrasound Transducers (cMUTs) that have been flip-chip attached to a rigid organic substrate. The pitch on the cMUT elements is 185 μm and the operating frequency is nominally 9 MHz. The spatial resolution of the new probe is comparable to those of production PZT probes; however the sensitivity is reduced by conditions that should be correctable. Simulated opposed-view image registration and Speed of Sound volume reconstruction results for ultrasound in the mammographic geometry are also presented.

Enhanced light extraction in tunnel junction-enabled top emitting UV LEDs

DOE PAGES

Zhang, Yuewei; Allerman, Andrew A.; Krishnamoorthy, Sriram; ...

2016-04-11

The efficiency of ultra violet LEDs has been critically limited by the absorption losses in p-type and metal layers. In this work, surface roughening based light extraction structures are combined with tunneling based p-contacts to realize highly efficient top-side light extraction efficiency in UV LEDs. Surface roughening of the top n-type AlGaN contact layer is demonstrated using self-assembled Ni nano-clusters as etch mask. The top surface roughened LEDs were found to enhance external quantum efficiency by over 40% for UV LEDs with a peak emission wavelength of 326 nm. The method described here can enable highly efficient UV LEDs withoutmore » the need for complex manufacturing methods such as flip chip bonding.« less

Monolithic silicon-photonic platforms in state-of-the-art CMOS SOI processes [Invited].

PubMed

Stojanović, Vladimir; Ram, Rajeev J; Popović, Milos; Lin, Sen; Moazeni, Sajjad; Wade, Mark; Sun, Chen; Alloatti, Luca; Atabaki, Amir; Pavanello, Fabio; Mehta, Nandish; Bhargava, Pavan

2018-05-14

Integrating photonics with advanced electronics leverages transistor performance, process fidelity and package integration, to enable a new class of systems-on-a-chip for a variety of applications ranging from computing and communications to sensing and imaging. Monolithic silicon photonics is a promising solution to meet the energy efficiency, sensitivity, and cost requirements of these applications. In this review paper, we take a comprehensive view of the performance of the silicon-photonic technologies developed to date for photonic interconnect applications. We also present the latest performance and results of our "zero-change" silicon photonics platforms in 45 nm and 32 nm SOI CMOS. The results indicate that the 45 nm and 32 nm processes provide a "sweet-spot" for adding photonic capability and enhancing integrated system applications beyond the Moore-scaling, while being able to offload major communication tasks from more deeply-scaled compute and memory chips without complicated 3D integration approaches.

Analyzing multiple data sets by interconnecting RSAT programs via SOAP Web services: an example with ChIP-chip data.

PubMed

Sand, Olivier; Thomas-Chollier, Morgane; Vervisch, Eric; van Helden, Jacques

2008-01-01

This protocol shows how to access the Regulatory Sequence Analysis Tools (RSAT) via a programmatic interface in order to automate the analysis of multiple data sets. We describe the steps for writing a Perl client that connects to the RSAT Web services and implements a workflow to discover putative cis-acting elements in promoters of gene clusters. In the presented example, we apply this workflow to lists of transcription factor target genes resulting from ChIP-chip experiments. For each factor, the protocol predicts the binding motifs by detecting significantly overrepresented hexanucleotides in the target promoters and generates a feature map that displays the positions of putative binding sites along the promoter sequences. This protocol is addressed to bioinformaticians and biologists with programming skills (notions of Perl). Running time is approximately 6 min on the example data set.

Self-Patterning of Silica/Epoxy Nanocomposite Underfill by Tailored Hydrophilic-Superhydrophobic Surfaces for 3D Integrated Circuit (IC) Stacking.

PubMed

Tuan, Chia-Chi; James, Nathan Pataki; Lin, Ziyin; Chen, Yun; Liu, Yan; Moon, Kyoung-Sik; Li, Zhuo; Wong, C P

2017-03-15

As microelectronics are trending toward smaller packages and integrated circuit (IC) stacks nowadays, underfill, the polymer composite filled in between the IC chip and the substrate, becomes increasingly important for interconnection reliability. However, traditional underfills cannot meet the requirements for low-profile and fine pitch in high density IC stacking packages. Post-applied underfills have difficulties in flowing into the small gaps between the chip and the substrate, while pre-applied underfills face filler entrapment at bond pads. In this report, we present a self-patterning underfilling technology that uses selective wetting of underfill on Cu bond pads and Si 3 N 4 passivation via surface energy engineering. This novel process, fully compatible with the conventional underfilling process, eliminates the issue of filler entrapment in typical pre-applied underfilling process, enabling high density and fine pitch IC die bonding.

Modular microfluidics for point-of-care protein purifications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Millet, L. J.; Lucheon, J. D.; Standaert, R. F.

Biochemical separations are the heart of diagnostic assays and purification methods for biologics. On-chip miniaturization and modularization of separation procedures will enable the development of customized, portable devices for personalized health-care diagnostics and point-of-use production of treatments. In this report, we describe the design and fabrication of miniature ion exchange, size exclusion and affinity chromatography modules for on-chip clean-up of recombinantly-produced proteins. Our results demonstrate that these common separations techniques can be implemented in microfluidic modules with performance comparable to conventional approaches. We introduce embedded 3-D microfluidic interconnects for integrating micro-scale separation modules that can be arranged and reconfigured tomore » suit a variety of fluidic operations or biochemical processes. In conclusion, we demonstrate the utility of the modular approach with a platform for the enrichment of enhanced green fluorescent protein (eGFP) from Escherichia coli lysate through integrated affinity and size-exclusion chromatography modules.« less

On-chip WDM mode-division multiplexing interconnection with optional demodulation function.

PubMed

Ye, Mengyuan; Yu, Yu; Chen, Guanyu; Luo, Yuchan; Zhang, Xinliang

2015-12-14

We propose and fabricate a wavelength-division-multiplexing (WDM) compatible and multi-functional mode-division-multiplexing (MDM) integrated circuit, which can perform the mode conversion and multiplexing for the incoming multipath WDM signals, avoiding the wavelength conflict. An phase-to-intensity demodulation function can be optionally applied within the circuit while performing the mode multiplexing. For demonstration, 4 × 10 Gb/s non-return-to-zero differential phase shift keying (NRZ-DPSK) signals are successfully processed, with open and clear eye diagrams. Measured bit error ratio (BER) results show less than 1 dB receive sensitivity variation for three modes and four wavelengths with demodulation. In the case without demodulation, the average power penalties at 4 wavelengths are -1.5, -3 and -3.5 dB for TE₀-TE₀, TE₀-TE₁ and TE₀-TE₂ mode conversions, respectively. The proposed flexible scheme can be used at the interface of long-haul and on-chip communication systems.

Air Force highly integrated photonics program: development and demonstration of an optically transparent fiber optic network for avionics applications

NASA Astrophysics Data System (ADS)

Whaley, Gregory J.; Karnopp, Roger J.

2010-04-01

The goal of the Air Force Highly Integrated Photonics (HIP) program is to develop and demonstrate single photonic chip components which support a single mode fiber network architecture for use on mobile military platforms. We propose an optically transparent, broadcast and select fiber optic network as the next generation interconnect on avionics platforms. In support of this network, we have developed three principal, single-chip photonic components: a tunable laser transmitter, a 32x32 port star coupler, and a 32 port multi-channel receiver which are all compatible with demanding avionics environmental and size requirements. The performance of the developed components will be presented as well as the results of a demonstration system which integrates the components into a functional network representative of the form factor used in advanced avionics computing and signal processing applications.

Phase space dynamics and control of the quantum particles associated to hypergraph states

NASA Astrophysics Data System (ADS)

Berec, Vesna

2015-05-01

As today's nanotechnology focus becomes primarily oriented toward production and manipulation of materials at the subatomic level, allowing the performance and complexity of interconnects where the device density accepts more than hundreds devices on a single chip, the manipulation of semiconductor nanostructures at the subatomic level sets its prime tasks on preserving and adequate transmission of information encoded in specified (quantum) states. The presented study employs the quantum communication protocol based on the hypergraph network model where the numerical solutions of equations of motion of quantum particles are associated to vertices (assembled with device chip), which follow specific controllable paths in the phase space. We address these findings towards ultimate quest for prediction and selective control of quantum particle trajectories. In addition, presented protocols could represent valuable tool for reducing background noise and uncertainty in low-dimensional and operationally meaningful, scalable complex systems.

Modular microfluidics for point-of-care protein purifications.

PubMed

Millet, L J; Lucheon, J D; Standaert, R F; Retterer, S T; Doktycz, M J

2015-04-21

Biochemical separations are the heart of diagnostic assays and purification methods for biologics. On-chip miniaturization and modularization of separation procedures will enable the development of customized, portable devices for personalized health-care diagnostics and point-of-use production of treatments. In this report, we describe the design and fabrication of miniature ion exchange, size exclusion and affinity chromatography modules for on-chip clean-up of recombinantly-produced proteins. Our results demonstrate that these common separations techniques can be implemented in microfluidic modules with performance comparable to conventional approaches. We introduce embedded 3-D microfluidic interconnects for integrating micro-scale separation modules that can be arranged and reconfigured to suit a variety of fluidic operations or biochemical processes. We demonstrate the utility of the modular approach with a platform for the enrichment of enhanced green fluorescent protein (eGFP) from Escherichia coli lysate through integrated affinity and size-exclusion chromatography modules.

IIIV/Si Nanoscale Lasers and Their Integration with Silicon Photonics

NASA Astrophysics Data System (ADS)

Bondarenko, Olesya

The rapidly evolving global information infrastructure requires ever faster data transfer within computer networks and stations. Integrated chip scale photonics can pave the way to accelerated signal manipulation and boost bandwidth capacity of optical interconnects in a compact and ergonomic arrangement. A key building block for integrated photonic circuits is an on-chip laser. In this dissertation we explore ways to reduce the physical footprint of semiconductor lasers and make them suitable for high density integration on silicon, a standard material platform for today's integrated circuits. We demonstrated the first room temperature metalo-dielectric nanolaser, sub-wavelength in all three dimensions. Next, we demonstrated a nanolaser on silicon, showing the feasibility of its integration with this platform. We also designed and realized an ultracompact feedback laser with edge-emitting structure, amenable for in-plane coupling with a standard silicon waveguide. Finally, we discuss the challenges and propose solutions for improvement of the device performance and practicality.

Power-Aware Compiler Controllable Chip Multiprocessor

NASA Astrophysics Data System (ADS)

Shikano, Hiroaki; Shirako, Jun; Wada, Yasutaka; Kimura, Keiji; Kasahara, Hironori

A power-aware compiler controllable chip multiprocessor (CMP) is presented and its performance and power consumption are evaluated with the optimally scheduled advanced multiprocessor (OSCAR) parallelizing compiler. The CMP is equipped with power control registers that change clock frequency and power supply voltage to functional units including processor cores, memories, and an interconnection network. The OSCAR compiler carries out coarse-grain task parallelization of programs and reduces power consumption using architectural power control support and the compiler's power saving scheme. The performance evaluation shows that MPEG-2 encoding on the proposed CMP with four CPUs results in 82.6% power reduction in real-time execution mode with a deadline constraint on its sequential execution time. Furthermore, MP3 encoding on a heterogeneous CMP with four CPUs and four accelerators results in 53.9% power reduction at 21.1-fold speed-up in performance against its sequential execution in the fastest execution mode.

Modular microfluidics for point-of-care protein purifications

DOE PAGES

Millet, L. J.; Lucheon, J. D.; Standaert, R. F.; ...

2015-01-01

Biochemical separations are the heart of diagnostic assays and purification methods for biologics. On-chip miniaturization and modularization of separation procedures will enable the development of customized, portable devices for personalized health-care diagnostics and point-of-use production of treatments. In this report, we describe the design and fabrication of miniature ion exchange, size exclusion and affinity chromatography modules for on-chip clean-up of recombinantly-produced proteins. Our results demonstrate that these common separations techniques can be implemented in microfluidic modules with performance comparable to conventional approaches. We introduce embedded 3-D microfluidic interconnects for integrating micro-scale separation modules that can be arranged and reconfigured tomore » suit a variety of fluidic operations or biochemical processes. In conclusion, we demonstrate the utility of the modular approach with a platform for the enrichment of enhanced green fluorescent protein (eGFP) from Escherichia coli lysate through integrated affinity and size-exclusion chromatography modules.« less

Monolithic short wave infrared (SWIR) detector array

NASA Technical Reports Server (NTRS)

1983-01-01

A monolithic self-scanned linear detector array was developed for remote sensing in the 1.1- 2.4-micron spectral region. A high-density IRCCD test chip was fabricated to verify new design approaches required for the detector array. The driving factors in the Schottky barrier IRCCD (Pdsub2Si) process development are the attainment of detector yield, uniformity, adequate quantum efficiency, and lowest possible dark current consistent with radiometric accuracy. A dual-band module was designed that consists of two linear detector arrays. The sensor architecture places the floating diffusion output structure in the middle of the chip, away from the butt edges. A focal plane package was conceptualized and includes a polycrystalline silicon substrate carrying a two-layer, thick-film interconnecting conductor pattern and five epoxy-mounted modules. A polycrystalline silicon cover encloses the modules and bond wires, and serves as a radiation and EMI shield, thermal conductor, and contamination seal.

A scalable silicon photonic chip-scale optical switch for high performance computing systems.

PubMed

Yu, Runxiang; Cheung, Stanley; Li, Yuliang; Okamoto, Katsunari; Proietti, Roberto; Yin, Yawei; Yoo, S J B

2013-12-30

This paper discusses the architecture and provides performance studies of a silicon photonic chip-scale optical switch for scalable interconnect network in high performance computing systems. The proposed switch exploits optical wavelength parallelism and wavelength routing characteristics of an Arrayed Waveguide Grating Router (AWGR) to allow contention resolution in the wavelength domain. Simulation results from a cycle-accurate network simulator indicate that, even with only two transmitter/receiver pairs per node, the switch exhibits lower end-to-end latency and higher throughput at high (>90%) input loads compared with electronic switches. On the device integration level, we propose to integrate all the components (ring modulators, photodetectors and AWGR) on a CMOS-compatible silicon photonic platform to ensure a compact, energy efficient and cost-effective device. We successfully demonstrate proof-of-concept routing functions on an 8 × 8 prototype fabricated using foundry services provided by OpSIS-IME.

Prototype of a gigabit data transmitter in 65 nm CMOS for DEPFET pixel detectors at Belle-II

NASA Astrophysics Data System (ADS)

Kishishita, T.; Krüger, H.; Hemperek, T.; Lemarenko, M.; Koch, M.; Gronewald, M.; Wermes, N.

2013-08-01

This paper describes the recent development of a gigabit data transmitter for the Belle-II pixel detector (PXD). The PXD is an innermost detector currently under development for the upgraded KEK-B factory in Japan. The PXD consists of two layers of DEPFET sensor modules located at 1.8 and 2.2 cm radii. Each module is equipped with three different ASIC types mounted on the detector substrate with a flip-chip technique: (a) SWITCHER for generating steering signals for the DEPFET sensors, (b) DCD for digitizing the signal currents, and (c) DHP for performing data processing and sending the data off the module to the back-end data handling hybrid via ∼ 40 cm Kapton flex and 12-15 m twisted pair (TWP) cables. To meet the requirements of the PXD data transmission, a prototype of the DHP data transmitter has been developed in a 65-nm standard CMOS technology. The transmitter test chip consists of current-mode logic (CML) drivers and a phase-locked loop (PLL) which generates a clock signal for a 1.6 Gbit/s output data stream from an 80 cm reference clock. A programmable pre-emphasis circuit is also implemented in the CML driver to compensate signal losses in the long cable by shaping the transmitted pulse response. The jitter performance was measured as 25 ps (1 σ distribution) by connecting the chip with 38 cm flex and 10 m TWP cables.

Mitigating leakage errors due to cavity modes in a superconducting quantum computer

NASA Astrophysics Data System (ADS)

McConkey, T. G.; Béjanin, J. H.; Earnest, C. T.; McRae, C. R. H.; Pagel, Z.; Rinehart, J. R.; Mariantoni, M.

2018-07-01

A practical quantum computer requires quantum bit (qubit) operations with low error probabilities in extensible architectures. We study a packaging method that makes it possible to address hundreds of superconducting qubits by means of coaxial Pogo pins. A qubit chip is housed in a superconducting box, where both box and chip dimensions lead to unwanted modes that can interfere with qubit operations. We analyze these interference effects in the context of qubit coherent leakage and qubit decoherence induced by damped modes. We propose two methods, half-wave fencing and antinode pinning, to mitigate the resulting errors by detuning the resonance frequency of the modes from the qubit frequency. We perform electromagnetic field simulations indicating that the resonance frequency of the modes increases with the number of installed pins and can be engineered to be significantly higher than the highest qubit frequency. We estimate that the error probabilities and decoherence rates due to suitably shifted modes in realistic scenarios can be up to two orders of magnitude lower than the state-of-the-art superconducting qubit error and decoherence rates. Our methods can be extended to different types of packages that do not rely on Pogo pins. Conductive bump bonds, for example, can serve the same purpose in qubit architectures based on flip chip technology. Metalized vias, instead, can be used to mitigate modes due to the increasing size of the dielectric substrate on which qubit arrays are patterned.

Ultrahigh-speed Si-integrated on-chip laser with tailored dynamic characteristics

NASA Astrophysics Data System (ADS)

Park, Gyeong Cheol; Xue, Weiqi; Piels, Molly; Zibar, Darko; Mørk, Jesper; Semenova, Elizaveta; Chung, Il-Sug

2016-12-01

For on-chip interconnects, an ideal light source should have an ultralow energy consumption per bandwidth (operating en-ergy) as well as sufficient output power for error-free detection. Nanocavity lasers have been considered the most ideal for smaller operating energy. However, they have a challenge in obtaining a sufficient output power. Here, as an alternative, we propose an ultrahigh-speed microcavity laser structure, based on a vertical cavity with a high-contrast grating (HCG) mirror for transverse magnetic (TM) polarisation. By using the TM HCG, a very small mode volume and an un-pumped compact optical feedback structure can be realised, which together tailor the frequency response function for achieving a very high speed at low injection currents. Furthermore, light can be emitted laterally into a Si waveguide. From an 1.54-μm optically-pumped laser, a 3-dB frequency of 27 GHz was obtained at a pumping level corresponding to sub-mA. Using measured 3-dB frequen-cies and calculated equivalent currents, the modulation current efficiency factor (MCEF) is estimated to be 42.1 GHz/mA1/2, which is superior among microcavity lasers. This shows a high potential for a very high speed at low injection currents or avery small heat generation at high bitrates, which are highly desirable for both on-chip and off-chip applications.

Ubiquitin-specific protease 8 links the PTEN-Akt-AIP4 pathway to the control of FLIPS stability and TRAIL sensitivity in glioblastoma multiforme.

PubMed

Panner, Amith; Crane, Courtney A; Weng, Changjiang; Feletti, Alberto; Fang, Shanna; Parsa, Andrew T; Pieper, Russell O

2010-06-15

The antiapoptotic protein FLIP(S) is a key suppressor of tumor necrosis factor-related apoptosis-inducing ligand (TRAIL)-induced apoptosis in human glioblastoma multiforme (GBM) cells. We previously reported that a novel phosphatase and tensin homologue (PTEN)-Akt-atrophin-interacting protein 4 (AIP4) pathway regulates FLIP(S) ubiquitination and stability, although the means by which PTEN and Akt were linked to AIP4 activity were unclear. Here, we report that a second regulator of ubiquitin metabolism, the ubiquitin-specific protease 8 (USP8), is a downstream target of Akt, and that USP8 links Akt to AIP4 and the regulation of FLIP(S) stability and TRAIL resistance. In human GBM xenografts, levels of USP8 correlated inversely with pAkt levels, and genetic or pharmacologic manipulation of Akt regulated USP8 levels in an inverse manner. Overexpression of wild-type USP8, but not catalytically inactive USP8, increased FLIP(S) ubiquitination, decreased FLIP(S) half-life, decreased FLIP(S) steady-state levels, and decreased TRAIL resistance, whereas short interfering RNA (siRNA)-mediated suppression of USP8 levels had the opposite effect. Because high levels of the USP8 deubiquitinase correlated with high levels of FLIP(S) ubiquitination, USP8 seemed to control FLIP(S) ubiquitination through an intermediate target. Consistent with this idea, overexpression of wild-type USP8 decreased the ubiquitination of the FLIP(S) E3 ubiquitin ligase AIP4, an event previously shown to increase AIP4-FLIP(S) interaction, whereas siRNA-mediated suppression of USP8 increased AIP4 ubiquitination. Furthermore, the suppression of FLIP(S) levels by USP8 overexpression was reversed by the introduction of siRNA targeting AIP4. These results show that USP8, a downstream target of Akt, regulates the ability of AIP4 to control FLIP(S) stability and TRAIL sensitivity.

Thin-Film Quantum Dot Photodiode for Monolithic Infrared Image Sensors.

PubMed

Malinowski, Pawel E; Georgitzikis, Epimitheas; Maes, Jorick; Vamvaka, Ioanna; Frazzica, Fortunato; Van Olmen, Jan; De Moor, Piet; Heremans, Paul; Hens, Zeger; Cheyns, David

2017-12-10

Imaging in the infrared wavelength range has been fundamental in scientific, military and surveillance applications. Currently, it is a crucial enabler of new industries such as autonomous mobility (for obstacle detection), augmented reality (for eye tracking) and biometrics. Ubiquitous deployment of infrared cameras (on a scale similar to visible cameras) is however prevented by high manufacturing cost and low resolution related to the need of using image sensors based on flip-chip hybridization. One way to enable monolithic integration is by replacing expensive, small-scale III-V-based detector chips with narrow bandgap thin-films compatible with 8- and 12-inch full-wafer processing. This work describes a CMOS-compatible pixel stack based on lead sulfide quantum dots (PbS QD) with tunable absorption peak. Photodiode with a 150-nm thick absorber in an inverted architecture shows dark current of 10 -6 A/cm² at -2 V reverse bias and EQE above 20% at 1440 nm wavelength. Optical modeling for top illumination architecture can improve the contact transparency to 70%. Additional cooling (193 K) can improve the sensitivity to 60 dB. This stack can be integrated on a CMOS ROIC, enabling order-of-magnitude cost reduction for infrared sensors.

Optical link by using optical wiring method for reducing EMI

NASA Astrophysics Data System (ADS)

Cho, In-Kui; Kwon, Jong-Hwa; Choi, Sung-Woong; Bondarik, Alexander; Yun, Je-Hoon; Kim, Chang-Joo; Ahn, Seung-Beom; Jeong, Myung-Yung; Park, Hyo Hoon

2008-12-01

A practical optical link system was prepared with a transmitter (Tx) and receiver (Rx) for reducing EMI (electromagnetic interference). The optical TRx module consisted of a metal optical bench, a module printed circuit board (PCB), a driver/receiver IC, a VCSEL/PD array, and an optical link block composed of plastic optical fiber (POF). For the optical interconnection between the light-sources and detectors, an optical wiring method has been proposed to enable easy assembly. The key benefit of fiber optic link is the absence of electromagnetic interference (EMI) noise creation and susceptibility. This paper provides a method for optical interconnection between an optical Tx and an optical Rx, comprising the following steps: (i) forming a light source device, an optical detection device, and an optical transmission unit on a substrate (metal optical bench (MOB)); (ii) preparing a flexible optical transmission-connection medium (optical wiring link) to optically connect the light source device formed on the substrate with the optical detection device; and (iii) directly connecting one end of the surface-finished optical transmission connection medium with the light source device and the other end with the optical detection device. Electronic interconnections have uniquely electronic problems such as EMI, shorting, and ground loops. Since these problems only arise during transduction (electronics-to-optics or opticsto- electronics), the purely optical part and optical link(interconnection) is free of these problems. 1 An optical link system constructed with TRx modules was fabricated and the optical characteristics about data links and EMI levels were measured. The results clearly demonstrate that the use of an optical wiring method can provide robust and cost-effective assembly for reducing EMI of inter-chip interconnect. We successfully achieved a 4.5 Gb/s data transmission rate without EMI problems.

Bioinspired architecture approach for a one-billion transistor smart CMOS camera chip

NASA Astrophysics Data System (ADS)

Fey, Dietmar; Komann, Marcus

2007-05-01

In the paper we present a massively parallel VLSI architecture for future smart CMOS camera chips with up to one billion transistors. To exploit efficiently the potential offered by future micro- or nanoelectronic devices traditional on central structures oriented parallel architectures based on MIMD or SIMD approaches will fail. They require too long and too many global interconnects for the distribution of code or the access to common memory. On the other hand nature developed self-organising and emergent principles to manage successfully complex structures based on lots of interacting simple elements. Therefore we developed a new as Marching Pixels denoted emergent computing paradigm based on a mixture of bio-inspired computing models like cellular automaton and artificial ants. In the paper we present different Marching Pixels algorithms and the corresponding VLSI array architecture. A detailed synthesis result for a 0.18 μm CMOS process shows that a 256×256 pixel image is processed in less than 10 ms assuming a moderate 100 MHz clock rate for the processor array. Future higher integration densities and a 3D chip stacking technology will allow the integration and processing of Mega pixels within the same time since our architecture is fully scalable.

InSb arrays with CCD readout for 1.0- to 5.5-microns infrared applications

NASA Technical Reports Server (NTRS)

Phillips, J. D.; Scorso, J. B.; Thom, R. D.

1976-01-01

There were two approaches for fabricating indium antimonide (InSb) arrays with CCD readout discussed. The hybrid approach integrated InSb detectors and silicon CCDs in a modular assembly via an advanced interconnection technology. In the monolithic approach, the InSb infrared detectors and the CCD readout were integrated on the same InSb chip. Both approaches utilized intrinsic (band-to-band) photodetection with the attendant advantages over extrinsic detectors. The status of each of these detector readout concepts, with pertinent performance characteristics, was presented.

Interchip link system using an optical wiring method.

PubMed

Cho, In-Kui; Ryu, Jin-Hwa; Jeong, Myung-Yung

2008-08-15

A chip-scale optical link system is presented with a transmitter/receiver and optical wire link. The interchip link system consists of a metal optical bench, a printed circuit board module, a driver/receiver integrated circuit, a vertical cavity surface-emitting laser/photodiode array, and an optical wire link composed of plastic optical fibers (POFs). We have developed a downsized POF and an optical wiring method that allows on-site installation with a simple annealing as optical wiring technologies for achieving high-density optical interchip interconnection within such devices. Successful data transfer measurements are presented.

Large-Constraint-Length, Fast Viterbi Decoder

NASA Technical Reports Server (NTRS)

Collins, O.; Dolinar, S.; Hsu, In-Shek; Pollara, F.; Olson, E.; Statman, J.; Zimmerman, G.

1990-01-01

Scheme for efficient interconnection makes VLSI design feasible. Concept for fast Viterbi decoder provides for processing of convolutional codes of constraint length K up to 15 and rates of 1/2 to 1/6. Fully parallel (but bit-serial) architecture developed for decoder of K = 7 implemented in single dedicated VLSI circuit chip. Contains six major functional blocks. VLSI circuits perform branch metric computations, add-compare-select operations, and then store decisions in traceback memory. Traceback processor reads appropriate memory locations and puts out decoded bits. Used as building block for decoders of larger K.

Low-dielectric constant insulators for future integrated circuits and packages.

PubMed

Kohl, Paul A

2011-01-01

Future integrated circuits and packages will require extraordinary dielectric materials for interconnects to allow transistor advances to be translated into system-level advances. Exceedingly low-permittivity and low-loss materials are required at every level of the electronic system, from chip-level insulators to packages and printed wiring boards. In this review, the requirements and goals for future insulators are discussed followed by a summary of current state-of-the-art materials and technical approaches. Much work needs to be done for insulating materials and structures to meet future needs.

High density electronic circuit and process for making

DOEpatents

Morgan, W.P.

1999-06-29

High density circuits with posts that protrude beyond one surface of a substrate to provide easy mounting of devices such as integrated circuits are disclosed. The posts also provide stress relief to accommodate differential thermal expansion. The process allows high interconnect density with fewer alignment restrictions and less wasted circuit area than previous processes. The resulting substrates can be test platforms for die testing and for multi-chip module substrate testing. The test platform can contain active components and emulate realistic operational conditions, replacing shorts/opens net testing. 8 figs.

The rectenna design on contact lens for wireless powering of the active intraocular pressure monitoring system.

PubMed

Cheng, H W; Jeng, B M; Chen, C Y; Huang, H Y; Chiou, J C; Luo, C H

2013-01-01

This paper proposed a wireless power harvesting system with micro-electro-mechanical-systems (MEMS) fabrication for noninvasive intraocular pressure (IOP) measurement on soft contact lens substructure. The power harvesting IC consists of a loop antenna, an impedance matching network and a rectifier. The proposed IC has been designed and fabricated by CMOS 0.18 um process that operates at the ISM band of 5.8 GHz. The antenna and the power harvesting IC would be bonded together by using flip chip bonding technologies without extra wire interference. The circuit utilized an impedance transformation circuit to boost the input RF signal that improves the circuit performance. The proposed design achieves an RF-to-DC conversion efficiency of 35% at 5.8 GHz.

Three-Dimensional Waveguide Arrays for Coupling Between Fiber-Optic Connectors and Surface-Mounted Optoelectronic Devices

NASA Astrophysics Data System (ADS)

Hiramatsu, Seiki; Kinoshita, Masao

2005-09-01

This paper describes the fabrication of novel surface-mountable waveguide connectors and presents test results for them. To ensure more highly integrated and low-cost fabrication, we propose new three-dimensional (3-D) waveguide arrays that feature two-dimensionally integrated optical inputs/outputs and optical path redirection. A wafer-level stack and lamination process was used to fabricate the waveguide arrays. Vertical-cavity surface-emitting lasers (VCSELs) and photodiodes were directly mounted on the arrays and combined with mechanical transferable ferrule using active alignment. With the help of a flip-chip bonder, the waveguide connectors were mounted on a printed circuit board by solder bumps. Using mechanical transferable connectors, which can easily plug into the waveguide connectors, we obtained multi-gigabits-per-second transmission performance.

Creation of a Radiation Hard 0.13 Micron CMOS Library at IHP

NASA Astrophysics Data System (ADS)

Jagdhold, U.

2010-08-01

To support space applications we will develop an 0.13 micron CMOS library which should be radiation hard up to 200 krad. By introducing new radiation hard design rules we will minimize IC-level leakage and single event latchup (SEL). To reduce single event upset (SEU) we will add two p-MOS transistors to all flip flops. For reliability reasons we will use double contacts in all library elements. The additional rules and the library elements will then be integrated in our Cadence mixed signal designkit, Virtuoso IC6.1 [1]. A test chip will be produced with our in house 0.13 micron BiCMOS technology, see Ref. [2].Thereafter we will doing radiation tests according the ESA specifications, see Ref. [3], [4].

Si photonics technology for future optical interconnection

NASA Astrophysics Data System (ADS)

Zheng, Xuezhe; Krishnamoorthy, Ashok V.

2011-12-01

Scaling of computing systems require ultra-efficient interconnects with large bandwidth density. Silicon photonics offers a disruptive solution with advantages in reach, energy efficiency and bandwidth density. We review our progress in developing building blocks for ultra-efficient WDM silicon photonic links. Employing microsolder based hybrid integration with low parasitics and high density, we optimize photonic devices on SOI platforms and VLSI circuits on more advanced bulk CMOS technology nodes independently. Progressively, we successfully demonstrated single channel hybrid silicon photonic transceivers at 5 Gbps and 10 Gbps, and 80 Gbps arrayed WDM silicon photonic transceiver using reverse biased depletion ring modulators and Ge waveguide photo detectors. Record-high energy efficiency of less than 100fJ/bit and 385 fJ/bit were achieved for the hybrid integrated transmitter and receiver, respectively. Waveguide grating based optical proximity couplers were developed with low loss and large optical bandwidth to enable multi-layer intra/inter-chip optical interconnects. Thermal engineering of WDM devices by selective substrate removal, together with WDM link using synthetic wavelength comb, we significantly improved the device tuning efficiency and reduced the tuning range. Using these innovative techniques, two orders of magnitude tuning power reduction was achieved. And tuning cost of only a few 10s of fJ/bit is expected for high data rate WDM silicon photonic links.

Full Flip, Half Flip and No Flip: Evaluation of Flipping an Introductory Programming Course

ERIC Educational Resources Information Center

Fryling, Meg; Yoder, Robert; Breimer, Eric

2016-01-01

While some research has suggested that video lectures are just as effective as in-person lectures to convey basic information to students, not everyone agrees that the flipped classroom model is an effective way of educating students. This research explores traditional, semi-flipped and fully-flipped classroom models by comparing three sections of…

Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

NASA Astrophysics Data System (ADS)

Yamamoto, Shuu'ichirou; Shuto, Yusuke; Sugahara, Satoshi

2013-07-01

We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks. Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

The Quantum Socket: Wiring for Superconducting Qubits - Part 1

NASA Astrophysics Data System (ADS)

McConkey, T. G.; Bejanin, J. H.; Rinehart, J. R.; Bateman, J. D.; Earnest, C. T.; McRae, C. H.; Rohanizadegan, Y.; Shiri, D.; Mariantoni, M.; Penava, B.; Breul, P.; Royak, S.; Zapatka, M.; Fowler, A. G.

Quantum systems with ten superconducting quantum bits (qubits) have been realized, making it possible to show basic quantum error correction (QEC) algorithms. However, a truly scalable architecture has not been developed yet. QEC requires a two-dimensional array of qubits, restricting any interconnection to external classical systems to the third axis. In this talk, we introduce an interconnect solution for solid-state qubits: The quantum socket. The quantum socket employs three-dimensional wires and makes it possible to connect classical electronics with quantum circuits more densely and accurately than methods based on wire bonding. The three-dimensional wires are based on spring-loaded pins engineered to insure compatibility with quantum computing applications. Extensive design work and machining was required, with focus on material quality to prevent magnetic impurities. Microwave simulations were undertaken to optimize the design, focusing on the interface between the micro-connector and an on-chip coplanar waveguide pad. Simulations revealed good performance from DC to 10 GHz and were later confirmed against experimental measurements.

Vertically Aligned and Interconnected Boron Nitride Nanosheets for Advanced Flexible Nanocomposite Thermal Interface Materials.

PubMed

Chen, Jin; Huang, Xingyi; Sun, Bin; Wang, Yuxin; Zhu, Yingke; Jiang, Pingkai

2017-09-13

The continuous evolution toward semiconductor technology in the "more-than-Moore" era and rapidly increasing power density of modern electronic devices call for advanced thermal interface materials (TIMs). Here, we report a novel strategy to construct flexible polymer nanocomposite TIMs for advanced thermal management applications. First, aligned polyvinyl alcohol (PVA) supported and interconnected 2D boron nitride nanosheets (BNNSs) composite fiber membranes were fabricated by electrospinning. Then, the nanocomposite TIMs were constructed by rolling the PVA/BNNS composite fiber membranes to form cylinders and subsequently vacuum-assisted impregnation of polydimethylsiloxane (PDMS) into the porous cylinders. The nanocomposite TIMs not only exhibit a superhigh through-plane thermal conductivity enhancement of about 10 times at a low BNNS loading of 15.6 vol % in comparison with the pristine PDMS but also show excellent electrical insulating property (i.e., high volume electrical resistivity). The outstanding thermal management capability of the nanocomposite TIMs was practically confirmed by capturing the surface temperature variations of a working LED chip integrated with the nanocomposite TIMs.

Technology achievements and projections for communication satellites of the future

NASA Technical Reports Server (NTRS)

Bagwell, J. W.

1986-01-01

Multibeam systems of the future using monolithic microwave integrated circuits to provide phase control and power gain are contrasted with discrete microwave power amplifiers from 10 to 75 W and their associated waveguide feeds, phase shifters and power splitters. Challenging new enabling technology areas include advanced electrooptical control and signal feeds. Large scale MMIC's will be used incorporating on chip control interfaces, latching, and phase and amplitude control with power levels of a few watts each. Beam forming algorithms for 80 to 90 deg. wide angle scanning and precise beam forming under wide ranging environments will be required. Satelllite systems using these dynamically reconfigured multibeam antenna systems will demand greater degrees of beam interconnectivity. Multiband and multiservice users will be interconnected through the same space platform. Monolithic switching arrays operating over a wide range of RF and IF frequencies are contrasted with current IF switch technology implemented discretely. Size, weight, and performance improvements by an order of magnitude are projected.

Multi-petascale highly efficient parallel supercomputer

DOEpatents

Asaad, Sameh; Bellofatto, Ralph E.; Blocksome, Michael A.; Blumrich, Matthias A.; Boyle, Peter; Brunheroto, Jose R.; Chen, Dong; Cher, Chen -Yong; Chiu, George L.; Christ, Norman; Coteus, Paul W.; Davis, Kristan D.; Dozsa, Gabor J.; Eichenberger, Alexandre E.; Eisley, Noel A.; Ellavsky, Matthew R.; Evans, Kahn C.; Fleischer, Bruce M.; Fox, Thomas W.; Gara, Alan; Giampapa, Mark E.; Gooding, Thomas M.; Gschwind, Michael K.; Gunnels, John A.; Hall, Shawn A.; Haring, Rudolf A.; Heidelberger, Philip; Inglett, Todd A.; Knudson, Brant L.; Kopcsay, Gerard V.; Kumar, Sameer; Mamidala, Amith R.; Marcella, James A.; Megerian, Mark G.; Miller, Douglas R.; Miller, Samuel J.; Muff, Adam J.; Mundy, Michael B.; O'Brien, John K.; O'Brien, Kathryn M.; Ohmacht, Martin; Parker, Jeffrey J.; Poole, Ruth J.; Ratterman, Joseph D.; Salapura, Valentina; Satterfield, David L.; Senger, Robert M.; Smith, Brian; Steinmacher-Burow, Burkhard; Stockdell, William M.; Stunkel, Craig B.; Sugavanam, Krishnan; Sugawara, Yutaka; Takken, Todd E.; Trager, Barry M.; Van Oosten, James L.; Wait, Charles D.; Walkup, Robert E.; Watson, Alfred T.; Wisniewski, Robert W.; Wu, Peng

2015-07-14

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

A MoTe2 based light emitting diode and photodetector for silicon photonic integrated circuits

NASA Astrophysics Data System (ADS)

Bie, Ya-Qing; Heuck, M.; Grosso, G.; Furchi, M.; Cao, Y.; Zheng, J.; Navarro-Moratalla, E.; Zhou, L.; Taniguchi, T.; Watanabe, K.; Kong, J.; Englund, D.; Jarillo-Herrero, P.

A key challenge in photonics today is to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, partly because many components such as waveguides, interferometers and modulators, could be integrated on silicon-based processors. However, light sources and photodetectors present continued challenges. Common approaches for light source include off-chip or wafer-bonded lasers based on III-V materials, but studies show advantages for directly modulated light sources. The most advanced photodetectors in silicon photonics are based on germanium growth which increases system cost. The emerging two dimensional transition metal dichalcogenides (TMDs) offer a path for optical interconnects components that can be integrated with the CMOS processing by back-end-of-the-line processing steps. Here we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe2, a TMD semiconductor with infrared band gap. The state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

Flexible multimode polymer waveguides for high-speed short-reach communication links

NASA Astrophysics Data System (ADS)

Bamiedakis, N.; Shi, F.; Chu, D.; Penty, R. V.; White, I. H.

2018-02-01

Multimode polymer waveguides have attracted great interest for use in high-speed short-reach communication links as they can be cost-effectively integrated onto standard PCBs using conventional methods of the electronics industry and provide low loss (<0.04 dB/cm at 850 nm) and high bandwidth (>30 GHz×m) interconnection. The formation of such waveguides on flexible substrates can further provide flexible low-weight low-thickness interconnects and offer additional freedom in the implementation of high-speed short-reach optical links. These attributes make these flexible waveguides particularly attractive for use in low-cost detachable chip-to-chip links and in environments where weight and shape conformity become important, such as in cars and aircraft. However, the highly-multimoded nature of these waveguides raises important questions about their performance under severe flex due to mode loss and mode coupling. In this work therefore, we investigate the loss, crosstalk and bandwidth performance of such waveguides under out-of plane bending and in-plane twisting under different launch conditions and carry out data transmission tests at 40 Gb/s on a 1 m long spiral flexible waveguide under flexure. Excellent optical transmission characteristics are obtained while robust loss, crosstalk and bandwidth performance are demonstrated under flexure. Error-free (BER<10-12) 40 Gb/s data transmission is achieved over the 1 m long spiral waveguide for a 180° bend with a 4 mm radius. The obtained results demonstrate the excellent optical and mechanical properties of this technology and highlight its potential for use in real-world systems.

Standard semiconductor packaging for high-reliability low-cost MEMS applications

NASA Astrophysics Data System (ADS)

Harney, Kieran P.

2005-01-01

Microelectronic packaging technology has evolved over the years in response to the needs of IC technology. The fundamental purpose of the package is to provide protection for the silicon chip and to provide electrical connection to the circuit board. Major change has been witnessed in packaging and today wafer level packaging technology has further revolutionized the industry. MEMS (Micro Electro Mechanical Systems) technology has created new challenges for packaging that do not exist in standard ICs. However, the fundamental objective of MEMS packaging is the same as traditional ICs, the low cost and reliable presentation of the MEMS chip to the next level interconnect. Inertial MEMS is one of the best examples of the successful commercialization of MEMS technology. The adoption of MEMS accelerometers for automotive airbag applications has created a high volume market that demands the highest reliability at low cost. The suppliers to these markets have responded by exploiting standard semiconductor packaging infrastructures. However, there are special packaging needs for MEMS that cannot be ignored. New applications for inertial MEMS devices are emerging in the consumer space that adds the imperative of small size to the need for reliability and low cost. These trends are not unique to MEMS accelerometers. For any MEMS technology to be successful the packaging must provide the basic reliability and interconnection functions, adding the least possible cost to the product. This paper will discuss the evolution of MEMS packaging in the accelerometer industry and identify the main issues that needed to be addressed to enable the successful commercialization of the technology in the automotive and consumer markets.

Standard semiconductor packaging for high-reliability low-cost MEMS applications

NASA Astrophysics Data System (ADS)

Harney, Kieran P.

2004-12-01

Microelectronic packaging technology has evolved over the years in response to the needs of IC technology. The fundamental purpose of the package is to provide protection for the silicon chip and to provide electrical connection to the circuit board. Major change has been witnessed in packaging and today wafer level packaging technology has further revolutionized the industry. MEMS (Micro Electro Mechanical Systems) technology has created new challenges for packaging that do not exist in standard ICs. However, the fundamental objective of MEMS packaging is the same as traditional ICs, the low cost and reliable presentation of the MEMS chip to the next level interconnect. Inertial MEMS is one of the best examples of the successful commercialization of MEMS technology. The adoption of MEMS accelerometers for automotive airbag applications has created a high volume market that demands the highest reliability at low cost. The suppliers to these markets have responded by exploiting standard semiconductor packaging infrastructures. However, there are special packaging needs for MEMS that cannot be ignored. New applications for inertial MEMS devices are emerging in the consumer space that adds the imperative of small size to the need for reliability and low cost. These trends are not unique to MEMS accelerometers. For any MEMS technology to be successful the packaging must provide the basic reliability and interconnection functions, adding the least possible cost to the product. This paper will discuss the evolution of MEMS packaging in the accelerometer industry and identify the main issues that needed to be addressed to enable the successful commercialization of the technology in the automotive and consumer markets.

Three-dimensional fit-to-flow microfluidic assembly.

PubMed

Chen, Arnold; Pan, Tingrui

2011-12-01

Three-dimensional microfluidics holds great promise for large-scale integration of versatile, digitalized, and multitasking fluidic manipulations for biological and clinical applications. Successful translation of microfluidic toolsets to these purposes faces persistent technical challenges, such as reliable system-level packaging, device assembly and alignment, and world-to-chip interface. In this paper, we extended our previously established fit-to-flow (F2F) world-to-chip interconnection scheme to a complete system-level assembly strategy that addresses the three-dimensional microfluidic integration on demand. The modular F2F assembly consists of an interfacial chip, pluggable alignment modules, and multiple monolithic layers of microfluidic channels, through which convoluted three-dimensional microfluidic networks can be easily assembled and readily sealed with the capability of reconfigurable fluid flow. The monolithic laser-micromachining process simplifies and standardizes the fabrication of single-layer pluggable polymeric modules, which can be mass-produced as the renowned Lego(®) building blocks. In addition, interlocking features are implemented between the plug-and-play microfluidic chips and the complementary alignment modules through the F2F assembly, resulting in facile and secure alignment with average misalignment of 45 μm. Importantly, the 3D multilayer microfluidic assembly has a comparable sealing performance as the conventional single-layer devices, providing an average leakage pressure of 38.47 kPa. The modular reconfigurability of the system-level reversible packaging concept has been demonstrated by re-routing microfluidic flows through interchangeable modular microchannel layers.

A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

NASA Technical Reports Server (NTRS)

Suarez, George; DuMonthier, Jeffrey J.; Sheikh, Salman S.; Powell, Wesley A.; King, Robyn L.

2012-01-01

Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

Biomimetic approaches for engineered organ chips and skin electronics for in vitro diagnostics

NASA Astrophysics Data System (ADS)

Suh, Kahp-Yang; Pang, Changhyun; Jang, Kyung-Jin; Kim, Hong Nam; Jiao, Alex; Hwang, Nathaniel S.; Kim, Min Sung; Kang, Do-Hyun; Kim, Deok-Ho

2012-10-01

Two kinds of biomimetic systems including engineered organ chip and flexible electronic sensor are presented. First, in vivo, renal tubular epithelial cells are exposed to luminal fluid shear stress (FSS) and a transepithelial osmotic gradient. In this study, we used a simple collecting-duct-on-a-chip to investigate the role of an altered luminal microenvironment in the translocation of aquaporin-2 (AQP2) and the reorganization of actin cytoskeleton (F-actin) in primary cultured inner medullary collecting duct (IMCD) cells of rat kidney. We demonstrate that several factors (i.e., luminal FSS, hormonal stimulation, transepithelial osmotic gradient) collectively exert a profound effect on the AQP2 trafficking in the collecting ducts, which is associated with actin cytoskeletal reorganization. Furthermore, with this kidney-mimicking chip, renal toxicity of cisplatin was tested under static and fluidic conditions, suggesting the physiological relevancy of fluidic environment compared to static culture. Second, we present a simple architecture for a flexible and highly sensitive strain sensor that enables the detection of pressure, shear and torsion. The device is based on two interlocked arrays of high-aspect-ratio Pt-coated polymeric nanofibres that are supported on thin polydimethylsiloxane layers. When different sensing stimuli are applied, the degree of interconnection and the electrical resistance of the sensor changes in a reversible, directional manner with specific, discernible strain-gauge factors. We show that the sensor can be used to monitor signals ranging from human heartbeats to the impact of a bouncing water droplet on a superhydrophobic surface.

Hemispherical and Longitudinal Asymmetries in the Heliospheric Magnetic Field: Flip-flops of a Bashful Ballerina

NASA Astrophysics Data System (ADS)

Hiltula, T.; Mursula, K.

2004-12-01

Several studies during many decennia have studied possible longitudinal and hemispherical asymmetries in various forms of solar activity. E.g., there are well known periods when one of the solar hemispheres has dominated the other in sunspot numbers, flare occurrence or some other form of solar activity. However, the solar asymmetries have not been found to be very conclusive, or to form any clear systematical patterns (e.g., relation to solar cycle). On the contrary, recent studies of similar longitudinal and hemispherical asymmetries in the heliospheric magnetic field have shown a very clear and systematic behaviour. E.g., it was found recently that the dominance of the two HMF sectors experiences an oscillation with a period of about 3.2 years. This new flip-flop periodicity in the heliospheric magnetic field is most likely related to a similar periodicity recently found in sunspots. Also, it has recently been found that the HMF sector coming from the northern solar hemisphere systematically dominates at 1AU during solar minimum times. This leads to a persistent southward shift or coning of the heliospheric current sheet at these times that can be picturesquely described by the concept of a Bashful Ballerina. This result also implies that the Sun has a large-scale quadrupole magnetic moment. Here we review these recent developments concerning the longitudinal and hemispherical asymmetries in the heliospheric magnetic field and study their inter-connection.

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

PubMed

Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

2018-04-01

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

Integrated Nanoscale Antenna-LED for On-Chip Optical Communication

NASA Astrophysics Data System (ADS)

Fortuna, Seth

Traditional semiconductor light emitting diodes (LEDs) have low modulation speed because of long spontaneous emission lifetime. Spontaneous emission in semiconductors (and indeed most light emitters) is an inherently slow process owing to the size mismatch between the dipole length of the optical dipole oscillators responsible for light emission and the wavelength of the emitted light. More simply stated: semiconductors behave as a poor antenna for its own light emission. By coupling a semiconductor at the nanoscale to an external antenna, the spontaneous emission rate can be dramatically increased alluding to the exciting possibility of an antenna-LED that can be directly modulated faster than the laser. Such an antenna-LED is well-suited as a light source for on-chip optical communication where small size, fast speed, and high efficiency are needed to achieve the promised benefit of reduced power consumption of on-chip optical interconnect links compared with less efficient electrical interconnect links. Despite the promise of the antenna-LED, significant challenges remain to implement an antenna-coupled device in a monolithically integrated manner. Notably, most demonstrations of antenna-enhanced spontaneous emission have relied upon optical pumping of the light emitting material which is useful for fundamental studies; however, an electrical injection scheme is required for practical implementation of an antenna-LED. In this dissertation, demonstration of an electrically-injected III-V antenna-LED is reported: an important milestone toward on-chip optical interconnects. In the first part of this dissertation, the general design principles of enhancing the spontaneous emission rate of a semiconductor with an optical antenna is discussed. The cavity-backed slot antenna is shown to be uniquely suited for an electrically-injected antenna-LED because of large spontaneous emission enhancement, simple fabrication, and directional emission of light. The design, fabrication, and experimental results of the electrically-injected III-V antenna-LED is then presented. Clear evidence of antenna-enhanced electroluminescence is demonstrated including a large increase in the emitted light intensity with respect to an LED without antenna. Furthermore, it is shown that the active region emission wavelength is influenced by the antenna resonance and the emitted light is polarized; consistent with the expected behavior of the cavity-backed slot antenna. An antenna-LED consisting of a InGaAs quantum well active region is shown to have a large 200-fold enhancement of the spontaneous emission rate. In the last half of this dissertation, the performance of the antenna-LED is discussed. Remarkably, despite the high III-V surface recombination velocity, it is shown that an efficient antenna-LED consisting of an InGaAs active region is possible with an antenna-enhanced spontaneous emission rate. This is true provided the active region surface quality is preserved through the entire device process. A novel technique to preserve and clean InGaAs surfaces is reported. Finally, a rate-equation analysis shows that the optimized antenna-LED with cavity-backed slot antenna is fundamentally capable of achieving greater than 100 GHz direct modulation rate at high efficiency thus showing that an antenna-LED faster than the laser is achievable with this device architecture.

Laser Direct Routing for High Density Interconnects

NASA Astrophysics Data System (ADS)

Moreno, Wilfrido Alejandro

The laser restructuring of electronic circuits fabricated using standard Very Large Scale Integration (VLSI) process techniques, is an excellent alternative that allows low-cost quick turnaround production with full circuit similarity between the Laser Restructured prototype and the customized product for mass production. Laser Restructurable VLSI (LRVLSI) would allow design engineers the capability to interconnect cells that implement generic logic functions and signal processing schemes to achieve a higher level of design complexity. LRVLSI of a particular circuit at the wafer or packaged chip level is accomplished using an integrated computer controlled laser system to create low electrical resistance links between conductors and to cut conductor lines. An infrastructure for rapid prototyping and quick turnaround using Laser Restructuring of VLSI circuits was developed to meet three main parallel objectives: to pursue research on novel interconnect technologies using LRVLSI, to develop the capability of operating in a quick turnaround mode, and to maintain standardization and compatibility with commercially available equipment for feasible technology transfer. The system is to possess a high degree of flexibility, high data quality, total controllability, full documentation, short downtime, a user-friendly operator interface, automation, historical record keeping, and error indication and logging. A specially designed chip "SLINKY" was used as the test vehicle for the complete characterization of the Laser Restructuring system. With the use of Design of Experiment techniques the Lateral Diffused Link (LDL), developed originally at MIT Lincoln Laboratories, was completely characterized and for the first time a set of optimum process parameters was obtained. With the designed infrastructure fully operational, the priority objective was the search for a substitute for the high resistance, high current leakage to substrate, and relatively low density Lateral Diffused Link. A high density Laser Vertical Link with resistance values below 10 ohms was developed, studied and tested using design of experiment methodologies. The vertical link offers excellent advantages in the area of quick prototyping of electronic circuits, but even more important, due to having similar characteristics to a foundry produced via, it gives quick transfer from the prototype system verification stage to the mass production stage.

Single-Chip CMUT-on-CMOS Front-End System for Real-Time Volumetric IVUS and ICE Imaging

PubMed Central

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F. Levent

2014-01-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of CMUT arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-µm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-µm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single-chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex-vivo chicken heart sample. The measured axial and lateral point resolutions are 92 µm and 251 µm, respectively. We successfully acquired volumetric imaging data from the ex-vivo chicken heart with 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce real-time volumetric images with image quality and speed suitable for catheter based clinical applications. PMID:24474131

A microfluidic circulatory system integrated with capillary-assisted pressure sensors.

PubMed

Chen, Yangfan; Chan, Ho Nam; Michael, Sean A; Shen, Yusheng; Chen, Yin; Tian, Qian; Huang, Lu; Wu, Hongkai

2017-02-14

The human circulatory system comprises a complex network of blood vessels interconnecting biologically relevant organs and a heart driving blood recirculation throughout this system. Recreating this system in vitro would act as a bridge between organ-on-a-chip and "body-on-a-chip" and advance the development of in vitro models. Here, we present a microfluidic circulatory system integrated with an on-chip pressure sensor to closely mimic human systemic circulation in vitro. A cardiac-like on-chip pumping system is incorporated in the device. It consists of four pumping units and passive check valves, which mimic the four heart chambers and heart valves, respectively. Each pumping unit is independently controlled with adjustable pressure and pump rate, enabling users to control the mimicked blood pressure and heartbeat rate within the device. A check valve is located downstream of each pumping unit to prevent backward leakage. Pulsatile and unidirectional flow can be generated to recirculate within the device by programming the four pumping units. We also report an on-chip capillary-assisted pressure sensor to monitor the pressure inside the device. One end of the capillary was placed in the measurement region, while the other end was sealed. Time-dependent pressure changes were measured by recording the movement of the liquid-gas interface in the capillary and calculating the pressure using the ideal gas law. The sensor covered the physiologically relevant blood pressure range found in humans (0-142.5 mmHg) and could respond to 0.2 s actuation time. With the aid of the sensor, the pressure inside the device could be adjusted to the desired range. As a proof of concept, human normal left ventricular and arterial pressure profiles were mimicked inside this device. Human umbilical vein endothelial cells (HUVECs) were cultured on chip and cells can respond to mechanical forces generated by arterial-like flow patterns.

Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

PubMed

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

2014-02-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

Hybrid indium phosphide-on-silicon nanolaser diode

NASA Astrophysics Data System (ADS)

Crosnier, Guillaume; Sanchez, Dorian; Bouchoule, Sophie; Monnier, Paul; Beaudoin, Gregoire; Sagnes, Isabelle; Raj, Rama; Raineri, Fabrice

2017-04-01

The most-awaited convergence of microelectronics and photonics promises to bring about a revolution for on-chip data communications and processing. Among all the optoelectronic devices to be developed, power-efficient nanolaser diodes able to be integrated densely with silicon photonics and electronics are essential to convert electrical data into the optical domain. Here, we report a demonstration of ultracompact laser diodes based on one-dimensional (1D) photonic crystal (PhC) nanocavities made in InP nanoribs heterogeneously integrated on a silicon-waveguide circuitry. The specific nanorib design enables an efficient electrical injection of carriers in the nanocavity without spoiling its optical properties. Room-temperature continuous-wave (CW) single-mode operation is obtained with a low current threshold of 100 µA. Laser emission at 1.56 µm in the silicon waveguides is obtained with wall-plug efficiencies greater than 10%. This result opens up exciting avenues for constructing optical networks at the submillimetre scale for on-chip interconnects and signal processing.

High-Responsivity Graphene-Boron Nitride Photodetector and Autocorrelator in a Silicon Photonic Integrated Circuit.

PubMed

Shiue, Ren-Jye; Gao, Yuanda; Wang, Yifei; Peng, Cheng; Robertson, Alexander D; Efetov, Dmitri K; Assefa, Solomon; Koppens, Frank H L; Hone, James; Englund, Dirk

2015-11-11

Graphene and other two-dimensional (2D) materials have emerged as promising materials for broadband and ultrafast photodetection and optical modulation. These optoelectronic capabilities can augment complementary metal-oxide-semiconductor (CMOS) devices for high-speed and low-power optical interconnects. Here, we demonstrate an on-chip ultrafast photodetector based on a two-dimensional heterostructure consisting of high-quality graphene encapsulated in hexagonal boron nitride. Coupled to the optical mode of a silicon waveguide, this 2D heterostructure-based photodetector exhibits a maximum responsivity of 0.36 A/W and high-speed operation with a 3 dB cutoff at 42 GHz. From photocurrent measurements as a function of the top-gate and source-drain voltages, we conclude that the photoresponse is consistent with hot electron mediated effects. At moderate peak powers above 50 mW, we observe a saturating photocurrent consistent with the mechanisms of electron-phonon supercollision cooling. This nonlinear photoresponse enables optical on-chip autocorrelation measurements with picosecond-scale timing resolution and exceptionally low peak powers.

A sub-femtojoule electrical spin-switch based on optically trapped polariton condensates.

PubMed

Dreismann, Alexander; Ohadi, Hamid; Del Valle-Inclan Redondo, Yago; Balili, Ryan; Rubo, Yuri G; Tsintzos, Simeon I; Deligeorgis, George; Hatzopoulos, Zacharias; Savvidis, Pavlos G; Baumberg, Jeremy J

2016-10-01

Practical challenges to extrapolating Moore's law favour alternatives to electrons as information carriers. Two promising candidates are spin-based and all-optical architectures, the former offering lower energy consumption, the latter superior signal transfer down to the level of chip-interconnects. Polaritons-spinor quasi-particles composed of semiconductor excitons and microcavity photons-directly couple exciton spins and photon polarizations, combining the advantages of both approaches. However, their implementation for spintronics has been hindered because polariton spins can be manipulated only optically or by strong magnetic fields. Here we use an external electric field to directly control the spin of a polariton condensate, bias-tuning the emission polarization. The nonlinear spin dynamics offers an alternative route to switching, allowing us to realize an electrical spin-switch exhibiting ultralow switching energies below 0.5 fJ. Our results lay the foundation for development of devices based on the electro-optical control of coherent spin ensembles on a chip.

Reconfigurable microfluidic hanging drop network for multi-tissue interaction and analysis.

PubMed

Frey, Olivier; Misun, Patrick M; Fluri, David A; Hengstler, Jan G; Hierlemann, Andreas

2014-06-30

Integration of multiple three-dimensional microtissues into microfluidic networks enables new insights in how different organs or tissues of an organism interact. Here, we present a platform that extends the hanging-drop technology, used for multi-cellular spheroid formation, to multifunctional complex microfluidic networks. Engineered as completely open, 'hanging' microfluidic system at the bottom of a substrate, the platform features high flexibility in microtissue arrangements and interconnections, while fabrication is simple and operation robust. Multiple spheroids of different cell types are formed in parallel on the same platform; the different tissues are then connected in physiological order for multi-tissue experiments through reconfiguration of the fluidic network. Liquid flow is precisely controlled through the hanging drops, which enable nutrient supply, substance dosage and inter-organ metabolic communication. The possibility to perform parallelized microtissue formation on the same chip that is subsequently used for complex multi-tissue experiments renders the developed platform a promising technology for 'body-on-a-chip'-related research.

Heterogeneously integrated silicon photonics for the mid-infrared and spectroscopic sensing.

PubMed

Chen, Yu; Lin, Hongtao; Hu, Juejun; Li, Mo

2014-07-22

Besides being the foundational material for microelectronics, crystalline silicon has long been used for the production of infrared lenses and mirrors. More recently, silicon has become the key material to achieve large-scale integration of photonic devices for on-chip optical interconnect and signal processing. For optics, silicon has significant advantages: it offers a very high refractive index and is highly transparent in the spectral range from 1.2 to 8 μm. To fully exploit silicon’s superior performance in a remarkably broad range and to enable new optoelectronic functionalities, here we describe a general method to integrate silicon photonic devices on arbitrary foreign substrates. In particular, we apply the technique to integrate silicon microring resonators on mid-infrared compatible substrates for operation in the mid-infrared. These high-performance mid-infrared optical resonators are utilized to demonstrate, for the first time, on-chip cavity-enhanced mid-infrared spectroscopic analysis of organic chemicals with a limit of detection of less than 0.1 ng.

Surface-Wave Pulse Routing around Sharp Right Angles

NASA Astrophysics Data System (ADS)

Gao, Z.; Xu, H.; Gao, F.; Zhang, Y.; Luo, Y.; Zhang, B.

2018-04-01

Surface-plasmon polaritons (SPPs), or localized electromagnetic surface waves propagating on a metal-dielectric interface, are deemed promising information carriers for future subwavelength terahertz and optical photonic circuitry. However, surface waves fundamentally suffer from scattering loss when encountering sharp corners in routing and interconnection of photonic signals. Previous approaches enabling scattering-free surface-wave guidance around sharp corners are limited to either volumetric waveguide environments or extremely narrow bandwidth, being unable to guide a surface-wave pulse (SPP wave packet) on an on-chip platform. Here, in a surface-wave band-gap crystal implemented on a single metal surface, we demonstrate in time-domain routing a surface-wave pulse around multiple sharp right angles without perceptible scattering. Our work not only offers a solution to on-chip surface-wave pulse routing along an arbitrary path, but it also provides spatiotemporal information on the interplay between surface-wave pulses and sharp corners, both of which are desirable in developing high-performance large-scale integrated photonic circuits.

Portable guided-mode resonance biosensor platform for point-of-care testing

NASA Astrophysics Data System (ADS)

Sung, Gun Yong; Kim, Wan-Joong; Ko, Hyunsung; Kim, Bong K.; Kim, Kyung-Hyun; Huh, Chul; Hong, Jongcheol

2012-10-01

It represents a viable solution for the realization of a portable biosensor platform that could screen/diagnose acute myocardial infarction by measuring cardiac marker concentrations such as cardiac troponin I (cTnI), creatine kinase MB (CK-MB), and myoglobin (MYO) for application to u-health monitoring system. The portable biosensor platform introduced in this presentation has a more compact structure and a much higher measuring resolution than a conventional spectrometer system. Portable guided-mode resonance (GMR) biosensor platform was composed of a biosensor chip stage, an optical pick-up module, and a data display panel. Disposable plastic GMR biosensor chips with nano-grating patterns were fabricated by injection-molding. Whole blood filtration and label-free immunoassay were performed on these single chips, automatically. Optical pick-up module was fabricated by using the miniaturized bulk optics and the interconnecting optical fibers and a tunable VCSEL (vertical cavity surface emitting laser). The reflectance spectrum from the GMR biosensor was measured by the optical pick-up module. Cardiac markers in human serum with concentrations less than 0.1ng/mL were analyzed using a GMR biosensor. Analysis time was 30min, which is short enough to meet clinical requirements. Our results show that the GMR biosensor will be very useful in developing lowcost portable biosensors that can screen for cardiac diseases.