3D integrated superconducting qubits

NASA Astrophysics Data System (ADS)

Rosenberg, D.; Kim, D.; Das, R.; Yost, D.; Gustavsson, S.; Hover, D.; Krantz, P.; Melville, A.; Racz, L.; Samach, G. O.; Weber, S. J.; Yan, F.; Yoder, J. L.; Kerman, A. J.; Oliver, W. D.

2017-10-01

As the field of quantum computing advances from the few-qubit stage to larger-scale processors, qubit addressability and extensibility will necessitate the use of 3D integration and packaging. While 3D integration is well-developed for commercial electronics, relatively little work has been performed to determine its compatibility with high-coherence solid-state qubits. Of particular concern, qubit coherence times can be suppressed by the requisite processing steps and close proximity of another chip. In this work, we use a flip-chip process to bond a chip with superconducting flux qubits to another chip containing structures for qubit readout and control. We demonstrate that high qubit coherence (T1, T2,echo > 20 μs) is maintained in a flip-chip geometry in the presence of galvanic, capacitive, and inductive coupling between the chips.

CSP Manufacturing Challenges and Assembly Reliability

NASA Technical Reports Server (NTRS)

Ghaffarian, Reza

2000-01-01

Although the expression of CSP is widely used by industry from suppliers to users, its implied definition had evolved as the technology has matured. There are "expert definition"- package that is up to 1.5 time die- or "interim definition". CSPs are miniature new packages that industry is starting to implement and there are many unresolved technical issues associated with their implementation. For example, in early 1997, packages with 1 mm pitch and lower were the dominant CSPs, whereas in early 1998 packages with 0.8 mm and lower became the norm for CSPs. Other changes included the use of flip chip die rather than wire bond in CSP. Nonetheless the emerging CSPs are competing with bare die assemblies and are becoming the package of choice for size reduction applications. These packages provide the benefits of small size and performance of the bare die or flip chip, with the advantage of standard die packages. The JPL-led MicrotypeBGA Consortium of enterprises representing government agencies and private companies have jointed together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. This talk will cover specifically the experience of our consortium on technology implementation challenges, including design and build of both standard and microvia boards, assembly of two types of test vehicles, and the most current environmental thermal cycling test results.

Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments.

PubMed

Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

2015-08-18

In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a "one-sensor-one-packaging_technology" concept. The second one uses a standard flip-chip bonding technique. The first sensor is a "floating-concept", capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not "floating" but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

Low temperature co-fired ceramic packaging of CMOS capacitive sensor chip towards cell viability monitoring.

PubMed

Halonen, Niina; Kilpijärvi, Joni; Sobocinski, Maciej; Datta-Chaudhuri, Timir; Hassinen, Antti; Prakash, Someshekar B; Möller, Peter; Abshire, Pamela; Kellokumpu, Sakari; Lloyd Spetz, Anita

2016-01-01

Cell viability monitoring is an important part of biosafety evaluation for the detection of toxic effects on cells caused by nanomaterials, preferably by label-free, noninvasive, fast, and cost effective methods. These requirements can be met by monitoring cell viability with a capacitance-sensing integrated circuit (IC) microchip. The capacitance provides a measurement of the surface attachment of adherent cells as an indication of their health status. However, the moist, warm, and corrosive biological environment requires reliable packaging of the sensor chip. In this work, a second generation of low temperature co-fired ceramic (LTCC) technology was combined with flip-chip bonding to provide a durable package compatible with cell culture. The LTCC-packaged sensor chip was integrated with a printed circuit board, data acquisition device, and measurement-controlling software. The packaged sensor chip functioned well in the presence of cell medium and cells, with output voltages depending on the medium above the capacitors. Moreover, the manufacturing of microfluidic channels in the LTCC package was demonstrated.

Advanced Flip Chips in Extreme Temperature Environments

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni

2010-01-01

The use of underfill materials is necessary with flip-chip interconnect technology to redistribute stresses due to mismatching coefficients of thermal expansion (CTEs) between dissimilar materials in the overall assembly. Underfills are formulated using organic polymers and possibly inorganic filler materials. There are a few ways to apply the underfills with flip-chip technology. Traditional capillary-flow underfill materials now possess high flow speed and reduced time to cure, but they still require additional processing steps beyond the typical surface-mount technology (SMT) assembly process. Studies were conducted using underfills in a temperature range of -190 to 85 C, which resulted in an increase of reliability by one to two orders of magnitude. Thermal shock of the flip-chip test articles was designed to induce failures at the interconnect sites (-40 to 100 C). The study on the reliability of flip chips using underfills in the extreme temperature region is of significant value for space applications. This technology is considered as an enabling technology for future space missions. Flip-chip interconnect technology is an advanced electrical interconnection approach where the silicon die or chip is electrically connected, face down, to the substrate by reflowing solder bumps on area-array metallized terminals on the die to matching footprints of solder-wettable pads on the chosen substrate. This advanced flip-chip interconnect technology will significantly improve the performance of high-speed systems, productivity enhancement over manual wire bonding, self-alignment during die joining, low lead inductances, and reduced need for attachment of precious metals. The use of commercially developed no-flow fluxing underfills provides a means of reducing the processing steps employed in the traditional capillary flow methods to enhance SMT compatibility. Reliability of flip chips may be significantly increased by matching/tailoring the CTEs of the substrate material and the silicon die or chip, and also the underfill materials. Advanced packaging interconnects technology such as flip-chip interconnect test boards have been subjected to various extreme temperature ranges that cover military specifications and extreme Mars and asteroid environments. The eventual goal of each process step and the entire process is to produce components with 100 percent interconnect and satisfy the reliability requirements. Underfill materials, in general, may possibly meet demanding end use requirements such as low warpage, low stress, fine pitch, high reliability, and high adhesion.

Silver flip chip interconnect technology and solid state bonding

NASA Astrophysics Data System (ADS)

Sha, Chu-Hsuan

In this dissertation, fluxless transient liquid phase (TLP) bonding and solid state bonding between thermal expansion mismatch materials have been developed using Ag-In binary systems, pure Au, Ag, and Cu-Ag composite. In contrast to the conventional soldering process, fluxless bonding technique eliminates any corrosion and contamination problems caused by flux. Without flux, it is possible to fabricate high quality joints in large bonding areas where the flux is difficult to clean entirely. High quality joints are crucial to bonding thermal expansion mismatch materials since shear stress develops in the bonded pair. Stress concentration at voids in joints could increases breakage probability. In addition, intermetallic compound (IMC) formation between solder and underbump metallurgy (UBM) is essential for interconnect joint formation in conventional soldering process. However, the interface between IMC and solder is shown to be the weak interface that tends to break first during thermal cycling and drop tests. In our solid state bonding technique, there is no IMC involved in the bonding between Au to Au, Ag and Cu, and Ag and Au. All the reliability issues related to IMC or IMC growth is not our concern. To sum up, ductile bonding media, such as Ag or Au, and proper metallic layered structure are utilized in this research to produce high quality joints. The research starts with developing a low temperature fluxless bonding process using electroplated Ag/In/Ag multilayer structures between Si chip and 304 stainless steel (304SS) substrate. Because the outer thin Ag layer effectively protects inner In layer from oxidation, In layer dissolves Ag layer and joints to Ag layer on the to-be-bonded Si chip when temperature reaches the reflow temperature of 166ºC. Joints consist of mainly Ag-rich Ag-In solid solution and Ag2In. Using this fluxless bonding technique, two 304SS substrates can be bonded together as well. From the high magnification SEM images taken at cross-section, there is no void or gap observed. The new bonding technique presented should be valuable in packaging high power electronic devices for high temperature operations. It should also be useful to bond two 304SS parts together at low bonding temperature of 190ºC. Solid state bonding technique is then introduced to bond semiconductor chips, such as Si, to common substrates, such as Cu or alumina, using pure Ag and Au at a temperature matching the typical reflow temperature used in packaging industries, 260°C. In bonding, we realize the possibilities of solid state bonding of Au to Au, Au to Ag, and Ag to Cu. The idea comes from that Cu, Ag, and Au are located in the same column on periodic table, meaning that they have similar electronic configuration. They therefore have a better chance to share electrons. Also, the crystal lattice of Cu, Ag, and Au is the same, face-centered cubic. In the project, the detailed bonding mechanism is beyond the scope and here we determine the bonding by the experimental result. Ag is chosen as the joint material because of its superior physical properties. It has the highest electrical and thermal conductivities among all metals. It has low yield strength and is relatively ductile. Au is considered as well because its excellent ductility and fatigue resistance. Thus, the Ag or Au joints can deform to accommodate the shear strain caused by CTE mismatch between Si and Cu. Ag and Au have melting temperatures higher than 950°C, so the pure Ag or Au joints are expected to sustain in high operating temperature. The resulting joints do not contain any intermetallic compound. Thus, all reliability issues associated with intermetallic growth in commonly used solder joints do not exist anymore. We finally move to the applications of solid state Ag bonding in flip chip interconnects design. At present, nearly all large-scale integrated circuit (IC) chips are packaged with flip-chip technology. This means that the chip is flipped over and the active (front) side is connected to the package using a large number of tiny solder joints, which provide mechanical support, electrical connection, and heat conduction. For chip-to-package level interconnects, a challenge is the severe mismatch in coefficient of thermal expansion (CTE) between chips and package substrates. The interconnect material thus needs to be compliant to deal with the CTE mismatch. At present, nearly all flip-chip interconnects in electronic industries are made of lead-free Sn-based solders. Soft solders are chosen due to high ductility, low yield strength, relatively low melting temperature, and reasonably good electrical and thermal conductivities. In the never ending scaling down trend, more and more transistors are placed on the same Si chip size. This results in larger pin-out numbers and smaller solder joints. According to International Technology Roadmap for Semiconductors (ITRS), by 2018, the pitch in flip-chip interconnects will become smaller than 70mum for high performance applications. Two problems occur. The first is increase in shear strain. The aspect ratio of flip-chip joints is constrained to 0.7 because it goes through molten phase in the reflow process. Therefore, smaller joints become shorter as well, resulting in larger shear strain arising from CTE mismatch between Si chips and package substrates. The second is increase in stress in the joints. Since intermetallic (IMC) thickness in the joint does not scale down with joint size, ratio of IMC thickness to joint height increases. This further enlarges the shear stress because the IMC does not deform as the soft solder does to accommodate CTE mismatch. In this research, the smallest dimension we achieve for Ag flip chip interconnect joint is 15mum in diameter. The ten advantages of Ag flip chip interconnect technology can be identified as (a) High electrical conductivity, 7.7 times of that of Pb-free solders, (b) High thermal conductivity, 5.2 times of that of Pb-free solders, (c) Completely fluxless, (d) No IMCs; all reliability issues associated with IMC and IMC growth do not exist, (e) Ag is very ductile and can manage CTE mismatch between chips and packages, (f) Ag joints can sustain at very high operation temperature because Ag has high melting temperature of 961°C, (g) No molten phase involved; the bump can better keep its shape and geometry, (h) No molten phase involved; bridging of adjacent bumps is less likely to occur, i. Aspect ratio of bumps can be made greater than 1, (j) The size of the bumps is only limited by the lithographic process. Cu-Ag composite flip chip interconnect joints is developed based on three reasons. The first is lower material cost. The second is to strengthen the columns because the yield strength of Cu is 6 times of that of Ag. The third is to avoid possible Ag migration between Ag electrodes under voltage at temperatures above 250°C. This Cu-Ag composite design presents a solution in the path to the scale down roadmap.

Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments

PubMed Central

Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

2015-01-01

In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a “one-sensor-one-packaging_technology” concept. The second one uses a standard flip-chip bonding technique. The first sensor is a “floating-concept”, capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not “floating” but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA. PMID:26295235

Microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2002-01-01

An apparatus for packaging of microelectronic devices, including an integral window. The microelectronic device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The package can include a cofired ceramic frame or body. The package can have an internal stepped structure made of one or more plates, with apertures, which are patterned with metallized conductive circuit traces. The microelectronic device can be flip-chip bonded on the plate to these traces, and oriented so that the light-sensitive side is optically accessible through the window. A cover lid can be attached to the opposite side of the package. The result is a compact, low-profile package, having an integral window that can be hermetically-sealed. The package body can be formed by low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the window being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. Multiple chips can be located within a single package. The cover lid can include a window. The apparatus is particularly suited for packaging of MEMS devices, since the number of handling steps is greatly reduced, thereby reducing the potential for contamination.

Flip chip bumping technology—Status and update

NASA Astrophysics Data System (ADS)

Juergen Wolf, M.; Engelmann, Gunter; Dietrich, Lothar; Reichl, Herbert

2006-09-01

Flip chip technology is a key driver for new complex system architectures and high-density packaging, e.g. sensor or pixel devices. Bumped wafers/dice as key elements become very important in terms of general availability at low cost, high yield and quality level. Today, different materials, e.g. Au, Ni, AuSn, SnAg, SnAgCu, SnCu, etc., are used for flip chip interconnects and different bumping approaches are available. Electroplating is the technology of choice for high-yield wafer bumping for small bump sizes and pitches. Lead-free solder bumps require an increase in knowledge in the field of under bump metallization (UBM) and the interaction of bump and substrate metallization, the formation and growth of intermetallic compounds (IMCs) during liquid- and solid-phase reactions. Results of a new bi-layer UBM of Ni-Cu which is especially designed for small-sized lead-free solder bumps will be discussed.

Laser-induced forward transfer for flip-chip packaging of single dies.

PubMed

Kaur, Kamal S; Van Steenberge, Geert

2015-03-20

Flip-chip (FC) packaging is a key technology for realizing high performance, ultra-miniaturized and high-density circuits in the micro-electronics industry. In this technique the chip and/or the substrate is bumped and the two are bonded via these conductive bumps. Many bumping techniques have been developed and intensively investigated since the introduction of the FC technology in 1960(1) such as stencil printing, stud bumping, evaporation and electroless/electroplating2. Despite the progress that these methods have made they all suffer from one or more than one drawbacks that need to be addressed such as cost, complex processing steps, high processing temperatures, manufacturing time and most importantly the lack of flexibility. In this paper, we demonstrate a simple and cost-effective laser-based bump forming technique known as Laser-induced Forward Transfer (LIFT)3. Using the LIFT technique a wide range of bump materials can be printed in a single-step with great flexibility, high speed and accuracy at RT. In addition, LIFT enables the bumping and bonding down to chip-scale, which is critical for fabricating ultra-miniature circuitry.

Flexible packaging of solid-state integrated circuit chips with elastomeric microfluidics

PubMed Central

Zhang, Bowei; Dong, Quan; Korman, Can E.; Li, Zhenyu; Zaghloul, Mona E.

2013-01-01

A flexible technology is proposed to integrate smart electronics and microfluidics all embedded in an elastomer package. The microfluidic channels are used to deliver both liquid samples and liquid metals to the integrated circuits (ICs). The liquid metals are used to realize electrical interconnects to the IC chip. This avoids the traditional IC packaging challenges, such as wire-bonding and flip-chip bonding, which are not compatible with current microfluidic technologies. As a demonstration we integrated a CMOS magnetic sensor chip and associate microfluidic channels on a polydimethylsiloxane (PDMS) substrate that allows precise delivery of small liquid samples to the sensor. Furthermore, the packaged system is fully functional under bending curvature radius of one centimetre and uniaxial strain of 15%. The flexible integration of solid-state ICs with microfluidics enables compact flexible electronic and lab-on-a-chip systems, which hold great potential for wearable health monitoring, point-of-care diagnostics and environmental sensing among many other applications.

Chip-scale thermal management of high-brightness LED packages

NASA Astrophysics Data System (ADS)

Arik, Mehmet; Weaver, Stanton

2004-10-01

The efficiency and reliability of the solid-state lighting devices strongly depend on successful thermal management. Light emitting diodes, LEDs, are a strong candidate for the next generation, general illumination applications. LEDs are making great strides in terms of lumen performance and reliability, however the barrier to widespread use in general illumination still remains the cost or $/Lumen. LED packaging designers are pushing the LED performance to its limits. This is resulting in increased drive currents, and thus the need for lower thermal resistance packaging designs. As the power density continues to rise, the integrity of the package electrical and thermal interconnect becomes extremely important. Experimental results with high brightness LED packages show that chip attachment defects can cause significant thermal gradients across the LED chips leading to premature failures. A numerical study was also carried out with parametric models to understand the chip active layer temperature profile variation due to the bump defects. Finite element techniques were utilized to evaluate the effects of localized hot spots at the chip active layer. The importance of "zero defects" in one of the more popular interconnect schemes; the "epi down" soldered flip chip configuration is investigated and demonstrated.

Chip-scale white flip-chip light-emitting diode containing indium phosphide/zinc selenide quantum dots

NASA Astrophysics Data System (ADS)

Fan, Bingfeng; Yan, Linchao; Lao, Yuqin; Ma, Yanfei; Chen, Zimin; Ma, Xuejin; Zhuo, Yi; Pei, Yanli; Wang, Gang

2017-08-01

A method for preparing a quantum dot (QD)-white light-emitting diode (WLED) is reported. Holes were etched in the SiO2 layer deposited on the sapphire substrate of the flip-chip LED by inductively coupled plasma, and these holes were then filled with QDs. An ultraviolet-curable resin was then spin-coated on top of the QD-containing SiO2 layer, and the resin was cured to act as a protecting layer. The reflective sidewall structure minimized sidelight leakage. The fabrication of the QD-WLED is simple in preparation and compatible with traditional LED processes, which was the minimum size of the WLED chip-scale integrated package. InP/ZnS core-shell QDs were used as the converter in the WLED. A blue light-emitting diode with a flip-chip structure was used as the excitation source. The QD-WLED exhibited color temperatures from 5900 to 6400 K and Commission Internationale De L'Elcairage color coordinates from (0.315, 0.325) to (0.325, 0.317), under drive currents from 100 to 400 mA. The QD-WLED exhibited stable optoelectronic properties.

A novel model for simulating the racing effect in capillary-driven underfill process in flip chip

NASA Astrophysics Data System (ADS)

Zhu, Wenhui; Wang, Kanglun; Wang, Yan

2018-04-01

Underfill is typically applied in flip chips to increase the reliability of the electronic packagings. In this paper, the evolution of the melt-front shape of the capillary-driven underfill flow is studied through 3D numerical analysis. Two different models, the prevailing surface force model and the capillary model based on the wetted wall boundary condition, are introduced to test their applicability, where level set method is used to track the interface of the two phase flow. The comparison between the simulation results and experimental data indicates that, the surface force model produces better prediction on the melt-front shape, especially in the central area of the flip chip. Nevertheless, the two above models cannot simulate properly the racing effect phenomenon that appears during underfill encapsulation. A novel ‘dynamic pressure boundary condition’ method is proposed based on the validated surface force model. Utilizing this approach, the racing effect phenomenon is simulated with high precision. In addition, a linear relationship is derived from this model between the flow front location at the edge of the flip chip and the filling time. Using the proposed approach, the impact of the underfill-dispensing length on the melt-front shape is also studied.

AIN-Based Packaging for SiC High-Temperature Electronics

NASA Technical Reports Server (NTRS)

Savrun, Ender

2004-01-01

Packaging made primarily of aluminum nitride has been developed to enclose silicon carbide-based integrated circuits (ICs), including circuits containing SiC-based power diodes, that are capable of operation under conditions more severe than can be withstood by silicon-based integrated circuits. A major objective of this development was to enable packaged SiC electronic circuits to operate continuously at temperatures up to 500 C. AlN-packaged SiC electronic circuits have commercial potential for incorporation into high-power electronic equipment and into sensors that must withstand high temperatures and/or high pressures in diverse applications that include exploration in outer space, well logging, and monitoring of nuclear power systems. This packaging embodies concepts drawn from flip-chip packaging of silicon-based integrated circuits. One or more SiC-based circuit chips are mounted on an aluminum nitride package substrate or sandwiched between two such substrates. Intimate electrical connections between metal conductors on the chip(s) and the metal conductors on external circuits are made by direct bonding to interconnections on the package substrate(s) and/or by use of holes through the package substrate(s). This approach eliminates the need for wire bonds, which have been the most vulnerable links in conventional electronic circuitry in hostile environments. Moreover, the elimination of wire bonds makes it possible to pack chips more densely than was previously possible.

AE (Acoustic Emission) for Flip-Chip CGA/FCBGA Defect Detection

NASA Technical Reports Server (NTRS)

Ghaffarian, Reza

2014-01-01

C-mode scanning acoustic microscopy (C-SAM) is a nondestructive inspection technique that uses ultrasound to show the internal feature of a specimen. A very high or ultra-high-frequency ultrasound passes through a specimen to produce a visible acoustic microimage (AMI) of its inner features. As ultrasound travels into a specimen, the wave is absorbed, scattered or reflected. The response is highly sensitive to the elastic properties of the materials and is especially sensitive to air gaps. This specific characteristic makes AMI the preferred method for finding "air gaps" such as delamination, cracks, voids, and porosity. C-SAM analysis, which is a type of AMI, was widely used in the past for evaluation of plastic microelectronic circuits, especially for detecting delamination of direct die bonding. With the introduction of the flip-chip die attachment in a package; its use has been expanded to nondestructive characterization of the flip-chip solder bumps and underfill. Figure 1.1 compares visual and C-SAM inspection approaches for defect detection, especially for solder joint interconnections and hidden defects. C-SAM is specifically useful for package features like internal cracks and delamination. C-SAM not only allows for the visualization of the interior features, it has the ability to produce images on layer-by-layer basis. Visual inspection; however, is only superior to C-SAM for the exposed features including solder dewetting, microcracks, and contamination. Ideally, a combination of various inspection techniques - visual, optical and SEM microscopy, C-SAM, and X-ray - need to be performed in order to assure quality at part, package, and system levels. This reports presents evaluations performed on various advanced packages/assemblies, especially the flip-chip die version of ball grid array/column grid array (BGA/CGA) using C-SAM equipment. Both external and internal equipment was used for evaluation. The outside facility provided images of the key features that could be detected using the most advanced C-SAM equipment with a skilled operator. Investigation continued using in-house equipment with its limitations. For comparison, representative X-rays of the assemblies were also gathered to show key defect detection features of these non-destructive techniques. Key images gathered and compared are: Compared the images of 2D X-ray and C-SAM for a plastic LGA assembly showing features that could be detected by either NDE technique. For this specific case, X-ray was a clear winner. Evaluated flip-chip CGA and FCBGA assemblies with and without heat sink by C-SAM. Only the FCCGA package that had no heat sink could be fully analyzed for underfill and bump quality. Cross-sectional microscopy did not revealed peripheral delamination features detected by C-SAM. Analyzed a number of fine pitch PBGA assemblies by C-SAM. Even though the internal features of the package assemblies could be detected, C-SAM was unable to detect solder joint failure at either the package or board level. Twenty times touch ups by solder iron with 700degF tip temperature, each with about 5 second duration, did not induce defects to be detected by C-SAM images. Other techniques need to be considered to induce known defects for characterization. Given NASA's emphasis on the use of microelectronic packages and assemblies and quality assurance on workmanship defect detection, understanding key features of various inspection systems that detect defects in the early stages of package and assembly is critical to developing approaches that will minimize future failures. Additional specific, tailored non-destructive inspection approaches could enable low-risk insertion of these advanced electronic packages having hidden and fine features.

A short review on thermosonic flip chip bonding

NASA Astrophysics Data System (ADS)

Suppiah, Sarveshvaran; Ong, Nestor Rubio; Sauli, Zaliman; Sarukunaselan, Karunavani; Alcain, Jesselyn Barro; Shahimin, Mukhzeer Mohamad; Retnasamy, Vithyacharan

2017-09-01

This review is to study the evolution and key findings, critical technical challenges, solutions and bonding equipment of thermosonic flip chip bonding. Based on the review done, it was found that ultrasonic power, bonding time and force are the three main critical parameters need to be optimized in order to achieve sound and reliable bonding between the die and substrate. A close monitoring of the ultrasonic power helped to prevent over bonding phenomena on flexible substrate. Gold stud bumping is commonly used in thermosonic bonding compared to solder due to its better reliability obtained in the LED and optoelectronic packages. The review comprised short details on the available thermosonic bonding equipment in the semiconductor industry as well.

Multilayered microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2003-01-01

An apparatus for packaging of microelectronic devices is disclosed, wherein the package includes an integral window. The microelectronic device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The package can comprise, for example, a cofired ceramic frame or body. The package has an internal stepped structure made of a plurality of plates, with apertures, which are patterned with metallized conductive circuit traces. The microelectronic device can be flip-chip bonded on the plate to these traces, and oriented so that the light-sensitive side is optically accessible through the window. A cover lid can be attached to the opposite side of the package. The result is a compact, low-profile package, having an integral window that can be hermetically-sealed. The package body can be formed by low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the window being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. Multiple chips can be located within a single package, according to some embodiments. The cover lid can include a window. The apparatus is particularly suited for packaging of MEMS devices, since the number of handling steps is greatly reduced, thereby reducing the potential for contamination. The integral window can further include a lens for optically transforming light passing through the window. The package can include an array of binary optic lenslets made integral with the window. The package can include an electrically-switched optical modulator, such as a lithium niobate window attached to the package, for providing a very fast electrically-operated shutter.

Mechanism of Void Prediction in Flip Chip Packages with Molded Underfill

NASA Astrophysics Data System (ADS)

Wu, Kuo-Tsai; Hwang, Sheng-Jye; Lee, Huei-Huang

2017-08-01

Voids have always been present using the molded underfill (MUF) package process, which is a problem that needs further investigation. In this study, the process was studied using the Moldex3D numerical analysis software. The effects of gas (air vent effect) on the overall melt front were also considered. In this isothermal process containing two fluids, the gas and melt colloid interact in the mold cavity. Simulation enabled an appropriate understanding of the actual situation to be gained, and, through analysis, the void region and exact location of voids were predicted. First, the global flow end area was observed to predict the void movement trend, and then the local flow ends were observed to predict the location and size of voids. In the MUF 518 case study, simulations predicted the void region as well as the location and size of the voids. The void phenomenon in a flip chip ball grid array underfill is discussed as part of the study.

Polarity effect of electromigration on mechanical properties of lead-free solder joints

NASA Astrophysics Data System (ADS)

Ren, Fei

The trend of electronic packaging is to package the chips and the associated interconnections in a compact way that allows high speed operation; that allows for sufficient heat removal; that can withstand the thermal cycling associated with the turning on and turning off of the circuits; and that protects the circuits from environmental attack. These goals require that flip chip solder joints have higher resistance to electromigration, stronger mechanical property to sustain thermal mechanical stress, and are lead-free materials to satisfy environment and health concern. With lots of work on chemical reaction, electromigration and mechanical study in flip chip solder joints, however, the interaction between different driving forces is still little known. As a matter of fact, the combination study of chemical, electrical and mechanical is more and more significant to the understanding of the behavior of flip chip solder joints. In this dissertation, I developed one dimensional Cu (wire)-eutectic SnAgCu(ball)-Cu(wire) structure to investigate the interaction between electrical and mechanical force in lead-free solder joints. Electromigration was first conducted. The mechanical behaviors of solder joints before, after, and during electromigration were examined. Electrical current and mechanical stress were applied either in serial or in parallel to the solder joints. Tensile, creep, and drop tests, combined with different electrical current densities (1˜5x10 3A/cm2) and different stressing time (3˜144 hours), have been performed to study the effect of electromigration on the mechanical behavior of solder joints. Nano-indentation test was conducted to study the localized mechanical property of IMC at both interfaces in nanometer scale. Fracture images help analyze the failure mechanism of solder joints driven by both electrical and mechanical forces. The combination study shows a strain build-up during electromigration. Furthermore, a ductile-to-brittle transition in flip chip solder joints induced by electromigration is observed, in which the fracture position migrates from the middle to the cathode interface of the joint with increasing current density and time. The transition is explained by the polarity effect of electromigration, particular due to the accumulation of vacancies at the cathode interface.

Broadband and scalable optical coupling for silicon photonics using polymer waveguides

NASA Astrophysics Data System (ADS)

La Porta, Antonio; Weiss, Jonas; Dangel, Roger; Jubin, Daniel; Meier, Norbert; Horst, Folkert; Offrein, Bert Jan

2018-04-01

We present optical coupling schemes for silicon integrated photonics circuits that account for the challenges in large-scale data processing systems such as those used for emerging big data workloads. Our waveguide based approach allows to optimally exploit the on-chip optical feature size, and chip- and package real-estate. It further scales well to high numbers of channels and is compatible with state-of-the-art flip-chip die packaging. We demonstrate silicon waveguide to polymer waveguide coupling losses below 1.5 dB for both the O- and C-bands with a polarisation dependent loss of <1 dB. Over 100 optical silicon waveguide to polymer waveguide interfaces were assembled within a single alignment step, resulting in a physical I/O channel density of up to 13 waveguides per millimetre along the chip-edge, with an average coupling loss of below 3.4 dB measured at 1310 nm.

Processing and Characterization of NiTi Shape Memory Alloy Particle Reinforced Sn-In Solders

DTIC Science & Technology

2006-12-01

solders generally operate at a high homologous temperature. Thermally induced grain growth, mechanical stress-induced grain growth and recrystallization ...the number of I/O connects available for flip chip as compared to the wirebond chip For interconnection and packaging, Pb-Sn and eutectic 63Sn...lower melting point is desired. The maximum use temperature for this alloy is around 120°C due to the fact that the eutectic reaction happened at

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

NASA Astrophysics Data System (ADS)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Integrated microsystems packaging approach with LCP

NASA Astrophysics Data System (ADS)

Jaynes, Paul; Shacklette, Lawrence W.

2006-05-01

Within the government communication market there is an increasing push to further miniaturize systems with the use of chip-scale packages, flip-chip bonding, and other advances over traditional packaging techniques. Harris' approach to miniaturization includes these traditional packaging advances, but goes beyond this level of miniaturization by combining the functional and structural elements of a system, thus creating a Multi-Functional Structural Circuit (MFSC). An emerging high-frequency, near hermetic, thermoplastic electronic substrate material, Liquid Crystal Polymer (LCP), is the material that will enable the combination of the electronic circuit and the physical structure of the system. The first embodiment of this vision for Harris is the development of a battlefield acoustic sensor module. This paper will introduce LCP and its advantages for MFSC, present an example of the work that Harris has performed, and speak to LCP MFSCs' potential benefits to miniature communications modules and sensor platforms.

Flip-chip light emitting diode with resonant optical microcavity

DOEpatents

Gee, James M.; Bogart, Katherine H.A.; Fischer, Arthur J.

2005-11-29

A flip-chip light emitting diode with enhanced efficiency. The device structure employs a microcavity structure in a flip-chip configuration. The microcavity enhances the light emission in vertical modes, which are readily extracted from the device. Most of the rest of the light is emitted into waveguided lateral modes. Flip-chip configuration is advantageous for light emitting diodes (LEDs) grown on dielectric substrates (e.g., gallium nitride LEDs grown on sapphire substrates) in general due to better thermal dissipation and lower series resistance. Flip-chip configuration is advantageous for microcavity LEDs in particular because (a) one of the reflectors is a high-reflectivity metal ohmic contact that is already part of the flip-chip configuration, and (b) current conduction is only required through a single distributed Bragg reflector. Some of the waveguided lateral modes can also be extracted with angled sidewalls used for the interdigitated contacts in the flip-chip configuration.

Fabrication of five-level ultraplanar micromirror arrays by flip-chip assembly

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper reports a detailed study of the fabrication of various piston, torsion, and cantilever style micromirror arrays using a novel, simple, and inexpensive flip-chip assembly technique. Several rectangular and polar arrays were commercially prefabricated in the MUMPs process and then flip-chip bonded to form advanced micromirror arrays where adverse effects typically associated with surface micromachining were removed. These arrays were bonded by directly fusing the MUMPs gold layers with no complex preprocessing. The modules were assembled using a computer-controlled, custom-built flip-chip bonding machine. Topographically opposed bond pads were designed to correct for slight misalignment errors during bonding and typically result in less than 2 micrometers of lateral alignment error. Although flip-chip micromirror performance is briefly discussed, the means used to create these arrays is the focus of the paper. A detailed study of flip-chip process yield is presented which describes the primary failure mechanisms for flip-chip bonding. Studies of alignment tolerance, bonding force, stress concentration, module planarity, bonding machine calibration techniques, prefabrication errors, and release procedures are presented in relation to specific observations in process yield. Ultimately, the standard thermo-compression flip-chip assembly process remains a viable technique to develop highly complex prototypes of advanced micromirror arrays.

High-sensitivity low-noise miniature fluxgate magnetometers using a flip chip conceptual design.

PubMed

Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

2014-07-30

This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current "flip chip" concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or "responsivity" for magnetometers) and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz) magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz(1/2) at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market.

Flip-chip assembly and reliability using gold/tin solder bumps

NASA Astrophysics Data System (ADS)

Oppermann, Hermann; Hutter, Matthias; Klein, Matthias; Reichl, Herbert

2004-09-01

Au/Sn solder bumps are commonly used for flip chip assembly of optoelectronic and RF devices. They allow a fluxless assembly which is required to avoid contamination at optical interfaces. Flip chip assembly experiments were carried out using as plated Au/Sn bumps without prior bump reflow. An RF and reliability test vehicles comprise a GaAs chip which was flip chip soldered on a silicon substrate. Temperature cycling tests with and without underfiller were performed and the results are presented. The different failure modes for underfilled and non-underfilled samples were discussed and compared. Additional reliability tests were performed with flip chip bonding by gold thermocompression for comparison. The test results and the failure modes are discussed in detail.

White thin-film flip-chip LEDs with uniform color temperature using laser lift-off and conformal phosphor coating technologies.

PubMed

Lin, Huan-Ting; Tien, Ching-Ho; Hsu, Chen-Peng; Horng, Ray-Hua

2014-12-29

We fabricated a phosphor-conversion white light emitting diode (PC-WLED) using a thin-film flip-chip GaN LED with a roughened u-GaN surface (TFFC-SR-LED) that emits blue light at 450 nm wavelength with a conformal phosphor coating that converts the blue light into yellow light. It was found that the TFFC-SR-LED with the thin-film substrate removal process and surface roughening exhibits a power enhancement of 16.1% when compared with the TFFC-LED without a sapphire substrate. When a TFFC-SR-LED with phosphors on a Cu-metal packaging-base (TFFC-SR-Cu-WLED) was operated at a forward-bias current of 350 mA, luminous flux and luminous efficacy were increased by 17.8 and 11.9%, compared to a TFFC-SR-LED on a Cup-shaped packaging-base (TFFC-SR-Cup-WLED). The angular correlated color temperature (CCT) deviation of a TFFC-SR-Cu-WLED reaches 77 K in the range of -70° to + 70° when the average CCT of white LEDs is around 4300 K. Consequently, the TFFC-SR-LED in a conformal coating phosphor structure on a Cu packaging-base could not only increase the luminous flux output, but also improve the angular-dependent CCT uniformity, thereby reducing the yellow ring effect.

Physics of Failure Analysis of Xilinx Flip Chip CCGA Packages: Effects of Mission Environments on Properties of LP2 Underfill and ATI Lid Adhesive Materials

NASA Technical Reports Server (NTRS)

Suh, Jong-ook

2013-01-01

The Xilinx Virtex 4QV and 5QV (V4 and V5) are next-generation field-programmable gate arrays (FPGAs) for space applications. However, there have been concerns within the space community regarding the non-hermeticity of V4/V5 packages; polymeric materials such as the underfill and lid adhesive will be directly exposed to the space environment. In this study, reliability concerns associated with the non-hermeticity of V4/V5 packages were investigated by studying properties and behavior of the underfill and the lid adhesvie materials used in V4/V5 packages.

A novel miniaturized PCR multi-reactor array fabricated using flip-chip bonding techniques

NASA Astrophysics Data System (ADS)

Zou, Zhi-Qing; Chen, Xiang; Jin, Qing-Hui; Yang, Meng-Su; Zhao, Jian-Long

2005-08-01

This paper describes a novel miniaturized multi-chamber array capable of high throughput polymerase chain reaction (PCR). The structure of the proposed device is verified by using finite element analysis (FEA) to optimize the thermal performance, and then implemented on a glass-silicon substrate using a standard MEMS process and post-processing. Thermal analysis simulation and verification of each reactor cell is equipped with integrated Pt temperature sensors and heaters at the bottom of the reaction chamber for real-time accurate temperature sensing and control. The micro-chambers are thermally separated from each other, and can be controlled independently. The multi-chip array was packaged on a printed circuit board (PCB) substrate using a conductive polymer flip-chip bonding technique, which enables effective heat dissipation and suppresses thermal crosstalk between the chambers. The designed system has successfully demonstrated a temperature fluctuation of ±0.5 °C during thermal multiplexing of up to 2 × 2 chambers, a full speed of 30 min for 30 cycle PCR, as well as the capability of controlling each chamber digitally and independently.

All-optical SR flip-flop based on SOA-MZI switches monolithically integrated on a generic InP platform

NASA Astrophysics Data System (ADS)

Pitris, St.; Vagionas, Ch.; Kanellos, G. T.; Kisacik, R.; Tekin, T.; Broeke, R.; Pleros, N.

2016-03-01

At the dawning of the exaflop era, High Performance Computers are foreseen to exploit integrated all-optical elements, to overcome the speed limitations imposed by electronic counterparts. Drawing from the well-known Memory Wall limitation, imposing a performance gap between processor and memory speeds, research has focused on developing ultra-fast latching devices and all-optical memory elements capable of delivering buffering and switching functionalities at unprecedented bit-rates. Following the master-slave configuration of electronic Flip-Flops, coupled SOA-MZI based switches have been theoretically investigated to exceed 40 Gb/s operation, provided a short coupling waveguide. However, this flip-flop architecture has been only hybridly integrated with silica-on-silicon integration technology exhibiting a total footprint of 45x12 mm2 and intra-Flip-Flop coupling waveguide of 2.5cm, limited at 5 Gb/s operation. Monolithic integration offers the possibility to fabricate multiple active and passive photonic components on a single chip at a close proximity towards, bearing promises for fast all-optical memories. Here, we present for the first time a monolithically integrated all-optical SR Flip-Flop with coupled master-slave SOA-MZI switches. The photonic chip is integrated on a 6x2 mm2 die as a part of a multi-project wafer run using library based components of a generic InP platform, fiber-pigtailed and fully packaged on a temperature controlled ceramic submount module with electrical contacts. The intra Flip-Flop coupling waveguide is 5 mm long, reducing the total footprint by two orders of magnitude. Successful flip flop functionality is evaluated at 10 Gb/s with clear open eye diagram, achieving error free operation with a power penalty of 4dB.

Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

NASA Astrophysics Data System (ADS)

Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

2003-06-01

We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

Silicon-based products and solutions

NASA Astrophysics Data System (ADS)

Painchaud, Y.; Poulin, M.; Pelletier, F.; Latrasse, C.; Gagné, J.-F.; Savard, S.; Robidoux, G.; Picard, M.-.; Paquet, S.; Davidson, C.-.; Pelletier, M.; Cyr, M.; Paquet, C.; Guy, M.; Morsy-Osman, M.; Chagnon, M.; Plant, D. V.

2014-03-01

TeraXion started silicon photonics activities aiming at developing building blocks for new products and customized solutions. Passive and active devices have been developed including MMI couplers, power splitters, Bragg grating filters, high responsivity photodetectors, high speed modulators and variable optical attenuators. Packaging solutions including fiber attachment and hybrid integration using flip-chip were also developed. More specifically, a compact packaged integrated coherent receiver has been realized. Good performances were obtained as demonstrated by our system tests results showing transmission up to 4800 km with BER below hard FEC threshold. The package size is small but still limited by the electrical interface. Migrating to more compact RF interface would allow realizing the full benefit of this technology.

High-Sensitivity Low-Noise Miniature Fluxgate Magnetometers Using a Flip Chip Conceptual Design

PubMed Central

Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

2014-01-01

This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current “flip chip” concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or “responsivity” for magnetometers) and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz) magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz1/2 at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market. PMID:25196107

Experiences in flip chip production of radiation detectors

NASA Astrophysics Data System (ADS)

Savolainen-Pulli, Satu; Salonen, Jaakko; Salmi, Jorma; Vähänen, Sami

2006-09-01

Modern imaging devices often require heterogeneous integration of different materials and technologies. Because of yield considerations, material availability, and various technological limitations, an extremely fine pitch is necessary to realize high-resolution images. Thus, there is a need for a hybridization technology that is able to join together readout amplifiers and pixel detectors at a very fine pitch. This paper describes radiation detector flip chip production at VTT. Our flip chip technology utilizes 25-μm diameter tin-lead solder bumps at a 50-μm pitch and is based on flux-free bonding. When preprocessed wafers are used, as is the case here, the total yield is defined only partly by the flip chip process. Wafer preprocessing done by a third-party silicon foundry and the flip chip process create different process defects. Wafer-level yield maps (based on probing) provided by the customer are used to select good readout chips for assembly. Wafer probing is often done outside of a real clean room environment, resulting in particle contamination and/or scratches on the wafers. Factors affecting the total yield of flip chip bonded detectors are discussed, and some yield numbers of the process are given. Ways to improve yield are considered, and finally guidelines for process planning and device design with respect to yield optimization are given.

Platform technologies for hybrid optoelectronic integration and packaging

NASA Astrophysics Data System (ADS)

Datta, Madhumita

In order to bring fiber-optics closer to individual home and business services, the optical network components have to be inexpensive and reliable. Integration and packaging of optoelectronic devices holds the key to high-volume low-cost component manufacturing. The goal of this dissertation is to propose, study, and demonstrate various ways to integrate optoelectronic devices on a packaging platform to implement cost-effective, functional optical modules. Two types of hybrid integration techniques have been proposed: flip-chip solder bump bonding for high-density two-dimensional array packaging of surface-emitting devices, and solder preform bonding for fiber-coupled edge-emitting semiconductor devices. For flip-chip solder bump bonding, we developed a simple, inexpensive remetallization process called "electroless plating", which converts the aluminum bond pads of foundry-made complementary metal oxide semiconductor (CMOS) chips into solder-bondable and wire-bondable gold surfaces. We have applied for a patent on this remetallization technique. For fiber-pigtailed edge-emitting laser modules, we have studied the coupling characteristics of different types of lensed single-mode fibers including semispherically lensed fiber, cylindrically lensed fiber and conically lensed fiber. We have experimentally demonstrated 66% coupling efficiency with semispherically lensed fiber and 50% efficiency with conically lensed fibers. We have proposed and designed a packaging platform on which lensed fibers can be actively aligned to a laser and solder-attached reliably to the platform so that the alignment is retained. We have designed thin-film nichrome heaters on fused quartz platforms as local heat source to facilitate on-board solder alignment and attachment of fiber. The thermal performance of the heaters was simulated using finite element analysis tool ANSYS prior to fabrication. Using the heater's reworkability advantage, we have estimated the shift of the fiber due to solder shrinkage and introduced a pre-correction in the alignment process to restore optimum coupling efficiency close to 50% with conically lensed fibers. We have applied for a patent on this unique active alignment method through the University of Maryland's Technology Commercialization Office. Although we have mostly concentrated on active alignment platforms, we have proposed the idea of combining the passive alignment advantages of silicon optical benches to the on-board heater-assisted active alignment technique. This passive-active alignment process has the potential of cost-effective array packaging of edge-emitting devices.

Pressure-Sensor Assembly Technique

NASA Technical Reports Server (NTRS)

Pruzan, Daniel A.

2003-01-01

Nielsen Engineering & Research (NEAR) recently developed an ultrathin data acquisition system for use in turbomachinery testing at NASA Glenn Research Center. This system integrates a microelectromechanical- systems- (MEMS-) based absolute pressure sensor [0 to 50 psia (0 to 345 kPa)], temperature sensor, signal-conditioning application-specific integrated circuit (ASIC), microprocessor, and digital memory into a package which is roughly 2.8 in. (7.1 cm) long by 0.75 in. (1.9 cm) wide. Each of these components is flip-chip attached to a thin, flexible circuit board and subsequently ground and polished to achieve a total system thickness of 0.006 in. (0.15 mm). Because this instrument is so thin, it can be quickly adhered to any surface of interest where data can be collected without disrupting the flow being investigated. One issue in the development of the ultrathin data acquisition system was how to attach the MEMS pressure sensor to the circuit board in a manner which allowed the sensor s diaphragm to communicate with the ambient fluid while providing enough support for the chip to survive the grinding and polishing operations. The technique, developed by NEAR and Jabil Technology Services Group (San Jose, CA), is described below. In the approach developed, the sensor is attached to the specially designed circuit board, see Figure 1, using a modified flip-chip technique. The circular diaphragm on the left side of the sensor is used to actively measure the ambient pressure, while the diaphragm on the right is used to compensate for changes in output due to temperature variations. The circuit board is fabricated with an access hole through it so that when the completed system is installed onto a wind tunnel model (chip side down), the active diaphragm is exposed to the environment. After the sensor is flip-chip attached to the circuit board, the die is underfilled to support the chip during the subsequent grinding and polishing operations. To prevent this underfill material from getting onto the sensor s diaphragms, the circuit board is fabricated with two 25- micrometer-tall polymer rings, sized so that the diaphragms fit inside the rings once the chip is attached.

Preparation of a YAG:Ce phosphor glass by screen-printing technology and its application in LED packaging.

PubMed

Yang, Liang; Chen, Mingxiang; Lv, Zhicheng; Wang, Simin; Liu, Xiaogang; Liu, Sheng

2013-07-01

A simple and practical method for preparing phosphor glass is proposed. Phosphor distribution and element analysis are investigated by optical microscope and field emission scanning electron microscope (FE-SEM). The phosphor particles dispersed in the matrix are vividly observed, and their distributions are uniform. Spectrum distribution and color coordinates dependent on the thickness of the screen-printed phosphor layer coupled with a blue light emitting diode (LED) chip are studied. The luminous efficacy of the 75 μm printed phosphor-layer phosphor glass packaged white LED is 81.24 lm/W at 350 mA. This study opens up many possibilities for applications using the phosphor glass on a selected chip in which emission is well absorbed by all phosphors. The screen-printing technique also offers possibilities for the design and engineering of complex phosphor layers on glass substrates. Phosphor screen-printing technology allows the realization of high stability and thermal conductivity for the phosphor layer. This phosphor glass method provides many possibilities for LED packing, including thin-film flip chip and remote phosphor technology.

Phase Equilibria of the Sn-Ni-Si Ternary System and Interfacial Reactions in Sn-(Cu)/Ni-Si Couples

NASA Astrophysics Data System (ADS)

Fang, Gu; Chen, Chih-chi

2015-07-01

Interfacial reactions in Sn/Ni-4.5 wt.%Si and Sn-Cu/Ni-4.5 wt.%Si couples at 250°C, and Sn-Ni-Si ternary phase equilibria at 250°C were investigated in this study. Ni-Si alloys, which are nonmagnetic, can be regarded as a diffusion barrier layer material in flip chip packaging. Solder/Ni-4.5 wt.%Si interfacial reactions are crucial to the reliability of soldered joints. Phase equilibria information is essential for development of solder/Ni-Si materials. No ternary compound is present in the Sn-Ni-Si ternary system at 250°C. Extended solubility of Si in the phases Ni3Sn2 and Ni3Sn is 3.8 and 6.1 at.%, respectively. As more Si dissolves in these phases their lattice constants decrease. No noticeable ternary solubility is observed for the other intermetallics. Interfacial reactions in solder/Ni-4.5 wt.%Si are similar to those for solder/Ni. Si does not alter the reaction phases. No Si solubility in the reaction phases was detected, although rates of growth of the reaction phases were reduced. Because the alloy Ni-4.5 wt.%Si reacts more slowly with solders than pure Ni, the Ni-4.5 wt.%Si alloy could be a potential new diffusion barrier layer material for flip chip packaging.

Hybridization of active and passive elements for planar photonic components and interconnects

NASA Astrophysics Data System (ADS)

Pearson, M.; Bidnyk, S.; Balakrishnan, A.

2007-02-01

The deployment of Passive Optical Networks (PON) for Fiber-to-the-Home (FTTH) applications currently represents the fastest growing sector of the telecommunication industry. Traditionally, FTTH transceivers have been manufactured using commodity bulk optics subcomponents, such as thin film filters (TFFs), micro-optic collimating lenses, TO-packaged lasers, and photodetectors. Assembling these subcomponents into a single housing requires active alignment and labor-intensive techniques. Today, the majority of cost reducing strategies using bulk subcomponents has been implemented making future reductions in the price of manufacturing FTTH transceivers unlikely. Future success of large scale deployments of FTTH depends on further cost reductions of transceivers. Realizing the necessity of a radically new packaging approach for assembly of photonic components and interconnects, we designed a novel way of hybridizing active and passive elements into a planar lightwave circuit (PLC) platform. In our approach, all the filtering components were monolithically integrated into the chip using advancements in planar reflective gratings. Subsequently, active components were passively hybridized with the chip using fully-automated high-capacity flip-chip bonders. In this approach, the assembly of the transceiver package required no active alignment and was readily suitable for large-scale production. This paper describes the monolithic integration of filters and hybridization of active components in both silica-on-silicon and silicon-on-insulator PLCs.

Hybrid integration of VCSELs onto a silicon photonic platform for biosensing application

NASA Astrophysics Data System (ADS)

Lu, Huihui; Lee, Jun Su; Zhao, Yan; Cardile, Paolo; Daly, Aidan; Carroll, Lee; O'Brien, Peter

2017-02-01

This paper presents a technology of hybrid integration vertical cavity surface emitting lasers (VCSELs) directly on silicon photonics chip. By controlling the reflow of the solder balls used for electrical and mechanical bonding, the VCSELs were bonded at 10 degree to achieve the optimum angle-of-incidence to the planar grating coupler through vision based flip-chip techniques. The 1 dB discrepancy between optical loss values of flip-chip passive assembly and active alignment confirmed that the general purpose of the flip-chip design concept is achieved. This hybrid approach of integrating a miniaturized light source on chip opens the possibly of highly compact sensor system, which enable future portable and wearable diagnostics devices.

High reliable and chromaticity-tunable flip-chip w-LEDs with Ce:YAG glass-ceramics phosphor for long-lifetime automotive headlights applications

NASA Astrophysics Data System (ADS)

Ma, Chaoyang; Cao, Yongge; Shen, Xiaofei; Wen, Zicheng; Ma, Ran; Long, Jiaqi; Yuan, Xuanyi

2017-07-01

Nowadays, major commercial w-LEDs fabricated by the traditionally gold-wire-welding packaging technology have undergone considerable development as indoor/outdoor lighting sources due to its high-energy utilization efficiency, long service life, environmental friendliness, and excellent chromatic stability. While, new generation applications in projections, automotive lighting, street lighting, plaza lighting, and high-end general lighting need further improvements in power handling and light extraction. Herein, transparent Ce:YAG glass-ceramics (GCs) phosphor was prepared by low-temperature co-sintering polycrystalline Ce:YAG phosphor powder and home-made PbO-B2O3-ZnO-SiO2 glass powder. Thereafter, the flip-chip (FC) w-LEDs were fabricated with the GCs phosphor plates and FC blue chips. The GCs-based FC w-LEDs show not only excellent heat- and humidity-resistance characteristics, but also superior optical performances with an LE of 112.8 lm/W, a CRI of 71.2, a CCT of 6103 K as well as a chromaticity coordinate of (0.3202, 0.3298), under a high operation current of 400 mA. The technology route will open a practically commercial feasible approach to achieve excellent performances for advanced high-power FC w-LEDs.

Evaluation of advanced microelectronic fluxless solder-bump contacts for hybrid microcircuits

NASA Technical Reports Server (NTRS)

Mandal, R. P.

1976-01-01

Technology for interconnecting monolithic integrated circuit chips with other components is investigated. The advantages and disadvantages of the current flip-chip approach as compared to other interconnection methods are outlined. A fluxless solder-bump contact technology is evaluated. Multiple solder-bump contacts were formed on silicon integrated circuit chips. The solder-bumps, comprised of a rigid nickel under layer and a compliant solder overlayer, were electroformed onto gold device pads with the aid of thick dry film photomasks. Different solder alloys and the use of conductive epoxy for bonding were explored. Fluxless solder-bump bond quality and reliability were evaluated by measuring the effects of centrifuge, thermal cycling, and high temperature storage on bond visual characteristics, bond electrical continuity, and bond shear tests. The applicability and suitability of this technology for hybrid microelectronic packaging is discussed.

Aging Studies of Cu-Sn Intermetallics in Cu Micropillars Used in Flip Chip Attachment onto Cu Lead Frames

NASA Astrophysics Data System (ADS)

Roma, Maria Penafrancia C.; Kudtarkar, Santosh; Kierse, Oliver; Sengupta, Dipak; Cho, Junghyun

2018-02-01

Copper micropillars plated onto a silicon die and soldered with Sn-Ag solder to a copper lead frame in a flip chip on lead package have been subjected to high-temperature storage at 150°C and 175°C for 500 h, 1000 h, and 1500 h. Cu6Sn5 and Cu3Sn intermetallic compounds were found on both sides of the solder, but the growth rates were not the same as evidenced by different values of the growth exponent n. Cu and Sn diffusion controlled the Cu3Sn growth in the Cu pillar interface ( n ≈ 0.5), while interface reactions controlled the growth in the Cu lead frame interface ( n ≈ 0.8). Increasing the aging temperature increased the growth of Cu3Sn as well as the presence of microvoids in the Cu lead frame side. Adding Ni as a barrier layer on the Cu pillar prevented the growth of Cu3Sn in the Cu pillar interface and reduced its growth rate on the lead frame side, even at higher aging temperatures.

Photodiodes integration on a suspended ridge structure VOA using 2-step flip-chip bonding method

NASA Astrophysics Data System (ADS)

Kim, Seon Hoon; Kim, Tae Un; Ki, Hyun Chul; Kim, Doo Gun; Kim, Hwe Jong; Lim, Jung Woon; Lee, Dong Yeol; Park, Chul Hee

2015-01-01

In this works, we have demonstrated a VOA integrated with mPDs, based on silica-on-silicon PLC and flip-chip bonding technologies. The suspended ridge structure was applied to reduce the power consumption. It achieves the attenuation of 30dB in open loop operation with the power consumption of below 30W. We have applied two-step flipchip bonding method using passive alignment to perform high density multi-chip integration on a VOA with eutectic AuSn solder bumps. The average bonding strength of the two-step flip-chip bonding method was about 90gf.

Microchannel cooling of face down bonded chips

DOEpatents

Bernhardt, A.F.

1993-06-08

Microchannel cooling is applied to flip-chip bonded integrated circuits, in a manner which maintains the advantages of flip-chip bonds, while overcoming the difficulties encountered in cooling the chips. The technique is suited to either multi chip integrated circuit boards in a plane, or to stacks of circuit boards in a three dimensional interconnect structure. Integrated circuit chips are mounted on a circuit board using flip-chip or control collapse bonds. A microchannel structure is essentially permanently coupled with the back of the chip. A coolant delivery manifold delivers coolant to the microchannel structure, and a seal consisting of a compressible elastomer is provided between the coolant delivery manifold and the microchannel structure. The integrated circuit chip and microchannel structure are connected together to form a replaceable integrated circuit module which can be easily decoupled from the coolant delivery manifold and the circuit board. The coolant supply manifolds may be disposed between the circuit boards in a stack and coupled to supplies of coolant through a side of the stack.

Advanced processing of CdTe pixel radiation detectors

NASA Astrophysics Data System (ADS)

Gädda, A.; Winkler, A.; Ott, J.; Härkönen, J.; Karadzhinova-Ferrer, A.; Koponen, P.; Luukka, P.; Tikkanen, J.; Vähänen, S.

2017-12-01

We report a fabrication process of pixel detectors made of bulk cadmium telluride (CdTe) crystals. Prior to processing, the quality and defect density in CdTe material was characterized by infrared (IR) spectroscopy. The semiconductor detector and Flip-Chip (FC) interconnection processing was carried out in the clean room premises of Micronova Nanofabrication Centre in Espoo, Finland. The chip scale processes consist of the aluminum oxide (Al2O3) low temperature thermal Atomic Layer Deposition (ALD), titanium tungsten (TiW) metal sputtering depositions and an electroless Nickel growth. CdTe crystals with the size of 10×10×0.5 mm3 were patterned with several photo-lithography techniques. In this study, gold (Au) was chosen as the material for the wettable Under Bump Metalization (UBM) pads. Indium (In) based solder bumps were grown on PSI46dig read out chips (ROC) having 4160 pixels within an area of 1 cm2. CdTe sensor and ROC were hybridized using a low temperature flip-chip (FC) interconnection technique. The In-Au cold weld bonding connections were successfully connecting both elements. After the processing the detector packages were wire bonded into associated read out electronics. The pixel detectors were tested at the premises of Finnish Radiation Safety Authority (STUK). During the measurement campaign, the modules were tested by exposure to a 137Cs source of 1.5 TBq for 8 minutes. We detected at the room temperature a photopeak at 662 keV with about 2 % energy resolution.

Microchannel cooling of face down bonded chips

DOEpatents

Bernhardt, Anthony F.

1993-01-01

Microchannel cooling is applied to flip-chip bonded integrated circuits, in a manner which maintains the advantages of flip-chip bonds, while overcoming the difficulties encountered in cooling the chips. The technique is suited to either multichip integrated circuit boards in a plane, or to stacks of circuit boards in a three dimensional interconnect structure. Integrated circuit chips are mounted on a circuit board using flip-chip or control collapse bonds. A microchannel structure is essentially permanently coupled with the back of the chip. A coolant delivery manifold delivers coolant to the microchannel structure, and a seal consisting of a compressible elastomer is provided between the coolant delivery manifold and the microchannel structure. The integrated circuit chip and microchannel structure are connected together to form a replaceable integrated circuit module which can be easily decoupled from the coolant delivery manifold and the circuit board. The coolant supply manifolds may be disposed between the circuit boards in a stack and coupled to supplies of coolant through a side of the stack.

Ultra-compact 32 × 32 strictly-non-blocking Si-wire optical switch with fan-out LGA interposer.

PubMed

Tanizawa, Ken; Suzuki, Keijiro; Toyama, Munehiro; Ohtsuka, Minoru; Yokoyama, Nobuyuki; Matsumaro, Kazuyuki; Seki, Miyoshi; Koshino, Keiji; Sugaya, Toshio; Suda, Satoshi; Cong, Guangwei; Kimura, Toshio; Ikeda, Kazuhiro; Namiki, Shu; Kawashima, Hitoshi

2015-06-29

We demonstrate a 32 × 32 path-independent-insertion-loss optical path switch that integrates 1024 thermooptic Mach-Zehnder switches and 961 intersections on a small, 11 × 25 mm2 die. The switch is fabricated on a 300-mm-diameter silicon-on-insulator wafer by a complementary metal-oxide semiconductor-compatible process with advanced ArF immersion lithography. For reliable electrical packaging, the switch chip is flip-chip bonded to a ceramic interposer that arranges the electrodes in a 0.5-mm pitch land grid array. The on-chip loss is measured to be 15.8 ± 1.0 dB, and successful switching is demonstrated for digital-coherent 43-Gb/s QPSK signals. The total crosstalk of the switch is estimated to be less than -20 dB at the center wavelength of 1545 nm. The bandwidth narrowing caused by dimensional errors that arise during fabrication is discussed.

Super-Lattice Light Emitting Diodes (SLEDS) on GaAs

DTIC Science & Technology

2016-03-31

Super-Lattice Light Emitting Diodes (SLEDS) on GaAs Kassem Nabha1, Russel Ricker2, Rodney McGee1, Nick Waite1, John Prineas2, Sydney Provence2...infrared light emitting diodes (LEDs). Typically, the LED arrays are mated with CMOS read-in integrated circuit (RIIC) chips using flip-chip bonding. In...circuit (RIIC) chips using flip-chip bonding. This established technology is called Hybrid-super-lattice light emitting diodes (Hybrid- SLEDS). In

Fundamental study of microelectronic chip response under laser ultrasonic-interferometric inspection using C-scan method

NASA Astrophysics Data System (ADS)

Yang, Lei; Gong, Jie; Ume, I. Charles

2014-02-01

In modern surface mount packaging technologies, such as flip chips, chip scale packages, and ball grid arrays(BGA), chips are attached to the substrates/printed wiring board (PWB) using solder bump interconnections. The quality of solder bumps between the chips and the substrate/board is difficult to inspect. Laser ultrasonic-interferometric technique was proved to be a promising approach for solder bump inspection because of its noncontact and nondestructive characteristics. Different indicators extracted from received signals have been used to predict the potential defects, such as correlation coefficient, error ratio, frequency shifting, etc. However, the fundamental understanding of the chip behavior under laser ultrasonic inspection is still missing. Specifically, it is not sure whether the laser interferometer detected out-of-plane displacements were due to wave propagation or structural vibration when the chip was excited by pulsed laser. Plus, it is found that the received signals are chip dependent. Both challenges impede the interpretation of acquired signals. In this paper, a C-scan method was proposed to study the underlying phenomenon during laser ultrasonic inspection. The full chip was inspected. The response of the chip under laser excitation was visualized in a movie resulted from acquired signals. Specifically, a BGA chip was investigated to demonstrate the effectiveness of this method. By characterizing signals using discrete wavelet transform(DWT), both ultrasonic wave propagation and vibration were observed. Separation of them was successfully achieved using ideal band-pass filter and visualized in resultant movies, too. The observed ultrasonic waves were characterized and their respective speeds were measured by applying 2-D FFT. The C-scan method, combined with different digital signal processing techniques, was proved to be an very effective methodology to learn the behavior of chips under laser excitation. This general procedure can be applied to any unknown chip before inspection. A wealth of information can be provided by this learning procedure, which greatly benefits the interpretation of inspection signals afterwards.

Thermal cycling reliability of Cu/SnAg double-bump flip chip assemblies for 100 μm pitch applications

NASA Astrophysics Data System (ADS)

Son, Ho-Young; Kim, Ilho; Lee, Soon-Bok; Jung, Gi-Jo; Park, Byung-Jin; Paik, Kyung-Wook

2009-01-01

A thick Cu column based double-bump flip chip structure is one of the promising alternatives for fine pitch flip chip applications. In this study, the thermal cycling (T/C) reliability of Cu/SnAg double-bump flip chip assemblies was investigated, and the failure mechanism was analyzed through the correlation of T/C test and the finite element analysis (FEA) results. After 1000 thermal cycles, T/C failures occurred at some Cu/SnAg bumps located at the edge and corner of chips. Scanning acoustic microscope analysis and scanning electron microscope observations indicated that the failure site was the Cu column/Si chip interface. It was identified by a FEA where the maximum stress concentration was located during T/C. During T/C, the Al pad between the Si chip and a Cu column bump was displaced due to thermomechanical stress. Based on the low cycle fatigue model, the accumulation of equivalent plastic strain resulted in thermal fatigue deformation of the Cu column bumps and ultimately reduced the thermal cycling lifetime. The maximum equivalent plastic strains of some bumps at the chip edge increased with an increased number of thermal cycles. However, equivalent plastic strains of the inner bumps did not increase regardless of the number of thermal cycles. In addition, the z-directional normal plastic strain ɛ22 was determined to be compressive and was a dominant component causing the plastic deformation of Cu/SnAg double bumps. As the number of thermal cycles increased, normal plastic strains in the perpendicular direction to the Si chip and shear strains were accumulated on the Cu column bumps at the chip edge at low temperature region. Thus it was found that the Al pad at the Si chip/Cu column interface underwent thermal fatigue deformation by compressive normal strain and the contact loss by displacement failure of the Al pad, the main T/C failure mode of the Cu/SnAg flip chip assembly, then occurred at the Si chip/Cu column interface shear strain deformation during T/C.

Semiconductor laser joint study program with Rome Laboratory

NASA Astrophysics Data System (ADS)

Schaff, William J.; Okeefe, Sean S.; Eastman, Lester F.

1994-09-01

A program to jointly study vertical-cavity surface emitting lasers (VCSEL) for high speed vertical optical interconnects (VOI) has been conducted under an ES&E between Rome Laboratory and Cornell University. Lasers were designed, grown, and fabricated at Cornell University. A VCSEL measurement laboratory has been designed, built, and utilized at Rome Laboratory. High quality VCSEL material was grown and characterized by fabricating conventional lateral cavity lasers that emitted at the design wavelength of 1.04 microns. The VCSEL's emit at 1.06 microns. Threshold currents of 16 mA at 4.8 volts were obtained for 30 microns diameter devices. Output powers of 5 mW were measured. This is 500 times higher power than from the light emitting diodes employed previously for vertical optical interconnects. A new form of compositional grading using a cosinusoidal function has been developed and is very successful for reducing diode series resistance for high speed interconnection applications. A flip-chip diamond package compatible with high speed operation of 16 VCSEL elements has been designed and characterized. A flip-chip device binding effort at Rome Laboratory was also designed and initiated. This report presents details of the one-year effort, including process recipes and results.

Advanced Packaging Technology Used in Fabricating a High-Temperature Silicon Carbide Pressure Sensor

NASA Technical Reports Server (NTRS)

Beheim, Glenn M.

2003-01-01

The development of new aircraft engines requires the measurement of pressures in hot areas such as the combustor and the final stages of the compressor. The needs of the aircraft engine industry are not fully met by commercially available high-temperature pressure sensors, which are fabricated using silicon. Kulite Semiconductor Products and the NASA Glenn Research Center have been working together to develop silicon carbide (SiC) pressure sensors for use at high temperatures. At temperatures above 850 F, silicon begins to lose its nearly ideal elastic properties, so the output of a silicon pressure sensor will drift. SiC, however, maintains its nearly ideal mechanical properties to extremely high temperatures. Given a suitable sensor material, a key to the development of a practical high-temperature pressure sensor is the package. A SiC pressure sensor capable of operating at 930 F was fabricated using a newly developed package. The durability of this sensor was demonstrated in an on-engine test. The SiC pressure sensor uses a SiC diaphragm, which is fabricated using deep reactive ion etching. SiC strain gauges on the surface of the diaphragm sense the pressure difference across the diaphragm. Conventionally, the SiC chip is mounted to the package with the strain gauges outward, which exposes the sensitive metal contacts on the chip to the hostile measurement environment. In the new Kulite leadless package, the SiC chip is flipped over so that the metal contacts are protected from oxidation by a hermetic seal around the perimeter of the chip. In the leadless package, a conductive glass provides the electrical connection between the pins of the package and the chip, which eliminates the fragile gold wires used previously. The durability of the leadless SiC pressure sensor was demonstrated when two 930 F sensors were tested in the combustor of a Pratt & Whitney PW4000 series engine. Since the gas temperatures in these locations reach 1200 to 1300 F, the sensors were installed in water-cooled jackets, as shown. This was a severe test because the pressure-sensing chips were exposed to the hot combustion gases. Prior to the installation of the SiC pressure sensors, two high-temperature silicon sensors, installed in the same locations, did not survive a single engine run. The durability of the leadless SiC pressure sensor was demonstrated when both SiC sensors operated properly throughout the two runs that were conducted.

Hybrid UV Imager Containing Face-Up AlGaN/GaN Photodiodes

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Pain, Bedabrata

2005-01-01

A proposed hybrid ultraviolet (UV) image sensor would comprise a planar membrane array of face-up AlGaN/GaN photodiodes integrated with a complementary metal oxide/semiconductor (CMOS) readout-circuit chip. Each pixel in the hybrid image sensor would contain a UV photodiode on the AlGaN/GaN membrane, metal oxide/semiconductor field-effect transistor (MOSFET) readout circuitry on the CMOS chip underneath the photodiode, and a metal via connection between the photodiode and the readout circuitry (see figure). The proposed sensor design would offer all the advantages of comparable prior CMOS active-pixel sensors and AlGaN UV detectors while overcoming some of the limitations of prior (AlGaN/sapphire)/CMOS hybrid image sensors that have been designed and fabricated according to the methodology of flip-chip integration. AlGaN is a nearly ideal UV-detector material because its bandgap is wide and adjustable and it offers the potential to attain extremely low dark current. Integration of AlGaN with CMOS is necessary because at present there are no practical means of realizing readout circuitry in the AlGaN/GaN material system, whereas the means of realizing readout circuitry in CMOS are well established. In one variant of the flip-chip approach to integration, an AlGaN chip on a sapphire substrate is inverted (flipped) and then bump-bonded to a CMOS readout circuit chip; this variant results in poor quantum efficiency. In another variant of the flip-chip approach, an AlGaN chip on a crystalline AlN substrate would be bonded to a CMOS readout circuit chip; this variant is expected to result in narrow spectral response, which would be undesirable in many applications. Two other major disadvantages of flip-chip integration are large pixel size (a consequence of the need to devote sufficient area to each bump bond) and severe restriction on the photodetector structure. The membrane array of AlGaN/GaN photodiodes and the CMOS readout circuit for the proposed image sensor would be fabricated separately.

Impact of Isothermal Aging and Testing Temperature on Large Flip-Chip BGA Interconnect Mechanical Shock Performance

NASA Astrophysics Data System (ADS)

Lee, Tae-Kyu; Chen, Zhiqiang; Guirguis, Cherif; Akinade, Kola

2017-10-01

The stability of solder interconnects in a mechanical shock environment is crucial for large body size flip-chip ball grid array (FCBGA) electronic packages. Additionally, the junction temperature increases with higher electric power condition, which brings the component into an elevated temperature environment, thus introducing another consideration factor for mechanical stability of interconnection joints. Since most of the shock performance data available were produced at room temperature, the effect of elevated temperature is of interest to ensure the reliability of the device in a mechanical shock environment. To achieve a stable␣interconnect in a dynamic shock environment, the interconnections must tolerate mechanical strain, which is induced by the shock wave input and reaches the particular component interconnect joint. In this study, large body size (52.5 × 52.5 mm2) FCBGA components assembled on 2.4-mm-thick boards were tested with various isothermal pre-conditions and testing conditions. With a heating element embedded in the test board, a test temperature range from room temperature to 100°C was established. The effects of elevated temperature on mechanical shock performance were investigated. Failure and degradation mechanisms are identified and discussed based on the microstructure evolution and grain structure transformations.

New Failure Mode of Flip-Chip Solder Joints Related to the Metallization of an Organic Substrate

NASA Astrophysics Data System (ADS)

Jang, J. W.; Yoo, S. J.; Hwang, H. I.; Yuk, S. Y.; Kim, C. K.; Kim, S. J.; Han, J. S.; An, S. H.

2015-10-01

We report a new failure phenomenon during flip-chip die attach. After reflow, flip-chip bumps were separated between the Al and Ti layers on the Si die side. This was mainly observed at the Si die corner. Transmission electron microscopy images revealed corrosion of the Al layer at the edge of the solder bump metallization. The corrosion at the metallization edge exhibited a notch shape with high stress concentration factor. The organic substrate had Cu metallization with an organic solderable preservative (OSP) coating layer, where a small amount of Cl ions were detected. A solder bump separation mechanism is suggested based on the reaction between Al and Cl, related to the flow of soldering flux. During reflow, the flux will dissolve the Cl-containing OSP layer and flow up to the Al layer on the Si die side. Then, the Cl-dissolved flux will actively react with Al, forming AlCl3. During cooling, solder bumps at the Si die corner will separate through the location of Al corrosion. This demonstrated that the chemistry of the substrate metallization can affect the thermomechanical reliability of flip-chip solder joints.

Neural Implants, Packaging for Biocompatible Implants, and Improving Fabricated Capacitors

NASA Astrophysics Data System (ADS)

Agger, Elizabeth Rose

We have completed the circuit design and packaging procedure for an NIH-funded neural implant, called a MOTE (Microscale Optoelectronically Transduced Electrode). Neural recording implants for mice have greatly advanced neuroscience, but they are often damaging and limited in their recording location. This project will result in free-floating implants that cause less damage, provide rapid electronic recording, and increase range of recording across the cortex. A low-power silicon IC containing amplification and digitization sub-circuits is powered by a dual-function gallium arsenide photovoltaic and LED. Through thin film deposition, photolithography, and chemical and physical etching, the Molnar Group and the McEuen Group (Applied and Engineering Physics department) will package the IC and LED into a biocompatible implant approximately 100microm3. The IC and LED are complete and we have begun refining this packaging procedure in the Cornell NanoScale Science & Technology Facility. ICs with 3D time-resolved imaging capabilities can image microorganisms and other biological samples given proper packaging. A portable, flat, easily manufactured package would enable scientists to place biological samples on slides directly above the Molnar group's imaging chip. We have developed a packaging procedure using laser cutting, photolithography, epoxies, and metal deposition. Using a flip-chip method, we verified the process by aligning and adhering a sample chip to a holder wafer. In the CNF, we have worked on a long-term metal-insulator-metal (MIM) capacitor characterization project. Former Fellow and continuing CNF user Kwame Amponsah developed the original procedure for the capacitor fabrication, and another former fellow, Jonilyn Longenecker, revised the procedure and began the arduous process of characterization. MIM caps are useful to clean room users as testing devices to verify electronic characteristics of their active circuitry. This project's objective is to determine differences in current-voltage (IV) and capacitor-voltage (CV) relationships across variations in capacitor size and dielectric type. This effort requires an approximately 20-step process repeated for two-to-six varieties (dependent on temperature and thermal versus plasma options) of the following dielectrics: HfO2, SiO2, Al2O3, TaOx, and TiO2.

Reliability and Qualification of Hardware to Enhance the Mission Assurance of JPL/NASA Projects

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni

2010-01-01

Packaging Qualification and Verification (PQV) and life testing of advanced electronic packaging, mechanical assemblies (motors/actuators), and interconnect technologies (flip-chip), platinum temperature thermometer attachment processes, and various other types of hardware for Mars Exploration Rover (MER)/Mars Science Laboratory (MSL), and JUNO flight projects was performed to enhance the mission assurance. The qualification of hardware under extreme cold to hot temperatures was performed with reference to various project requirements. The flight like packages, assemblies, test coupons, and subassemblies were selected for the study to survive three times the total number of expected temperature cycles resulting from all environmental and operational exposures occurring over the life of the flight hardware including all relevant manufacturing, ground operations, and mission phases. Qualification/life testing was performed by subjecting flight-like qualification hardware to the environmental temperature extremes and assessing any structural failures, mechanical failures or degradation in electrical performance due to either overstress or thermal cycle fatigue. Experimental flight qualification test results will be described in this presentation.

Electromigration and thermomigration in lead-free tin-silver-copper and eutectic tin-lead flip chip solder joints

NASA Astrophysics Data System (ADS)

Ou Yang, Fan-Yi

Phase separation and microstructure change of eutectic SnPb and SnAgCu flip chip solder joint were investigated under thermomigration, electromigration, stressmigration and the combination of these effects. Different morphological behaviors under DC and AC electromigration were seen. Phase separation with Pb rich phase migration to the anode was observed when current density is below 1.6 x 104 A/cm2 at 100°C. For some cases, phase separation of Pb-rich phase and Su-rich phase as well as refinement of lamellar microstructure has also been observed. We propose that the refinement is due to recrystallization. On the other hand, time-dependent melting of eutectic SnPb flip chip solder joints has been observed to occur frequently with current density above 1.6 x 104 A/cm 2at 100°C. It has been found that it is due to joule heating of the on-chip Al interconnects. We found that electromigration has especially generated voids at the anode of the Al. This damage has greatly increased the resistance of the Al, which produces the heat needed to melt the solder joint. Owing to the line-to-bump configuration in flip chip solder joints, current crowding occurs when electrons enters into or exits from the solder bump. At the cathode contact, current crowding induced pancake-type void formation was observed widely. Furthermore, at the anode contact, we note that hillock or whisker forms. The cross-sectioned surface in SnPb showed dimple and bulge after electromigration, while that of SnAgCu remained flat. The difference is due to a larger back stress in the SnAgCu, consequently electromigration in SnAgCu is slower than that in SnPb. For thermomigration in eutectic SnPb flip chip solder joints, phase separation of Sn and Pb occurred, with Pb moving to the cold end. Both Sn and Pb have a stepwise concentration profile across solder bump. Refinement of lamellar microstructure was observed, indicating recrystallization. Also, thermomigration in eutectic SnAgCu flip chip solder joint were presented. It seems that vacancy flux plays a dominant role in thermomigration in Pb-free solder bumps; voids formed on the cold end and Sn moved to the hot end.

Broad Frequency LTCC Vertical Interconnect Transition for Multichip Modules and System on Package Applications

NASA Technical Reports Server (NTRS)

Decrossas, Emmanuel; Glover, Michael D.; Porter, Kaoru; Cannon, Tom; Mantooth, H. Alan; Hamilton, M. C.

2013-01-01

Various stripline structures and flip chip interconnect designs for high-speed digital communication systems implemented in low temperature co-fired ceramic (LTCC) substrates are studied in this paper. Specifically, two different transition designs from edge launch 2.4 millimeter connectors to stripline transmission lines embedded in LTCC are discussed. After characterizing the DuPont (sup trademark) 9K7 green tape, different designs are proposed to improve signal integrity for high-speed digital data. The full-wave simulations and experimental data validate the presented designs over a broad frequency band from Direct Current to 50 gigahertz and beyond.

Evaluation of the thermal conductance of flip-chip bonding structure utilizing the measurement based on Fourier's law of heat conduction at steady-state

NASA Astrophysics Data System (ADS)

Wu, Chia-Yu; Huang, Yin-Hsien; Wu, Hsin-Han; Hsieh, Tsung-Eong

2018-06-01

Fourier's law of heat conduction at steady-state was adopted to establish a measurement method utilizing platinum (Pt) thin-film electrodes as the heater and the temperature sensor. The thermal conductivities (κ's) of Pyrex glass, an epoxy resin and a commercial underfill for flip-chip devices were measured and a good agreement with previously reported values was obtained. The thermal boundary resistances (RTBR's) of Pt/sample interfaces were also extracted for discussing their influence on the thermal conduction of samples. Afterward, the flip-chip samples with 2×2 solder joint array utilizing Si wafers as the die and the substrate, without and with the underfills, were prepared and their thermal conductance were measured. For the sample without underfill, the air presenting in the gap of die and the substrate led to the poor thermal conductance of sample. With the insertion of underfills, the thermal conductance of flip-chip samples improved. The resistance to heat transfer across Si/underfill interfaces was also suppressed and to promote the thermal conductance of samples. The thermal properties of underfill and RTBR at Si/underfill interface were further implanted in the calculation of thermal conductance of flip-chip samples containing various solder joint arrays. The increasing number of solder joints diminished the influence of thermal conduction of underfill and RTBR of Si/underfill interface on the thermal conductance of samples. The insertion of underfill with high-κ value might promote the heat conductance of samples containing low-density solder joint arrays; however, it became insignificant in improving the heat conductance of samples containing high-density solder joint arrays.

Flip-chip integration of tilted VCSELs onto a silicon photonic integrated circuit.

PubMed

Lu, Huihui; Lee, Jun Su; Zhao, Yan; Scarcella, Carmelo; Cardile, Paolo; Daly, Aidan; Ortsiefer, Markus; Carroll, Lee; O'Brien, Peter

2016-07-25

In this article we describe a cost-effective approach for hybrid laser integration, in which vertical cavity surface emitting lasers (VCSELs) are passively-aligned and flip-chip bonded to a Si photonic integrated circuit (PIC), with a tilt-angle optimized for optical-insertion into standard grating-couplers. A tilt-angle of 10° is achieved by controlling the reflow of the solder ball deposition used for the electrical-contacting and mechanical-bonding of the VCSEL to the PIC. After flip-chip integration, the VCSEL-to-PIC insertion loss is -11.8 dB, indicating an excess coupling penalty of -5.9 dB, compared to Fibre-to-PIC coupling. Finite difference time domain simulations indicate that the penalty arises from the relatively poor match between the VCSEL mode and the grating-coupler.

Wafer-level vacuum/hermetic packaging technologies for MEMS

NASA Astrophysics Data System (ADS)

Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

2010-02-01

An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

Ten-channel InP-based large-scale photonic integrated transmitter fabricated by SAG technology

NASA Astrophysics Data System (ADS)

Zhang, Can; Zhu, Hongliang; Liang, Song; Cui, Xiao; Wang, Huitao; Zhao, Lingjuan; Wang, Wei

2014-12-01

A 10-channel InP-based large-scale photonic integrated transmitter was fabricated by selective area growth (SAG) technology combined with butt-joint regrowth (BJR) technology. The SAG technology was utilized to fabricate the electroabsorption modulated distributed feedback (DFB) laser (EML) arrays at the same time. The design of coplanar electrodes for electroabsorption modulator (EAM) was used for the flip-chip bonding package. The lasing wavelength of DFB laser could be tuned by the integrated micro-heater to match the ITU grids, which only needs one electrode pad. The average output power of each channel is 250 μW with an injection current of 200 mA. The static extinction ratios of the EAMs for 10 channels tested are ranged from 15 to 27 dB with a reverse bias of 6 V. The frequencies of 3 dB bandwidth of the chip for each channel are around 14 GHz. The novel design and simple fabrication process show its enormous potential in reducing the cost of large-scale photonic integrated circuit (LS-PIC) transmitter with high chip yields.

Electromigration induced high fraction of compound formation in SnAgCu flip chip solder joints with copper column

NASA Astrophysics Data System (ADS)

Xu, Luhua; Han, Jung-Kyu; Liang, Jarrett Jun; Tu, K. N.; Lai, Yi-Shao

2008-06-01

To overcome the effect of current crowding on electromigration-induced pancake-type void formation in flip chip solder joints, two types of Cu column in 90μm flip chip SnAgCu solder joints have been studied. They were (1) the solder contacts the Cu column at bottom and side walls and (2) the solder wets only the bottom surface of the copper column. With a current density of 1.6×104A/cm2 at 135°C, no failure was detected after 1290h. However, the resistance increased by about 10% due to the formation of a large fraction of intermetallic compounds. We found that electromigration has accelerated the consumption rate of copper column and converted almost the entire solder joint into intermetallic compound. Mechanically, drop impact test indicates a brittle fracture failure in the intermetallic. The electromigration critical product for the intermetallic is discussed.

276 nm Substrate-Free Flip-Chip AlGaN Light-Emitting Diodes

NASA Astrophysics Data System (ADS)

Hwang, Seongmo; Morgan, Daniel; Kesler, Amanda; Lachab, Mohamed; Zhang, Bin; Heidari, Ahmad; Nazir, Haseeb; Ahmad, Iftikhar; Dion, Joe; Fareed, Qhalid; Adivarahan, Vinod; Islam, Monirul; Khan, Asif

2011-03-01

Lateral-conduction, substrate-free flip-chip (SFFC) light-emitting diodes (LEDs) with peak emission at 276 nm are demonstrated for the first time. The AlGaN multiple quantum well LED structures were grown by metal-organic chemical vapor deposition (MOCVD) on thick-AlN laterally overgrown on sapphire substrates. To fabricate the SFFC LEDs, a newly-developed laser-assisted ablation process was employed to separate the substrate from the LED chips. The chips had physical dimensions of 1100×900 µm2, and were comprised of four devices each with a 100×100 µm2 junction area. Electrical and optical characterization of the devices revealed no noticeable degradation to their performance due to the laser-lift-off process.

Mitigating leakage errors due to cavity modes in a superconducting quantum computer

NASA Astrophysics Data System (ADS)

McConkey, T. G.; Béjanin, J. H.; Earnest, C. T.; McRae, C. R. H.; Pagel, Z.; Rinehart, J. R.; Mariantoni, M.

2018-07-01

A practical quantum computer requires quantum bit (qubit) operations with low error probabilities in extensible architectures. We study a packaging method that makes it possible to address hundreds of superconducting qubits by means of coaxial Pogo pins. A qubit chip is housed in a superconducting box, where both box and chip dimensions lead to unwanted modes that can interfere with qubit operations. We analyze these interference effects in the context of qubit coherent leakage and qubit decoherence induced by damped modes. We propose two methods, half-wave fencing and antinode pinning, to mitigate the resulting errors by detuning the resonance frequency of the modes from the qubit frequency. We perform electromagnetic field simulations indicating that the resonance frequency of the modes increases with the number of installed pins and can be engineered to be significantly higher than the highest qubit frequency. We estimate that the error probabilities and decoherence rates due to suitably shifted modes in realistic scenarios can be up to two orders of magnitude lower than the state-of-the-art superconducting qubit error and decoherence rates. Our methods can be extended to different types of packages that do not rely on Pogo pins. Conductive bump bonds, for example, can serve the same purpose in qubit architectures based on flip chip technology. Metalized vias, instead, can be used to mitigate modes due to the increasing size of the dielectric substrate on which qubit arrays are patterned.

Development of a RadFET Linear Array for Intracavitary in vivo Dosimetry During External Beam Radiotherapy and Brachytherapy

NASA Astrophysics Data System (ADS)

Price, R. A.; Benson, C.; Joyce, M. J.; Rodgers, K.

2004-08-01

We present the details of a new linear array dosimeter consisting of a chain of semiconductors mounted on an ultra-thin (50 /spl mu/m thick) flexible substrate and housed in an intracavitary catheter. The semiconductors, manufactured by NMRC Cork, have not been packaging and incorporate a passivation layer that allows them to be mounted on the substrate using flip-chip-bonding. This paper reports, for the first time, the construction of a multiple (ten) detector array suited to in vivo dosimetry in the rectum, esophagus and vagina during external beam radiotherapy, as well as being adaptable to in vivo dosimetry during brachytherapy and diagnostic radiology.

DOE Office of Scientific and Technical Information (OSTI.GOV)

McAdams, Brian J.; Pearson, Raymond A.

With the continuing trend of decreasing feature sizes in flip-chip assemblies, the reliability tolerance to interfacial flaws is also decreasing. Small-scale disbonds will become more of a concern, pointing to the need for a better understanding of the initiation stage of interfacial delamination. With most accepted adhesion metric methodologies tailored to predict failure under the prior existence of a disbond, the study of the initiation phenomenon is open to development and standardization of new testing procedures. Traditional fracture mechanics approaches are not suitable, as the mathematics assume failure to originate at a disbond or crack tip. Disbond initiation is believedmore » to first occur at free edges and corners, which act as high stress concentration sites and exhibit singular stresses similar to a crack tip, though less severe in intensity. As such, a 'fracture mechanics-like' approach may be employed which defines a material parameter--a critical stress intensity factor (K{sub c})--that can be used to predict when initiation of a disbond at an interface will occur. The factors affecting the adhesion of underfill/polyimide interfaces relevant to flip-chip assemblies were investigated in this study. The study consisted of two distinct parts: a comparison of the initiation and propagation phenomena and a comparison of the relationship between sub-critical and critical initiation of interfacial failure. The initiation of underfill interfacial failure was studied by characterizing failure at a free-edge with a critical stress intensity factor. In comparison with the interfacial fracture toughness testing, it was shown that a good correlation exists between the initiation and propagation of interfacial failures. Such a correlation justifies the continuing use of fracture mechanics to predict the reliability of flip-chip packages. The second aspect of the research involved fatigue testing of tensile butt joint specimens to determine lifetimes at sub-critical load levels. The results display an interfacial strength ranking similar to that observed during monotonic testing. The fatigue results indicate that monotonic fracture mechanics testing may be an adequate screening tool to help predict cyclic underfill failure; however lifetime data is required to predict reliability.« less

Spatial redistribution of radiation in flip-chip photodiodes based on InAsSbP/InAs double heterostructures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zakgeim, A. L.; Il’inskaya, N. D.; Karandashev, S. A.

2017-02-15

The spatial distribution of equilibrium and nonequilibrium (including luminescent) IR (infrared) radiation in flip-chip photodiodes based on InAsSbP/InAs double heterostructures (λ{sub max} = 3.4 μm) is measured and analyzed; the structural features of the photodiodes, including the reflective properties of the ohmic contacts, are taken into account. Optical area enhancement due to multiple internal reflection in photodiodes with different geometric characteristics is estimated.

Flip Chip Bonding of 68 x 68 MWIR LED Arrays

DTIC Science & Technology

2009-01-01

transmission of IR light through GaSb material varies between 5%–30% and depends on the type of substrate dopants (n- or p-type). Hence, for bottom...emission regions (8.9/16 monolayer’s (ml) InAs/GaSb) separated by (n InAs/GaSb super lattice grade)/(p+ GaSb) tunnel junctions. Graded super lattices were...flip chip bonding process. Besides four corner LED test pads, there are 296 bonding pads in the CMOS driver to bias each LED pixel independently. The

Flip-chip replacement within the constraints imposed by multilayer ceramic (MLC) modules

NASA Astrophysics Data System (ADS)

Puttlitz, Karl J.

1984-01-01

Economics often dictates that suitable module rework procedures be established to replace solder bump devices (flip chips) reflowed to multichip carriers. These operations are complicated, owing to various constraints such as the substrate's physical and mechanical properties, close proximity of surface features, etc. This paper describes the constraints and the methods to circumvent them. An order of preference based upon the degree of constraint is recommended to achieve device removal and subsequent site dress of the residual solder left on the substrate. It has been determined that rework (device replacement) can be successfully achieved in even highly constricted situations. This is illustrated by the example of utilizing a localized heating technique, hot gas, to remove solder from microsockets from which chips were previously removed. Microsockets are areas to which chips are reflowed to the top surface of IBM's densely populated multilayer ceramic (MLC) modules, thus forming the so-called controlled collapse chip connection or C-4. The microsocket patterns are thus identical to the chip footprint.

Development of advanced micromirror arrays by flip-chip assembly

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper presents the design, commercial prefabrication, modeling and testing of advanced micromirror arrays fabricated using a novel, simple and inexpensive flip-chip assembly technique. Several polar piston arrays and rectangular cantilever arrays were fabricated using flip-chip assembly by which the upper layers of the array are fabricated on a separate chip and then transferred to a receiving module containing the lower layers. Typical polar piston arrays boast 98.3% active surface area, highly planarized surfaces, low address potentials compatible with CMOS electronics, highly standardized actuation between devices, and complex segmentation of mirror surfaces which allows for custom aberration configurations. Typical cantilever arrays boast large angles of rotation as well as an average surface planarity of only 1.779 nm of RMS roughness across 100 +m mirrors. Continuous torsion devices offer stable operation through as much as six degrees of rotation while binary operation devices offer stable activated positions with as much as 20 degrees of rotation. All arrays have desirable features of costly fabrication services like five structural layers and planarized mirror surfaces, but are prefabricated in the less costly MUMPs process. Models are developed for all devices and used to compare empirical data.

A crunch on thermocompression flip chip bonding

NASA Astrophysics Data System (ADS)

Suppiah, Sarveshvaran; Ong, Nestor Rubio; Sauli, Zaliman; Sarukunaselan, Karunavani; Alcain, Jesselyn Barro; Mahmed, Norsuria; Retnasamy, Vithyacharan

2017-09-01

This study discussed the evolution and important findings, critical technical challenges, solutions and bonding equipment of flip chip thermo compression bonding (TCB). The bonding force, temperature and time were the key bonding parameters that need to be tweaked based on the researches done by others. TCB technology worked well with both pre-applied underfill and flux (still under development). Lower throughput coupled with higher processing costs was example of challenges in the TCB technology. The paper is concluded with a brief description of the current equipment used in thermo compression process.

High-frequency ultrasonic wire bonding systems

PubMed

Tsujino; Yoshihara; Sano; Ihara

2000-03-01

The vibration characteristics of longitudinal-complex transverse vibration systems with multiple resonance frequencies of 350-980 kHz for ultrasonic wire bonding of IC, LSI or electronic devices were studied. The complex vibration systems can be applied for direct welding of semiconductor tips (face-down bonding, flip-chip bonding) and packaging of electronic devices. A longitudinal-complex transverse vibration bonding system consists of a complex transverse vibration rod, two driving longitudinal transducers 7.0 mm in diameter and a transverse vibration welding tip. The vibration distributions along ceramic and stainless-steel welding tips were measured at up to 980 kHz. A high-frequency vibration system with a height of 20.7 mm and a weight of less than 15 g was obtained.

Light-extraction enhancement of GaN-based 395  nm flip-chip light-emitting diodes by an Al-doped ITO transparent conductive electrode.

PubMed

Xu, Jin; Zhang, Wei; Peng, Meng; Dai, Jiangnan; Chen, Changqing

2018-06-01

The distinct ultraviolet (UV) light absorption of indium tin oxide (ITO) limits the performance of GaN-based near-UV light-emitting diodes (LEDs). Herein, we report an Al-doped ITO with enhanced UV transmittance and low sheet resistance as the transparent conductive electrode for GaN-based 395 nm flip-chip near-UV LEDs. The thickness dependence of optical and electrical properties of Al-doped ITO films is investigated. The optimal Al-doped ITO film exhibited a transmittance of 93.2% at 395 nm and an average sheet resistance of 30.1  Ω/sq. Meanwhile, at an injection current of 300 mA, the forward voltage decreased from 3.14 to 3.11 V, and the light output power increased by 13% for the 395 nm near-UV flip-chip LEDs with the optimal Al-doped ITO over those with pure ITO. This Letter provides a simple and repeatable approach to further improve the light extraction efficiency of GaN-based near-UV LEDs.

Qualification and Reliability for MEMS and IC Packages

NASA Technical Reports Server (NTRS)

Ghaffarian, Reza

2004-01-01

Advanced IC electronic packages are moving toward miniaturization from two key different approaches, front and back-end processes, each with their own challenges. Successful use of more of the back-end process front-end, e.g. microelectromechanical systems (MEMS) Wafer Level Package (WLP), enable reducing size and cost. Use of direct flip chip die is the most efficient approach if and when the issues of know good die and board/assembly are resolved. Wafer level package solve the issue of known good die by enabling package test, but it has its own limitation, e.g., the I/O limitation, additional cost, and reliability. From the back-end approach, system-in-a-package (SIAP/SIP) development is a response to an increasing demand for package and die integration of different functions into one unit to reduce size and cost and improve functionality. MEMS add another challenging dimension to electronic packaging since they include moving mechanical elements. Conventional qualification and reliability need to be modified and expanded in most cases in order to detect new unknown failures. This paper will review four standards that already released or being developed that specifically address the issues on qualification and reliability of assembled packages. Exposures to thermal cycles, monotonic bend test, mechanical shock and drop are covered in these specifications. Finally, mechanical and thermal cycle qualification data generated for MEMS accelerometer will be presented. The MEMS was an element of an inertial measurement unit (IMU) qualified for NASA Mars Exploration Rovers (MERs), Spirit and Opportunity that successfully is currently roaring the Martian surface

Detection of micro solder balls using active thermography and probabilistic neural network

NASA Astrophysics Data System (ADS)

He, Zhenzhi; Wei, Li; Shao, Minghui; Lu, Xingning

2017-03-01

Micro solder ball/bump has been widely used in electronic packaging. It has been challenging to inspect these structures as the solder balls/bumps are often embedded between the component and substrates, especially in flip-chip packaging. In this paper, a detection method for micro solder ball/bump based on the active thermography and the probabilistic neural network is investigated. A VH680 infrared imager is used to capture the thermal image of the test vehicle, SFA10 packages. The temperature curves are processed using moving average technique to remove the peak noise. And the principal component analysis (PCA) is adopted to reconstruct the thermal images. The missed solder balls can be recognized explicitly in the second principal component image. Probabilistic neural network (PNN) is then established to identify the defective bump intelligently. The hot spots corresponding to the solder balls are segmented from the PCA reconstructed image, and statistic parameters are calculated. To characterize the thermal properties of solder bump quantitatively, three representative features are selected and used as the input vector in PNN clustering. The results show that the actual outputs and the expected outputs are consistent in identification of the missed solder balls, and all the bumps were recognized accurately, which demonstrates the viability of the PNN in effective defect inspection in high-density microelectronic packaging.

A 16K-bit static IIL RAM with 25-ns access time

NASA Astrophysics Data System (ADS)

Inabe, Y.; Hayashi, T.; Kawarada, K.; Miwa, H.; Ogiue, K.

1982-04-01

A 16,384 x 1-bit RAM with 25-ns access time, 600-mW power dissipation, and 33 sq mm chip size has been developed. Excellent speed-power performance with high packing density has been achieved by an oxide isolation technology in conjunction with novel ECL circuit techniques and IIL flip-flop memory cells, 980 sq microns (35 x 28 microns) in cell size. Development results have shown that IIL flip-flop memory cell is a trump card for assuring achievement of a high-performance large-capacity bipolar RAM, in the above 16K-bit/chip area.

Electromigration in solder joints and solder lines

NASA Astrophysics Data System (ADS)

Gan, H.; Choi, W. J.; Xu, G.; Tu, K. N.

2002-06-01

Electromigration may affect the reliability of flip-chip solder joints. Eutectic solder is a two-phase alloy, so its electromigration behavior is different from that in aluminum or copper interconnects. In addition, a flipchip solder joint has a built-in currentcrowding configuration to enhance electromigration failure. To better understand electromigration in SnPb and lead-free solder alloys, the authors prepared solder lines in v-grooves etched on Si (001). This article discusses the results of those tests and compares the electromigration failure modes of eutectic SnPb and SnAgCu flip-chip solder joints along with the mean-timeto-failure.

Quantifying the benefits of improved rolling of chip seals : final report, June 2008.

DOT National Transportation Integrated Search

2008-06-01

This report presents an improvement in the rolling protocol for chip seals based on an evaluation of aggregate : retention performance and aggregate embedment depth. The flip-over test (FOT), Vialit test, modified sand circle : test, digital image pr...

Mean-time-to-failure study of flip chip solder joints on Cu/Ni(V)/Al thin-film under-bump-metallization

NASA Astrophysics Data System (ADS)

Choi, W. J.; Yeh, E. C. C.; Tu, K. N.

2003-11-01

Electromigration of eutectic SnPb flip chip solder joints and their mean-time-to-failure (MTTF) have been studied in the temperature range of 100 to 140 °C with current densities of 1.9 to 2.75×104 A/cm2. In these joints, the under-bump-metallization (UBM) on the chip side is a multilayer thin film of Al/Ni(V)/Cu, and the metallic bond-pad on the substrate side is a very thick, electroless Ni layer covered with 30 nm of Au. When stressed at the higher current densities, the MTTF was found to decrease much faster than what is expected from the published Black's equation. The failure occurred by interfacial void propagation at the cathode side, and it is due to current crowding near the contact interface between the solder bump and the thin-film UBM. The current crowding is confirmed by a simulation of current distribution in the solder joint. Besides the interfacial void formation, the intermetallic compounds formed on the UBM as well as the Ni(V) film in the UBM have been found to dissolve completely into the solder bump during electromigration. Therefore, the electromigation failure is a combination of the interfacial void formation and the loss of UBM. Similar findings in eutectic SnAgCu flip chip solder joints have also been obtained and compared.

Flipping the Calculus Classroom: An Evaluative Study

ERIC Educational Resources Information Center

Maciejewski, Wes

2016-01-01

Classroom flipping is the practice of moving new content instruction out of class time, usually packaging it as online videos and reading assignments for students to cover on their own, and devoting in-class time to interactive engagement activities. Flipping has garnered a large amount of hype from the popular education media and has been adopted…

Development of n+-in-p planar pixel quadsensor flip-chipped with FE-I4 readout ASICs

NASA Astrophysics Data System (ADS)

Unno, Y.; Kamada, S.; Yamamura, K.; Yamamoto, H.; Hanagaki, K.; Hori, R.; Ikegami, Y.; Nakamura, K.; Takubo, Y.; Takashima, R.; Tojo, J.; Kono, T.; Nagai, R.; Saito, S.; Sugibayashi, K.; Hirose, M.; Jinnouchi, O.; Sato, S.; Sawai, H.; Hara, K.; Sato, Kz.; Sato, Kj.; Iwabuchi, S.; Suzuki, J.

2017-01-01

We have developed flip-chip modules applicable to the pixel detector for the HL-LHC. New radiation-tolerant n+-in-p planar pixel sensors of a size of four FE-I4 application-specific integrated circuits (ASICs) are laid out in a 6-in wafer. Variation in readout connection for the pixels at the boundary of ASICs is implemented in the design of quadsensors. Bump bonding technology is developed for four ASICs onto one quadsensor. Both sensors and ASICs are thinned to 150 μm before bump bonding, and are held flat with vacuum chucks. Using lead-free SnAg solder bumps, we encounter deficiency with large areas of disconnected bumps after thermal stress treatment, including irradiation. Surface oxidation of the solder bumps is identified as a critical source of this deficiency after bump bonding trials, using SnAg bumps with solder flux, indium bumps, and SnAg bumps with a newly-introduced hydrogen-reflow process. With hydrogen-reflow, we establish flux-less bump bonding technology with SnAg bumps, appropriate for mass production of the flip-chip modules with thin sensors and thin ASICs.

Embeded photonic crystal at the interface of p-GaN and Ag reflector to improve light extraction of GaN-based flip-chip light-emitting diode

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhen, Aigong; Ma, Ping, E-mail: maping@semi.ac.cn; Zhang, Yonghui

2014-12-22

In this experiment, a flip-chip light-emitting diode with photonic crystal was fabricated at the interface of p-GaN and Ag reflector via nanospheres lithography technique. In this structure, photonic crystal could couple with the guide-light efficiently by reason of the little distance between photonic crystal and active region. The light output power of light emitting diode with embedded photonic crystal was 1.42 times larger than that of planar flip-chip light-emitting diode. Moreover, the embedded photonic crystal structure makes the far-field divergence angle decreased by 18° without spectra shift. The three-dimensional finite difference time domain simulation results show that photonic crystal couldmore » improve the light extraction, and enhance the light absorption caused by Ag reflector simultaneously, because of the roughed surface. The depth of photonic crystal is the key parameter affecting the light extraction and absorption. Light extraction efficiency increases with the depth photonic crystal structure rapidly, and reaches the maximum at the depth 80 nm, beyond which light extraction decrease drastically.« less

Multigigabit optical transceivers for high-data rate military applications

NASA Astrophysics Data System (ADS)

Catanzaro, Brian E.; Kuznia, Charlie

2012-01-01

Avionics has experienced an ever increasing demand for processing power and communication bandwidth. Currently deployed avionics systems require gigabit communication using opto-electronic transceivers connected with parallel optical fiber. Ultra Communications has developed a series of transceiver solutions combining ASIC technology with flip-chip bonding and advanced opto-mechanical molded optics. Ultra Communications custom high speed ASIC chips are developed using an SoS (silicon on sapphire) process. These circuits are flip chip bonded with sources (VCSEL arrays) and detectors (PIN diodes) to create an Opto-Electronic Integrated Circuit (OEIC). These have been combined with micro-optics assemblies to create transceivers with interfaces to standard fiber array (MT) cabling technology. We present an overview of the demands for transceivers in military applications and how new generation transceivers leverage both previous generation military optical transceivers as well as commercial high performance computing optical transceivers.

Improved light extraction efficiency of GaN-based flip-chip light-emitting diodes with an antireflective interface layer

NASA Astrophysics Data System (ADS)

Wu, Dongxue; Ma, Ping; Liu, Boting; Zhang, Shuo; Wang, Junxi; Li, Jinmin

2016-05-01

GaN-based flip-chip light-emitting diodes (FC-LEDs) grown on nanopatterned sapphire substrates (NPSS) are fabricated using self-assembled SiO2 nanospheres as masks during inductively coupled plasma etching. By controlling the pattern spacing, epitaxial GaN can be grown from the top or bottom of patterns to obtain two different GaN/substrate interfaces. The optoelectronic characteristics of FC-LED chips with different GaN/sapphire interfaces are studied. The FC-LED with an antireflective interface layer consisting of a NPSS with GaN in the pattern spacings demonstrates better optical properties than the FC-LED with an interface embedded with air voids. Our study indicates that the two types of FC-LEDs grown on NPSS show higher crystal quality and improved electrical and optical characteristics compared with those of FC-LEDs grown on conventional planar sapphire substrates.

4-GHz counters bring synthesizers up to speed

NASA Astrophysics Data System (ADS)

Lee, F.; Miller, R.

1984-06-01

The availability of digital IC counters built on GaAs makes direct frequency division in microwave synthesizers possible. Four GHz is the highest clock rate achievable in production designs. These devices have the ability to drive TTL/CMOS logic, and the counter can be connected directly to single-chip frequency synthesizers controllers. A complete microwave sythesizer is formed by two chips and a voltage-controlled oscillator (VCO). The advantages of GaAs are discussed along with flip-flop basics, aspects of device fabrication, and the characteristics of GaAs MESAFETs. Attention is given to a GaAs prescaler usable for direct conversion, four kinds of flip-flops in a divide-by-two mode, and seven-stage binary ripple counters.

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Li, K.; Shih, Y. C.

1992-01-01

Packaging schemes were developed that provide low-loss, hermetic enclosure for advanced monolithic microwave and millimeter-wave integrated circuits (MMICs). The package designs are based on a fused quartz substrate material that offers improved radio frequency (RF) performance through 44 gigahertz (GHz). The small size and weight of the packages make them appropriate for a variety of applications, including phased array antenna systems. Packages were designed in two forms; one for housing a single MMIC chip, the second in the form of a multi-chip phased array module. The single chip array module was developed in three separate sizes, for chips of different geometry and frequency requirements. The phased array module was developed to address packaging directly for antenna applications, and includes transmission line and interconnect structures to support multi-element operation. All packages are fabricated using fused quartz substrate materials. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices. The package and test fixture designs were both developed in a generic sense, optimizing performance for a wide range of possible applications and devices.

Read disturb errors in a CMOS static RAM chip. [radiation hardened for spacedraft

NASA Technical Reports Server (NTRS)

Wood, Steven H.; Marr, James C., IV; Nguyen, Tien T.; Padgett, Dwayne J.; Tran, Joe C.; Griswold, Thomas W.; Lebowitz, Daniel C.

1989-01-01

Results are reported from an extensive investigation into pattern-sensitive soft errors (read disturb errors) in the TCC244 CMOS static RAM chip. The TCC244, also known as the SA2838, is a radiation-hard single-event-upset-resistant 4 x 256 memory chip. This device is being used by the Jet Propulsion Laboratory in the Galileo and Magellan spacecraft, which will have encounters with Jupiter and Venus, respectively. Two aspects of the part's design are shown to result in the occurrence of read disturb errors: the transparence of the signal path from the address pins to the array of cells, and the large resistance in the Vdd and Vss lines of the cells in the center of the array. Probe measurements taken during a read disturb failure illustrate how address skews and the data pattern in the chip combine to produce a bit flip. A capacitive charge pump formed by the individual cell capacitances and the resistance in the supply lines pumps down both the internal cell voltage and the local supply voltage until a bit flip occurs.

Biwavelength transceiver module for parallel simultaneous bidirectional optical interconnections

NASA Astrophysics Data System (ADS)

Nguyen, Nga T. H.; Ukaegbu, Ikechi A.; Sangirov, Jamshid; Cho, Mu-Hee; Lee, Tae-Woo; Park, Hyo-Hoon

2013-12-01

The design of a biwavelength transceiver (TRx) module for parallel simultaneous bidirectional optical interconnects is described. The TRx module has been implemented using two different wavelengths, 850 and 1060 nm, to send and receive signals simultaneously through a common optical interface while optimizing cost and performance. Filtering mirrors are formed in the optical fibers which are embedded on a V-grooved silicon substrate for reflecting and filtering optical signals from/to vertical-cavity surface-emitting laser (VCSEL)/photodiode (PD). The VCSEL and PD are flip-chip bonded on individual silicon optical benches, which are attached on the silicon substrate for optical signal coupling from the VCSEL to fiber and from fiber to the PD. A high-speed and low-loss ceramic printed circuit board, which has a compact size of 0.033 cc, has been designed to carry transmitter and receiver chips for easy packaging of the TRx module. Applied for quad small form-factor pluggable applications at 40-Gbps operation, the four-channel biwavelength TRx module showed clear eye diagrams with a bit error rate (BER) of 10-12 at input powers of -5 and -5.8 dBm for 1060 and 850 nm operation modes, respectively.

Current crowding and self-heating effects in AlGaN-based flip-chip deep-ultraviolet light-emitting diodes

NASA Astrophysics Data System (ADS)

Hao, Guo-Dong; Taniguchi, Manabu; Tamari, Naoki; Inoue, Shin-ichiro

2018-01-01

We thoroughly explored the physical origin of the efficiency decrease with increasing injection current and current crowding effect in 280 nm AlGaN-based flip-chip deep-ultraviolet (DUV) light-emitting diodes (LEDs). The current spreading length was experimentally determined to be much smaller in DUV LEDs than that in conventional InGaN-based visible LEDs. The severe self-heating caused by the low power conversion efficiency of DUV LEDs should be mainly responsible for the considerable decrease of efficiency when current crowding is present. The wall-plug efficiency of the DUV LEDs was markedly enhanced by using a well-designed p-electrode pattern to improve the current distribution.

Effect of Al-trace dimension on Joule heating and current crowding in flip-chip solder joints under accelerated electromigration

NASA Astrophysics Data System (ADS)

Liang, S. W.; Chang, Y. W.; Chen, Chih

2006-04-01

Three-dimensional thermoelectrical simulation was conducted to investigate the influence of Al-trace dimension on Joule heating and current crowding in flip-chip solder joints. It is found that the dimension of the Al-trace effects significantly on the Joule heating, and thus directly determines the mean time to failure (MTTF). Simulated at a stressing current of 0.6A at 70°C, we estimate that the MTTF of the joints with Al traces in 100μm width was 6.1 times longer than that of joints with Al traces in 34μm width. Lower current crowding effect and reduced hot-spot temperature are responsible for the improved MTTF.

Flip-chip fabrication of integrated micromirror arrays using a novel latching off-chip hinge mechanism

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper presents the design, fabrication, modeling, and testing of various arrays of cantilever micromirror devices integrated atop CMOS control electronics. The upper layers of the arrays are prefabricated in the MUMPs process and then flip-chip transferred to CMOS receiving modules using a novel latching off-chip hinge mechanism. This mechanism allows the micromirror arrays to be released, rotated off the edge of the host module and then bonded to the receiving module using a standard probe station. The hinge mechanism supports the arrays by tethers that are severed to free the arrays once bonded. The resulting devices are inherently planarized since the bottom of the first releasable MUMPs layer becomes the surface of the integrated mirror. The working devices are formed by mirror surfaces bonded to address electrodes fabricated above static memory cells on the CMOS module. These arrays demonstrate highly desirable features such as compatible address potentials, less than 2 nm of RMS roughness, approximately 1 micrometers of lateral position accuracy and the unique ability to metallize reflective surfaces without masking. Ultimately, the off-chip hinge mechanism enables very low-cost, simple, reliable, repeatable and accurate assembly of advanced MEMS and integrated microsystems without specialized equipment or complex procedures.

A review on solder reflow and flux application for flip chip

NASA Astrophysics Data System (ADS)

Suppiah, Sarveshvaran; Ong, Nestor Rubio; Sauli, Zaliman; Sarukunaselan, Karunavani; Alcain, Jesselyn Barro; Visvanathan, Susthitha Menon; Retnasamy, Vithyacharan

2017-09-01

This paper encompassed of the evolution and key findings, critical technical challenges, solutions and bonding equipment of solder reflow in flip chip bonding. Upon scrutinizing researches done by others, it can be deduced that peak temperature, time above liquidus, soak temperature, soak time, cooling rate and reflow environment played a vital role in achieving the desired bonding profile. In addition, flux is also needed with the purpose of removing oxides/contaminations on bump surface as well as to promote wetting of solder balls. Electromigration and warpage are the two main challenges faced by solder reflow process which can be overcome by the advancement in under bump metallization (UBM) and substrate technology. The review is ended with a brief description of the current equipment used in solder reflow process.

Effect of thermal cycling ramp rate on CSP assembly reliability

NASA Technical Reports Server (NTRS)

Ghaffarian, R.

2001-01-01

A JPL-led chip scale package consortium of enterprises recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages for a variety of projects. The experience of the consortium in building more than 150 test vehicle assemblies, single and double sided multilayer PWBs, and the environmental test results has now been published as a chip scale package guidelines document.

Storage stability of banana chips in polypropylene based nanocomposite packaging films.

PubMed

Manikantan, M R; Sharma, Rajiv; Kasturi, R; Varadharaju, N

2014-11-01

In this study, polypropylene (PP) based nanocomposite films of 15 different compositions of nanoclay, compatibilizer and thickness were developed and used for packaging and storage of banana chips. The effect of nanocomposite films on the quality characteristics viz. moisture content (MC), water activity (WA), total color difference(TCD), breaking force (BF), free fatty acid (FFA), peroxide value(PV), total plate count (TPC) and overall acceptability score of banana chips under ambient condition at every 15 days interval were studied for 120 days. All quality parameters of stored banana chips increased whereas overall acceptability scores decreased during storage. The elevation in FFA, BF and TCD of stored banana chips increased with elapse of storage period as well as with increased proportion of both nanoclay and compatibilizer but decreased by reducing the thickness of film. Among all the packaging materials, the WA of banana chips remained lower than 0.60 i.e. critical limit for microbial growth up to 90 days of storage. The PV of banana chips packaged also remained within the safe limit of 25 meq oxygen kg(-1) throughout the storage period. Among all the nanocomposite films, packaging material having 5 % compatibilizer, 2 % nanoclay & 100 μm thickness (treatment E) and 10 % compatibilizer, 4 % nanoclay & 120 μm thickness (treatment N) showed better stability of measured quality characteristics of banana chips than any other treatment.

Integrated circuit package with lead structure and method of preparing the same

NASA Technical Reports Server (NTRS)

Kennedy, B. W. (Inventor)

1973-01-01

A beam-lead integrated circuit package assembly including a beam-lead integrated circuit chip, a lead frame array bonded to projecting fingers of the chip, a rubber potting compound disposed around the chip, and an encapsulating molded plastic is described. The lead frame array is prepared by photographically printing a lead pattern on a base metal sheet, selectively etching to remove metal between leads, and plating with gold. Joining of the chip to the lead frame array is carried out by thermocompression bonding of mating goldplated surfaces. A small amount of silicone rubber is then applied to cover the chip and bonded joints, and the package is encapsulated with epoxy resin, applied by molding.

Reliability study of high-brightness multiple single emitter diode lasers

NASA Astrophysics Data System (ADS)

Zhu, Jing; Yang, Thomas; Zhang, Cuipeng; Lang, Chao; Jiang, Xiaochen; Liu, Rui; Gao, Yanyan; Guo, Weirong; Jiang, Yuhua; Liu, Yang; Zhang, Luyan; Chen, Louisa

2015-03-01

In this study the chip bonding processes for various chips from various chip suppliers around the world have been optimized to achieve reliable chip on sub-mount for high performance. These chip on sub-mounts, for examples, includes three types of bonding, 8xx nm-1.2W/10.0W Indium bonded lasers, 9xx nm 10W-20W AuSn bonded lasers and 1470 nm 6W Indium bonded lasers will be reported below. The MTTF@25 of 9xx nm chip on sub-mount (COS) is calculated to be more than 203,896 hours. These chips from various chip suppliers are packaged into many multiple single emitter laser modules, using similar packaging techniques from 2 emitters per module to up to 7 emitters per module. A reliability study including aging test is performed on those multiple single emitter laser modules. With research team's 12 years' experienced packaging design and techniques, precise optical and fiber alignment processes and superior chip bonding capability, we have achieved a total MTTF exceeding 177,710 hours of life time with 60% confidence level for those multiple single emitter laser modules. Furthermore, a separated reliability study on wavelength stabilized laser modules have shown this wavelength stabilized module packaging process is reliable as well.

Ultrafast all-optical flip-flop based on passive micro Sagnac waveguide ring with photonic crystal fiber.

PubMed

Xu, Ming; Yang, Wan; Hong, Tao; Kang, TangZhen; Ji, JianHua; Wang, Ke

2017-06-01

Ultrafast all-optical flip-flop based on a passive micro Sagnac waveguide ring is studied through theoretical analysis and numerical simulation in this paper. The types of D, R-S, J-K, and T flip-flop are designed by controlling the cross-phase modulation effect of lights in this special microring. The high nonlinearity of the hollow-core photonic crystal fiber is implanted on a chip to shorten the length of the ring and reduce input power. By sensible management, the pulse width ratio of the input and the control signal, problems of pulse narrowing, and residual pedestal at the out port are solved. The parameters affecting the performance of flip-flops are optimized. The results show that the all-optical flip-flops have stable performance, low power consumption, high transmission rate (up to 100  Gb/s), and response time in picosecond order. The small size microwaveguide structure is suitable for photonic integration.

Optimization of Indium Bump Morphology for Improved Flip Chip Devices

NASA Technical Reports Server (NTRS)

Jones, Todd J.; Nikzad, Shouleh; Cunningham, Thomas J.; Blazejewski, Edward; Dickie, Matthew R.; Hoenk, Michael E.; Greer, Harold F.

2011-01-01

Flip-chip hybridization, also known as bump bonding, is a packaging technique for microelectronic devices that directly connects an active element or detector to a substrate readout face-to-face, eliminating the need for wire bonding. In order to make conductive links between the two parts, a solder material is used between the bond pads on each side. Solder bumps, composed of indium metal, are typically deposited by thermal evaporation onto the active regions of the device and substrate. While indium bump technology has been a part of the electronic interconnect process field for many years and has been extensively employed in the infrared imager industry, obtaining a reliable, high-yield process for high-density patterns of bumps can be quite difficult. Under the right conditions, a moderate hydrogen plasma exposure can raise the temperature of the indium bump to the point where it can flow. This flow can result in a desirable shape where indium will efficiently wet the metal contact pad to provide good electrical contact to the underlying readout or imager circuit. However, it is extremely important to carefully control this process as the intensity of the hydrogen plasma treatment dramatically affects the indium bump morphology. To ensure the fine-tuning of this reflow process, it is necessary to have realtime feedback on the status of the bumps. With an appropriately placed viewport in a plasma chamber, one can image a small field (a square of approximately 5 millimeters on each side) of the bumps (10-20 microns in size) during the hydrogen plasma reflow process. By monitoring the shape of the bumps in real time using a video camera mounted to a telescoping 12 magnifying zoom lens and associated optical elements, an engineer can precisely determine when the reflow of the bumps has occurred, and can shut off the plasma before evaporation or de-wetting takes place.

Nano-engineered Multiwall Carbon Nanotube-copper Composite Thermal Interface Material for Efficient Heat Conduction

NASA Technical Reports Server (NTRS)

Ngo, Quoc; Cruden, Brett A.; Cassell, Alan M.; Sims, Gerard; Li, Jun; Meyyappa, M.; Yang, Cary Y.

2005-01-01

Efforts in integrated circuit (IC) packaging technologies have recently been focused on management of increasing heat density associated with high frequency and high density circuit designs. While current flip-chip package designs can accommodate relatively high amounts of heat density, new materials need to be developed to manage thermal effects of next-generation integrated circuits. Multiwall carbon nanotubes (MWNT) have been shown to significantly enhance thermal conduction in the axial direction and thus can be considered to be a candidate for future thermal interface materials by facilitating efficient thermal transport. This work focuses on fabrication and characterization of a robust MWNT-copper composite material as an element in IC package designs. We show that using vertically aligned MWNT arrays reduces interfacial thermal resistance by increasing conduction surface area, and furthermore, the embedded copper acts as a lateral heat spreader to efficiently disperse heat, a necessary function for packaging materials. In addition, we demonstrate reusability of the material, and the absence of residue on the contacting material, both novel features of the MWNT-copper composite that are not found in most state-of-the-art thermal interface materials. Electrochemical methods such as metal deposition and etch are discussed for the creation of the MWNT-Cu composite, detailing issues and observations with using such methods. We show that precise engineering of the composite surface affects the ability of this material to act as an efficient thermal interface material. A thermal contact resistance measurement has been designed to obtain a value of thermal contact resistance for a variety of different thermal contact materials.

Chip design for thin-film deep ultraviolet LEDs fabricated by laser lift-off of the sapphire substrate

NASA Astrophysics Data System (ADS)

Cho, H. K.; Krüger, O.; Külberg, A.; Rass, J.; Zeimer, U.; Kolbe, T.; Knauer, A.; Einfeldt, S.; Weyers, M.; Kneissl, M.

2017-12-01

We report on a chip design which allows the laser lift-off (LLO) of the sapphire substrate sustaining the epitaxial film of flip-chip mounted deep ultraviolet light emitting diodes. A nanosecond pulsed excimer laser with a wavelength of 248 nm was used for the LLO. A mechanically stable chip design was found to be the key to prevent crack formation in the epitaxial layers and material chipping during the LLO process. Stabilization was achieved by introducing a Ti/Au leveling layer that mechanically supports the fragile epitaxial film. The electrical and optical characterization of devices before and after the LLO process shows that the device performance did not degrade by the LLO.

Apparatus and methods for packaging integrated circuit chips with antenna modules providing closed electromagnetic environment for integrated antennas

NASA Technical Reports Server (NTRS)

Gaucher, Brian P. (Inventor); Grzyb, Janusz (Inventor); Liu, Duixian (Inventor); Pfeiffer, Ullrich R. (Inventor)

2008-01-01

Apparatus and methods are provided for packaging IC chips together with integrated antenna modules designed to provide a closed EM (electromagnetic) environment for antenna radiators, thereby allowing antennas to be designed independent from the packaging technology.

3D packaging of a microfluidic system with sensory applications

NASA Astrophysics Data System (ADS)

Morrissey, Anthony; Kelly, Gerard; Alderman, John C.

1997-09-01

Among the main benefits of microsystem technology are its contributions to cost reductio, reliability and improved performance. however, the packaging of microsystems, and particularly microsensor, has proven to be one of the biggest limitations to their commercialization and the packaging of silicon sensor devices can be the most costly part of their fabrication. This paper describes the integration of 3D packaging of a microsystem. Central to the operation of the 3D demonstrator is a micromachined silicon membrane pump to supply fluids to a sensing chamber constructed about the active area of a sensor chip. This chip carries ISFET based chemical sensors, pressure sensors and thermal sensors. The electronics required for controlling and regulating the activity of the various sensors ar also available on this chip and as other chips in the 3D assembly. The demonstrator also contains a power supply module with optical fiber interconnections. All of these modules are integrated into a single plastic- encapsulated 3D vertical multichip module. The reliability of such a structure, initially proposed by Val was demonstrated by Barrett et al. An additional module available for inclusion in some of our assemblies is a test chip capable of measuring the packaging-induced stress experienced during and after assembly. The packaging process described produces a module with very high density and utilizes standard off-the-shelf components to minimize costs. As the sensor chip and micropump include micromachined silicon membranes and microvalves, the packaging of such structures has to allow consideration for the minimization of the packaging-induced stresses. With this in mind, low stress techniques, including the use of soft glob-top materials, were employed.

Mechanical flip-chip for ultra-high electron mobility devices

DOE PAGES

Bennaceur, Keyan; Schmidt, Benjamin A.; Gaucher, Samuel; ...

2015-09-22

In this study, electrostatic gates are of paramount importance for the physics of devices based on high-mobility two-dimensional electron gas (2DEG) since they allow depletion of electrons in selected areas. This field-effect gating enables the fabrication of a wide range of devices such as, for example, quantum point contacts (QPC), electron interferometers and quantum dots. To fabricate these gates, processing is usually performed on the 2DEG material, which is in many cases detrimental to its electron mobility. Here we propose an alternative process which does not require any processing of the 2DEG material other than for the ohmic contacts. Thismore » approach relies on processing a separate wafer that is then mechanically mounted on the 2DEG material in a flip-chip fashion. This technique proved successful to fabricate quantum point contacts on both GaAs/AlGaAs materials with both moderate and ultra-high electron mobility.« less

Nanoparticle embedded p-type electrodes for GaN-based flip-chip light emitting diodes.

PubMed

Kwak, Joon Seop; Song, J O; Seong, T Y; Kim, B I; Cho, J; Sone, C; Park, Y

2006-11-01

We have investigated high-quality ohmic contacts for flip-chip light emitting diodes using Zn-Ni nanoparticles/Ag schemes. The Zn-Ni nanoparticles/Ag contacts produce specific contact resistances of 10(-5)-10(-6) omegacm2 when annealed at temperatures of 330-530 degrees C for 1 min in air ambient, which are much better than those obtained from the Ag contacts. It is shown that blue InGaN/GaN multi-quantum well light emitting diodes fabricated with the annealed Zn-Ni nanoparticles/Ag contacts give much lower forward-bias voltages at 20 mA compared with those of the multi-quantum well light emitting diodes made with the as-deposited Ag contacts. It is further presented that the multi-quantum well light emitting diodes made with the Zn-Ni nanoparticles/Ag contacts show similar output power compared to those fabricated with the Ag contact layers.

Flip-chip integrated silicon Mach-Zehnder modulator with a 28nm fully depleted silicon-on-insulator CMOS driver.

PubMed

Yong, Zheng; Shopov, Stefan; Mikkelsen, Jared C; Mallard, Robert; Mak, Jason C C; Voinigescu, Sorin P; Poon, Joyce K S

2017-03-20

We present a silicon electro-optic transmitter consisting of a 28nm ultra-thin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) CMOS driver flip-chip integrated onto a Mach-Zehnder modulator. The Mach-Zehnder silicon optical modulator was optimized to have a 3dB bandwidth of around 25 GHz at -1V bias and a 50 Ω impedance. The UTBB FD-SOI CMOS driver provided a large output voltage swing around 5 V_pp to enable a high dynamic extinction ratio and a low device insertion loss. At 44 Gbps, the transmitter achieved a high extinction ratio of 6.4 dB at the modulator quadrature operation point. This result shows open eye diagrams at the highest bit rates and with the largest extinction ratios for silicon electro-optic transmitter using a CMOS driver.

Effect of current crowding on whisker growth at the anode in flip chip solder joints

NASA Astrophysics Data System (ADS)

Ouyang, Fan-Yi; Chen, Kai; Tu, K. N.; Lai, Yi-Shao

2007-12-01

Owing to the line-to-bump configuration in flip chip solder joints, current crowding occurs when electrons enter into or exit from the solder bump. At the cathode contact, where electrons enter into the bump, current crowding induced pancake-type void formation has now been observed widely. At the anode contact, where electrons exit from the bump, we report here that whisker is formed. Results of both eutectic SnPb and SnAgCu solder joints are presented and compared. The cross-sectioned surface in SnPb showed dimple and bulge after electromigration, while that of SnAgCu remained flat. The difference is due to a larger back stress in the SnAgCu, consequently, electromigration in SnAgCu is slower than that in SnPb. Nanoindentation markers were used to measure the combined atomic fluxes of back stress and electromigration.

Microcircuit Device Reliability Digital Detailed Data

DTIC Science & Technology

1976-01-01

TYPE s No. FUNCTION A LASS PINS TEMP. TYPE CLASS LEVEL I eFAILED 8 NO. CHIP TEST APPL. TEST PAR1 t T AGATES PROTECT. DATE E:V. D TYPE HOURST :708 FLIP...LEVEL # EFAILED s a NO. t CHIP i TEST 3 APPL. a TEST I PAR! 3 a GATES s PROTECT. a DATE 3 ENV. t TYPE I 3 -OUHb s 354H0( 3 GATE C-I CDIP 14 150C :11.A

Influence of the container on the consumption of cosmetic products.

PubMed

Gomez-Berrada, M P; Ficheux, A S; Galonnier, M; Rolfo, J E; Rielland, A; Guillou, S; De Javel, D; Roudot, A C; Ferret, P J

2017-11-01

The container, also known as primary package or inner package, could be defined as the packaging designed to come into direct contact with the cosmetic product. To author's knowledge, no study was available regarding the effect of the primary package on the consumption of cosmetic products. The aim of the study was to assess the impact of the container on the consumption of three cosmetic products widely used, i.e. shampoo, shower gel and emollient cream. The three products were contained in a tube with a flip top cap and in a bottle with a pump. The study was conducted on 221 French adults: 108 women and 113 men. Results showed that the consumption of each cosmetic product was slightly higher when the product was packaged in tube with a flip top cap than in bottle with a pump. The difference of consumption could vary from 5 % to 23 % when calculated with mean values. This information could be interesting for safety evaluators, safety agencies and commercial services of cosmetic manufacturers. Copyright © 2017 Elsevier Ltd. All rights reserved.

Integrated packaging of 2D MOEMS mirrors with optical position feedback

NASA Astrophysics Data System (ADS)

Baumgart, M.; Lenzhofer, M.; Kremer, M. P.; Tortschanoff, A.

2015-02-01

Many applications of MOEMS microscanners rely on accurate position feedback. For MOEMS devices which do not have intrinsic on-chip feedback, position information can be provided with optical methods, most simply by using a reflection from the backside of a MOEMS scanner. By measuring the intensity distribution of the reflected beam across a quadrant diode, one can precisely detect the mirror's deflection angles. Previously, we have presented a position sensing device, applicable to arbitrary trajectories, which is based on the measurement of the position of the reflected laser beam with a quadrant diode. In this work, we present a novel setup, which comprises the optical position feedback functionality integrated into the device package itself. The new device's System-in-Package (SiP) design is based on a flip-folded 2.5D PCB layout and fully assembled as small as 9.2×7×4 mm³ in total. The device consists of four layers, which supply the MOEMS mirror, a spacer to provide the required optical path length, the quadrant photo-diode and a laser diode to serve as the light source. In addition to describing the mechanical setup of the novel device, we will present first experimental results and optical simulation studies. Accurate position feedback is the basis for closed-loop control of the MOEMS devices, which is crucial for some applications as image projection for example. Position feedback and the possibility of closed-loop control will significantly improve the performance of these devices.

Thermal management of LEDs: package to system

NASA Astrophysics Data System (ADS)

Arik, Mehmet; Becker, Charles A.; Weaver, Stanton E.; Petroski, James

2004-01-01

Light emitting diodes, LEDs, historically have been used for indicators and produced low amounts of heat. The introduction of high brightness LEDs with white light and monochromatic colors have led to a movement towards general illumination. The increased electrical currents used to drive the LEDs have focused more attention on the thermal paths in the developments of LED power packaging. The luminous efficiency of LEDs is soon expected to reach over 80 lumens/W, this is approximately 6 times the efficiency of a conventional incandescent tungsten bulb. Thermal management for the solid-state lighting applications is a key design parameter for both package and system level. Package and system level thermal management is discussed in separate sections. Effect of chip packages on junction to board thermal resistance was compared for both SiC and Sapphire chips. The higher thermal conductivity of the SiC chip provided about 2 times better thermal performance than the latter, while the under-filled Sapphire chip package can only catch the SiC chip performance. Later, system level thermal management was studied based on established numerical models for a conceptual solid-state lighting system. A conceptual LED illumination system was chosen and CFD models were created to determine the availability and limitations of passive air-cooling.

Demonstration of glass-based photonic interposer for mid-board-optical engines and electrical-optical circuit board (EOCB) integration strategy

NASA Astrophysics Data System (ADS)

Schröder, H.; Neitz, M.; Schneider-Ramelow, M.

2018-02-01

Due to its optical transparency and superior dielectric properties glass is regarded as a promising candidate for advanced applications as active photonic interposer for mid-board-optics and optical PCB waveguide integration. The concepts for multi-mode and single-mode photonic system integration are discussed and related demonstration project results will be presented. A hybrid integrated photonic glass body interposer with integrated optical lenses for multi-mode data communication wavelength of 850 nm have been realized. The paper summarizes process developments which allow cost efficient metallization of TGV. Electro-optical elements like photodiodes and VCSELs can be directly flip-chip mounted on the glass substrate according to the desired lens positions. Furthermore results for a silicon photonic based single-mode active interposer integration onto a single mode glass made EOCB will be compared in terms of packaging challenges. The board level integration strategy for both of these technological approaches and general next generation board level integration concepts for photonic interposer will be introductorily discussed.

An implantable integrated low-power amplifier-microelectrode array for Brain-Machine Interfaces.

PubMed

Patrick, Erin; Sankar, Viswanath; Rowe, William; Sanchez, Justin C; Nishida, Toshikazu

2010-01-01

One of the important challenges in designing Brain-Machine Interfaces (BMI) is to build implantable systems that have the ability to reliably process the activity of large ensembles of cortical neurons. In this paper, we report the design, fabrication, and testing of a polyimide-based microelectrode array integrated with a low-power amplifier as part of the Florida Wireless Integrated Recording Electrode (FWIRE) project at the University of Florida developing a fully implantable neural recording system for BMI applications. The electrode array was fabricated using planar micromachining MEMS processes and hybrid packaged with the amplifier die using a flip-chip bonding technique. The system was tested both on bench and in-vivo. Acute and chronic neural recordings were obtained from a rodent for a period of 42 days. The electrode-amplifier performance was analyzed over the chronic recording period with the observation of a noise floor of 4.5 microVrms, and an average signal-to-noise ratio of 3.8.

An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging.

PubMed

Wygant, Ira O; Jamal, Nafis S; Lee, Hyunjoo J; Nikoozadeh, Amin; Oralkan, Omer; Karaman, Mustafa; Khuri-Yakub, Butrus T

2009-10-01

State-of-the-art 3-D medical ultrasound imaging requires transmitting and receiving ultrasound using a 2-D array of ultrasound transducers with hundreds or thousands of elements. A tight combination of the transducer array with integrated circuitry eliminates bulky cables connecting the elements of the transducer array to a separate system of electronics. Furthermore, preamplifiers located close to the array can lead to improved receive sensitivity. A combined IC and transducer array can lead to a portable, high-performance, and inexpensive 3-D ultrasound imaging system. This paper presents an IC flip-chip bonded to a 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array for 3-D ultrasound imaging. The IC includes a transmit beamformer that generates 25-V unipolar pulses with programmable focusing delays to 224 of the 256 transducer elements. One-shot circuits allow adjustment of the pulse widths for different ultrasound transducer center frequencies. For receiving reflected ultrasound signals, the IC uses the 32-elements along the array diagonals. The IC provides each receiving element with a low-noise 25-MHz-bandwidth transimpedance amplifier. Using a field-programmable gate array (FPGA) clocked at 100 MHz to operate the IC, the IC generated properly timed transmit pulses with 5-ns accuracy. With the IC flip-chip bonded to a CMUT array, we show that the IC can produce steered and focused ultrasound beams. We present 2-D and 3-D images of a wire phantom and 2-D orthogonal cross-sectional images (Bscans) of a latex heart phantom.

Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Neudeck, Philip G.; Behelm, Glenn M.; Spry, David J.; Meredith, Roger D.; Hunter, Gary W.

2015-01-01

This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

Towards co-packaging of photonics and microelectronics in existing manufacturing facilities

NASA Astrophysics Data System (ADS)

Janta-Polczynski, Alexander; Cyr, Elaine; Bougie, Jerome; Drouin, Alain; Langlois, Richard; Childers, Darrell; Takenobu, Shotaro; Taira, Yoichi; Lichoulas, Ted W.; Kamlapurkar, Swetha; Engelmann, Sebastian; Fortier, Paul; Boyer, Nicolas; Barwicz, Tymon

2018-02-01

The impact of integrated photonics on optical interconnects is currently muted by challenges in photonic packaging and in the dense integration of photonic modules with microelectronic components on printed circuit boards. Single mode optics requires tight alignment tolerance for optical coupling and maintaining this alignment in a cost-efficient package can be challenging during thermal excursions arising from downstream microelectronic assembly processes. In addition, the form factor of typical fiber connectors is incompatible with the dense module integration expected on printed circuit boards. We have implemented novel approaches to interfacing photonic chips to standard optical fibers. These leverage standard high throughput microelectronic assembly tooling and self-alignment techniques resulting in photonic packaging that is scalable in manufacturing volume and in the number of optical IOs per chip. In addition, using dense optical fiber connectors with space-efficient latching of fiber patch cables results in compact module size and efficient board integration, bringing the optics closer to the logic chip to alleviate bandwidth bottlenecks. This packaging direction is also well suited for embedding optics in multi-chip modules, including both photonic and microelectronic chips. We discuss the challenges and rewards in this type of configuration such as thermal management and signal integrity.

C-MOS array design techniques

NASA Technical Reports Server (NTRS)

Feller, A.

1978-01-01

The entire complement of standard cells and components, except for the set-reset flip-flop, was completed. Two levels of checking were performed on each device. Logic cells and topological layout are described. All the related computer programs were coded and one level of debugging was completed. The logic for the test chip was modified and updated. This test chip served as the first test vehicle to exercise the standard cell complementary MOS(C-MOS) automatic artwork generation capability.

Packaging Technologies for High Temperature Electronics and Sensors

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Spry, David J.; Meredith, Roger D.

2013-01-01

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500 C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550 C. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500 C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500 C are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Package Holds Five Monolithic Microwave Integrated Circuits

NASA Technical Reports Server (NTRS)

Mysoor, Narayan R.; Decker, D. Richard; Olson, Hilding M.

1996-01-01

Packages protect and hold monolithic microwave integrated circuit (MMIC) chips while providing dc and radio-frequency (RF) electrical connections for chips undergoing development. Required to be compact, lightweight, and rugged. Designed to minimize undesired resonances, reflections, losses, and impedance mismatches.

Dry-film polymer waveguide for silicon photonics chip packaging.

PubMed

Hsu, Hsiang-Han; Nakagawa, Shigeru

2014-09-22

Polymer waveguide made by dry film process is demonstrated for silicon photonics chip packaging. With 8 μm × 11.5 μm core waveguide, little penalty is observed up to 25 Gbps before or after the light propagate through a 10-km long single-mode fiber (SMF). Coupling loss to SMF is 0.24 dB and 1.31 dB at the polymer waveguide input and output ends, respectively. Alignment tolerance for 0.5 dB loss increase is +/- 1.0 μm along both vertical and horizontal directions for the coupling from the polymer waveguide to SMF. The dry-film polymer waveguide demonstrates promising performance for silicon photonics chip packaging used in next generation optical multi-chip module.

Microfabricated Electrical Connector for Atomic Force Microscopy Probes with Integrated Sensor/Actuator

NASA Astrophysics Data System (ADS)

Akiyama, Terunobu; Staufer, Urs; Rooij, Nico F. de

2002-06-01

A microfabricated, electrical connector is proposed for facilitating the mounting of atomic force microscopy (AFM) probes, which have an integrated sensor and/or actuator. Only a base chip, which acts as a socket, is permanently fixed onto a printed circuit board and electronically connected by standard wire bonding. The AFM chip, the “plug”, is flipped onto the base chip and pressed from the backside by a spring. Electrical contact with the eventual stress sensors, capacitive or piezoelectric sensor/actuators, is provided by contact bumps. These bumps of about 8 μm height are placed onto the base chip. They touch the pads on the AFM chip that were originally foreseen to be for wire bonding and thus provide the electrical contact. This connector schema was successfully used to register AFM images with piezoresistive cantilevers.

Surface and buried interfacial structures of epoxy resins used as underfills studied by sum frequency generation vibrational spectroscopy.

PubMed

Vázquez, Anne V; Holden, Brad; Kristalyn, Cornelius; Fuller, Mike; Wilkerson, Brett; Chen, Zhan

2011-05-01

Flip chip technology has greatly improved the performance of semiconductor devices, but relies heavily on the performance of epoxy underfill adhesives. Because epoxy underfills are cured in situ in flip chip semiconductor devices, understanding their surface and interfacial structures is critical for understanding their adhesion to various substrates. Here, sum frequency generation (SFG) vibrational spectroscopy was used to study surface and buried interfacial structures of two model epoxy resins used as underfills in flip chip devices, bisphenol A digylcidyl ether (BADGE) and 1,4-butanediol diglycidyl ether (BDDGE). The surface structures of these epoxies were compared before and after cure, and the orientations of their surface functional groups were deduced to understand how surface structural changes during cure may affect adhesion properties. Further, the effect of moisture exposure, a known cause of adhesion failure, on surface structures was studied. It was found that the BADGE surface significantly restructured upon moisture exposure while the BDDGE surface did not, showing that BADGE adhesives may be more prone to moisture-induced delamination. Lastly, although surface structure can give some insight into adhesion, buried interfacial structures more directly correspond to adhesion properties of polymers. SFG was used to study buried interfaces between deuterated polystyrene (d-PS) and the epoxies before and after moisture exposure. It was shown that moisture exposure acted to disorder the buried interfaces, most likely due to swelling. These results correlated with lap shear adhesion testing showing a decrease in adhesion strength after moisture exposure. The presented work showed that surface and interfacial structures can be correlated to adhesive strength and may be helpful in understanding and designing optimized epoxy underfill adhesives.

Thermal cycling test results of CSP and RF assemblies

NASA Technical Reports Server (NTRS)

Ghaffarian, R.; Nelson, G.; Cooper, M.; Lam, D.; Strudler, S.; Umdekar, A.; Selk, K.; Bjorndahl, B.; Duprey, R.

2000-01-01

A JPL-led chip scale package (CSP) Consortium of enterprises, composed of representing agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.

A Robust Strategy for Total Ionizing Dose Testing of Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Wilcox, Edward; Berg, Melanie; Friendlich, Mark; Lakeman, Joseph; KIm, Hak; Pellish, Jonathan; LaBel, Kenneth

2012-01-01

We present a novel method of FPGA TID testing that measures propagation delay between flip-flops operating at maximum speed. Measurement is performed on-chip at-speed and provides a key design metric when building system-critical synchronous designs.

Numerical analysis of light extraction enhancement of GaN-based thin-film flip-chip light-emitting diodes with high-refractive-index buckling nanostructures

NASA Astrophysics Data System (ADS)

Yue, Qing-Yang; Yang, Yang; Cheng, Zhen-Jia; Guo, Cheng-Shan

2018-06-01

In this work, the light extraction efficiency enhancement of GaN-based thin-film flip-chip (TFFC) light-emitting diodes (LEDs) with high-refractive-index (TiO2) buckling nanostructures was studied using the three-dimensional finite difference time domain method. Compared with 2-D photonic crystals, the buckling structures have the advantages of a random directionality and a broad distribution in periodicity, which can effectively extract the guided light propagating in all azimuthal directions over a wide spectrum. Numerical studies revealed that the light extraction efficiency of buckling-structured LEDs reaches 1.1 times that of triangular lattice photonic crystals. The effects of the buckling structure feature sizes and the thickness of the N-GaN layer on the light extraction efficiency for TFFC LEDs were also investigated systematically. With optimized structural parameters, a significant light extraction enhancement of about 2.6 times was achieved for TiO2 buckling-structured TFFC LEDs compared with planar LEDs.

MEMS packaging: state of the art and future trends

NASA Astrophysics Data System (ADS)

Bossche, Andre; Cotofana, Carmen V. B.; Mollinger, Jeff R.

1998-07-01

Now that the technology for Integrated sensor and MEMS devices has become sufficiently mature to allow mass production, it is expected that the prices of bare chips will drop dramatically. This means that the package prices will become a limiting factor in market penetration, unless low cost packaging solutions become available. This paper will discuss the developments in packaging technology. Both single-chip and multi-chip packaging solutions will be addressed. It first starts with a discussion on the different requirements that have to be met; both from a device point of view (open access paths to the environment, vacuum cavities, etc.) and from the application point of view (e.g. environmental hostility). Subsequently current technologies are judged on their applicability for MEMS and sensor packaging and a forecast is given for future trends. It is expected that the large majority of sensing devices will be applied in relative friendly environments for which plastic packages would suffice. Therefore, on the short term an important role is foreseen for recently developed plastic packaging techniques such as precision molding and precision dispensing. Just like in standard electronic packaging, complete wafer level packaging methods for sensing devices still have a long way to go before they can compete with the highly optimized and automated plastic packaging processes.

Leadless Chip Carrier Packaging and CAD/CAM-Supported Wire Wrap Interconnect Technology for Subnanosecond ECL.

DTIC Science & Technology

1981-11-01

Showing Wire . 99 Impregnanted Silicone Rubber Contacts, Chip Carrier, ard Lid 35. Technit Connector For 68-Pad JEDEC Type A Leadless . . 100 Chip Carrier...Points of Various . . . . 124 Solders 4. Composition of Alloys Employed in Dual-In-Line . . . . 128 Package Pins and Plating by Mass Spectrographic...swings, and subnanosecond gate delays and risetimes. Presently, emitter coupled logic (ECL) and current mode logic (CML), both fabricated with silicon tech

Design considerations for FET-gated power transistors

NASA Technical Reports Server (NTRS)

Chen, D. Y.; Chin, S. A.

1983-01-01

An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.

3-D readout-electronics packaging for high-bandwidth massively paralleled imager

DOEpatents

Kwiatkowski, Kris; Lyke, James

2007-12-18

Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a "mirror cube"). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a 45.degree. angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.

Optomechanical Design and Characterization of a Printed-Circuit-Board-Based Free-Space Optical Interconnect Package

NASA Astrophysics Data System (ADS)

Zheng, Xuezhe; Marchand, Philippe J.; Huang, Dawei; Kibar, Osman; Ozkan, Nur S. E.; Esener, Sadik C.

1999-09-01

We present a proof of concept and a feasibility demonstration of a practical packaging approach in which free-space optical interconnects (FSOI s) can be integrated simply on electronic multichip modules (MCM s) for intra-MCM board interconnects. Our system-level packaging architecture is based on a modified folded 4 f imaging system that has been implemented with only off-the-shelf optics, conventional electronic packaging, and passive-assembly techniques to yield a potentially low-cost and manufacturable packaging solution. The prototypical system as built supports 48 independent FSOI channels with 8 separate laser and detector chips, for which each chip consists of a one-dimensional array of 12 devices. All the chips are assembled on a single substrate that consists of a printed circuit board or a ceramic MCM. Optical link channel efficiencies of greater than 90% and interchannel cross talk of less than 20 dB at low frequency have been measured. The system is compact at only 10 in. 3 (25.4 cm 3 ) and is scalable, as it can easily accommodate additional chips as well as two-dimensional optoelectronic device arrays for increased interconnection density.

Effects of Solder Volume and Reflow Conditions on Self-Alignment Accuracy for Fan-Out Package Applications

NASA Astrophysics Data System (ADS)

Park, Hwan-Pil; Seo, Gwancheol; Kim, Sungchul; Kim, Young-Ho

2018-01-01

The effects of solder volume and reaction time between molten solder and a metal pad at the peak temperature of reflow on the self-alignment effect have been investigated in flip chip bonding. A glass die with two different pad designs and a flame retardant-4 (FR-4) organic substrate were used. Sn-3.0Ag-0.5Cu and Sn-3.5Ag solders were formed on Cu-organic solderability preservation (Cu-OSP) and electroless nickel electroless palladium immersion gold (ENEPIG) pads on FR-4 substrates using the stencil printing method. To assess the effect of solder volume, the thickness and opening size of the stencil mask were controlled. Reflow experiments were performed at 250°C with wetting times of 40 s, 55 s, 65 s, and 75 s. After flip chip reflow soldering, the bonding areas were cross-sectioned to inspect the shape of the interconnected solder using scanning electron microscopy. The results revealed that using an insufficient solder volume on the pad was responsible for die shifts larger than 1 μm, while a sufficient solder volume on the pad and a stable solder joint shape could ensure misalignment less than 1 μm. The Sn-3.0Ag-0.5Cu solder showed a lower die shift value than the Sn-3.5Ag solder because the Sn-3.0Ag-0.5Cu solder has stronger surface tension than the Sn-3.5Ag solder. Using a longer wetting time between the solder and the pad at the peak temperature also improved the die shift value because the increased reaction time changed the interconnected solder shape between the die and substrate from concave to convex, moving the die to a more accurate position. Furthermore, the restoring forces on die self-alignment influenced the die shift value. A stronger solder surface tension and a larger volume of solder on the pad produced stronger restoring forces for die self-alignment, thereby improving the die shift value.

Assembly reliability of CSPs with various chiip sizes by accelerated thermal and mechanical cycling test

NASA Technical Reports Server (NTRS)

Ghaffarian, R.

2000-01-01

A JPL-led chip scale package (CSP) Consortium, composed of team members representing government agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.

The Chip-Scale Atomic Clock - Low-Power Physics Package

DTIC Science & Technology

2004-12-01

36th Annual Precise Time and Time Interval (PTTI) Meeting 339 THE CHIP-SCALE ATOMIC CLOCK – LOW-POWER PHYSICS PACKAGE R. Lutwak ...pdf/documents/ds-x72.pdf [2] R. Lutwak , D. Emmons, W. Riley, and R. M. Garvey, 2003, “The Chip-Scale Atomic Clock – Coherent Population Trapping vs...2002, Reston, Virginia, USA (U.S. Naval Observatory, Washington, D.C.), pp. 539-550. [3] R. Lutwak , D. Emmons, T. English, and W. Riley, 2004

Recent advances in the science and technology for solid state lighting

NASA Astrophysics Data System (ADS)

Munkholm, Anneli

2003-03-01

Recent development of high power light emitting diodes (LEDs) has enabled fabrication of solid state devices with efficiencies that surpass that of incandescent light, as well as providing a total light output significantly exceeding that of conventional indicator LEDs. This breakthrough in high flux is opening up new applications for use of high power LEDs, such as liquid crystal display backlighting and automotive headlights. Some of the key elements to this technological breakthrough are the flip-chip device design, power packaging and phosphor coating technology, which will be discussed. In addition to device design improvements, our fundamental knowledge of the III-nitride material system is improving and has resulted in higher internal quantum efficiencies. Strain plays a significant role in complex AlInGaN heterostructures used in current devices. Using a multi-beam optical strain sensor (MOSS) system to measure the wafer curvature in situ, we have characterized the strain during metal-organic chemical vapor deposition of III-nitrides. Strain measurements of InGaN, AlGaN and Si-doped GaN films on GaN will be presented.

Design, fabrication and actuation of a MEMS-based image stabilizer for photographic cell phone applications

NASA Astrophysics Data System (ADS)

Chiou, Jin-Chern; Hung, Chen-Chun; Lin, Chun-Ying

2010-07-01

This work presents a MEMS-based image stabilizer applied for anti-shaking function in photographic cell phones. The proposed stabilizer is designed as a two-axis decoupling XY stage 1.4 × 1.4 × 0.1 mm3 in size, and adequately strong to suspend an image sensor for anti-shaking photographic function. This stabilizer is fabricated by complex fabrication processes, including inductively coupled plasma (ICP) processes and flip-chip bonding technique. Based on the special designs of a hollow handle layer and a corresponding wire-bonding assisted holder, electrical signals of the suspended image sensor can be successfully sent out with 32 signal springs without incurring damage during wire-bonding packaging. The longest calculated traveling distance of the stabilizer is 25 µm which is sufficient to resolve the anti-shaking problem in a three-megapixel image sensor. Accordingly, the applied voltage for the 25 µm moving distance is 38 V. Moreover, the resonant frequency of the actuating device with the image sensor is 1.123 kHz.

RGB-Stack Light Emitting Diode Modules with Transparent Glass Circuit Board and Oil Encapsulation

PubMed Central

Li, Ying-Chang; Chang, Yuan-Hsiao; Singh, Preetpal; Chang, Liann-Be; Yeh, Der-Hwa; Chao, Ting-Yu; Jian, Si-Yun; Li, Yu-Chi; Lai, Chao-Sung; Ying, Shang-Ping

2018-01-01

The light emitting diode (LED) is widely used in modern solid-state lighting applications, and its output efficiency is closely related to the submounts’ material properties. Most submounts used today, such as low-power printed circuit boards (PCBs) or high-power metal core printed circuit boards (MCPCBs), are not transparent and seriously decrease the output light extraction. To meet the requirements of high light output and better color mixing, a three-dimensional (3-D) stacked flip-chip (FC) LED module is proposed and demonstrated. To realize light penetration and mixing, the mentioned 3-D vertically stacking RGB LEDs use transparent glass as FC package submounts called glass circuit boards (GCB). Light emitted from each GCB stacked LEDs passes through each other and thus exhibits good output efficiency and homogeneous light-mixing characteristics. In this work, the parasitic problem of heat accumulation, which caused by the poor thermal conductivity of GCB and leads to a serious decrease in output efficiency, is solved by a proposed transparent cooling oil encapsulation (OCP) method. PMID:29494534

K-Band Phased Array Developed for Low- Earth-Orbit Satellite Communications

NASA Technical Reports Server (NTRS)

Anzic, Godfrey

1999-01-01

Future rapid deployment of low- and medium-Earth-orbit satellite constellations that will offer various narrow- to wide-band wireless communications services will require phased-array antennas that feature wide-angle and superagile electronic steering of one or more antenna beams. Antennas, which employ monolithic microwave integrated circuits (MMIC), are perfectly suited for this application. Under a cooperative agreement, an MMIC-based, K-band phased-array antenna is being developed with 50/50 cost sharing by the NASA Lewis Research Center and Raytheon Systems Company. The transmitting array, which will operate at 19 gigahertz (GHz), is a state-of-the-art design that features dual, independent, electronically steerable beam operation ( 42 ), a stand-alone thermal management, and a high-density tile architecture. This array can transmit 622 megabits per second (Mbps) in each beam from Earth orbit to small Earth terminals. The weight of the total array package is expected to be less than 8 lb. The tile integration technology (flip chip MMIC tile) chosen for this project represents a major advancement in phased-array engineering and holds much promise for reducing manufacturing costs.

Impact of Data Transmission over 10 Gbps on High-Density and Low-Cost Optoelectronic Module with Polynorbornene Waveguides

NASA Astrophysics Data System (ADS)

Ito, Yuka; Terada, Shinsuke; Arai, Shinya; Fujiwara, Makoto; Mori, Tetsuya; Choki, Koji; Fukushima, Takafumi; Koyanagi, Mitsumasa

2012-04-01

We proposed a rigid/flex optoelectronic (O/E) module with 48-channel polymeric waveguides for short-distance board-level optical interconnection. A flexible O/E test module was fabricated in the following two steps by using standard packaging processes. First, two vertical cavity surface emitting laser diodes (VCSELs) and one VCSEL driver (VD) were flip-chip bonded to a completed flexible printed circuit board (PCB), and two photodiodes (PDs) and one transimpedance amplifier/limiting amplifier (TIA/LA) to another flexible PCB. Second, the two flexible PCBs were attached with a polynorbornene (PNB) sheet in which high-density PNB waveguides were formed by UV exposure. Active areas of VCSELs and PDs on the flexible PCBs were aligned to micromirrors of the waveguides with -6 µm offset toward the signal propagation direction. We successfully demonstrated data transmission over 10 Gbps and low inter-channel crosstalk of less than -20 dB was achieved in the flexible O/E test module with 120-mm-long and 62.5-µm-pitch waveguides.

RGB-Stack Light Emitting Diode Modules with Transparent Glass Circuit Board and Oil Encapsulation.

PubMed

Li, Ying-Chang; Chang, Yuan-Hsiao; Singh, Preetpal; Chang, Liann-Be; Yeh, Der-Hwa; Chao, Ting-Yu; Jian, Si-Yun; Li, Yu-Chi; Tan, Cher Ming; Lai, Chao-Sung; Chow, Lee; Ying, Shang-Ping

2018-03-01

The light emitting diode (LED) is widely used in modern solid-state lighting applications, and its output efficiency is closely related to the submounts' material properties. Most submounts used today, such as low-power printed circuit boards (PCBs) or high-power metal core printed circuit boards (MCPCBs), are not transparent and seriously decrease the output light extraction. To meet the requirements of high light output and better color mixing, a three-dimensional (3-D) stacked flip-chip (FC) LED module is proposed and demonstrated. To realize light penetration and mixing, the mentioned 3-D vertically stacking RGB LEDs use transparent glass as FC package submounts called glass circuit boards (GCB). Light emitted from each GCB stacked LEDs passes through each other and thus exhibits good output efficiency and homogeneous light-mixing characteristics. In this work, the parasitic problem of heat accumulation, which caused by the poor thermal conductivity of GCB and leads to a serious decrease in output efficiency, is solved by a proposed transparent cooling oil encapsulation (OCP) method.

Silicon Carbide Integrated Circuit Chip

NASA Image and Video Library

2015-02-17

A multilevel interconnect silicon carbide integrated circuit chip with co-fired ceramic package and circuit board recently developed at the NASA GRC Smart Sensors and Electronics Systems Branch for high temperature applications. High temperature silicon carbide electronics and compatible packaging technologies are elements of instrumentation for aerospace engine control and long term inner-solar planet explorations.

Development of a package-free transparent disposable biosensor chip for simultaneous measurements of blood constituents and investigation of its storage stability.

PubMed

Nakamura, Hideaki; Tohyama, Kana; Tanaka, Masanori; Shinohara, Shouji; Tokunaga, Yuichi; Kurusu, Fumiyo; Koide, Satoshi; Gotoh, Masao; Karube, Isao

2007-12-15

A package-free transparent disposable biosensor chip was developed by a screen-printing technique. The biosensor chip was fabricated by stacking a substrate with two carbon electrodes on its surface, a spacer consisting of a resist layer and an adhesive layer, and a cover. The structure of the chip keeps the interior of the reaction-detecting section airtight until use. The chip is equipped with double electrochemical measuring elements for the simultaneous measurement of multiple items, and the reagent layer was developed in sample-feeding path. The sample-inlet port and air-discharge port are simultaneously opened by longitudinally folding in two biosensor units with a notch as a boundary. Then the shape of the chip is changed to a V-shape. The reaction-detecting section of the chip has a 1.0 microl sample volume for one biosensor unit. Excellent results were obtained with the chip in initial simultaneous chronoamperometric measurements of both glucose (r=1.00) and lactate (r=0.998) in the same samples. The stability of the enzyme sensor signals of the chip was estimated at ambient atmosphere on 8 testing days during a 6-month period. The results were compared with those obtained for an unpackaged chip used as a control. The package-free chip proved to be twice as good as the control chip in terms of the reproducibility of slopes from 16 calibration curves (one calibration curve: 0, 100, 300, 500 mg dl(-1) glucose; n=3) and 4.6 times better in terms of the reproducibility of correlation coefficients from the 16 calibration curves.

Fluxless flip-chip bonding using a lead-free solder bumping technique

NASA Astrophysics Data System (ADS)

Hansen, K.; Kousar, S.; Pitzl, D.; Arab, S.

2017-09-01

With the LHC exceeding the nominal instantaneous luminosity, the current barrel pixel detector (BPIX) of the CMS experiment at CERN will reach its performance limits and undergo significant radiation damage. In order to improve detector performance in high luminosity conditions, the entire BPIX is replaced with an upgraded version containing an additional detection layer. Half of the modules comprising this additional layer are produced at DESY using fluxless and lead-free bumping and bonding techniques. Sequential solder-jetting technique is utilized to wet 40-μm SAC305 solder spheres on the silicon-sensor pads with electroless Ni, Pd and immersion Au (ENEPIG) under-bump metallization (UBM). The bumped sensors are flip-chip assembled with readout chips (ROCs) and then reflowed using a flux-less bonding facility. The challenges for jetting low solder volume have been analyzed and will be presented in this paper. An average speed of 3.4 balls per second is obtained to jet about 67 thousand solder balls on a single chip. On average, 7 modules have been produced per week. The bump-bond quality is evaluated in terms of electrical and mechanical properties. The peak-bump resistance is about 17.5 mΩ. The cross-section study revealed different types of intermetallic compounds (IMC) as a result of interfacial reactions between UBM and solder material. The effect of crystalline phases on the mechanical properties of the joint is discussed. The mean shear strength per bump after the final module reflow is about 16 cN. The results and sources of yield loss of module production are reported. The achieved yield is 95%.

Effect of surface finish on the failure mechanisms of flip-chip solder joints under electromigration

NASA Astrophysics Data System (ADS)

Lin, Y. L.; Lai, Y. S.; Tsai, C. M.; Kao, C. R.

2006-12-01

Two substrate surface finishes, Au/Ni and organic solderable preservative (OSP), were used to study the effect of the surface finish on the reliability of flip-chip solder joints under electromigration at 150°C ambient temperature. The solder used was eutectic PbSn, and the applied current density was 5×103 A/cm2 at the contact window of the chip. The under bump metallurgy (UBM) on the chip was sputtered Cu/Ni. It was found that the mean-time-to-failure (MTTF) of the OSP joints was six times better than that of the Au/Ni joints (3080 h vs. 500 h). Microstructure examinations uncovered that the combined effect of current crowding and the accompanying local Joule heating accelerated the local Ni UBM consumption near the point of electron entrance. Once Ni was depleted at a certain region, this region became nonconductive, and the flow of the electrons was diverted to the neighboring region. This neighboring region then became the place where electrons entered the joint, and the local Ni UBM consumption was accelerated. This process repeated itself, and the Ni-depleted region extended further on, creating an ever-larger nonconductive region. The solder joint eventually, failed when the nonconductive region became too large, making the effective current density very high. Accordingly, the key factor determining the MTTF was the Ni consumption rate. The joints with the OSP surface finish had a longer MTTF because Cu released from the substrate was able to reduce the Ni consumption rate.

Two-Step Plasma Process for Cleaning Indium Bonding Bumps

NASA Technical Reports Server (NTRS)

Greer, Harold F.; Vasquez, Richard P.; Jones, Todd J.; Hoenk, Michael E.; Dickie, Matthew R.; Nikzad, Shouleh

2009-01-01

A two-step plasma process has been developed as a means of removing surface oxide layers from indium bumps used in flip-chip hybridization (bump bonding) of integrated circuits. The two-step plasma process makes it possible to remove surface indium oxide, without incurring the adverse effects of the acid etching process.

High-Modulation-Speed LEDs Based on III-Nitride

NASA Astrophysics Data System (ADS)

Chen, Hong

III-nitride InGaN light-emitting diodes (LEDs) enable wide range of applications in solid-state lighting, full-color displays, and high-speed visible-light communication. Conventional InGaN quantum well LEDs grown on polar c-plane substrate suffer from quantum confined Stark effect due to the large internal polarization-related fields, leading to a reduced radiative recombination rate and device efficiency, which limits the performance of InGaN LEDs in high-speed communication applications. To circumvent these negative effects, non-trivial-cavity designs such as flip-chip LEDs, metallic grating coated LEDs are proposed. This oral defense will show the works on the high-modulation-speed LEDs from basic ideas to applications. Fundamental principles such as rate equations for LEDs/laser diodes (LDs), plasmonic effects, Purcell effects will be briefly introduced. For applications, the modal properties of flip-chip LEDs are solved by implementing finite difference method in order to study the modulation response. The emission properties of highly polarized InGaN LEDs coated by metallic gratings are also investigated by finite difference time domain method.

Neighbour-die effect on the measurement of wafer-level flip-chip LED dies in production lines

NASA Astrophysics Data System (ADS)

Chen, Tengfei; Wan, Zirui; Li, Bin

2017-11-01

The light from the side surfaces of the test flip-chip light-emitting diode (FCLED) dies is reflected, refracted or absorbed by neighbour dies during the measurement of wafer-level FCLED dies in production lines. A notable measurement deviation is caused by the neighbour-die effect, which is not considered in current industry practice. In this paper, Monte Carlo ray-tracing simulations are used to study the measurement deviations caused by the neighbour-die effect and extension ratios of the film. The simulation results show that the maximal deviation of radiant flux impinging the photodiode can reach 5.5%, if the die is tested without any neighbour dies, or is surrounded by a set of neighbour dies at an extension ratio of 1.1. Moreover, the dependence between the measurement results and neighbour cases for different extension ratios is also investigated. Then, a modified calibration method is proposed and studied. The proposed technique can be used to improve the calibration and measurement accuracy of the test equipment used for measurement of wafer-level FCLED dies in production lines.

ChIPpeakAnno: a Bioconductor package to annotate ChIP-seq and ChIP-chip data

PubMed Central

2010-01-01

Background Chromatin immunoprecipitation (ChIP) followed by high-throughput sequencing (ChIP-seq) or ChIP followed by genome tiling array analysis (ChIP-chip) have become standard technologies for genome-wide identification of DNA-binding protein target sites. A number of algorithms have been developed in parallel that allow identification of binding sites from ChIP-seq or ChIP-chip datasets and subsequent visualization in the University of California Santa Cruz (UCSC) Genome Browser as custom annotation tracks. However, summarizing these tracks can be a daunting task, particularly if there are a large number of binding sites or the binding sites are distributed widely across the genome. Results We have developed ChIPpeakAnno as a Bioconductor package within the statistical programming environment R to facilitate batch annotation of enriched peaks identified from ChIP-seq, ChIP-chip, cap analysis of gene expression (CAGE) or any experiments resulting in a large number of enriched genomic regions. The binding sites annotated with ChIPpeakAnno can be viewed easily as a table, a pie chart or plotted in histogram form, i.e., the distribution of distances to the nearest genes for each set of peaks. In addition, we have implemented functionalities for determining the significance of overlap between replicates or binding sites among transcription factors within a complex, and for drawing Venn diagrams to visualize the extent of the overlap between replicates. Furthermore, the package includes functionalities to retrieve sequences flanking putative binding sites for PCR amplification, cloning, or motif discovery, and to identify Gene Ontology (GO) terms associated with adjacent genes. Conclusions ChIPpeakAnno enables batch annotation of the binding sites identified from ChIP-seq, ChIP-chip, CAGE or any technology that results in a large number of enriched genomic regions within the statistical programming environment R. Allowing users to pass their own annotation data such as a different Chromatin immunoprecipitation (ChIP) preparation and a dataset from literature, or existing annotation packages, such as GenomicFeatures and BSgenome, provides flexibility. Tight integration to the biomaRt package enables up-to-date annotation retrieval from the BioMart database. PMID:20459804

Enhanced thermaly managed packaging for III-nitride light emitters

NASA Astrophysics Data System (ADS)

Kudsieh, Nicolas

In this Dissertation our work on `enhanced thermally managed packaging of high power semiconductor light sources for solid state lighting (SSL)' is presented. The motivation of this research and development is to design thermally high stable cost-efficient packaging of single and multi-chip arrays of III-nitrides wide bandgap semiconductor light sources through mathematical modeling and simulations. Major issues linked with this technology are device overheating which causes serious degradation in their illumination intensity and decrease in the lifetime. In the introduction the basics of III-nitrides WBG semiconductor light emitters are presented along with necessary thermal management of high power cingulated and multi-chip LEDs and laser diodes. This work starts at chip level followed by its extension to fully packaged lighting modules and devices. Different III-nitride structures of multi-quantum well InGaN/GaN and AlGaN/GaN based LEDs and LDs were analyzed using advanced modeling and simulation for different packaging designs and high thermal conductivity materials. Study started with basic surface mounted devices using conventional packaging strategies and was concluded with the latest thermal management of chip-on-plate (COP) method. Newly discovered high thermal conductivity materials have also been incorporated for this work. Our study also presents the new approach of 2D heat spreaders using such materials for SSL and micro LED array packaging. Most of the work has been presented in international conferences proceedings and peer review journals. Some of the latest work has also been submitted to well reputed international journals which are currently been reviewed for publication. .

On-chip detection of non-classical light by scalable integration of single-photon detectors

PubMed Central

Najafi, Faraz; Mower, Jacob; Harris, Nicholas C.; Bellei, Francesco; Dane, Andrew; Lee, Catherine; Hu, Xiaolong; Kharel, Prashanta; Marsili, Francesco; Assefa, Solomon; Berggren, Karl K.; Englund, Dirk

2015-01-01

Photonic-integrated circuits have emerged as a scalable platform for complex quantum systems. A central goal is to integrate single-photon detectors to reduce optical losses, latency and wiring complexity associated with off-chip detectors. Superconducting nanowire single-photon detectors (SNSPDs) are particularly attractive because of high detection efficiency, sub-50-ps jitter and nanosecond-scale reset time. However, while single detectors have been incorporated into individual waveguides, the system detection efficiency of multiple SNSPDs in one photonic circuit—required for scalable quantum photonic circuits—has been limited to <0.2%. Here we introduce a micrometer-scale flip-chip process that enables scalable integration of SNSPDs on a range of photonic circuits. Ten low-jitter detectors are integrated on one circuit with 100% device yield. With an average system detection efficiency beyond 10%, and estimated on-chip detection efficiency of 14–52% for four detectors operated simultaneously, we demonstrate, to the best of our knowledge, the first on-chip photon correlation measurements of non-classical light. PMID:25575346

Electromigration and solid state aging of flip chip solder joints and analysis of tin whisker on lead-frame

NASA Astrophysics Data System (ADS)

Lee, Taekyeong

Electromigration and solid state aging in flip chip joint, and whisker on lead frame of Pb-containing (eutectic SnPb) and Pb-free solders (SnAg 3.5, SnAg3.8Cu0.7, and SnCu0.7), have been studied systematically, using Scanning Electron Microscopy (SEM), Energy Dispersive X-ray Analysis (EDX), and synchrotron radiation. The high current density in flip chip joint drives the diffusion of atoms of eutectic SnPb and SnAgCu. A marker is used to measure the diffusion flux in a half cross-sectioned solder joint. SnAgCu shows higher resistance against electromigration than eutectic SnPb. In the half cross-sectioned solder joint, void growth is the dominant failure mechanism. However, the whole solder balls in the underfill show that the failure mechanism is a result from the dissolution of electroless Ni under bump metallization (UBM) of about 10 mum thickness. The growth rate between intermetallic compounds in molten and solid solders differed by four orders of magnitude. In liquid solder, the growth rate is about 1 mum/min; the growth rate in solid solder is only about 10 -4 mum/min. The difference is not resulting from factors of thermodynamics, which is the change of Gibbs free energy before and after intermetallic compound formation, but from kinetic factors, which is the rate of change of Gibbs free energy. Even though the difference in growth rate between eutectic SnPb and Pb-free solders during solid state aging was found, the reason behind such difference shown is unclear. The orientation and stress levels of whiskers are measured by white X-ray of synchrotron radiation. The growth direction is nearly parallel to one of the principal axes of tin. The compressive stress level is quite low because the residual stress is relaxed by the whisker growth.

Backside contacted field effect transistor array for extracellular signal recording.

PubMed

Ingebrandt, S; Yeung, C K; Staab, W; Zetterer, T; Offenhäusser, A

2003-04-01

A new approach to the design of field-effect transistor (FET) sensors and the use of these FETs in detecting extracellular electrophysiological recordings is reported. Backside contacts were engineered by deep reactive ion etching and a gas phase boron doping process of the holes using planar diffusion sources. The metal contacts were designed to fit on top of the bonding pads of a standard industrial 22-pin DIL (dual inline) chip carrier. To minimise contact resistance, the metal backside contacts of the chips were electroless plated with gold. The chips were mounted on top of the bonding pads using a standard flip-chip process and a fineplacer unit previously described. Rat embryonic myocytes were cultured on these new devices (effective growth area 6 x 6 mm(2)) in order to confirm their validity in electrophysiological recording. Copyright 2003 Elsevier Science B.V.

Packaging Technologies for 500C SiC Electronics and Sensors

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu

2013-01-01

Various SiC electronics and sensors are currently under development for applications in 500C high temperature environments such as hot sections of aerospace engines and the surface of Venus. In order to conduct long-term test and eventually commercialize these SiC devices, compatible packaging technologies for the SiC electronics and sensors are required. This presentation reviews packaging technologies developed for 500C SiC electronics and sensors to address both component and subsystem level packaging needs for high temperature environments. The packaging system for high temperature SiC electronics includes ceramic chip-level packages, ceramic printed circuit boards (PCBs), and edge-connectors. High temperature durable die-attach and precious metal wire-bonding are used in the chip-level packaging process. A high temperature sensor package is specifically designed to address high temperature micro-fabricated capacitive pressure sensors for high differential pressure environments. This presentation describes development of these electronics and sensor packaging technologies, including some testing results of SiC electronics and capacitive pressure sensors using these packaging technologies.

Monolithic integration of a silica AWG and Ge photodiodes on Si photonic platform for one-chip WDM receiver.

PubMed

Nishi, Hidetaka; Tsuchizawa, Tai; Kou, Rai; Shinojima, Hiroyuki; Yamada, Takashi; Kimura, Hideaki; Ishikawa, Yasuhiko; Wada, Kazumi; Yamada, Koji

2012-04-09

On the silicon (Si) photonic platform, we monolithically integrated a silica-based arrayed-waveguide grating (AWG) and germanium (Ge) photodiodes (PDs) using low-temperature fabrication technology. We confirmed demultiplexing by the AWG, optical-electrical signal conversion by Ge PDs, and high-speed signal detection at all channels. In addition, we mounted a multichannel transimpedance amplifier/limiting amplifier (TIA/LA) circuit on the fabricated AWG-PD device using flip-chip bonding technology. The results show the promising potential of our Si photonic platform as a photonics-electronics convergence.

chipPCR: an R package to pre-process raw data of amplification curves.

PubMed

Rödiger, Stefan; Burdukiewicz, Michał; Schierack, Peter

2015-09-01

Both the quantitative real-time polymerase chain reaction (qPCR) and quantitative isothermal amplification (qIA) are standard methods for nucleic acid quantification. Numerous real-time read-out technologies have been developed. Despite the continuous interest in amplification-based techniques, there are only few tools for pre-processing of amplification data. However, a transparent tool for precise control of raw data is indispensable in several scenarios, for example, during the development of new instruments. chipPCR is an R: package for the pre-processing and quality analysis of raw data of amplification curves. The package takes advantage of R: 's S4 object model and offers an extensible environment. chipPCR contains tools for raw data exploration: normalization, baselining, imputation of missing values, a powerful wrapper for amplification curve smoothing and a function to detect the start and end of an amplification curve. The capabilities of the software are enhanced by the implementation of algorithms unavailable in R: , such as a 5-point stencil for derivative interpolation. Simulation tools, statistical tests, plots for data quality management, amplification efficiency/quantification cycle calculation, and datasets from qPCR and qIA experiments are part of the package. Core functionalities are integrated in GUIs (web-based and standalone shiny applications), thus streamlining analysis and report generation. http://cran.r-project.org/web/packages/chipPCR. Source code: https://github.com/michbur/chipPCR. stefan.roediger@b-tu.de Supplementary data are available at Bioinformatics online. © The Author 2015. Published by Oxford University Press. All rights reserved. For Permissions, please e-mail: journals.permissions@oup.com.

Packaging Technologies for High Temperature Electronics and Sensors

NASA Technical Reports Server (NTRS)

Chen, Liangyu; Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Spry, David J.; Meredith, Roger D.

2013-01-01

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

CE chips fabricated by injection molding and polyethylene/thermoplastic elastomer film packaging methods.

PubMed

Huang, Fu-Chun; Chen, Yih-Far; Lee, Gwo-Bin

2007-04-01

This study presents a new packaging method using a polyethylene/thermoplastic elastomer (PE/TPE) film to seal an injection-molded CE chip made of either poly(methyl methacrylate) (PMMA) or polycarbonate (PC) materials. The packaging is performed at atmospheric pressure and at room temperature, which is a fast, easy, and reliable bonding method to form a sealed CE chip for chemical analysis and biomedical applications. The fabrication of PMMA and PC microfluidic channels is accomplished by using an injection-molding process, which could be mass-produced for commercial applications. In addition to microfluidic CE channels, 3-D reservoirs for storing biosamples, and CE buffers are also formed during this injection-molding process. With this approach, a commercial CE chip can be of low cost and disposable. Finally, the functionality of the mass-produced CE chip is demonstrated through its successful separation of phiX174 DNA/HaeIII markers. Experimental data show that the S/N for the CE chips using the PE/TPE film has a value of 5.34, when utilizing DNA markers with a concentration of 2 ng/microL and a CE buffer of 2% hydroxypropyl-methylcellulose (HPMC) in Tris-borate-EDTA (TBE) with 1% YO-PRO-1 fluorescent dye. Thus, the detection limit of the developed chips is improved. Lastly, the developed CE chips are used for the separation and detection of PCR products. A mixture of an amplified antibiotic gene for Streptococcus pneumoniae and phiX174 DNA/HaeIII markers was successfully separated and detected by using the proposed CE chips. Experimental data show that these DNA samples were separated within 2 min. The study proposed a promising method for the development of mass-produced CE chips.

Thin glass based packaging and photonic single-mode waveguide integration by ion-exchange technology on board and module level

NASA Astrophysics Data System (ADS)

Brusberg, Lars; Lang, Günter; Schröder, Henning

2011-01-01

The proposed novel packaging approach merges micro-system packaging and glass integrated optics. It provides 3D optical single-mode intra system links to bridge the gap between novel photonic integrated circuits and the glass fibers for inter system interconnects. We introduce our hybrid 3D photonic packaging approach based on thin glass substrates with planar integrated optical single-mode waveguides for fiber-to-chip and chip-to-chip links. Optical mirrors and lenses provide optical mode matching for photonic IC assemblies and optical fiber interconnects. Thin glass is commercially available in panel and wafer formats and characterizes excellent optical and high-frequency properties as reviewed in the paper. That makes it perfect for micro-system packaging. The adopted planar waveguide process based on ion-exchange technology is capable for high-volume manufacturing. This ion-exchange process and the optical propagation are described in detail for thin glass substrates. An extensive characterization of all basic circuit elements like straight and curved waveguides, couplers and crosses proves the low attenuation of the optical circuit elements.

Development of chip passivated monolithic complementary MISFET circuits with beam leads

NASA Technical Reports Server (NTRS)

Ragonese, L. J.; Kim, M. J.; Corrie, B. L.; Brouillette, J. W.; Warr, R. E.

1972-01-01

The results are presented of a program to demonstrate the processes for fabricating complementary MISFET beam-leaded circuits, which, potentially, are comparable in quality to available bipolar beam-lead chips that use silicon nitride passivation in conjunction with a platinum-titanium-gold metal system. Materials and techniques, different from the bipolar case, were used in order to be more compatible with the special requirements of fully passivated complementary MISFET devices. Two types of circuits were designed and fabricated, a D-flip-flop and a three-input NOR/NAND gate. Fifty beam-leaded chips of each type were constructed. A quality and reliability assurance program was performed to identify failure mechanisms. Sample tests and inspections (including destructive) were developed to measure the physical characteristics of the circuits.

Vertical integration of array-type miniature interferometers at wafer level by using multistack anodic bonding

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Wiemer, Maik; Froemel, Joerg; Enderlein, Tom; Gessner, Thomas; Lullin, Justine; Bargiel, Sylwester; Passilly, Nicolas; Albero, Jorge; Gorecki, Christophe

2016-04-01

In this work, vertical integration of miniaturized array-type Mirau interferometers at wafer level by using multi-stack anodic bonding is presented. Mirau interferometer is suitable for MEMS metrology and for medical imaging according to its vertical-, lateral- resolutions and working distances. Miniaturized Mirau interferometer can be a promising candidate as a key component of an optical coherence tomography (OCT) system. The miniaturized array-type interferometer consists of a microlens doublet, a Si-based MEMS Z scanner, a spacer for focus-adjustment and a beam splitter. Therefore, bonding technologies which are suitable for heterogeneous substrates are of high interest and necessary for the integration of MEMS/MOEMS devices. Multi-stack anodic bonding, which meets the optical and mechanical requirements of the MOEMS device, is adopted to integrate the array-type interferometers. First, the spacer and the beam splitter are bonded, followed by bonding of the MEMS Z scanner. In the meanwhile, two microlenses, which are composed of Si and glass wafers, are anodically bonded to form a microlens doublet. Then, the microlens doublet is aligned and bonded with the scanner/spacer/beam splitter stack. The bonded array-type interferometer is a 7- wafer stack and the thickness is approximately 5mm. To separate such a thick wafer stack with various substrates, 2-step laser cutting is used to dice the bonded stack into Mirau chips. To simplify fabrication process of each component, electrical connections are created at the last step by mounting a Mirau chip onto a flip chip PCB instead of through wafer vias. Stability of Au/Ti films on the MEMS Z scanner after anodic bonding, laser cutting and flip chip bonding are discussed as well.

Fluxless Bonding Processes Using Silver-Indium System for High Temperature Electronics and Silver Flip-Chip Interconnect Technology

NASA Astrophysics Data System (ADS)

Wu, Yuan-Yun

In this dissertation, fluxless silver (Ag)-indium (In) binary system bonding and Ag solid-state bonding are used between different bonded pairs which have large thermal expansion coefficient (CTE) mismatch and flip-chip interconnect bonding application. In contrast to the conventional soldering process, fluxless bonding technique eliminates contamination and reliability problems caused by flux to fabricate high quality joints. There are two section are reported. In the first section, the reactions of Ag-In binary system are presented. In the second section, the high melting temperature, thermal and electrical conductivity joint materials bonding by either Ag-In binary system bonding or solid-state bonding processes for different bonded pairs and flip-chip application are designed, developed, and reported. Our group have studied Ag-In system for several years and developed the bonding processes successfully. However, the detailed reactions of Ag and In were seldom studied. To design a proper bonding structure, it is necessary to understand the reaction between Ag and In. The systematic experiments were performed to investigate these reactions. A 40 um Ag layer was electroplated on copper (Cu) substrates, followed by indium layers of 1, 3, 5, 10, and 15 um, respectively. The samples were annealed at 180 °C in 0.1 torr vacuum. For samples with In thickness less than 5 mum, the joint compositions are Ag2In only (1 um) or AgIn2, Ag2In, and Ag solid solution (Ag) after annealing. No indium is identified. For 10 and 15 um thick In samples, In covers almost over the entire sample surface after annealing. Later, an Ag layer was annealed at 450 °C for 3 hours to grow Ag grains, followed by plating 10 um In and annealing at 180 °C. By annealing Ag before plating In, more In is kept in the structure during annealing at 180 °C. Based on above results, for those designs with In thinner than 5 um, the Ag layer needs to be annealed, prior to In plating in order to make a successful bonding. In this section, we further studied the Ag-In bonding and solid-state bonding for different bonded pairs and flip-chip application. For the silicon (Si) and aluminum (Al) pair, Al has been used as the material for interconnect pads on the ICs. However, its high CTE (23 x 10-6/°C) and non-solderable property limit its applications in electronic products. To overcome these problems, a fluxless Ag-In bonding was developed. Al was deposited Cr/Cu layer on the surface by E-beam evaporator to make it solderable. 15 um of Ag and 8 um of In were sequentially plated on the Al substrates and 15 um of Ag was on Si chips with Cr/Au coating layer. The bonding was performed at 180 °C in 0.1 torr vacuum. The joint consists of Ag/(Ag)/Ag2In/(Ag)/Ag. The joint can achieve a solidus temperature of beyond 600 °C. From shear test results, the shear strengths far exceed the requirement in MIL-STD-883H. Al is not considered as a favorable substrate material because it is not solderable and has a high CTE. The new method presented in this thesis seems to have surmounted these two challenges. Since Ag2In is weak inside the joint in Ag-In system, an annealed process was used to convert the joints into Ag solid solution (Ag) to increase the joint strength and ductility. Two copper (Cu) substrates were bonded at 180 °C without flux. Bonding samples were annealed at 200 °C for 1,000 hours (first design) and at 250 °C for 350 hours (second design), respectively. Scanning electron microscope with energy dispersive X-ray (EDX) analysis results indicate that the joint of the first design is an alloy of mostly (Ag) with micron-size Ag2In and Ag3In regions, and that of second design has converted to a single (Ag) phase. Shear test results show that the breaking forces far exceed the requirement in MIL-STD-883H. The joint solidus temperatures are 600 °C and 800 °C for the first and second designs, respectively. The research results have shown that high-strength and high temperature joints can be manufactured using fluxless low temperature processes with the Ag-In system and are valuable in developing high temperature package. (Abstract shortened by UMI.).

Packaging and testing of multi-wavelength DFB laser array using REC technology

NASA Astrophysics Data System (ADS)

Ni, Yi; Kong, Xuan; Gu, Xiaofeng; Chen, Xiangfei; Zheng, Guanghui; Luan, Jia

2014-02-01

Packaging of distributed feedback (DFB) laser array based on reconstruction-equivalent-chirp (REC) technology is a bridge from chip to system, and influences the practical process of REC chip. In this paper, DFB laser arrays of 4-channel @1310 nm and 8-channel @1550 nm are packaged. Our experimental results show that both these laser arrays have uniform wavelength spacing and larger than 35 dB average Side Mode Suppression Ratio (SMSR). When I=35 mA, we obtain the total output power of 1 mW for 4-channel @1310 nm, and 227 μw for 8-channel @1550 nm respectively. The high frequency characteristics of the packaged chips are also obtained, and the requirements for 4×10 G or even 8×10 G systems can be reached. Our results demonstrate the practical and low cost performance of REC technology and indicate its potential in the future fiber-to-the-home (FTTH) application.

Upset due to a single particle caused propagated transients in a bulk CMOS microprocessor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Leavy, J.F.; Hoffmann, L.F.; Shoran, R.W.

1991-12-01

This paper reports on data pattern advances observed in preset, single event upset (SEU) hardened clocked flip-flops, during static Cf-252 exposures on a bulk CMOS microprocessor, that were attributable to particle caused anomalous clock signals, or propagated transients. SPICE simulations established that particle strikes in the output nodes of a clock control logic flip-flop could produce transients of sufficient amplitude and duration to be accepted as legitimate pulses by clock buffers fed by the flip-flop's output nodes. The buffers would then output false clock pulses, thereby advancing the state of the present flip-flops. Masking the clock logic on one ofmore » the test chips made the flip-flop data advance cease, confirming the clock logic as the source of the SEU. By introducing N{sub 2} gas, at reduced pressures, into the SEU test chamber to attenuate Cf-252 particle LET's, a 24-26 MeV-cm{sup 2}/mg LET threshold was deduced. Subsequent tests, at the 88-inch cyclotron at Berkeley, established an LET threshold of 30 MeV-cm{sup 2}/mg (283 MeV Cu at 0{degrees}) for the generation of false clocks. Cyclotron SEU tests are considered definitive, while Cf-252 data usually is not. However, in this instance Cf-252 tests proved analytically useful, providing SEU characterization data that was both timely and inexpensive.« less

Chip packaging technique

NASA Technical Reports Server (NTRS)

Jayaraj, Kumaraswamy (Inventor); Noll, Thomas E. (Inventor); Lockwood, Harry F. (Inventor)

2001-01-01

A hermetically sealed package for at least one semiconductor chip is provided which is formed of a substrate having electrical interconnects thereon to which the semiconductor chips are selectively bonded, and a lid which preferably functions as a heat sink, with a hermetic seal being formed around the chips between the substrate and the heat sink. The substrate is either formed of or includes a layer of a thermoplastic material having low moisture permeability which material is preferably a liquid crystal polymer (LCP) and is a multiaxially oriented LCP material for preferred embodiments. Where the lid is a heat sink, the heat sink is formed of a material having high thermal conductivity and preferably a coefficient of thermal expansion which substantially matches that of the chip. A hermetic bond is formed between the side of each chip opposite that connected to the substrate and the heat sink. The thermal bond between the substrate and the lid/heat sink may be a pinched seal or may be provided, for example by an LCP frame which is hermetically bonded or sealed on one side to the substrate and on the other side to the lid/heat sink. The chips may operate in the RF or microwave bands with suitable interconnects on the substrate and the chips may also include optical components with optical fibers being sealed into the substrate and aligned with corresponding optical components to transmit light in at least one direction. A plurality of packages may be physically and electrically connected together in a stack to form a 3D array.

Chip Scale Package Integrity Assessment by Isothermal Aging

NASA Technical Reports Server (NTRS)

Ghaffarian, Reza

1998-01-01

Many aspects of chip scale package (CSP) technology, with focus on assembly reliability characteristics, are being investigated by the JPL-led consortia. Three types of test vehicles were considered for evaluation and currently two configurations have been built to optimize attachment processes. These test vehicles use numerous package types. To understand potential failure mechanisms of the packages, particularly solder ball attachment, the grid CSPs were subjected to environmental exposure. Package I/Os ranged from 40 to nearly 300. This paper presents both as assembled, up to 1, 000 hours of isothermal aging shear test results and photo micrographs, and tensile test results before and after 1,500 cycles in the range of -30/100 C for CSPs. Results will be compared to BGAs with the same the same isothermal aging environmental exposures.

Single-mode glass waveguide technology for optical interchip communication on board level

NASA Astrophysics Data System (ADS)

Brusberg, Lars; Neitz, Marcel; Schröder, Henning

2012-01-01

The large bandwidth demand in long-distance telecom networks lead to single-mode fiber interconnects as result of low dispersion, low loss and dense wavelength multiplexing possibilities. In contrast, multi-mode interconnects are suitable for much shorter lengths up to 300 meters and are promising for optical links between racks and on board level. Active optical cables based on multi-mode fiber links are at the market and research in multi-mode waveguide integration on board level is still going on. Compared to multi-mode, a single-mode waveguide has much more integration potential because of core diameters of around 20% of a multi-mode waveguide by a much larger bandwidth. But light coupling in single-mode waveguides is much more challenging because of lower coupling tolerances. Together with the silicon photonics technology, a single-mode waveguide technology on board-level will be the straight forward development goal for chip-to-chip optical interconnects integration. Such a hybrid packaging platform providing 3D optical single-mode links bridges the gap between novel photonic integrated circuits and the glass fiber based long-distance telecom networks. Following we introduce our 3D photonic packaging approach based on thin glass substrates with planar integrated optical single-mode waveguides for fiber-to-chip and chip-to-chip interconnects. This novel packaging approach merges micro-system packaging and glass integrated optics. It consists of a thin glass substrate with planar integrated singlemode waveguide circuits, optical mirrors and lenses providing an integration platform for photonic IC assembly and optical fiber interconnect. Thin glass is commercially available in panel and wafer formats and characterizes excellent optical and high-frequency properties. That makes it perfect for microsystem packaging. The paper presents recent results in single-mode waveguide technology on wafer level and waveguide characterization. Furthermore the integration in a hybrid packaging process and design issues are discussed.

Electromigration Critical Product to Measure Effect of Underfill Material in Suppressing Bi Segregation in Sn-58Bi Solder

NASA Astrophysics Data System (ADS)

Zhao, Xu; Takaya, Satoshi; Muraoka, Mikio

2017-08-01

Recently, we detected length-dependent electromigration (EM) behavior in Sn-58Bi (SB) solder and revealed the existence of Bi back-flow, which retards EM-induced Bi segregation and is dependent on solder length. The cause of the back-flow is attributed to an oxide layer formed on the SB solder. At present, underfill (UF) material is commonly used in flip-chip packaging as filler between chip and substrate to surround solder bumps. In this study, we quantitatively investigated the effect of UF material as a passivation layer on EM in SB solder strips. EM tests on SB solder strips with length of 50 μm, 100 μm, and 150 μm were conducted simultaneously. Some samples were coated with commercial thermosetting epoxy UF material, which acted as a passivation layer on the Cu-SB-Cu interconnections. The value of the critical product for SB solder was estimated to be 38 A/cm to 43 A/cm at 353 K to 373 K without UF coating and 59 A/cm at 373 K with UF coating. The UF material acting as a passivation layer suppressed EM-induced Bi segregation and increased the threshold current density by 37% to 55%. However, at very high current density, this effect became very slight. In addition, Bi atoms can diffuse to the anode side through the Sn phase, hence addition of microelements to the Sn phase to form obstacles, such as intermetallic compounds, may retard Bi segregation in SB solder.

A new on-chip all-digital three-phase full-bridge dc/ac power inverter with feedforward and frequency control techniques.

PubMed

Chen, Jiann-Jong; Kung, Che-Min

2010-09-01

The communication speed between components is far from satisfactory. To achieve high speed, simple control system configuration, and low cost, a new on-chip all-digital three-phase dc/ac power inverter using feedforward and frequency control techniques is proposed. The controller of the proposed power inverter, called the shift register, consists of six-stage D-latch flip-flops with a goal of achieving low-power consumption and area efficiency. Variable frequency is achieved by controlling the clocks of the shift register. One advantage regarding the data signal (D) and the common clock (CK) is that, regardless of the phase difference between the two, all of the D-latch flip-flops are capable of delaying data by one CK period. To ensure stability, the frequency of CK must be six times higher than that of D. The operation frequency of the proposed power inverter ranges from 10 Hz to 2 MHz, and the maximum output loading current is 0.8 A. The prototype of the proposed circuit has been fabricated with TSMC 0.35 μm 2P4M CMOS processes. The total chip area is 2.333 x 1.698 mm2. The three-phase dc/ac power inverter is applicable in uninterrupted power supplies, cold cathode fluorescent lamps, and motors, because of its ability to convert the dc supply voltage into the three-phase ac power sources.

Analysis pipelines and packages for Infinium HumanMethylation450 BeadChip (450k) data

PubMed Central

Morris, Tiffany J.; Beck, Stephan

2015-01-01

The Illumina HumanMethylation450 BeadChip has become a popular platform for interrogating DNA methylation in epigenome-wide association studies (EWAS) and related projects as well as resource efforts such as the International Cancer Genome Consortium (ICGC) and the International Human Epigenome Consortium (IHEC). This has resulted in an exponential increase of 450k data in recent years and triggered the development of numerous integrated analysis pipelines and stand-alone packages. This review will introduce and discuss the currently most popular pipelines and packages and is particularly aimed at new 450k users. PMID:25233806

Comparative experimental and simulation studies of high-power AlGaN-based 353 nm ultraviolet flip-chip and top-emitting LEDs

NASA Astrophysics Data System (ADS)

Liu, Mengling; Zhou, Shengjun; Liu, Xingtong; Gao, Yilin; Ding, Xinghuo

2018-03-01

Experimental and simulation studies of high-power AlGaN-based 353 nm ultraviolet (UV) flip-chip (FC) and top-emitting (TE) light-emitting diodes (LEDs) are performed here. To improve the optical and electrical properties of ultraviolet LEDs, we fabricate high-power FC-UV LEDs with Ta2O5/SiO2 distributed Bragg reflectors (DBRs) and a strip-shaped SiO2 current blocking layer (CBL). The reflectance of fourteen pairs of Ta2O5/SiO2 DBRs is 96.4% at 353 nm. The strip-shaped SiO2 CBL underneath the strip-shaped p-electrode can prevent the current concentrating in regions immediately adjacent to the p-electrode where the overlying opaque p-electrode metal layer absorbs the emitted UV light. Moreover, two-level metallization electrodes are used to improve current spreading. Our numerical results show that FC-UV LED has a more favorable current spreading uniformity than TE-UV LED. The light output power of 353 nm FC-UV LED was 23.22 mW at 350 mA, which is 24.7% higher than that of TE-UV LED.

Nucleation rates of Sn in undercooled Sn-Ag-Cu flip-chip solder joints

NASA Astrophysics Data System (ADS)

Arfaei, B.; Benedict, M.; Cotts, E. J.

2013-11-01

The nucleation of Sn from the melt in commercial SnAgCu flip chip solder joints was monitored at a number of different temperatures. Nucleation rates were estimated from measurements of nucleation times for 440 solder balls after one reflow and were found to be well epitomized by the expression I = 2 × 109 exp[(-1.6 × 105)/(T × (ΔT)2)] m-3 s-1, as per classical nucleation theory. After an additional reflow, the nucleation rates of the same 440 samples were observed to increase to I = 2 × 109 exp[(-8.9 × 104)/(T × (ΔT)2)] m-3 s-1. Thus it was shown that the expressions of classical nucleation theory well characterize nucleation kinetics for this system. These changes in nucleation kinetics were correlated with continued dissolution of Al and Ni in to the SnAgCu melt. Such increases in nucleation rates meant increases in the average solidification temperatures of the solder balls after reflow. Variations in the Sn grain morphology of the solder joints were correlated with these changes in solidification temperature, with larger Sn grains (beach ball Sn grain morphology) observed at higher solidification temperatures.

Fabrication of Fresnel micro lens array in borosilicate glass by F2-laser ablation for glass interposer application

NASA Astrophysics Data System (ADS)

Brusberg, Lars; Neitz, Marcel; Schröder, Henning; Fricke-Begemann, Thomas; Ihlemann, Jürgen

2014-03-01

The future need for more bandwidth forces the development of optical transmission solutions for rack-to-rack, boardto- board and chip-to-chip interconnects. The goals are significant reduction of power consumption, highest density and potential for bandwidth scalability to overcome the limitations of the systems today with mostly copper based interconnects. For system integration the enabling of thin glass as a substrate material for electro-optical components with integrated micro-optics for efficient light coupling to integrated optical waveguides or fibers is becoming important. Our glass based packaging approach merges micro-system packaging and glass integrated optics. This kind of packaging consists of a thin glass substrate with integrated micro lenses providing a platform for photonic component assembly and optical fiber or waveguide interconnection. Thin glass is commercially available in panel and wafer size and characterizes excellent optical and high frequency properties. That makes it perfect for microsystem packaging. A suitable micro lens approach has to be comparable with different commercial glasses and withstand post-processing like soldering. A benefit of using laser ablated Fresnel lenses is the planar integration capability in the substrate for highest integration density. In the paper we introduce our glass based packaging concept and the Fresnel lens design for different scenarios like chip-to-fiber, chip-to-optical-printed-circuit-board coupling. Based on the design the Fresnel lenses were fabricated by using a 157 nm fluorine laser ablation system.

27 CFR 19.303 - Addition of caramel to rum or brandy and addition of oak chips to spirits.

Code of Federal Regulations, 2012 CFR

2012-04-01

... or brandy and addition of oak chips to spirits. 19.303 Section 19.303 Alcohol, Tobacco Products and... rum or brandy and addition of oak chips to spirits. A proprietor may add caramel that has no material... oak chips that have not been treated with any chemical to packages of spirits prior to or after the...

27 CFR 19.303 - Addition of caramel to rum or brandy and addition of oak chips to spirits.

Code of Federal Regulations, 2014 CFR

2014-04-01

... or brandy and addition of oak chips to spirits. 19.303 Section 19.303 Alcohol, Tobacco Products and... rum or brandy and addition of oak chips to spirits. A proprietor may add caramel that has no material... oak chips that have not been treated with any chemical to packages of spirits prior to or after the...

27 CFR 19.303 - Addition of caramel to rum or brandy and addition of oak chips to spirits.

Code of Federal Regulations, 2011 CFR

2011-04-01

... or brandy and addition of oak chips to spirits. 19.303 Section 19.303 Alcohol, Tobacco Products and... rum or brandy and addition of oak chips to spirits. A proprietor may add caramel that has no material... oak chips that have not been treated with any chemical to packages of spirits prior to or after the...

27 CFR 19.303 - Addition of caramel to rum or brandy and addition of oak chips to spirits.

Code of Federal Regulations, 2013 CFR

2013-04-01

... or brandy and addition of oak chips to spirits. 19.303 Section 19.303 Alcohol, Tobacco Products and... rum or brandy and addition of oak chips to spirits. A proprietor may add caramel that has no material... oak chips that have not been treated with any chemical to packages of spirits prior to or after the...

Comment on "Enhancement of flip-chip white light-emitting diodes with a one-dimensional photonic crystal".

PubMed

Liu, Zong-Yuan; Liu, Sheng; Wang, Kai; Luo, Xiao-Bing

2010-06-01

We show that research presented in Opt. Lett.34, 301 (2009)OPLEDP0146-959210.1364/OL.34.000301 applied questionable phosphor definitions and a questionable simulation procedure for light-emitting diodes. Our simulation indicates that a one-dimensional photonic crystal is beneficial for color control but cannot improve the light extraction as asserted in that Letter.

Adaptive Optoelectronic Eyes: Hybrid Sensor/Processor Architectures

DTIC Science & Technology

2006-11-13

corresponding calculated data. The width of the mirror stopband is proportional to the refractive index difference between the high and low index materials ...Silicon VLSI Neuron Unit Arrays 56 Development of a Single-Sided Flip-Chip Bonding Process 65 Development of High Refractive Index Diffractive Optical ...Elements (DOEs) 68 Development of High-Performance Antireflection Coatings for High Refractive Index DOEs 69 Design and Fabrication of Low Threshold

Lithographic chip identification: meeting the failure analysis challenge

NASA Astrophysics Data System (ADS)

Perkins, Lynn; Riddell, Kevin G.; Flack, Warren W.

1992-06-01

This paper describes a novel method using stepper photolithography to uniquely identify individual chips for permanent traceability. A commercially available 1X stepper is used to mark chips with an identifier or `serial number' which can be encoded with relevant information for the integrated circuit manufacturer. The permanent identification of individual chips can improve current methods of quality control, failure analysis, and inventory control. The need for this technology is escalating as manufacturers seek to provide six sigma quality control for their products and trace fabrication problems to their source. This need is especially acute for parts that fail after packaging and are returned to the manufacturer for analysis. Using this novel approach, failure analysis data can be tied back to a particular batch, wafer, or even a position within a wafer. Process control can be enhanced by identifying the root cause of chip failures. Chip identification also addresses manufacturers concerns with increasing incidences of chip theft. Since chips currently carry no identification other than the manufacturer's name and part number, recovery efforts are hampered by the inability to determine the sales history of a specific packaged chip. A definitive identifier or serial number for each chip would address this concern. The results of chip identification (patent pending) are easily viewed through a low power microscope. Batch number, wafer number, exposure step, and chip location within the exposure step can be recorded, as can dates and other items of interest. An explanation of the chip identification procedure and processing requirements are described. Experimental testing and results are presented, and potential applications are discussed.

Student Responses to a Flipped Introductory Physics Class with built-in Post-Video Feedback Quizzes

NASA Astrophysics Data System (ADS)

Ramos, Roberto

We present and analyze student responses to multiple Introductory physics classes in a university setting, taught in a ''flipped'' class format. The classes included algebra- and calculus-based introductory physics. Outside class, students viewed over 100 online video lectures on Classical Mechanics, Electricity and Magnetism, and Modern Physics prepared by this author and in some cases, by a third-party lecture package available over YouTube. Inside the class, students solved and discussed problems and conceptual issues in greater detail. A pre-class online quiz was deployed as an important source of feedback. I will report on the student reactions to the feedback mechanism, student responses using data based on anonymous surveys, as well as on learning gains from pre-/post- physics diagnostic tests. The results indicate a broad mixture of responses to different lecture video packages that depend on learning styles and perceptions. Students preferred the online quizzes as a mechanism to validate their understanding. The learning gains based on FCI and CSEM surveys were significant.

Novel Ruggedized Packaging Technology for VCSELs

DTIC Science & Technology

2017-03-01

Novel Ruggedized Packaging Technology for VCSELs Charlie Kuznia ckuznia@ultracomm-inc.com Ultra Communications, Inc. Vista, CA, USA, 92081...n ac hieve l ow-power, E MI-immune links within hi gh-performance m ilitary computing an d sensor systems. Figure 1. Chip-scale-packaging of

A non-volatile flip-flop based on diode-selected PCM for ultra-low power systems

NASA Astrophysics Data System (ADS)

Ye, Yong; Du, Yuan; Gao, Dan; Kang, Yong; Song, Zhitang; Chen, Bomy

2016-10-01

As the process technology is continuously shrinking, low power consumption is a major issue in VLSI Systems-on-Chip (SoCs), especially for standby-power-critical applications. Recently, the emerging CMOS-compatible non-volatile memories (NVMs), such as Phase Change Memory (PCM), have been used as on-chip storage elements, which can obtain non-volatile processing, nearly-zero standby power and instant-on capability. PCM has been considered as the best candidate for the next generation of NVMs for its low cost, high density and high resistance transformation ratio. In this paper, for the first time, we present a diode-selected PCM based non-volatile flip-flop (NVFF) which is optimized for better power consumption and process variation tolerance. With dual trench isolation process, the diode-selected PCM realizes ultra small area, which is very suitable for multi-context configuration and large scale flip-flops matrix. Since the MOS-selected PCM is hard to shrink further due to large amount of PCM write current, the proposed NVFF achieves higher power efficiency without loss of current driving capability. Using the 40nm manufacturing process, the area of the cell (1D1R) is as small as 0.016 μm2. Simulation results show that the energy consumption during the recall operation is 62 fJ with 1.1 standard supply voltage, which is reduced by 54.9% compared to the previous 2T2R based NVFF. When the supply voltage reduces to 0.7 V, the recall energy is as low as 17 fJ. With the great advantages in cell size and energy, the proposed diode-selected NVFF is very applicable and cost-effective for ULP systems.

Student Perceptions of a Flipped Pharmacotherapy Course

PubMed Central

Khanova, Julia; McLaughlin, Jacqueline E.; Rhoney, Denise H.; Roth, Mary T.

2015-01-01

Objective. To evaluate student perception of the flipped classroom redesign of a required pharmacotherapy course. Design. Key foundational content was packaged into interactive, text-based online modules for self-paced learning prior to class. Class time was used for active and applied—but primarily case-based—learning. Assessment. For students with a strong preference for traditional lecture learning, the perception of the learning experience was negatively affected by the flipped course design. Module length and time required to complete preclass preparation were the most frequently cited impediments to learning. Students desired instructor-directed reinforcement of independently acquired knowledge to connect foundational knowledge and its application. Conclusion. This study illustrates the challenges and highlights the importance of designing courses to effectively balance time requirements and connect preclass and in-class learning activities. It underscores the crucial role of the instructor in bridging the gap between material learned as independent study and its application. PMID:26839429

RELIC: a novel dye-bias correction method for Illumina Methylation BeadChip.

PubMed

Xu, Zongli; Langie, Sabine A S; De Boever, Patrick; Taylor, Jack A; Niu, Liang

2017-01-03

The Illumina Infinium HumanMethylation450 BeadChip and its successor, Infinium MethylationEPIC BeadChip, have been extensively utilized in epigenome-wide association studies. Both arrays use two fluorescent dyes (Cy3-green/Cy5-red) to measure methylation level at CpG sites. However, performance difference between dyes can result in biased estimates of methylation levels. Here we describe a novel method, called REgression on Logarithm of Internal Control probes (RELIC) to correct for dye bias on whole array by utilizing the intensity values of paired internal control probes that monitor the two color channels. We evaluate the method in several datasets against other widely used dye-bias correction methods. Results on data quality improvement showed that RELIC correction statistically significantly outperforms alternative dye-bias correction methods. We incorporated the method into the R package ENmix, which is freely available from the Bioconductor website ( https://www.bioconductor.org/packages/release/bioc/html/ENmix.html ). RELIC is an efficient and robust method to correct for dye-bias in Illumina Methylation BeadChip data. It outperforms other alternative methods and conveniently implemented in R package ENmix to facilitate DNA methylation studies.

High-power, format-flexible, 885-nm vertical-cavity surface-emitting laser arrays

NASA Astrophysics Data System (ADS)

Wang, Chad; Talantov, Fedor; Garrett, Henry; Berdin, Glen; Cardellino, Terri; Millenheft, David; Geske, Jonathan

2013-03-01

High-power, format flexible, 885 nm vertical-cavity surface-emitting laser (VCSEL) arrays have been developed for solid-state pumping and illumination applications. In this approach, a common VCSEL size format was designed to enable tiling into flexible formats and operating configurations. The fabrication of a common chip size on ceramic submount enables low-cost volume manufacturing of high-power VCSEL arrays. This base VCSEL chip was designed to be 5x3.33 mm2, and produced up to 50 Watts of peak continuous wave (CW) power. To scale to higher powers, multiple chips can be tiled into a combination of series or parallel configurations tailored to the application driver conditions. In actively cooled CW operation, the VCSEL array chips were packaged onto a single water channel cooler, and we have demonstrated 0.5x1, 1x1, and 1x3 cm2 formats, producing 150, 250, and 500 Watts of peak power, respectively, in under 130 A operating current. In QCW operation, the 1x3 cm2 VCSEL module, which contains 18 VCSEL array chips packaged on a single water cooler, produced over 1.3 kW of peak power. In passively cooled packages, multiple chip configurations have been developed for illumination applications, producing over 300 Watts of peak power in QCW operating conditions. These VCSEL chips use a substrate-removed structure to allow for efficient thermal heatsinking to enable high-power operation. This scalable, format flexible VCSEL architecture can be applied to wavelengths ranging from 800 to 1100 nm, and can be used to tailor emission spectral widths and build high-power hyperspectral sources.

Packaged integrated opto-fluidic solution for harmful fluid analysis

NASA Astrophysics Data System (ADS)

Allenet, T.; Bucci, D.; Geoffray, F.; Canto, F.; Couston, L.; Jardinier, E.; Broquin, J.-E.

2016-02-01

Advances in nuclear fuel reprocessing have led to a surging need for novel chemical analysis tools. In this paper, we present a packaged lab-on-chip approach with co-integration of optical and micro-fluidic functions on a glass substrate as a solution. A chip was built and packaged to obtain light/fluid interaction in order for the entire device to make spectral measurements using the photo spectroscopy absorption principle. The interaction between the analyte solution and light takes place at the boundary between a waveguide and a fluid micro-channel thanks to the evanescent part of the waveguide's guided mode that propagates into the fluid. The waveguide was obtained via ion exchange on a glass wafer. The input and the output of the waveguides were pigtailed with standard single mode optical fibers. The micro-scale fluid channel was elaborated with a lithography procedure and hydrofluoric acid wet etching resulting in a 150+/-8 μm deep channel. The channel was designed with fluidic accesses, in order for the chip to be compatible with commercial fluidic interfaces/chip mounts. This allows for analyte fluid in external capillaries to be pumped into the device through micro-pipes, hence resulting in a fully packaged chip. In order to produce this co-integrated structure, two substrates were bonded. A study of direct glass wafer-to-wafer molecular bonding was carried-out to improve detector sturdiness and durability and put forward a bonding protocol with a bonding surface energy of γ>2.0 J.m-2. Detector viability was shown by obtaining optical mode measurements and detecting traces of 1.2 M neodymium (Nd) solute in 12+/-1 μL of 0.01 M and pH 2 nitric acid (HNO3) solvent by obtaining an absorption peak specific to neodymium at 795 nm.

Analysis pipelines and packages for Infinium HumanMethylation450 BeadChip (450k) data.

PubMed

Morris, Tiffany J; Beck, Stephan

2015-01-15

The Illumina HumanMethylation450 BeadChip has become a popular platform for interrogating DNA methylation in epigenome-wide association studies (EWAS) and related projects as well as resource efforts such as the International Cancer Genome Consortium (ICGC) and the International Human Epigenome Consortium (IHEC). This has resulted in an exponential increase of 450k data in recent years and triggered the development of numerous integrated analysis pipelines and stand-alone packages. This review will introduce and discuss the currently most popular pipelines and packages and is particularly aimed at new 450k users. Copyright © 2014 The Authors. Published by Elsevier Inc. All rights reserved.

Phosphor-Free InGaN White Light Emitting Diodes Using Flip-Chip Technology

PubMed Central

Li, Ying-Chang; Chang, Liann-Be; Chen, Hou-Jen; Yen, Chia-Yi; Pan, Ke-Wei; Huang, Bohr-Ran; Kuo, Wen-Yu; Chow, Lee; Zhou, Dan; Popko, Ewa

2017-01-01

Monolithic phosphor-free two-color gallium nitride (GaN)-based white light emitting diodes (LED) have the potential to replace current phosphor-based GaN white LEDs due to their low cost and long life cycle. Unfortunately, the growth of high indium content indium gallium nitride (InGaN)/GaN quantum dot and reported LED’s color rendering index (CRI) are still problematic. Here, we use flip-chip technology to fabricate an upside down monolithic two-color phosphor-free LED with four grown layers of high indium quantum dots on top of the three grown layers of lower indium quantum wells separated by a GaN tunneling barrier layer. The photoluminescence (PL) and electroluminescence (EL) spectra of this white LED reveal a broad spectrum ranging from 475 to 675 nm which is close to an ideal white-light source. The corresponding color temperature and color rendering index (CRI) of the fabricated white LED, operated at 350, 500, and 750 mA, are comparable to that of the conventional phosphor-based LEDs. Insights of the epitaxial structure and the transport mechanism were revealed through the TEM and temperature dependent PL and EL measurements. Our results show true potential in the Epi-ready GaN white LEDs for future solid state lighting applications. PMID:28772792

Analysis of light extraction efficiency enhancement for thin-film-flip-chip InGaN quantum wells light-emitting diodes with GaN micro-domes.

PubMed

Zhao, Peng; Zhao, Hongping

2012-09-10

The enhancement of light extraction efficiency for thin-film flip-chip (TFFC) InGaN quantum wells (QWs) light-emitting diodes (LEDs) with GaN micro-domes on n-GaN layer was studied. The light extraction efficiency of TFFC InGaN QWs LEDs with GaN micro-domes were calculated and compared to that of the conventional TFFC InGaN QWs LEDs with flat surface. The three dimensional finite difference time domain (3D-FDTD) method was used to calculate the light extraction efficiency for the InGaN QWs LEDs emitting at 460nm and 550 nm, respectively. The effects of the GaN micro-dome feature size and the p-GaN layer thickness on the light extraction efficiency were studied systematically. Studies indicate that the p-GaN layer thickness is critical for optimizing the TFFC LED light extraction efficiency. Significant enhancement of the light extraction efficiency (2.5-2.7 times for λ(peak) = 460nm and 2.7-2.8 times for λ(peak) = 550nm) is achievable from TFFC InGaN QWs LEDs with optimized GaN micro-dome diameter and height.

Thermal Design and Characterization of Heterogeneously Integrated InGaP/GaAs HBTs

DOE PAGES

Choi, Sukwon; Peake, Gregory M.; Keeler, Gordon A.; ...

2016-04-21

Flip-chip heterogeneously integrated n-p-n InGaP/GaAs heterojunction bipolar transistors (HBTs) with integrated thermal management on wide-bandgap AlN substrates followed by GaAs substrate removal are demonstrated. Without thermal management, substrate removal after integration significantly aggravates self-heating effects, causing poor I–V characteristics due to excessive device self-heating. An electrothermal codesign scheme is demonstrated that involves simulation (design), thermal characterization, fabrication, and evaluation. Thermoreflectance thermal imaging, electrical-temperature sensitive parameter-based thermometry, and infrared thermography were utilized to assess the junction temperature rise in HBTs under diverse configurations. In order to reduce the thermal resistance of integrated devices, passive cooling schemes assisted by structural modification, i.e.,more » positioning indium bump heat sinks between the devices and the carrier, were employed. By implementing thermal heat sinks in close proximity to the active region of flip-chip integrated HBTs, the junction-to-baseplate thermal resistance was reduced over a factor of two, as revealed by junction temperature measurements and improvement of electrical performance. In conclusion, the suggested heterogeneous integration method accounts for not only electrical but also thermal requirements providing insight into realization of advanced and robust III–V/Si heterogeneously integrated electronics.« less

Effects of PCB Pad Metal Finishes on the Cu-Pillar/Sn-Ag Micro Bump Joint Reliability of Chip-on-Board (COB) Assembly

NASA Astrophysics Data System (ADS)

Kim, Youngsoon; Lee, Seyong; Shin, Ji-won; Paik, Kyung-Wook

2016-06-01

While solder bumps have been used as the bump structure to form the interconnection during the last few decades, the continuing scaling down of devices has led to a change in the bump structure to Cu-pillar/Sn-Ag micro-bumps. Cu-pillar/Sn-Ag micro-bump interconnections differ from conventional solder bump interconnections in terms of their assembly processing and reliability. A thermo-compression bonding method with pre-applied b-stage non-conductive films has been adopted to form solder joints between Cu pillar/Sn-Ag micro bumps and printed circuit board vehicles, using various pad metal finishes. As a result, various interfacial inter-metallic compounds (IMCs) reactions and stress concentrations occur at the Cu pillar/Sn-Ag micro bumps joints. Therefore, it is necessary to investigate the influence of pad metal finishes on the structural reliability of fine pitch Cu pillar/Sn-Ag micro bumps flip chip packaging. In this study, four different pad surface finishes (Thin Ni ENEPIG, OSP, ENEPIG, ENIG) were evaluated in terms of their interconnection reliability by thermal cycle (T/C) test up to 2000 cycles at temperatures ranging from -55°C to 125°C and high-temperature storage test up to 1000 h at 150°C. The contact resistances of the Cu pillar/Sn-Ag micro bump showed significant differences after the T/C reliability test in the following order: thin Ni ENEPIG > OSP > ENEPIG where the thin Ni ENEPIG pad metal finish provided the best Cu pillar/Sn-Ag micro bump interconnection in terms of bump joint reliability. Various IMCs formed between the bump joint areas can account for the main failure mechanism.

White light emitting diode based on InGaN chip with core/shell quantum dots

NASA Astrophysics Data System (ADS)

Shen, Changyu; Hong, Yan; Ma, Jiandong; Ming, Jiangzhou

2009-08-01

Quantum dots have many applications in optoelectronic device such as LEDs for its many superior properties resulting from the three-dimensional confinement effect of its carrier. In this paper, single chip white light-emitting diodes (WLEDs) were fabricated by combining blue InGaN chip with luminescent colloidal quantum dots (QDs). Two kinds of QDs of core/shell CdSe /ZnS and core/shell/shell CdSe /ZnS /CdS nanocrystals were synthesized by thermal deposition using cadmium oxide and selenium as precursors in a hot lauric acid and hexadecylamine trioctylphosphine oxide hybrid. This two kinds of QDs exhibited high photoluminescence efficiency with a quantum yield more than 41%, and size-tunable emission wavelengths from 500 to 620 nm. The QDs LED mainly consists of flip luminescent InGaN chip, glass ceramic protective coating, glisten cup, QDs using as the photoluminescence material, pyroceram, gold line, electric layer, dielectric layer, silicon gel and bottom layer for welding. The WLEDs had the CIE coordinates of (0.319, 0.32). The InGaN chip white-light-emitting diodes with quantum dots as the emitting layer are potentially useful in illumination and display applications.

High Temperature Pt/Alumina Co-Fired System for 500 C Electronic Packaging Applications

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Neudeck, Philip G.; Spry, David J.; Beheim, Glenn M.; Hunter, Gary W.

2015-01-01

Gold thick-film metallization and 96 alumina substrate based prototype packaging system developed for 500C SiC electronics and sensors is briefly reviewed, the needs of improvement are discussed. A high temperature co-fired alumina material system based packaging system composed of 32-pin chip-level package and printed circuit board is discussed for packaging 500C SiC electronics and sensors.

Contamination control in hybrid microelectronic modules. Part 2: Selection and evaluation of coating materials

NASA Technical Reports Server (NTRS)

Himmel, R. P.

1975-01-01

The selection, test, and evaluation of organic coating materials for contamination control in hybrid circuits is reported. The coatings were evaluated to determine their suitability for use as a conformal coating over the hybrid microcircuit (including chips and wire bonds) inside a hermetically sealed package. Evaluations included ease of coating application and repair and effect on thin film and thick film resistors, beam leads, wire bonds, transistor chips, and capacitor chips. The coatings were also tested for such properties as insulation resistance, voltage breakdown strength, and capability of immobilizing loose particles inside the packages. The selected coatings were found to be electrically, mechanically, and chemically compatible with all components and materials normally used in hybrid microcircuits.

Thick resist for MEMS processing

NASA Astrophysics Data System (ADS)

Brown, Joe; Hamel, Clifford

2001-11-01

The need for technical innovation is always present in today's economy. Microfabrication methods have evolved in support of the demand for smaller and faster integrated circuits with price performance improvements always in the scope of the manufacturing design engineer. The dispersion of processing technology spans well beyond IC fabrication today with batch fabrication and wafer scale processing lending advantages to MEMES applications from biotechnology to consumer electronics from oil exploration to aerospace. Today the demand for innovative processing techniques that enable technology is apparent where only a few years ago appeared too costly or not reliable. In high volume applications where yield and cost improvements are measured in fractions of a percent it is imperative to have process technologies that produce consistent results. Only a few years ago thick resist coatings were limited to thickness less than 20 microns. Factors such as uniformity, edge bead and multiple coatings made high volume production impossible. New developments in photoresist formulation combined with advanced coating equipment techniques that closely controls process parameters have enable thick photoresist coatings of 70 microns with acceptable uniformity and edge bead in one pass. Packaging of microelectronic and micromechanical devices is often a significant cost factor and a reliability issue for high volume low cost production. Technologies such as flip- chip assembly provide a solution for cost and reliability improvements over wire bond techniques. The processing for such technology demands dimensional control and presents a significant cost savings if it were compatible with mainstream technologies. Thick photoresist layers, with good sidewall control would allow wafer-bumping technologies to penetrate the barriers to yield and production where costs for technology are the overriding issue. Single pass processing is paramount to the manufacturability of packaging technology. Uniformity and edge bead control defined the success of process implementation. Today advanced packaging solutions are created with thick photoresist coatings. The techniques and results will be presented.

Light emitting diode package element with internal meniscus for bubble free lens placement

DOEpatents

Tarsa, Eric; Yuan, Thomas C.; Becerra, Maryanne; Yadev, Praveen

2010-09-28

A method for fabricating a light emitting diode (LED) package comprising providing an LED chip and covering at least part of the LED chip with a liquid encapsulant having a radius of curvature. An optical element is provided having a bottom surface with at least a portion having a radius of curvature larger than the liquid encapsulant. The larger radius of curvature portion of the optical element is brought into contact with the liquid encapsulant. The optical element is then moved closer to the LED chip, growing the contact area between said optical element and said liquid encapsulant. The liquid encapsulant is then cured. A light emitting diode comprising a substrate with an LED chip mounted to it. A meniscus ring is on the substrate around the LED chip with the meniscus ring having a meniscus holding feature. An inner encapsulant is provided over the LED chip with the inner encapsulant having a contacting surface on the substrate, with the meniscus holding feature which defines the edge of the contacting surface. An optical element is included having a bottom surface with at least a portion that is concave. The optical element is arranged on the substrate with the concave portion over the LED chip. A contacting encapsulant is included between the inner encapsulant and optical element.

75 FR 447 - In the Matter of Certain Semiconductor Chips With Minimized Chip Package Size and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-01-05

... review (1) the finding that the claim term ``top layer'' recited in claim 1 of the '106 patent means ``an outer layer of the chip assembly upon which the terminals are fixed,'' the requirement that ``the `top layer' is a single layer,'' and the effect of the findings on the infringement analysis, invalidity...

Three Dimensional Integration and On-Wafer Packaging for Heterogeneous Wafer-Scale Circuit Architectures

DTIC Science & Technology

2006-11-01

Chip Level CMOS Chip High resistivity Si Metal Interconnect 25μm 24GHz fully integrated receiver CMOS transimpedance Amplifier (13GHz BW, 52dBΩ...power of a high-resistivity SiGe power amplifier chip with the wide operating frequency range and compactness of a CMOS mixed signal chip operating...With good RF channel selectivity, system specifications such as the linearity of the low noise amplifier (LNA), the phase noise of the voltage

A 50Mbit/Sec. CMOS Video Linestore System

NASA Astrophysics Data System (ADS)

Jeung, Yeun C.

1988-10-01

This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

Fabrication of Quench Condensed Thin Films Using an Integrated MEMS Fab on a Chip

NASA Astrophysics Data System (ADS)

Lally, Richard; Reeves, Jeremy; Stark, Thomas; Barrett, Lawrence; Bishop, David

Atomic calligraphy is a microelectromechanical systems (MEMS)-based dynamic stencil nanolithography technique. Integrating MEMS devices into a bonded stacked array of three die provides a unique platform for conducting quench condensed thin film mesoscopic experiments. The atomic calligraphy Fab on a Chip process incorporates metal film sources, electrostatic comb driven stencil plate, mass sensor, temperature sensor, and target surface into one multi-die assembly. Three separate die are created using the PolyMUMPs process and are flip-chip bonded together. A die containing joule heated sources must be prepared with metal for evaporation prior to assembly. A backside etch of the middle/central die exposes the moveable stencil plate allowing the flux to pass through the stencil from the source die to the target die. The chip assembly is mounted in a cryogenic system at ultra-high vacuum for depositing extremely thin films down to single layers of atoms across targeted electrodes. Experiments such as the effect of thin film alloys or added impurities on their superconductivity can be measured in situ with this process.

Flexible Chip Scale Package and Interconnect for Implantable MEMS Movable Microelectrodes for the Brain

PubMed Central

Jackson, Nathan; Muthuswamy, Jit

2009-01-01

We report here a novel approach called MEMS microflex interconnect (MMFI) technology for packaging a new generation of Bio-MEMS devices that involve movable microelectrodes implanted in brain tissue. MMFI addresses the need for (i) operating space for movable parts and (ii) flexible interconnects for mechanical isolation. We fabricated a thin polyimide substrate with embedded bond-pads, vias, and conducting traces for the interconnect with a backside dry etch, so that the flexible substrate can act as a thin-film cap for the MEMS package. A double gold stud bump rivet bonding mechanism was used to form electrical connections to the chip and also to provide a spacing of approximately 15–20 µm for the movable parts. The MMFI approach achieved a chip scale package (CSP) that is lightweight, biocompatible, having flexible interconnects, without an underfill. Reliability tests demonstrated minimal increases of 0.35 mΩ, 0.23 mΩ and 0.15 mΩ in mean contact resistances under high humidity, thermal cycling, and thermal shock conditions respectively. High temperature tests resulted in an increase in resistance of > 90 mΩ when aluminum bond pads were used, but an increase of ~ 4.2 mΩ with gold bond pads. The mean-time-to-failure (MTTF) was estimated to be at least one year under physiological conditions. We conclude that MMFI technology is a feasible and reliable approach for packaging and interconnecting Bio-MEMS devices. PMID:20160981

PbS-PbSe IR detector arrays

NASA Technical Reports Server (NTRS)

Barrett, John R. (Inventor)

1986-01-01

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chipping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

Miniature stick-packaging--an industrial technology for pre-storage and release of reagents in lab-on-a-chip systems.

PubMed

van Oordt, Thomas; Barb, Yannick; Smetana, Jan; Zengerle, Roland; von Stetten, Felix

2013-08-07

Stick-packaging of goods in tubular-shaped composite-foil pouches has become a popular technology for food and drug packaging. We miniaturized stick-packaging for use in lab-on-a-chip (LOAC) systems to pre-store and on-demand release the liquid and dry reagents in a volume range of 80-500 μl. An integrated frangible seal enables the pressure-controlled release of reagents and simplifies the layout of LOAC systems, thereby making the package a functional microfluidic release unit. The frangible seal is adjusted to defined burst pressures ranging from 20 to 140 kPa. The applied ultrasonic welding process allows the packaging of temperature sensitive reagents. Stick-packs have been successfully tested applying recovery tests (where 99% (STDV = 1%) of 250 μl pre-stored liquid is released), long-term storage tests (where there is loss of only <0.5% for simulated 2 years) and air transport simulation tests. The developed technology enables the storage of a combination of liquid and dry reagents. It is a scalable technology suitable for rapid prototyping and low-cost mass production.

Heterogeneously integrated microsystem-on-a-chip

DOEpatents

Chanchani, Rajen [Albuquerque, NM

2008-02-26

A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.

Cleanup Verification Package for the 118-F-1 Burial Ground

DOE Office of Scientific and Technical Information (OSTI.GOV)

E. J. Farris and H. M. Sulloway

2008-01-10

This cleanup verification package documents completion of remedial action for the 118-F-1 Burial Ground on the Hanford Site. This burial ground is a combination of two locations formerly called Minor Construction Burial Ground No. 2 and Solid Waste Burial Ground No. 2. This waste site received radioactive equipment and other miscellaneous waste from 105-F Reactor operations, including dummy elements and irradiated process tubing; gun barrel tips, steel sleeves, and metal chips removed from the reactor; filter boxes containing reactor graphite chips; and miscellaneous construction solid waste.

Hybrid-integrated coherent receiver using silica-based planar lightwave circuit technology

NASA Astrophysics Data System (ADS)

Kim, Jong-Hoi; Choe, Joong-Seon; Choi, Kwang-Seong; Youn, Chun-Ju; Kim, Duk-Jun; Jang, Sun-Hyok; Kwon, Yong-Hwan; Nam, Eun-Soo

2011-12-01

A hybrid-integrated coherent receiver module has been achieved using flip-chip bonding technology, consisting of a silica-based 90°-hybrid planar lightwave circuit (PLC) platform, a spot-size converter integrated waveguide photodiode (SSC-WG-PD), and a dual-channel transimpedance amplifier (TIA). The receiver module shows error-free operation up to 40Gb/s and OSNR sensitivity of 11.5 dB for BER = 10-3 at 25 Gb/s.

Intelligent structures technology

NASA Astrophysics Data System (ADS)

Crawley, Edward F.

1991-07-01

Viewgraphs on intelligent structures technology are presented. Topics covered include: embedding electronics; electrical and mechanical compatibility; integrated circuit chip packaged for embedding; embedding devices within composite structures; test of embedded circuit in G/E coupon; temperature/humidity/bias test; single-chip microcomputer control experiment; and structural shape determination.

Intelligent structures technology

NASA Technical Reports Server (NTRS)

Crawley, Edward F.

1991-01-01

Viewgraphs on intelligent structures technology are presented. Topics covered include: embedding electronics; electrical and mechanical compatibility; integrated circuit chip packaged for embedding; embedding devices within composite structures; test of embedded circuit in G/E coupon; temperature/humidity/bias test; single-chip microcomputer control experiment; and structural shape determination.

Identification of Bacterial Factors Involved in Type 1 Fimbria Expression using an Escherichia coli K12 Proteome Chip*

PubMed Central

Chen, Yi-Wen; Teng, Ching-Hao; Ho, Yu-Hsuan; Jessica Ho, Tien Yu; Huang, Wen-Chun; Hashimoto, Masayuki; Chiang, I-Yuan; Chen, Chien-Sheng

2014-01-01

Type 1 fimbriae are filamentous structures on Escherichia coli. These structures are important adherence factors. Because binding to the host cells is the first step of infection, type 1 fimbria is an important virulence factor of pathogenic E. coli. Expression of type 1 fimbria is regulated by a phase variation in which each individual bacterium can alternate between fimbriated (phase-ON) and nonfimbriated (phase-OFF) states. The phase variation is regulated by the flipping of the 314-bp fimS fragment, which contains the promoter driving the expression of the genes required for the synthesis of type 1 fimbria. Thus, the bacterial proteins able to interact with fimS are likely to be involved in regulating the expression of type 1 fimbria. To identify novel type 1 fimbria-regulating factors, we used an E. coli K12 proteome chip to screen for the bacterial factors able to interact with a 602-bp DNA fragment containing fimS and its adjacent regions. The Spr protein was identified by the proteome chip-based screening and further confirmed to be able to interact with fimS by electrophoretic mobility shift assay. Deletion of spr in the neonatal meningitis E. coli strain RS218 significantly increased the ratio of the bacterial colonies that contained the type 1 fimbria phase-ON cells on agar plates. In addition, Spr interfered with the interactions of fimS with the site-specific recombinases, FimB and FimE, which are responsible for mediating the flipping of fimS. These results suggest that Spr is involved in the regulation of type 1 fimbria expression through direct interaction with the invertible element fimS. These findings facilitate our understanding of the regulation of type 1 fimbria. PMID:24692643

Influence of different materials on the thermal behavior of a CDIP-8 ceramic package

NASA Astrophysics Data System (ADS)

Weide, Kirsten; Keck, Christian

1999-08-01

The temperature distribution inside a package is determined by the heat transfer from the package to the ambient, depending on the heat conductivities of the different used materials. With the help of finite element simulations the thermal behavior of the package can be characterized. In precise simulations convection and radiation effects have to be taken into account. In this paper the influence of different materials like the ceramic, the pin and die attach material and adhesive material between the chip and the die attach on the thermal resistance of the ceramic package will be investigated. A finite element model of the ceramic package including a voltage regulator on the chip was created. The simulations were carried out with the finite element program ANSYS. An easy way to take the radiation effect into account, which normally is difficult to handle in the simulation, will be shown. The results of the simulations are verified by infrared measurements. A comparison of the thermal resistance between the best case and worst case for different package materials was done. The thermal conductivity of the ceramic material shows the strongest influence on the thermal resistance.

Merging parallel optics packaging and surface mount technologies

NASA Astrophysics Data System (ADS)

Kopp, Christophe; Volpert, Marion; Routin, Julien; Bernabé, Stéphane; Rossat, Cyrille; Tournaire, Myriam; Hamelin, Régis

2008-02-01

Optical links are well known to present significant advantages over electrical links for very high-speed data rate at 10Gpbs and above per channel. However, the transition towards optical interconnects solutions for short and very short reach applications requires the development of innovative packaging solutions that would deal with very high volume production capability and very low cost per unit. Moreover, the optoelectronic transceiver components must be able to move from the edge to anywhere on the printed circuit board, for instance close to integrated circuits with high speed IO. In this paper, we present an original packaging design to manufacture parallel optic transceivers that are surface mount devices. The package combines highly integrated Multi-Chip-Module on glass and usual IC ceramics packaging. The use of ceramic and the development of sealing technologies achieve hermetic requirements. Moreover, thanks to a chip scale package approach the final device exhibits a much minimized footprint. One of the main advantages of the package is its flexibility to be soldered or plugged anywhere on the printed circuit board as any other electronic device. As a demonstrator we present a 2 by 4 10Gbps transceiver operating at 850nm.

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Li, K.; Shih, Y. C.

1992-01-01

Packaging schemes are developed that provide low-loss, hermetic enclosure for enhanced monolithic microwave and millimeter-wave integrated circuits. These package schemes are based on a fused quartz substrate material offering improved RF performance through 44 GHz. The small size and weight of the packages make them useful for a number of applications, including phased array antenna systems. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices.

A Comparative Study of Inspection Techniques for Array Packages

NASA Technical Reports Server (NTRS)

Mohammed, Jelila; Green, Christopher

2008-01-01

This viewgraph presentation reviews the inspection techniques for Column Grid Array (CGA) packages. The CGA is a method of chip scale packaging using high temperature solder columns to attach part to board. It is becoming more popular over other techniques (i.e. quad flat pack (QFP) or ball grid array (BGA)). However there are environmental stresses and workmanship challenges that require good inspection techniques for these packages.

Investigation Of The Effects Of Reflow Profile Parameters On Lead-free Solder Bump Volumes And Joint Integrity

NASA Astrophysics Data System (ADS)

Amalu, E. H.; Lui, Y. T.; Ekere, N. N.; Bhatti, R. S.; Takyi, G.

2011-01-01

The electronics manufacturing industry was quick to adopt and use the Surface Mount Technology (SMT) assembly technique on realization of its huge potentials in achieving smaller, lighter and low cost product implementations. Increasing global customer demand for miniaturized electronic products is a key driver in the design, development and wide application of high-density area array package format. Electronic components and their associated solder joints have reduced in size as the miniaturization trend in packaging continues to be challenged by printing through very small stencil apertures required for fine pitch flip-chip applications. At very narrow aperture sizes, solder paste rheology becomes crucial for consistent paste withdrawal. The deposition of consistent volume of solder from pad-to-pad is fundamental to minimizing surface mount assembly defects. This study investigates the relationship between volume of solder paste deposit (VSPD) and the volume of solder bump formed (VSBF) after reflow, and the effect of reflow profile parameters on lead-free solder bump formation and the associated solder joint integrity. The study uses a fractional factorial design (FFD) of 24-1 Ramp-Soak-Spike reflow profile, with all main effects and two-way interactions estimable to determine the optimal factorial combination. The results from the study show that the percentage change in the VSPD depends on the combination of the process parameters and reliability issues could become critical as the size of solder joints soldered on the same board assembly vary greatly. Mathematical models describe the relationships among VSPD, VSBF and theoretical volume of solder paste. Some factors have main effects across the volumes and a number of interactions exist among them. These results would be useful for R&D personnel in designing and implementing newer applications with finer-pitch interconnect.

Dose-dependent X-ray measurements using a 64×64 hybrid GaAs pixel detector with photon counting

NASA Astrophysics Data System (ADS)

Schwarz, C.; Campbell, M.; Goeppert, R.; Ludwig, J.; Mikulec, B.; Rogalla, M.; Runge, K.; Soeldner-Rembold, A.; Smith, K. M.; Snoeys, W.; Watt, J.

2001-03-01

New developments in medical imaging head towards semiconductor detectors flip-chip bonded to CMOS readout chips. In this work, detectors fabricated on SI-GaAs bulk material were bonded to Photon Counting Chips. This PCC consists of a matrix of 64×64 identical square pixels (170 μm×170 μm) with a 15-bit counter in each cell. We investigated the imaging properties of these detector systems under exposure of a dental X-ray tube. First, a dose calibration of the X-ray tube was performed. Fixed pattern noise in flood exposure images was determined for a fixed dose and an image correction method, which uses a gain map, was applied. For characterising the imaging properties, the signal-to-noise ratio (SNR) was calculated as function of exposure dose. Finally, the dynamic range of the system was estimated. Developed in the framework of the MEDIPIX collaboration: CERN, Universities of Freiburg, Glasgow, Naples and Pisa.

Enabling Large Focal Plane Arrays Through Mosaic Hybridization

NASA Technical Reports Server (NTRS)

Miller, TImothy M.; Jhabvala, Christine A.; Leong, Edward; Costen, Nicholas P.; Sharp, Elmer; Adachi, Tomoko; Benford, Dominic

2012-01-01

We have demonstrated advances in mosaic hybridization that will enable very large format far-infrared detectors. Specifically we have produced electrical detector models via mosaic hybridization yielding superconducting circuit paths by hybridizing separately fabricated sub-units onto a single detector unit. The detector model was made on a 100mm diameter wafer while four model readout quadrant chips were made from a separate 100mm wafer. The individually fabricated parts were hybridized using a flip-chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the model mosaic-hybrid detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently available.

Enabling Large Focal Plane Arrays through Mosaic Hybridization

NASA Technical Reports Server (NTRS)

Miller, Timothy M.; Jhabvala, Christine A.; Costen, Nick; Benford, Dominic J.

2012-01-01

We have demonstrated the hybridization of large mosaics of far-infrared detectors, joining separately fabricated sub-units into a single unit on a single, large substrate. We produced a single detector mockup on a 100mm diameter wafer and four mockup readout quadrant chips from a separate 100mm wafer. The individually fabricated parts were hybridized using a Suss FC150 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion (CTE) match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the mockup mosaic-hybridized detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently demonstrated.

Development of non-destructive evaluation system using an HTS-SQUID gradiometer for magnetized materials

NASA Astrophysics Data System (ADS)

Kawano, J.; Tsukamoto, A.; Adachi, S.; Oshikubo, Y.; Hato, T.; Tanabe, K.; Okamura, T.

We have developed a new eddy-current non-destructive evaluation (NDE) system using an HTS SQUID gradiometer with the aim of applying it to practical materials with magnetization. The new NDE system employs a LN2-cooled external Cu pickup coil and an HTS SQUID chip placed in a magnetic shield made of HTS material. The HTS SQUID chip consists of an HTS planar gradiometer manufactured by using a ramp-edge junction technology and a multi-turn HTS thin film input coil coupled with the flip-chip configuration. The first-order coaxial gradiometric Cu pickup coil with a diameter of 16 mm and the baseline of 5.6 mm was used in the present NDE experiments. By using this NDE system, we could observe defect-induced magnetic signals without an appreciable influence of magnetization up to 10 mT. We also examined the ability of detecting deep-lying defects and compared with the results obtained using our previous NDE system.

PICSiP: new system-in-package technology using a high bandwidth photonic interconnection layer for converged microsystems

NASA Astrophysics Data System (ADS)

Tekin, Tolga; Töpper, Michael; Reichl, Herbert

2009-05-01

Technological frontiers between semiconductor technology, packaging, and system design are disappearing. Scaling down geometries [1] alone does not provide improvement of performance, less power, smaller size, and lower cost. It will require "More than Moore" [2] through the tighter integration of system level components at the package level. System-in-Package (SiP) will deliver the efficient use of three dimensions (3D) through innovation in packaging and interconnect technology. A key bottleneck to the implementation of high-performance microelectronic systems, including SiP, is the lack of lowlatency, high-bandwidth, and high density off-chip interconnects. Some of the challenges in achieving high-bandwidth chip-to-chip communication using electrical interconnects include the high losses in the substrate dielectric, reflections and impedance discontinuities, and susceptibility to crosstalk [3]. Obviously, the incentive for the use of photonics to overcome the challenges and leverage low-latency and highbandwidth communication will enable the vision of optical computing within next generation architectures. Supercomputers of today offer sustained performance of more than petaflops, which can be increased by utilizing optical interconnects. Next generation computing architectures are needed with ultra low power consumption; ultra high performance with novel interconnection technologies. In this paper we will discuss a CMOS compatible underlying technology to enable next generation optical computing architectures. By introducing a new optical layer within the 3D SiP, the development of converged microsystems, deployment for next generation optical computing architecture will be leveraged.

Flexible Chip Scale Package and Interconnect for Implantable MEMS Movable Microelectrodes for the Brain.

PubMed

Jackson, Nathan; Muthuswamy, Jit

2009-04-01

We report here a novel approach called MEMS microflex interconnect (MMFI) technology for packaging a new generation of Bio-MEMS devices that involve movable microelectrodes implanted in brain tissue. MMFI addresses the need for (i) operating space for movable parts and (ii) flexible interconnects for mechanical isolation. We fabricated a thin polyimide substrate with embedded bond-pads, vias, and conducting traces for the interconnect with a backside dry etch, so that the flexible substrate can act as a thin-film cap for the MEMS package. A double gold stud bump rivet bonding mechanism was used to form electrical connections to the chip and also to provide a spacing of approximately 15-20 µm for the movable parts. The MMFI approach achieved a chip scale package (CSP) that is lightweight, biocompatible, having flexible interconnects, without an underfill. Reliability tests demonstrated minimal increases of 0.35 mΩ, 0.23 mΩ and 0.15 mΩ in mean contact resistances under high humidity, thermal cycling, and thermal shock conditions respectively. High temperature tests resulted in an increase in resistance of > 90 mΩ when aluminum bond pads were used, but an increase of ~ 4.2 mΩ with gold bond pads. The mean-time-to-failure (MTTF) was estimated to be at least one year under physiological conditions. We conclude that MMFI technology is a feasible and reliable approach for packaging and interconnecting Bio-MEMS devices.

ChAMP: updated methylation analysis pipeline for Illumina BeadChips.

PubMed

Tian, Yuan; Morris, Tiffany J; Webster, Amy P; Yang, Zhen; Beck, Stephan; Feber, Andrew; Teschendorff, Andrew E

2017-12-15

The Illumina Infinium HumanMethylationEPIC BeadChip is the new platform for high-throughput DNA methylation analysis, effectively doubling the coverage compared to the older 450 K array. Here we present a significantly updated and improved version of the Bioconductor package ChAMP, which can be used to analyze EPIC and 450k data. Many enhanced functionalities have been added, including correction for cell-type heterogeneity, network analysis and a series of interactive graphical user interfaces. ChAMP is a BioC package available from https://bioconductor.org/packages/release/bioc/html/ChAMP.html. a.teschendorff@ucl.ac.uk or s.beck@ucl.ac.uk or a.feber@ucl.ac.uk. Supplementary data are available at Bioinformatics online. © The Author(s) 2017. Published by Oxford University Press.

NSC 800, 8-bit CMOS microprocessor

NASA Technical Reports Server (NTRS)

Suszko, S. F.

1984-01-01

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Chip-on-Board Technology 1996 Year-end Report (Design, Manufacturing, and Reliability Study)

NASA Technical Reports Server (NTRS)

Le, Binh Q.; Nhan, Elbert; Maurer, Richard H.; Lew, Ark L.; Lander, Juan R.

1996-01-01

The major impetus for flight qualifying Chip-On-Board (COB) packaging technology is the shift in emphasis for space missions to smaller, better, and cheaper spacecraft and satellites resulting from the NASA New Millenium initiative and similar requirements in DoD-sponsored programs. The most important benefit that can potentially be derived from miniaturizing spacecraft and satellites is the significant cost saving realizable if a smaller launch vehicle may be employed. Besides the program cost saving, there are several other advantages to building COB-based space hardware. First, once a well-controlled process is established, COB can be low cost compared to standard Multi-Chip Module (MCM) technology. This cost competitiveness is regarded as a result of the generally greater availability and lower cost of Known Good Die (KGD). Coupled with the elimination of the first level of packaging (chip package), compact, high-density circuit boards can be realized with Printed Wiring Boards (PWB) that can now be made with ever-decreasing feature size in line width and via hole. Since the COB packaging technique in this study is based mainly on populating bare dice on a suitable multi-layer laminate substrate which is not hermetically sealed, die coating for protection from the environment is required. In recent years, significant improvements have been made in die coating materials which further enhance the appeal of COB. Hysol epoxies, silicone, parylene and silicon nitride are desirable because of their compatible Thermal Coefficient of Expansion (TCE) and good moisture resistant capability. These die coating materials have all been used in the space and other industries with varying degrees of success. COB technology, specifically siliconnitride coated hardware, has been flown by Lockheed on the Polar satellite. In addition, DARPA has invested a substantial amount of resources on MCM and COB-related activities recently. With COB on the verge of becoming a dominant player in DoD programs, DARPA is increasing its support of the availability of KGDs which will help decrease their cost. Aside from the various major developments and trends in the space and defense industries that are favorable to the acceptance and widespread use of'COB packaging technology, implementing COB can be appealing in other aspects. Since the interconnection interface is usually the weak link in a system, the overall circuit or system reliability may actually be improved because of the elimination of a level of interconnect/packaging at the chip. With COB, mixing packaging technologies is possible. Because some devices are only available in commercial plastic packages, populating a multi-layer laminate substrate with both bare dice and plastic-package parts is inevitable. Another attractive feature of COB is that re-workability is possible if die coating is applied only on the die top. This method allows local replacement of individual dice that were found to be defective instead of replacing an entire board. In terms of thermal management, unpackaged devices offer a shorter thermal resistance path than their packaged counterparts thereby improving thermal sinking and heat removal from the parts.

Visual and x-ray inspection characteristics of eutectic and lead free assemblies

NASA Technical Reports Server (NTRS)

Ghaffarian, R.

2003-01-01

For high reliability applications, visual inspection has been the key technique for most conventional electronic package assemblies. Now, the use of x-ray technique has become an additional inspection requirement for quality control and detection of unique defects due to manufacturing of advanced electronic array packages such as ball grid array (BGAs) and chip scale packages (CSPs).

An ultra-compact and low-power oven-controlled crystal oscillator design for precision timing applications.

PubMed

Lim, Jaehyun; Kim, Hyunsoo; Jackson, Thomas; Choi, Kyusun; Kenny, David

2010-09-01

A novel design for a chip-scale miniature oven-controlled crystal oscillator (OCXO) is presented. In this design, all the main components of an OCXO--consisting of an oscillator, a temperature sensor, a heater, and temperature-control circuitry--are integrated on a single CMOS chip. The OCXO package size can be reduced significantly with this design, because the resonator does not require a separate package and most of the circuitry is integrated on a single CMOS chip. Other characteristics such as power consumption and warm-up time are also improved. Two different types of quartz resonators, an AT-cut tab mesa-type quartz crystal and a frame enclosed resonator, allow miniaturization of the OCXO structure. Neither of these quartz resonator types requires a separate package inside the oven structure; therefore, they can each be directly integrated with the custom-designed CMOS chip. The miniature OCXO achieves a frequency stability of +/- 0.35 ppm with an AT-cut tab mesa-type quartz crystal in the temperature range of 0 °C to 60 °C. The maximum power consumption of this miniature OCXO is 1.2 W at start-up and 303 mW at steady state. The warm-up time to reach the steady state is 190 s. These results using the proposed design are better than or the same as high-frequency commercial OCXOs.

Innovative on-chip packaging applied to uncooled IRFPA

NASA Astrophysics Data System (ADS)

Dumont, Geoffroy; Arnaud, Agnès; Impérinetti, Pierre; Vialle, Claire; Rabaud, Wilfried; Goudon, Valérie; Yon, Jean-Jacques

2008-04-01

The Laboratoire Infrarouge (LIR) of the Laboratoire d'Electronique et de Technologie de l'Information (LETI) has been involved in the development of microbolometers for over fifteen years. Two generations of technology have been transferred to ULIS and LETI is still working to improve performances of low cost detectors. Simultaneously, packaging still represents a significant part of detectors price. Reducing production costs would contribute to keep on extending applications of uncooled IRFPA to high volume markets like automotive. Therefore LETI is developing an on-chip packaging technology dedicated to microbolometers. This paper presents an original microcap structure that enables the use of IR window materials as sealing layers to maintain the expected vacuum level. The modelling and integration of an IR window suitable for this structure is also presented. This monolithic packaging technology is performed in a standard collective way, in continuation of bolometers' technology. The CEA-LETI, MINATEC presents status of these developments concerning this innovating technology including optical simulations results and SEM views of technical realizations.

Botulism challenge studies of a modified atmosphere package for fresh mussels: inoculated pack studies.

PubMed

Newell, C R; Ma, Li; Doyle, Michael

2012-06-01

A series of botulism challenge studies were performed to determine the possibility of production of botulinum toxin in mussels (Mytilus edulis) held under a commercial high-oxygen (60 to 65% O(2)), modified atmosphere packaging (MAP) condition. Spore mixtures of six strains of nonproteolytic Clostridium botulinum were introduced into mussel MAP packages receiving different packaging buffers with or without the addition of lactic acid bacteria. Dye studies and package flipping trials were conducted to ensure internalization of spores by packed mussels. Inoculated mussel packages were stored at normal (4°C) and abusive (12°C) temperatures for 21 and 13 days, respectively, which were beyond the packaged mussels' intended shelf life. Microbiological and chemical analyses were conducted at predetermined intervals (a total of five sampling times at each temperature), including total aerobic plate counts, C. botulinum counts, lactic acid bacterial counts, package headspace gas composition, pH of packaging buffer and mussel meat, and botulinum toxin assays of packaging buffer and mussel meat. Results revealed that C. botulinum inoculated in fresh mussels packed under MAP packaging did not produce toxin, even at an abusive storage temperature and when held beyond their shelf life. No evidence was found that packaging buffers or gas composition influenced the lack of botulinum toxin production in packed mussels.

Alumina Based 500 C Electronic Packaging Systems and Future Development

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu

2012-01-01

NASA space and aeronautical missions for probing the inner solar planets as well as for in situ monitoring and control of next-generation aeronautical engines require high-temperature environment operable sensors and electronics. A 96% aluminum oxide and Au thick-film metallization based packaging system including chip-level packages, printed circuit board, and edge-connector is in development for high temperature SiC electronics. An electronic packaging system based on this material system was successfully tested and demonstrated with SiC electronics at 500 C for over 10,000 hours in laboratory conditions previously. In addition to the tests in laboratory environments, this packaging system has more recently been tested with a SiC junction field effect transistor (JFET) on low earth orbit through the NASA Materials on the International Space Station Experiment 7 (MISSE7). A SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE7 suite to International Space Station via a Shuttle mission and tested on the orbit for eighteen months. A summary of results of tests in both laboratory and space environments will be presented. The future development of alumina based high temperature packaging using co-fired material systems for improved performance at high temperature and more feasible mass production will also be discussed.

Standard semiconductor packaging for high-reliability low-cost MEMS applications

NASA Astrophysics Data System (ADS)

Harney, Kieran P.

2005-01-01

Microelectronic packaging technology has evolved over the years in response to the needs of IC technology. The fundamental purpose of the package is to provide protection for the silicon chip and to provide electrical connection to the circuit board. Major change has been witnessed in packaging and today wafer level packaging technology has further revolutionized the industry. MEMS (Micro Electro Mechanical Systems) technology has created new challenges for packaging that do not exist in standard ICs. However, the fundamental objective of MEMS packaging is the same as traditional ICs, the low cost and reliable presentation of the MEMS chip to the next level interconnect. Inertial MEMS is one of the best examples of the successful commercialization of MEMS technology. The adoption of MEMS accelerometers for automotive airbag applications has created a high volume market that demands the highest reliability at low cost. The suppliers to these markets have responded by exploiting standard semiconductor packaging infrastructures. However, there are special packaging needs for MEMS that cannot be ignored. New applications for inertial MEMS devices are emerging in the consumer space that adds the imperative of small size to the need for reliability and low cost. These trends are not unique to MEMS accelerometers. For any MEMS technology to be successful the packaging must provide the basic reliability and interconnection functions, adding the least possible cost to the product. This paper will discuss the evolution of MEMS packaging in the accelerometer industry and identify the main issues that needed to be addressed to enable the successful commercialization of the technology in the automotive and consumer markets.

Standard semiconductor packaging for high-reliability low-cost MEMS applications

NASA Astrophysics Data System (ADS)

Harney, Kieran P.

2004-12-01

Microelectronic packaging technology has evolved over the years in response to the needs of IC technology. The fundamental purpose of the package is to provide protection for the silicon chip and to provide electrical connection to the circuit board. Major change has been witnessed in packaging and today wafer level packaging technology has further revolutionized the industry. MEMS (Micro Electro Mechanical Systems) technology has created new challenges for packaging that do not exist in standard ICs. However, the fundamental objective of MEMS packaging is the same as traditional ICs, the low cost and reliable presentation of the MEMS chip to the next level interconnect. Inertial MEMS is one of the best examples of the successful commercialization of MEMS technology. The adoption of MEMS accelerometers for automotive airbag applications has created a high volume market that demands the highest reliability at low cost. The suppliers to these markets have responded by exploiting standard semiconductor packaging infrastructures. However, there are special packaging needs for MEMS that cannot be ignored. New applications for inertial MEMS devices are emerging in the consumer space that adds the imperative of small size to the need for reliability and low cost. These trends are not unique to MEMS accelerometers. For any MEMS technology to be successful the packaging must provide the basic reliability and interconnection functions, adding the least possible cost to the product. This paper will discuss the evolution of MEMS packaging in the accelerometer industry and identify the main issues that needed to be addressed to enable the successful commercialization of the technology in the automotive and consumer markets.

Evaluation of copy number variation detection for a SNP array platform

PubMed Central

2014-01-01

Background Copy Number Variations (CNVs) are usually inferred from Single Nucleotide Polymorphism (SNP) arrays by use of some software packages based on given algorithms. However, there is no clear understanding of the performance of these software packages; it is therefore difficult to select one or several software packages for CNV detection based on the SNP array platform. We selected four publicly available software packages designed for CNV calling from an Affymetrix SNP array, including Birdsuite, dChip, Genotyping Console (GTC) and PennCNV. The publicly available dataset generated by Array-based Comparative Genomic Hybridization (CGH), with a resolution of 24 million probes per sample, was considered to be the “gold standard”. Compared with the CGH-based dataset, the success rate, average stability rate, sensitivity, consistence and reproducibility of these four software packages were assessed compared with the “gold standard”. Specially, we also compared the efficiency of detecting CNVs simultaneously by two, three and all of the software packages with that by a single software package. Results Simply from the quantity of the detected CNVs, Birdsuite detected the most while GTC detected the least. We found that Birdsuite and dChip had obvious detecting bias. And GTC seemed to be inferior because of the least amount of CNVs it detected. Thereafter we investigated the detection consistency produced by one certain software package and the rest three software suits. We found that the consistency of dChip was the lowest while GTC was the highest. Compared with the CNVs detecting result of CGH, in the matching group, GTC called the most matching CNVs, PennCNV-Affy ranked second. In the non-overlapping group, GTC called the least CNVs. With regards to the reproducibility of CNV calling, larger CNVs were usually replicated better. PennCNV-Affy shows the best consistency while Birdsuite shows the poorest. Conclusion We found that PennCNV outperformed the other three packages in the sensitivity and specificity of CNV calling. Obviously, each calling method had its own limitations and advantages for different data analysis. Therefore, the optimized calling methods might be identified using multiple algorithms to evaluate the concordance and discordance of SNP array-based CNV calling. PMID:24555668

Rutger's CAM2000 chip architecture

NASA Technical Reports Server (NTRS)

Smith, Donald E.; Hall, J. Storrs; Miyake, Keith

1993-01-01

This report describes the architecture and instruction set of the Rutgers CAM2000 memory chip. The CAM2000 combines features of Associative Processing (AP), Content Addressable Memory (CAM), and Dynamic Random Access Memory (DRAM) in a single chip package that is not only DRAM compatible but capable of applying simple massively parallel operations to memory. This document reflects the current status of the CAM2000 architecture and is continually updated to reflect the current state of the architecture and instruction set.

AIN-Coated Al(2)O(3) Substrates For Electronic Circuits

NASA Technical Reports Server (NTRS)

Kolawa, Elzbieta; Lowry, Lynn; Herman, Martin; Lee, Karen

1996-01-01

Type of improved ceramic substrate for high-frequency, high-power electronic circuits combines relatively high thermal conductivity of aluminum nitride with surface smoothness of alumina. Consists of 15-micrometer layer of AIN deposited on highly polished alumina. Used for packaging millimeter-wave gallium arsenide transmitter chips, power silicon chips, and like.

From functional structure to packaging: full-printing fabrication of a microfluidic chip.

PubMed

Zheng, Fengyi; Pu, Zhihua; He, Enqi; Huang, Jiasheng; Yu, Bocheng; Li, Dachao; Li, Zhihong

2018-05-24

This paper presents a concept of a full-printing methodology aiming at convenient and fast fabrication of microfluidic devices. For the first time, we achieved a microfluidic biochemical sensor with all functional structures fabricated by inkjet printing, including electrodes, immobilized enzymes, microfluidic components and packaging. With the cost-effective and rapid process, this method provides the possibility of quick model validation of a novel lab-on-chip system. In this study, a three-electrode electrochemical system was integrated successfully with glucose oxidase immobilization gel and sealed in an ice channel, forming a disposable microfluidic sensor for glucose detection. This fully-printed chip was characterized and showed good sensitivity and a linear section at a low-level concentration of glucose (0-10 mM). With the aid of automatic equipment, the fully-printed sensor can be massively produced with low cost.

Color design model of high color rendering index white-light LED module.

PubMed

Ying, Shang-Ping; Fu, Han-Kuei; Hsieh, Hsin-Hsin; Hsieh, Kun-Yang

2017-05-10

The traditional white-light light-emitting diode (LED) is packaged with a single chip and a single phosphor but has a poor color rendering index (CRI). The next-generation package comprises two chips and a single phosphor, has a high CRI, and retains high luminous efficacy. This study employs two chips and two phosphors to improve the diode's color tunability with various proportions of two phosphors and various densities of phosphor in the silicone used. A color design model is established for color fine-tuning of the white-light LED module. The maximum difference between the measured and color-design-model simulated CIE 1931 color coordinates is approximately 0.0063 around a correlated color temperature (CCT) of 2500 K. This study provides a rapid method to obtain the color fine-tuning of a white-light LED module with a high CRI and luminous efficacy.

Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

PubMed

Shen, Wen-Wei; Lin, Yu-Min; Wu, Sheng-Tsai; Lee, Chia-Hsin; Huang, Shin-Yi; Chang, Hsiang-Hung; Chang, Tao-Chih; Chen, Kuan-Neng

2018-08-01

In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

puma: a Bioconductor package for propagating uncertainty in microarray analysis.

PubMed

Pearson, Richard D; Liu, Xuejun; Sanguinetti, Guido; Milo, Marta; Lawrence, Neil D; Rattray, Magnus

2009-07-09

Most analyses of microarray data are based on point estimates of expression levels and ignore the uncertainty of such estimates. By determining uncertainties from Affymetrix GeneChip data and propagating these uncertainties to downstream analyses it has been shown that we can improve results of differential expression detection, principal component analysis and clustering. Previously, implementations of these uncertainty propagation methods have only been available as separate packages, written in different languages. Previous implementations have also suffered from being very costly to compute, and in the case of differential expression detection, have been limited in the experimental designs to which they can be applied. puma is a Bioconductor package incorporating a suite of analysis methods for use on Affymetrix GeneChip data. puma extends the differential expression detection methods of previous work from the 2-class case to the multi-factorial case. puma can be used to automatically create design and contrast matrices for typical experimental designs, which can be used both within the package itself but also in other Bioconductor packages. The implementation of differential expression detection methods has been parallelised leading to significant decreases in processing time on a range of computer architectures. puma incorporates the first R implementation of an uncertainty propagation version of principal component analysis, and an implementation of a clustering method based on uncertainty propagation. All of these techniques are brought together in a single, easy-to-use package with clear, task-based documentation. For the first time, the puma package makes a suite of uncertainty propagation methods available to a general audience. These methods can be used to improve results from more traditional analyses of microarray data. puma also offers improvements in terms of scope and speed of execution over previously available methods. puma is recommended for anyone working with the Affymetrix GeneChip platform for gene expression analysis and can also be applied more generally.

Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails

NASA Astrophysics Data System (ADS)

Hashida, Takushi; Nagata, Makoto

Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100Mbps. A pair of transceivers consumes 1.35mA from 3.3V, at 130Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50dB.

System on a Chip (SoC) Overview

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.

2010-01-01

System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions all on a single chip substrate. Complexity drives it all: Radiation tolerance and testability are challenges for fault isolation, propagation, and validation. Bigger single silicon die than flown before and technology is scaling below 90nm (new qual methods). Packages have changed and are bigger and more difficult to inspect, test, and understand. Add in embedded passives. Material interfaces are more complex (underfills, processing). New rules for board layouts. Mechanical and thermal designs, etc.

Pressure driven digital logic in PDMS based microfluidic devices fabricated by multilayer soft lithography.

PubMed

Devaraju, Naga Sai Gopi K; Unger, Marc A

2012-11-21

Advances in microfluidics now allow an unprecedented level of parallelization and integration of biochemical reactions. However, one challenge still faced by the field has been the complexity and cost of the control hardware: one external pressure signal has been required for each independently actuated set of valves on chip. Using a simple post-modification to the multilayer soft lithography fabrication process, we present a new implementation of digital fluidic logic fully analogous to electronic logic with significant performance advances over the previous implementations. We demonstrate a novel normally closed static gain valve capable of modulating pressure signals in a fashion analogous to an electronic transistor. We utilize these valves to build complex fluidic logic circuits capable of arbitrary control of flows by processing binary input signals (pressure (1) and atmosphere (0)). We demonstrate logic gates and devices including NOT, NAND and NOR gates, bi-stable flip-flops, gated flip-flops (latches), oscillators, self-driven peristaltic pumps, delay flip-flops, and a 12-bit shift register built using static gain valves. This fluidic logic shows cascade-ability, feedback, programmability, bi-stability, and autonomous control capability. This implementation of fluidic logic yields significantly smaller devices, higher clock rates, simple designs, easy fabrication, and integration into MSL microfluidics.

Consortia for Known Good Die (KGD), phase 1

NASA Astrophysics Data System (ADS)

Andrews, Marshall; Carey, David; Fellows, Mary M.; Gilg, Larry; Murphy, Cindy; Noddings, Chad; Pitts, Greg; Rathmell, Claude; Spooner, Charles

1994-02-01

This report describes the results of Phase 1 of the Infrastructure for KGD program at MCC. The objective of the work is to resolve the issues for supplying and procuring Known Good Die (KGD) in a way that fosters industry acceptance and confidence in Application Specific Electronic Modules (ASEM's for military systems) and MultiChip Modules (MCM's for commercial systems). This report is divided into four sections. Section 1 describes the technical assessment of proposed industry approaches to KGD implementation. Section 2 of the report contains an outline for the plan for industry and government cooperation for the demonstration, validation, and implementation of KGD methodologies identified in this Phase 1 study. Section 3 of the report contains the industry-generated requirements for KGD implementation. Section IV of the report contains the KGD specifications for TAB and flip chip IC's.

32 x 16 CMOS smart pixel array for optical interconnects

NASA Astrophysics Data System (ADS)

Kim, Jongwoo; Guilfoyle, Peter S.; Stone, Richard V.; Hessenbruch, John M.; Choquette, Kent D.; Kiamilev, Fouad E.

2000-05-01

Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32 X 16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 micrometers technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 micrometers technology.

Design and fabrication of a foldable 3D silicon based package for solid state lighting applications

NASA Astrophysics Data System (ADS)

Sokolovskij, R.; Liu, P.; van Zeijl, H. W.; Mimoun, B.; Zhang, G. Q.

2015-05-01

Miniaturization of solid state lighting (SSL) luminaires as well as reduction of packaging and assembly costs are of prime interest for the SSL lighting industry. A novel silicon based LED package for lighting applications is presented in this paper. The proposed design consists of 5 rigid Si tiles connected by flexible polyimide hinges with embedded interconnects (ICs). Electrical, optical and thermal characteristics were taken into consideration during design. The fabrication process involved polyimide (PI) application and patterning, aluminium interconnect integration in the flexible hinge, LED reflector cavity formation and metalization followed by through wafer DRIE etching for chip formation and release. A method to connect chip front to backside without TSVs was also integrated into the process. Post-fabrication wafer level assembly included LED mounting and wirebond, phosphor-based colour conversion and silicone encapsulation. The package formation was finalized by vacuum assisted wrapping around an assembly structure to form a 3D geometry, which is beneficial for omnidirectional lighting. Bending tests were performed on the flexible ICs and optical performance at different temperatures was evaluated. It is suggested that 3D packages can be expanded to platforms for miniaturized luminaire applications by combining monolithic silicon integration and system-in-package (SiP) technologies.

Cost-effective method of manufacturing a 3D MEMS optical switch

NASA Astrophysics Data System (ADS)

Carr, Emily; Zhang, Ping; Keebaugh, Doug; Chau, Kelvin

2009-02-01

growth of data and video transport networks. All-optical switching eliminates the need for optical-electrical conversion offering the ability to switch optical signals transparently: independent of data rates, formats and wavelength. It also provides network operators much needed automation capabilities to create, monitor and protect optical light paths. To further accelerate the market penetration, it is necessary to identify a path to reduce the manufacturing cost significantly as well as enhance the overall system performance, uniformity and reliability. Currently, most MEMS optical switches are assembled through die level flip-chip bonding with either epoxies or solder bumps. This is due to the alignment accuracy requirements of the switch assembly, defect matching of individual die, and cost of the individual components. In this paper, a wafer level assembly approach is reported based on silicon fusion bonding which aims to reduce the packaging time, defect count and cost through volume production. This approach is successfully demonstrated by the integration of two 6-inch wafers: a mirror array wafer and a "snap-guard" wafer, which provides a mechanical structure on top of the micromirror to prevent electrostatic snap-down. The direct silicon-to-silicon bond eliminates the CTEmismatch and stress issues caused by non-silicon bonding agents. Results from a completed integrated switch assembly will be presented, which demonstrates the reliability and uniformity of some key parameters of this MEMS optical switch.

Organic electronics based pressure sensor towards intracranial pressure monitoring

NASA Astrophysics Data System (ADS)

Rai, Pratyush; Varadan, Vijay K.

2010-04-01

The intra-cranial space, which houses the brain, contains cerebrospinal fluid (CSF) that acts as a fluid suspension medium for the brain. The CSF is always in circulation, is secreted in the cranium and is drained out through ducts called epidural veins. The venous drainage system has inherent resistance to the flow. Pressure is developed inside the cranium, which is similar to a rigid compartment. Normally a pressure of 5-15 mm Hg, in excess of atmospheric pressure, is observed at different locations inside the cranium. Increase in Intra-Cranial Pressure (ICP) can be caused by change in CSF volume caused by cerebral tumors, meningitis, by edema of a head injury or diseases related to cerebral atrophy. Hence, efficient ways of monitoring ICP need to be developed. A sensor system and monitoring scheme has been discussed here. The system architecture consists of a membrane less piezoelectric pressure sensitive element, organic thin film transistor (OTFT) based signal transduction, and signal telemetry. The components were fabricated on flexible substrate and have been assembled using flip-chip packaging technology. Material science and fabrication processes, subjective to the device performance, have been discussed. Capability of the device in detecting pressure variation, within the ICP pressure range, is investigated and applicability of measurement scheme to medical conditions has been argued for. Also, applications of such a sensor-OTFT assembly for logic sensor switching and patient specific-secure monitoring system have been discussed.

GaN-based flip-chip LEDs with highly reflective ITO/DBR p-type and via hole-based n-type contacts for enhanced current spreading and light extraction

NASA Astrophysics Data System (ADS)

Zhou, Shengjun; Zheng, Chenju; Lv, Jiajiang; Gao, Yilin; Wang, Ruiqing; Liu, Sheng

2017-07-01

We demonstrate GaN-based double-layer electrode flip-chip light-emitting diodes (DLE-FCLED) with highly reflective indium-tin oxide (ITO)/distributed bragg reflector (DBR) p-type contact and via hole-based n-type contacts. Transparent thin ITO in combination with TiO2/SiO2 DBR is used for reflective p-type ohmic contact, resulting in a significant reduction in absorption of light by opaque metal electrodes. The finely distributed via hole-based n-type contacts are formed on the n-GaN layer by etching via holes through p-GaN and multiple quantum well (MQW) active layer, leading to reduced lateral current spreading length, and hence alleviated current crowding effect. The forward voltage of the DLE-FCLED is 0.31 V lower than that of the top-emitting LED at 90 mA. The light output power of DLE-FCLED is 15.7% and 80.8% higher than that of top-emitting LED at 90 mA and 300 mA, respectively. Compared to top- emitting LED, the external quantum efficiency (EQE) of DLE-FCLED is enhanced by 15.4% and 132% at 90 mA and 300 mA, respectively. The maximum light output power of the DLE-FCLED obtained at 195.6 A/cm2 is 1.33 times larger than that of the top-emitting LED obtained at 93 A/cm2.

Numerical and experimental investigation of GaN-based flip-chip light-emitting diodes with highly reflective Ag/TiW and ITO/DBR Ohmic contacts.

PubMed

Zhou, Shengjun; Liu, Xingtong; Gao, Yilin; Liu, Yingce; Liu, Mengling; Liu, Zongyuan; Gui, Chengqun; Liu, Sheng

2017-10-30

We demonstrate two types of GaN-based flip-chip light-emitting diodes (FCLEDs) with highly reflective Ag/TiW and indium-tin oxide (ITO)/distributed Bragg reflector (DBR) p-type Ohmic contacts. We show that a direct Ohmic contact to p-GaN layer using pure Ag is obtained when annealed at 600°C in N 2 ambient. A TiW diffusion barrier layer covered onto Ag is used to suppress the agglomeration of Ag and thus maintain high reflectance of Ag during high temperature annealing process. We develop a strip-shaped SiO 2 current blocking layer beneath the ITO/DBR to alleviate current crowding occurring in FCLED with ITO/DBR. Owing to negligibly small spreading resistance of Ag, however, our combined numerical and experimental results show that the FCLED with Ag/TiW has a more favorable current spreading uniformity in comparison to the FCLED with ITO/DBR. As a result, the light output power of FCLED with Ag/TiW is 7.5% higher than that of FCLED with ITO/DBR at 350 mA. The maximum output power of the FCLED with Ag/TiW obtained at 305.6 A/cm 2 is 29.3% larger than that of the FCLED with ITO/DBR obtained at 278.9 A/cm 2 . The improvement appears to be due to the enhanced current spreading and higher optical reflectance provided by the Ag/TiW.

Micro packaged MEMS pressure sensor for intracranial pressure measurement

NASA Astrophysics Data System (ADS)

Xiong, Liu; Yan, Yao; Jiahao, Ma; Yanhang, Zhang; Qian, Wang; Zhaohua, Zhang; Tianling, Ren

2015-06-01

This paper presents a micro packaged MEMS pressure sensor for intracranial pressure measurement which belongs to BioMEMS. It can be used in lumbar puncture surgery to measure intracranial pressure. Miniaturization is key for lumbar puncture surgery because the sensor must be small enough to allow it be placed in the reagent chamber of the lumbar puncture needle. The size of the sensor is decided by the size of the sensor chip and package. Our sensor chip is based on silicon piezoresistive effect and the size is 400 × 400 μm2. It is much smaller than the reported polymer intracranial pressure sensors such as liquid crystal polymer sensors. In terms of package, the traditional dual in-line package obviously could not match the size need, the minimal size of recently reported MEMS-based intracranial pressure sensors after packaging is 10 × 10 mm2. In this work, we are the first to introduce a quad flat no-lead package as the package form of piezoresistive intracranial pressure sensors, the whole size of the sensor is minimized to only 3 × 3 mm2. Considering the liquid measurement environment, the sensor is gummed and waterproof performance is tested; the sensitivity of the sensor is 0.9 × 10-2 mV/kPa. Project supported by the National Natural Science Foundation of China (Nos. 61025021, 61434001), and the ‘Thousands Talents’ Program for Pioneer Researchers and Its Innovation Team, China.

Electromigration Failure Mechanism in Sn-Cu Solder Alloys with OSP Cu Surface Finish

NASA Astrophysics Data System (ADS)

Chu, Ming-Hui; Liang, S. W.; Chen, Chih; Huang, Annie T.

2012-09-01

Organic solderable preservative (OSP) has been adopted as the Cu substrate surface finish in flip-chip solder joints for many years. In this study, the electromigration behavior of lead-free Sn-Cu solder alloys with thin-film under bump metallization and OSP surface finish was investigated. The results showed that severe damage occurred on the substrate side (cathode side), whereas the damage on the chip side (cathode side) was not severe. The damage on the substrate side included void formation, copper dissolution, and formation of intermetallic compounds (IMCs). The OSP Cu interface on the substrate side became the weakest point in the solder joint even when thin-film metallization was used on the chip side. Three-dimensional simulations were employed to investigate the current density distribution in the area between the OSP Cu surface finish and the solder. The results indicated that the current density was higher along the periphery of the bonding area between the solder and the Cu pad, consistent with the area of IMC and void formation in our experimental results.

Enabling Large Focal Plane Arrays Through Mosaic Hybridization

NASA Technical Reports Server (NTRS)

Miller, Timothy M.; Jhabvala, Christine A.; Leong, Edward; Costen, Nick P.; Sharp, Elmer; Adachi, Tomoko; Benford, Dominic J.

2012-01-01

We have demonstrated advances in mosaic hybridization that will enable very large format far-infrared detectors. Specifically we have produced electrical detector models via mosaic hybridization yielding superconducting circuit patbs by hybridizing separately fabricated sub-units onto a single detector unit. The detector model was made on a 100mm diameter wafer while four model readout quadrant chips were made from a separate 100mm wafer. The individually fabric.ted parts were hybridized using a Suss FCI50 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the model mosaic-hybrid detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently available.

An integrated workflow for analysis of ChIP-chip data.

PubMed

Weigelt, Karin; Moehle, Christoph; Stempfl, Thomas; Weber, Bernhard; Langmann, Thomas

2008-08-01

Although ChIP-chip is a powerful tool for genome-wide discovery of transcription factor target genes, the steps involving raw data analysis, identification of promoters, and correlation with binding sites are still laborious processes. Therefore, we report an integrated workflow for the analysis of promoter tiling arrays with the Genomatix ChipInspector system. We compare this tool with open-source software packages to identify PU.1 regulated genes in mouse macrophages. Our results suggest that ChipInspector data analysis, comparative genomics for binding site prediction, and pathway/network modeling significantly facilitate and enhance whole-genome promoter profiling to reveal in vivo sites of transcription factor-DNA interactions.

Thin-film decoupling capacitors for multi-chip modules

NASA Astrophysics Data System (ADS)

Dimos, D.; Lockwood, S. J.; Schwartz, R. W.; Rogers, M. S.

Thin-film decoupling capacitors based on ferroelectric lead lanthanum zirconate titanate (PLZT) films are being developed for use in advanced packages, such as multi-chip modules. These thin-film decoupling capacitors are intended to replace multi-layer ceramic capacitors for certain applications, since they can be more fully integrated into the packaging architecture. The increased integration that can be achieved should lead to decreased package volume and improved high-speed performance, due to a decrease in interconnect inductance. PLZT films are fabricated by spin coating using metal carboxylate/alkoxide solutions. These films exhibit very high dielectric constants ((var epsilon) greater than or equal to 900), low dielectric losses (tan(delta) = 0.01), excellent insulation resistances (rho greater than 10(exp 13) (Omega)-cm at 125 C), and good breakdown field strengths (E(sub B) = 900 kV/cm). For integrated circuit applications, the PLZT dielectric is less than 1 micron thick, which results in a large capacitance/area (8-9 nF/sq mm). The thin-film geometry and processing conditions also make these capacitors suitable for direct incorporation onto integrated circuits and for packages that require embedded components.

Integrated Electrode Arrays for Neuro-Prosthetic Implants

NASA Technical Reports Server (NTRS)

Brandon, Erik; Mojarradi, Mohammede

2003-01-01

Arrays of electrodes integrated with chip-scale packages and silicon-based integrated circuits have been proposed for use as medical electronic implants, including neuro-prosthetic devices that might be implanted in brains of patients who suffer from strokes, spinal-cord injuries, or amyotrophic lateral sclerosis. The electrodes of such a device would pick up signals from neurons in the cerebral cortex, and the integrated circuit would perform acquisition and preprocessing of signal data. The output of the integrated circuit could be used to generate, for example, commands for a robotic arm. Electrode arrays capable of acquiring electrical signals from neurons already exist, but heretofore, there has been no convenient means to integrate these arrays with integrated-circuit chips. Such integration is needed in order to eliminate the need for the extensive cabling now used to pass neural signals to data-acquisition and -processing equipment outside the body. The proposed integration would enable progress toward neuro-prostheses that would be less restrictive of patients mobility. An array of electrodes would comprise a set of thin wires of suitable length and composition protruding from and supported by a fine-pitch micro-ball grid array or chip-scale package (see figure). The associated integrated circuit would be mounted on the package face opposite the probe face, using the solder bumps (the balls of the ball grid array) to make the electrical connections between the probes and the input terminals of the integrated circuit. The key innovation is the insertion of probe wires of the appropriate length and material into the solder bumps through a reflow process, thereby fixing the probes in place and electrically connecting them with the integrated circuit. The probes could be tailored to any distribution of lengths and made of any suitable metal that could be drawn into fine wires. Furthermore, the wires could be coated with an insulating layer using anodization or other processes, to achieve the correct electrical impedance. The probe wires and the packaging materials must be biocompatible using such materials as lead-free solders. For protection, the chip and package can be coated with parylene.

Chip-package nano-structured copper and nickel interconnections with metallic and polymeric bonding interfaces

NASA Astrophysics Data System (ADS)

Aggarwal, Ankur

With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 that support computing speed in terabits per second, with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Decreasing I/O pitch together with low cost, high electrical performance and high reliability are the key technological challenges identified by the 2005 International Technology Roadmap for Semiconductors (ITRS). Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. In addition, the materials must be environmentally-friendly, corrosion resistant, thermally stable over a long time, and resistant to electro-migration. A major challenge is also to develop economic processes that can be integrated into back end of the wafer foundry, i.e. with wafer level packaging. Device-to-system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches of the order of 30 microns and less. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. A novel chip-package interconnection technology is developed to address the IC packaging requirements beyond the ITRS projections and to introduce innovative design and fabrication concepts that will further advance the performance of the chip, the package, and the system board. The nano-structured interconnect technology simultaneously packages all the ICs intact in wafer form with quantum jump in the number of interconnections with the lowest electrical parasitics. The intrinsic properties of nano materials also enable several orders of magnitude higher interconnect densities with the best mechanical properties for the highest reliability and yet provide higher current and heat transfer densities. Nano-structured interconnects provides the ability to assemble the packaged parts on the system board without the use of underfill materials and to enable advanced analog/digital testing, reliability testing, and burn-in at wafer level. This thesis investigates the electrical and mechanical performance of nanostructured interconnections through modeling and test vehicle fabrication. The analytical models evaluate the performance improvements over solder and compliant interconnections. Test vehicles with nano-interconnections were fabricated using low cost electro-deposition techniques and assembled with various bonding interfaces. Interconnections were fabricated at 200 micron pitch to compare with the existing solder joints and at 50 micron pitch to demonstrate fabrication processes at fine pitches. Experimental and modeling results show that the proposed nano-interconnections could enhance the reliability and potentially meet all the system performance requirements for the emerging micro/nano-systems.

A review of digital microfluidics as portable platforms for lab-on a-chip applications.

PubMed

Samiei, Ehsan; Tabrizian, Maryam; Hoorfar, Mina

2016-07-07

Following the development of microfluidic systems, there has been a high tendency towards developing lab-on-a-chip devices for biochemical applications. A great deal of effort has been devoted to improve and advance these devices with the goal of performing complete sets of biochemical assays on the device and possibly developing portable platforms for point of care applications. Among the different microfluidic systems used for such a purpose, digital microfluidics (DMF) shows high flexibility and capability of performing multiplex and parallel biochemical operations, and hence, has been considered as a suitable candidate for lab-on-a-chip applications. In this review, we discuss the most recent advances in the DMF platforms, and evaluate the feasibility of developing multifunctional packages for performing complete sets of processes of biochemical assays, particularly for point-of-care applications. The progress in the development of DMF systems is reviewed from eight different aspects, including device fabrication, basic fluidic operations, automation, manipulation of biological samples, advanced operations, detection, biological applications, and finally, packaging and portability of the DMF devices. Success in developing the lab-on-a-chip DMF devices will be concluded based on the advances achieved in each of these aspects.

New On-board Microprocessors

NASA Astrophysics Data System (ADS)

Weigand, R.

Two new processor devices have been developed for the use on board of spacecrafts. An 8-bit 8032-microcontroller targets typical controlling applications in instruments and sub-systems, or could be used as a main processor on small satellites, whereas the LEON 32-bit SPARC processor can be used for high performance controlling and data processing tasks. The ADV80S32 is fully compliant to the Intel 80x1 architecture and instruction set, extended by additional peripherals, 512 bytes on-chip RAM and a bootstrap PROM, which allows downloading the application software using the CCSDS PacketWire pro- tocol. The memory controller provides a de-multiplexed address/data bus, and allows to access up to 16 MB data and 8 MB program RAM. The peripherals have been de- signed for the specific needs of a spacecraft, such as serial interfaces compatible to RS232, PacketWire and TTC-B-01, counters/timers for extended duration and a CRC calculation unit accelerating the CCSDS TM/TC protocol. The 0.5 um Atmel manu- facturing technology (MG2RT) provides latch-up and total dose immunity; SEU fault immunity is implemented by using SEU hardened Flip-Flops and EDAC protection of internal and external memories. The maximum clock frequency of 20 MHz allows a processing power of 3 MIPS. Engineering samples are available. For SW develop- ment, various SW packages for the 8051 architecture are on the market. The LEON processor implements a 32-bit SPARC V8 architecture, including all the multiply and divide instructions, complemented by a floating-point unit (FPU). It includes several standard peripherals, such as timers/watchdog, interrupt controller, UARTs, parallel I/Os and a memory controller, allowing to use 8, 16 and 32 bit PROM, SRAM or memory mapped I/O. With on-chip separate instruction and data caches, almost one instruction per clock cycle can be reached in some applications. A 33-MHz 32-bit PCI master/target interface and a PCI arbiter allow operating the device in a plug-in card (for SW development on PC etc.), or to consider using it as a PCI master controller in an on-board system. Advanced SEU fault tolerance is in- troduced by design, using triple modular redundancy (TMR) flip-flops for all registers and EDAC protection for all memories. The device will be manufactured in a radia- tion hard Atmel 0.25 um technology, targeting 100 MHz processor clock frequency. The non fault-tolerant LEON processor VHDL model is available as free source code, and the SPARC architecture is a well-known industry standard. Therefore, know-how, software tools and operating systems are widely available.

Automated Absorber Attachment for X-ray Microcalorimeter Arrays

NASA Technical Reports Server (NTRS)

Moseley, S.; Allen, Christine; Kilbourne, Caroline; Miller, Timothy M.; Costen, Nick; Schulte, Eric; Moseley, Samuel J.

2007-01-01

Our goal is to develop a method for the automated attachment of large numbers of absorber tiles to large format detector arrays. This development includes the fabrication of high quality, closely spaced HgTe absorber tiles that are properly positioned for pick-and-place by our FC150 flip chip bonder. The FC150 also transfers the appropriate minute amount of epoxy to the detectors for permanent attachment of the absorbers. The success of this development will replace an arduous, risky and highly manual task with a reliable, high-precision automated process.

Transportable GPU (General Processor Units) chip set technology for standard computer architectures

NASA Astrophysics Data System (ADS)

Fosdick, R. E.; Denison, H. C.

1982-11-01

The USAFR-developed GPU Chip Set has been utilized by Tracor to implement both USAF and Navy Standard 16-Bit Airborne Computer Architectures. Both configurations are currently being delivered into DOD full-scale development programs. Leadless Hermetic Chip Carrier packaging has facilitated implementation of both architectures on single 41/2 x 5 substrates. The CMOS and CMOS/SOS implementations of the GPU Chip Set have allowed both CPU implementations to use less than 3 watts of power each. Recent efforts by Tracor for USAF have included the definition of a next-generation GPU Chip Set that will retain the application-proven architecture of the current chip set while offering the added cost advantages of transportability across ISO-CMOS and CMOS/SOS processes and across numerous semiconductor manufacturers using a newly-defined set of common design rules. The Enhanced GPU Chip Set will increase speed by an approximate factor of 3 while significantly reducing chip counts and costs of standard CPU implementations.

High Coherence Qubit packaging

NASA Astrophysics Data System (ADS)

Pappas, David P.; Wu, Xian; Olivadese, Salvatore B.; Adiga, V. P.; Hertzberg, Jared B.; Bronn, Nicholas T.; Chow, Jerry M.; NIST Team; IBM Team

Development of sockets and associated interconnects for multi-qubit chips is presented. Considerations include thermalization, RF hygiene, non-magnetic environment, and self-alignment of the chips to allow for rapid testing, scalable integration, and high coherence operation. The sockets include wirebond free, vertical take-off launches with pogopins. This allows for high interconnectivity to non-trivial topology of qubits. Furthermore, vertical grounding is accomplished to reduce chip modes and suppress box modes. Low energy loss and high phase coherence is observed using this paradigm. We acknowledge support from IARPA, LPS, and the NIST Quantum Based Metrology Initiative.

Applications of multi-walled carbon nanotube in electronic packaging

PubMed Central

2012-01-01

Thermal management of integrated circuit chip is an increasing important challenge faced today. Heat dissipation of the chip is generally achieved through the die attach material and solders. With the temperature gradients in these materials, high thermo-mechanical stress will be developed in them, and thus they must also be mechanically strong so as to provide a good mechanical support to the chip. The use of multi-walled carbon nanotube to enhance the thermal conductivity, and the mechanical strength of die attach epoxy and Pb-free solder is demonstrated in this work. PMID:22405035

Ice-assisted transfer of carbon nanotube arrays.

PubMed

Wei, Haoming; Wei, Yang; Lin, Xiaoyang; Liu, Peng; Fan, Shoushan; Jiang, Kaili

2015-03-11

Decoupling the growth and the application of nanomaterials by transfer is an important issue in nanotechnology. Here, we developed an efficient transfer technique for carbon nanotube (CNT) arrays by using ice as a binder to temporarily bond the CNT array and the target substrate. Ice makes it an ultraclean transfer because the evaporation of ice ensures that no contaminants are introduced. The transferred superaligned carbon nanotube (SACNT) arrays not only keep their original appearance and initial alignment but also inherit their spinnability, which is the most desirable feature. The transfer-then-spin strategy can be employed to fabricate patterned CNT arrays, which can act as 3-dimensional electrodes in CNT thermoacoustic chips. Besides, the flip-chipped CNTs are promising field electron emitters. Furthermore, the ice-assisted transfer technique provides a cost-effective solution for mass production of SACNTs, giving CNT technologies a competitive edge, and this method may inspire new ways to transfer other nanomaterials.

On-chip cooling by superlattice-based thin-film thermoelectrics.

PubMed

Chowdhury, Ihtesham; Prasher, Ravi; Lofgreen, Kelly; Chrysler, Gregory; Narasimhan, Sridhar; Mahajan, Ravi; Koester, David; Alley, Randall; Venkatasubramanian, Rama

2009-04-01

There is a significant need for site-specific and on-demand cooling in electronic, optoelectronic and bioanalytical devices, where cooling is currently achieved by the use of bulky and/or over-designed system-level solutions. Thermoelectric devices can address these limitations while also enabling energy-efficient solutions, and significant progress has been made in the development of nanostructured thermoelectric materials with enhanced figures-of-merit. However, fully functional practical thermoelectric coolers have not been made from these nanomaterials due to the enormous difficulties in integrating nanoscale materials into microscale devices and packaged macroscale systems. Here, we show the integration of thermoelectric coolers fabricated from nanostructured Bi2Te3-based thin-film superlattices into state-of-the-art electronic packages. We report cooling of as much as 15 degrees C at the targeted region on a silicon chip with a high ( approximately 1,300 W cm-2) heat flux. This is the first demonstration of viable chip-scale refrigeration technology and has the potential to enable a wide range of currently thermally limited applications.

Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

PubMed

Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

2015-12-16

In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

PubMed Central

Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

2015-01-01

In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction. PMID:26694407

Accelerated thermal and mechanical testing of CSP assemblies

NASA Technical Reports Server (NTRS)

Ghaffarian, R.

2000-01-01

Chip Scale Packages (CSP) are now widely used for many electronic applications including portable and telecommunication products. A test vehicle (TV-1) with eleven package types and pitches was built and tested by the JPL MicrotypeBGA Consortium during 1997 to 1999. Lessons learned by the team were published as a guidelines document for industry use. The finer pitch CSP packages which recently became available were indluded in the next test vehicle of the JPL CSP Consortium.

Nutrition labelling, marketing techniques, nutrition claims and health claims on chip and biscuit packages from sixteen countries.

PubMed

Mayhew, Alexandra J; Lock, Karen; Kelishadi, Roya; Swaminathan, Sumathi; Marcilio, Claudia S; Iqbal, Romaina; Dehghan, Mahshid; Yusuf, Salim; Chow, Clara K

2016-04-01

Food packages were objectively assessed to explore differences in nutrition labelling, selected promotional marketing techniques and health and nutrition claims between countries, in comparison to national regulations. Cross-sectional. Chip and sweet biscuit packages were collected from sixteen countries at different levels of economic development in the EPOCH (Environmental Profile of a Community's Health) study between 2008 and 2010. Seven hundred and thirty-seven food packages were systematically evaluated for nutrition labelling, selected promotional marketing techniques relevant to nutrition and health, and health and nutrition claims. We compared pack labelling in countries with labelling regulations, with voluntary regulations and no regulations. Overall 86 % of the packages had nutrition labels, 30 % had health or nutrition claims and 87 % displayed selected marketing techniques. On average, each package displayed two marketing techniques and one health or nutrition claim. In countries with mandatory nutrition labelling a greater proportion of packages displayed nutrition labels, had more of the seven required nutrients present, more total nutrients listed and higher readability compared with those with voluntary or no regulations. Countries with no health or nutrition claim regulations had fewer claims per package compared with countries with regulations. Nutrition label regulations were associated with increased prevalence and quality of nutrition labels. Health and nutrition claim regulations were unexpectedly associated with increased use of claims, suggesting that current regulations may not have the desired effect of protecting consumers. Of concern, lack of regulation was associated with increased promotional marketing techniques directed at children and misleadingly promoting broad concepts of health.

Research pressure instrumentation for NASA Space Shuttle main engine, modification no. 5

NASA Technical Reports Server (NTRS)

Anderson, P. J.; Nussbaum, P.; Gustafson, G.

1984-01-01

The advantages of silicon piezoresistive strain sensing technology are being used to achieve the objectives of state of the art pressure sensors for SSME applications. The integration of multiple functions on a single chip is the key attribute being exploited. Progress is reported in transducer packaging and materials; silicon resistor characterization at cryogenic temperatures; chip mounting; and frequency response optimization.

27 CFR 19.343 - Addition of oak chips to spirits and addition of caramel to brandy and rum.

Code of Federal Regulations, 2010 CFR

2010-04-01

... spirits and addition of caramel to brandy and rum. 19.343 Section 19.343 Alcohol, Tobacco Products and... PLANTS Storage § 19.343 Addition of oak chips to spirits and addition of caramel to brandy and rum. Oak... records. Caramel possessing no material sweetening properties may be added to rum or brandy in packages or...

The ideal chip is not enough: Issues retarding the success of wide band-gap devices

NASA Astrophysics Data System (ADS)

Kaminski, Nando

2017-04-01

Semiconductor chips made from the wide band-gap (WBG) materials silicon carbide (SiC) or gallium nitride (GaN) are already approaching the theoretical limits given by the respective materials. Unfortunately, their advantages over silicon devices cannot be fully exploited due to limitations imposed by the device packaging or the circuitry around the semiconductors. Stray inductances slow down the switching speed and increase losses, packaging materials limit the maximum temperature and the maximum useful temperature swing, and passives limit the maximum switching frequency. All these issues have to be solved or at least minimised to make WBG attractive for a wider range of applications and, consequently, to profit from the economy of scale.

Technology and design of an active-matrix OLED on crystalline silicon direct-view display for a wristwatch computer

NASA Astrophysics Data System (ADS)

Sanford, James L.; Schlig, Eugene S.; Prache, Olivier; Dove, Derek B.; Ali, Tariq A.; Howard, Webster E.

2002-02-01

The IBM Research Division and eMagin Corp. jointly have developed a low-power VGA direct view active matrix OLED display, fabricated on a crystalline silicon CMOS chip. The display is incorporated in IBM prototype wristwatch computers running the Linus operating system. IBM designed the silicon chip and eMagin developed the organic stack and performed the back-end-of line processing and packaging. Each pixel is driven by a constant current source controlled by a CMOS RAM cell, and the display receives its data from the processor memory bus. This paper describes the OLED technology and packaging, and outlines the design of the pixel and display electronics and the processor interface. Experimental results are presented.

Numerical simulation and experimental investigation of GaN-based flip-chip LEDs and top-emitting LEDs.

PubMed

Liu, Xingtong; Zhou, Shengjun; Gao, Yilin; Hu, Hongpo; Liu, Yingce; Gui, Chengqun; Liu, Sheng

2017-12-01

We demonstrate a GaN-based flip-chip LED (FC-LED) with a highly reflective indium-tin oxide (ITO)/distributed Bragg reflector (DBR) ohmic contact. A transparent ITO current spreading layer combined with Ta 2 O 5 /SiO 2 double DBR stacks is used as a reflective p-type ohmic contact in the FC-LED. We develop a strip-shaped SiO 2 current blocking layer, which is well aligned with a p-electrode, to prevent the current from crowding around the p-electrode. Our combined numerical simulation and experimental results revealed that the FC-LED with ITO/DBR has advantages of better current spreading and superior heat dissipation performance compared to top-emitting LEDs (TE-LEDs). As a result, the light output power (LOP) of the FC-LED with ITO/DBR was 7.6% higher than that of the TE-LED at 150 mA, and the light output saturation current was shifted from 130.9  A/cm 2 for the TE-LED to 273.8  A/cm 2 for the FC-LED with ITO/DBR. Owing to the high reflectance of the ITO/DBR ohmic contact, the LOP of the FC-LED with ITO/DBR was 13.0% higher than that of a conventional FC-LED with Ni/Ag at 150 mA. However, because of the better heat dissipation of the Ni/Ag ohmic contact, the conventional FC-LED with Ni/Ag exhibited higher light output saturation current compared to the FC-LED with ITO/DBR.

High coherence plane breaking packaging for superconducting qubits.

PubMed

Bronn, Nicholas T; Adiga, Vivekananda P; Olivadese, Salvatore B; Wu, Xian; Chow, Jerry M; Pappas, David P

2018-04-01

We demonstrate a pogo pin package for a superconducting quantum processor specifically designed with a nontrivial layout topology (e.g., a center qubit that cannot be accessed from the sides of the chip). Two experiments on two nominally identical superconducting quantum processors in pogo packages, which use commercially available parts and require modest machining tolerances, are performed at low temperature (10 mK) in a dilution refrigerator and both found to behave comparably to processors in standard planar packages with wirebonds where control and readout signals come in from the edges. Single- and two-qubit gate errors are also characterized via randomized benchmarking, exhibiting similar error rates as in standard packages, opening the possibility of integrating pogo pin packaging with extensible qubit architectures.

High coherence plane breaking packaging for superconducting qubits

NASA Astrophysics Data System (ADS)

Bronn, Nicholas T.; Adiga, Vivekananda P.; Olivadese, Salvatore B.; Wu, Xian; Chow, Jerry M.; Pappas, David P.

2018-04-01

We demonstrate a pogo pin package for a superconducting quantum processor specifically designed with a nontrivial layout topology (e.g., a center qubit that cannot be accessed from the sides of the chip). Two experiments on two nominally identical superconducting quantum processors in pogo packages, which use commercially available parts and require modest machining tolerances, are performed at low temperature (10 mK) in a dilution refrigerator and both found to behave comparably to processors in standard planar packages with wirebonds where control and readout signals come in from the edges. Single- and two-qubit gate errors are also characterized via randomized benchmarking, exhibiting similar error rates as in standard packages, opening the possibility of integrating pogo pin packaging with extensible qubit architectures.

A Boundary Scan Test Vehicle for Direct Chip Attach Testing

NASA Technical Reports Server (NTRS)

Parsons, Heather A.; DAgostino, Saverio; Arakaki, Genji

2000-01-01

To facilitate the new faster, better and cheaper spacecraft designs, smaller more mass efficient avionics and instruments are using higher density electronic packaging technologies such as direct chip attach (DCA). For space flight applications, these technologies need to have demonstrated reliability and reasonably well defined fabrication and assembly processes before they will be accepted as baseline designs in new missions. As electronics shrink in size, not only can repair be more difficult, but 49 probing" circuitry can be very risky and it becomes increasingly more difficult to identify the specific source of a problem. To test and monitor these new technologies, the Direct Chip Attach Task, under NASA's Electronic Parts and Packaging Program (NEPP), chose the test methodology of boundary scan testing. The boundary scan methodology was developed for interconnect integrity and functional testing at hard to access electrical nodes. With boundary scan testing, active devices are used and failures can be identified to the specific device and lead. This technology permits the incorporation of "built in test" into almost any circuit and thus gives detailed test access to the highly integrated electronic assemblies. This presentation will describe boundary scan, discuss the development of the boundary scan test vehicle for DCA and current plans for testing of direct chip attach configurations.

An Implantable Neural Sensing Microsystem with Fiber-Optic Data Transmission and Power Delivery

PubMed Central

Park, Sunmee; Borton, David A.; Kang, Mingyu; Nurmikko, Arto V.; Song, Yoon-Kyu

2013-01-01

We have developed a prototype cortical neural sensing microsystem for brain implantable neuroengineering applications. Its key feature is that both the transmission of broadband, multichannel neural data and power required for the embedded microelectronics are provided by optical fiber access. The fiber-optic system is aimed at enabling neural recording from rodents and primates by converting cortical signals to a digital stream of infrared light pulses. In the full microsystem whose performance is summarized in this paper, an analog-to-digital converter and a low power digital controller IC have been integrated with a low threshold, semiconductor laser to extract the digitized neural signals optically from the implantable unit. The microsystem also acquires electrical power and synchronization clocks via optical fibers from an external laser by using a highly efficient photovoltaic cell on board. The implantable unit employs a flexible polymer substrate to integrate analog and digital microelectronics and on-chip optoelectronic components, while adapting to the anatomical and physiological constraints of the environment. A low power analog CMOS chip, which includes preamplifier and multiplexing circuitry, is directly flip-chip bonded to the microelectrode array to form the cortical neurosensor device. PMID:23666130

Oxide-confined 2D VCSEL arrays for high-density inter/intra-chip interconnects

NASA Astrophysics Data System (ADS)

King, Roger; Michalzik, Rainer; Jung, Christian; Grabherr, Martin; Eberhard, Franz; Jaeger, Roland; Schnitzer, Peter; Ebeling, Karl J.

1998-04-01

We have designed and fabricated 4 X 8 vertical-cavity surface-emitting laser (VCSEL) arrays intended to be used as transmitters in short-distance parallel optical interconnects. In order to meet the requirements of 2D, high-speed optical links, each of the 32 laser diodes is supplied with two individual top contacts. The metallization scheme allows flip-chip mounting of the array modules junction-side down on silicon complementary metal oxide semiconductor (CMOS) chips. The optical and electrical characteristics across the arrays with device pitch of 250 micrometers are quite homogeneous. Arrays with 3 micrometers , 6 micrometers and 10 micrometers active diameter lasers have been investigated. The small devices show threshold currents of 600 (mu) A, single-mode output powers as high as 3 mW and maximum wavelength deviations of only 3 nm. The driving characteristics of all arrays are fully compatible to advanced 3.3 V CMOS technology. Using these arrays, we have measured small-signal modulation bandwidths exceeding 10 GHz and transmitted pseudo random data at 8 Gbit/s channel over 500 m graded index multimode fiber. This corresponds to a data transmission rate of 256 Gbit/s per array of 1 X 2 mm2 footprint area.

Cell Patterning Chip for Controlling the Stem Cell Microenvironment

PubMed Central

Rosenthal, Adam; Macdonald, Alice; Voldman, Joel

2007-01-01

Cell-cell signaling is an important component of the stem cell microenvironment, affecting both differentiation and self-renewal. However, traditional cell-culture techniques do not provide precise control over cell-cell interactions, while existing cell patterning technologies are limited when used with proliferating or motile cells. To address these limitations, we created the Bio Flip Chip (BFC), a microfabricated polymer chip containing thousands of microwells, each sized to trap down to a single stem cell. We have demonstrated the functionality of the BFC by patterning a 50×50 grid of murine embryonic stem cells (mESCs), with patterning efficiencies > 75%, onto a variety of substrates – a cell-culture dish patterned with gelatin, a 3-D substrate, and even another layer of cells. We also used the BFC to pattern small groups of cells, with and without cell-cell contact, allowing incremental and independent control of contact-mediated signaling. We present quantitative evidence that cell-cell contact plays an important role in depressing mESC colony formation, and show that E-cadherin is involved in this negative regulatory pathway. Thus, by allowing exquisite control of the cellular microenvironment, we provide a technology that enables new applications in tissue engineering and regenerative medicine. PMID:17434582

Chips in black boxes? Convenience life span, parafood, brandwidth, families, and co-creation.

PubMed

Jacobs, Marc

2015-11-01

Any consumer who opens a bag of potato or corn chips (or crisps in the UK) knows there is no time to waste to enjoy or share them. The convenience life span of chips is limited: it is the shelf or storage life and a very limited time once outside the bag. Many technologies converge to generate the desired effect as a black box, not only of the packaging but also of the chips themselves. The concept of paratext can be applied to printed messages on the package, including the brand name and other texts like advertising (epitexts), which can be expanded into the concept of parafood. These concepts help to discuss technological developments and interpret why this has recently become a negotiation zone for co-creation (see the Do us a flavor campaigns). They are symptoms of changing relations between production, research and development, marketing, and consumption. This paper pays special attention to back stories, underdog brand biographies and narratives about origin. The concept of brandwidth is introduced to sensitize about the limits of combining different stories about chips. A recent brand biography, a family history and a cookery book are used to discuss the phenomenon of cooking with Fritos. Together with the concepts of parafood, brandwidth and black boxes, more reflection and dialogue about the role of history and heritage in marketing put new challenging perspectives on the agenda. Copyright © 2015 Elsevier Ltd. All rights reserved.

Advanced packaging for Integrated Micro-Instruments

NASA Technical Reports Server (NTRS)

Lyke, James L.

1995-01-01

The relationship between packaging, microelectronics, and micro-electrical-mechanical systems (MEMS) is an important one, particularly when the edges of performance boundaries are pressed, as in the case of miniaturized systems. Packaging is a sort of physical backbone that enables the maximum performance of these systems to be realized, and the penalties imposed by conventional packing approaches is particularly limiting for MEMS devices. As such, advanced packaging approaches, such as multi-chip modules (MCM's) have been touted as a true means of electronic 'enablement' for a variety of application domains. Realizing an optimum system of packaging, however, in not as simple as replacing a set of single chip packages with a substrate of interconnections. Research at Phillips Laboratory has turned up a number of integrating options in the two- and three-dimensional rending of miniature systems with physical interconnection structures with intrinsically high performance. Not only do these structures motivate the redesign of integrated circuits (IC's) for lower power, but they possess interesting features that provide a framework for the direct integration of MEMS devices. Cost remains a barrier to the application of MEMS devices, even in space systems. Several innovations are suggested that will result in lower cost and more rapid cycle time. First, the novelty of a 'constant floor plan' MCM which encapsulates a variety of commonly used components into a stockable, easily customized assembly is discussed. Next, the use of low-cost substrates is examined. The anticipated advent of ultra-high density interconnect (UHDI) is suggested as the limit argument of advanced packaging. Finally, the concept of a heterogeneous 3-D MCM system is outlined that allows for the combination of different compatible packaging approaches into a uniformly dense structure that could also include MEMS-based sensors.

100-GHz Phase Switch/Mixer Containing a Slot-Line Transition

NASA Technical Reports Server (NTRS)

Gaier, Todd; Wells, Mary; Dawson, Douglas

2009-01-01

A circuit that can function as a phase switch, frequency mixer, or frequency multiplier operates over a broad frequency range in the vicinity of 100 GHz. Among the most notable features of this circuit is a grounded uniplanar transition (in effect, a balun) between a slot line and one of two coplanar waveguides (CPWs). The design of this circuit is well suited to integration of the circuit into a microwave monolithic integrated circuit (MMIC) package. One CPW is located at the input end and one at the output end of the top side of a substrate on which the circuit is fabricated (see Figure 1). The input CPW feeds the input signal to antiparallel flip-chip Schottky diodes connected to the edges of the slot line. Phase switching is effected by the combination of (1) the abrupt transition from the input CPW to the slot line and (2) CPW ground tuning effected by switching of the bias on the diodes. Grounding of the slot metal to the bottom metal gives rise to a frequency cutoff in the slot. This cutoff is valuable for separating different frequency components when the circuit is used as a mixer or multiplier. Proceeding along the slot line toward the output end, one encounters the aforementioned transition, which couples the slot line to the output CPW. Impedance tuning of the transition is accomplished by use of a high-impedance section immediately before the transition.

77 FR 14569 - Notice of Intent To Grant Exclusive License

Federal Register 2010, 2011, 2012, 2013, 2014

2012-03-12

... Direct Chip Attach Packaging Methodologies and Apparatuses for Harsh Environments, LEW 17,256-1, to... equipment; semiconductor manufacturing; material manufacturing such as metallurgy, refractory processes, and...

The extended Beer-Lambert theory for ray tracing modeling of LED chip-scaled packaging application with multiple luminescence materials

NASA Astrophysics Data System (ADS)

Yuan, Cadmus C. A.

2015-12-01

Optical ray tracing modeling applied Beer-Lambert method in the single luminescence material system to model the white light pattern from blue LED light source. This paper extends such algorithm to a mixed multiple luminescence material system by introducing the equivalent excitation and emission spectrum of individual luminescence materials. The quantum efficiency numbers of individual material and self-absorption of the multiple luminescence material system are considered as well. By this combination, researchers are able to model the luminescence characteristics of LED chip-scaled packaging (CSP), which provides simple process steps and the freedom of the luminescence material geometrical dimension. The method will be first validated by the experimental results. Afterward, a further parametric investigation has been then conducted.

CMOS Image Sensor with a Built-in Lane Detector.

PubMed

Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

2009-01-01

This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%.

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

NASA Astrophysics Data System (ADS)

Bartelink, Dirk J.

1998-11-01

The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must recognize—test is also performed using IC's. A system interconnection is proposed using multiple chips fabricated with conventional silicon processes, including MEMS technology. The system resembles an MCM that can be joined without committing to final assembly to perform at-speed testing. 50-Ohm test probes never load the circuit; only intended neighboring chips are ever connected. A `back-plane' chip provides the connection layers for both inter- and intra-chip signals and also serves as the probe card, in analogy with membrane probes now used for single-chip testing. Intra-chip connections, which require complicated connections during test that exactly match the product, are then properly made and all waveforms and loading conditions under test will be identical to those of the product. The major benefit is that all front-end chip technologies can be merged—logic, memory, RF, even passives. ESD protection is required only on external system connections. Manufacturing test information will accurately characterize process faults and thus avoid the Known-Good-Die problem that has slowed the arrival of conventional MCM's.

Designing an Electronics Data Package for Printed Circuit Boards (PCBs)

DTIC Science & Technology

2013-08-01

finished PCB flatness deviation should be less than 0.010 inches per inch. 4  The minimum copper wall thickness of plated-thru holes should be...Memory Card International Association)  IPC-6015 MCM-L (Multi-Chip Module – Laminated )  IPC-6016 HDI (High Density Interconnect)  IPC-6018...Interconnect ICT In Circuit Tester IPC Association Connecting Electronics Industries MCM-L Multi-Chip Module – Laminated MIL Military NEMA National

Radiation-Resistant Photon-Counting Detector Package Providing Sub-ps Stability for Laser Time Transfer in Space

NASA Technical Reports Server (NTRS)

Prochzaka, Ivan; Kodat, Jan; Blazej, Josef; Sun, Xiaoli (Editor)

2015-01-01

We are reporting on a design, construction and performance of photon-counting detector packages based on silicon avalanche photodiodes. These photon-counting devices have been optimized for extremely high stability of their detection delay. The detectors have been designed for future applications in fundamental metrology and optical time transfer in space. The detectors have been qualified for operation in space missions. The exceptional radiation tolerance of the detection chip itself and of all critical components of a detector package has been verified in a series of experiments.

Low-dielectric constant insulators for future integrated circuits and packages.

PubMed

Kohl, Paul A

2011-01-01

Future integrated circuits and packages will require extraordinary dielectric materials for interconnects to allow transistor advances to be translated into system-level advances. Exceedingly low-permittivity and low-loss materials are required at every level of the electronic system, from chip-level insulators to packages and printed wiring boards. In this review, the requirements and goals for future insulators are discussed followed by a summary of current state-of-the-art materials and technical approaches. Much work needs to be done for insulating materials and structures to meet future needs.

Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

PubMed

Li, Lin; Yin, Heyu; Mason, Andrew J

2018-04-01

The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

Study on vacuum packaging reliability of micromachined quartz tuning fork gyroscopes

NASA Astrophysics Data System (ADS)

Fan, Maoyan; Zhang, Lifang

2017-09-01

Packaging technology of the micromachined quartz tuning fork gyroscopes by vacuum welding has been experimentally studied. The performance of quartz tuning fork is influenced by the encapsulation shell, encapsulation method and fixation of forks. Alloy solder thick film is widely used in the package to avoid the damage of the chip structure by the heat resistance and hot temperature, and this can improve the device performance and welding reliability. The results show that the bases and the lids plated with gold and nickel can significantly improve the airtightness and reliability of the vacuum package. Vacuum packaging is an effective method to reduce the vibration damping, improve the quality factor and further enhance the performance. The threshold can be improved nearly by 10 times.

Performance of High-Speed PWM Control Chips at Cryogenic Temperatures

NASA Technical Reports Server (NTRS)

Elbuluk, Malik E.; Gerber, Scott; Hammoud, Ahmad; Patterson, Richard; Overton, Eric

2001-01-01

The operation of power electronic systems at cryogenic temperatures is anticipated in many NASA space missions such as planetary exploration and deep space probes. In addition to surviving the space hostile environment, electronics capable of low temperature operation would contribute to improving circuit performance, increasing system efficiency, and reducing development and launch costs. As part of the NASA Glenn Low Temperature Electronics Program, several commercial high-speed Pulse Width Modulation (PWM) chips have been characterized in terms of their performance as a function of temperature in the range of 25 to -196 C (liquid nitrogen). These chips ranged in their electrical characteristics, modes of control, packaging options, and applications. The experimental procedures along with the experimental data obtained on the investigated chips are presented and discussed.

Toward more efficient fabrication of high-density 2-D VCSEL arrays for spatial redundancy and/or multi-level signal communication

NASA Astrophysics Data System (ADS)

Roscher, Hendrik; Gerlach, Philipp; Khan, Faisal Nadeem; Kroner, Andrea; Stach, Martin; Weigl, Alexander; Michalzik, Rainer

2006-04-01

We present flip-chip attached high-speed VCSELs in 2-D arrays with record-high intra-cell packing densities. The advances of VCSEL array technology toward improved thermal performance and more efficient fabrication are reviewed, and the introduction of self-aligned features to these devices is pointed out. The structure of close-spaced wedge-shaped VCSELs is discussed and their static and dynamic characteristics are presented including an examination of the modal structure by near-field measurements. The lasers flip-chip bonded to a silicon-based test platform exhibit 3-dB and 10-dB bandwidths of 7.7 GHz and 9.8 GHz, respectively. Open 12.5 Gbit/s two-level eye patterns are demonstrated. We discuss the uses of high packing densities for the increase of the total amount of data throughput an array can deliver in the course of its life. One such approach is to provide up to two backup VCSELs per fiber channel that can extend the lifetimes of parallel transmitters through redundancy of light sources. Another is to increase the information density by using multiple VCSELs per 50 μm core diameter multimode fiber to generate more complex signals. A novel scheme using three butt-coupled VCSELs per fiber for the generation of four-level signals in the optical domain is proposed. First experiments are demonstrated using two VCSELs butt-coupled to the same standard glass fiber, each modulated with two-level signals to produce four-level signals at the photoreceiver. A four-level direct modulation of one VCSEL within a triple of devices produced first 20.6 Gbit/s (10.3 Gsymbols/s) four-level eyes, leaving two VCSELs as backup sources.

Life test of the InGaAs focal plane arrays detector for space applications

NASA Astrophysics Data System (ADS)

Zhu, Xian-Liang; Zhang, Hai-Yan; Li, Xue; Huang, Zhang-Cheng; Gong, Hai-Mei

2017-08-01

The short-wavelength infrared (SWIR) InGaAs focal plane array (FPA) detector consists of infrared detector chip, readout integrated circuit (ROIC), and flip-chip bonding interconnection by Indium bump. In order to satisfy space application requirements for failure rates or Mean Time to Failure (MTTF), which can only be demonstrated with the large number of detectors manufactured, the single pixel in InGaAs FPAs was chosen as the research object in this paper. The constant-stress accelerated life tests were carried out at 70°C 80°C 90°C and100°C. The failed pixels increased gradually during more than 14000 hours at each elevated temperatures. From the random failure data the activation energy was estimated to be 0.46eV, and the average lifetime of a single pixel in InGaAs FPAs was estimated to be longer than 1E+7h at the practical operating temperature (5°C).

Vertically Integrated MEMS SOI Composite Porous Silicon-Crystalline Silicon Cantilever-Array Sensors: Concept for Continuous Sensing of Explosives and Warfare Agents

NASA Astrophysics Data System (ADS)

Stolyarova, Sara; Shemesh, Ariel; Aharon, Oren; Cohen, Omer; Gal, Lior; Eichen, Yoav; Nemirovsky, Yael

This study focuses on arrays of cantilevers made of crystalline silicon (c-Si), using SOI wafers as the starting material and using bulk micromachining. The arrays are subsequently transformed into composite porous silicon-crystalline silicon cantilevers, using a unique vapor phase process tailored for providing a thin surface layer of porous silicon on one side only. This results in asymmetric cantilever arrays, with one side providing nano-structured porous large surface, which can be further coated with polymers, thus providing additional sensing capabilities and enhanced sensing. The c-Si cantilevers are vertically integrated with a bottom silicon die with electrodes allowing electrostatic actuation. Flip Chip bonding is used for the vertical integration. The readout is provided by a sensitive Capacitance to Digital Converter. The fabrication, processing and characterization results are reported. The reported study is aimed towards achieving miniature cantilever chips with integrated readout for sensing explosives and chemical warfare agents in the field.

Miniaturized force/torque sensor for in vivo measurements of tissue characteristics.

PubMed

Hessinger, M; Pilic, T; Werthschutzky, R; Pott, P P

2016-08-01

This paper presents the development of a surgical instrument to measure interaction forces/torques with organic tissue during operation. The focus is on the design progress of the sensor element, consisting of a spoke wheel deformation element with a diameter of 12 mm and eight inhomogeneous doped piezoresistive silicon strain gauges on an integrated full-bridge assembly with an edge length of 500 μm. The silicon chips are contacted to flex-circuits via flip chip and bonded on the substrate with a single component adhesive. A signal processing board with an 18 bit serial A/D converter is integrated into the sensor. The design concept of the handheld surgical sensor device consists of an instrument coupling, the six-axis sensor, a wireless communication interface and battery. The nominal force of the sensing element is 10 N and the nominal torque is 1 N-m in all spatial directions. A first characterization of the force sensor results in a maximal systematic error of 4.92 % and random error of 1.13 %.

Demonstration of a Packaged Capacitive Pressure Sensor System Suitable for Jet Turbofan Engine Health Monitoring

NASA Technical Reports Server (NTRS)

Scardelletti, Maximilian C.; Jordan, Jennifer L.; Meredith, Roger D.; Harsh, Kevin; Pilant, Evan; Usrey, Michael W.; Beheim, Glenn M.; Hunter, Gary W.; Zorman, Christian A.

2016-01-01

In this paper, the development and characterization of a packaged pressure sensor system suitable for jet engine health monitoring is demonstrated. The sensing system operates from 97 to 117 MHz over a pressure range from 0 to 350 psi and a temperature range from 25 to 500 deg. The sensing system consists of a Clapp-type oscillator that is fabricated on an alumina substrate and is comprised of a Cree SiC MESFET, MIM capacitors, a wire-wound inductor, chip resistors and a SiCN capacitive pressure sensor. The pressure sensor is located in the LC tank circuit of the oscillator so that a change in pressure causes a change in capacitance, thus changing the resonant frequency of the sensing system. The chip resistors, wire-wound inductors and MIM capacitors have all been characterized at temperature and operational frequency, and perform with less than 5% variance in electrical performance. The measured capacitive pressure sensing system agrees very well with simulated results. The packaged pressure sensing system is specifically designed to measure the pressure on a jet turbofan engine. The packaged system can be installed by way of borescope plug adaptor fitted to a borescope port exposed to the gas path of a turbofan engine.

Passive UHF RFID Tag with Multiple Sensing Capabilities

PubMed Central

Fernández-Salmerón, José; Rivadeneyra, Almudena; Martínez-Martí, Fernando; Capitán-Vallvey, Luis Fermín; Palma, Alberto J.; Carvajal, Miguel A.

2015-01-01

This work presents the design, fabrication, and characterization of a printed radio frequency identification tag in the ultra-high frequency band with multiple sensing capabilities. This passive tag is directly screen printed on a cardboard box with the aim of monitoring the packaging conditions during the different stages of the supply chain. This tag includes a commercial force sensor and a printed opening detector. Hence, the force applied to the package can be measured as well as the opening of the box can be detected. The architecture presented is a passive single-chip RFID tag. An electronic switch has been implemented to be able to measure both sensor magnitudes in the same access without including a microcontroller or battery. Moreover, the chip used here integrates a temperature sensor and, therefore, this tag provides three different parameters in every reading. PMID:26506353

Fabrication and Qualification of Coated Chip-on-Board Technology for Miniaturized Space Systems

NASA Technical Reports Server (NTRS)

Maurer, R. H.; Le, B. Q.; Nhan, E.; Lew, A. L.; Darrin, M. Ann Garrison

1997-01-01

The results of a study carried out in order to manufacture and verify the quality of chip-on-board (COB) packaging technology are presented. The COB, designed for space applications, was tested under environmental stresses, temperature cycling, and temperature-humidity-bias. Both robustness in space applications and in environmental protection on the ground-complete reliability without hermeticity were searched for. The epoxy-parylene combinations proved to be superior to other materials tested.

TOPICAL REVIEW: Microsystem technologies for implantable applications

NASA Astrophysics Data System (ADS)

Receveur, Rogier A. M.; Lindemans, Fred W.; de Rooij, Nicolaas F.

2007-05-01

Microsystem technologies (MST) have become the basis of a large industry. The advantages of MST compared to other technologies provide opportunities for application in implantable biomedical devices. This paper presents a general and broad literature review of MST for implantable applications focused on the technical domain. A classification scheme is introduced to order the examples, basic technological building blocks relevant for implantable applications are described and finally a case study on the role of microsystems for one clinical condition is presented. We observe that the microfabricated parts span a wide range for implantable applications in various clinical areas. There are 94 active and 67 commercial 'end items' out of a total of 142. End item refers to the total concept, of which the microsystem may only be a part. From the 105 active end items 18 (13% of total number of end items) are classified as products. From these 18 products, there are only two for chronic use. The number of active end items in clinical, animal and proto phase for chronic use is 17, 13 and 20, respectively. The average year of first publication of chronic end items that are still in the animal or clinical phase is 1994 (n = 7) and 1993 (n = 11), respectively. The major technology market combinations are sensors for cardiovascular, drug delivery for drug delivery and electrodes for neurology and ophthalmology. Together these form 51% of all end items. Pressure sensors form the majority of sensors and there is just one product (considered to be an implantable microsystem) in the neurological area. Micro-machined ceramic packages, glass sealed packages and polymer encapsulations are used. Glass to metal seals are used for feedthroughs. Interconnection techniques such as flip chip, wirebonding or conductive epoxy as used in the semiconductor packaging and assembly industry are also used for manufacturing of implantable devices. Coatings are polymers or metal. As an alternative to implantable primary batteries, rechargeable batteries were introduced or concepts in which energy is provided from the outside based on inductive coupling. Long-term developments aiming at autonomous power are, for example, based on electrostatic conversion of mechanical vibrations. Communication with the implantable device is usually done using an inductive link. A large range of materials commonly used in microfabrication are also used for implantable microsystems.

Packaging's Contribution for the Effectiveness of the Space Station's Food Service Operation

NASA Technical Reports Server (NTRS)

Rausch, B. A.

1985-01-01

Storage limitations will have a major effect on space station food service. For example: foods with low bulk density such as ice cream, bread, cake, standard type potato chips and other low density snacks, flaked cereals, etc., will exacerbate the problem of space limitations; package containers are inherently volume consuming and refuse creating; and the useful observation that the optimum package is no package at all leads to the tentative conclusion that the least amount of packaging per unit of food, consistent with storage, aesthetics, preservation, cleanliness, cost and disposal criteria, is the most practical food package for the space station. A series of trade offs may have to be made to arrive at the most appropriate package design for a particular type of food taking all the criteria into account. Some of these trade offs are: single serve vs. bulk; conventional oven vs. microwave oven; nonmetallic aseptically vs. non-aseptically packaged foods; and comparison of aseptic vs. nonaseptic food packages. The advantages and disadvantages are discussed.

High Performance Hermetic Package For LiNbO3 Electro-Optic Waveguide Devices

NASA Astrophysics Data System (ADS)

Preston, K. R.; Macdonald, B. M.; Harmon, R. A.; Ford, C. W.; Shaw, R. N.; Reid, I.; Davidson, J. H.; Beaumont, A. R.; Booth, R. C.

1989-02-01

A high performance fibre-tailed package for LiNbO3 electro-optic waveguide devices is described. The package is based around a hermetic metal submodule which contains no epoxy or other organic materials. The LiNbO3 chip is mounted using a soldering technique, and laser welding is used for fibre fixing to give stable, low loss optical coupling to single mode fibres. Optical reflections are minimised by the use of antireflective coatings on the fibre ends and waveguide facets. High speed electrical connections are made via coplanar glass-sealed leadthroughs to LiNb03 travelling wave devices, and packaged device operation to frequencies in excess of 4GHz is demonstrated.

Accelerated Thermal Cycling and Failure Mechanisms

NASA Technical Reports Server (NTRS)

Ghaffarian, R.

1999-01-01

This paper reviews the accelerated thermal cycling test methods that are currently used by industry to characterize the interconnect reliability of commercial-off-the-shelf (COTS) ball grid array (BGA) and chip scale package (CSP) assemblies.

Introduction to Special Section on Recent Advances in the Study of Optical Variability in the Near-Surface and Upper Ocean

DTIC Science & Technology

2012-06-30

laser wave height ( lidar ) measurement system was deployed from a boom connected between the bows of the R/V Kilo Moana’s twin hulls [Zappa et al...Robbins et al., 2006], and a surfactant skimmer called the Lil KM (Figure 1). Also, a small aircraft equipped with lidar instrumentation made...c) R/P FLIP starboard boom during the Hawaii Exper- iment in September 2009. The air-sea flux package, orthogonal scanning laser altimeters

Fabrication of a Silicon Backshort Assembly for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

Radiation hardness and timing studies of a monolithic TowerJazz pixel design for the new ATLAS Inner Tracker

NASA Astrophysics Data System (ADS)

Riegel, C.; Backhaus, M.; Van Hoorne, J. W.; Kugathasan, T.; Musa, L.; Pernegger, H.; Riedler, P.; Schaefer, D.; Snoeys, W.; Wagner, W.

2017-01-01

A part of the upcoming HL-LHC upgrade of the ATLAS Detector is the construction of a new Inner Tracker. This upgrade opens new possibilities, but also presents challenges in terms of occupancy and radiation tolerance. For the pixel detector inside the inner tracker, hybrid modules containing passive silicon sensors and connected readout chips are presently used, but require expensive assembly techniques like fine-pitch bump bonding. Silicon devices fabricated in standard commercial CMOS technologies, which include part or all of the readout chain, are also investigated offering a reduced cost as they are cheaper per unit area than traditional silicon detectors. If they contain the full readout chain, as for a fully monolithic approach, there is no need for the expensive flip-chip assembly, resulting in a further cost reduction and material savings. In the outer pixel layers of the ATLAS Inner Tracker, the pixel sensors must withstand non-ionising energy losses of up to 1015 n/cm2 and offer a timing resolution of 25 ns or less. This paper presents test results obtained on a monolithic test chip, the TowerJazz 180nm Investigator, towards these specifications. The presented program of radiation hardness and timing studies has been launched to investigate this technology's potential for the new ATLAS Inner Tracker.

Thick photosensitive polyimide film side wall angle variability and scum improvement for IC packaging stress control

NASA Astrophysics Data System (ADS)

Mehta, Sohan Singh; Yeung, Marco; Mirza, Fahad; Raman, Thiagarajan; Longenbach, Travis; Morgan, Justin; Duggan, Mark; Soedibyo, Rio A.; Reidy, Sean; Rabie, Mohamed; Cho, Jae Kyu; Premachandran, C. S.; Faruqui, Danish

2018-03-01

In this paper, we demonstrate photosensitive polyimide (PSPI) profile optimization to effectively reduce stress concentrations and enable PSPI as protection package-induced stress. Through detailed package simulation, we demonstrate 45% reduction in stress as the sidewall angle (SWA) of PSPI is increased from 45 to 80 degrees in Cu pillar package types. Through modulation of coating and develop multi-step baking temperature and time, as well as dose energy and post litho surface treatments, we demonstrate a method for reliably obtaining PSPI sidewall angle >75 degree. Additionally, we experimentally validate the simulation findings that PSPI sidewall angle impacts chip package interaction (CPI). Finally, we conclude this paper with PSPI material and tool qualification requirements for future technology node based on current challenges.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

Off-line, built-in test techniques for VLSI circuits

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Sievers, M. W.

1982-01-01

It is shown that the use of redundant on-chip circuitry improves the testability of an entire VLSI circuit. In the study described here, five techniques applied to a two-bit ripple carry adder are compared. The techniques considered are self-oscillation, self-comparison, partition, scan path, and built-in logic block observer. It is noted that both classical stuck-at faults and nonclassical faults, such as bridging faults (shorts), stuck-on x faults where x may be 0, 1, or vary between the two, and parasitic flip-flop faults occur in IC structures. To simplify the analysis of the testing techniques, however, a stuck-at fault model is assumed.

Research on defects inspection of solder balls based on eddy current pulsed thermography.

PubMed

Zhou, Xiuyun; Zhou, Jinlong; Tian, Guiyun; Wang, Yizhe

2015-10-13

In order to solve tiny defect detection for solder balls in high-density flip-chip, this paper proposed feasibility study on the effect of detectability as well as classification based on eddy current pulsed thermography (ECPT). Specifically, numerical analysis of 3D finite element inductive heat model is generated to investigate disturbance on the temperature field for different kind of defects such as cracks, voids, etc. The temperature variation between defective and non-defective solder balls is monitored for defects identification and classification. Finally, experimental study is carried on the diameter 1mm tiny solder balls by using ECPT and verify the efficacy of the technique.

78 FR 42159 - Medicaid and Children's Health Insurance Programs: Essential Health Benefits in Alternative...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-07-15

...This final rule implements provisions of the Patient Protection and Affordable Care Act and the Health Care and Education Reconciliation Act of 2010 (collectively referred to as the Affordable Care Act. This final rule finalizes new Medicaid eligibility provisions; finalizes changes related to electronic Medicaid and the Children's Health Insurance Program (CHIP) eligibility notices and delegation of appeals; modernizes and streamlines existing Medicaid eligibility rules; revises CHIP rules relating to the substitution of coverage to improve the coordination of CHIP coverage with other coverage; and amends requirements for benchmark and benchmark- equivalent benefit packages consistent with sections 1937 of the Social Security Act (which we refer to as ``alternative benefit plans'') to ensure that these benefit packages include essential health benefits and meet certain other minimum standards. This rule also implements specific provisions including those related to authorized representatives, notices, and verification of eligibility for qualifying coverage in an eligible employer-sponsored plan for Affordable Insurance Exchanges. This rule also updates and simplifies the complex Medicaid premium and cost sharing requirements, to promote the most effective use of services, and to assist states in identifying cost sharing flexibilities. It includes transition policies for 2014 as applicable.

SVGA and XGA active matrix microdisplays for head-mounted applications

NASA Astrophysics Data System (ADS)

Alvelda, Phillip; Bolotski, Michael; Brown, Imani L.

2000-03-01

The MicroDisplay Corporation's liquid crystal on silicon (LCOS) display devices are based on the union of several technologies with the extreme integration capability of conventionally fabricated CMOS substrates. The fast liquid crystal operation modes and new scalable high-performance pixel addressing architectures presented in this paper enable substantially improved color, contrast, and brightness while still satisfying the optical, packaging, and power requirements of portable applications. The entire suite of MicroDisplay's technologies was devised to create a line of mixed-signal application-specific integrated circuits (ASICs) in single-chip display systems. Mixed-signal circuits can integrate computing, memory, and communication circuitry on the same substrate as the display drivers and pixel array for a multifunctional complete system-on-a-chip. System-on-a-chip benefits also include reduced head supported weight requirements through the elimination of off-chip drive electronics.

Effect of Slice Error of Glass on Zero Offset of Capacitive Accelerometer

NASA Astrophysics Data System (ADS)

Hao, R.; Yu, H. J.; Zhou, W.; Peng, B.; Guo, J.

2018-03-01

Packaging process had been studied on capacitance accelerometer. The silicon-glass bonding process had been adopted on sensor chip and glass, and sensor chip and glass was adhered on ceramic substrate, the three-layer structure was curved due to the thermal mismatch, the slice error of glass lead to asymmetrical curve of sensor chip. Thus, the sensitive mass of accelerometer deviated along the sensitive direction, which was caused in zero offset drift. It was meaningful to confirm the influence of slice error of glass, the simulation results showed that the zero output drift was 12.3×10-3 m/s2 when the deviation was 40μm.

Self-Patterning of Silica/Epoxy Nanocomposite Underfill by Tailored Hydrophilic-Superhydrophobic Surfaces for 3D Integrated Circuit (IC) Stacking.

PubMed

Tuan, Chia-Chi; James, Nathan Pataki; Lin, Ziyin; Chen, Yun; Liu, Yan; Moon, Kyoung-Sik; Li, Zhuo; Wong, C P

2017-03-15

As microelectronics are trending toward smaller packages and integrated circuit (IC) stacks nowadays, underfill, the polymer composite filled in between the IC chip and the substrate, becomes increasingly important for interconnection reliability. However, traditional underfills cannot meet the requirements for low-profile and fine pitch in high density IC stacking packages. Post-applied underfills have difficulties in flowing into the small gaps between the chip and the substrate, while pre-applied underfills face filler entrapment at bond pads. In this report, we present a self-patterning underfilling technology that uses selective wetting of underfill on Cu bond pads and Si 3 N 4 passivation via surface energy engineering. This novel process, fully compatible with the conventional underfilling process, eliminates the issue of filler entrapment in typical pre-applied underfilling process, enabling high density and fine pitch IC die bonding.

Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips

NASA Astrophysics Data System (ADS)

Yu, Thomas Edison; Yoneda, Tomokazu; Chakrabarty, Krishnendu; Fujiwara, Hideo

Rapid advances in semiconductor manufacturing technology have led to higher chip power densities, which places greater emphasis on packaging and temperature control during testing. For system-on-chips, peak power-based scheduling algorithms have been used to optimize tests under specified power constraints. However, imposing power constraints does not always solve the problem of overheating due to the non-uniform distribution of power across the chip. This paper presents a TAM/Wrapper co-design methodology for system-on-chips that ensures thermal safety while still optimizing the test schedule. The method combines a simplified thermal-cost model with a traditional bin-packing algorithm to minimize test time while satisfying temperature constraints. Furthermore, for temperature checking, thermal simulation is done using cycle-accurate power profiles for more realistic results. Experiments show that even a minimal sacrifice in test time can yield a considerable decrease in test temperature as well as the possibility of further lowering temperatures beyond those achieved using traditional power-based test scheduling.

Effect of processing conditions on the quality characteristics of barley chips.

PubMed

Prakash, Jyoti; Naik, H R; Hussain, Syed Zameer; Singh, Baljit

2015-01-01

The aim of the present study was to study the effect of lime concentration, frying temperature and frying time on quality characteristics of barley chips. Effect of salt concentration and packaging material on the quality and stability of the product was also studied during 180 days of storage under ambient conditions. An increase in fat content of chips was observed with the increase in lime concentration, frying temperature and time, whereas a decreasing trend was observed in moisture content of chips. An increase in amylose content of chips was observed during frying. However, it was found that the amylopectin in chips decreased during frying as frying temperature and time was increased. An increase in colour difference (ΔE) and crispness was noted in chips during frying as frying temperature and time increased. With the increase in lime concentration (0.5 and 1.0 %) both ΔE and break force of chips was found decreased. The results further revealed that there was gradual decrease in fat (%) and amylopectin (%) during storage, whereas moisture (%) and amylose (%) increased during storage period. Organoleptic evaluation of the product revealed that scores of colour, texture, flavour and over all acceptability decrease during storage. However the treatment (salt 2 % and aluminium based laminate) recorded better score with respect to colour, flavour, texture and overall acceptability.

Long-Term Stability of NIST Chip-Scale Atomic Clock Physics Packages

DTIC Science & Technology

2007-01-01

vacuum packaging), as has been demonstrated by Lutwak et al. [3]. Nevertheless, we tried to investigate the causes for the frequency shifts of...stability,” Optics Express, 13, 1249-1253. [3] R. Lutwak , J. Deng, W. Riley, M. Varghese, J. Leblanc, G. Tepolt, M. Mescher, D. K. Serkland, K. M. Geib...the 1st Annual Multiconference on Electronics and Photonics, 7-11 November 2006, Guanajuato, Mexico, in press. [6] R. Lutwak , P. Vlitas, M

Three-dimensional fit-to-flow microfluidic assembly.

PubMed

Chen, Arnold; Pan, Tingrui

2011-12-01

Three-dimensional microfluidics holds great promise for large-scale integration of versatile, digitalized, and multitasking fluidic manipulations for biological and clinical applications. Successful translation of microfluidic toolsets to these purposes faces persistent technical challenges, such as reliable system-level packaging, device assembly and alignment, and world-to-chip interface. In this paper, we extended our previously established fit-to-flow (F2F) world-to-chip interconnection scheme to a complete system-level assembly strategy that addresses the three-dimensional microfluidic integration on demand. The modular F2F assembly consists of an interfacial chip, pluggable alignment modules, and multiple monolithic layers of microfluidic channels, through which convoluted three-dimensional microfluidic networks can be easily assembled and readily sealed with the capability of reconfigurable fluid flow. The monolithic laser-micromachining process simplifies and standardizes the fabrication of single-layer pluggable polymeric modules, which can be mass-produced as the renowned Lego(®) building blocks. In addition, interlocking features are implemented between the plug-and-play microfluidic chips and the complementary alignment modules through the F2F assembly, resulting in facile and secure alignment with average misalignment of 45 μm. Importantly, the 3D multilayer microfluidic assembly has a comparable sealing performance as the conventional single-layer devices, providing an average leakage pressure of 38.47 kPa. The modular reconfigurability of the system-level reversible packaging concept has been demonstrated by re-routing microfluidic flows through interchangeable modular microchannel layers.

High-Temperature High-Power Packaging Techniques for HEV Traction Applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Elshabini, Aicha; Barlow, Fred D.

A key issue associated with the wider adoption of hybrid-electric vehicles (HEV) and plug in hybrid-electric vehicles (PHEV) is the implementation of the power electronic systems that are required in these products. One of the primary industry goals is the reduction in the price of these vehicles relative to the cost of traditional gasoline powered vehicles. Today these systems, such as the Prius, utilize one coolant loop for the engine at approximately 100 C coolant temperatures, and a second coolant loop for the inverter at 65 C. One way in which significant cost reduction of these systems could be achievedmore » is through the use of a single coolant loop for both the power electronics as well as the internal combustion engine (ICE). This change in coolant temperature significantly increases the junction temperatures of the devices and creates a number of challenges for both device fabrication and the assembly of these devices into inverters and converters for HEV and PHEV applications. Traditional power modules and the state-of-the-art inverters in the current HEV products, are based on chip and wire assembly and direct bond copper (DBC) on ceramic substrates. While a shift to silicon carbide (SiC) devices from silicon (Si) devices would allow the higher operating temperatures required for a single coolant loop, it also creates a number of challenges for the assembly of these devices into power inverters. While this traditional packaging technology can be extended to higher temperatures, the key issues are the substrate material and conductor stability, die bonding material, wire bonds, and bond metallurgy reliability as well as encapsulation materials that are stable at high operating temperatures. The larger temperature differential during power cycling, which would be created by higher coolant temperatures, places tremendous stress on traditional aluminum wire bonds that are used to interconnect power devices. Selection of the bond metallurgy and wire bond geometry can play a key role in mitigating this stress. An alternative solution would be to eliminate the wire bonds completely through a fundamentally different method of forming a reliable top side interconnect. Similarly, the solders used in most power modules exhibit too low of a liquidus to be viable solutions for maximum junction temperatures of 200 C. Commonly used encapsulation materials, such as silicone gels, also suffer from an inability to operate at 200 C for extended periods of time. Possible solutions to these problems exist in most cases but require changes to the traditional manufacturing process used in these modules. In addition, a number of emerging technologies such as Si nitride, flip-chip assembly methods, and the elimination of base-plates would allow reliable module development for operation of HEV and PHEV inverters at elevated junction temperatures.« less

Rapid qualification of CSP assemblies by increase of ramp rates and cycling temperature ranges

NASA Technical Reports Server (NTRS)

Ghaffarian, R.; Kim, N.; Rose, D.; Hunter, B.; Devitt, K.; Long, T.

2001-01-01

Team members representing government agencies and private companies have joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.

An ultra-compact processor module based on the R3000

NASA Astrophysics Data System (ADS)

Mullenhoff, D. J.; Kaschmitter, J. L.; Lyke, J. C.; Forman, G. A.

1992-08-01

Viable high density packaging is of critical importance for future military systems, particularly space borne systems which require minimum weight and size and high mechanical integrity. A leading, emerging technology for high density packaging is multi-chip modules (MCM). During the 1980's, a number of different MCM technologies have emerged. In support of Strategic Defense Initiative Organization (SDIO) programs, Lawrence Livermore National Laboratory (LLNL) has developed, utilized, and evaluated several different MCM technologies. Prior LLNL efforts include modules developed in 1986, using hybrid wafer scale packaging, which are still operational in an Air Force satellite mission. More recent efforts have included very high density cache memory modules, developed using laser pantography. As part of the demonstration effort, LLNL and Phillips Laboratory began collaborating in 1990 in the Phase 3 Multi-Chip Module (MCM) technology demonstration project. The goal of this program was to demonstrate the feasibility of General Electric's (GE) High Density Interconnect (HDI) MCM technology. The design chosen for this demonstration was the processor core for a MIPS R3000 based reduced instruction set computer (RISC), which has been described previously. It consists of the R3000 microprocessor, R3010 floating point coprocessor and 128 Kbytes of cache memory.

Highly efficient on-chip direct electronic-plasmonic transducers

NASA Astrophysics Data System (ADS)

Du, Wei; Wang, Tao; Chu, Hong-Son; Nijhuis, Christian A.

2017-10-01

Photonic elements can carry information with a capacity exceeding 1,000 times that of electronic components, but, due to the optical diffraction limit, these elements are large and difficult to integrate with modern-day nanoelectronics or upcoming packages, such as three-dimensional integrated circuits or stacked high-bandwidth memories1-3. Surface plasmon polaritons can be confined to subwavelength dimensions and can carry information at high speeds (>100 THz)4-6. To combine the small dimensions of nanoelectronics with the fast operating speed of optics via plasmonics, on-chip electronic-plasmonic transducers that directly convert electrical signals into plasmonic signals (and vice versa) are required. Here, we report electronic-plasmonic transducers based on metal-insulator-metal tunnel junctions coupled to plasmonic waveguides with high-efficiency on-chip generation, manipulation and readout of plasmons. These junctions can be readily integrated into existing technologies, and we thus believe that they are promising for applications in on-chip integrated plasmonic circuits.

Thermal Cycle Reliability and Failure Mechanisms of CCGA and PBGA Assemblies with and without Corner Staking

NASA Technical Reports Server (NTRS)

Ghaffarian, Reza

2008-01-01

Area array packages (AAPs) with 1.27 mm pitch have been the packages of choice for commercial applications; they are now starting to be implemented for use in military and aerospace applications. Thermal cycling characteristics of plastic ball grid array (PBGA) and chip scale package assemblies, because of their wide usage for commercial applications, have been extensively reported on in literature. Thermal cycling represents the on-off environmental condition for most electronic products and therefore is a key factor that defines reliability.However, very limited data is available for thermal cycling behavior of ceramic packages commonly used for the aerospace applications. For high reliability applications, numerous AAPs are available with an identical design pattern both in ceramic and plastic packages. This paper compares assembly reliability of ceramic and plastic packages with the identical inputs/outputs(I/Os) and pattern. The ceramic package was in the form of ceramic column grid array (CCGA) with 560 I/Os peripheral array with the identical pad design as its plastic counterpart.

Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

NASA Astrophysics Data System (ADS)

Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

2001-11-01

The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

Floating-Point Units and Algorithms for field-programmable gate arrays

DOE Office of Scientific and Technical Information (OSTI.GOV)

Underwood, Keith D.; Hemmert, K. Scott

2005-11-01

The software that we are attempting to copyright is a package of floating-point unit descriptions and example algorithm implementations using those units for use in FPGAs. The floating point units are best-in-class implementations of add, multiply, divide, and square root floating-point operations. The algorithm implementations are sample (not highly flexible) implementations of FFT, matrix multiply, matrix vector multiply, and dot product. Together, one could think of the collection as an implementation of parts of the BLAS library or something similar to the FFTW packages (without the flexibility) for FPGAs. Results from this work has been published multiple times and wemore » are working on a publication to discuss the techniques we use to implement the floating-point units, For some more background, FPGAS are programmable hardware. "Programs" for this hardware are typically created using a hardware description language (examples include Verilog, VHDL, and JHDL). Our floating-point unit descriptions are written in JHDL, which allows them to include placement constraints that make them highly optimized relative to some other implementations of floating-point units. Many vendors (Nallatech from the UK, SRC Computers in the US) have similar implementations, but our implementations seem to be somewhat higher performance. Our algorithm implementations are written in VHDL and models of the floating-point units are provided in VHDL as well. FPGA "programs" make multiple "calls" (hardware instantiations) to libraries of intellectual property (IP), such as the floating-point unit library described here. These programs are then compiled using a tool called a synthesizer (such as a tool from Synplicity, Inc.). The compiled file is a netlist of gates and flip-flops. This netlist is then mapped to a particular type of FPGA by a mapper and then a place- and-route tool. These tools assign the gates in the netlist to specific locations on the specific type of FPGA chip used and constructs the required routes between them. The result is a "bitstream" that is analogous to a compiled binary. The bitstream is loaded into the FPGA to create a specific hardware configuration.« less

Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays.

PubMed

Ciçek, Ihsan; Bozkurt, Ayhan; Karaman, Mustafa

2005-12-01

Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMUT element, we developed an electrical CMUT model with parameters derived through finite element analysis, and performed both the pre- and postlayout verification. An experimental chip consisting of 4 X 4 array of the designed circuit cells, each cell occupying a 200 X 200 microm2 area, was formed for the initial test studies and scheduled for fabrication in 0.8 microm, 50 V CMOS technology. The designed circuit is suitable for integration with CMUT arrays through flip-chip bonding and the CMUT-on-CMOS process.

Large Area MEMS Based Ultrasound Device for Cancer Detection.

PubMed

Wodnicki, Robert; Thomenius, Kai; Hooi, Fong Ming; Sinha, Sumedha P; Carson, Paul L; Lin, Der-Song; Zhuang, Xuefeng; Khuri-Yakub, Pierre; Woychik, Charles

2011-08-21

We present image results obtained using a prototype ultrasound array which demonstrates the fundamental architecture for a large area MEMS based ultrasound device for detection of breast cancer. The prototype array consists of a tiling of capacitive Micro-Machined Ultrasound Transducers (cMUTs) which have been flip-chip attached to a rigid organic substrate. The pitch on the cMUT elements is 185 um and the operating frequency is nominally 9 MHz. The spatial resolution of the new probe is comparable to production PZT probes, however the sensitivity is reduced by conditions that should be correctable. Simulated opposed-view image registration and Speed of Sound volume reconstruction results for ultrasound in the mammographic geometry are also presented.

Method to Improve Indium Bump Bonding via Indium Oxide Removal Using a Multi-Step Plasma Process

NASA Technical Reports Server (NTRS)

Dickie, Matthew R. (Inventor); Nikzad, Shouleh (Inventor); Greer, H. Frank (Inventor); Jones, Todd J. (Inventor); Vasquez, Richard P. (Inventor); Hoenk, Michael E. (Inventor)

2012-01-01

A process for removing indium oxide from indium bumps in a flip-chip structure to reduce contact resistance, by a multi-step plasma treatment. A first plasma treatment of the indium bumps with an argon, methane and hydrogen plasma reduces indium oxide, and a second plasma treatment with an argon and hydrogen plasma removes residual organics. The multi-step plasma process for removing indium oxide from the indium bumps is more effective in reducing the oxide, and yet does not require the use of halogens, does not change the bump morphology, does not attack the bond pad material or under-bump metallization layers, and creates no new mechanisms for open circuits.

Medicaid and Children's Health Insurance Programs: essential health benefits in alternative benefit plans, eligibility notices, fair hearing and appeal processes, and premiums and cost sharing; exchanges: eligibility and enrollment. Final rule.

PubMed

2013-07-15

This final rule implements provisions of the Patient Protection and Affordable Care Act and the Health Care and Education Reconciliation Act of 2010 (collectively referred to as the Affordable Care Act. This final rule finalizes new Medicaid eligibility provisions; finalizes changes related to electronic Medicaid and the Children's Health Insurance Program (CHIP) eligibility notices and delegation of appeals; modernizes and streamlines existing Medicaid eligibility rules; revises CHIP rules relating to the substitution of coverage to improve the coordination of CHIP coverage with other coverage; and amends requirements for benchmark and benchmark-equivalent benefit packages consistent with sections 1937 of the Social Security Act (which we refer to as ``alternative benefit plans'') to ensure that these benefit packages include essential health benefits and meet certain other minimum standards. This rule also implements specific provisions including those related to authorized representatives, notices, and verification of eligibility for qualifying coverage in an eligible employer-sponsored plan for Affordable Insurance Exchanges. This rule also updates and simplifies the complex Medicaid premium and cost sharing requirements, to promote the most effective use of services, and to assist states in identifying cost sharing flexibilities. It includes transition policies for 2014 as applicable.

Effecting aging time of epoxy molding compound to molding process for integrated circuit packaging

NASA Astrophysics Data System (ADS)

Tachapitunsuk, Jirayu; Ugsornrat, Kessararat; Srisuwitthanon, Warayoot; Thonglor, Panakamon

2017-09-01

This research studied about effecting aging time of epoxy molding compound (EMC) that effect to reliability performance of integrated circuit (IC) package in molding process. Molding process is so important of IC packaging process for protecting IC chip (or die) from temperature and humidity environment using encapsulated EMC. For general molding process, EMC are stored in the frozen at 5°C and left at room temperature at 25 °C for aging time on self before molding of die onto lead frame is 24 hours. The aging time effect to reliability performance of IC package due to different temperature and humidity inside the package. In experiment, aging time of EMC were varied from 0 to 24 hours for molding process of SOIC-8L packages. For analysis, these packages were tested by x-ray and scanning acoustic microscope to analyze properties of EMC with an aging time and also analyzed delamination, internal void, and wire sweep inside the packages with different aging time. The results revealed that different aging time of EMC effect to properties and reliability performance of molding process.

Food product design: emerging evidence for food policy.

PubMed

Al-Hamdani, Mohammed; Smith, Steven

2017-03-01

The research on the impact of specific brand elements such as food descriptors and package colors is underexplored. We tested whether a "light" color and a "low-calorie" descriptor on food packages gain favorable consumer perception ratings as compared with regular packages. Our online experiment recruited 406 adults in a 3 (product type: Chips versus Juice versus Yoghurt) × 2 (descriptor type: regular versus low-calorie) × 2 (color type: regular versus light) mixed design. Dependent variables were sensory (evaluations of the product's nutritional value and quality), product-based (evaluations of the product's physical appeal), and consumer-based (evaluations of the potential consumers of the product) scales. "Low-calorie" descriptors were found to increase sensory ratings as compared with regular descriptors and light-colored packages received higher product-based ratings as compared with their regular-colored counterparts. Food package color and descriptors present a promising venue for understanding preventative measures against obesity.[Formula: see text].

Partition resampling and extrapolation averaging: approximation methods for quantifying gene expression in large numbers of short oligonucleotide arrays.

PubMed

Goldstein, Darlene R

2006-10-01

Studies of gene expression using high-density short oligonucleotide arrays have become a standard in a variety of biological contexts. Of the expression measures that have been proposed to quantify expression in these arrays, multi-chip-based measures have been shown to perform well. As gene expression studies increase in size, however, utilizing multi-chip expression measures is more challenging in terms of computing memory requirements and time. A strategic alternative to exact multi-chip quantification on a full large chip set is to approximate expression values based on subsets of chips. This paper introduces an extrapolation method, Extrapolation Averaging (EA), and a resampling method, Partition Resampling (PR), to approximate expression in large studies. An examination of properties indicates that subset-based methods can perform well compared with exact expression quantification. The focus is on short oligonucleotide chips, but the same ideas apply equally well to any array type for which expression is quantified using an entire set of arrays, rather than for only a single array at a time. Software implementing Partition Resampling and Extrapolation Averaging is under development as an R package for the BioConductor project.

Development Of A Three-Dimensional Circuit Integration Technology And Computer Architecture

NASA Astrophysics Data System (ADS)

Etchells, R. D.; Grinberg, J.; Nudd, G. R.

1981-12-01

This paper is the first of a series 1,2,3 describing a range of efforts at Hughes Research Laboratories, which are collectively referred to as "Three-Dimensional Microelectronics." The technology being developed is a combination of a unique circuit fabrication/packaging technology and a novel processing architecture. The packaging technology greatly reduces the parasitic impedances associated with signal-routing in complex VLSI structures, while simultaneously allowing circuit densities orders of magnitude higher than the current state-of-the-art. When combined with the 3-D processor architecture, the resulting machine exhibits a one- to two-order of magnitude simultaneous improvement over current state-of-the-art machines in the three areas of processing speed, power consumption, and physical volume. The 3-D architecture is essentially that commonly referred to as a "cellular array", with the ultimate implementation having as many as 512 x 512 processors working in parallel. The three-dimensional nature of the assembled machine arises from the fact that the chips containing the active circuitry of the processor are stacked on top of each other. In this structure, electrical signals are passed vertically through the chips via thermomigrated aluminum feedthroughs. Signals are passed between adjacent chips by micro-interconnects. This discussion presents a broad view of the total effort, as well as a more detailed treatment of the fabrication and packaging technologies themselves. The results of performance simulations of the completed 3-D processor executing a variety of algorithms are also presented. Of particular pertinence to the interests of the focal-plane array community is the simulation of the UNICORNS nonuniformity correction algorithms as executed by the 3-D architecture.

Nonvolatile memory chips: critical technology for high-performance recce systems

NASA Astrophysics Data System (ADS)

Kaufman, Bruce

2000-11-01

Airborne recce systems universally require nonvolatile storage of recorded data. Both present and next generation designs make use of flash memory chips. Flash memory devices are in high volume use for a variety of commercial products ranging form cellular phones to digital cameras. Fortunately, commercial applications call for increasing capacities and fast write times. These parameters are important to the designer of recce recorders. Of economic necessity COTS devices are used in recorders that must perform in military avionics environments. Concurrently, recording rates are moving to $GTR10Gb/S. Thus to capture imagery for even a few minutes of record time, tactically meaningful solid state recorders will require storage capacities in the 100s of Gbytes. Even with memory chip densities at present day 512Mb, such capacities require thousands of chips. The demands on packaging technology are daunting. This paper will consider the differing flash chip architectures, both available and projected and discuss the impact on recorder architecture and performance. Emerging nonvolatile memory technologies, FeRAM AND MIRAM will be reviewed with regard to their potential use in recce recorders.

A novel readout integrated circuit for ferroelectric FPA detector

NASA Astrophysics Data System (ADS)

Bai, Piji; Li, Lihua; Ji, Yulong; Zhang, Jia; Li, Min; Liang, Yan; Hu, Yanbo; Li, Songying

2017-11-01

Uncooled infrared detectors haves some advantages such as low cost light weight low power consumption, and superior reliability, compared with cryogenically cooled ones Ferroelectric uncooled focal plane array(FPA) are being developed for its AC response and its high reliability As a key part of the ferroelectric assembly the ROIC determines the performance of the assembly. A top-down design model for uncooled ferroelectric readout integrated circuit(ROIC) has been developed. Based on the optical thermal and electrical properties of the ferroelectric detector the RTIA readout integrated circuit is designed. The noise bandwidth of RTIA readout circuit has been developed and analyzed. A novel high gain amplifier, a high pass filter and a low pass filter circuits are designed on the ROIC. In order to improve the ferroelectric FPA package performance and decrease of package cost a temperature sensor is designed on the ROIC chip At last the novel RTIA ROIC is implemented on 0.6μm 2P3M CMOS silicon techniques. According to the experimental chip test results the temporal root mean square(RMS)noise voltage is about 1.4mV the sensitivity of the on chip temperature sensor is 0.6 mV/K from -40°C to 60°C the linearity performance of the ROIC chip is better than 99% Based on the 320×240 RTIA ROIC, a 320×240 infrared ferroelectric FPA is fabricated and tested. Test results shows that the 320×240 RTIA ROIC meets the demand of infrared ferroelectric FPA.

Indium phosphide-based monolithically integrated PIN waveguide photodiode readout for resonant cantilever sensors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Siwak, N. P.; Laboratory for the Physical Sciences, 8050 Greenmead Drive, College Park, Maryland 20740; Fan, X. Z.

2014-10-06

An integrated photodiode displacement readout scheme for a microelectromechanical cantilever waveguide resonator sensing platform is presented. III-V semiconductors are used to enable the monolithic integration of passive waveguides with active optical components. This work builds upon previously demonstrated results by measuring the displacement of cantilever waveguide resonators with on-chip waveguide PIN photodiodes. The on-chip integration of the readout provides an additional 70% improvement in mass sensitivity compared to off-chip photodetector designs due to measurement stability and minimized coupling loss. In addition to increased measurement stability, reduced packaging complexity is achieved due to the simplicity of the readout design. We havemore » fabricated cantilever waveguides with integrated photodetectors and experimentally characterized these cantilever sensors with monolithically integrated PIN photodiodes.« less

Perforated hollow-core optical waveguides for on-chip atomic spectroscopy and gas sensing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Giraud-Carrier, M., E-mail: mgeecee@byu.edu; Hill, C.; Decker, T.

2016-03-28

A hollow-core waveguide structure for on-chip atomic spectroscopy is presented. The devices are based on Anti-Resonant Reflecting Optical Waveguides and may be used for a wide variety of applications which rely on the interaction of light with gases and vapors. The designs presented here feature short delivery paths of the atomic vapor into the hollow waveguide. They also have excellent environmental stability by incorporating buried solid-core waveguides to deliver light to the hollow cores. Completed chips were packaged with an Rb source and the F = 3 ≥ F′ = 2, 3, 4 transitions of the D2 line in {sup 85}Rb were monitored formore » optical absorption. Maximum absorption peak depths of 9% were measured.« less

QTL mapping of potato chip color and tuber traits within an autotetraploid family

USDA-ARS?s Scientific Manuscript database

Cultivated potato (Solanum tuberosum L.) is a highly heterozygous autotetraploid crop species, and this presents challenges for traditional line development and molecular breeding. Recent availability of a single nucleotide polymorphism (SNP) array with 8303 features and software packages for linkag...

Fabrication method to create high-aspect ratio pillars for photonic coupling of board level interconnects

NASA Astrophysics Data System (ADS)

Debaes, C.; Van Erps, J.; Karppinen, M.; Hiltunen, J.; Suyal, H.; Last, A.; Lee, M. G.; Karioja, P.; Taghizadeh, M.; Mohr, J.; Thienpont, H.; Glebov, A. L.

2008-04-01

An important challenge that remains to date in board level optical interconnects is the coupling between the optical waveguides on printed wiring boards and the packaged optoelectronics chips, which are preferably surface mountable on the boards. One possible solution is the use of Ball Grid Array (BGA) packages. This approach offers a reliable attachment despite the large CTE mismatch between the organic FR4 board and the semiconductor materials. Collimation via micro-lenses is here typically deployed to couple the light vertically from the waveguide substrate to the optoelectronics while allowing for a small misalignment between board and package. In this work, we explore the fabrication issues of an alternative approach in which the vertical photonic connection between board and package is governed by a micro-optical pillar which is attached both to the board substrate and to the optoelectronic chips. Such an approach allows for high density connections and small, high-speed detector footprints while maintaining an acceptable tolerance between board and package. The pillar should exhibit some flexibility and thus a high-aspect ratio is preferred. This work presents and compares different fabrication methods and applies different materials for such high-aspect ratio pillars. The different fabrication methods are: photolithography, direct laser writing and deep proton writing. The selection of optical materials that was investigated is: SU8, Ormocers, PU and a multifunctional acrylate polymer. The resulting optical pillars have diameters ranging from 20um up to 80um, with total heights ranging between 30um and 100um (symbol for micron). The aspect-ratio of the fabricated structures ranges from 1.5 to 5.

Use of optical technique for inspection of warpage of IC packages

NASA Astrophysics Data System (ADS)

Toh, Siew-Lok; Chau, Fook S.; Ong, Sim Heng

2001-06-01

The packaging of IC packages has changed over the years, form dual-in-line, wire-bond, and pin-through-hole in printed wiring board technologies in the 1970s to ball grid array, chip scale and surface mount technologies in the 1990s. Reliability has been a big problem for manufacturers for some moisture-sensitive packages. One of the potential problems in plastic IC packages is moisture-induced popcorn effect which can arise during the reflow process. Shearography is a non-destructive inspection technique that may be used to detect the delamination and warpage of IC packages. It is non-contacting and permits a full-field observation of surface displacement derivatives. Another advantage of this technique is that it is able to give the real-time formation of the fringes which indicate flaws in the IC package under real-time simulation condition of Surface Mount Technology (SMT) IR reflow profile. It is extremely fast and convenient to study the true behavior of the packaging deformation during the SMT process. It can be concluded that shearography has the potential for the real- time detection, in situ and non-destructive inspection of IC packages during the surface mount process.

Design and realization of 144 x 7 TDI ROIC with hybrid integrated test structure

NASA Astrophysics Data System (ADS)

Ceylan, Omer; Kayahan, Huseyin; Yazici, Melik; Baran, Muhammet Burak; Gurbuz, Yasar

2012-06-01

Design and realization of a 144x7 silicon readout integrated circuit (ROIC) based on switched capacitor TDI for MCT LWIR scanning type focal plane arrays (FPAs) and its corresponding hybrid integrated test circuits are presented. TDI operation with 7 detectors improves the SNR of the system by a factor of √7, while oversampling rate of 3 improves the spatial resolution of the system. ROIC supports bidirectional scan, 5 adjustable gain settings, bypass operation, automatic gain adjustment in case of mulfunctioning pixels and pixel select/deselect properties. Integration time of the system can be determined by the help of an external clock. Programming of ROIC can be done in parallel or serial mode according to the needs of the system. All properties except pixel select/deselect property can be performed in parallel mode, while pixel select/deselect property can be performed only in serial mode. ROIC can handle up to 3.75V dynamic range with a load of 25pF and output settling time of 80ns. Input referred noise of the ROIC is less than 750 rms electrons, while the power consumption is less than 100mW. To test ROIC in absence of detector array, a process and temperature compensated current reference array, which supplies uniform input current in range of 1-50nA to ROIC, is designed and measured both in room and cryogenic (77ºK) temperatures. Standard deviations of current reference arrays are measured 3.26% for 1nA and 0.99% for 50nA. ROIC and current reference array are fabricated seperately, and then flip-chip bonded for the test of the system. Flip-chip bonded system including ROIC and current reference test array is successfully measured both in room and cryogenic temperatures, and measurement results are presented. The manufacturing technology is 0.35μm, double poly-Si, four metal, 5V CMOS process.

Crossmodal correspondences in product packaging. Assessing color-flavor correspondences for potato chips (crisps).

PubMed

Piqueras-Fiszman, Betina; Spence, Charles

2011-12-01

We report a study designed to investigate consumers' crossmodal associations between the color of packaging and flavor varieties in crisps (potato chips). This product category was chosen because of the long-established but conflicting color-flavor conventions that exist for the salt and vinegar and cheese and onion flavor varieties in the UK. The use of both implicit and explicit measures of this crossmodal association revealed that consumers responded more slowly, and made more errors, when they had to pair the color and flavor that they implicitly thought of as being "incongruent" with the same response key. Furthermore, clustering consumers by the brand that they normally purchased revealed that the main reason why this pattern of results was observed could be their differing acquaintance with one brand versus another. In addition, when participants tried the two types of crisps from "congruently" and "incongruently" colored packets, some were unable to guess the flavor correctly in the latter case. These strong crossmodal associations did not have a significant effect on participants' hedonic appraisal of the crisps, but did arouse confusion. These results are relevant in terms of R&D, since ascertaining the appropriate color of the packaging across flavor varieties ought normally to help achieve immediate product recognition and consumer satisfaction. Copyright © 2011 Elsevier Ltd. All rights reserved.

Stochastic and Deterministic Crystal Structure Solution Methods in GSAS-II: Monte Carlo/Simulated Annealing Versus Charge Flipping

DOE PAGES

Von Dreele, Robert

2017-08-29

One of the goals in developing GSAS-II was to expand from the capabilities of the original General Structure Analysis System (GSAS) which largely encompassed just structure refinement and post refinement analysis. GSAS-II has been written almost entirely in Python loaded with graphics, GUI and mathematical packages (matplotlib, pyOpenGL, wxpython, numpy and scipy). Thus, GSAS-II has a fully developed modern GUI as well as extensive graphical display of data and results. However, the structure and operation of Python has required new approaches to many of the algorithms used in crystal structure analysis. The extensions beyond GSAS include image calibration/integration as wellmore » as peak fitting and unit cell indexing for powder data which are precursors for structure solution. Structure solution within GSAS-II begins with either Pawley or LeBail extracted structure factors from powder data or those measured in a single crystal experiment. Both charge flipping and Monte Carlo-Simulated Annealing techniques are available; the former can be applied to (3+1) incommensurate structures as well as conventional 3D structures.« less

EdREC: Design and Development of Adaptive Platform for Scaling-up Flipped Mastery Learning

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gautam, Thakur

EdREC is an adaptive learning and management platform designed to enhance the adoption of differential classroom and mastery flipped learning in K-12 school system. The platform is an innovative approach to teaching and learning that addresses education needs of each student separately by providing customized education plans and adaptive learning methodologies that tunes to the students abilities as well as giving students freedom to learn in their own way. On one side, EdREC provides innovative ways to help students learn; on the other side, it reduces educators' workload and empowers them to understand their students better. EdREC comes with amore » state-of-the-art computer algorithm package that enables educators to store and retrieve their students' information and augment their abilities to individualize student attention, get real-time feedback about student education progress, and provide corrective actions. The platform provides approaches to design and develop a differential classroom concept that frees much needed time by the teachers to focus more on the students at the individual level and to increase communication and collaboration opportunities among them.« less

Novel Micro ElectroMechanical Systems (MEMS) Packaging for the Skin of the Satellite

NASA Technical Reports Server (NTRS)

Darrin, M. Ann; Osiander, Robert; Lehtonen, John; Farrar, Dawnielle; Douglas, Donya; Swanson, Ted

2004-01-01

This paper includes a discussion of the novel packaging techniques that are needed to place MEMS based thermal control devices on the skin of various satellites, eliminating the concern associated with potential particulates &om integration and test or the launch environment. Protection of this MEMS based thermal device is achieved using a novel polymer that is both IR transmissive and electrically conductive. This polymer was originally developed and qualified for space flight application by NASA at the Langley Research Center. The polymer material, commercially known as CPI, is coated with a thin layer of ITO and sandwiched between two window-like frames. The packaging of the MEMS based radiator assembly offers the benefits of micro-scale devices in a chip on board fashion, with the level of protection generally found in packaged parts.

The chip-scale atomic clock : prototype evaluation.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mescher, Mark; Varghese, Mathew; Lutwak, Robert

2007-12-01

The authors have developed a chip-scale atomic clock (CSAC) for applications requiring atomic timing accuracy in portable battery-powered applications. At PTTI/FCS 2005, they reported on the demonstration of a prototype CSAC, with an overall size of 10 cm{sup 3}, power consumption > 150 mW, and short-term stability sy(t) < 1 x 10-9t-1/2. Since that report, they have completed the development of the CSAC, including provision for autonomous lock acquisition and a calibrated output at 10.0 MHz, in addition to modifications to the physics package and system architecture to improve performance and manufacturability.

Chip Scale Atomic Resonator Frequency Stabilization System With Ultra-Low Power Consumption for Optoelectronic Oscillators.

PubMed

Zhao, Jianye; Zhang, Yaolin; Lu, Haoyuan; Hou, Dong; Zhang, Shuangyou; Wang, Zhong

2016-07-01

We present a long-term chip scale stabilization scheme for optoelectronic oscillators (OEOs) based on a rubidium coherent population trapping (CPT) atomic resonator. By locking a single mode of an OEO to the (85)Rb 3.035-GHz CPT resonance utilizing an improved phase-locked loop (PLL) with a PID regulator, we achieved a chip scale frequency stabilization system for the OEO. The fractional frequency stability of the stabilized OEO by overlapping Allan deviation reaches 6.2 ×10(-11) (1 s) and  ∼ 1.45 ×10 (-11) (1000 s). This scheme avoids a decrease in the extra phase noise performance induced by the electronic connection between the OEO and the microwave reference in common injection locking schemes. The total physical package of the stabilization system is [Formula: see text] and the total power consumption is 400 mW, which provides a chip scale and portable frequency stabilization approach with ultra-low power consumption for OEOs.

Electronic Switch Arrays for Managing Microbattery Arrays

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Alahmad, Mahmoud; Sukumar, Vinesh; Zghoul, Fadi; Buck, Kevin; Hess, Herbert; Li, Harry; Cox, David

2008-01-01

Integrated circuits have been invented for managing the charging and discharging of such advanced miniature energy-storage devices as planar arrays of microscopic energy-storage elements [typically, microscopic electrochemical cells (microbatteries) or microcapacitors]. The architecture of these circuits enables implementation of the following energy-management options: dynamic configuration of the elements of an array into a series or parallel combination of banks (subarrarys), each array comprising a series of parallel combination of elements; direct addressing of individual banks for charging/or discharging; and, disconnection of defective elements and corresponding reconfiguration of the rest of the array to utilize the remaining functional elements to obtain the desited voltage and current performance. An integrated circuit according to the invention consists partly of a planar array of field-effect transistors that function as switches for routing electric power among the energy-storage elements, the power source, and the load. To connect the energy-storage elements to the power source for charging, a specific subset of switches is closed; to connect the energy-storage elements to the load for discharging, a different specific set of switches is closed. Also included in the integrated circuit is circuitry for monitoring and controlling charging and discharging. The control and monitoring circuitry, the switching transistors, and interconnecting metal lines are laid out on the integrated-circuit chip in a pattern that registers with the array of energy-storage elements. There is a design option to either (1) fabricate the energy-storage elements in the corresponding locations on, and as an integral part of, this integrated circuit; or (2) following a flip-chip approach, fabricate the array of energy-storage elements on a separate integrated-circuit chip and then align and bond the two chips together.

Scalable Manufacturing of Solderable and Stretchable Physiologic Sensing Systems.

PubMed

Kim, Yun-Soung; Lu, Jesse; Shih, Benjamin; Gharibans, Armen; Zou, Zhanan; Matsuno, Kristen; Aguilera, Roman; Han, Yoonjae; Meek, Ann; Xiao, Jianliang; Tolley, Michael T; Coleman, Todd P

2017-10-01

Methods for microfabrication of solderable and stretchable sensing systems (S4s) and a scaled production of adhesive-integrated active S4s for health monitoring are presented. S4s' excellent solderability is achieved by the sputter-deposited nickel-vanadium and gold pad metal layers and copper interconnection. The donor substrate, which is modified with "PI islands" to become selectively adhesive for the S4s, allows the heterogeneous devices to be integrated with large-area adhesives for packaging. The feasibility for S4-based health monitoring is demonstrated by developing an S4 integrated with a strain gauge and an onboard optical indication circuit. Owing to S4s' compatibility with the standard printed circuit board assembly processes, a variety of commercially available surface mount chip components, such as the wafer level chip scale packages, chip resistors, and light-emitting diodes, can be reflow-soldered onto S4s without modifications, demonstrating the versatile and modular nature of S4s. Tegaderm-integrated S4 respiration sensors are tested for robustness for cyclic deformation, maximum stretchability, durability, and biocompatibility for multiday wear time. The results of the tests and demonstration of the respiration sensing indicate that the adhesive-integrated S4s can provide end users a way for unobtrusive health monitoring. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Extremely Low Frequency-Magnetic Field (ELF-MF) Exposure Characteristics among Semiconductor Workers

PubMed Central

Choi, Sangjun; Cha, Wonseok; Kim, Won; Yoon, Chungsik; Park, Ju-Hyun; Ha, Kwonchul; Park, Donguk

2018-01-01

We assessed the exposure of semiconductor workers to extremely low frequency-magnetic fields (ELF-MF) and identified job characteristics affecting ELF-MF exposure. These were demonstrated by assessing the exposure of 117 workers involved in wafer fabrication (fab) and chip packaging wearing personal dosimeters for a full shift. A portable device was used to monitor ELF-MF in high temporal resolution. All measurements were categorized by operation, job and working activity during working time. ELF-MF exposure of workers were classified based on the quartiles of ELF-MF distribution. The average levels of ELF-MF exposure were 0.56 µT for fab workers, 0.59 µT for chip packaging workers and 0.89 µT for electrical engineers, respectively. Exposure to ELF-MF differed among types of factory, operation, job and activity. Workers engaged in the diffusion and chip testing activities showed the highest ELF-MF exposure. The ELF-MF exposures of process operators were found to be higher than those of maintenance engineers, although peak exposure and/or patterns varied. The groups with the highest quartile ELF-MF exposure level are operators in diffusion, ion implantation, module and testing operations, and maintenance engineers in diffusion, module and testing operations. In conclusion, ELF-MF exposure among workers can be substantially affected by the type of operation and job, and the activity or location. PMID:29614730

Ultra-thin ohmic contacts for p-type nitride light emitting devices

DOEpatents

Raffetto, Mark; Bharathan, Jayesh; Haberern, Kevin; Bergmann, Michael; Emerson, David; Ibbetson, James; Li, Ting

2014-06-24

A flip-chip semiconductor based Light Emitting Device (LED) can include an n-type semiconductor substrate and an n-type GaN epi-layer on the substrate. A p-type GaN epi-layer can be on the n-type GaN epi-layer and a metal ohmic contact p-electrode can be on the p-type GaN epi-layer, where the metal ohmic contact p-electrode can have an average thickness less than about 25 .ANG.. A reflector can be on the metal ohmic contact p-electrode and a metal stack can be on the reflector. An n-electrode can be on the substrate opposite the n-type GaN epi-layer and a bonding pad can be on the n-electrode.

Large area MEMS based ultrasound device for cancer detection

NASA Astrophysics Data System (ADS)

Wodnicki, Robert; Thomenius, Kai; Ming Hooi, Fong; Sinha, Sumedha P.; Carson, Paul L.; Lin, Der-Song; Zhuang, Xuefeng; Khuri-Yakub, Pierre; Woychik, Charles

2011-08-01

We present image results obtained using a prototype ultrasound array that demonstrates the fundamental architecture for a large area MEMS based ultrasound device for detection of breast cancer. The prototype array consists of a tiling of capacitive Micromachined Ultrasound Transducers (cMUTs) that have been flip-chip attached to a rigid organic substrate. The pitch on the cMUT elements is 185 μm and the operating frequency is nominally 9 MHz. The spatial resolution of the new probe is comparable to those of production PZT probes; however the sensitivity is reduced by conditions that should be correctable. Simulated opposed-view image registration and Speed of Sound volume reconstruction results for ultrasound in the mammographic geometry are also presented.

Enhanced light extraction in tunnel junction-enabled top emitting UV LEDs

DOE PAGES

Zhang, Yuewei; Allerman, Andrew A.; Krishnamoorthy, Sriram; ...

2016-04-11

The efficiency of ultra violet LEDs has been critically limited by the absorption losses in p-type and metal layers. In this work, surface roughening based light extraction structures are combined with tunneling based p-contacts to realize highly efficient top-side light extraction efficiency in UV LEDs. Surface roughening of the top n-type AlGaN contact layer is demonstrated using self-assembled Ni nano-clusters as etch mask. The top surface roughened LEDs were found to enhance external quantum efficiency by over 40% for UV LEDs with a peak emission wavelength of 326 nm. The method described here can enable highly efficient UV LEDs withoutmore » the need for complex manufacturing methods such as flip chip bonding.« less

An implantable myoelectric sensor based prosthesis control system.

PubMed

DeMichele, Glenn A; Troyk, Philip R; Kerns, Douglas A; Weir, Richard

2006-01-01

We present progress on the design and testing of an upper-extremity prosthesis control system based on implantable myoelectric sensors. The implant consists of a single silicon chip packaged with transmit and receive coils. Forward control telemetry to, and reverse EMG data telemetry from multiple implants has been demonstrated.

Convenience stores and the marketing of foods and beverages through product assortment.

PubMed

Sharkey, Joseph R; Dean, Wesley R; Nalty, Courtney

2012-09-01

Product assortment (presence and variety) is a key in-store marketing strategy to influence consumer choice. Quantifying the product assortment of healthier and less-healthy foods and beverages in convenience stores can inform changes in the food environment. To document product assortment (i.e., presence and variety of specific foods and beverages) in convenience stores. Observational survey data were collected onsite in 2011 by trained promotora-researchers in 192 convenience stores. Frequencies of presence and distributions of variety were calculated in 2012. Paired differences were examined using the Wilcoxon matched-pairs signed-rank test. Convenience stores displayed a large product assortment of sugar-sweetened beverages (median 86.5 unique varieties); candy (76 varieties); salty snacks (77 varieties); fried chips (44 varieties); cookies and pastries (19 varieties); and frozen sweets (21 varieties). This compared with 17 varieties of non-sugar sweetened beverages and three varieties of baked chips. The Wilcoxon signed-rank test confirmed a (p<0.001) greater variety of sugar-sweetened than non-sugar-sweetened beverages, and of fried chips compared with baked chips. Basic food items provided by convenience stores included milk (84% of stores); fresh fruit (33%); fresh vegetables (35%); canned vegetables (78%); white bread (71%); and deli-style packaged meat (57%). Healthier versions of milk, canned fruit, canned tuna, bread, and deli-style packaged meat were displayed in 17%-71% of convenience stores. Convenience stores in this area provide a greater assortment of less-healthy compared with healthier foods and beverages. There are opportunities to influence consumer food choice through programs that alter the balance between healthier and less-healthy foods and beverages in existing convenience stores that serve rural and underserved neighborhoods and communities. Copyright © 2012 American Journal of Preventive Medicine. Published by Elsevier Inc. All rights reserved.

Prototype of a gigabit data transmitter in 65 nm CMOS for DEPFET pixel detectors at Belle-II

NASA Astrophysics Data System (ADS)

Kishishita, T.; Krüger, H.; Hemperek, T.; Lemarenko, M.; Koch, M.; Gronewald, M.; Wermes, N.

2013-08-01

This paper describes the recent development of a gigabit data transmitter for the Belle-II pixel detector (PXD). The PXD is an innermost detector currently under development for the upgraded KEK-B factory in Japan. The PXD consists of two layers of DEPFET sensor modules located at 1.8 and 2.2 cm radii. Each module is equipped with three different ASIC types mounted on the detector substrate with a flip-chip technique: (a) SWITCHER for generating steering signals for the DEPFET sensors, (b) DCD for digitizing the signal currents, and (c) DHP for performing data processing and sending the data off the module to the back-end data handling hybrid via ∼ 40 cm Kapton flex and 12-15 m twisted pair (TWP) cables. To meet the requirements of the PXD data transmission, a prototype of the DHP data transmitter has been developed in a 65-nm standard CMOS technology. The transmitter test chip consists of current-mode logic (CML) drivers and a phase-locked loop (PLL) which generates a clock signal for a 1.6 Gbit/s output data stream from an 80 cm reference clock. A programmable pre-emphasis circuit is also implemented in the CML driver to compensate signal losses in the long cable by shaping the transmitted pulse response. The jitter performance was measured as 25 ps (1 σ distribution) by connecting the chip with 38 cm flex and 10 m TWP cables.

On the release of cppxfel for processing X-ray free-electron laser images.

PubMed

Ginn, Helen Mary; Evans, Gwyndaf; Sauter, Nicholas K; Stuart, David Ian

2016-06-01

As serial femtosecond crystallography expands towards a variety of delivery methods, including chip-based methods, and smaller collected data sets, the requirement to optimize the data analysis to produce maximum structure quality is becoming increasingly pressing. Here cppxfel , a software package primarily written in C++, which showcases several data analysis techniques, is released. This software package presently indexes images using DIALS (diffraction integration for advanced light sources) and performs an initial orientation matrix refinement, followed by post-refinement of individual images against a reference data set. Cppxfel is released with the hope that the unique and useful elements of this package can be repurposed for existing software packages. However, as released, it produces high-quality crystal structures and is therefore likely to be also useful to experienced users of X-ray free-electron laser (XFEL) software who wish to maximize the information extracted from a limited number of XFEL images.

Packaging Technology for SiC High Temperature Circuits Operable up to 500 Degrees Centigrade

NASA Technical Reports Server (NTRS)

Chen, Lian-Yu

2002-01-01

New high temperature low power 8-pin packages have been fabricated using commercial fabrication service. These packages are made of aluminum nitride and 96 percent alumina with Au metallization. The new design of these packages provides the chips inside with EM shielding. Wirebond geometry control has been achieved for precise mechanical tests. Au wirebond samples with 45 degree heel-angle have been tested using wireloop test module. The geometry control improves the consistency of measurement of the wireloop breaking point.Also reported on is a parametric study of the thermomechanical reliability of a Au thick-film based SiC die-attach assembly using nonlinear finite element analysis (FEA) was conducted to optimize the die-attach thermo-mechanical performance for operation at temperatures from room temperature to 500 degrees Centigrade. This parametric study centered on material selection, structure design and process control.

On the release of cppxfel for processing X-ray free-electron laser images

DOE PAGES

Ginn, Helen Mary; Evans, Gwyndaf; Sauter, Nicholas K.; ...

2016-05-11

As serial femtosecond crystallography expands towards a variety of delivery methods, including chip-based methods, and smaller collected data sets, the requirement to optimize the data analysis to produce maximum structure quality is becoming increasingly pressing. Herecppxfel, a software package primarily written in C++, which showcases several data analysis techniques, is released. This software package presently indexes images using DIALS (diffraction integration for advanced light sources) and performs an initial orientation matrix refinement, followed by post-refinement of individual images against a reference data set.Cppxfelis released with the hope that the unique and useful elements of this package can be repurposed formore » existing software packages. However, as released, it produces high-quality crystal structures and is therefore likely to be also useful to experienced users of X-ray free-electron laser (XFEL) software who wish to maximize the information extracted from a limited number of XFEL images.« less

Ubiquitin-specific protease 8 links the PTEN-Akt-AIP4 pathway to the control of FLIPS stability and TRAIL sensitivity in glioblastoma multiforme.

PubMed

Panner, Amith; Crane, Courtney A; Weng, Changjiang; Feletti, Alberto; Fang, Shanna; Parsa, Andrew T; Pieper, Russell O

2010-06-15

The antiapoptotic protein FLIP(S) is a key suppressor of tumor necrosis factor-related apoptosis-inducing ligand (TRAIL)-induced apoptosis in human glioblastoma multiforme (GBM) cells. We previously reported that a novel phosphatase and tensin homologue (PTEN)-Akt-atrophin-interacting protein 4 (AIP4) pathway regulates FLIP(S) ubiquitination and stability, although the means by which PTEN and Akt were linked to AIP4 activity were unclear. Here, we report that a second regulator of ubiquitin metabolism, the ubiquitin-specific protease 8 (USP8), is a downstream target of Akt, and that USP8 links Akt to AIP4 and the regulation of FLIP(S) stability and TRAIL resistance. In human GBM xenografts, levels of USP8 correlated inversely with pAkt levels, and genetic or pharmacologic manipulation of Akt regulated USP8 levels in an inverse manner. Overexpression of wild-type USP8, but not catalytically inactive USP8, increased FLIP(S) ubiquitination, decreased FLIP(S) half-life, decreased FLIP(S) steady-state levels, and decreased TRAIL resistance, whereas short interfering RNA (siRNA)-mediated suppression of USP8 levels had the opposite effect. Because high levels of the USP8 deubiquitinase correlated with high levels of FLIP(S) ubiquitination, USP8 seemed to control FLIP(S) ubiquitination through an intermediate target. Consistent with this idea, overexpression of wild-type USP8 decreased the ubiquitination of the FLIP(S) E3 ubiquitin ligase AIP4, an event previously shown to increase AIP4-FLIP(S) interaction, whereas siRNA-mediated suppression of USP8 increased AIP4 ubiquitination. Furthermore, the suppression of FLIP(S) levels by USP8 overexpression was reversed by the introduction of siRNA targeting AIP4. These results show that USP8, a downstream target of Akt, regulates the ability of AIP4 to control FLIP(S) stability and TRAIL sensitivity.

Interconnect mechanisms in microelectronic packaging

NASA Astrophysics Data System (ADS)

Roma, Maria Penafrancia C.

Global economic, environmental and market developments caused major impact in the microelectronics industry. Astronomical rise of gold metal prices over the last decade shifted the use of copper and silver alloys as bonding wires. Environmental legislation on the restriction of the use of Pb launched worldwide search for lead-free solders and platings. Finally, electrical and digital uses demanded smaller, faster and cheaper devices. Ultra-fine pitch bonding, decreasing bond wire sizes and hard to bond substrates have put the once-robust stitch bond in the center of reliability issues due to stitch bond lift or open wires .Unlike the ball bond, stitch bonding does not lead to intermetallic compound formation but adhesion is dependent on mechanical deformation, interdiffusion, solid solution formation, void formation and mechanical interlocking depending on the wire material, bond configuration, substrate type , thickness and surface condition. Using Au standoff stitch bonds on NiPdAu plated substrates eliminated stitch bond lift even when the Au and Pd layers are reduced. Using the Matano-Boltzmann analysis on a STEM (Scanning Transmission Analysis) concentration profile the interdiffusion coefficient is measured to be 10-16 cm 2/s. Wire pull strength data showed that the wire pull strength is 0.062N and increases upon stress testing. Meanwhile, coating the Cu wire with Pd, not only increases oxidation resistance but also improved adhesion due to the formation of a unique interfacial adhesion layers. Adhesion strength as measured by pull showed the Cu wire bonded to Ag plated Cu substrate (0.132N) to be stronger than the Au wire bonded on the same substrate (0.124N). Ag stitch bonded to Au is predicted to be strong but surface modification made the adhesion stronger. However, on the Ag ball bonded to Al showed multiple IMC formation with unique morphology exposed by ion milling and backscattered scanning electron microscopy. Adding alloying elements in the Ag wire alloy showed differences in adhesion strength and IMC formation. Bond strength by wire pull testing showed the 95Ag alloy with higher values while shear bond testing showed the 88Ag higher bond strength. Use of Cu pillars in flip chips and eutectic bonding in wafer level chip scale packages are direct consequences of diminishing interconnect dimension as a result of the drive for miniaturization. The combination of Cu-Sn interdiffusion, Kirkendall mechanism and heterogeneous vacancy precipitation are the main causes of IMC and void formation in Cu pillar - Sn solder - Cu lead frame sandwich structure. However, adding a Ni barrier agent showed less porous IMC layer as well as void formation as a result of the modified Cu and Sn movement well as the void formation. Direct die to die bonding using Al-Ge eutectic bonds is necessary when 3D integration is needed to reduce the footprint of a package. Hermeticity and adhesion strength are a function of the Al/Ge thickness ratio, bonding pressure, temperature and time. Scanning Electron Microscope (SEM) and Focused Ion Beam (FIB) allowed imaging of interfacial microstructures, porosity, grain morphology while Scanning Transmission Electron microscope (STEM) provided diffusion profile and confirmed interdiffusion. Ion polishing technique provided information on porosity and when imaged using backscattered mode, grain structure confirmed mechanical deformation of the bonds. Measurements of the interfacial bond strength are made by wire pull tests and ball shear tests based on existing industry standard tests. However, for the Al-Ge eutectic bonds, no standard strength is available so a test is developed using the stud pull test method using the Dage 4000 Plus to yield consistent results. Adhesion strengths of 30-40 MPa are found for eutectic bonded packages however, as low as 20MPa was measured in low temperature bonded areas.

Miniaturized tool for optogenetics based on an LED and an optical fiber interfaced by a silicon housing.

PubMed

Schwaerzle, M; Elmlinger, P; Paul, O; Ruther, P

2014-01-01

This paper reports on the design, simulation, fabrication and characterization of a tool for optogenetic experiments based on a light emitting diode (LED). A minimized silicon (Si) interface houses the LED and aligns it to an optical fiber. With a Si housing size of 550×500×380 μm(3) and an electrical interconnection of the LED by a highly flexible polyimide (PI) ribbon cable is the system very variable. PI cables and Si housings are fabricated using established microsystem technologies. A 270×220×50 μm(3) bare LED chip is flip-chip-bonded onto the PI cable. The Si housing is adhesively attached to the PI cable, thereby hosting the LED in a recess. An opposite recess guides the optical fiber with a diameter of 125 μm. An aperture in-between restricts the emitted LED light to the fiber core. The optical fiber is adhesively fixed into the Si housing recess. An optical output intensity at the fiber end facet of 1.71 mW/mm(2) was achieved at a duty cycle of 10 % and a driving current of 30 mA.

Thin-Film Quantum Dot Photodiode for Monolithic Infrared Image Sensors.

PubMed

Malinowski, Pawel E; Georgitzikis, Epimitheas; Maes, Jorick; Vamvaka, Ioanna; Frazzica, Fortunato; Van Olmen, Jan; De Moor, Piet; Heremans, Paul; Hens, Zeger; Cheyns, David

2017-12-10

Imaging in the infrared wavelength range has been fundamental in scientific, military and surveillance applications. Currently, it is a crucial enabler of new industries such as autonomous mobility (for obstacle detection), augmented reality (for eye tracking) and biometrics. Ubiquitous deployment of infrared cameras (on a scale similar to visible cameras) is however prevented by high manufacturing cost and low resolution related to the need of using image sensors based on flip-chip hybridization. One way to enable monolithic integration is by replacing expensive, small-scale III-V-based detector chips with narrow bandgap thin-films compatible with 8- and 12-inch full-wafer processing. This work describes a CMOS-compatible pixel stack based on lead sulfide quantum dots (PbS QD) with tunable absorption peak. Photodiode with a 150-nm thick absorber in an inverted architecture shows dark current of 10 -6 A/cm² at -2 V reverse bias and EQE above 20% at 1440 nm wavelength. Optical modeling for top illumination architecture can improve the contact transparency to 70%. Additional cooling (193 K) can improve the sensitivity to 60 dB. This stack can be integrated on a CMOS ROIC, enabling order-of-magnitude cost reduction for infrared sensors.

Apparatus and Method for Packaging and Integrating Microphotonic Devices

NASA Technical Reports Server (NTRS)

Nguyen, Hung (Inventor)

2008-01-01

An apparatus is disclosed that includes a carrier structure and an optical coupling arrangement. The carrier structure is made of a silicon material and allows for the packaging and integrating of microphotonic devices onto a single chip. The optical coupling mechanism enables laser light to be coupled into and out of a microphotonic resonant disk integrated on the carrier. The carrier provides first, second and third cavities that are dimensioned so as to accommodate the insertion and snug fitting of the microphotonic resonant disk and first and second prisms that are implemented by the optical coupling arrangement to accommodate the laser coupling.

Design automation for complex CMOS/SOS LSI hybrid substrates

NASA Technical Reports Server (NTRS)

Ramondetta, P. W.; Smiley, J. W.

1976-01-01

A design automated approach used to develop thick-film hybrid packages is described. The hybrid packages produced combine thick-film and silicon on sapphire (SOS) laser surface interaction technologies to bring the on-chip performance level of SOS to the subsystem level. Packing densities are improved by a factor of eight over ceramic dual in-line packing; interchip wiring capacitance is low. Due to significant time savings, the design automated approach presented can be expected to yield a 3:1 reduction in cost over the use of manual methods for the initial design of a hybrid.

Fabricating a Microcomputer on a Single Silicon Wafer

NASA Technical Reports Server (NTRS)

Evanchuk, V. L.

1983-01-01

Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

Study on the mechanism of color coordinate shift of LED package

NASA Astrophysics Data System (ADS)

Zhuang, Yunyi; Wang, Yong; Yang, Bobo; Li, Zhanguo; Yang, Lei; Zou, Jun

2017-07-01

In the paper, the influences of the chip, silicone and phosphors on the color coordinate shift of LED were studied. In the process of LED baking, it was found that the effect of the chip and silicone on the color coordinate drift is less than 3% through the analysis of each influencing factor. But the influence of the phosphors is large and accounted for 11.11% of the overall impact factors. Therefore, it is important to select the better green phosphors in thermal stability for the LED package and it has a guiding significance to the color coordinate of LED distribution. Project supported by the National Natural Science Foundation of China (No. 11474036), the Natural Science Foundation of Shanghai (No. 12ZR1430900), the Shanghai Institute of Technology Talents Scheme (No. YJ2014-04), the Shanghai Municipal Alliance Program (Nos. Lm201514, Lm201505, Lm201455), the Science and Technology Commission of Shanghai Municipality (CN) (No. 14500503300), the Shanghai Cooperative Project (No. ShanghaiCXY-2013-61), and the Jiashan County Technology Program (No. 20141316).

Ultra Small Integrated Optical Fiber Sensing System

PubMed Central

Van Hoe, Bram; Lee, Graham; Bosman, Erwin; Missinne, Jeroen; Kalathimekkad, Sandeep; Maskery, Oliver; Webb, David J.; Sugden, Kate; Van Daele, Peter; Van Steenberge, Geert

2012-01-01

This paper introduces a revolutionary way to interrogate optical fiber sensors based on fiber Bragg gratings (FBGs) and to integrate the necessary driving optoelectronic components with the sensor elements. Low-cost optoelectronic chips are used to interrogate the optical fibers, creating a portable dynamic sensing system as an alternative for the traditionally bulky and expensive fiber sensor interrogation units. The possibility to embed these laser and detector chips is demonstrated resulting in an ultra thin flexible optoelectronic package of only 40 μm, provided with an integrated planar fiber pigtail. The result is a fully embedded flexible sensing system with a thickness of only 1 mm, based on a single Vertical-Cavity Surface-Emitting Laser (VCSEL), fiber sensor and photodetector chip. Temperature, strain and electrodynamic shaking tests have been performed on our system, not limited to static read-out measurements but dynamically reconstructing full spectral information datasets.

Enhanced light output from a nitride-based power chip of green light-emitting diodes with nano-rough surface using nanoimprint lithography.

PubMed

Huang, H W; Lin, C H; Yu, C C; Lee, B D; Chiu, C H; Lai, C F; Kuo, H C; Leung, K M; Lu, T C; Wang, S C

2008-05-07

Enhanced light extraction from a GaN-based power chip (PC) of green light-emitting diodes (LEDs) with a rough p-GaN surface using nanoimprint lithography is presented. At a driving current of 350 mA and with a chip size of 1 mm × 1 mm packaged on transistor outline (TO)-cans, the light output power of the green PC LEDs with nano-rough p-GaN surface is enhanced by 48% when compared with the same device without a rough p-GaN surface. In addition, by examining the radiation patterns, the green PC LED with nano-rough p-GaN surface shows stronger light extraction with a wider view angle. These results offer promising potential to enhance the light output powers of commercial light-emitting devices by using the technique of nanoimprint lithography under suitable nanopattern design.

Two-Volt Josephson Arbitrary Waveform Synthesizer Using Wilkinson Dividers.

PubMed

Flowers-Jacobs, Nathan E; Fox, Anna E; Dresselhaus, Paul D; Schwall, Robert E; Benz, Samuel P

2016-09-01

The root-mean-square (rms) output voltage of the NIST Josephson arbitrary waveform synthesizer (JAWS) has been doubled from 1 V to a record 2 V by combining two new 1 V chips on a cryocooler. This higher voltage will improve calibrations of ac thermal voltage converters and precision voltage measurements that require state-of-the-art quantum accuracy, stability, and signal-to-noise ratio. We achieved this increase in output voltage by using four on-chip Wilkinson dividers and eight inner-outer dc blocks, which enable biasing of eight Josephson junction (JJ) arrays with high-speed inputs from only four high-speed pulse generator channels. This approach halves the number of pulse generator channels required in future JAWS systems. We also implemented on-chip superconducting interconnects between JJ arrays, which reduces systematic errors and enables a new modular chip package. Finally, we demonstrate a new technique for measuring and visualizing the operating current range that reduces the measurement time by almost two orders of magnitude and reveals the relationship between distortion in the output spectrum and output pulse sequence errors.

Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process

NASA Astrophysics Data System (ADS)

Saleem, Amin M.; Andersson, Rickard; Desmaris, Vincent; Enoksson, Peter

2018-01-01

Complete miniaturized on-chip integrated solid-state capacitors have been fabricated based on conformal coating of vertically aligned carbon nanofibers (VACNFs), using a CMOS temperature compatible microfabrication processes. The 5 μm long VACNFs, operating as electrode, are grown on a silicon substrate and conformally coated by aluminum oxide dielectric using atomic layer deposition (ALD) technique. The areal (footprint) capacitance density value of 11-15 nF/mm2 is realized with high reproducibility. The CMOS temperature compatible microfabrication, ultra-low profile (less than 7 μm thickness) and high capacitance density would enables direct integration of micro energy storage devices on the active CMOS chip, multi-chip package and passives on silicon or glass interposer. A model is developed to calculate the surface area of VACNFs and the effective capacitance from the devices. It is thereby shown that 71% of surface area of the VACNFs has contributed to the measured capacitance, and by using the entire area the capacitance can potentially be increased.

Design of a high-efficiency train headlamp with low power consumption using dual half-parabolic aluminized reflectors.

PubMed

Liang, Wei-Lun; Su, Guo-Dung J

2018-02-20

We propose a train headlamp system using dual half-circular parabolic aluminized reflectors. Each half-circular reflector contains five high-efficiency and small-package light-emitting diode (LED) chips, and the halves are 180° rotationally symmetric. For traffic safety, the headlamp satisfies the Code of Federal Regulations. To predict the pattern of illumination, an analytical derivation is developed for the optical path of a ray that is perpendicular to and emitted from the center of an LED chip. This ray represents the main ray emitted from the LED chip and is located at the maximum illuminance of the spot projected by the LED source onto a screen. We then analyze the design systematically to determine the locations of the LED chips in the reflector that minimize electricity consumption while satisfying reliability constraints associated with traffic safety. Compared to a typical train headlamp system with an incandescent or halogen lamp needing several hundred watts, the proposed system only uses 20.18 W to achieve the luminous intensity requirements.

Compact Receiver Front Ends for Submillimeter-Wave Applications

NASA Technical Reports Server (NTRS)

Mehdi, Imran; Chattopadhyay, Goutam; Schlecht, Erich T.; Lin, Robert H.; Sin, Seth; Peralta, Alejandro; Lee, Choonsup; Gill, John J.; Gulkis, Samuel; Thomas, Bertrand C.

2012-01-01

The current generation of submillimeter-wave instruments is relatively mass and power-hungry. The receiver front ends (RFEs) of a submillimeter instrument form the heart of the instrument, and any mass reduction achieved in this subsystem is propagated through the instrument. In the current implementation, the RFE consists of different blocks for the mixer and LO circuits. The motivation for this work is to reduce the mass of the RFE by integrating the mixer and LO circuits in one waveguide block. The mixer and its associated LO chips will all be packaged in a single waveguide package. This will reduce the mass of the RFE and also provide a number of other advantages. By bringing the mixer and LO circuits close together, losses in the waveguide will be reduced. Moreover, the compact nature of the block will allow for better thermal control of the block, which is important in order to reduce gain fluctuations. A single waveguide block with a 600- GHz RFE functionality (based on a subharmonically pumped Schottky diode pair) has been demonstrated. The block is about 3x3x3 cubic centimeters. The block combines the mixer and multiplier chip in a single package. 3D electromagnetic simulations were carried out to design the waveguide circuit around the mixer and multiplier chip. The circuit is optimized to provide maximum output power and maximum bandwidth. An integrated submillimeter front end featuring a 520-600-GHz sub-harmonic mixer and a 260-300-GHz frequency tripler in a single cavity was tested. Both devices used GaAs MMIC membrane planar Schottky diode technology. The sub-harmonic mixer/tripler circuit has been tested using conventional metal-machined blocks. Measurement results on the metal block give best DSB (double sideband) mixer noise temperature of 2,360 K and conversion losses of 7.7 dB at 520 GHz. The LO input power required to pump the integrated tripler/sub-harmonic mixer is between 30 and 50 mW.

Smart and functional polymer materials for smart and functional microfluidic instruments

NASA Astrophysics Data System (ADS)

Gray, Bonnie L.

2014-04-01

As microfluidic systems evolve from "chip-in-the-lab" to true portable lab-on-a-chip (LoC) or lab-in-a-package (LiP) microinstrumentation, there is a need for increasingly miniaturized sensors, actuators, and integration/interconnect technologies with high levels of functionality and self-direction. Furthermore, as microfluidic instruments are increasingly realized in polymer-based rather than glass- or silicon- based platforms, there is a need to realize these highly functional components in materials that are polymer-compatible. Polymers that are altered to possess basic functionality, and even higher-functioning "smart" polymer materials, may help to realize high-functioning and selfdirecting portable microinstrumentation. Stimuli-responsive hydrogels have been recognized for over a decade as beneficial to the development of smart microfluidics systems and instrumentation. In addition, functional materials such as conductive and magnetic composite polymers are being increasingly employed to push microfluidics systems to greater degrees of functionality, portability, and/or flexibility for wearable/implantable systems. Functional and smart polymer materials can be employed to realize electrodes, electronic routing, heaters, mixers, valves, pumps, sensors, and interconnect structures in polymer-based microfluidic systems. Stimuli for such materials can be located on-chip or in a small package, thus greatly increasing the degree of portability and the potential for mechanical flexibility of such systems. This paper will examine the application of functional polymer materials to the development of high-functioning microfluidics instruments with a goal towards self-direction.

The rectenna design on contact lens for wireless powering of the active intraocular pressure monitoring system.

PubMed

Cheng, H W; Jeng, B M; Chen, C Y; Huang, H Y; Chiou, J C; Luo, C H

2013-01-01

This paper proposed a wireless power harvesting system with micro-electro-mechanical-systems (MEMS) fabrication for noninvasive intraocular pressure (IOP) measurement on soft contact lens substructure. The power harvesting IC consists of a loop antenna, an impedance matching network and a rectifier. The proposed IC has been designed and fabricated by CMOS 0.18 um process that operates at the ISM band of 5.8 GHz. The antenna and the power harvesting IC would be bonded together by using flip chip bonding technologies without extra wire interference. The circuit utilized an impedance transformation circuit to boost the input RF signal that improves the circuit performance. The proposed design achieves an RF-to-DC conversion efficiency of 35% at 5.8 GHz.

Three-Dimensional Waveguide Arrays for Coupling Between Fiber-Optic Connectors and Surface-Mounted Optoelectronic Devices

NASA Astrophysics Data System (ADS)

Hiramatsu, Seiki; Kinoshita, Masao

2005-09-01

This paper describes the fabrication of novel surface-mountable waveguide connectors and presents test results for them. To ensure more highly integrated and low-cost fabrication, we propose new three-dimensional (3-D) waveguide arrays that feature two-dimensionally integrated optical inputs/outputs and optical path redirection. A wafer-level stack and lamination process was used to fabricate the waveguide arrays. Vertical-cavity surface-emitting lasers (VCSELs) and photodiodes were directly mounted on the arrays and combined with mechanical transferable ferrule using active alignment. With the help of a flip-chip bonder, the waveguide connectors were mounted on a printed circuit board by solder bumps. Using mechanical transferable connectors, which can easily plug into the waveguide connectors, we obtained multi-gigabits-per-second transmission performance.

Method of fabricating a PbS-PbSe IR detector array

NASA Technical Reports Server (NTRS)

Barrett, John R. (Inventor)

1987-01-01

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chiping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

Creation of a Radiation Hard 0.13 Micron CMOS Library at IHP

NASA Astrophysics Data System (ADS)

Jagdhold, U.

2010-08-01

To support space applications we will develop an 0.13 micron CMOS library which should be radiation hard up to 200 krad. By introducing new radiation hard design rules we will minimize IC-level leakage and single event latchup (SEL). To reduce single event upset (SEU) we will add two p-MOS transistors to all flip flops. For reliability reasons we will use double contacts in all library elements. The additional rules and the library elements will then be integrated in our Cadence mixed signal designkit, Virtuoso IC6.1 [1]. A test chip will be produced with our in house 0.13 micron BiCMOS technology, see Ref. [2].Thereafter we will doing radiation tests according the ESA specifications, see Ref. [3], [4].

Reliability of Sn/Pb and Lead-Free (SnAgCu) Solders of Surface Mounted Miniaturized Passive Components for Extreme Temperature (-185 C to +125 C) Space Missions

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni

2011-01-01

Surface mount electronic package test boards have been assembled using tin/lead (Sn/Pb) and lead-free (Pb-free or SnAgCu or SAC305) solders. The soldered surface mount packages include ball grid arrays (BGA), flat packs, various sizes of passive chip components, etc. They have been optically inspected after assembly and subsequently subjected to extreme temperature thermal cycling to assess their reliability or future deep space, long-term, extreme temperature environmental missions. In this study, the employed temperature range (-185oC to +125oC) covers military specifications (-55oC to +100oC), extreme old Martian (-120oC to +115oC), asteroid Nereus (-180oC to +25oC) and JUNO (-150oC to +120oC) environments. The boards were inspected at room temperature and at various intervals as a function of extreme temperature thermal cycling and bake duration. Electrical resistance measurements made at room temperature are reported and the tests to date have shown some change in resistance as a function of extreme temperature thermal cycling and some showed increase in resistance. However, the change in interconnect resistance becomes more noticeable with increasing number of thermal cycles. Further research work will be carried out to understand the reliability of packages under extreme temperature applications (-185oC to +125oC) via continuously monitoring the daisy chain resistance for BGA, Flat-packs, lead less chip packages, etc. This paper will describe the experimental reliability results of miniaturized passive components (01005, 0201, 0402, 0603, 0805, and 1206) assembled using surface mounting processes with tin-lead and lead-free solder alloys under extreme temperature environments.

Reliability of Sn/Pb and lead-free (SnAgCu) solders of surface mounted miniaturized passive components for extreme temperature (-185°C to +125°C) space missions

NASA Astrophysics Data System (ADS)

Ramesham, Rajeshuni

2011-02-01

Surface mount electronic package test boards have been assembled using tin/lead (Sn/Pb) and lead-free (Pb-free or SnAgCu or SAC305) solders. The soldered surface mount packages include ball grid arrays (BGA), flat packs, various sizes of passive chip components, etc. They have been optically inspected after assembly and subsequently subjected to extreme temperature thermal cycling to assess their reliability for future deep space, long-term, extreme temperature environmental missions. In this study, the employed temperature range (-185°C to +125°C) covers military specifications (-55°C to +100°C), extreme cold Martian (-120°C to +115°C), asteroid Nereus (-180°C to +25°C) and JUNO (-150°C to +120°C) environments. The boards were inspected at room temperature and at various intervals as a function of extreme temperature thermal cycling and bake duration. Electrical resistance measurements made at room temperature are reported and the tests to date have shown some change in resistance as a function of extreme temperature thermal cycling and some showed increase in resistance. However, the change in interconnect resistance becomes more noticeable with increasing number of thermal cycles. Further research work will be carried out to understand the reliability of packages under extreme temperature applications (-185°C to +125°C) via continuously monitoring the daisy chain resistance for BGA, Flat-packs, lead less chip packages, etc. This paper will describe the experimental reliability results of miniaturized passive components (01005, 0201, 0402, 0603, 0805, and 1206) assembled using surface mounting processes with tin-lead and lead-free solder alloys under extreme temperature environments.

Reliability and Characteristics of Wafer-Level Chip-Scale Packages under Current Stress

NASA Astrophysics Data System (ADS)

Chen, Po-Ying; Kung, Heng-Yu; Lai, Yi-Shao; Hsiung Tsai, Ming; Yeh, Wen-Kuan

2008-02-01

In this work, we present a novel approach and method for elucidating the characteristics of wafer-level chip-scale packages (WLCSPs) for electromigration (EM) tests. The die in WLCSP was directly attached to the substrate via a soldered interconnect. The shrinking of the area of the die that is available for power, and the solder bump also shrinks the volume and increases the density of electrons for interconnect efficiency. The bump current density now approaches to 106 A/cm2, at which point the EM becomes a significant reliability issue. As known, the EM failure depends on numerous factors, including the working temperature and the under bump metallization (UBM) thickness. A new interconnection geometry is adopted extensively with moderate success in overcoming larger mismatches between the displacements of components during current and temperature changes. Both environments and testing parameters for WLCSP are increasingly demanded. Although failure mechanisms are considered to have been eliminated or at least made manageable, new package technologies are again challenging its process, integrity and reliability. WLCSP technology was developed to eliminate the need for encapsulation to ensure compatibility with smart-mount technology (SMT). The package has good handing properties but is now facing serious reliability problems. In this work, we investigated the reliability of a WLCSP subjected to different accelerated current stressing conditions at a fixed ambient temperature of 125 °C. A very strong correlation exists between the mean time to failure (MTTF) of the WLCSP test vehicle and the mean current density that is carried by a solder joint. A series of current densities were applied to the WLCSP architecture; Black's power law was employed in a failure mode simulation. Additionally, scanning electron microscopy (SEM) was adopted to determine the differences existing between high- and low-current-density failure modes.

Full Flip, Half Flip and No Flip: Evaluation of Flipping an Introductory Programming Course

ERIC Educational Resources Information Center

Fryling, Meg; Yoder, Robert; Breimer, Eric

2016-01-01

While some research has suggested that video lectures are just as effective as in-person lectures to convey basic information to students, not everyone agrees that the flipped classroom model is an effective way of educating students. This research explores traditional, semi-flipped and fully-flipped classroom models by comparing three sections of…

Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

NASA Astrophysics Data System (ADS)

Yamamoto, Shuu'ichirou; Shuto, Yusuke; Sugahara, Satoshi

2013-07-01

We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks. Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

VLSI research

NASA Astrophysics Data System (ADS)

Brodersen, R. W.

1984-04-01

A scaled version of the RISC II chip has been fabricated and tested and these new chips have a cycle time that would outperform a VAX 11/780 by about a factor of two on compiled integer C programs. The architectural work on a RISC chip designed for a Smalltalk implementation has been completed. This chip, called SOAR (Smalltalk On a RISC), should run program s4-15 times faster than the Xerox 1100 (Dolphin), a TTL minicomputer, and about as fast as the Xerox 1132 (Dorado), a $100,000 ECL minicomputer. The 1983 VLSI tools tape has been converted for use under the latest UNIX release (4.2). The Magic (formerly called Caddy) layout system will be a unified set of highly automated tools that cover all aspects of the layout process, including stretching, compaction, tiling and routing. A multiple window package and design rule checker for this system have just been completed and compaction and stretching are partially implemented. New slope-based timing models for the Crystal timing analyzer are now fully implemented and in regular use. In an accuracy test using a dozen critical paths from the RISC II processor and cache chips it was found that Crystal's estimates were within 5-10% of SPICE's estimates, while being a factor of 10,000 times faster.

Reliability assessment of Multichip Module technologies via the Triservice/NASA RELTECH program

NASA Astrophysics Data System (ADS)

Fayette, Daniel F.

1994-10-01

Multichip Module (MCM) packaging/interconnect technologies have seen increased emphasis from both the commercial and military communities as a means of increasing capability and performance while providing a vehicle for reducing cost, power and weight of the end item electronic application. This is accomplished through three basic Multichip module technologies, MCM-L that are laminates, MCM-C that are ceramic type substrates and MCM-D that are deposited substrates (e.g., polymer dielectric with thin film metals). Three types of interconnect structures are also used with these substrates and include, wire bond, Tape Automated Bonds (TAB) and flip chip ball bonds. Application, cost, producibility and reliability are the drivers that will determine which MCM technology will best fit a respective need or requirement. With all the benefits and technologies cited, it would be expected that the use of, or the planned use of, MCM's would be more extensive in both military and commercial applications. However, two significant roadblocks exist to implementation of these new technologies: the absence of reliability data and a single national standard for the procurement of reliable/quality MCM's. To address the preceding issues, the Reliability Technology to Achieve Insertion of Advanced Packaging (RELTECH) program has been established. This program, which began in May 1992, has endeavored to evaluate a cross section of MCM technologies covering all classes of MCM's previously cited. NASA and the Tri-Services (Air Force Rome Laboratory, Naval Surface Warfare Center, Crane IN and Army Research Laboratory) have teamed together with sponsorship from ARPA to evaluate the performance, reliability and producibility of MCM's for both military and commercial usage. This is done in close cooperation with our industry partners whose support is critical to the goals of the program. Several tasks are being performed by the RELTECH program and data from this effort, in conjunction with information from our industry partners as well as discussions with industry organizations (IPC, EIA, ISHM, etc.) are being used to develop the qualification and screening requirements for MCM's. Specific tasks being performed by the RELTECH program include technical assessments, product evaluations, reliability modeling, environmental testing, and failure analysis. This paper will describe the various tasks associated with the RELTECH program, status, progress and a description of the national dual use specification being developed for MCM technologies.

Design, Fabrication, and Characterization of a Microelectromechanical Directional Microphone

DTIC Science & Technology

2011-06-01

7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) 8. PERFORMING ORGANIZATION REPORT NUMBER 9. SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES...Figure 5.2 SOIC packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 5.3 Laboratory setup...Mean Squared SOC System-On-Chip SOIC Small Outline Integrated Circuit SOIMUMPS Silicon-On-Insulator Multi-User MEMS Process SPL Sound Pressure Level

Phosphor chessboard packaging for white LEDs in high efficiency and high color performance

NASA Astrophysics Data System (ADS)

Nguyen, Quang-Khoi; Chang, Yu-Yu; Lu, Chun-Yan; Yang, Tsung-Hsun; Chung, Te-Yuan; Sun, Ching-Cherng

2016-09-01

We performed the simulation of white LEDs packaging with different chessboard structures of white light converting phosphor layer covered on GaN die chip. Three different types of chessboard structures are called type 1, type 2 and type 3, respectively. The result of investigation according to the phosphor thickness show the increasing of thickness of phosphor layer are, the decreasing of output blue light power are. Meanwhile, the changes of yellow light are neglect. Type 3 shows highest packaging efficiency of 74.3 % compares with packaging efficiency of type 2 and type 1 (72.5 % and 71.3 %, respectively). Type 3 also shows the most effect of forward light. Attention that the type 3 chessboard structure gets packaging efficiency of 74.3 % at color temperature of daylight as well as high saving of phosphor amount. The color temperatures of three types of chessboard structure are higher than 5000 K, so they are suitable for lighting purpose. The angular correlate color temperature deviation (ACCTD) of type 1, type 2 and type 3 are 6500K, 11500K and 17000K, respectively.

Reliability of high I/O high density CCGA interconnect electronic packages under extreme thermal environments

NASA Astrophysics Data System (ADS)

Ramesham, Rajeshuni

2012-03-01

Ceramic column grid array (CCGA) packages have been increasing in use based on their advantages such as high interconnect density, very good thermal and electrical performances, compatibility with standard surfacemount packaging assembly processes, and so on. CCGA packages are used in space applications such as in logic and microprocessor functions, telecommunications, payload electronics, and flight avionics. As these packages tend to have less solder joint strain relief than leaded packages or more strain relief over lead-less chip carrier packages, the reliability of CCGA packages is very important for short-term and long-term deep space missions. We have employed high density CCGA 1152 and 1272 daisy chained electronic packages in this preliminary reliability study. Each package is divided into several daisy-chained sections. The physical dimensions of CCGA1152 package is 35 mm x 35 mm with a 34 x 34 array of columns with a 1 mm pitch. The dimension of the CCGA1272 package is 37.5 mm x 37.5 mm with a 36 x 36 array with a 1 mm pitch. The columns are made up of 80% Pb/20%Sn material. CCGA interconnect electronic package printed wiring polyimide boards have been assembled and inspected using non-destructive x-ray imaging techniques. The assembled CCGA boards were subjected to extreme temperature thermal atmospheric cycling to assess their reliability for future deep space missions. The resistance of daisy-chained interconnect sections were monitored continuously during thermal cycling. This paper provides the experimental test results of advanced CCGA packages tested in extreme temperature thermal environments. Standard optical inspection and x-ray non-destructive inspection tools were used to assess the reliability of high density CCGA packages for deep space extreme temperature missions.

Polymer dispensing and embossing technology for the lens type LED packaging

NASA Astrophysics Data System (ADS)

Chien, Chien-Lin Chang; Huang, Yu-Che; Hu, Syue-Fong; Chang, Chung-Min; Yip, Ming-Chuen; Fang, Weileun

2013-06-01

This study presents a ring-type micro-structure design on the substrate and its corresponding micro fabrication processes for a lens-type light-emitting diode (LED) package. The dome-type or crater-type silicone lenses are achieved by a dispensing and embossing process rather than a molding process. Silicone with a high viscosity and thixotropy index is used as the encapsulant material. The ring-type micro structure is adopted to confine the dispensed silicone encapsulant so as to form the packaged lens. With the architecture and process described, this LED package technology herein has three merits: (1) the flexibility of lens-type LED package designs is enhanced; (2) a dome-type package design is used to enhance the intensity; (3) a crater-type package design is used to enhance the view angle. Measurement results show the ratio between the lens height and lens radius can vary from 0.4 to 1 by changing the volume of dispensed silicone. The view angles of dome-type and crater-type packages can reach 155° ± 5° and 175° ± 5°, respectively. As compared with the commercial plastic leaded chip carrier-type package, the luminous flux of a monochromatic blue light LED is improved by 15% by the dome-type package (improved by 7% by the crater-type package) and the luminous flux of a white light LED is improved by 25% by the dome-type package (improved by 13% by the crater-type package). The luminous flux of monochromatic blue light LED and white light LED are respectively improved by 8% and 12% by the dome-type package as compare with the crater-type package.

The silicon-glass microreactor with embedded sensors—technology and results of preliminary qualitative tests, toward intelligent microreaction plant

NASA Astrophysics Data System (ADS)

Knapkiewicz, P.

2013-03-01

The technology and preliminary qualitative tests of silicon-glass microreactors with embedded pressure and temperature sensors are presented. The concept of microreactors for leading highly exothermic reactions, e.g. nitration of hydrocarbons, and design process-included computer-aided simulations are described in detail. The silicon-glass microreactor chip consisting of two micromixers (multistream micromixer), reaction channels, cooling/heating chambers has been proposed. The microreactor chip was equipped with a set of pressure and temperature sensors and packaged. Tests of mixing quality, pressure drops in channels, heat exchange efficiency and dynamic behavior of pressure and temperature sensors were documented. Finally, two applications were described.

On-chip photonic particle sensor

NASA Astrophysics Data System (ADS)

Singh, Robin; Ma, Danhao; Agarwal, Anu; Anthony, Brian

2018-02-01

We propose an on-chip photonic particle sensor design that can perform particle sizing and counting for various environmental applications. The sensor is based on micro photonic ring resonators that are able to detect the presence of the free space particles through the interaction with their evanescent electric field tail. The sensor can characterize a wide range of the particle size ranging from a few nano meters to micron ( 1 micron). The photonic platform offers high sensitivity, compactness, fast response of the device. Further, FDTD simulations are performed to analyze different particle-light interactions. Such a compact and portable platform, packaged with integrated photonic circuit provides a useful sensing modality in space shuttle and environmental applications.

Improvement of modulation bandwidth in electroabsorption-modulated laser by utilizing the resonance property in bonding wire.

PubMed

Kwon, Oh Kee; Han, Young Tak; Baek, Yong Soon; Chung, Yun C

2012-05-21

We present and demonstrate a simple and cost-effective technique for improving the modulation bandwidth of electroabsorption-modulated laser (EML). This technique utilizes the RF resonance caused by the EML chip (i.e., junction capacitance) and bonding wire (i.e, wire inductance). We analyze the effects of the lengths of the bonding wires on the frequency responses of EML by using an equivalent circuit model. To verify this analysis, we package a lumped EML chip on the sub-mount and measure its frequency responses. The results show that, by using the proposed technique, we can increase the modulation bandwidth of EML from ~16 GHz to ~28 GHz.

Thermal conductivity on stud bump interconnection of high power COB LED

NASA Astrophysics Data System (ADS)

Sarukunaselan, K.; Ong, N. R.; Sauli, Z.; Mahmed, N.; Kirtsaeng, S.; Sakuntasathien, S.; Suppiah, S.; Alcain, J. B.; Retnasamy, V.

2017-09-01

In this paper, the impacts of bump dimensions and material conductivity on the thermal performances of a high power chip on board (COB) LED package were investigated using open source software, Elmer. The stud bump acted as interconnection join which has an extra role in dissipating heat generated by the chip to the ambience. Simulation data showed that for a bump with a fixed contact length of 1mm, the most suitable height was 171 µm with material conductivity of 238W/mK or 319W/mK. Materials with thermal conductivity of lower than 20W/mK, had the poorest heat dissipation irrespective of the height.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

PubMed

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-11-04

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications †

PubMed Central

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-01-01

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. PMID:27827904

Development of a MEMS acoustic emission sensor system

NASA Astrophysics Data System (ADS)

Greve, David W.; Oppenheim, Irving J.; Wu, Wei; Wright, Amelia P.

2007-04-01

An improved multi-channel MEMS chip for acoustic emission sensing has been designed and fabricated in 2006 to create a device that is smaller in size, superior in sensitivity, and more practical to manufacture than earlier designs. The device, fabricated in the MUMPS process, contains four resonant-type capacitive transducers in the frequency range between 100 kHz and 500 kHz on a chip with an area smaller than 2.5 sq. mm. The completed device, with its circuit board, electronics, housing, and connectors, possesses a square footprint measuring 25 mm x 25 mm. The small footprint is an important attribute for an acoustic emission sensor, because multiple sensors must typically be arrayed around a crack location. Superior sensitivity was achieved by a combination of four factors: the reduction of squeeze film damping, a resonant frequency approximating a rigid body mode rather than a bending mode, a ceramic package providing direct acoustic coupling to the structural medium, and high-gain amplifiers implemented on a small circuit board. Manufacture of the system is more practical because of higher yield (lower unit costs) in the MUMPS fabrication task and because of a printed circuit board matching the pin array of the MEMS chip ceramic package for easy assembly and compactness. The transducers on the MEMS chip incorporate two major mechanical improvements, one involving squeeze film damping and one involving the separation of resonance modes. For equal proportions of hole area to plate area, a triangular layout of etch holes reduces squeeze film damping as compared to the conventional square layout. The effect is modeled analytically, and is verified experimentally by characterization experiments on the new transducers. Structurally, the transducers are plates with spring supports; a rigid plate would be the most sensitive transducer, and bending decreases the sensitivity. In this chip, the structure was designed for an order-of-magnitude separation between the first and the second mode frequency, strongly approximating the desirable rigid plate limit. The effect is modeled analytically and is verified experimentally by measurement of the resonance frequencies in the new transducers. Another improvement arises from the use of a pin grid array ceramic package, in which the MEMS chip is acoustically coupled to the structure with only two interfaces, through a ceramic medium that is negligible in thickness when compared to wavelengths of interest. Like other acoustic emission sensors, those on the 2006 MEMS chip are sensitive only to displacements normal to the surface on which the device is mounted. To overcome that long-standing limitation, a new MEMS sensor sensitive to in-plane motion has been designed, featuring a different spring-mass mechanism and creating the signal by the change in capacitance between stationary and moving fingers. Predicted damping is much lower for the case of the in-plane sensor, and squeeze-film damping is used selectively to isolate the desired in-plane mechanical response from any unwanted out-of-plane response. The new spring-mass mechanism satisfies the design rules for the PolyMUMPS fabrication (foundry) process. A 3-D MEMS sensor system is presently being fabricated, collocating two in-plane sensors and one out-of-plane sensor at the mm scale, which is very short compared to the acoustic wavelength of interest for stress waves created by acoustic emission events.

missMethyl: an R package for analyzing data from Illumina's HumanMethylation450 platform.

PubMed

Phipson, Belinda; Maksimovic, Jovana; Oshlack, Alicia

2016-01-15

DNA methylation is one of the most commonly studied epigenetic modifications due to its role in both disease and development. The Illumina HumanMethylation450 BeadChip is a cost-effective way to profile >450 000 CpGs across the human genome, making it a popular platform for profiling DNA methylation. Here we introduce missMethyl, an R package with a suite of tools for performing normalization, removal of unwanted variation in differential methylation analysis, differential variability testing and gene set analysis for the 450K array. missMethyl is an R package available from the Bioconductor project at www.bioconductor.org. alicia.oshlack@mcri.edu.au Supplementary data are available at Bioinformatics online. © The Author 2015. Published by Oxford University Press. All rights reserved. For Permissions, please e-mail: journals.permissions@oup.com.

Low-cost and miniaturized 100-Gb/s (2 × 50 Gb/s) PAM-4 TO-packaged ROSA for data center networks.

PubMed

Kang, Sae-Kyoung; Huh, Joon Young; Lee, Jie Hyun; Lee, Joon Ki

2018-03-05

We design and implement a cost-effective and compact 100-Gb/s (2 × 50 Gb/s) PAM-4 receiver optical sub-assembly (ROSA) by using a TO-can package instead of an expensive box-type package. It consists of an optical demultiplexer, two PIN-PDs and a 2-channel linear transimpedance amplifier. The components are passively aligned and assembled using alignment marks engraved on each part. With a real-time PAM-4 DSP chip, we measured the back-to-back receiver sensitivities of the 100-Gb/s ROSA based on TO-56 to be less than -13.2 dBm for both channels at a bit error rate of 2.4e-4. The crosstalk penalty due to the adjacent channel interference was observed around 0.1 dB.

The effects of additives to SnAgCu alloys on microstructure and drop impact reliability of solder joints

NASA Astrophysics Data System (ADS)

Liu, Weiping; Lee, Ning-Cheng

2007-07-01

The impact reliability of solder joints in electronic packages is critical to the lifetime of electronic products, especially those portable devices using area array packages such as ball-grid array (BGA) and chip-scale packages (CSP). Currently, SnAgCu (SAC) solders are most widely used for lead-free applications. However, BGA and CSP solder joints using SAC alloys are fragile and prone to premature interfacial failure, especially under shock loading. To further enhance impact reliability, a family of SAC alloys doped with a small amount of additives such as Mn, Ce, Ti, Bi, and Y was developed. The effects of doping elements on drop test performance, creep resistance, and microstructure of the solder joints were investigated, and the solder joints made with the modified alloys exhibited significantly higher impact reliability.

Reliability of Semiconductor Laser Packaging in Space Applications

NASA Technical Reports Server (NTRS)

Gontijo, Ivair; Qiu, Yueming; Shapiro, Andrew A.

2008-01-01

A typical set up used to perform lifetime tests of packaged, fiber pigtailed semiconductor lasers is described, as well as tests performed on a set of four pump lasers. It was found that two lasers failed after 3200, and 6100 hours under device specified bias conditions at elevated temperatures. Failure analysis of the lasers indicates imperfections and carbon contamination of the laser metallization, possibly from improperly cleaned photo resist. SEM imaging of the front facet of one of the lasers, although of poor quality due to the optical fiber charging effects, shows evidence of catastrophic damage at the facet. More stringent manufacturing controls with 100% visual inspection of laser chips are needed to prevent imperfect lasers from proceeding to packaging and ending up in space applications, where failure can result in the loss of a space flight mission.

Microarray Я US: a user-friendly graphical interface to Bioconductor tools that enables accurate microarray data analysis and expedites comprehensive functional analysis of microarray results.

PubMed

Dai, Yilin; Guo, Ling; Li, Meng; Chen, Yi-Bu

2012-06-08

Microarray data analysis presents a significant challenge to researchers who are unable to use the powerful Bioconductor and its numerous tools due to their lack of knowledge of R language. Among the few existing software programs that offer a graphic user interface to Bioconductor packages, none have implemented a comprehensive strategy to address the accuracy and reliability issue of microarray data analysis due to the well known probe design problems associated with many widely used microarray chips. There is also a lack of tools that would expedite the functional analysis of microarray results. We present Microarray Я US, an R-based graphical user interface that implements over a dozen popular Bioconductor packages to offer researchers a streamlined workflow for routine differential microarray expression data analysis without the need to learn R language. In order to enable a more accurate analysis and interpretation of microarray data, we incorporated the latest custom probe re-definition and re-annotation for Affymetrix and Illumina chips. A versatile microarray results output utility tool was also implemented for easy and fast generation of input files for over 20 of the most widely used functional analysis software programs. Coupled with a well-designed user interface, Microarray Я US leverages cutting edge Bioconductor packages for researchers with no knowledge in R language. It also enables a more reliable and accurate microarray data analysis and expedites downstream functional analysis of microarray results.

Nanotechnology for Food Packaging and Food Quality Assessment.

PubMed

Rossi, Marco; Passeri, Daniele; Sinibaldi, Alberto; Angjellari, Mariglen; Tamburri, Emanuela; Sorbo, Angela; Carata, Elisabetta; Dini, Luciana

Nanotechnology has paved the way to innovative food packaging materials and analytical methods to provide the consumers with healthier food and to reduce the ecological footprint of the whole food chain. Combining antimicrobial and antifouling properties, thermal and mechanical protection, oxygen and moisture barrier, as well as to verify the actual quality of food, e.g., sensors to detect spoilage, bacterial growth, and to monitor incorrect storage conditions, or anticounterfeiting devices in food packages may extend the products shelf life and ensure higher quality of foods. Also the ecological footprint of food chain can be reduced by developing new completely recyclable and/or biodegradable packages from natural and eco-friendly resources. The contribution of nanotechnologies to these goals is reviewed in this chapter, together with a description of portable devices ("lab-on-chip," sensors, nanobalances, etc.) which can be used to assess the quality of food and an overview of regulations in force on food contact materials. © 2017 Elsevier Inc. All rights reserved.

Examination of shipping package 9975-04985

DOE Office of Scientific and Technical Information (OSTI.GOV)

Daugherty, W. L.

Package 9975-04985 was examined following the identification of several unexpected conditions during surveillance activities. A heavy layer of corrosion product on the shield and the shield outer diameter being larger that allowed by drawing tolerances contributed to a very tight fit between the upper fiberboard assembly and shield. The average corrosion rate for the shield is estimated to be 0.0018 inch/year or less, which falls within the bounding rate of 0.002 inch/year that has been previously recommended for these packages. Several apparent foreign objects were noted within the package. One object observed on the air shield was identified as tape.more » The other objects were comprised of mostly fine fibers from the cane fiberboard. It is postulated that the upper and lower fiberboard assemblies were able to rub against each other due to the upper fiberboard assembly being held tight to the shield, and a few stray cane chips became frayed under vibratory motions.« less

Pre-release plastic packaging of MEMS and IMEMS devices

DOEpatents

Peterson, Kenneth A.; Conley, William R.

2002-01-01

A method is disclosed for pre-release plastic packaging of MEMS and IMEMS devices. The method can include encapsulating the MEMS device in a transfer molded plastic package. Next, a perforation can be made in the package to provide access to the MEMS elements. The non-ablative material removal process can include wet etching, dry etching, mechanical machining, water jet cutting, and ultrasonic machining, or any combination thereof. Finally, the MEMS elements can be released by using either a wet etching or dry plasma etching process. The MEMS elements can be protected with a parylene protective coating. After releasing the MEMS elements, an anti-stiction coating can be applied. The perforating step can be applied to both sides of the device or package. A cover lid can be attached to the face of the package after releasing any MEMS elements. The cover lid can include a window for providing optical access. The method can be applied to any plastic packaged microelectronic device that requires access to the environment, including chemical, pressure, or temperature-sensitive microsensors; CCD chips, photocells, laser diodes, VCSEL's, and UV-EPROMS. The present method places the high-risk packaging steps ahead of the release of the fragile portions of the device. It also provides protection for the die in shipment between the molding house and the house that will release the MEMS elements and subsequently treat the surfaces.

Lab-on-a-Chip Pathogen Sensors for Food Safety

PubMed Central

Yoon, Jeong-Yeol; Kim, Bumsang

2012-01-01

There have been a number of cases of foodborne illness among humans that are caused by pathogens such as Escherichia coli O157:H7, Salmonella typhimurium, etc. The current practices to detect such pathogenic agents are cell culturing, immunoassays, or polymerase chain reactions (PCRs). These methods are essentially laboratory-based methods that are not at all real-time and thus unavailable for early-monitoring of such pathogens. They are also very difficult to implement in the field. Lab-on-a-chip biosensors, however, have a strong potential to be used in the field since they can be miniaturized and automated; they are also potentially fast and very sensitive. These lab-on-a-chip biosensors can detect pathogens in farms, packaging/processing facilities, delivery/distribution systems, and at the consumer level. There are still several issues to be resolved before applying these lab-on-a-chip sensors to field applications, including the pre-treatment of a sample, proper storage of reagents, full integration into a battery-powered system, and demonstration of very high sensitivity, which are addressed in this review article. Several different types of lab-on-a-chip biosensors, including immunoassay- and PCR-based, have been developed and tested for detecting foodborne pathogens. Their assay performance, including detection limit and assay time, are also summarized. Finally, the use of optical fibers or optical waveguide is discussed as a means to improve the portability and sensitivity of lab-on-a-chip pathogen sensors. PMID:23112625

Fabrication of Silicon Backshorts with Improved Out-of-Band Rejection for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

Increased effective reflection and transmission at the GaN-sapphire interface of LEDs grown on patterned sapphire substrates

NASA Astrophysics Data System (ADS)

Dongxue, Wu; Ping, Ma; Boting, Liu; Shuo, Zhang; Junxi, Wang; Jinmin, Li

2016-10-01

The effect of patterned sapphire substrate (PSS) on the top-surface (P-GaN-surface) and the bottom-surface (sapphire-surface) of the light output power (LOP) of GaN-based LEDs was investigated, in order to study the changes in reflection and transmission of the GaN-sapphire interface. Experimental research and computer simulations were combined to reveal a great enhancement in LOP from either the top or bottom surface of GaN-based LEDs, which are prepared on patterned sapphire substrates (PSS-LEDs). Furthermore, the results were compared to those of the conventional LEDs prepared on the planar sapphire substrates (CSS-LEDs). A detailed theoretical analysis was also presented to further support the explanation for the increase in both the effective reflection and transmission of PSS-GaN interface layers and to explain the causes of increased LOP values. Moreover, the bottom-surface of the PSS-LED chip shows slightly increased light output performance when compared to that of the top-surface. Therefore, the light extraction efficiency (LEE) can be further enhanced by integrating the method of PSS and flip-chip structure design. Project supported by the National High Technology Program of China (No. Y48A040000) and the National High Technology Program of China (No. Y48A040000).

Thin-Film Quantum Dot Photodiode for Monolithic Infrared Image Sensors †

PubMed Central

Georgitzikis, Epimitheas; Vamvaka, Ioanna; Frazzica, Fortunato; Van Olmen, Jan; De Moor, Piet; Heremans, Paul; Hens, Zeger; Cheyns, David

2017-01-01

Imaging in the infrared wavelength range has been fundamental in scientific, military and surveillance applications. Currently, it is a crucial enabler of new industries such as autonomous mobility (for obstacle detection), augmented reality (for eye tracking) and biometrics. Ubiquitous deployment of infrared cameras (on a scale similar to visible cameras) is however prevented by high manufacturing cost and low resolution related to the need of using image sensors based on flip-chip hybridization. One way to enable monolithic integration is by replacing expensive, small-scale III–V-based detector chips with narrow bandgap thin-films compatible with 8- and 12-inch full-wafer processing. This work describes a CMOS-compatible pixel stack based on lead sulfide quantum dots (PbS QD) with tunable absorption peak. Photodiode with a 150-nm thick absorber in an inverted architecture shows dark current of 10−6 A/cm2 at −2 V reverse bias and EQE above 20% at 1440 nm wavelength. Optical modeling for top illumination architecture can improve the contact transparency to 70%. Additional cooling (193 K) can improve the sensitivity to 60 dB. This stack can be integrated on a CMOS ROIC, enabling order-of-magnitude cost reduction for infrared sensors. PMID:29232871

Advanced Interconnect Roadmap for Space Applications

NASA Technical Reports Server (NTRS)

Galbraith, Lissa

1999-01-01

This paper presents the NASA electronic parts and packaging program for space applications. The topics include: 1) Forecasts; 2) Technology Challenges; 3) Research Directions; 4) Research Directions for Chip on Board (COB); 5) Research Directions for HDPs: Multichip Modules (MCMs); 6) Research Directions for Microelectromechanical systems (MEMS); 7) Research Directions for Photonics; and 8) Research Directions for Materials. This paper is presented in viewgraph form.

Thermal management of high heat flux electronic components in space and aircraft systems, phase 1

NASA Astrophysics Data System (ADS)

Iversen, Arthur H.

1991-03-01

The objectives of this Phase 1 program were to analyze, design, construct and demonstrate the application of curved surface cooling to power devices with the goal of demonstrating greater than 200 W/sq cm chip dissipation while maintaining junction temperatures within specification. Major components of the experiment comprised the test fixture for mounting the device under test and the cooling loop equipment and instrumentation. The work conducted in this Phase 1 study was to establish the basic parameters for the design of an entire class of efficient, compact, lightweight and cost competitive power conversion/conditioning systems for space, aircraft and general DOD requirements. This has been accomplished. Chip power dissipation of greater than 400 W/sq cm was demonstrated, and a general packaging and the thermal management design has been devised to meet the above requirements. The power limit reached was dictated by the junction temperature and not power dissipation, i.e., critical heat flux. The key to the packaging design is a basic construction concept that provides low junction to fluid thermal resistance. High heat flux dissipation without low thermal resistance is useless because excessive junction temperatures will results.

A Time-Domain CMOS Oscillator-Based Thermostat with Digital Set-Point Programming

PubMed Central

Chen, Chun-Chi; Lin, Shih-Hao

2013-01-01

This paper presents a time-domain CMOS oscillator-based thermostat with digital set-point programming [without a digital-to-analog converter (DAC) or external resistor] to achieve on-chip thermal management of modern VLSI systems. A time-domain delay-line-based thermostat with multiplexers (MUXs) was used to substantially reduce the power consumption and chip size, and can benefit from the performance enhancement due to the scaling down of fabrication processes. For further cost reduction and accuracy enhancement, this paper proposes a thermostat using two oscillators that are suitable for time-domain curvature compensation instead of longer linear delay lines. The final time comparison was achieved using a time comparator with a built-in custom hysteresis to generate the corresponding temperature alarm and control. The chip size of the circuit was reduced to 0.12 mm2 in a 0.35-μm TSMC CMOS process. The thermostat operates from 0 to 90 °C, and achieved a fine resolution better than 0.05 °C and an improved inaccuracy of ± 0.6 °C after two-point calibration for eight packaged chips. The power consumption was 30 μW at a sample rate of 10 samples/s. PMID:23385403

Mechanical design optimization of a single-axis MOEMS accelerometer based on a grating interferometry cavity for ultrahigh sensitivity

NASA Astrophysics Data System (ADS)

Lu, Qianbo; Bai, Jian; Wang, Kaiwei; Lou, Shuqi; Jiao, Xufen; Han, Dandan; Yang, Guoguang

2016-08-01

The ultrahigh static displacement-acceleration sensitivity of a mechanical sensing chip is essential primarily for an ultrasensitive accelerometer. In this paper, an optimal design to implement to a single-axis MOEMS accelerometer consisting of a grating interferometry cavity and a micromachined sensing chip is presented. The micromachined sensing chip is composed of a proof mass along with its mechanical cantilever suspension and substrate. The dimensional parameters of the sensing chip, including the length, width, thickness and position of the cantilevers are evaluated and optimized both analytically and by finite-element-method (FEM) simulation to yield an unprecedented acceleration-displacement sensitivity. Compared with one of the most sensitive single-axis MOEMS accelerometers reported in the literature, the optimal mechanical design can yield a profound sensitivity improvement with an equal footprint area, specifically, 200% improvement in displacement-acceleration sensitivity with moderate resonant frequency and dynamic range. The modified design was microfabricated, packaged with the grating interferometry cavity and tested. The experimental results demonstrate that the MOEMS accelerometer with modified design can achieve the acceleration-displacement sensitivity of about 150μm/g and acceleration sensitivity of greater than 1500V/g, which validates the effectiveness of the optimal design.

Development of Equivalent Material Properties of Microbump for Simulating Chip Stacking Packaging

PubMed Central

Lee, Chang-Chun; Tzeng, Tzai-Liang; Huang, Pei-Chen

2015-01-01

A three-dimensional integrated circuit (3D-IC) structure with a significant scale mismatch causes difficulty in analytic model construction. This paper proposes a simulation technique to introduce an equivalent material composed of microbumps and their surrounding wafer level underfill (WLUF). The mechanical properties of this equivalent material, including Young’s modulus (E), Poisson’s ratio, shear modulus, and coefficient of thermal expansion (CTE), are directly obtained by applying either a tensile load or a constant displacement, and by increasing the temperature during simulations, respectively. Analytic results indicate that at least eight microbumps at the outermost region of the chip stacking structure need to be considered as an accurate stress/strain contour in the concerned region. In addition, a factorial experimental design with analysis of variance is proposed to optimize chip stacking structure reliability with four factors: chip thickness, substrate thickness, CTE, and E-value. Analytic results show that the most significant factor is CTE of WLUF. This factor affects microbump reliability and structural warpage under a temperature cycling load and high-temperature bonding process. WLUF with low CTE and high E-value are recommended to enhance the assembly reliability of the 3D-IC architecture. PMID:28793495

To Flip or Not to Flip? An Exploratory Study Comparing Student Performance in Calculus I

ERIC Educational Resources Information Center

Schroeder, Larissa B.; McGivney-Burelle, Jean; Xue, Fei

2015-01-01

The purpose of this exploratory, mixed-methods study was to compare student performance in flipped and non-flipped sections of Calculus I. The study also examined students' perceptions of the flipping pedagogy. Students in the flipped courses reported spending, on average, an additional 1-2 hours per week outside of class on course content.…

The Partially Flipped Classroom: The Effects of Flipping a Module on "Junk Science" in a Large Methods Course

ERIC Educational Resources Information Center

Burgoyne, Stephanie; Eaton, Judy

2018-01-01

Flipped classrooms are gaining popularity, especially in psychology statistics courses. However, not all courses lend themselves to a fully flipped design, and some instructors might not want to commit to flipping every class. We tested the effectiveness of flipping just one component (a module on junk science) of a large methods course. We…

Vacuum packaging of InGaAs focal plane array with four-stage thermoelectric cooler

NASA Astrophysics Data System (ADS)

Mo, De-feng; Liu, Da-fu; Yang, Li-yi; Xu, Qin-fei; Li, Xue

2013-09-01

The InGaAs focal plane array (FPA) detectors, covering the near-infrared 1~2.4 μm wavelength range, have been developed for application in space-based spectroscopy of the Earth atmosphere. This paper shows an all-metal vacuum package design for area array InGaAs detector of 1024×64 pixels, and its architecture will be given. Four-stage thermoelectric cooler (TEC) is used to cool down the FPA chip. To acquire high heat dissipation for TEC's Joule-heat, tungsten copper (CuW80) and kovar (4J29) is used as motherboard and cavity material respectively which joined by brazing. The heat loss including conduction, convection and radiation is analyzed. Finite element model is established to analyze the temperature uniformity of the chip substrate which is made of aluminum nitride (AlN). The performance of The TEC with and without heat load in vacuum condition is tested. The results show that the heat load has little influence to current-voltage relationship of TEC. The temperature difference (ΔT) increases as the input current increases. A linear relationship exists between heat load and ΔT of the TEC. Theoretical analysis and calculation show that the heat loss of radiation and conduction is about 187 mW and 82 mW respectively. Considering the Joule-heat of readout circuit and the heat loss of radiation and conduction, the FPA for a 220 K operation at room temperature can be achieved. As the thickness of AlN chip substrate is thicker than 1 millimeter, the temperature difference can be less than 0.3 K.

Ceramic ball grid array package stress analysis

NASA Astrophysics Data System (ADS)

Badri, S. H. B. S.; Aziz, M. H. A.; Ong, N. R.; Sauli, Z.; Alcain, J. B.; Retnasamy, V.

2017-09-01

The ball grid array (BGA), a form of chip scale package (CSP), was developed as one of the most advanced surface mount devices, which may be assembled by an ordinary surface ball bumps are used instead of plated nickel and gold (Ni/Au) bumps. Assembly and reliability of the BGA's printed circuit board (PCB), which is soldered by conventional surface mount technology is considered in this study. The Ceramic Ball Grid Array (CBGA) is a rectangular ceramic package or square-shaped that will use the solder ball for external electrical connections instead of leads or wire for connections. The solder balls will be arranged in an array or grid at the bottom of the ceramic package body. In this study, ANSYS software is used to investigate the stress on the package for 2 balls and 4 balls of the CBGA package with the various force range of 1-3 Newton applied to the top of the die, top of the substrate and side of the substrate. The highest maximum stress was analyzed and the maximum equivalent stress was observed on the solder ball and the die. From the simulation result, the CBGA package with less solder balls experience higher stress compared to the package with many solder balls. Therefore, less number of solder ball on the CBGA package results higher stress and critically affect the reliability of the solder balls itself, substrate and die which can lead to the solder crack and also die crack.

Quartz/fused silica chip carriers

NASA Technical Reports Server (NTRS)

1992-01-01

The primary objective of this research and development effort was to develop monolithic microwave integrated circuit (MMIC) packaging which will operate efficiently at millimeter-wave frequencies. The packages incorporated fused silica as the substrate material which was selected due to its favorable electrical properties and potential performance improvement over more conventional materials for Ka-band operation. The first step towards meeting this objective is to develop a package that meets standard mechanical and thermal requirements using fused silica and to be compatible with semiconductor devices operating up to at least 44 GHz. The second step is to modify the package design and add multilayer and multicavity capacity to allow for application specific integrated circuits (ASIC's) to control multiple phase shifters. The final step is to adapt the package design to a phased array module with integral radiating elements. The first task was a continuation of the SBIR Phase 1 work. Phase 1 identified fused silica as a viable substrate material by demonstrating various plating, machining, and adhesion properties. In Phase 2 Task 1, a package was designed and fabricated to validate these findings. Task 2 was to take the next step in packaging and fabricate a multilayer, multichip module (MCM). This package is the predecessor to the phased array module and demonstrates the ability to via fill, circuit print, laminate, and to form vertical interconnects. The final task was to build a phased array module. The radiating elements were to be incorporated into the package instead of connecting to it with wire or ribbon bonds.

Process development of beam-lead silicon-gate COS/MOS integrated circuits

NASA Technical Reports Server (NTRS)

Baptiste, B.; Boesenberg, W.

1974-01-01

Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.

Hollow Core Bragg Waveguide Design and Fabrication for Enhanced Raman Spectroscopy

NASA Astrophysics Data System (ADS)

Ramanan, Janahan

Raman spectroscopy is a widely used technique to unambiguously ascertain the chemical composition of a sample. The caveat with this technique is its extremely weak optical cross-section, making it difficult to measure Raman signal with standard optical setups. In this thesis, a novel hollow core Bragg Reflection Waveguide was designed to simultaneously increase the generation and collection of Raman scattered photons. A robust fabrication process of this waveguide was developed employing flip-chip bonding methods to securely seal the hollow core channel. The waveguide air-core propagation loss was experimentally measured to be 0.17 dB/cm, and the Raman sensitivity limit was measured to be 3 mmol/L for glycerol solution. The waveguide was also shown to enhance Raman modes of standard household aerosols that could not be seen with other devices.

Wireless poly(dimethylsiloxane) quartz-crystal-microbalance biosensor chip fabricated by nanoimprint lithography for micropump integration aiming at application in lab-on-a-chip

NASA Astrophysics Data System (ADS)

Kato, Fumihito; Noguchi, Hiroyuki; Kodaka, Yukinari; Oshida, Naoya; Ogi, Hirotsugu

2018-07-01

We developed a quartz-crystal-microbalance (QCM) biosensor chip that operates wirelessly via electromagnetic waves, using poly(dimethylsiloxane) (PDMS). An AT-cut quartz oscillator (22–30 µm) is packaged in a microchannel, where it is supported by micropillars without mechanical fixing. As a result, the quartz oscillator is little affected by the thermal stress caused by the difference in the thermal expansion coefficients of the components, and the leakage of the vibration energy of the quartz oscillator is reduced. Consequently, high-frequency (∼56 MHz) measurement with a stable baseline (±∼2 ppm) is realized. We succeeded in repeatedly monitoring the binding reaction between immunoglobulin G (IgG) and Staphylococcus aureus protein A (SPA) with the quartz oscillator on which SPA molecules were immobilized nonspecifically. In addition, the affinity between SPA and IgG was calculated from the association and dissociation curves, and the usefulness of our wireless PDMS QCM biosensor was demonstrated.

Detection of M. tuberculosis using DNA chips combined with an image analysis system.

PubMed

Huang, T-S; Liu, Y-C; Bair, C-H; Sy, C-L; Chen, Y-S; Tu, H-Z; Chen, B-C

2008-01-01

To develop a packaged DNA chip assay (the DR. MTBC Screen assay) for direct detection of the Mycobacterium tuberculosis complex. We described a DNA chip assay based on the IS6110 gene that can be used for the detection of M. tuberculosis complex. Probes were spotted onto the polystyrene strips in the wells of 96-well microtitre plates and used for hybridisation with biotin-labelled amplicon to yield a pattern of visualised positive spots. The plate image was scanned, analysed and interpreted automatically. The results corresponded well with those obtained by conventional culture as well as clinical diagnosis, with sensitivity and specificity rates of respectively 83.8% and 94.2%, and 84.6% and 96.3%. We conclude that the DR. MTBC Screen assay can detect M. tuberculosis complex rapidly in respiratory specimens, readily adapts to routine work and provides a flexible choice to meet different cost-effectiveness and automation needs in TB-endemic countries. The cost for reagents is around US$10 per sample.

Demonstration of Compact and Low-Loss Athermal Arrayed-Waveguide Grating Module Based on 2.5%-Δ Silica-Based Waveguides

NASA Astrophysics Data System (ADS)

Maru, Koichi; Abe, Yukio; Uetsuka, Hisato

2008-10-01

We demonstrated a compact and low-loss athermal arrayed-waveguide grating (AWG) module utilizing silica-based planar lightwave circuit (PLC) technology. Spot-size converters based on a vertical ridge-waveguide taper were integrated with a 2.5%-Δ athermal AWG to reduce the loss at chip-to-fiber interface. Spot-size converters based on a segmented core were formed around resin-filled trenches for athermalization formed in the slab to reduce the diffraction loss at the trenches. A 16-channel athermal AWG module with 100-GHz channel spacing was fabricated. The use of a 2.5%-Δ athermal chip with a single-side fiber array enabled a compact package of the size of 41.6×16.6×4.5 mm3. Athermal characteristics and a small insertion loss of 3.5-3.8 dB were obtained by virtue of low fiber-to-chip coupling loss and athermalization with low excess loss.

Comparing the Effectiveness of Blended, Semi-Flipped, and Flipped Formats in an Engineering Numerical Methods Course

ERIC Educational Resources Information Center

Clark, Renee M.; Kaw, Autar; Besterfield-Sacre, Mary

2016-01-01

Blended, flipped, and semi-flipped instructional approaches were used in various sections of a numerical methods course for undergraduate mechanical engineers. During the spring of 2014, a blended approach was used; in the summer of 2014, a combination of blended and flipped instruction was used to deliver a semi-flipped course; and in the fall of…

Fat fraction bias correction using T1 estimates and flip angle mapping.

PubMed

Yang, Issac Y; Cui, Yifan; Wiens, Curtis N; Wade, Trevor P; Friesen-Waldner, Lanette J; McKenzie, Charles A

2014-01-01

To develop a new method of reducing T1 bias in proton density fat fraction (PDFF) measured with iterative decomposition of water and fat with echo asymmetry and least-squares estimation (IDEAL). PDFF maps reconstructed from high flip angle IDEAL measurements were simulated and acquired from phantoms and volunteer L4 vertebrae. T1 bias was corrected using a priori T1 values for water and fat, both with and without flip angle correction. Signal-to-noise ratio (SNR) maps were used to measure precision of the reconstructed PDFF maps. PDFF measurements acquired using small flip angles were then compared to both sets of corrected large flip angle measurements for accuracy and precision. Simulations show similar results in PDFF error between small flip angle measurements and corrected large flip angle measurements as long as T1 estimates were within one standard deviation from the true value. Compared to low flip angle measurements, phantom and in vivo measurements demonstrate better precision and accuracy in PDFF measurements if images were acquired at a high flip angle, with T1 bias corrected using T1 estimates and flip angle mapping. T1 bias correction of large flip angle acquisitions using estimated T1 values with flip angle mapping yields fat fraction measurements of similar accuracy and superior precision compared to low flip angle acquisitions. Copyright © 2013 Wiley Periodicals, Inc.

FLICE-like inhibitory protein (FLIP) protects against apoptosis and suppresses NF-kappaB activation induced by bacterial lipopolysaccharide.

PubMed

Bannerman, Douglas D; Eiting, Kristine T; Winn, Robert K; Harlan, John M

2004-10-01

Bacterial lipopolysaccharide (LPS) via its activation of Toll-like receptor-4 contributes to much of the vascular injury/dysfunction associated with gram-negative sepsis. Inhibition of de novo gene expression has been shown to sensitize endothelial cells (EC) to LPS-induced apoptosis, the onset of which correlates with decreased expression of FLICE-like inhibitory protein (FLIP). We now have data that conclusively establish a role for FLIP in protecting EC against LPS-induced apoptosis. Overexpression of FLIP protected against LPS-induced apoptosis, whereas down-regulation of FLIP using antisense oligonucleotides sensitized EC to direct LPS killing. Interestingly, FLIP overexpression suppressed NF-kappaB activation induced by LPS, but not by phorbol ester, suggesting a specific role for FLIP in mediating LPS activation. Conversely, mouse embryo fibroblasts (MEF) obtained from FLIP -/- mice showed enhanced LPS-induced NF-kappaB activation relative to those obtained from wild-type mice. Reconstitution of FLIP-/- MEF with full-length FLIP reversed the enhanced NF-kappaB activity elicited by LPS in the FLIP -/- cells. Changes in the expression of FLIP had no demonstrable effect on other known LPS/Tlr-4-activated signaling pathways including the p38, Akt, and Jnk pathways. Together, these data support a dual role for FLIP in mediating LPS-induced apoptosis and NF-kappaB activation.

Plasticized methylcellulose coating for reducing oil uptake in potato chips.

PubMed

Tavera-Quiroz, María José; Urriza, Marina; Pinotti, Adriana; Bertola, Nora

2012-05-01

As a result of consumers' health concerns and the trend towards healthier and low-fat food products, research has been undertaken to reduce the amount of fat absorbed in fried foods. This work focused on studying the efficacy of sorbitol and glycerol as plasticizers of methylcellulose coatings used to reduce oil uptake during the frying process of potato chips Changes in color, mechanical properties, water activity and lipid oxidation during storage were monitored. Also, an explanation regarding the different performances between both methylcellulose coatings with and without plasticizer was attained and techniques from the field of packaging films such as dynamic mechanical analyzer (DMA) and Fourier transform infrared spectroscopy were applied to analyze the behavior of coatings submitted to the frying operation. The application of a methylcellulose coating was an adequate choice to reduce oil absorption in fried potato chips. The most effective formulation was 10 g L(-1) methylcellulose with the addition of 7.5 g L(-1) sorbitol. With the incorporation of this formulation, oil absorption was reduced by 30%. Neither the sorbitol concentration nor the presence of the MC coating affected the puncture maximum force and color parameters L and a*. The results of the sensory analysis indicated that the panelists could not distinguish between the coated and uncoated potato chips. Methylcellulose-based coating plasticized with sorbitol could be an alternative for obtaining healthier potato chips. Copyright © 2011 Society of Chemical Industry.

Digital PCR on an integrated self-priming compartmentalization chip.

PubMed

Zhu, Qiangyuan; Qiu, Lin; Yu, Bingwen; Xu, Yanan; Gao, Yibo; Pan, Tingting; Tian, Qingchang; Song, Qi; Jin, Wei; Jin, Qinhan; Mu, Ying

2014-03-21

An integrated on-chip valve-free and power-free microfluidic digital PCR device is for the first time developed by making use of a novel self-priming compartmentalization and simple dehydration control to realize 'divide and conquer' for single DNA molecule detection. The high gas solubility of PDMS is exploited to provide the built-in power of self-priming so that the sample and oil are sequentially sucked into the device to realize sample self-compartmentalization based on surface tension. The lifespan of its self-priming capability was about two weeks tested using an air-tight packaging bottle sealed with a small amount of petroleum jelly, which is significant for a practical platform. The SPC chip contains 5120 independent 5 nL microchambers, allowing the samples to be compartmentalized completely. Using this platform, three different abundances of lung cancer related genes are detected to demonstrate the feasibility and flexibility of the microchip for amplifying a single nucleic acid molecule. For maximal accuracy, within less than 5% of the measurement deviation, the optimal number of positive chambers is between 400 and 1250 evaluated by the Poisson distribution, which means one panel can detect an average of 480 to 4804 template molecules. This device without world-to-chip connections eliminates the constraint of the complex pipeline control, and is an integrated on-chip platform, which would be a significant improvement to digital PCR automation and more user-friendly.

Biocompatible circuit-breaker chip for thermal management of biomedical microsystems

NASA Astrophysics Data System (ADS)

Luo, Yi; Dahmardeh, Masoud; Takahata, Kenichi

2015-05-01

This paper presents a thermoresponsive micro circuit breaker for biomedical applications specifically targeted at electronic intelligent implants. The circuit breaker is micromachined to have a shape-memory-alloy cantilever actuator as a normally closed temperature-sensitive switch to protect the device of interest from overheating, a critical safety feature for smart implants including those that are electrothermally driven with wireless micro heaters. The device is fabricated in a size of 1.5  ×  2.0  ×  0.46 mm3 using biocompatible materials and a chip-based titanium package, exhibiting a nominal cold-state resistance of 14 Ω. The breaker rapidly enters the full open condition when the chip temperature exceeds 63 °C, temporarily breaking the circuit of interest to lower its temperature until chip temperature drops to 51 °C, at which the breaker closes the circuit to allow current to flow through it again, physically limiting the maximum temperature of the circuit. This functionality is tested in combination with a wireless resonant heater powered by radio-frequency electromagnetic radiation, demonstrating self-regulation of heater temperature. The developed circuit-breaker chip operates in a fully passive manner that removes the need for active sensor and circuitry to achieve temperature regulation in a target device, contributing to the miniaturization of biomedical microsystems including electronic smart implants where thermal management is essential.

Direct-referencing Two-dimensional-array Digital Microfluidics Using Multi-layer Printed Circuit Board

PubMed Central

Gong, Jian; Kim, Chang-Jin “CJ”

2008-01-01

Digital (i.e. droplet-based) microfluidics, by the electrowetting-on-dielectric (EWOD) mechanism, has shown great potential for a wide range of applications, such as lab-on-a-chip. While most reported EWOD chips use a series of electrode pads essentially in one-dimensional line pattern designed for specific tasks, the desired universal chips allowing user-reconfigurable paths would require the electrode pads in two-dimensional pattern. However, to electrically access the electrode pads independently, conductive lines need to be fabricated underneath the pads in multiple layers, raising a cost issue especially for disposable chip applications. In this article, we report the building of digital microfluidic plates based on a printed-circuit-board (PCB), in which multilayer electrical access lines were created inexpensively using mature PCB technology. However, due to its surface topography and roughness and resulting high resistance against droplet movement, as-fabricated PCB surfaces require unacceptably high (~500 V) voltages unless coated with or immersed in oil. Our goal is EWOD operations of aqueous droplets not only on oil-covered but also on dry surfaces. To meet varying levels of performances, three types of gradually complex post-PCB microfabrication processes are developed and evaluated. By introducing land-grid-array (LGA) sockets in the packaging, a scalable digital microfluidics system with reconfigurable and low-cost chip is also demonstrated. PMID:19234613

GeoChip 3.0 as a high-thoughput tool for analyzing microbial community composition, structure, and functional activity

DOE Office of Scientific and Technical Information (OSTI.GOV)

He, Z.; Deng, Y.; Van Nostrand, J.D.

A new generation of functional gene arrays (FGAs; GeoChip 3.0) has been developed, with {approx}28,000 probes covering approximately 57,000 gene variants from 292 functional gene families involved in carbon, nitrogen, phosphorus and sulfur cycles, energy metabolism, antibiotic resistance, metal resistance and organic contaminant degradation. GeoChip 3.0 also has several other distinct features, such as a common oligo reference standard (CORS) for data normalization and comparison, a software package for data management and future updating and the gyrB gene for phylogenetic analysis. Computational evaluation of probe specificity indicated that all designed probes would have a high specificity to their corresponding targets.more » Experimental analysis with synthesized oligonucleotides and genomic DNAs showed that only 0.0036-0.025% false-positive rates were observed, suggesting that the designed probes are highly specific under the experimental conditions examined. In addition, GeoChip 3.0 was applied to analyze soil microbial communities in a multifactor grassland ecosystem in Minnesota, USA, which showed that the structure, composition and potential activity of soil microbial communities significantly changed with the plant species diversity. As expected, GeoChip 3.0 is a high-throughput powerful tool for studying microbial community functional structure, and linking microbial communities to ecosystem processes and functioning.« less

Challenges and Opportunities in Gen3 Embedded Cooling with High-Quality Microgap Flow

NASA Technical Reports Server (NTRS)

Bar-Cohen, Avram; Robinson, Franklin L.; Deisenroth, David C.

2018-01-01

Gen3, Embedded Cooling, promises to revolutionize thermal management of advanced microelectronic systems by eliminating the sequential conductive and interfacial thermal resistances which dominate the present 'remote cooling' paradigm. Single-phase interchip microfluidic flow with high thermal conductivity chips and substrates has been used successfully to cool single transistors dissipating more than 40kW/sq cm, but efficient heat removal from transistor arrays, larger chips, and chip stacks operating at these prodigious heat fluxes would require the use of high vapor fraction (quality), two-phase cooling in intra- and inter-chip microgap channels. The motivation, as well as the challenges and opportunities associated with evaporative embedded cooling in realistic form factors, is the focus of this paper. The paper will begin with a brief review of the history of thermal packaging, reflecting the 70-year 'inward migration' of cooling technology from the computer-room, to the rack, and then to the single chip and multichip module with 'remote' or attached air- and liquid-cooled coldplates. Discussion of the limitations of this approach and recent results from single-phase embedded cooling will follow. This will set the stage for discussion of the development challenges associated with application of this Gen3 thermal management paradigm to commercial semiconductor hardware, including dealing with the effects of channel length, orientation, and manifold-driven centrifugal acceleration on the governing behavior.

Design, development, fabrication and delivery of register and multiplexer units. [CMOS monolithic chip development

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardi, T.

1978-01-01

Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated. The CMOS standard cell array technique was selected and implemented. Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation. One of the chip types, multiplexer register type 1, is fabricated on a 0.143 x 0.123 inch chip. It uses nine standard cell types for a total of 54 standard cells. This involves more than 350 transistors and has the functional equivalent of 111 gates. The second chip, multiplexer register type 2, is housed on a 0.12 x 0.12 inch die. It uses 13 standard cell types, for a total of 42 standard cells. It contains more than 300 transistors, the functional equivalent of 112 gates. All of the hermetically sealed units were initially screened for proper functional operation. The static leakage and the dynamic leakage were measured. Dynamic measurements were made and recorded. At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1. At 5 V these units shifted data at a 6.6 MHz rate. The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C.

A cost-effective 25-Gb/s EML TOSA using all-in-one FPCB wiring and metal optical bench.

PubMed

Han, Young-Tak; Kwon, Oh-Kee; Lee, Dong-Hun; Lee, Chul-Wook; Leem, Young-Ahn; Shin, Jang-Uk; Park, Sang-Ho; Baek, Yongsoon

2013-11-04

We present a cost-effective 25-Gb/s electro-absorption modulator integrated laser (EML) transmitter optical sub-assembly (TOSA) using all-in-one flexible printed circuit board (FPCB) wiring and a metal optical bench (MOB). For a low cost and high bandwidth TOSA, internal and external wirings and feed-through of the TOSA to transmit radio-frequency (RF) signal are configured all-in-one using the FPCB. The FPCB is extended from an exterior of the TOSA package up to an EML chip inside the package through the slit formed on a rear sidewall of the package and die-bonded on the MOB. The EML TOSA shows a modulated output power of more than 3.5 dBm and a clear eye pattern with a dynamic extinction ratio of ~8.4 dB at a data rate of 25.78 Gb/s.

MEMS Direct Chip Attach Packaging Methodologies and Apparatuses for Harsh Environments

NASA Technical Reports Server (NTRS)

Okojie, Robert S. (Inventor)

2009-01-01

Methods of bulk manufacturing high temperature sensor subassembly packages are disclosed and claimed. Sensors are sandwiched between a top cover and a bottom cover so as to enable the peripheries of the top covers, sensors and bottom covers to be sealed and bound securely together are disclosed and claimed. Sensors are placed on the bottom covers leaving the periphery of the bottom cover exposed. Likewise, top covers are placed on the sensors leaving the periphery of the sensor exposed. Individual sensor sub-assemblies are inserted into final packaging elements which are also disclosed and claimed. Methods of directly attaching wires or pins to contact pads on the sensors are disclosed and claimed. Sensors, such as pressure sensors and accelerometers, and headers made out of silicon carbide and aluminum nitride are disclosed and claimed. Reference cavities are formed in some embodiments disclosed and claimed herein where top covers are not employed.

MEMS Direct Chip Attach Packaging Methodologies and Apparatuses for Harsh Environments

NASA Technical Reports Server (NTRS)

Okojie, Robert S. (Inventor)

2005-01-01

Methods of bulk manufacturing high temperature sensor sub-assembly packages are disclosed and claimed. Sensors are sandwiched between a top cover and a bottom cover so as to enable the peripheries of the top covers, sensors and bottom covers to be sealed and bound securely together are disclosed and claimed. Sensors are placed on the bottom covers leaving the periphery of the bottom cover exposed. Likewise, top covers are placed on the sensors leaving the periphery of the sensor exposed. Individual sensor sub- assemblies are inserted into final packaging elements which are also disclosed and claimed. Methods of directly attach- ing wires or pins to contact pads on the sensors are disclosed and claimed. Sensors, such as pressure sensors and accelerometers, and headers made out of silicon carbide and aluminum nitride are disclosed and claimed. Reference cavities are formed in some embodiments disclosed and claimed herein where top covers are not employed.

Bypass diode integration

NASA Technical Reports Server (NTRS)

Shepard, N. F., Jr.

1981-01-01

Protective bypass diodes and mounting configurations which are applicable for use with photovoltaic modules having power dissipation requirements in the 5 to 50 watt range were investigated. Using PN silicon and Schottky diode characterization data on packaged diodes and diode chips, typical diodes were selected as representative for each range of current carrying capacity, an appropriate heat dissipating mounting concept along with its environmental enclosure was defined, and a thermal analysis relating junction temperature as a function of power dissipation was performed. In addition, the heat dissipating mounting device dimensions were varied to determine the effect on junction temperature. The results of the analysis are presented as a set of curves indicating junction temperature as a function of power dissipation for each diode package.

Contamination control in hybrid microelectronic modules. Part 3: Specifications for coating material and process controls

NASA Technical Reports Server (NTRS)

Himmel, R. P.

1975-01-01

Resin systems for coating hybrids prior to hermetic sealing are described. The resin systems are a flexible silicone junction resin system and a flexible cycloaliphatic epoxy resin system. The coatings are intended for application to the hybrid after all the chips have been assembled and wire bonded, but prior to hermetic sealing of the package. The purpose of the coating is to control particulate contamination by immobilizing particles and by passivating the hybrid. Recommended process controls for the purpose of minimizing contamination in hybrid microcircuit packages are given. Emphasis is placed on those critical hybrid processing steps in which contamination is most likely to occur.

New developments on high-efficiency infrared and InGaAlP light-emitting diodes at OSRAM Opto Semiconductors

NASA Astrophysics Data System (ADS)

Broell, Markus; Sundgren, Petrus; Rudolph, Andreas; Schmid, Wolfgang; Vogl, Anton; Behringer, Martin

2014-02-01

We present our latest results on developments of infrared and red light emitting diodes. Both chiptypes are based on the Thinfilm technology. For infrared the brightness has been raised by 25% with respect to former products in a package with standard silicon casting, corresponding to a brightness increase of 33% for the bare chip. In a lab package a wallplug efficiency of more than 72% at a wavelength of 850nm could be reached. For red InGaAlP LEDs we could demonstrate a light output in excess of 200lm/W and a brightness of 133lm at a typical operating current of 350mA.

Flipping Math in a Secondary Classroom

ERIC Educational Resources Information Center

Graziano, Kevin J.; Hall, John D.

2017-01-01

Research on flipped instruction with K-12 English Language Learners (ELLs) is limited. The purpose of this study was to examine the academic performance of ELLs who received flipped instruction in an algebra course at a newcomer high school, and to investigate ELLs' perceptions of flipped learning. Results indicate flipped instruction engaged…

Flipped Classroom Experiences: Student Preferences and Flip Strategy in a Higher Education Context

ERIC Educational Resources Information Center

McNally, Brenton; Chipperfield, Janine; Dorsett, Pat; Del Fabbro, Letitia; Frommolt, Valda; Goetz, Sandra; Lewohl, Joanne; Molineux, Matthew; Pearson, Andrew; Reddan, Gregory; Roiko, Anne; Rung, Andrea

2017-01-01

Despite the popularity of the flipped classroom, its effectiveness in achieving greater engagement and learning outcomes is currently lacking substantial empirical evidence. This study surveyed 563 undergraduate and postgraduate students (61% female) participating in flipped teaching environments and ten convenors of the flipped courses in which…

FLIP the Switch: Regulation of Apoptosis and Necroptosis by cFLIP

PubMed Central

Tsuchiya, Yuichi; Nakabayashi, Osamu; Nakano, Hiroyasu

2015-01-01

cFLIP (cellular FLICE-like inhibitory protein) is structurally related to caspase-8 but lacks proteolytic activity due to multiple amino acid substitutions of catalytically important residues. cFLIP protein is evolutionarily conserved and expressed as three functionally different isoforms in humans (cFLIPL, cFLIPS, and cFLIPR). cFLIP controls not only the classical death receptor-mediated extrinsic apoptosis pathway, but also the non-conventional pattern recognition receptor-dependent apoptotic pathway. In addition, cFLIP regulates the formation of the death receptor-independent apoptotic platform named the ripoptosome. Moreover, recent studies have revealed that cFLIP is also involved in a non-apoptotic cell death pathway known as programmed necrosis or necroptosis. These functions of cFLIP are strictly controlled in an isoform-, concentration- and tissue-specific manner, and the ubiquitin-proteasome system plays an important role in regulating the stability of cFLIP. In this review, we summarize the current scientific findings from biochemical analyses, cell biological studies, mathematical modeling, and gene-manipulated mice models to illustrate the critical role of cFLIP as a switch to determine the destiny of cells among survival, apoptosis, and necroptosis. PMID:26694384

Terahertz MMICs and Antenna-in-Package Technology at 300 GHz for KIOSK Download System

NASA Astrophysics Data System (ADS)

Tajima, Takuro; Kosugi, Toshihiko; Song, Ho-Jin; Hamada, Hiroshi; El Moutaouakil, Amine; Sugiyama, Hiroki; Matsuzaki, Hideaki; Yaita, Makoto; Kagami, Osamu

2016-12-01

Toward the realization of ultra-fast wireless communications systems, the inherent broad bandwidth of the terahertz (THz) band is attracting attention, especially for short-range instant download applications. In this paper, we present our recent progress on InP-based THz MMICs and packaging techniques based on low-temperature co-fibered ceramic (LTCC) technology. The transmitter MMICs are based on 80-nm InP-based high electron mobility transistors (HEMTs). Using the transmitter packaged in an E-plane split-block waveguide and compact lens receiver packaged in LTCC multilayered substrates, we tested wireless data transmission up to 27 Gbps with the simple amplitude key shifting (ASK) modulation scheme. We also present several THz antenna-in-packaging solutions based on substrate integrated waveguide (SIW) technology. A vertical hollow (VH) SIW was applied to a compact medium-gain SIW antenna and low-loss interconnection integrated in LTCC multi-layer substrates. The size of the LTCC antennas with 15-dBi gain is less than 0.1 cm3. For feeding the antenna, we investigated an LTCC-integrated transition and polyimide transition to LTCC VH SIWs. These transitions exhibit around 1-dB estimated loss at 300 GHz and more than 35 GHz bandwidth with 10-dB return loss. The proposed package solutions make antennas and interconnections easy to integrate in a compact LTCC package with an MMIC chip for practical applications.

Silicon Photonics: Challenges and Future

DTIC Science & Technology

2007-01-01

process or phonon assisted. It directly impacts the internal quantum efficiency through the relationship : ηi = (1+ (τrad/τ non-rad ))-1 There are...linear cavity approach, the reported differential quantum efficiency is currently low. The measured characteristic temperature (To), is lower than...rule changes • package design 4.1.2 Inter-chip interconnects There is a requirement on the circuit card to transfer data more efficiently between

On-Chip Hardware for Cell Monitoring: Contact Imaging and Notch Filtering

DTIC Science & Technology

2005-07-07

a polymer carrier. Spectrophotometer chosen and purchased for testing optical filters and materials. Characterization and comparison of fabricated...reproducibility of behavior. Multi-level SU8 process developed. Optimization of actuator for closing vial lids and development of lid sealing technology is...bending angles characterized as a function of temperature in NaDBS solution. " Photopatternable polymers are a viable interim packaging solution; through

Linear Fresnel Spectrometer Chip with Gradient Line Grating

NASA Technical Reports Server (NTRS)

Choi, Sang Hyouk (Inventor); Park, Yeonjoon (Inventor)

2015-01-01

A spectrometer that includes a grating that disperses light via Fresnel diffraction according to wavelength onto a sensing area that coincides with an optical axis plane of the grating. The sensing area detects the dispersed light and measures the light intensity associated with each wavelength of the light. Because the spectrometer utilizes Fresnel diffraction, it can be miniaturized and packaged as an integrated circuit.

Advanced Sensors for TBI

DTIC Science & Technology

2016-12-01

SMD-VAC- GP, Virtual Industries) with plastic tip. Then the chip was covered with silicone open-cell foam (0.062” thick, HT -870, Stockwell...the build. 26 We discussed with a sub- contractor in Livermore who might be able to perform the packaging assembly work. Dr. Kotovsky...worked with the sub- contractor on practice assemblies anticipating the new upcoming build. Working through an outside contractor represents an enormous

Flipped Learning in the Workplace

ERIC Educational Resources Information Center

Nederveld, Allison; Berge, Zane L.

2015-01-01

Purpose: The purpose of this paper is to serve as a summary of resources on flipped learning for workplace learning professionals. A recent buzzword in the training world is "flipped". Flipped learning and the flipped classroom are hot topics that have emerged in K-12 education, made their way to the university and are now being noticed…

How to Flip the Classroom--"Productive Failure or Traditional Flipped Classroom" Pedagogical Design?

ERIC Educational Resources Information Center

Song, Yanjie; Kapur, Manu

2017-01-01

The paper reports a quasi-experimental study comparing the "traditional flipped classroom" pedagogical design with the "productive failure" (Kapur, 2016) pedagogical design in the flipped classroom for a 2-week curricular unit on polynomials in a Hong Kong Secondary school. Different from the flipped classroom where students…

How Flipping Much? Consecutive Flipped Mathematics Courses and Their Influence on Students' Anxieties and Perceptions of Learning

ERIC Educational Resources Information Center

Dove, Anthony; Dove, Emily

2017-01-01

While studies have shown positive attributes related to flipped learning, especially in mathematics and statistics, there is limited understanding of how taking multiple flipped courses may impact students' learning of mathematics and their perceptions of mathematics. Specifically, this study examined how completing consecutive flipped mathematics…

A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Man-Chia; Perez, Aldo Pena; Kothapalli, Sri-Rajasekhar

This study presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 μm by 250 μm. The proof-of-concept receiver was implemented in an STMicroelectronics's 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a 4 × 4 subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables anmore » efficient in-pixel A/D conversion. The per-pixel switched-capacitor ΔΣ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator's measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. Finally, the functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array.« less

A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI

DOE PAGES

Chen, Man-Chia; Perez, Aldo Pena; Kothapalli, Sri-Rajasekhar; ...

2017-10-16

This study presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 μm by 250 μm. The proof-of-concept receiver was implemented in an STMicroelectronics's 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a 4 × 4 subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables anmore » efficient in-pixel A/D conversion. The per-pixel switched-capacitor ΔΣ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator's measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. Finally, the functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Soer, Wouter

LED luminaires have seen dramatic changes in cost breakdown over the past few years. The LED component cost, which until recently was the dominant portion of luminaire cost, has fallen to a level of the same order as the other luminaire components, such as the driver, housing, optics etc. With the current state of the technology, further luminaire performance improvement and cost reduction is realized most effectively by optimization of the whole system, rather than a single component. This project focuses on improving the integration between LEDs and drivers. Lumileds has developed a light engine platform based on low-cost high-powermore » LEDs and driver topologies optimized for integration with these LEDs on a single substrate. The integration of driver and LEDs enables an estimated luminaire cost reduction of about 25% for targeted applications, mostly due to significant reductions in driver and housing cost. The high-power LEDs are based on Lumileds’ patterned sapphire substrate flip-chip (PSS-FC) technology, affording reduced die fabrication and packaging cost compared to existing technology. Two general versions of PSS-FC die were developed in order to create the desired voltage and flux increments for driver integration: (i) small single-junction die (0.5 mm 2), optimal for distributed lighting applications, and (ii) larger multi-junction die (2 mm 2 and 4 mm 2) for high-power directional applications. Two driver topologies were developed: a tapped linear driver topology and a single-stage switch-mode topology, taking advantage of the flexible voltage configurations of the new PSS-FC die and the simplification opportunities enabled by integration of LEDs and driver on the same board. A prototype light engine was developed for an outdoor “core module” application based on the multi-junction PSS-FC die and the single-stage switch-mode driver. The light engine meets the project efficacy target of 128 lm/W at a luminous flux greater than 4100 lm, a correlated color temperature (CCT) of 4000K and a color rendering index (CRI) greater than 70.« less

Flipping the Graduate Qualitative Research Methods Classroom: Did It Lead to Flipped Learning?

ERIC Educational Resources Information Center

Earley, Mark

2016-01-01

The flipped, or inverted, classroom has gained popularity in a variety of fields and at a variety of educational levels, from K-12 through higher education. This paper describes the author's positive experience flipping a graduate qualitative research methods classroom. After a review of the current literature on flipped classrooms in higher…

Re-Envisioning the Archaic Higher Education Learning Environment: Implementation Processes for Flipped Classrooms

ERIC Educational Resources Information Center

Rabidoux, Salena; Rottmann, Amy

2018-01-01

Flipped classrooms are often utilized in PK-12 classrooms; however, there is also a growing trend of flipped classrooms in higher education. This paper presents the benefits and limitations of implementing flipped classrooms in higher education as well as resources for integrating a flipped classroom design to instruction. The various technology…

Flip-J: Development of the System for Flipped Jigsaw Supported Language Learning

ERIC Educational Resources Information Center

Yamada, Masanori; Goda, Yoshiko; Hata, Kojiro; Matsukawa, Hideya; Yasunami, Seisuke

2016-01-01

This study aims to develop and evaluate a language learning system supported by the "flipped jigsaw" technique, called "Flip-J". This system mainly consists of three functions: (1) the creation of a learning material database, (2) allocation of learning materials, and (3) formation of an expert and jigsaw group. Flip-J was…

Self-priming compartmentalization digital LAMP for point-of-care.

PubMed

Zhu, Qiangyuan; Gao, Yibo; Yu, Bingwen; Ren, Hao; Qiu, Lin; Han, Sihai; Jin, Wei; Jin, Qinhan; Mu, Ying

2012-11-21

Digital nucleic acid amplification provides unprecedented opportunities for absolute nucleic acid quantification by counting of single molecules. This technique is useful for molecular genetic analysis in cancer, stem cell, bacterial, non-invasive prenatal diagnosis in which many biologists are interested. This paper describes a self-priming compartmentalization (SPC) microfluidic chip platform for performing digital loop-mediated amplification (LAMP). The energy for the pumping is pre-stored in the degassed bulk PDMS by exploiting the high gas solubility of PDMS; therefore, no additional structures other than channels and reservoirs are required. The sample and oil are sequentially sucked into the channels, and the pressure difference of gas dissolved in PDMS allows sample self-compartmentalization without the need for further chip manipulation such as with pneumatic microvalves and control systems, and so on. The SPC digital LAMP chip can be used like a 384-well plate, so, the world-to-chip fluidic interconnections are avoided. The microfluidic chip contains 4 separate panels, each panel contains 1200 independent 6 nL chambers and can be used to detect 4 samples simultaneously. Digital LAMP on the microfluidic chip was tested quantitatively by using β-actin DNA from humans. The self-priming compartmentalization behavior is roughly predictable using a two-dimensional model. The uniformity of compartmentalization was analyzed by fluorescent intensity and fraction of volume. The results showed that the feasibility and flexibility of the microfluidic chip platform for amplifying single nucleic acid molecules in different chambers made by diluting and distributing sample solutions. The SPC chip has the potential to meet the requirements of a general laboratory: power-free, valve-free, operating at isothermal temperature, inexpensive, sensitive, economizing labour time and reagents. The disposable analytical devices with appropriate air-tight packaging should be useful for point-of-care, and enabling it to become one of the common tools for biology research, especially, in point-of-care testing.

Low-complexity peak-to-average power ratio reduction scheme for flip-orthogonal frequency division multiplexing visible light communication system based on μ-law mapping

NASA Astrophysics Data System (ADS)

Wang, Jianping; Zhang, Peiran; Lu, Huimin; Feng, LiFang

2017-06-01

An orthogonal frequency division multiplexing (OFDM) technique called flipped OFDM (flip-OFDM) is apposite for a visible light communication system that needs the transmitted signal to be real and positive. Flip-OFDM uses two consecutive OFDM subframes to transmit the positive and negative parts of the signal. However, peak-to-average power ratio (PAPR) for flip-OFDM is increased tremendously due to the low value of total average power that arises from many zero values in both the positive and flipped frames. We first analyze the performance of flip-OFDM and perform a comparison with the conventional DC-biased OFDM (DCO-OFDM); then we propose a flip-OFDM scheme combined with μ-law mapping to reduce the high PAPR. The simulation results show that the PAPR of the system is reduced about 17.2 and 5.9 dB when compared with the normal flip-OFDM and DCO-OFDM signals, respectively.

Poisson property of the occurrence of flip-flops in a model membrane.

PubMed

Arai, Noriyoshi; Akimoto, Takuma; Yamamoto, Eiji; Yasui, Masato; Yasuoka, Kenji

2014-02-14

How do lipid molecules in membranes perform a flip-flop? The flip-flops of lipid molecules play a crucial role in the formation and flexibility of membranes. However, little has been determined about the behavior of flip-flops, either experimentally, or in molecular dynamics simulations. Here, we provide numerical results of the flip-flops of model lipid molecules in a model membrane and investigate the statistical properties, using millisecond-order coarse-grained molecular simulations (dissipative particle dynamics). We find that there are three different ways of flip-flops, which can be clearly characterized by their paths on the free energy surface. Furthermore, we found that the probability of the number of the flip-flops is well fitted by the Poisson distribution, and the probability density function for the inter-occurrence times of flip-flops coincides with that of the forward recurrence times. These results indicate that the occurrence of flip-flops is a Poisson process, which will play an important role in the flexibilities of membranes.

Perceptions of Senior-Year ELT Students for Flipped Classroom: A Materials Development Course

ERIC Educational Resources Information Center

Adnan, Müge

2017-01-01

This paper describes a structured attempt to integrate the flipped classroom model into a senior-level course at the higher education level. This study's purpose is to examine and compare the impact of flipped classrooms versus non-flipped as a means to contribute to the growing line of research on flipped teaching through an evaluation of both…

To Flip or Not to Flip? Analysis of a Flipped Classroom Pedagogy in a General Biology Course

ERIC Educational Resources Information Center

Heyborne, William H.; Perrett, Jamis J.

2016-01-01

In an attempt to better understand the flipped technique and evaluate its purported superiority in terms of student learning gains, the authors conducted an experiment comparing a flipped classroom to a traditional lecture classroom. Although the outcomes were mixed, regarding the superiority of either pedagogical approach, there does seem to be a…

Single-pipetting microfluidic assay device for rapid detection of Salmonella from poultry package.

PubMed

Fronczek, Christopher F; You, David J; Yoon, Jeong-Yeol

2013-02-15

A direct, sensitive, near-real-time, handheld optical immunoassay device was developed to detect Salmonella typhimurium in the naturally occurring liquid from fresh poultry packages (hereafter "chicken matrix"), with just single pipetting of sample (i.e., no filtration, culturing and/or isolation, thus reducing the assay time and the error associated with them). Carboxylated, polystyrene microparticles were covalently conjugated with anti-Salmonella, and the immunoagglutination due to the presence of Salmonella was detected by reading the Mie scatter signals from the microfluidic channels using a handheld device. The presence of chicken matrix did not affect the light scatter signal, since the optical parameters (particle size d, wavelength of incident light λ and scatter angle θ) were optimized to minimize the effect of sample matrix (animal tissues and blood proteins, etc.). The sample was loaded into a microfluidic chip that was split into two channels, one pre-loaded with vacuum-dried, antibody-conjugated particles and the other with vacuum-dried, bovine serum albumin-conjugated particles. This eliminated the need for a separate negative control, effectively minimizing chip-to-chip and sample-to-sample variations. Particles and the sample were diffused in-channel through chemical agitation by Tween 80, also vacuum-dried within the microchannels. Sequential mixing of the sample to the reagents under a strict laminar flow condition synergistically improved the reproducibility and linearity of the assay. In addition, dried particles were shown to successfully detect lower Salmonella concentrations for up to 8 weeks. The handheld device contains simplified circuitry eliminating unnecessary adjustment stages, providing a stable signal, thus maximizing sensitivity. Total assay time was 10 min, and the detection limit 10 CFU mL(-1) was observed in all matrices, demonstrating the suitability of this device for field assays. Copyright © 2012 Elsevier B.V. All rights reserved.

ELEVATION OF C-FLIP IN CASTRATE-RESISTANT PROSTATE CANCER ANTAGONIZES THERAPEUTIC RESPONSE TO ANDROGEN-RECEPTOR TARGETED THERAPY

PubMed Central

McCourt, Clare; Maxwell, Pamela; Mazzucchelli, Roberta; Montironi, Rodolfo; Scarpelli, Marina; Salto-Tellez, Manuel; O’Sullivan, Joe M.; Longley, Daniel B.; Waugh, David J.J.

2012-01-01

Purpose To characterize the importance of cellular Fas-associated death domain (FADD)-like interleukin 1β-converting enzyme (FLICE) inhibitory protein (c-FLIP), a key regulator of caspase 8 (FLICE)-promoted apoptosis, in modulating the response of prostate cancer (CaP) cells to androgen receptor (AR)-targeted therapy. Experimental Design c-FLIP expression was characterized by immunohistochemical analysis of prostatectomy tissue. The functional importance of c-FLIP to survival and modulating response to bicalutamide was studied by molecular and pharmacological interventions. Results c-FLIP expression was increased in high-grade prostatic intra-epithelial neoplasia (HGPIN) and CaP tissue relative to normal prostate epithelium (P<0.001). Maximal c-FLIP expression was detected in castrate-resistant CaP (CRPC) (P<0.001). In vitro, silencing of c-FLIP induced spontaneous apoptosis and increased 22Rv1 and LNCaP cell sensitivity to bicalutamide, determined by flow cytometry, PARP cleavage and caspase activity assays. The histone deacetylase inhibitors (HDACi), droxinostat and SAHA, also down-regulated c-FLIP expression, induced caspase-8 and caspase-3/7 mediated apoptosis and increased apoptosis in bicalutamide-treated cells. Conversely, the elevated expression of c-FLIP detected in the CRPC cell line VCaP underpinned their insensitivity to bicalutamide and SAHA in vitro. However, knockdown of c-FLIP induced spontaneous apoptosis in VCaP cells, indicating its relevance to cell survival and therapeutic resistance. Conclusion c-FLIP reduces the efficacy of AR-targeted therapy and maintains the viability of CaP cells. A combination of HDACi with androgen-deprivation therapy (ADT) may be effective in early-stage disease, using c-FLIP expression as a predictive biomarker of sensitivity. Direct targeting of c-FLIP however may be relevant to enhance the response of existing and novel therapeutics in CRPC. PMID:22623731

Points about Shoes

MedlinePlus

... comfortable in the store. Slip off the flip-flops. Flip-flops don’t give your feet enough support, so ... things like stubbing your toe. Consider some flip-flop how-tos: Buy new flip-flops when they ...

Polymer waveguides for electro-optical integration in data centers and high-performance computers.

PubMed

Dangel, Roger; Hofrichter, Jens; Horst, Folkert; Jubin, Daniel; La Porta, Antonio; Meier, Norbert; Soganci, Ibrahim Murat; Weiss, Jonas; Offrein, Bert Jan

2015-02-23

To satisfy the intra- and inter-system bandwidth requirements of future data centers and high-performance computers, low-cost low-power high-throughput optical interconnects will become a key enabling technology. To tightly integrate optics with the computing hardware, particularly in the context of CMOS-compatible silicon photonics, optical printed circuit boards using polymer waveguides are considered as a formidable platform. IBM Research has already demonstrated the essential silicon photonics and interconnection building blocks. A remaining challenge is electro-optical packaging, i.e., the connection of the silicon photonics chips with the system. In this paper, we present a new single-mode polymer waveguide technology and a scalable method for building the optical interface between silicon photonics chips and single-mode polymer waveguides.

A new Cu(GeNx) alloy film for industrial applications

NASA Astrophysics Data System (ADS)

Lin, Chon-Hsin

2014-11-01

In this study, a copper alloy [Cu(GeNx)] film is developed for industrial applications by cosputtering Cu and Ge targets on a barrierless Si substrate within a vacuum chamber sparsely filled with N2 gas. Through extensive tests conducted in this study, the alloy film shows good thermal stability and adhesion to the substrate with no noticeable interactions between the film and the substrate after annealing at 720 °C for 1 h. The new Cu(GeNx) alloy film also renders adequate wetting for solders, shows good solderability, and has a dissolution rate lower than pure Cu by at least one order of magnitude, in addition to having a comparable consumption rate to Ni. The alloy film seems suitable for industrial applications in, e.g., barrierless Si metallization, interconnect manufacture and, the replacement of the wetting and diffusion layers for flip-chip solder joints in conventional metallurgy.

The description of friction of silicon MEMS with surface roughness: virtues and limitations of a stochastic Prandtl-Tomlinson model and the simulation of vibration-induced friction reduction.

PubMed

van Spengen, W Merlijn; Turq, Viviane; Frenken, Joost W M

2010-01-01

We have replaced the periodic Prandtl-Tomlinson model with an atomic-scale friction model with a random roughness term describing the surface roughness of micro-electromechanical systems (MEMS) devices with sliding surfaces. This new model is shown to exhibit the same features as previously reported experimental MEMS friction loop data. The correlation function of the surface roughness is shown to play a critical role in the modelling. It is experimentally obtained by probing the sidewall surfaces of a MEMS device flipped upright in on-chip hinges with an AFM (atomic force microscope). The addition of a modulation term to the model allows us to also simulate the effect of vibration-induced friction reduction (normal-force modulation), as a function of both vibration amplitude and frequency. The results obtained agree very well with measurement data reported previously.

Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator

NASA Astrophysics Data System (ADS)

Nishikata, Daisuke; Ali, Mohammad Alimudin Bin Mohd; Hosoda, Kento; Matsumoto, Hiroshi; Nakamura, Kazuyuki

2018-04-01

A 36-bit × 32-entry fully digital ternary content addressable memory (TCAM) using the ratioless static random access memory (RL-SRAM) technology and fully complementary hierarchical-AND matching comparators (HAMCs) was developed. Since its fully complementary and digital operation enables the effect of device variabilities to be avoided, it can operate with a quite low supply voltage. A test chip incorporating a conventional TCAM and a proposed 24-transistor ratioless TCAM (RL-TCAM) cells and HAMCs was developed using a 0.18 µm CMOS process. The minimum operating voltage of 0.25 V of the developed RL-TCAM, which is less than half of that of the conventional TCAM, was measured via the conventional CMOS push–pull output buffers with the level-shifting and flipping technique using optimized pull-up voltage and resistors.

Dense Vertically Aligned Copper Nanowire Composites as High Performance Thermal Interface Materials.

PubMed

Barako, Michael T; Isaacson, Scott G; Lian, Feifei; Pop, Eric; Dauskardt, Reinhold H; Goodson, Kenneth E; Tice, Jesse

2017-12-06

Thermal interface materials (TIMs) are essential for managing heat in modern electronics, and nanocomposite TIMs can offer critical improvements. Here, we demonstrate thermally conductive, mechanically compliant TIMs based on dense, vertically aligned copper nanowires (CuNWs) embedded into polymer matrices. We evaluate the thermal and mechanical characteristics of 20-25% dense CuNW arrays with and without polydimethylsiloxane infiltration. The thermal resistance achieved is below 5 mm 2 K W -1 , over an order of magnitude lower than commercial heat sink compounds. Nanoindentation reveals that the nonlinear deformation mechanics of this TIM are influenced by both the CuNW morphology and the polymer matrix. We also implement a flip-chip bonding protocol to directly attach CuNW composites to copper surfaces, as required in many thermal architectures. Thus, we demonstrate a rational design strategy for nanocomposite TIMs that simultaneously retain the high thermal conductivity of aligned CuNWs and the mechanical compliance of a polymer.

Micromechanical Waveguide Mounts for Hot Electron Bolometer Terahertz Mixers

NASA Astrophysics Data System (ADS)

Brandt, Michael; Jacobs, Karl; Honingh, C. E.; Stodolka, Jörg

The superior beam matching of waveguide horn antennas to a telescope suggests using waveguide mounts even at THz-frequencies. In contrast to the more common quasi-optical (substrate lens) designs, the exceedingly small dimensions of the waveguide require novel micro-mechanical fabrication technologies. We will present a novel fabrication scheme for 1.9 THz waveguide mixers for SOFIA. Hot Electron Bolometer devices (HEB) are fabricated on 2 μm thick Si3N4 membrane strips. The strips are robust enough to be mounted on a separately fabricated Si support frame using an adapted flip-chip technology. Mounted onto the frame, the devices can be easily positioned and glued into a copper waveguide mount. Further developments regarding micro-mechanical processes to fabricate this copper waveguide mount and the receiving horn antenna will be presented, as well as the KOSMA Micro Assembly Station and its capabilities to handle mixer substrates.

Radiation Hard 0.13 Micron CMOS Library at IHP

NASA Astrophysics Data System (ADS)

Jagdhold, U.

2013-08-01

To support space applications we have developed an 0.13 micron CMOS library which should be radiation hard up to 200 krad. The article describes the concept to come to a radiation hard digital circuit and was introduces in 2010 [1]. By introducing new radiation hard design rules we will minimize IC-level leakage and single event latch-up (SEL). To reduce single event upset (SEU) we add two p-MOS transistors to all flip flops. For reliability reasons we use double contacts in all library elements. The additional rules and the library elements are integrated in our Cadence mixed signal design kit, “Virtuoso” IC6.1 [2]. A test chip is produced with our in house 0.13 micron BiCMOS technology, see Ref. [3]. As next step we will doing radiation tests according the european space agency (ESA) specifications, see Ref. [4], [5].

MEMS-based thermally-actuated image stabilizer for cellular phone camera

NASA Astrophysics Data System (ADS)

Lin, Chun-Ying; Chiou, Jin-Chern

2012-11-01

This work develops an image stabilizer (IS) that is fabricated using micro-electro-mechanical system (MEMS) technology and is designed to counteract the vibrations when human using cellular phone cameras. The proposed IS has dimensions of 8.8 × 8.8 × 0.3 mm3 and is strong enough to suspend an image sensor. The processes that is utilized to fabricate the IS includes inductive coupled plasma (ICP) processes, reactive ion etching (RIE) processes and the flip-chip bonding method. The IS is designed to enable the electrical signals from the suspended image sensor to be successfully emitted out using signal output beams, and the maximum actuating distance of the stage exceeds 24.835 µm when the driving current is 155 mA. Depending on integration of MEMS device and designed controller, the proposed IS can decrease the hand tremor by 72.5%.

Hybrid macro-micro fluidics system for a chip-based biosensor

NASA Astrophysics Data System (ADS)

Tamanaha, C. R.; Whitman, L. J.; Colton, R. J.

2002-03-01

We describe the engineering of a hybrid fluidics platform for a chip-based biosensor system that combines high-performance microfluidics components with powerful, yet compact, millimeter-scale pump and valve actuators. The microfluidics system includes channels, valveless diffuser-based pumps, and pinch-valves that are cast into a poly(dimethylsiloxane) (PDMS) membrane and packaged along with the sensor chip into a palm-sized plastic cartridge. The microfluidics are driven by pump and valve actuators contained in an external unit (with a volume ~30 cm3) that interfaces kinematically with the PDMS microelements on the cartridge. The pump actuator is a simple-lever, flexure-hinge displacement amplifier that increases the motion of a piezoelectric stack. The valve actuators are an array of cantilevers operated by shape memory alloy wires. All components can be fabricated without the need for complex lithography or micromachining, and can be used with fluids containing micron-sized particulates. Prototypes have been modeled and tested to ensure the delivery of microliter volumes of fluid and the even dispersion of reagents over the chip sensing elements. With this hybrid approach to the fluidics system, the biochemical assay benefits from the many advantages of microfluidics yet we avoid the complexity and unknown reliability of immature microactuator technologies.

Integrated Optoelectronic Position Sensor for Scanning Micromirrors.

PubMed

Cheng, Xiang; Sun, Xinglin; Liu, Yan; Zhu, Lijun; Zhang, Xiaoyang; Zhou, Liang; Xie, Huikai

2018-03-26

Scanning micromirrors have been used in a wide range of areas, but many of them do not have position sensing built in, which significantly limits their application space. This paper reports an integrated optoelectronic position sensor (iOE-PS) that can measure the linear displacement and tilting angle of electrothermal MEMS (Micro-electromechanical Systems) scanning mirrors. The iOE-PS integrates a laser diode and its driving circuits, a quadrant photo-detector (QPD) and its readout circuits, and a band-gap reference all on a single chip, and it has been fabricated in a standard 0.5 μm CMOS (Complementary Metal Oxide Semiconductor) process. The footprint of the iOE-PS chip is 5 mm × 5 mm. Each quadrant of the QPD has a photosensitive area of 500 µm × 500 µm and the spacing between adjacent quadrants is 500 μm. The iOE-PS chip is simply packaged underneath of an electrothermally-actuated MEMS mirror. Experimental results show that the iOE-PS has a linear response when the MEMS mirror plate moves vertically between 2.0 mm and 3.0 mm over the iOE-PS chip or scans from -5 to +5°. Such MEMS scanning mirrors integrated with the iOE-PS can greatly reduce the complexity and cost of the MEMS mirrors-enabled modules and systems.

Real-time label-free biosensing with integrated planar waveguide ring resonators

NASA Astrophysics Data System (ADS)

Sohlström, Hans; Gylfason, Kristinn B.; Hill, Daniel

2010-05-01

We review the use of planar integrated optical waveguide ring resonators for label free bio-sensing and present recent results from two European biosensor collaborations: SABIO and InTopSens. Planar waveguide ring resonators are attractive for label-free biosensing due to their small footprint, high Q-factors, and compatibility with on-chip optics and microfluidics. This enables integrated sensor arrays for compact labs-on-chip. One application of label-free sensor arrays is for point-of-care medical diagnostics. Bringing such powerful tools to the single medical practitioner is an important step towards personalized medicine, but requires addressing a number of issues: improving limit of detection, managing the influence of temperature, parallelization of the measurement for higher throughput and on-chip referencing, efficient light-coupling strategies to simplify alignment, and packaging of the optical chip and integration with microfluidics. From the SABIO project we report refractive index measurement and label-free biosensing in an 8-channel slotwaveguide ring resonator sensor array, within a compact cartridge with integrated microfluidics. The sensors show a volume sensing detection limit of 5 x 10-6 RIU and a surface sensing detection limit of 0.9 pg/mm2. From the InTopSens project we report early results on silicon-on-insulator racetrack resonators.

On-chip infrared sensors: redefining the benefits of scaling

NASA Astrophysics Data System (ADS)

Kita, Derek; Lin, Hongtao; Agarwal, Anu; Yadav, Anupama; Richardson, Kathleen; Luzinov, Igor; Gu, Tian; Hu, Juejun

2017-03-01

Infrared (IR) spectroscopy is widely recognized as a gold standard technique for chemical and biological analysis. Traditional IR spectroscopy relies on fragile bench-top instruments located in dedicated laboratory settings, and is thus not suitable for emerging field-deployed applications such as in-line industrial process control, environmental monitoring, and point-of-care diagnosis. Recent strides in photonic integration technologies provide a promising route towards enabling miniaturized, rugged platforms for IR spectroscopic analysis. It is therefore attempting to simply replace the bulky discrete optical elements used in conventional IR spectroscopy with their on-chip counterparts. This size down-scaling approach, however, cripples the system performance as both the sensitivity of spectroscopic sensors and spectral resolution of spectrometers scale with optical path length. In light of this challenge, we will discuss two novel photonic device designs uniquely capable of reaping performance benefits from microphotonic scaling. We leverage strong optical and thermal confinement in judiciously designed micro-cavities to circumvent the thermal diffusion and optical diffraction limits in conventional photothermal sensors and achieve a record 104 photothermal sensitivity enhancement. In the second example, an on-chip spectrometer design with the Fellgett's advantage is analyzed. The design enables sub-nm spectral resolution on a millimeter-sized, fully packaged chip without moving parts.

Induced Polarization Influences the Fundamental Forces in DNA Base Flipping

PubMed Central

2015-01-01

Base flipping in DNA is an important process involved in genomic repair and epigenetic control of gene expression. The driving forces for these processes are not fully understood, especially in the context of the underlying dynamics of the DNA and solvent effects. We studied double-stranded DNA oligomers that have been previously characterized by imino proton exchange NMR using both additive and polarizable force fields. Our results highlight the importance of induced polarization on the base flipping process, yielding near-quantitative agreement with experimental measurements of the equilibrium between the base-paired and flipped states. Further, these simulations allow us to quantify for the first time the energetic implications of polarization on the flipping pathway. Free energy barriers to base flipping are reduced by changes in dipole moments of both the flipped bases that favor solvation of the bases in the open state and water molecules adjacent to the flipping base. PMID:24976900

Fine-grained parallelism accelerating for RNA secondary structure prediction with pseudoknots based on FPGA.

PubMed

Xia, Fei; Jin, Guoqing

2014-06-01

PKNOTS is a most famous benchmark program and has been widely used to predict RNA secondary structure including pseudoknots. It adopts the standard four-dimensional (4D) dynamic programming (DP) method and is the basis of many variants and improved algorithms. Unfortunately, the O(N(6)) computing requirements and complicated data dependency greatly limits the usefulness of PKNOTS package with the explosion in gene database size. In this paper, we present a fine-grained parallel PKNOTS package and prototype system for accelerating RNA folding application based on FPGA chip. We adopted a series of storage optimization strategies to resolve the "Memory Wall" problem. We aggressively exploit parallel computing strategies to improve computational efficiency. We also propose several methods that collectively reduce the storage requirements for FPGA on-chip memory. To the best of our knowledge, our design is the first FPGA implementation for accelerating 4D DP problem for RNA folding application including pseudoknots. The experimental results show a factor of more than 50x average speedup over the PKNOTS-1.08 software running on a PC platform with Intel Core2 Q9400 Quad CPU for input RNA sequences. However, the power consumption of our FPGA accelerator is only about 50% of the general-purpose micro-processors.

Performance of the THS4302 and the Class V Radiation-Tolerant THS4304-SP Silicon Germanium Wideband Amplifiers at Extreme Temperatures

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Elbuluk, Malik; Hammoud, Ahmad; VanKeuls, Frederick W.

2009-01-01

This report discusses the performance of silicon germanium, wideband gain amplifiers under extreme temperatures. The investigated devices include Texas Instruments THS4304-SP and THS4302 amplifiers. Both chips are manufactured using the BiCom3 process based on silicon germanium technology along with silicon-on-insulator (SOI) buried oxide layers. The THS4304-SP device was chosen because it is a Class V radiation-tolerant (150 kRad, TID silicon), voltage-feedback operational amplifier designed for use in high-speed analog signal applications and is very desirable for NASA missions. It operates with a single 5 V power supply [1]. It comes in a 10-pin ceramic flatpack package, and it provides balanced inputs, low offset voltage and offset current, and high common mode rejection ratio. The fixed-gain THS4302 chip, which comes in a 16-pin leadless package, offers high bandwidth, high slew rate, low noise, and low distortion [2]. Such features have made the amplifier useful in a number of applications such as wideband signal processing, wireless transceivers, intermediate frequency (IF) amplifier, analog-to-digital converter (ADC) preamplifier, digital-to-analog converter (DAC) output buffer, measurement instrumentation, and medical and industrial imaging.