A short review on thermosonic flip chip bonding

NASA Astrophysics Data System (ADS)

Suppiah, Sarveshvaran; Ong, Nestor Rubio; Sauli, Zaliman; Sarukunaselan, Karunavani; Alcain, Jesselyn Barro; Shahimin, Mukhzeer Mohamad; Retnasamy, Vithyacharan

2017-09-01

This review is to study the evolution and key findings, critical technical challenges, solutions and bonding equipment of thermosonic flip chip bonding. Based on the review done, it was found that ultrasonic power, bonding time and force are the three main critical parameters need to be optimized in order to achieve sound and reliable bonding between the die and substrate. A close monitoring of the ultrasonic power helped to prevent over bonding phenomena on flexible substrate. Gold stud bumping is commonly used in thermosonic bonding compared to solder due to its better reliability obtained in the LED and optoelectronic packages. The review comprised short details on the available thermosonic bonding equipment in the semiconductor industry as well.

Laser-induced forward transfer for flip-chip packaging of single dies.

PubMed

Kaur, Kamal S; Van Steenberge, Geert

2015-03-20

Flip-chip (FC) packaging is a key technology for realizing high performance, ultra-miniaturized and high-density circuits in the micro-electronics industry. In this technique the chip and/or the substrate is bumped and the two are bonded via these conductive bumps. Many bumping techniques have been developed and intensively investigated since the introduction of the FC technology in 1960(1) such as stencil printing, stud bumping, evaporation and electroless/electroplating2. Despite the progress that these methods have made they all suffer from one or more than one drawbacks that need to be addressed such as cost, complex processing steps, high processing temperatures, manufacturing time and most importantly the lack of flexibility. In this paper, we demonstrate a simple and cost-effective laser-based bump forming technique known as Laser-induced Forward Transfer (LIFT)3. Using the LIFT technique a wide range of bump materials can be printed in a single-step with great flexibility, high speed and accuracy at RT. In addition, LIFT enables the bumping and bonding down to chip-scale, which is critical for fabricating ultra-miniature circuitry.

Bi-level multilayered microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2002-01-01

A bi-level, multilayered package with an integral window for housing a microelectronic device. The device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The multilayered package can be formed of a low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the window being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. The microelectronic device can be flip-chip bonded and oriented so that the light-sensitive side is optically accessible through the window. A second chip can be bonded to the backside of the first chip, with the second chip being wirebonded to the second level of the bi-level package. The result is a compact, low-profile package, having an integral window that can be hermetically-sealed.

Flip-chip fabrication of integrated micromirror arrays using a novel latching off-chip hinge mechanism

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper presents the design, fabrication, modeling, and testing of various arrays of cantilever micromirror devices integrated atop CMOS control electronics. The upper layers of the arrays are prefabricated in the MUMPs process and then flip-chip transferred to CMOS receiving modules using a novel latching off-chip hinge mechanism. This mechanism allows the micromirror arrays to be released, rotated off the edge of the host module and then bonded to the receiving module using a standard probe station. The hinge mechanism supports the arrays by tethers that are severed to free the arrays once bonded. The resulting devices are inherently planarized since the bottom of the first releasable MUMPs layer becomes the surface of the integrated mirror. The working devices are formed by mirror surfaces bonded to address electrodes fabricated above static memory cells on the CMOS module. These arrays demonstrate highly desirable features such as compatible address potentials, less than 2 nm of RMS roughness, approximately 1 micrometers of lateral position accuracy and the unique ability to metallize reflective surfaces without masking. Ultimately, the off-chip hinge mechanism enables very low-cost, simple, reliable, repeatable and accurate assembly of advanced MEMS and integrated microsystems without specialized equipment or complex procedures.

Vertical integration of array-type miniature interferometers at wafer level by using multistack anodic bonding

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Wiemer, Maik; Froemel, Joerg; Enderlein, Tom; Gessner, Thomas; Lullin, Justine; Bargiel, Sylwester; Passilly, Nicolas; Albero, Jorge; Gorecki, Christophe

2016-04-01

In this work, vertical integration of miniaturized array-type Mirau interferometers at wafer level by using multi-stack anodic bonding is presented. Mirau interferometer is suitable for MEMS metrology and for medical imaging according to its vertical-, lateral- resolutions and working distances. Miniaturized Mirau interferometer can be a promising candidate as a key component of an optical coherence tomography (OCT) system. The miniaturized array-type interferometer consists of a microlens doublet, a Si-based MEMS Z scanner, a spacer for focus-adjustment and a beam splitter. Therefore, bonding technologies which are suitable for heterogeneous substrates are of high interest and necessary for the integration of MEMS/MOEMS devices. Multi-stack anodic bonding, which meets the optical and mechanical requirements of the MOEMS device, is adopted to integrate the array-type interferometers. First, the spacer and the beam splitter are bonded, followed by bonding of the MEMS Z scanner. In the meanwhile, two microlenses, which are composed of Si and glass wafers, are anodically bonded to form a microlens doublet. Then, the microlens doublet is aligned and bonded with the scanner/spacer/beam splitter stack. The bonded array-type interferometer is a 7- wafer stack and the thickness is approximately 5mm. To separate such a thick wafer stack with various substrates, 2-step laser cutting is used to dice the bonded stack into Mirau chips. To simplify fabrication process of each component, electrical connections are created at the last step by mounting a Mirau chip onto a flip chip PCB instead of through wafer vias. Stability of Au/Ti films on the MEMS Z scanner after anodic bonding, laser cutting and flip chip bonding are discussed as well.

A novel miniaturized PCR multi-reactor array fabricated using flip-chip bonding techniques

NASA Astrophysics Data System (ADS)

Zou, Zhi-Qing; Chen, Xiang; Jin, Qing-Hui; Yang, Meng-Su; Zhao, Jian-Long

2005-08-01

This paper describes a novel miniaturized multi-chamber array capable of high throughput polymerase chain reaction (PCR). The structure of the proposed device is verified by using finite element analysis (FEA) to optimize the thermal performance, and then implemented on a glass-silicon substrate using a standard MEMS process and post-processing. Thermal analysis simulation and verification of each reactor cell is equipped with integrated Pt temperature sensors and heaters at the bottom of the reaction chamber for real-time accurate temperature sensing and control. The micro-chambers are thermally separated from each other, and can be controlled independently. The multi-chip array was packaged on a printed circuit board (PCB) substrate using a conductive polymer flip-chip bonding technique, which enables effective heat dissipation and suppresses thermal crosstalk between the chambers. The designed system has successfully demonstrated a temperature fluctuation of ±0.5 °C during thermal multiplexing of up to 2 × 2 chambers, a full speed of 30 min for 30 cycle PCR, as well as the capability of controlling each chamber digitally and independently.

Flip-chip integration of tilted VCSELs onto a silicon photonic integrated circuit.

PubMed

Lu, Huihui; Lee, Jun Su; Zhao, Yan; Scarcella, Carmelo; Cardile, Paolo; Daly, Aidan; Ortsiefer, Markus; Carroll, Lee; O'Brien, Peter

2016-07-25

In this article we describe a cost-effective approach for hybrid laser integration, in which vertical cavity surface emitting lasers (VCSELs) are passively-aligned and flip-chip bonded to a Si photonic integrated circuit (PIC), with a tilt-angle optimized for optical-insertion into standard grating-couplers. A tilt-angle of 10° is achieved by controlling the reflow of the solder ball deposition used for the electrical-contacting and mechanical-bonding of the VCSEL to the PIC. After flip-chip integration, the VCSEL-to-PIC insertion loss is -11.8 dB, indicating an excess coupling penalty of -5.9 dB, compared to Fibre-to-PIC coupling. Finite difference time domain simulations indicate that the penalty arises from the relatively poor match between the VCSEL mode and the grating-coupler.

Hybrid UV Imager Containing Face-Up AlGaN/GaN Photodiodes

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Pain, Bedabrata

2005-01-01

A proposed hybrid ultraviolet (UV) image sensor would comprise a planar membrane array of face-up AlGaN/GaN photodiodes integrated with a complementary metal oxide/semiconductor (CMOS) readout-circuit chip. Each pixel in the hybrid image sensor would contain a UV photodiode on the AlGaN/GaN membrane, metal oxide/semiconductor field-effect transistor (MOSFET) readout circuitry on the CMOS chip underneath the photodiode, and a metal via connection between the photodiode and the readout circuitry (see figure). The proposed sensor design would offer all the advantages of comparable prior CMOS active-pixel sensors and AlGaN UV detectors while overcoming some of the limitations of prior (AlGaN/sapphire)/CMOS hybrid image sensors that have been designed and fabricated according to the methodology of flip-chip integration. AlGaN is a nearly ideal UV-detector material because its bandgap is wide and adjustable and it offers the potential to attain extremely low dark current. Integration of AlGaN with CMOS is necessary because at present there are no practical means of realizing readout circuitry in the AlGaN/GaN material system, whereas the means of realizing readout circuitry in CMOS are well established. In one variant of the flip-chip approach to integration, an AlGaN chip on a sapphire substrate is inverted (flipped) and then bump-bonded to a CMOS readout circuit chip; this variant results in poor quantum efficiency. In another variant of the flip-chip approach, an AlGaN chip on a crystalline AlN substrate would be bonded to a CMOS readout circuit chip; this variant is expected to result in narrow spectral response, which would be undesirable in many applications. Two other major disadvantages of flip-chip integration are large pixel size (a consequence of the need to devote sufficient area to each bump bond) and severe restriction on the photodetector structure. The membrane array of AlGaN/GaN photodiodes and the CMOS readout circuit for the proposed image sensor would be fabricated separately.

Investigation of electromigration behavior in lead-free flip chip solder bumps

NASA Astrophysics Data System (ADS)

Kalkundri, Kaustubh Jayant

Packaging technology has also evolved over time in an effort to keep pace with the demanding requirements. Wirebond and flip chip packaging technologies have become extremely versatile and ubiquitous in catering to myriad applications due to their inherent potential. This research is restricted strictly to flip chip technology. This technology incorporates a process in which the bare chip is turned upside down, i.e., active face down, and is bonded through the I/O to the substrate, hence called flip chip. A solder interconnect that provides electrical connection between the chip and substrate is bumped on a processed silicon wafer prior to dicing for die-attach. The assembly is then reflow-soldered followed by the underfill process to provide the required encapsulation. The demand for smaller and lighter products has increased the number of I/Os without increasing the package sizes, thereby drastically reducing the size of the flip chip solder bumps and their pitch. Reliability assessment and verification of these devices has gained tremendous importance due to their shrinking size. To add to the complexity, changing material sets that are results of recently enacted lead-free solder legislations have raised some compatibility issues that are already being researched. In addition to materials and process related flip chip challenges such as solder-flux compatibility, Coefficient of Thermal Expansion (CTE) mismatch, underfill-flux compatibility and thermal management, flip chip packages are vulnerable to a comparatively newer challenge, namely electromigration observed in solder bumps. It is interesting to note that electromigration has come to the forefront of challenges only recently. It has been exacerbated by the reduction in bump cross-section due to the seemingly continuous shrinking in package size over time. The focus of this research was to understand the overall electromigration behavior in lead-free (SnAg) flip chip solder bumps. The objectives of the research were to comprehend the physics of failure mechanism in electromigration for lead-free solder bumps assembled in a flip chip ceramic package having thick copper under bump metallization and to estimate the unknown critical material parameters from Black's equation that describe failure due to electromigration. In addition, the intent was to verify the 'use condition reliability' by extrapolation from experimental conditions. The methodology adopted for this research was comprised of accelerated electromigration tests on SnAg flip chip solder bumps assembled on ceramic substrate with a thick copper under bump metallization. The experimental approach was comprised of elaborate measurement of the temperature of each sample by separate metallization resistance exhibiting positive resistance characteristics to overcome the variation in Joule heating. After conducting the constant current experiments and analyzing the failed samples, it was found that the primary electromigration failure mode observed was the dissolution of the thick copper under bump metallization in the solder, leading to a change in resistance. The lifetime data obtained from different experiments was solved simultaneously using a multiple regression approach to yield the unknown Black's equation parameters of current density exponent and activation energy. In addition to the implementation of a systematic failure analysis and data analysis procedure, it was also deduced that thermomigration due to the temperature gradient across the chip does impact the overall electromigration behavior. This research and the obtained results were significant in bridging the gap for an overall understanding of this critical failure mode observed in flip chip solder bumps. The measurement of each individual sample temperature instead of an average temperature enabled an accurate analysis for predicting the 'use condition reliability' of a comparable product. The obtained results and the conclusions can be used as potential inputs in future designs and newer generations of flip chip devices that might undergo aggressive scaling. This will enable these devices to retain their functionality during their intended useful life with minimal threat of failure due to the potent issue of electromigration. (Abstract shortened by UMI.)

Advanced processing of CdTe pixel radiation detectors

NASA Astrophysics Data System (ADS)

Gädda, A.; Winkler, A.; Ott, J.; Härkönen, J.; Karadzhinova-Ferrer, A.; Koponen, P.; Luukka, P.; Tikkanen, J.; Vähänen, S.

2017-12-01

We report a fabrication process of pixel detectors made of bulk cadmium telluride (CdTe) crystals. Prior to processing, the quality and defect density in CdTe material was characterized by infrared (IR) spectroscopy. The semiconductor detector and Flip-Chip (FC) interconnection processing was carried out in the clean room premises of Micronova Nanofabrication Centre in Espoo, Finland. The chip scale processes consist of the aluminum oxide (Al2O3) low temperature thermal Atomic Layer Deposition (ALD), titanium tungsten (TiW) metal sputtering depositions and an electroless Nickel growth. CdTe crystals with the size of 10×10×0.5 mm3 were patterned with several photo-lithography techniques. In this study, gold (Au) was chosen as the material for the wettable Under Bump Metalization (UBM) pads. Indium (In) based solder bumps were grown on PSI46dig read out chips (ROC) having 4160 pixels within an area of 1 cm2. CdTe sensor and ROC were hybridized using a low temperature flip-chip (FC) interconnection technique. The In-Au cold weld bonding connections were successfully connecting both elements. After the processing the detector packages were wire bonded into associated read out electronics. The pixel detectors were tested at the premises of Finnish Radiation Safety Authority (STUK). During the measurement campaign, the modules were tested by exposure to a 137Cs source of 1.5 TBq for 8 minutes. We detected at the room temperature a photopeak at 662 keV with about 2 % energy resolution.

Backside contacted field effect transistor array for extracellular signal recording.

PubMed

Ingebrandt, S; Yeung, C K; Staab, W; Zetterer, T; Offenhäusser, A

2003-04-01

A new approach to the design of field-effect transistor (FET) sensors and the use of these FETs in detecting extracellular electrophysiological recordings is reported. Backside contacts were engineered by deep reactive ion etching and a gas phase boron doping process of the holes using planar diffusion sources. The metal contacts were designed to fit on top of the bonding pads of a standard industrial 22-pin DIL (dual inline) chip carrier. To minimise contact resistance, the metal backside contacts of the chips were electroless plated with gold. The chips were mounted on top of the bonding pads using a standard flip-chip process and a fineplacer unit previously described. Rat embryonic myocytes were cultured on these new devices (effective growth area 6 x 6 mm(2)) in order to confirm their validity in electrophysiological recording. Copyright 2003 Elsevier Science B.V.

Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments.

PubMed

Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

2015-08-18

In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a "one-sensor-one-packaging_technology" concept. The second one uses a standard flip-chip bonding technique. The first sensor is a "floating-concept", capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not "floating" but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

Sealed symmetric multilayered microelectronic device package with integral windows

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2002-01-01

A sealed symmetric multilayered package with integral windows for housing one or more microelectronic devices. The devices can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The multilayered package can be formed of a low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the windows being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. The microelectronic devices can be flip-chip bonded and oriented so that the light-sensitive sides are optically accessible through the windows. The result is a compact, low-profile, sealed symmetric package, having integral windows that can be hermetically-sealed.

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

NASA Astrophysics Data System (ADS)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Bi-level microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2004-01-06

A package with an integral window for housing a microelectronic device. The integral window is bonded directly to the package without having a separate layer of adhesive material disposed in-between the window and the package. The device can be a semiconductor chip, CCD chip, CMOS chip, VCSEL chip, laser diode, MEMS device, or IMEMS device. The multilayered package can be formed of a LTCC or HTCC cofired ceramic material, with the integral window being simultaneously joined to the package during LTCC or HTCC processing. The microelectronic device can be flip-chip bonded so that the light-sensitive side is optically accessible through the window. The package has at least two levels of circuits for making electrical interconnections to a pair of microelectronic devices. The result is a compact, low-profile package having an integral window that is hermetically sealed to the package prior to mounting and interconnecting the microelectronic device(s).

Novel First-Level Interconnect Techniques for Flip Chip on MEMS Devices

PubMed Central

Sutanto, Jemmy; Anand, Sindhu; Patel, Chetan; Muthuswamy, Jit

2013-01-01

Flip-chip packaging is desirable for microelectro-mechanical systems (MEMS) devices because it reduces the overall package size and allows scaling up the number of MEMS chips through 3-D stacks. In this report, we demonstrate three novel techniques to create first-level interconnect (FLI) on MEMS: 1) Dip and attach technology for Ag epoxy; 2) Dispense technology for solder paste; 3) Dispense, pull, and attach technology (DPAT) for solder paste. The above techniques required no additional microfabrication steps, produced no visible surface contamination on the MEMS active structures, and generated high-aspect-ratio interconnects. The developed FLIs were successfully tested on MEMS moveable microelectrodes microfabricated by SUMMiTVTM process producing no apparent detrimental effect due to outgassing. The bumping processes were successfully applied on Al-deposited bond pads of 100 μm × 100 μm with an average bump height of 101.3 μm for Ag and 184.8 μm for solder (63Sn, 37Pb). DPAT for solder paste produced bumps with the aspect ratio of 1.8 or more. The average shear strengths of Ag and solder bumps were 78 MPa and 689 kPa, respectively. The electrical test on Ag bumps at 794 A/cm2 demonstrated reliable electrical interconnects with negligible resistance. These scalable FLI technologies are potentially useful for MEMS flip-chip packaging and 3-D stacking. PMID:24504168

Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments

PubMed Central

Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

2015-01-01

In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a “one-sensor-one-packaging_technology” concept. The second one uses a standard flip-chip bonding technique. The first sensor is a “floating-concept”, capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not “floating” but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA. PMID:26295235

Method of fabricating a microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2003-01-01

A method of fabricating a microelectronic device package with an integral window for providing optical access through an aperture in the package. The package is made of a multilayered insulating material, e.g., a low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC). The window is inserted in-between personalized layers of ceramic green tape during stackup and registration. Then, during baking and firing, the integral window is simultaneously bonded to the sintered ceramic layers of the densified package. Next, the microelectronic device is flip-chip bonded to cofired thick-film metallized traces on the package, where the light-sensitive side is optically accessible through the window. Finally, a cover lid is attached to the opposite side of the package. The result is a compact, low-profile package, flip-chip bonded, hermetically-sealed package having an integral window.

Fluxless Bonding Processes Using Silver-Indium System for High Temperature Electronics and Silver Flip-Chip Interconnect Technology

NASA Astrophysics Data System (ADS)

Wu, Yuan-Yun

In this dissertation, fluxless silver (Ag)-indium (In) binary system bonding and Ag solid-state bonding are used between different bonded pairs which have large thermal expansion coefficient (CTE) mismatch and flip-chip interconnect bonding application. In contrast to the conventional soldering process, fluxless bonding technique eliminates contamination and reliability problems caused by flux to fabricate high quality joints. There are two section are reported. In the first section, the reactions of Ag-In binary system are presented. In the second section, the high melting temperature, thermal and electrical conductivity joint materials bonding by either Ag-In binary system bonding or solid-state bonding processes for different bonded pairs and flip-chip application are designed, developed, and reported. Our group have studied Ag-In system for several years and developed the bonding processes successfully. However, the detailed reactions of Ag and In were seldom studied. To design a proper bonding structure, it is necessary to understand the reaction between Ag and In. The systematic experiments were performed to investigate these reactions. A 40 um Ag layer was electroplated on copper (Cu) substrates, followed by indium layers of 1, 3, 5, 10, and 15 um, respectively. The samples were annealed at 180 °C in 0.1 torr vacuum. For samples with In thickness less than 5 mum, the joint compositions are Ag2In only (1 um) or AgIn2, Ag2In, and Ag solid solution (Ag) after annealing. No indium is identified. For 10 and 15 um thick In samples, In covers almost over the entire sample surface after annealing. Later, an Ag layer was annealed at 450 °C for 3 hours to grow Ag grains, followed by plating 10 um In and annealing at 180 °C. By annealing Ag before plating In, more In is kept in the structure during annealing at 180 °C. Based on above results, for those designs with In thinner than 5 um, the Ag layer needs to be annealed, prior to In plating in order to make a successful bonding. In this section, we further studied the Ag-In bonding and solid-state bonding for different bonded pairs and flip-chip application. For the silicon (Si) and aluminum (Al) pair, Al has been used as the material for interconnect pads on the ICs. However, its high CTE (23 x 10-6/°C) and non-solderable property limit its applications in electronic products. To overcome these problems, a fluxless Ag-In bonding was developed. Al was deposited Cr/Cu layer on the surface by E-beam evaporator to make it solderable. 15 um of Ag and 8 um of In were sequentially plated on the Al substrates and 15 um of Ag was on Si chips with Cr/Au coating layer. The bonding was performed at 180 °C in 0.1 torr vacuum. The joint consists of Ag/(Ag)/Ag2In/(Ag)/Ag. The joint can achieve a solidus temperature of beyond 600 °C. From shear test results, the shear strengths far exceed the requirement in MIL-STD-883H. Al is not considered as a favorable substrate material because it is not solderable and has a high CTE. The new method presented in this thesis seems to have surmounted these two challenges. Since Ag2In is weak inside the joint in Ag-In system, an annealed process was used to convert the joints into Ag solid solution (Ag) to increase the joint strength and ductility. Two copper (Cu) substrates were bonded at 180 °C without flux. Bonding samples were annealed at 200 °C for 1,000 hours (first design) and at 250 °C for 350 hours (second design), respectively. Scanning electron microscope with energy dispersive X-ray (EDX) analysis results indicate that the joint of the first design is an alloy of mostly (Ag) with micron-size Ag2In and Ag3In regions, and that of second design has converted to a single (Ag) phase. Shear test results show that the breaking forces far exceed the requirement in MIL-STD-883H. The joint solidus temperatures are 600 °C and 800 °C for the first and second designs, respectively. The research results have shown that high-strength and high temperature joints can be manufactured using fluxless low temperature processes with the Ag-In system and are valuable in developing high temperature package. (Abstract shortened by UMI.).

Fabrication of Quench Condensed Thin Films Using an Integrated MEMS Fab on a Chip

NASA Astrophysics Data System (ADS)

Lally, Richard; Reeves, Jeremy; Stark, Thomas; Barrett, Lawrence; Bishop, David

Atomic calligraphy is a microelectromechanical systems (MEMS)-based dynamic stencil nanolithography technique. Integrating MEMS devices into a bonded stacked array of three die provides a unique platform for conducting quench condensed thin film mesoscopic experiments. The atomic calligraphy Fab on a Chip process incorporates metal film sources, electrostatic comb driven stencil plate, mass sensor, temperature sensor, and target surface into one multi-die assembly. Three separate die are created using the PolyMUMPs process and are flip-chip bonded together. A die containing joule heated sources must be prepared with metal for evaporation prior to assembly. A backside etch of the middle/central die exposes the moveable stencil plate allowing the flux to pass through the stencil from the source die to the target die. The chip assembly is mounted in a cryogenic system at ultra-high vacuum for depositing extremely thin films down to single layers of atoms across targeted electrodes. Experiments such as the effect of thin film alloys or added impurities on their superconductivity can be measured in situ with this process.

Defect Inspection of Flip Chip Solder Bumps Using an Ultrasonic Transducer

PubMed Central

Su, Lei; Shi, Tielin; Xu, Zhensong; Lu, Xiangning; Liao, Guanglan

2013-01-01

Surface mount technology has spurred a rapid decrease in the size of electronic packages, where solder bump inspection of surface mount packages is crucial in the electronics manufacturing industry. In this study we demonstrate the feasibility of using a 230 MHz ultrasonic transducer for nondestructive flip chip testing. The reflected time domain signal was captured when the transducer scanning the flip chip, and the image of the flip chip was generated by scanning acoustic microscopy. Normalized cross-correlation was used to locate the center of solder bumps for segmenting the flip chip image. Then five features were extracted from the signals and images. The support vector machine was adopted to process the five features for classification and recognition. The results show the feasibility of this approach with high recognition rate, proving that defect inspection of flip chip solder bumps using the ultrasonic transducer has high potential in microelectronics packaging.

Multilayered Microelectronic Device Package With An Integral Window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2004-10-26

A microelectronic package with an integral window mounted in a recessed lip for housing a microelectronic device. The device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The package can be formed of a low temperature co-fired ceramic (LTCC) or high temperature cofired ceramic (HTCC) multilayered material, with the integral window being simultaneously joined (e.g. co-fired) to the package body during LTCC or HTCC processing. The microelectronic device can be flip-chip bonded and oriented so that a light-sensitive side is optically accessible through the window. The result is a compact, low profile package, having an integral window mounted in a recessed lip, that can be hermetically sealed.

Adaptive Optoelectronic Eyes: Hybrid Sensor/Processor Architectures

DTIC Science & Technology

2006-11-13

corresponding calculated data. The width of the mirror stopband is proportional to the refractive index difference between the high and low index materials ...Silicon VLSI Neuron Unit Arrays 56 Development of a Single-Sided Flip-Chip Bonding Process 65 Development of High Refractive Index Diffractive Optical ...Elements (DOEs) 68 Development of High-Performance Antireflection Coatings for High Refractive Index DOEs 69 Design and Fabrication of Low Threshold

Evaluation of advanced microelectronic fluxless solder-bump contacts for hybrid microcircuits

NASA Technical Reports Server (NTRS)

Mandal, R. P.

1976-01-01

Technology for interconnecting monolithic integrated circuit chips with other components is investigated. The advantages and disadvantages of the current flip-chip approach as compared to other interconnection methods are outlined. A fluxless solder-bump contact technology is evaluated. Multiple solder-bump contacts were formed on silicon integrated circuit chips. The solder-bumps, comprised of a rigid nickel under layer and a compliant solder overlayer, were electroformed onto gold device pads with the aid of thick dry film photomasks. Different solder alloys and the use of conductive epoxy for bonding were explored. Fluxless solder-bump bond quality and reliability were evaluated by measuring the effects of centrifuge, thermal cycling, and high temperature storage on bond visual characteristics, bond electrical continuity, and bond shear tests. The applicability and suitability of this technology for hybrid microelectronic packaging is discussed.

Method to Improve Indium Bump Bonding via Indium Oxide Removal Using a Multi-Step Plasma Process

NASA Technical Reports Server (NTRS)

Dickie, Matthew R. (Inventor); Nikzad, Shouleh (Inventor); Greer, H. Frank (Inventor); Jones, Todd J. (Inventor); Vasquez, Richard P. (Inventor); Hoenk, Michael E. (Inventor)

2012-01-01

A process for removing indium oxide from indium bumps in a flip-chip structure to reduce contact resistance, by a multi-step plasma treatment. A first plasma treatment of the indium bumps with an argon, methane and hydrogen plasma reduces indium oxide, and a second plasma treatment with an argon and hydrogen plasma removes residual organics. The multi-step plasma process for removing indium oxide from the indium bumps is more effective in reducing the oxide, and yet does not require the use of halogens, does not change the bump morphology, does not attack the bond pad material or under-bump metallization layers, and creates no new mechanisms for open circuits.

An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging.

PubMed

Wygant, Ira O; Jamal, Nafis S; Lee, Hyunjoo J; Nikoozadeh, Amin; Oralkan, Omer; Karaman, Mustafa; Khuri-Yakub, Butrus T

2009-10-01

State-of-the-art 3-D medical ultrasound imaging requires transmitting and receiving ultrasound using a 2-D array of ultrasound transducers with hundreds or thousands of elements. A tight combination of the transducer array with integrated circuitry eliminates bulky cables connecting the elements of the transducer array to a separate system of electronics. Furthermore, preamplifiers located close to the array can lead to improved receive sensitivity. A combined IC and transducer array can lead to a portable, high-performance, and inexpensive 3-D ultrasound imaging system. This paper presents an IC flip-chip bonded to a 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array for 3-D ultrasound imaging. The IC includes a transmit beamformer that generates 25-V unipolar pulses with programmable focusing delays to 224 of the 256 transducer elements. One-shot circuits allow adjustment of the pulse widths for different ultrasound transducer center frequencies. For receiving reflected ultrasound signals, the IC uses the 32-elements along the array diagonals. The IC provides each receiving element with a low-noise 25-MHz-bandwidth transimpedance amplifier. Using a field-programmable gate array (FPGA) clocked at 100 MHz to operate the IC, the IC generated properly timed transmit pulses with 5-ns accuracy. With the IC flip-chip bonded to a CMUT array, we show that the IC can produce steered and focused ultrasound beams. We present 2-D and 3-D images of a wire phantom and 2-D orthogonal cross-sectional images (Bscans) of a latex heart phantom.

Evaluation of the thermal conductance of flip-chip bonding structure utilizing the measurement based on Fourier's law of heat conduction at steady-state

NASA Astrophysics Data System (ADS)

Wu, Chia-Yu; Huang, Yin-Hsien; Wu, Hsin-Han; Hsieh, Tsung-Eong

2018-06-01

Fourier's law of heat conduction at steady-state was adopted to establish a measurement method utilizing platinum (Pt) thin-film electrodes as the heater and the temperature sensor. The thermal conductivities (κ's) of Pyrex glass, an epoxy resin and a commercial underfill for flip-chip devices were measured and a good agreement with previously reported values was obtained. The thermal boundary resistances (RTBR's) of Pt/sample interfaces were also extracted for discussing their influence on the thermal conduction of samples. Afterward, the flip-chip samples with 2×2 solder joint array utilizing Si wafers as the die and the substrate, without and with the underfills, were prepared and their thermal conductance were measured. For the sample without underfill, the air presenting in the gap of die and the substrate led to the poor thermal conductance of sample. With the insertion of underfills, the thermal conductance of flip-chip samples improved. The resistance to heat transfer across Si/underfill interfaces was also suppressed and to promote the thermal conductance of samples. The thermal properties of underfill and RTBR at Si/underfill interface were further implanted in the calculation of thermal conductance of flip-chip samples containing various solder joint arrays. The increasing number of solder joints diminished the influence of thermal conduction of underfill and RTBR of Si/underfill interface on the thermal conductance of samples. The insertion of underfill with high-κ value might promote the heat conductance of samples containing low-density solder joint arrays; however, it became insignificant in improving the heat conductance of samples containing high-density solder joint arrays.

Fluxless flip-chip bonding using a lead-free solder bumping technique

NASA Astrophysics Data System (ADS)

Hansen, K.; Kousar, S.; Pitzl, D.; Arab, S.

2017-09-01

With the LHC exceeding the nominal instantaneous luminosity, the current barrel pixel detector (BPIX) of the CMS experiment at CERN will reach its performance limits and undergo significant radiation damage. In order to improve detector performance in high luminosity conditions, the entire BPIX is replaced with an upgraded version containing an additional detection layer. Half of the modules comprising this additional layer are produced at DESY using fluxless and lead-free bumping and bonding techniques. Sequential solder-jetting technique is utilized to wet 40-μm SAC305 solder spheres on the silicon-sensor pads with electroless Ni, Pd and immersion Au (ENEPIG) under-bump metallization (UBM). The bumped sensors are flip-chip assembled with readout chips (ROCs) and then reflowed using a flux-less bonding facility. The challenges for jetting low solder volume have been analyzed and will be presented in this paper. An average speed of 3.4 balls per second is obtained to jet about 67 thousand solder balls on a single chip. On average, 7 modules have been produced per week. The bump-bond quality is evaluated in terms of electrical and mechanical properties. The peak-bump resistance is about 17.5 mΩ. The cross-section study revealed different types of intermetallic compounds (IMC) as a result of interfacial reactions between UBM and solder material. The effect of crystalline phases on the mechanical properties of the joint is discussed. The mean shear strength per bump after the final module reflow is about 16 cN. The results and sources of yield loss of module production are reported. The achieved yield is 95%.

Microfabricated Electrical Connector for Atomic Force Microscopy Probes with Integrated Sensor/Actuator

NASA Astrophysics Data System (ADS)

Akiyama, Terunobu; Staufer, Urs; Rooij, Nico F. de

2002-06-01

A microfabricated, electrical connector is proposed for facilitating the mounting of atomic force microscopy (AFM) probes, which have an integrated sensor and/or actuator. Only a base chip, which acts as a socket, is permanently fixed onto a printed circuit board and electronically connected by standard wire bonding. The AFM chip, the “plug”, is flipped onto the base chip and pressed from the backside by a spring. Electrical contact with the eventual stress sensors, capacitive or piezoelectric sensor/actuators, is provided by contact bumps. These bumps of about 8 μm height are placed onto the base chip. They touch the pads on the AFM chip that were originally foreseen to be for wire bonding and thus provide the electrical contact. This connector schema was successfully used to register AFM images with piezoresistive cantilevers.

Detection of solder bump defects on a flip chip using vibration analysis

NASA Astrophysics Data System (ADS)

Liu, Junchao; Shi, Tielin; Xia, Qi; Liao, Guanglan

2012-03-01

Flip chips are widely used in microelectronics packaging owing to the high demand of integration in IC fabrication. Solder bump defects on flip chips are difficult to detect, because the solder bumps are obscured by the chip and substrate. In this paper a nondestructive detection method combining ultrasonic excitation with vibration analysis is presented for detecting missing solder bumps, which is a typical defect in flip chip packaging. The flip chip analytical model is revised by considering the influence of spring mass on mechanical energy of the system. This revised model is then applied to estimate the flip chip resonance frequencies. We use an integrated signal generator and power amplifier together with an air-coupled ultrasonic transducer to excite the flip chips. The vibrations are measured by a laser scanning vibrometer to detect the resonance frequencies. A sensitivity coefficient is proposed to select the sensitive resonance frequency order for defect detection. Finite element simulation is also implemented for further investigation. The results of analytical computation, experiment, and simulation prove the efficacy of the revised flip chip analytical model and verify the effectiveness of this detection method. Therefore, it may provide a guide for the improvement and innovation of the flip chip on-line inspection systems.

Molded underfill (MUF) encapsulation for flip-chip package: A numerical investigation

NASA Astrophysics Data System (ADS)

Azmi, M. A.; Abdullah, M. K.; Abdullah, M. Z.; Ariff, Z. M.; Saad, Abdullah Aziz; Hamid, M. F.; Ismail, M. A.

2017-07-01

This paper presents the numerical simulation of epoxy molding compound (EMC) filling in multi flip-chip packages during encapsulation process. The empty and a group flip chip packages were considered in the mold cavity in order to study the flow profile of the EMC. SOLIDWORKS software was used for three-dimensional modeling and it was incorporated into fluid analysis software namely as ANSYS FLUENT. The volume of fluid (VOF) technique was used for capturing the flow front profiles and Power Law model was applied for its rheology model. The numerical result are compared and discussed with previous experimental and it was shown a good conformity for model validation. The prediction of flow front was observed and analyzed at different filling time. The possibility and visual of void formation in the package is captured and the number of flip-chip is one factor that contributed to the void formation.

Flip-chip light emitting diode with resonant optical microcavity

DOEpatents

Gee, James M.; Bogart, Katherine H.A.; Fischer, Arthur J.

2005-11-29

A flip-chip light emitting diode with enhanced efficiency. The device structure employs a microcavity structure in a flip-chip configuration. The microcavity enhances the light emission in vertical modes, which are readily extracted from the device. Most of the rest of the light is emitted into waveguided lateral modes. Flip-chip configuration is advantageous for light emitting diodes (LEDs) grown on dielectric substrates (e.g., gallium nitride LEDs grown on sapphire substrates) in general due to better thermal dissipation and lower series resistance. Flip-chip configuration is advantageous for microcavity LEDs in particular because (a) one of the reflectors is a high-reflectivity metal ohmic contact that is already part of the flip-chip configuration, and (b) current conduction is only required through a single distributed Bragg reflector. Some of the waveguided lateral modes can also be extracted with angled sidewalls used for the interdigitated contacts in the flip-chip configuration.

Optimization of Indium Bump Morphology for Improved Flip Chip Devices

NASA Technical Reports Server (NTRS)

Jones, Todd J.; Nikzad, Shouleh; Cunningham, Thomas J.; Blazejewski, Edward; Dickie, Matthew R.; Hoenk, Michael E.; Greer, Harold F.

2011-01-01

Flip-chip hybridization, also known as bump bonding, is a packaging technique for microelectronic devices that directly connects an active element or detector to a substrate readout face-to-face, eliminating the need for wire bonding. In order to make conductive links between the two parts, a solder material is used between the bond pads on each side. Solder bumps, composed of indium metal, are typically deposited by thermal evaporation onto the active regions of the device and substrate. While indium bump technology has been a part of the electronic interconnect process field for many years and has been extensively employed in the infrared imager industry, obtaining a reliable, high-yield process for high-density patterns of bumps can be quite difficult. Under the right conditions, a moderate hydrogen plasma exposure can raise the temperature of the indium bump to the point where it can flow. This flow can result in a desirable shape where indium will efficiently wet the metal contact pad to provide good electrical contact to the underlying readout or imager circuit. However, it is extremely important to carefully control this process as the intensity of the hydrogen plasma treatment dramatically affects the indium bump morphology. To ensure the fine-tuning of this reflow process, it is necessary to have realtime feedback on the status of the bumps. With an appropriately placed viewport in a plasma chamber, one can image a small field (a square of approximately 5 millimeters on each side) of the bumps (10-20 microns in size) during the hydrogen plasma reflow process. By monitoring the shape of the bumps in real time using a video camera mounted to a telescoping 12 magnifying zoom lens and associated optical elements, an engineer can precisely determine when the reflow of the bumps has occurred, and can shut off the plasma before evaporation or de-wetting takes place.

Identifying Professional Competencies of the Flip-Chip Packaging Engineer in Taiwan

ERIC Educational Resources Information Center

Guu, Y. H.; Lin, Kuen-Yi; Lee, Lung-Sheng

2014-01-01

This study employed a literature review, expert interviews, and a questionnaire survey to construct a set of two-tier competencies for a flip-chip packaging engineer. The fuzzy Delphi questionnaire was sent to 12 flip-chip engineering experts to identify professional competencies that a flip-chip packaging engineer must have. Four competencies,…

Platform technologies for hybrid optoelectronic integration and packaging

NASA Astrophysics Data System (ADS)

Datta, Madhumita

In order to bring fiber-optics closer to individual home and business services, the optical network components have to be inexpensive and reliable. Integration and packaging of optoelectronic devices holds the key to high-volume low-cost component manufacturing. The goal of this dissertation is to propose, study, and demonstrate various ways to integrate optoelectronic devices on a packaging platform to implement cost-effective, functional optical modules. Two types of hybrid integration techniques have been proposed: flip-chip solder bump bonding for high-density two-dimensional array packaging of surface-emitting devices, and solder preform bonding for fiber-coupled edge-emitting semiconductor devices. For flip-chip solder bump bonding, we developed a simple, inexpensive remetallization process called "electroless plating", which converts the aluminum bond pads of foundry-made complementary metal oxide semiconductor (CMOS) chips into solder-bondable and wire-bondable gold surfaces. We have applied for a patent on this remetallization technique. For fiber-pigtailed edge-emitting laser modules, we have studied the coupling characteristics of different types of lensed single-mode fibers including semispherically lensed fiber, cylindrically lensed fiber and conically lensed fiber. We have experimentally demonstrated 66% coupling efficiency with semispherically lensed fiber and 50% efficiency with conically lensed fibers. We have proposed and designed a packaging platform on which lensed fibers can be actively aligned to a laser and solder-attached reliably to the platform so that the alignment is retained. We have designed thin-film nichrome heaters on fused quartz platforms as local heat source to facilitate on-board solder alignment and attachment of fiber. The thermal performance of the heaters was simulated using finite element analysis tool ANSYS prior to fabrication. Using the heater's reworkability advantage, we have estimated the shift of the fiber due to solder shrinkage and introduced a pre-correction in the alignment process to restore optimum coupling efficiency close to 50% with conically lensed fibers. We have applied for a patent on this unique active alignment method through the University of Maryland's Technology Commercialization Office. Although we have mostly concentrated on active alignment platforms, we have proposed the idea of combining the passive alignment advantages of silicon optical benches to the on-board heater-assisted active alignment technique. This passive-active alignment process has the potential of cost-effective array packaging of edge-emitting devices.

Ultra-compact 32 × 32 strictly-non-blocking Si-wire optical switch with fan-out LGA interposer.

PubMed

Tanizawa, Ken; Suzuki, Keijiro; Toyama, Munehiro; Ohtsuka, Minoru; Yokoyama, Nobuyuki; Matsumaro, Kazuyuki; Seki, Miyoshi; Koshino, Keiji; Sugaya, Toshio; Suda, Satoshi; Cong, Guangwei; Kimura, Toshio; Ikeda, Kazuhiro; Namiki, Shu; Kawashima, Hitoshi

2015-06-29

We demonstrate a 32 × 32 path-independent-insertion-loss optical path switch that integrates 1024 thermooptic Mach-Zehnder switches and 961 intersections on a small, 11 × 25 mm2 die. The switch is fabricated on a 300-mm-diameter silicon-on-insulator wafer by a complementary metal-oxide semiconductor-compatible process with advanced ArF immersion lithography. For reliable electrical packaging, the switch chip is flip-chip bonded to a ceramic interposer that arranges the electrodes in a 0.5-mm pitch land grid array. The on-chip loss is measured to be 15.8 ± 1.0 dB, and successful switching is demonstrated for digital-coherent 43-Gb/s QPSK signals. The total crosstalk of the switch is estimated to be less than -20 dB at the center wavelength of 1545 nm. The bandwidth narrowing caused by dimensional errors that arise during fabrication is discussed.

Physics-based process modeling, reliability prediction, and design guidelines for flip-chip devices

NASA Astrophysics Data System (ADS)

Michaelides, Stylianos

Flip Chip on Board (FCOB) and Chip-Scale Packages (CSPs) are relatively new technologies that are being increasingly used in the electronic packaging industry. Compared to the more widely used face-up wirebonding and TAB technologies, flip-chips and most CSPs provide the shortest possible leads, lower inductance, higher frequency, better noise control, higher density, greater input/output (I/O), smaller device footprint and lower profile. However, due to the short history and due to the introduction of several new electronic materials, designs, and processing conditions, very limited work has been done to understand the role of material, geometry, and processing parameters on the reliability of flip-chip devices. Also, with the ever-increasing complexity of semiconductor packages and with the continued reduction in time to market, it is too costly to wait until the later stages of design and testing to discover that the reliability is not satisfactory. The objective of the research is to develop integrated process-reliability models that will take into consideration the mechanics of assembly processes to be able to determine the reliability of face-down devices under thermal cycling and long-term temperature dwelling. The models incorporate the time and temperature-dependent constitutive behavior of various materials in the assembly to be able to predict failure modes such as die cracking and solder cracking. In addition, the models account for process-induced defects and macro-micro features of the assembly. Creep-fatigue and continuum-damage mechanics models for the solder interconnects and fracture-mechanics models for the die have been used to determine the reliability of the devices. The results predicted by the models have been successfully validated against experimental data. The validated models have been used to develop qualification and test procedures for implantable medical devices. In addition, the research has helped develop innovative face-down devices without the underfill, based on the thorough understanding of the failure modes. Also, practical design guidelines for material, geometry and process parameters for reliable flip-chip devices have been developed.

Flexible packaging of solid-state integrated circuit chips with elastomeric microfluidics

PubMed Central

Zhang, Bowei; Dong, Quan; Korman, Can E.; Li, Zhenyu; Zaghloul, Mona E.

2013-01-01

A flexible technology is proposed to integrate smart electronics and microfluidics all embedded in an elastomer package. The microfluidic channels are used to deliver both liquid samples and liquid metals to the integrated circuits (ICs). The liquid metals are used to realize electrical interconnects to the IC chip. This avoids the traditional IC packaging challenges, such as wire-bonding and flip-chip bonding, which are not compatible with current microfluidic technologies. As a demonstration we integrated a CMOS magnetic sensor chip and associate microfluidic channels on a polydimethylsiloxane (PDMS) substrate that allows precise delivery of small liquid samples to the sensor. Furthermore, the packaged system is fully functional under bending curvature radius of one centimetre and uniaxial strain of 15%. The flexible integration of solid-state ICs with microfluidics enables compact flexible electronic and lab-on-a-chip systems, which hold great potential for wearable health monitoring, point-of-care diagnostics and environmental sensing among many other applications.

Mean-time-to-failure study of flip chip solder joints on Cu/Ni(V)/Al thin-film under-bump-metallization

NASA Astrophysics Data System (ADS)

Choi, W. J.; Yeh, E. C. C.; Tu, K. N.

2003-11-01

Electromigration of eutectic SnPb flip chip solder joints and their mean-time-to-failure (MTTF) have been studied in the temperature range of 100 to 140 °C with current densities of 1.9 to 2.75×104 A/cm2. In these joints, the under-bump-metallization (UBM) on the chip side is a multilayer thin film of Al/Ni(V)/Cu, and the metallic bond-pad on the substrate side is a very thick, electroless Ni layer covered with 30 nm of Au. When stressed at the higher current densities, the MTTF was found to decrease much faster than what is expected from the published Black's equation. The failure occurred by interfacial void propagation at the cathode side, and it is due to current crowding near the contact interface between the solder bump and the thin-film UBM. The current crowding is confirmed by a simulation of current distribution in the solder joint. Besides the interfacial void formation, the intermetallic compounds formed on the UBM as well as the Ni(V) film in the UBM have been found to dissolve completely into the solder bump during electromigration. Therefore, the electromigation failure is a combination of the interfacial void formation and the loss of UBM. Similar findings in eutectic SnAgCu flip chip solder joints have also been obtained and compared.

276 nm Substrate-Free Flip-Chip AlGaN Light-Emitting Diodes

NASA Astrophysics Data System (ADS)

Hwang, Seongmo; Morgan, Daniel; Kesler, Amanda; Lachab, Mohamed; Zhang, Bin; Heidari, Ahmad; Nazir, Haseeb; Ahmad, Iftikhar; Dion, Joe; Fareed, Qhalid; Adivarahan, Vinod; Islam, Monirul; Khan, Asif

2011-03-01

Lateral-conduction, substrate-free flip-chip (SFFC) light-emitting diodes (LEDs) with peak emission at 276 nm are demonstrated for the first time. The AlGaN multiple quantum well LED structures were grown by metal-organic chemical vapor deposition (MOCVD) on thick-AlN laterally overgrown on sapphire substrates. To fabricate the SFFC LEDs, a newly-developed laser-assisted ablation process was employed to separate the substrate from the LED chips. The chips had physical dimensions of 1100×900 µm2, and were comprised of four devices each with a 100×100 µm2 junction area. Electrical and optical characterization of the devices revealed no noticeable degradation to their performance due to the laser-lift-off process.

Microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2002-01-01

An apparatus for packaging of microelectronic devices, including an integral window. The microelectronic device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The package can include a cofired ceramic frame or body. The package can have an internal stepped structure made of one or more plates, with apertures, which are patterned with metallized conductive circuit traces. The microelectronic device can be flip-chip bonded on the plate to these traces, and oriented so that the light-sensitive side is optically accessible through the window. A cover lid can be attached to the opposite side of the package. The result is a compact, low-profile package, having an integral window that can be hermetically-sealed. The package body can be formed by low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the window being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. Multiple chips can be located within a single package. The cover lid can include a window. The apparatus is particularly suited for packaging of MEMS devices, since the number of handling steps is greatly reduced, thereby reducing the potential for contamination.

High performance low cost interconnections for flip chip attachment with electrically conductive adhesive. Final report

DOE Office of Scientific and Technical Information (OSTI.GOV)

NONE

1998-05-01

This final report is a compilation of final reports from each of the groups participating in the program. The main three groups involved in this effort are the Thomas J. Watson Research Center of IBM Corporation in Yorktown Heights, New York, Assembly Process Design of IBM Corporation in Endicott, New York, and SMT Laboratory of Universal Instruments Corporation in Binghamton, New York. The group at the research center focused on the conductive adhesive materials development and characterization. The group in process development focused on processing of the Polymer-Metal-Solvent Paste (PMSP) to form conductive adhesive bumps, formation of the Polymer-Metal Compositemore » (PMC) on semiconductor devices and study of the bonding process to circuitized organic carriers, and the long term durability and reliability of joints formed using the process. The group at Universal Instruments focused on development of an equipment set and bonding parameters for the equipment to produce bond assembly tooling. Reports of each of these individual groups are presented here reviewing their technical efforts and achievements.« less

PbS-PbSe IR detector arrays

NASA Technical Reports Server (NTRS)

Barrett, John R. (Inventor)

1986-01-01

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chipping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

The rectenna design on contact lens for wireless powering of the active intraocular pressure monitoring system.

PubMed

Cheng, H W; Jeng, B M; Chen, C Y; Huang, H Y; Chiou, J C; Luo, C H

2013-01-01

This paper proposed a wireless power harvesting system with micro-electro-mechanical-systems (MEMS) fabrication for noninvasive intraocular pressure (IOP) measurement on soft contact lens substructure. The power harvesting IC consists of a loop antenna, an impedance matching network and a rectifier. The proposed IC has been designed and fabricated by CMOS 0.18 um process that operates at the ISM band of 5.8 GHz. The antenna and the power harvesting IC would be bonded together by using flip chip bonding technologies without extra wire interference. The circuit utilized an impedance transformation circuit to boost the input RF signal that improves the circuit performance. The proposed design achieves an RF-to-DC conversion efficiency of 35% at 5.8 GHz.

Monolithic integration of a silica AWG and Ge photodiodes on Si photonic platform for one-chip WDM receiver.

PubMed

Nishi, Hidetaka; Tsuchizawa, Tai; Kou, Rai; Shinojima, Hiroyuki; Yamada, Takashi; Kimura, Hideaki; Ishikawa, Yasuhiko; Wada, Kazumi; Yamada, Koji

2012-04-09

On the silicon (Si) photonic platform, we monolithically integrated a silica-based arrayed-waveguide grating (AWG) and germanium (Ge) photodiodes (PDs) using low-temperature fabrication technology. We confirmed demultiplexing by the AWG, optical-electrical signal conversion by Ge PDs, and high-speed signal detection at all channels. In addition, we mounted a multichannel transimpedance amplifier/limiting amplifier (TIA/LA) circuit on the fabricated AWG-PD device using flip-chip bonding technology. The results show the promising potential of our Si photonic platform as a photonics-electronics convergence.

High-frequency ultrasonic wire bonding systems

PubMed

Tsujino; Yoshihara; Sano; Ihara

2000-03-01

The vibration characteristics of longitudinal-complex transverse vibration systems with multiple resonance frequencies of 350-980 kHz for ultrasonic wire bonding of IC, LSI or electronic devices were studied. The complex vibration systems can be applied for direct welding of semiconductor tips (face-down bonding, flip-chip bonding) and packaging of electronic devices. A longitudinal-complex transverse vibration bonding system consists of a complex transverse vibration rod, two driving longitudinal transducers 7.0 mm in diameter and a transverse vibration welding tip. The vibration distributions along ceramic and stainless-steel welding tips were measured at up to 980 kHz. A high-frequency vibration system with a height of 20.7 mm and a weight of less than 15 g was obtained.

Vertically Integrated MEMS SOI Composite Porous Silicon-Crystalline Silicon Cantilever-Array Sensors: Concept for Continuous Sensing of Explosives and Warfare Agents

NASA Astrophysics Data System (ADS)

Stolyarova, Sara; Shemesh, Ariel; Aharon, Oren; Cohen, Omer; Gal, Lior; Eichen, Yoav; Nemirovsky, Yael

This study focuses on arrays of cantilevers made of crystalline silicon (c-Si), using SOI wafers as the starting material and using bulk micromachining. The arrays are subsequently transformed into composite porous silicon-crystalline silicon cantilevers, using a unique vapor phase process tailored for providing a thin surface layer of porous silicon on one side only. This results in asymmetric cantilever arrays, with one side providing nano-structured porous large surface, which can be further coated with polymers, thus providing additional sensing capabilities and enhanced sensing. The c-Si cantilevers are vertically integrated with a bottom silicon die with electrodes allowing electrostatic actuation. Flip Chip bonding is used for the vertical integration. The readout is provided by a sensitive Capacitance to Digital Converter. The fabrication, processing and characterization results are reported. The reported study is aimed towards achieving miniature cantilever chips with integrated readout for sensing explosives and chemical warfare agents in the field.

AIN-Based Packaging for SiC High-Temperature Electronics

NASA Technical Reports Server (NTRS)

Savrun, Ender

2004-01-01

Packaging made primarily of aluminum nitride has been developed to enclose silicon carbide-based integrated circuits (ICs), including circuits containing SiC-based power diodes, that are capable of operation under conditions more severe than can be withstood by silicon-based integrated circuits. A major objective of this development was to enable packaged SiC electronic circuits to operate continuously at temperatures up to 500 C. AlN-packaged SiC electronic circuits have commercial potential for incorporation into high-power electronic equipment and into sensors that must withstand high temperatures and/or high pressures in diverse applications that include exploration in outer space, well logging, and monitoring of nuclear power systems. This packaging embodies concepts drawn from flip-chip packaging of silicon-based integrated circuits. One or more SiC-based circuit chips are mounted on an aluminum nitride package substrate or sandwiched between two such substrates. Intimate electrical connections between metal conductors on the chip(s) and the metal conductors on external circuits are made by direct bonding to interconnections on the package substrate(s) and/or by use of holes through the package substrate(s). This approach eliminates the need for wire bonds, which have been the most vulnerable links in conventional electronic circuitry in hostile environments. Moreover, the elimination of wire bonds makes it possible to pack chips more densely than was previously possible.

Dose-dependent X-ray measurements using a 64×64 hybrid GaAs pixel detector with photon counting

NASA Astrophysics Data System (ADS)

Schwarz, C.; Campbell, M.; Goeppert, R.; Ludwig, J.; Mikulec, B.; Rogalla, M.; Runge, K.; Soeldner-Rembold, A.; Smith, K. M.; Snoeys, W.; Watt, J.

2001-03-01

New developments in medical imaging head towards semiconductor detectors flip-chip bonded to CMOS readout chips. In this work, detectors fabricated on SI-GaAs bulk material were bonded to Photon Counting Chips. This PCC consists of a matrix of 64×64 identical square pixels (170 μm×170 μm) with a 15-bit counter in each cell. We investigated the imaging properties of these detector systems under exposure of a dental X-ray tube. First, a dose calibration of the X-ray tube was performed. Fixed pattern noise in flood exposure images was determined for a fixed dose and an image correction method, which uses a gain map, was applied. For characterising the imaging properties, the signal-to-noise ratio (SNR) was calculated as function of exposure dose. Finally, the dynamic range of the system was estimated. Developed in the framework of the MEDIPIX collaboration: CERN, Universities of Freiburg, Glasgow, Naples and Pisa.

Single level microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2003-12-09

A package with an integral window for housing a microelectronic device. The integral window is bonded directly to the package without having a separate layer of adhesive material disposed in-between the window and the package. The device can be a semiconductor chip, CCD chip, CMOS chip, VCSEL chip, laser diode, MEMS device, or IMEMS device. The package can be formed of a multilayered LTCC or HTCC cofired ceramic material, with the integral window being simultaneously joined to the package during cofiring. The microelectronic device can be flip-chip interconnected so that the light-sensitive side is optically accessible through the window. A glob-top encapsulant or protective cover can be used to protect the microelectronic device and electrical interconnections. The result is a compact, low profile package having an integral window that is hermetically sealed to the package prior to mounting and interconnecting the microelectronic device.

Development and Industrialization of InGaN/GaN LEDs on Patterned Sapphire Substrates for Low Cost Emitter Architecture

DOE Office of Scientific and Technical Information (OSTI.GOV)

Flemish, Joseph; Soer, Wouter

2015-11-30

Patterned sapphire substrate (PSS) technology has proven to be an effective approach to improve efficacy and reduce cost of light-emitting diodes (LEDs). The volume emission from the transparent substrate leads to high package efficiency, while the simple and robust architecture of PSS-based LEDs enables low cost. PSS substrates have gained wide use in mid-power LEDs over the past years. In this project, Lumileds has developed and industrialized PSS and epitaxy technology for high- power flip-chip LEDs to bring these benefits to a broader range of applications and accelerate the adoption of energy-efficient solid-state lighting (SSL). PSS geometries were designed formore » highly efficient light extraction in a flip-chip architecture and high-volume manufacturability, and corresponding sapphire patterning and epitaxy manufacturing processes were integrally developed. Concurrently, device and package architectures were developed to take advantage of the PSS flip-chip die in different types of products that meet application needs. The developed PSS and epitaxy technology has been fully implemented in manufacturing at Lumileds’ San Jose, CA location, and incorporated in illumination-grade LED products that have been successfully introduced to the market, including LUXEON Q and LUXEON FlipChip White.« less

A novel model for simulating the racing effect in capillary-driven underfill process in flip chip

NASA Astrophysics Data System (ADS)

Zhu, Wenhui; Wang, Kanglun; Wang, Yan

2018-04-01

Underfill is typically applied in flip chips to increase the reliability of the electronic packagings. In this paper, the evolution of the melt-front shape of the capillary-driven underfill flow is studied through 3D numerical analysis. Two different models, the prevailing surface force model and the capillary model based on the wetted wall boundary condition, are introduced to test their applicability, where level set method is used to track the interface of the two phase flow. The comparison between the simulation results and experimental data indicates that, the surface force model produces better prediction on the melt-front shape, especially in the central area of the flip chip. Nevertheless, the two above models cannot simulate properly the racing effect phenomenon that appears during underfill encapsulation. A novel ‘dynamic pressure boundary condition’ method is proposed based on the validated surface force model. Utilizing this approach, the racing effect phenomenon is simulated with high precision. In addition, a linear relationship is derived from this model between the flow front location at the edge of the flip chip and the filling time. Using the proposed approach, the impact of the underfill-dispensing length on the melt-front shape is also studied.

Chip-scale white flip-chip light-emitting diode containing indium phosphide/zinc selenide quantum dots

NASA Astrophysics Data System (ADS)

Fan, Bingfeng; Yan, Linchao; Lao, Yuqin; Ma, Yanfei; Chen, Zimin; Ma, Xuejin; Zhuo, Yi; Pei, Yanli; Wang, Gang

2017-08-01

A method for preparing a quantum dot (QD)-white light-emitting diode (WLED) is reported. Holes were etched in the SiO2 layer deposited on the sapphire substrate of the flip-chip LED by inductively coupled plasma, and these holes were then filled with QDs. An ultraviolet-curable resin was then spin-coated on top of the QD-containing SiO2 layer, and the resin was cured to act as a protecting layer. The reflective sidewall structure minimized sidelight leakage. The fabrication of the QD-WLED is simple in preparation and compatible with traditional LED processes, which was the minimum size of the WLED chip-scale integrated package. InP/ZnS core-shell QDs were used as the converter in the WLED. A blue light-emitting diode with a flip-chip structure was used as the excitation source. The QD-WLED exhibited color temperatures from 5900 to 6400 K and Commission Internationale De L'Elcairage color coordinates from (0.315, 0.325) to (0.325, 0.317), under drive currents from 100 to 400 mA. The QD-WLED exhibited stable optoelectronic properties.

Design, fabrication and actuation of a MEMS-based image stabilizer for photographic cell phone applications

NASA Astrophysics Data System (ADS)

Chiou, Jin-Chern; Hung, Chen-Chun; Lin, Chun-Ying

2010-07-01

This work presents a MEMS-based image stabilizer applied for anti-shaking function in photographic cell phones. The proposed stabilizer is designed as a two-axis decoupling XY stage 1.4 × 1.4 × 0.1 mm3 in size, and adequately strong to suspend an image sensor for anti-shaking photographic function. This stabilizer is fabricated by complex fabrication processes, including inductively coupled plasma (ICP) processes and flip-chip bonding technique. Based on the special designs of a hollow handle layer and a corresponding wire-bonding assisted holder, electrical signals of the suspended image sensor can be successfully sent out with 32 signal springs without incurring damage during wire-bonding packaging. The longest calculated traveling distance of the stabilizer is 25 µm which is sufficient to resolve the anti-shaking problem in a three-megapixel image sensor. Accordingly, the applied voltage for the 25 µm moving distance is 38 V. Moreover, the resonant frequency of the actuating device with the image sensor is 1.123 kHz.

Ten-channel InP-based large-scale photonic integrated transmitter fabricated by SAG technology

NASA Astrophysics Data System (ADS)

Zhang, Can; Zhu, Hongliang; Liang, Song; Cui, Xiao; Wang, Huitao; Zhao, Lingjuan; Wang, Wei

2014-12-01

A 10-channel InP-based large-scale photonic integrated transmitter was fabricated by selective area growth (SAG) technology combined with butt-joint regrowth (BJR) technology. The SAG technology was utilized to fabricate the electroabsorption modulated distributed feedback (DFB) laser (EML) arrays at the same time. The design of coplanar electrodes for electroabsorption modulator (EAM) was used for the flip-chip bonding package. The lasing wavelength of DFB laser could be tuned by the integrated micro-heater to match the ITU grids, which only needs one electrode pad. The average output power of each channel is 250 μW with an injection current of 200 mA. The static extinction ratios of the EAMs for 10 channels tested are ranged from 15 to 27 dB with a reverse bias of 6 V. The frequencies of 3 dB bandwidth of the chip for each channel are around 14 GHz. The novel design and simple fabrication process show its enormous potential in reducing the cost of large-scale photonic integrated circuit (LS-PIC) transmitter with high chip yields.

Silver free III-nitride flip chip light-emitting-diode with wall plug efficiency over 70% utilizing a GaN tunnel junction

NASA Astrophysics Data System (ADS)

Yonkee, B. P.; Young, E. C.; DenBaars, S. P.; Nakamura, S.; Speck, J. S.

2016-11-01

A molecular beam epitaxy regrowth technique was demonstrated on standard industrial patterned sapphire substrate light-emitting diode (LED) epitaxial wafers emitting at 455 nm to form a GaN tunnel junction. By using an HF pretreatment on the wafers before regrowth, a voltage of 3.08 V at 20 A/cm2 was achieved on small area devices. A high extraction package was developed for comparison with flip chip devices which utilize an LED floating in silicone over a BaSO4 coated header and produced a peak external quantum efficiency (EQE) of 78%. A high reflectivity mirror was designed using a seven-layer dielectric coating backed by aluminum which has a calculated angular averaged reflectivity over 98% between 400 and 500 nm. This was utilized to fabricate a flip chip LED which had a peak EQE and wall plug efficiency of 76% and 73%, respectively. This flip chip could increase light extraction over a traditional flip chip LED due to the increased reflectivity of the dielectric based mirror.

Hybrid-integrated coherent receiver using silica-based planar lightwave circuit technology

NASA Astrophysics Data System (ADS)

Kim, Jong-Hoi; Choe, Joong-Seon; Choi, Kwang-Seong; Youn, Chun-Ju; Kim, Duk-Jun; Jang, Sun-Hyok; Kwon, Yong-Hwan; Nam, Eun-Soo

2011-12-01

A hybrid-integrated coherent receiver module has been achieved using flip-chip bonding technology, consisting of a silica-based 90°-hybrid planar lightwave circuit (PLC) platform, a spot-size converter integrated waveguide photodiode (SSC-WG-PD), and a dual-channel transimpedance amplifier (TIA). The receiver module shows error-free operation up to 40Gb/s and OSNR sensitivity of 11.5 dB for BER = 10-3 at 25 Gb/s.

Chip bonding of low-melting eutectic alloys by transmitted laser radiation

NASA Astrophysics Data System (ADS)

Hoff, Christian; Venkatesh, Arjun; Schneider, Friedrich; Hermsdorf, Jörg; Bengsch, Sebastian; Wurz, Marc C.; Kaierle, Stefan; Overmeyer, Ludger

2017-06-01

Present-day thermode bond systems for the assembly of radio-frequency identification (RFID) chips are mechanically inflexible, difficult to control, and will not meet future manufacturing challenges sufficiently. Chip bonding, one of the key processes in the production of integrated circuits (ICs), has a high potential for optimization with respect to process duration and process flexibility. For this purpose, the technologies used, so far, are supposed to be replaced by a transmission laser-bonding process using low-melting eutectic alloys. In this study, successful bonding investigations of mock silicon chips and of RFID chips on flexible polymer substrates are presented using the low-melting eutectic alloy, 52In48Sn, and a laser with a wavelength of 2 μm.

Design and realization of 144 x 7 TDI ROIC with hybrid integrated test structure

NASA Astrophysics Data System (ADS)

Ceylan, Omer; Kayahan, Huseyin; Yazici, Melik; Baran, Muhammet Burak; Gurbuz, Yasar

2012-06-01

Design and realization of a 144x7 silicon readout integrated circuit (ROIC) based on switched capacitor TDI for MCT LWIR scanning type focal plane arrays (FPAs) and its corresponding hybrid integrated test circuits are presented. TDI operation with 7 detectors improves the SNR of the system by a factor of √7, while oversampling rate of 3 improves the spatial resolution of the system. ROIC supports bidirectional scan, 5 adjustable gain settings, bypass operation, automatic gain adjustment in case of mulfunctioning pixels and pixel select/deselect properties. Integration time of the system can be determined by the help of an external clock. Programming of ROIC can be done in parallel or serial mode according to the needs of the system. All properties except pixel select/deselect property can be performed in parallel mode, while pixel select/deselect property can be performed only in serial mode. ROIC can handle up to 3.75V dynamic range with a load of 25pF and output settling time of 80ns. Input referred noise of the ROIC is less than 750 rms electrons, while the power consumption is less than 100mW. To test ROIC in absence of detector array, a process and temperature compensated current reference array, which supplies uniform input current in range of 1-50nA to ROIC, is designed and measured both in room and cryogenic (77ºK) temperatures. Standard deviations of current reference arrays are measured 3.26% for 1nA and 0.99% for 50nA. ROIC and current reference array are fabricated seperately, and then flip-chip bonded for the test of the system. Flip-chip bonded system including ROIC and current reference test array is successfully measured both in room and cryogenic temperatures, and measurement results are presented. The manufacturing technology is 0.35μm, double poly-Si, four metal, 5V CMOS process.

Development of advanced micromirror arrays by flip-chip assembly

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper presents the design, commercial prefabrication, modeling and testing of advanced micromirror arrays fabricated using a novel, simple and inexpensive flip-chip assembly technique. Several polar piston arrays and rectangular cantilever arrays were fabricated using flip-chip assembly by which the upper layers of the array are fabricated on a separate chip and then transferred to a receiving module containing the lower layers. Typical polar piston arrays boast 98.3% active surface area, highly planarized surfaces, low address potentials compatible with CMOS electronics, highly standardized actuation between devices, and complex segmentation of mirror surfaces which allows for custom aberration configurations. Typical cantilever arrays boast large angles of rotation as well as an average surface planarity of only 1.779 nm of RMS roughness across 100 +m mirrors. Continuous torsion devices offer stable operation through as much as six degrees of rotation while binary operation devices offer stable activated positions with as much as 20 degrees of rotation. All arrays have desirable features of costly fabrication services like five structural layers and planarized mirror surfaces, but are prefabricated in the less costly MUMPs process. Models are developed for all devices and used to compare empirical data.

Low temperature co-fired ceramic packaging of CMOS capacitive sensor chip towards cell viability monitoring.

PubMed

Halonen, Niina; Kilpijärvi, Joni; Sobocinski, Maciej; Datta-Chaudhuri, Timir; Hassinen, Antti; Prakash, Someshekar B; Möller, Peter; Abshire, Pamela; Kellokumpu, Sakari; Lloyd Spetz, Anita

2016-01-01

Cell viability monitoring is an important part of biosafety evaluation for the detection of toxic effects on cells caused by nanomaterials, preferably by label-free, noninvasive, fast, and cost effective methods. These requirements can be met by monitoring cell viability with a capacitance-sensing integrated circuit (IC) microchip. The capacitance provides a measurement of the surface attachment of adherent cells as an indication of their health status. However, the moist, warm, and corrosive biological environment requires reliable packaging of the sensor chip. In this work, a second generation of low temperature co-fired ceramic (LTCC) technology was combined with flip-chip bonding to provide a durable package compatible with cell culture. The LTCC-packaged sensor chip was integrated with a printed circuit board, data acquisition device, and measurement-controlling software. The packaged sensor chip functioned well in the presence of cell medium and cells, with output voltages depending on the medium above the capacitors. Moreover, the manufacturing of microfluidic channels in the LTCC package was demonstrated.

Repairable chip bonding/interconnect process

DOEpatents

Bernhardt, Anthony F.; Contolini, Robert J.; Malba, Vincent; Riddle, Robert A.

1997-01-01

A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.

Miniaturized force/torque sensor for in vivo measurements of tissue characteristics.

PubMed

Hessinger, M; Pilic, T; Werthschutzky, R; Pott, P P

2016-08-01

This paper presents the development of a surgical instrument to measure interaction forces/torques with organic tissue during operation. The focus is on the design progress of the sensor element, consisting of a spoke wheel deformation element with a diameter of 12 mm and eight inhomogeneous doped piezoresistive silicon strain gauges on an integrated full-bridge assembly with an edge length of 500 μm. The silicon chips are contacted to flex-circuits via flip chip and bonded on the substrate with a single component adhesive. A signal processing board with an 18 bit serial A/D converter is integrated into the sensor. The design concept of the handheld surgical sensor device consists of an instrument coupling, the six-axis sensor, a wireless communication interface and battery. The nominal force of the sensing element is 10 N and the nominal torque is 1 N-m in all spatial directions. A first characterization of the force sensor results in a maximal systematic error of 4.92 % and random error of 1.13 %.

Fabrication of a Silicon Backshort Assembly for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

Aeroflex Technology as Class-Y Demonstrator

NASA Technical Reports Server (NTRS)

Suh, Jong-ook; Agarwal, Shri; Popelar, Scott

2014-01-01

Modern space field programmable gate array (FPGA) devices with increased functional density and operational frequency, such as Xilinx Virtex 4 (V4) and S (V5), are packaged in non-hermetic ceramic flip chip forms. These next generation space parts were not qualified to the MIL-PRF-38535 Qualified Manufacturer Listing (QML) class-V when they were released because class-V was only intended for hermetic parts. In order to bring Xilinx V5 type packages into the QML system, it was suggested that class-Y be set up as a new category. From 2010 through 2014, a JEDEC G12 task group developed screening and qualification requirements for Class-Y products. The Document Standardization Division of the Defense Logistics Agency (DLA) has completed an engineering practice study. In parallel with the class-Y efforts, the NASA Electronic Parts and Packaging (NEPP) program has funded JPL to study potential reliability issues of the class-Y products. The major hurdle of this task was the absence of adequate research samples. Figure 1-1 shows schematic diagrams of typical structures of class-Y type products. Typically, class-Y products are either in ceramic flip chip column grid array (CGA) or land grid array (LGA) form. In class-Y packages, underfill and heat spread adhesive materials are directly exposed to the spacecraft environment due to their non-hermeticity. One of the concerns originally raised was that the underfill material could degrade due to the spacecraft environment and negatively impact the reliability of the package. In order to study such issues, it was necessary to use ceramic daisy chain flip chip package samples so that continuity of flip chip solder bumps could be monitored during the reliability tests. However, none of the commercially available class-Y daisy chain parts had electrical connections through flip chip solder bumps; only solder columns were daisy chained, which made it impossible to test continuity of flip chip solder bumps without using extremely costly functional parts. Among space parts manufacturers who were interested in producing class-Y products, Aeroflex Microelectronic Solutions-HiRel had been developing assembly processes using their internal R&D classy type samples. In early 2012, JPL and Aeroflex initiated a collaboration to study reliability of the Aeroflex technology as a class-Y demonstrator.

Repairable chip bonding/interconnect process

DOEpatents

Bernhardt, A.F.; Contolini, R.J.; Malba, V.; Riddle, R.A.

1997-08-05

A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules is disclosed. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder. 10 figs.

Delamination study of chip-to-chip bonding for a LIGA-based safety and arming system

NASA Astrophysics Data System (ADS)

Subramanian, Gowrishankar; Deeds, Michael; Cochran, Kevin R.; Raghavan, Raghu; Sandborn, Peter A.

1999-08-01

The development of a miniature underwater weapon safety and arming system requires reliable chip-to-chip bonding of die that contain microelectromechanical actuators and sensors fabricated using a LIGA MEMS fabrication process. Chip-to- chip bonding is associated for several different bond materials (indium solder, thermoplastic paste, thermoplastic film and epoxy film), and bonding configurations (with an alloy 42 spacer, silicon to ceramic, and silicon to silicon). Metrology using acoustic micro imaging has been developed to determine the fraction of delamination of samples.

MEMS-based thermally-actuated image stabilizer for cellular phone camera

NASA Astrophysics Data System (ADS)

Lin, Chun-Ying; Chiou, Jin-Chern

2012-11-01

This work develops an image stabilizer (IS) that is fabricated using micro-electro-mechanical system (MEMS) technology and is designed to counteract the vibrations when human using cellular phone cameras. The proposed IS has dimensions of 8.8 × 8.8 × 0.3 mm3 and is strong enough to suspend an image sensor. The processes that is utilized to fabricate the IS includes inductive coupled plasma (ICP) processes, reactive ion etching (RIE) processes and the flip-chip bonding method. The IS is designed to enable the electrical signals from the suspended image sensor to be successfully emitted out using signal output beams, and the maximum actuating distance of the stage exceeds 24.835 µm when the driving current is 155 mA. Depending on integration of MEMS device and designed controller, the proposed IS can decrease the hand tremor by 72.5%.

Mechanical flip-chip for ultra-high electron mobility devices

DOE PAGES

Bennaceur, Keyan; Schmidt, Benjamin A.; Gaucher, Samuel; ...

2015-09-22

In this study, electrostatic gates are of paramount importance for the physics of devices based on high-mobility two-dimensional electron gas (2DEG) since they allow depletion of electrons in selected areas. This field-effect gating enables the fabrication of a wide range of devices such as, for example, quantum point contacts (QPC), electron interferometers and quantum dots. To fabricate these gates, processing is usually performed on the 2DEG material, which is in many cases detrimental to its electron mobility. Here we propose an alternative process which does not require any processing of the 2DEG material other than for the ohmic contacts. Thismore » approach relies on processing a separate wafer that is then mechanically mounted on the 2DEG material in a flip-chip fashion. This technique proved successful to fabricate quantum point contacts on both GaAs/AlGaAs materials with both moderate and ultra-high electron mobility.« less

Thermal cycling reliability of Cu/SnAg double-bump flip chip assemblies for 100 μm pitch applications

NASA Astrophysics Data System (ADS)

Son, Ho-Young; Kim, Ilho; Lee, Soon-Bok; Jung, Gi-Jo; Park, Byung-Jin; Paik, Kyung-Wook

2009-01-01

A thick Cu column based double-bump flip chip structure is one of the promising alternatives for fine pitch flip chip applications. In this study, the thermal cycling (T/C) reliability of Cu/SnAg double-bump flip chip assemblies was investigated, and the failure mechanism was analyzed through the correlation of T/C test and the finite element analysis (FEA) results. After 1000 thermal cycles, T/C failures occurred at some Cu/SnAg bumps located at the edge and corner of chips. Scanning acoustic microscope analysis and scanning electron microscope observations indicated that the failure site was the Cu column/Si chip interface. It was identified by a FEA where the maximum stress concentration was located during T/C. During T/C, the Al pad between the Si chip and a Cu column bump was displaced due to thermomechanical stress. Based on the low cycle fatigue model, the accumulation of equivalent plastic strain resulted in thermal fatigue deformation of the Cu column bumps and ultimately reduced the thermal cycling lifetime. The maximum equivalent plastic strains of some bumps at the chip edge increased with an increased number of thermal cycles. However, equivalent plastic strains of the inner bumps did not increase regardless of the number of thermal cycles. In addition, the z-directional normal plastic strain ɛ22 was determined to be compressive and was a dominant component causing the plastic deformation of Cu/SnAg double bumps. As the number of thermal cycles increased, normal plastic strains in the perpendicular direction to the Si chip and shear strains were accumulated on the Cu column bumps at the chip edge at low temperature region. Thus it was found that the Al pad at the Si chip/Cu column interface underwent thermal fatigue deformation by compressive normal strain and the contact loss by displacement failure of the Al pad, the main T/C failure mode of the Cu/SnAg flip chip assembly, then occurred at the Si chip/Cu column interface shear strain deformation during T/C.

Reliability study of high-brightness multiple single emitter diode lasers

NASA Astrophysics Data System (ADS)

Zhu, Jing; Yang, Thomas; Zhang, Cuipeng; Lang, Chao; Jiang, Xiaochen; Liu, Rui; Gao, Yanyan; Guo, Weirong; Jiang, Yuhua; Liu, Yang; Zhang, Luyan; Chen, Louisa

2015-03-01

In this study the chip bonding processes for various chips from various chip suppliers around the world have been optimized to achieve reliable chip on sub-mount for high performance. These chip on sub-mounts, for examples, includes three types of bonding, 8xx nm-1.2W/10.0W Indium bonded lasers, 9xx nm 10W-20W AuSn bonded lasers and 1470 nm 6W Indium bonded lasers will be reported below. The MTTF@25 of 9xx nm chip on sub-mount (COS) is calculated to be more than 203,896 hours. These chips from various chip suppliers are packaged into many multiple single emitter laser modules, using similar packaging techniques from 2 emitters per module to up to 7 emitters per module. A reliability study including aging test is performed on those multiple single emitter laser modules. With research team's 12 years' experienced packaging design and techniques, precise optical and fiber alignment processes and superior chip bonding capability, we have achieved a total MTTF exceeding 177,710 hours of life time with 60% confidence level for those multiple single emitter laser modules. Furthermore, a separated reliability study on wavelength stabilized laser modules have shown this wavelength stabilized module packaging process is reliable as well.

Multilayered microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2003-01-01

An apparatus for packaging of microelectronic devices is disclosed, wherein the package includes an integral window. The microelectronic device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The package can comprise, for example, a cofired ceramic frame or body. The package has an internal stepped structure made of a plurality of plates, with apertures, which are patterned with metallized conductive circuit traces. The microelectronic device can be flip-chip bonded on the plate to these traces, and oriented so that the light-sensitive side is optically accessible through the window. A cover lid can be attached to the opposite side of the package. The result is a compact, low-profile package, having an integral window that can be hermetically-sealed. The package body can be formed by low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the window being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. Multiple chips can be located within a single package, according to some embodiments. The cover lid can include a window. The apparatus is particularly suited for packaging of MEMS devices, since the number of handling steps is greatly reduced, thereby reducing the potential for contamination. The integral window can further include a lens for optically transforming light passing through the window. The package can include an array of binary optic lenslets made integral with the window. The package can include an electrically-switched optical modulator, such as a lithium niobate window attached to the package, for providing a very fast electrically-operated shutter.

CSP Manufacturing Challenges and Assembly Reliability

NASA Technical Reports Server (NTRS)

Ghaffarian, Reza

2000-01-01

Although the expression of CSP is widely used by industry from suppliers to users, its implied definition had evolved as the technology has matured. There are "expert definition"- package that is up to 1.5 time die- or "interim definition". CSPs are miniature new packages that industry is starting to implement and there are many unresolved technical issues associated with their implementation. For example, in early 1997, packages with 1 mm pitch and lower were the dominant CSPs, whereas in early 1998 packages with 0.8 mm and lower became the norm for CSPs. Other changes included the use of flip chip die rather than wire bond in CSP. Nonetheless the emerging CSPs are competing with bare die assemblies and are becoming the package of choice for size reduction applications. These packages provide the benefits of small size and performance of the bare die or flip chip, with the advantage of standard die packages. The JPL-led MicrotypeBGA Consortium of enterprises representing government agencies and private companies have jointed together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. This talk will cover specifically the experience of our consortium on technology implementation challenges, including design and build of both standard and microvia boards, assembly of two types of test vehicles, and the most current environmental thermal cycling test results.

Chip design for thin-film deep ultraviolet LEDs fabricated by laser lift-off of the sapphire substrate

NASA Astrophysics Data System (ADS)

Cho, H. K.; Krüger, O.; Külberg, A.; Rass, J.; Zeimer, U.; Kolbe, T.; Knauer, A.; Einfeldt, S.; Weyers, M.; Kneissl, M.

2017-12-01

We report on a chip design which allows the laser lift-off (LLO) of the sapphire substrate sustaining the epitaxial film of flip-chip mounted deep ultraviolet light emitting diodes. A nanosecond pulsed excimer laser with a wavelength of 248 nm was used for the LLO. A mechanically stable chip design was found to be the key to prevent crack formation in the epitaxial layers and material chipping during the LLO process. Stabilization was achieved by introducing a Ti/Au leveling layer that mechanically supports the fragile epitaxial film. The electrical and optical characterization of devices before and after the LLO process shows that the device performance did not degrade by the LLO.

Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays.

PubMed

Ciçek, Ihsan; Bozkurt, Ayhan; Karaman, Mustafa

2005-12-01

Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMUT element, we developed an electrical CMUT model with parameters derived through finite element analysis, and performed both the pre- and postlayout verification. An experimental chip consisting of 4 X 4 array of the designed circuit cells, each cell occupying a 200 X 200 microm2 area, was formed for the initial test studies and scheduled for fabrication in 0.8 microm, 50 V CMOS technology. The designed circuit is suitable for integration with CMUT arrays through flip-chip bonding and the CMUT-on-CMOS process.

Reliability Assessment of Advanced Flip-clip Interconnect Electronic Package Assemblies under Extreme Cold Temperatures (-190 and -120 C)

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni; Ghaffarian, Reza; Shapiro, Andrew; Napala, Phil A.; Martin, Patrick A.

2005-01-01

Flip-chip interconnect electronic package boards have been assembled, underfilled, non-destructively evaluated and subsequently subjected to extreme temperature thermal cycling to assess the reliability of this advanced packaging interconnect technology for future deep space, long-term, extreme temperature missions. In this very preliminary study, the employed temperature range covers military specifications (-55 C to 100 C), extreme cold Martian (-120 C to 115 C) and asteroid Nereus (-180 C to 25 C) environments. The resistance of daisy-chained, flip-chip interconnects were measured at room temperature and at various intervals as a function of extreme temperature thermal cycling. Electrical resistance measurements are reported and the tests to date have not shown significant change in resistance as a function of extreme temperature thermal cycling. However, the change in interconnect resistance becomes more noticeable with increasing number of thermal cycles. Further research work has been carried out to understand the reliability of flip-chip interconnect packages under extreme temperature applications (-190 C to 85 C) via continuously monitoring the daisy chain resistance. Adaptation of suitable diagnostic techniques to identify the failure mechanisms is in progress. This presentation will describe the experimental test results of flip-chip testing under extreme temperatures.

Flip Chip on Organic Substrates: A Feasibility Study for Space Applications

DTIC Science & Technology

2017-03-01

scheme, a 1752 I/O land grid array (LGA) package with decoupling capacitors, heat sink and optional column attach [1] as shown in Figure 1...investigated the effect of moisture and current loading on the Class Y flip chip on ceramic reliability [ 2 ]. The UT1752FC Class Y technology has...chip assembly to ceramic test substrates, the FA10 die are assembled to build-up organic test substrates as shown in Figure 2 . These assemblies

Low-temperature direct bonding of glass nanofluidic chips using a two-step plasma surface activation process.

PubMed

Xu, Yan; Wang, Chenxi; Dong, Yiyang; Li, Lixiao; Jang, Kihoon; Mawatari, Kazuma; Suga, Tadatomo; Kitamori, Takehiko

2012-01-01

Owing to the well-established nanochannel fabrication technology in 2D nanoscales with high resolution, reproducibility, and flexibility, glass is the leading, ideal, and unsubstitutable material for the fabrication of nanofluidic chips. However, high temperature (~1,000 °C) and a vacuum condition are usually required in the conventional fusion bonding process, unfortunately impeding the nanofluidic applications and even the development of the whole field of nanofluidics. We present a direct bonding of fused silica glass nanofluidic chips at low temperature, around 200 °C in ambient air, through a two-step plasma surface activation process which consists of an O(2) reactive ion etching plasma treatment followed by a nitrogen microwave radical activation. The low-temperature bonded glass nanofluidic chips not only had high bonding strength but also could work continuously without leakage during liquid introduction driven by air pressure even at 450 kPa, a very high pressure which can meet the requirements of most nanofluidic operations. Owing to the mild conditions required in the bonding process, the method has the potential to allow the integration of a range of functional elements into nanofluidic chips during manufacture, which is nearly impossible in the conventional high-temperature fusion bonding process. Therefore, we believe that the developed low-temperature bonding would be very useful and contribute to the field of nanofluidics.

Process for 3D chip stacking

DOEpatents

Malba, V.

1998-11-10

A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: (1) holding individual chips for batch processing, (2) depositing a dielectric passivation layer on the top and sidewalls of the chips, (3) opening vias in the dielectric, (4) forming the interconnects by laser pantography, and (5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume. 3 figs.

Process for 3D chip stacking

DOEpatents

Malba, Vincent

1998-01-01

A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: 1) holding individual chips for batch processing, 2) depositing a dielectric passivation layer on the top and sidewalls of the chips, 3) opening vias in the dielectric, 4) forming the interconnects by laser pantography, and 5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume.

Hollow Core Bragg Waveguide Design and Fabrication for Enhanced Raman Spectroscopy

NASA Astrophysics Data System (ADS)

Ramanan, Janahan

Raman spectroscopy is a widely used technique to unambiguously ascertain the chemical composition of a sample. The caveat with this technique is its extremely weak optical cross-section, making it difficult to measure Raman signal with standard optical setups. In this thesis, a novel hollow core Bragg Reflection Waveguide was designed to simultaneously increase the generation and collection of Raman scattered photons. A robust fabrication process of this waveguide was developed employing flip-chip bonding methods to securely seal the hollow core channel. The waveguide air-core propagation loss was experimentally measured to be 0.17 dB/cm, and the Raman sensitivity limit was measured to be 3 mmol/L for glycerol solution. The waveguide was also shown to enhance Raman modes of standard household aerosols that could not be seen with other devices.

Automated Hybridization of X-ray Absorber Elements-A Path to Large Format Microcalorimeter Arrays

NASA Technical Reports Server (NTRS)

Moseley, S.; Kelley, R.; Allen, C.; Kilbourne, C.; Costen, N.; Miller, T.

2007-01-01

In the design of microcalorimeters, it is often desirable to produce the X-ray absorber separately from the detector element. In this case, the attachment of the absorber to the detector element with the required thermal and mechanical characteristics is a major challenge. In such arrays, the attachment has been done by hand. This process is not easily extended to the large format arrays required for future X- ray astronomy missions such as the New x-ray Telescope or NeXT. In this paper we present an automated process for attaching absorber tiles to the surface of a large-scale X-ray detector array. The absorbers are attached with stycast epoxy to a thermally isolating polymer structure made of SU-8. SU-8 is a negative epoxy based photo resist produced by Microchem. We describe the fabrication of the X-ray absorbers and their suspension on a handle die in an adhesive matrix. We describe the production process for the polymer isolators on the detector elements. We have developed a new process for the alignment, and simultaneous bonding of the absorber tiles to an entire detector array. This process uses equipment and techniques used in the flip-chip bonding industry and approaches developed in the fabrication of the XRS-2 instrument. XRS-2 was an X-ray spectrometer that was launched on the Suzaku telescope in July 10, 2005. We describe the process and show examples of sample arrays produced by this process. Arrays with up to 300 elements have been bonded. The present tests have used dummy absorbers made of Si. In future work, we will demonstrate bonding of HgTe absorbers.

Detection of trans–cis flips and peptide-plane flips in protein structures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Touw, Wouter G., E-mail: wouter.touw@radboudumc.nl; Joosten, Robbie P.; Vriend, Gert, E-mail: wouter.touw@radboudumc.nl

A method is presented to detect peptide bonds that need either a trans–cis flip or a peptide-plane flip. A coordinate-based method is presented to detect peptide bonds that need correction either by a peptide-plane flip or by a trans–cis inversion of the peptide bond. When applied to the whole Protein Data Bank, the method predicts 4617 trans–cis flips and many thousands of hitherto unknown peptide-plane flips. A few examples are highlighted for which a correction of the peptide-plane geometry leads to a correction of the understanding of the structure–function relation. All data, including 1088 manually validated cases, are freely availablemore » and the method is available from a web server, a web-service interface and through WHAT-CHECK.« less

New Failure Mode of Flip-Chip Solder Joints Related to the Metallization of an Organic Substrate

NASA Astrophysics Data System (ADS)

Jang, J. W.; Yoo, S. J.; Hwang, H. I.; Yuk, S. Y.; Kim, C. K.; Kim, S. J.; Han, J. S.; An, S. H.

2015-10-01

We report a new failure phenomenon during flip-chip die attach. After reflow, flip-chip bumps were separated between the Al and Ti layers on the Si die side. This was mainly observed at the Si die corner. Transmission electron microscopy images revealed corrosion of the Al layer at the edge of the solder bump metallization. The corrosion at the metallization edge exhibited a notch shape with high stress concentration factor. The organic substrate had Cu metallization with an organic solderable preservative (OSP) coating layer, where a small amount of Cl ions were detected. A solder bump separation mechanism is suggested based on the reaction between Al and Cl, related to the flow of soldering flux. During reflow, the flux will dissolve the Cl-containing OSP layer and flow up to the Al layer on the Si die side. Then, the Cl-dissolved flux will actively react with Al, forming AlCl3. During cooling, solder bumps at the Si die corner will separate through the location of Al corrosion. This demonstrated that the chemistry of the substrate metallization can affect the thermomechanical reliability of flip-chip solder joints.

Mechanism of Void Prediction in Flip Chip Packages with Molded Underfill

NASA Astrophysics Data System (ADS)

Wu, Kuo-Tsai; Hwang, Sheng-Jye; Lee, Huei-Huang

2017-08-01

Voids have always been present using the molded underfill (MUF) package process, which is a problem that needs further investigation. In this study, the process was studied using the Moldex3D numerical analysis software. The effects of gas (air vent effect) on the overall melt front were also considered. In this isothermal process containing two fluids, the gas and melt colloid interact in the mold cavity. Simulation enabled an appropriate understanding of the actual situation to be gained, and, through analysis, the void region and exact location of voids were predicted. First, the global flow end area was observed to predict the void movement trend, and then the local flow ends were observed to predict the location and size of voids. In the MUF 518 case study, simulations predicted the void region as well as the location and size of the voids. The void phenomenon in a flip chip ball grid array underfill is discussed as part of the study.

A novel bonding method for large scale poly(methyl methacrylate) micro- and nanofluidic chip fabrication

NASA Astrophysics Data System (ADS)

Qu, Xingtian; Li, Jinlai; Yin, Zhifu

2018-04-01

Micro- and nanofluidic chips are becoming increasing significance for biological and medical applications. Future advances in micro- and nanofluidics and its utilization in commercial applications depend on the development and fabrication of low cost and high fidelity large scale plastic micro- and nanofluidic chips. However, the majority of the present fabrication methods suffer from a low bonding rate of the chip during thermal bonding process due to air trapping between the substrate and the cover plate. In the present work, a novel bonding technique based on Ar plasma and water treatment was proposed to fully bond the large scale micro- and nanofluidic chips. The influence of Ar plasma parameters on the water contact angle and the effect of bonding conditions on the bonding rate and the bonding strength of the chip were studied. The fluorescence tests demonstrate that the 5 × 5 cm2 poly(methyl methacrylate) chip with 180 nm wide and 180 nm deep nanochannels can be fabricated without any block and leakage by our newly developed method.

Method of fabricating a PbS-PbSe IR detector array

NASA Technical Reports Server (NTRS)

Barrett, John R. (Inventor)

1987-01-01

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chiping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

Electromigration and thermomigration in lead-free tin-silver-copper and eutectic tin-lead flip chip solder joints

NASA Astrophysics Data System (ADS)

Ou Yang, Fan-Yi

Phase separation and microstructure change of eutectic SnPb and SnAgCu flip chip solder joint were investigated under thermomigration, electromigration, stressmigration and the combination of these effects. Different morphological behaviors under DC and AC electromigration were seen. Phase separation with Pb rich phase migration to the anode was observed when current density is below 1.6 x 104 A/cm2 at 100°C. For some cases, phase separation of Pb-rich phase and Su-rich phase as well as refinement of lamellar microstructure has also been observed. We propose that the refinement is due to recrystallization. On the other hand, time-dependent melting of eutectic SnPb flip chip solder joints has been observed to occur frequently with current density above 1.6 x 104 A/cm 2at 100°C. It has been found that it is due to joule heating of the on-chip Al interconnects. We found that electromigration has especially generated voids at the anode of the Al. This damage has greatly increased the resistance of the Al, which produces the heat needed to melt the solder joint. Owing to the line-to-bump configuration in flip chip solder joints, current crowding occurs when electrons enters into or exits from the solder bump. At the cathode contact, current crowding induced pancake-type void formation was observed widely. Furthermore, at the anode contact, we note that hillock or whisker forms. The cross-sectioned surface in SnPb showed dimple and bulge after electromigration, while that of SnAgCu remained flat. The difference is due to a larger back stress in the SnAgCu, consequently electromigration in SnAgCu is slower than that in SnPb. For thermomigration in eutectic SnPb flip chip solder joints, phase separation of Sn and Pb occurred, with Pb moving to the cold end. Both Sn and Pb have a stepwise concentration profile across solder bump. Refinement of lamellar microstructure was observed, indicating recrystallization. Also, thermomigration in eutectic SnAgCu flip chip solder joint were presented. It seems that vacancy flux plays a dominant role in thermomigration in Pb-free solder bumps; voids formed on the cold end and Sn moved to the hot end.

Fabrication of Silicon Backshorts with Improved Out-of-Band Rejection for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

An implantable integrated low-power amplifier-microelectrode array for Brain-Machine Interfaces.

PubMed

Patrick, Erin; Sankar, Viswanath; Rowe, William; Sanchez, Justin C; Nishida, Toshikazu

2010-01-01

One of the important challenges in designing Brain-Machine Interfaces (BMI) is to build implantable systems that have the ability to reliably process the activity of large ensembles of cortical neurons. In this paper, we report the design, fabrication, and testing of a polyimide-based microelectrode array integrated with a low-power amplifier as part of the Florida Wireless Integrated Recording Electrode (FWIRE) project at the University of Florida developing a fully implantable neural recording system for BMI applications. The electrode array was fabricated using planar micromachining MEMS processes and hybrid packaged with the amplifier die using a flip-chip bonding technique. The system was tested both on bench and in-vivo. Acute and chronic neural recordings were obtained from a rodent for a period of 42 days. The electrode-amplifier performance was analyzed over the chronic recording period with the observation of a noise floor of 4.5 microVrms, and an average signal-to-noise ratio of 3.8.

Processing and Characterization of NiTi Shape Memory Alloy Particle Reinforced Sn-In Solders

DTIC Science & Technology

2006-12-01

solders generally operate at a high homologous temperature. Thermally induced grain growth, mechanical stress-induced grain growth and recrystallization ...the number of I/O connects available for flip chip as compared to the wirebond chip For interconnection and packaging, Pb-Sn and eutectic 63Sn...lower melting point is desired. The maximum use temperature for this alloy is around 120°C due to the fact that the eutectic reaction happened at

Electromigration induced high fraction of compound formation in SnAgCu flip chip solder joints with copper column

NASA Astrophysics Data System (ADS)

Xu, Luhua; Han, Jung-Kyu; Liang, Jarrett Jun; Tu, K. N.; Lai, Yi-Shao

2008-06-01

To overcome the effect of current crowding on electromigration-induced pancake-type void formation in flip chip solder joints, two types of Cu column in 90μm flip chip SnAgCu solder joints have been studied. They were (1) the solder contacts the Cu column at bottom and side walls and (2) the solder wets only the bottom surface of the copper column. With a current density of 1.6×104A/cm2 at 135°C, no failure was detected after 1290h. However, the resistance increased by about 10% due to the formation of a large fraction of intermetallic compounds. We found that electromigration has accelerated the consumption rate of copper column and converted almost the entire solder joint into intermetallic compound. Mechanically, drop impact test indicates a brittle fracture failure in the intermetallic. The electromigration critical product for the intermetallic is discussed.

Flip chip bumping technology—Status and update

NASA Astrophysics Data System (ADS)

Juergen Wolf, M.; Engelmann, Gunter; Dietrich, Lothar; Reichl, Herbert

2006-09-01

Flip chip technology is a key driver for new complex system architectures and high-density packaging, e.g. sensor or pixel devices. Bumped wafers/dice as key elements become very important in terms of general availability at low cost, high yield and quality level. Today, different materials, e.g. Au, Ni, AuSn, SnAg, SnAgCu, SnCu, etc., are used for flip chip interconnects and different bumping approaches are available. Electroplating is the technology of choice for high-yield wafer bumping for small bump sizes and pitches. Lead-free solder bumps require an increase in knowledge in the field of under bump metallization (UBM) and the interaction of bump and substrate metallization, the formation and growth of intermetallic compounds (IMCs) during liquid- and solid-phase reactions. Results of a new bi-layer UBM of Ni-Cu which is especially designed for small-sized lead-free solder bumps will be discussed.

Ice-assisted transfer of carbon nanotube arrays.

PubMed

Wei, Haoming; Wei, Yang; Lin, Xiaoyang; Liu, Peng; Fan, Shoushan; Jiang, Kaili

2015-03-11

Decoupling the growth and the application of nanomaterials by transfer is an important issue in nanotechnology. Here, we developed an efficient transfer technique for carbon nanotube (CNT) arrays by using ice as a binder to temporarily bond the CNT array and the target substrate. Ice makes it an ultraclean transfer because the evaporation of ice ensures that no contaminants are introduced. The transferred superaligned carbon nanotube (SACNT) arrays not only keep their original appearance and initial alignment but also inherit their spinnability, which is the most desirable feature. The transfer-then-spin strategy can be employed to fabricate patterned CNT arrays, which can act as 3-dimensional electrodes in CNT thermoacoustic chips. Besides, the flip-chipped CNTs are promising field electron emitters. Furthermore, the ice-assisted transfer technique provides a cost-effective solution for mass production of SACNTs, giving CNT technologies a competitive edge, and this method may inspire new ways to transfer other nanomaterials.

Integrated microsystems packaging approach with LCP

NASA Astrophysics Data System (ADS)

Jaynes, Paul; Shacklette, Lawrence W.

2006-05-01

Within the government communication market there is an increasing push to further miniaturize systems with the use of chip-scale packages, flip-chip bonding, and other advances over traditional packaging techniques. Harris' approach to miniaturization includes these traditional packaging advances, but goes beyond this level of miniaturization by combining the functional and structural elements of a system, thus creating a Multi-Functional Structural Circuit (MFSC). An emerging high-frequency, near hermetic, thermoplastic electronic substrate material, Liquid Crystal Polymer (LCP), is the material that will enable the combination of the electronic circuit and the physical structure of the system. The first embodiment of this vision for Harris is the development of a battlefield acoustic sensor module. This paper will introduce LCP and its advantages for MFSC, present an example of the work that Harris has performed, and speak to LCP MFSCs' potential benefits to miniature communications modules and sensor platforms.

Multi-wafer bonding technology for the integration of a micromachined Mirau interferometer

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Lullin, Justine; Froemel, Joerg; Wiemer, Maik; Bargiel, Sylwester; Passilly, Nicolas; Gorecki, Christophe; Gessner, Thomas

2015-02-01

The paper presents the multi-wafer bonding technology as well as the integration of electrical connection to the zscanner wafer of the micromachined array-type Mirau interferometer. A Mirau interferometer, which is a key-component of optical coherence tomography (OCT) microsystem, consists of a microlens doublet, a MOEMS Z-scanner, a focusadjustment spacer and a beam splitter plate. For the integration of this MOEMS device heterogeneous bonding of Si, glass and SOI wafers is necessary. Previously, most of the existing methods for multilayer wafer bonding require annealing at high temperature, i.e., 1100°C. To be compatible with MEMS devices, bonding of different material stacks at temperatures lower than 400°C has also been investigated. However, if more components are involved, it becomes less effective due to the alignment accuracy or degradation of surface quality of the not-bonded side after each bonding operation. The proposed technology focuses on 3D integration of heterogeneous building blocks, where the assembly process is compatible with the materials of each wafer stack and with position accuracy which fits optical requirement. A demonstrator with up to 5 wafers bonded lower than 400°C is presented and bond interfaces are evaluated. To avoid the complexity of through wafer vias, a design which creates electrical connections along vertical direction by mounting a wafer stack on a flip chip PCB is proposed. The approach, which adopts vertically-stacked wafers along with electrical connection functionality, provides not only a space-effective integration of MOEMS device but also a design where the Mirau stack can be further integrated with other components of the OCT microsystem easily.

Electromigration Failure Mechanism in Sn-Cu Solder Alloys with OSP Cu Surface Finish

NASA Astrophysics Data System (ADS)

Chu, Ming-Hui; Liang, S. W.; Chen, Chih; Huang, Annie T.

2012-09-01

Organic solderable preservative (OSP) has been adopted as the Cu substrate surface finish in flip-chip solder joints for many years. In this study, the electromigration behavior of lead-free Sn-Cu solder alloys with thin-film under bump metallization and OSP surface finish was investigated. The results showed that severe damage occurred on the substrate side (cathode side), whereas the damage on the chip side (cathode side) was not severe. The damage on the substrate side included void formation, copper dissolution, and formation of intermetallic compounds (IMCs). The OSP Cu interface on the substrate side became the weakest point in the solder joint even when thin-film metallization was used on the chip side. Three-dimensional simulations were employed to investigate the current density distribution in the area between the OSP Cu surface finish and the solder. The results indicated that the current density was higher along the periphery of the bonding area between the solder and the Cu pad, consistent with the area of IMC and void formation in our experimental results.

Cost-effective parallel optical interconnection module based on fully passive-alignment process

NASA Astrophysics Data System (ADS)

Son, Dong Hoon; Heo, Young Soon; Park, Hyoung-Jun; Kang, Hyun Seo; Kim, Sung Chang

2017-11-01

In optical interconnection technology, high-speed and large data transitions with low error rate and cost reduction are key issues for the upcoming 8K media era. The researchers present notable types of optical manufacturing structures of a four-channel parallel optical module by fully passive alignment, which are able to reduce manufacturing time and cost. Each of the components, such as vertical-cavity surface laser/positive-intrinsic negative-photodiode array, microlens array, fiber array, and receiver (RX)/transmitter (TX) integrated circuit, is integrated successfully using flip-chip bonding, die bonding, and passive alignment with a microscope. Clear eye diagrams are obtained by 25.78-Gb/s (for TX) and 25.7-Gb/s (for RX) nonreturn-to-zero signals of pseudorandom binary sequence with a pattern length of 231 to 1. The measured responsivity and minimum sensitivity of the RX are about 0.5 A/W and ≤-6.5 dBm at a bit error rate (BER) of 10-12, respectively. The optical power margin at a BER of 10-12 is 7.5 dB, and cross talk by the adjacent channel is ≤1 dB.

Spatial redistribution of radiation in flip-chip photodiodes based on InAsSbP/InAs double heterostructures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zakgeim, A. L.; Il’inskaya, N. D.; Karandashev, S. A.

2017-02-15

The spatial distribution of equilibrium and nonequilibrium (including luminescent) IR (infrared) radiation in flip-chip photodiodes based on InAsSbP/InAs double heterostructures (λ{sub max} = 3.4 μm) is measured and analyzed; the structural features of the photodiodes, including the reflective properties of the ohmic contacts, are taken into account. Optical area enhancement due to multiple internal reflection in photodiodes with different geometric characteristics is estimated.

Flip-chip replacement within the constraints imposed by multilayer ceramic (MLC) modules

NASA Astrophysics Data System (ADS)

Puttlitz, Karl J.

1984-01-01

Economics often dictates that suitable module rework procedures be established to replace solder bump devices (flip chips) reflowed to multichip carriers. These operations are complicated, owing to various constraints such as the substrate's physical and mechanical properties, close proximity of surface features, etc. This paper describes the constraints and the methods to circumvent them. An order of preference based upon the degree of constraint is recommended to achieve device removal and subsequent site dress of the residual solder left on the substrate. It has been determined that rework (device replacement) can be successfully achieved in even highly constricted situations. This is illustrated by the example of utilizing a localized heating technique, hot gas, to remove solder from microsockets from which chips were previously removed. Microsockets are areas to which chips are reflowed to the top surface of IBM's densely populated multilayer ceramic (MLC) modules, thus forming the so-called controlled collapse chip connection or C-4. The microsocket patterns are thus identical to the chip footprint.

Non-aqueous electrolytes for isotachophoresis of weak bases and its application to the comprehensive preconcentration of the 20 proteinogenic amino acids in column-coupling ITP/CE-MS.

PubMed

Kler, Pablo A; Huhn, Carolin

2014-11-01

Isotachophoresis (ITP) has long been used alone but also as a preconcentration technique for capillary electrophoresis (CE). Unfortunately, up to now, its application is restricted to relatively strong acids and bases as either the degree of (de)protonation is too low or the water dissociation is too high, evoking zone electrophoresis. With the comprehensive ITP analysis of all 20 proteinogenic amino acids as model analytes, we, here, show that non-aqueous ITP using dimethylsulfoxide as a solvent solves this ITP shortcoming. Dimethylsulfoxide changes the pH regime of analytes and electrolytes but, more importantly, strongly reduces the proton mobility by prohibiting hydrogen bonds and thus, the so-called Zundel-Eigen-Zundel electrical conduction mechanism of flipping hydrogen bonds. The effects are demonstrated in an electrolyte system with taurine or H(+) as terminator, and imidazole as leader together with strong acids such as oxalic and even trifluoroacetic acid as counterions, both impossible to use in aqueous solution. Mass spectrometric as well as capacitively coupled contactless conductivity detection (C(4)D) are used to follow the ITP processes. To demonstrate the preconcentration capabilities of ITP in a two-dimensional set-up, we, here, also demonstrate that our non-aqueous ITP method can be combined with capillary electrophoresis-mass spectrometry in a column-coupling system using a hybrid approach of capillaries coupled to a microfluidic interface. For this, C(4)D was optimized for on-chip detection with the electrodes aligned on top of a thin glass lid of the microfluidic chip.

32 x 16 CMOS smart pixel array for optical interconnects

NASA Astrophysics Data System (ADS)

Kim, Jongwoo; Guilfoyle, Peter S.; Stone, Richard V.; Hessenbruch, John M.; Choquette, Kent D.; Kiamilev, Fouad E.

2000-05-01

Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32 X 16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 micrometers technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 micrometers technology.

Development of a RadFET Linear Array for Intracavitary in vivo Dosimetry During External Beam Radiotherapy and Brachytherapy

NASA Astrophysics Data System (ADS)

Price, R. A.; Benson, C.; Joyce, M. J.; Rodgers, K.

2004-08-01

We present the details of a new linear array dosimeter consisting of a chain of semiconductors mounted on an ultra-thin (50 /spl mu/m thick) flexible substrate and housed in an intracavitary catheter. The semiconductors, manufactured by NMRC Cork, have not been packaging and incorporate a passivation layer that allows them to be mounted on the substrate using flip-chip-bonding. This paper reports, for the first time, the construction of a multiple (ten) detector array suited to in vivo dosimetry in the rectum, esophagus and vagina during external beam radiotherapy, as well as being adaptable to in vivo dosimetry during brachytherapy and diagnostic radiology.

A non-volatile flip-flop based on diode-selected PCM for ultra-low power systems

NASA Astrophysics Data System (ADS)

Ye, Yong; Du, Yuan; Gao, Dan; Kang, Yong; Song, Zhitang; Chen, Bomy

2016-10-01

As the process technology is continuously shrinking, low power consumption is a major issue in VLSI Systems-on-Chip (SoCs), especially for standby-power-critical applications. Recently, the emerging CMOS-compatible non-volatile memories (NVMs), such as Phase Change Memory (PCM), have been used as on-chip storage elements, which can obtain non-volatile processing, nearly-zero standby power and instant-on capability. PCM has been considered as the best candidate for the next generation of NVMs for its low cost, high density and high resistance transformation ratio. In this paper, for the first time, we present a diode-selected PCM based non-volatile flip-flop (NVFF) which is optimized for better power consumption and process variation tolerance. With dual trench isolation process, the diode-selected PCM realizes ultra small area, which is very suitable for multi-context configuration and large scale flip-flops matrix. Since the MOS-selected PCM is hard to shrink further due to large amount of PCM write current, the proposed NVFF achieves higher power efficiency without loss of current driving capability. Using the 40nm manufacturing process, the area of the cell (1D1R) is as small as 0.016 μm2. Simulation results show that the energy consumption during the recall operation is 62 fJ with 1.1 standard supply voltage, which is reduced by 54.9% compared to the previous 2T2R based NVFF. When the supply voltage reduces to 0.7 V, the recall energy is as low as 17 fJ. With the great advantages in cell size and energy, the proposed diode-selected NVFF is very applicable and cost-effective for ULP systems.

Life test of the InGaAs focal plane arrays detector for space applications

NASA Astrophysics Data System (ADS)

Zhu, Xian-Liang; Zhang, Hai-Yan; Li, Xue; Huang, Zhang-Cheng; Gong, Hai-Mei

2017-08-01

The short-wavelength infrared (SWIR) InGaAs focal plane array (FPA) detector consists of infrared detector chip, readout integrated circuit (ROIC), and flip-chip bonding interconnection by Indium bump. In order to satisfy space application requirements for failure rates or Mean Time to Failure (MTTF), which can only be demonstrated with the large number of detectors manufactured, the single pixel in InGaAs FPAs was chosen as the research object in this paper. The constant-stress accelerated life tests were carried out at 70°C 80°C 90°C and100°C. The failed pixels increased gradually during more than 14000 hours at each elevated temperatures. From the random failure data the activation energy was estimated to be 0.46eV, and the average lifetime of a single pixel in InGaAs FPAs was estimated to be longer than 1E+7h at the practical operating temperature (5°C).

Characterization and Modeling of Fine-Pitch Copper Ball Bonding on a Cu/Low- k Chip

NASA Astrophysics Data System (ADS)

Che, F. X.; Wai, L. C.; Zhang, Xiaowu; Chai, T. C.

2015-02-01

Cu ball bonding faces more challenges than Au ball bonding, for example, excessive deformation of the bond pad and damage of Cu/low- k structures, because of the much greater hardness of Cu free air balls. In this study, dynamic finite-element analysis (FEA) modeling with displacement control was developed to simulate the ball-bonding process. The three-dimensional (3D) FEA simulation results were confirmed by use of stress-measurement data, obtained by use of stress sensors built into the test chip. Stress comparison between two-dimensional (2D) and 3D FEA models showed the 2D plain strain model to be a reasonable and effective model for simulation of the ball-bonding process without loss of accuracy; it also saves computing resources. The 2D FEA model developed was then used in studies of a Cu/low- k chip to find ways of reducing Al bond pad deformation and stresses of low- k structures. The variables studied included Al pad properties, capillary geometry, bond pad design (Al pad thickness, Al pad coated with Ni layer), and the effect of ultrasonic bonding power.

An Implantable Neural Sensing Microsystem with Fiber-Optic Data Transmission and Power Delivery

PubMed Central

Park, Sunmee; Borton, David A.; Kang, Mingyu; Nurmikko, Arto V.; Song, Yoon-Kyu

2013-01-01

We have developed a prototype cortical neural sensing microsystem for brain implantable neuroengineering applications. Its key feature is that both the transmission of broadband, multichannel neural data and power required for the embedded microelectronics are provided by optical fiber access. The fiber-optic system is aimed at enabling neural recording from rodents and primates by converting cortical signals to a digital stream of infrared light pulses. In the full microsystem whose performance is summarized in this paper, an analog-to-digital converter and a low power digital controller IC have been integrated with a low threshold, semiconductor laser to extract the digitized neural signals optically from the implantable unit. The microsystem also acquires electrical power and synchronization clocks via optical fibers from an external laser by using a highly efficient photovoltaic cell on board. The implantable unit employs a flexible polymer substrate to integrate analog and digital microelectronics and on-chip optoelectronic components, while adapting to the anatomical and physiological constraints of the environment. A low power analog CMOS chip, which includes preamplifier and multiplexing circuitry, is directly flip-chip bonded to the microelectrode array to form the cortical neurosensor device. PMID:23666130

Light-extraction enhancement of GaN-based 395  nm flip-chip light-emitting diodes by an Al-doped ITO transparent conductive electrode.

PubMed

Xu, Jin; Zhang, Wei; Peng, Meng; Dai, Jiangnan; Chen, Changqing

2018-06-01

The distinct ultraviolet (UV) light absorption of indium tin oxide (ITO) limits the performance of GaN-based near-UV light-emitting diodes (LEDs). Herein, we report an Al-doped ITO with enhanced UV transmittance and low sheet resistance as the transparent conductive electrode for GaN-based 395 nm flip-chip near-UV LEDs. The thickness dependence of optical and electrical properties of Al-doped ITO films is investigated. The optimal Al-doped ITO film exhibited a transmittance of 93.2% at 395 nm and an average sheet resistance of 30.1  Ω/sq. Meanwhile, at an injection current of 300 mA, the forward voltage decreased from 3.14 to 3.11 V, and the light output power increased by 13% for the 395 nm near-UV flip-chip LEDs with the optimal Al-doped ITO over those with pure ITO. This Letter provides a simple and repeatable approach to further improve the light extraction efficiency of GaN-based near-UV LEDs.

Printability Optimization For Fine Pitch Solder Bonding

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kwon, Sang-Hyun; Lee, Chang-Woo; Yoo, Sehoon

2011-01-17

Effect of metal mask and pad design on solder printability was evaluated by DOE in this study. The process parameters were stencil thickness, squeegee angle, squeegee speed, mask separating speed, and pad angle of PCB. The main process parameters for printability were stencil thickness and squeegee angle. The response surface showed that maximum printability of 1005 chip was achieved at the stencil thickness of 0.12 mm while the maximum printability of 0603 and 0402 chip was obtained at the stencil thickness of 0.05 mm. The bonding strength of the MLCC chips was also directly related with the printability.

A 16K-bit static IIL RAM with 25-ns access time

NASA Astrophysics Data System (ADS)

Inabe, Y.; Hayashi, T.; Kawarada, K.; Miwa, H.; Ogiue, K.

1982-04-01

A 16,384 x 1-bit RAM with 25-ns access time, 600-mW power dissipation, and 33 sq mm chip size has been developed. Excellent speed-power performance with high packing density has been achieved by an oxide isolation technology in conjunction with novel ECL circuit techniques and IIL flip-flop memory cells, 980 sq microns (35 x 28 microns) in cell size. Development results have shown that IIL flip-flop memory cell is a trump card for assuring achievement of a high-performance large-capacity bipolar RAM, in the above 16K-bit/chip area.

Electromigration in solder joints and solder lines

NASA Astrophysics Data System (ADS)

Gan, H.; Choi, W. J.; Xu, G.; Tu, K. N.

2002-06-01

Electromigration may affect the reliability of flip-chip solder joints. Eutectic solder is a two-phase alloy, so its electromigration behavior is different from that in aluminum or copper interconnects. In addition, a flipchip solder joint has a built-in currentcrowding configuration to enhance electromigration failure. To better understand electromigration in SnPb and lead-free solder alloys, the authors prepared solder lines in v-grooves etched on Si (001). This article discusses the results of those tests and compares the electromigration failure modes of eutectic SnPb and SnAgCu flip-chip solder joints along with the mean-timeto-failure.

Ultra-thin ohmic contacts for p-type nitride light emitting devices

DOEpatents

Raffetto, Mark; Bharathan, Jayesh; Haberern, Kevin; Bergmann, Michael; Emerson, David; Ibbetson, James; Li, Ting

2014-06-24

A flip-chip semiconductor based Light Emitting Device (LED) can include an n-type semiconductor substrate and an n-type GaN epi-layer on the substrate. A p-type GaN epi-layer can be on the n-type GaN epi-layer and a metal ohmic contact p-electrode can be on the p-type GaN epi-layer, where the metal ohmic contact p-electrode can have an average thickness less than about 25 .ANG.. A reflector can be on the metal ohmic contact p-electrode and a metal stack can be on the reflector. An n-electrode can be on the substrate opposite the n-type GaN epi-layer and a bonding pad can be on the n-electrode.

Enhanced light extraction in tunnel junction-enabled top emitting UV LEDs

DOE PAGES

Zhang, Yuewei; Allerman, Andrew A.; Krishnamoorthy, Sriram; ...

2016-04-11

The efficiency of ultra violet LEDs has been critically limited by the absorption losses in p-type and metal layers. In this work, surface roughening based light extraction structures are combined with tunneling based p-contacts to realize highly efficient top-side light extraction efficiency in UV LEDs. Surface roughening of the top n-type AlGaN contact layer is demonstrated using self-assembled Ni nano-clusters as etch mask. The top surface roughened LEDs were found to enhance external quantum efficiency by over 40% for UV LEDs with a peak emission wavelength of 326 nm. The method described here can enable highly efficient UV LEDs withoutmore » the need for complex manufacturing methods such as flip chip bonding.« less

High-sensitivity low-noise miniature fluxgate magnetometers using a flip chip conceptual design.

PubMed

Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

2014-07-30

This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current "flip chip" concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or "responsivity" for magnetometers) and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz) magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz(1/2) at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market.

Quantifying the benefits of improved rolling of chip seals : final report, June 2008.

DOT National Transportation Integrated Search

2008-06-01

This report presents an improvement in the rolling protocol for chip seals based on an evaluation of aggregate : retention performance and aggregate embedment depth. The flip-over test (FOT), Vialit test, modified sand circle : test, digital image pr...

Broadband and scalable optical coupling for silicon photonics using polymer waveguides

NASA Astrophysics Data System (ADS)

La Porta, Antonio; Weiss, Jonas; Dangel, Roger; Jubin, Daniel; Meier, Norbert; Horst, Folkert; Offrein, Bert Jan

2018-04-01

We present optical coupling schemes for silicon integrated photonics circuits that account for the challenges in large-scale data processing systems such as those used for emerging big data workloads. Our waveguide based approach allows to optimally exploit the on-chip optical feature size, and chip- and package real-estate. It further scales well to high numbers of channels and is compatible with state-of-the-art flip-chip die packaging. We demonstrate silicon waveguide to polymer waveguide coupling losses below 1.5 dB for both the O- and C-bands with a polarisation dependent loss of <1 dB. Over 100 optical silicon waveguide to polymer waveguide interfaces were assembled within a single alignment step, resulting in a physical I/O channel density of up to 13 waveguides per millimetre along the chip-edge, with an average coupling loss of below 3.4 dB measured at 1310 nm.

Embeded photonic crystal at the interface of p-GaN and Ag reflector to improve light extraction of GaN-based flip-chip light-emitting diode

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhen, Aigong; Ma, Ping, E-mail: maping@semi.ac.cn; Zhang, Yonghui

2014-12-22

In this experiment, a flip-chip light-emitting diode with photonic crystal was fabricated at the interface of p-GaN and Ag reflector via nanospheres lithography technique. In this structure, photonic crystal could couple with the guide-light efficiently by reason of the little distance between photonic crystal and active region. The light output power of light emitting diode with embedded photonic crystal was 1.42 times larger than that of planar flip-chip light-emitting diode. Moreover, the embedded photonic crystal structure makes the far-field divergence angle decreased by 18° without spectra shift. The three-dimensional finite difference time domain simulation results show that photonic crystal couldmore » improve the light extraction, and enhance the light absorption caused by Ag reflector simultaneously, because of the roughed surface. The depth of photonic crystal is the key parameter affecting the light extraction and absorption. Light extraction efficiency increases with the depth photonic crystal structure rapidly, and reaches the maximum at the depth 80 nm, beyond which light extraction decrease drastically.« less

Development of chip passivated monolithic complementary MISFET circuits with beam leads

NASA Technical Reports Server (NTRS)

Ragonese, L. J.; Kim, M. J.; Corrie, B. L.; Brouillette, J. W.; Warr, R. E.

1972-01-01

The results are presented of a program to demonstrate the processes for fabricating complementary MISFET beam-leaded circuits, which, potentially, are comparable in quality to available bipolar beam-lead chips that use silicon nitride passivation in conjunction with a platinum-titanium-gold metal system. Materials and techniques, different from the bipolar case, were used in order to be more compatible with the special requirements of fully passivated complementary MISFET devices. Two types of circuits were designed and fabricated, a D-flip-flop and a three-input NOR/NAND gate. Fifty beam-leaded chips of each type were constructed. A quality and reliability assurance program was performed to identify failure mechanisms. Sample tests and inspections (including destructive) were developed to measure the physical characteristics of the circuits.

On-chip detection of non-classical light by scalable integration of single-photon detectors

PubMed Central

Najafi, Faraz; Mower, Jacob; Harris, Nicholas C.; Bellei, Francesco; Dane, Andrew; Lee, Catherine; Hu, Xiaolong; Kharel, Prashanta; Marsili, Francesco; Assefa, Solomon; Berggren, Karl K.; Englund, Dirk

2015-01-01

Photonic-integrated circuits have emerged as a scalable platform for complex quantum systems. A central goal is to integrate single-photon detectors to reduce optical losses, latency and wiring complexity associated with off-chip detectors. Superconducting nanowire single-photon detectors (SNSPDs) are particularly attractive because of high detection efficiency, sub-50-ps jitter and nanosecond-scale reset time. However, while single detectors have been incorporated into individual waveguides, the system detection efficiency of multiple SNSPDs in one photonic circuit—required for scalable quantum photonic circuits—has been limited to <0.2%. Here we introduce a micrometer-scale flip-chip process that enables scalable integration of SNSPDs on a range of photonic circuits. Ten low-jitter detectors are integrated on one circuit with 100% device yield. With an average system detection efficiency beyond 10%, and estimated on-chip detection efficiency of 14–52% for four detectors operated simultaneously, we demonstrate, to the best of our knowledge, the first on-chip photon correlation measurements of non-classical light. PMID:25575346

Wafer-level vacuum/hermetic packaging technologies for MEMS

NASA Astrophysics Data System (ADS)

Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

2010-02-01

An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

Design and fabrication of vertically-integrated CMOS image sensors.

PubMed

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

Design and Fabrication of Vertically-Integrated CMOS Image Sensors

PubMed Central

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

Electrically-pumped 850-nm micromirror VECSELs.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Geib, Kent Martin; Peake, Gregory Merwin; Serkland, Darwin Keith

Vertical-external-cavity surface-emitting lasers (VECSELs) combine high optical power and good beam quality in a device with surface-normal output. In this paper, we describe the design and operating characteristics of an electrically-pumped VECSEL that employs a wafer-scale fabrication process and operates at 850 nm. A curved micromirror output coupler is heterogeneously integrated with AlGaAs-based semiconductor material to form a compact and robust device. The structure relies on flip-chip bonding the processed epitaxial material to an aluminum nitride mount; this heatsink both dissipates thermal energy and permits high frequency modulation using coplanar traces that lead to the VECSEL mesa. Backside emission ismore » employed, and laser operation at 850 nm is made possible by removing the entire GaAs substrate through selective wet etching. While substrate removal eliminates absorptive losses, it simultaneously compromises laser performance by increasing series resistance and degrading the spatial uniformity of current injection. Several aspects of the VECSEL design help to mitigate these issues, including the use of a novel current-spreading n type distributed Bragg reflector (DBR). Additionally, VECSEL performance is improved through the use of a p-type DBR that is modified for low thermal resistance.« less

Electrically pumped 850-nm micromirror VECSELs

NASA Astrophysics Data System (ADS)

Keeler, Gordon A.; Serkland, Darwin K.; Geib, Kent M.; Peake, Gregory M.; Mar, Alan

2005-03-01

Vertical-external-cavity surface-emitting lasers (VECSELs) combine high optical power and good beam quality in a device with surface-normal output. In this paper, we describe the design and operating characteristics of an electrically-pumped VECSEL that employs a wafer-scale fabrication process and operates at 850 nm. A curved micromirror output coupler is heterogeneously integrated with AlGaAs-based semiconductor material to form a compact and robust device. The structure relies on flip-chip bonding the processed epitaxial material to an aluminum nitride mount; this heatsink both dissipates thermal energy and permits high frequency modulation using coplanar traces that lead to the VECSEL mesa. Backside emission is employed, and laser operation at 850 nm is made possible by removing the entire GaAs substrate through selective wet etching. While substrate removal eliminates absorptive losses, it simultaneously compromises laser performance by increasing series resistance and degrading the spatial uniformity of current injection. Several aspects of the VECSEL design help to mitigate these issues, including the use of a novel current-spreading n type distributed Bragg reflector (DBR). Additionally, VECSEL performance is improved through the use of a p-type DBR that is modified for low thermal resistance.

3D capillary stop valves for versatile patterning inside microfluidic chips.

PubMed

Papadimitriou, V A; Segerink, L I; van den Berg, A; Eijkel, J C T

2018-02-13

The patterning of antibodies in microfluidics chips is always a delicate process that is usually done in an open chip before bonding. Typical bonding techniques such as plasma treatment can harm the antibodies with as result that they are removed from our fabrication toolbox. Here we propose a method, based on capillary phenomena using 3D capillary valves, that autonomously and conveniently allows us to pattern liquids inside closed chips. We theoretically analyse the system and demonstrate how our analysis can be used as a design tool for various applications. Chips patterned with the method were used for simple immunodetection of a cardiac biomarker which demonstrates its suitability for antibody patterning. Copyright © 2017 The Authors. Published by Elsevier B.V. All rights reserved.

AE (Acoustic Emission) for Flip-Chip CGA/FCBGA Defect Detection

NASA Technical Reports Server (NTRS)

Ghaffarian, Reza

2014-01-01

C-mode scanning acoustic microscopy (C-SAM) is a nondestructive inspection technique that uses ultrasound to show the internal feature of a specimen. A very high or ultra-high-frequency ultrasound passes through a specimen to produce a visible acoustic microimage (AMI) of its inner features. As ultrasound travels into a specimen, the wave is absorbed, scattered or reflected. The response is highly sensitive to the elastic properties of the materials and is especially sensitive to air gaps. This specific characteristic makes AMI the preferred method for finding "air gaps" such as delamination, cracks, voids, and porosity. C-SAM analysis, which is a type of AMI, was widely used in the past for evaluation of plastic microelectronic circuits, especially for detecting delamination of direct die bonding. With the introduction of the flip-chip die attachment in a package; its use has been expanded to nondestructive characterization of the flip-chip solder bumps and underfill. Figure 1.1 compares visual and C-SAM inspection approaches for defect detection, especially for solder joint interconnections and hidden defects. C-SAM is specifically useful for package features like internal cracks and delamination. C-SAM not only allows for the visualization of the interior features, it has the ability to produce images on layer-by-layer basis. Visual inspection; however, is only superior to C-SAM for the exposed features including solder dewetting, microcracks, and contamination. Ideally, a combination of various inspection techniques - visual, optical and SEM microscopy, C-SAM, and X-ray - need to be performed in order to assure quality at part, package, and system levels. This reports presents evaluations performed on various advanced packages/assemblies, especially the flip-chip die version of ball grid array/column grid array (BGA/CGA) using C-SAM equipment. Both external and internal equipment was used for evaluation. The outside facility provided images of the key features that could be detected using the most advanced C-SAM equipment with a skilled operator. Investigation continued using in-house equipment with its limitations. For comparison, representative X-rays of the assemblies were also gathered to show key defect detection features of these non-destructive techniques. Key images gathered and compared are: Compared the images of 2D X-ray and C-SAM for a plastic LGA assembly showing features that could be detected by either NDE technique. For this specific case, X-ray was a clear winner. Evaluated flip-chip CGA and FCBGA assemblies with and without heat sink by C-SAM. Only the FCCGA package that had no heat sink could be fully analyzed for underfill and bump quality. Cross-sectional microscopy did not revealed peripheral delamination features detected by C-SAM. Analyzed a number of fine pitch PBGA assemblies by C-SAM. Even though the internal features of the package assemblies could be detected, C-SAM was unable to detect solder joint failure at either the package or board level. Twenty times touch ups by solder iron with 700degF tip temperature, each with about 5 second duration, did not induce defects to be detected by C-SAM images. Other techniques need to be considered to induce known defects for characterization. Given NASA's emphasis on the use of microelectronic packages and assemblies and quality assurance on workmanship defect detection, understanding key features of various inspection systems that detect defects in the early stages of package and assembly is critical to developing approaches that will minimize future failures. Additional specific, tailored non-destructive inspection approaches could enable low-risk insertion of these advanced electronic packages having hidden and fine features.

Radiation hardness and timing studies of a monolithic TowerJazz pixel design for the new ATLAS Inner Tracker

NASA Astrophysics Data System (ADS)

Riegel, C.; Backhaus, M.; Van Hoorne, J. W.; Kugathasan, T.; Musa, L.; Pernegger, H.; Riedler, P.; Schaefer, D.; Snoeys, W.; Wagner, W.

2017-01-01

A part of the upcoming HL-LHC upgrade of the ATLAS Detector is the construction of a new Inner Tracker. This upgrade opens new possibilities, but also presents challenges in terms of occupancy and radiation tolerance. For the pixel detector inside the inner tracker, hybrid modules containing passive silicon sensors and connected readout chips are presently used, but require expensive assembly techniques like fine-pitch bump bonding. Silicon devices fabricated in standard commercial CMOS technologies, which include part or all of the readout chain, are also investigated offering a reduced cost as they are cheaper per unit area than traditional silicon detectors. If they contain the full readout chain, as for a fully monolithic approach, there is no need for the expensive flip-chip assembly, resulting in a further cost reduction and material savings. In the outer pixel layers of the ATLAS Inner Tracker, the pixel sensors must withstand non-ionising energy losses of up to 1015 n/cm2 and offer a timing resolution of 25 ns or less. This paper presents test results obtained on a monolithic test chip, the TowerJazz 180nm Investigator, towards these specifications. The presented program of radiation hardness and timing studies has been launched to investigate this technology's potential for the new ATLAS Inner Tracker.

Improved light extraction efficiency of GaN-based flip-chip light-emitting diodes with an antireflective interface layer

NASA Astrophysics Data System (ADS)

Wu, Dongxue; Ma, Ping; Liu, Boting; Zhang, Shuo; Wang, Junxi; Li, Jinmin

2016-05-01

GaN-based flip-chip light-emitting diodes (FC-LEDs) grown on nanopatterned sapphire substrates (NPSS) are fabricated using self-assembled SiO2 nanospheres as masks during inductively coupled plasma etching. By controlling the pattern spacing, epitaxial GaN can be grown from the top or bottom of patterns to obtain two different GaN/substrate interfaces. The optoelectronic characteristics of FC-LED chips with different GaN/sapphire interfaces are studied. The FC-LED with an antireflective interface layer consisting of a NPSS with GaN in the pattern spacings demonstrates better optical properties than the FC-LED with an interface embedded with air voids. Our study indicates that the two types of FC-LEDs grown on NPSS show higher crystal quality and improved electrical and optical characteristics compared with those of FC-LEDs grown on conventional planar sapphire substrates.

Toggling Bistable Atoms via Mechanical Switching of Bond Angle

NASA Astrophysics Data System (ADS)

Sweetman, Adam; Jarvis, Sam; Danza, Rosanna; Bamidele, Joseph; Gangopadhyay, Subhashis; Shaw, Gordon A.; Kantorovich, Lev; Moriarty, Philip

2011-04-01

We reversibly switch the state of a bistable atom by direct mechanical manipulation of bond angle using a dynamic force microscope. Individual buckled dimers at the Si(100) surface are flipped via the formation of a single covalent bond, actuating the smallest conceivable in-plane toggle switch (two atoms) via chemical force alone. The response of a given dimer to a flip event depends critically on both the local and nonlocal environment of the target atom—an important consideration for future atomic scale fabrication strategies.

Impact of Data Transmission over 10 Gbps on High-Density and Low-Cost Optoelectronic Module with Polynorbornene Waveguides

NASA Astrophysics Data System (ADS)

Ito, Yuka; Terada, Shinsuke; Arai, Shinya; Fujiwara, Makoto; Mori, Tetsuya; Choki, Koji; Fukushima, Takafumi; Koyanagi, Mitsumasa

2012-04-01

We proposed a rigid/flex optoelectronic (O/E) module with 48-channel polymeric waveguides for short-distance board-level optical interconnection. A flexible O/E test module was fabricated in the following two steps by using standard packaging processes. First, two vertical cavity surface emitting laser diodes (VCSELs) and one VCSEL driver (VD) were flip-chip bonded to a completed flexible printed circuit board (PCB), and two photodiodes (PDs) and one transimpedance amplifier/limiting amplifier (TIA/LA) to another flexible PCB. Second, the two flexible PCBs were attached with a polynorbornene (PNB) sheet in which high-density PNB waveguides were formed by UV exposure. Active areas of VCSELs and PDs on the flexible PCBs were aligned to micromirrors of the waveguides with -6 µm offset toward the signal propagation direction. We successfully demonstrated data transmission over 10 Gbps and low inter-channel crosstalk of less than -20 dB was achieved in the flexible O/E test module with 120-mm-long and 62.5-µm-pitch waveguides.

3D hybrid integrated lasers for silicon photonics

NASA Astrophysics Data System (ADS)

Song, B.; Pinna, S.; Liu, Y.; Megalini, L.; Klamkin, J.

2018-02-01

A novel 3D hybrid integration platform combines group III-V materials and silicon photonics to yield high-performance lasers is presented. This platform is based on flip-chip bonding and vertical optical coupling integration. In this work, indium phosphide (InP) devices with monolithic vertical total internal reflection turning mirrors were bonded to active silicon photonic circuits containing vertical grating couplers. Greater than 2 mW of optical power was coupled into a silicon waveguide from an InP laser. The InP devices can also be bonded directly to the silicon substrate, providing an efficient path for heat dissipation owing to the higher thermal conductance of silicon compared to InP. Lasers realized with this technique demonstrated a thermal impedance as low as 6.2°C/W, allowing for high efficiency and operation at high temperature. InP reflective semiconductor optical amplifiers were also integrated with 3D hybrid integration to form integrated external cavity lasers. These lasers demonstrated a wavelength tuning range of 30 nm, relative intensity noise lower than -135 dB/Hz and laser linewidth of 1.5 MHz. This platform is promising for integration of InP lasers and photonic integrated circuits on silicon photonics.

4-GHz counters bring synthesizers up to speed

NASA Astrophysics Data System (ADS)

Lee, F.; Miller, R.

1984-06-01

The availability of digital IC counters built on GaAs makes direct frequency division in microwave synthesizers possible. Four GHz is the highest clock rate achievable in production designs. These devices have the ability to drive TTL/CMOS logic, and the counter can be connected directly to single-chip frequency synthesizers controllers. A complete microwave sythesizer is formed by two chips and a voltage-controlled oscillator (VCO). The advantages of GaAs are discussed along with flip-flop basics, aspects of device fabrication, and the characteristics of GaAs MESAFETs. Attention is given to a GaAs prescaler usable for direct conversion, four kinds of flip-flops in a divide-by-two mode, and seven-stage binary ripple counters.

All-optical SR flip-flop based on SOA-MZI switches monolithically integrated on a generic InP platform

NASA Astrophysics Data System (ADS)

Pitris, St.; Vagionas, Ch.; Kanellos, G. T.; Kisacik, R.; Tekin, T.; Broeke, R.; Pleros, N.

2016-03-01

At the dawning of the exaflop era, High Performance Computers are foreseen to exploit integrated all-optical elements, to overcome the speed limitations imposed by electronic counterparts. Drawing from the well-known Memory Wall limitation, imposing a performance gap between processor and memory speeds, research has focused on developing ultra-fast latching devices and all-optical memory elements capable of delivering buffering and switching functionalities at unprecedented bit-rates. Following the master-slave configuration of electronic Flip-Flops, coupled SOA-MZI based switches have been theoretically investigated to exceed 40 Gb/s operation, provided a short coupling waveguide. However, this flip-flop architecture has been only hybridly integrated with silica-on-silicon integration technology exhibiting a total footprint of 45x12 mm2 and intra-Flip-Flop coupling waveguide of 2.5cm, limited at 5 Gb/s operation. Monolithic integration offers the possibility to fabricate multiple active and passive photonic components on a single chip at a close proximity towards, bearing promises for fast all-optical memories. Here, we present for the first time a monolithically integrated all-optical SR Flip-Flop with coupled master-slave SOA-MZI switches. The photonic chip is integrated on a 6x2 mm2 die as a part of a multi-project wafer run using library based components of a generic InP platform, fiber-pigtailed and fully packaged on a temperature controlled ceramic submount module with electrical contacts. The intra Flip-Flop coupling waveguide is 5 mm long, reducing the total footprint by two orders of magnitude. Successful flip flop functionality is evaluated at 10 Gb/s with clear open eye diagram, achieving error free operation with a power penalty of 4dB.

Metadynamics Simulation Study on the Conformational Transformation of HhaI Methyltransferase: An Induced-Fit Base-Flipping Hypothesis

PubMed Central

Ye, Fei; Zhao, Dan; Chen, Shijie; Jiang, Ren-Wang; Jiang, Hualiang; Luo, Cheng

2014-01-01

DNA methyltransferases play crucial roles in establishing and maintenance of DNA methylation, which is an important epigenetic mark. Flipping the target cytosine out of the DNA helical stack and into the active site of protein provides DNA methyltransferases with an opportunity to access and modify the genetic information hidden in DNA. To investigate the conversion process of base flipping in the HhaI methyltransferase (M.HhaI), we performed different molecular simulation approaches on M.HhaI-DNA-S-adenosylhomocysteine ternary complex. The results demonstrate that the nonspecific binding of DNA to M.HhaI is initially induced by electrostatic interactions. Differences in chemical environment between the major and minor grooves determine the orientation of DNA. Gln237 at the target recognition loop recognizes the GCGC base pair from the major groove side by hydrogen bonds. In addition, catalytic loop motion is a key factor during this process. Our study indicates that base flipping is likely to be an “induced-fit” process. This study provides a solid foundation for future studies on the discovery and development of mechanism-based DNA methyltransferases regulators. PMID:25045662

Polarity effect of electromigration on mechanical properties of lead-free solder joints

NASA Astrophysics Data System (ADS)

Ren, Fei

The trend of electronic packaging is to package the chips and the associated interconnections in a compact way that allows high speed operation; that allows for sufficient heat removal; that can withstand the thermal cycling associated with the turning on and turning off of the circuits; and that protects the circuits from environmental attack. These goals require that flip chip solder joints have higher resistance to electromigration, stronger mechanical property to sustain thermal mechanical stress, and are lead-free materials to satisfy environment and health concern. With lots of work on chemical reaction, electromigration and mechanical study in flip chip solder joints, however, the interaction between different driving forces is still little known. As a matter of fact, the combination study of chemical, electrical and mechanical is more and more significant to the understanding of the behavior of flip chip solder joints. In this dissertation, I developed one dimensional Cu (wire)-eutectic SnAgCu(ball)-Cu(wire) structure to investigate the interaction between electrical and mechanical force in lead-free solder joints. Electromigration was first conducted. The mechanical behaviors of solder joints before, after, and during electromigration were examined. Electrical current and mechanical stress were applied either in serial or in parallel to the solder joints. Tensile, creep, and drop tests, combined with different electrical current densities (1˜5x10 3A/cm2) and different stressing time (3˜144 hours), have been performed to study the effect of electromigration on the mechanical behavior of solder joints. Nano-indentation test was conducted to study the localized mechanical property of IMC at both interfaces in nanometer scale. Fracture images help analyze the failure mechanism of solder joints driven by both electrical and mechanical forces. The combination study shows a strain build-up during electromigration. Furthermore, a ductile-to-brittle transition in flip chip solder joints induced by electromigration is observed, in which the fracture position migrates from the middle to the cathode interface of the joint with increasing current density and time. The transition is explained by the polarity effect of electromigration, particular due to the accumulation of vacancies at the cathode interface.

Effect of surface finish on the failure mechanisms of flip-chip solder joints under electromigration

NASA Astrophysics Data System (ADS)

Lin, Y. L.; Lai, Y. S.; Tsai, C. M.; Kao, C. R.

2006-12-01

Two substrate surface finishes, Au/Ni and organic solderable preservative (OSP), were used to study the effect of the surface finish on the reliability of flip-chip solder joints under electromigration at 150°C ambient temperature. The solder used was eutectic PbSn, and the applied current density was 5×103 A/cm2 at the contact window of the chip. The under bump metallurgy (UBM) on the chip was sputtered Cu/Ni. It was found that the mean-time-to-failure (MTTF) of the OSP joints was six times better than that of the Au/Ni joints (3080 h vs. 500 h). Microstructure examinations uncovered that the combined effect of current crowding and the accompanying local Joule heating accelerated the local Ni UBM consumption near the point of electron entrance. Once Ni was depleted at a certain region, this region became nonconductive, and the flow of the electrons was diverted to the neighboring region. This neighboring region then became the place where electrons entered the joint, and the local Ni UBM consumption was accelerated. This process repeated itself, and the Ni-depleted region extended further on, creating an ever-larger nonconductive region. The solder joint eventually, failed when the nonconductive region became too large, making the effective current density very high. Accordingly, the key factor determining the MTTF was the Ni consumption rate. The joints with the OSP surface finish had a longer MTTF because Cu released from the substrate was able to reduce the Ni consumption rate.

System and Method for Fabricating Super Conducting Circuitry on Both Sides of an Ultra-Thin Layer

NASA Technical Reports Server (NTRS)

Brown, Ari D. (Inventor); Mikula, Vilem (Inventor)

2017-01-01

A method of fabricating circuitry in a wafer includes depositing a superconducting metal on a silicon on insulator wafer having a handle wafer, coating the wafer with a sacrificial layer and bonding the wafer to a thermally oxide silicon wafer with a first epoxy. The method includes flipping the wafer, thinning the flipped wafer by removing a handle wafer, etching a buried oxide layer, depositing a superconducting layer, bonding the wafer to a thermally oxidized silicon wafer having a handle wafer using an epoxy, flipping the wafer again, thinning the flipped wafer, etching a buried oxide layer from the wafer and etching the sacrificial layer from the wafer. The result is a wafer having superconductive circuitry on both sides of an ultra-thin silicon layer.

Read disturb errors in a CMOS static RAM chip. [radiation hardened for spacedraft

NASA Technical Reports Server (NTRS)

Wood, Steven H.; Marr, James C., IV; Nguyen, Tien T.; Padgett, Dwayne J.; Tran, Joe C.; Griswold, Thomas W.; Lebowitz, Daniel C.

1989-01-01

Results are reported from an extensive investigation into pattern-sensitive soft errors (read disturb errors) in the TCC244 CMOS static RAM chip. The TCC244, also known as the SA2838, is a radiation-hard single-event-upset-resistant 4 x 256 memory chip. This device is being used by the Jet Propulsion Laboratory in the Galileo and Magellan spacecraft, which will have encounters with Jupiter and Venus, respectively. Two aspects of the part's design are shown to result in the occurrence of read disturb errors: the transparence of the signal path from the address pins to the array of cells, and the large resistance in the Vdd and Vss lines of the cells in the center of the array. Probe measurements taken during a read disturb failure illustrate how address skews and the data pattern in the chip combine to produce a bit flip. A capacitive charge pump formed by the individual cell capacitances and the resistance in the supply lines pumps down both the internal cell voltage and the local supply voltage until a bit flip occurs.

Tacky COC: a solvent bonding technique for fabrication of microfluidic systems

NASA Astrophysics Data System (ADS)

Keller, Nico; Nargang, Tobias M.; Helmer, Dorothea; Rapp, Bastian E.

2016-03-01

The academic community knows cyclic olefin copolymer (COC) as a well suited material for microfluidic applications because COC has numerous interesting properties such as high transmittance, good chemical resistance and good biocompatibility. Here we present a fast and cost-effective method for bonding of two COC substrates: exposure to appropriate solvents gives a tacky COC surface which when brought in contact with untreated COC forms a strong and optical clear bond. The bonding process is carried out at room temperature and takes less than three minutes which makes it significantly faster than currently described methods: This method does not require special lab equipment such as hot plates or hydraulic presses. The mild conditions of the bond process also allow for such "tacky COC" lids to be used for sealing of microfluidic chips containing immobilized protein patterns which is of high interest for immunodiagnostic testing inside microfluidic chips.

A fast and simple bonding method for low cost microfluidic chip fabrication

NASA Astrophysics Data System (ADS)

Yin, Zhifu; Zou, Helin

2018-01-01

With the development of the microstructure fabrication technique, microfluidic chips are widely used in biological and medical researchers. Future advances in their commercial applications depend on the mass bonding of microfluidic chip. In this study we are presenting a simple, low cost and fast way of bonding microfluidic chips at room temperature. The influence of the bonding pressure on the deformation of the microchannel and adhesive tape was analyzed by numerical simulation. By this method, the microfluidic chip can be fully sealed at low temperature and pressure without using any equipment. The dye water and gas leakage test indicated that the microfluidic chip can be bonded without leakage or block and its bonding strength can up to 0.84 MPa.

Effects of Solder Volume and Reflow Conditions on Self-Alignment Accuracy for Fan-Out Package Applications

NASA Astrophysics Data System (ADS)

Park, Hwan-Pil; Seo, Gwancheol; Kim, Sungchul; Kim, Young-Ho

2018-01-01

The effects of solder volume and reaction time between molten solder and a metal pad at the peak temperature of reflow on the self-alignment effect have been investigated in flip chip bonding. A glass die with two different pad designs and a flame retardant-4 (FR-4) organic substrate were used. Sn-3.0Ag-0.5Cu and Sn-3.5Ag solders were formed on Cu-organic solderability preservation (Cu-OSP) and electroless nickel electroless palladium immersion gold (ENEPIG) pads on FR-4 substrates using the stencil printing method. To assess the effect of solder volume, the thickness and opening size of the stencil mask were controlled. Reflow experiments were performed at 250°C with wetting times of 40 s, 55 s, 65 s, and 75 s. After flip chip reflow soldering, the bonding areas were cross-sectioned to inspect the shape of the interconnected solder using scanning electron microscopy. The results revealed that using an insufficient solder volume on the pad was responsible for die shifts larger than 1 μm, while a sufficient solder volume on the pad and a stable solder joint shape could ensure misalignment less than 1 μm. The Sn-3.0Ag-0.5Cu solder showed a lower die shift value than the Sn-3.5Ag solder because the Sn-3.0Ag-0.5Cu solder has stronger surface tension than the Sn-3.5Ag solder. Using a longer wetting time between the solder and the pad at the peak temperature also improved the die shift value because the increased reaction time changed the interconnected solder shape between the die and substrate from concave to convex, moving the die to a more accurate position. Furthermore, the restoring forces on die self-alignment influenced the die shift value. A stronger solder surface tension and a larger volume of solder on the pad produced stronger restoring forces for die self-alignment, thereby improving the die shift value.

High-Temperature High-Power Packaging Techniques for HEV Traction Applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Elshabini, Aicha; Barlow, Fred D.

A key issue associated with the wider adoption of hybrid-electric vehicles (HEV) and plug in hybrid-electric vehicles (PHEV) is the implementation of the power electronic systems that are required in these products. One of the primary industry goals is the reduction in the price of these vehicles relative to the cost of traditional gasoline powered vehicles. Today these systems, such as the Prius, utilize one coolant loop for the engine at approximately 100 C coolant temperatures, and a second coolant loop for the inverter at 65 C. One way in which significant cost reduction of these systems could be achievedmore » is through the use of a single coolant loop for both the power electronics as well as the internal combustion engine (ICE). This change in coolant temperature significantly increases the junction temperatures of the devices and creates a number of challenges for both device fabrication and the assembly of these devices into inverters and converters for HEV and PHEV applications. Traditional power modules and the state-of-the-art inverters in the current HEV products, are based on chip and wire assembly and direct bond copper (DBC) on ceramic substrates. While a shift to silicon carbide (SiC) devices from silicon (Si) devices would allow the higher operating temperatures required for a single coolant loop, it also creates a number of challenges for the assembly of these devices into power inverters. While this traditional packaging technology can be extended to higher temperatures, the key issues are the substrate material and conductor stability, die bonding material, wire bonds, and bond metallurgy reliability as well as encapsulation materials that are stable at high operating temperatures. The larger temperature differential during power cycling, which would be created by higher coolant temperatures, places tremendous stress on traditional aluminum wire bonds that are used to interconnect power devices. Selection of the bond metallurgy and wire bond geometry can play a key role in mitigating this stress. An alternative solution would be to eliminate the wire bonds completely through a fundamentally different method of forming a reliable top side interconnect. Similarly, the solders used in most power modules exhibit too low of a liquidus to be viable solutions for maximum junction temperatures of 200 C. Commonly used encapsulation materials, such as silicone gels, also suffer from an inability to operate at 200 C for extended periods of time. Possible solutions to these problems exist in most cases but require changes to the traditional manufacturing process used in these modules. In addition, a number of emerging technologies such as Si nitride, flip-chip assembly methods, and the elimination of base-plates would allow reliable module development for operation of HEV and PHEV inverters at elevated junction temperatures.« less

Toward more efficient fabrication of high-density 2-D VCSEL arrays for spatial redundancy and/or multi-level signal communication

NASA Astrophysics Data System (ADS)

Roscher, Hendrik; Gerlach, Philipp; Khan, Faisal Nadeem; Kroner, Andrea; Stach, Martin; Weigl, Alexander; Michalzik, Rainer

2006-04-01

We present flip-chip attached high-speed VCSELs in 2-D arrays with record-high intra-cell packing densities. The advances of VCSEL array technology toward improved thermal performance and more efficient fabrication are reviewed, and the introduction of self-aligned features to these devices is pointed out. The structure of close-spaced wedge-shaped VCSELs is discussed and their static and dynamic characteristics are presented including an examination of the modal structure by near-field measurements. The lasers flip-chip bonded to a silicon-based test platform exhibit 3-dB and 10-dB bandwidths of 7.7 GHz and 9.8 GHz, respectively. Open 12.5 Gbit/s two-level eye patterns are demonstrated. We discuss the uses of high packing densities for the increase of the total amount of data throughput an array can deliver in the course of its life. One such approach is to provide up to two backup VCSELs per fiber channel that can extend the lifetimes of parallel transmitters through redundancy of light sources. Another is to increase the information density by using multiple VCSELs per 50 μm core diameter multimode fiber to generate more complex signals. A novel scheme using three butt-coupled VCSELs per fiber for the generation of four-level signals in the optical domain is proposed. First experiments are demonstrated using two VCSELs butt-coupled to the same standard glass fiber, each modulated with two-level signals to produce four-level signals at the photoreceiver. A four-level direct modulation of one VCSEL within a triple of devices produced first 20.6 Gbit/s (10.3 Gsymbols/s) four-level eyes, leaving two VCSELs as backup sources.

Current crowding and self-heating effects in AlGaN-based flip-chip deep-ultraviolet light-emitting diodes

NASA Astrophysics Data System (ADS)

Hao, Guo-Dong; Taniguchi, Manabu; Tamari, Naoki; Inoue, Shin-ichiro

2018-01-01

We thoroughly explored the physical origin of the efficiency decrease with increasing injection current and current crowding effect in 280 nm AlGaN-based flip-chip deep-ultraviolet (DUV) light-emitting diodes (LEDs). The current spreading length was experimentally determined to be much smaller in DUV LEDs than that in conventional InGaN-based visible LEDs. The severe self-heating caused by the low power conversion efficiency of DUV LEDs should be mainly responsible for the considerable decrease of efficiency when current crowding is present. The wall-plug efficiency of the DUV LEDs was markedly enhanced by using a well-designed p-electrode pattern to improve the current distribution.

Effect of Al-trace dimension on Joule heating and current crowding in flip-chip solder joints under accelerated electromigration

NASA Astrophysics Data System (ADS)

Liang, S. W.; Chang, Y. W.; Chen, Chih

2006-04-01

Three-dimensional thermoelectrical simulation was conducted to investigate the influence of Al-trace dimension on Joule heating and current crowding in flip-chip solder joints. It is found that the dimension of the Al-trace effects significantly on the Joule heating, and thus directly determines the mean time to failure (MTTF). Simulated at a stressing current of 0.6A at 70°C, we estimate that the MTTF of the joints with Al traces in 100μm width was 6.1 times longer than that of joints with Al traces in 34μm width. Lower current crowding effect and reduced hot-spot temperature are responsible for the improved MTTF.

Progress on TSV technology for Medipix3RX chip

NASA Astrophysics Data System (ADS)

Sarajlić, M.; Pennicard, D.; Smoljanin, S.; Fritzsch, T.; Zoschke, K.; Graafsma, H.

2017-12-01

The progress of Through Silicon Via (TSV) technology for Medipix3RX chip done at DESY is presented here. The goal of this development is to replace the wire bonds in X-ray detectors with TSVs, in order to reduce the dead area between detectors. We obtained the first working chips assembled together with Si based sensors for X-ray detection. The 3D integration technology, including TSV, Re-distribution layer deposition, bump bonding to the Si sensor and bump bonding to the carrier PCB, was done by Fraunhofer Institute IZM in Berlin. After assembly, the module was successfully tested by recording background radiation and making X-ray images of small objects. The active area of the Medipix3RX chip is 14.1 mm×14.1 mm or 256×256 pixels. During TSV processing, the Medipix3RX chip was thinned from 775 μm original thickness, to 130 μm. The diameter of the vias is 40 μm, and the pitch between the vias is 120 μm. A liner filling approach was used to contact the TSV with the RDL on the backside of the Medipix3RX readout chip.

Semiconductor laser joint study program with Rome Laboratory

NASA Astrophysics Data System (ADS)

Schaff, William J.; Okeefe, Sean S.; Eastman, Lester F.

1994-09-01

A program to jointly study vertical-cavity surface emitting lasers (VCSEL) for high speed vertical optical interconnects (VOI) has been conducted under an ES&E between Rome Laboratory and Cornell University. Lasers were designed, grown, and fabricated at Cornell University. A VCSEL measurement laboratory has been designed, built, and utilized at Rome Laboratory. High quality VCSEL material was grown and characterized by fabricating conventional lateral cavity lasers that emitted at the design wavelength of 1.04 microns. The VCSEL's emit at 1.06 microns. Threshold currents of 16 mA at 4.8 volts were obtained for 30 microns diameter devices. Output powers of 5 mW were measured. This is 500 times higher power than from the light emitting diodes employed previously for vertical optical interconnects. A new form of compositional grading using a cosinusoidal function has been developed and is very successful for reducing diode series resistance for high speed interconnection applications. A flip-chip diamond package compatible with high speed operation of 16 VCSEL elements has been designed and characterized. A flip-chip device binding effort at Rome Laboratory was also designed and initiated. This report presents details of the one-year effort, including process recipes and results.

Pressure-Sensor Assembly Technique

NASA Technical Reports Server (NTRS)

Pruzan, Daniel A.

2003-01-01

Nielsen Engineering & Research (NEAR) recently developed an ultrathin data acquisition system for use in turbomachinery testing at NASA Glenn Research Center. This system integrates a microelectromechanical- systems- (MEMS-) based absolute pressure sensor [0 to 50 psia (0 to 345 kPa)], temperature sensor, signal-conditioning application-specific integrated circuit (ASIC), microprocessor, and digital memory into a package which is roughly 2.8 in. (7.1 cm) long by 0.75 in. (1.9 cm) wide. Each of these components is flip-chip attached to a thin, flexible circuit board and subsequently ground and polished to achieve a total system thickness of 0.006 in. (0.15 mm). Because this instrument is so thin, it can be quickly adhered to any surface of interest where data can be collected without disrupting the flow being investigated. One issue in the development of the ultrathin data acquisition system was how to attach the MEMS pressure sensor to the circuit board in a manner which allowed the sensor s diaphragm to communicate with the ambient fluid while providing enough support for the chip to survive the grinding and polishing operations. The technique, developed by NEAR and Jabil Technology Services Group (San Jose, CA), is described below. In the approach developed, the sensor is attached to the specially designed circuit board, see Figure 1, using a modified flip-chip technique. The circular diaphragm on the left side of the sensor is used to actively measure the ambient pressure, while the diaphragm on the right is used to compensate for changes in output due to temperature variations. The circuit board is fabricated with an access hole through it so that when the completed system is installed onto a wind tunnel model (chip side down), the active diaphragm is exposed to the environment. After the sensor is flip-chip attached to the circuit board, the die is underfilled to support the chip during the subsequent grinding and polishing operations. To prevent this underfill material from getting onto the sensor s diaphragms, the circuit board is fabricated with two 25- micrometer-tall polymer rings, sized so that the diaphragms fit inside the rings once the chip is attached.

High-Sensitivity Low-Noise Miniature Fluxgate Magnetometers Using a Flip Chip Conceptual Design

PubMed Central

Lu, Chih-Cheng; Huang, Jeff; Chiu, Po-Kai; Chiu, Shih-Liang; Jeng, Jen-Tzong

2014-01-01

This paper presents a novel class of miniature fluxgate magnetometers fabricated on a print circuit board (PCB) substrate and electrically connected to each other similar to the current “flip chip” concept in semiconductor package. This sensor is soldered together by reversely flipping a 5 cm × 3 cm PCB substrate to the other identical one which includes dual magnetic cores, planar pick-up coils, and 3-D excitation coils constructed by planar Cu interconnections patterned on PCB substrates. Principles and analysis of the fluxgate sensor are introduced first, and followed by FEA electromagnetic modeling and simulation for the proposed sensor. Comprehensive characteristic experiments of the miniature fluxgate device exhibit favorable results in terms of sensitivity (or “responsivity” for magnetometers) and field noise spectrum. The sensor is driven and characterized by employing the improved second-harmonic detection technique that enables linear V-B correlation and responsivity verification. In addition, the double magnitude of responsivity measured under very low frequency (1 Hz) magnetic fields is experimentally demonstrated. As a result, the maximum responsivity of 593 V/T occurs at 50 kHz of excitation frequency with the second harmonic wave of excitation; however, the minimum magnetic field noise is found to be 0.05 nT/Hz1/2 at 1 Hz under the same excitation. In comparison with other miniature planar fluxgates published to date, the fluxgate magnetic sensor with flip chip configuration offers advances in both device functionality and fabrication simplicity. More importantly, the novel design can be further extended to a silicon-based micro-fluxgate chip manufactured by emerging CMOS-MEMS technologies, thus enriching its potential range of applications in modern engineering and the consumer electronics market. PMID:25196107

3D MOEMS-based optical micro-bench platform for the miniaturization of sensing devices

NASA Astrophysics Data System (ADS)

Garcia-Blanco, Sonia; Caron, Jean-Sol; Leclair, Sébastien; Topart, Patrice A.; Jerominek, Hubert

2008-02-01

As we enter into the 21st century, the need for miniaturized portable diagnostic devices is increasing continuously. Portable devices find important applications for point-of-care diagnostics, patient self-monitoring and in remote areas, such as unpopulated regions where the cost of large laboratory facilities is not justifiable, underdeveloped countries and other remote locations such as space missions. The advantage of miniaturized sensing optical systems includes not only the reduced weight and size but also reduced cost, decreased time to results and robustness (e.g. no need for frequent re-alignments). Recent advances in micro-fabrication and assembly technologies have enabled important developments in the field of miniaturized sensing systems. INO has developed a technology platform for the three dimensional integration of MOEMS on an optical microbench. Building blocks of the platform include microlenses, micromirrors, dichroic beamsplitters, filters and optical fibers, which can be positioned using passive alignment structures to build the desired miniaturised system. The technology involves standard microfabrication, thick resist UV-lithography, thick metal electroplating, soldering, replication in sol-gel materials and flip-chip bonding processes. The technology is compatible with wafer-to-wafer bonding. A placement accuracy of +/- 5 μm has been demonstrated thanks to the integration of alignment marks co registered with other optical elements fabricated on different wafers. In this paper, the building blocks of the technology will be detailed. The design and fabrication of a 5x5 channels light processing unit including optical fibers, mirrors and collimating microlenses will be described. Application of the technology to various kinds of sensing devices will be discussed.

Synthesis, Structure, and Conformational Dynamics of Rhodium and Iridium Complexes of Dimethylbis(2-pyridyl)borate.

PubMed

Pennington-Boggio, Megan K; Conley, Brian L; Richmond, Michael G; Williams, Travis J

2014-12-14

Rhodium(I) and Iridium(I) borate complexes of the structure [Me 2 B(2-py) 2 ]ML 2 (L 2 = (tBuNC) 2 , (CO) 2 , (C 2 H 4 ) 2 , cod, dppe) were prepared and structurally characterized (cod = 1,5-cyclooctadiene; dppe = 1,2-diphenylphosphinoethane). Each contains a boat-configured chelate ring that participates in a boat-to-boat ring flip. Computational evidence shows that the ring flip proceeds through a transition state that is near planarity about the chelate ring. We observe an empirical, quantitative correlation between the barrier of this ring flip and the π acceptor ability of the ancillary ligand groups on the metal. The ring flip barrier correlates weakly to the Tolman and Lever ligand parameterization schemes, apparently because these combine both σ and π effects while we propose that the ring flip barrier is dominated by π bonding. This observation is consistent with metal-ligand π interactions becoming temporarily available only in the near-planar transition state of the chelate ring flip and not the boat-configured ground state. Thus, this is a first-of-class observation of metal-ligand π bonding governing conformational dynamics.

Synthesis, Structure, and Conformational Dynamics of Rhodium and Iridium Complexes of Dimethylbis(2-pyridyl)borate†

PubMed Central

Pennington-Boggio, Megan K.; Conley, Brian L.; Richmond, Michael G.; Williams, Travis J.

2014-01-01

Rhodium(I) and Iridium(I) borate complexes of the structure [Me2B(2-py)2]ML2 (L2 = (tBuNC)2, (CO)2, (C2H4)2, cod, dppe) were prepared and structurally characterized (cod = 1,5-cyclooctadiene; dppe = 1,2-diphenylphosphinoethane). Each contains a boat-configured chelate ring that participates in a boat-to-boat ring flip. Computational evidence shows that the ring flip proceeds through a transition state that is near planarity about the chelate ring. We observe an empirical, quantitative correlation between the barrier of this ring flip and the π acceptor ability of the ancillary ligand groups on the metal. The ring flip barrier correlates weakly to the Tolman and Lever ligand parameterization schemes, apparently because these combine both σ and π effects while we propose that the ring flip barrier is dominated by π bonding. This observation is consistent with metal-ligand π interactions becoming temporarily available only in the near-planar transition state of the chelate ring flip and not the boat-configured ground state. Thus, this is a first-of-class observation of metal-ligand π bonding governing conformational dynamics. PMID:25435645

Design and process development of a photonic crystal polymer biosensor for point-of-care diagnostics

NASA Astrophysics Data System (ADS)

Dortu, F.; Egger, H.; Kolari, K.; Haatainen, T.; Furjes, P.; Fekete, Z.; Bernier, D.; Sharp, G.; Lahiri, B.; Kurunczi, S.; Sanchez, J.-C.; Turck, N.; Petrik, P.; Patko, D.; Horvath, R.; Eiden, S.; Aalto, T.; Watts, S.; Johnson, N. P.; De La Rue, R. M.; Giannone, D.

2011-07-01

In this work, we report advances in the fabrication and anticipated performance of a polymer biosensor photonic chip developed in the European Union project P3SENS (FP7-ICT4-248304). Due to the low cost requirements of point-ofcare applications, the photonic chip is fabricated from nanocomposite polymeric materials, using highly scalable nanoimprint- lithography (NIL). A suitable microfluidic structure transporting the analyte solutions to the sensor area is also fabricated in polymer and adequately bonded to the photonic chip. We first discuss the design and the simulated performance of a high-Q resonant cavity photonic crystal sensor made of a high refractive index polyimide core waveguide on a low index polymer cladding. We then report the advances in doped and undoped polymer thin film processing and characterization for fabricating the photonic sensor chip. Finally the development of the microfluidic chip is presented in details, including the characterisation of the fluidic behaviour, the technological and material aspects of the 3D polymer structuring and the stable adhesion strategies for bonding the fluidic and the photonic chips, with regards to the constraints imposed by the bioreceptors supposedly already present on the sensors.

Characterizations of Rapid Sintered Nanosilver Joint for Attaching Power Chips

PubMed Central

Feng, Shuang-Tao; Mei, Yun-Hui; Chen, Gang; Li, Xin; Lu, Guo-Quan

2016-01-01

Sintering of nanosilver paste has been extensively studied as a lead-free die-attach solution for bonding semiconductor power chips, such as the power insulated gated bipolar transistor (IGBT). However, for the traditional method of bonding IGBT chips, an external pressure of a few MPa is reported necessary for the sintering time of ~1 h. In order to shorten the processing duration time, we developed a rapid way to sinter nanosilver paste for bonding IGBT chips in less than 5 min using pulsed current. In this way, we firstly dried as-printed paste at about 100 °C to get rid of many volatile solvents because they may result in defects or voids during the out-gassing from the paste. Then, the pre-dried paste was further heated by pulse current ranging from 1.2 kA to 2.4 kA for several seconds. The whole procedure was less than 3 min and did not require any gas protection. We could obtain robust sintered joint with shear strength of 30–35 MPa for bonding 1200-V, 25-A IGBT and superior thermal properties. Static and dynamic electrical performance of the as-bonded IGBT assemblies was also characterized to verify the feasibility of this rapid sintering method. The results indicate that the electrical performance is comparable or even partially better than that of commercial IGBT modules. The microstructure evolution of the rapid sintered joints was also studied by scanning electron microscopy (SEM). This work may benefit the wide usage of nanosilver paste for rapid bonding IGBT chips in the future. PMID:28773686

Characterizations of Rapid Sintered Nanosilver Joint for Attaching Power Chips.

PubMed

Feng, Shuang-Tao; Mei, Yun-Hui; Chen, Gang; Li, Xin; Lu, Guo-Quan

2016-07-12

Sintering of nanosilver paste has been extensively studied as a lead-free die-attach solution for bonding semiconductor power chips, such as the power insulated gated bipolar transistor (IGBT). However, for the traditional method of bonding IGBT chips, an external pressure of a few MPa is reported necessary for the sintering time of ~1 h. In order to shorten the processing duration time, we developed a rapid way to sinter nanosilver paste for bonding IGBT chips in less than 5 min using pulsed current. In this way, we firstly dried as-printed paste at about 100 °C to get rid of many volatile solvents because they may result in defects or voids during the out-gassing from the paste. Then, the pre-dried paste was further heated by pulse current ranging from 1.2 kA to 2.4 kA for several seconds. The whole procedure was less than 3 min and did not require any gas protection. We could obtain robust sintered joint with shear strength of 30-35 MPa for bonding 1200-V, 25-A IGBT and superior thermal properties. Static and dynamic electrical performance of the as-bonded IGBT assemblies was also characterized to verify the feasibility of this rapid sintering method. The results indicate that the electrical performance is comparable or even partially better than that of commercial IGBT modules. The microstructure evolution of the rapid sintered joints was also studied by scanning electron microscopy (SEM). This work may benefit the wide usage of nanosilver paste for rapid bonding IGBT chips in the future.

Cost-effective method of manufacturing a 3D MEMS optical switch

NASA Astrophysics Data System (ADS)

Carr, Emily; Zhang, Ping; Keebaugh, Doug; Chau, Kelvin

2009-02-01

growth of data and video transport networks. All-optical switching eliminates the need for optical-electrical conversion offering the ability to switch optical signals transparently: independent of data rates, formats and wavelength. It also provides network operators much needed automation capabilities to create, monitor and protect optical light paths. To further accelerate the market penetration, it is necessary to identify a path to reduce the manufacturing cost significantly as well as enhance the overall system performance, uniformity and reliability. Currently, most MEMS optical switches are assembled through die level flip-chip bonding with either epoxies or solder bumps. This is due to the alignment accuracy requirements of the switch assembly, defect matching of individual die, and cost of the individual components. In this paper, a wafer level assembly approach is reported based on silicon fusion bonding which aims to reduce the packaging time, defect count and cost through volume production. This approach is successfully demonstrated by the integration of two 6-inch wafers: a mirror array wafer and a "snap-guard" wafer, which provides a mechanical structure on top of the micromirror to prevent electrostatic snap-down. The direct silicon-to-silicon bond eliminates the CTEmismatch and stress issues caused by non-silicon bonding agents. Results from a completed integrated switch assembly will be presented, which demonstrates the reliability and uniformity of some key parameters of this MEMS optical switch.

A new on-chip all-digital three-phase full-bridge dc/ac power inverter with feedforward and frequency control techniques.

PubMed

Chen, Jiann-Jong; Kung, Che-Min

2010-09-01

The communication speed between components is far from satisfactory. To achieve high speed, simple control system configuration, and low cost, a new on-chip all-digital three-phase dc/ac power inverter using feedforward and frequency control techniques is proposed. The controller of the proposed power inverter, called the shift register, consists of six-stage D-latch flip-flops with a goal of achieving low-power consumption and area efficiency. Variable frequency is achieved by controlling the clocks of the shift register. One advantage regarding the data signal (D) and the common clock (CK) is that, regardless of the phase difference between the two, all of the D-latch flip-flops are capable of delaying data by one CK period. To ensure stability, the frequency of CK must be six times higher than that of D. The operation frequency of the proposed power inverter ranges from 10 Hz to 2 MHz, and the maximum output loading current is 0.8 A. The prototype of the proposed circuit has been fabricated with TSMC 0.35 μm 2P4M CMOS processes. The total chip area is 2.333 x 1.698 mm2. The three-phase dc/ac power inverter is applicable in uninterrupted power supplies, cold cathode fluorescent lamps, and motors, because of its ability to convert the dc supply voltage into the three-phase ac power sources.

Biwavelength transceiver module for parallel simultaneous bidirectional optical interconnections

NASA Astrophysics Data System (ADS)

Nguyen, Nga T. H.; Ukaegbu, Ikechi A.; Sangirov, Jamshid; Cho, Mu-Hee; Lee, Tae-Woo; Park, Hyo-Hoon

2013-12-01

The design of a biwavelength transceiver (TRx) module for parallel simultaneous bidirectional optical interconnects is described. The TRx module has been implemented using two different wavelengths, 850 and 1060 nm, to send and receive signals simultaneously through a common optical interface while optimizing cost and performance. Filtering mirrors are formed in the optical fibers which are embedded on a V-grooved silicon substrate for reflecting and filtering optical signals from/to vertical-cavity surface-emitting laser (VCSEL)/photodiode (PD). The VCSEL and PD are flip-chip bonded on individual silicon optical benches, which are attached on the silicon substrate for optical signal coupling from the VCSEL to fiber and from fiber to the PD. A high-speed and low-loss ceramic printed circuit board, which has a compact size of 0.033 cc, has been designed to carry transmitter and receiver chips for easy packaging of the TRx module. Applied for quad small form-factor pluggable applications at 40-Gbps operation, the four-channel biwavelength TRx module showed clear eye diagrams with a bit error rate (BER) of 10-12 at input powers of -5 and -5.8 dBm for 1060 and 850 nm operation modes, respectively.

Miniaturized tool for optogenetics based on an LED and an optical fiber interfaced by a silicon housing.

PubMed

Schwaerzle, M; Elmlinger, P; Paul, O; Ruther, P

2014-01-01

This paper reports on the design, simulation, fabrication and characterization of a tool for optogenetic experiments based on a light emitting diode (LED). A minimized silicon (Si) interface houses the LED and aligns it to an optical fiber. With a Si housing size of 550×500×380 μm(3) and an electrical interconnection of the LED by a highly flexible polyimide (PI) ribbon cable is the system very variable. PI cables and Si housings are fabricated using established microsystem technologies. A 270×220×50 μm(3) bare LED chip is flip-chip-bonded onto the PI cable. The Si housing is adhesively attached to the PI cable, thereby hosting the LED in a recess. An opposite recess guides the optical fiber with a diameter of 125 μm. An aperture in-between restricts the emitted LED light to the fiber core. The optical fiber is adhesively fixed into the Si housing recess. An optical output intensity at the fiber end facet of 1.71 mW/mm(2) was achieved at a duty cycle of 10 % and a driving current of 30 mA.

Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

NASA Astrophysics Data System (ADS)

Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

2001-11-01

The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

Fabrication of a microfluidic chip by UV bonding at room temperature for integration of temperature-sensitive layers

NASA Astrophysics Data System (ADS)

Schlautmann, S.; Besselink, G. A. J.; Radhakrishna Prabhu, G.; Schasfoort, R. B. M.

2003-07-01

A method for the bonding of a microfluidic device at room temperature is presented. The wafer with the fluidic structures was bonded to a sensor wafer with gold pads by means of adhesive bonding, utilizing an UV-curable glue layer. To avoid filling the fluidic channels with the glue, a stamping process was developed which allows the selective application of a thin glue layer. In this way a microfluidic glass chip was fabricated that could be used for performing surface plasmon resonance measurements without signs of leakage. The advantage of this method is the possibility of integration of organic layers as well as other temperature-sensitive layers into a microfluidic glass device.

Self-Patterning of Silica/Epoxy Nanocomposite Underfill by Tailored Hydrophilic-Superhydrophobic Surfaces for 3D Integrated Circuit (IC) Stacking.

PubMed

Tuan, Chia-Chi; James, Nathan Pataki; Lin, Ziyin; Chen, Yun; Liu, Yan; Moon, Kyoung-Sik; Li, Zhuo; Wong, C P

2017-03-15

As microelectronics are trending toward smaller packages and integrated circuit (IC) stacks nowadays, underfill, the polymer composite filled in between the IC chip and the substrate, becomes increasingly important for interconnection reliability. However, traditional underfills cannot meet the requirements for low-profile and fine pitch in high density IC stacking packages. Post-applied underfills have difficulties in flowing into the small gaps between the chip and the substrate, while pre-applied underfills face filler entrapment at bond pads. In this report, we present a self-patterning underfilling technology that uses selective wetting of underfill on Cu bond pads and Si 3 N 4 passivation via surface energy engineering. This novel process, fully compatible with the conventional underfilling process, eliminates the issue of filler entrapment in typical pre-applied underfilling process, enabling high density and fine pitch IC die bonding.

Route to one-step microstructure mold fabrication for PDMS microfluidic chip

NASA Astrophysics Data System (ADS)

Lv, Xiaoqing; Geng, Zhaoxin; Fan, Zhiyuan; Wang, Shicai; Su, Yue; Fang, Weihao; Pei, Weihua; Chen, Hongda

2018-04-01

The microstructure mold fabrication for PDMS microfluidic chip remains complex and time-consuming process requiring special equipment and protocols: photolithography and etching. Thus, a rapid and cost-effective method is highly needed. Comparing with the traditional microfluidic chip fabricating process based on the micro-electromechanical system (MEMS), this method is simple and easy to implement, and the whole fabrication process only requires 1-2 h. Different size of microstructure from 100 to 1000 μm was fabricated, and used to culture four kinds of breast cancer cell lines. Cell viability and morphology was assessed when they were cultured in the micro straight channels, micro square holes and the bonding PDMS-glass microfluidic chip. The experimental results indicate that the microfluidic chip is good and meet the experimental requirements. This method can greatly reduce the process time and cost of the microfluidic chip, and provide a simple and effective way for the structure design and in the field of biological microfabrications and microfluidic chips.

Overview of the Design, Fabrication and Performance Requirements of Micro-Spec, an Integrated Submillimeter Spectrometer

NASA Technical Reports Server (NTRS)

Barrentine, Emily M.; Noroozian, Omid; Brown, Ari D.; Cataldo, Giuseppe; Ehsan, Negar; Hsieh, Wen-Ting; Stevenson, Thomas R.; U-Yen, Kongpop; Wollack, Edward J.; Moseley, S. Harvey

2015-01-01

Micro-Spec is a compact submillimeter (350-700 GHz) spectrometer which uses low loss superconducting niobium microstrip transmission lines and a single-crystal silicon dielectric to integrate all of the components of a grating-analog spectrometer onto a single chip. Here we present details of the fabrication and design of a prototype Micro-Spec spectrometer with resolution, R64, where we use a high-yield single-flip wafer bonding process to realize instrument components on a 0.45 m single-crystal silicon dielectric. We discuss some of the electromagnetic design concerns (such as loss, stray-light, cross-talk, and fabrication tolerances) for each of the spectrometer components and their integration into the instrument as a whole. These components include a slot antenna with a silicon lens for optical coupling, a phase delay transmission line network, parallel plate waveguide interference region, and aluminum microstrip transmission line kinetic inductance detectors with extremely low cross-talk and immunity to stray light. We have demonstrated this prototype spectrometer with design resolution of R64. Given the optical performance of this prototype, we will also discuss the extension of this design to higher resolutions suitable for balloon-flight.

Pressure driven digital logic in PDMS based microfluidic devices fabricated by multilayer soft lithography.

PubMed

Devaraju, Naga Sai Gopi K; Unger, Marc A

2012-11-21

Advances in microfluidics now allow an unprecedented level of parallelization and integration of biochemical reactions. However, one challenge still faced by the field has been the complexity and cost of the control hardware: one external pressure signal has been required for each independently actuated set of valves on chip. Using a simple post-modification to the multilayer soft lithography fabrication process, we present a new implementation of digital fluidic logic fully analogous to electronic logic with significant performance advances over the previous implementations. We demonstrate a novel normally closed static gain valve capable of modulating pressure signals in a fashion analogous to an electronic transistor. We utilize these valves to build complex fluidic logic circuits capable of arbitrary control of flows by processing binary input signals (pressure (1) and atmosphere (0)). We demonstrate logic gates and devices including NOT, NAND and NOR gates, bi-stable flip-flops, gated flip-flops (latches), oscillators, self-driven peristaltic pumps, delay flip-flops, and a 12-bit shift register built using static gain valves. This fluidic logic shows cascade-ability, feedback, programmability, bi-stability, and autonomous control capability. This implementation of fluidic logic yields significantly smaller devices, higher clock rates, simple designs, easy fabrication, and integration into MSL microfluidics.

Dense Vertically Aligned Copper Nanowire Composites as High Performance Thermal Interface Materials.

PubMed

Barako, Michael T; Isaacson, Scott G; Lian, Feifei; Pop, Eric; Dauskardt, Reinhold H; Goodson, Kenneth E; Tice, Jesse

2017-12-06

Thermal interface materials (TIMs) are essential for managing heat in modern electronics, and nanocomposite TIMs can offer critical improvements. Here, we demonstrate thermally conductive, mechanically compliant TIMs based on dense, vertically aligned copper nanowires (CuNWs) embedded into polymer matrices. We evaluate the thermal and mechanical characteristics of 20-25% dense CuNW arrays with and without polydimethylsiloxane infiltration. The thermal resistance achieved is below 5 mm 2 K W -1 , over an order of magnitude lower than commercial heat sink compounds. Nanoindentation reveals that the nonlinear deformation mechanics of this TIM are influenced by both the CuNW morphology and the polymer matrix. We also implement a flip-chip bonding protocol to directly attach CuNW composites to copper surfaces, as required in many thermal architectures. Thus, we demonstrate a rational design strategy for nanocomposite TIMs that simultaneously retain the high thermal conductivity of aligned CuNWs and the mechanical compliance of a polymer.

An analysis of the pull strength behaviors of fine-pitch, flip chip solder interconnections using a Au-Pt-Pd thick film conductor on Low-Temperature, Co-fired Ceramic (LTCC) substrates.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Uribe, Fernando R.; Kilgo, Alice C.; Grazier, John Mark

2008-09-01

The assembly of the BDYE detector requires the attachment of sixteen silicon (Si) processor dice (eight on the top side; eight on the bottom side) onto a low-temperature, co-fired ceramic (LTCC) substrate using 63Sn-37Pb (wt.%, Sn-Pb) in a double-reflow soldering process (nitrogen). There are 132 solder joints per die. The bond pads were gold-platinum-palladium (71Au-26Pt-3Pd, wt.%) thick film layers fired onto the LTCC in a post-process sequence. The pull strength and failure modes provided the quality metrics for the Sn-Pb solder joints. Pull strengths were measured in both the as-fabricated condition and after exposure to thermal cycling (-55/125 C; 15more » min hold times; 20 cycles). Extremely low pull strengths--referred to as the low pull strength phenomenon--were observed intermittently throughout the product build, resulting in added program costs, schedule delays, and a long-term reliability concern for the detector. There was no statistically significant correlation between the low pull strength phenomenon and (1) the LTCC 'sub-floor' lot; (2) grit blasting the LTCC surfaces prior to the post-process steps; (3) the post-process parameters; (4) the conductor pad height (thickness); (5) the dice soldering assembly sequence; or (5) the dice pull test sequence. Formation of an intermetallic compound (IMC)/LTCC interface caused by thick film consumption during either the soldering process or by solid-state IMC formation was not directly responsible for the low-strength phenomenon. Metallographic cross sections of solder joints from dice that exhibited the low pull strength behavior, revealed the presence of a reaction layer resulting from an interaction between Sn from the molten Sn-Pb and the glassy phase at the TKN/LTCC interface. The thick film porosity did not contribute, explicitly, to the occurrence of reaction layer. Rather, the process of printing the very thin conductor pads was too sensitive to minor thixotropic changes to ink, which resulted in inconsistent proportions of metal and glassy phase particles present during the subsequent firing process. The consequences were subtle, intermittent changes to the thick film microstructure that gave rise to the reaction layer and, thus, the low pull strength phenomenon. A mitigation strategy would be the use of physical vapor deposition (PVD) techniques to create thin film bond pads; this is multi-chip module, deposited (MCM-D) technology.« less

Ultrafast all-optical flip-flop based on passive micro Sagnac waveguide ring with photonic crystal fiber.

PubMed

Xu, Ming; Yang, Wan; Hong, Tao; Kang, TangZhen; Ji, JianHua; Wang, Ke

2017-06-01

Ultrafast all-optical flip-flop based on a passive micro Sagnac waveguide ring is studied through theoretical analysis and numerical simulation in this paper. The types of D, R-S, J-K, and T flip-flop are designed by controlling the cross-phase modulation effect of lights in this special microring. The high nonlinearity of the hollow-core photonic crystal fiber is implanted on a chip to shorten the length of the ring and reduce input power. By sensible management, the pulse width ratio of the input and the control signal, problems of pulse narrowing, and residual pedestal at the out port are solved. The parameters affecting the performance of flip-flops are optimized. The results show that the all-optical flip-flops have stable performance, low power consumption, high transmission rate (up to 100  Gb/s), and response time in picosecond order. The small size microwaveguide structure is suitable for photonic integration.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Videla, Pablo E.; Rossky, Peter J.; Laria, D., E-mail: dhlaria@cnea.gov.ar

We present results of ring polymer molecular dynamics simulations that shed light on the effects of nuclear quantum fluctuations on tunneling motions in cyclic [H{sub 2}O]{sub 3} and [D{sub 2}O]{sub 3}, at the representative temperature of T = 75 K. In particular, we focus attention on free energies associated with two key isomerization processes: The first one corresponds to flipping transitions of dangling OH bonds, between up and down positions with respect to the O–O–O plane of the cluster; the second involves the interchange between connecting and dangling hydrogen bond character of the H-atoms in a tagged water molecule. Zeromore » point energy and tunneling effects lead to sensible reductions of the free energy barriers. Due to the lighter nature of the H nuclei, these modifications are more marked in [H{sub 2}O]{sub 3} than in [D{sub 2}O]{sub 3}. Estimates of the characteristic time scales describing the flipping transitions are consistent with those predicted based on standard transition-state-approximation arguments.« less

Communication: Isotopic effects on tunneling motions in the water trimer.

PubMed

Videla, Pablo E; Rossky, Peter J; Laria, D

2016-02-14

We present results of ring polymer molecular dynamics simulations that shed light on the effects of nuclear quantum fluctuations on tunneling motions in cyclic [H2O]3 and [D2O]3, at the representative temperature of T = 75 K. In particular, we focus attention on free energies associated with two key isomerization processes: The first one corresponds to flipping transitions of dangling OH bonds, between up and down positions with respect to the O-O-O plane of the cluster; the second involves the interchange between connecting and dangling hydrogen bond character of the H-atoms in a tagged water molecule. Zero point energy and tunneling effects lead to sensible reductions of the free energy barriers. Due to the lighter nature of the H nuclei, these modifications are more marked in [H2O]3 than in [D2O]3. Estimates of the characteristic time scales describing the flipping transitions are consistent with those predicted based on standard transition-state-approximation arguments.

Three dimensional, multi-chip module

DOEpatents

Bernhardt, A.F.; Petersen, R.W.

1993-08-31

A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow dummy chips'' are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned on the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

Three dimensional, multi-chip module

DOEpatents

Bernhardt, Anthony F.; Petersen, Robert W.

1993-01-01

A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow "dummy chips" are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned o the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

Mitigating leakage errors due to cavity modes in a superconducting quantum computer

NASA Astrophysics Data System (ADS)

McConkey, T. G.; Béjanin, J. H.; Earnest, C. T.; McRae, C. R. H.; Pagel, Z.; Rinehart, J. R.; Mariantoni, M.

2018-07-01

A practical quantum computer requires quantum bit (qubit) operations with low error probabilities in extensible architectures. We study a packaging method that makes it possible to address hundreds of superconducting qubits by means of coaxial Pogo pins. A qubit chip is housed in a superconducting box, where both box and chip dimensions lead to unwanted modes that can interfere with qubit operations. We analyze these interference effects in the context of qubit coherent leakage and qubit decoherence induced by damped modes. We propose two methods, half-wave fencing and antinode pinning, to mitigate the resulting errors by detuning the resonance frequency of the modes from the qubit frequency. We perform electromagnetic field simulations indicating that the resonance frequency of the modes increases with the number of installed pins and can be engineered to be significantly higher than the highest qubit frequency. We estimate that the error probabilities and decoherence rates due to suitably shifted modes in realistic scenarios can be up to two orders of magnitude lower than the state-of-the-art superconducting qubit error and decoherence rates. Our methods can be extended to different types of packages that do not rely on Pogo pins. Conductive bump bonds, for example, can serve the same purpose in qubit architectures based on flip chip technology. Metalized vias, instead, can be used to mitigate modes due to the increasing size of the dielectric substrate on which qubit arrays are patterned.

Chip-to-chip interconnects based on 3D stacking of optoelectrical dies on Si

NASA Astrophysics Data System (ADS)

Duan, P.; Raz, O.; Smalbrugge, B. E.; Duis, J.; Dorren, H. J. S.

2012-01-01

We demonstrate a new approach to increase the optical interconnection bandwidth density by stacking the opto-electrical dies directly on the CMOS driver. The suggested implementation is aiming to provide a wafer scale process which will make the use of wire bonding redundant and will allow for impedance matched metallic wiring between the electronic driving circuit and its opto-electronic counter part. We suggest the use of a thick photoresist ramp between CMOS driver and opto-electrical dies surface as the bridge for supporting co-plannar waveguides (CPW) electrically plated with lithographic accuracy. In this way all three dimensions of the interconnecting metal layer, width, length and thickness can be completely controlled. In this 1st demonstration all processing is done on commercially available devices and products, and is compatible with CMOS processing technology. To test the applicability of CPW instead of wire bonds for interconnecting the CMOS circuit and opto-electronic chips, we have made test samples and tested their performance at speeds up to 10 Gbps. In this demonstration, a silicon substrate was used on which we evaporated gold co-planar waveguides (CPW) to mimic a wire on the driver. An optical link consisting of a VCSEL chip and a photodiode chip has been assembled and fully characterized using optical coupling into and out of a multimode fiber (MMF). A 10 Gb/s 27-1 NRZ PRBS signal transmitted from one chip to another chip was detected error free. A 4 dB receiver sensitivity penalty is measured for the integrated device compared to a commercial link.

Design, processing and testing of LSI arrays, hybrid microelectronics task

NASA Technical Reports Server (NTRS)

Himmel, R. P.; Stuhlbarg, S. M.; Ravetti, R. G.; Zulueta, P. J.; Rothrock, C. W.

1979-01-01

Mathematical cost models previously developed for hybrid microelectronic subsystems were refined and expanded. Rework terms related to substrate fabrication, nonrecurring developmental and manufacturing operations, and prototype production are included. Sample computer programs were written to demonstrate hybrid microelectric applications of these cost models. Computer programs were generated to calculate and analyze values for the total microelectronics costs. Large scale integrated (LST) chips utilizing tape chip carrier technology were studied. The feasibility of interconnecting arrays of LSU chips utilizing tape chip carrier and semiautomatic wire bonding technology was demonstrated.

Electronic Switch Arrays for Managing Microbattery Arrays

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Alahmad, Mahmoud; Sukumar, Vinesh; Zghoul, Fadi; Buck, Kevin; Hess, Herbert; Li, Harry; Cox, David

2008-01-01

Integrated circuits have been invented for managing the charging and discharging of such advanced miniature energy-storage devices as planar arrays of microscopic energy-storage elements [typically, microscopic electrochemical cells (microbatteries) or microcapacitors]. The architecture of these circuits enables implementation of the following energy-management options: dynamic configuration of the elements of an array into a series or parallel combination of banks (subarrarys), each array comprising a series of parallel combination of elements; direct addressing of individual banks for charging/or discharging; and, disconnection of defective elements and corresponding reconfiguration of the rest of the array to utilize the remaining functional elements to obtain the desited voltage and current performance. An integrated circuit according to the invention consists partly of a planar array of field-effect transistors that function as switches for routing electric power among the energy-storage elements, the power source, and the load. To connect the energy-storage elements to the power source for charging, a specific subset of switches is closed; to connect the energy-storage elements to the load for discharging, a different specific set of switches is closed. Also included in the integrated circuit is circuitry for monitoring and controlling charging and discharging. The control and monitoring circuitry, the switching transistors, and interconnecting metal lines are laid out on the integrated-circuit chip in a pattern that registers with the array of energy-storage elements. There is a design option to either (1) fabricate the energy-storage elements in the corresponding locations on, and as an integral part of, this integrated circuit; or (2) following a flip-chip approach, fabricate the array of energy-storage elements on a separate integrated-circuit chip and then align and bond the two chips together.

Nanoparticle embedded p-type electrodes for GaN-based flip-chip light emitting diodes.

PubMed

Kwak, Joon Seop; Song, J O; Seong, T Y; Kim, B I; Cho, J; Sone, C; Park, Y

2006-11-01

We have investigated high-quality ohmic contacts for flip-chip light emitting diodes using Zn-Ni nanoparticles/Ag schemes. The Zn-Ni nanoparticles/Ag contacts produce specific contact resistances of 10(-5)-10(-6) omegacm2 when annealed at temperatures of 330-530 degrees C for 1 min in air ambient, which are much better than those obtained from the Ag contacts. It is shown that blue InGaN/GaN multi-quantum well light emitting diodes fabricated with the annealed Zn-Ni nanoparticles/Ag contacts give much lower forward-bias voltages at 20 mA compared with those of the multi-quantum well light emitting diodes made with the as-deposited Ag contacts. It is further presented that the multi-quantum well light emitting diodes made with the Zn-Ni nanoparticles/Ag contacts show similar output power compared to those fabricated with the Ag contact layers.

Flip-chip integrated silicon Mach-Zehnder modulator with a 28nm fully depleted silicon-on-insulator CMOS driver.

PubMed

Yong, Zheng; Shopov, Stefan; Mikkelsen, Jared C; Mallard, Robert; Mak, Jason C C; Voinigescu, Sorin P; Poon, Joyce K S

2017-03-20

We present a silicon electro-optic transmitter consisting of a 28nm ultra-thin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) CMOS driver flip-chip integrated onto a Mach-Zehnder modulator. The Mach-Zehnder silicon optical modulator was optimized to have a 3dB bandwidth of around 25 GHz at -1V bias and a 50 Ω impedance. The UTBB FD-SOI CMOS driver provided a large output voltage swing around 5 V_pp to enable a high dynamic extinction ratio and a low device insertion loss. At 44 Gbps, the transmitter achieved a high extinction ratio of 6.4 dB at the modulator quadrature operation point. This result shows open eye diagrams at the highest bit rates and with the largest extinction ratios for silicon electro-optic transmitter using a CMOS driver.

Effect of current crowding on whisker growth at the anode in flip chip solder joints

NASA Astrophysics Data System (ADS)

Ouyang, Fan-Yi; Chen, Kai; Tu, K. N.; Lai, Yi-Shao

2007-12-01

Owing to the line-to-bump configuration in flip chip solder joints, current crowding occurs when electrons enter into or exit from the solder bump. At the cathode contact, where electrons enter into the bump, current crowding induced pancake-type void formation has now been observed widely. At the anode contact, where electrons exit from the bump, we report here that whisker is formed. Results of both eutectic SnPb and SnAgCu solder joints are presented and compared. The cross-sectioned surface in SnPb showed dimple and bulge after electromigration, while that of SnAgCu remained flat. The difference is due to a larger back stress in the SnAgCu, consequently, electromigration in SnAgCu is slower than that in SnPb. Nanoindentation markers were used to measure the combined atomic fluxes of back stress and electromigration.

Microcircuit Device Reliability Digital Detailed Data

DTIC Science & Technology

1976-01-01

TYPE s No. FUNCTION A LASS PINS TEMP. TYPE CLASS LEVEL I eFAILED 8 NO. CHIP TEST APPL. TEST PAR1 t T AGATES PROTECT. DATE E:V. D TYPE HOURST :708 FLIP...LEVEL # EFAILED s a NO. t CHIP i TEST 3 APPL. a TEST I PAR! 3 a GATES s PROTECT. a DATE 3 ENV. t TYPE I 3 -OUHb s 354H0( 3 GATE C-I CDIP 14 150C :11.A

The fabrication of a double-layer atom chip with through silicon vias for an ultra-high-vacuum cell

NASA Astrophysics Data System (ADS)

Chuang, Ho-Chiao; Lin, Yun-Siang; Lin, Yu-Hsin; Huang, Chi-Sheng

2014-04-01

This study presents a double-layer atom chip that provides users with increased diversity in the design of the wire patterns and flexibility in the design of the magnetic field. It is more convenient for use in atomic physics experiments. A negative photoresist, SU-8, was used as the insulating layer between the upper and bottom copper wires. The electrical measurement results show that the upper and bottom wires with a width of 100 µm can sustain a 6 A current without burnout. Another focus of this study is the double-layer atom chips integrated with the through silicon via (TSV) technique, and anodically bonded to a Pyrex glass cell, which makes it a desired vacuum chamber for atomic physics experiments. Thus, the bonded glass cell not only significantly reduces the overall size of the ultra-high-vacuum (UHV) chamber but also conducts the high current from the backside to the front side of the atom chip via the TSV under UHV (9.5 × 10-10 Torr). The TSVs with a diameter of 70 µm were etched through by the inductively coupled plasma ion etching and filled by the bottom-up copper electroplating method. During the anodic bonding process, the electroplated copper wires and TSVs on atom chips also need to pass the examination of the required bonding temperature of 250 °C, under an applied voltage of 1000 V. Finally, the UHV test of the double-layer atom chips with TSVs at room temperature can be reached at 9.5 × 10-10 Torr, thus satisfying the requirements of atomic physics experiments under an UHV environment.

Automated Absorber Attachment for X-ray Microcalorimeter Arrays

NASA Technical Reports Server (NTRS)

Moseley, S.; Allen, Christine; Kilbourne, Caroline; Miller, Timothy M.; Costen, Nick; Schulte, Eric; Moseley, Samuel J.

2007-01-01

Our goal is to develop a method for the automated attachment of large numbers of absorber tiles to large format detector arrays. This development includes the fabrication of high quality, closely spaced HgTe absorber tiles that are properly positioned for pick-and-place by our FC150 flip chip bonder. The FC150 also transfers the appropriate minute amount of epoxy to the detectors for permanent attachment of the absorbers. The success of this development will replace an arduous, risky and highly manual task with a reliable, high-precision automated process.

Silicon ball grid array chip carrier

DOEpatents

Palmer, David W.; Gassman, Richard A.; Chu, Dahwey

2000-01-01

A ball-grid-array integrated circuit (IC) chip carrier formed from a silicon substrate is disclosed. The silicon ball-grid-array chip carrier is of particular use with ICs having peripheral bond pads which can be reconfigured to a ball-grid-array. The use of a semiconductor substrate such as silicon for forming the ball-grid-array chip carrier allows the chip carrier to be fabricated on an IC process line with, at least in part, standard IC processes. Additionally, the silicon chip carrier can include components such as transistors, resistors, capacitors, inductors and sensors to form a "smart" chip carrier which can provide added functionality and testability to one or more ICs mounted on the chip carrier. Types of functionality that can be provided on the "smart" chip carrier include boundary-scan cells, built-in test structures, signal conditioning circuitry, power conditioning circuitry, and a reconfiguration capability. The "smart" chip carrier can also be used to form specialized or application-specific ICs (ASICs) from conventional ICs. Types of sensors that can be included on the silicon ball-grid-array chip carrier include temperature sensors, pressure sensors, stress sensors, inertia or acceleration sensors, and/or chemical sensors. These sensors can be fabricated by IC processes and can include microelectromechanical (MEM) devices.

Low-temperature bonding process for the fabrication of hybrid glass-membrane organ-on-a-chip devices

NASA Astrophysics Data System (ADS)

Pocock, Kyall J.; Gao, Xiaofang; Wang, Chenxi; Priest, Craig; Prestidge, Clive A.; Mawatari, Kazuma; Kitamori, Takehiko; Thierry, Benjamin

2016-10-01

The integration of microfluidics with living biological systems has paved the way to the exciting concept of "organs-on-a-chip," which aims at the development of advanced in vitro models that replicate the key features of human organs. Glass-based devices have long been utilized in the field of microfluidics but the integration of alternative functional elements within multilayered glass microdevices, such as polymeric membranes, remains a challenge. To this end, we have extended a previously reported approach for the low-temperature bonding of glass devices that enables the integration of a functional polycarbonate porous membrane. The process was initially developed and optimized on specialty low-temperature bonding equipment (μTAS2001, Bondtech, Japan) and subsequently adapted to more widely accessible hot embosser units (EVG520HE Hot Embosser, EVG, Austria). The key aspect of this method is the use of low temperatures compatible with polymeric membranes. Compared to borosilicate glass bonding (650°C) and quartz/fused silica bonding (1050°C) processes, this method maintains the integrity and functionality of the membrane (Tg 150°C for polycarbonate). Leak tests performed showed no damage or loss of integrity of the membrane for up to 150 h, indicating sufficient bond strength for long-term cell culture. A feasibility study confirmed the growth of dense and functional monolayers of Caco-2 cells within 5 days.

Rapid bonding of Pyrex glass microchips.

PubMed

Akiyama, Yoshitake; Morishima, Keisuke; Kogi, Atsuna; Kikutani, Yoshikuni; Tokeshi, Manabu; Kitamori, Takehiko

2007-03-01

A newly developed vacuum hot press system has been specially designed for the thermal bonding of glass substrates in the fabrication process of Pyrex glass microchemical chips. This system includes a vacuum chamber equipped with a high-pressure piston cylinder and carbon plate heaters. A temperature of up to 900 degrees C and a force of as much as 9800 N could be applied to the substrates in a vacuum atmosphere. The Pyrex substrates bonded with this system under different temperatures, pressures, and heating times were evaluated by tensile strength tests, by measurements of thickness, and by observations of the cross-sectional shapes of the microchannels. The optimal bonding conditions of the Pyrex glass substrates were 570 degrees C for 10 min under 4.7 N/mm(2) of applied pressure. Whereas more than 16 h is required for thermal bonding with a conventional furnace, the new system could complete the whole bonding processes within just 79 min, including heating and cooling periods. Such improvements should considerably enhance the production rate of Pyrex glass microchemical chips. Whereas flat and dust-free surfaces are required for conventional thermal bonding, especially without long and repeated heating periods, our hot press system could press a fine dust into glass substrates so that even the areas around the dust were bonded. Using this capability, we were able to successfully integrate Pt/Ti thin film electrodes into a Pyrex glass microchip.

C-MOS array design techniques

NASA Technical Reports Server (NTRS)

Feller, A.

1978-01-01

The entire complement of standard cells and components, except for the set-reset flip-flop, was completed. Two levels of checking were performed on each device. Logic cells and topological layout are described. All the related computer programs were coded and one level of debugging was completed. The logic for the test chip was modified and updated. This test chip served as the first test vehicle to exercise the standard cell complementary MOS(C-MOS) automatic artwork generation capability.

Bonding prediction in friction stir consolidation of aluminum alloys: A preliminary study

NASA Astrophysics Data System (ADS)

Baffari, Dario; Reynolds, Anthony P.; Li, Xiao; Fratini, Livan

2018-05-01

Friction Stir Consolidation (FSC) is a solid-state process that results in consolidation of metal powders or chips producing solid billet through severe plastic deformation and the solid-state bonding phenomena. This process can be used both for primary production and for metal scrap recycling. During the FSC process, a rotating die is plunged into a hollow chamber containing the finely divided, unconsolidated material to be processed. In this paper, a FEM numerical model for the prediction of the quality of the consolidated billet is presented. In particular, a dedicated bonding criterion that takes into account the peculiar process mechanics of this innovative technology is proposed.

White thin-film flip-chip LEDs with uniform color temperature using laser lift-off and conformal phosphor coating technologies.

PubMed

Lin, Huan-Ting; Tien, Ching-Ho; Hsu, Chen-Peng; Horng, Ray-Hua

2014-12-29

We fabricated a phosphor-conversion white light emitting diode (PC-WLED) using a thin-film flip-chip GaN LED with a roughened u-GaN surface (TFFC-SR-LED) that emits blue light at 450 nm wavelength with a conformal phosphor coating that converts the blue light into yellow light. It was found that the TFFC-SR-LED with the thin-film substrate removal process and surface roughening exhibits a power enhancement of 16.1% when compared with the TFFC-LED without a sapphire substrate. When a TFFC-SR-LED with phosphors on a Cu-metal packaging-base (TFFC-SR-Cu-WLED) was operated at a forward-bias current of 350 mA, luminous flux and luminous efficacy were increased by 17.8 and 11.9%, compared to a TFFC-SR-LED on a Cup-shaped packaging-base (TFFC-SR-Cup-WLED). The angular correlated color temperature (CCT) deviation of a TFFC-SR-Cu-WLED reaches 77 K in the range of -70° to + 70° when the average CCT of white LEDs is around 4300 K. Consequently, the TFFC-SR-LED in a conformal coating phosphor structure on a Cu packaging-base could not only increase the luminous flux output, but also improve the angular-dependent CCT uniformity, thereby reducing the yellow ring effect.

Development and Status of Cu Ball/Wedge Bonding in 2012

NASA Astrophysics Data System (ADS)

Schneider-Ramelow, Martin; Geißler, Ute; Schmitz, Stefan; Grübl, Wolfgang; Schuch, Bernhard

2013-03-01

Starting in the 1980s and continuing right into the last decade, a great deal of research has been published on Cu ball/wedge (Cu B/W) wire bonding. Despite this, the technology has not been established in industrial manufacturing to any meaningful extent. Only spikes in the price of Au, improvements in equipment and techniques, and better understanding of the Cu wire-bonding process have seen Cu B/W bonding become more widespread—initially primarily for consumer goods manufacturing. Cu wire bonding is now expected to soon be used for at least 20% of all ball/wedge-bonded components, and its utilization in more sophisticated applications is around the corner. In light of this progress, the present paper comprehensively reviews the existing literature on this topic and discusses wire-bonding materials, equipment, and tools in the ongoing development of Cu B/W bonding technology. Key bonding techniques, such as flame-off, how to prevent damage to the chip (cratering), and bond formation on various common chip and substrate finishes are also described. Furthermore, apart from discussing quality assessment of Cu wire bonds in the initial state, the paper also provides an overview of Cu bonding reliability, in particular regarding Cu balls on Al metalization at high temperatures and in humidity (including under the influence of halide ions).

High-performance genetic analysis on microfabricated capillary array electrophoresis plastic chips fabricated by injection molding.

PubMed

Dang, Fuquan; Tabata, Osamu; Kurokawa, Masaya; Ewis, Ashraf A; Zhang, Lihua; Yamaoka, Yoshihisa; Shinohara, Shouji; Shinohara, Yasuo; Ishikawa, Mitsuru; Baba, Yoshinobu

2005-04-01

We have developed a novel technique for mass production of microfabricated capillary array electrophoresis (mu-CAE) plastic chips for high-speed, high-throughput genetic analysis. The mu-CAE chips, containing 10 individual separation channels of 50-microm width, 50-microm depth, and a 100-microm lane-to-lane spacing at the detection region and a sacrificial channel network, were fabricated on a poly(methyl methacrylate) substrate by injection molding and then bonded manually using a pressure-sensitive sealing tape within several seconds at room temperature. The conditions for injection molding and bonding were carefully characterized to yield mu-CAE chips with well-defined channel and injection structures. A CCD camera equipped with an image intensifier was used to monitor simultaneously the separation in a 10-channel array with laser-induced fluorescence detection. High-performance electrophoretic separations of phiX174 HaeIII DNA restriction fragments and PCR products related to the human beta-globin gene and SP-B gene (the surfactant protein B) have been demonstrated on mu-CAE plastic chips using a methylcellulose sieving matrix in individual channels. The current work demonstrated greatly simplified the fabrication process as well as a detection scheme for mu-CAE chips and will bring the low-cost mass production and application of mu-CAE plastic chips for genetic analysis.

Effects of PCB Pad Metal Finishes on the Cu-Pillar/Sn-Ag Micro Bump Joint Reliability of Chip-on-Board (COB) Assembly

NASA Astrophysics Data System (ADS)

Kim, Youngsoon; Lee, Seyong; Shin, Ji-won; Paik, Kyung-Wook

2016-06-01

While solder bumps have been used as the bump structure to form the interconnection during the last few decades, the continuing scaling down of devices has led to a change in the bump structure to Cu-pillar/Sn-Ag micro-bumps. Cu-pillar/Sn-Ag micro-bump interconnections differ from conventional solder bump interconnections in terms of their assembly processing and reliability. A thermo-compression bonding method with pre-applied b-stage non-conductive films has been adopted to form solder joints between Cu pillar/Sn-Ag micro bumps and printed circuit board vehicles, using various pad metal finishes. As a result, various interfacial inter-metallic compounds (IMCs) reactions and stress concentrations occur at the Cu pillar/Sn-Ag micro bumps joints. Therefore, it is necessary to investigate the influence of pad metal finishes on the structural reliability of fine pitch Cu pillar/Sn-Ag micro bumps flip chip packaging. In this study, four different pad surface finishes (Thin Ni ENEPIG, OSP, ENEPIG, ENIG) were evaluated in terms of their interconnection reliability by thermal cycle (T/C) test up to 2000 cycles at temperatures ranging from -55°C to 125°C and high-temperature storage test up to 1000 h at 150°C. The contact resistances of the Cu pillar/Sn-Ag micro bump showed significant differences after the T/C reliability test in the following order: thin Ni ENEPIG > OSP > ENEPIG where the thin Ni ENEPIG pad metal finish provided the best Cu pillar/Sn-Ag micro bump interconnection in terms of bump joint reliability. Various IMCs formed between the bump joint areas can account for the main failure mechanism.

How does huperzine A enter and leave the binding gorge of acetylcholinesterase? Steered molecular dynamics simulations.

PubMed

Xu, Yechun; Shen, Jianhua; Luo, Xiaomin; Silman, Israel; Sussman, Joel L; Chen, Kaixian; Jiang, Hualiang

2003-09-17

The entering and leaving processes of Huperzine A (HupA) binding with the long active-site gorge of Torpedo californica acetylcholinesterase (TcAChE) have been investigated by using steered molecular dynamics simulations. The analysis of the force required along the pathway shows that it is easier for HupA to bind to the active site of AChE than to disassociate from it, which for the first time interprets at the atomic level the previous experimental result that unbinding process of HupA is much slower than its binding process to AChE. The direct hydrogen bonds, water bridges, and hydrophobic interactions were analyzed during two steered molecular dynamics (SMD) simulations. Break of the direct hydrogen bond needs a great pulling force. The steric hindrance of bottleneck might be the most important factor to produce the maximal rupture force for HupA to leave the binding site but it has a little effect on the binding process of HupA with AChE. Residue Asp72 forms a lot of water bridges with HupA leaving and entering the AChE binding gorge, acting as a clamp to take out HupA from or put HupA into the active site. The flip of the peptide bond between Gly117 and Gly118 has been detected during both the conventional MD and SMD simulations. The simulation results indicate that this flip phenomenon could be an intrinsic property of AChE and the Gly117-Gly118 peptide bond in both HupA bound and unbound AChE structures tends to adopt the native enzyme structure. At last, in a vacuum the rupture force is increased up to 1500 pN while in water solution the greatest rupture force is about 800 pN, which means water molecules in the binding gorge act as lubricant to facilitate HupA entering or leaving the binding gorge.

Integrated circuit package with lead structure and method of preparing the same

NASA Technical Reports Server (NTRS)

Kennedy, B. W. (Inventor)

1973-01-01

A beam-lead integrated circuit package assembly including a beam-lead integrated circuit chip, a lead frame array bonded to projecting fingers of the chip, a rubber potting compound disposed around the chip, and an encapsulating molded plastic is described. The lead frame array is prepared by photographically printing a lead pattern on a base metal sheet, selectively etching to remove metal between leads, and plating with gold. Joining of the chip to the lead frame array is carried out by thermocompression bonding of mating goldplated surfaces. A small amount of silicone rubber is then applied to cover the chip and bonded joints, and the package is encapsulated with epoxy resin, applied by molding.

Surface and buried interfacial structures of epoxy resins used as underfills studied by sum frequency generation vibrational spectroscopy.

PubMed

Vázquez, Anne V; Holden, Brad; Kristalyn, Cornelius; Fuller, Mike; Wilkerson, Brett; Chen, Zhan

2011-05-01

Flip chip technology has greatly improved the performance of semiconductor devices, but relies heavily on the performance of epoxy underfill adhesives. Because epoxy underfills are cured in situ in flip chip semiconductor devices, understanding their surface and interfacial structures is critical for understanding their adhesion to various substrates. Here, sum frequency generation (SFG) vibrational spectroscopy was used to study surface and buried interfacial structures of two model epoxy resins used as underfills in flip chip devices, bisphenol A digylcidyl ether (BADGE) and 1,4-butanediol diglycidyl ether (BDDGE). The surface structures of these epoxies were compared before and after cure, and the orientations of their surface functional groups were deduced to understand how surface structural changes during cure may affect adhesion properties. Further, the effect of moisture exposure, a known cause of adhesion failure, on surface structures was studied. It was found that the BADGE surface significantly restructured upon moisture exposure while the BDDGE surface did not, showing that BADGE adhesives may be more prone to moisture-induced delamination. Lastly, although surface structure can give some insight into adhesion, buried interfacial structures more directly correspond to adhesion properties of polymers. SFG was used to study buried interfaces between deuterated polystyrene (d-PS) and the epoxies before and after moisture exposure. It was shown that moisture exposure acted to disorder the buried interfaces, most likely due to swelling. These results correlated with lap shear adhesion testing showing a decrease in adhesion strength after moisture exposure. The presented work showed that surface and interfacial structures can be correlated to adhesive strength and may be helpful in understanding and designing optimized epoxy underfill adhesives.

Attachment method for stacked integrated circuit (IC) chips

DOEpatents

Bernhardt, Anthony F.; Malba, Vincent

1999-01-01

An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM.

Effect of oxalic acid pretreatment of wood chips on manufacturing medium-density fiberboard

Treesearch

Xianjun Li; Zhiyong Cai; Eric Horn; Jerrold E. Winandy

2011-01-01

The main objective of this study was to evaluate the effect of oxalic acid (OA) wood chips pretreatment prior to refining, which is done to reduce energy used during the refining process. Selected mechanical and physical performances of medium-density fiberboard (MDF) – internal bonding (IB), modulus of elasticity (MOE), modulus of rupture (MOR), water absorption (WA)...

Fundamental study of microelectronic chip response under laser ultrasonic-interferometric inspection using C-scan method

NASA Astrophysics Data System (ADS)

Yang, Lei; Gong, Jie; Ume, I. Charles

2014-02-01

In modern surface mount packaging technologies, such as flip chips, chip scale packages, and ball grid arrays(BGA), chips are attached to the substrates/printed wiring board (PWB) using solder bump interconnections. The quality of solder bumps between the chips and the substrate/board is difficult to inspect. Laser ultrasonic-interferometric technique was proved to be a promising approach for solder bump inspection because of its noncontact and nondestructive characteristics. Different indicators extracted from received signals have been used to predict the potential defects, such as correlation coefficient, error ratio, frequency shifting, etc. However, the fundamental understanding of the chip behavior under laser ultrasonic inspection is still missing. Specifically, it is not sure whether the laser interferometer detected out-of-plane displacements were due to wave propagation or structural vibration when the chip was excited by pulsed laser. Plus, it is found that the received signals are chip dependent. Both challenges impede the interpretation of acquired signals. In this paper, a C-scan method was proposed to study the underlying phenomenon during laser ultrasonic inspection. The full chip was inspected. The response of the chip under laser excitation was visualized in a movie resulted from acquired signals. Specifically, a BGA chip was investigated to demonstrate the effectiveness of this method. By characterizing signals using discrete wavelet transform(DWT), both ultrasonic wave propagation and vibration were observed. Separation of them was successfully achieved using ideal band-pass filter and visualized in resultant movies, too. The observed ultrasonic waves were characterized and their respective speeds were measured by applying 2-D FFT. The C-scan method, combined with different digital signal processing techniques, was proved to be an very effective methodology to learn the behavior of chips under laser excitation. This general procedure can be applied to any unknown chip before inspection. A wealth of information can be provided by this learning procedure, which greatly benefits the interpretation of inspection signals afterwards.

A Robust Strategy for Total Ionizing Dose Testing of Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Wilcox, Edward; Berg, Melanie; Friendlich, Mark; Lakeman, Joseph; KIm, Hak; Pellish, Jonathan; LaBel, Kenneth

2012-01-01

We present a novel method of FPGA TID testing that measures propagation delay between flip-flops operating at maximum speed. Measurement is performed on-chip at-speed and provides a key design metric when building system-critical synchronous designs.

Numerical analysis of light extraction enhancement of GaN-based thin-film flip-chip light-emitting diodes with high-refractive-index buckling nanostructures

NASA Astrophysics Data System (ADS)

Yue, Qing-Yang; Yang, Yang; Cheng, Zhen-Jia; Guo, Cheng-Shan

2018-06-01

In this work, the light extraction efficiency enhancement of GaN-based thin-film flip-chip (TFFC) light-emitting diodes (LEDs) with high-refractive-index (TiO2) buckling nanostructures was studied using the three-dimensional finite difference time domain method. Compared with 2-D photonic crystals, the buckling structures have the advantages of a random directionality and a broad distribution in periodicity, which can effectively extract the guided light propagating in all azimuthal directions over a wide spectrum. Numerical studies revealed that the light extraction efficiency of buckling-structured LEDs reaches 1.1 times that of triangular lattice photonic crystals. The effects of the buckling structure feature sizes and the thickness of the N-GaN layer on the light extraction efficiency for TFFC LEDs were also investigated systematically. With optimized structural parameters, a significant light extraction enhancement of about 2.6 times was achieved for TiO2 buckling-structured TFFC LEDs compared with planar LEDs.

Process development of beam-lead silicon-gate COS/MOS integrated circuits

NASA Technical Reports Server (NTRS)

Baptiste, B.; Boesenberg, W.

1974-01-01

Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.

Effect of Slice Error of Glass on Zero Offset of Capacitive Accelerometer

NASA Astrophysics Data System (ADS)

Hao, R.; Yu, H. J.; Zhou, W.; Peng, B.; Guo, J.

2018-03-01

Packaging process had been studied on capacitance accelerometer. The silicon-glass bonding process had been adopted on sensor chip and glass, and sensor chip and glass was adhered on ceramic substrate, the three-layer structure was curved due to the thermal mismatch, the slice error of glass lead to asymmetrical curve of sensor chip. Thus, the sensitive mass of accelerometer deviated along the sensitive direction, which was caused in zero offset drift. It was meaningful to confirm the influence of slice error of glass, the simulation results showed that the zero output drift was 12.3×10-3 m/s2 when the deviation was 40μm.

High reliable and chromaticity-tunable flip-chip w-LEDs with Ce:YAG glass-ceramics phosphor for long-lifetime automotive headlights applications

NASA Astrophysics Data System (ADS)

Ma, Chaoyang; Cao, Yongge; Shen, Xiaofei; Wen, Zicheng; Ma, Ran; Long, Jiaqi; Yuan, Xuanyi

2017-07-01

Nowadays, major commercial w-LEDs fabricated by the traditionally gold-wire-welding packaging technology have undergone considerable development as indoor/outdoor lighting sources due to its high-energy utilization efficiency, long service life, environmental friendliness, and excellent chromatic stability. While, new generation applications in projections, automotive lighting, street lighting, plaza lighting, and high-end general lighting need further improvements in power handling and light extraction. Herein, transparent Ce:YAG glass-ceramics (GCs) phosphor was prepared by low-temperature co-sintering polycrystalline Ce:YAG phosphor powder and home-made PbO-B2O3-ZnO-SiO2 glass powder. Thereafter, the flip-chip (FC) w-LEDs were fabricated with the GCs phosphor plates and FC blue chips. The GCs-based FC w-LEDs show not only excellent heat- and humidity-resistance characteristics, but also superior optical performances with an LE of 112.8 lm/W, a CRI of 71.2, a CCT of 6103 K as well as a chromaticity coordinate of (0.3202, 0.3298), under a high operation current of 400 mA. The technology route will open a practically commercial feasible approach to achieve excellent performances for advanced high-power FC w-LEDs.

Attachment method for stacked integrated circuit (IC) chips

DOEpatents

Bernhardt, A.F.; Malba, V.

1999-08-03

An attachment method for stacked integrated circuit (IC) chips is disclosed. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM. 12 figs.

Power-efficient dual-rate optical transceiver.

PubMed

Zuo, Yongrong; Kiamiley, Fouad E; Wang, Xiaoqing; Gui, Ping; Ekman, Jeremy; Wang, Xingle; McFadden, Michael J; Haney, Michael W

2005-11-20

A dual-rate (2 Gbit/s and 100 Mbit/s) optical transceiver designed for power-efficient connections within and between modern high-speed digital systems is described. The transceiver can dynamically adjust its data rate according to performance requirements, allowing for power-on-demand operation. Dynamic power management permits energy saving and lowers device operating temperatures, improving the reliability and lifetime of optoelectronic-devices such as vertical-cavity surface-emitting lasers (VCSELs). To implement dual-rate functionality, we include in the transmitter and receiver circuits separate high-speed and low-power data path modules. The high-speed module is designed for gigabit operation to achieve high bandwidth. A simpler low-power module is designed for megabit data transmission with low power consumption. The transceiver is fabricated in a 0.5 microm silicon-on-sapphire complementary metal-oxide semiconductor. The VCSEL and photodetector devices are attached to the transceiver's integrated circuit by flip-chip bonding. A free-space optical link system is constructed to demonstrate correct dual-rate functionality. Experimental results show reliable link operation at 2 Gbit/s and 100 Mbit/s data transfer rates with approximately 104 and approximately 9 mW power consumption, respectively. The transceiver's switching time between these two data rates is demonstrated as 10 micros, which is limited by on-chip register reconfiguration time. Improvement of this switching time can be obtained by use of dedicated input-output pads for dual-rate control signals.

Low-temperature bonded glass-membrane microfluidic device for in vitro organ-on-a-chip cell culture models

NASA Astrophysics Data System (ADS)

Pocock, Kyall J.; Gao, Xiaofang; Wang, Chenxi; Priest, Craig; Prestidge, Clive A.; Mawatari, Kazuma; Kitamori, Takehiko; Thierry, Benjamin

2015-12-01

The integration of microfluidics with living biological systems has paved the way to the exciting concept of "organson- a-chip", which aims at the development of advanced in vitro models that replicate the key features of human organs. Glass based devices have long been utilised in the field of microfluidics but the integration of alternative functional elements within multi-layered glass microdevices, such as polymeric membranes, remains a challenge. To this end, we have extended a previously reported approach for the low-temperature bonding of glass devices that enables the integration of a functional polycarbonate porous membrane. The process was initially developed and optimised on specialty low-temperature bonding equipment (μTAS2001, Bondtech, Japan) and subsequently adapted to more widely accessible hot embosser units (EVG520HE Hot Embosser, EVG, Austria). The key aspect of this method is the use of low temperatures compatible with polymeric membranes. Compared to borosilicate glass bonding (650 °C) and quartz/fused silica bonding (1050 °C) processes, this method maintains the integrity and functionality of the membrane (Tg 150 °C for polycarbonate). Leak tests performed showed no damage or loss of integrity of the membrane for up to 150 hours, indicating sufficient bond strength for long term cell culture. A feasibility study confirmed the growth of dense and functional monolayers of Caco-2 cells within 5 days.

3D Stacked Memory Final Report CRADA No. TC-0494-93

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bernhardt, A.; Beene, G.

TI and LLNL demonstrated: (1) a process for the fabrication of 3-D memory using stacked DRAM chips, and (2) a fast prototyping process for 3-D stacks and MCMs. The metallization to route the chip pads to the sides of the die was carried out in a single high-speed masking step. The mask was not the usual physical one in glass and chrome, but was simply a computer file used to control the laser patterning process. Changes in either chip or customer circuit-board pad layout were easily and inexpensively accommodated, so that prototyping was a natural consequence of the laser patterningmore » process. As in the current TI process, a dielectric layer was added to the wafer, and vias to the chip I/0 pads were formed. All of the steps in Texas Instruments earlier process that were required to gold bump the pads were eliminated, significantly reducing fabrication cost and complexity. Pads were created on the sides of ·the die, which became pads on the side of the stack. In order to extend the process to accommodate non-memory devices with substantially greater I/0 than is required for DRAMs, pads were patterned on two sides of the memory stacks as a proof of principle. Stacking and bonding were done using modifications of the current TI process. After stacking and bonding, the pads on the sides of the dice were connected by application of a polyimide insulator film with laser ablation of the polyimide to form contacts to the pads. Then metallization was accomplished in the same manner as on the individual die.« less

Numerical and experimental investigation of GaN-based flip-chip light-emitting diodes with highly reflective Ag/TiW and ITO/DBR Ohmic contacts.

PubMed

Zhou, Shengjun; Liu, Xingtong; Gao, Yilin; Liu, Yingce; Liu, Mengling; Liu, Zongyuan; Gui, Chengqun; Liu, Sheng

2017-10-30

We demonstrate two types of GaN-based flip-chip light-emitting diodes (FCLEDs) with highly reflective Ag/TiW and indium-tin oxide (ITO)/distributed Bragg reflector (DBR) p-type Ohmic contacts. We show that a direct Ohmic contact to p-GaN layer using pure Ag is obtained when annealed at 600°C in N 2 ambient. A TiW diffusion barrier layer covered onto Ag is used to suppress the agglomeration of Ag and thus maintain high reflectance of Ag during high temperature annealing process. We develop a strip-shaped SiO 2 current blocking layer beneath the ITO/DBR to alleviate current crowding occurring in FCLED with ITO/DBR. Owing to negligibly small spreading resistance of Ag, however, our combined numerical and experimental results show that the FCLED with Ag/TiW has a more favorable current spreading uniformity in comparison to the FCLED with ITO/DBR. As a result, the light output power of FCLED with Ag/TiW is 7.5% higher than that of FCLED with ITO/DBR at 350 mA. The maximum output power of the FCLED with Ag/TiW obtained at 305.6 A/cm 2 is 29.3% larger than that of the FCLED with ITO/DBR obtained at 278.9 A/cm 2 . The improvement appears to be due to the enhanced current spreading and higher optical reflectance provided by the Ag/TiW.

Ultra-low loss fully-etched grating couplers for perfectly vertical coupling compatible with DUV lithography tools

NASA Astrophysics Data System (ADS)

Dabos, G.; Pleros, N.; Tsiokos, D.

2016-03-01

Hybrid integration of VCSELs onto silicon-on-insulator (SOI) substrates has emerged as an attractive approach for bridging the gap between cost-effective and energy-efficient directly modulated laser sources and silicon-based PICs by leveraging flip-chip (FC) bonding techniques and silicon grating couplers (GCs). In this context, silicon GCs, should comply with the process requirements imposed by the complimentary-metal-oxide-semiconductor manufacturing tools addressing in parallel the challenges originating from the perfectly vertical incidence. Firstly, fully etched GCs compatible with deep-ultraviolet lithography tools offering high coupling efficiencies are imperatively needed to maintain low fabrication cost. Secondly, GC's tolerance to VCSEL bonding misalignment errors is a prerequisite for practical deployment. Finally, a major challenge originating from the perfectly vertical coupling scheme is the minimization of the direct back-reflection to the VCSEL's outgoing facet which may destabilize its operation. Motivated from the above challenges, we used numerical simulation tools to design an ultra-low loss, bidirectional VCSEL-to-SOI optical coupling scheme for either TE or TM polarization, based on low-cost fully etched GCs with a Si-layer of 340 nm without employing bottom reflectors or optimizing the buried-oxide layer. Comprehensive 2D Finite-Difference-Time- Domain simulations have been performed. The reported GC layout remains fully compatible with the back-end-of-line (BEOL) stack associated with the 3D integration technology exploiting all the inter-metal-dielectric (IMD) layers of the CMOS fab. Simulation results predicted for the first time in fully etched structures a coupling efficiency of as low as -0.87 dB at 1548 nm and -1.47 dB at 1560 nm with a minimum direct back-reflection of -27.4 dB and -14.2 dB for TE and TM polarization, respectively.

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

PubMed

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Man-Chia; Perez, Aldo Pena; Kothapalli, Sri-Rajasekhar

This study presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 μm by 250 μm. The proof-of-concept receiver was implemented in an STMicroelectronics's 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a 4 × 4 subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables anmore » efficient in-pixel A/D conversion. The per-pixel switched-capacitor ΔΣ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator's measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. Finally, the functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array.« less

A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI

DOE PAGES

Chen, Man-Chia; Perez, Aldo Pena; Kothapalli, Sri-Rajasekhar; ...

2017-10-16

This study presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 μm by 250 μm. The proof-of-concept receiver was implemented in an STMicroelectronics's 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a 4 × 4 subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables anmore » efficient in-pixel A/D conversion. The per-pixel switched-capacitor ΔΣ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator's measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. Finally, the functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array.« less

Flip-flop resolving time test circuit

NASA Technical Reports Server (NTRS)

Rosenberger, F.; Chaney, T. J.

1982-01-01

Integrated circuit (IC) flip-flop resolving time parameters are measured by wafer probing, without need of dicing or bonding, throught the incorporation of test structures on an IC together with the flip-flop to be measured. Several delays that are fabricated as part of the test circuit, including a voltage-controlled delay with a resolution of a few picosecs, are calibrated as part of the test procedure by integrating them into, and out of, the delay path of a ring oscillator. Each of the delay values is calculated by subtracting the period of the ring oscillator with the delay omitted from the period with the delay included. The delay measurement technique is sufficiently general for other applications. The technique is illustrated for the case of the flip-flop parameters of a 5-micron feature size NMOS circuit.

Capacitor bonding techniques and reliability. [thermal cycling tests

NASA Technical Reports Server (NTRS)

Kinser, D. L.; Graff, S. M.; Allen, R. V.; Caruso, S. V.

1974-01-01

The effect of thermal cycling on the mechanical failure of bonded ceramic chip capacitors mounted on alumina substrates is studied. It is shown that differential thermal expansion is responsible for the cumulative effects which lead to delayed failure of the capacitors. Harder or higher melting solders are found to be less susceptible to thermal cycling effects, although they are more likely to fail during initial processing operations.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

A simple and low-cost chip bonding solution for high pressure, high temperature and biological applications.

PubMed

Serra, M; Pereiro, I; Yamada, A; Viovy, J-L; Descroix, S; Ferraro, D

2017-02-14

The sealing of microfluidic devices remains a complex and time-consuming process requiring specific equipment and protocols: a universal method is thus highly desirable. We propose here the use of a commercially available sealing tape as a robust, versatile, reversible solution, compatible with cell and molecular biology protocols, and requiring only the application of manually achievable pressures. The performance of the seal was tested with regards to the most commonly used chip materials. For most materials, the bonding resisted 5 bars at room temperature and 1 bar at 95 °C. This method should find numerous uses, ranging from fast prototyping in the laboratory to implementation in low technology environments or industrial production.

Flexure mechanism-based parallelism measurements for chip-on-glass bonding

NASA Astrophysics Data System (ADS)

Jung, Seung Won; Yun, Won Soo; Jin, Songwan; Kim, Bo Sun; Jeong, Young Hun

2011-08-01

Recently, liquid crystal displays (LCDs) have played vital roles in a variety of electronic devices such as televisions, cellular phones, and desktop/laptop monitors because of their enhanced volume, performance, and functionality. However, there is still a need for thinner LCD panels due to the trend of miniaturization in electronic applications. Thus, chip-on-glass (COG) bonding has become one of the most important aspects in the LCD panel manufacturing process. In this study, a novel sensor was developed to measure the parallelism between the tooltip planes of the bonding head and the backup of the COG main bonder, which has previously been estimated by prescale pressure films in industry. The sensor developed in this study is based on a flexure mechanism, and it can measure the total pressing force and the inclination angles in two directions that satisfy the quantitative definition of parallelism. To improve the measurement accuracy, the sensor was calibrated based on the estimation of the total pressing force and the inclination angles using the least-squares method. To verify the accuracy of the sensor, the estimation results for parallelism were compared with those from prescale pressure film measurements. In addition, the influence of parallelism on the bonding quality was experimentally demonstrated. The sensor was successfully applied to the measurement of parallelism in the COG-bonding process with an accuracy of more than three times that of the conventional method using prescale pressure films.

Characterization of Calcite Mineral Precipitation Process by EICP in Porous Media

NASA Astrophysics Data System (ADS)

Kim, D.; Mahabadi, N.; Hall, C.; Jang, J.; van Paassen, L. A.

2017-12-01

One of the most prevalent ground improvement techniques is injection of synthetic materials, such as cement grout or silicates into the pore space to create cementing bonds between soil particles. Besides these traditional ground improvement methods, several biological processes have been developed to improve soil properties. Enzyme induced carbonate precipitation (EICP) is a biological process in which urea hydrolyzes into ammonia and inorganic carbon, and promotes carbonate mineral precipitation. Different morphologies and patterns of calcite mineral precipitation, such as particle surface coating, pore filling, and soil particles bonding, have been observed in the previous studies. Most of the researches have detected precipitated minerals after the completion of the treatment using SEM (Scanning Electron Microscope) imaging and XRD (X-ray Diffractometer) structural analysis. In this research, an EICP reaction medium is injected into a microfluidic chip to observe the entire process of carbonate precipitation through several cycles of EICP treatment in the porous medium. Once the process of mineral precipitation is completed, water is injected into the microfluidic chip with different flow rates to evaluate the stability of carbonates during fluid flow injection.

High-Modulation-Speed LEDs Based on III-Nitride

NASA Astrophysics Data System (ADS)

Chen, Hong

III-nitride InGaN light-emitting diodes (LEDs) enable wide range of applications in solid-state lighting, full-color displays, and high-speed visible-light communication. Conventional InGaN quantum well LEDs grown on polar c-plane substrate suffer from quantum confined Stark effect due to the large internal polarization-related fields, leading to a reduced radiative recombination rate and device efficiency, which limits the performance of InGaN LEDs in high-speed communication applications. To circumvent these negative effects, non-trivial-cavity designs such as flip-chip LEDs, metallic grating coated LEDs are proposed. This oral defense will show the works on the high-modulation-speed LEDs from basic ideas to applications. Fundamental principles such as rate equations for LEDs/laser diodes (LDs), plasmonic effects, Purcell effects will be briefly introduced. For applications, the modal properties of flip-chip LEDs are solved by implementing finite difference method in order to study the modulation response. The emission properties of highly polarized InGaN LEDs coated by metallic gratings are also investigated by finite difference time domain method.

Neighbour-die effect on the measurement of wafer-level flip-chip LED dies in production lines

NASA Astrophysics Data System (ADS)

Chen, Tengfei; Wan, Zirui; Li, Bin

2017-11-01

The light from the side surfaces of the test flip-chip light-emitting diode (FCLED) dies is reflected, refracted or absorbed by neighbour dies during the measurement of wafer-level FCLED dies in production lines. A notable measurement deviation is caused by the neighbour-die effect, which is not considered in current industry practice. In this paper, Monte Carlo ray-tracing simulations are used to study the measurement deviations caused by the neighbour-die effect and extension ratios of the film. The simulation results show that the maximal deviation of radiant flux impinging the photodiode can reach 5.5%, if the die is tested without any neighbour dies, or is surrounded by a set of neighbour dies at an extension ratio of 1.1. Moreover, the dependence between the measurement results and neighbour cases for different extension ratios is also investigated. Then, a modified calibration method is proposed and studied. The proposed technique can be used to improve the calibration and measurement accuracy of the test equipment used for measurement of wafer-level FCLED dies in production lines.

Aging Studies of Cu-Sn Intermetallics in Cu Micropillars Used in Flip Chip Attachment onto Cu Lead Frames

NASA Astrophysics Data System (ADS)

Roma, Maria Penafrancia C.; Kudtarkar, Santosh; Kierse, Oliver; Sengupta, Dipak; Cho, Junghyun

2018-02-01

Copper micropillars plated onto a silicon die and soldered with Sn-Ag solder to a copper lead frame in a flip chip on lead package have been subjected to high-temperature storage at 150°C and 175°C for 500 h, 1000 h, and 1500 h. Cu6Sn5 and Cu3Sn intermetallic compounds were found on both sides of the solder, but the growth rates were not the same as evidenced by different values of the growth exponent n. Cu and Sn diffusion controlled the Cu3Sn growth in the Cu pillar interface ( n ≈ 0.5), while interface reactions controlled the growth in the Cu lead frame interface ( n ≈ 0.8). Increasing the aging temperature increased the growth of Cu3Sn as well as the presence of microvoids in the Cu lead frame side. Adding Ni as a barrier layer on the Cu pillar prevented the growth of Cu3Sn in the Cu pillar interface and reduced its growth rate on the lead frame side, even at higher aging temperatures.

Caught in the act: visualization of an intermediate in the DNA base-flipping pathway induced by HhaI methyltransferase | Center for Cancer Research

Cancer.gov

HHAI methyltransferase (blue ribbon) bound to oligonucleotide (strands with bonds colored yellow and green) containing a pseudorotationally constrained sugar analogue at the target position (orange bonds with cyan atoms). The south-constrained pseudosugar is rotated about its flanking phosphodiester bonds, 90° from its initial position in B-form DNA, but short of a completely

Electromigration and solid state aging of flip chip solder joints and analysis of tin whisker on lead-frame

NASA Astrophysics Data System (ADS)

Lee, Taekyeong

Electromigration and solid state aging in flip chip joint, and whisker on lead frame of Pb-containing (eutectic SnPb) and Pb-free solders (SnAg 3.5, SnAg3.8Cu0.7, and SnCu0.7), have been studied systematically, using Scanning Electron Microscopy (SEM), Energy Dispersive X-ray Analysis (EDX), and synchrotron radiation. The high current density in flip chip joint drives the diffusion of atoms of eutectic SnPb and SnAgCu. A marker is used to measure the diffusion flux in a half cross-sectioned solder joint. SnAgCu shows higher resistance against electromigration than eutectic SnPb. In the half cross-sectioned solder joint, void growth is the dominant failure mechanism. However, the whole solder balls in the underfill show that the failure mechanism is a result from the dissolution of electroless Ni under bump metallization (UBM) of about 10 mum thickness. The growth rate between intermetallic compounds in molten and solid solders differed by four orders of magnitude. In liquid solder, the growth rate is about 1 mum/min; the growth rate in solid solder is only about 10 -4 mum/min. The difference is not resulting from factors of thermodynamics, which is the change of Gibbs free energy before and after intermetallic compound formation, but from kinetic factors, which is the rate of change of Gibbs free energy. Even though the difference in growth rate between eutectic SnPb and Pb-free solders during solid state aging was found, the reason behind such difference shown is unclear. The orientation and stress levels of whiskers are measured by white X-ray of synchrotron radiation. The growth direction is nearly parallel to one of the principal axes of tin. The compressive stress level is quite low because the residual stress is relaxed by the whisker growth.

Physics of self-aligned assembly at room temperature

NASA Astrophysics Data System (ADS)

Dubey, V.; Beyne, E.; Derakhshandeh, J.; De Wolf, I.

2018-01-01

Self-aligned assembly, making use of capillary forces, is considered as an alternative to active alignment during thermo-compression bonding of Si chips in the 3D heterogeneous integration process. Various process parameters affect the alignment accuracy of the chip over the patterned binding site on a substrate/carrier wafer. This paper discusses the chip motion due to wetting and capillary force using a transient coupled physics model for the two regimes (that is, wetting regime and damped oscillatory regime) in the temporal domain. Using the transient model, the effect of the volume of the liquid and the placement accuracy of the chip on the alignment force is studied. The capillary time (that is, the time it takes for the chip to reach its mean position) for the chip is directly proportional to the placement offset and inversely proportional to the viscosity. The time constant of the harmonic oscillations is directly proportional to the gap between the chips due to the volume of the fluid. The predicted behavior from transient simulations is next experimentally validated and it is confirmed that the liquid volume and the initial placement affect the final alignment accuracy of the top chip on the bottom substrate. With statistical experimental data, we demonstrate an alignment accuracy reaching <1 μm.

Rotational symmetry breaking toward a string-valence bond solid phase in frustrated J1 -J2 transverse field Ising model

NASA Astrophysics Data System (ADS)

Sadrzadeh, M.; Langari, A.

2018-06-01

We study the effect of quantum fluctuations by means of a transverse magnetic field (Γ) on the highly degenerate ground state of antiferromagnetic J1 -J2 Ising model on the square lattice, at the limit J2 /J1 = 0.5 . We show that harmonic quantum fluctuations based on single spin flips can not lift such degeneracy, however an-harmonic quantum fluctuations based on multi spin cluster flip excitations lift the degeneracy toward a unique ground state with string-valence bond solid (VBS) nature. A cluster operator formalism has been implemented to incorporate an-harmonic quantum fluctuations. We show that cluster-type excitations of the model lead not only to lower the excitation energy compared with a single-spin flip but also to lift the extensive degeneracy in favor of a string-VBS state, which breaks lattice rotational symmetry with only two fold degeneracy. The tendency toward the broken symmetry state is justified by numerical exact diagonalization. Moreover, we introduce a map to find the relation between the present model on the checkerboard and square lattices.

Interconnect mechanisms in microelectronic packaging

NASA Astrophysics Data System (ADS)

Roma, Maria Penafrancia C.

Global economic, environmental and market developments caused major impact in the microelectronics industry. Astronomical rise of gold metal prices over the last decade shifted the use of copper and silver alloys as bonding wires. Environmental legislation on the restriction of the use of Pb launched worldwide search for lead-free solders and platings. Finally, electrical and digital uses demanded smaller, faster and cheaper devices. Ultra-fine pitch bonding, decreasing bond wire sizes and hard to bond substrates have put the once-robust stitch bond in the center of reliability issues due to stitch bond lift or open wires .Unlike the ball bond, stitch bonding does not lead to intermetallic compound formation but adhesion is dependent on mechanical deformation, interdiffusion, solid solution formation, void formation and mechanical interlocking depending on the wire material, bond configuration, substrate type , thickness and surface condition. Using Au standoff stitch bonds on NiPdAu plated substrates eliminated stitch bond lift even when the Au and Pd layers are reduced. Using the Matano-Boltzmann analysis on a STEM (Scanning Transmission Analysis) concentration profile the interdiffusion coefficient is measured to be 10-16 cm 2/s. Wire pull strength data showed that the wire pull strength is 0.062N and increases upon stress testing. Meanwhile, coating the Cu wire with Pd, not only increases oxidation resistance but also improved adhesion due to the formation of a unique interfacial adhesion layers. Adhesion strength as measured by pull showed the Cu wire bonded to Ag plated Cu substrate (0.132N) to be stronger than the Au wire bonded on the same substrate (0.124N). Ag stitch bonded to Au is predicted to be strong but surface modification made the adhesion stronger. However, on the Ag ball bonded to Al showed multiple IMC formation with unique morphology exposed by ion milling and backscattered scanning electron microscopy. Adding alloying elements in the Ag wire alloy showed differences in adhesion strength and IMC formation. Bond strength by wire pull testing showed the 95Ag alloy with higher values while shear bond testing showed the 88Ag higher bond strength. Use of Cu pillars in flip chips and eutectic bonding in wafer level chip scale packages are direct consequences of diminishing interconnect dimension as a result of the drive for miniaturization. The combination of Cu-Sn interdiffusion, Kirkendall mechanism and heterogeneous vacancy precipitation are the main causes of IMC and void formation in Cu pillar - Sn solder - Cu lead frame sandwich structure. However, adding a Ni barrier agent showed less porous IMC layer as well as void formation as a result of the modified Cu and Sn movement well as the void formation. Direct die to die bonding using Al-Ge eutectic bonds is necessary when 3D integration is needed to reduce the footprint of a package. Hermeticity and adhesion strength are a function of the Al/Ge thickness ratio, bonding pressure, temperature and time. Scanning Electron Microscope (SEM) and Focused Ion Beam (FIB) allowed imaging of interfacial microstructures, porosity, grain morphology while Scanning Transmission Electron microscope (STEM) provided diffusion profile and confirmed interdiffusion. Ion polishing technique provided information on porosity and when imaged using backscattered mode, grain structure confirmed mechanical deformation of the bonds. Measurements of the interfacial bond strength are made by wire pull tests and ball shear tests based on existing industry standard tests. However, for the Al-Ge eutectic bonds, no standard strength is available so a test is developed using the stud pull test method using the Dage 4000 Plus to yield consistent results. Adhesion strengths of 30-40 MPa are found for eutectic bonded packages however, as low as 20MPa was measured in low temperature bonded areas.

Chip packaging technique

NASA Technical Reports Server (NTRS)

Jayaraj, Kumaraswamy (Inventor); Noll, Thomas E. (Inventor); Lockwood, Harry F. (Inventor)

2001-01-01

A hermetically sealed package for at least one semiconductor chip is provided which is formed of a substrate having electrical interconnects thereon to which the semiconductor chips are selectively bonded, and a lid which preferably functions as a heat sink, with a hermetic seal being formed around the chips between the substrate and the heat sink. The substrate is either formed of or includes a layer of a thermoplastic material having low moisture permeability which material is preferably a liquid crystal polymer (LCP) and is a multiaxially oriented LCP material for preferred embodiments. Where the lid is a heat sink, the heat sink is formed of a material having high thermal conductivity and preferably a coefficient of thermal expansion which substantially matches that of the chip. A hermetic bond is formed between the side of each chip opposite that connected to the substrate and the heat sink. The thermal bond between the substrate and the lid/heat sink may be a pinched seal or may be provided, for example by an LCP frame which is hermetically bonded or sealed on one side to the substrate and on the other side to the lid/heat sink. The chips may operate in the RF or microwave bands with suitable interconnects on the substrate and the chips may also include optical components with optical fibers being sealed into the substrate and aligned with corresponding optical components to transmit light in at least one direction. A plurality of packages may be physically and electrically connected together in a stack to form a 3D array.

Transient thermal characteristics of high-temperature SiC power module enhanced with Al-bump technology

NASA Astrophysics Data System (ADS)

Tanisawa, Hidekazu; Kato, Fumiki; Koui, Kenichi; Sato, Shinji; Watanabe, Kinuyo; Takahashi, Hiroki; Murakami, Yoshinori; Sato, Hiroshi

2018-04-01

In this paper, we demonstrate a mounting technology that improves the tolerance to transient power loss by adding a heat capacity near the device. Silicon carbide (SiC) power devices can operate at high temperatures, up to 250 °C, at which silicon (Si) power devices cannot. Therefore, it is possible to allow a large temperature difference between the device and ambient air. Thus, the size of a power converter equipped with an SiC power module is reduced by simplifying the cooling system. The temperature of the power module is important not only in the steady state, but in transient loads as well. Therefore, we developed the Al-bump flip-chip mounting technology to increase heat capacity near the device. With this proposed structure, the heat capacity per device increased by 1.7% compared with the total heat capacity of the conventional structure using wire bonding. The reduction in transient thermal impedance is observed from 0.003 to 3 s, and we confirmed that the transient thermal impedance is reduced very efficiently by 15% at the maximum, compared with the conventional structure.

Design and demonstration of ultra-fast W-band photonic transmitter-mixer and detectors for 25 Gbits/sec error-free wireless linking.

PubMed

Chen, Nan-Wei; Shi, Jin-Wei; Tsai, Hsuan-Ju; Wun, Jhih-Min; Kuo, Fong-Ming; Hesler, Jeffery; Crowe, Thomas W; Bowers, John E

2012-09-10

A 25 Gbits/s error-free on-off-keying (OOK) wireless link between an ultra high-speed W-band photonic transmitter-mixer (PTM) and a fast W-band envelope detector is demonstrated. At the transmission end, the high-speed PTM is developed with an active near-ballistic uni-traveling carrier photodiode (NBUTC-PD) integrated with broadband front-end circuitry via the flip-chip bonding technique. Compared to our previous work, the wireless data rate is significantly increased through the improvement on the bandwidth of the front-end circuitry together with the reduction of the intermediate-frequency (IF) driving voltage of the active NBUTC-PD. The demonstrated PTM has a record-wide IF modulation (DC-25 GHz) and optical-to-electrical fractional bandwidths (68-128 GHz, ~67%). At the receiver end, the demodulation is realized with an ultra-fast W-band envelope detector built with a zero-bias Schottky barrier diode with a record wide video bandwidth (37 GHz) and excellent sensitivity. The demonstrated PTM is expected to find applications in multi-gigabit short-range wireless communication.

Advanced sensor systems for biotelemetry

NASA Technical Reports Server (NTRS)

Ricks, Robert D. (Inventor); Mundt, Carsten W. (Inventor); Hines, John W. (Inventor); Somps, Christopher J. (Inventor)

2003-01-01

The present invention relates to telemetry-based sensing systems that continuously measures physical, chemical and biological parameters. More specifically, these sensing systems comprise a small, modular, low-power implantable biotelemetry system capable of continuously sensing physiological characteristics using implantable transmitters, a receiver, and a data acquisition system to analyze and record the transmitted signal over several months. The preferred embodiment is a preterm labor and fetal monitoring system. Key features of the invention include Pulse Interval Modulation (PIM) that is used to send temperature and pressure information out of the biological environment. The RF carrier frequency is 174-216 MHz and a pair of RF bursts (pulses) is transmitted at a frequency of about 1-2 Hz. The transmission range is 3 to 10 feet, depending on the position of the transmitter in the body and its biological environment. The entire transmitter is encapsulated in biocompatible silicone rubber. Power is supplied by on-board silver-oxide batteries. The average power consumption of the current design is less than 30 .mu.W., which yields a lifetime of approximately 6-9 months. Chip-on-Board technology (COB) drastically reduces the size of the printed circuit board from 38.times.28 mm to 22.times.8 mm. Unpackaged dies are flip-chip bonded directly onto the printed circuit board, along with surface mount resistors and capacitors. The invention can monitor additional physiological parameters including, but not limited to, ECG, blood gases, glucose, and ions such as calcium, potassium, and sodium.

Advanced Sensor Systems for Biotelemetry

NASA Technical Reports Server (NTRS)

Hines, John W. (Inventor); Somps, Christopher J. (Inventor); Ricks, Robert D. (Inventor); Mundt, Carsten W. (Inventor)

2003-01-01

The present invention relates to telemetry-based sensing systems that continuously measures physical, chemical and biological parameters. More specifically, these sensing systems comprise a small, modular, low-power implantable biotelemetry system capable of continuously sensing physiological characteristics using implantable transmitters, a receiver, and a data acquisition system to analyze and record the transmitted signal over several months. The preferred embodiment is a preterm labor and fetal monitoring system. Key features of the invention include Pulse Interval Modulation (PIM) that is used to send temperature and pressure information out of the biological environment. The RF carrier frequency is 174-216 MHz and a pair of RF bursts (pulses) is transmitted at a frequency of about 1-2 Hz. The transmission range is 3 to 10 feet, depending on the position of the transmitter in the body and its biological environment. The entire transmitter is encapsulated in biocompatible silicone rubber. Power is supplied by on-board silver-oxide batteries. The average power consumption of the current design is less than 30 microW, which yields a lifetime of approximately 6 - 9 months. Chip-on-Board technology (COB) drastically reduces the size of the printed circuit board from 38 x 28 mm to 22 x 8 mm. Unpackaged dies are flip-chip bonded directly onto the printed circuit board, along with surface mount resistors and capacitors. The invention can monitor additional physiological parameters including, but not limited to, ECG, blood gases, glucose, and ions such as calcium, potassium, and sodium.

Effect of ultrasonic capillary dynamics on the mechanics of thermosonic ball bonding.

PubMed

Huang, Yan; Shah, Aashish; Mayer, Michael; Zhou, Norman Y; Persic, John

2010-01-01

Microelectronic wire bonding is an essential step in today's microchip production. It is used to weld (bond) microwires to metallized pads of integrated circuits using ultrasound with hundreds of thousands of vibration cycles. Thermosonic ball bonding is the most popular variant of the wire bonding process and frequently investigated using finite element (FE) models that simplify the ultrasonic dynamics of the process with static or quasistatic boundary conditions. In this study, the ultrasonic dynamics of the bonding tool (capillary), made from Al(2)O(3), is included in a FE model. For more accuracy of the FE model, the main material parameters are measured. The density of the capillary was measured to be rho(cap) = 3552 +/- 100 kg/m(3). The elastic modulus of the capillary, E(cap) = 389 +/- 11 GPa, is found by comparing an auxiliary FE model of the free vibrating capillary with measured values. A capillary "nodding effect" is identified and found to be essential when describing the ultrasonic vibration shape. A main FE model builds on these results and adds bonded ball, pad, chip, and die attach components. There is excellent agreement between the main model and the ultrasonic force measured at the interface on a test chip with stress microsensors. Bonded ball and underpad stress results are reported. When adjusted to the same ultrasonic force, a simplified model without ultrasonic dynamics and with an infinitely stiff capillary tip is substantially off target by -40% for the maximum underpad stress. The compliance of the capillary causes a substantial inclination effect at the bonding interface between wire and pad. This oscillating inclination effect massively influences the stress fields under the pad and is studied in more detail. For more accurate results, it is therefore recommended to include ultrasonic dynamics of the bonding tool in mechanical FE models of wire bonding.

Assembly of opto-electronic module with improved heat sink

DOEpatents

Chan, Benson; Fortier, Paul Francis; Freitag, Ladd William; Galli, Gary T.; Guindon, Francois; Johnson, Glen Walden; Letourneau, Martial; Sherman, John H.; Tetreault, Real

2004-11-23

A heat sink for a transceiver optoelectronic module including dual direct heat paths and a structure which encloses a number of chips having a central web which electrically isolates transmitter and receiver chips from each other. A retainer for an optical coupler having a port into which epoxy is poured. An overmolded base for an optoelectronic module having epoxy flow controller members built thereon. Assembly methods for an optoelectronic module including gap setting and variation of a TAB bonding process.

Thick resist for MEMS processing

NASA Astrophysics Data System (ADS)

Brown, Joe; Hamel, Clifford

2001-11-01

The need for technical innovation is always present in today's economy. Microfabrication methods have evolved in support of the demand for smaller and faster integrated circuits with price performance improvements always in the scope of the manufacturing design engineer. The dispersion of processing technology spans well beyond IC fabrication today with batch fabrication and wafer scale processing lending advantages to MEMES applications from biotechnology to consumer electronics from oil exploration to aerospace. Today the demand for innovative processing techniques that enable technology is apparent where only a few years ago appeared too costly or not reliable. In high volume applications where yield and cost improvements are measured in fractions of a percent it is imperative to have process technologies that produce consistent results. Only a few years ago thick resist coatings were limited to thickness less than 20 microns. Factors such as uniformity, edge bead and multiple coatings made high volume production impossible. New developments in photoresist formulation combined with advanced coating equipment techniques that closely controls process parameters have enable thick photoresist coatings of 70 microns with acceptable uniformity and edge bead in one pass. Packaging of microelectronic and micromechanical devices is often a significant cost factor and a reliability issue for high volume low cost production. Technologies such as flip- chip assembly provide a solution for cost and reliability improvements over wire bond techniques. The processing for such technology demands dimensional control and presents a significant cost savings if it were compatible with mainstream technologies. Thick photoresist layers, with good sidewall control would allow wafer-bumping technologies to penetrate the barriers to yield and production where costs for technology are the overriding issue. Single pass processing is paramount to the manufacturability of packaging technology. Uniformity and edge bead control defined the success of process implementation. Today advanced packaging solutions are created with thick photoresist coatings. The techniques and results will be presented.

Upset due to a single particle caused propagated transients in a bulk CMOS microprocessor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Leavy, J.F.; Hoffmann, L.F.; Shoran, R.W.

1991-12-01

This paper reports on data pattern advances observed in preset, single event upset (SEU) hardened clocked flip-flops, during static Cf-252 exposures on a bulk CMOS microprocessor, that were attributable to particle caused anomalous clock signals, or propagated transients. SPICE simulations established that particle strikes in the output nodes of a clock control logic flip-flop could produce transients of sufficient amplitude and duration to be accepted as legitimate pulses by clock buffers fed by the flip-flop's output nodes. The buffers would then output false clock pulses, thereby advancing the state of the present flip-flops. Masking the clock logic on one ofmore » the test chips made the flip-flop data advance cease, confirming the clock logic as the source of the SEU. By introducing N{sub 2} gas, at reduced pressures, into the SEU test chamber to attenuate Cf-252 particle LET's, a 24-26 MeV-cm{sup 2}/mg LET threshold was deduced. Subsequent tests, at the 88-inch cyclotron at Berkeley, established an LET threshold of 30 MeV-cm{sup 2}/mg (283 MeV Cu at 0{degrees}) for the generation of false clocks. Cyclotron SEU tests are considered definitive, while Cf-252 data usually is not. However, in this instance Cf-252 tests proved analytically useful, providing SEU characterization data that was both timely and inexpensive.« less

Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

PubMed

Shen, Wen-Wei; Lin, Yu-Min; Wu, Sheng-Tsai; Lee, Chia-Hsin; Huang, Shin-Yi; Chang, Hsiang-Hung; Chang, Tao-Chih; Chen, Kuan-Neng

2018-08-01

In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

Knudsen pump produced via silicon deep RIE, thermal oxidation, and anodic bonding processes for on-chip vacuum pumping

NASA Astrophysics Data System (ADS)

Van Toan, Nguyen; Inomata, Naoki; Trung, Nguyen Huu; Ono, Takahito

2018-05-01

This work describes the fabrication and evaluation of the Knudsen pump for on-chip vacuum pumping that works based on the principle of a thermal transpiration. Three AFM (atomic force microscope) cantilevers are integrated into small chambers with a size of 5 mm  ×  3 mm  ×  0.4 mm for the pump’s evaluation. Knudsen pump is fabricated using deep RIE (reactive ion etching), wet thermal oxidation and anodic bonding processes. The fabricated device is evaluated by monitoring the quality (Q) factor of the integrated cantilevers. The Q factor of the cantilever is increased from 300 -1150 in cases without and with a temperature difference approximately 25 °C between the top (the hot side at 40 °C) and bottom (the cold side at 15 °C) sides of the fabricated device, respectively. The evacuated chamber pressure of around 10 kPa is estimated from the Q factor of the integrated cantilevers.

High reliability bond program using small diameter aluminum wire

NASA Technical Reports Server (NTRS)

Macha, M.; Thiel, R. A.

1975-01-01

The program was undertaken to characterize the performance of small diameter aluminum wire ultrasonically bonded to conductors commonly encountered in hybrid assemblies, and to recommend guidelines for improving this performance. Wire, 25.4, 38.1 and 50.8 um (1, 1.5 and 2 mil), was used with bonding metallization consisting of thick film gold, thin film gold and aluminum as well as conventional aluminum pads on semiconductor chips. The chief tool for evaluating the performance was the double bond pull test in conjunction with a 72 hour - 150 C heat soak and -65 C to +150 C thermal cycling. In practice the thermal cycling was found to have relatively little effect compared to the heat soak. Pull strength will decrease after heat soak as a result of annealing of the aluminum wire; when bonded to thick film gold, the pull strength decreased by about 50% (weakening of the bond interface was the major cause of the reduction). Bonds to thin film gold lost about 30 - 40% of their initial pull strenth; weakening of the wire itself at the bond heel was the predominant cause. Bonds to aluminum substrate metallization lost only about 22%. Bonds between thick and thin film gold substrate metallization and semiconductor chips substantiated the previous conclusions but also showed that in about 20 to 25% of the cases, bond interface failure occurred at the semiconductor chip.

Reliable bonding using indium-based solders

NASA Astrophysics Data System (ADS)

Cheong, Jongpil; Goyal, Abhijat; Tadigadapa, Srinivas; Rahn, Christopher

2004-01-01

Low temperature bonding techniques with high bond strengths and reliability are required for the fabrication and packaging of MEMS devices. Indium and indium-tin based bonding processes are explored for the fabrication of a flextensional MEMS actuator, which requires the integration of lead zirconate titanate (PZT) substrate with a silicon micromachined structure at low temperatures. The developed technique can be used either for wafer or chip level bonding. The lithographic steps used for the patterning and delineation of the seed layer limit the resolution of this technique. Using this technique, reliable bonds were achieved at a temperature of 200°C. The bonds yielded an average tensile strength of 5.41 MPa and 7.38 MPa for samples using indium and indium-tin alloy solders as the intermediate bonding layers respectively. The bonds (with line width of 100 microns) showed hermetic sealing capability of better than 10-11 mbar-l/s when tested using a commercial helium leak tester.

Reliable bonding using indium-based solders

NASA Astrophysics Data System (ADS)

Cheong, Jongpil; Goyal, Abhijat; Tadigadapa, Srinivas; Rahn, Christopher

2003-12-01

Low temperature bonding techniques with high bond strengths and reliability are required for the fabrication and packaging of MEMS devices. Indium and indium-tin based bonding processes are explored for the fabrication of a flextensional MEMS actuator, which requires the integration of lead zirconate titanate (PZT) substrate with a silicon micromachined structure at low temperatures. The developed technique can be used either for wafer or chip level bonding. The lithographic steps used for the patterning and delineation of the seed layer limit the resolution of this technique. Using this technique, reliable bonds were achieved at a temperature of 200°C. The bonds yielded an average tensile strength of 5.41 MPa and 7.38 MPa for samples using indium and indium-tin alloy solders as the intermediate bonding layers respectively. The bonds (with line width of 100 microns) showed hermetic sealing capability of better than 10-11 mbar-l/s when tested using a commercial helium leak tester.

3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer.

PubMed

Asano, Sho; Muroyama, Masanori; Nakayama, Takahiro; Hata, Yoshiyuki; Nonomura, Yutaka; Tanaka, Shuji

2017-10-25

This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively.

3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer †

PubMed Central

Asano, Sho; Nakayama, Takahiro; Hata, Yoshiyuki; Tanaka, Shuji

2017-01-01

This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively. PMID:29068429

Comparative experimental and simulation studies of high-power AlGaN-based 353 nm ultraviolet flip-chip and top-emitting LEDs

NASA Astrophysics Data System (ADS)

Liu, Mengling; Zhou, Shengjun; Liu, Xingtong; Gao, Yilin; Ding, Xinghuo

2018-03-01

Experimental and simulation studies of high-power AlGaN-based 353 nm ultraviolet (UV) flip-chip (FC) and top-emitting (TE) light-emitting diodes (LEDs) are performed here. To improve the optical and electrical properties of ultraviolet LEDs, we fabricate high-power FC-UV LEDs with Ta2O5/SiO2 distributed Bragg reflectors (DBRs) and a strip-shaped SiO2 current blocking layer (CBL). The reflectance of fourteen pairs of Ta2O5/SiO2 DBRs is 96.4% at 353 nm. The strip-shaped SiO2 CBL underneath the strip-shaped p-electrode can prevent the current concentrating in regions immediately adjacent to the p-electrode where the overlying opaque p-electrode metal layer absorbs the emitted UV light. Moreover, two-level metallization electrodes are used to improve current spreading. Our numerical results show that FC-UV LED has a more favorable current spreading uniformity than TE-UV LED. The light output power of 353 nm FC-UV LED was 23.22 mW at 350 mA, which is 24.7% higher than that of TE-UV LED.

Nucleation rates of Sn in undercooled Sn-Ag-Cu flip-chip solder joints

NASA Astrophysics Data System (ADS)

Arfaei, B.; Benedict, M.; Cotts, E. J.

2013-11-01

The nucleation of Sn from the melt in commercial SnAgCu flip chip solder joints was monitored at a number of different temperatures. Nucleation rates were estimated from measurements of nucleation times for 440 solder balls after one reflow and were found to be well epitomized by the expression I = 2 × 109 exp[(-1.6 × 105)/(T × (ΔT)2)] m-3 s-1, as per classical nucleation theory. After an additional reflow, the nucleation rates of the same 440 samples were observed to increase to I = 2 × 109 exp[(-8.9 × 104)/(T × (ΔT)2)] m-3 s-1. Thus it was shown that the expressions of classical nucleation theory well characterize nucleation kinetics for this system. These changes in nucleation kinetics were correlated with continued dissolution of Al and Ni in to the SnAgCu melt. Such increases in nucleation rates meant increases in the average solidification temperatures of the solder balls after reflow. Variations in the Sn grain morphology of the solder joints were correlated with these changes in solidification temperature, with larger Sn grains (beach ball Sn grain morphology) observed at higher solidification temperatures.

Quantum Devices Bonded Beneath a Superconducting Shield: Part 2

NASA Astrophysics Data System (ADS)

McRae, Corey Rae; Abdallah, Adel; Bejanin, Jeremy; Earnest, Carolyn; McConkey, Thomas; Pagel, Zachary; Mariantoni, Matteo

The next-generation quantum computer will rely on physical quantum bits (qubits) organized into arrays to form error-robust logical qubits. In the superconducting quantum circuit implementation, this architecture will require the use of larger and larger chip sizes. In order for on-chip superconducting quantum computers to be scalable, various issues found in large chips must be addressed, including the suppression of box modes (due to the sample holder) and the suppression of slot modes (due to fractured ground planes). By bonding a metallized shield layer over a superconducting circuit using thin-film indium as a bonding agent, we have demonstrated proof of concept of an extensible circuit architecture that holds the key to the suppression of spurious modes. Microwave characterization of shielded transmission lines and measurement of superconducting resonators were compared to identical unshielded devices. The elimination of box modes was investigated, as well as bond characteristics including bond homogeneity and the presence of a superconducting connection.

Chip-scale thermal management of high-brightness LED packages

NASA Astrophysics Data System (ADS)

Arik, Mehmet; Weaver, Stanton

2004-10-01

The efficiency and reliability of the solid-state lighting devices strongly depend on successful thermal management. Light emitting diodes, LEDs, are a strong candidate for the next generation, general illumination applications. LEDs are making great strides in terms of lumen performance and reliability, however the barrier to widespread use in general illumination still remains the cost or $/Lumen. LED packaging designers are pushing the LED performance to its limits. This is resulting in increased drive currents, and thus the need for lower thermal resistance packaging designs. As the power density continues to rise, the integrity of the package electrical and thermal interconnect becomes extremely important. Experimental results with high brightness LED packages show that chip attachment defects can cause significant thermal gradients across the LED chips leading to premature failures. A numerical study was also carried out with parametric models to understand the chip active layer temperature profile variation due to the bump defects. Finite element techniques were utilized to evaluate the effects of localized hot spots at the chip active layer. The importance of "zero defects" in one of the more popular interconnect schemes; the "epi down" soldered flip chip configuration is investigated and demonstrated.

640x512 pixel InGaAs FPAs for short-wave infrared and visible light imaging

NASA Astrophysics Data System (ADS)

Shao, Xiumei; Yang, Bo; Huang, Songlei; Wei, Yang; Li, Xue; Zhu, Xianliang; Li, Tao; Chen, Yu; Gong, Haimei

2017-08-01

The spectral irradiance of moonlight and air glow is mainly in the wavelength region from visible to short-wave infrared (SWIR) band. The imaging over the wavelength range of visible to SWIR is of great significance for applications such as civil safety, night vision, and agricultural sorting. In this paper, 640×512 visible-SWIR InGaAs focal plane arrays (FPAs) were studied for night vision and SWIR imaging. A special epitaxial wafer structure with etch-stop layer was designed and developed. Planar-type 640×512 InGaAs detector arrays were fabricated. The photosensitive arrays were bonded with readout circuit through Indium bumps by flip-chip process. Then, the InP substrate was removed by mechanical thinning and chemical wet etching. The visible irradiance can reach InGaAs absorption layer and then to be detected. As a result, the detection spectrum of the InGaAs FPAs has been extended toward visible spectrum from 0.5μm to 1.7μm. The quantum efficiency is approximately 15% at 0.5μm, 30% at 0.7μm, 50% at 0.8μm, 90% at 1.55μm. The average peak detectivity is higher than 2×1012 cm·Hz1/2/W at room temperature with an integrated time of 10 ms. The Visible-SWIR InGaAs FPAs were applied to an imaging system for SWIR and visible light imaging.

Induced Polarization Influences the Fundamental Forces in DNA Base Flipping

PubMed Central

2015-01-01

Base flipping in DNA is an important process involved in genomic repair and epigenetic control of gene expression. The driving forces for these processes are not fully understood, especially in the context of the underlying dynamics of the DNA and solvent effects. We studied double-stranded DNA oligomers that have been previously characterized by imino proton exchange NMR using both additive and polarizable force fields. Our results highlight the importance of induced polarization on the base flipping process, yielding near-quantitative agreement with experimental measurements of the equilibrium between the base-paired and flipped states. Further, these simulations allow us to quantify for the first time the energetic implications of polarization on the flipping pathway. Free energy barriers to base flipping are reduced by changes in dipole moments of both the flipped bases that favor solvation of the bases in the open state and water molecules adjacent to the flipping base. PMID:24976900

The fabrication of flip-covered plasmonic nanostructure surfaces with enhanced wear resistance

NASA Astrophysics Data System (ADS)

Jung, Joo-Yun; Sung, Sang-Keun; Kim, Kwang-Seop; Cheon, So-Hui; Lee, Jihye; Choi, Jun-Hyuk; Lee, Eungsug

2017-01-01

Exposed nanostructure surfaces often suffer from external dynamic wear, particularly when used in human interaction, resulting in surface defects and the degradation of plasmonic resonance properties particularly in terms of transmittance extinction rate and peak-to-valley slope. In this work, a method for the fabrication of flip-covered silver nanostructure-arrayed surfaces is shown to enhance wear resistance. Selectively transferred silver dot and silver webbed-trench exposed reference samples were fabricated by metal nanoimprint, and flip-covered samples were created by flipping and bonding reference samples onto a PET film coated with an adhesive layer. The samples' spectral transmittance was measured before and after a dynamic wear test. Some spectral shift was observed due to the change in refractive index of the surrounding media, but this was not as significant as the effects of the other chosen geometry factors. It was found that dynamic wear had a greater effect on the plasmonic resonance behavior of the exposed samples than in those that had been flip-covered. This suggests that flip-covering may be an effective strategy for the protection of plasmonic resonators against dynamic wear. It is expected that the slight variations in spectral transmittance could be compensated through proper tuning of the sample geometry.

Ultrasonic friction power during Al wire wedge-wedge bonding

NASA Astrophysics Data System (ADS)

Shah, A.; Gaul, H.; Schneider-Ramelow, M.; Reichl, H.; Mayer, M.; Zhou, Y.

2009-07-01

Al wire bonding, also called ultrasonic wedge-wedge bonding, is a microwelding process used extensively in the microelectronics industry for interconnections to integrated circuits. The bonding wire used is a 25μm diameter AlSi1 wire. A friction power model is used to derive the ultrasonic friction power during Al wire bonding. Auxiliary measurements include the current delivered to the ultrasonic transducer, the vibration amplitude of the bonding tool tip in free air, and the ultrasonic force acting on the bonding pad during the bond process. The ultrasonic force measurement is like a signature of the bond as it allows for a detailed insight into mechanisms during various phases of the process. It is measured using piezoresistive force microsensors integrated close to the Al bonding pad (Al-Al process) on a custom made test chip. A clear break-off in the force signal is observed, which is followed by a relatively constant force for a short duration. A large second harmonic content is observed, describing a nonsymmetric deviation of the signal wave form from the sinusoidal shape. This deviation might be due to the reduced geometrical symmetry of the wedge tool. For bonds made with typical process parameters, several characteristic values used in the friction power model are determined. The ultrasonic compliance of the bonding system is 2.66μm/N. A typical maximum value of the relative interfacial amplitude of ultrasonic friction is at least 222nm. The maximum interfacial friction power is at least 11.5mW, which is only about 4.8% of the total electrical power delivered to the ultrasonic generator.

Comment on "Enhancement of flip-chip white light-emitting diodes with a one-dimensional photonic crystal".

PubMed

Liu, Zong-Yuan; Liu, Sheng; Wang, Kai; Luo, Xiao-Bing

2010-06-01

We show that research presented in Opt. Lett.34, 301 (2009)OPLEDP0146-959210.1364/OL.34.000301 applied questionable phosphor definitions and a questionable simulation procedure for light-emitting diodes. Our simulation indicates that a one-dimensional photonic crystal is beneficial for color control but cannot improve the light extraction as asserted in that Letter.

DOE Office of Scientific and Technical Information (OSTI.GOV)

McAdams, Brian J.; Pearson, Raymond A.

With the continuing trend of decreasing feature sizes in flip-chip assemblies, the reliability tolerance to interfacial flaws is also decreasing. Small-scale disbonds will become more of a concern, pointing to the need for a better understanding of the initiation stage of interfacial delamination. With most accepted adhesion metric methodologies tailored to predict failure under the prior existence of a disbond, the study of the initiation phenomenon is open to development and standardization of new testing procedures. Traditional fracture mechanics approaches are not suitable, as the mathematics assume failure to originate at a disbond or crack tip. Disbond initiation is believedmore » to first occur at free edges and corners, which act as high stress concentration sites and exhibit singular stresses similar to a crack tip, though less severe in intensity. As such, a 'fracture mechanics-like' approach may be employed which defines a material parameter--a critical stress intensity factor (K{sub c})--that can be used to predict when initiation of a disbond at an interface will occur. The factors affecting the adhesion of underfill/polyimide interfaces relevant to flip-chip assemblies were investigated in this study. The study consisted of two distinct parts: a comparison of the initiation and propagation phenomena and a comparison of the relationship between sub-critical and critical initiation of interfacial failure. The initiation of underfill interfacial failure was studied by characterizing failure at a free-edge with a critical stress intensity factor. In comparison with the interfacial fracture toughness testing, it was shown that a good correlation exists between the initiation and propagation of interfacial failures. Such a correlation justifies the continuing use of fracture mechanics to predict the reliability of flip-chip packages. The second aspect of the research involved fatigue testing of tensile butt joint specimens to determine lifetimes at sub-critical load levels. The results display an interfacial strength ranking similar to that observed during monotonic testing. The fatigue results indicate that monotonic fracture mechanics testing may be an adequate screening tool to help predict cyclic underfill failure; however lifetime data is required to predict reliability.« less

Chip-scale integrated optical interconnects: a key enabler for future high-performance computing

NASA Astrophysics Data System (ADS)

Haney, Michael; Nair, Rohit; Gu, Tian

2012-01-01

High Performance Computing (HPC) systems are putting ever-increasing demands on the throughput efficiency of their interconnection fabrics. In this paper, the limits of conventional metal trace-based inter-chip interconnect fabrics are examined in the context of state-of-the-art HPC systems, which currently operate near the 1 GFLOPS/W level. The analysis suggests that conventional metal trace interconnects will limit performance to approximately 6 GFLOPS/W in larger HPC systems that require many computer chips to be interconnected in parallel processing architectures. As the HPC communications bottlenecks push closer to the processing chips, integrated Optical Interconnect (OI) technology may provide the ultra-high bandwidths needed at the inter- and intra-chip levels. With inter-chip photonic link energies projected to be less than 1 pJ/bit, integrated OI is projected to enable HPC architecture scaling to the 50 GFLOPS/W level and beyond - providing a path to Peta-FLOPS-level HPC within a single rack, and potentially even Exa-FLOPSlevel HPC for large systems. A new hybrid integrated chip-scale OI approach is described and evaluated. The concept integrates a high-density polymer waveguide fabric directly on top of a multiple quantum well (MQW) modulator array that is area-bonded to the Silicon computing chip. Grayscale lithography is used to fabricate 5 μm x 5 μm polymer waveguides and associated novel small-footprint total internal reflection-based vertical input/output couplers directly onto a layer containing an array of GaAs MQW devices configured to be either absorption modulators or photodetectors. An external continuous wave optical "power supply" is coupled into the waveguide links. Contrast ratios were measured using a test rider chip in place of a Silicon processing chip. The results suggest that sub-pJ/b chip-scale communication is achievable with this concept. When integrated into high-density integrated optical interconnect fabrics, it could provide a seamless interconnect fabric spanning the intra-

Syringe Injectable Electronics: Precise Targeted Delivery with Quantitative Input/Output Connectivity.

PubMed

Hong, Guosong; Fu, Tian-Ming; Zhou, Tao; Schuhmann, Thomas G; Huang, Jinlin; Lieber, Charles M

2015-10-14

Syringe-injectable mesh electronics with tissue-like mechanical properties and open macroporous structures is an emerging powerful paradigm for mapping and modulating brain activity. Indeed, the ultraflexible macroporous structure has exhibited unprecedented minimal/noninvasiveness and the promotion of attractive interactions with neurons in chronic studies. These same structural features also pose new challenges and opportunities for precise targeted delivery in specific brain regions and quantitative input/output (I/O) connectivity needed for reliable electrical measurements. Here, we describe new results that address in a flexible manner both of these points. First, we have developed a controlled injection approach that maintains the extended mesh structure during the "blind" injection process, while also achieving targeted delivery with ca. 20 μm spatial precision. Optical and microcomputed tomography results from injections into tissue-like hydrogel, ex vivo brain tissue, and in vivo brains validate our basic approach and demonstrate its generality. Second, we present a general strategy to achieve up to 100% multichannel I/O connectivity using an automated conductive ink printing methodology to connect the mesh electronics and a flexible flat cable, which serves as the standard "plug-in" interface to measurement electronics. Studies of resistance versus printed line width were used to identify optimal conditions, and moreover, frequency-dependent noise measurements show that the flexible printing process yields values comparable to commercial flip-chip bonding technology. Our results address two key challenges faced by syringe-injectable electronics and thereby pave the way for facile in vivo applications of injectable mesh electronics as a general and powerful tool for long-term mapping and modulation of brain activity in fundamental neuroscience through therapeutic biomedical studies.

Microstructural Evolution of Ni-Sn Transient Liquid Phase Sintering Bond during High-Temperature Aging

NASA Astrophysics Data System (ADS)

Feng, Hongliang; Huang, Jihua; Peng, Xianwen; Lv, Zhiwei; Wang, Yue; Yang, Jian; Chen, Shuhai; Zhao, Xingke

2018-05-01

For high-temperature-resistant packaging of new generation power chip, a chip packaging simulation structure of Ni/Ni-Sn/Ni was bonded by a transient liquid-phase sintering process. High-temperature aging experiments were carried out to investigate joint heat stability. The microstructural evolution and mechanism during aging, and mechanical properties after aging were analyzed. The results show that the 30Ni-70Sn bonding layer as-bonded at 340°C for 240 min is mainly composed of Ni3Sn4 and residual Ni particles. When aged at 350°C, because of the difficulty of nucleation for Ni3Sn and quite slow growth of Ni3Sn2, the bonding layer is stable and the strength of that doesn't change obviously with aging time. When aging temperature increased to 500°C, however, the residual Ni particles were gradually dissolved and the bonding layer formed a stable structure with dominated Ni3Sn2 after 36 h. Meanwhile, due to the volume shrinkage (4.43%) from Ni3Sn2 formation, a number of voids were formed. The shear strength shows an increase, resulting from Ni3Sn2 formation, but then it decreases slightly caused by voids. After aging at 500°C for 100 h, shear strength is still maintained at 29.6 MPa. In addition, the mechanism of void formation was analyzed and microstructural evolution model was also established.

Effect of Silver Flakes in Silver Paste on the Joining Process and Properties of Sandwich Power Modules (IGBTs Chip/Silver Paste/Bare Cu)

NASA Astrophysics Data System (ADS)

Zhao, Su-Yan; Li, Xin; Mei, Yun-Hui; Lu, Guo-Quan

2016-11-01

In this study, a silver paste has been introduced for attaching chips onto bare Cu substrates (without coating) without applying pressure. Small nano-thickness Ag flakes, measuring 1 μm-5 μm length, were embedded uniformly in Ag nanoparticles for improving the density of the material. The presence of silver flakes in the silver paste affected the joining process and its microstructure. Microstructure characterization revealed that densification of the silver layer was affected by the presence of silver flakes as the flakes coarsened and formed reactive in situ nanoparticles, which facilitated the sintering between the flakes and the incorporated nanoparticles. Coarsening of silver flakes depended on the sintering temperature, time, and the atmosphere, which affected the decomposition and burning out of organics presented on the surface of the flakes. A high-density silver layer was obtained due to the presence of compact silver flakes. With an increase in the microstructure density, a higher bonding strength and a lower thermal impedance of the sintered joints were achieved. On performing pressureless sintering at 270°C for 30 min under 99.99% N2 or 4% H2/N2, the bonding strength and thermal impedance for 11 × 11 mm2 chips were excellent, measuring approximately 21.9 MPa and 0.077°C/W, respectively.

CE chips fabricated by injection molding and polyethylene/thermoplastic elastomer film packaging methods.

PubMed

Huang, Fu-Chun; Chen, Yih-Far; Lee, Gwo-Bin

2007-04-01

This study presents a new packaging method using a polyethylene/thermoplastic elastomer (PE/TPE) film to seal an injection-molded CE chip made of either poly(methyl methacrylate) (PMMA) or polycarbonate (PC) materials. The packaging is performed at atmospheric pressure and at room temperature, which is a fast, easy, and reliable bonding method to form a sealed CE chip for chemical analysis and biomedical applications. The fabrication of PMMA and PC microfluidic channels is accomplished by using an injection-molding process, which could be mass-produced for commercial applications. In addition to microfluidic CE channels, 3-D reservoirs for storing biosamples, and CE buffers are also formed during this injection-molding process. With this approach, a commercial CE chip can be of low cost and disposable. Finally, the functionality of the mass-produced CE chip is demonstrated through its successful separation of phiX174 DNA/HaeIII markers. Experimental data show that the S/N for the CE chips using the PE/TPE film has a value of 5.34, when utilizing DNA markers with a concentration of 2 ng/microL and a CE buffer of 2% hydroxypropyl-methylcellulose (HPMC) in Tris-borate-EDTA (TBE) with 1% YO-PRO-1 fluorescent dye. Thus, the detection limit of the developed chips is improved. Lastly, the developed CE chips are used for the separation and detection of PCR products. A mixture of an amplified antibiotic gene for Streptococcus pneumoniae and phiX174 DNA/HaeIII markers was successfully separated and detected by using the proposed CE chips. Experimental data show that these DNA samples were separated within 2 min. The study proposed a promising method for the development of mass-produced CE chips.

Impact of Isothermal Aging and Testing Temperature on Large Flip-Chip BGA Interconnect Mechanical Shock Performance

NASA Astrophysics Data System (ADS)

Lee, Tae-Kyu; Chen, Zhiqiang; Guirguis, Cherif; Akinade, Kola

2017-10-01

The stability of solder interconnects in a mechanical shock environment is crucial for large body size flip-chip ball grid array (FCBGA) electronic packages. Additionally, the junction temperature increases with higher electric power condition, which brings the component into an elevated temperature environment, thus introducing another consideration factor for mechanical stability of interconnection joints. Since most of the shock performance data available were produced at room temperature, the effect of elevated temperature is of interest to ensure the reliability of the device in a mechanical shock environment. To achieve a stable␣interconnect in a dynamic shock environment, the interconnections must tolerate mechanical strain, which is induced by the shock wave input and reaches the particular component interconnect joint. In this study, large body size (52.5 × 52.5 mm2) FCBGA components assembled on 2.4-mm-thick boards were tested with various isothermal pre-conditions and testing conditions. With a heating element embedded in the test board, a test temperature range from room temperature to 100°C was established. The effects of elevated temperature on mechanical shock performance were investigated. Failure and degradation mechanisms are identified and discussed based on the microstructure evolution and grain structure transformations.

Phosphor-Free InGaN White Light Emitting Diodes Using Flip-Chip Technology

PubMed Central

Li, Ying-Chang; Chang, Liann-Be; Chen, Hou-Jen; Yen, Chia-Yi; Pan, Ke-Wei; Huang, Bohr-Ran; Kuo, Wen-Yu; Chow, Lee; Zhou, Dan; Popko, Ewa

2017-01-01

Monolithic phosphor-free two-color gallium nitride (GaN)-based white light emitting diodes (LED) have the potential to replace current phosphor-based GaN white LEDs due to their low cost and long life cycle. Unfortunately, the growth of high indium content indium gallium nitride (InGaN)/GaN quantum dot and reported LED’s color rendering index (CRI) are still problematic. Here, we use flip-chip technology to fabricate an upside down monolithic two-color phosphor-free LED with four grown layers of high indium quantum dots on top of the three grown layers of lower indium quantum wells separated by a GaN tunneling barrier layer. The photoluminescence (PL) and electroluminescence (EL) spectra of this white LED reveal a broad spectrum ranging from 475 to 675 nm which is close to an ideal white-light source. The corresponding color temperature and color rendering index (CRI) of the fabricated white LED, operated at 350, 500, and 750 mA, are comparable to that of the conventional phosphor-based LEDs. Insights of the epitaxial structure and the transport mechanism were revealed through the TEM and temperature dependent PL and EL measurements. Our results show true potential in the Epi-ready GaN white LEDs for future solid state lighting applications. PMID:28772792

Analysis of light extraction efficiency enhancement for thin-film-flip-chip InGaN quantum wells light-emitting diodes with GaN micro-domes.

PubMed

Zhao, Peng; Zhao, Hongping

2012-09-10

The enhancement of light extraction efficiency for thin-film flip-chip (TFFC) InGaN quantum wells (QWs) light-emitting diodes (LEDs) with GaN micro-domes on n-GaN layer was studied. The light extraction efficiency of TFFC InGaN QWs LEDs with GaN micro-domes were calculated and compared to that of the conventional TFFC InGaN QWs LEDs with flat surface. The three dimensional finite difference time domain (3D-FDTD) method was used to calculate the light extraction efficiency for the InGaN QWs LEDs emitting at 460nm and 550 nm, respectively. The effects of the GaN micro-dome feature size and the p-GaN layer thickness on the light extraction efficiency were studied systematically. Studies indicate that the p-GaN layer thickness is critical for optimizing the TFFC LED light extraction efficiency. Significant enhancement of the light extraction efficiency (2.5-2.7 times for λ(peak) = 460nm and 2.7-2.8 times for λ(peak) = 550nm) is achievable from TFFC InGaN QWs LEDs with optimized GaN micro-dome diameter and height.

Thermal Design and Characterization of Heterogeneously Integrated InGaP/GaAs HBTs

DOE PAGES

Choi, Sukwon; Peake, Gregory M.; Keeler, Gordon A.; ...

2016-04-21

Flip-chip heterogeneously integrated n-p-n InGaP/GaAs heterojunction bipolar transistors (HBTs) with integrated thermal management on wide-bandgap AlN substrates followed by GaAs substrate removal are demonstrated. Without thermal management, substrate removal after integration significantly aggravates self-heating effects, causing poor I–V characteristics due to excessive device self-heating. An electrothermal codesign scheme is demonstrated that involves simulation (design), thermal characterization, fabrication, and evaluation. Thermoreflectance thermal imaging, electrical-temperature sensitive parameter-based thermometry, and infrared thermography were utilized to assess the junction temperature rise in HBTs under diverse configurations. In order to reduce the thermal resistance of integrated devices, passive cooling schemes assisted by structural modification, i.e.,more » positioning indium bump heat sinks between the devices and the carrier, were employed. By implementing thermal heat sinks in close proximity to the active region of flip-chip integrated HBTs, the junction-to-baseplate thermal resistance was reduced over a factor of two, as revealed by junction temperature measurements and improvement of electrical performance. In conclusion, the suggested heterogeneous integration method accounts for not only electrical but also thermal requirements providing insight into realization of advanced and robust III–V/Si heterogeneously integrated electronics.« less

White light emitting diode based on InGaN chip with core/shell quantum dots

NASA Astrophysics Data System (ADS)

Shen, Changyu; Hong, Yan; Ma, Jiandong; Ming, Jiangzhou

2009-08-01

Quantum dots have many applications in optoelectronic device such as LEDs for its many superior properties resulting from the three-dimensional confinement effect of its carrier. In this paper, single chip white light-emitting diodes (WLEDs) were fabricated by combining blue InGaN chip with luminescent colloidal quantum dots (QDs). Two kinds of QDs of core/shell CdSe /ZnS and core/shell/shell CdSe /ZnS /CdS nanocrystals were synthesized by thermal deposition using cadmium oxide and selenium as precursors in a hot lauric acid and hexadecylamine trioctylphosphine oxide hybrid. This two kinds of QDs exhibited high photoluminescence efficiency with a quantum yield more than 41%, and size-tunable emission wavelengths from 500 to 620 nm. The QDs LED mainly consists of flip luminescent InGaN chip, glass ceramic protective coating, glisten cup, QDs using as the photoluminescence material, pyroceram, gold line, electric layer, dielectric layer, silicon gel and bottom layer for welding. The WLEDs had the CIE coordinates of (0.319, 0.32). The InGaN chip white-light-emitting diodes with quantum dots as the emitting layer are potentially useful in illumination and display applications.

One and two-phonon processes of the spin-flip relaxation in quantum dots: Spin-phonon coupling mechanism

NASA Astrophysics Data System (ADS)

Wang, Zi-Wu; Li, Shu-Shen

2012-07-01

We investigate the spin-flip relaxation in quantum dots using a non-radiation transition approach based on the descriptions for the electron-phonon deformation potential and Fröhlich interaction in the Pavlov-Firsov spin-phonon Hamiltonian. We give the comparisons of the electron relaxations with and without spin-flip assisted by one and two-phonon processes. Calculations are performed for the dependence of the relaxation time on the external magnetic field, the temperature and the energy separation between the Zeeman sublevels of the ground and first-excited state. We find that the electron relaxation time of the spin-flip process is more longer by three orders of magnitudes than that of no spin-flip process.

Aluminum-Scandium: A Material for Semiconductor Packaging

NASA Astrophysics Data System (ADS)

Geissler, Ute; Thomas, Sven; Schneider-Ramelow, Martin; Mukhopadhyay, Biswajit; Lang, Klaus-Dieter

2016-10-01

A well-known aluminum-scandium (Al-Sc) alloy, already used in lightweight sports equipment, is about to be established for use in electronic packaging. One application for Al-Sc alloy is manufacture of bonding wires. The special feature of the alloy is its ability to harden by precipitation. The new bonding wires with electrical conductivity similar to pure Al wires can be processed on common wire bonders for aluminum wedge/wedge (w/w) bonding. The wires exhibit very fine-grained microstructure. Small Al3Sc particles are the main reason for its high strength and prevent recrystallization and grain growth at higher temperatures (>150°C). After the wire-bonding process, the interface is well closed. Reliability investigations by active power cycling demonstrated considerably improved lifetime compared with pure Al heavy wires. Furthermore, the Al-Sc alloy was sputter-deposited onto silicon wafer to test it as chip metallization in copper (Cu) ball/wedge bonding technology. After deposition, the layers exhibited fine-grained columnar structure and small coherent Al3Sc particles with dimensions of a few nanometers. These particles inhibit softening processes such as Al splashing in fine wire bonding processes and increase the thickness of remnant Al under the copper balls to 85% of the initial thickness.

Characterization of the Photon Counting CHASE Jr., Chip Built in a 40-nm CMOS Process With a Charge Sharing Correction Algorithm Using a Collimated X-Ray Beam

DOE Office of Scientific and Technical Information (OSTI.GOV)

Krzyżanowska, A.; Deptuch, G. W.; Maj, P.

This paper presents the detailed characterization of a single photon counting chip, named CHASE Jr., built in a CMOS 40-nm process, operating with synchrotron radiation. The chip utilizes an on-chip implementation of the C8P1 algorithm. The algorithm eliminates the charge sharing related uncertainties, namely, the dependence of the number of registered photons on the discriminator’s threshold, set for monochromatic irradiation, and errors in the assignment of an event to a certain pixel. The article presents a short description of the algorithm as well as the architecture of the CHASE Jr., chip. The analog and digital functionalities, allowing for proper operationmore » of the C8P1 algorithm are described, namely, an offset correction for two discriminators independently, two-stage gain correction, and different operation modes of the digital blocks. The results of tests of the C8P1 operation are presented for the chip bump bonded to a silicon sensor and exposed to the 3.5- μm -wide pencil beam of 8-keV photons of synchrotron radiation. It was studied how sensitive the algorithm performance is to the chip settings, as well as the uniformity of parameters of the analog front-end blocks. Presented results prove that the C8P1 algorithm enables counting all photons hitting the detector in between readout channels and retrieving the actual photon energy.« less

Investigation of ball bond integrity for 0.8 mil (20 microns) diameter gold bonding wire on low k die in wire bonding technology

NASA Astrophysics Data System (ADS)

Kudtarkar, Santosh Anil

Microelectronics technology has been undergoing continuous scaling to accommodate customer driven demand for smaller, faster and cheaper products. This demand has been satisfied by using novel materials, design techniques and processes. This results in challenges for the chip connection technology and also the package technology. The focus of this research endeavor was restricted to wire bond interconnect technology using gold bonding wires. Wire bond technology is often regarded as a simple first level interconnection technique. In reality, however, this is a complex process that requires a thorough understanding of the interactions between the design, material and process variables, and their impact on the reliability of the bond formed during this process. This research endeavor primarily focused on low diameter, 0.8 mil thick (20 mum) diameter gold bonding wire. Within the scope of this research, the integrity of the ball bond formed by 1.0 mil (25 mum) and 0.8 mil (20 mum) diameter wires was compared. This was followed by the evaluation of bonds formed on bond pads having doped SiO2 (low k) as underlying structures. In addition, the effect of varying the percentage of the wire dopant, palladium and bonding process parameters (bonding force, bond time, ultrasonic energy) for 0.8 mil (20 mum) bonding wire was also evaluated. Finally, a degradation empirical model was developed to understand the decrease in the wire strength. This research effort helped to develop a fundamental understanding of the various factors affecting the reliability of a ball bond from a design (low diameter bonding wire), material (low k and bonding wire dopants), and process (wire bonding process parameters) perspective for a first level interconnection technique, namely wire bonding. The significance of this research endeavor was the systematic investigation of the ball bonds formed using 0.8 mil (20 microm) gold bonding wire within the wire bonding arena. This research addressed low k structures on 90 nm silicon technology, bonding wires with different percentage of doping element (palladium), and different levels of bonding process parameters. An empirical model to understand the high temperature effects for bonds formed using the low diameter wire was also developed.

Shrink film patterning by craft cutter: complete plastic chips with high resolution/high-aspect ratio channel.

PubMed

Taylor, Douglas; Dyer, David; Lew, Valerie; Khine, Michelle

2010-09-21

This paper presents a rapid, ultra-low-cost approach to fabricate microfluidic devices using a polyolefin shrink film and a digital craft cutter. The shrinking process (with a 95% reduction in area) results in relatively uniform and consistent microfluidic channels with smooth surfaces, vertical sidewalls, and high aspect ratio channels with lateral resolutions well beyond the tool used to cut them. The thermal bonding of the layers results in strongly bonded devices. Complex microfluidic designs are easily designed on the fly and protein assays are also readily integrated into the device. Full device characterization including channel consistency, optical properties, and bonding strength are assessed in this technical note.

Re-Envisioning the Archaic Higher Education Learning Environment: Implementation Processes for Flipped Classrooms

ERIC Educational Resources Information Center

Rabidoux, Salena; Rottmann, Amy

2018-01-01

Flipped classrooms are often utilized in PK-12 classrooms; however, there is also a growing trend of flipped classrooms in higher education. This paper presents the benefits and limitations of implementing flipped classrooms in higher education as well as resources for integrating a flipped classroom design to instruction. The various technology…

A one-step strategy for ultra-fast and low-cost mass production of plastic membrane microfluidic chips.

PubMed

Hu, Chong; Lin, Sheng; Li, Wanbo; Sun, Han; Chen, Yangfan; Chan, Chiu-Wing; Leung, Chung-Hang; Ma, Dik-Lung; Wu, Hongkai; Ren, Kangning

2016-10-05

An ultra-fast, extremely cost-effective, and environmentally friendly method was developed for fabricating flexible microfluidic chips with plastic membranes. With this method, we could fabricate plastic microfluidic chips rapidly (within 12 seconds per piece) at an extremely low cost (less than $0.02 per piece). We used a heated perfluoropolymer perfluoroalkoxy (often called Teflon PFA) solid stamp to press a pile of two pieces of plastic membranes, low density polyethylene (LDPE) and polyethylene terephthalate (PET) coated with an ethylene-vinyl acetate copolymer (EVA). During the short period of contact with the heated PFA stamp, the pressed area of the membranes permanently bonded, while the LDPE membrane spontaneously rose up at the area not pressed, forming microchannels automatically. These two regions were clearly distinguishable even at the micrometer scale so we were able to fabricate microchannels with widths down to 50 microns. This method combines the two steps in the conventional strategy for microchannel fabrication, generating microchannels and sealing channels, into a single step. The production is a green process without using any solvent or generating any waste. Also, the chips showed good resistance against the absorption of Rhodamine 6G, oligonucleotides, and green fluorescent protein (GFP). We demonstrated some typical microfluidic manipulations with the flexible plastic membrane chips, including droplet formation, on-chip capillary electrophoresis, and peristaltic pumping for quantitative injection of samples and reagents. In addition, we demonstrated convenient on-chip detection of lead ions in water samples by a peristaltic-pumping design, as an example of the application of the plastic membrane chips in a resource-limited environment. Due to the high speed and low cost of the fabrication process, this single-step method will facilitate the mass production of microfluidic chips and commercialization of microfluidic technologies.

Should We Flip the Social Studies Classrooms? The Opinions of Social Studies Teacher Candidates on Flipped Classroom

ERIC Educational Resources Information Center

Erdogan, Erdi; Akbaba, Bulent

2018-01-01

The technology revolution continues to profoundly influence the educational process. Thus, the traditional teaching process is changing and education which is individualized with technology supported teaching processes comes to the forefront. One of the concrete indicators is the flipped classroom model. The purpose of this study is to determine…

Three-Dimensional Waveguide Arrays for Coupling Between Fiber-Optic Connectors and Surface-Mounted Optoelectronic Devices

NASA Astrophysics Data System (ADS)

Hiramatsu, Seiki; Kinoshita, Masao

2005-09-01

This paper describes the fabrication of novel surface-mountable waveguide connectors and presents test results for them. To ensure more highly integrated and low-cost fabrication, we propose new three-dimensional (3-D) waveguide arrays that feature two-dimensionally integrated optical inputs/outputs and optical path redirection. A wafer-level stack and lamination process was used to fabricate the waveguide arrays. Vertical-cavity surface-emitting lasers (VCSELs) and photodiodes were directly mounted on the arrays and combined with mechanical transferable ferrule using active alignment. With the help of a flip-chip bonder, the waveguide connectors were mounted on a printed circuit board by solder bumps. Using mechanical transferable connectors, which can easily plug into the waveguide connectors, we obtained multi-gigabits-per-second transmission performance.

Carbon nanotubes for thermal interface materials in microelectronic packaging

NASA Astrophysics Data System (ADS)

Lin, Wei

As the integration scale of transistors/devices in a chip/system keeps increasing, effective cooling has become more and more important in microelectronics. To address the thermal dissipation issue, one important solution is to develop thermal interface materials with higher performance. Carbon nanotubes, given their high intrinsic thermal and mechanical properties, and their high thermal and chemical stabilities, have received extensive attention from both academia and industry as a candidate for high-performance thermal interface materials. The thesis is devoted to addressing some challenges related to the potential application of carbon nanotubes as thermal interface materials in microelectronics. These challenges include: 1) controlled synthesis of vertically aligned carbon nanotubes on various bulk substrates via chemical vapor deposition and the fundamental understanding involved; 2) development of a scalable annealing process to improve the intrinsic properties of synthesized carbon nanotubes; 3) development of a state-of-art assembling process to effectively implement high-quality vertically aligned carbon nanotubes into a flip-chip assembly; 4) a reliable thermal measurement of intrinsic thermal transport property of vertically aligned carbon nanotube films; 5) improvement of interfacial thermal transport between carbon nanotubes and other materials. The major achievements are summarized. 1. Based on the fundamental understanding of catalytic chemical vapor deposition processes and the growth mechanism of carbon nanotube, fast synthesis of high-quality vertically aligned carbon nanotubes on various bulk substrates (e.g., copper, quartz, silicon, aluminum oxide, etc.) has been successfully achieved. The synthesis of vertically aligned carbon nanotubes on the bulk copper substrate by the thermal chemical vapor deposition process has set a world record. In order to functionalize the synthesized carbon nanotubes while maintaining their good vertical alignment, an in situ functionalization process has for the first time been demonstrated. The in situ functionalization renders the vertically aligned carbon nanotubes a proper chemical reactivity for forming chemical bonding with other substrate materials such as gold and silicon. 2. An ultrafast microwave annealing process has been developed to reduce the defect density in vertically aligned carbon nanotubes. Raman and thermogravimetric analyses have shown a distinct defect reduction in the CNTs annealed in microwave for 3 min. Fibers spun from the as-annealed CNTs, in comparison with those from the pristine CNTs, show increases of ˜35% and ˜65%, respectively, in tensile strength (˜0.8 GPa) and modulus (˜90 GPa) during tensile testing; an ˜20% improvement in electrical conductivity (˜80000 S m-1) was also reported. The mechanism of the microwave response of CNTs was discussed. Such a microwave annealing process has been extended to the preparation of reduced graphene oxide. 3. Based on the fundamental understanding of interfacial thermal transport and surface chemistry of metals and carbon nanotubes, two major transfer/assembling processes have been developed: molecular bonding and metal bonding. Effective improvement of the interfacial thermal transport has been achieved by the interfacial bonding. 4. The thermal diffusivity of vertically aligned carbon nanotube (VACNT, multi-walled) films was measured by a laser flash technique, and shown to be ˜30 mm2 s-1 along the tube-alignment direction. The calculated thermal conductivities of the VACNT film and the individual CNTs are ˜27 and ˜540 W m-1 K-1, respectively. The technique was verified to be reliable although a proper sampling procedure is critical. A systematic parametric study of the effects of defects, buckling, tip-to-tip contacts, packing density, and tube-tube interaction on the thermal diffusivity was carried out. Defects and buckling decreased the thermal diffusivity dramatically. An increased packing density was beneficial in increasing the collective thermal conductivity of the VACNT film; however, the increased tube-tube interaction in dense VACNT films decreased the thermal conductivity of the individual CNTs. The tip-to-tip contact resistance was shown to be ˜1x10-7 m2 K W -1. The study will shed light on the potential application of VACNTs as thermal interface materials in microelectronic packaging. 5. A combined process of in situ functionalization and microwave curing has been developed to effective enhance the interface between carbon nanotubes and the epoxy matrix. Effective medium theory has been used to analyze the interfacial thermal resistance between carbon nanotubes and polymer matrix, and that between graphite nanoplatlets and polymer matrix.

Identification of Bacterial Factors Involved in Type 1 Fimbria Expression using an Escherichia coli K12 Proteome Chip*

PubMed Central

Chen, Yi-Wen; Teng, Ching-Hao; Ho, Yu-Hsuan; Jessica Ho, Tien Yu; Huang, Wen-Chun; Hashimoto, Masayuki; Chiang, I-Yuan; Chen, Chien-Sheng

2014-01-01

Type 1 fimbriae are filamentous structures on Escherichia coli. These structures are important adherence factors. Because binding to the host cells is the first step of infection, type 1 fimbria is an important virulence factor of pathogenic E. coli. Expression of type 1 fimbria is regulated by a phase variation in which each individual bacterium can alternate between fimbriated (phase-ON) and nonfimbriated (phase-OFF) states. The phase variation is regulated by the flipping of the 314-bp fimS fragment, which contains the promoter driving the expression of the genes required for the synthesis of type 1 fimbria. Thus, the bacterial proteins able to interact with fimS are likely to be involved in regulating the expression of type 1 fimbria. To identify novel type 1 fimbria-regulating factors, we used an E. coli K12 proteome chip to screen for the bacterial factors able to interact with a 602-bp DNA fragment containing fimS and its adjacent regions. The Spr protein was identified by the proteome chip-based screening and further confirmed to be able to interact with fimS by electrophoretic mobility shift assay. Deletion of spr in the neonatal meningitis E. coli strain RS218 significantly increased the ratio of the bacterial colonies that contained the type 1 fimbria phase-ON cells on agar plates. In addition, Spr interfered with the interactions of fimS with the site-specific recombinases, FimB and FimE, which are responsible for mediating the flipping of fimS. These results suggest that Spr is involved in the regulation of type 1 fimbria expression through direct interaction with the invertible element fimS. These findings facilitate our understanding of the regulation of type 1 fimbria. PMID:24692643

Flipping the Composing Process: Collaborative Drafting and Résumé Writing

ERIC Educational Resources Information Center

Anders, Abram

2016-01-01

This article argues for a flipped learning approach to business and professional communication composing processes. Flipped learning sequences can scaffold more robust engagement with prewriting activities and support opportunities for in-class collaborative and facilitated drafting exercises. These types of learning experiences offer numerous…

The molecular mechanism of flop-selectivity and subsite recognition for an AMPA receptor allosteric modulator: Structures of GluA2 and GluA3 complexed with PEPA

PubMed Central

Ahmed, Ahmed H.; Ptak, Christopher P.; Oswald, Robert E.

2011-01-01

Glutamate receptors are important potential drug targets for cognitive enhancement and the treatment of schizophrenia in part because they are the most prevalent excitatory neurotransmitter receptors in the vertebrate central nervous system. One approach to the application of therapeutic agents to the AMPA subtype of glutamate receptors is the use of allosteric modulators, which promote dimerization by binding to a dimer interface thereby reducing desensitization and deactivation. AMPA receptors exist in two alternatively spliced variants (flip and flop) that differ in desensitization and receptor activation profiles. Most of the structural information on modulators of the AMPA receptor target the flip subtype. We report here the crystal structure of the flop-selective allosteric modulator, PEPA, bound to the binding domains of the GluA2 and GluA3 flop isoforms of AMPA receptors. Specific hydrogen bonding patterns can explain the preference for the flop isoform. This includes a bidentate hydrogen bonding pattern between PEPA and N754 of the flop isoforms of GluA2 and GluA3 (the corresponding position in the flip isoform is S754). Comparison with other allosteric modulators provides a framework for the development of new allosteric modulators with preferences for either the flip or flop isoforms. In addition to interactions with N/S754, specific interactions of the sulfonamide with conserved residues in the binding site are characteristics of a number of allosteric modulators. These, in combination, with variable interactions with five subsites on the binding surface lead to different stoichiometries, orientations within the binding pockets, and functional outcomes. PMID:20199107

Discrete component bonding and thick film materials study. [of capacitor chips bonded with solders and conductive epoxies

NASA Technical Reports Server (NTRS)

Kinser, D. L.

1976-01-01

The bonding reliability of discrete capacitor chips bonded with solders and conductive epoxies was examined along with the thick film resistor materials consisting of iron oxide phosphate and vanadium oxide phosphates. It was concluded from the bonding reliability studies that none of the wide range of types of solders examined is capable of resisting failure during thermal cycling while the conductive epoxy gives substantially lower failure rates. The thick film resistor studies proved the feasibility of iron oxide phosphate resistor systems although some environmental sensitivity problems remain. One of these resistor compositions has inadvertently proven to be a candidate for thermistor applications because of the excellent control achieved upon the temperature coefficient of resistance. One new and potentially damaging phenomenon observed was the degradation of thick film conductors during the course of thermal cycling.

A strategy for design and fabrication of low cost microchannel for future reproductivity of bio/chemical lab-on-chip application

NASA Astrophysics Data System (ADS)

Humayun, Q.; Hashim, U.; Ruzaidi, C. M.; Noriman, N. Z.

2017-03-01

The fabrication and characterization of sensitive and selective fluids delivery system for the application of nano laboratory on a single chip is a challenging task till to date. This paper is one of the initial attempt to resolve this challenging task by using a simple, cost effective and reproductive technique for pattering a microchannel structures on SU-8 resist. The objective of the research is to design, fabricate and characterize polydimethylsiloxane (PDMS) microchannel. The proposed device mask was designed initially by using AutoCAD software and then the designed was transferred to transparency sheet and to commercial chrome mask for better photo masking process. The standard photolithography process coupled with wet chemical etching process was used for the fabrication of proposed microchannel. This is a low cost fabrication technique for the formation of microchannel structure at resist. The fabrication process start from microchannel formation and then the structure was transformed to PDMS substrate, the microchannel structure was cured from mold and then the cured mold was bonded with the glass substrate by plasma oxidation bonding process. The surface morphology was characterized by high power microscope (HPM) and the structure was characterized by Hawk 3 D surface nanoprofiler. The next part of the research will be focus onto device testing and validation by using real biological samples by the implementation of a simple manual injection technique.

Feasibility study of silicon nitride protection of plastic encapsulated semiconductors

NASA Technical Reports Server (NTRS)

Peters, J. W.; Hall, T. C.; Erickson, J. J.; Gebhart, F. L.

1979-01-01

The application of low temperature silicon nitride protective layers on wire bonded integrated circuits mounted on lead frame assemblies is reported. An evaluation of the mechanical and electrical compatibility of both plasma nitride and photochemical silicon nitride (photonitride) passivations (parallel evaluations) of integrated circuits which were then encapsulated in plastic is described. Photonitride passivation is compatible with all wire bonded lead frame assemblies, with or without initial chip passivation. Plasma nitride passivation of lead frame assemblies is possible only if the chip is passivated before lead frame assembly. The survival rate after the environmental test sequence of devices with a coating of plasma nitride on the chip and a coating of either plasma nitride or photonitride over the assembled device is significantly greater than that of devices assembled with no nitride protective coating over either chip or lead frame.

Dissociative adsorption of CH{sub 3}X (X = Br and Cl) on a silicon(100) surface revisited by density functional theory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Chen-Guang; Lash Miller Chemical Laboratories, Department of Chemistry and Institute of Optical Sciences, University of Toronto, Toronto, Ontario M5S 3H6; Huang, Kai, E-mail: khuang@chem.utoronto.ca, E-mail: wji@ruc.edu.cn

During the dissociative adsorption on a solid surface, the substrate usually participates in a passive manner to accommodate fragments produced upon the cleavage of the internal bond(s) of a (transient) molecular adsorbate. This simple picture, however, neglects the flexibility of surface atoms. Here, we report a Density Functional Theory study to revisit our early studies of the dissociative adsorption of CH{sub 3}X (X = Br and Cl) on Si(100). We have identified a new reaction pathway, which involves a flip of a silicon dimer; this new pathway agrees better with experiments. For our main exemplar of CH{sub 3}Br, insights havemore » been gained using a simple model that involves a three-atom reactive center, Br-C-Si. When the silicon dimer flips, the interaction between C and Si in the Br-C-Si center is enhanced, evident in the increased energy-split of the frontier orbitals. We also examine how the dissociation dynamics of CH{sub 3}Br is altered on a heterodimer (Si-Al, Si-P, and Si-Ge) in a Si(100) surface. In each case, we conclude, on the basis of computed reaction pathways, that no heterodimer flipping is involved before the system transverses the transition state to dissociative adsorption.« less

Thin-Film Quantum Dot Photodiode for Monolithic Infrared Image Sensors.

PubMed

Malinowski, Pawel E; Georgitzikis, Epimitheas; Maes, Jorick; Vamvaka, Ioanna; Frazzica, Fortunato; Van Olmen, Jan; De Moor, Piet; Heremans, Paul; Hens, Zeger; Cheyns, David

2017-12-10

Imaging in the infrared wavelength range has been fundamental in scientific, military and surveillance applications. Currently, it is a crucial enabler of new industries such as autonomous mobility (for obstacle detection), augmented reality (for eye tracking) and biometrics. Ubiquitous deployment of infrared cameras (on a scale similar to visible cameras) is however prevented by high manufacturing cost and low resolution related to the need of using image sensors based on flip-chip hybridization. One way to enable monolithic integration is by replacing expensive, small-scale III-V-based detector chips with narrow bandgap thin-films compatible with 8- and 12-inch full-wafer processing. This work describes a CMOS-compatible pixel stack based on lead sulfide quantum dots (PbS QD) with tunable absorption peak. Photodiode with a 150-nm thick absorber in an inverted architecture shows dark current of 10 -6 A/cm² at -2 V reverse bias and EQE above 20% at 1440 nm wavelength. Optical modeling for top illumination architecture can improve the contact transparency to 70%. Additional cooling (193 K) can improve the sensitivity to 60 dB. This stack can be integrated on a CMOS ROIC, enabling order-of-magnitude cost reduction for infrared sensors.

Test systems of the STS-XYTER2 ASIC: from wafer-level to in-system verification

NASA Astrophysics Data System (ADS)

Kasinski, Krzysztof; Zubrzycka, Weronika

2016-09-01

The STS/MUCH-XYTER2 ASIC is a full-size prototype chip for the Silicon Tracking System (STS) and Muon Chamber (MUCH) detectors in the new fixed-target experiment Compressed Baryonic Matter (CBM) at FAIR-center, Darmstadt, Germany. The STS assembly includes more than 14000 ASICs. The complicated, time-consuming, multi-step assembly process of the detector building blocks and tight quality assurance requirements impose several intermediate testing to be performed for verifying crucial assembly steps (e.g. custom microcable tab-bonding before wire-bonding to the PCB) and - if necessary - identifying channels or modules for rework. The chip supports the multi-level testing with different probing / contact methods (wafer probe-card, pogo-probes, in-system tests). A huge number of ASICs to be tested restricts the number and kind of tests possible to be performed within a reasonable time. The proposed architectures of test stand equipment and a brief summary of methodologies are presented in this paper.

Enabling Large Focal Plane Arrays Through Mosaic Hybridization

NASA Technical Reports Server (NTRS)

Miller, TImothy M.; Jhabvala, Christine A.; Leong, Edward; Costen, Nicholas P.; Sharp, Elmer; Adachi, Tomoko; Benford, Dominic

2012-01-01

We have demonstrated advances in mosaic hybridization that will enable very large format far-infrared detectors. Specifically we have produced electrical detector models via mosaic hybridization yielding superconducting circuit paths by hybridizing separately fabricated sub-units onto a single detector unit. The detector model was made on a 100mm diameter wafer while four model readout quadrant chips were made from a separate 100mm wafer. The individually fabricated parts were hybridized using a flip-chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the model mosaic-hybrid detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently available.

Enabling Large Focal Plane Arrays through Mosaic Hybridization

NASA Technical Reports Server (NTRS)

Miller, Timothy M.; Jhabvala, Christine A.; Costen, Nick; Benford, Dominic J.

2012-01-01

We have demonstrated the hybridization of large mosaics of far-infrared detectors, joining separately fabricated sub-units into a single unit on a single, large substrate. We produced a single detector mockup on a 100mm diameter wafer and four mockup readout quadrant chips from a separate 100mm wafer. The individually fabricated parts were hybridized using a Suss FC150 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion (CTE) match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the mockup mosaic-hybridized detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently demonstrated.

Development of non-destructive evaluation system using an HTS-SQUID gradiometer for magnetized materials

NASA Astrophysics Data System (ADS)

Kawano, J.; Tsukamoto, A.; Adachi, S.; Oshikubo, Y.; Hato, T.; Tanabe, K.; Okamura, T.

We have developed a new eddy-current non-destructive evaluation (NDE) system using an HTS SQUID gradiometer with the aim of applying it to practical materials with magnetization. The new NDE system employs a LN2-cooled external Cu pickup coil and an HTS SQUID chip placed in a magnetic shield made of HTS material. The HTS SQUID chip consists of an HTS planar gradiometer manufactured by using a ramp-edge junction technology and a multi-turn HTS thin film input coil coupled with the flip-chip configuration. The first-order coaxial gradiometric Cu pickup coil with a diameter of 16 mm and the baseline of 5.6 mm was used in the present NDE experiments. By using this NDE system, we could observe defect-induced magnetic signals without an appreciable influence of magnetization up to 10 mT. We also examined the ability of detecting deep-lying defects and compared with the results obtained using our previous NDE system.

A Microsystem Based on Porous Silicon-Glass Anodic Bonding for Gas and Liquid Optical Sensing

PubMed Central

De Stefano, Luca; Malecki, Krzysztof; Della Corte, Francesco G.; Moretti, Luigi; Rea, Ilaria; Rotiroti, Lucia; Rendina, Ivo

2006-01-01

We have recently presented an integrated silicon-glass opto-chemical sensor for lab-on-chip applications, based on porous silicon and anodic bonding technologies. In this work, we have optically characterized the sensor response on exposure to vapors of several organic compounds by means of reflectivity measurements. The interaction between the porous silicon, which acts as transducer layer, and the organic vapors fluxed into the glass sealed microchamber, is preserved by the fabrication process, resulting in optical path increase, due to the capillary condensation of the vapors into the pores. Using the Bruggemann theory, we have calculated the filled pores volume for each substance. The sensor dynamic has been described by time-resolved measurements: due to the analysis chamber miniaturization, the response time is only of 2 s. All these results have been compared with data acquired on the same PSi structure before the anodic bonding process.

Phase Equilibria of the Sn-Ni-Si Ternary System and Interfacial Reactions in Sn-(Cu)/Ni-Si Couples

NASA Astrophysics Data System (ADS)

Fang, Gu; Chen, Chih-chi

2015-07-01

Interfacial reactions in Sn/Ni-4.5 wt.%Si and Sn-Cu/Ni-4.5 wt.%Si couples at 250°C, and Sn-Ni-Si ternary phase equilibria at 250°C were investigated in this study. Ni-Si alloys, which are nonmagnetic, can be regarded as a diffusion barrier layer material in flip chip packaging. Solder/Ni-4.5 wt.%Si interfacial reactions are crucial to the reliability of soldered joints. Phase equilibria information is essential for development of solder/Ni-Si materials. No ternary compound is present in the Sn-Ni-Si ternary system at 250°C. Extended solubility of Si in the phases Ni3Sn2 and Ni3Sn is 3.8 and 6.1 at.%, respectively. As more Si dissolves in these phases their lattice constants decrease. No noticeable ternary solubility is observed for the other intermetallics. Interfacial reactions in solder/Ni-4.5 wt.%Si are similar to those for solder/Ni. Si does not alter the reaction phases. No Si solubility in the reaction phases was detected, although rates of growth of the reaction phases were reduced. Because the alloy Ni-4.5 wt.%Si reacts more slowly with solders than pure Ni, the Ni-4.5 wt.%Si alloy could be a potential new diffusion barrier layer material for flip chip packaging.

Structural Basis for Flip-Flop Action of Thiamin Pyrophosphate-Dependent Enzymes Revealed by Human Pyruvate Dehydrogenase

NASA Technical Reports Server (NTRS)

Dominiak, Paulina; Ciszak, Ewa M.; Korotchkina, Lioubov; Sidhu, Sukhdeep; Patel, Mulchand

2003-01-01

Thiamin pyrophosphate (TPP), the biologically active form of vitamin BI, is a cofactor of enzymes catalyzing reactions involving the cleavage of a carbon-carbon bond adjacent to an oxo group. TPP-dependent enzymes show a common mechanism of TPP activation by: (1) forming the ionic N-H...O(sup -) hydrogen bonding between the N1' atom of the aminopirymidine ring of the coenzyme and intrinsic gamma-carboxylate group of glutamate and (2) imposing an "active" V-conformation that brings the N4' atom of the aminopirymidine to the distance required for the intramolecular C-H.. .N hydrogen bonding with the thiazolium C2 atom. Within these two hydrogen bonds that rapidly exchange protons, protonation of the N1' atom is strictly coordinated with the deprotonation of the 4' -amino group and eventually abstraction of the proton from C2. The human pyruvate dehydrogenase Elp, component of human pyruvate dehydrogenase complex, catalyzes the irreversible decarboxylation of the pyruvate followed by the reductive acetylation of the lipoyl group of dihydrolipoyl acyltransferase. Elp is alpha(sub 2)beta(sub2)-heterotetrameric with a molecular mass of I54 kDa, which has two catalytic sites, each providing TPP and magnesium ion as cofactors and each formed on the interface between the PP and PYR domains. The dynamic nonequivalence of two otherwise chemically equivalent catalytic sites has been observed and the flip-flop mechanism was suggested, according to which two active sites affect each other and in which different steps of the catalytic reaction are performed in each of the sites at any given moment. Based on specific futures of human pyruvate dehydrogenase including rigid and flexible connections between domains that bind the cofactor we propose a mechanistic model for the flip-flop action of this enzyme. We postulate that the dynamic protein environment drives the exchange of tautomers in the 4' -aminopyrimidine ring of the cofactor through a concerted shuttl-like motion of tightly connected domains. The dynamic exchange of those tautomers, in turns, is required during the reactions of pyruvate decarboxylation and reductive acetylation of lipoamide. Thus the shuttle-like motion of the domains is coordinated with the reactions of decarboxylation and acetylation, which are carried out in each of the cofactor sites resulting in a flip-flop action of the enzyme. The structure-derived mechanism of action of human pyruvate dehydrogenase may be likely common for other TPP-dependent enzymes.

Significance of wood extractives for wood bonding.

PubMed

Roffael, Edmone

2016-02-01

Wood contains primary extractives, which are present in all woods, and secondary extractives, which are confined in certain wood species. Extractives in wood play a major role in wood-bonding processes, as they can contribute to or determine the bonding relevant properties of wood such as acidity and wettability. Therefore, extractives play an immanent role in bonding of wood chips and wood fibres with common synthetic adhesives such as urea-formaldehyde-resins (UF-resins) and phenol-formaldehyde-resins (PF-resins). Extractives of high acidity accelerate the curing of acid curing UF-resins and decelerate bonding with alkaline hardening PF-resins. Water-soluble extractives like free sugars are detrimental for bonding of wood with cement. Polyphenolic extractives (tannins) can be used as a binder in the wood-based industry. Additionally, extractives in wood can react with formaldehyde and reduce the formaldehyde emission of wood-based panels. Moreover, some wood extractives are volatile organic compounds (VOC) and insofar also relevant to the emission of VOC from wood and wood-based panels.

Pressure activated diaphragm bonder

DOEpatents

Evans, L.B.; Malba, V.

1997-05-27

A device is available for bonding one component to another, particularly for bonding electronic components of integrated circuits, such as chips, to a substrate. The bonder device in one embodiment includes a bottom metal block having a machined opening wherein a substrate is located, a template having machined openings which match solder patterns on the substrate, a thin diaphragm placed over the template after the chips have been positioned in the openings therein, and a top metal block positioned over the diaphragm and secured to the bottom block, with the diaphragm retained therebetween. The top block includes a countersink portion which extends over at least the area of the template and an opening through which a high pressure inert gas is supplied to exert uniform pressure distribution over the diaphragm to keep the chips in place during soldering. A heating means is provided to melt the solder patterns on the substrate and thereby solder the chips thereto. 4 figs.

Pressure activated diaphragm bonder

DOEpatents

Evans, Leland B.; Malba, Vincent

1997-01-01

A device is available for bonding one component to another, particularly for bonding electronic components of integrated circuits, such as chips, to a substrate. The bonder device in one embodiment includes a bottom metal block having a machined opening wherein a substrate is located, a template having machined openings which match solder patterns on the substrate, a thin diaphragm placed over the template after the chips have been positioned in the openings therein, and a top metal block positioned over the diaphragm and secured to the bottom block, with the diaphragm retained therebetween. The top block includes a countersink portion which extends over at least the area of the template and an opening through which a high pressure inert gas is supplied to exert uniform pressure distribution over the diaphragm to keep the chips in place during soldering. A heating means is provided to melt the solder patterns on the substrate and thereby solder the chips thereto.

Creating Sub-50 Nm Nanofluidic Junctions in PDMS Microfluidic Chip via Self-Assembly Process of Colloidal Particles

PubMed Central

Wei, Xi; Syed, Abeer; Mao, Pan; Han, Jongyoon; Song, Yong-Ak

2016-01-01

Polydimethylsiloxane (PDMS) is the prevailing building material to make microfluidic devices due to its ease of molding and bonding as well as its transparency. Due to the softness of the PDMS material, however, it is challenging to use PDMS for building nanochannels. The channels tend to collapse easily during plasma bonding. In this paper, we present an evaporation-driven self-assembly method of silica colloidal nanoparticles to create nanofluidic junctions with sub-50 nm pores between two microchannels. The pore size as well as the surface charge of the nanofluidic junction is tunable simply by changing the colloidal silica bead size and surface functionalization outside of the assembled microfluidic device in a vial before the self-assembly process. Using the self-assembly of nanoparticles with a bead size of 300 nm, 500 nm, and 900 nm, it was possible to fabricate a porous membrane with a pore size of ~45 nm, ~75 nm and ~135 nm, respectively. Under electrical potential, this nanoporous membrane initiated ion concentration polarization (ICP) acting as a cation-selective membrane to concentrate DNA by ~1,700 times within 15 min. This non-lithographic nanofabrication process opens up a new opportunity to build a tunable nanofluidic junction for the study of nanoscale transport processes of ions and molecules inside a PDMS microfluidic chip. PMID:27023724

Packaged integrated opto-fluidic solution for harmful fluid analysis

NASA Astrophysics Data System (ADS)

Allenet, T.; Bucci, D.; Geoffray, F.; Canto, F.; Couston, L.; Jardinier, E.; Broquin, J.-E.

2016-02-01

Advances in nuclear fuel reprocessing have led to a surging need for novel chemical analysis tools. In this paper, we present a packaged lab-on-chip approach with co-integration of optical and micro-fluidic functions on a glass substrate as a solution. A chip was built and packaged to obtain light/fluid interaction in order for the entire device to make spectral measurements using the photo spectroscopy absorption principle. The interaction between the analyte solution and light takes place at the boundary between a waveguide and a fluid micro-channel thanks to the evanescent part of the waveguide's guided mode that propagates into the fluid. The waveguide was obtained via ion exchange on a glass wafer. The input and the output of the waveguides were pigtailed with standard single mode optical fibers. The micro-scale fluid channel was elaborated with a lithography procedure and hydrofluoric acid wet etching resulting in a 150+/-8 μm deep channel. The channel was designed with fluidic accesses, in order for the chip to be compatible with commercial fluidic interfaces/chip mounts. This allows for analyte fluid in external capillaries to be pumped into the device through micro-pipes, hence resulting in a fully packaged chip. In order to produce this co-integrated structure, two substrates were bonded. A study of direct glass wafer-to-wafer molecular bonding was carried-out to improve detector sturdiness and durability and put forward a bonding protocol with a bonding surface energy of γ>2.0 J.m-2. Detector viability was shown by obtaining optical mode measurements and detecting traces of 1.2 M neodymium (Nd) solute in 12+/-1 μL of 0.01 M and pH 2 nitric acid (HNO3) solvent by obtaining an absorption peak specific to neodymium at 795 nm.

Prototype of a gigabit data transmitter in 65 nm CMOS for DEPFET pixel detectors at Belle-II

NASA Astrophysics Data System (ADS)

Kishishita, T.; Krüger, H.; Hemperek, T.; Lemarenko, M.; Koch, M.; Gronewald, M.; Wermes, N.

2013-08-01

This paper describes the recent development of a gigabit data transmitter for the Belle-II pixel detector (PXD). The PXD is an innermost detector currently under development for the upgraded KEK-B factory in Japan. The PXD consists of two layers of DEPFET sensor modules located at 1.8 and 2.2 cm radii. Each module is equipped with three different ASIC types mounted on the detector substrate with a flip-chip technique: (a) SWITCHER for generating steering signals for the DEPFET sensors, (b) DCD for digitizing the signal currents, and (c) DHP for performing data processing and sending the data off the module to the back-end data handling hybrid via ∼ 40 cm Kapton flex and 12-15 m twisted pair (TWP) cables. To meet the requirements of the PXD data transmission, a prototype of the DHP data transmitter has been developed in a 65-nm standard CMOS technology. The transmitter test chip consists of current-mode logic (CML) drivers and a phase-locked loop (PLL) which generates a clock signal for a 1.6 Gbit/s output data stream from an 80 cm reference clock. A programmable pre-emphasis circuit is also implemented in the CML driver to compensate signal losses in the long cable by shaping the transmitted pulse response. The jitter performance was measured as 25 ps (1 σ distribution) by connecting the chip with 38 cm flex and 10 m TWP cables.

Molecular mechanism for lipid flip-flops.

PubMed

Gurtovenko, Andrey A; Vattulainen, Ilpo

2007-12-06

Transmembrane lipid translocation (flip-flop) processes are involved in a variety of properties and functions of cell membranes, such as membrane asymmetry and programmed cell death. Yet, flip-flops are one of the least understood dynamical processes in membranes. In this work, we elucidate the molecular mechanism of pore-mediated transmembrane lipid translocation (flip-flop) acquired from extensive atomistic molecular dynamics simulations. On the basis of 50 successful flip-flop events resolved in atomic detail, we demonstrate that lipid flip-flops may spontaneously occur in protein-free phospholipid membranes under physiological conditions through transient water pores on a time scale of tens of nanoseconds. While the formation of a water pore is induced here by a transmembrane ion density gradient, the particular way by which the pore is formed is irrelevant for the reported flip-flop mechanism: the appearance of a transient pore (defect) in the membrane inevitably leads to diffusive translocation of lipids through the pore, which is driven by thermal fluctuations. Our findings strongly support the idea that the formation of membrane defects in terms of water pores is the rate-limiting step in the process of transmembrane lipid flip-flop, which, on average, requires several hours. The findings are consistent with available experimental and computational data and provide a view to interpret experimental observations. For example, the simulation results provide a molecular-level explanation in terms of pores for the experimentally observed fact that the exposure of lipid membranes to electric field pulses considerably reduces the time required for lipid flip-flops.

Triggering of spin-flipping-modulated exchange bias in FeCo nanoparticles by electronic excitation

PubMed Central

Sarker, Debalaya; Bhattacharya, Saswata; Srivastava, Pankaj; Ghosh, Santanu

2016-01-01

The exchange coupling between ferromagnetic (FM)-antiferromagnetic (AF) interfaces is a key element of modern spintronic devices. We here introduce a new way of triggering exchange bias (EB) in swift heavy ion (SHI) irradiated FeCo-SiO2 films, which is a manifestation of spin-flipping at high irradiation fluence. The elongation of FeCo nanoparticles (NPs) in SiO2 matrix gives rise to perpendicular magnetic anisotropy at intermediate fluence. However, a clear shift in hysteresis loop is evident at the highest fluence. This reveals the existence of an AF exchange pinning domain in the NPs, which is identified not to be oxide shell from XANES analysis. Thermal spike calculations along with first-principles based simulations under the framework of density functional theory (DFT) demonstrate that spin flipping of 3d valence electrons is responsible for formation of these AF domains inside the FM NPs. EXAFS experiments at Fe and Co K-edges further unravel that spin-flipping in highest fluence irradiated film results in reduced bond lengths. The results highlight the possibility of miniaturization of magnetic storage devices by using irradiated NPs instead of conventionally used FM-AF multilayers. PMID:27991552

Intramolecular hydrogen bonds: ab initio Car Parrinello simulations of arylamide torsions

NASA Astrophysics Data System (ADS)

Doerksen, Robert J.; Chen, Bin; Klein, Michael L.

2003-10-01

Gas-phase, room temperature Car-Parrinello molecular dynamics simulations using the HCTH density functional are reported for the arylamides acetanilide ( 1) and ortho-methylthioacetanilide ( 2). The simulations show that in 1, rotation around the ring-amide bond is relatively unrestricted. By contrast, in 2 the methylthio side chain encourages the amide to be directed with N-H pointing toward S, not to flip by 360°, and furthermore to remain close to coplanar with the benzene ring. Because of an intramolecular N-H⋯S hydrogen bond, the N-H stretch frequency of 2 is red-shifted by ˜78 cm -1 compared to that of 1.

27 CFR 19.318 - Addition of caramel to rum or brandy and addition of oak chips to spirits.

Code of Federal Regulations, 2010 CFR

2010-04-01

... or brandy and addition of oak chips to spirits. 19.318 Section 19.318 Alcohol, Tobacco Products and... PLANTS Production § 19.318 Addition of caramel to rum or brandy and addition of oak chips to spirits. Caramel possessing no material sweetening properties may be added to rum or brandy on bonded premises...

Multilayer based lab-on-a-chip-systems for substance testing

NASA Astrophysics Data System (ADS)

Sonntag, Frank; Grünzner, Stefan; Schmieder, Florian; Busek, Mathias; Klotzbach, Udo; Franke, Volker

2015-03-01

An integrated technology chain for laser-microstructuring and bonding of polymer foils for fast, flexible and low-cost manufacturing of multilayer lab-on-a-chip devices especially for complex cell and tissue culture applications, which provides pulsatile fluid flow within physiological ranges at low media-to-cells ratio, was developed and established. Initially the microfluidic system is constructively divided into individual layers which are formed by separate foils or plates. Based on the functional boundary conditions and the necessary properties of each layer the corresponding foils and plates are chosen. In the third step the foils and plates are laser microstructured and functionalized from both sides. In the fourth and last manufacturing step the multiple plates and foils are joined using thermal diffusion bonding. Membranes for pneumatically driven valves and micropumps where bonded via chemical surface modification. Based on the established lab-on-a-chip platform for perfused cell-based assays, a multilayer microfluidic system with two parallel connected cell culture chambers was successfully implemented.

Fabrication of Cantilever-Bump Type Si Probe Card

NASA Astrophysics Data System (ADS)

Park, Jeong-Yong; Lee, Dong-Seok; Kim, Dong-Kwon; Lee, Jong-Hyun

2000-12-01

Probe card is most important part in the test system which selects the good or bad chip of integrated circuit (IC) chips. Silicon vertical probe card is able to test multiple semiconductor chips simultaneously. We presented cantilever-bump type vertical probe card. It was fabricated by dry etching using RIE(reactive ion etching) technique and porous silicon micromachining using silicon direct bonded (SDB) wafer. Cantilevers and bumps were fabricated by isotropic etching using RIE@. 3-dimensional structures were formed by porous silicon micromachining technique using SDB wafer. Contact resistance of fabricated probe card was less than 2 Ω and its life time was more than 200,000 turns. The process used in this work is very simple and reproducible, which has good controllability in the tip dimension and spacing. It is expected that the fabricated probe card can reduce testing time, can promote productivity and enables burn-in test.

A monolithic glass chip for active single-cell sorting based on mechanical phenotyping.

PubMed

Faigle, Christoph; Lautenschläger, Franziska; Whyte, Graeme; Homewood, Philip; Martín-Badosa, Estela; Guck, Jochen

2015-03-07

The mechanical properties of biological cells have long been considered as inherent markers of biological function and disease. However, the screening and active sorting of heterogeneous populations based on serial single-cell mechanical measurements has not been demonstrated. Here we present a novel monolithic glass chip for combined fluorescence detection and mechanical phenotyping using an optical stretcher. A new design and manufacturing process, involving the bonding of two asymmetrically etched glass plates, combines exact optical fiber alignment, low laser damage threshold and high imaging quality with the possibility of several microfluidic inlet and outlet channels. We show the utility of such a custom-built optical stretcher glass chip by measuring and sorting single cells in a heterogeneous population based on their different mechanical properties and verify sorting accuracy by simultaneous fluorescence detection. This offers new possibilities of exact characterization and sorting of small populations based on rheological properties for biological and biomedical applications.

Contamination control in hybrid microelectronic modules. Part 2: Selection and evaluation of coating materials

NASA Technical Reports Server (NTRS)

Himmel, R. P.

1975-01-01

The selection, test, and evaluation of organic coating materials for contamination control in hybrid circuits is reported. The coatings were evaluated to determine their suitability for use as a conformal coating over the hybrid microcircuit (including chips and wire bonds) inside a hermetically sealed package. Evaluations included ease of coating application and repair and effect on thin film and thick film resistors, beam leads, wire bonds, transistor chips, and capacitor chips. The coatings were also tested for such properties as insulation resistance, voltage breakdown strength, and capability of immobilizing loose particles inside the packages. The selected coatings were found to be electrically, mechanically, and chemically compatible with all components and materials normally used in hybrid microcircuits.

Improvement of modulation bandwidth in electroabsorption-modulated laser by utilizing the resonance property in bonding wire.

PubMed

Kwon, Oh Kee; Han, Young Tak; Baek, Yong Soon; Chung, Yun C

2012-05-21

We present and demonstrate a simple and cost-effective technique for improving the modulation bandwidth of electroabsorption-modulated laser (EML). This technique utilizes the RF resonance caused by the EML chip (i.e., junction capacitance) and bonding wire (i.e, wire inductance). We analyze the effects of the lengths of the bonding wires on the frequency responses of EML by using an equivalent circuit model. To verify this analysis, we package a lumped EML chip on the sub-mount and measure its frequency responses. The results show that, by using the proposed technique, we can increase the modulation bandwidth of EML from ~16 GHz to ~28 GHz.

Hot embossing and thermal bonding of poly(methyl methacrylate) microfluidic chips using positive temperature coefficient ceramic heater.

PubMed

Wang, Xia; Zhang, Luyan; Chen, Gang

2011-11-01

As a self-regulating heating device, positive temperature coefficient ceramic heater was employed for hot embossing and thermal bonding of poly(methyl methacrylate) microfluidic chip because it supplied constant-temperature heating without electrical control circuits. To emboss a channel plate, a piece of poly(methyl methacrylate) plate was sandwiched between a template and a microscopic glass slide on a positive temperature coefficient ceramic heater. All the assembled components were pressed between two elastic press heads of a spring-driven press while a voltage was applied to the heater for 10 min. Subsequently, the embossed poly(methyl methacrylate) plate bearing negative relief of channel networks was bonded with a piece of poly(methyl methacrylate) cover sheet to obtain a complete microchip using a positive temperature coefficient ceramic heater and a spring-driven press. High quality microfluidic chips fabricated by using the novel embossing/bonding device were successfully applied in the electrophoretic separation of three cations. Positive temperature coefficient ceramic heater indicates great promise for the low-cost production of poly(methyl methacrylate) microchips and should find wide applications in the fabrication of other thermoplastic polymer microfluidic devices.

Development and Applications of Advanced Electronic Structure Methods

NASA Astrophysics Data System (ADS)

Bell, Franziska

This dissertation contributes to three different areas in electronic structure theory. The first part of this thesis advances the fundamentals of orbital active spaces. Orbital active spaces are not only essential in multi-reference approaches, but have also become of interest in single-reference methods as they allow otherwise intractably large systems to be studied. However, despite their great importance, the optimal choice and, more importantly, their physical significance are still not fully understood. In order to address this problem, we studied the higher-order singular value decomposition (HOSVD) in the context of electronic structure methods. We were able to gain a physical understanding of the resulting orbitals and proved a connection to unrelaxed natural orbitals in the case of Moller-Plesset perturbation theory to second order (MP2). In the quest to find the optimal choice of the active space, we proposed a HOSVD for energy-weighted integrals, which yielded the fastest convergence in MP2 correlation energy for small- to medium-sized active spaces to date, and is also potentially transferable to coupled-cluster theory. In the second part, we studied monomeric and dimeric glycerol radical cations and their photo-induced dissociation in collaboration with Prof. Leone and his group. Understanding the mechanistic details involved in these processes are essential for further studies on the combustion of glycerol and carbohydrates. To our surprise, we found that in most cases, the experimentally observed appearance energies arise from the separation of product fragments from one another rather than rearrangement to products. The final chapters of this work focus on the development, assessment, and application of the spin-flip method, which is a single-reference approach, but capable of describing multi-reference problems. Systems exhibiting multi-reference character, which arises from the (near-) degeneracy of orbital energies, are amongst the most interesting in chemistry, biology and materials science, yet amongst the most challenging to study with electronic structure methods. In particular, we explored a substituted dimeric BPBP molecule with potential tetraradical character, which gained attention as one of the most promising candidates for an organic conductor. Furthermore, we extended the spin-flip approach to include variable orbital active spaces and multiple spin-flips. This allowed us to perform wave-function-based studies of ground- and excited-states of polynuclear metal complexes, polyradicals, and bond-dissociation processes involving three or more bonds.

Edge chipping and flexural resistance of monolithic ceramics☆

PubMed Central

Zhang, Yu; Lee, James J.-W.; Srikanth, Ramanathan; Lawn, Brian R.

2014-01-01

Objective Test the hypothesis that monolithic ceramics can be developed with combined esthetics and superior fracture resistance to circumvent processing and performance drawbacks of traditional all-ceramic crowns and fixed-dental-prostheses consisting of a hard and strong core with an esthetic porcelain veneer. Specifically, to demonstrate that monolithic prostheses can be produced with a much reduced susceptibility to fracture. Methods Protocols were applied for quantifying resistance to chipping as well as resistance to flexural failure in two classes of dental ceramic, microstructurally-modified zirconias and lithium disilicate glass–ceramics. A sharp indenter was used to induce chips near the edges of flat-layer specimens, and the results compared with predictions from a critical load equation. The critical loads required to produce cementation surface failure in monolithic specimens bonded to dentin were computed from established flexural strength relations and the predictions validated with experimental data. Results Monolithic zirconias have superior chipping and flexural fracture resistance relative to their veneered counterparts. While they have superior esthetics, glass–ceramics exhibit lower strength but higher chip fracture resistance relative to porcelain-veneered zirconias. Significance The study suggests a promising future for new and improved monolithic ceramic restorations, with combined durability and acceptable esthetics. PMID:24139756

Conformational state of β-hydroxynaphthylamides: Barriers for the rotation of the amide group around CN bond and dynamics of the morpholine ring

NASA Astrophysics Data System (ADS)

Kozlecki, Tomasz; Tolstoy, Peter M.; Kwocz, Agnieszka; Vovk, Mikhail A.; Kochel, Andrzej; Polowczyk, Izabela; Tretyakov, Peter Yu.; Filarowski, Aleksander

2015-10-01

Three β-hydroxynaphthylamides (morpholine, pyrrolidine and dimethylamine derivatives) have been synthesized and their conformational state was analyzed by NMR, X-ray and DFT calculations. In aprotic solution the molecules contain intramolecular OHO hydrogen bonds, which change into intermolecular ones in solid state. The energy barriers for the amide group rotation around the CN bond were estimated from the line shape analysis of 1H and 13C NMR signals. A tentative correlation between the barrier height and the strength of OHO bond was proposed. Calculations of the potential energy profiles for the rotations around CC and CN bonds were done. In case of morpholine derivative experimental indications of additional dynamics: chair-chair 'ring flip' in combination with the twisting around CC bond were obtained and confirmed by quantum chemistry calculations.

Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip

NASA Technical Reports Server (NTRS)

Carson, John C. (Inventor); Indin, Ronald J. (Inventor); Shanken, Stuart N. (Inventor)

1994-01-01

A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.

Sparsely-Bonded CMOS Hybrid Imager

NASA Technical Reports Server (NTRS)

Sun, Chao (Inventor); Jones, Todd J. (Inventor); Nikzad, Shouleh (Inventor); Newton, Kenneth W. (Inventor); Cunningham, Thomas J. (Inventor); Hancock, Bruce R. (Inventor); Dickie, Matthew R. (Inventor); Hoenk, Michael E. (Inventor); Wrigley, Christopher J. (Inventor); Pain, Bedabrata (Inventor)

2015-01-01

A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.

Modular integration of electronics and microfluidic systems using flexible printed circuit boards.

PubMed

Wu, Amy; Wang, Lisen; Jensen, Erik; Mathies, Richard; Boser, Bernhard

2010-02-21

Microfluidic systems offer an attractive alternative to conventional wet chemical methods with benefits including reduced sample and reagent volumes, shorter reaction times, high-throughput, automation, and low cost. However, most present microfluidic systems rely on external means to analyze reaction products. This substantially adds to the size, complexity, and cost of the overall system. Electronic detection based on sub-millimetre size integrated circuits (ICs) has been demonstrated for a wide range of targets including nucleic and amino acids, but deployment of this technology to date has been limited due to the lack of a flexible process to integrate these chips within microfluidic devices. This paper presents a modular and inexpensive process to integrate ICs with microfluidic systems based on standard printed circuit board (PCB) technology to assemble the independently designed microfluidic and electronic components. The integrated system can accommodate multiple chips of different sizes bonded to glass or PDMS microfluidic systems. Since IC chips and flex PCB manufacturing and assembly are industry standards with low cost, the integrated system is economical for both laboratory and point-of-care settings.

Structural Model for the Flip-Flop Action in Thiamin Pyrophosphate-Dependent Human Pyruvate Dehydrogenase

NASA Technical Reports Server (NTRS)

Ciszak, Ewa; Dominiak, Paulina

2003-01-01

The derivative of vitamin B1 thiamin pyrophosphate (TPP) is a cofactor of enzymes performing catalysis in pathways of energy production, including (i) decarboxylation of alpha-keto acids followed by (ii) transketolation. These enzymes have shown a common mechanism of TPP activation by imposing an active V-conformation of this coenzyme that brings the N4 atom of the aminopyrimidine ring to the distance required for the intramolecular C-H N hydrogen-bonding with the C2- atom of the thiazolium ring. The reactive C2 atom of TPP is the nucleophile that attacks the carbonyl carbon of different substrates used by the TPP-dependent enzymes. The structure of the heterotetrameric human pyruvate dehydrogenase (Elp) recently determined in our laboratory (1) revealed the association pattern of the subunits and the specifics of two chemically equivalent cofactor binding sites. Dynamic nonequivalence of these two cofactor sites directs the flip-flop action of this enzyme, depending upon which two active sites effect each other (2). The crystal structure derived from the holo-form of Elp provided the basis for the model of the flip-flop action of Elp in which different steps of the catalytic reaction are performed in each of the two cofactor sites at any given moment, where these steps are governed by the concerted shuttle-like motion of the subunits. It is further proposed that balancing a hydrogen-bond network and related cofactor geometry determine the continuity of catalytic events.

Study of the docking of competitive inhibitors at a model of tyrosinase active site: insights from joint broken-symmetry/Spin-Flip DFT computations and ELF topological analysis

PubMed Central

de la Lande, A.; Maddaluno, J.; Parisel, O.; Darden, T. A.; Piquemal, J-P

2010-01-01

Following our previous study (Piquemal et al., New J. Chem., 2003, 27, 909), we present here a DFT study of the inhibition of the Tyrosinase enzyme. Broken-symmetry DFT computations are supplemented with Spin-Flip TD-DFT calculations, which, for the first time, are applied to such a dicopper enzyme. The chosen biomimetic model encompasses a dioxygen molecule, two Cu(II) cations, and six imidazole rings. The docking energy of a natural substrate, namely phenolate, together with those of several inhibitor and non-inhibitor compounds, are reported and show the ability of the model to rank the most potent inhibitors in agreement with experimental data. With respect to broken-symmetry calculations, the Spin-Flip TD-DFT approach reinforces the possibility for theory to point out potent inhibitors: the need for the deprotonation of the substrates, natural or inhibitors, is now clearly established. Moreover, Electron Localization Function (ELF) topological analysis computations are used to deeply track the particular electronic distribution of the Cu-O-Cu three-center bonds involved in the enzymatic Cu2O2 metallic core (Piquemal and Pilmé, J. Mol. Struct.: Theochem, 2006, 77, 764). It is shown that such bonds exhibit very resilient out-of-plane density expansions that play a key role in docking interactions: their 3D-orientation could be the topological electronic signature of oxygen activation within such systems. PMID:20396590

Submillimeter-Wave Amplifier Module with Integrated Waveguide Transitions

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Chattopadhyay, Goutam; Pukala, David; Gaier, Todd; Soria, Mary; ManFung, King; Deal, William; Mei, Gerry; Radisic, Vesna; Lai, Richard

2009-01-01

To increase the usefulness of monolithic millimeter-wave integrated circuit (MMIC) components at submillimeter-wave frequencies, a chip has been designed that incorporates two integrated, radial E-plane probes with an MMIC amplifier in between, thus creating a fully integrated waveguide module. The integrated amplifier chip has been fabricated in 35-nm gate length InP high-electron-mobility-transistor (HEMT) technology. The radial probes were mated to grounded coplanar waveguide input and output lines in the internal amplifier. The total length of the internal HEMT amplifier is 550 m, while the total integrated chip length is 1,085 m. The chip thickness is 50 m with the chip width being 320 m. The internal MMIC amplifier is biased through wire-bond connections to the gates and drains of the chip. The chip has 3 stages, employing 35-nm gate length transistors in each stage. Wire bonds from the DC drain and gate pads are connected to off-chip shunt 51-pF capacitors, and additional off-chip capacitors and resistors are added to the gate and drain bias lines for low-frequency stability of the amplifier. Additionally, bond wires to the grounded coplanar waveguide pads at the RF input and output of the internal amplifier are added to ensure good ground connections to the waveguide package. The S-parameters of the module, not corrected for input or output waveguide loss, are measured at the waveguide flange edges. The amplifier module has over 10 dB of gain from 290 to 330 GHz, with a peak gain of over 14 dB at 307 GHz. The WR2.2 waveguide cutoff is again observed at 268 GHz. The module is biased at a drain current of 27 mA, a drain voltage of 1.24 V, and a gate voltage of +0.21 V. Return loss of the module is very good between 5 to 25 dB. This result illustrates the usefulness of the integrated radial probe transition, and the wide (over 10-percent) bandwidth that one can expect for amplifier modules with integrated radial probes in the submillimeter-regime (>300 GHz).

A PDMS membrane microvalve with one-dimensional line valve seat for robust microfluidics

NASA Astrophysics Data System (ADS)

Park, Chin-Sung; Hwang, Kyu-Youn; Jung, Wonjong; Namkoong, Kak; Chung, Wonseok; Kim, Joon-Ho; Huh, Nam

2014-02-01

We have developed a monolithic polydimethylsiloxane (PDMS) membrane microvalve with an isotropically etched valve seat for robust microfluidics. In order to avoid bonding or sticking of the PDMS membrane to the valve seat during the bonding process, the valve seat was wet-etched to be a one-dimensional line instead of a plane. The simple wet-etching technique allowed for the fabrication of an anti-bonding architecture in a scalable manner, and it intrinsically prevented contact between the PDMS membrane and valve seat when no external force was applied (i.e., normally open). This approach enables the permanent device assembly so that the microfluidic chip can be operable in a wide range of fluid pressures (e.g., over 200 kPa) without any leakage and sticking problems.

Microfluidic "thin chips" for chemical separations.

PubMed

Gaspar, Attila; Salgado, Marisol; Stevens, Schetema; Gomez, Frank A

2010-08-01

This paper describes the design, development and application of microfluidic "thin chips" fabricated from PDMS. Thin chips consist of multiple layers of PDMS chemically bonded onto each other. Unlike thicker PDMS chips that suffer from lack of sensitivity due to PDMS absorption in the VIS and UV range, the thinness of these chips allows for the detection of chromophoric species within the microchannel via an external fiber optics detection system. C18-modified reversed-phase silica particles are packed into the microchannel using a temporary taper created by a magnetic valve and separations using both pressure- and electrochromatographic-driven methods are detailed.

Ultra-thin GaAs single-junction solar cells integrated with a reflective back scattering layer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Weiquan; Becker, Jacob; Liu, Shi

2014-05-28

This paper reports the proposal, design, and demonstration of ultra-thin GaAs single-junction solar cells integrated with a reflective back scattering layer to optimize light management and minimize non-radiative recombination. According to our recently developed semi-analytical model, this design offers one of the highest potential achievable efficiencies for GaAs solar cells possessing typical non-radiative recombination rates found among commercially available III-V arsenide and phosphide materials. The structure of the demonstrated solar cells consists of an In{sub 0.49}Ga{sub 0.51}P/GaAs/In{sub 0.49}Ga{sub 0.51}P double-heterostructure PN junction with an ultra-thin 300 nm thick GaAs absorber, combined with a 5 μm thick Al{sub 0.52}In{sub 0.48}P layer with amore » textured as-grown surface coated with Au used as a reflective back scattering layer. The final devices were fabricated using a substrate-removal and flip-chip bonding process. Solar cells with a top metal contact coverage of 9.7%, and a MgF{sub 2}/ZnS anti-reflective coating demonstrated open-circuit voltages (V{sub oc}) up to 1.00 V, short-circuit current densities (J{sub sc}) up to 24.5 mA/cm{sup 2}, and power conversion efficiencies up to 19.1%; demonstrating the feasibility of this design approach. If a commonly used 2% metal grid coverage is assumed, the anticipated J{sub sc} and conversion efficiency of these devices are expected to reach 26.6 mA/cm{sup 2} and 20.7%, respectively.« less

Consortia for Known Good Die (KGD), phase 1

NASA Astrophysics Data System (ADS)

Andrews, Marshall; Carey, David; Fellows, Mary M.; Gilg, Larry; Murphy, Cindy; Noddings, Chad; Pitts, Greg; Rathmell, Claude; Spooner, Charles

1994-02-01

This report describes the results of Phase 1 of the Infrastructure for KGD program at MCC. The objective of the work is to resolve the issues for supplying and procuring Known Good Die (KGD) in a way that fosters industry acceptance and confidence in Application Specific Electronic Modules (ASEM's for military systems) and MultiChip Modules (MCM's for commercial systems). This report is divided into four sections. Section 1 describes the technical assessment of proposed industry approaches to KGD implementation. Section 2 of the report contains an outline for the plan for industry and government cooperation for the demonstration, validation, and implementation of KGD methodologies identified in this Phase 1 study. Section 3 of the report contains the industry-generated requirements for KGD implementation. Section IV of the report contains the KGD specifications for TAB and flip chip IC's.

Using a non-spin flip model to rationalize the irregular patterns observed in the activation of the C-H and Si-H bonds of small molecules by CpMCO (M = Co, Rh) complexes.

PubMed

Castro, Guadalupe; Colmenares, Fernando

2017-09-20

The activation of the C-H and Si-H bonds of CH(CH 3 ) 3 and SiH(CH 3 ) 3 molecules by organometallic compounds CpMCO (M = Co, Rh) has been investigated through DFT and CASSCF-MRMP2 calculations. In particular, we have analyzed the pathways joining the lowest-lying triplet and singlet states of the reactants with the products arising from the insertion of the metal atom into the C-H or Si-H bonds of the organic molecules. Channels connecting the reactants with the inserted structure Cp(CO)H-M-C(CH 3 ) 3 through the oxidative addition of the C-H bond of the organic molecule to the metal fragment were found only for the reaction CpRhCO + CH(CH 3 ) 3 . However, inserted structures could also be obtained for the interactions of SiH(CH 3 ) 3 with CpCoCO and CpRhCO by two sequential reactions involving the formation and rebounding of the radical fragments Cp(CO)H-M + Si(CH 3 ) 3 . According to this two-step reaction scheme, the complex CpCoCO is unable to activate the C-H bond of the CH(CH 3 ) 3 molecule due to the high energy at which the radical fragments Cp(CO)H-M + C(CH 3 ) 3 are located. The picture attained for these interactions is consistent with the available experimental data for this kind of reaction and allows rationalization of the differences in the reactivity patterns determined for them without using spin-flip models, as has been proposed in previous studies.

Flipping the Classroom without Flipping Out the Students: Working with an Instructional Designer in an Undergraduate Evidence-Based Nursing Practice Course

ERIC Educational Resources Information Center

Matsuda, Yui; Azaiza, Khitam; Salani, Deborah

2017-01-01

The flipped classroom approach is an innovative teaching method to promote students' active learning. It has been used in nursing education and has showed positive results. The purpose of this article is to describe the process of developing a flipped classroom approach for an undergraduate evidence-based nursing practice course and discuss…

How we flipped the medical classroom.

PubMed

Sharma, Neel; Lau, C S; Doherty, Iain; Harbutt, Darren

2015-04-01

Flipping the classroom centres on the delivery of print, audio or video based material prior to a lecture or class session. The class session is then dedicated to more active learning processes with application of knowledge through problem solving or case based scenarios. The rationale behind this approach is that teachers can spend their face-to-face time supporting students in deeper learning processes. In this paper we provide a background literature review on the flipped classroom along with a three step approach to flipping the classroom comprising implementing, enacting and evaluating this form of pedagogy. Our three step approach is based on actual experience of delivering a flipped classroom at the University of Hong Kong. This initiative was evaluated with positive results. We hope our experience will be transferable to other medical institutions.

GaN-based flip-chip LEDs with highly reflective ITO/DBR p-type and via hole-based n-type contacts for enhanced current spreading and light extraction

NASA Astrophysics Data System (ADS)

Zhou, Shengjun; Zheng, Chenju; Lv, Jiajiang; Gao, Yilin; Wang, Ruiqing; Liu, Sheng

2017-07-01

We demonstrate GaN-based double-layer electrode flip-chip light-emitting diodes (DLE-FCLED) with highly reflective indium-tin oxide (ITO)/distributed bragg reflector (DBR) p-type contact and via hole-based n-type contacts. Transparent thin ITO in combination with TiO2/SiO2 DBR is used for reflective p-type ohmic contact, resulting in a significant reduction in absorption of light by opaque metal electrodes. The finely distributed via hole-based n-type contacts are formed on the n-GaN layer by etching via holes through p-GaN and multiple quantum well (MQW) active layer, leading to reduced lateral current spreading length, and hence alleviated current crowding effect. The forward voltage of the DLE-FCLED is 0.31 V lower than that of the top-emitting LED at 90 mA. The light output power of DLE-FCLED is 15.7% and 80.8% higher than that of top-emitting LED at 90 mA and 300 mA, respectively. Compared to top- emitting LED, the external quantum efficiency (EQE) of DLE-FCLED is enhanced by 15.4% and 132% at 90 mA and 300 mA, respectively. The maximum light output power of the DLE-FCLED obtained at 195.6 A/cm2 is 1.33 times larger than that of the top-emitting LED obtained at 93 A/cm2.

Grinding damage assessment on four high-strength ceramics.

PubMed

Canneto, Jean-Jacques; Cattani-Lorente, Maria; Durual, Stéphane; Wiskott, Anselm H W; Scherrer, Susanne S

2016-02-01

The purpose of this study was to assess surface and subsurface damage on 4 CAD-CAM high-strength ceramics after grinding with diamond disks of 75 μm, 54 μm and 18 μm and to estimate strength losses based on damage crack sizes. The materials tested were: 3Y-TZP (Lava), dense Al2O3 (In-Ceram AL), alumina glass-infiltrated (In-Ceram ALUMINA) and alumina-zirconia glass-infiltrated (In-Ceram ZIRCONIA). Rectangular specimens with 2 mirror polished orthogonal sides were bonded pairwise together prior to degrading the top polished surface with diamond disks of either 75 μm, 54 μm or 18 μm. The induced chip damage was evaluated on the bonded interface using SEM for chip depth measurements. Fracture mechanics were used to estimate fracture stresses based on average and maximum chip depths considering these as critical flaws subjected to tension and to calculate possible losses in strength compared to manufacturer's data. 3Y-TZP was hardly affected by grinding chip damage viewed on the bonded interface. Average chip depths were of 12.7±5.2 μm when grinding with 75 μm diamond inducing an estimated loss of 12% in strength compared to manufacturer's reported flexural strength values of 1100 MPa. Dense alumina showed elongated chip cracks and was suffering damage of an average chip depth of 48.2±16.3 μm after 75 μm grinding, representing an estimated loss in strength of 49%. Grinding with 54 μm was creating chips of 32.2±9.1 μm in average, representing a loss in strength of 23%. Alumina glass-infiltrated ceramic was exposed to chipping after 75 μm (mean chip size=62.4±19.3 μm) and 54 μm grinding (mean chip size=42.8±16.6 μm), with respectively 38% and 25% estimated loss in strength. Alumina-zirconia glass-infiltrated ceramic was mainly affected by 75 μm grinding damage with a chip average size of 56.8±15.1 μm, representing an estimated loss in strength of 34%. All four ceramics were not exposed to critical chipping at 18 μm diamond grinding. Reshaping a ceramic framework post sintering should be avoided with final diamond grits of 75 μm as a general rule. For alumina and the glass-infiltrated alumina, using a 54 μm diamond still induces chip damage which may affect strength. Removal of such damage from a reshaped framework is mandatory by using sequentially finer diamonds prior to the application of veneering ceramics especially in critical areas such as margins, connectors and inner surfaces. Copyright © 2015 Academy of Dental Materials. Published by Elsevier Ltd. All rights reserved.

Preparation of a YAG:Ce phosphor glass by screen-printing technology and its application in LED packaging.

PubMed

Yang, Liang; Chen, Mingxiang; Lv, Zhicheng; Wang, Simin; Liu, Xiaogang; Liu, Sheng

2013-07-01

A simple and practical method for preparing phosphor glass is proposed. Phosphor distribution and element analysis are investigated by optical microscope and field emission scanning electron microscope (FE-SEM). The phosphor particles dispersed in the matrix are vividly observed, and their distributions are uniform. Spectrum distribution and color coordinates dependent on the thickness of the screen-printed phosphor layer coupled with a blue light emitting diode (LED) chip are studied. The luminous efficacy of the 75 μm printed phosphor-layer phosphor glass packaged white LED is 81.24 lm/W at 350 mA. This study opens up many possibilities for applications using the phosphor glass on a selected chip in which emission is well absorbed by all phosphors. The screen-printing technique also offers possibilities for the design and engineering of complex phosphor layers on glass substrates. Phosphor screen-printing technology allows the realization of high stability and thermal conductivity for the phosphor layer. This phosphor glass method provides many possibilities for LED packing, including thin-film flip chip and remote phosphor technology.

Enabling Large Focal Plane Arrays Through Mosaic Hybridization

NASA Technical Reports Server (NTRS)

Miller, Timothy M.; Jhabvala, Christine A.; Leong, Edward; Costen, Nick P.; Sharp, Elmer; Adachi, Tomoko; Benford, Dominic J.

2012-01-01

We have demonstrated advances in mosaic hybridization that will enable very large format far-infrared detectors. Specifically we have produced electrical detector models via mosaic hybridization yielding superconducting circuit patbs by hybridizing separately fabricated sub-units onto a single detector unit. The detector model was made on a 100mm diameter wafer while four model readout quadrant chips were made from a separate 100mm wafer. The individually fabric.ted parts were hybridized using a Suss FCI50 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the model mosaic-hybrid detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently available.

Thin-Film Quantum Dot Photodiode for Monolithic Infrared Image Sensors †

PubMed Central

Georgitzikis, Epimitheas; Vamvaka, Ioanna; Frazzica, Fortunato; Van Olmen, Jan; De Moor, Piet; Heremans, Paul; Hens, Zeger; Cheyns, David

2017-01-01

Imaging in the infrared wavelength range has been fundamental in scientific, military and surveillance applications. Currently, it is a crucial enabler of new industries such as autonomous mobility (for obstacle detection), augmented reality (for eye tracking) and biometrics. Ubiquitous deployment of infrared cameras (on a scale similar to visible cameras) is however prevented by high manufacturing cost and low resolution related to the need of using image sensors based on flip-chip hybridization. One way to enable monolithic integration is by replacing expensive, small-scale III–V-based detector chips with narrow bandgap thin-films compatible with 8- and 12-inch full-wafer processing. This work describes a CMOS-compatible pixel stack based on lead sulfide quantum dots (PbS QD) with tunable absorption peak. Photodiode with a 150-nm thick absorber in an inverted architecture shows dark current of 10−6 A/cm2 at −2 V reverse bias and EQE above 20% at 1440 nm wavelength. Optical modeling for top illumination architecture can improve the contact transparency to 70%. Additional cooling (193 K) can improve the sensitivity to 60 dB. This stack can be integrated on a CMOS ROIC, enabling order-of-magnitude cost reduction for infrared sensors. PMID:29232871

Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator

NASA Astrophysics Data System (ADS)

Nishikata, Daisuke; Ali, Mohammad Alimudin Bin Mohd; Hosoda, Kento; Matsumoto, Hiroshi; Nakamura, Kazuyuki

2018-04-01

A 36-bit × 32-entry fully digital ternary content addressable memory (TCAM) using the ratioless static random access memory (RL-SRAM) technology and fully complementary hierarchical-AND matching comparators (HAMCs) was developed. Since its fully complementary and digital operation enables the effect of device variabilities to be avoided, it can operate with a quite low supply voltage. A test chip incorporating a conventional TCAM and a proposed 24-transistor ratioless TCAM (RL-TCAM) cells and HAMCs was developed using a 0.18 µm CMOS process. The minimum operating voltage of 0.25 V of the developed RL-TCAM, which is less than half of that of the conventional TCAM, was measured via the conventional CMOS push–pull output buffers with the level-shifting and flipping technique using optimized pull-up voltage and resistors.

Micromechanical Waveguide Mounts for Hot Electron Bolometer Terahertz Mixers

NASA Astrophysics Data System (ADS)

Brandt, Michael; Jacobs, Karl; Honingh, C. E.; Stodolka, Jörg

The superior beam matching of waveguide horn antennas to a telescope suggests using waveguide mounts even at THz-frequencies. In contrast to the more common quasi-optical (substrate lens) designs, the exceedingly small dimensions of the waveguide require novel micro-mechanical fabrication technologies. We will present a novel fabrication scheme for 1.9 THz waveguide mixers for SOFIA. Hot Electron Bolometer devices (HEB) are fabricated on 2 μm thick Si3N4 membrane strips. The strips are robust enough to be mounted on a separately fabricated Si support frame using an adapted flip-chip technology. Mounted onto the frame, the devices can be easily positioned and glued into a copper waveguide mount. Further developments regarding micro-mechanical processes to fabricate this copper waveguide mount and the receiving horn antenna will be presented, as well as the KOSMA Micro Assembly Station and its capabilities to handle mixer substrates.

A simple method of fabricating mask-free microfluidic devices for biological analysis

PubMed Central

Yi, Xin; Kodzius, Rimantas; Gong, Xiuqing; Xiao, Kang; Wen, Weijia

2010-01-01

We report a simple, low-cost, rapid, and mask-free method to fabricate two-dimensional (2D) and three-dimensional (3D) microfluidic chip for biological analysis researches. In this fabrication process, a laser system is used to cut through paper to form intricate patterns and differently configured channels for specific purposes. Bonded with cyanoacrylate-based resin, the prepared paper sheet is sandwiched between glass slides (hydrophilic) or polymer-based plates (hydrophobic) to obtain a multilayer structure. In order to examine the chip’s biocompatibility and applicability, protein concentration was measured while DNA capillary electrophoresis was carried out, and both of them show positive results. With the utilization of direct laser cutting and one-step gas-sacrificing techniques, the whole fabrication processes for complicated 2D and 3D microfluidic devices are shorten into several minutes which make it a good alternative of poly(dimethylsiloxane) microfluidic chips used in biological analysis researches. PMID:20890452

Miniaturized optical wavelength sensors

NASA Astrophysics Data System (ADS)

Kung, Helen Ling-Ning

Recently semiconductor processing technology has been applied to the miniaturization of optical wavelength sensors. Compact sensors enable new applications such as integrated diode-laser wavelength monitors and frequency lockers, portable chemical and biological detection, and portable and adaptive hyperspectral imaging arrays. Small sensing systems have trade-offs between resolution, operating range, throughput, multiplexing and complexity. We have developed a new wavelength sensing architecture that balances these parameters for applications involving hyperspectral imaging spectrometer arrays. In this thesis we discuss and demonstrate two new wavelength-sensing architectures whose single-pixel designs can easily be extended into spectrometer arrays. The first class of devices is based on sampling a standing wave. These devices are based on measuring the wavelength-dependent period of optical standing waves formed by the interference of forward and reflected waves at a mirror. We fabricated two different devices based on this principle. The first device is a wavelength monitor, which measures the wavelength and power of a monochromatic source. The second device is a spectrometer that can also act as a selective spectral coherence sensor. The spectrometer contains a large displacement piston-motion MEMS mirror and a thin GaAs photodiode flip-chip bonded to a quartz substrate. The performance of this spectrometer is similar to that of a Michelson in resolution, operating range, throughput and multiplexing but with the added advantages of fewer components and one-dimensional architecture. The second class of devices is based on the Talbot self-imaging effect. The Talbot effect occurs when a periodic object is illuminated with a spatially coherent wave. Periodically spaced self-images are formed behind the object. The spacing of the self-images is proportional to wavelength of the incident light. We discuss and demonstrate how this effect can be used for spectroscopy. In the conclusion we compare these two new miniaturized spectrometer architectures to existing miniaturized spectrometers. We believe that the combination of miniaturized wavelength sensors and smart processing should facilitate the development real-time, adaptive and portable sensing systems.

Poisson property of the occurrence of flip-flops in a model membrane.

PubMed

Arai, Noriyoshi; Akimoto, Takuma; Yamamoto, Eiji; Yasui, Masato; Yasuoka, Kenji

2014-02-14

How do lipid molecules in membranes perform a flip-flop? The flip-flops of lipid molecules play a crucial role in the formation and flexibility of membranes. However, little has been determined about the behavior of flip-flops, either experimentally, or in molecular dynamics simulations. Here, we provide numerical results of the flip-flops of model lipid molecules in a model membrane and investigate the statistical properties, using millisecond-order coarse-grained molecular simulations (dissipative particle dynamics). We find that there are three different ways of flip-flops, which can be clearly characterized by their paths on the free energy surface. Furthermore, we found that the probability of the number of the flip-flops is well fitted by the Poisson distribution, and the probability density function for the inter-occurrence times of flip-flops coincides with that of the forward recurrence times. These results indicate that the occurrence of flip-flops is a Poisson process, which will play an important role in the flexibilities of membranes.

A 16 x 16-pixel retinal-prosthesis vision chip with in-pixel digital image processing in a frequency domain by use of a pulse-frequency-modulation photosensor

NASA Astrophysics Data System (ADS)

Kagawa, Keiichiro; Furumiya, Tetsuo; Ng, David C.; Uehara, Akihiro; Ohta, Jun; Nunoshita, Masahiro

2004-06-01

We are exploring the application of pulse-frequency-modulation (PFM) photosensor to retinal prosthesis for the blind because behavior of PFM photosensors is similar to retinal ganglion cells, from which visual data are transmitted from the retina toward the brain. We have developed retinal-prosthesis vision chips that reshape the output pulses of the PFM photosensor to biphasic current pulses suitable for electric stimulation of retinal cells. In this paper, we introduce image-processing functions to the pixel circuits. We have designed a 16x16-pixel retinal-prosthesis vision chip with several kinds of in-pixel digital image processing such as edge enhancement, edge detection, and low-pass filtering. This chip is a prototype demonstrator of the retinal prosthesis vision chip applicable to in-vitro experiments. By utilizing the feature of PFM photosensor, we propose a new scheme to implement the above image processing in a frequency domain by digital circuitry. Intensity of incident light is converted to a 1-bit data stream by a PFM photosensor, and then image processing is executed by a 1-bit image processor based on joint and annihilation of pulses. The retinal prosthesis vision chip is composed of four blocks: a pixels array block, a row-parallel stimulation current amplifiers array block, a decoder block, and a base current generators block. All blocks except PFM photosensors and stimulation current amplifiers are embodied as digital circuitry. This fact contributes to robustness against noises and fluctuation of power lines. With our vision chip, we can control photosensitivity and intensity and durations of stimulus biphasic currents, which are necessary for retinal prosthesis vision chip. The designed dynamic range is more than 100 dB. The amplitude of the stimulus current is given by a base current, which is common for all pixels, multiplied by a value in an amplitude memory of pixel. Base currents of the negative and positive pulses are common for the all pixels, and they are set in a linear manner. Otherwise, the value in the amplitude memory of the pixel is presented in an exponential manner to cover the wide range. The stimulus currents are put out column by column by scanning. The pixel size is 240um x 240um. Each pixel has a bonding pad on which stimulus electrode is to be formed. We will show the experimental results of the test chip.

DINS Final Report.

DTIC Science & Technology

1979-10-19

A optical input from a laser ggw system . The photodetector assembly shall consist of two chips: (1) photodiode chip and (2) preamplifier chip. The...181 4.1 Transienit Gamm ------ - 182 4.2 Therm~al Noise ------------------- 186 2 1 System F’unatioma Diagram -B 2 Bonding...5 2u.0 ed IG o Hl MM The desJign reurnents of the DIM~ Pbto detector System are - The system sball 1eev a 300 nhnowatt, (Min.) 63282 signal from a

Family of fuzzy J-K flip-flops based on bounded product, bounded sum and complementation.

PubMed

Gniewek, L; Kluska, J

1998-01-01

This paper presents a concept of new fuzzy J-K flip-flops based on bounded product, bounded sum and fuzzy complementation operations. Relationships between various types of the J-K flip-flops are given and characteristics of them are graphically shown by computer simulation. Two examples of circuits able to memorize and fuzzy information processing using the proposed fuzzy J-K flip-flops are presented.

Cellular FLICE-inhibitory Protein (cFLIP) Isoforms Block CD95- and TRAIL Death Receptor-induced Gene Induction Irrespective of Processing of Caspase-8 or cFLIP in the Death-inducing Signaling Complex*

PubMed Central

Kavuri, Shyam M.; Geserick, Peter; Berg, Daniela; Dimitrova, Diana Panayotova; Feoktistova, Maria; Siegmund, Daniela; Gollnick, Harald; Neumann, Manfred; Wajant, Harald; Leverkus, Martin

2011-01-01

Death receptors (DRs) induce apoptosis but also stimulate proinflammatory “non-apoptotic” signaling (e.g. NF-κB and mitogen-activated protein kinase (MAPK) activation) and inhibit distinct steps of DR-activated maturation of procaspase-8. To examine whether isoforms of cellular FLIP (cFLIP) or its cleavage products differentially regulate DR signaling, we established HaCaT cells expressing cFLIPS, cFLIPL, or mutants of cFLIPL (cFLIPD376N and cFLIPp43). cFLIP variants blocked TRAIL- and CD95L-induced apoptosis, but the cleavage pattern of caspase-8 in the death inducing signaling complex was different: cFLIPL induced processing of caspase-8 to the p43/41 fragments irrespective of cFLIP cleavage. cFLIPS or cFLIPp43 blocked procaspase-8 cleavage. Analyzing non-apoptotic signaling pathways, we found that TRAIL and CD95L activate JNK and p38 within 15 min. cFLIP variants and different caspase inhibitors blocked late death ligand-induced JNK or p38 MAPK activation suggesting that these responses are secondary to cell death. cFLIP isoforms/mutants also blocked death ligand-mediated gene induction of CXCL-8 (IL-8). Knockdown of caspase-8 fully suppressed apoptotic and non-apoptotic signaling. Knockdown of cFLIP isoforms in primary human keratinocytes enhanced CD95L- and TRAIL-induced NF-κB activation, and JNK and p38 activation, underscoring the regulatory role of cFLIP for these DR-mediated signals. Whereas the presence of caspase-8 is critical for apoptotic and non-apoptotic signaling, cFLIP isoforms are potent inhibitors of TRAIL- and CD95L-induced apoptosis, NF-κB activation, and the late JNK and p38 MAPK activation. cFLIP-mediated inhibition of CD95 and TRAIL DR could be of crucial importance during keratinocyte skin carcinogenesis and for the activation of innate and/or adaptive immune responses triggered by DR activation in the skin. PMID:21454681

MEMS Incandescent Light Source

NASA Technical Reports Server (NTRS)

Tuma, Margaret; King, Kevin; Kim, Lynn; Hansler, Richard; Jones, Eric; George, Thomas

2001-01-01

A MEMS-based, low-power, incandescent light source is being developed. This light source is fabricated using three bonded chips. The bottom chip consists of a reflector on Silicon, the middle chip contains a Tungsten filament bonded to silicon and the top layer is a transparent window. A 25-micrometer-thick spiral filament is fabricated in Tungsten using lithography and wet-etching. A proof-of-concept device has been fabricated and tested in a vacuum chamber. Results indicate that the filament is electrically heated to approximately 2650 K. The power required to drive the proof-of-concept spiral filament to incandescence is 1.25 W. The emitted optical power is expected to be approximately 1.0 W with the spectral peak at 1.1 microns. The micromachining techniques used to fabricate this light source can be applied to other MEMS devices.

Exploring Flipped Classroom Effects on Second Language Learners' Cognitive Processing

ERIC Educational Resources Information Center

Kim, Jeong-eun; Park, Hyunjin; Jang, Mijung; Nam, Hosung

2017-01-01

This study investigated the cognitive effects of the flipped classroom approach in a content-based instructional context by comparing second language learners' discourse in flipped vs. traditional classrooms in terms of (1) participation rate, (2) content of comments, (3) reasoning skills, and (4) interactional patterns. Learners in two intact…

Molecular mechanism of H+ conduction in the single-file water chain of the gramicidin channel.

PubMed

Pomès, Régis; Roux, Benoît

2002-05-01

The conduction of protons in the hydrogen-bonded chain of water molecules (or "proton wire") embedded in the lumen of gramicidin A is studied with molecular dynamics free energy simulations. The process may be described as a "hop-and-turn" or Grotthuss mechanism involving the chemical exchange (hop) of hydrogen nuclei between hydrogen-bonded water molecules arranged in single file in the lumen of the pore, and the subsequent reorganization (turn) of the hydrogen-bonded network. Accordingly, the conduction cycle is modeled by two complementary steps corresponding respectively to the translocation 1) of an ionic defect (H+) and 2) of a bonding defect along the hydrogen-bonded chain of water molecules in the pore interior. The molecular mechanism and the potential of mean force are analyzed for each of these two translocation steps. It is found that the mobility of protons in gramicidin A is essentially determined by the fine structure and the dynamic fluctuations of the hydrogen-bonded network. The translocation of H+ is mediated by spontaneous (thermal) fluctuations in the relative positions of oxygen atoms in the wire. In this diffusive mechanism, a shallow free-energy well slightly favors the presence of the excess proton near the middle of the channel. In the absence of H+, the water chain adopts either one of two polarized configurations, each of which corresponds to an oriented donor-acceptor hydrogen-bond pattern along the channel axis. Interconversion between these two conformations is an activated process that occurs through the sequential and directional reorientation of water molecules of the wire. The effect of hydrogen-bonding interactions between channel and water on proton translocation is analyzed from a comparison to the results obtained previously in a study of model nonpolar channels, in which such interactions were missing. Hydrogen-bond donation from water to the backbone carbonyl oxygen atoms lining the pore interior has a dual effect: it provides a coordination of water molecules well suited both to proton hydration and to high proton mobility, and it facilitates the slower reorientation or turn step of the Grotthuss mechanism by stabilizing intermediate configurations of the hydrogen-bonded network in which water molecules are in the process of flipping between their two preferred, polarized states. This mechanism offers a detailed molecular model for the rapid transport of protons in channels, in energy-transducing membrane proteins, and in enzymes.

High Efficiency Coupling of Optical Fibres with SU8 Micro-droplet Using Laser Welding Process

NASA Astrophysics Data System (ADS)

Yardi, Seema; Gupta, Ankur; Sundriyal, Poonam; Bhatt, Geeta; Kant, Rishi; Boolchandani, D.; Bhattacharya, Shantanu

2016-09-01

Apart from micro- structure fabrication, ablation, lithography etc., lasers find a lot of utility in various areas like precision joining, device fabrication, local heat delivery for surface texturing and local change of microstructure fabrication of standalone optical micro-devices (like microspheres, micro-prisms, micro-scale ring resonators, optical switches etc). There is a wide utility of such systems in chemical/ biochemical diagnostics and also communications where the standalone optical devices exist at a commercial scale but chip based devices with printed optics are necessary due to coupling issues between printed structures and external optics. This paper demonstrates a novel fabrication strategy used to join standalone optical fibres to microchip based printed optics using a simple SU8 drop. The fabrication process is deployed for fiber to fiber optical coupling and coupling between fiber and printed SU-8 waveguides. A CO2 laser is used to locally heat the coupling made up of SU8 material. Optimization of various dimensional parameters using design of experiments (DOE) on the bonded assembly has been performed as a function of laser power, speed, cycle control, spot size so on so forth. Exclusive optical [RF] modelling has been performed to estimate the transmissibility of the optical fibers bonded to each other on a surface with SU8. Our studies indicate the formation of a Whispering gallery mode (WGM) across the micro-droplet leading to high transmissibility of the signal. Through this work we have thus been able to develop a method of fabrication for optical coupling of standalone fibers or coupling of on-chip optics with off-chip illumination/detection.

On-demand acoustic droplet splitting and steering in a disposable microfluidic chip.

PubMed

Park, Jinsoo; Jung, Jin Ho; Park, Kwangseok; Destgeer, Ghulam; Ahmed, Husnain; Ahmad, Raheel; Sung, Hyung Jin

2018-01-30

On-chip droplet splitting is one of the fundamental droplet-based microfluidic unit operations to control droplet volume after production and increase operational capability, flexibility, and throughput. Various droplet splitting methods have been proposed, and among them the acoustic droplet splitting method is promising because of its label-free operation without any physical or thermal damage to droplets. Previous acoustic droplet splitting methods faced several limitations: first, they employed a cross-type acoustofluidic device that precluded multichannel droplet splitting; second, they required irreversible bonding between a piezoelectric substrate and a microfluidic chip, such that the fluidic chip was not replaceable. Here, we present a parallel-type acoustofluidic device with a disposable microfluidic chip to address the limitations of previous acoustic droplet splitting devices. In the proposed device, an acoustic field is applied in the direction opposite to the flow direction to achieve multichannel droplet splitting and steering. A disposable polydimethylsiloxane microfluidic chip is employed in the developed device, thereby removing the need for permanent bonding and improving the flexibility of the droplet microfluidic device. We experimentally demonstrated on-demand acoustic droplet bi-splitting and steering with precise control over the droplet splitting ratio, and we investigated the underlying physical mechanisms of droplet splitting and steering based on Laplace pressure and ray acoustics analyses, respectively. We also demonstrated droplet tri-splitting to prove the feasibility of multichannel droplet splitting. The proposed on-demand acoustic droplet splitting device enables on-chip droplet volume control in various droplet-based microfluidic applications.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fahim, Farah; Deptuch, Grzegorz; Shenai, Alpana

The Vertically Integrated Photon Imaging Chip - Large, (VIPIC-L), is a large area, small pixel (65μm), 3D integrated, photon counting ASIC with zero-suppressed or full frame dead-time-less data readout. It features data throughput of 14.4 Gbps per chip with a full frame readout speed of 56kframes/s in the imaging mode. VIPIC-L contain 192 x 192 pixel array and the total size of the chip is 1.248cm x 1.248cm with only a 5μm periphery. It contains about 120M transistors. A 1.3M pixel camera module will be developed by arranging a 6 x 6 array of 3D VIPIC-L’s bonded to a largemore » area silicon sensor on the analog side and to a readout board on the digital side. The readout board hosts a bank of FPGA’s, one per VIPIC-L to allow processing of up to 0.7 Tbps of raw data produced by the camera.« less

Stacked Fresnel Zone Plates for High Energy X-rays

NASA Astrophysics Data System (ADS)

Snigireva, Irina; Snigirev, Anatoly; Vaughan, Gavin; Di Michiel, Marco; Kohn, Viktor; Yunkin, Vyacheslav; Grigoriev, Maxim

2007-01-01

A stacking technique was developed in order to increase focusing efficiency of Fresnel zone plates (FZP) at high energies. Two identical Si chips each of which containing 9 FZPs were used for stacking. Alignment of the chips was achieved by on-line observation of the moiré pattern. The formation of moiré patterns was studied theoretically and experimentally at different experimental conditions. To provide the desired stability Si-chips were bonded together with slow solidification speed epoxy glue. A technique of angular alignment in order to compensate a linear displacement in the process of gluing was proposed. Two sets of stacked FZPs were experimentally tested to focus 15 and 50 keV x rays. The gain in the efficiency by factor 2.5 was demonstrated at 15 keV. The focal spot of 1.8 μm vertically and 14 μm horizontally with 35% efficiency was measured at 50 keV. Forecast for the stacking of nanofocusing FZPs was discussed.

Hard X-ray focusing by stacked Fresnel zone plates

NASA Astrophysics Data System (ADS)

Snigireva, Irina; Snigirev, Anatoly; Kohn, Viktor; Yunkin, Vyacheslav; Grigoriev, Maxim; Kuznetsov, Serguei; Vaughan, Gavin; Di Michiel, Marco

2007-09-01

Stacking technique was developed in order to increase focusing efficiency of Fresnel zone plates at high energies. Two identical Si chips each of which containing Fresnel zone plates were used for stacking. Alignment of the chips was achieved by on-line observation of the moiré pattern from the two zone plates. The formation of moiré patterns was studied theoretically and experimentally at different experimental conditions. To provide the desired stability Si-chips with zone plates were bonded together with slow solidification speed epoxy glue. Technique of angular alignment in order to compensate a linear displacement in the process of gluing was proposed. Two sets of stacked FZPs were produced and experimentally tested to focus 15 and 50 keV X-rays. Gain in the efficiency by factor 2.5 was demonstrated at 15 keV. Focal spot of 1.8 μm vertically and 14 μm horizontally with 35% efficiency was measured at 50 keV. Forecast for the stacking of nanofocusing Fresnel zone plates was discussed.

Atom Chips on Direct Bonded Copper Substrates (Postprint)

DTIC Science & Technology

2012-01-19

joining of a thin sheet of pure copper to a ceramic substrate14 and is commonly used in power electronics due to its high current handling and heat...Squires et al. Rev. Sci. Instrum. 82, 023101 (2011) FIG. 1. A scanning electron micrograph of the top view of test chip A. the photolithographically...the etching pro- cesses and masking methods were quantified using a scanning electron microscope. Two test chips (A and B) are presented below and are

Implementing the Flipped Classroom in Teacher Education: Evidence from Turkey

ERIC Educational Resources Information Center

Kurt, Gökçe

2017-01-01

The flipped classroom, a form of blended learning, is an emerging instructional strategy reversing a traditional lecture-based teaching model to improve the quality and efficiency of the teaching and learning process. The present article reports a study that focused on the implementation of the flipped approach in a higher education institution in…

Integration of Indium Phosphide Based Devices with Flexible Substrates

NASA Astrophysics Data System (ADS)

Chen, Wayne Huai

2011-12-01

Flexible substrates have many advantages in applications where bendability, space, or weight play important roles or where rigid circuits are undesirable. However, conventional flexible thin film transistors are typically characterized as having low carrier mobility as compared to devices used in the electronics industry. This is in part due to the limited temperature tolerance of plastic flexible substrates, which commonly reduces the highest processing temperature to below 200°C. Common approaches of implementation include low temperature deposition of organic, amorphous, or polycrystalline semiconductors, all of which result in carrier mobility well below 100 cm2V -1s-1. High quality, single crystalline III-V semiconductors such as indium phosphide (InP), on the other hand, have carrier mobility well over 1000 cm 2V-1s-1 at room temperature, depending on carrier concentration. Recently, the ion-cut process has been used in conjunction with wafer bonding to integrate thin layers of III-V material onto silicon for optoelectronic applications. This approach has the advantage of high scalability, reusability of the initial III-V substrate, and the ability to tailor the location (depth) of the layer splitting. However, the transferred substrate usually suffers from hydrogen implantation damage. This dissertation demonstrates a new approach to enable integration of InP with various substrates, called the double-flip transfer process. The process combines ion-cutting with adhesive bonding. The problem of hydrogen implantation was overcome by patterned ion-cut transfer. In this type of transfer, areas of interest are shielded from implantation but still transferred by surrounding implanted regions. We found that patterned ion-cut transfer is strongly dependent upon crystal orientation and that using cleavage-plane oriented donors can be beneficial in transferring large areas of high quality semiconductor material. InP-based devices were fabricated to demonstrate the transfer process and test functionality following transfer. Passive devices (photodetectors) as well as active transistors were transferred and fabricated on various substrates. The transferred device layers were either implanted through with a blanket implant or protected with an ion-mask during implantation. Results demonstrate the viability of the double-flip ion-cut process in achieving very high electron mobility (˜2800 cm2V-1s-1) transistors on plastic flexible substrates.

Enhancement of slope efficiency and output power in GaN-based vertical-cavity surface-emitting lasers with a SiO2-buried lateral index guide

NASA Astrophysics Data System (ADS)

Kuramoto, Masaru; Kobayashi, Seiichiro; Akagi, Takanobu; Tazawa, Komei; Tanaka, Kazufumi; Saito, Tatsuma; Takeuchi, Tetsuya

2018-03-01

We have achieved a high output power of 6 mW from a 441 nm GaN-based vertical-cavity surface-emitting laser (VCSEL) under continuous wave (CW) operation, by reducing both the internal loss and the reflectivity of the front cavity mirror. A preliminary analysis of the internal loss revealed an enormously high transverse radiation loss in a conventional GaN-based VCSEL without lateral optical confinement (LOC). Introducing an LOC structure enhanced the slope efficiency by a factor of 4.7, with a further improvement to a factor of 6.7 upon reducing the front mirror reflectivity. The result was a slope efficiency of 0.87 W/A and an external differential quantum efficiency of 32% under pulsed operation. A flip-chip-bonded VCSEL also exhibited a high slope efficiency of 0.64 W/A and an external differential quantum efficiency of 23% for the front-side output under CW operation. The reflectivity of the cavity mirror was adjusted by varying the number of AlInN/GaN distributed Bragg reflector pairs from 46 to 42, corresponding to reflectivity values from 99.8% to 99.5%. These results demonstrate that a combination of internal loss reduction and cavity mirror control is a very effective way of obtaining a high output GaN-based VCSEL.

Design considerations for FET-gated power transistors

NASA Technical Reports Server (NTRS)

Chen, D. Y.; Chin, S. A.

1983-01-01

An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.

Development and applications of 3-dimensional integration nanotechnologies.

PubMed

Kim, Areum; Choi, Eunmi; Son, Hyungbin; Pyo, Sung Gyu

2014-02-01

Unlike conventional two-dimensional (2D) planar structures, signal or power is supplied through through-silicon via (TSV) in three-dimensional (3D) integration technology to replace wires for binding the chip/wafer. TSVs have becomes an essential technology, as they satisfy Moore's law. This 3D integration technology enables system and sensor functions at a nanoscale via the implementation of a highly integrated nano-semiconductor as well as the fabrication of a single chip with multiple functions. Thus, this technology is considered to be a new area of development for the systemization of the nano-bio area. In this review paper, the basic technology required for such 3D integration is described and methods to measure the bonding strength in order to measure the void occurring during bonding are introduced. Currently, CMOS image sensors and memory chips associated with nanotechnology are being realized on the basis of 3D integration technology. In this paper, we intend to describe the applications of high-performance nano-biosensor technology currently under development and the direction of development of a high performance lab-on-a-chip (LOC).

Laser vibrometry characterisation of a microfluidic lab-on-a-chip device: a preliminary investigation

NASA Astrophysics Data System (ADS)

Fury, C.; Gélat, P. N.; Jones, P. H.; Memoli, G.

2014-04-01

Since their original inception as ultrasound contrast agents, potential applications of microbubbles have evolved to encompass molecular imaging and targeted drug delivery. As these areas develop, so does the need to understand the mechanisms behind the interaction of microbubbles both with biological tissue and with other microbubbles. There is therefore a metrological requirement to develop a controlled environment in which to study these processes. Presented here is the design and characterisation of such a system, which consists of a microfluidic chip, specifically developed for manipulating microbubbles using both optical and acoustic trapping. A laser vibrometer is used to observe the coupling of acoustic energy into the chip from a piezoelectric transducer bonded to the surface. Measurement of the velocity of surface waves on the chip is investigated as a potential method for inferring the nature of the acoustic fields excited within the liquid medium of the device. Comparison of measured surface wavelengths with wave types suggests the observation of anti-symmetric Lamb or Love-Kirchhoff waves. Further visual confirmation of the acoustic fields through bubble aggregation highlights differences between the model and experimental results in predicting the position of acoustic pressure nodes in relation to excitation frequency.

Development of Equivalent Material Properties of Microbump for Simulating Chip Stacking Packaging

PubMed Central

Lee, Chang-Chun; Tzeng, Tzai-Liang; Huang, Pei-Chen

2015-01-01

A three-dimensional integrated circuit (3D-IC) structure with a significant scale mismatch causes difficulty in analytic model construction. This paper proposes a simulation technique to introduce an equivalent material composed of microbumps and their surrounding wafer level underfill (WLUF). The mechanical properties of this equivalent material, including Young’s modulus (E), Poisson’s ratio, shear modulus, and coefficient of thermal expansion (CTE), are directly obtained by applying either a tensile load or a constant displacement, and by increasing the temperature during simulations, respectively. Analytic results indicate that at least eight microbumps at the outermost region of the chip stacking structure need to be considered as an accurate stress/strain contour in the concerned region. In addition, a factorial experimental design with analysis of variance is proposed to optimize chip stacking structure reliability with four factors: chip thickness, substrate thickness, CTE, and E-value. Analytic results show that the most significant factor is CTE of WLUF. This factor affects microbump reliability and structural warpage under a temperature cycling load and high-temperature bonding process. WLUF with low CTE and high E-value are recommended to enhance the assembly reliability of the 3D-IC architecture. PMID:28793495

Flexible Chip Scale Package and Interconnect for Implantable MEMS Movable Microelectrodes for the Brain

PubMed Central

Jackson, Nathan; Muthuswamy, Jit

2009-01-01

We report here a novel approach called MEMS microflex interconnect (MMFI) technology for packaging a new generation of Bio-MEMS devices that involve movable microelectrodes implanted in brain tissue. MMFI addresses the need for (i) operating space for movable parts and (ii) flexible interconnects for mechanical isolation. We fabricated a thin polyimide substrate with embedded bond-pads, vias, and conducting traces for the interconnect with a backside dry etch, so that the flexible substrate can act as a thin-film cap for the MEMS package. A double gold stud bump rivet bonding mechanism was used to form electrical connections to the chip and also to provide a spacing of approximately 15–20 µm for the movable parts. The MMFI approach achieved a chip scale package (CSP) that is lightweight, biocompatible, having flexible interconnects, without an underfill. Reliability tests demonstrated minimal increases of 0.35 mΩ, 0.23 mΩ and 0.15 mΩ in mean contact resistances under high humidity, thermal cycling, and thermal shock conditions respectively. High temperature tests resulted in an increase in resistance of > 90 mΩ when aluminum bond pads were used, but an increase of ~ 4.2 mΩ with gold bond pads. The mean-time-to-failure (MTTF) was estimated to be at least one year under physiological conditions. We conclude that MMFI technology is a feasible and reliable approach for packaging and interconnecting Bio-MEMS devices. PMID:20160981

Numerical simulation and experimental investigation of GaN-based flip-chip LEDs and top-emitting LEDs.

PubMed

Liu, Xingtong; Zhou, Shengjun; Gao, Yilin; Hu, Hongpo; Liu, Yingce; Gui, Chengqun; Liu, Sheng

2017-12-01

We demonstrate a GaN-based flip-chip LED (FC-LED) with a highly reflective indium-tin oxide (ITO)/distributed Bragg reflector (DBR) ohmic contact. A transparent ITO current spreading layer combined with Ta 2 O 5 /SiO 2 double DBR stacks is used as a reflective p-type ohmic contact in the FC-LED. We develop a strip-shaped SiO 2 current blocking layer, which is well aligned with a p-electrode, to prevent the current from crowding around the p-electrode. Our combined numerical simulation and experimental results revealed that the FC-LED with ITO/DBR has advantages of better current spreading and superior heat dissipation performance compared to top-emitting LEDs (TE-LEDs). As a result, the light output power (LOP) of the FC-LED with ITO/DBR was 7.6% higher than that of the TE-LED at 150 mA, and the light output saturation current was shifted from 130.9  A/cm 2 for the TE-LED to 273.8  A/cm 2 for the FC-LED with ITO/DBR. Owing to the high reflectance of the ITO/DBR ohmic contact, the LOP of the FC-LED with ITO/DBR was 13.0% higher than that of a conventional FC-LED with Ni/Ag at 150 mA. However, because of the better heat dissipation of the Ni/Ag ohmic contact, the conventional FC-LED with Ni/Ag exhibited higher light output saturation current compared to the FC-LED with ITO/DBR.

Implementing a Flipped Classroom: A Case Study of Biology Teaching in a Greek High School

ERIC Educational Resources Information Center

Gariou-Papalexiou, Angeliki; Papadakis, Spyros; Manousou, Evangelia; Georgiadu, Irene

2017-01-01

The purpose of this study was to investigate the application of the model of the "flipped classroom" as a complementary method to school distance education in junior high school Biology. The "flipped classroom" model attempts a different way of organizing the educational process according to which the traditional methods of…

Student Perspectives on the Flipped-Classroom Approach and Collaborative Problem-Solving Process

ERIC Educational Resources Information Center

Karabulut-Ilgu, Aliye; Yao, Suhan; Savolainen, Peter; Jahren, Charles

2018-01-01

The flipped-classroom approach has gained increasing popularity and interest in engineering education. The purpose of this study was to investigate (a) student perspectives on the flipped-classroom approach in a transportation-engineering course and (b) how students used the in-class time dedicated to collaborative problem solving. To this end,…

Students' Perceptions and Emotions Toward Learning in a Flipped General Science Classroom

NASA Astrophysics Data System (ADS)

Jeong, Jin Su; González-Gómez, David; Cañada-Cañada, Florentina

2016-10-01

Recently, the inverted instruction methodologies are gaining attentions in higher educations by claiming that flipping the classroom engages more effectively students with the learning process. Besides, students' perceptions and emotions involved in their learning process must be assessed in order to gauge the usability of this relatively new instruction methodology, since it is vital in the educational formation. For this reason, this study intends to evaluate the students' perceptions and emotions when a flipped classroom setting is used as instruction methodology. This research was conducted in a general science course, sophomore of the Primary Education bachelor degree in the Training Teaching School of the University of Extremadura (Spain). The results show that the students have the overall positive perceptions to a flipped classroom setting. Particularly, over 80 % of them considered that the course was a valuable learning experience. They also found this course more interactive and were willing to have more courses following a flipped model. According to the students' emotions toward a flipped classroom course, the highest scores were given to the positive emotions, being fun and enthusiasm along with keyword frequency test. Then, the lowest scores were corresponded to negative emotions, being boredom and fear. Therefore, the students attending to a flipped course demonstrated to have more positive and less negative emotions. The results obtained in this study allow drawing a promising tendency about the students' perceptions and emotions toward the flipped classroom methodology and will contribute to fully frame this relatively new instruction methodology.

Silicon Hard-Stop Mesas for 3D Integration of Superconducting Qubits

NASA Astrophysics Data System (ADS)

Kim, David; Rosenberg, Danna; Osadchy, Brenda; Calusine, Greg; Das, Rabindra; Melville, Alexander; Yoder, Jonilyn; Yost, Donna-Ruth; Racz, Livia; Oliver, William

As quantum computing with superconducting qubits advances past the few-qubit stage, implementing 3D packaging/integration to route readout/control lines will become increasingly important. One approach is to bond chips that perform different functions using indium bump bonds. Because indium is malleable, however, achieving the desired spacing and tilt between two chips can be challenging. We present an approach based on etching several microns into the silicon substrate to produce hard stop silicon posts. Since this process involves etching into a pristine substrate, it is essential to evaluate its impact on qubit performance. We report the etched surface's effect on the resonator quality factor and qubit coherence time, as well as the improvement in planarity and tilt. This research was funded in part by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA) and by the Assistant Secretary of Defense for Research & Engineering under Air Force Contract No. FA8721-05-C-0002. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of ODNI, IARPA, or the US Government.

Particleboard made from remediated CCA-treated wood : evaluation of panel properties

Treesearch

Carol A. Clausen; S. Nami Kartal; James Muehl

2001-01-01

CCA-treated southern yellow pine (SYP) chips were remediated utilizing acid extraction alone, and using acid extraction followed by bioleaching with the metal-tolerant bacterium Bacillus licheniformis CC01. bCleanedc chips were used to make particleboard (PB) with 10 percent urea-formaldehyde (UF) resin, and the PB samples were evaluated for internal bond (IB), modulus...

Thermoelectric Coolers with Sintered Silver Interconnects

NASA Astrophysics Data System (ADS)

Kähler, Julian; Stranz, Andrej; Waag, Andreas; Peiner, Erwin

2014-06-01

The fabrication and performance of a sintered Peltier cooler (SPC) based on bismuth telluride with sintered silver interconnects are described. Miniature SPC modules with a footprint of 20 mm2 were assembled using pick-and-place pressure-assisted silver sintering at low pressure (5.5 N/mm2) and moderate temperature (250°C to 270°C). A modified flip-chip bonder combined with screen/stencil printing for paste transfer was used for the pick-and-place process, enabling high positioning accuracy, easy handling of the tiny bismuth telluride pellets, and immediate visual process control. A specific contact resistance of (1.4 ± 0.1) × 10-5 Ω cm2 was found, which is in the range of values reported for high-temperature solder interconnects of bismuth telluride pellets. The realized SPCs were evaluated from room temperature to 300°C, considerably outperforming the operating temperature range of standard commercial Peltier coolers. Temperature cycling capability was investigated from 100°C to 235°C over more than 200 h, i.e., 850 cycles, during which no degradation of module resistance or cooling performance occurred.

Oxide-confined 2D VCSEL arrays for high-density inter/intra-chip interconnects

NASA Astrophysics Data System (ADS)

King, Roger; Michalzik, Rainer; Jung, Christian; Grabherr, Martin; Eberhard, Franz; Jaeger, Roland; Schnitzer, Peter; Ebeling, Karl J.

1998-04-01

We have designed and fabricated 4 X 8 vertical-cavity surface-emitting laser (VCSEL) arrays intended to be used as transmitters in short-distance parallel optical interconnects. In order to meet the requirements of 2D, high-speed optical links, each of the 32 laser diodes is supplied with two individual top contacts. The metallization scheme allows flip-chip mounting of the array modules junction-side down on silicon complementary metal oxide semiconductor (CMOS) chips. The optical and electrical characteristics across the arrays with device pitch of 250 micrometers are quite homogeneous. Arrays with 3 micrometers , 6 micrometers and 10 micrometers active diameter lasers have been investigated. The small devices show threshold currents of 600 (mu) A, single-mode output powers as high as 3 mW and maximum wavelength deviations of only 3 nm. The driving characteristics of all arrays are fully compatible to advanced 3.3 V CMOS technology. Using these arrays, we have measured small-signal modulation bandwidths exceeding 10 GHz and transmitted pseudo random data at 8 Gbit/s channel over 500 m graded index multimode fiber. This corresponds to a data transmission rate of 256 Gbit/s per array of 1 X 2 mm2 footprint area.

Cell Patterning Chip for Controlling the Stem Cell Microenvironment

PubMed Central

Rosenthal, Adam; Macdonald, Alice; Voldman, Joel

2007-01-01

Cell-cell signaling is an important component of the stem cell microenvironment, affecting both differentiation and self-renewal. However, traditional cell-culture techniques do not provide precise control over cell-cell interactions, while existing cell patterning technologies are limited when used with proliferating or motile cells. To address these limitations, we created the Bio Flip Chip (BFC), a microfabricated polymer chip containing thousands of microwells, each sized to trap down to a single stem cell. We have demonstrated the functionality of the BFC by patterning a 50×50 grid of murine embryonic stem cells (mESCs), with patterning efficiencies > 75%, onto a variety of substrates – a cell-culture dish patterned with gelatin, a 3-D substrate, and even another layer of cells. We also used the BFC to pattern small groups of cells, with and without cell-cell contact, allowing incremental and independent control of contact-mediated signaling. We present quantitative evidence that cell-cell contact plays an important role in depressing mESC colony formation, and show that E-cadherin is involved in this negative regulatory pathway. Thus, by allowing exquisite control of the cellular microenvironment, we provide a technology that enables new applications in tissue engineering and regenerative medicine. PMID:17434582

Rapid prototyping of versatile atom chips for atom interferometry applications.

NASA Astrophysics Data System (ADS)

Kasch, Brian; Squires, Matthew; Olson, Spencer; Kroese, Bethany; Imhof, Eric; Kohn, Rudolph; Stuhl, Benjamin; Schramm, Stacy; Stickney, James

2016-05-01

We present recent advances in the manipulation of ultracold atoms with ex-vacuo atom chips (i.e. atom chips that are not inside to the UHV chamber). Details will be presented of an experimental system that allows direct bonded copper (DBC) atom chips to be removed and replaced in minutes, requiring minimal re-optimization of parameters. This system has been used to create Bose-Einstein condensates, as well as magnetic waveguides with precisely tunable axial parameters, allowing double wells, pure harmonic confinement, and modified harmonic traps. We investigate the effects of higher order magnetic field contributions to the waveguide, and the implications for confined atom interferometry.

Testing an alternate informed consent process.

PubMed

Yates, Bernice C; Dodendorf, Diane; Lane, Judy; LaFramboise, Louise; Pozehl, Bunny; Duncan, Kathleen; Knodel, Kendra

2009-01-01

One of the main problems in conducting clinical trials is low participation rate due to potential participants' misunderstanding of the rationale for the clinical trial or perceptions of loss of control over treatment decisions. The objective of this study was to test an alternate informed consent process in cardiac rehabilitation participants that involved the use of a multimedia flip chart to describe a future randomized clinical trial and then asked, hypothetically, if they would participate in the future trial. An attractive and inviting visual presentation of the study was created in the form of a 23-page flip chart that included 24 color photographs displaying information about the purpose of the study, similarities and differences between the two treatment groups, and the data collection process. We tested the flip chart in 35 cardiac rehabilitation participants. Participants were asked if they would participate in this future study on two occasions: immediately after the description of the flip chart and 24 hours later, after reading through the informed consent document. Participants were also asked their perceptions of the flip chart and consent process. Of the 35 participants surveyed, 19 (54%) indicated that they would participate in the future study. No participant changed his or her decision 24 hours later after reading the full consent form. The participation rate improved 145% over that of an earlier feasibility study where the recruitment rate was 22%. Most participants stated that the flip chart was helpful and informative and that the photographs were effective in communicating the purpose of the study. Participation rates could be enhanced in future clinical trials by using a visual presentation to explain and describe the study as part of the informed consent process. More research is needed to test alternate methods of obtaining informed consent.

Vibration characteristics of an inclined flip-flow screen panel in banana flip-flow screens

NASA Astrophysics Data System (ADS)

Xiong, Xiaoyan; Niu, Linkai; Gu, Chengxiang; Wang, Yinhua

2017-12-01

A banana flip-flow screen is an effective solution for the screening of high-viscosity, high-water and fine materials. As one of the key components, the vibration characteristics of the inclined flip-flow screen panel largely affects the screen performance and the processing capacity. In this paper, a mathematical model for the vibration characteristic of the inclined flip-flow screen panel is proposed based on Catenary theory. The reasonability of Catenary theory in analyzing the vibration characteristic of flip-flow screen panels is verified by a published experiment. Moreover, the effects of the rotation speed of exciters, the incline angle, the slack length and the characteristics of the screen on the vertical deflection, the vertical velocity and the vertical acceleration of the screen panel are investigated parametrically. The results show that the rotation speed of exciters, the incline angle, the slack length and the characteristics of the screen have significant effects on the vibrations of an inclined flip-flow screen panel, and these parameters should be optimized.

High-Efficiency Nitride-Base Photonic Crystal Light Sources

DOE Office of Scientific and Technical Information (OSTI.GOV)

James Speck; Evelyn Hu; Claude Weisbuch

2010-01-31

The research activities performed in the framework of this project represent a major breakthrough in the demonstration of Photonic Crystals (PhC) as a competitive technology for LEDs with high light extraction efficiency. The goals of the project were to explore the viable approaches to manufacturability of PhC LEDS through proven standard industrial processes, establish the limits of light extraction by various concepts of PhC LEDs, and determine the possible advantages of PhC LEDs over current and forthcoming LED extraction concepts. We have developed three very different geometries for PhC light extraction in LEDs. In addition, we have demonstrated reliable methodsmore » for their in-depth analysis allowing the extraction of important parameters such as light extraction efficiency, modal extraction length, directionality, internal and external quantum efficiency. The information gained allows better understanding of the physical processes and the effect of the design parameters on the light directionality and extraction efficiency. As a result, we produced LEDs with controllable emission directionality and a state of the art extraction efficiency that goes up to 94%. Those devices are based on embedded air-gap PhC - a novel technology concept developed in the framework of this project. They rely on a simple and planar fabrication process that is very interesting for industrial implementation due to its robustness and scalability. In fact, besides the additional patterning and regrowth steps, the process is identical as that for standard industrially used p-side-up LEDs. The final devices exhibit the same good electrical characteristics and high process yield as a series of test standard LEDs obtained in comparable conditions. Finally, the technology of embedded air-gap patterns (PhC) has significant potential in other related fields such as: increasing the optical mode interaction with the active region in semiconductor lasers; increasing the coupling of the incident light into the active region of solar cells; increasing the efficiency of the phosphorous light conversion in white light LEDs etc. In addition to the technology of embedded PhC LEDs, we demonstrate a technique for improvement of the light extraction and emission directionality for existing flip-chip microcavity (thin) LEDs by introducing PhC grating into the top n-contact. Although, the performances of these devices in terms of increase of the extraction efficiency are not significantly superior compared to those obtained by other techniques like surface roughening, the use of PhC offers some significant advantages such as improved and controllable emission directionality and a process that is directly applicable to any material system. The PhC microcavity LEDs have also potential for industrial implementation as the fabrication process has only minor differences to that already used for flip-chip thin LEDs. Finally, we have demonstrated that achieving good electrical properties and high fabrication yield for these devices is straightforward.« less

Thin hybrid pixel assembly with backside compensation layer on ROIC

NASA Astrophysics Data System (ADS)

Bates, R.; Buttar, C.; McMullen, T.; Cunningham, L.; Ashby, J.; Doherty, F.; Gray, C.; Pares, G.; Vignoud, L.; Kholti, B.; Vahanen, S.

2017-01-01

The entire ATLAS inner tracking system will be replaced for operation at the HL-LHC . This will include a significantly larger pixel detector of approximately 15 m2. For this project, it is critical to reduce the mass of the hybrid pixel modules and this requires thinning both the sensor and readout chips to about 150 micrometres each. The thinning of the silicon chips leads to low bump yield for SnAg bumps due to bad co-planarity of the two chips at the solder reflow stage creating dead zones within the pixel array. In the case of the ATLAS FEI4 pixel readout chip thinned to 100 micrometres, the chip is concave, with the front side in compression, with a bow of +100 micrometres at room temperature which varies to a bow of -175 micrometres at the SnAg solder reflow temperature, caused by the CTE mismatch between the materials in the CMOS stack and the silicon substrate. A new wafer level process to address the issue of low bump yield be controlling the chip bow has been developed. A back-side dielectric and metal stack of SiN and Al:Si has been deposited on the readout chip wafer to dynamically compensate the stress of the front side stack. In keeping with a 3D process the materials used are compatible with Through Silicon Via (TSV) technology with a TSV last approach which is under development for this chip. It is demonstrated that the amplitude of the correction can be manipulated by the deposition conditions and thickness of the SiN/Al:Si stack. The bow magnitude over the temperature range for the best sample to date is reduced by almost a factor of 4 and the sign of the bow (shape of the die) remains constant. Further development of the backside deposition conditions is on-going with the target of close to zero bow at the solder reflow temperature and a minimal bow magnitude throughout the temperature range. Assemblies produced from FEI4 readout wafers thinned to 100 micrometres with the backside compensation layer have been made for the first time and demonstrate bond yields close to 100%.

Simulation of finite-strain inelastic phenomena governed by creep and plasticity

NASA Astrophysics Data System (ADS)

Li, Zhen; Bloomfield, Max O.; Oberai, Assad A.

2017-11-01

Inelastic mechanical behavior plays an important role in many applications in science and engineering. Phenomenologically, this behavior is often modeled as plasticity or creep. Plasticity is used to represent the rate-independent component of inelastic deformation and creep is used to represent the rate-dependent component. In several applications, especially those at elevated temperatures and stresses, these processes occur simultaneously. In order to model these process, we develop a rate-objective, finite-deformation constitutive model for plasticity and creep. The plastic component of this model is based on rate-independent J_2 plasticity, and the creep component is based on a thermally activated Norton model. We describe the implementation of this model within a finite element formulation, and present a radial return mapping algorithm for it. This approach reduces the additional complexity of modeling plasticity and creep, over thermoelasticity, to just solving one nonlinear scalar equation at each quadrature point. We implement this algorithm within a multiphysics finite element code and evaluate the consistent tangent through automatic differentiation. We verify and validate the implementation, apply it to modeling the evolution of stresses in the flip chip manufacturing process, and test its parallel strong-scaling performance.

Hyperthermia enhances mapatumumab-induced apoptotic death through ubiquitin-mediated degradation of cellular FLIP(long) in human colon cancer cells.

PubMed

Song, X; Kim, S-Y; Zhou, Z; Lagasse, E; Kwon, Y T; Lee, Y J

2013-04-04

Colorectal cancer is the third leading cause of cancer-related mortality in the world; the main cause of death of colorectal cancer is hepatic metastases, which can be treated with hyperthermia using isolated hepatic perfusion (IHP). In this study, we report that mild hyperthermia potently reduced cellular FLIP(long), (c-FLIP(L)), a major regulator of the death receptor (DR) pathway of apoptosis, thereby enhancing humanized anti-DR4 antibody mapatumumab (Mapa)-mediated mitochondria-independent apoptosis. We observed that overexpression of c-FLIP(L) in CX-1 cells abrogated the synergistic effect of Mapa and hyperthermia, whereas silencing of c-FLIP in CX-1 cells enhanced Mapa-induced apoptosis. Hyperthermia altered c-FLIP(L) protein stability without concomitant reductions in FLIP mRNA. Ubiquitination of c-FLIP(L) was increased by hyperthermia, and proteasome inhibitor MG132 prevented heat-induced downregulation of c-FLIP(L). These results suggest the involvement of the ubiquitin-proteasome system in this process. We also found lysine residue 195 (K195) to be essential for c-FLIP(L) ubiquitination and proteolysis, as mutant c-FLIP(L) lysine 195 arginine (arginine replacing lysine) was left virtually un-ubiquitinated and was refractory to hyperthermia-triggered degradation, and thus partially blocked the synergistic effect of Mapa and hyperthermia. Our observations reveal that hyperthermia transiently reduced c-FLIP(L) by proteolysis linked to K195 ubiquitination, which contributed to the synergistic effect between Mapa and hyperthermia. This study supports the application of hyperthermia combined with other regimens to treat colorectal hepatic metastases.

Flexible Chip Scale Package and Interconnect for Implantable MEMS Movable Microelectrodes for the Brain.

PubMed

Jackson, Nathan; Muthuswamy, Jit

2009-04-01

We report here a novel approach called MEMS microflex interconnect (MMFI) technology for packaging a new generation of Bio-MEMS devices that involve movable microelectrodes implanted in brain tissue. MMFI addresses the need for (i) operating space for movable parts and (ii) flexible interconnects for mechanical isolation. We fabricated a thin polyimide substrate with embedded bond-pads, vias, and conducting traces for the interconnect with a backside dry etch, so that the flexible substrate can act as a thin-film cap for the MEMS package. A double gold stud bump rivet bonding mechanism was used to form electrical connections to the chip and also to provide a spacing of approximately 15-20 µm for the movable parts. The MMFI approach achieved a chip scale package (CSP) that is lightweight, biocompatible, having flexible interconnects, without an underfill. Reliability tests demonstrated minimal increases of 0.35 mΩ, 0.23 mΩ and 0.15 mΩ in mean contact resistances under high humidity, thermal cycling, and thermal shock conditions respectively. High temperature tests resulted in an increase in resistance of > 90 mΩ when aluminum bond pads were used, but an increase of ~ 4.2 mΩ with gold bond pads. The mean-time-to-failure (MTTF) was estimated to be at least one year under physiological conditions. We conclude that MMFI technology is a feasible and reliable approach for packaging and interconnecting Bio-MEMS devices.

Neural Implants, Packaging for Biocompatible Implants, and Improving Fabricated Capacitors

NASA Astrophysics Data System (ADS)

Agger, Elizabeth Rose

We have completed the circuit design and packaging procedure for an NIH-funded neural implant, called a MOTE (Microscale Optoelectronically Transduced Electrode). Neural recording implants for mice have greatly advanced neuroscience, but they are often damaging and limited in their recording location. This project will result in free-floating implants that cause less damage, provide rapid electronic recording, and increase range of recording across the cortex. A low-power silicon IC containing amplification and digitization sub-circuits is powered by a dual-function gallium arsenide photovoltaic and LED. Through thin film deposition, photolithography, and chemical and physical etching, the Molnar Group and the McEuen Group (Applied and Engineering Physics department) will package the IC and LED into a biocompatible implant approximately 100microm3. The IC and LED are complete and we have begun refining this packaging procedure in the Cornell NanoScale Science & Technology Facility. ICs with 3D time-resolved imaging capabilities can image microorganisms and other biological samples given proper packaging. A portable, flat, easily manufactured package would enable scientists to place biological samples on slides directly above the Molnar group's imaging chip. We have developed a packaging procedure using laser cutting, photolithography, epoxies, and metal deposition. Using a flip-chip method, we verified the process by aligning and adhering a sample chip to a holder wafer. In the CNF, we have worked on a long-term metal-insulator-metal (MIM) capacitor characterization project. Former Fellow and continuing CNF user Kwame Amponsah developed the original procedure for the capacitor fabrication, and another former fellow, Jonilyn Longenecker, revised the procedure and began the arduous process of characterization. MIM caps are useful to clean room users as testing devices to verify electronic characteristics of their active circuitry. This project's objective is to determine differences in current-voltage (IV) and capacitor-voltage (CV) relationships across variations in capacitor size and dielectric type. This effort requires an approximately 20-step process repeated for two-to-six varieties (dependent on temperature and thermal versus plasma options) of the following dielectrics: HfO2, SiO2, Al2O3, TaOx, and TiO2.

Short form FLICE-inhibitory protein promotes TNFα-induced necroptosis in fibroblasts derived from CFLARs transgenic mice.

PubMed

Shindo, Ryodai; Yamazaki, Soh; Ohmuraya, Masaki; Araki, Kimi; Nakano, Hiroyasu

2016-11-04

Cellular FLICE-inhibitory protein (cFLIP) is a catalytically inactive homolog of the initiator caspase, caspase 8 and blocks apoptosis through binding to caspase 8. Human CFLAR gene encodes two proteins, a long form cFLIP (cFLIP L ) and a short form cFLIP (cFLIPs) due to an alternative splicing. Recent studies have shown that expression of cFLIPs, but not cFLIP L promotes programmed necrosis (also referred to as necroptosis) in an immortalized human keratinocyte cell line, HaCaT. Here, we found that expression of cFLIPs similarly promoted necroptosis in immortalized fibroblasts. To further expand this observation and exclude the possibility that immortalization process of keratinocytes or fibroblasts might affect the phenotype induced by cFLIPs expression, we generated human CFLARs transgenic (Tg) mice. Primary fibroblasts derived from CFLARs Tg mice were increased in susceptibility to TNFα-induced necroptosis, but not apoptosis compared to wild-type (WT) fibroblasts. Moreover, hallmarks of necroptosis, such as phosphorylation of receptor-interacting protein kinase (RIPK)1 and RIPK3, and oligomer formation of mixed lineage kinase domain-like (MLKL) were robustly induced in CFLARs Tg fibroblasts compared to wild-type fibroblasts following TNFα stimulation. Thus, cFLIPs-dependent promotion of necroptosis is not unique to immortalized keratinocytes or fibroblasts, but also to generalized to primary fibroblasts. Copyright © 2016 Elsevier Inc. All rights reserved.

Detection of acrylamide in potato chips using a fluorescent sensing method based on acrylamide polymerization-induced distance increase between quantum dots.

PubMed

Hu, Qinqin; Xu, Xiahong; Li, Zhanming; Zhang, Ying; Wang, Jianping; Fu, Yingchun; Li, Yanbin

2014-04-15

Acrylamide is a neurotoxin and potential carcinogen, but is found in various thermally processed foods such as potato chips, biscuits, and coffee. Simple and sensitive methods for on-line detection of acrylamide are needed to ensure food safety. In this paper, a novel fluorescent sensing method based on acrylamide polymerization-induced distance increase between quantum dots (QDs) was proposed for detecting acrylamide in potato chips. The functional QDs were prepared by their binding with N-acryloxysuccinimide (NAS), which was characterized by Fourier transform infrared (FR-IR) spectra. The carbon-carbon double bonds of NAS modified QDs polymerized with assistance of photo initiator under UV irradiation, leading to QDs getting closer along with fluorescence intensity decreasing. Acrylamide in the sample participated in the polymerization and induced an increase of fluorescence intensity. This method possessed a linear range from 3.5×10(-5) to 3.5 g L(-1) (r(2)=0.94) and a limit of detection of 3.5×10(-5) g L(-1). Although the sensitivity and specificity cannot be compared with standard LC-MS/MS analysis, this new method requires much less time and cost, which is promising for on-line rapid detection of acrylamide in food processing. © 2013 Published by Elsevier B.V.

Students' Perceptions and Emotions toward Learning in a Flipped General Science Classroom

ERIC Educational Resources Information Center

Jeong, Jin Su; González-Gómez, David; Cañada-Cañada, Florentina

2016-01-01

Recently, the inverted instruction methodologies are gaining attentions in higher educations by claiming that flipping the classroom engages more effectively students with the learning process. Besides, students' perceptions and emotions involved in their learning process must be assessed in order to gauge the usability of this relatively new…

‘Chip-olate’ and dry-film resists for efficient fabrication, singulation and sealing of microfluidic chips

NASA Astrophysics Data System (ADS)

Temiz, Yuksel; Delamarche, Emmanuel

2014-09-01

This paper describes a technique for high-throughput fabrication and efficient singulation of chips having closed microfluidic structures and takes advantage of dry-film resists (DFRs) for efficient sealing of capillary systems. The technique is illustrated using 4-inch Si/SiO2 wafers. Wafers carrying open microfluidic structures are partially diced to about half of their thickness. Treatments such as surface cleaning are done at wafer-level, then the structures are sealed using low-temperature (45 °C) lamination of a DFR that is pre-patterned using a craft cutter, and ready-to-use chips are finally separated manually like a chocolate bar by applying a small force (≤ 4 N). We further show that some DFRs have low auto-fluorescence at wavelengths typically used for common fluorescent dyes and that mechanical properties of some DFRs allow for the lamination of 200 μm wide microfluidic structures with negligible sagging (~1 μm). The hydrophilicity (advancing contact angle of ~60°) of the DFR supports autonomous capillary-driven flow without the need for additional surface treatment of the microfluidic chips. Flow rates from 1 to 5 µL min-1 are generated using different geometries of channels and capillary pumps. In addition, the ‘chip-olate’ technique is compatible with the patterning of capture antibodies on DFR for use in immunoassays. We believe this technique to be applicable to the fabrication of a wide range of microfluidic and lab-on-a-chip devices and to offer a viable alternative to many labor-intensive processes that are currently based on wafer bonding techniques or on the molding of poly(dimethylsiloxane) (PDMS) layers.

Integrated optical transceiver with electronically controlled optical beamsteering

DOE Office of Scientific and Technical Information (OSTI.GOV)

Davids, Paul; DeRose, Christopher; Tauke-Pedretti, Anna

A beam-steering optical transceiver is provided. The transceiver includes one or more modules, each comprising an antenna chip and a control chip bonded to the antenna chip. Each antenna chip has a feeder waveguide, a plurality of row waveguides that tap off from the feeder waveguide, and a plurality of metallic nanoantenna elements arranged in a two-dimensional array of rows and columns such that each row overlies one of the row waveguides. Each antenna chip also includes a plurality of independently addressable thermo-optical phase shifters, each configured to produce a thermo-optical phase shift in a respective row. Each antenna chipmore » also has, for each row, a row-wise heating circuit configured to produce a respective thermo-optic phase shift at each nanoantenna element along its row. The control chip includes controllable current sources for the independently addressable thermo-optical phase shifters and the row-wise heating circuits.« less

Fabrication of polydimethylsiloxane (PDMS) nanofluidic chips with controllable channel size and spacing.

PubMed

Peng, Ran; Li, Dongqing

2016-10-07

The ability to create reproducible and inexpensive nanofluidic chips is essential to the fundamental research and applications of nanofluidics. This paper presents a novel and cost-effective method for fabricating a single nanochannel or multiple nanochannels in PDMS chips with controllable channel size and spacing. Single nanocracks or nanocrack arrays, positioned by artificial defects, are first generated on a polystyrene surface with controllable size and spacing by a solvent-induced method. Two sets of optimal working parameters are developed to replicate the nanocracks onto the polymer layers to form the nanochannel molds. The nanochannel molds are used to make the bi-layer PDMS microchannel-nanochannel chips by simple soft lithography. An alignment system is developed for bonding the nanofluidic chips under an optical microscope. Using this method, high quality PDMS nanofluidic chips with a single nanochannel or multiple nanochannels of sub-100 nm width and height and centimeter length can be obtained with high repeatability.

Demonstration of glass-based photonic interposer for mid-board-optical engines and electrical-optical circuit board (EOCB) integration strategy

NASA Astrophysics Data System (ADS)

Schröder, H.; Neitz, M.; Schneider-Ramelow, M.

2018-02-01

Due to its optical transparency and superior dielectric properties glass is regarded as a promising candidate for advanced applications as active photonic interposer for mid-board-optics and optical PCB waveguide integration. The concepts for multi-mode and single-mode photonic system integration are discussed and related demonstration project results will be presented. A hybrid integrated photonic glass body interposer with integrated optical lenses for multi-mode data communication wavelength of 850 nm have been realized. The paper summarizes process developments which allow cost efficient metallization of TGV. Electro-optical elements like photodiodes and VCSELs can be directly flip-chip mounted on the glass substrate according to the desired lens positions. Furthermore results for a silicon photonic based single-mode active interposer integration onto a single mode glass made EOCB will be compared in terms of packaging challenges. The board level integration strategy for both of these technological approaches and general next generation board level integration concepts for photonic interposer will be introductorily discussed.

Using drugs to target necroptosis: dual roles in disease therapy.

PubMed

Wang, Zhen; Guo, Li-Min; Zhou, Hong-Kang; Qu, Hong-Ke; Wang, Shu-Chao; Liu, Feng-Xia; Chen, Dan; Huang, Ju-Fang; Xiong, Kun

2018-02-01

Necroptosis is programmed necrosis, a process which has been studied for over a decade. The most common accepted mechanism is through the RIP1-RIP3-MLKL axis to regulate necroptotic cell death. As a result of previous studies on necroptosis, positive regulation for promoting necroptosis such as HSP90 stabilization and hyperactivation of TAK1 on RIP1 is clear. Similarly, the negative regulation of necroptosis, such as through caspase 8, c-FLIP, CHIP, MK2, PELI1, ABIN-1, is also clear. Therefore, the promise of corresponding applications in treating diseases becomes hopeful. Studies have shown that necroptosis is involved in the development of many diseases, such as ischemic injury diseases in various organs, neurodegenerative diseases, infectious diseases, and cancer. Given these results, drugs that inhibit or trigger necroptosis can be discovered to treat diseases. In this review, we briefly introduce up to date concepts concerning the mechanism of necroptosis, the diseases that involve necroptosis, and the drugs that can be applied to treat such diseases.

Reliability and Qualification of Hardware to Enhance the Mission Assurance of JPL/NASA Projects

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni

2010-01-01

Packaging Qualification and Verification (PQV) and life testing of advanced electronic packaging, mechanical assemblies (motors/actuators), and interconnect technologies (flip-chip), platinum temperature thermometer attachment processes, and various other types of hardware for Mars Exploration Rover (MER)/Mars Science Laboratory (MSL), and JUNO flight projects was performed to enhance the mission assurance. The qualification of hardware under extreme cold to hot temperatures was performed with reference to various project requirements. The flight like packages, assemblies, test coupons, and subassemblies were selected for the study to survive three times the total number of expected temperature cycles resulting from all environmental and operational exposures occurring over the life of the flight hardware including all relevant manufacturing, ground operations, and mission phases. Qualification/life testing was performed by subjecting flight-like qualification hardware to the environmental temperature extremes and assessing any structural failures, mechanical failures or degradation in electrical performance due to either overstress or thermal cycle fatigue. Experimental flight qualification test results will be described in this presentation.

Separation of superparamagnetic particles through ratcheted Brownian motion and periodically switching magnetic fields.

PubMed

Liu, Fan; Jiang, Li; Tan, Huei Ming; Yadav, Ashutosh; Biswas, Preetika; van der Maarel, Johan R C; Nijhuis, Christian A; van Kan, Jeroen A

2016-11-01

Brownian ratchet based particle separation systems for application in lab on chip devices have drawn interest and are subject to ongoing theoretical and experimental investigations. We demonstrate a compact microfluidic particle separation chip, which implements an extended on-off Brownian ratchet scheme that actively separates and sorts particles using periodically switching magnetic fields, asymmetric sawtooth channel sidewalls, and Brownian motion. The microfluidic chip was made with Polydimethylsiloxane (PDMS) soft lithography of SU-8 molds, which in turn was fabricated using Proton Beam Writing. After bonding of the PDMS chip to a glass substrate through surface activation by oxygen plasma treatment, embedded electromagnets were cofabricated by the injection of InSn metal into electrode channels. This fabrication process enables rapid production of high resolution and high aspect ratio features, which results in parallel electrodes accurately aligned with respect to the separation channel. The PDMS devices were tested with mixtures of 1.51  μ m, 2.47  μ m, and 2.60  μ m superparamagnetic particles suspended in water. Experimental results show that the current device design has potential for separating particles with a size difference around 130 nm. Based on the promising results, we will be working towards extending this design for the separation of cells or biomolecules.

Separation of superparamagnetic particles through ratcheted Brownian motion and periodically switching magnetic fields

PubMed Central

Liu, Fan; Jiang, Li; Tan, Huei Ming; Yadav, Ashutosh; Biswas, Preetika; van der Maarel, Johan R. C.; Nijhuis, Christian A.; van Kan, Jeroen A.

2016-01-01

Brownian ratchet based particle separation systems for application in lab on chip devices have drawn interest and are subject to ongoing theoretical and experimental investigations. We demonstrate a compact microfluidic particle separation chip, which implements an extended on-off Brownian ratchet scheme that actively separates and sorts particles using periodically switching magnetic fields, asymmetric sawtooth channel sidewalls, and Brownian motion. The microfluidic chip was made with Polydimethylsiloxane (PDMS) soft lithography of SU-8 molds, which in turn was fabricated using Proton Beam Writing. After bonding of the PDMS chip to a glass substrate through surface activation by oxygen plasma treatment, embedded electromagnets were cofabricated by the injection of InSn metal into electrode channels. This fabrication process enables rapid production of high resolution and high aspect ratio features, which results in parallel electrodes accurately aligned with respect to the separation channel. The PDMS devices were tested with mixtures of 1.51 μm, 2.47 μm, and 2.60 μm superparamagnetic particles suspended in water. Experimental results show that the current device design has potential for separating particles with a size difference around 130 nm. Based on the promising results, we will be working towards extending this design for the separation of cells or biomolecules. PMID:27917252

The Image Understanding Architecture Project

DTIC Science & Technology

1988-04-01

The error resulted in the frame being reduced in size and incorrectly bonded . The problem has been corrected and3 the design has been re-submitted...Promotional literature, Beaverton, OR, 1985. Nii, 1986] Nil, H.P., The Blackboard Model of Problem Solving and the Evolution of Blackboard...microns. This resulted in a reduction in pad sizes to two thirds of the minimum required for safe bonding . All chips had many wire bonds on the die

Prototyping of Silicon Strip Detectors for the Inner Tracker of the ALICE Experiment

NASA Astrophysics Data System (ADS)

Sokolov, Oleksiy

2006-04-01

The ALICE experiment at CERN will study heavy ion collisions at a center-of-mass energy 5.5˜TeV per nucleon. Particle tracking around the interaction region at radii r<45 cm is done by the Inner Tracking System (ITS), consisting of six cylindrical layers of silicon detectors. The outer two layers of the ITS use double-sided silicon strip detectors. This thesis focuses on testing of these detectors and performance studies of the detector module prototypes at the beam test. Silicon strip detector layers will require about 20 thousand HAL25 front-end readout chips and about 3.5 thousand hybrids each containing 6 HAL25 chips. During the assembly procedure, chips are bonded on a patterned TAB aluminium microcables which connect to all the chip input and output pads, and then the chips are assembled on the hybrids. Bonding failures at the chip or hybrid level may either render the component non-functional or deteriorate its the performance such that it can not be used for the module production. After each bonding operation, the component testing is done to reject the non-functional or poorly performing chips and hybrids. The LabView-controlled test station for this operation has been built at Utrecht University and was successfully used for mass production acceptance tests of chips and hybrids at three production labs. The functionality of the chip registers, bonding quality and analogue functionality of the chips and hybrids are addressed in the test. The test routines were optimized to minimize the testing time to make sure that testing is not a bottleneck of the mass production. For testing of complete modules the laser scanning station with 1060 nm diode laser has been assembled at Utrecht University. The testing method relies of the fact that a response of the detector module to a short collimated laser beam pulse resembles a response to a minimum ionizing particle. A small beam spot size (˜7 μm ) allows to deposit the charge in a narrow region and measure the response of individual detector channels. First several module prototypes have been studied with this setup, the strip gain and charge sharing function have been measured, the later is compared with the model predictions. It was also shown that for a laser beam of a high monochromaticity, interference in the sensor bulk significantly modulates the deposited charge and introduces a systematic error of the gain measurement. Signatures of disconnected strips and pinholes defects have been observed, the response of the disconnected strips to the laser beam has been correlated with the noise measurements. Beam test of four prototype modules have been carried out at PS accelerator at CERN using 7 GeV/c pions. It was demonstrated that the modules provide an excellent signal-to-noise ratio in the range 40-75. The estimated spatial resolution for the normally incident tracks is about 18 μm using the center-of-gravity cluster reconstruction method. A non-iterative method for spatial resolution determination was developed, it was shown that in order to determine the resolution of each individual detector in the telescope, the telescope should consist of at least 5 detectors. The detectors showed high detection efficiency, in the order 99%. It was shown that the particle loss occurs mostly in the defected regions near the noisy strips or strips with a very low gain. The efficiency of the sensor area with nominal characteristics is consistent with 100%.

The Effects of a Flipped Classroom Model of Instruction on Students' Performance and Attitudes Towards Chemistry

NASA Astrophysics Data System (ADS)

Olakanmi, Eunice Eyitayo

2017-02-01

This study establishes the effects of a flipped classroom model of instruction on academic performance and attitudes of 66 first-year secondary school students towards chemistry. A pre-test and post-test experimental design was employed to assign students randomly into either the experimental or control group. In order to assess the suitability of using flipped model of instruction, students were divided in two groups. For the first group called the experimental group, a "flipped classroom" was used in which the students were given video lessons and reading materials, before the class to be revised at home. On the other hand, the second group followed traditional methodology, and it was used as control. The rate of reaction knowledge test and the chemistry attitude scale were administered. In addition, the researcher documented classroom observations, experiences, thoughts and insights regarding the intervention in a journal on a daily basis in order to enrich the data. Students were interviewed at the end of the research in order to enrich the qualitative data also. Findings from this study reveal that the flipped instruction model facilitates a shift in students' conceptual understanding of the rate of chemical reaction significantly more than the control condition. Positive significant differences were found on all assessments with the flipped class students performing higher on average. Students in the flipped classroom model condition benefited by preparing for the lesson before the classes and had the opportunity to interact with peers and the teacher during the learning processes in the classroom. The findings support the notion that teachers should be trained or retrained on how to incorporate the flipped classroom model into their teaching and learning processes because it encourages students to be directly involved and active in the learning.

Study and practice of flipped classroom in optoelectronic technology curriculum

NASA Astrophysics Data System (ADS)

Shi, Jianhua; Lei, Bing; Liu, Wei; Yao, Tianfu; Jiang, Wenjie

2017-08-01

"Flipped Classroom" is one of the most popular teaching models, and has been applied in more and more curriculums. It is totally different from the traditional teaching model. In the "Flipped Classroom" model, the students should watch the teaching video afterschool, and in the classroom only the discussion is proceeded to improve the students' comprehension. In this presentation, "Flipped Classroom" was studied and practiced in opto-electronic technology curriculum; its effect was analyzed by comparing it with the traditional teaching model. Based on extensive and deep investigation, the phylogeny, the characters and the important processes of "Flipped Classroom" are studied. The differences between the "Flipped Classroom" and the traditional teaching model are demonstrated. Then "Flipped Classroom" was practiced in opto-electronic technology curriculum. In order to obtain high effectiveness, a lot of teaching resources were prepared, such as the high-quality teaching video, the animations and the virtual experiments, the questions that the students should finish before and discussed in the class, etc. At last, the teaching effect was evaluated through analyzing the result of the examination and the students' surveys.

Marvels of enzyme catalysis at true atomic resolution: distortions, bond elongations, hidden flips, protonation states and atom identities.

PubMed

Neumann, Piotr; Tittmann, Kai

2014-12-01

Although general principles of enzyme catalysis are fairly well understood nowadays, many important details of how exactly the substrate is bound and processed in an enzyme remain often invisible and as such elusive. In fortunate cases, structural analysis of enzymes can be accomplished at true atomic resolution thus making possible to shed light on otherwise concealed fine-structural traits of bound substrates, intermediates, cofactors and protein groups. We highlight recent structural studies of enzymes using ultrahigh-resolution X-ray protein crystallography showcasing its enormous potential as a tool in the elucidation of enzymatic mechanisms and in unveiling fundamental principles of enzyme catalysis. We discuss the observation of seemingly hyper-reactive, physically distorted cofactors and intermediates with elongated scissile substrate bonds, the detection of 'hidden' conformational and chemical equilibria and the analysis of protonation states with surprising findings. In delicate cases, atomic resolution is required to unambiguously disclose the identity of atoms as demonstrated for the metal cluster in nitrogenase. In addition to the pivotal structural findings and the implications for our understanding of enzyme catalysis, we further provide a practical framework for resolution enhancement through optimized data acquisition and processing. Copyright © 2014 Elsevier Ltd. All rights reserved.

Step to improve neural cryptography against flipping attacks.

PubMed

Zhou, Jiantao; Xu, Qinzhen; Pei, Wenjiang; He, Zhenya; Szu, Harold

2004-12-01

Synchronization of neural networks by mutual learning has been demonstrated to be possible for constructing key exchange protocol over public channel. However, the neural cryptography schemes presented so far are not the securest under regular flipping attack (RFA) and are completely insecure under majority flipping attack (MFA). We propose a scheme by splitting the mutual information and the training process to improve the security of neural cryptosystem against flipping attacks. Both analytical and simulation results show that the success probability of RFA on the proposed scheme can be decreased to the level of brute force attack (BFA) and the success probability of MFA still decays exponentially with the weights' level L. The synchronization time of the parties also remains polynomial with L. Moreover, we analyze the security under an advanced flipping attack.

New results on diamond pixel sensors using ATLAS frontend electronics

NASA Astrophysics Data System (ADS)

Keil, M.; Adam, W.; Berdermann, E.; Bergonzo, P.; de Boer, W.; Bogani, F.; Borchi, E.; Brambilla, A.; Bruzzi, M.; Colledani, C.; Conway, J.; D'Angelo, P.; Dabrowski, W.; Delpierre, P.; Dulinski, W.; Doroshenko, J.; Doucet, M.; van Eijk, B.; Fallou, A.; Fischer, P.; Fizzotti, F.; Kania, D.; Gan, K. K.; Grigoriev, E.; Hallewell, G.; Han, S.; Hartjes, F.; Hrubec, J.; Husson, D.; Kagan, H.; Kaplon, J.; Kass, R.; Knöpfle, K. T.; Koeth, T.; Krammer, M.; Logiudice, A.; mac Lynne, L.; Manfredotti, C.; Meier, D.; Menichelli, D.; Meuser, S.; Mishina, M.; Moroni, L.; Noomen, J.; Oh, A.; Pan, L. S.; Pernicka, M.; Perera, L.; Riester, J. L.; Roe, S.; Rudge, A.; Russ, J.; Sala, S.; Sampietro, M.; Schnetzer, S.; Sciortino, S.; Stelzer, H.; Stone, R.; Suter, B.; Trischuk, W.; Tromson, D.; Vittone, E.; Weilhammer, P.; Wermes, N.; Wetstein, M.; Zeuner, W.; Zoeller, M.

2003-03-01

Diamond is a promising sensor material for future collider experiments due to its radiation hardness. Diamond pixel sensors have been bump bonded to an ATLAS pixel readout chip using PbSn solder bumps. Single chip devices have been characterised by lab measurements and in a high-energy pion beam at CERN. Results on charge collection, spatial resolution, efficiency and the charge carrier lifetime are presented.

Method of developing all-optical trinary JK, D-type, and T-type flip-flops using semiconductor optical amplifiers.

PubMed

Garai, Sisir Kumar

2012-04-10

To meet the demand of very fast and agile optical networks, the optical processors in a network system should have a very fast execution rate, large information handling, and large information storage capacities. Multivalued logic operations and multistate optical flip-flops are the basic building blocks for such fast running optical computing and data processing systems. In the past two decades, many methods of implementing all-optical flip-flops have been proposed. Most of these suffer from speed limitations because of the low switching response of active devices. The frequency encoding technique has been used because of its many advantages. It can preserve its identity throughout data communication irrespective of loss of light energy due to reflection, refraction, attenuation, etc. The action of polarization-rotation-based very fast switching of semiconductor optical amplifiers increases processing speed. At the same time, tristate optical flip-flops increase information handling capacity.

Contamination control in hybrid microelectronic modules. Part 3: Specifications for coating material and process controls

NASA Technical Reports Server (NTRS)

Himmel, R. P.

1975-01-01

Resin systems for coating hybrids prior to hermetic sealing are described. The resin systems are a flexible silicone junction resin system and a flexible cycloaliphatic epoxy resin system. The coatings are intended for application to the hybrid after all the chips have been assembled and wire bonded, but prior to hermetic sealing of the package. The purpose of the coating is to control particulate contamination by immobilizing particles and by passivating the hybrid. Recommended process controls for the purpose of minimizing contamination in hybrid microcircuit packages are given. Emphasis is placed on those critical hybrid processing steps in which contamination is most likely to occur.

Grinding damage assessment for CAD-CAM restorative materials.

PubMed

Curran, Philippe; Cattani-Lorente, Maria; Anselm Wiskott, H W; Durual, Stéphane; Scherrer, Susanne S

2017-03-01

To assess surface/subsurface damage after grinding with diamond discs on five CAD-CAM restorative materials and to estimate potential losses in strength based on crack size measurements of the generated damage. The materials tested were: Lithium disilicate (LIT) glass-ceramic (e.max CAD), leucite glass-ceramic (LEU) (Empress CAD), feldspar ceramic (VM2) (Vita Mark II), feldspar ceramic-resin infiltrated (EN) (Enamic) and a composite reinforced with nano ceramics (LU) (Lava Ultimate). Specimens were cut from CAD-CAM blocs and pair-wise mirror polished for the bonded interface technique. Top surfaces were ground with diamond discs of respectively 75, 54 and 18μm. Chip damage was measured on the bonded interface using SEM. Fracture mechanics relationships were used to estimate fracture stresses based on average and maximum chip depths assuming these to represent strength limiting flaws subjected to tension and to calculate potential losses in strength compared to manufacturer's data. Grinding with a 75μm diamond disc induced on a bonded interface critical chips averaging 100μm with a potential strength loss estimated between 33% and 54% for all three glass-ceramics (LIT, LEU, VM2). The softer materials EN and LU were little damage susceptible with chips averaging respectively 26μm and 17μm with no loss in strength. Grinding with 18μm diamond discs was still quite detrimental for LIT with average chip sizes of 43μm and a potential strength loss of 42%. It is essential to understand that when grinding glass-ceramics or feldspar ceramics with diamond discs surface and subsurface damage are induced which have the potential of lowering the strength of the ceramic. Careful polishing steps should be carried out after grinding especially when dealing with glass-ceramics. Copyright © 2017 The Academy of Dental Materials. Published by Elsevier Ltd. All rights reserved.

Wide-band (2.5 - 10.5 µm), high-frame rate IRFPAs based on high-operability MCT on silicon

NASA Astrophysics Data System (ADS)

Crosbie, Michael J.; Giess, Jean; Gordon, Neil T.; Hall, David J.; Hails, Janet E.; Lees, David J.; Little, Christopher J.; Phillips, Tim S.

2010-04-01

We have previously presented results from our mercury cadmium telluride (MCT, Hg1-xCdxTe) growth on silicon substrate technology for different applications, including negative luminescence, long waveband and mid/long dual waveband infrared imaging. In this paper, we review recent developments in QinetiQ's combined molecular beam epitaxy (MBE) and metal-organic vapor phase epitaxy (MOVPE) MCT growth on silicon; including MCT defect density, uniformity and reproducibility. We also present a new small-format (128 x 128) focal plane array (FPA) for high frame-rate applications. A custom high-speed readout integrated circuit (ROIC) was developed with a large pitch and large charge storage aimed at producing a very high performance FPA (NETD ~10mK) operating at frame rates up to 2kHz for the full array. The array design allows random addressing and this allows the maximum frame rate to be increased as the window size is reduced. A broadband (2.5-10.5 μm) MCT heterostructure was designed and grown by the MBE/MOVPE technique onto silicon substrates. FPAs were fabricated using our standard techniques; wet-etched mesa diodes passivated with epitaxial CdTe and flip-chip bonded to the ROIC. The resulting focal plane arrays were characterized at the maximum frame rate and shown to have the high operabilities and low NETD values characteristic of our LWIR MCT on silicon technology.

Characterisation of Redlen high-flux CdZnTe

NASA Astrophysics Data System (ADS)

Thomas, B.; Veale, M. C.; Wilson, M. D.; Seller, P.; Schneider, A.; Iniewski, K.

2017-12-01

CdZnTe is a promising material for the current generation of free electron laser light sources and future laser-driven γ-ray sources which require detectors capable of high flux imaging at X-ray and γ-ray energies (> 10 keV) . However, at high fluxes CdZnTe has been shown to polarise due to hole trapping, leading to poor performance. Novel Redlen CdZnTe material with improved hole transport properties has been designed for high flux applications. Small pixel CdZnTe detectors were fabricated by Redlen Technologies and flip-chip bonded to PIXIE ASICs. An XIA Digital Gamma Finder PIXIE-16 system was used to digitise each of the nine analogue signals with a timing resolution of 10 ns. Pulse shape analysis was used to extract the rise times and amplitude of signals. These were measured as a function of applied bias voltage and used to calculate the mobility (μ) and mobility-lifetime (μτ) of electrons and holes in the material for three identical detectors. The measured values of the transport properties of electrons in the high-flux-capable material was lower than previously reported for Redlen CdZnTe material (μeτe ~ 1 × 10-3 cm2V-1 and μe ~ 1000 cm2V-1s-1) while the hole transport properties were found to have improved (μhτh ~ 3 × 10-4 cm2V-1 and μh ~ 100 cm2V-1s-1).

Advancing MEMS Technology Usage through the MUMPS (Multi-User MEMS Processes) Program

NASA Technical Reports Server (NTRS)

Koester, D. A.; Markus, K. W.; Dhuler, V.; Mahadevan, R.; Cowen, A.

1995-01-01

In order to help provide access to advanced micro-electro-mechanical systems (MEMS) technologies and lower the barriers for both industry and academia, the Microelectronic Center of North Carolina (MCNC) and ARPA have developed a program which provides users with access to both MEMS processes and advanced electronic integration techniques. The four distinct aspects of this program, the multi-user MEMS processes (MUMP's), the consolidated micro-mechanical element library, smart MEMS, and the MEMS technology network are described in this paper. MUMP's is an ARPA-supported program created to provide inexpensive access to MEMS technology in a multi-user environment. It is both a proof-of-concept and educational tool that aids in the development of MEMS in the domestic community. MUMP's technologies currently include a 3-layer poly-silicon surface micromachining process and LIGA (lithography, electroforming, and injection molding) processes that provide reasonable design flexibility within set guidelines. The consolidated micromechanical element library (CaMEL) is a library of active and passive MEMS structures that can be downloaded by the MEMS community via the internet. Smart MEMS is the development of advanced electronics integration techniques for MEMS through the application of flip chip technology. The MEMS technology network (TechNet) is a menu of standard substrates and MEMS fabrication processes that can be purchased and combined to create unique process flows. TechNet provides the MEMS community greater flexibility and enhanced technology accessibility.

A molecular dynamics study of slow base flipping in DNA using conformational flooding.

PubMed

Bouvier, Benjamin; Grubmüller, Helmut

2007-08-01

Individual DNA bases are known to be able to flip out of the helical stack, providing enzymes with access to the genetic information otherwise hidden inside the helix. Consequently, base flipping is a necessary first step to many more complex biological processes such as DNA transcription or replication. Much remains unknown about this elementary step, despite a wealth of experimental and theoretical studies. From the theoretical point of view, the involved timescale of milliseconds or longer requires the use of enhanced sampling techniques. In contrast to previous theoretical studies employing umbrella sampling along a predefined flipping coordinate, this study attempts to induce flipping without prior knowledge of the pathway, using information from a molecular dynamics simulation of a B-DNA fragment and the conformational flooding method. The relevance to base flipping of the principal components of the simulation is assayed, and a combination of modes optimally related to the flipping of the base through either helical groove is derived for each of the two bases of the central guanine-cytosine basepair. By applying an artificial flooding potential along these collective coordinates, the flipping mechanism is accelerated to within the scope of molecular dynamics simulations. The associated free energy surface is found to feature local minima corresponding to partially flipped states, particularly relevant to flipping in isolated DNA; further transitions from these minima to the fully flipped conformation are accelerated by additional flooding potentials. The associated free energy profiles feature similar barrier heights for both bases and pathways; the flipped state beyond is a broad and rugged attraction basin, only a few kcal/mol higher in energy than the closed conformation. This result diverges from previous works but echoes some aspects of recent experimental findings, justifying the need for novel approaches to this difficult problem: this contribution represents a first step in this direction. Important structural factors involved in flipping, both local (sugar-phosphate backbone dihedral angles) and global (helical axis bend), are also identified.

Synthesis of antiviral tetrahydrocarbazole derivatives by photochemical and acid-catalyzed C-H functionalization via intermediate peroxides (CHIPS).

PubMed

Gulzar, Naeem; Klussmann, Martin

2014-06-20

The direct functionalization of C-H bonds is an important and long standing goal in organic chemistry. Such transformations can be very powerful in order to streamline synthesis by saving steps, time and material compared to conventional methods that require the introduction and removal of activating or directing groups. Therefore, the functionalization of C-H bonds is also attractive for green chemistry. Under oxidative conditions, two C-H bonds or one C-H and one heteroatom-H bond can be transformed to C-C and C-heteroatom bonds, respectively. Often these oxidative coupling reactions require synthetic oxidants, expensive catalysts or high temperatures. Here, we describe a two-step procedure to functionalize indole derivatives, more specifically tetrahydrocarbazoles, by C-H amination using only elemental oxygen as oxidant. The reaction uses the principle of C-H functionalization via Intermediate PeroxideS (CHIPS). In the first step, a hydroperoxide is generated oxidatively using visible light, a photosensitizer and elemental oxygen. In the second step, the N-nucleophile, an aniline, is introduced by Brønsted-acid catalyzed activation of the hydroperoxide leaving group. The products of the first and second step often precipitate and can be conveniently filtered off. The synthesis of a biologically active compound is shown.

Fast and reliable method to estimate losses of single-mode waveguides with an arbitrary 2D trajectory.

PubMed

Negredo, F; Blaicher, M; Nesic, A; Kraft, P; Ott, J; Dörfler, W; Koos, C; Rockstuhl, C

2018-06-01

Photonic wire bonds, i.e., freeform waveguides written by 3D direct laser writing, emerge as a technology to connect different optical chips in fully integrated photonic devices. With the long-term vision of scaling up this technology to a large-scale fabrication process, the in situ optimization of the trajectory of photonic wire bonds is at stake. A prerequisite for the real-time optimization is the availability of a fast loss estimator for single-mode waveguides of arbitrary trajectory. Losses occur because of the bending of the waveguides and at transitions among sections of the waveguide with different curvatures. Here, we present an approach that resides on the fundamental mode approximation, i.e., the assumption that the photonic wire bonds predominantly carry their energy in a single mode. It allows us to predict in a quick and reliable way the pertinent losses from pre-computed modal properties of the waveguide, enabling fast design of optimum paths.

Microfabrication of plastic-PDMS microfluidic devices using polyimide release layer and selective adhesive bonding

DOE PAGES

Wang, Shuyu; Yu, Shifeng; Lu, Ming; ...

2017-03-15

In this study, we present an improved method to bond poly(dimethylsiloxane) (PDMS) with polyimide (PI) to develop flexible substrate microfluidic devices. The PI film was separately fabricated on a silicon wafer by spin coating followed by thermal treatment to avoid surface unevenness of the flexible substrate. In this way, we could also integrate flexible substrate into standard micro-electromechanical systems (MEMS) fabrication. Meanwhile, the adhesive epoxy was selectively transferred to the PDMS microfluidic device by a stamp-and-stick method to avoid epoxy clogging the microfluidic channels. To spread out the epoxy evenly on the transferring substrate, we used superhydrophilic vanadium oxide filmmore » coated glass as the transferring substrate. After the bonding process, the flexible substrate could easily be peeled off from the rigid substrate. Contact angle measurement was used to characterize the hydrophicity of the vanadium oxide film. X-ray photoelectron spectroscopy analysis was conducted to study the surface of the epoxy. We further evaluated the bonding quality by peeling tests, which showed a maximum bonding strength of 100 kPa. By injecting with black ink, the plastic microfluidic device was confirmed to be well bonded with no leakage for a day under 1 atm. Finally, this proposed versatile method could bond the microfluidic device and plastic substrate together and be applied in the fabrication of some biosensors and lab-on-a-chip systems.« less

Microfabrication of plastic-PDMS microfluidic devices using polyimide release layer and selective adhesive bonding

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Shuyu; Yu, Shifeng; Lu, Ming

In this study, we present an improved method to bond poly(dimethylsiloxane) (PDMS) with polyimide (PI) to develop flexible substrate microfluidic devices. The PI film was separately fabricated on a silicon wafer by spin coating followed by thermal treatment to avoid surface unevenness of the flexible substrate. In this way, we could also integrate flexible substrate into standard micro-electromechanical systems (MEMS) fabrication. Meanwhile, the adhesive epoxy was selectively transferred to the PDMS microfluidic device by a stamp-and-stick method to avoid epoxy clogging the microfluidic channels. To spread out the epoxy evenly on the transferring substrate, we used superhydrophilic vanadium oxide filmmore » coated glass as the transferring substrate. After the bonding process, the flexible substrate could easily be peeled off from the rigid substrate. Contact angle measurement was used to characterize the hydrophicity of the vanadium oxide film. X-ray photoelectron spectroscopy analysis was conducted to study the surface of the epoxy. We further evaluated the bonding quality by peeling tests, which showed a maximum bonding strength of 100 kPa. By injecting with black ink, the plastic microfluidic device was confirmed to be well bonded with no leakage for a day under 1 atm. Finally, this proposed versatile method could bond the microfluidic device and plastic substrate together and be applied in the fabrication of some biosensors and lab-on-a-chip systems.« less

Rapid bonding of polydimethylsiloxane (PDMS) to various stereolithographically (STL) structurable epoxy resins using photochemically cross-linked intermediary siloxane layers

NASA Astrophysics Data System (ADS)

Wilhelm, Elisabeth; Neumann, Christiane; Sachsenheimer, Kai; Länge, Kerstin; Rapp, Bastian E.

2014-03-01

In this paper we present a fast, low cost bonding technology for combining rigid epoxy components with soft membranes made out of polydimethylsiloxane (PDMS). Both materials are commonly used for microfluidic prototyping. Epoxy resins are often applied when rigid channels are required, that will not deform if exposed to high pressure. PDMS, on the other hand, is a flexible material, which allows integration of membrane valves on the chip. However, the integration of pressure driven components, such as membrane valves and pumps, into a completely flexible device leads to pressure losses. In order to build up pressure driven components with maximum energy efficiency a combination of rigid guiding channels and flexible membranes would be advisable. Stereolithographic (STL) structuring would be an ideal fabrication technique for this purpose, because complex 3D-channels structures can easily be fabricated using this technology. Unfortunately, the STL epoxies cannot be bonded using common bonding techniques. For this reason we propose two UV-light based silanization techniques that enable plasma induced bonding of epoxy components. The entire process including silanization and corona discharge bonding can be carried out within half an hour. Average bond strengths up to 350 kPa (depending on the silane) were determined in ISO-conform tensile testing. The applicability of both techniques for microfluidic applications was proven by hydrolytic stability testing lasting more than 40 hours.

Nanofiber Anisotropic Conductive Films (ACF) for Ultra-Fine-Pitch Chip-on-Glass (COG) Interconnections

NASA Astrophysics Data System (ADS)

Lee, Sang-Hoon; Kim, Tae-Wan; Suk, Kyung-Lim; Paik, Kyung-Wook

2015-11-01

Nanofiber anisotropic conductive films (ACF) were invented, by adapting nanofiber technology to ACF materials, to overcome the limitations of ultra-fine-pitch interconnection packaging, i.e. shorts and open circuits as a result of the narrow space between bumps and electrodes. For nanofiber ACF, poly(vinylidene fluoride) (PVDF) and poly(butylene succinate) (PBS) polymers were used as nanofiber polymer materials. For PVDF and PBS nanofiber ACF, conductive particles of diameter 3.5 μm were incorporated into nanofibers by electrospinning. In ultra-fine-pitch chip-on-glass assembly, insulation was significantly improved by using nanofiber ACF, because nanofibers inside the ACF suppressed the mobility of conductive particles, preventing them from flowing out during the bonding process. Capture of conductive particles was increased from 31% (conventional ACF) to 65%, and stable electrical properties and reliability were achieved by use of nanofiber ACF.

Sample flow switching techniques on microfluidic chips.

PubMed

Pan, Yu-Jen; Lin, Jin-Jie; Luo, Win-Jet; Yang, Ruey-Jen

2006-02-15

This paper presents an experimental investigation into electrokinetically focused flow injection for bio-analytical applications. A novel microfluidic device for microfluidic sample handling is presented. The microfluidic chip is fabricated on glass substrates using conventional photolithographic and chemical etching processes and is bonded using a high-temperature fusion method. The proposed valve-less device is capable not only of directing a single sample flow to a specified output port, but also of driving multiple samples to separate outlet channels or even to a single outlet to facilitate sample mixing. The experimental results confirm that the sample flow can be electrokinetically pre-focused into a narrow stream and guided to the desired outlet port by means of a simple control voltage model. The microchip presented within this paper has considerable potential for use in a variety of applications, including high-throughput chemical analysis, cell fusion, fraction collection, sample mixing, and many other applications within the micro-total-analysis systems field.

Monolithic short wave infrared (SWIR) detector array

NASA Technical Reports Server (NTRS)

1983-01-01

A monolithic self-scanned linear detector array was developed for remote sensing in the 1.1- 2.4-micron spectral region. A high-density IRCCD test chip was fabricated to verify new design approaches required for the detector array. The driving factors in the Schottky barrier IRCCD (Pdsub2Si) process development are the attainment of detector yield, uniformity, adequate quantum efficiency, and lowest possible dark current consistent with radiometric accuracy. A dual-band module was designed that consists of two linear detector arrays. The sensor architecture places the floating diffusion output structure in the middle of the chip, away from the butt edges. A focal plane package was conceptualized and includes a polycrystalline silicon substrate carrying a two-layer, thick-film interconnecting conductor pattern and five epoxy-mounted modules. A polycrystalline silicon cover encloses the modules and bond wires, and serves as a radiation and EMI shield, thermal conductor, and contamination seal.

Plastic lab-on-a-chip for fluorescence excitation with integrated organic semiconductor lasers.

PubMed

Vannahme, Christoph; Klinkhammer, Sönke; Lemmer, Uli; Mappes, Timo

2011-04-25

Laser light excitation of fluorescent markers offers highly sensitive and specific analysis for bio-medical or chemical analysis. To profit from these advantages for applications in the field or at the point-of-care, a plastic lab-on-a-chip with integrated organic semiconductor lasers is presented here. First order distributed feedback lasers based on the organic semiconductor tris(8-hydroxyquinoline) aluminum (Alq3) doped with the laser dye 4-dicyanomethylene-2-methyl-6-(p-dimethylaminostyril)-4H-pyrane (DCM), deep ultraviolet induced waveguides, and a nanostructured microfluidic channel are integrated into a poly(methyl methacrylate) (PMMA) substrate. A simple and parallel fabrication process is used comprising thermal imprint, DUV exposure, evaporation of the laser material, and sealing by thermal bonding. The excitation of two fluorescent marker model systems including labeled antibodies with light emitted by integrated lasers is demonstrated.

Hybridization of active and passive elements for planar photonic components and interconnects

NASA Astrophysics Data System (ADS)

Pearson, M.; Bidnyk, S.; Balakrishnan, A.

2007-02-01

The deployment of Passive Optical Networks (PON) for Fiber-to-the-Home (FTTH) applications currently represents the fastest growing sector of the telecommunication industry. Traditionally, FTTH transceivers have been manufactured using commodity bulk optics subcomponents, such as thin film filters (TFFs), micro-optic collimating lenses, TO-packaged lasers, and photodetectors. Assembling these subcomponents into a single housing requires active alignment and labor-intensive techniques. Today, the majority of cost reducing strategies using bulk subcomponents has been implemented making future reductions in the price of manufacturing FTTH transceivers unlikely. Future success of large scale deployments of FTTH depends on further cost reductions of transceivers. Realizing the necessity of a radically new packaging approach for assembly of photonic components and interconnects, we designed a novel way of hybridizing active and passive elements into a planar lightwave circuit (PLC) platform. In our approach, all the filtering components were monolithically integrated into the chip using advancements in planar reflective gratings. Subsequently, active components were passively hybridized with the chip using fully-automated high-capacity flip-chip bonders. In this approach, the assembly of the transceiver package required no active alignment and was readily suitable for large-scale production. This paper describes the monolithic integration of filters and hybridization of active components in both silica-on-silicon and silicon-on-insulator PLCs.

Rotational spectra of tetracyclic quinolizidine alkaloids: does a water molecule flip sparteine?

PubMed

Lesarri, Alberto; Pinacho, Ruth; Enríquez, Lourdes; Rubio, José E; Jaraíz, Martín; Abad, José L; Gigosos, Marco A

2017-07-21

Sparteine is a quinolizidine alkaloid used as a chiral auxiliary in asymmetric synthesis. We examine whether hydration by a single molecule can flip sparteine from the most stable trans conformation to the bidentate cis arrangement observed in catalytic complexation to a metal center. Sparteine and the sparteine-water dimer were generated in a supersonic jet expansion with H 2 16 O and H 2 18 O, and characterized by broadband chirped-pulse microwave spectroscopy. Even though the bidentate water dimer was predicted with larger binding energy, a single isomer was observed for the monohydrated cluster, with sparteine retaining the trans conformation observed for the free molecule. The absence of the bidentate dimer is attributed to the kinetic control of cluster formation, favoring the pre-expansion most abundant monomer. The structural properties of the O-HN hydrogen bond in the dimer are compared with those of complexes of other secondary and tertiary amines.

Direct Measurement of the Flip-Flop Rate of Electron Spins in the Solid State

NASA Astrophysics Data System (ADS)

Dikarov, Ekaterina; Zgadzai, Oleg; Artzi, Yaron; Blank, Aharon

2016-10-01

Electron spins in solids have a central role in many current and future spin-based devices, ranging from sensitive sensors to quantum computers. Many of these apparatuses rely on the formation of well-defined spin structures (e.g., a 2D array) with controlled and well-characterized spin-spin interactions. While being essential for device operation, these interactions can also result in undesirable effects, such as decoherence. Arguably, the most important pure quantum interaction that causes decoherence is known as the "flip-flop" process, where two interacting spins interchange their quantum state. Currently, for electron spins, the rate of this process can only be estimated theoretically, or measured indirectly, under limiting assumptions and approximations, via spin-relaxation data. This work experimentally demonstrates how the flip-flop rate can be directly and accurately measured by examining spin-diffusion processes in the solid state for physically fixed spins. Under such terms, diffusion can occur only through this flip-flop-mediated quantum-state exchange and not via actual spatial motion. Our approach is implemented on two types of samples, phosphorus-doped 28Si and nitrogen vacancies in diamond, both of which are significantly relevant to quantum sensors and information processing. However, while the results for the former sample are conclusive and reveal a flip-flop rate of approximately 12.3 Hz, for the latter sample only an upper limit of approximately 0.2 Hz for this rate can be estimated.

Off-line, built-in test techniques for VLSI circuits

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Sievers, M. W.

1982-01-01

It is shown that the use of redundant on-chip circuitry improves the testability of an entire VLSI circuit. In the study described here, five techniques applied to a two-bit ripple carry adder are compared. The techniques considered are self-oscillation, self-comparison, partition, scan path, and built-in logic block observer. It is noted that both classical stuck-at faults and nonclassical faults, such as bridging faults (shorts), stuck-on x faults where x may be 0, 1, or vary between the two, and parasitic flip-flop faults occur in IC structures. To simplify the analysis of the testing techniques, however, a stuck-at fault model is assumed.

Broad Frequency LTCC Vertical Interconnect Transition for Multichip Modules and System on Package Applications

NASA Technical Reports Server (NTRS)

Decrossas, Emmanuel; Glover, Michael D.; Porter, Kaoru; Cannon, Tom; Mantooth, H. Alan; Hamilton, M. C.

2013-01-01

Various stripline structures and flip chip interconnect designs for high-speed digital communication systems implemented in low temperature co-fired ceramic (LTCC) substrates are studied in this paper. Specifically, two different transition designs from edge launch 2.4 millimeter connectors to stripline transmission lines embedded in LTCC are discussed. After characterizing the DuPont (sup trademark) 9K7 green tape, different designs are proposed to improve signal integrity for high-speed digital data. The full-wave simulations and experimental data validate the presented designs over a broad frequency band from Direct Current to 50 gigahertz and beyond.

Research on defects inspection of solder balls based on eddy current pulsed thermography.

PubMed

Zhou, Xiuyun; Zhou, Jinlong; Tian, Guiyun; Wang, Yizhe

2015-10-13

In order to solve tiny defect detection for solder balls in high-density flip-chip, this paper proposed feasibility study on the effect of detectability as well as classification based on eddy current pulsed thermography (ECPT). Specifically, numerical analysis of 3D finite element inductive heat model is generated to investigate disturbance on the temperature field for different kind of defects such as cracks, voids, etc. The temperature variation between defective and non-defective solder balls is monitored for defects identification and classification. Finally, experimental study is carried on the diameter 1mm tiny solder balls by using ECPT and verify the efficacy of the technique.

Germanium ``hexa'' detector: production and testing

NASA Astrophysics Data System (ADS)

Sarajlić, M.; Pennicard, D.; Smoljanin, S.; Hirsemann, H.; Struth, B.; Fritzsch, T.; Rothermund, M.; Zuvic, M.; Lampert, M. O.; Askar, M.; Graafsma, H.

2017-01-01

Here we present new result on the testing of a Germanium sensor for X-ray radiation. The system is made of 3 × 2 Medipix3RX chips, bump-bonded to a monolithic sensor, and is called ``hexa''. Its dimensions are 45 × 30 mm2 and the sensor thickness was 1.5 mm. The total number of the pixels is 393216 in the matrix 768 × 512 with pixel pitch 55 μ m. Medipix3RX read-out chip provides photon counting read-out with single photon sensitivity. The sensor is cooled to -126°C and noise levels together with flat field response are measured. For -200 V polarization bias, leakage current was 4.4 mA (3.2 μ A/mm2). Due to higher leakage around 2.5% of all pixels stay non-responsive. More than 99% of all pixels are bump bonded correctly. In this paper we present the experimental set-up, threshold equalization procedure, image acquisition and the technique for bump bond quality estimate.

Wind and Wind Stress Measurements in HiRes

DTIC Science & Technology

2008-09-30

to design the experimental system to be conducted on R /P FLIP. Data from a past experiment are also being analyzed with respect to processes...For the HiRes experiment on R /P FLIP, the air temperature profile will be measured along with wind stress, surface heat flux, sea surface...the best as it registered the lower ambient temperature. In preparation for the HiRes experiment onboard R /P FLIP a mast prototype was built in

Integrated Inductors for RF Transmitters in CMOS/MEMS Smart Microsensor Systems

PubMed Central

Kim, Jong-Wan; Takao, Hidekuni; Sawada, Kazuaki; Ishida, Makoto

2007-01-01

This paper presents the integration of an inductor by complementary metal-oxide-semiconductor (CMOS) compatible processes for integrated smart microsensor systems that have been developed to monitor the motion and vital signs of humans in various environments. Integration of radio frequency transmitter (RF) technology with complementary metal-oxide-semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize the wireless smart microsensors system. The essential RF components such as a voltage controlled RF-CMOS oscillator (VCO), spiral inductors for an LC resonator and an integrated antenna have been fabricated and evaluated experimentally. The fabricated RF transmitter and integrated antenna were packaged with subminiature series A (SMA) connectors, respectively. For the impedance (50 Ω) matching, a bonding wire type inductor was developed. In this paper, the design and fabrication of the bonding wire inductor for impedance matching is described. Integrated techniques for the RF transmitter by CMOS compatible processes have been successfully developed. After matching by inserting the bonding wire inductor between the on-chip integrated antenna and the VCO output, the measured emission power at distance of 5 m from RF transmitter was -37 dBm (0.2 μW).

Vacuum Gap Microstrip Microwave Resonators for 2.5-D Integration in Quantum Computing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lewis, Rupert M.; Henry, Michael David; Schroeder, Katlin

We demonstrate vacuum gap λ/2 microwave resonators as a route toward higher integration in superconducting qubit circuits. The resonators are fabricated from pieces on two silicon chips bonded together with an In-Sb bond. Measurements of the devices yield resonant frequencies in good agreement with simulations. Furthermore, we discuss creating low loss circuits in this geometry.

Vacuum Gap Microstrip Microwave Resonators for 2.5-D Integration in Quantum Computing

DOE PAGES

Lewis, Rupert M.; Henry, Michael David; Schroeder, Katlin

2017-02-22

We demonstrate vacuum gap λ/2 microwave resonators as a route toward higher integration in superconducting qubit circuits. The resonators are fabricated from pieces on two silicon chips bonded together with an In-Sb bond. Measurements of the devices yield resonant frequencies in good agreement with simulations. Furthermore, we discuss creating low loss circuits in this geometry.

Self-regenerating and hybrid irreversible/reversible PDMS microfluidic devices.

PubMed

Shiroma, Letícia S; Piazzetta, Maria H O; Duarte-Junior, Gerson F; Coltro, Wendell K T; Carrilho, Emanuel; Gobbi, Angelo L; Lima, Renato S

2016-05-16

This paper outlines a straightforward, fast, and low-cost method to fabricate polydimethylsiloxane (PDMS) chips. Termed sandwich bonding (SWB), this method requires only a laboratory oven. Initially, SWB relies on the reversible bonding of a coverslip over PDMS channels. The coverslip is smaller than the substrate, leaving a border around the substrate exposed. Subsequently, a liquid composed of PDMS monomers and a curing agent is poured onto the structure. Finally, the cover is cured. We focused on PDMS/glass chips because of their key advantages in microfluidics. Despite its simplicity, this method created high-performance microfluidic channels. Such structures featured self-regeneration after leakages and hybrid irreversible/reversible behavior. The reversible nature was achieved by removing the cover of PDMS with acetone. Thus, the PDMS substrate and glass coverslip could be detached for reuse. These abilities are essential in the stages of research and development. Additionally, SWB avoids the use of surface oxidation, half-cured PDMS as an adhesive, and surface chemical modification. As a consequence, SWB allows surface modifications before the bonding, a long time for alignment, the enclosure of sub-micron channels, and the prototyping of hybrid devices. Here, the technique was successfully applied to bond PDMS to Au and Al.

Self-regenerating and hybrid irreversible/reversible PDMS microfluidic devices

PubMed Central

Shiroma, Letícia S.; Piazzetta, Maria H. O.; Duarte-Junior, Gerson F.; Coltro, Wendell K. T.; Carrilho, Emanuel; Gobbi, Angelo L.; Lima, Renato S.

2016-01-01

This paper outlines a straightforward, fast, and low-cost method to fabricate polydimethylsiloxane (PDMS) chips. Termed sandwich bonding (SWB), this method requires only a laboratory oven. Initially, SWB relies on the reversible bonding of a coverslip over PDMS channels. The coverslip is smaller than the substrate, leaving a border around the substrate exposed. Subsequently, a liquid composed of PDMS monomers and a curing agent is poured onto the structure. Finally, the cover is cured. We focused on PDMS/glass chips because of their key advantages in microfluidics. Despite its simplicity, this method created high-performance microfluidic channels. Such structures featured self-regeneration after leakages and hybrid irreversible/reversible behavior. The reversible nature was achieved by removing the cover of PDMS with acetone. Thus, the PDMS substrate and glass coverslip could be detached for reuse. These abilities are essential in the stages of research and development. Additionally, SWB avoids the use of surface oxidation, half-cured PDMS as an adhesive, and surface chemical modification. As a consequence, SWB allows surface modifications before the bonding, a long time for alignment, the enclosure of sub-micron channels, and the prototyping of hybrid devices. Here, the technique was successfully applied to bond PDMS to Au and Al. PMID:27181918

Micro flow-through PCR in a PMMA chip fabricated by KrF excimer laser.

PubMed

Yao, Liying; Liu, Baoan; Chen, Tao; Liu, Shibing; Zuo, Tiechuan

2005-09-01

As the third PCR technology, micro flow-through PCR chip can amplify DNA specifically in an exponential fashion in vitro. Nowadays many academies in the world have successfully amplified DNA using their own-made flow-through PCR chip. In this paper, the ablation principle of PMMA at 248 nm excimer laser was studied, then a PMMA based flow-through PCR chip with 20 cycles was fabricated by excimer laser at 19 kv and 18 mm/min. The chip was bonded together with another cover chip at 105( composite function)C, 160 N and 20 minutes. In the end, it was integrated with electrical thermal thin films and Pt 100 temperature sensors. The temperature controllers was built standard PID digital temperature controller, the temperature control precision was +/- 0.2( composite function)C. The temperature grads between the three temperature zones were 16.5 and 22.2( composite function)C respectively, the gaps between the temperature zones could realize heat insulation.

Influence of radiation on metastability-based TRNG

NASA Astrophysics Data System (ADS)

Wieczorek, Piotr Z.; Wieczorek, Zbigniew

2017-08-01

This paper presents a True Random Number Generator (TRNG) based on Flip-Flops with violated timing constraints. The proposed circuit has been implemented in a Xilinx Spartan 6 device. The TRNG circuit utilizes the metastability phenomenon as a source of randomness. Therefore, in the paper the influence of timing constraints on the flip-flop metastability proximity is discussed. The metastable range of operation enhances the noise influence on a Flip-Flop behavior. Therefore, the influence of an external stochastic source on the flip-flop operation is also investigated. For this purpose a radioactive source of radiation was used. According to the results shown in the paper the radiation increases the unpredictability of the metastable process of flip-flops operating as the randomness source in the TRNG. The statistical properties of TRNG operating in an increased radiation conditions were verified with the NIST battery of statistical tests.

Multilayer-based lab-on-a-chip systems for perfused cell-based assays

NASA Astrophysics Data System (ADS)

Klotzbach, Udo; Sonntag, Frank; Grünzner, Stefan; Busek, Mathias; Schmieder, Florian; Franke, Volker

2014-12-01

A novel integrated technology chain of laser-microstructured multilayer foils for fast, flexible, and low-cost manufacturing of lab-on-a-chip devices especially for complex cell and tissue culture applications, which provides pulsatile fluid flow within physiological ranges at low media-to-cells ratio, was developed and established. Initially the microfluidic system is constructively divided into individual layers, which are formed by separate foils or plates. Based on the functional boundary conditions and the necessary properties of each layer, their corresponding foils and plates are chosen. In the third step, the foils and plates are laser microstructured and functionalized from both sides. In the fourth and last manufacturing step, the multiple plates and foils are joined using different bonding techniques like adhesive bonding, welding, etc. This multilayer technology together with pneumatically driven micropumps and valves permits the manufacturing of fluidic structures and perfusion systems, which spread out above multiple planes. Based on the established lab-on-a-chip platform for perfused cell-based assays, a multilayer microfluidic system with two parallel connected cell culture chambers was successfully implemented.

A modified implementation of tristate inverter based static master-slave flip-flop with improved power-delay-area product.

PubMed

Singh, Kunwar; Tiwari, Satish Chandra; Gupta, Maneesha

2014-01-01

The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C(2)MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C(2)MOS based flip-flop designs mC(2)MOSff1 and mC(2)MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC(2)MOSff1. Postlayout simulations indicate that mC(2)MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes.

A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product

PubMed Central

Tiwari, Satish Chandra; Gupta, Maneesha

2014-01-01

The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C2MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C2MOS based flip-flop designs mC2MOSff1 and mC2MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC2MOSff1. Postlayout simulations indicate that mC2MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes. PMID:24723808

Body of Knowledge (BOK) for Copper Wire Bonds

NASA Technical Reports Server (NTRS)

Rutkowski, E.; Sampson, M. J.

2015-01-01

Copper wire bonds have replaced gold wire bonds in the majority of commercial semiconductor devices for the latest technology nodes. Although economics has been the driving mechanism to lower semiconductor packaging costs for a savings of about 20% by replacing gold wire bonds with copper, copper also has materials property advantages over gold. When compared to gold, copper has approximately: 25% lower electrical resistivity, 30% higher thermal conductivity, 75% higher tensile strength and 45% higher modulus of elasticity. Copper wire bonds on aluminum bond pads are also more mechanically robust over time and elevated temperature due to the slower intermetallic formation rate - approximately 1/100th that of the gold to aluminum intermetallic formation rate. However, there are significant tradeoffs with copper wire bonding - copper has twice the hardness of gold which results in a narrower bonding manufacturing process window and requires that the semiconductor companies design more mechanically rigid bonding pads to prevent cratering to both the bond pad and underlying chip structure. Furthermore, copper is significantly more prone to corrosion issues. The semiconductor packaging industry has responded to this corrosion concern by creating a palladium coated copper bonding wire, which is more corrosion resistant than pure copper bonding wire. Also, the selection of the device molding compound is critical because use of environmentally friendly green compounds can result in internal CTE (Coefficient of Thermal Expansion) mismatches with the copper wire bonds that can eventually lead to device failures during thermal cycling. Despite the difficult problems associated with the changeover to copper bonding wire, there are billions of copper wire bonded devices delivered annually to customers. It is noteworthy that Texas Instruments announced in October of 2014 that they are shipping microcircuits containing copper wire bonds for safety critical automotive applications. An evaluation of copper wire bond technology for applicability to spaceflight hardware may be warranted along with concurrently compiling a comprehensive understanding of the failure mechanisms involved with copper wire bonded semiconductor devices.

The effectiveness of flipped classroom learning model in secondary physics classroom setting

NASA Astrophysics Data System (ADS)

Prasetyo, B. D.; Suprapto, N.; Pudyastomo, R. N.

2018-03-01

The research aimed to describe the effectiveness of flipped classroom learning model on secondary physics classroom setting during Fall semester of 2017. The research object was Secondary 3 Physics group of Singapore School Kelapa Gading. This research was initiated by giving a pre-test, followed by treatment setting of the flipped classroom learning model. By the end of the learning process, the pupils were given a post-test and questionnaire to figure out pupils' response to the flipped classroom learning model. Based on the data analysis, 89% of pupils had passed the minimum criteria of standardization. The increment level in the students' mark was analysed by normalized n-gain formula, obtaining a normalized n-gain score of 0.4 which fulfil medium category range. Obtains from the questionnaire distributed to the students that 93% of students become more motivated to study physics and 89% of students were very happy to carry on hands-on activity based on the flipped classroom learning model. Those three aspects were used to generate a conclusion that applying flipped classroom learning model in Secondary Physics Classroom setting is effectively applicable.

[Preparation of poly(methyl acrylate) microfluidic chips surface-modified by hyperbranched polyamide ester and their application in the separation of biomolecules].

PubMed

Liu, Bing; Lin, Donge; Xu, Lin; Lei, Yanhui; Bo, Qianglong; Shou, Chongqi

2012-05-01

The surface of poly (methyl acrylate) (PMMA) microfluidic chips were modified using hyperbranched polyamide ester via chemical bonding. The contact angles of the modified chips were measured. The surface morphology was observed by scanning electron microscope (SEM) and stereo microscope. The results showed that the surface of the modified chips was coated by a dense, uniform, continuous, hydrophilic layer of hyperbranched polyamide ester. The hydrophilic of the chip surface was markedly improved. The contact angle of the chips modified decreased from 89.9 degrees to 29.5 degrees. The electro osmotic flow (EOF) in the modified microchannel was lower than that in the unmodified microchannel. Adenosine and L-lysine were detected and separated via the modified PMMA microfluidic chips. Compared with unmodified chips, the modified chips successfully separated the two biomolecules. The detection peaks were clear and sharp. The separation efficiencies of adenosine and L-lysine were 8.44 x 10(4) plates/m and 9.82 x 10(4) plates/m respectively, and the resolutions (Rs) was 5.31. The column efficiencies and resolutions of the modified chips were much higher than those of the unmodified chips. It was also observed that the modified chips possessed good reproducibility of migration time. This research may provide a new and effective method to improve the hydrophilicity of the PMMA surface and the application of PMMA microfluidic chips in the determination of trace biomolecules.

Carbon dioxide hydrogenation on Ni(110).

PubMed

Vesselli, Erik; De Rogatis, Loredana; Ding, Xunlei; Baraldi, Alessandro; Savio, Letizia; Vattuone, Luca; Rocca, Mario; Fornasiero, Paolo; Peressi, Maria; Baldereschi, Alfonso; Rosei, Renzo; Comelli, Giovanni

2008-08-27

We demonstrate that the key step for the reaction of CO 2 with hydrogen on Ni(110) is a change of the activated molecule coordination to the metal surface. At 90 K, CO 2 is negatively charged and chemically bonded via the carbon atom. When the temperature is increased and H approaches, the H-CO 2 complex flips and binds to the surface through the two oxygen atoms, while H binds to the carbon atom, thus yielding formate. We provide the atomic-level description of this process by means of conventional ultrahigh vacuum surface science techniques combined with density functional theory calculations and corroborated by high pressure reactivity tests. Knowledge about the details of the mechanisms involved in this reaction can yield a deeper comprehension of heterogeneous catalytic organic synthesis processes involving carbon dioxide as a reactant. We show why on Ni the CO 2 hydrogenation barrier is remarkably smaller than that on the common Cu metal-based catalyst. Our results provide a possible interpretation of the observed high catalytic activity of NiCu alloys.

E-motif formed by extrahelical cytosine bases in DNA homoduplexes of trinucleotide and hexanucleotide repeats

PubMed Central

Pan, Feng; Zhang, Yuan; Man, Viet Hoang; Roland, Christopher

2018-01-01

Abstract Atypical DNA secondary structures play an important role in expandable trinucleotide repeat (TR) and hexanucleotide repeat (HR) diseases. The cytosine mismatches in C-rich homoduplexes and hairpin stems are weakly bonded; experiments show that for certain sequences these may flip out of the helix core, forming an unusual structure termed an ‘e-motif’. We have performed molecular dynamics simulations of C-rich TR and HR DNA homoduplexes in order to characterize the conformations, stability and dynamics of formation of the e-motif, where the mismatched cytosines symmetrically flip out in the minor groove, pointing their base moieties towards the 5′-direction in each strand. TRs have two non-equivalent reading frames, (GCC)n and (CCG)n; while HRs have three: (CCCGGC)n, (CGGCCC)n, (CCCCGG)n. We define three types of pseudo basepair steps related to the mismatches and show that the e-motif is only stable in (GCC)n and (CCCGGC)n homoduplexes due to the favorable stacking of pseudo GpC steps (whose nature depends on whether TRs or HRs are involved) and the formation of hydrogen bonds between the mismatched cytosine at position i and the cytosine (TRs) or guanine (HRs) at position i − 2 along the same strand. We also characterize the extended e-motif, where all mismatched cytosines are extruded, their extra-helical stacking additionally stabilizing the homoduplexes. PMID:29190385

Design and fabrication of a multilayered polymer microfluidic chip with nanofluidic interconnects via adhesive contact printing.

PubMed

Flachsbart, Bruce R; Wong, Kachuen; Iannacone, Jamie M; Abante, Edward N; Vlach, Robert L; Rauchfuss, Peter A; Bohn, Paul W; Sweedler, Jonathan V; Shannon, Mark A

2006-05-01

The design and fabrication of a multilayered polymer micro-nanofluidic chip is described that consists of poly(methylmethacrylate) (PMMA) layers that contain microfluidic channels separated in the vertical direction by polycarbonate (PC) membranes that incorporate an array of nanometre diameter cylindrical pores. The materials are optically transparent to allow inspection of the fluids within the channels in the near UV and visible spectrum. The design architecture enables nanofluidic interconnections to be placed in the vertical direction between microfluidic channels. Such an architecture allows microchannel separations within the chip, as well as allowing unique operations that utilize nanocapillary interconnects: the separation of analytes based on molecular size, channel isolation, enhanced mixing, and sample concentration. Device fabrication is made possible by a transfer process of labile membranes and the development of a contact printing method for a thermally curable epoxy based adhesive. This adhesive is shown to have bond strengths that prevent leakage and delamination and channel rupture tests exceed 6 atm (0.6 MPa) under applied pressure. Channels 100 microm in width and 20 microm in depth are contact printed without the adhesive entering the microchannel. The chip is characterized in terms of resistivity measurements along the microfluidic channels, electroosmotic flow (EOF) measurements at different pH values and laser-induced-fluorescence (LIF) detection of green-fluorescent protein (GFP) plugs injected across the nanocapillary membrane and into a microfluidic channel. The results indicate that the mixed polymer micro-nanofluidic multilayer chip has electrical characteristics needed for use in microanalytical systems.

Design of frequency-encoded data-based optical master-slave-JK flip-flop using polarization switch

NASA Astrophysics Data System (ADS)

Mandal, Sumana; Mandal, Dhoumendra; Mandal, Mrinal Kanti; Garai, Sisir Kumar

2017-06-01

An optical data processing and communication system provides enormous potential bandwidth and a very high processing speed, and it can fulfill the demands of the present generation. For an optical computing system, several data processing units that work in the optical domain are essential. Memory elements are undoubtedly essential to storing any information. Optical flip-flops can store one bit of optical information. From these flip-flop registers, counters can be developed. Here, the authors proposed an optical master-slave (MS)-JK flip-flop with the help of two-input and three-input optical NAND gates. Optical NAND gates have been developed using semiconductor optical amplifiers (SOAs). The nonlinear polarization switching property of an SOA has been exploited here, and it acts as a polarization switch in the proposed scheme. A frequency encoding technique is adopted for representing data. A specific frequency of an optical signal represents a binary data bit. This technique of data representation is helpful because frequency is the fundamental property of a signal, and it remains unaltered during reflection, refraction, absorption, etc. throughout the data propagation. The simulated results enhance the admissibility of the scheme.

Tunnel magnetoresistance for coherent spin-flip processes on an interacting quantum dot.

PubMed

Rudziński, W

2009-01-28

Spin-polarized electronic tunneling through a quantum dot coupled to ferromagnetic electrodes is investigated within a nonequilibrium Green function approach. An interplay between coherent intradot spin-flip transitions, tunneling processes and Coulomb correlations on the dot is studied for current-voltage characteristics of the tunneling junction in parallel and antiparallel magnetic configurations of the leads. It is found that due to the spin-flip processes electric current in the antiparallel configuration tends to the current characteristics in the parallel configuration, thus giving rise to suppression of the tunnel magnetoresistance (TMR) between the threshold bias voltages at which the dot energy level becomes active in tunneling. Also, the effect of a negative differential conductance in symmetrical junctions, splitting of the conductance peaks, significant modulation of TMR peaks around the threshold bias voltages as well as suppression of the diode-like behavior in asymmetrical junctions is discussed in the context of coherent intradot spin-flip transitions. It is also shown that TMR may be inverted at selected gate voltages, which qualitatively reproduces the TMR behavior predicted recently for temperatures in the Kondo regime, and observed experimentally beyond the Kondo regime for a semiconductor InAs quantum dot coupled to nickel electrodes.

Silicon Integrated Optics: Fabrication and Characterization

NASA Astrophysics Data System (ADS)

Shearn, Michael Joseph, II

For decades, the microelectronics industry has sought integration and miniaturization as canonized in Moore's Law, and has continued doubling transistor density about every two years. However, further miniaturization of circuit elements is creating a bandwidth problem as chip interconnect wires shrink as well. A potential solution is the creation of an on-chip optical network with low delays that would be impossible to achieve using metal buses. However, this technology requires integrating optics with silicon microelectronics. The lack of efficient silicon optical sources has stymied efforts of an all-Si optical platform. Instead, the integration of efficient emitter materials, such as III-V semiconductors, with Si photonic structures is a low-cost, CMOS-compatible alternative platform. This thesis focuses on making and measuring on-chip photonic structures suitable for on-chip optical networking. The first part of the thesis assesses processing techniques of silicon and other semiconductor materials. Plasmas for etching and surface modification are described and used to make bonded, hybrid Si/III-V structures. Additionally, a novel masking method using gallium implantation into silicon for pattern definition is characterized. The second part of the thesis focuses on demonstrations of fabricated optical structures. A dense array of silicon devices is measured, consisting of fully-etched grating couplers, low-loss waveguides and ring resonators. Finally, recent progress in the Si/III-V hybrid system is discussed. Supermode control of devices is described, which uses changing Si waveguide width to control modal overlap with the gain material. Hybrid Si/III-V, Fabry-Perot evanescent lasers are demonstrated, utilizing a CMOS-compatible process suitable for integration on in electronics platforms. Future prospects and ultimate limits of Si devices and the hybrid Si/III-V system are also considered.

Reliability assessment of Multichip Module technologies via the Triservice/NASA RELTECH program

NASA Astrophysics Data System (ADS)

Fayette, Daniel F.

1994-10-01

Multichip Module (MCM) packaging/interconnect technologies have seen increased emphasis from both the commercial and military communities as a means of increasing capability and performance while providing a vehicle for reducing cost, power and weight of the end item electronic application. This is accomplished through three basic Multichip module technologies, MCM-L that are laminates, MCM-C that are ceramic type substrates and MCM-D that are deposited substrates (e.g., polymer dielectric with thin film metals). Three types of interconnect structures are also used with these substrates and include, wire bond, Tape Automated Bonds (TAB) and flip chip ball bonds. Application, cost, producibility and reliability are the drivers that will determine which MCM technology will best fit a respective need or requirement. With all the benefits and technologies cited, it would be expected that the use of, or the planned use of, MCM's would be more extensive in both military and commercial applications. However, two significant roadblocks exist to implementation of these new technologies: the absence of reliability data and a single national standard for the procurement of reliable/quality MCM's. To address the preceding issues, the Reliability Technology to Achieve Insertion of Advanced Packaging (RELTECH) program has been established. This program, which began in May 1992, has endeavored to evaluate a cross section of MCM technologies covering all classes of MCM's previously cited. NASA and the Tri-Services (Air Force Rome Laboratory, Naval Surface Warfare Center, Crane IN and Army Research Laboratory) have teamed together with sponsorship from ARPA to evaluate the performance, reliability and producibility of MCM's for both military and commercial usage. This is done in close cooperation with our industry partners whose support is critical to the goals of the program. Several tasks are being performed by the RELTECH program and data from this effort, in conjunction with information from our industry partners as well as discussions with industry organizations (IPC, EIA, ISHM, etc.) are being used to develop the qualification and screening requirements for MCM's. Specific tasks being performed by the RELTECH program include technical assessments, product evaluations, reliability modeling, environmental testing, and failure analysis. This paper will describe the various tasks associated with the RELTECH program, status, progress and a description of the national dual use specification being developed for MCM technologies.

Putting Structure to Flipped Classrooms Using Team-Based Learning

ERIC Educational Resources Information Center

Jakobsen, Krisztina V.; Knetemann, Megan

2017-01-01

Current educational practices and cognitive-developmental theories emphasize the importance of active participation in the learning environment, and they suggest that the first, and arguably most important, step to creating a better learning environment is to make learning an active and reciprocal process. Flipped classrooms, in which students…

Silicon-based products and solutions

NASA Astrophysics Data System (ADS)

Painchaud, Y.; Poulin, M.; Pelletier, F.; Latrasse, C.; Gagné, J.-F.; Savard, S.; Robidoux, G.; Picard, M.-.; Paquet, S.; Davidson, C.-.; Pelletier, M.; Cyr, M.; Paquet, C.; Guy, M.; Morsy-Osman, M.; Chagnon, M.; Plant, D. V.

2014-03-01

TeraXion started silicon photonics activities aiming at developing building blocks for new products and customized solutions. Passive and active devices have been developed including MMI couplers, power splitters, Bragg grating filters, high responsivity photodetectors, high speed modulators and variable optical attenuators. Packaging solutions including fiber attachment and hybrid integration using flip-chip were also developed. More specifically, a compact packaged integrated coherent receiver has been realized. Good performances were obtained as demonstrated by our system tests results showing transmission up to 4800 km with BER below hard FEC threshold. The package size is small but still limited by the electrical interface. Migrating to more compact RF interface would allow realizing the full benefit of this technology.

Large Area MEMS Based Ultrasound Device for Cancer Detection.

PubMed

Wodnicki, Robert; Thomenius, Kai; Hooi, Fong Ming; Sinha, Sumedha P; Carson, Paul L; Lin, Der-Song; Zhuang, Xuefeng; Khuri-Yakub, Pierre; Woychik, Charles

2011-08-21

We present image results obtained using a prototype ultrasound array which demonstrates the fundamental architecture for a large area MEMS based ultrasound device for detection of breast cancer. The prototype array consists of a tiling of capacitive Micro-Machined Ultrasound Transducers (cMUTs) which have been flip-chip attached to a rigid organic substrate. The pitch on the cMUT elements is 185 um and the operating frequency is nominally 9 MHz. The spatial resolution of the new probe is comparable to production PZT probes, however the sensitivity is reduced by conditions that should be correctable. Simulated opposed-view image registration and Speed of Sound volume reconstruction results for ultrasound in the mammographic geometry are also presented.

Physics of Failure Analysis of Xilinx Flip Chip CCGA Packages: Effects of Mission Environments on Properties of LP2 Underfill and ATI Lid Adhesive Materials

NASA Technical Reports Server (NTRS)

Suh, Jong-ook

2013-01-01

The Xilinx Virtex 4QV and 5QV (V4 and V5) are next-generation field-programmable gate arrays (FPGAs) for space applications. However, there have been concerns within the space community regarding the non-hermeticity of V4/V5 packages; polymeric materials such as the underfill and lid adhesive will be directly exposed to the space environment. In this study, reliability concerns associated with the non-hermeticity of V4/V5 packages were investigated by studying properties and behavior of the underfill and the lid adhesvie materials used in V4/V5 packages.

Facing the challenges in ophthalmology clerkship teaching: Is flipped classroom the answer?

PubMed Central

Lin, Ying; Zhu, Yi; Chen, Chuan; Wang, Wei; Chen, Tingting; Li, Tao; Li, Yonghao; Liu, Bingqian; Lian, Yu; Lu, Lin; Zou, Yuxian

2017-01-01

Recent reform of medical education highlights the growing concerns about the capability of the current educational model to equip medical school students with essential skills for future career development. In the field of ophthalmology, although many attempts have been made to address the problem of the decreasing teaching time and the increasing load of course content, a growing body of literature indicates the need to reform the current ophthalmology teaching strategies. Flipped classroom is a new pedagogical model in which students develop a basic understanding of the course materials before class, and use in-class time for learner-centered activities, such as group discussion and presentation. However, few studies have evaluated the effectiveness of the flipped classroom in ophthalmology education. This study, for the first time, assesses the use of flipped classroom in ophthalmology, specifically glaucoma and ocular trauma clerkship teaching. A total number of 44 international medical school students from diverse background were enrolled in this study, and randomly divided into two groups. One group took the flipped glaucoma classroom and lecture-based ocular trauma classroom, while the other group took the flipped ocular trauma classroom and lecture-based glaucoma classroom. In the traditional lecture-based classroom, students attended the didactic lecture and did the homework after class. In the flipped classroom, students were asked to watch the prerecorded lectures before the class, and use the class time for homework discussion. Both the teachers and students were asked to complete feedback questionnaires after the classroom. We found that the two groups did not show differences in the final exam scores. However, the flipped classroom helped students to develop skills in problem solving, creative thinking and team working. Also, compared to the lecture-based classroom, both teachers and students were more satisfied with the flipped classroom. Interestingly, students had a more positive attitude towards the flipped ocular trauma classroom than the flipped glaucoma classroom regarding the teaching process, the course materials, and the value of the classroom. Therefore, the flipped classroom model in ophthalmology teaching showed promise as an effective approach to promote active learning. PMID:28384167

Facing the challenges in ophthalmology clerkship teaching: Is flipped classroom the answer?

PubMed

Lin, Ying; Zhu, Yi; Chen, Chuan; Wang, Wei; Chen, Tingting; Li, Tao; Li, Yonghao; Liu, Bingqian; Lian, Yu; Lu, Lin; Zou, Yuxian; Liu, Yizhi

2017-01-01

Recent reform of medical education highlights the growing concerns about the capability of the current educational model to equip medical school students with essential skills for future career development. In the field of ophthalmology, although many attempts have been made to address the problem of the decreasing teaching time and the increasing load of course content, a growing body of literature indicates the need to reform the current ophthalmology teaching strategies. Flipped classroom is a new pedagogical model in which students develop a basic understanding of the course materials before class, and use in-class time for learner-centered activities, such as group discussion and presentation. However, few studies have evaluated the effectiveness of the flipped classroom in ophthalmology education. This study, for the first time, assesses the use of flipped classroom in ophthalmology, specifically glaucoma and ocular trauma clerkship teaching. A total number of 44 international medical school students from diverse background were enrolled in this study, and randomly divided into two groups. One group took the flipped glaucoma classroom and lecture-based ocular trauma classroom, while the other group took the flipped ocular trauma classroom and lecture-based glaucoma classroom. In the traditional lecture-based classroom, students attended the didactic lecture and did the homework after class. In the flipped classroom, students were asked to watch the prerecorded lectures before the class, and use the class time for homework discussion. Both the teachers and students were asked to complete feedback questionnaires after the classroom. We found that the two groups did not show differences in the final exam scores. However, the flipped classroom helped students to develop skills in problem solving, creative thinking and team working. Also, compared to the lecture-based classroom, both teachers and students were more satisfied with the flipped classroom. Interestingly, students had a more positive attitude towards the flipped ocular trauma classroom than the flipped glaucoma classroom regarding the teaching process, the course materials, and the value of the classroom. Therefore, the flipped classroom model in ophthalmology teaching showed promise as an effective approach to promote active learning.

Label-free sensing of the binding state of MUC1 peptide and anti-MUC1 aptamer solution in fluidic chip by terahertz spectroscopy.

PubMed

Zhao, Xiang; Zhang, Mingkun; Wei, Dongshan; Wang, Yunxia; Yan, Shihan; Liu, Mengwan; Yang, Xiang; Yang, Ke; Cui, Hong-Liang; Fu, Weiling

2017-10-01

The aptamer and target molecule binding reaction has been widely applied for construction of aptasensors, most of which are labeled methods. In contrast, terahertz technology proves to be a label-free sensing tool for biomedical applications. We utilize terahertz absorption spectroscopy and molecular dynamics simulation to investigate the variation of binding-induced collective vibration of hydrogen bond network in a mixed solution of MUC1 peptide and anti-MUC1 aptamer. The results show that binding-induced alterations of hydrogen bond numbers could be sensitively reflected by the variation of terahertz absorption coefficients of the mixed solution in a customized fluidic chip. The minimal detectable concentration is determined as 1 pmol/μL, which is approximately equal to the optimal immobilized concentration of aptasensors.

A method for UV-bonding in the fabrication of glass electrophoretic microchips.

PubMed

Huang, Z; Sanders, J C; Dunsmor, C; Ahmadzadeh, H; Landers, J P

2001-10-01

This paper presents an approach for the development of methodologies amenable to simple and inexpensive microchip fabrication, potentially applicable to dissimilar materials bonding and chip integration. The method involves a UV-curable glue that can be used for glass microchip fabrication bonding at room temperature. This involves nothing more than fabrication of glue "guide channels" into the microchip architecture that upon exposure to the appropriate UV light source, bonds the etched plate and cover plate together. The microchip performance was verified by capillary zone electrophoresis (CZE) of small fluorescent molecules with no microchannel surface modification carried out, as well as with a DNA fragment separation following surface modification. The performance of these UV-bonded electrophoretic microchips indicates that this method may provide an alternative to high temperature bonding.

Comparison of contamination of femoral heads and pre-processed bone chips during hip revision arthroplasty.

PubMed

Mathijssen, N M C; Sturm, P D; Pilot, P; Bloem, R M; Buma, P; Petit, P L; Schreurs, B W

2013-12-01

With bone impaction grafting, cancellous bone chips made from allograft femoral heads are impacted in a bone defect, which introduces an additional source of infection. The potential benefit of the use of pre-processed bone chips was investigated by comparing the bacterial contamination of bone chips prepared intraoperatively with the bacterial contamination of pre-processed bone chips at different stages in the surgical procedure. To investigate baseline contamination of the bone grafts, specimens were collected during 88 procedures before actual use or preparation of the bone chips: in 44 procedures intraoperatively prepared chips were used (Group A) and in the other 44 procedures pre-processed bone chips were used (Group B). In 64 of these procedures (32 using locally prepared bone chips and 32 using pre-processed bone chips) specimens were also collected later in the procedure to investigate contamination after use and preparation of the bone chips. In total, 8 procedures had one or more positive specimen(s) (12.5 %). Contamination rates were not significantly different between bone chips prepared at the operating theatre and pre-processed bone chips. In conclusion, there was no difference in bacterial contamination between bone chips prepared from whole femoral heads in the operating room and pre-processed bone chips, and therefore, both types of bone allografts are comparable with respect to risk of infection.

An NFC-Enabled CMOS IC for a Wireless Fully Implantable Glucose Sensor.

PubMed

DeHennis, Andrew; Getzlaff, Stefan; Grice, David; Mailand, Marko

2016-01-01

This paper presents an integrated circuit (IC) that merges integrated optical and temperature transducers, optical interface circuitry, and a near-field communication (NFC)-enabled digital, wireless readout for a fully passive implantable sensor platform to measure glucose in people with diabetes. A flip-chip mounted LED and monolithically integrated photodiodes serve as the transduction front-end to enable fluorescence readout. A wide-range programmable transimpedance amplifier adapts the sensor signals to the input of an 11-bit analog-to-digital converter digitizing the measurements. Measurement readout is enabled by means of wireless backscatter modulation to a remote NFC reader. The system is able to resolve current levels of less than 10 pA with a single fluorescent measurement energy consumption of less than 1 μJ. The wireless IC is fabricated in a 0.6-μm-CMOS process and utilizes a 13.56-MHz-based ISO15693 for passive wireless readout through a NFC interface. The IC is utilized as the core interface to a fluorescent, glucose transducer to enable a fully implantable sensor-based continuous glucose monitoring system.

Design and fabrication of giant micromirrors using electroplating-based technology

NASA Astrophysics Data System (ADS)

Ilias, Samir; Topart, Patrice A.; Larouche, Carl; Leclair, Sebastien; Jerominek, Hubert

2005-01-01

Giant micromirrors with large scanning deflection and good flatness are required for many space and terrestrial applications. A novel approach to manufacturing this category of micromirrors is proposed. The approach combines selective electroplating and flip-chip based technologies. It allows for large air gaps, flat and smooth active micromirror surfaces and permits independent fabrication of the micromirrors and control electronics, avoiding temperature and sacrificial layer incompatibilities between them. In this work, electrostatically actuated piston and torsion micromirrors were designed and simulated. The simulated structures were designed to allow large deflection, i.e. piston displacement larger than 10 um and torsional deflection up to 35°. To achieve large micromirror deflections, up to seventy micron-thick resists were used as a micromold for nickel and solder electroplating. Smooth micromirror surfaces (roughness lower than 5 nm rms) and large radius of curvature (R as large as 23 cm for a typical 1000x1000 um2 micromirror fabricated without address circuits) were achieved. A detailed fabrication process is presented. First piston mirror prototypes were fabricated and a preliminary evaluation of static deflection of a piston mirror is presented.

The Pharmaceutical Capping Process-Correlation between Residual Seal Force, Torque Moment, and Flip-off Removal Force.

PubMed

Mathaes, Roman; Mahler, Hanns-Christian; Vorgrimler, Lothar; Steinberg, Henrik; Dreher, Sascha; Roggo, Yves; Nieto, Alejandra; Brown, Helen; Roehl, Holger; Adler, Michael; Luemkemann, Joerg; Huwyler, Joerg; Lam, Philippe; Stauch, Oliver; Mohl, Silke; Streubel, Alexander

2016-01-01

The majority of parenteral drug products are manufactured in glass vials with an elastomeric rubber stopper and a crimp cap. The vial sealing process is a critical process step during fill-and-finish operations, as it defines the seal quality of the final product. Different critical capping process parameters can affect rubber stopper defects, rubber stopper compression, container closure integrity, and also crimp cap quality. A sufficiently high force to remove the flip-off button prior to usage is required to ensure quality of the drug product unit by the flip-off button during storage, transportation, and until opening and use. Therefore, the final product is 100% visually inspected for lose or defective crimp caps, which is subjective as well as time- and labor-intensive. In this study, we sealed several container closure system configurations with different capping equipment settings (with corresponding residual seal force values) to investigate the torque moment required to turn the crimp cap. A correlation between torque moment and residual seal force has been established. The torque moment was found to be influenced by several parameters, including diameter of the vial head, type of rubber stopper (serum or lyophilized) and type of crimp cap (West(®) or Datwyler(®)). In addition, we measured the force required to remove the flip-off button of a sealed container closure system. The capping process had no influence on measured forces; however, it was possible to detect partially crimped vials. In conclusion, a controlled capping process with a defined target residual seal force range leads to a tight crimp cap on a sealed container closure system and can ensure product quality. The majority of parenteral drug products are manufactured in a glass vials with an elastomeric rubber stopper and a crimp cap. The vial sealing process is a critical process step during fill-and-finish operations, as it defines the seal quality of the final product. An adequate force to remove the flip-off button prior to usage is required to ensure product quality during storage and transportation until use. In addition, the complete crimp cap needs to be fixed in a tight position on the vial. In this study, we investigated the torque moment required to turn the crimp cap and the force required to remove the flip-off button of container closure system sealed with different capping equipment process parameters (having different residual seal force values). © PDA, Inc. 2016.

Formation and Sustainment of Flipped Spherical Torus Plasmas on HIST

NASA Astrophysics Data System (ADS)

Oguro, T.; Jinno, T.; Hasegawa, H.; Nagata, M.; Fukumoto, N.; Uyama, T.; Masamune, S.; Iida, M.; Katsurai, M.

2002-11-01

In order to understand comprehensively the relaxation and self-organization in the coaxial helicity injection system, we have investigated dynamics of ST plasmas produced in the HIST device by decreasing the external toroidal field (TF) and reversing its sign in time. In results, we have discovered that the ST relaxes towards flipped/reversed ST configurations. Surprisingly, it has been observed that not only toroidal flux but also poloidal flux reverses sign spontaneously during the relaxation process. This self-reversal of the poloidal field is thought to be evidence for global helicity conservation. Taylor helicity-driven relaxed theory predicts that there exists the relaxed state of the flipped ST plasma when the TF current is reversed. We found that when q_axis passes through the q_axis =1 rational barrier in the initial phase, the ST plasma becomes unstable and relaxes to flipped states through RFP states. The n=1 mode activities are essential in the formation and sustainment of the flipped ST.

Flip-flopping binary black holes.

PubMed

Lousto, Carlos O; Healy, James

2015-04-10

We study binary spinning black holes to display the long term individual spin dynamics. We perform a full numerical simulation starting at an initial proper separation of d≈25M between equal mass holes and evolve them down to merger for nearly 48 orbits, 3 precession cycles, and half of a flip-flop cycle. The simulation lasts for t=20 000M and displays a total change in the orientation of the spin of one of the black holes from an initial alignment with the orbital angular momentum to a complete antialignment after half of a flip-flop cycle. We compare this evolution with an integration of the 3.5 post-Newtonian equations of motion and spin evolution to show that this process continuously flip flops the spin during the lifetime of the binary until merger. We also provide lower order analytic expressions for the maximum flip-flop angle and frequency. We discuss the effects this dynamics may have on spin growth in accreting binaries and on the observational consequences for galactic and supermassive binary black holes.

A Monte Carlo simulation study of associated liquid crystals

NASA Astrophysics Data System (ADS)

Berardi, R.; Fehervari, M.; Zannoni, C.

We have performed a Monte Carlo simulation study of a system of ellipsoidal particles with donor-acceptor sites modelling complementary hydrogen-bonding groups in real molecules. We have considered elongated Gay-Berne particles with terminal interaction sites allowing particles to associate and form dimers. The changes in the phase transitions and in the molecular organization and the interplay between orientational ordering and dimer formation are discussed. Particle flip and dimer moves have been used to increase the convergency rate of the Monte Carlo (MC) Markov chain.

National Dam Safety Program. Tivoli Lake Dam (Inventory Number N.Y. 52), Hudson River Basin, Rockland County, New York. Phase I Inspection Report,

DTIC Science & Technology

1980-09-30

3/8" pea gravel., Apply I coat of Uniweld or Sika Dur Hi-Mod over old concrete to insure the proper bonding. V 2. Repeat process one for section over...Bay 1. 3. Chip out cracked concrete along Bays 7 and 8, apply one coat Colma Joint Primer and fill with Colma Joint Sealer (As manufactured by Sika ) 4...deck. Cracked concrete should be repaired with Sika Dur. Hi-Mod and application of low slump nonshrink grout’ made with antihydro cement

Thin film fabrication and system integration test run for a microactuator for a tuneable lens

NASA Astrophysics Data System (ADS)

Hoheisel, Dominik; Rissing, Lutz

2014-03-01

An electromagnetic microactuator, for controlling of a tuneable lens, with an integrated electrostatic element is fabricated by thin film technology. The actuator consists of two parts: the first part with microcoil and flux guide and the second part with a ring shaped back iron on a polyimide membrane. The back iron is additionally useable as electrode for electrostatic measurement of the air gap and for electrostatic actuation. By attracting the back iron an optical liquid is displaced and forms a liquid lens inside the back iron ring covered by the membrane. For testing the thin film fabrication sequence, up-scaled systems are generated in a test run. To fabricate the flux guide in an easy and quick way, a Ni-Fe foil with a thickness of 50 μm is laminated on the Si-wafer. This foil is also utilized in the following fabrication sequence as seed layer for electroplating. Compared to Ni-Fe structures deposited by electroplating, the foil is featuring better soft magnetic properties. The foil is structured by wet chemical etching and the backside of the wafer is structured by deep reactive ion etching (DRIE). For post fabrication thinning, the polyimide membrane is treated by oxygen plasma etching. To align the back iron to the microcoil and the flux guide, a flip-chip-bonder is used during test run of system integration. To adjust a constant air gap, a water solvable polymer is tested. A two component epoxy and a polyimide based glue are compared for their bonding properties of the actuator parts.

Design and test of data acquisition systems for the Medipix2 chip based on PC standard interfaces

NASA Astrophysics Data System (ADS)

Fanti, Viviana; Marzeddu, Roberto; Piredda, Giuseppina; Randaccio, Paolo

2005-07-01

We describe two readout systems for hybrid detectors using the Medipix2 single photon counting chip, developed within the Medipix Collaboration. The Medipix2 chip (256×256 pixels, 55 μm pitch) has an active area of about 2 cm 2 and is bump-bonded to a pixel semiconductor array of silicon or other semiconductor material. The readout systems we are developing are based on two widespread standard PC interfaces: parallel port and USB (Universal Serial Bus) version 1.1. The parallel port is the simplest PC interface even if slow and the USB is a serial bus interface present nowadays on all PCs and offering good performances.

Designing Instruction for Active and Reflective Learners in the Flipped Classroom

ERIC Educational Resources Information Center

Shahnaz, Sherina Mohamed Fauzi; Hussain, Raja Maznah Raja

2016-01-01

Purpose: This paper proposes a framework of instructional strategies that would facilitate active and reflective learning processes in the flipped classroom It is aimed at allowing one's maximum potential to be reached regardless of any individual learning style. As tertiary classrooms increasingly needs to be as active and social as possible, the…

Empowering Students in the Process of Social Inquiry Learning through Flipping the Classroom

ERIC Educational Resources Information Center

Jong, Morris Siu-Yung

2017-01-01

The "flipped classroom" is an educational strategy about inverting the traditional use of in-class time for conducting lower-level learning activities and out-of-class time for conducting higher-level learning activities. "Guided social inquiry learning" (GSIL), which is a scaffolded constructivist pedagogic approach, has been…

LED Die-Bonded on the Ag/Cu Substrate by a Sn-BiZn-Sn Bonding System

NASA Astrophysics Data System (ADS)

Tang, Y. K.; Hsu, Y. C.; Lin, E. J.; Hu, Y. J.; Liu, C. Y.

2016-12-01

In this study, light emitting diode (LED) chips were die-bonded on a Ag/Cu substrate by a Sn-BixZn-Sn bonding system. A high die-bonding strength is successfully achieved by using a Sn-BixZn-Sn ternary system. At the bonding interface, there is observed a Bi-segregation phenomenon. This Bi-segregation phenomenon solves the problems of the brittle layer-type Bi at the joint interface. Our shear test results show that the bonding interface with Bi-segregation enhances the shear strength of the LED die-bonding joints. The Bi-0.3Zn and Bi-0.5Zn die-bonding cases have the best shear strength among all die-bonding systems. In addition, we investigate the atomic depth profile of the deposited Bi-xZn layer by evaporating Bi-xZn E-gun alloy sources. The initial Zn content of the deposited Bi-Zn alloy layers are much higher than the average Zn content in the deposited Bi-Zn layers.

Structural Basis for Flip-Flop Action of Thiamin Pyrophosphate-dependent Enzymes Revealed by Human Pyruvate Dehydrogenase

NASA Technical Reports Server (NTRS)

Ciszak, Ewa M.; Korotchkina, Lioubov G.; Dominiak, Paulina M.; Sidhu, Sukdeep; Patel, Mulchand S.

2003-01-01

The derivative of vitamin B1, thiamin pyrophosphate, is a cofactor of enzymes performing catalysis in pathways of energy production. In alpha (sub 2) beta (sub 2)-heterotetrameric human pyruvate dehydrogenase, this cofactor is used to cleave the C(sup alpha) -C(=O) bond of pyruvate followed by reductive acetyl transfer to lipoyl-dihydrolipoamide acetyltransferase. The dynamic nonequivalence of two, otherwise chemically equivalent, catalytic sites has not yet been understood. To understand the mechanism of action of this enzyme, we determined the crystal structure of the holo-form of human pyruvate dehydrogenase at 1.95-Angstrom resolution. We propose a model for the flip-flop action of this enzyme through a concerted approximately 2-Angstrom shuttle-like motion of its heterodimers. Similarity of thiamin pyrophosphate binding in human pyruvate dehydrogenase with functionally related enzymes suggests that this newly defined shuttle-like motion of domains is common to the family of thiamin pyrophosphate-dependent enzymes.

Alkylpurine glycosylase D employs DNA sculpting as a strategy to extrude and excise damaged bases.

PubMed

Kossmann, Bradley; Ivanov, Ivaylo

2014-07-01

Alkylpurine glycosylase D (AlkD) exhibits a unique base excision strategy. Instead of interacting directly with the lesion, the enzyme engages the non-lesion DNA strand. AlkD induces flipping of the alkylated and opposing base accompanied by DNA stack compression. Since this strategy leaves the alkylated base solvent exposed, the means to achieve enzymatic cleavage had remained unclear. We determined a minimum energy path for flipping out a 3-methyl adenine by AlkD and computed a potential of mean force along this path to delineate the energetics of base extrusion. We show that AlkD acts as a scaffold to stabilize three distinct DNA conformations, including the final extruded state. These states are almost equivalent in free energy and separated by low barriers. Thus, AlkD acts by sculpting the global DNA conformation to achieve lesion expulsion from DNA. N-glycosidic bond scission is then facilitated by a backbone phosphate group proximal to the alkylated base.

RFID and Memory Devices Fabricated Integrally on Substrates

NASA Technical Reports Server (NTRS)

Schramm, Harry F.

2004-01-01

Electronic identification devices containing radio-frequency identification (RFID) circuits and antennas would be fabricated integrally with the objects to be identified, according to a proposal. That is to say, the objects to be identified would serve as substrates for the deposition and patterning of the materials of the devices used to identify them, and each identification device would be bonded to the identified object at the molecular level. Vacuum arc vapor deposition (VAVD) is the NASA derived process for depositing layers of material on the substrate. This proposal stands in contrast to the current practice of fabricating RFID and/or memory devices as wafer-based, self-contained integrated-circuit chips that are subsequently embedded in or attached to plastic cards to make smart account-information cards and identification badges. If one relies on such a chip to store data on the history of an object to be tracked and the chip falls off or out of the object, then one loses both the historical data and the means to track the object and verify its identity electronically. Also, in contrast is the manufacturing philosophy in use today to make many memory devices. Today s methods involve many subtractive processes such as etching. This proposal only uses additive methods, building RFID and memory devices from the substrate up in thin layers. VAVD is capable of spraying silicon, copper, and other materials commonly used in electronic devices. The VAVD process sprays most metals and some ceramics. The material being sprayed has a very strong bond with the substrate, whether that substrate is metal, ceramic, or even wood, rock, glass, PVC, or paper. An object to be tagged with an identification device according to the proposal must be compatible with a vacuum deposition process. Temperature is seldom an issue as the substrate rarely reaches 150 F (66 C) during the deposition process. A portion of the surface of the object would be designated as a substrate for the deposition of the device. By use of a vacuum arc vapor deposition apparatus, a thin electrically insulating film would first be deposited on the substrate. Subsequent layers of materials would then be deposited and patterned by use of known integrated-circuit fabrication techniques. The total thickness of the deposited layers could be much less than the 100- m thickness of the thinnest state-of-the-art self-contained microchips. Such a thin deposit could be readily concealed by simply painting over it. Both large vacuum chambers for production runs and portable hand-held devices for in situ applications are available.

Wedge-shaped microfluidic chip for circulating tumor cells isolation and its clinical significance in gastric cancer.

PubMed

Yang, Chaogang; Zhang, Nangang; Wang, Shuyi; Shi, Dongdong; Zhang, Chunxiao; Liu, Kan; Xiong, Bin

2018-05-23

Circulating tumor cells (CTCs) have great potential in both basic research and clinical application for the managements of cancer. However, the complicated fabrication processes and expensive materials of the existing CTCs isolation devices, to a large extent, limit their clinical translation and CTCs' clinical value. Therefore, it remains to be urgently needed to develop a new platform for achieving CTCs detection with low-cost, mass-producible but high performance. In the present study, we introduced a novel wedge-shaped microfluidic chip (named CTC-ΔChip) fabricated by two pieces of glass through wet etching and thermal bonding technique for CTCs isolation, which achieved CTCs enrichment by different size without cell surface expression markers and CTCs identification with three-color immunocytochemistry method (CK+/CD45-/Nucleus+). We validated the feasibility of CTC-ΔChip for detecting CTCs from different types of solid tumor. Furthermore, we applied the newly-developed platform to investigate the clinical significance of CTCs in gastric cancer (GC). Based on "label-free" characteristic, the capture efficiency of CTC-ΔChip can be as high as 93.7 ± 3.2% in DMEM and 91.0 ± 3.0% in whole blood sample under optimized conditions. Clinically, CTC-ΔChip exhibited the feasibility of detecting CTCs from different types of solid tumor, and it identified 7.30 ± 7.29 CTCs from 2 mL peripheral blood with a positive rate of 75% (30/40) in GC patients. Interestingly, we found that GC CTCs count was significantly correlated with multiple systemic inflammation indexes, including the lymphocyte count, platelet count, the level of neutrophil to lymphocyte ratio and platelet to lymphocyte ratio. In addition, we also found that both the positivity rate and CTCs count were significantly associated with multiple clinicopathology parameters. Our novel CTC-ΔChip shows high performance for detecting CTCs from less volume of blood samples of cancer patients and important clinical significance in GC. Owing to the advantages of low-cost and mass-producible, CTC-ΔChip holds great potential of clinical application for cancer therapeutic guidance and prognostic monitoring in the future.

Improved fabrication techniques for infrared bolometers

NASA Technical Reports Server (NTRS)

Lange, A. E.; Mcbride, S. E.; Richards, P. L.; Haller, E. E.; Kreysa, E.

1983-01-01

Ion implantation and sputter metallization are used to produce ohmic electrical contacts to Ge:Ga chips. The method is shown to give a high yield of small monolithic bolometers with very little low-frequency noise. It is noted that when one of the chips is used as the thermometric element of a composite bolometer it must be bonded to a dielectric substrate. The thermal resistance of the conventional epoxy bond is measured and found to be undesirably large. A procedure for soldering the chip to a metallized portion of the substrate in such a way as to reduce this resistance is outlined. An evaluation is made of the contribution of the metal film absorber to the heat capacity of a composite bolometer. It is found that the heat capacity of a NiCr absorber at 1.3 K can dominate the bolometer performance. A Bi absorber possesses significantly lower heat capacity. A low-temperature blackbody calibrator is built to measure the optical responsivity of bolometers. A composite bolometer system with a throughput of approximately 0.1 sr sq cm is constructed using the new techniques. The noise in this bolometer is white above 2.5 Hz and is slightly below the value predicted by thermodynamic equilibrium theory.

Packaging Technologies for 500C SiC Electronics and Sensors

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu

2013-01-01

Various SiC electronics and sensors are currently under development for applications in 500C high temperature environments such as hot sections of aerospace engines and the surface of Venus. In order to conduct long-term test and eventually commercialize these SiC devices, compatible packaging technologies for the SiC electronics and sensors are required. This presentation reviews packaging technologies developed for 500C SiC electronics and sensors to address both component and subsystem level packaging needs for high temperature environments. The packaging system for high temperature SiC electronics includes ceramic chip-level packages, ceramic printed circuit boards (PCBs), and edge-connectors. High temperature durable die-attach and precious metal wire-bonding are used in the chip-level packaging process. A high temperature sensor package is specifically designed to address high temperature micro-fabricated capacitive pressure sensors for high differential pressure environments. This presentation describes development of these electronics and sensor packaging technologies, including some testing results of SiC electronics and capacitive pressure sensors using these packaging technologies.

A Compact Polarization Imager

NASA Technical Reports Server (NTRS)

Thompson, Karl E.; Rust, David M.; Chen, Hua

1995-01-01

A new type of image detector has been designed to analyze the polarization of light simultaneously at all picture elements (pixels) in a scene. The Integrated Dual Imaging Detector (IDID) consists of a polarizing beamsplitter bonded to a custom-designed charge-coupled device with signal-analysis circuitry, all integrated on a silicon chip. The IDID should simplify the design and operation of imaging polarimeters and spectroscopic imagers used, for example, in atmospheric and solar research. Other applications include environmental monitoring and robot vision. Innovations in the IDID include two interleaved 512 x 1024 pixel imaging arrays (one for each polarization plane), large dynamic range (well depth of 10(exp 6) electrons per pixel), simultaneous readout and display of both images at 10(exp 6) pixels per second, and on-chip analog signal processing to produce polarization maps in real time. When used with a lithium niobate Fabry-Perot etalon or other color filter that can encode spectral information as polarization, the IDID can reveal tiny differences between simultaneous images at two wavelengths.

3D interconnect metrology in CMS/ITRI

NASA Astrophysics Data System (ADS)

Ku, Y. S.; Shyu, D. M.; Hsu, W. T.; Chang, P. Y.; Chen, Y. C.; Pang, H. L.

2011-05-01

Semiconductor device packaging technology is rapidly advancing, in response to the demand for thinner and smaller electronic devices. Three-dimensional chip/wafer stacking that uses through-silicon vias (TSV) is a key technical focus area, and the continuous development of this novel technology has created a need for non-contact characterization. Many of these challenges are novel to the industry due to the relatively large variety of via sizes and density, and new processes such as wafer thinning and stacked wafer bonding. This paper summarizes the developing metrology that has been used during via-middle & via-last TSV process development at EOL/ITRI. While there is a variety of metrology and inspection applications for 3D interconnect processing, the main topics covered here are via CD/depth measurement, thinned wafer inspection and wafer warpage measurement.

Chip-package nano-structured copper and nickel interconnections with metallic and polymeric bonding interfaces

NASA Astrophysics Data System (ADS)

Aggarwal, Ankur

With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 that support computing speed in terabits per second, with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Decreasing I/O pitch together with low cost, high electrical performance and high reliability are the key technological challenges identified by the 2005 International Technology Roadmap for Semiconductors (ITRS). Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. In addition, the materials must be environmentally-friendly, corrosion resistant, thermally stable over a long time, and resistant to electro-migration. A major challenge is also to develop economic processes that can be integrated into back end of the wafer foundry, i.e. with wafer level packaging. Device-to-system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches of the order of 30 microns and less. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. A novel chip-package interconnection technology is developed to address the IC packaging requirements beyond the ITRS projections and to introduce innovative design and fabrication concepts that will further advance the performance of the chip, the package, and the system board. The nano-structured interconnect technology simultaneously packages all the ICs intact in wafer form with quantum jump in the number of interconnections with the lowest electrical parasitics. The intrinsic properties of nano materials also enable several orders of magnitude higher interconnect densities with the best mechanical properties for the highest reliability and yet provide higher current and heat transfer densities. Nano-structured interconnects provides the ability to assemble the packaged parts on the system board without the use of underfill materials and to enable advanced analog/digital testing, reliability testing, and burn-in at wafer level. This thesis investigates the electrical and mechanical performance of nanostructured interconnections through modeling and test vehicle fabrication. The analytical models evaluate the performance improvements over solder and compliant interconnections. Test vehicles with nano-interconnections were fabricated using low cost electro-deposition techniques and assembled with various bonding interfaces. Interconnections were fabricated at 200 micron pitch to compare with the existing solder joints and at 50 micron pitch to demonstrate fabrication processes at fine pitches. Experimental and modeling results show that the proposed nano-interconnections could enhance the reliability and potentially meet all the system performance requirements for the emerging micro/nano-systems.

Localized heating and bonding technique for MEMS packaging

NASA Astrophysics Data System (ADS)

Cheng, Yu-Ting

Localized heating and bonding techniques have been developed for hermetic and vacuum packaging of MEMS devices, including silicon-to-glass fusion, silicon-gold eutectic, and silicon-to-glass bonding using PSG, indium, aluminum, and aluminum/silicon alloy as the intermediate layer. Line shaped phosphorus-doped polysilicon or gold films are used as resistive microheaters to provide enough thermal energy for bonding. The bonding processes are conducted in the common environment of room temperature and atmospheric pressure and can achieve bonding strength comparable to the fracture toughness of bulk silicon in less than 10 minutes. About 5 watts of input power is needed for localized bonding which can seal a 500 x 500 mum2 area. The total input power is determined by the thermal properties of bonding materials, including the heat capacity and latent heat. Two important bonding results are obtained: (1) The surface step created by the electrical interconnect line can be planarized by reflowing the metal solder. (2) Small applied pressure, less than 1MPa, for intimate contact reduces mechanical damage to the device substrate. This new class of bonding technology has potential applications for MEMS fabrication and packaging that require low temperature processing at the wafer level, excellent bonding strength and hermetic sealing characteristics. A hermetic package based on localized aluminum/silicon-to-glass bonding has been successfully fabricated. Less than 0.2 MPa contact pressure with 46mA input current for two parallel 3.5mum wide polysilicon on-chip microheaters can create as high as 700°C bonding temperature and achieve a strong and reliable bond in 7.5 minutes. Accelerated testing in an autoclave shows some packages survive more than 450 hours under 3 atm, 100%RH and 128°C. Premature failure has been attributed to some unbonded regions on the failed samples. The bonding yield and reliability have been improved by increasing bonding time and applied pressure. Finally, vacuum encapsulation of folded-beam comb-drive mu-resonators used as pressure monitors has been demonstrated using localized aluminum/silicon-to-glass bonding. With 3.4 watt heating power, ˜0.2MPa applied contact pressure, and 90 minutes wait time before bonding, vacuum encapsulation can be achieved with the same vacuum level as the packaging environment which is about 25 mtorr. Metal coating used as diffusion barrier and a longer wait time before bonding are used to improve the vacuum level of the package. Long-term measurement of the Q of un-annealed vacuum-packaged mu-resonators, illustrates stable operation after 19 weeks.

A Comparison between Shear Bond Strength of VMK Master Porcelain with Three Base-metal Alloys (Ni-cr-T3, VeraBond, Super Cast) and One Noble Alloy (X-33) in Metal-ceramic Restorations

PubMed Central

Ahmadzadeh, A; Neshati, A; Mousavi, N; Epakchi, S; Dabaghi Tabriz, F; Sarbazi, AH

2013-01-01

Statement of Problem: The increase in the use of metal-ceramic restorations and a high prevalence of porcelain chipping entails introducing an alloy which is more compatible with porcelain and causes a stronger bond between the two. This study is to compare shear bond strength of three base-metal alloys and one noble alloy with the commonly used VMK Master Porcelain. Materials and Method: Three different groups of base-metal alloys (Ni-cr-T3, Super Cast, and VeraBond) and one group of noble alloy (X-33) were selected. Each group consisted of 15 alloy samples. All groups went through the casting process and change from wax pattern into metal disks. The VMK Master Porcelain was then fired on each group. All the specimens were put in the UTM; a shear force was loaded until a fracture occurred and the fracture force was consequently recorded. The data were analyzed by SPSS Version 16 and One-Way ANOVA was run to compare the shear strength between the groups. Furthermore, the groups were compared two-by-two by adopting Tukey test. Results: The findings of this study revealed shear bond strength of Ni-Cr-T3 alloy was higher than the three other alloys (94 MPa or 330 N). Super Cast alloy had the second greatest shear bond strength (80. 87Mpa or 283.87 N). Both VeraBond (69.66 MPa or 245 N) and x-33 alloys (66.53 MPa or 234 N) took the third place. Conclusion: Ni-Cr-T3 with VMK Master Porcelain has the greatest shear bond strength. Therefore, employment of this low-cost alloy is recommended in metal-ceramic restorations. PMID:24724144

Development of low fat potato chips through microwave processing.

PubMed

Joshi, A; Rudra, S G; Sagar, V R; Raigond, P; Dutt, S; Singh, B; Singh, B P

2016-08-01

Since snacks high in fats are known to be a significant source of fat and energy intake, these have been put in high dietary restraint category. Therefore, an attempt was made to process potato chips through microwave processing without incorporation of any oil in potato chips. Microwave processing of potato chips was done using microwave power varying from 180 to 600 W using constant sample size. Among eleven different drying models, Parabolic model was found to be the best fit through non-linear regression analysis to illustrate drying kinetics of potato chips. The structural, textural and colour attributes of microwaved potato chips were similar to commercial fried potato chips. It was found that at 600 W after 2.5-3.0 min of processing, potato chips gained the fracturability and crispiness index as that of commercial fried chips. Microwave processing was found suitable for processing of potato chips with low fat content (~3.09 vs 35.5 % in commercial preparation) and with acceptable sensory scores (≥7.6 on 9.0 point on hedonic scale vs 8.0 of control preparation).

New On-board Microprocessors

NASA Astrophysics Data System (ADS)

Weigand, R.

Two new processor devices have been developed for the use on board of spacecrafts. An 8-bit 8032-microcontroller targets typical controlling applications in instruments and sub-systems, or could be used as a main processor on small satellites, whereas the LEON 32-bit SPARC processor can be used for high performance controlling and data processing tasks. The ADV80S32 is fully compliant to the Intel 80x1 architecture and instruction set, extended by additional peripherals, 512 bytes on-chip RAM and a bootstrap PROM, which allows downloading the application software using the CCSDS PacketWire pro- tocol. The memory controller provides a de-multiplexed address/data bus, and allows to access up to 16 MB data and 8 MB program RAM. The peripherals have been de- signed for the specific needs of a spacecraft, such as serial interfaces compatible to RS232, PacketWire and TTC-B-01, counters/timers for extended duration and a CRC calculation unit accelerating the CCSDS TM/TC protocol. The 0.5 um Atmel manu- facturing technology (MG2RT) provides latch-up and total dose immunity; SEU fault immunity is implemented by using SEU hardened Flip-Flops and EDAC protection of internal and external memories. The maximum clock frequency of 20 MHz allows a processing power of 3 MIPS. Engineering samples are available. For SW develop- ment, various SW packages for the 8051 architecture are on the market. The LEON processor implements a 32-bit SPARC V8 architecture, including all the multiply and divide instructions, complemented by a floating-point unit (FPU). It includes several standard peripherals, such as timers/watchdog, interrupt controller, UARTs, parallel I/Os and a memory controller, allowing to use 8, 16 and 32 bit PROM, SRAM or memory mapped I/O. With on-chip separate instruction and data caches, almost one instruction per clock cycle can be reached in some applications. A 33-MHz 32-bit PCI master/target interface and a PCI arbiter allow operating the device in a plug-in card (for SW development on PC etc.), or to consider using it as a PCI master controller in an on-board system. Advanced SEU fault tolerance is in- troduced by design, using triple modular redundancy (TMR) flip-flops for all registers and EDAC protection for all memories. The device will be manufactured in a radia- tion hard Atmel 0.25 um technology, targeting 100 MHz processor clock frequency. The non fault-tolerant LEON processor VHDL model is available as free source code, and the SPARC architecture is a well-known industry standard. Therefore, know-how, software tools and operating systems are widely available.

Design and Fabrication of an Implantable Cortical Semiconductor Integrated Circuit Electrode Array

DTIC Science & Technology

1990-12-01

25 Array Pads....................25 Polyimide ....................26 III. METHODOLOGY.........................27 Brain Chip Electronics...38 Ionic Permeation. .................. 38 Polyimide . ................... 38 Implantation. .................... 39 Wire Bonding...53 Pad Sensitivity ................. 53 Ionic Permeat:.on. .................. 54 Polyimide . ................... 54 Implantation

DNA decorated carbon nanotube sensors on CMOS circuitry for environmental monitoring

NASA Astrophysics Data System (ADS)

Liu, Yu; Chen, Chia-Ling; Agarwal, V.; Li, Xinghui; Sonkusale, S.; Dokmeci, Mehmet R.; Wang, Ming L.

2010-04-01

Single-walled carbon nanotubes (SWNTs) with their large surface area, high aspect ratio are one of the novel materials which have numerous attractive features amenable for high sensitivity sensors. Several nanotube based sensors including, gas, chemical and biosensors have been demonstrated. Moreover, most of these sensors require off chip components to detect the variations in the signals making them complicated and hard to commercialize. Here we present a novel complementary metal oxide semiconductor (CMOS) integrated carbon nanotube sensors for portable high sensitivity chemical sensing applications. Multiple zincation steps have been developed to ascertain proper electrical connectivity between the carbon nanotubes and the foundry made CMOS circuitry. The SWNTs have been integrated onto (CMOS) circuitry as the feedback resistor of a Miller compensated operational amplifier utilizing low temperature Dielectrophoretic (DEP) assembly process which has been tailored to be compatible with the post-CMOS integration at the die level. Building nanotube sensors directly on commercial CMOS circuitry allows single chip solutions eliminating the need for long parasitic lines and numerous wire bonds. The carbon nanotube sensors realized on CMOS circuitry show strong response to various vapors including Dimethyl methylphosphonate and Dinitrotoluene. The remarkable set of attributes of the SWNTs realized on CMOS electronic chips provides an attractive platform for high sensitivity portable nanotube based bio and chemical sensors.

A battery-free multichannel digital neural/EMG telemetry system for flying insects.

PubMed

Thomas, Stewart J; Harrison, Reid R; Leonardo, Anthony; Reynolds, Matthew S

2012-10-01

This paper presents a digital neural/EMG telemetry system small enough and lightweight enough to permit recording from insects in flight. It has a measured flight package mass of only 38 mg. This system includes a single-chip telemetry integrated circuit (IC) employing RF power harvesting for battery-free operation, with communication via modulated backscatter in the UHF (902-928 MHz) band. An on-chip 11-bit ADC digitizes 10 neural channels with a sampling rate of 26.1 kSps and 4 EMG channels at 1.63 kSps, and telemeters this data wirelessly to a base station. The companion base station transceiver includes an RF transmitter of +36 dBm (4 W) output power to wirelessly power the telemetry IC, and a digital receiver with a sensitivity of -70 dBm for 10⁻⁵ BER at 5.0 Mbps to receive the data stream from the telemetry IC. The telemetry chip was fabricated in a commercial 0.35 μ m 4M1P (4 metal, 1 poly) CMOS process. The die measures 2.36 × 1.88 mm, is 250 μm thick, and is wire bonded into a flex circuit assembly measuring 4.6 × 6.8 mm.

Bench-Top Fabrication of an All-PDMS Microfluidic Electrochemical Cell Sensor Integrating Micro/Nanostructured Electrodes.

PubMed

Saem, Sokunthearath; Zhu, Yujie; Luu, Helen; Moran-Mirabal, Jose

2017-03-31

In recent years, efforts in the development of lab-on-a-chip (LoC) devices for point-of-care (PoC) applications have increased to bring affordable, portable, and sensitive diagnostics to the patients' bedside. To reach this goal, research has shifted from using traditional microfabrication methods to more versatile, rapid, and low-cost options. This work focuses on the benchtop fabrication of a highly sensitive, fully transparent, and flexible poly (dimethylsiloxane) (PDMS) microfluidic (μF) electrochemical cell sensor. The μF device encapsulates 3D structured gold and platinum electrodes, fabricated using a shape-memory polymer shrinking method, which are used to set up an on-chip electrochemical cell. The PDMS to PDMS-structured electrode bonding protocol to fabricate the μF chip was optimized and found to have sufficient bond strength to withstand up to 100 mL/min flow rates. The sensing capabilities of the on-chip electrochemical cell were demonstrated by using cyclic voltammetry to monitor the adhesion of murine 3T3 fibroblasts in the presence of a redox reporter. The charge transfer across the working electrode was reduced upon cell adhesion, which was used as the detection mechanism, and allowed the detection of as few as 24 cells. The effective utilization of simple and low cost bench-top fabrication methods could accelerate the prototyping and development of LoC technologies and bring PoC diagnostics and personalized medicine to the patients' bedside.

Bench-Top Fabrication of an All-PDMS Microfluidic Electrochemical Cell Sensor Integrating Micro/Nanostructured Electrodes

PubMed Central

Saem, Sokunthearath; Zhu, Yujie; Luu, Helen; Moran-Mirabal, Jose

2017-01-01

In recent years, efforts in the development of lab-on-a-chip (LoC) devices for point-of-care (PoC) applications have increased to bring affordable, portable, and sensitive diagnostics to the patients’ bedside. To reach this goal, research has shifted from using traditional microfabrication methods to more versatile, rapid, and low-cost options. This work focuses on the benchtop fabrication of a highly sensitive, fully transparent, and flexible poly (dimethylsiloxane) (PDMS) microfluidic (μF) electrochemical cell sensor. The μF device encapsulates 3D structured gold and platinum electrodes, fabricated using a shape-memory polymer shrinking method, which are used to set up an on-chip electrochemical cell. The PDMS to PDMS-structured electrode bonding protocol to fabricate the μF chip was optimized and found to have sufficient bond strength to withstand up to 100 mL/min flow rates. The sensing capabilities of the on-chip electrochemical cell were demonstrated by using cyclic voltammetry to monitor the adhesion of murine 3T3 fibroblasts in the presence of a redox reporter. The charge transfer across the working electrode was reduced upon cell adhesion, which was used as the detection mechanism, and allowed the detection of as few as 24 cells. The effective utilization of simple and low cost bench-top fabrication methods could accelerate the prototyping and development of LoC technologies and bring PoC diagnostics and personalized medicine to the patients’ bedside. PMID:28362329

Flow lithography in ultraviolet-curable polydimethylsiloxane microfluidic chips

PubMed Central

Kim, Junbeom; An, Heseong; Seo, Yoojin; Jung, Youngmee; Lee, Jong Suk; Bong, Ki Wan

2017-01-01

Flow Lithography (FL) is the technique used for the synthesis of hydrogel microparticles with various complex shapes and distinct chemical compositions by combining microfluidics with photolithography. Although polydimethylsiloxane (PDMS) has been used most widely as almost the sole material for FL, PDMS microfluidic chips have limitations: (1) undesired shrinkage due to the thermal expansion of masters used for replica molding and (2) interfacial delamination between two thermally cured PDMS layers. Here, we propose the utilization of ultraviolet (UV)-curable PDMS (X-34-4184) for FL as an excellent alternative material of the conventional PDMS. Our proposed utilization of the UV-curable PDMS offers three key advantages, observed in our study: (1) UV-curable PDMS exhibited almost the same oxygen permeability as the conventional PDMS. (2) The almost complete absence of shrinkage facilitated the fabrication of more precise reverse duplication of microstructures. (3) UV-cured PDMS microfluidic chips were capable of much stronger interfacial bonding so that the burst pressure increased to ∼0.9 MPa. Owing to these benefits, we demonstrated a substantial improvement of productivity in synthesizing polyethylene glycol diacrylate microparticles via stop flow lithography, by applying a flow time (40 ms) an order of magnitude shorter. Our results suggest that UV-cured PDMS chips can be used as a general platform for various types of flow lithography and also be employed readily in other applications where very precise replication of structures on micro- or sub-micrometer scales and/or strong interfacial bonding are desirable. PMID:28469763

The Flipped Classroom, Disruptive Pedagogies, Enabling Technologies and Wicked Problems: Responding to "The Bomb in the Basement"

ERIC Educational Resources Information Center

Hutchings, Maggie; Quinney, Anne

2015-01-01

The adoption of enabling technologies by universities provides unprecedented opportunities for flipping the classroom to achieve student-centred learning. While higher education policies focus on placing students at the heart of the education process, the propensity for student identities to shift from partners in learning to consumers of…

Flipping the Educational System: Putting Teachers at the Heart of Teaching

ERIC Educational Resources Information Center

Kneyber, René

2014-01-01

This article describes an initiative led by two classroom teachers from the Netherlands to put teachers back at the centre of the educational process. The article argues that the educational system has become inverted, with those who are most influential (teachers) having the least opportunity to influence. The challenge is to "flip the…

Phonon-mediated spin-flipping mechanism in the spin ices Dy 2 Ti 2 O 7 and Ho 2 Ti 2 O 7

DOE PAGES

Ruminy, M.; Chi, S.; Calder, S.; ...

2017-02-21

To understand emergent magnetic monopole dynamics in the spin ices Ho 2Ti 2O 7 and Dy 2Ti 2O 7, it is necessary to investigate the mechanisms by which spins flip in these materials. Presently there are thought to be two processes: quantum tunneling at low and intermediate temperatures and thermally activated at high temperatures. We identify possible couplings between crystal field and optical phonon excitations and construct a strictly constrained model of phonon-mediated spin flipping that quantitatively describes the high-temperature processes in both compounds, as measured by quasielastic neutron scattering. We support the model with direct experimental evidence of themore » coupling between crystal field states and optical phonons in Ho 2Ti 2O 7.« less

Characterizing structural transitions using localized free energy landscape analysis.

PubMed

Banavali, Nilesh K; Mackerell, Alexander D

2009-01-01

Structural changes in molecules are frequently observed during biological processes like replication, transcription and translation. These structural changes can usually be traced to specific distortions in the backbones of the macromolecules involved. Quantitative energetic characterization of such distortions can greatly advance the atomic-level understanding of the dynamic character of these biological processes. Molecular dynamics simulations combined with a variation of the Weighted Histogram Analysis Method for potential of mean force determination are applied to characterize localized structural changes for the test case of cytosine (underlined) base flipping in a GTCAGCGCATGG DNA duplex. Free energy landscapes for backbone torsion and sugar pucker degrees of freedom in the DNA are used to understand their behavior in response to the base flipping perturbation. By simplifying the base flipping structural change into a two-state model, a free energy difference of upto 14 kcal/mol can be attributed to the flipped state relative to the stacked Watson-Crick base paired state. This two-state classification allows precise evaluation of the effect of base flipping on local backbone degrees of freedom. The calculated free energy landscapes of individual backbone and sugar degrees of freedom expectedly show the greatest change in the vicinity of the flipping base itself, but specific delocalized effects can be discerned upto four nucleotide positions away in both 5' and 3' directions. Free energy landscape analysis thus provides a quantitative method to pinpoint the determinants of structural change on the atomic scale and also delineate the extent of propagation of the perturbation along the molecule. In addition to nucleic acids, this methodology is anticipated to be useful for studying conformational changes in all macromolecules, including carbohydrates, lipids, and proteins.

Microfabricated electrochemical sensors for combustion applications

NASA Astrophysics Data System (ADS)

Vulcano Rossi, Vitor A.; Mullen, Max R.; Karker, Nicholas A.; Zhao, Zhouying; Kowarz, Marek W.; Dutta, Prabir K.; Carpenter, Michael A.

2015-05-01

A new design for the miniaturization of an existing oxygen sensor is proposed based on the application of silicon microfabrication technologies to a cm sized O2 sensor demonstrated by Argonne National Laboratory and The Ohio State University which seals a metal/metal oxide within the structure to provide an integrated oxygen reference. The structural and processing changes suggested will result in a novel MEMS-based device meeting the semiconductor industry standards for cost efficiency and mass production. The MEMS design requires thin film depositions to create a YSZ membrane, palladium oxide reference and platinum electrodes. Pt electrodes are studied under operational conditions ensuring film conductivity over prolonged usage. SEM imaging confirms void formation after extended tests, consistent with the literature. Furthermore, hydrophilic bonding of pairs of silicon die samples containing the YSZ membrane and palladium oxide is discussed in order to create hermetic sealed cavities for oxygen reference. The introduction of tensile Si3N4 films to the backside of the silicon die generates bowing of the chips, compromising bond quality. This effect is controlled through the application of pressure during the initial bonding stages. In addition, KOH etching of the bonded die samples is discussed, and a YSZ membrane that survives the etching step is characterized by Raman spectroscopy.

Amplifier Module for 260-GHz Band Using Quartz Waveguide Transitions

NASA Technical Reports Server (NTRS)

Padmanabhan, Sharmila; Fung, King Man; Kangaslahti, Pekka P.; Peralta, Alejandro; Soria, Mary M.; Pukala, David M.; Sin, Seth; Samoska, Lorene A.; Sarkozy, Stephen; Lai, Richard

2012-01-01

Packaging of MMIC LNA (monolithic microwave integrated circuit low-noise amplifier) chips at frequencies over 200 GHz has always been problematic due to the high loss in the transition between the MMIC chip and the waveguide medium in which the chip will typically be used. In addition, above 200 GHz, wire-bond inductance between the LNA and the waveguide can severely limit the RF matching and bandwidth of the final waveguide amplifier module. This work resulted in the development of a low-loss quartz waveguide transition that includes a capacitive transmission line between the MMIC and the waveguide probe element. This capacitive transmission line tunes out the wirebond inductance (where the wire-bond is required to bond between the MMIC and the probe element). This inductance can severely limit the RF matching and bandwidth of the final waveguide amplifier module. The amplifier module consists of a quartz E-plane waveguide probe transition, a short capacitive tuning element, a short wire-bond to the MMIC, and the MMIC LNA. The output structure is similar, with a short wire-bond at the output of the MMIC, a quartz E-plane waveguide probe transition, and the output waveguide. The quartz probe element is made of 3-mil quartz, which is the thinnest commercially available material. The waveguide band used is WR4, from 170 to 260 GHz. This new transition and block design is an improvement over prior art because it provides for better RF matching, and will likely yield lower loss and better noise figure. The development of high-performance, low-noise amplifiers in the 180-to- 700-GHz range has applications for future earth science and planetary instruments with low power and volume, and astrophysics array instruments for molecular spectroscopy. This frequency band, while suitable for homeland security and commercial applications (such as millimeter-wave imaging, hidden weapons detection, crowd scanning, airport security, and communications), also has applications to future NASA missions. The Global Atmospheric Composition Mission (GACM) in the NRC Decadel Survey will need low-noise amplifiers with extremely low noise temperatures, either at room temperature or for cryogenic applications, for atmospheric remote sensing.

An Integrative Review of Flipped Classroom Teaching Models in Nursing Education.

PubMed

Njie-Carr, Veronica P S; Ludeman, Emilie; Lee, Mei Ching; Dordunoo, Dzifa; Trocky, Nina M; Jenkins, Louise S

Nursing care is changing dramatically given the need for students to address complex and multiple patient comorbidities. Students experience difficulties applying knowledge gained from didactic instruction to make important clinical decisions for optimal patient care. To optimize nursing education pedagogy, innovative teaching strategies are required to prepare future nurses for practice. This integrative review synthesized the state of the science on flipped classroom models from 13 empirical studies published through May 2016. The purpose of the review was to evaluate studies conducted on flipped classroom models among nursing students using a validated framework by Whittemore and Knafl. Multiple academic databases were searched, ranging in scope including PubMed, Embase (Elsevier), CINAHL (Ebsco), Scopus, Web of Science, and Google Scholar, resulting in 95 unique records. After screening and full-text reviews, 82 papers were removed. Thirteen empirical studies were included in the final analysis and results provided (a) design and process information on flipped classroom models in nursing education, (b) a summary of the state of the evidence to inform the implementation of flipped classrooms, and (c) a foundation to build future research in this area of nursing education. To develop sound evidence-based teaching strategies, rigorous scientific methods are needed to inform the implementation of flipped classroom approaches. Copyright © 2016 Elsevier Inc. All rights reserved.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Murray, E.; Floether, F. F.; Cavendish Laboratory, University of Cambridge, J.J. Thomson Avenue, Cambridge CB3 0HE

Fundamental to integrated photonic quantum computing is an on-chip method for routing and modulating quantum light emission. We demonstrate a hybrid integration platform consisting of arbitrarily designed waveguide circuits and single-photon sources. InAs quantum dots (QD) embedded in GaAs are bonded to a SiON waveguide chip such that the QD emission is coupled to the waveguide mode. The waveguides are SiON core embedded in a SiO{sub 2} cladding. A tuneable Mach Zehnder interferometer (MZI) modulates the emission between two output ports and can act as a path-encoded qubit preparation device. The single-photon nature of the emission was verified using themore » on-chip MZI as a beamsplitter in a Hanbury Brown and Twiss measurement.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shin, Heekeun; Schwarze, A; Diehl, R D

Earlier studies of C60 adsorption on Au(111) reported many interesting and complex features. We have performed coordinated low-energy electron diffraction, scanning tunneling microscopy (STM), and density functional theory studies to elucidate some of the details of the monolayer commensurate (2√3 × 2√3)R30° phase. We have identified the adsorption geometries of the two states that image as dim and bright in STM. These consist of a C60 molecule with a hexagon side down in a vacancy (hex-vac) and a C60 molecule with a carbon-carbon 6:6 bond down on a top site (6:6-top), respectively. We have studied the detailed geometries of thesemore » states and find that there is little distortion of the C60 molecules, but there is a rearrangement of the substrate near the C60 molecules. The two types of molecules differ in height, by about 0.7 Å, which accounts for most of the difference in their contrast in the STM images. The monolayer displays dynamical behavior, in which the molecules flip from bright to dim, and vice versa. We interpret this flipping as the result of the diffusion of vacancies in the surface layers of the substrate. Our measurements of the dynamics of this flipping from one state to the other indicate that the activation energy is 0.66 ± 0.03 eV for flips that involve nearest-neighbor C60 molecules, and 0.93 ± 0.03 for more distant flips. Based on calculated activation energies for vacancies diffusing in Au, we interpret these to be a result of surface vacancy diffusion and bulk vacancy diffusion. These results are compared to the similar system of Ag(111)-(2√3 × 2√3)R30°-C60. In both systems, the formation of the commensurate C60 monolayer produces a large number of vacancies in the top substrate layer that are highly mobile, effectively melting the interfacial metal layer at temperatures well below their normal melting temperatures.« less

Large area MEMS based ultrasound device for cancer detection

NASA Astrophysics Data System (ADS)

Wodnicki, Robert; Thomenius, Kai; Ming Hooi, Fong; Sinha, Sumedha P.; Carson, Paul L.; Lin, Der-Song; Zhuang, Xuefeng; Khuri-Yakub, Pierre; Woychik, Charles

2011-08-01

We present image results obtained using a prototype ultrasound array that demonstrates the fundamental architecture for a large area MEMS based ultrasound device for detection of breast cancer. The prototype array consists of a tiling of capacitive Micromachined Ultrasound Transducers (cMUTs) that have been flip-chip attached to a rigid organic substrate. The pitch on the cMUT elements is 185 μm and the operating frequency is nominally 9 MHz. The spatial resolution of the new probe is comparable to those of production PZT probes; however the sensitivity is reduced by conditions that should be correctable. Simulated opposed-view image registration and Speed of Sound volume reconstruction results for ultrasound in the mammographic geometry are also presented.

Distinct constrictive processes, separated in time and space, divide caulobacter inner and outer membranes.

PubMed

Judd, Ellen M; Comolli, Luis R; Chen, Joseph C; Downing, Kenneth H; Moerner, W E; McAdams, Harley H

2005-10-01

Cryoelectron microscope tomography (cryoEM) and a fluorescence loss in photobleaching (FLIP) assay were used to characterize progression of the terminal stages of Caulobacter crescentus cell division. Tomographic cryoEM images of the cell division site show separate constrictive processes closing first the inner membrane (IM) and then the outer membrane (OM) in a manner distinctly different from that of septum-forming bacteria. FLIP experiments had previously shown cytoplasmic compartmentalization (when cytoplasmic proteins can no longer diffuse between the two nascent progeny cell compartments) occurring 18 min before daughter cell separation in a 135-min cell cycle so the two constrictive processes are separated in both time and space. In the very latest stages of both IM and OM constriction, short membrane tether structures are observed. The smallest observed pre-fission tethers were 60 nm in diameter for both the inner and outer membranes. Here, we also used FLIP experiments to show that both membrane-bound and periplasmic fluorescent proteins diffuse freely through the FtsZ ring during most of the constriction procession.