Implementation of the Timepix ASIC in the Scalable Readout System

NASA Astrophysics Data System (ADS)

Lupberger, M.; Desch, K.; Kaminski, J.

2016-09-01

We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

Analog front-end design of the STS/MUCH-XYTER2—full size prototype ASIC for the CBM experiment

NASA Astrophysics Data System (ADS)

Kleczek, Rafal

2017-01-01

The design of the analog front-end of the STS/MUCH-XYTER2 ASIC, a full-size prototype chip for the Silicon Tracking System (STS, based on double-sided silicon strip sensors) and Muon Chamber (MUCH, based on gas sensors) detectors is presented. The ASIC contains 128 charge processing channels, each built of a charge sensitive amplifier, a polarity selection circuit and two pulse shaping amplifiers forming two parallel signal paths. The first path is used for timing measurement with a fast discriminator. The second path allows low-noise amplitude measurement with a 5-bit continuous-time flash ADC. Different operating conditions and constraints posed by two target detectors' applications require front-end electronics flexibility to meet extended system-wise requirements. The presented circuit implements switchable shaper peaking time, gain switching and trimming, input amplifier pulsed reset circuit, fail-safe measures. The power consumption is scalable (for the STS and the MUCH modes), but limited to 10 mW/channel.

A front-end readout mixed chip for high-efficiency small animal PET imaging

NASA Astrophysics Data System (ADS)

Ollivier-Henry, N.; Berst, J. D.; Colledani, C.; Hu-Guo, Ch.; Mbow, N. A.; Staub, D.; Guyonnet, J. L.; Hu, Y.

2007-02-01

Today, the main challenge of Positron Emission Tomography (PET) systems dedicated to small animal imaging is to obtain high detection efficiency and a highly accurate localization of radioisotopes. If we focus only on the PET characteristics such as the spatial resolution, its accuracy depends on the design of detector and on the electronics readout system as well. In this paper, we present a new design of such readout system with full custom submicrometer CMOS implementation. The front end chip consists of two main blocks from which the energy information and the time stamp with subnanosecond resolution can be obtained. In our A Multi-Modality Imaging System for Small Animal (AMISSA) PET system design, a matrix of LYSO crystals has to be read at each end by a 64 channels multianode photomultiplier tube. A specific readout electronic has been developed at the Hubert Curien Multidisciplinary Institute (IPHC, France). The architecture of this readout for the energy information detection is composed of a low-noise preamplifier, a CR-RC shaper and an analogue memory. In order to obtain the required dynamic range from 15 to 650 photoelectrons with good linearity, a current mode approach has been chosen for the preamplifier. To detect the signal with a temporal resolution of 1 ns, a comparator with a very low threshold (˜0.3 photoelectron) has been implemented. It gives the time reference of arrival signal coming from the detector. In order to obtain the time coincidence with a temporal resolution of 1 ns, a Time-to-Digital Converter (TDC) based on a Delay-Locked-Loop (DLL) has been designed. The chip is fabricated with AMS 0.35 μm process. The ASIC architecture and some simulation results will be presented in the paper.

Design of a Multi-Channel Front-End Readout ASIC With Low Noise and Large Dynamic Input Range for APD-Based PET Imaging

NASA Astrophysics Data System (ADS)

Fang, X. C.; Hu-Guo, Ch.; Ollivier-Henry, N.; Brasse, D.; Hu, Y.

2010-06-01

This paper represents the design of a low-noise, wide band multi-channel readout integrated circuit (IC) used as front end readout electronics of avalanche photo diodes (APD) dedicated to a small animal positron emission tomography (PET) system. The first ten-channel prototype chip (APD-Chip) of the analog parts has been designed and fabricated in a 0.35 μm CMOS process. Every channel of the APD_Chip includes a charge-sensitive preamplifier (CSA), a CR-(RC)2 shaper, and an analog buffer. In a channel, the CSA reads charge signals (10 bits dynamic range) from an APD array having 10 pF of capacitance per pixel. A linearized degenerated differential pair which ensures high linearity in all dynamical range is used as the high feedback resistor for preventing pile up of signals. The designed CSA has the capability of compensating automatically up to 200 nA leakage current from the detector. The CR-(RC)2 shaper filters and shapes the output signal of the CSA. An equivalent input noise charge obtained from test is 275 e -+ 10 e-/pF. In this paper the prototype is presented for both its theoretical analysis and its test results.

Single event effects on the APV25 front-end chip

NASA Astrophysics Data System (ADS)

Friedl, M.; Bauer, T.; Pernicka, M.

2003-03-01

The Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider at CERN will include a Silicon Strip Tracker covering a sensitive area of 206 m2. About ten million channels will be read out by APV25 front-end chips, fabricated in the 0.25 μm deep submicron process. Although permanent damage is not expected within CMS radiation levels, transient Single Event Upsets are inevitable. Moreover, localized ionization can also produce fake signals in the analog circuitry. Eight APV25 chips were exposed to a high-intensity pion beam at the Paul Scherrer Institute (Villigen/CH) to study the radiation induced effects in detail. The results, which are compatible to similar measurements performed with heavy ions, are used to predict the chip error rate at CMS.

An RFID tag system-on-chip with wireless ECG monitoring for intelligent healthcare systems.

PubMed

Wang, Cheng-Pin; Lee, Shuenn-Yuh; Lai, Wei-Chih

2013-01-01

This paper presents a low-power wireless ECG acquisition system-on-chip (SoC), including an RF front-end circuit, a power unit, an analog front-end circuit, and a digital circuitry. The proposed RF front-end circuit can provide the amplitude shift keying demodulation and distance to digital conversion to accurately receive the data from the reader. The received data will wake up the power unit to provide the required supply voltages of analog front-end (AFE) and digital circuitry. The AFE, including a pre-amplifier, an analog filter, a post-amplifier, and an analog-to-digital converter, is used for the ECG acquisition. Moreover, the EPC Class I Gen 2 UHF standard is employed in the digital circuitry for the handshaking of communication and the control of the system. The proposed SoC has been implemented in 0.18-µm standard CMOS process and the measured results reveal the communication is compatible to the RFID protocol. The average power consumption for the operating chip is 12 µW. Using a Sony PR44 battery to the supply power (605mAh@1.4V), the RFID tag SoC operates continuously for about 50,000 hours (>5 years), which is appropriate for wireless wearable ECG monitoring systems.

Electronic readout system for the Belle II imaging Time-Of-Propagation detector

NASA Astrophysics Data System (ADS)

Kotchetkov, Dmitri

2017-07-01

The imaging Time-Of-Propagation (iTOP) detector, constructed for the Belle II experiment at the SuperKEKB e+e- collider, is an 8192-channel high precision Cherenkov particle identification detector with timing resolution below 50 ps. To acquire data from the iTOP, a novel front-end electronic readout system was designed, built, and integrated. Switched-capacitor array application-specific integrated circuits are used to sample analog signals. Triggering, digitization, readout, and data transfer are controlled by Xilinx Zynq-7000 system on a chip devices.

Digital front end electronics design for the EUSO photon detector

NASA Astrophysics Data System (ADS)

Musico, P.; Pallavicini, M.; Petrolini, A.; Pratolongo, F.

2003-09-01

In this paper we will present the design status of the Digital Front End Electronic system (DFEE), that will be used for the EUSO photon detector. The DFEE is able to count the single photoelectrons coming form the detector for a given time period, store the numbers in a memory buffer and read them out after a trigger, using a serial communication line. Because of space, mass and power consumption constraints, the system will be implemented in an ASIC using a deep submicron technology. The actual design follows the original ideas of the system, though adding several new functionalities. A fully functional prototype chip has been submitted for fabrication in fall 2002. Extensive tests will be performed on it both with bench instrumentations and with the real sensor (the multi anode photomultiplier Hamamatsu R7600-M64), expecting significant results by early Summer 2003. Future work is needed to convert the design into a more robust RAD-hard technology, suitable for space applications and to include in the final die an additional circuit used to optimize the performances at high photons rates: the Analog Front End Electronics (AFEE). Moreover the base board used to house the multi anode photomultipliers is presented: it is the back-bone of the microcell and will be the basic block used to build up the EUSO focal surface.

A SAR-ADC using unit bridge capacitor and with calibration for the front-end electronics of PET imaging

NASA Astrophysics Data System (ADS)

Liu, Wei; Wei, Tingcun; Li, Bo; Yang, Lifeng; Xue, Feifei; Hu, Yongcai

2016-05-01

This paper presents a 12-bit 1 MS/s successive approximation register-analog to digital converter (SAR-ADC) for the 32-channel front-end electronics of CZT-based PET imaging system. To reduce the capacitance mismatch, instead of the fractional capacitor, the unit capacitor is used as the bridge capacitor in the split-capacitor digital to analog converter (DAC) circuit. In addition, in order to eliminate the periodical DNL errors of -1 LSB which often exists in the SAR-ADC using the charge-redistributed DAC, a calibration algorithm is proposed and verified by the experiments. The proposed 12-bit 1 MS/s SAR-ADC is designed and implemented using a 0.35 μm CMOS technology, it occupies only an active area of 986×956 μm2. The measurement results show that, at the power supply of 3.3/5.0 V and the sampling rate of 1 MS/s, the ADC with calibration has a signal-to-noise-and-distortion ratio (SINAD) of 67.98 dB, the power dissipation of 5 mW, and a figure of merit (FOM) of 2.44 pJ/conv.-step. This ADC is with the features of high accuracy, low power and small layout area, it is especially suitable to the one-chip integration of the front-end readout electronics.

CMOS Rad-Hard Front-End Electronics for Precise Sensors Measurements

NASA Astrophysics Data System (ADS)

Sordo-Ibáñez, Samuel; Piñero-García, Blanca; Muñoz-Díaz, Manuel; Ragel-Morales, Antonio; Ceballos-Cáceres, Joaquín; Carranza-González, Luis; Espejo-Meana, Servando; Arias-Drake, Alberto; Ramos-Martos, Juan; Mora-Gutiérrez, José Miguel; Lagos-Florido, Miguel Angel

2016-08-01

This paper reports a single-chip solution for the implementation of radiation-tolerant CMOS front-end electronics (FEE) for applications requiring the acquisition of base-band sensor signals. The FEE has been designed in a 0.35μm CMOS process, and implements a set of parallel conversion channels with high levels of configurability to adapt the resolution, conversion rate, as well as the dynamic input range for the required application. Each conversion channel has been designed with a fully-differential implementation of a configurable-gain instrumentation amplifier, followed by an also configurable dual-slope ADC (DS ADC) up to 16 bits. The ASIC also incorporates precise thermal monitoring, sensor conditioning and error detection functionalities to ensure proper operation in extreme environments. Experimental results confirm that the proposed topologies, in conjunction with the applied radiation-hardening techniques, are reliable enough to be used without loss in the performance in environments with an extended temperature range (between -25 and 125 °C) and a total dose beyond 300 krad.

Performance evaluation of the analogue front-end and ADC prototypes for the Gotthard-II development

NASA Astrophysics Data System (ADS)

Zhang, J.; Andrä, M.; Barten, R.; Bergamaschi, A.; Brückner, M.; Dinapoli, R.; Fröjdh, E.; Greiffenberg, D.; Lopez-Cuenca, C.; Mezza, D.; Mozzanica, A.; Ramilli, M.; Redford, S.; Ruat, M.; Ruder, C.; Schmitt, B.; Shi, X.; Thattil, D.; Tinti, G.; Turcato, M.; Vetter, S.

2017-12-01

Gotthard-II is a silicon microstrip detector developed for the European X-ray Free-Electron Laser (XFEL.EU). Its potential scientific applications include X-ray absorption/emission spectroscopy, hard X-ray high resolution single-shot spectrometry (HiREX), energy dispersive experiments at 4.5 MHz frame rate, beam diagnostics, as well as veto signal generation for pixel detectors. Gotthard-II uses a silicon microstrip sensor with a pitch of 50 μm or 25 μm and with 1280 or 2560 channels wire-bonded to readout chips (ROCs). In the ROC, an adaptive gain switching pre-amplifier (PRE), a fully differential Correlated-Double-Sampling (CDS) stage, an Analog-to-Digital Converter (ADC) as well as a Static Random-Access Memory (SRAM) capable of storing all the 2700 images in an XFEL.EU bunch train will be implemented. Several prototypes with different designs of the analogue front-end (PRE and CDS) and ADC test structures have been fabricated in UMC-110 nm CMOS technology and their performance has been evaluated. In this paper, the performance of the analogue front-end and ADC will be summarized.

Photodetectors and front-end electronics for the LHCb RICH upgrade

NASA Astrophysics Data System (ADS)

Cassina, L.; LHCb RICH

2017-12-01

The RICH detectors of the LHCb experiment provide identification of hadrons produced in high energy proton-proton collisions in the LHC at CERN over a wide momentum range (2-100 GeV/c). Cherenkov light is collected on photon detector planes sensitive to single photons. The RICH will be upgraded (in 2019) to read out every bunch crossing, at a rate of 40 MHz. The current hybrid photon detectors (HPD) will be replaced with multi-anode photomultiplier tubes (customisations of the Hamamatsu R11265 and the H12699 MaPMTs). These 8×8 pixel devices meet the experimental requirements thanks to their small pixel size, high gain, negligible dark count rate (∼50 Hz/cm2) and moderate cross-talk. The measured performance of several tubes is reported, together with their long-term stability. A new 8-channel front-end chip, named CLARO, has been designed in 0.35 μm CMOS AMS technology for the MaPMT readout. The CLARO chip operates in binary mode and combines low power consumption (∼1 mW/Ch), wide bandwidth (baseline restored in ⩽ 25 ns) and radiation hardness. A 12-bit digital register permits the optimisation of the dynamic range and the threshold level for each channel and provides tools for the on-site calibration. The design choices and the characterization of the electronics are presented.

Precision tracking with a single gaseous pixel detector

NASA Astrophysics Data System (ADS)

Tsigaridas, S.; van Bakel, N.; Bilevych, Y.; Gromov, V.; Hartjes, F.; Hessey, N. P.; de Jong, P.; Kluit, R.

2015-09-01

The importance of micro-pattern gaseous detectors has grown over the past few years after successful usage in a large number of applications in physics experiments and medicine. We develop gaseous pixel detectors using micromegas-based amplification structures on top of CMOS pixel readout chips. Using wafer post-processing we add a spark-protection layer and a grid to create an amplification region above the chip, allowing individual electrons released above the grid by the passage of ionising radiation to be recorded. The electron creation point is measured in 3D, using the pixel position for (x, y) and the drift time for z. The track can be reconstructed by fitting a straight line to these points. In this work we have used a pixel-readout-chip which is a small-scale prototype of Timepix3 chip (designed for both silicon and gaseous detection media). This prototype chip has several advantages over the existing Timepix chip, including a faster front-end (pre-amplifier and discriminator) and a faster TDC which reduce timewalk's contribution to the z position error. Although the chip is very small (sensitive area of 0.88 × 0.88mm2), we have built it into a detector with a short drift gap (1.3 mm), and measured its tracking performance in an electron beam at DESY. We present the results obtained, which lead to a significant improvement for the resolutions with respect to Timepix-based detectors.

SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades

NASA Astrophysics Data System (ADS)

Adolfsson, J.; Ayala Pabon, A.; Bregant, M.; Britton, C.; Brulin, G.; Carvalho, D.; Chambert, V.; Chinellato, D.; Espagnon, B.; Hernandez Herrera, H. D.; Ljubicic, T.; Mahmood, S. M.; Mjörnmark, U.; Moraes, D.; Munhoz, M. G.; Noël, G.; Oskarsson, A.; Osterman, L.; Pilyar, A.; Read, K.; Ruette, A.; Russo, P.; Sanches, B. C. S.; Severo, L.; Silvermyr, D.; Suire, C.; Tambave, G. J.; Tun-Lanoë, K. M. M.; van Noije, W.; Velure, A.; Vereschagin, S.; Wanlin, E.; Weber, T. O.; Zaporozhets, S.

2017-04-01

This paper presents the test results of the second prototype of SAMPA, the ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chamber (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply and provides 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel consists of a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC; a Digital Signal Processor provides digital filtering and compression capability. In the second prototype run both full chip and single test blocks were fabricated, allowing block characterization and full system behaviour studies. Experimental results are here presented showing agreement with requirements for both the blocks and the full chip.

The Zero-Degree Detector System

NASA Technical Reports Server (NTRS)

Adams, James H.; Christl, Mark J.; Howell, Leonard W.; Kouznetsov, Evgueni

2006-01-01

We will report on a detector system used for accelerator measurement of nuclear fragmentation cross sections. This system consists of two detector planes, each carrying a ring of 8 detectors. Each detector has 64 pads. These two detector planes are arranged facing each other so that the matching detector pads on each plane form a two element charged particle telescope. Each of these telescopes is capable of determining the elemental identity of nuclear fragments passing through it. The system is used to measure light fragment production in the presence of heavier fragments. We will present a detailed discussion of the 64-pad detector design, the substrate design. The front-end electronics used to read out the signals is based on a custom VLSI chip developed for the Advanced Thin Ionization Calorimeter experiment which has been flown successfully twice in Antarctica. Each of these chips has 16 channels and each channel consists of a charge-sensitive preamplifier followed by a shaping amplifier and a track-and-hold circuit. The track-and-hold circuits are connected via a multiplexer to an output line driver. This allows the held signals to be presented, one-by-one via a common data line to a analog-to-digital converter. Because the output line driver can be placed in a high input impedance state when not in use, it is possible to daisy-change many chips on the same common data line. The front-end electronics and data readout scheme will be discussed in detail. The Zero Degree Detector has been used in several accelerator experiments conducted at the NASA Space Radiation Laboratory and the Alternating Gradient Synchrotron at Brookhaven National Laboratory as well as at the HIMAC accelerator in Japan. We will show examples of data taken at these accelerator runs to demonstrate how the system works.

Apparatus and method for harvesting woody plantations

DOEpatents

Eggen, David L.

1988-11-15

A tree harvester for harvesting felled trees includes a wheel mounted wood chipper which moves toward the butt ends of the tree stems to be processed. The harvester includes a plurality of rotating alignment discs in front of the chipper. These discs align the tree stems to be processed with the mouth of the chipper. A chipper infeed cylinder is rotatably mounted between the discs and the front end of the chipper, and lifts the tree stem butts up from the ground into alignment with the chipper inlet port. The chips discharge from the chipper and go into a chip hopper which moves with the tree harvester.

Apparatus and method for harvesting woody plantations

DOEpatents

Eggen, D.L.

1988-11-15

A tree harvester for harvesting felled trees includes a wheel mounted wood chipper which moves toward the butt ends of the tree stems to be processed. The harvester includes a plurality of rotating alignment discs in front of the chipper. These discs align the tree stems to be processed with the mouth of the chipper. A chipper infeed cylinder is rotatably mounted between the discs and the front end of the chipper, and lifts the tree stem butts up from the ground into alignment with the chipper inlet port. The chips discharge from the chipper and go into a chip hopper which moves with the tree harvester. 8 figs.

GET: A generic electronics system for TPCs and nuclear physics instrumentation

NASA Astrophysics Data System (ADS)

Pollacco, E. C.; Grinyer, G. F.; Abu-Nimeh, F.; Ahn, T.; Anvar, S.; Arokiaraj, A.; Ayyad, Y.; Baba, H.; Babo, M.; Baron, P.; Bazin, D.; Beceiro-Novo, S.; Belkhiria, C.; Blaizot, M.; Blank, B.; Bradt, J.; Cardella, G.; Carpenter, L.; Ceruti, S.; De Filippo, E.; Delagnes, E.; De Luca, S.; De Witte, H.; Druillole, F.; Duclos, B.; Favela, F.; Fritsch, A.; Giovinazzo, J.; Gueye, C.; Isobe, T.; Hellmuth, P.; Huss, C.; Lachacinski, B.; Laffoley, A. T.; Lebertre, G.; Legeard, L.; Lynch, W. G.; Marchi, T.; Martina, L.; Maugeais, C.; Mittig, W.; Nalpas, L.; Pagano, E. V.; Pancin, J.; Poleshchuk, O.; Pedroza, J. L.; Pibernat, J.; Primault, S.; Raabe, R.; Raine, B.; Rebii, A.; Renaud, M.; Roger, T.; Roussel-Chomaz, P.; Russotto, P.; Saccà, G.; Saillant, F.; Sizun, P.; Suzuki, D.; Swartz, J. A.; Tizon, A.; Usher, N.; Wittwer, G.; Yang, J. C.

2018-04-01

General Electronics for TPCs (GET) is a generic, reconfigurable and comprehensive electronics and data-acquisition system for nuclear physics instrumentation of up to 33792 channels. The system consists of a custom-designed ASIC for signal processing, front-end cards that each house 4 ASIC chips and digitize the data in parallel through 12-bit ADCs, concentration boards to read and process the digital data from up to 16 ASICs, a 3-level trigger and master clock module to trigger the system and synchronize the data, as well as all of the associated firmware, communication and data-acquisition software. An overview of the system including its specifications and measured performances are presented.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ianakiev, Kiril Dimitrov; Iliev, Metodi; Swinhoe, Martyn Thomas

The KM200 device is a versatile, configurable front-end electronics boards that can be used as a functional replacement for Canberra’s JAB-01 boards based on the Amptek A-111 hybrid chip, which continues to be the preferred choice of electronics for large number of the boards in junction boxes of multiplicity counters that process the signal from an array of 3He detectors. Unlike the A-111 chip’s fixed time constants and sensitivity range, the shaping time and sensitivity of the new KM200 can be optimized for demanding applications such as spent fuel, and thus could improve the safeguards measurements of existing systems wheremore » the A-111 or PDT electronics does not perform well.« less

Back-end and interface implementation of the STS-XYTER2 prototype ASIC for the CBM experiment

NASA Astrophysics Data System (ADS)

Kasinski, K.; Szczygiel, R.; Zabolotny, W.

2016-11-01

Each front-end readout ASIC for the High-Energy Physics experiments requires robust and effective hit data streaming and control mechanism. A new STS-XYTER2 full-size prototype chip for the Silicon Tracking System and Muon Chamber detectors in the Compressed Baryonic Matter experiment at Facility for Antiproton and Ion Research (FAIR, Germany) is a 128-channel time and amplitude measuring solution for silicon microstrip and gas detectors. It operates at 250 kHit/s/channel hit rate, each hit producing 27 bits of information (5-bit amplitude, 14-bit timestamp, position and diagnostics data). The chip back-end implements fast front-end channel read-out, timestamp-wise hit sorting, and data streaming via a scalable interface implementing the dedicated protocol (STS-HCTSP) for chip control and hit transfer with data bandwidth from 9.7 MHit/s up to 47 MHit/s. It also includes multiple options for link diagnostics, failure detection, and throttling features. The back-end is designed to operate with the data acquisition architecture based on the CERN GBTx transceivers. This paper presents the details of the back-end and interface design and its implementation in the UMC 180 nm CMOS process.

Front-end receiver electronics for a matrix transducer for 3-D transesophageal echocardiography.

PubMed

Yu, Zili; Blaak, Sandra; Chang, Zu-yao; Yao, Jiajian; Bosch, Johan G; Prins, Christian; Lancée, Charles T; de Jong, Nico; Pertijs, Michiel A P; Meijer, Gerard C M

2012-07-01

There is a clear clinical need for creating 3-D images of the heart. One promising technique is the use of transesophageal echocardiography (TEE). To enable 3-D TEE, we are developing a miniature ultrasound probe containing a matrix piezoelectric transducer with more than 2000 elements. Because a gastroscopic tube cannot accommodate the cables needed to connect all transducer elements directly to an imaging system, a major challenge is to locally reduce the number of channels, while maintaining a sufficient signal-to-noise ratio. This can be achieved by using front-end receiver electronics bonded to the transducers to provide appropriate signal conditioning in the tip of the probe. This paper presents the design of such electronics, realizing time-gain compensation (TGC) and micro-beamforming using simple, low-power circuits. Prototypes of TGC amplifiers and micro-beamforming cells have been fabricated in 0.35-μm CMOS technology. These prototype chips have been combined on a printed circuit board (PCB) to form an ultrasound-receiver system capable of reading and combining the signals of three transducer elements. Experimental results show that this design is a suitable candidate for 3-D TEE.

Construction and first beam-tests of silicon-tungsten prototype modules for the CMS High Granularity Calorimeter for HL-LHC

NASA Astrophysics Data System (ADS)

Jain, S.

2017-03-01

The High Granularity Calorimeter (HGCAL) is the technology choice of the CMS collaboration for the endcap calorimetry upgrade planned to cope with the harsh radiation and pileup environment at the High Luminosity-LHC . The HGCAL is realized as a sampling calorimeter, including an electromagnetic compartment comprising 28 layers of silicon pad detectors with pad areas of 0.5-01. cm2 interspersed with absorbers made from tungsten and copper to form a highly compact and granular device. Prototype modules, based on hexagonal silicon pad sensors, with 128 channels, have been constructed and tested in beams at FNAL and at CERN. The modules include many of the features required for this challenging detector, including a PCB glued directly to the sensor, using through-hole wire-bonding for signal readout and 5 mm spacing between layers—including the front-end electronics and all services. Tests in 2016 have used an existing front-end chip —Skiroc2 (designed for the CALICE experiment for ILC). We present results from first tests of these modules both in the laboratory and with beams of electrons, pions and protons, including noise performance, calibration with mips and electron signals.

Readout Electronics for the Forward Vertex Detector at PHENIX

NASA Astrophysics Data System (ADS)

Phillips, Michael

2010-11-01

The PHENIX experiment at RHIC at Brookhaven National Laboratory has been providing high quality physics data for over 10 years. The current PHENIX physics program will be significantly enhanced by addition of the Forward Silicon Vertex upgrade detector (FVTX) in the acceptance of existing muon arm detectors. The proposed tracker is planned to be put into operation in 2012. Each arm of the FVTX detector consist of 4 discs of silicon strip sensors combined with FPHX readout chips, designed at FNAL. The full detector consists of over 1 million active mini-strip channels with instantaneous bandwidth topping 3.4 Tb/s. The FPHX chip utilizes data push architecture with 2 serial output streams at 200 MHz. The readout electronics design consists of Read-Out Cards (ROC) located in the vicinity of the detector and Front End Modules (FEM) located in the Counting House. ROC boards combine the data from several chips, synchronizes data streams and send them to FEM over a Fiber Optics Link. The data are buffered in the FEM and then sent to a standard PHENIX DAQ interface upon Level-1 trigger request. We will present the current status of the readout electronics development and testing, including tests with data from production wedges.

A custom readout electronics for the BESIII CGEM detector

NASA Astrophysics Data System (ADS)

Da Rocha Rolo, M.; Alexeev, M.; Amoroso, A.; Baldini Ferroli, R.; Bertani, M.; Bettoni, D.; Bianchi, F.; Bugalho, R.; Calcaterra, A.; Canale, N.; Capodiferro, M.; Carassiti, V.; Cerioni, S.; Chai, J. Y.; Chiozzi, S.; Cibinetto, G.; Cossio, F.; Cotta Ramusino, A.; De Mori, F.; Destefanis, M.; Di Francesco, A.; Dong, J.; Evangelisti, F.; Farinelli, R.; Fava, L.; Felici, G.; Fioravanti, E.; Garzia, I.; Gatta, M.; Greco, M.; Lavezzi, L.; Leng, C. Y.; Li, H.; Maggiora, M.; Malaguti, R.; Marcello, S.; Marciniewski, P.; Melchiorri, M.; Mezzadri, G.; Mignone, M.; Morello, G.; Pacetti, S.; Patteri, P.; Pellegrino, J.; Pelosi, A.; Rivetti, A.; Savrié, M.; Scodeggio, M.; Soldani, E.; Sosio, S.; Spataro, S.; Tskhadadze, E.; Varela, J.; Verma, S.; Wheadon, R.; Yan, L.

2017-07-01

For the upgrade of the inner tracker of the BESIII spectrometer, planned for 2018, a lightweight tracker based on an innovative Cylindrical Gas Electron Multiplier (CGEM) detector is now under development. The analogue readout of the CGEM enables the use of a charge centroid algorithm to improve the spatial resolution to better than 130 μm while loosening the pitch strip to 650 μm, which allows to reduce the total number of channels to about 10 000. The channels are readout by 160 dedicated integrated 64-channel front-end ASICs, providing a time and charge measurement and featuring a fully-digital output. The energy measurement is extracted either from the time-over-threshold (ToT) or the 10-bit digitisation of the peak amplitude of the signal. The time of the event is generated by quad-buffered low-power TDCs, allowing for rates in excess of 60 kHz per channel. The TDCs are based on analogue interpolation techniques and produce a time stamp (or two, if working in ToT mode) of the event with a time resolution better than 50 ps. The front-end noise, based on a CSA and a two-stage complex conjugated pole shapers, dominate the channel intrinsic time jitter, which is less than 5 ns r.m.s. The time information of the hit can be used to reconstruct the track path, operating the detector as a small TPC and hence improving the position resolution when the distribution of the cloud, due to large incident angle or magnetic field, is very broad. Event data is collected by an off-detector motherboard, where each GEM-ROC readout card handles 4 ASIC carrier FEBs (512 channels). Configuration upload and data readout between the off-detector electronics and the VME-based data collector cards are managed by bi-directional fibre optical links. This paper covers the design of a custom front-end electronics for the readout of the new inner tracker of the BESIII experiment, addressing the relevant design aspects of the detector electronics and the front-end ASIC for the CGEM readout, and reviewing the first silicon results of the chip prototype.

Towards on-chip integration of brain imaging photodetectors using standard CMOS process.

PubMed

Kamrani, Ehsan; Lesage, Frederic; Sawan, Mohamad

2013-01-01

The main effects of on-chip integration on the performance and efficiency of silicon avalanche photodiode (SiAPD) and photodetector front-end is addressed in this paper based on the simulation and fabrication experiments. Two different silicon APDs are fabricated separately and also integrated with a transimpedance amplifier (TIA) front-end using standard CMOS technology. SiAPDs are designed in p+/n-well structure with guard rings realized in different shapes. The TIA front-end has been designed using distributed-gain concept combined with resistive-feedback and common-gate topology to reach low-noise and high gain-bandwidth product (GBW) characteristics. The integrated SiAPDs show higher signal-to-noise ratio (SNR), sensitivity and detection efficiency comparing to the separate SiAPDs. The integration does not show a significant effect on the gain and preserves the low power consumption. Using APDs with p-well guard-ring is preferred due to the higher observed efficiency after integration.

Progress on the upgrade of the CMS Hadron Calorimeter Front-End electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Anderson, Jake; Whitmore, Juliana; /Fermilab

2011-11-01

We present a scheme to upgrade the CMS HCAL front-end electronics in the second long shutdown to upgrade the LHC (LS2), which is expected to occur around 2018. The HCAL electronics upgrade is required to handle the major instantaneous luminosity increase (up to 5 * 10{sup 34} cm{sup -2} s{sup -1}) and an expected integrated luminosity of {approx}3000 fb{sup -1}. A key aspect of the HCAL upgrade is to read out longitudinal segmentation information to improve background rejection, energy resolution, and electron isolation at the L1 trigger. This paper focuses on the requirements for the new electronics and on themore » proposed solutions. The requirements include increased channel count, additional timing capabilities, and additional redundancy. The electronics are required to operate in a harsh environment and are constrained by the existing infrastructure. The proposed solutions span from chip level to system level. They include the development of a new ASIC ADC, the design and testing of higher speed transmitters to handle the increased data volume, the evaluation and use of circuits from other developments, evaluation of commercial FPGAs, better thermal design, and improvements in the overall readout architecture. We will report on the progress of the designs for these upgraded systems, along with performance requirements and initial design studies.« less

A low-power CMOS operational amplifier IC for a heterogeneous paper-based potentiostat

NASA Astrophysics Data System (ADS)

Bezuidenhout, P.; Land, K.; Joubert, T.-H.

2016-02-01

Electrochemical biosensing is used to detect specific analytes in fluids, such as bacterial and chemical contaminants. A common implementation of an electrochemical readout is a potentiostat, which usually includes potentiometric, amperometric, and impedimetric detection. Recently several researchers have developed small, low-cost, single-chip silicon-based potentiostats. With the advances in heterogeneous integration technology, low-power potentiostats can be implemented on paper and similar low cost substrates. This paper deals with the design of a low-power paper-based amperometric front-end for a low-cost and rapid detection environment. In amperometric detection a voltage signal is provided to a sensor system, while a small current value generated by an electrochemical redox reaction in the system is measured. In order to measure low current values, the noise of the circuit must be minimized, which is accomplished with a pre-amplification front-end stage, typically designed around an operational amplifier core. An appropriate circuit design for a low-power and low-cost amperometric front-end is identified, taking the heterogeneous integration of various components into account. The operational amplifier core is on a bare custom CMOS chip, which will be integrated onto the paper substrate alongside commercial off-the-shelf electronic components. A general-purpose low-power two-stage CMOS amplifier circuit is designed and simulated for the ams 350 nm 5 V process. After the layout design and verification, the IC was submitted for a multi-project wafer manufacturing run. The simulated results are a bandwidth of 2.4 MHz, a common-mode rejection ratio of 70.04 dB, and power dissipation of 0.154 mW, which are comparable with the analytical values.

Toward Realization of 2.4 GHz Balunless Narrowband Receiver Front-End for Short Range Wireless Applications.

PubMed

El-Desouki, Munir M; Qasim, Syed Manzoor; BenSaleh, Mohammed S; Deen, M Jamal

2015-05-07

The demand for radio frequency (RF) transceivers operating at 2.4 GHz band has attracted considerable research interest due to the advancement in short range wireless technologies. The performance of RF transceivers depends heavily on the transmitter and receiver front-ends. The receiver front-end is comprised of a low-noise amplifier (LNA) and a downconversion mixer. There are very few designs that focus on connecting the single-ended output LNA to a double-balanced mixer without the use of on-chip transformer, also known as a balun. The objective of designing such a receiver front-end is to achieve high integration and low power consumption. To meet these requirements, we present the design of fully-integrated 2.4 GHz receiver front-end, consisting of a narrow-band LNA and a double balanced mixer without using a balun. Here, the single-ended RF output signal of the LNA is translated into differential signal using an NMOS-PMOS (n-channel metal-oxide-semiconductor, p-channel metal-oxide-semiconductor) transistor differential pair instead of the conventional NMOS-NMOS transistor configuration, for the RF amplification stage of the double-balanced mixer. The proposed receiver circuit fabricated using TSMC 0.18 µm CMOS technology operates at 2.4 GHz and produces an output signal at 300 MHz. The fabricated receiver achieves a gain of 16.3 dB and consumes only 6.74 mW operating at 1.5 V, while utilizing 2.08 mm2 of chip area. Measurement results demonstrate the effectiveness and suitability of the proposed receiver for short-range wireless applications, such as in wireless sensor network (WSN).

Internal monitoring of GBTx emulator using IPbus for CBM experiment

NASA Astrophysics Data System (ADS)

Mandal, Swagata; Zabolotny, Wojciech; Sau, Suman; Chkrabarti, Amlan; Saini, Jogender; Chattopadhyay, Subhasis; Pal, Sushanta Kumar

2015-09-01

The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) in Darmstadt at GSI. In CBM experiment a precisely time synchronized fault tolerant self-triggered electronics is required for Data Acquisition (DAQ) system in CBM experiments which can support high data rate (up to several TB/s). As a part of the implementation of the DAQ system of Muon Chamber (MUCH) which is one of the important detectors in CBM experiment, a FPGA based Gigabit Transceiver (GBTx) emulator is implemented. Readout chain for MUCH consists of XYTER chips (Front end electronics) which will be directly connected to detector, GBTx emulator, Data Processing Board (DPB) and First level event selector board (FLIB) with backend software interface. GBTx emulator will be connected with the XYTER emulator through LVDS (Low Voltage Differential Signalling) line in the front end and in the back end it is connected with DPB through 4.8 Gbps optical link. IPBus over Ethernet is used for internal monitoring of the registers within the GBTx. In IPbus implementation User Datagram Protocol (UDP) stack is used in transport layer of OSI model so that GBTx can be controlled remotely. A Python script is used at computer side to drive IPbus controller.

SYRMEP front-end and read-out electronics

NASA Astrophysics Data System (ADS)

Arfelli, F.; Bonvicini, V.; Bravin, A.; Cantatore, G.; Castelli, E.; Cristaudo, P.; Di Michiel, M.; Longo, R.; Olivo, A.; Pani, S.; Pontoni, D.; Poropat, P.; Prest, M.; Rashevsky, A.; Tomasini, F.; Tromba, G.; Vacchi, A.; Vallazza, E.

1998-02-01

The SYRMEP approach to digital mammography implies the use of a monochromatic X-ray beam from a synchrotron source and a slot of superimposed silicon microstrip detectors as a scanning image receptor. The microstrips are read by 32-channel chips mounted on 7-layer hybrid circuits which receive control signals and operating voltages from a MASTER-SLAVE configuration of cards. The MASTER card is driven by the CIRM, a dedicated CAMAC module whose timing function can be easily excluded to obtain data-storage-only units connected to different MASTERs: this second-level modular expansion capability fully achieves the tasks of an electronics system able to follow the SYRMEP detector growth till the final size of seven thousands of channels.

Advanced RF Front End Technology

NASA Technical Reports Server (NTRS)

Herman, M. I.; Valas, S.; Katehi, L. P. B.

2001-01-01

The ability to achieve low-mass low-cost micro/nanospacecraft for Deep Space exploration requires extensive miniaturization of all subsystems. The front end of the Telecommunication subsystem is an area in which major mass (factor of 10) and volume (factor of 100) reduction can be achieved via the development of new silicon based micromachined technology and devices. Major components that make up the front end include single-pole and double-throw switches, diplexer, and solid state power amplifier. JPL's Center For Space Microsystems - System On A Chip (SOAC) Program has addressed the challenges of front end miniaturization (switches and diplexers). Our objectives were to develop the main components that comprise a communication front end and enable integration in a single module that we refer to as a 'cube'. In this paper we will provide the latest status of our Microelectromechanical System (MEMS) switches and surface micromachined filter development. Based on the significant progress achieved we can begin to provide guidelines of the proper system insertion for these emerging technologies. Additional information is contained in the original extended abstract.

AFEII Analog Front End Board Design Specifications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rubinov, Paul; /Fermilab

2005-04-01

This document describes the design of the 2nd iteration of the Analog Front End Board (AFEII), which has the function of receiving charge signals from the Central Fiber Tracker (CFT) and providing digital hit pattern and charge amplitude information from those charge signals. This second iteration is intended to address limitations of the current AFE (referred to as AFEI in this document). These limitations become increasingly deleterious to the performance of the Central Fiber Tracker as instantaneous luminosity increases. The limitations are inherent in the design of the key front end chips on the AFEI board (the SVXIIe and themore » SIFT) and the architecture of the board itself. The key limitations of the AFEI are: (1) SVX saturation; (2) Discriminator to analog readout cross talk; (3) Tick to tick pedestal variation; and (4) Channel to channel pedestal variation. The new version of the AFE board, AFEII, addresses these limitations by use of a new chip, the TriP-t and by architectural changes, while retaining the well understood and desirable features of the AFEI board.« less

Silicon drift detectors with on-chip electronics for x-ray spectroscopy.

PubMed

Fiorini, C; Longoni, A; Hartmann, R; Lechner, P; Strüder, L

1997-01-01

The silicon drift detector (SDD) is a semiconductor device based on high resistivity silicon fully depleted through junctions implanted on both sides of the semiconductor wafer. The electrons generated by the ionizing radiation are driven by means of a suitable electric field from the point of interaction toward a collecting anode of small capacitance, independent of the active area of the detector. A suitably designed front-end JFET has been directly integrated on the detector chip close to the anode region, in order to obtain a nearly ideal capacitive matching between detector and transistor and to minimize the stray capacitances of the connections. This feature allows it to reach high energy resolution also at high count rates and near room temperature. The present work describes the structure and the performance of SDDs specially designed for high resolution spectroscopy with soft x rays at high detection rate. Experimental results of SDDs used in spectroscopy applications are also reported.

MICROROC: MICRO-mesh gaseous structure Read-Out Chip

NASA Astrophysics Data System (ADS)

Adloff, C.; Blaha, J.; Chefdeville, M.; Dalmaz, A.; Drancourt, C.; Dulucq, F.; Espargilière, A.; Gaglione, R.; Geffroy, N.; Jacquemier, J.; Karyotakis, Y.; Martin-Chassard, G.; Prast, J.; Seguin-Moreau, N.; de La Taille, Ch; Vouters, G.

2012-01-01

MICRO MEsh GAseous Structure (MICROMEGAS) and Gas Electron Multipliers (GEM) detectors are two candidates for the active medium of a Digital Hadronic CALorimeter (DHCAL) as part of a high energy physics experiment at a future linear collider (ILC/CLIC). Physics requirements lead to a highly granular hadronic calorimeter with up to thirty million channels with probably only hit information (digital readout calorimeter). To validate the concept of digital hadronic calorimetry with such small cell size, the construction and test of a cubic meter technological prototype, made of 40 planes of one square meter each, is necessary. This technological prototype would contain about 400 000 electronic channels, thus requiring the development of front-end ASIC. Based on the experience gained with previous ASIC that were mounted on detectors and tested in particle beams, a new ASIC called MICROROC has been developped. This paper summarizes the caracterisation campaign that was conducted on this new chip as well as its integration into a large area Micromegas chamber of one square meter.

Dedicated multichannel readout ASIC coupled with single crystal diamond for dosimeter application

NASA Astrophysics Data System (ADS)

Fabbri, A.; Falco, M. D.; De Notaristefani, F.; Galasso, M.; Marinelli, M.; Orsolini Cencelli, V.; Tortora, L.; Verona, C.; Verona Rinati, G.

2013-02-01

This paper reports on the tests of a low-noise, multi-channel readout integrated circuit used as a readout electronic front-end for a diamond multi-pixel dosimeter. The system is developed for dose distribution measurement in radiotherapy applications. The first 10-channel prototype chip was designed and fabricated in a 0.18 um CMOS process. Every channel includes a charge integrator with a 10 pF capacitor and a double slope A/D converter. The diamond multi-pixel detector, based on CVD synthetic single crystal diamond Schottky diodes, is made by a 3 × 3 sensor matrix. The overall device has been tested under irradiation with 6 MeV radio therapeutic photon beams at the Policlinico ``Tor Vergata'' (PTV) hospital. Measurements show a 20 fA RMS leakage current from the front-end input stage and a negligible dark current from the diamond detector, a stable temporal response and a good linear behaviour as a function of both dose and dose rate. These characteristics were common to each tested channel.

Concept Design for a 1-Lead Wearable/Implantable ECG Front-End: Power Management

PubMed Central

George, Libin; Gargiulo, Gaetano Dario; Lehmann, Torsten; Hamilton, Tara Julia

2015-01-01

Power supply quality and stability are critical for wearable and implantable biomedical applications. For this reason we have designed a reconfigurable switched-capacitor DC-DC converter that, aside from having an extremely small footprint (with an active on-chip area of only 0.04 mm2), uses a novel output voltage control method based upon a combination of adaptive gain and discrete frequency scaling control schemes. This novel DC-DC converter achieves a measured output voltage range of 1.0 to 2.2 V with power delivery up to 7.5 mW with 75% efficiency. In this paper, we present the use of this converter as a power supply for a concept design of a wearable (15 mm × 15 mm) 1-lead ECG front-end sensor device that simultaneously harvests power and communicates with external receivers when exposed to a suitable RF field. Due to voltage range limitations of the fabrication process of the current prototype chip, we focus our analysis solely on the power supply of the ECG front-end whose design is also detailed in this paper. Measurement results show not just that the power supplied is regulated, clean and does not infringe upon the ECG bandwidth, but that there is negligible difference between signals acquired using standard linear power-supplies and when the power is regulated by our power management chip. PMID:26610497

Concept Design for a 1-Lead Wearable/Implantable ECG Front-End: Power Management.

PubMed

George, Libin; Gargiulo, Gaetano Dario; Lehmann, Torsten; Hamilton, Tara Julia

2015-11-19

Power supply quality and stability are critical for wearable and implantable biomedical applications. For this reason we have designed a reconfigurable switched-capacitor DC-DC converter that, aside from having an extremely small footprint (with an active on-chip area of only 0.04 mm²), uses a novel output voltage control method based upon a combination of adaptive gain and discrete frequency scaling control schemes. This novel DC-DC converter achieves a measured output voltage range of 1.0 to 2.2 V with power delivery up to 7.5 mW with 75% efficiency. In this paper, we present the use of this converter as a power supply for a concept design of a wearable (15 mm × 15 mm) 1-lead ECG front-end sensor device that simultaneously harvests power and communicates with external receivers when exposed to a suitable RF field. Due to voltage range limitations of the fabrication process of the current prototype chip, we focus our analysis solely on the power supply of the ECG front-end whose design is also detailed in this paper. Measurement results show not just that the power supplied is regulated, clean and does not infringe upon the ECG bandwidth, but that there is negligible difference between signals acquired using standard linear power-supplies and when the power is regulated by our power management chip.

Programmable optical processor chips: toward photonic RF filters with DSP-level flexibility and MHz-band selectivity

NASA Astrophysics Data System (ADS)

Xie, Yiwei; Geng, Zihan; Zhuang, Leimeng; Burla, Maurizio; Taddei, Caterina; Hoekman, Marcel; Leinse, Arne; Roeloffzen, Chris G. H.; Boller, Klaus-J.; Lowery, Arthur J.

2017-12-01

Integrated optical signal processors have been identified as a powerful engine for optical processing of microwave signals. They enable wideband and stable signal processing operations on miniaturized chips with ultimate control precision. As a promising application, such processors enables photonic implementations of reconfigurable radio frequency (RF) filters with wide design flexibility, large bandwidth, and high-frequency selectivity. This is a key technology for photonic-assisted RF front ends that opens a path to overcoming the bandwidth limitation of current digital electronics. Here, the recent progress of integrated optical signal processors for implementing such RF filters is reviewed. We highlight the use of a low-loss, high-index-contrast stoichiometric silicon nitride waveguide which promises to serve as a practical material platform for realizing high-performance optical signal processors and points toward photonic RF filters with digital signal processing (DSP)-level flexibility, hundreds-GHz bandwidth, MHz-band frequency selectivity, and full system integration on a chip scale.

Architecture of a general purpose embedded Slow-Control Adapter ASIC for future high-energy physics experiments

NASA Astrophysics Data System (ADS)

Gabrielli, Alessandro; Loddo, Flavio; Ranieri, Antonio; De Robertis, Giuseppe

2008-10-01

This work is aimed at defining the architecture of a new digital ASIC, namely Slow-Control Adapter (SCA), which will be designed in a commercial 130-nm CMOS technology. This chip will be embedded within a high-speed data acquisition optical link (GBT) to control and monitor the front-end electronics in future high-energy physics experiments. The GBT link provides a transparent transport layer between the SCA and control electronics in the counting room. The proposed SCA supports a variety of common bus protocols to interface with end-user general-purpose electronics. Between the GBT and the SCA a standard 100 Mb/s IEEE-802.3 compatible protocol will be implemented. This standard protocol allows off-line tests of the prototypes using commercial components that support the same standard. The project is justified because embedded applications in modern large HEP experiments require particular care to assure the lowest possible power consumption, still offering the highest reliability demanded by very large particle detectors.

Front-end electronics development for TPC detector in the MPD/NICA project

NASA Astrophysics Data System (ADS)

Cheremukhina, G.; Movchan, S.; Vereschagin, S.; Zaporozhets, S.

2017-06-01

The article is aimed at describing the development status, measuring results and design changes of the TPC front-end electronics. The TPC is placed in the middle of Multi-Purpose Detector (MPD) and provides tracing and identifying of charged particles in the pseudorapidity range |η| < 1.2. The readout system is one of the most complex parts of the TPC. The electronics of each readout chamber is an independent system. The whole system contains 95232 channels, 1488 64-channel—front-end cards (FEC), 24 readout control units (RCU). The front-end electronics (FEE) is based on ASICs, FPGAs and high-speed serial links. The concept of the TPC front-end electronics has been motivated from one side—by the requirements concerning the NICA accelerator complex which will operate at the luminosity up to 1027 cm-2 s-1 for Au79+ ions over the energy range of 4 < √SNN < 11 GeV with the trigger rate up to 7 kHz and from the other side—by the requirements of the 4-π geometry to minimize the substance on the end-caps of the TPC.

Central Drift Chamber for Belle-II

NASA Astrophysics Data System (ADS)

Taniguchi, N.

2017-06-01

The Central Drift Chamber (CDC) is the main device for tracking and identification of charged particles for Belle-II experiment. The Belle-II CDC is cylindrical wire chamber with 14336 sense wires, 2.3 m-length and 2.2 m-diameter. The wire chamber and readout electronics have been completely replaced from the Belle CDC. The new readout electronics system must handle higher trigger rate of 30 kHz with less dead time at the design luminosity of 8 × 1035 cm-2s-1. The front-end electronics are located close to detector and send digitized signal through optical fibers. The Amp-Shaper-Discriminator chips, FADC and FPGA are assembled on a single board. Belle-II CDC with readout electronics has been installed successfully in Belle structure in October 2016. We will present overview of the Belle-II CDC and status of commissioning with cosmic ray.

Upgrading the ATLAS Tile Calorimeter Electronics

NASA Astrophysics Data System (ADS)

Carrió, Fernando

2013-11-01

This work summarizes the status of the on-detector and off-detector electronics developments for the Phase 2 Upgrade of the ATLAS Tile Calorimeter at the LHC scheduled around 2022. A demonstrator prototype for a slice of the calorimeter including most of the new electronics is planned to be installed in ATLAS in the middle of 2014 during the first Long Shutdown. For the on-detector readout, three different front-end boards (FEB) alternatives are being studied: a new version of the 3-in-1 card, the QIE chip and a dedicated ASIC called FATALIC. The Main Board will provide communication and control to the FEBs and the Daughter Board will transmit the digitized data to the off-detector electronics in the counting room, where the super Read-Out Driver (sROD) will perform processing tasks on them and will be the interface to the trigger levels 0, 1 and 2.

A time-based front-end ASIC for the silicon micro strip sensors of the bar PANDA Micro Vertex Detector

NASA Astrophysics Data System (ADS)

Di Pietro, V.; Brinkmann, K.-Th.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Zambanini, A.

2016-03-01

The bar PANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA (bar PANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels.

A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

NASA Astrophysics Data System (ADS)

Lattuca, A.; Mazza, G.; Aglieri Rinella, G.; Cavicchioli, C.; Chanlek, N.; Collu, A.; Degerli, Y.; Dorokhov, A.; Flouzat, C.; Gajanana, D.; Gao, C.; Guilloux, F.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kim, D.; Kofarago, M.; Kugathasan, T.; Kwon, Y.; Mager, M.; Sielewicz, K. Marek; Marin Tobon, C. Augusto; Marras, D.; Martinengo, P.; Mugnier, H.; Musa, L.; Pham, T. Hung; Puggioni, C.; Reidt, F.; Riedler, P.; Rousset, J.; Siddhanta, S.; Snoeys, W.; Song, M.; Usai, G.; Van Hoorne, J. Willem; Yang, P.

2016-01-01

This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.

Conceptual design of front ends for the advanced photon source multi-bend achromats upgrade

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jaski, Y., E-mail: jaskiy@aps.anl.gov; Westferro, F., E-mail: westferr@aps.anl.gov; Lee, S. H., E-mail: shlee@aps.anl.gov

2016-07-27

The proposed Advanced Photon Source (APS) upgrade from a double-bend achromats (DBA) to multi-bend achromats (MBA) lattice with ring energy change from 7 GeV to 6 GeV and beam current from 100 mA to 200 mA poses new challenges for front ends. All front ends must be upgraded to fulfill the following requirements: 1) handle the high heat load from two insertion devices in either inline or canted configuration, 2) include a clearing magnet in the front end to deflect and dump any electrons in case the electrons escape from the storage ring during swap-out injection with the safety shuttersmore » open, 3) incorporate the next generation x-ray beam position monitors (XBPMs) into the front end to meet the new stringent beam stability requirements. This paper presents the evaluation of the existing APS front ends and standardizes the insertion device (ID) front ends into two types: one for the single beam and one for the canted beams. The conceptual design of high heat load front end (HHLFE) and canted undulator front end (CUFE) for APS MBA upgrade is presented.« less

Conceptual Design of Front Ends for the Advanced Photon Source Multi-bend Achromats Upgrade

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jaski, Y.; Westferro, F.; Lee, S. H.

2016-07-27

The proposed Advanced Photon Source (APS) upgrade from a double-bend achromats (DBA) to multi-bend achromats (MBA) lattice with ring energy change from 7 GeV to 6 GeV and beam current from 100 mA to 200 mA poses new challenges for front ends. All front ends must be upgraded to fulfill the following requirements: 1) handle the high heat load from two insertion devices in either inline or canted configuration, 2) include a clearing magnet in the front end to deflect and dump any electrons in case the electrons escape from the storage ring during swap-out injection with the safety shuttersmore » open, 3) incorporate the next generation x-ray beam position monitors (XBPMs) into the front end to meet the new stringent beam stability requirements. This paper presents the evaluation of the existing APS front ends and standardizes the insertion device (ID) front ends into two types: one for the single beam and one for the canted beams. The conceptual design of high heat load front end (HHLFE) and canted undulator front end (CUFE) for APS MBA upgrade is presented.« less

The GBT-SCA, a radiation tolerant ASIC for detector control and monitoring applications in HEP experiments

NASA Astrophysics Data System (ADS)

Caratelli, A.; Bonacini, S.; Kloukinas, K.; Marchioro, A.; Moreira, P.; De Oliveira, R.; Paillard, C.

2015-03-01

The future upgrades of the LHC experiments will increase the beam luminosity leading to a corresponding growth of the amounts of data to be treated by the data acquisition systems. To address these needs, the GBT (Giga-Bit Transceiver optical link [1,2]) architecture was developed to provide the simultaneous transfer of readout data, timing and trigger signals as well as slow control and monitoring data. The GBT-SCA ASIC, part of the GBT chip-set, has the purpose to distribute control and monitoring signals to the on-detector front-end electronics and perform monitoring operations of detector environmental parameters. In order to meet the requirements of different front-end ASICs used in the experiments, it provides various user-configurable interfaces capable to perform simultaneous operations. It is designed employing radiation tolerant design techniques to ensure robustness against SEUs and TID radiation effects and is implemented in a commercial 130 nm CMOS technology. This work presents the GBT-SCA architecture, the ASIC interfaces, the data transfer protocol, and its integration with the GBT optical link.

A novel model for simulating the racing effect in capillary-driven underfill process in flip chip

NASA Astrophysics Data System (ADS)

Zhu, Wenhui; Wang, Kanglun; Wang, Yan

2018-04-01

Underfill is typically applied in flip chips to increase the reliability of the electronic packagings. In this paper, the evolution of the melt-front shape of the capillary-driven underfill flow is studied through 3D numerical analysis. Two different models, the prevailing surface force model and the capillary model based on the wetted wall boundary condition, are introduced to test their applicability, where level set method is used to track the interface of the two phase flow. The comparison between the simulation results and experimental data indicates that, the surface force model produces better prediction on the melt-front shape, especially in the central area of the flip chip. Nevertheless, the two above models cannot simulate properly the racing effect phenomenon that appears during underfill encapsulation. A novel ‘dynamic pressure boundary condition’ method is proposed based on the validated surface force model. Utilizing this approach, the racing effect phenomenon is simulated with high precision. In addition, a linear relationship is derived from this model between the flow front location at the edge of the flip chip and the filling time. Using the proposed approach, the impact of the underfill-dispensing length on the melt-front shape is also studied.

Fast wire per wire X-ray data acquisition system for time-resolved small angle scattering experiments

NASA Astrophysics Data System (ADS)

Epstein, A.; Briquet-Laugier, F.; Sheldon, S.; Boulin, C.

2000-04-01

Most of the X-ray multi-wire gas detectors used at the EMBL Hamburg outstation for time-resolved studies of biological samples are readout, using the delay line method. The main disadvantage of such readout systems is their event rate limitation introduced by the delay line and the required time to digital conversion step. They also lack the possibility to deal with multiple events. To overcome these limitations, a new approach for the complete readout system was introduced. The new linear detection system is based on the wire per wire approach where each individual wire is associated to preamplifier/discriminator/counter electronics channel. High-density, front-end electronics were designed around a fast current sensitive preamplifier. An eight-channel board was designed to include the preamplifiers-discriminators and the differential ECL drivers output stages. The detector front-end consists of 25 boards directly mounted inside the detector assembly. To achieve a time framing resolution as short as 10 /spl mu/s, very fast histogramming is required. The only way to implement this for a high number of channels (200 in our case) is by using a distributed system. The digital part of the system consists of a crate controller, up to 16 acquisition boards (capable of handling fast histogramming for up to 32-channels each) and an optical-link board (based on the Cypress "Hot-Link" chip set). Both the crate controller and the acquisition boards are based on a standard RISC microcontroller (IDT R3081) plug-in board. At present, a dedicated CAMAC module which we developed is used to interface the digital front-end acquisition crate to the host via the optical link.

SALT, a dedicated readout chip for high precision tracking silicon strip detectors at the LHCb Upgrade

NASA Astrophysics Data System (ADS)

Bugiel, Sz.; Dasgupta, R.; Firlej, M.; Fiutowski, T.; Idzik, M.; Kuczynska, M.; Moron, J.; Swientek, K.; Szumlak, T.

2016-02-01

The Upstream Tracker (UT) silicon strip detector, one of the central parts of the tracker system of the modernised LHCb experiment, will use a new 128-channel readout ASIC called SALT. It will extract and digitise analogue signals from the UT sensors, perform digital signal processing and transmit a serial output data. The SALT is being designed in CMOS 130 nm process and uses a novel architecture comprising of analog front-end and fast (40 MSps) ultra-low power (<0.5 mW) 6-bit ADC in each channel. The prototype ASICs of important functional blocks, like analogue front-end, 6-bit SAR ADC, PLL, and DLL, were designed, fabricated and tested. A prototype of an 8-channel version of the SALT chip, comprising all important functionalities was also designed and fabricated. The architecture and design of the SALT, together with the selected preliminary tests results, are presented.

Beam test results of a monolithic pixel sensor in the 0.18 μm tower-jazz technology with high resistivity epitaxial layer

NASA Astrophysics Data System (ADS)

Mattiazzo, S.; Aimo, I.; Baudot, J.; Bedda, C.; La Rocca, P.; Perez, A.; Riggi, F.; Spiriti, E.

2015-10-01

The ALICE experiment at CERN will undergo a major upgrade in the second Long LHC Shutdown in the years 2018-2019; this upgrade includes the full replacement of the Inner Tracking System (ITS), deploying seven layers of Monolithic Active Pixel Sensors (MAPS). For the development of the new ALICE ITS, the Tower-Jazz 0.18 μm CMOS imaging sensor process has been chosen as it is possible to use full CMOS in the pixel and different silicon wafers (including high resistivity epitaxial layers). A large test campaign has been carried out on several small prototype chips, designed to optimize the pixel sensor layout and the front-end electronics. Results match the target requirements both in terms of performance and of radiation hardness. Following this development, the first full scale chips have been designed, submitted and are currently under test, with promising results. A telescope composed of 4 planes of Mimosa-28 and 2 planes of Mimosa-18 chips is under development at the DAFNE Beam Test Facility (BTF) at the INFN Laboratori Nazionali di Frascati (LNF) in Italy with the final goal to perform a comparative test of the full scale prototypes. The telescope has been recently used to test a Mimosa-22THRb chip (a monolithic pixel sensor built in the 0.18 μm Tower-Jazz process) and we foresee to perform tests on the full scale chips for the ALICE ITS upgrade at the beginning of 2015. In this contribution we will describe some first measurements of spatial resolution, fake hit rate and detection efficiency of the Mimosa-22THRb chip obtained at the BTF facility in June 2014 with an electron beam of 500 MeV.

MEDIPIX: a VLSI chip for a GaAs pixel detector for digital radiology

NASA Astrophysics Data System (ADS)

Amendolia, S. R.; Bertolucci, E.; Bisogni, M. G.; Bottigli, U.; Ceccopieri, A.; Ciocci, M. A.; Conti, M.; Delogu, P.; Fantacci, M. E.; Maestro, P.; Marzulli, V.; Pernigotti, E.; Romeo, N.; Rosso, V.; Rosso, P.; Stefanini, A.; Stumbo, S.

1999-02-01

A GaAs pixel detector designed for digital mammography, equipped with a 36-channel single photon counting discrete read-out electronics, was tested using a test object developed for quality control purposes in mammography. Each pixel was 200×200 μm 2 large, and 200 μm deep. The choice of GaAs with respect to silicon (largely used in other applications and with a more established technique) has been made because of the much better detection efficiency at mammographic energies, combined with a very good charge collection efficiency achieved thanks to new ohmic contacts. This GaAs detector is able to perform a measurement of low-contrast details, with minimum contrast lower (nearly a factor two) than that typically achievable with standard mammographic film+screen systems in the same conditions of clinical routine. This should allow for an earlier diagnosis of breast tumour masses. Due to these encouraging results, the next step in the evolution of our imaging system based on GaAs detectors has been the development of a VLSI front-end prototype chip (MEDIPIX ) in order to cover a much larger diagnostic area. The chip reads 64×64 channels in single photon counting mode, each one 170 μm wide. Each channel contains also a test input where a signal can be simulated, injecting a known charge through a 16 f F capacitor. Fake signals have been injected via the test input measuring and equalizing minimum thresholds for all the channels. On an average, in most of the performing chips available up to now, we have found that it is possible to set a threshold as low as 1800 electrons with an RMS of 150 electrons (10 standard deviations lower than the 20 keV photon signal roughly equivalent to 4500 electrons). The detector, bump-bonded to the chip, will be tested and a ladder of detectors will be prepared to be able to scan large surface objects.

Low-power analog integrated circuits for wireless ECG acquisition systems.

PubMed

Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

2012-09-01

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

[A modified speech enhancement algorithm for electronic cochlear implant and its digital signal processing realization].

PubMed

Wang, Yulin; Tian, Xuelong

2014-08-01

In order to improve the speech quality and auditory perceptiveness of electronic cochlear implant under strong noise background, a speech enhancement system used for electronic cochlear implant front-end was constructed. Taking digital signal processing (DSP) as the core, the system combines its multi-channel buffered serial port (McBSP) data transmission channel with extended audio interface chip TLV320AIC10, so speech signal acquisition and output with high speed are realized. Meanwhile, due to the traditional speech enhancement method which has the problems as bad adaptability, slow convergence speed and big steady-state error, versiera function and de-correlation principle were used to improve the existing adaptive filtering algorithm, which effectively enhanced the quality of voice communications. Test results verified the stability of the system and the de-noising performance of the algorithm, and it also proved that they could provide clearer speech signals for the deaf or tinnitus patients.

Qualification and Reliability for MEMS and IC Packages

NASA Technical Reports Server (NTRS)

Ghaffarian, Reza

2004-01-01

Advanced IC electronic packages are moving toward miniaturization from two key different approaches, front and back-end processes, each with their own challenges. Successful use of more of the back-end process front-end, e.g. microelectromechanical systems (MEMS) Wafer Level Package (WLP), enable reducing size and cost. Use of direct flip chip die is the most efficient approach if and when the issues of know good die and board/assembly are resolved. Wafer level package solve the issue of known good die by enabling package test, but it has its own limitation, e.g., the I/O limitation, additional cost, and reliability. From the back-end approach, system-in-a-package (SIAP/SIP) development is a response to an increasing demand for package and die integration of different functions into one unit to reduce size and cost and improve functionality. MEMS add another challenging dimension to electronic packaging since they include moving mechanical elements. Conventional qualification and reliability need to be modified and expanded in most cases in order to detect new unknown failures. This paper will review four standards that already released or being developed that specifically address the issues on qualification and reliability of assembled packages. Exposures to thermal cycles, monotonic bend test, mechanical shock and drop are covered in these specifications. Finally, mechanical and thermal cycle qualification data generated for MEMS accelerometer will be presented. The MEMS was an element of an inertial measurement unit (IMU) qualified for NASA Mars Exploration Rovers (MERs), Spirit and Opportunity that successfully is currently roaring the Martian surface

Noise propagation effects in power supply distribution systems for high-energy physics experiments

NASA Astrophysics Data System (ADS)

Arteche, F.; Rivetta, C.; Iglesias, M.; Echeverria, I.; Pradas, A.; Arcega, F. J.

2017-12-01

High-energy physics experiments are supplied by thousands of power supply units placed in distant areas from the front-end electronics. The power supply units and the front-end electronics are connected through long power cables that propagate the output noise from the power supplies to the detector. This paper addresses the effect of long cables on the noise propagation and the impact that those cables have on the conducted emission levels required for the power supplies and the selection of EMI filters for the front-end electronic low-voltage input. This analysis is part of the electromagnetic compatibility based design focused on functional safety to define the type of cable, shield connections, EMI filters and power supply specifications required to ensure the successful integration of the detector and, specifically, to achieve the designed performance of the front-end electronics.

Noise propagation effects in power supply distribution systems for high-energy physics experiments

DOE PAGES

Arteche, F.; Rivetta, C.; Iglesias, M.; ...

2017-12-05

High-energy physics experiments are supplied by thousands of power supply units placed in distant areas from the front-end electronics. The power supply units and the front-end electronics are connected through long power cables that propagate the output noise from the power supplies to the detector. Here, this paper addresses the effect of long cables on the noise propagation and the impact that those cables have on the conducted emission levels required for the power supplies and the selection of EMI filters for the front-end electronic low-voltage input. Lastly, this analysis is part of the electromagnetic compatibility based design focused onmore » functional safety to define the type of cable, shield connections, EMI filters and power supply specifications required to ensure the successful integration of the detector and, specifically, to achieve the designed performance of the front-end electronics.« less

Noise propagation effects in power supply distribution systems for high-energy physics experiments

DOE Office of Scientific and Technical Information (OSTI.GOV)

Arteche, F.; Rivetta, C.; Iglesias, M.

High-energy physics experiments are supplied by thousands of power supply units placed in distant areas from the front-end electronics. The power supply units and the front-end electronics are connected through long power cables that propagate the output noise from the power supplies to the detector. Here, this paper addresses the effect of long cables on the noise propagation and the impact that those cables have on the conducted emission levels required for the power supplies and the selection of EMI filters for the front-end electronic low-voltage input. Lastly, this analysis is part of the electromagnetic compatibility based design focused onmore » functional safety to define the type of cable, shield connections, EMI filters and power supply specifications required to ensure the successful integration of the detector and, specifically, to achieve the designed performance of the front-end electronics.« less

The readout electronics for Plastic Scintillator Detector of DAMPE

NASA Astrophysics Data System (ADS)

Kong, Jie; Yang, Haibo; Zhao, Hongyun; Su, Hong; Sun, Zhiyu; Yu, Yuhong; JingZhe, Zhang; Wang, XiaoHui; Liu, Jie; Xiao, Guoqing; Ma, Xinwen

2016-07-01

The Dark Matter Particle Explorer (DAMPE) satellite, which launched in December 2015, is designed to find the evidence of the existence of dark matter particles in the universe via the detection of the high-energy electrons and gamma-ray particles produced possibly by the annihilation of dark matter particles. Plastic Scintillator Detector (PSD) is one of major part of the satellite payload, which is comprised of a crossed pair of layers with 41 plastic scintillator-strips, each read out from both ends by the same Hamamatsu R4443MOD2 photo-multiplier tubes (PMTs). In order to extend linear dynamic range of detector, PMTs read out each plastic scintillator-strip separately with two dynode pickoffs. Therefore, the readout electronics system comprises of four Front-end boards to receive the pulses from 328 PMTs and implement charge measurement, which is based on the Application Specific Integrated Circuit (ASIC) chip VA160, 16 bits ADC and FPGA. The electronics of the detector has been designed following stringent requirements on mechanical and thermal stability, power consumption, radiation hardness and double redundancy. Various experiments are designed and implemented to check the performance of the electronics, some excellent results has been achieved.According to experimental results analysis, it is proved that the readout electronics works well.

A single active nanoelectromechanical tuning fork front-end radio-frequency receiver

NASA Astrophysics Data System (ADS)

Bartsch, Sebastian T.; Rusu, A.; Ionescu, Adrian M.

2012-06-01

Nanoelectromechanical systems (NEMS) offer the potential to revolutionize fundamental methods employed for signal processing in today’s telecommunication systems, owing to their spectral purity and the prospect of integration with existing technology. In this work we present a novel, front-end receiver topology based on a single device silicon nanoelectromechanical mixer-filter. The operation is demonstrated by using the signal amplification in a field effect transistor (FET) merged into a tuning fork resonator. The combination of both a transistor and a mechanical element into a hybrid unit enables on-chip functionality and performance previously unachievable in silicon. Signal mixing, filtering and demodulation are experimentally demonstrated at very high frequencies ( > 100 MHz), maintaining a high quality factor of Q = 800 and stable operation at near ambient pressure (0.1 atm) and room temperature (T = 300 K). The results show that, ultimately miniaturized, silicon NEMS can be utilized to realize multi-band, single-chip receiver systems based on NEMS mixer-filter arrays with reduced system complexity and power consumption.

A Charge Sensitive Pre-Amplifier for Smart Point-of-Care Devices Employing Polymer Based Lab-on-a-Chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Hanfeng; Britton, Charles; Quaiyum, Farhan

With increasing emphasis on implantable and portable medical devices, low-power, small-chip-area sensor readout system realized in lab-on-a-chip (LOC) platform is gaining more and more importance these days. The main building blocks of the LOC system include a front-end transducer that generates an electrical signal in response to the presence of an analyte of interest, signal processing electronics to process the signal to comply with a specific transmission protocol and a low-power transmitter, all realized in a single integrated circuit platform. Low power consumption and compactness of the components are essential requirements of the LOC system. This paper presents a novelmore » charge sensitive pre-amplifier developed in a standard 180-nm CMOS process suitable for implementing in an LOC platform. The pre-amplifier converts the charge generated by a pyroelectric transducer into a voltage signal, which provides a measurement of the temperature variation in biological fluids. The proposed design is capable of providing 0.8-mV/pC gain while consuming only 2.1 μW of power. Finally, the pre-amplifier composed of integrated components occupies an area of 0.038 mm 2.« less

A Charge Sensitive Pre-Amplifier for Smart Point-of-Care Devices Employing Polymer Based Lab-on-a-Chip

DOE PAGES

Wang, Hanfeng; Britton, Charles; Quaiyum, Farhan; ...

2018-01-01

With increasing emphasis on implantable and portable medical devices, low-power, small-chip-area sensor readout system realized in lab-on-a-chip (LOC) platform is gaining more and more importance these days. The main building blocks of the LOC system include a front-end transducer that generates an electrical signal in response to the presence of an analyte of interest, signal processing electronics to process the signal to comply with a specific transmission protocol and a low-power transmitter, all realized in a single integrated circuit platform. Low power consumption and compactness of the components are essential requirements of the LOC system. This paper presents a novelmore » charge sensitive pre-amplifier developed in a standard 180-nm CMOS process suitable for implementing in an LOC platform. The pre-amplifier converts the charge generated by a pyroelectric transducer into a voltage signal, which provides a measurement of the temperature variation in biological fluids. The proposed design is capable of providing 0.8-mV/pC gain while consuming only 2.1 μW of power. Finally, the pre-amplifier composed of integrated components occupies an area of 0.038 mm 2.« less

Low-noise front-end electronics for detection of intermediate-frequency weak light signals

NASA Astrophysics Data System (ADS)

Lin, Cunbao; Yan, Shuhua; Du, Zhiguang; Wei, Chunhua; Wang, Guochao

2015-02-01

A novel low-noise front-end electronics was proposed for detection of light signals with intensity about 10 μW and frequency above 2.7 MHz. The direct current (DC) power supply, pre-amplifier and main-amplifier were first designed, simulated and then realized. Small-size components were used to make the power supply small, and the pre-amplifier and main-amplifier were the least capacitors to avoid the phase shift of the signals. The performance of the developed front-end electronics was verified in cross-grating diffraction experiments. The results indicated that the output peak-topeak noise of the +/-5 V DC power supply was about 2 mV, and the total output current was 1.25 A. The signal-to-noise ratio (SNR) of the output signal of the pre-amplifier was about 50 dB, and it increased to nearly 60 dB after the mainamplifier, which means this front-end electronics was especially suitable for using in the phase-sensitive and integrated precision measurement systems.

Front-End Processing of Cell Lysates for Enhanced Chip-Based Detection

DTIC Science & Technology

2006-07-28

manipulation used in lab-on-a-chip devices. A small unknown sample is first mixed with the PNA surfactants (“PNAA”) to tag the DNA targets, and then the...unknown sample is first mixed with the PNA surfactants (hereafter referred to as “PNA amphiphiles” or “PNAA”) to tag the DNA targets, and then the...prolate ellipsoid, and mixed PNAA/SDS micelles form spherical micelles. On addition of complementary DNA, the PNAA/DNA duplexes do not participate in

Front-end Electronics for Unattended Measurement (FEUM). Prototype Test Plan

DOE Office of Scientific and Technical Information (OSTI.GOV)

Conrad, Ryan C.; Morris, Scott J.; Smith, Leon E.

2015-09-16

The IAEA has requested that PNNL perform an initial set of tests on front-end electronics for unattended measurement (FEUM) prototypes. The FEUM prototype test plan details the tests to be performed, the criteria for evaluation, and the procedures used to execute the tests.

Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy

PubMed Central

Valente, Virgilio; Demosthenous, Andreas

2016-01-01

This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) channels suitable for both bipolar and tetrapolar electrical impedance spectroscopy (EIS) analysis. Each VR channel occupies an area of 0.48 mm2, is capable of an operational bandwidth of 8 MHz and a linear gain in the range between −6 dB and 42 dB. The gain of the CR channel can be set to 10 kΩ, 50 kΩ or 100 kΩ and is capable of 80-dB dynamic range, with a very linear response for input currents between 10 nA and 100 μA. Each CR channel occupies an area of 0.21 mm2. The chip consumes between 530 μA and 690 μA per channel and operates from a 1.8-V supply. The chip was used to measure the impedance of capacitive interdigitated electrodes in saline solution. Measurements show close matching with results obtained using a commercial impedance analyser. The chip will be part of a fully flexible and configurable fully-integrated dual-mode EIS system for impedance sensors and bioimpedance analysis. PMID:27463721

Readout, first- and second-level triggers of the new Belle silicon vertex detector

NASA Astrophysics Data System (ADS)

Friedl, M.; Abe, R.; Abe, T.; Aihara, H.; Asano, Y.; Aso, T.; Bakich, A.; Browder, T.; Chang, M. C.; Chao, Y.; Chen, K. F.; Chidzik, S.; Dalseno, J.; Dowd, R.; Dragic, J.; Everton, C. W.; Fernholz, R.; Fujii, H.; Gao, Z. W.; Gordon, A.; Guo, Y. N.; Haba, J.; Hara, K.; Hara, T.; Harada, Y.; Haruyama, T.; Hasuko, K.; Hayashi, K.; Hazumi, M.; Heenan, E. M.; Higuchi, T.; Hirai, H.; Hitomi, N.; Igarashi, A.; Igarashi, Y.; Ikeda, H.; Ishino, H.; Itoh, K.; Iwaida, S.; Kaneko, J.; Kapusta, P.; Karawatzki, R.; Kasami, K.; Kawai, H.; Kawasaki, T.; Kibayashi, A.; Koike, S.; Korpar, S.; Križan, P.; Kurashiro, H.; Kusaka, A.; Lesiak, T.; Limosani, A.; Lin, W. C.; Marlow, D.; Matsumoto, H.; Mikami, Y.; Miyake, H.; Moloney, G. R.; Mori, T.; Nakadaira, T.; Nakano, Y.; Natkaniec, Z.; Nozaki, S.; Ohkubo, R.; Ohno, F.; Okuno, S.; Onuki, Y.; Ostrowicz, W.; Ozaki, H.; Peak, L.; Pernicka, M.; Rosen, M.; Rozanska, M.; Sato, N.; Schmid, S.; Shibata, T.; Stamen, R.; Stanič, S.; Steininger, H.; Sumisawa, K.; Suzuki, J.; Tajima, H.; Tajima, O.; Takahashi, K.; Takasaki, F.; Tamura, N.; Tanaka, M.; Taylor, G. N.; Terazaki, H.; Tomura, T.; Trabelsi, K.; Trischuk, W.; Tsuboyama, T.; Uchida, K.; Ueno, K.; Ueno, K.; Uozaki, N.; Ushiroda, Y.; Vahsen, S.; Varner, G.; Varvell, K.; Velikzhanin, Y. S.; Wang, C. C.; Wang, M. Z.; Watanabe, M.; Watanabe, Y.; Yamada, Y.; Yamamoto, H.; Yamashita, Y.; Yamashita, Y.; Yamauchi, M.; Yanai, H.; Yang, R.; Yasu, Y.; Yokoyama, M.; Ziegler, T.; Žontar, D.

2004-12-01

A major upgrade of the Silicon Vertex Detector (SVD 2.0) of the Belle experiment at the KEKB factory was installed along with new front-end and back-end electronics systems during the summer shutdown period in 2003 to cope with higher particle rates, improve the track resolution and meet the increasing requirements of radiation tolerance. The SVD 2.0 detector modules are read out by VA1TA chips which provide "fast or" (hit) signals that are combined by the back-end FADCTF modules to coarse, but immediate level 0 track trigger signals at rates of several tens of a kHz. Moreover, the digitized detector signals are compared to threshold lookup tables in the FADCTFs to pass on hit information on a single strip basis to the subsequent level 1.5 trigger system, which reduces the rate below the kHz range. Both FADCTF and level 1.5 electronics make use of parallel real-time processing in Field Programmable Gate Arrays (FPGAs), while further data acquisition and event building is done by PC farms running Linux. The new readout system hardware is described and the first results obtained with cosmics are shown.

Optical and electrical interfacing technologies for living cell bio-chips.

PubMed

Shacham-Diamand, Y; Belkin, S; Rishpon, J; Elad, T; Melamed, S; Biran, A; Yagur-Kroll, S; Almog, R; Daniel, R; Ben-Yoav, H; Rabner, A; Vernick, S; Elman, N; Popovtzer, R

2010-06-01

Whole-cell bio-chips for functional sensing integrate living cells on miniaturized platforms made by micro-system-technologies (MST). The cells are integrated, deposited or immersed in a media which is in contact with the chip. The cells behavior is monitored via electrical, electrochemical or optical methods. In this paper we describe such whole-cell biochips where the signal is generated due to the genetic response of the cells. The solid-state platform hosts the biological component, i.e. the living cells, and integrates all the required micro-system technologies, i.e. the micro-electronics, micro-electro optics, micro-electro or magneto mechanics and micro-fluidics. The genetic response of the cells expresses proteins that generate: a. light by photo-luminescence or bioluminescence, b. electrochemical signal by interaction with a substrate, or c. change in the cell impedance. The cell response is detected by a front end unit that converts it to current or voltage amplifies and filters it. The resultant signal is analyzed and stored for further processing. In this paper we describe three examples of whole-cell bio chips, photo-luminescent, bioluminescent and electrochemical, which are based on the genetic response of genetically modified E. coli microbes integrated on a micro-fluidics MEMS platform. We describe the chip outline as well as the basic modeling scheme of such sensors. We discuss the highlights and problems of such system, from the point of view of micro-system-technology.

Novel x-ray silicon detector for 2D imaging and high-resolution spectroscopy

NASA Astrophysics Data System (ADS)

Castoldi, Andrea; Gatti, Emilio; Guazzoni, Chiara; Longoni, Antonio; Rehak, Pavel; Strueder, Lothar

1999-10-01

A novel x-ray silicon detector for 2D imaging has been recently proposed. The detector, called Controlled-Drift Detector, is operated in integrate-readout mode. Its basic feature is the fast transport of the integrated charge to the output electrode by means of a uniform drift field. The drift time of the charge packet identifies the pixel of incidence. A new architecture to implement the Controlled- Drift Detector concept will be presented. The potential wells for the integration of the signal charge are obtained by means of a suitable pattern of deep n-implants and deep p-implants. During the readout mode the signal electrons are transferred in the drift channel that flanks each column of potential wells where they drift towards the collecting electrode at constant velocity. The first experimental measurements demonstrate the successful integration, transfer and drift of the signal electrons. The low output capacitance of the readout electrode together with the on- chip front-end electronics allows high resolution spectroscopy of the detected photons.

Science Enabling ASICs and FEEs for the JUICE and JEO Missions

NASA Technical Reports Server (NTRS)

Paschalidis, Nicholas; Sittler, Ed; Cooper, John; Christian, Eric; Moore, Tom

2011-01-01

A family of science enabling radiation hard Application Specific Integrated Circuits (ASICs), Front End Electronics (FEEs) and Event Processing Systems, with flight heritage on many NASA missions, is presented. These technologies play an important role in the miniaturization of instruments -and spacecraft systems- at the same time increasing performance and reducing power. The technologies target time of flight, position sensing, and energy measurements as well as standard housekeeping and telemetry functions for particle and fields instruments, but find applications in other instrument categories too. More specifically the technologies include: the TOF chip, 1D and 2D Delay Lines with MCP detectors, for high precision fast and low power time of flight and position sensing; the Energy chip for multichannel SSD readout with time over threshold and standard voltage read out for TDC and ADC digitization; Fast multi channel read out chip with commandable thresholds; the TRIO chip for multiplexed ADC and housekeeping etc. It should be mentioned that the ASICs include basic trigger capabilities to enable random event processing in a heavy background of penetrators and UV foreground. Typical instruments include time of flight versus energy and look angle particle analyzers such as: plasma composition, energetic particle, neutral atom imaging as well as fast plasma and deltaE/E ion/electron telescopes. Flight missions include: Cassini/LEMMS, IMAGE/HENA, MESSENGER/EPPS/MLA/X-ray/MLA, STEREO, PLUTO-NH/PEPSSI/LORI, IBEX-Lo, JUNO/JEDI, RBSP/RBSPICE, MMS/HPCA/EPD, SO/SIS. Given the proven capability on heavy radiation missions such as JUNO, MMS and RBSB, as well diverse long duration missions such as MESSENGER, PLUTO and Cassini, it is expected that these technologies will play an important role in the particle and fields (at least) instruments on the upcoming JUICE and JEO missions.

Design and characterization of the PREC (Prototype Readout Electronics for Counting particles)

NASA Astrophysics Data System (ADS)

Assis, P.; Brogueira, P.; Ferreira, M.; Luz, R.; Mendes, L.

2016-08-01

The design, tests and performance of a novel, low noise, acquisition system—the PREC (Prototype Readout Electronics for Counting particles) is presented in this article. PREC is a system developed using discrete electronics for particle counting applications using RPCs (Resistive Plate Chamber) detectors. PREC can, however, be used with other kind of detectors that present fast pulses, e.g. Silicon Photomultipliers. The PREC system consists in several Front-End boards that transmit data to a purely digital Motherboard. The amplification and discrimination of the signal is performed in the Front-End boards, making them the critical component of the system. In this paper, the Front-End was tested extensively by measuring the gain, noise level, crosstalk, trigger efficiency, propagation time and power consumption. The gain shows a decrease with the working temperature and an increase with the power supply voltage. The Front-End board shows a low noise level (<= 1.6 mV at 3σ level) and no crosstalk is detected above this level. The s-curve of the trigger efficiency is characterized by a 3 mV gap from the region where most of the signals are triggered to almost no signal is triggered. The signal transit time between the Front-End input and the digital Motherboard is estimated to be 5.82 ns. The maximum power consumption is 3.372 W for the Motherboard and 3.576 W and 1.443 W for each Front-End analogue circuitry and digital part, respectively.

Test of ATLAS RPCs Front-End electronics

NASA Astrophysics Data System (ADS)

Aielli, G.; Camarri, P.; Cardarelli, R.; Di Ciaccio, A.; Di Stante, L.; Liberti, B.; Paoloni, A.; Pastori, E.; Santonico, R.

2003-08-01

The Front-End Electronics performing the ATLAS RPCs readout is a full custom 8 channels GaAs circuit, which integrates in a single die both the analog and digital signal processing. The die is bonded on the Front-End board which is completely closed inside the detector Faraday cage. About 50 000 FE boards are foreseen for the experiment. The complete functionality of the FE boards will be certificated before the detector assembly. We describe here the systematic test devoted to check the dynamic functionality of each single channel and the selection criteria applied. It measures and registers all relevant electronics parameters to build up a complete database for the experiment. The statistical results from more than 1100 channels are presented.

FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

NASA Astrophysics Data System (ADS)

Anderson, J.; Bauer, K.; Borga, A.; Boterenbrood, H.; Chen, H.; Chen, K.; Drake, G.; Dönszelmann, M.; Francis, D.; Guest, D.; Gorini, B.; Joos, M.; Lanni, F.; Lehmann Miotto, G.; Levinson, L.; Narevicius, J.; Panduro Vazquez, W.; Roich, A.; Ryu, S.; Schreuder, F.; Schumacher, J.; Vandelli, W.; Vermeulen, J.; Whiteson, D.; Wu, W.; Zhang, J.

2016-12-01

The ATLAS Phase-I upgrade (2019) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

A 0.5 cm(3) four-channel 1.1 mW wireless biosignal interface with 20 m range.

PubMed

Morrison, Tim; Nagaraju, Manohar; Winslow, Brent; Bernard, Amy; Otis, Brian P

2014-02-01

This paper presents a self-contained, single-chip biosignal monitoring system with wireless programmability and telemetry interface suitable for mainstream healthcare applications. The system consists of low-noise front end amplifiers, ADC, MICS/ISM transmitter and infrared programming capability to configure the state of the chip. An on-chip packetizer ensures easy pairing with standard off-the-shelf receivers. The chip is realized in the IBM 130 nm CMOS process with an area of 2×2 mm(2). The entire system consumes 1.07 mW from a 1.2 V supply. It weighs 0.6 g including a zinc-air battery. The system has been extensively tested in in vivo biological experiments and requires minimal human interaction or calibration.

2.5 Gbit/s Optical Receiver Front-End Circuit with High Sensitivity and Wide Dynamic Range

NASA Astrophysics Data System (ADS)

Zhu, Tiezhu; Mo, Taishan; Ye, Tianchun

2017-12-01

An optical receiver front-end circuit is designed for passive optical network and fabricated in a 0.18 um CMOS technology. The whole circuit consists of a transimpedance amplifier (TIA), a single-ended to differential amplifier and an output driver. The TIA employs a cascode stage as the input stage and auxiliary amplifier to reduce the miller effect. Current injecting technique is employed to enlarge the input transistor's transconductance, optimize the noise performance and overcome the lack of voltage headroom. To achieve a wide dynamic range, an automatic gain control circuit with self-adaptive function is proposed. Experiment results show an optical sensitivity of -28 dBm for a bit error rate of 10-10 at 2.5 Gbit/s and a maxim input optical power of 2 dBm using an external photodiode. The chip occupies an area of 1×0.9 mm2 and consumes around 30 mW from single 1.8 V supply. The front-end circuit can be used in various optical receivers.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, K.; Chen, H.; Wu, W.

We present that in the upgrade of ATLAS experiment, the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, themore » GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system is used to interface the front end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. Finally, the system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.« less

Optimization on fixed low latency implementation of the GBT core in FPGA

DOE PAGES

Chen, K.; Chen, H.; Wu, W.; ...

2017-07-11

We present that in the upgrade of ATLAS experiment, the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, themore » GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system is used to interface the front end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. Finally, the system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.« less

Optimization on fixed low latency implementation of the GBT core in FPGA

NASA Astrophysics Data System (ADS)

Chen, K.; Chen, H.; Wu, W.; Xu, H.; Yao, L.

2017-07-01

In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

Novel Micromegas trackers

NASA Astrophysics Data System (ADS)

Sabatie, Franck

2017-09-01

The latest development in Micromegas trackers includes the Micromegas Vertex Tracker (MVT) soon to be installed in Jefferson Lab Hall B, in the CLAS12 central tracking system. The MVT is composed of 6 cylindrical layers and 6 flat disks of resistive bulk Micromegas detectors. They have been designed to withstand the high particle flux environment and the high magnetic field using a low material budget of less than 0.5% of a radiation length per detector. The MVT is read out using front-end electronics based on the ``Dream'' Asic developed at CEA Saclay/Irfu. The low material budget requirements and very stringent space restrictions of the central tracking system surrounded by a 5T solenoid prevent the use of on-detector frontend electronics. The ability of the Dream chip to work with high-capacitance detectors allows deploying the electronics some 2 m away using flat micro-coaxial cables. After a short introduction to Micromegas detectors and the state-of-the-art achievements in this technology, I will focus on the CLAS12 MVT detector system, from the fabrication techniques to the readout electronics. Possible future developments will briefly be presented as well.

Compact Receiver Front Ends for Submillimeter-Wave Applications

NASA Technical Reports Server (NTRS)

Mehdi, Imran; Chattopadhyay, Goutam; Schlecht, Erich T.; Lin, Robert H.; Sin, Seth; Peralta, Alejandro; Lee, Choonsup; Gill, John J.; Gulkis, Samuel; Thomas, Bertrand C.

2012-01-01

The current generation of submillimeter-wave instruments is relatively mass and power-hungry. The receiver front ends (RFEs) of a submillimeter instrument form the heart of the instrument, and any mass reduction achieved in this subsystem is propagated through the instrument. In the current implementation, the RFE consists of different blocks for the mixer and LO circuits. The motivation for this work is to reduce the mass of the RFE by integrating the mixer and LO circuits in one waveguide block. The mixer and its associated LO chips will all be packaged in a single waveguide package. This will reduce the mass of the RFE and also provide a number of other advantages. By bringing the mixer and LO circuits close together, losses in the waveguide will be reduced. Moreover, the compact nature of the block will allow for better thermal control of the block, which is important in order to reduce gain fluctuations. A single waveguide block with a 600- GHz RFE functionality (based on a subharmonically pumped Schottky diode pair) has been demonstrated. The block is about 3x3x3 cubic centimeters. The block combines the mixer and multiplier chip in a single package. 3D electromagnetic simulations were carried out to design the waveguide circuit around the mixer and multiplier chip. The circuit is optimized to provide maximum output power and maximum bandwidth. An integrated submillimeter front end featuring a 520-600-GHz sub-harmonic mixer and a 260-300-GHz frequency tripler in a single cavity was tested. Both devices used GaAs MMIC membrane planar Schottky diode technology. The sub-harmonic mixer/tripler circuit has been tested using conventional metal-machined blocks. Measurement results on the metal block give best DSB (double sideband) mixer noise temperature of 2,360 K and conversion losses of 7.7 dB at 520 GHz. The LO input power required to pump the integrated tripler/sub-harmonic mixer is between 30 and 50 mW.

Monitoring the CMS strip tracker readout system

NASA Astrophysics Data System (ADS)

Mersi, S.; Bainbridge, R.; Baulieu, G.; Bel, S.; Cole, J.; Cripps, N.; Delaere, C.; Drouhin, F.; Fulcher, J.; Giassi, A.; Gross, L.; Hahn, K.; Mirabito, L.; Nikolic, M.; Tkaczyk, S.; Wingham, M.

2008-07-01

The CMS Silicon Strip Tracker at the LHC comprises a sensitive area of approximately 200 m2 and 10 million readout channels. Its data acquisition system is based around a custom analogue front-end chip. Both the control and the readout of the front-end electronics are performed by off-detector VME boards in the counting room, which digitise the raw event data and perform zero-suppression and formatting. The data acquisition system uses the CMS online software framework to configure, control and monitor the hardware components and steer the data acquisition. The first data analysis is performed online within the official CMS reconstruction framework, which provides many services, such as distributed analysis, access to geometry and conditions data, and a Data Quality Monitoring tool based on the online physics reconstruction. The data acquisition monitoring of the Strip Tracker uses both the data acquisition and the reconstruction software frameworks in order to provide real-time feedback to shifters on the operational state of the detector, archiving for later analysis and possibly trigger automatic recovery actions in case of errors. Here we review the proposed architecture of the monitoring system and we describe its software components, which are already in place, the various monitoring streams available, and our experiences of operating and monitoring a large-scale system.

Electro-optical detector for use in a wide mass range mass spectrometer

NASA Technical Reports Server (NTRS)

Giffin, Charles E. (Inventor)

1976-01-01

An electro-optical detector is disclosed for use in a wide mass range mass spectrometer (MS), in the latter the focal plane is at or very near the exit end of the magnetic analyzer, so that a strong magnetic field of the order of 1000G or more is present at the focal plane location. The novel detector includes a microchannel electron multiplier array (MCA) which is positioned at the focal plane to convert ion beams which are focused by the MS at the focal plane into corresponding electron beams which are then accelerated to form visual images on a conductive phosphored surface. These visual images are then converted into images on the target of a vidicon camera or the like for electronic processing. Due to the strong magnetic field at the focal plane, in one embodiment of the invention, the MCA with front and back parallel ends is placed so that its front end forms an angle of not less than several degrees, preferably on the order of 10.degree.-20.degree., with respect to the focal plane, with the center line of the front end preferably located in the focal plane. In another embodiment the MCA is wedge-shaped, with its back end at an angle of about 10.degree.-20.degree. with respect to the front end. In this embodiment the MCA is placed so that its front end is located at the focal plane.

FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

DOE Office of Scientific and Technical Information (OSTI.GOV)

Anderson, J.; Bauer, K.; Borga, A.

The ATLAS Phase-I upgrade (2019) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. Furthermore, the Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. Here, the FELIX system, the design of the PCIe prototypemore » card and the integration test results are presented.« less

FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

DOE PAGES

Anderson, J.; Bauer, K.; Borga, A.; ...

2016-12-13

The ATLAS Phase-I upgrade (2019) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. Furthermore, the Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. Here, the FELIX system, the design of the PCIe prototypemore » card and the integration test results are presented.« less

Readout ASICs and Electronics for the 144-channel HAPDs for the Aerogel RICH at Belle II

NASA Astrophysics Data System (ADS)

Nishida, S.; Adachi, I.; Ikeda, H.; Hara, K.; Iijima, T.; Iwata, S.; Korpar, S.; Križan, P.; Kuroda, E.; Pestotnik, R.; Seljak, A.; Sumiyoshi, T.; Takagaki, H.

The particle identification (PID) device in the endcap of the Belle detector will be upgraded to a ring imaging Cherenkov counter (RICH) using aerogel as a radiator at the Belle II experiment. We develop the electronics to read out the 70,000 channels of hit information from the 144-channel hybrid avalanche photodetectors (HAPD), of the aerogel RICH detector. A readout ASIC is developed to digitize the HAPD signals, and was used in a beam test with the prototype detector. The performance and plan of the ASIC is reported in this study. We have also designed the readout electronics for the aerogel RICH, which consist of front-end boards with the ASICs merger boards to collect data from the front-end boards. A front-end board that fits in the actual available space for the aerogel RICH electronics was produced.

Search for New Physics in Top Quark Production and Upgrade of the CMS Hadron Calorimeter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yumiceva, Francisco

2016-10-07

Our goal is to measure precisely the properties of the heaviest subatomic particle ever discovered, the top quark. In the proton-proton collisions at the LHC, top quarks are produced copiously. The largest set of top quarks recorded by the CMS detector make it an ideal laboratory to measure properties such as its mass and the rate at which pair of top quarks are produced in association with energetic photons. Quantum electrodynamics, or QED, describes the emission of light by charged particles and is the most precise physics theory ever devised. Typically this means light emitted by electrons, but any chargedmore » particles will do, such as the top quark. Studies of the light-emitting properties of top quarks help us to refine our current theoretical predictions at the finest level, and provide additional tools to study in more detail the recently discovered Higgs boson particle. However, during this process, the studies may reveal interesting features not yet observed. Deviations from the standard predictions would be a strong sign of something entirely new. These new physics theories are motivated to answer the current big mysteries in the universe such as what is the nature of mass or what is dark matter. As the LHC increases the collision energy and its luminosity, the detectors need to be improved to cope with these high-luminosity scenarios. New sensors will be installed in the hadron calorimeter detectors along with new front and end electronics at the end of 2016. We are testing and calibrating the new front-end readout electronics that will allow us to have more options to reduce the noise on these detectors. In order to do this calibration, we have developed a system that can inject electric charge in the full range of the charge integrator chip, the QIE ASICs.« less

On-chip copper-dielectric interference filters for manufacturing of ambient light and proximity CMOS sensors.

PubMed

Frey, Laurent; Masarotto, Lilian; D'Aillon, Patrick Gros; Pellé, Catherine; Armand, Marilyn; Marty, Michel; Jamin-Mornet, Clémence; Lhostis, Sandrine; Le Briz, Olivier

2014-07-10

Filter technologies implemented on CMOS image sensors for spectrally selective applications often use a combination of on-chip organic resists and an external substrate with multilayer dielectric coatings. The photopic-like and near-infrared bandpass filtering functions respectively required by ambient light sensing and user proximity detection through time-of-flight can be fully integrated on chip with multilayer metal-dielectric filters. Copper, silicon nitride, and silicon oxide are the materials selected for a technological proof-of-concept on functional wafers, due to their immediate availability in front-end semiconductor fabs. Filter optical designs are optimized with respect to specific performance criteria, and the robustness of the designs regarding process errors are evaluated for industrialization purposes.

First results of the front-end ASIC for the strip detector of the PANDA MVD

NASA Astrophysics Data System (ADS)

Quagli, T.; Brinkmann, K.-T.; Calvo, D.; Di Pietro, V.; Lai, A.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Wheadon, R.; Zambanini, A.

2017-03-01

PANDA is a key experiment of the future FAIR facility and the Micro Vertex Detector (MVD) is the innermost part of its tracking system. PASTA (PAnda STrip ASIC) is the readout chip for the strip part of the MVD. The chip is designed to provide high resolution timestamp and charge information with the Time over Threshold (ToT) technique. Its architecture is based on Time to Digital Converters with analog interpolators, with a time bin width of 50 ps. The chip implements Single Event Upset (SEU) protection techniques for its digital parts. A first full-size prototype with 64 channels was produced in a commercial 110 nm CMOS technology and the first characterizations of the prototype were performed.

A multichannel compact readout system for single photon detection: Design and performances

NASA Astrophysics Data System (ADS)

Argentieri, A. G.; Cisbani, E.; Colilli, S.; Cusanno, F.; De Leo, R.; Fratoni, R.; Garibaldi, F.; Giuliani, F.; Gricia, M.; Lucentini, M.; Marra, M.; Musico, Paolo; Santavenere, F.; Torrioli, S.

2010-05-01

Optimal exploitation of Multi Anode PhotoMultiplier Tubes (MAPMT) as imaging devices requires the acquisition of a large number of independent channels; despite the rather wide demand, on-the-shelf electronics for this purpose does not exist. A compact independent channel readout system for an array of MAPMTs has been developed and tested [1,2]. The system can handle up to 4096 independent channels, covering an area of about 20×20 cm2 with pixel size of 3×3 mm2, using Hamamatsu H-9500 devices. The front-end is based on a 64 channels VLSI custom chip called MAROC, developed by IN2P3 Orsay (France) group, controlled by means of a Field Programmable Gate Array (FPGA) which implements configuration, triggering and data conversion controls. Up to 64 front-end cards can be housed in four backplanes and a central unit collects data from all of them, communicating with a control Personal Computer (PC) using an high speed USB 2.0 connection. A complete system has been built and tested. Eight Flat MAPMTs (256 anodes Hamamatsu H-9500) have been arranged on a boundary of a 3×3 matrix for a grand total of 2048 channels. This detector has been used to verify the performances of a focusing aerogel RICH prototype using an electron beam at the Frascati (Rome) INFN National Laboratory Beam Test Facility (BTF) during the last week of January 2009. Data analysis is ongoing: the first results are encouraging, showing that the Cherenkov rings are well identified by this system.

The Belle II Silicon Vertex Detector

NASA Astrophysics Data System (ADS)

Friedl, M.; Ackermann, K.; Aihara, H.; Aziz, T.; Bergauer, T.; Bozek, A.; Campbell, A.; Dingfelder, J.; Drasal, Z.; Frankenberger, A.; Gadow, K.; Gfall, I.; Haba, J.; Hara, K.; Hara, T.; Higuchi, T.; Himori, S.; Irmler, C.; Ishikawa, A.; Joo, C.; Kah, D. H.; Kang, K. H.; Kato, E.; Kiesling, C.; Kodys, P.; Kohriki, T.; Koike, S.; Kvasnicka, P.; Marinas, C.; Mayekar, S. N.; Mibe, T.; Mohanty, G. B.; Moll, A.; Negishi, K.; Nakayama, H.; Natkaniec, Z.; Niebuhr, C.; Onuki, Y.; Ostrowicz, W.; Park, H.; Rao, K. K.; Ritter, M.; Rozanska, M.; Saito, T.; Sakai, K.; Sato, N.; Schmid, S.; Schnell, M.; Shimizu, N.; Steininger, H.; Tanaka, S.; Tanida, K.; Taylor, G.; Tsuboyama, T.; Ueno, K.; Uozumi, S.; Ushiroda, Y.; Valentan, M.; Yamamoto, H.

2013-12-01

The KEKB machine and the Belle experiment in Tsukuba (Japan) are now undergoing an upgrade, leading to an ultimate luminosity of 8×1035 cm-2 s-1 in order to measure rare decays in the B system with high statistics. The previous vertex detector cannot cope with this 40-fold increase of luminosity and thus needs to be replaced. Belle II will be equipped with a two-layer Pixel Detector surrounding the beam pipe, and four layers of double-sided silicon strip sensors at higher radii than the old detector. The Silicon Vertex Detector (SVD) will have a total sensitive area of 1.13 m2 and 223,744 channels-twice as many as its predecessor. All silicon sensors will be made from 150 mm wafers in order to maximize their size and thus to reduce the relative contribution of the support structure. The forward part has slanted sensors of trapezoidal shape to improve the measurement precision and to minimize the amount of material as seen by particles from the vertex. Fast-shaping front-end amplifiers will be used in conjunction with an online hit time reconstruction algorithm in order to reduce the occupancy to the level of a few percent at most. A novel “Origami” chip-on-sensor scheme is used to minimize both the distance between strips and amplifier (thus reducing the electronic noise) as well as the overall material budget. This report gives an overview on the status of the Belle II SVD and its components, including sensors, front-end detector ladders, mechanics, cooling and the readout electronics.

The new front-end electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

NASA Astrophysics Data System (ADS)

Gomes, A.

2016-02-01

We present the plans, design, and performance results to date for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increased luminosity at the HL-LHC around 2025, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector. The new on-detector electronics contains five main parts: the front-end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low voltage power supply. There are different options for implementing these subcomponents, which will be described. The new system contains new features that in the current version include power system redundancy, data collection redundancy, data transmission redundancy with 2 QSFP optical transceivers and Kintex-7 FPGAs with firmware enhanced scheme for single event upset mitigation. To date, we have built a Demonstrator—a fully functional prototype of the new system. Performance results and plans are presented.

Market trends in the projection display industry

NASA Astrophysics Data System (ADS)

Dash, Sweta

2001-03-01

The projection display industry represents a multibillion- dollar market that includes four distinct technologies. High-volume consumer products and high-value business products drive the market, with different technologies being used in different application markets. The consumer market is dominated by rear CRT technology, especially in the projection TV segment. Rear LCD (liquid crystal display), MEMS/DLP (or Digital Light Processing TM) and LCOS (Liquid-crystal-on-silicon) TVs are slowly emerging as future competitors to rear CRT projectors. Front CRT projectors are also facing challenges from LCD and DLP technology for the home theater market while the business market is completely dominated by front LCD and DLP technology. Three-chip DLP projectors have replaced liquid crystal light valves in large venue applications where projectors have higher light output requirements. In recent years front LCD and LCOS projectors have been increasingly competing with 3-chip DLP projectors especially at the low end of the large venue application market. Within the next five years the projection market will experience very fast growth. Sales and presentation applications, which are the fastest growing applications in the business market, will continue to be the major driving force for the growth for front projectors, and the shift in the consumer market to digital and HDTV products will drive the rear projection market.

A 0.09 μW low power front-end biopotential amplifier for biosignal recording.

PubMed

Tseng, Yuhwai; Ho, Yingchieh; Kao, Shuoting; Su, Chauchin

2012-10-01

This work presents a biopotential front-end amplifier in which the MOS transistors are biased in subthreshold region with a supply voltage and current of 0.4-0.8 V and 0.23-1.86 μA, respectively, to reduce the system power. Flicker noise is then removed using a chopping technique, and differential interference produced by electrode impedance imbalance is suppressed using a Gm-C filter. Additionally, the circuit is fabricated using TSMC 0.18 μm CMOS technology with a core area of 0.77 × 0.36 mm². With a minimum supply voltage of 0.4 V, the measured SNR and power consumption of the proposed IC chip are 54.1 dB and 0.09μW, respectively.

Passive front-ends for wideband millimeter wave electronic warfare

NASA Astrophysics Data System (ADS)

Jastram, Nathan Joseph

This thesis presents the analysis, design and measurements of novel passive front ends of interest to millimeter wave electronic warfare systems. However, emerging threats in the millimeter waves (18 GHz and above) has led to a push for new systems capable of addressing these threats. At these frequencies, traditional techniques of design and fabrication are challenging due to small size, limited bandwidth and losses. The use of surface micromachining technology for wideband direction finding with multiple element antenna arrays for electronic support is demonstrated. A wideband tapered slot antenna is first designed and measured as an array element for the subsequent arrays. Both 18--36 GHz and 75--110 GHz amplitude only and amplitude/phase two element direction finding front ends are designed and measured. The design of arrays using Butler matrix and Rotman lens beamformers for greater than two element direction finding over W band and beyond using is also presented. The design of a dual polarized high power capable front end for electronic attack over an 18--45 GHz band is presented. To combine two polarizations into the same radiating aperture, an orthomode transducer (OMT) based upon a new double ridge waveguide cross section is developed. To provide greater flexibility in needed performance characteristics, several different turnstile junction matching sections are tested. A modular horn section is proposed to address flexible and ever changing operational requirements, and is designed for performance criteria such as constant gain, beamwidth, etc. A multi-section branch guide coupler and low loss Rotman lens based upon the proposed cross section are also developed. Prototyping methods for the herein designed millimeter wave electronic warfare front ends are investigated. Specifically, both printed circuit board (PCB) prototyping of micromachined systems and 3D printing of conventionally machined horns are presented. A 4--8 GHz two element array with integrated beamformer fabricated using the stacking of PCB boards is shown, and measured results compare favorably with the micromachined front ends. A 3D printed small aperture horn is compared with a conventionally machined horn, and measured results show similar performance with a ten-fold reduction in cost and weight.

Absolute dose calibration of an X-ray system and dead time investigations of photon-counting techniques

NASA Astrophysics Data System (ADS)

Carpentieri, C.; Schwarz, C.; Ludwig, J.; Ashfaq, A.; Fiederle, M.

2002-07-01

High precision concerning the dose calibration of X-ray sources is required when counting and integrating methods are compared. The dose calibration for a dental X-ray tube was executed with special dose calibration equipment (dosimeter) as function of exposure time and rate. Results were compared with a benchmark spectrum and agree within ±1.5%. Dead time investigations with the Medipix1 photon-counting chip (PCC) have been performed by rate variations. Two different types of dead time, paralysable and non-paralysable will be discussed. The dead time depends on settings of the front-end electronics and is a function of signal height, which might lead to systematic defects of systems. Dead time losses in excess of 30% have been found for the PCC at 200 kHz absorbed photons per pixel.

All-Dielectric Photonic-Assisted Radio Front-End Technology

NASA Astrophysics Data System (ADS)

Ayazi, Hossein Ali

The threats to civil society posed by high-power electromagnetic weapons are viewed as a grim but real possibility in the world after 11 September 2001. These weapons produce a power surge capable of destroying or damaging sensitive circuitry in electronic systems. Unfortunately, the trend towards circuits with smaller sizes and voltages renders modern electronics highly susceptible to such damage. Radiofrequency communication systems are particularly vulnerable, because the antenna provides a direct port of entry for electromagnetic radiation. In this work, we present a novel type of radiofrequency receiver front end featuring a complete absence of electronic circuitry and metal interconnects, the traditional 'soft spots' of a conventional radiofrequency receiver. The device exploits a dielectric resonator antenna to capture and deliver the radiofrequency signal onto a whispering-gallery mode electro-optic field sensor. The dielectric approach has an added benefit in that it reduces the physical size of the front end, an important benefit in mobile applications.

STIC3 - Silicon Photomultiplier Timing Chip with picosecond resolution

NASA Astrophysics Data System (ADS)

Stankova, Vera; Shen, Wei; Briggl, Konrad; Chen, Huangshan; Fischer, Peter; Gil, Alejandro; Harion, Tobias; Kiworra, Volker; Munwes, Yonathan; Ritzert, Michael; Schultz-Coulon, Hans-Christian

2015-07-01

The diagnostic of pancreas and prostate cancer is a challenging task due to the background noise coming from the closer organs. The EndoToFPET-US project aims to combine the synergy between metabolic and anatomical (ultrasound) image in order to improve the precision in the tumor localization. The goal of the project is to develop a Positron Emission Tomography (PET) system that provides a time-of-flight resolution of 200 ps FWHM for improving the signal to noise ratio and further to improve the medical image quality. In order to achieve this purpose an ASIC has been designed for very high timing resolution in time-of-flight (ToF) applications. In this paper we present the ASIC performance and the first characterization measurements with the 64-channels prototype version (STiC3). Measurements are performed with LYSO scintillator crystal and a Multi Pixel Photon Counter (MPPC). Measurements with the chip show an analog-front-end stage jitter of 35 ps for the first photo-electron equivalent charge and reach 18 ps for the third photo-electron. Coincidence time resolution (CTR) of 240 ps FWHM is measured with 3.1×3.1×15 mm3 LYSO crystal and 50 μm pixel pitch MPPC. Further optimization including the Time-to-Digital Converter (TDC) non-linearity corrections and setup fine tuning are ongoing for achieving the desired CTR of 200 ps FWHM.

Integrated front-end electronics in a detector compatible process: source-follower and charge-sensitive preamplifier configurations

NASA Astrophysics Data System (ADS)

Ratti, Lodovico; Manghisoni, Massimo; Re, Valerio; Speziali, Valeria

2001-12-01

This study is concerned with the simulation and design of low-noise front-end electronics monolithically integrated on the same high-resistivity substrate as multielectrode silicon detectors, in a process made available by the Istituto per la Ricerca Scientifica e Tecnologica (ITC-IRST) of Trento, Italy. The integrated front-end solutions described in this paper use N-channel JFETs as basic elements. The first one is based upon an all-NJFET charge preamplifier designed to match detector capacitances of a few picofarads and available in both a resistive and a non resistive feedback configuration. In the second solution, a single NJFET in the source-follower configuration is connected to the detector, while its source is wired to an external readout channel through an integrated capacitor.

Architecture of PAU survey camera readout electronics

NASA Astrophysics Data System (ADS)

Castilla, Javier; Cardiel-Sas, Laia; De Vicente, Juan; Illa, Joseph; Jimenez, Jorge; Maiorino, Marino; Martinez, Gustavo

2012-07-01

PAUCam is a new camera for studying the physics of the accelerating universe. The camera will consist of eighteen 2Kx4K HPK CCDs: sixteen for science and two for guiding. The camera will be installed at the prime focus of the WHT (William Herschel Telescope). In this contribution, the architecture of the readout electronics system is presented. Back- End and Front-End electronics are described. Back-End consists of clock, bias and video processing boards, mounted on Monsoon crates. The Front-End is based on patch panel boards. These boards are plugged outside the camera feed-through panel for signal distribution. Inside the camera, individual preamplifier boards plus kapton cable completes the path to connect to each CCD. The overall signal distribution and grounding scheme is shown in this paper.

Recent progress of RD53 Collaboration towards next generation Pixel Read-Out Chip for HL-LHC

DOE PAGES

Demaria, N.

2016-12-21

This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. Critical building blocks and analog very front end chains have been designed, tested before and after 5–800 Mrad. Small prototypes of 64×64 pixels with complex digital architectures have been produced, and point to address the main issues of dealing with extremely high pixel rates, while operating at very small in-time thresholds in the analog front end. Lastly, the collaborationmore » is now proceeding at full speed towards the design of a large scale prototype, called RD53A, in 65 nm CMOS technology.« less

A CMOS Front-End With Integrated Magnetoresistive Sensors for Biomolecular Recognition Detection Applications.

PubMed

Costa, Tiago; Cardoso, Filipe A; Germano, Jose; Freitas, Paulo P; Piedade, Moises S

2017-10-01

The development of giant magnetoresistive (GMR) sensors has demonstrated significant advantages in nanomedicine, particularly for ultrasensitive point-of-care diagnostics. To this end, the detection system is required to be compact, portable, and low power consuming at the same time that a maximum signal to noise ratio is maintained. This paper reports a CMOS front-end with integrated magnetoresistive sensors for biomolecular recognition detection applications. Based on the characterization of the GMR sensor's signal and noise, CMOS building blocks (i.e., current source, multiplexers, and preamplifier) were designed targeting a negligible noise when compared with the GMR sensor's noise and a low power consumption. The CMOS front-end was fabricated using AMS [Formula: see text] technology and the magnetoresistive sensors were post-fabricated on top of the CMOS chip with high yield ( [Formula: see text]). Due to its low circuit noise (16 [Formula: see text]) and overall equivalent magnetic noise ([Formula: see text]), the full system was able to detect 250 nm magnetic nanoparticles with a circuit imposed signal-to-noise ratio degradation of only -1.4 dB. Furthermore, the low power consumption (6.5 mW) and small dimensions ([Formula: see text] ) of the presented solution guarantees the portability of the detection system allowing its usage at the point-of-care.

The 150 ns detector project: Prototype preamplifier results

NASA Astrophysics Data System (ADS)

Warburton, W. K.; Russell, S. R.; Kleinfelder, Stuart A.

1994-08-01

The long-term goal of the 150 ns detector project is to develop a pixel area detector capable of 6 MHz frame rates (150 ns/frame). Our milestones toward this goal are: a single pixel, 1×256 1D and 8×8 2D detectors, 256×256 2D detectors and, finally, 1024 × 1024 2D detectors. The design strategy is to supply a complete electronics chain (resetting preamp, selectable gain amplifier, analog-to-digital converter (ADC), and memory) for each pixel. In the final detectors these will all be custom integrated circuits. The front-end preamplifiers are integrated first, since their design and performance are the most unusual and also critical to the project's success. Similarly, our early work is concentrated on devising and perfecting detector structures. In this paper we demonstrate the performance of prototypes of our integrated preamplifiers. While the final design will have 64 preamps to a chip, including a switchable gain stage, the prototypes were integrated 8 channels to a "Tiny Chip" and tested in 4 configurations (feedback capacitor Cf equal 2.5 or 4.0 pF, output directly or through a source follower). These devices have been tested thoroughly for reset settling times, gain, linearity, and electronic noise. They generally work as designed, being fast enough to easily integrate detector charge, settle, and reset in 150 ns. Gain and linearity appear to be acceptable. Current values of electronic noise, in double-sampling mode, are about twice the design goal of {2}/{3} of a single photon at 6 keV. We expect this figure to improve with the addition of the onboard amplifier stage and improved packaging. Our next test chip will include these improvements and allow testing with our first detector samples, which will be 1×256 (50 μm wide pixels) and 8×8 (1 mm 2 pixels) element detector on 1 mm thick silicon.

A front-end electronic system for large arrays of bolometers

NASA Astrophysics Data System (ADS)

Arnaboldi, C.; Carniti, P.; Cassina, L.; Gotti, C.; Liu, X.; Maino, M.; Pessina, G.; Rosenfeld, C.; Zhu, B. X.

2018-02-01

CUORE is an array of thermal calorimeters composed of 988 crystals held at about 10 mK, whose absorbed energy is read out with semiconductor thermistors. The composition of the crystal is TeO2, and the aim is the study of the double beta decay of 130Te on very long and stable runs. CUPID-0 is an array of 26 Zn82Se crystals with double thermistor readout to study the double beta decay of 82Se. In the present paper, we present an overview of the entire front-end electronic readout chain, from the preamplifier to the anti-aliasing filter. This overview includes motivations, design strategies, circuit implementation and performance results of the electronic system, including other auxiliary yet important elements like power supplies and the slow control communication system. The stringent requirements of stability on the very long experimental runs that are foreseen during CUORE and CUPID-0 operation, are achieved thanks to novel solutions of the front-end preamplifier and of the detector bias circuit setup.

The OPERA muon spectrometer tracking electronics

NASA Astrophysics Data System (ADS)

Ambrosio, M.; Barichello, G.; Brugnera, R.; Carrara, E.; Consiglio, L.; Corradi, A.; Dal Corso, F.; Dusini, S.; Felici, G.; Garfagnini, A.; Manea, C.; Masone, V.; Paoloni, A.; Paoluzzi, G.; Papalino, G.; Parascandolo, P.; Sorrentino, G.; Spinetti, M.; Stanco, L.; Terranova, F.; Votano, L.

2004-11-01

The document describes the front-end electronics that instrument the spectrometer of the OPERA experiment. The spectrometer is made of two separate modules. Each module consists of 22 RPC planes equipped with horizontal and vertical strips readout for a total amount of about 25,000 digital channels. The front end electronics is self-triggered and has single plane readout capability. It is made of three different stages: the Front End Boards (FEBs) system, the Controller Boards (CBs) system and the Timing Boards (TBs) system. The FEB system provides discrimination of the strip incoming signals; a FAST OR output of the input signals is also available for trigger plane signal generation. FEBs discriminated signals are acquired by the CBs system that manages also the communication to the experiment DAQ and Slow Control interface. A Trigger Board allows to operate in both self-trigger (the FEB FAST OR signal starts the plane acquisition) or external-trigger (different conditions can be set on the OR signals generated from different planes) modes.

Holistic design in high-speed optical interconnects

NASA Astrophysics Data System (ADS)

Saeedi, Saman

Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a corresponding increase in inter-chip communication bandwidth. As bandwidth requirements for chip-to-chip interconnection scale, deficiencies of electrical channels become more apparent. Optical links present a viable alternative due to their low frequency-dependent loss and higher bandwidth density in the form of wavelength division multiplexing. As integrated photonics and bonding technologies are maturing, commercialization of hybrid-integrated optical links are becoming a reality. Increasing silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics brings their performance to unprecedented levels. This thesis presents developments in high-speed optical links by co-designing and co-integrating the primary elements of an optical link: receiver, transmitter, and clocking. In the first part of this thesis a 3D-integrated CMOS/Silicon-photonic receiver will be presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. Measured results show -14.9dBm of sensitivity and energy eciency of 170fJ/b at 25Gb/s. The same receiver front-end is also used to implement source-synchronous 4-channel WDM-based parallel optical receiver. Quadrature ILO-based clocking is employed for synchronization and a novel frequency-tracking method that exploits the dynamics of IL in a quadrature ring oscillator to increase the effective locking range. An adaptive body-biasing circuit is designed to maintain the per-bit-energy consumption constant across wide data-rates. The prototype measurements indicate a record-low power consumption of 153fJ/b at 32Gb/s. The receiver sensitivity is measured to be -8.8dBm at 32Gb/s. Next, on the optical transmitter side, three new techniques will be presented. First one is a differential ring modulator that breaks the optical bandwidth/quality factor trade-off known to limit the speed of high-Q ring modulators. This structure maintains a constant energy in the ring to avoid pattern-dependent power droop. As a first proof of concept, a prototype has been fabricated and measured up to 10Gb/s. The second technique is thermal stabilization of micro-ring resonator modulators through direct measurement of temperature using a monolithic PTAT temperature sensor. The measured temperature is used in a feedback loop to adjust the thermal tuner of the ring. A prototype is fabricated and a closed-loop feedback system is demonstrated to operate at 20Gb/s in the presence of temperature fluctuations. The third technique is a switched-capacitor based pre-emphasis technique designed to extend the inherently low bandwidth of carrier injection micro-ring modulators. A measured prototype of the optical transmitter achieves energy efficiency of 342fJ/bit at 10Gb/s and the wavelength stabilization circuit based on the monolithic PTAT sensor consumes 0.29mW. Lastly, a first-order frequency synthesizer that is suitable for high-speed on-chip clock generation will be discussed. The proposed design features an architecture combining an LC quadrature VCO, two sample-and-holds, a PI, digital coarse-tuning, and rotational frequency detection for fine-tuning. In addition to an electrical reference clock, as an extra feature, the prototype chip is capable of receiving a low jitter optical reference clock generated by a high-repetition-rate mode-locked laser. The output clock at 8GHz has an integrated RMS jitter of 490fs, peak-to-peak periodic jitter of 2.06ps, and total RMS jitter of 680fs. The reference spurs are measured to be 64.3dB below the carrier frequency. At 8GHz the system consumes 2.49mW from a 1V supply.

New Detector Developments for Future UV Space Missions

NASA Astrophysics Data System (ADS)

Werner, Klaus; Kappelmann, Norbert

Ultraviolet (UV) astronomy is facing “dark ages”: After the shutdown of the Hubble Space Tele-scope only the WSO/UV mission will be operable in the UV wavelength region with efficient instruments. Improved optics and detectors are necessary for future successor missions to tackle new scientific goals. This drives our development of microchannel plate (MCP) UV-detectors with high quantum efficiency, high spatial resolution and low-power readout electronics. To enhance the quantum efficiency and the lifetime of the MCP detectors we are developing new cathodes and new anodes for these detectors. To achieve high quantum efficiency, we will use caesium-activated gallium nitride as semitransparent photocathodes with a much higher efficiency than default CsI/CsTe cathodes in this wavelength range. The new anodes will be cross-strip anodes with 64 horizontal and 64 vertical electrodes. This type of anode requires a lower gain and leads to an increased lifetime of the detector, compared to MCP detectors with other anode types. The heart of the new developed front-end-electronic for such type of anode is the so called “BEETLE chip”, which was designed by the MPI für Kernphysik Heidelberg for the LHCb ex-periment at CERN. This chip provides 128 input channels with charge-sensitive preamplifiers and shapers. Our design of the complete front-end readout electronics enables a total power con-sumption of less than 10 W. The MCP detector is intrinsically solar blind, single photon counting and has a very low read-out noise. To qualify this new type of detectors we are presently planning to build a small UV telescope for the usage on the German Technology Experimental Carrier (TET). Furthermore we are involved in the new German initiative for a Public Telescope, a space telescope equipped with an 80 cm mirror. One of the main instruments will be a high-resolution UV-Echelle Spectrograph that will be built by the University of Tübingen. The launch of this mission is scheduled for 2017.

Characterization of Multianode Photomultiplier Tubes for a Cherenkov Detector

NASA Astrophysics Data System (ADS)

Benninghoff, Morgen; Turisini, Matteo; Kim, Andrey; Benmokhtar, Fatiha; Kubarovsky, Valery; Duquesne University Collaboration; Jefferson Lab Collaboration

2017-09-01

In the Fall of 2017, Jefferson Lab's CLAS12 (CEBAF Large Acceptance Spectrometer) detector is expecting the addition of a RICH (ring imaging Cherenkov) detector which will allow enhanced particle identification in the momentum range of 3 to 8 GeV/c. RICH detectors measure the velocity of charged particles through the detection of produced Cherenkov radiation and the reconstruction of the angle of emission. The emitted Cherenkov photons are detected by a triangular-shaped grid of 391 multianode photomultiplier tubes (MAPMTs) made by Hamamatsu. The custom readout electronics consist of MAROC (multianode read out chip) boards controlled by FPGA (Field Programmable Gate Array) boards, and adapters used to connect the MAROC boards and MAPMTs. The focus of this project is the characterization of the MAPMTs with the new front end electronics. To perform these tests, a black box setup with a picosecond diode laser was constructed with low and high voltage supplies. A highly automated procedure was developed to acquire data at different combinations of high voltage values, light intensities and readout electronics settings. Future work involves using the collected data in calibration procedures and analyzing that data to resolve the best location for each MAPMT. SULI, NSF.

Design and demonstration of ultra-fast W-band photonic transmitter-mixer and detectors for 25 Gbits/sec error-free wireless linking.

PubMed

Chen, Nan-Wei; Shi, Jin-Wei; Tsai, Hsuan-Ju; Wun, Jhih-Min; Kuo, Fong-Ming; Hesler, Jeffery; Crowe, Thomas W; Bowers, John E

2012-09-10

A 25 Gbits/s error-free on-off-keying (OOK) wireless link between an ultra high-speed W-band photonic transmitter-mixer (PTM) and a fast W-band envelope detector is demonstrated. At the transmission end, the high-speed PTM is developed with an active near-ballistic uni-traveling carrier photodiode (NBUTC-PD) integrated with broadband front-end circuitry via the flip-chip bonding technique. Compared to our previous work, the wireless data rate is significantly increased through the improvement on the bandwidth of the front-end circuitry together with the reduction of the intermediate-frequency (IF) driving voltage of the active NBUTC-PD. The demonstrated PTM has a record-wide IF modulation (DC-25 GHz) and optical-to-electrical fractional bandwidths (68-128 GHz, ~67%). At the receiver end, the demodulation is realized with an ultra-fast W-band envelope detector built with a zero-bias Schottky barrier diode with a record wide video bandwidth (37 GHz) and excellent sensitivity. The demonstrated PTM is expected to find applications in multi-gigabit short-range wireless communication.

Deep Space Network, Cryogenic HEMT LNAs

NASA Technical Reports Server (NTRS)

Bautista, J. Javier

2006-01-01

Exploration of the Solar System with automated spacecraft that are more than ten astronomical units (1 AU = 149,597,870.691 km) from earth requires very large antennae employing extremely sensitive receivers. A key figure of merit in the specification of the spacecraft-to-earth telecommunications link is the ratio of the antenna gain to operatio nal noise temperature (G/Top) of the system. The Deep Space Network (DSN) receivers are cryogenic, low-noise amplifiers (LNAs) which addres s the need to maintain Top as low as technology permits. Historicall y, the extra-ordinarily sensitive receive systems operated by the DSN have required ctyogenically cooled, ruby masers, operating at a physi cal temperature near the boiling point of helium, as the LNA. Althoug h masers continue to be used today, they are hand crafted at JPL and expensive to manufacture and maintain. Recent advances in the developm ent of indium phosphide (InP) based high electron mobility transistor s (HEMTs) combined with cryogenic cooling near the boiling point of h ydrogen have made this alternate technology comparable with and a fraction of the cost of maser technology. InP HEMT LNA modules are demons trating noise temperatures less than ten times the quantum noise limi t (10hf/k) from 1 to 100 GHz. To date, the lowest noise LNA modules developed for the DSN have demonstrated noise temperatures of 3.5 K and 8.5 K at 8.5 K at 32 GHz, respectively. Front-end receiver packages employing these modules have demonstrated operating system noise temperatures of 17 K at 8.4 GHz (on a 70m antenna at zenith) and 39 K at 3 2 GHz (on a 34m antenna at zenith). The development and demonstration of cryogenic, InP HEMT based front-end amplifiers for the DSN requir es accurate component and module characterization, and modeling from 1 to 100 GHz at physical temperatures down to 12 K. The characterizati on and modeling begins with the HEMT chip, proceeds to the multi-stag e HEMT LNA module, and culminates with the complete front-end cryogenic receiver package for the antenna. This presentation will provide a n overview of this development process. Examples will be shown for de vices, LNA modules, front-end receiver packages, antennae employing these packages and the improvements to the down-link capacity.

A low power low noise analog front end for portable healthcare system

NASA Astrophysics Data System (ADS)

Yanchao, Wang; Keren, Ke; Wenhui, Qin; Yajie, Qin; Ting, Yi; Zhiliang, Hong

2015-10-01

The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5-100 Hz) and the achieved noise efficient factor is 6.48. Project supported by the Science and Technology Commission of Shanghai Municipality (No. 13511501100), the State Key Laboratory Project of China (No. 11MS002), and the State Key Laboratory of ASIC & System, Fudan University.

Low power analog front-end electronics in deep submicrometer CMOS technology based on gain enhancement techniques

NASA Astrophysics Data System (ADS)

Gómez-Galán, J. A.; Sánchez-Rodríguez, T.; Sánchez-Raya, M.; Martel, I.; López-Martín, A.; Carvajal, R. G.; Ramírez-Angulo, J.

2014-06-01

This paper evaluates the design of front-end electronics in modern technologies to be used in a new generation of heavy ion detectors—HYDE (FAIR, Germany)—proposing novel architectures to achieve high gain in a low voltage environment. As conventional topologies of operational amplifiers in modern CMOS processes show limitations in terms of gain, novel approaches must be raised. The work addresses the design using transistors with channel length of no more than double the feature size and a supply voltage as low as 1.2 V. A front-end system has been fabricated in a 90 nm process including gain boosting techniques based on regulated cascode circuits. The analog channel has been optimized to match a detector capacitance of 5 pF and exhibits a good performance in terms of gain, speed, linearity and power consumption.

Development of a front end controller/heap manager for PHENIX

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ericson, M.N.; Allen, M.D.; Musrock, M.S.

1996-12-31

A controller/heap manager has been designed for applicability to all detector subsystem types of PHENIX. the heap manager performs all functions associated with front end electronics control including ADC and analog memory control, data collection, command interpretation and execution, and data packet forming and communication. Interfaces to the unit consist of a timing and control bus, a serial bus, a parallel data bus, and a trigger interface. The topology developed is modular so that many functional blocks are identical for a number of subsystem types. Programmability is maximized through the use of flexible modular functions and implementation using field programmablemore » gate arrays (FPGAs). Details of unit design and functionality will be discussed with particular detail given to subsystems having analog memory-based front end electronics. In addition, mode control, serial functions, and FPGA implementation details will be presented.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the first six months of this project were to lay the foundations for both the SiC front-end optical chip fabrication as well as the free-space laser beam interferometer designs and preliminary tests. In addition, a Phase I goal was to design and experimentally build the high temperature and pressure infrastructure and test systems that will be used in the next 6 months for proposed sensor experimentation and data processing. All these goals have been achieved and are described in detail in the report. Both design process and diagrams for the mechanical elements as well as the opticalmore » systems are provided. In addition, photographs of the fabricated SiC optical chips, the high temperature & pressure test chamber instrument, the optical interferometer, the SiC sample chip holder, and signal processing data are provided. The design and experimentation results are summarized to give positive conclusions on the proposed novel high temperature optical sensor technology.« less

A 30 GHz monolithic receive module technology assessment

NASA Technical Reports Server (NTRS)

Geddes, J.; Sokolov, V.; Bauhahn, P.; Contolatis, T.

1988-01-01

This report is a technology assessment relevant to the 30 GHz Monolithic Receive Module development. It is based on results obtained on the present NASA Contract (NAS3-23356) as well as on information gathered from literature and other industry sources. To date the on-going Honeywell program has concentrated on demonstrating the so-called interconnected receive module which consists of four monolithic chips - the low noise front-end amplifier (LNA), the five bit phase shifter (PS), the gain control amplifier (GC), and the RF to IF downconverter (RF/IF). Results on all four individual chips have been obtained and interconnection of the first three functions has been accomplished. Future work on this contract is aimed at a higher level of integration, i.e., integration of the first three functions (LNA + PS + GC) on a single GaAs chip. The report presents the status of this technology and projections of its future directions.

MuTRiG: a mixed signal Silicon Photomultiplier readout ASIC with high timing resolution and gigabit data link

NASA Astrophysics Data System (ADS)

Chen, H.; Briggl, K.; Eckert, P.; Harion, T.; Munwes, Y.; Shen, W.; Stankova, V.; Schultz-Coulon, H. C.

2017-01-01

MuTRiG is a mixed signal Silicon Photomultiplier readout ASIC designed in UMC 180 nm CMOS technology for precise timing and high event rate applications in high energy physics experiments and medical imaging. It is dedicated to the readout of the scintillating fiber detector and the scintillating tile detector of the Mu3e experiment. The MuTRiG chip extends the excellent timing performance of the STiCv3 chip with a fast digital readout for high rate applications. The high timing performance of the fully differential SiPM readout channels and 50 ps time binning TDCs are complemented by an upgraded digital readout logic and a 1.28 Gbps LVDS serial data link. The design of the chip and the characterization results of the analog front-end, TDC and the LVDS data link are presented.

RF-Interrogated End-State Chip-Scale Atomic Clock

DTIC Science & Technology

2007-11-01

coherent population trapping,” Electronics Letters 37, (24), 1449-1451. [2] R. Lutwak , P. Vlitas, M. Varghese, M. Mescher, D. K. Serkland, and G. M...367. [9] R. Lutwak , D. Emmons, T. English, W. Riley, A. Duwel, M. Varghese, D. K. Serland, and G. M. Peake, 2003, “Chip-Scale Atomic Clock, Recent

Low-power, transparent optical network interface for high bandwidth off-chip interconnects.

PubMed

Liboiron-Ladouceur, Odile; Wang, Howard; Garg, Ajay S; Bergman, Keren

2009-04-13

The recent emergence of multicore architectures and chip multiprocessors (CMPs) has accelerated the bandwidth requirements in high-performance processors for both on-chip and off-chip interconnects. For next generation computing clusters, the delivery of scalable power efficient off-chip communications to each compute node has emerged as a key bottleneck to realizing the full computational performance of these systems. The power dissipation is dominated by the off-chip interface and the necessity to drive high-speed signals over long distances. We present a scalable photonic network interface approach that fully exploits the bandwidth capacity offered by optical interconnects while offering significant power savings over traditional E/O and O/E approaches. The power-efficient interface optically aggregates electronic serial data streams into a multiple WDM channel packet structure at time-of-flight latencies. We demonstrate a scalable optical network interface with 70% improvement in power efficiency for a complete end-to-end PCI Express data transfer.

Front-end electronics and DAQ for the EURITRACK tagged neutron inspection system

NASA Astrophysics Data System (ADS)

Lunardon, M.; Bottosso, C.; Fabris, D.; Moretto, S.; Nebbia, G.; Pesente, S.; Viesti, G.; Bigongiari, A.; Colonna, A.; Tintori, C.; Valkovic, V.; Sudac, D.; Peerani, P.; Sequeira, V.; Salvato, M.

2007-08-01

The EURopean Illicit TRAfficing Countermeasures Kit (EURITRACK) Front-End and Data Acquisition System is a compact set of VME boards interfaced with a standard PC. The system is part of a cargo container inspection portal based on the tagged neutrons technique. The front-end processes all detector signals and checks coincidences between any of the 64 pixels of the alpha particle detector and any gamma-ray signals in 22 NaI(Tl) scintillators. The system is capable of handling the data flow at neutron flux up to the portal limiting value of 108 neutrons/second. Some typical applications are presented.

The Argonne CDF Group

Science.gov Websites

calorimeter, Shower Max., Preshower, Crack Chambers (1979-present) Run II Upgrade: Front end electronics (QIE , Preshower electronics and DAQ Support for Level-2 electron and photon triggers (RECES and ISO) Deputy Head

A Universal Intelligent System-on-Chip Based Sensor Interface

PubMed Central

Mattoli, Virgilio; Mondini, Alessio; Mazzolai, Barbara; Ferri, Gabriele; Dario, Paolo

2010-01-01

The need for real-time/reliable/low-maintenance distributed monitoring systems, e.g., wireless sensor networks, has been becoming more and more evident in many applications in the environmental, agro-alimentary, medical, and industrial fields. The growing interest in technologies related to sensors is an important indicator of these new needs. The design and the realization of complex and/or distributed monitoring systems is often difficult due to the multitude of different electronic interfaces presented by the sensors available on the market. To address these issues the authors propose the concept of a Universal Intelligent Sensor Interface (UISI), a new low-cost system based on a single commercial chip able to convert a generic transducer into an intelligent sensor with multiple standardized interfaces. The device presented offers a flexible analog and/or digital front-end, able to interface different transducer typologies (such as conditioned, unconditioned, resistive, current output, capacitive and digital transducers). The device also provides enhanced processing and storage capabilities, as well as a configurable multi-standard output interface (including plug-and-play interface based on IEEE 1451.3). In this work the general concept of UISI and the design of reconfigurable hardware are presented, together with experimental test results validating the proposed device. PMID:22163624

Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

NASA Astrophysics Data System (ADS)

Zeng, Huiming; Wei, Tingcun; Wang, Jia

2017-03-01

A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal-oxide-semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 μm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e-+16.3e-/pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

Front-end Electronics for Unattended Measurement (FEUM). Results of Prototype Evaluation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Conrad, Ryan C.; Keller, Daniel T.; Morris, Scott J.

2015-07-01

The International Atomic Energy Agency (IAEA) deploys unattended monitoring systems to provide continuous monitoring of nuclear material within safeguarded facilities around the world. As the number of unattended monitoring instruments increases, the IAEA is challenged to become more efficient in the implementation of those systems. In 2010, the IAEA initiated the Front-End Electronics for Unattended Measurement (FEUM) project with the goals of greater flexibility in the interfaces to various sensors and data acquisition systems, and improved capabilities for remotely located sensors (e.g., where sensor and front-end electronics might be separated by tens of meters). In consultation with the IAEA, amore » technical evaluation of a candidate FEUM device produced by a commercial vendor has been performed. This evaluation assessed the device against the IAEA’s original technical specifications and a broad range of important parameters that include sensor types, cable lengths and types, industrial electromagnetic noise that can degrade signals from remotely located detectors, and high radiation fields. Testing data, interpretation, findings and recommendations are provided.« less

Efficient storage, computation, and exposure of computer-generated holograms by electron-beam lithography.

PubMed

Newman, D M; Hawley, R W; Goeckel, D L; Crawford, R D; Abraham, S; Gallagher, N C

1993-05-10

An efficient storage format was developed for computer-generated holograms for use in electron-beam lithography. This method employs run-length encoding and Lempel-Ziv-Welch compression and succeeds in exposing holograms that were previously infeasible owing to the hologram's tremendous pattern-data file size. These holograms also require significant computation; thus the algorithm was implemented on a parallel computer, which improved performance by 2 orders of magnitude. The decompression algorithm was integrated into the Cambridge electron-beam machine's front-end processor.Although this provides much-needed ability, some hardware enhancements will be required in the future to overcome inadequacies in the current front-end processor that result in a lengthy exposure time.

System-level considerations for the front-end readout ASIC in the CBM experiment from the power supply perspective

NASA Astrophysics Data System (ADS)

Kasinski, K.; Koczon, P.; Ayet, S.; Löchner, S.; Schmidt, C. J.

2017-03-01

New fixed target experiments using high intensity beams with energy up to 10 AGeV from the SIS100 synchrotron presently being constructed at FAIR/GSI are under preparation. Most of the readout electronics and power supplies are expected to be exposed to a very high flux of nuclear reaction products and have to be radiation tolerant up to 3 MRad (TID) and sustain up to 1014/cm2 of 1 MeV neutron equivalent in their life time. Moreover, the mostly minimum ionising particles under investigation leave very little signal in the sensors. Therefore very low noise level amplitude measurements are required by the front-end electronics for effective tracking. Sensor and interconnecting micro-cable capacitance and series resistance in conjunction with intrinsic noise of the charge sensitive amplifier are dominant noise sources in the system. However, the single-ended architecture of the amplifiers employed for the charge processing channels implies a potential problem with noise contributions from power supply sources. Strict system-level constraints leave very little freedom in selecting a power supply structure optimal with respect to: power efficiency, cooling capabilities and power density on modules, but also noise injection to the front-end via the power supply lines. Design of the power supply and distribution system of the Silicon Tracking System in the CBM experiment together with details on the front-end ASICs (STS -XYTER2) and measurement results of power supply and conditioning electronics (selected DC/DC converter and LDO regulators) are presented.

A Monolithic Multisensor Microchip with Complete On-Chip RF Front-End

PubMed Central

Felini, Corrado; Della Corte, Francesco G.

2018-01-01

In this paper, a new wireless sensor, designed for a 0.35 µm CMOS technology, is presented. The microchip was designed to be placed on an object for the continuous remote monitoring of its temperature and illumination state. The temperature sensor is based on the temperature dependence of the I-V characteristics of bipolar transistors available in CMOS technology, while the illumination sensor is an integrated p-n junction photodiode. An on-chip 2.5 GHz transmitter, coupled to a mm-sized dipole radiating element fabricated on the same microchip and made in the top metal layer of the same die, sends the collected data wirelessly to a radio receiver using an On-Off Keying (OOK) modulation pattern. PMID:29301297

Front-end electronics for the LZ experiment

NASA Astrophysics Data System (ADS)

Morad, James; LZ Collaboration

2016-03-01

LZ is a second generation direct dark matter detection experiment with 5.6 tonnes of liquid xenon active target, which will be instrumented as a two-phase time projection chamber (TPC). The peripheral xenon outside the active TPC (``skin'') will also be instrumented. In addition, there will be a liquid scintillator based outer veto surrounding the main cryostat. All of these systems will be read out using photomultiplier tubes. I will present the designs for front-end electronics for all these systems, which have been optimized for shaping times, gains, and low noise. Preliminary results from prototype boards will also be presented.

Propagating gene expression fronts in a one-dimensional coupled system of artificial cells

NASA Astrophysics Data System (ADS)

Tayar, Alexandra M.; Karzbrun, Eyal; Noireaux, Vincent; Bar-Ziv, Roy H.

2015-12-01

Living systems employ front propagation and spatiotemporal patterns encoded in biochemical reactions for communication, self-organization and computation. Emulating such dynamics in minimal systems is important for understanding physical principles in living cells and in vitro. Here, we report a one-dimensional array of DNA compartments in a silicon chip as a coupled system of artificial cells, offering the means to implement reaction-diffusion dynamics by integrated genetic circuits and chip geometry. Using a bistable circuit we programmed a front of protein synthesis propagating in the array as a cascade of signal amplification and short-range diffusion. The front velocity is maximal at a saddle-node bifurcation from a bistable regime with travelling fronts to a monostable regime that is spatially homogeneous. Near the bifurcation the system exhibits large variability between compartments, providing a possible mechanism for population diversity. This demonstrates that on-chip integrated gene circuits are dynamical systems driving spatiotemporal patterns, cellular variability and symmetry breaking.

Upgraded Readout Electronics for the ATLAS Liquid Argon Calorimeters at the High Luminosity LHC

NASA Astrophysics Data System (ADS)

Andeen, Timothy R.; ATLAS Liquid Argon Calorimeter Group

2012-12-01

The ATLAS liquid-argon calorimeters produce a total of 182,486 signals which are digitized and processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics sum analog signals to provide coarsely grained energy sums, called trigger towers, to the first-level trigger system, which is optimized for nominal LHC luminosities. However, the pile-up background expected during the high luminosity phases of the LHC will be increased by factors of 3 to 7. An improved spatial granularity of the trigger primitives is therefore proposed in order to improve the identification performance for trigger signatures, like electrons or photons, at high background rejection rates. For the first upgrade phase in 2018, new Liquid Argon Trigger Digitizer Boards are being designed to receive higher granularity signals, digitize them on detector and send them via fast optical links to a new, off-detector digital processing system. The digital processing system applies digital filtering and identifies significant energy depositions. The refined trigger primitives are then transmitted to the first level trigger system to extract improved trigger signatures. The general concept of the upgraded liquid-argon calorimeter readout together with the various electronics components to be developed for such a complex system is presented. The research activities and architectural studies undertaken by the ATLAS Liquid Argon Calorimeter Group are described, particularly details of the on-going design of mixed-signal front-end electronics, of radiation tolerant optical-links, and of the high-speed off-detector digital processing system.

A Test Apparatus for the MAJORANA DEMONSTRATOR Front-end Electronics

NASA Astrophysics Data System (ADS)

Singh, Harjit; Loach, James; Poon, Alan

2012-10-01

One of the most important experimental programs in neutrino physics is the search for neutrinoless double-beta decay. The MAJORANA collaboration is searching for this rare nuclear process in the Ge-76 isotope using HPGe detectors. Each detector is instrumented with high-performance electronics to read out and amplify the signals. The part of the electronics close to the detectors, consisting of a novel front-end circuit, cables and connectors, is made of radio-pure materials and is exceedingly delicate. In this work a dedicated test apparatus was created to benchmark the performance of the electronics before installation in the experiment. The apparatus was designed for cleanroom use, with fixtures to hold the components without contaminating them, and included the electronics necessary for power and readout. In addition to testing, the station will find longer term use in development of future versions of the electronics.

Mechanism of Void Prediction in Flip Chip Packages with Molded Underfill

NASA Astrophysics Data System (ADS)

Wu, Kuo-Tsai; Hwang, Sheng-Jye; Lee, Huei-Huang

2017-08-01

Voids have always been present using the molded underfill (MUF) package process, which is a problem that needs further investigation. In this study, the process was studied using the Moldex3D numerical analysis software. The effects of gas (air vent effect) on the overall melt front were also considered. In this isothermal process containing two fluids, the gas and melt colloid interact in the mold cavity. Simulation enabled an appropriate understanding of the actual situation to be gained, and, through analysis, the void region and exact location of voids were predicted. First, the global flow end area was observed to predict the void movement trend, and then the local flow ends were observed to predict the location and size of voids. In the MUF 518 case study, simulations predicted the void region as well as the location and size of the voids. The void phenomenon in a flip chip ball grid array underfill is discussed as part of the study.

PMF: The front end electronic of the ALFA detector

NASA Astrophysics Data System (ADS)

Barrillon, P.; Blin, S.; Cheikali, C.; Cuisy, D.; Gaspard, M.; Fournier, D.; Heller, M.; Iwanski, W.; Lavigne, B.; De la Taille, C.; Puzo, P.; Socha, J.-L.

2010-11-01

The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed of a MAPMT and a compact stack of three PCBs, which deliver high voltage, route and read out of the output signals. The third board contains an FPGA and MAROC, a 64-channel ASIC, which can correct the non-uniformity of the MAPMT channels gain, thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements and have fulfilled the approval criteria for the final production of all elements.

The HADES-RICH upgrade using Hamamatsu H12700 MAPMTs with DiRICH FEE + Readout

NASA Astrophysics Data System (ADS)

Patel, V.; Traxler, M.

2018-03-01

The High Acceptance Di-Electron Spectrometer (HADES) is operational since the year 2000 and uses a hadron blind RICH detector for electron identification. The RICH photon detector is currently replaced by Hamamatsu H12700 MAPMTs with a readout system based on the DiRICH front-end module. The electronic readout chain is being developed as a joint effort of the HADES-, CBM- and PANDA collaborations and will also be used in the photon detectors for the upcoming Compressed Baryonic Matter (CBM) and PANDA experiments at FAIR . This article gives a brief overview on the photomultipliers and their quality assurance test measurements, as well as first measurements of the new DiRICH front-end module in final configurations.

Particle identification using the time-over-threshold measurements in straw tube detectors

NASA Astrophysics Data System (ADS)

Jowzaee, S.; Fioravanti, E.; Gianotti, P.; Idzik, M.; Korcyl, G.; Palka, M.; Przyborowski, D.; Pysz, K.; Ritman, J.; Salabura, P.; Savrie, M.; Smyrski, J.; Strzempek, P.; Wintz, P.

2013-08-01

The identification of charged particles based on energy losses in straw tube detectors has been simulated. The response of a new front-end chip developed for the PANDA straw tube tracker was implemented in the simulations and corrections for track distance to sense wire were included. Separation power for p - K, p - π and K - π pairs obtained using the time-over-threshold technique was compared with the one based on the measurement of collected charge.

Asymmetric Multilevel Outphasing (AMO): A New Architecture for All-Silicon mm-Wave Transmitter ICs

DTIC Science & Technology

2015-06-12

power-amplifiers for mobile basestation infrastructure and handsets. NanoSemi Inc. designs linearization solutions for analog front-ends such as...ward flexible, multi-standard radio chips, increases the need for high-precision, high-throughput and energy-efficient backend processing. The desire...peak PAE is affected by less than 1% (46 mW/(46 mW 1.8 W/0.4)) by this 64-QAM capable AMO SCS backend . 378 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48

Satellite-On-A-Chip Feasibility for Distributed Space Missions

DTIC Science & Technology

2006-07-10

S.pdf Satellite Systems Conference and Exhibit, Monterey, [33] H . Helvajian and S. W. Janson, "The Fabrication of a CA, 2004, Paper AIAA-2004-3152. 100...pp. 12-15. 700. [52]0. Yadid-Pecht and R. Etienne-Cummings, CMOS [64]S. W. Janson, H . Helvajian , S. Amimoto, G. Smit, D. Imagers: From...Janson, H . Helvajian , and K. Breuer "MEMS, Hasler, "A 80 p W/frame 104x128 CMOS Imager Microengineering and Aerospace Systems," in Proc. Front End for

Ultrahigh Responsivity-Bandwidth Product in a Compact InP Nanopillar Phototransistor Directly Grown on Silicon

NASA Astrophysics Data System (ADS)

Ko, Wai Son; Bhattacharya, Indrasen; Tran, Thai-Truong D.; Ng, Kar Wei; Adair Gerke, Stephen; Chang-Hasnain, Connie

2016-09-01

Highly sensitive and fast photodetectors can enable low power, high bandwidth on-chip optical interconnects for silicon integrated electronics. III-V compound semiconductor direct-bandgap materials with high absorption coefficients are particularly promising for photodetection in energy-efficient optical links because of the potential to scale down the absorber size, and the resulting capacitance and dark current, while maintaining high quantum efficiency. We demonstrate a compact bipolar junction phototransistor with a high current gain (53.6), bandwidth (7 GHz) and responsivity (9.5 A/W) using a single crystalline indium phosphide nanopillar directly grown on a silicon substrate. Transistor gain is obtained at sub-picowatt optical power and collector bias close to the CMOS line voltage. The quantum efficiency-bandwidth product of 105 GHz is the highest for photodetectors on silicon. The bipolar junction phototransistor combines the receiver front end circuit and absorber into a monolithic integrated device, eliminating the wire capacitance between the detector and first amplifier stage.

A Micromegas-based telescope for muon tomography: The WatTo experiment

NASA Astrophysics Data System (ADS)

Bouteille, S.; Attié, D.; Baron, P.; Calvet, D.; Magnier, P.; Mandjavidze, I.; Procureur, S.; Riallot, M.; Winkler, M.

2016-10-01

This paper reports about the first Micromegas-based telescope built for applications in muon tomography. The telescope consists of four, 50×50 cm2 resistive multiplexed Micromegas with a 2D layout and a self-triggering electronics based on the Dream chip. Thanks to the multiplexing, the four detectors were readout with a single Front-End Unit. The high voltages were provided by a dedicated card using low consumption CAEN miniaturized modules. A nano-PC (Hummingboard) ensured the HV control and monitoring coupled with a temperature feedback as well as the data acquisition and storage. The overall consumption of the instrument yielded 30 W only, i.e. the equivalent of a standard bulb. The telescope was operated outside during 3.5 months to image the water tower of the CEA-Saclay research center, including a 1.5-month campaign with solar panels. The development of autonomous, low consumption muon telescopes with unprecedented accuracy opens new applications in imaging as well as in the field of muon metrology.

Ultrahigh Responsivity-Bandwidth Product in a Compact InP Nanopillar Phototransistor Directly Grown on Silicon

PubMed Central

Ko, Wai Son; Bhattacharya, Indrasen; Tran, Thai-Truong D.; Ng, Kar Wei; Adair Gerke, Stephen; Chang-Hasnain, Connie

2016-01-01

Highly sensitive and fast photodetectors can enable low power, high bandwidth on-chip optical interconnects for silicon integrated electronics. III-V compound semiconductor direct-bandgap materials with high absorption coefficients are particularly promising for photodetection in energy-efficient optical links because of the potential to scale down the absorber size, and the resulting capacitance and dark current, while maintaining high quantum efficiency. We demonstrate a compact bipolar junction phototransistor with a high current gain (53.6), bandwidth (7 GHz) and responsivity (9.5 A/W) using a single crystalline indium phosphide nanopillar directly grown on a silicon substrate. Transistor gain is obtained at sub-picowatt optical power and collector bias close to the CMOS line voltage. The quantum efficiency-bandwidth product of 105 GHz is the highest for photodetectors on silicon. The bipolar junction phototransistor combines the receiver front end circuit and absorber into a monolithic integrated device, eliminating the wire capacitance between the detector and first amplifier stage. PMID:27659796

Integrated input protection against discharges for Micro Pattern Gas Detectors readout ASICs

NASA Astrophysics Data System (ADS)

Fiutowski, T.; Dąbrowski, W.; Koperny, S.; Wiącek, P.

2017-02-01

Immunity against possible random discharges inside active detector volume of MPGDs is one of the key aspects that should be addressed in the design of the front-end electronics. This issue becomes particularly critical for systems with high channel counts and high density readout employing the front-end electronics built as multichannel ASICs implemented in modern CMOS technologies, for which the breakdown voltages are in the range of a few Volts. The paper presents the design of various input protection structures integrated in the ASIC manufactured in a 350 nm CMOS process and test results using an electrical circuit to mimic discharges in the detectors.

The Majorana Low-noise Low-background Front-end Electronics

NASA Astrophysics Data System (ADS)

Abgrall, N.; Aguayo, E.; Avignone, F. T.; Barabash, A. S.; Bertrand, F. E.; Boswell, M.; Brudanin, V.; Busch, M.; Byram, D.; Caldwell, A. S.; Chan, Y.-D.; Christofferson, C. D.; Combs, D. C.; Cuesta, C.; Detwiler, J. A.; Doe, P. J.; Efremenko, Yu.; Egorov, V.; Ejiri, H.; Elliott, S. R.; Fast, J. E.; Finnerty, P.; Fraenkle, F. M.; Galindo-Uribarri, A.; Giovanetti, G. K.; Goett, J.; Green, M. P.; Gruszko, J.; Guiseppe, V. E.; Gusev, K.; Hallin, A. L.; Hazama, R.; Hegai, A.; Henning, R.; Hoppe, E. W.; Howard, S.; Howe, M. A.; Keeter, K. J.; Kidd, M. F.; Kochetov, O.; Konovalov, S. I.; Kouzes, R. T.; LaFerriere, B. D.; Leon, J.; Leviner, L. E.; Loach, J. C.; MacMullin, J.; MacMullin, S.; Martin, R. D.; Meijer, S.; Mertens, S.; Nomachi, M.; Orrell, J. L.; O'Shaughnessy, C.; Overman, N. R.; Phillips, D. G.; Poon, A. W. P.; Pushkin, K.; Radford, D. C.; Rager, J.; Rielage, K.; Robertson, R. G. H.; Romero-Romero, E.; Ronquest, M. C.; Schubert, A. G.; Shanks, B.; Shima, T.; Shirchenko, M.; Snavely, K. J.; Snyder, N.; Suriano, A. M.; Thompson, J.; Timkin, V.; Tornow, W.; Trimble, J. E.; Varner, R. L.; Vasilyev, S.; Vetter, K.; Vorren, K.; White, B. R.; Wilkerson, J. F.; Wiseman, C.; Xu, W.; Yakushev, E.; Young, A. R.; Yu, C.-H.; Yumatov, V.

The MAJORANA DEMONSTRATOR will search for the neutrinoless double beta decay (ββ(0ν)) of the isotope 76Ge with a mixed array of enriched and natural germanium detectors. In view of the next generation of tonne-scale germanium-based ββ(0ν)-decay searches, a major goal of the MAJORANA DEMONSTRATOR is to demonstrate a path forward to achieving a background rate at or below 1 cnt/(ROI-t-y) in the 4 keV region of interest (ROI) around the 2039-keV Q-value of the 76Ge ββ(0ν)-decay. Such a requirement on the background level significantly constrains the design of the readout electronics, which is further driven by noise and energy resolution performances. We present here the low-noise low- background front-end electronics developed for the low-capacitance p-type point contact (P-PC) germanium detectors of the MAJORANA DEMONSTRATOR. This resistive-feedback front-end, specifically designed to have low mass, is fabricated on a radioassayed fused-silica substrate where the feedback resistor consists of a sputtered thin film of high purity amorphous germanium and the feedback capacitor is based on the capacitance between gold conductive traces.

The Majorana low-noise low-background front-end electronics

DOE PAGES

Abgrall, N.; Aguayo, E.; Avignone, III, F. T.; ...

2015-03-24

The Majorana Demonstrator will search for the neutrinoless double beta decay (ββ(0ν)) of the isotope ⁷⁶Ge with a mixed array of enriched and natural germanium detectors. In view of the next generation of tonne-scale germanium-based ββ(0ν)-decay searches, a major goal of the Majorana Demonstrator is to demonstrate a path forward to achieving a background rate at or below 1 cnt/(ROI-t-y) in the 4 keV region of interest (ROI) around the 2039-keV Q-value of the ⁷⁶Ge ββ(0ν)-decay. Such a requirement on the background level significantly constrains the design of the readout electronics, which is further driven by noise and energy resolutionmore » performances. We present here the low-noise low-background front-end electronics developed for the low-capacitance p-type point contact (P-PC) germanium detectors of the Majorana Demonstrator. This resistive-feedback front-end, specifically designed to have low mass, is fabricated on a radioassayed fused-silica substrate where the feedback resistor consists of a sputtered thin film of high purity amorphous germanium and the feedback capacitor is based on the capacitance between gold conductive traces.« less

Ultrafast-laser dicing of thin silicon wafers: strategies to improve front- and backside breaking strength

NASA Astrophysics Data System (ADS)

Domke, Matthias; Egle, Bernadette; Stroj, Sandra; Bodea, Marius; Schwarz, Elisabeth; Fasching, Gernot

2017-12-01

Thin 50-µm silicon wafers are used to improve heat dissipation of chips with high power densities. However, mechanical dicing methods cause chipping at the edges of the separated dies that reduce the mechanical stability. Thermal load changes may then lead to sudden chip failure. Recent investigations showed that the mechanical stability of the cut chips could be increased using ultrashort-pulsed lasers, but only at the laser entrance (front) side and not at the exit (back) side. The goal of this study was to find strategies to improve both front- and backside breaking strength of chips that were cut out of an 8″ wafer with power metallization using an ultrafast laser. In a first experiment, chips were cut by scanning the laser beam in single lines across the wafer using varying fluencies and scan speeds. Three-point bending tests of the cut chips were performed to measure front and backside breaking strengths. The results showed that the breaking strength of both sides increased with decreasing accumulated fluence per scan. Maximum breaking strengths of about 1100 MPa were achieved at the front side, but only below 600 MPa were measured for the backside. A second experiment was carried out to optimize the backside breaking strength. Here, parallel line scans to increase the distance between separated dies and step cuts to minimize the effect of decreasing fluence during scribing were performed. Bending tests revealed that breaking strengths of about 1100 MPa could be achieved also on the backside using the step cut. A reason for the superior performance could be found by calculating the fluence absorbed by the sidewalls. The calculations suggested that an optimal fluence level to minimize thermal side effects and periodic surface structures was achieved due to the step cut. Remarkably, the best breaking strengths values achieved in this study were even higher than the values obtained on state of the art ns-laser and mechanical dicing machines. This is the first study to the knowledge of the authors, which demonstrates that ultrafast-laser dicing improves the mechanical stability of thin silicon chips.

A Front-End electronics board for single photo-electron timing and charge from MaPMT

NASA Astrophysics Data System (ADS)

Giordano, F.; Breton, D.; Beigbeder, C.; De Robertis, G.; Fusco, P.; Gargano, F.; Liuzzi, R.; Loparco, F.; Mazziotta, M. N.; Rizzi, V.; Tocut, V.

2013-08-01

A Front-End (FE) design based on commercial operational amplifiers has been developed to read-out signals from a Multianode PhotoMultiplier Tube (MaPMT). The overall design has been optimised for single photo-electron signal from the Hamamatsu H8500. The signal is collected by a current sensitive preamplifier and then it is fed into both a ECL fast discriminator and a shaper for analog output readout in differential mode. The analog signal and the digital gates are then registered on VME ADC and TDC modules respectively. Performances in terms of linearity, gain and timing resolution will be discussed, presenting results obtained on a test bench with differentiated step voltage inputs and also with a prototype electronic board plugged into the H8500 PMT illuminated by a picosecond laser.

An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit.

PubMed

Tao Tang; Wang Ling Goh; Lei Yao; Jia Hao Cheong; Yuan Gao

2017-07-01

This paper describes an integrated multichannel neural recording analog front end (AFE) with a novel area-efficient driven right leg (DRL) circuit to improve the system common mode rejection ratio (CMRR). The proposed AFE consists of an AC-coupled low-noise programmable-gain amplifier, an area-efficient DRL block and a 10-bit SAR ADC. Compared to conventional DRL circuit, the proposed capacitor-less DRL design achieves 90% chip area reduction with enhanced CMRR performance, making it ideal for multichannel biomedical recording applications. The AFE circuit has been designed in a standard 0.18-μm CMOS process. Post-layout simulation results show that the AFE provides two gain settings of 54dB/60dB while consuming 1 μA per channel under a supply voltage of 1 V. The input-referred noise of the AFE integrated from 1 Hz to 10k Hz is only 4 μVrms and the CMRR is 110 dB.

A low power wearable transceiver for human body communication.

PubMed

Huang, Jin; Chen, Lian-Kang; Zhang, Yuan-Ting

2009-01-01

This paper reports a low power transceiver designed for wearable medical healthcare system. Based on a novel energy-efficient wideband wireless communication scheme that uses human body as a transmission medium, the transceiver can achieve a maximum 15 Mbps data rate with total receiver sensitivity of -30 dBm. The chip measures only 0.56 mm(2) and was fabricated in the SMIC 0.18um 1P6M RF CMOS process. The RX consumes 5mW and TX dissipates 1mW with delivering power up to 10uW, which is suitable for the body area network short range application. Real-time medical information collecting through the human body is fully simulated. Architecture of the chip together with the detail characterizes from its wireless analog front-end are presented.

Design and analysis of high gain and low noise figure CMOS low noise amplifier for Q-band nano-sensor application

NASA Astrophysics Data System (ADS)

Suganthi, K.; Malarvizhi, S.

2018-03-01

A high gain, low power, low Noise figure (NF) and wide band of milli-meter Wave (mmW) circuits design at 50 GHz are used for Radio Frequency (RF) front end. The fundamental necessity of a receiver front-end includes perfect output and input impedance matching and port-to-port isolation with high gain and low noise over the entire band of interest. In this paper, a design of Cascade-Cascode CMOS LNA circuit at 50 GHz for Q-band application is proposed. The design of Low noise amplifier at 50 GHz using Agilent ADS tool with microstrip lines which provides simplicity in fabrication and less chip area. The low off-leakage current Ioff can be maintained with high K-dielectrics CMOS structure. Nano-scale electronics can be achieved with increased robustness. The design has overall gain of 11.091 dB and noise figure of 2.673 dB for the Q-band of 48.3 GHz to 51.3 GHz. Impedance matching is done by T matching network and the obtained input and output reflection coefficients are S11 = <-10 dB and S22 = <-10 dB. Compared to Silicon (Si) material, Wide Band Gap semiconductor materials used attains higher junction temperatures which is well matched to ceramics used in packaging technology, the protection and reliability also can be achieved with the electronic packaging. The reverse transmission coefficient S21 is less than -21 dB has shown that LNA has better isolation between input and output, Stability factor greater than 1 and Power is also optimized in this design. Layout is designed, power gain of 4.6 dB is achieved and area is optimized which is nearly equal to 502 740 μm2. The observed results show that the proposed Cascade-Cascode LNA design can find its suitability in future milli-meter Wave Radar application.

The Panda Strip Asic: Pasta

NASA Astrophysics Data System (ADS)

Lai, A.

2018-01-01

PASTA is the 64 channel front-end chip, designed in a 110 nm CMOS technology to read out the strip sensors of the Micro Vertex Detector (MVD) of the PANDA experiment. This chip provides high resolution timestamp and deposited charge information by means of the time-over-threshold technique. Its working principle is based on a predecessor, the TOFPET ASIC, that was designed for medical applications. A general restructuring of the architecture was needed, in order to meet the specific requirements imposed by the physics programme of PANDA, especially in terms of radiation tolerance, spatial constraints, and readout in absence of a first level hardware trigger. The first revision of PASTA is currently under evaluation at the Forschungszentrum Jülich, where a data acquisition system dedicated to the MVD prototypes has been developed. This paper describes the main aspect of the chip design, gives an overview of the data acquisition system used for the verification, and shows the first results regarding the performance of PASTA.

An Inductively-Powered Wireless Neural Recording System with a Charge Sampling Analog Front-End

PubMed Central

Lee, Seung Bae; Lee, Byunghun; Kiani, Mehdi; Mahmoudi, Babak; Gross, Robert; Ghovanloo, Maysam

2015-01-01

An inductively-powered wireless integrated neural recording system (WINeR-7) is presented for wireless and battery less neural recording from freely-behaving animal subjects inside a wirelessly-powered standard homecage. The WINeR-7 system employs a novel wide-swing dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which performs amplification, filtering, sampling, and analog-to-time conversion (ATC) with minimal interference and small amount of power. The output of the DSCS-AFE produces a pseudo-digital pulse width modulated (PWM) signal. A circular shift register (CSR) time division multiplexes (TDM) the PWM pulses to create a TDM-PWM signal, which is fed into an on-chip 915 MHz transmitter (Tx). The AFE and Tx are supplied at 1.8 V and 4.2 V, respectively, by a power management block, which includes a high efficiency active rectifier and automatic resonance tuning (ART), operating at 13.56 MHz. The 8-ch system-on-a-chip (SoC) was fabricated in a 0.35-μm CMOS process, occupying 5.0 × 2.5 mm2 and consumed 51.4 mW. For each channel, the sampling rate is 21.48 kHz and the power consumption is 19.3 μW. In vivo experiments were conducted on freely behaving rats in an energized homecage by continuously delivering 51.4 mW to the WINeR-7 system in a closed-loop fashion and recording local field potentials (LFP). PMID:27069422

An Inductively-Powered Wireless Neural Recording System with a Charge Sampling Analog Front-End.

PubMed

Lee, Seung Bae; Lee, Byunghun; Kiani, Mehdi; Mahmoudi, Babak; Gross, Robert; Ghovanloo, Maysam

2016-01-15

An inductively-powered wireless integrated neural recording system (WINeR-7) is presented for wireless and battery less neural recording from freely-behaving animal subjects inside a wirelessly-powered standard homecage. The WINeR-7 system employs a novel wide-swing dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which performs amplification, filtering, sampling, and analog-to-time conversion (ATC) with minimal interference and small amount of power. The output of the DSCS-AFE produces a pseudo-digital pulse width modulated (PWM) signal. A circular shift register (CSR) time division multiplexes (TDM) the PWM pulses to create a TDM-PWM signal, which is fed into an on-chip 915 MHz transmitter (Tx). The AFE and Tx are supplied at 1.8 V and 4.2 V, respectively, by a power management block, which includes a high efficiency active rectifier and automatic resonance tuning (ART), operating at 13.56 MHz. The 8-ch system-on-a-chip (SoC) was fabricated in a 0.35-μm CMOS process, occupying 5.0 × 2.5 mm 2 and consumed 51.4 mW. For each channel, the sampling rate is 21.48 kHz and the power consumption is 19.3 μW. In vivo experiments were conducted on freely behaving rats in an energized homecage by continuously delivering 51.4 mW to the WINeR-7 system in a closed-loop fashion and recording local field potentials (LFP).

Radiation testing campaign results for understanding the suitability of FPGAs in detector electronics

DOE PAGES

Citterio, M.; Camplani, A.; Cannon, M.; ...

2015-11-19

SRAM based Field Programmable Gate Arrays (FPGAs) have been rarely used in High Energy Physics (HEP) due to their sensitivity to radiation. The last generation of commercial FPGAs based on 28 nm feature size and on Silicon On Insulator (SOI) technologies are more tolerant to radiation to the level that their use in front-end electronics is now feasible. FPGAs provide re-programmability, high-speed computation and fast data transmission through the embedded serial transceivers. They could replace custom application specific integrated circuits in front end electronics in locations with moderate radiation field. Finally, the use of a FPGA in HEP experiments ismore » only limited by our ability to mitigate single event effects induced by the high energy hadrons present in the radiation field.« less

Design and Measurement of a Low-Noise 64-Channels Front-End Readout ASIC for CdZnTe Detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gan, Bo; Wei, Tingcun; Gao, Wu

Cadmium zinc telluride (CdZnTe) detectors, as one of the principal detectors for the next-generation X-ray and γ-ray imagers, have high energy resolution and supporting electrode patterning in the radiation environment at room-temperature. In the present, a number of internationally renowned research institutions and universities are actively using these detector systems to carry out researches of energy spectrum analysis, medical imaging, materials characterization, high-energy physics, nuclear plant monitoring, and astrophysics. As the most important part of the readout system for the CdZnTe detector, the front-end readout application specific integrated circuit (ASIC) would have an important impact on the performances of themore » whole detector system. In order to ensure the small signal to noise ratio (SNR) and sufficient range of the output signal, it is necessary to design a front-end readout ASIC with very low noise and very high dynamic range. In addition, radiation hardness should be considered when the detectors are utilized in the space applications and high energy physics experiments. In this paper, we present measurements and performances of a novel multi-channel radiation-hardness low-noise front-end readout ASIC for CdZnTe detectors. The readout circuits in each channel consist of charge sensitive amplifier, leakage current compensation circuit (LCC), CR-RC shaper, S-K filter, inverse proportional amplifier, peak detect and hold circuit (PDH), discriminator and trigger logic, time sequence control circuit and driving buffer. All of 64 readout channels' outputs enter corresponding inputs of a 64 channel multiplexer. The output of the mux goes directly out of the chip via the output buffer. The 64-channel readout ASIC is implemented using the TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 2.7 mm x 8 mm. At room temperature, the equivalent noise level of a typical channel reaches 66 e{sup -} (rms) at zero farad for a power consumption of 8 mW per channel. The linearity error is lower than 1% and the overall gain of the readout channel is 165 V/pC. The crosstalk between the channels is less than 3%. By connecting the readout ASIC to a CdZnTe detector, we obtained a γ-ray spectrum, the energy resolution is 5.1% at the 59.5-keV line of {sup 241}Am source. (authors)« less

Ultrasound phase rotation beamforming on multi-core DSP.

PubMed

Ma, Jieming; Karadayi, Kerem; Ali, Murtaza; Kim, Yongmin

2014-01-01

Phase rotation beamforming (PRBF) is a commonly-used digital receive beamforming technique. However, due to its high computational requirement, it has traditionally been supported by hardwired architectures, e.g., application-specific integrated circuits (ASICs) or more recently field-programmable gate arrays (FPGAs). In this study, we investigated the feasibility of supporting software-based PRBF on a multi-core DSP. To alleviate the high computing requirement, the analog front-end (AFE) chips integrating quadrature demodulation in addition to analog-to-digital conversion were defined and used. With these new AFE chips, only delay alignment and phase rotation need to be performed by DSP, substantially reducing the computational load. We implemented the delay alignment and phase rotation modules on a Texas Instruments C6678 DSP with 8 cores. We found it takes 200 μs to beamform 2048 samples from 64 channels using 2 cores. With 4 cores, 20 million samples can be beamformed in one second. Therefore, ADC frequencies up to 40 MHz with 2:1 decimation in AFE chips or up to 20 MHz with no decimation can be supported as long as the ADC-to-DSP I/O requirement can be met. The remaining 4 cores can work on back-end processing tasks and applications, e.g., color Doppler or ultrasound elastography. One DSP being able to handle both beamforming and back-end processing could lead to low-power and low-cost ultrasound machines, benefiting ultrasound imaging in general, particularly portable ultrasound machines. Copyright © 2013 Elsevier B.V. All rights reserved.

Performance of the Fully Digital FPGA-Based Front-End Electronics for the GALILEO Array

NASA Astrophysics Data System (ADS)

Barrientos, D.; Bellato, M.; Bazzacco, D.; Bortolato, D.; Cocconi, P.; Gadea, A.; González, V.; Gulmini, M.; Isocrate, R.; Mengoni, D.; Pullia, A.; Recchia, F.; Rosso, D.; Sanchis, E.; Toniolo, N.; Ur, C. A.; Valiente-Dobón, J. J.

2015-12-01

In this work we present the architecture and results of a fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The FEE system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. This work presents the first results of the digital FEE system coupled with a GALILEO germanium detector, which has demonstrated the capability to achieve an energy resolution of 1.530/00 at an energy of 1.33 MeV, similar to the one obtained with a conventional analog system. While keeping a good performance in terms of energy resolution, digital electronics will allow to instrument the full GALILEO array with a versatile system with high integration and low power consumption and costs.

Gravitational Reference Sensor Front-End Electronics Simulator for LISA

NASA Astrophysics Data System (ADS)

Meshksar, Neda; Ferraioli, Luigi; Mance, Davor; ten Pierick, Jan; Zweifel, Peter; Giardini, Domenico; ">LISA Pathfinder colaboration, Analysis and Quantification of Coupling Mechanisms of External Signal Perturbations on Silicon Detectors for Particle Physics Experiments

NASA Astrophysics Data System (ADS)

Arteche, F.; Rivetta, C.; Iglesias, M.; Echeverria, I.

2016-05-01

Silicon detectors have been used in astrophysics satellites and particle detectors for high energy physics (HEP) experiments. For HEP applications, EMC studies have been conducted in silicon detectors to characterize the impact of external noise on the system. They have shown that problems associated with the new generation of silicon detectors are related with interferences generated by the power supplies and auxiliary equipment connected to the device. Characterization of these interferences along with the coupling and their propagation into the susceptible front-end circuits is required for a successful integration of these systems. This paper presents the analysis of the sensitivity curves and coupling mechanisms between the noise and the front-end electronics that have been observed during the characterization of two silicon detector prototypes: the CMS-Silicon tracker detector (CMS-ST) and Silicon Vertex Detector (Belle II-SVD). As a result of these studies, it is possible to identify critical elements in prototypes to take corrective actions in the design and improve the front-end electronics performance.

Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

NASA Astrophysics Data System (ADS)

Rivetti, Angelo

2014-11-01

In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8-10 bit resolution, 50-100 MHz conversion frequency and less than 1 mW power consumption are the today's standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130 nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC's and TDC's developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.

Characterization of the Photon Counting CHASE Jr., Chip Built in a 40-nm CMOS Process With a Charge Sharing Correction Algorithm Using a Collimated X-Ray Beam

DOE Office of Scientific and Technical Information (OSTI.GOV)

Krzyżanowska, A.; Deptuch, G. W.; Maj, P.

This paper presents the detailed characterization of a single photon counting chip, named CHASE Jr., built in a CMOS 40-nm process, operating with synchrotron radiation. The chip utilizes an on-chip implementation of the C8P1 algorithm. The algorithm eliminates the charge sharing related uncertainties, namely, the dependence of the number of registered photons on the discriminator’s threshold, set for monochromatic irradiation, and errors in the assignment of an event to a certain pixel. The article presents a short description of the algorithm as well as the architecture of the CHASE Jr., chip. The analog and digital functionalities, allowing for proper operationmore » of the C8P1 algorithm are described, namely, an offset correction for two discriminators independently, two-stage gain correction, and different operation modes of the digital blocks. The results of tests of the C8P1 operation are presented for the chip bump bonded to a silicon sensor and exposed to the 3.5- μm -wide pencil beam of 8-keV photons of synchrotron radiation. It was studied how sensitive the algorithm performance is to the chip settings, as well as the uniformity of parameters of the analog front-end blocks. Presented results prove that the C8P1 algorithm enables counting all photons hitting the detector in between readout channels and retrieving the actual photon energy.« less

Status of the design of the ITER ECE diagnostic

DOE PAGES

Taylor, G.; Austin, M. E.; Beno, J. H.; ...

2015-03-12

In this study, the baseline design for the ITER electron cyclotron emission (ECE) diagnostic has entered the detailed preliminary design phase. Two plasma views are planned, a radial view and an oblique view that is sensitive to distortions in the electron momentum distribution near the average thermal momentum. Both views provide high spatial resolution electron temperature profiles when the momentum distribution remains Maxwellian. The ECE diagnostic system consists of the front-end optics, including two 1000 K calibration sources, in equatorial port plug EP9, the 70-1000 GHz transmission system from the front-end to the diagnostics hall, and the ECE instrumentation inmore » the diagnostics hall. The baseline ECE instrumentation will include two Michelson interferometers that can simultaneously measure ordinary and extraordinary mode ECE from 70 to 1000 GHz, and two heterodyne radiometer systems, covering 122-230 GHz and 244-355 GHz. Significant design challenges include 1) developing highly-reliable 1000 K calibration sources and the associated shutters/mirrors, 2) providing compliant couplings between the front-end optics and the polarization splitter box that accommodate displacements of the vacuum vessel during plasma operations and bake out, 3) protecting components from damage due to stray ECH radiation and other intense millimeter wave emission and 4) providing the low-loss broadband transmission system.« less

Radiation hard programmable delay line for LHCb calorimeter upgrade

NASA Astrophysics Data System (ADS)

Mauricio, J.; Gascón, D.; Vilasís, X.; Picatoste, E.; Machefert, F.; Lefrancois, J.; Duarte, O.; Beigbeder, C.

2014-01-01

This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with less than 5 ps jitter and 23 ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end analog signal processing ASIC in the near future. The stringent noise requirements on the ASIC imply minimizing the noise contribution of digital components. This is accomplished by implementing the DLL in differential mode. To achieve the required radiation tolerance several techniques are applied: double guard rings between PMOS and NMOS transistors as well as glitch suppressors and TMR Registers. This 5.7 mm2 chip has been implemented in CMOS 0.35 μm technology.

Study of run time errors of the ATLAS pixel detector in the 2012 data taking period

NASA Astrophysics Data System (ADS)

Gandrajula, Reddy Pratap

The high resolution silicon Pixel detector is critical in event vertex reconstruction and in particle track reconstruction in the ATLAS detector. During the pixel data taking operation, some modules (Silicon Pixel sensor +Front End Chip+ Module Control Chip (MCC)) go to an auto-disable state, where the Modules don't send the data for storage. Modules become operational again after reconfiguration. The source of the problem is not fully understood. One possible source of the problem is traced to the occurrence of single event upset (SEU) in the MCC. Such a module goes to either a Timeout or Busy state. This report is the study of different types and rates of errors occurring in the Pixel data taking operation. Also, the study includes the error rate dependency on Pixel detector geometry.

A Fully Implantable, NFC Enabled, Continuous Interstitial Glucose Monitor

PubMed Central

Anabtawi, Nijad; Freeman, Sabrina; Ferzli, Rony

2017-01-01

This work presents an integrated system-on-chip (SoC) that forms the core of a long-term, fully implantable, battery assisted, passive continuous glucose monitor. It integrates an amperometric glucose sensor interface, a near field communication (NFC) wireless front-end and a fully digital switched mode power management unit for supply regulation and on board battery charging. It uses 13.56 MHz (ISM) band to harvest energy and backscatter data to an NFC reader. System was implemented in 14nm CMOS technology and validated with post layout simulations. PMID:28702512

A Fully Implantable, NFC Enabled, Continuous Interstitial Glucose Monitor.

PubMed

Anabtawi, Nijad; Freeman, Sabrina; Ferzli, Rony

2016-02-01

This work presents an integrated system-on-chip (SoC) that forms the core of a long-term, fully implantable, battery assisted, passive continuous glucose monitor. It integrates an amperometric glucose sensor interface, a near field communication (NFC) wireless front-end and a fully digital switched mode power management unit for supply regulation and on board battery charging. It uses 13.56 MHz (ISM) band to harvest energy and backscatter data to an NFC reader. System was implemented in 14nm CMOS technology and validated with post layout simulations.

Programmable architecture for pixel level processing tasks in lightweight strapdown IR seekers

NASA Astrophysics Data System (ADS)

Coates, James L.

1993-06-01

Typical processing tasks associated with missile IR seeker applications are described, and a straw man suite of algorithms is presented. A fully programmable multiprocessor architecture is realized on a multimedia video processor (MVP) developed by Texas Instruments. The MVP combines the elements of RISC, floating point, advanced DSPs, graphics processors, display and acquisition control, RAM, and external memory. Front end pixel level tasks typical of missile interceptor applications, operating on 256 x 256 sensor imagery, can be processed at frame rates exceeding 100 Hz in a single MVP chip.

Continuous-time ΣΔ ADC with implicit variable gain amplifier for CMOS image sensor.

PubMed

Tang, Fang; Bermak, Amine; Abbes, Amira; Benammar, Mohieddine Amor

2014-01-01

This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

The electronics and data acquisition system for the DarkSide-50 veto detectors

NASA Astrophysics Data System (ADS)

Agnes, P.; Agostino, L.; Albuquerque, I. F. M.; Alexander, T.; Alton, A. K.; Arisaka, K.; Back, H. O.; Baldin, B.; Biery, K.; Bonfini, G.; Bossa, M.; Bottino, B.; Brigatti, A.; Brodsky, J.; Budano, F.; Bussino, S.; Cadeddu, M.; Cadoni, M.; Calaprice, F.; Canci, N.; Candela, A.; Cao, H.; Cariello, M.; Carlini, M.; Catalanotti, S.; Cavalcante, P.; Chepurnov, A.; Cocco, A. G.; Covone, G.; Crippa, L.; D'Angelo, D.; D'Incecco, M.; Davini, S.; De Cecco, S.; De Deo, M.; De Vincenzi, M.; Derbin, A.; Devoto, A.; Di Eusanio, F.; Di Pietro, G.; Edkins, E.; Empl, A.; Fan, A.; Fiorillo, G.; Fomenko, K.; Foster, G.; Franco, D.; Gabriele, F.; Galbiati, C.; Giganti, C.; Goretti, A. M.; Granato, F.; Grandi, L.; Gromov, M.; Guan, M.; Guardincerri, Y.; Hackett, B. R.; Herner, K. R.; Hungerford, E. V.; Ianni, Aldo; Ianni, Andrea; James, I.; Jollet, C.; Keeter, K.; Kendziora, C. L.; Kobychev, V.; Koh, G.; Korablev, D.; Korga, G.; Kubankin, A.; Li, X.; Lissia, M.; Lombardi, P.; Luitz, S.; Ma, Y.; Machulin, I. N.; Mandarano, A.; Mari, S. M.; Maricic, J.; Marini, L.; Martoff, C. J.; Meregaglia, A.; Meyers, P. D.; Miletic, T.; Milincic, R.; Montanari, D.; Monte, A.; Montuschi, M.; Monzani, M. E.; Mosteiro, P.; Mount, B. J.; Muratova, V. N.; Musico, P.; Napolitano, J.; Nelson, A.; Odrowski, S.; Orsini, M.; Ortica, F.; Pagani, L.; Pallavicini, M.; Pantic, E.; Parmeggiano, S.; Pelczar, K.; Pelliccia, N.; Pocar, A.; Pordes, S.; Pugachev, D. A.; Qian, H.; Randle, K.; Ranucci, G.; Razeto, A.; Reinhold, B.; Renshaw, A. L.; Riffard, Q.; Romani, A.; Rossi, B.; Rossi, N.; Rountree, S. D.; Sablone, D.; Saggese, P.; Saldanha, R.; Sands, W.; Sangiorgio, S.; Savarese, C.; Segreto, E.; Semenov, D. A.; Shields, E.; Singh, P. N.; Skorokhvatov, M. D.; Smirnov, O.; Sotnikov, A.; Stanford, C.; Suvorov, Y.; Tartaglia, R.; Tatarowicz, J.; Testera, G.; Tonazzo, A.; Trinchese, P.; Unzhakov, E. V.; Vishneva, A.; Vogelaar, R. B.; Wada, M.; Walker, S.; Wang, H.; Wang, Y.; Watson, A. W.; Westerdale, S.; Wilhelmi, J.; Wojcik, M. M.; Xiang, X.; Xu, J.; Yang, C.; Yoo, J.; Zavatarelli, S.; Zec, A.; Zhong, W.; Zhu, C.; Zuzel, G.

2016-12-01

DarkSide-50 is a detector for dark matter candidates in the form of weakly interacting massive particles. It utilizes a liquid argon time projection chamber for the inner main detector, surrounded by a liquid scintillator veto (LSV) and a water Cherenkov veto detector (WCV). The LSV and WCV act as the neutron and cosmogenic muon veto detectors for DarkSide-50. This paper describes the electronics and data acquisition system used for these two detectors. The system is made of a custom built front end electronics and commercial National Instruments high speed digitizers. The front end electronics, the DAQ, and the trigger system have been used to acquire data in the form of zero-suppressed waveform samples from the 110 PMTs of the LSV and the 80 PMTs of the WCV. The veto DAQ system has proven its performance and reliability. This electronics and DAQ system can be scaled and used as it is for the veto of the next generation DarkSide-20k detector.

Reviewed approach to defining the Active Interlock Envelope for Front End ray tracing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Seletskiy, S.; Shaftan, T.

To protect the NSLS-II Storage Ring (SR) components from damage from synchrotron radiation produced by insertion devices (IDs) the Active Interlock (AI) keeps electron beam within some safe envelope (a.k.a Active Interlock Envelope or AIE) in the transverse phase space. The beamline Front Ends (FEs) are designed under assumption that above certain beam current (typically 2 mA) the ID synchrotron radiation (IDSR) fan is produced by the interlocked e-beam. These assumptions also define how the ray tracing for FE is done. To simplify the FE ray tracing for typical uncanted ID it was decided to provide the Mechanical Engineering groupmore » with a single set of numbers (x,x’,y,y’) for the AIE at the center of the long (or short) ID straight section. Such unified approach to the design of the beamline Front Ends will accelerate the design process and save valuable human resources. In this paper we describe our new approach to defining the AI envelope and provide the resulting numbers required for design of the typical Front End.« less

Design of fast signal processing readout front-end electronics implemented in CMOS 40 nm technology

NASA Astrophysics Data System (ADS)

Kleczek, Rafal

2016-12-01

The author presents considerations on the design of fast readout front-end electronics implemented in a CMOS 40 nm technology with an emphasis on the system dead time, noise performance and power dissipation. The designed processing channel consists of a charge sensitive amplifier with different feedback types (Krummenacher, resistive and constant current blocks), a threshold setting block, a discriminator and a counter with logic circuitry. The results of schematic and post-layout simulations with randomly generated input pulses in a time domain according to the Poisson distribution are presented and analyzed. Dead time below 20 ns is possible while keeping noise ENC ≈ 90 e- for a detector capacitance CDET = 160 fF.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Citterio, M.; Camplani, A.; Cannon, M.

SRAM based Field Programmable Gate Arrays (FPGAs) have been rarely used in High Energy Physics (HEP) due to their sensitivity to radiation. The last generation of commercial FPGAs based on 28 nm feature size and on Silicon On Insulator (SOI) technologies are more tolerant to radiation to the level that their use in front-end electronics is now feasible. FPGAs provide re-programmability, high-speed computation and fast data transmission through the embedded serial transceivers. They could replace custom application specific integrated circuits in front end electronics in locations with moderate radiation field. Finally, the use of a FPGA in HEP experiments ismore » only limited by our ability to mitigate single event effects induced by the high energy hadrons present in the radiation field.« less

The upgrade of the CMS hadron calorimeter with silicon photomultipliers

DOE PAGES

Strobbe, N.

2017-01-26

The upgrade of the hadron calorimeter of the CMS experiment at the CERN Large Hadron Collider is currently underway. The endcap sections will be upgraded in the winter of 2016–2017 and the barrel sections during the second LHC long shutdown in 2019. The existing photosensors will be replaced with about 16 000 new silicon photomultipliers (SiPMs), resulting in the first large installation of SiPMs in a radiation environment. All associated front-end electronics will also be upgraded. Here, this paper discusses the motivation for the upgrade and provides a description 17 of the new system, including the SiPMs with associated controlmore » electronics and the front-end readout cards.« less

A multi-year survey of stem-end chip defect in chipping potatoes (Solanum tuberosum L.)

USDA-ARS?s Scientific Manuscript database

One of the most serious tuber quality concerns of US chip potato growers is stem-end chip defect, which is defined as a localized post-fry discoloration in and adjacent to the vasculature on the stem end portion of potato chips. The incidence and severity of stem-end chip defect vary with growing lo...

Optimizing read-out of the NECTAr front-end electronics

NASA Astrophysics Data System (ADS)

Vorobiov, S.; Feinstein, F.; Bolmont, J.; Corona, P.; Delagnes, E.; Falvard, A.; Gascón, D.; Glicenstein, J.-F.; Naumann, C. L.; Nayman, P.; Ribo, M.; Sanuy, A.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.

2012-12-01

We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

JFET front-end circuits integrated in a detector-grade silicon substrate

NASA Astrophysics Data System (ADS)

Manghisoni, M.; Ratti, L.; Re, V.; Speziali, V.; Traversi, G.; Dalla Betta, G. F.; Boscardin, M.; Batignani, G.; Giorgi, M.; Bosisio, L.

2003-08-01

This paper presents the design and experimental results relevant to front-end circuits integrated on detector-grade high resistivity silicon. The fabrication technology is made available by the Istituto per la Ricerca Scientifica e Tecnologica (ITC-IRST), Trento, Italy and allows using a common substrate for different kinds of active devices, such as N-channel JFETs and MOSFETs, and for pixel, microstrip, and PIN detectors. This research activity is being carried out in the framework of a project aiming at the fabrication of a multichannel mixed analog-digital chip for the readout of solid-state detectors integrated in the same substrate. Possible applications are in the field of medical and industrial imaging and space and high energy physics experiments. An all-JFET charge sensitive amplifier, which can use either a resistive or a nonresistive feedback network, has been characterized. The two configurations have been compared to each other, paying particular attention to noise performances, in view of the design of the complete readout channel. Operation capability in harsh radiation environment has been evaluated through exposure to /spl gamma/-rays from a /sup 60/Co source.

The design of CMOS general-purpose analog front-end circuit with tunable gain and bandwidth for biopotential signal recording systems.

PubMed

Chen, Wei-Ming; Yang, Wen-Chia; Tsai, Tzung-Yun; Chiueh, Herming; Wu, Chung-Yu

2011-01-01

In this paper an 8-channel CMOS general-purpose analog front-end (AFE) circuit with tunable gain and bandwidth for biopotential signal recording systems is presented. The proposed AFE consists of eight chopper stabilized pre-amplifiers, an 8-to-1 analog multiplexer, and a programmable gain amplifier. It can be used to sense and amplify different kinds of biopotential signals, such as electrocorticogram (ECoG), electrocardiogram (ECG) and electromyogram (EMG). The AFE chip is designed and fabricated in 0.18-μm CMOS technology. The measured maximum gain of AFE is 60.8 dB. The low cutoff frequency can achieve as low as 0.8 Hz and high cutoff frequency can be adjusted from 200 Hz to 10 kHz to suit for different kinds of biopotential signals. The measured input-referred noise is 0.9 μV(rms), with the power consumption of 18μW per channel at 1.8-V power supply. And the noise efficiency factor (NEF) is only 1.3 for pre-amplifier.

7 CFR 1717.852 - Financing purposes.

Code of Federal Regulations, 2014 CFR

2014-01-01

... the borrower: water and waste disposal systems, solid waste disposal systems, telecommunication and other electronic communications systems, and natural gas distribution systems; (4) Front-end costs, when...

The Front-End System For MARE In Milano

NASA Astrophysics Data System (ADS)

Arnaboldi, Claudio; Pessina, Gianluigi

2009-12-01

The first phase of MARE consists of 72 μ-bolometers composed each of a crystal of AgReO4 readout by Si thermistors. The spread in the thermistor characteristics and bolometer thermal coupling leads to different energy conversion gains and optimum operating points of the detectors. Detector biasing levels and voltage gains are completely remote-adjustable by the front end system developed, the subject of this paper, achieving the same signal range at the input of the DAQ system. The front end consists of a cold buffer stage, a second pseudo differential stage followed by a gain stage, an antialiasing filter, and a battery powered detector biasing set up. The DAQ system can be used to set all necessary parameters of the electronics remotely, by writing to a μ-controller located on each board. Fiber optics are used for the serial communication between the DAQ and the front end. To suppress interference noise during normal operation, the clocked devices of the front end are maintained in sleep-mode, except during the set-up phase of the experiment. An automatic DC detector characterization procedure is used to establish the optimum operating point of every detector of the array. A very low noise level has been achieved: about 3nV/□Hz at 1 Hz and 1 nV/□Hz for the white component, high frequencies.

An Implantable RFID Sensor Tag toward Continuous Glucose Monitoring.

PubMed

Xiao, Zhibin; Tan, Xi; Chen, Xianliang; Chen, Sizheng; Zhang, Zijian; Zhang, Hualei; Wang, Junyu; Huang, Yue; Zhang, Peng; Zheng, Lirong; Min, Hao

2015-05-01

This paper presents a wirelessly powered implantable electrochemical sensor tag for continuous blood glucose monitoring. The system is remotely powered by a 13.56-MHz inductive link and utilizes an ISO 15693 radio frequency identification (RFID) standard for communication. This paper provides reliable and accurate measurement for changing glucose level. The sensor tag employs a long-term glucose sensor, a winding ferrite antenna, an RFID front-end, a potentiostat, a 10-bit sigma-delta analog to digital converter, an on-chip temperature sensor, and a digital baseband for protocol processing and control. A high-frequency external reader is used to power, command, and configure the sensor tag. The only off-chip support circuitry required is a tuned antenna and a glucose microsensor. The integrated chip fabricated in SMIC 0.13-μm CMOS process occupies an area of 1.2 mm ×2 mm and consumes 50 μW. The power sensitivity of the whole system is -4 dBm. The sensor tag achieves a measured glucose range of 0-30 mM with a sensitivity of 0.75 nA/mM.

Planar MEMS bio-chip for recording ion-channel currents in biological cells

NASA Astrophysics Data System (ADS)

Pandey, Santosh; Ferdous, Zannatul; White, Marvin H.

2003-10-01

We describe a planar MEMS silicon structure to record ion-channel currents in biological cells. The conventional method of performing an electrophysiological experiment, 'patch-clamping,' employs a glass micropipette. Despite careful treatments of the micropipette tip, such as fire polishing and surface coating, the latter is a source of thermal noise because of its inherent, tapered, conical structure, which gives rise to a large pipette resistance. This pipette resistance, when coupled with the self-capacitance of the biological cell, limits the available bandwidth and processing of fast transient, ion channel current pulses. In this work, we reduce considerably the pipette resistance with a planar micropipette on a silicon chip to permit the resolution of sub-millisecond, ion-channel pulses. We discuss the design topology of the device, describe the fabrication sequence, and highlight important critical issues. The design of an integrated on-chip CMOS instrumentation amplifier is described, which has a low-noise front-end, input-offset cancellation, correlated double sampling (CDS), and an ultra-high gain in the order of 1012V/A.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the first six months of this project were to begin laying the foundations for both the SiC front-end optical chip fabrication techniques for high pressure gas species sensing as well as the design, assembly, and test of a portable high pressure high temperature calibration test cell chamber for introducing gas species. This calibration cell will be used in the remaining months for proposed first stage high pressure high temperature gas species sensor experimentation and data processing. All these goals have been achieved and are described in detail in the report. Both design process and diagrams for themore » mechanical elements as well as the optical systems are provided. Photographs of the fabricated calibration test chamber cell, the optical sensor setup with the calibration cell, the SiC sample chip holder, and relevant signal processing mathematics are provided. Initial experimental data from both the optical sensor and fabricated test gas species SiC chips is provided. The design and experimentation results are summarized to give positive conclusions on the proposed novel high temperature high pressure gas species detection optical sensor technology.« less

FELIX: The new detector readout system for the ATLAS experiment

NASA Astrophysics Data System (ADS)

Ryu, Soo; ATLAS TDAQ Collaboration

2017-10-01

After the Phase-I upgrades (2019) of the ATLAS experiment, the Front-End Link eXchange (FELIX) system will be the interface between the data acquisition system and the detector front-end and trigger electronics. FELIX will function as a router between custom serial links and a commodity switch network using standard technologies (Ethernet or Infiniband) to communicate with commercial data collecting and processing components. The system architecture of FELIX will be described and the status of the firmware implementation and hardware development currently in progress will be presented.

Non-Electronic Radio Front-End (NERF)

DTIC Science & Technology

2007-04-01

electro - optic field sensor. The absence of metallic interconnects and the charge isolation provided by the optics removes the soft spots in a traditional receiver. In the proof-of concept experiment, detection of C band electromagnetic signals at 7.38 GHz with a sensitivity of 4.3x10 -3 V/m.Hz(exp 1/2) is demonstrated. The dielectric approach has an added benefit: it reduces physical size of the front end an important benefit in mobile applications. DIELECTRIC RESONATOR ANTENNA, PHOTONICALLY ISOLATED ANTENNA RECEIVER, ELECTRO - OPTIC DIELECTRIC ANTENNA,

Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

PubMed

Gurun, Gokce; Hasler, Paul; Degertekin, F

2011-08-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

The FE-I4 Pixel Readout Chip and the IBL Module

DOE Office of Scientific and Technical Information (OSTI.GOV)

Barbero, Marlon; Arutinov, David; Backhaus, Malte

2012-05-01

FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the 'Insertable B-Layer' project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on testmore » results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.« less

A fully integrated direct-conversion digital satellite tuner in 0.18 μm CMOS

NASA Astrophysics Data System (ADS)

Si, Chen; Zengwang, Yang; Mingliang, Gu

2011-04-01

A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented. A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end, while the synthesizer integrated the loop filter to reduce the solution cost and system debug time. Fabricated in 0.18 μm CMOS, the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector. The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1 °C integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Agnes, P.; Agostino, L.; Albuquerque, I. F. M.

DarkSide-50 is a detector for dark matter candidates in the form of weakly interacting massive particles. It utilizes a liquid argon time projection chamber for the inner main detector, surrounded by a liquid scintillator veto (LSV) and a water Cherenkov veto detector (WCV). The LSV and WCV act as the neutron and cosmogenic muon veto detectors for DarkSide-50. This paper describes the electronics and data acquisition system used for these two detectors. The system is made of a custom built front end electronics and commercial National Instruments high speed digitizers. The front end electronics, the DAQ, and the trigger systemmore » have been used to acquire data in the form of zero-suppressed waveform samples from the 110 PMTs of the LSV and the 80 PMTs of the WCV. The veto DAQ system has proven its performance and reliability. This electronics and DAQ system can be scaled and used as it is for the veto of the next generation DarkSide-20k detector. Abstract (arXiv)« less

Ergonomic risk factors of work processes in the semiconductor industry in Peninsular Malaysia.

PubMed

Chee, Heng-Leng; Rampal, Krishna Gopal; Chandrasakaran, Abherhame

2004-07-01

A cross-sectional survey of semiconductor factories was conducted to identify the ergonomic risk factors in the work processes, the prevalence of body pain among workers, and the relationship between body pain and work processes. A total of 906 women semiconductor workers took part in the study. In wafer preparation and polishing, a combination of lifting weights and prolonged standing might have led to high pain prevalences in the low back (35.0% wafer preparation, 41.7% wafer polishing) and lower limbs (90.0% wafer preparation, 66.7% wafer polishing). Semiconductor front of line workers, who mostly walked around to operate machines in clean rooms, had the lowest prevalences of body pain. Semiconductor assembly middle of line workers, especially the molding workers, who did frequent lifting, had high pain prevalences in the neck/shoulders (54.8%) and upper back (43.5 %). In the semiconductor assembly end of line work section, chip inspection workers who were exposed to prolonged sitting without back support had high prevalences of neck/shoulder (62.2%) and upper back pain (50.0%), while chip testing workers who had to climb steps to load units had a high prevalence of lower limb pain (68.0%). Workers in the assembly of electronic components, carrying out repetitive tasks with hands and fingers, and standing in awkward postures had high pain prevalences in the neck/shoulders (61.5%), arms (38.5%), and hands/wrists (30.8%).

The front-end data conversion and readout electronics for the CMS ECAL upgrade

NASA Astrophysics Data System (ADS)

Mazza, G.; Cometti, S.

2018-03-01

The High Luminosity LHC (HL-LHC) will require a significant upgrade of the readout electronics for the CMS Electromagnetic Calorimeter (ECAL). The Very Front-End (VFE) output signal will be sampled at 160 MS/s (i.e. four times the current sampling rate) with a 13 bits resolution. Therefore, a high-speed, high-resolution ADC is required. Moreover, each readout channel will produce 2.08 Gb/s, thus requiring a fast data transmission circuitry. A new readout architecture, based on two 12 bit, 160 MS/s ADCs, lossless data compression algorithms and fast serial links have been developed for the ECAL upgrade. These functions will be integrated in a single ASIC which is currently under design in a commercial CMOS 65 nm technology using radiation damage mitigation techniques.

A free-running, time-based readout method for particle detectors

NASA Astrophysics Data System (ADS)

Goerres, A.; Bugalho, R.; Di Francesco, A.; Gastón, C.; Gonçalves, F.; Mazza, G.; Mignone, M.; Di Pietro, V.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; da Silva, J. C.; Silva, R.; Stockmanns, T.; Varela, J.; Veckalns, V.; Wheadon, R.

2014-03-01

For the EndoTOFPET-US experiment, the TOFPET ASIC has been developed as a front-end chip to read out data from silicon photomultipliers (SiPM) [1]. It introduces a time of flight information into the measurement of a PET scanner and hence reduces radiation exposure of the patient [2]. The chip is designed to work with a high event rate up to 100 kHz and a time resolution of 50 ps LSB. Using two threshold levels, it can measure the leading edge of the event pulse precisely while successfully suppressing dark counts from the SiPM. This also enables a time over threshold determination, leading to a charge measurement of the signal's pulse. The same, time-based concept is chosen for the PASTA chip used in the PANDA experiment. This high-energy particle detector contains sub-systems for specific measurement goals. The innermost of these is the Micro Vertex Detector, a silicon-based tracking system. The PASTA chip's approach is much like the TOFPET ASIC with some differences. The most significant ones are a changed amplifying part for different input signals as well as protection for radiation effects of the high-radiation environment. Apart from that, the simple and general concept combined with a small area and low power consumption support the choice for using this approach.

Molded underfill (MUF) encapsulation for flip-chip package: A numerical investigation

NASA Astrophysics Data System (ADS)

Azmi, M. A.; Abdullah, M. K.; Abdullah, M. Z.; Ariff, Z. M.; Saad, Abdullah Aziz; Hamid, M. F.; Ismail, M. A.

2017-07-01

This paper presents the numerical simulation of epoxy molding compound (EMC) filling in multi flip-chip packages during encapsulation process. The empty and a group flip chip packages were considered in the mold cavity in order to study the flow profile of the EMC. SOLIDWORKS software was used for three-dimensional modeling and it was incorporated into fluid analysis software namely as ANSYS FLUENT. The volume of fluid (VOF) technique was used for capturing the flow front profiles and Power Law model was applied for its rheology model. The numerical result are compared and discussed with previous experimental and it was shown a good conformity for model validation. The prediction of flow front was observed and analyzed at different filling time. The possibility and visual of void formation in the package is captured and the number of flip-chip is one factor that contributed to the void formation.

Design of a Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

NASA Astrophysics Data System (ADS)

Gao, W.; Liu, H.; Gan, B.; Wei, T.; Gao, D.; Hu, Y.

2014-10-01

In this paper, we present the design and preliminary results of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for a PET imaging system whose objective is to achieve the following performances: the spatial resolution of 1 mm3, the detection efficiency of 15% and the time resolution of 1 ns. A cascode amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuits is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. An eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm ×2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy level of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC. The tested result of ENC is 86.5 e- at zero farad plus 9.3 e- per picofarad. The nonlinearity is less than 3%. The crosstalk is less than 2%. The power dissipation is about 3 mW/channel.

Algorithm for fast event parameters estimation on GEM acquired data

NASA Astrophysics Data System (ADS)

Linczuk, Paweł; Krawczyk, Rafał D.; Poźniak, Krzysztof T.; Kasprowicz, Grzegorz; Wojeński, Andrzej; Chernyshova, Maryna; Czarski, Tomasz

2016-09-01

We present study of a software-hardware environment for developing fast computation with high throughput and low latency methods, which can be used as back-end in High Energy Physics (HEP) and other High Performance Computing (HPC) systems, based on high amount of input from electronic sensor based front-end. There is a parallelization possibilities discussion and testing on Intel HPC solutions with consideration of applications with Gas Electron Multiplier (GEM) measurement systems presented in this paper.

Electronic drive and acquisition system for mass spectrometry

NASA Technical Reports Server (NTRS)

Schaefer, Rembrandt Thomas (Inventor); Chutjian, Ara (Inventor); Tran, Tuan (Inventor); Madzunkov, Stojan M. (Inventor); Thomas, John L. (Inventor); Mojarradi, Mohammad (Inventor); MacAskill, John (Inventor); Blaes, Brent R. (Inventor); Darrach, Murray R. (Inventor); Burke, Gary R. (Inventor)

2010-01-01

The present invention discloses a mixed signal RF drive electronics board that offers small, low power, reliable, and customizable method for driving and generating mass spectra from a mass spectrometer, and for control of other functions such as electron ionizer, ion focusing, single-ion detection, multi-channel data accumulation and, if desired, front-end interfaces such as pumps, valves, heaters, and columns.

Effects of Verticillium dahliae infection on stem-end chip defect development in potatoes (Solanum tuberosum L.)

USDA-ARS?s Scientific Manuscript database

Potato chips are America's favorite snack food with annual retail sales of over $6 billion. Stem-end chip defect, which is characterized by discoloration of the vasculature and surrounding tissues at the tuber stem end portion of chips, is an important tuber quality concern for US chip production. T...

Electronics and triggering challenges for the CMS High Granularity Calorimeter

NASA Astrophysics Data System (ADS)

Lobanov, A.

2018-02-01

The High Granularity Calorimeter (HGCAL), presently being designed by the CMS collaboration to replace the CMS endcap calorimeters for the High Luminosity phase of LHC, will feature six million channels distributed over 52 longitudinal layers. The requirements for the front-end electronics are extremely challenging, including high dynamic range (0.2 fC-10 pC), low noise (~2000 e- to be able to calibrate on single minimum ionising particles throughout the detector lifetime) and low power consumption (~20 mW/channel), as well as the need to select and transmit trigger information with a high granularity. Exploiting the intrinsic precision-timing capabilities of silicon sensors also requires careful design of the front-end electronics as well as the whole system, particularly clock distribution. The harsh radiation environment and requirement to keep the whole detector as dense as possible will require novel solutions to the on-detector electronics layout. Processing the data from the HGCAL imposes equally large challenges on the off-detector electronics, both for the hardware and incorporated algorithms. We present an overview of the complete electronics architecture, as well as the performance of prototype components and algorithms.

Cryogenic bolometric systems

NASA Astrophysics Data System (ADS)

Kangas, Miikka Matias

The big bang, early galaxy formation, the interstellar medium, and high z galaxy cluster evolution are all science objectives that are studied in the far infrared (FIR). The cosmological parameters that describe the universe are encoded in anisotropies in the Cosmic Microwave Background (CMB), and can be extracted from precision subdegree angular resolution FIR maps. Cryogenic bolometers are well suited for these science objectives, and are evolving rapidly today. A cryogenic bolometric system is made up of a few building blocks, which can be modularized or integrated depending on the maturity of the scientific field they are used for. Integration of systems increases with the maturity of the technology. The basic building blocks are the bolometer, the cryogenics, the dewar, the optics, the filters, and electronics. The electronics can be further subdivided into room temperature back-end and cryogenic front-end electronics. The electronics are often partly integrated into the dewar. The dewar is part of the support structure, and only the subkelvin portion the dewar is referred to as cryogenics here. Each of these can be a sophisticated engineering feat on their own, and this dissertation revolves around the development of several of these elements. The microfabrication sequence for a free standing micromesh detector was developed. Polarization preserving photometer optics and filters were constructed and tested. A test dewar mechanical and optical structure was created to test single pixel photometers prior to mounting in the flight dewar. A modular flight dewar capable of holding an array of photometers and adaptable to a number of different cryogenics schemes and detector arrays was engineered and constructed. A zero gravity dilution refrigerator coil was constructed and tested. A corrugated platelet array concept was designed and tested. Metal mesh filter design and fabrication techniques were developed. Kevlar isolator structures were improved to work in subkelvin dewars, and detector modules that mounted the bolometer chips to the photometer tubes were created. These subsystems underwent testing to compare the predicted behavior and actual performance.

Actuation stability test of the LISA pathfinder inertial sensor front-end electronics

NASA Astrophysics Data System (ADS)

Mance, Davor; Gan, Li; Weber, Bill; Weber, Franz; Zweifel, Peter

In order to limit the residual stray forces on the inertial sensor test mass in LISA pathfinder, √ it is required that the fluctuation of the test mass actuation voltage is within 2ppm/ Hz. The actuation voltage stability test on the flight hardware of the inertial sensor front-end electronics (IS FEE) is presented in this paper. This test is completed during the inertial sensor integration at EADS Astrium Friedrichshafen, Germany. The standard measurement method using voltmeter is not sufficient for verification, since the instrument low frequency √ fluctuation is higher than the 2ppm/ Hz requirement. In this test, by using the differential measurement method and the lock-in amplifier, the actuation stability performance is verified and the quality of the IS FEE hardware is confirmed by the test results.

Development and evaluation of a comprehensive clinical decision support taxonomy: comparison of front-end tools in commercial and internally developed electronic health record systems

PubMed Central

Sittig, Dean F; Ash, Joan S; Feblowitz, Joshua; Meltzer, Seth; McMullen, Carmit; Guappone, Ken; Carpenter, Jim; Richardson, Joshua; Simonaitis, Linas; Evans, R Scott; Nichol, W Paul; Middleton, Blackford

2011-01-01

Background Clinical decision support (CDS) is a valuable tool for improving healthcare quality and lowering costs. However, there is no comprehensive taxonomy of types of CDS and there has been limited research on the availability of various CDS tools across current electronic health record (EHR) systems. Objective To develop and validate a taxonomy of front-end CDS tools and to assess support for these tools in major commercial and internally developed EHRs. Study design and methods We used a modified Delphi approach with a panel of 11 decision support experts to develop a taxonomy of 53 front-end CDS tools. Based on this taxonomy, a survey on CDS tools was sent to a purposive sample of commercial EHR vendors (n=9) and leading healthcare institutions with internally developed state-of-the-art EHRs (n=4). Results Responses were received from all healthcare institutions and 7 of 9 EHR vendors (response rate: 85%). All 53 types of CDS tools identified in the taxonomy were found in at least one surveyed EHR system, but only 8 functions were present in all EHRs. Medication dosing support and order facilitators were the most commonly available classes of decision support, while expert systems (eg, diagnostic decision support, ventilator management suggestions) were the least common. Conclusion We developed and validated a comprehensive taxonomy of front-end CDS tools. A subsequent survey of commercial EHR vendors and leading healthcare institutions revealed a small core set of common CDS tools, but identified significant variability in the remainder of clinical decision support content. PMID:21415065

MATLAB/Simulink Pulse-Echo Ultrasound System Simulator Based on Experimentally Validated Models.

PubMed

Kim, Taehoon; Shin, Sangmin; Lee, Hyongmin; Lee, Hyunsook; Kim, Heewon; Shin, Eunhee; Kim, Suhwan

2016-02-01

A flexible clinical ultrasound system must operate with different transducers, which have characteristic impulse responses and widely varying impedances. The impulse response determines the shape of the high-voltage pulse that is transmitted and the specifications of the front-end electronics that receive the echo; the impedance determines the specification of the matching network through which the transducer is connected. System-level optimization of these subsystems requires accurate modeling of pulse-echo (two-way) response, which in turn demands a unified simulation of the ultrasonics and electronics. In this paper, this is realized by combining MATLAB/Simulink models of the high-voltage transmitter, the transmission interface, the acoustic subsystem which includes wave propagation and reflection, the receiving interface, and the front-end receiver. To demonstrate the effectiveness of our simulator, the models are experimentally validated by comparing the simulation results with the measured data from a commercial ultrasound system. This simulator could be used to quickly provide system-level feedback for an optimized tuning of electronic design parameters.

The New APD Based Readout for the Crystal Barrel Calorimeter

NASA Astrophysics Data System (ADS)

Urban, M.; Honisch, Ch; Steinacher, M.; CBELSA/TAPS Collaboration

2015-02-01

The CBELSA/TAPS experiment at ELSA measures double polarization observables in meson photoproduction off protons and neutrons. To be able to measure purely neutral reactions off polarized neutrons with high efficiency, the main calorimeter has to be integrated into the first level trigger. This requires to exchange the existing PIN photo diode by a new avalanche photo diode (APD) readout. The newly developed readout electronics will provide an energy resolution compatible to the previous set-up and a fast trigger signal down to 10 MeV energy deposit per crystal. After the successful final tests with a 3x3 CsI crystal matrix in Bonn at ELSA and in Mainz at MAMI all front-end electronics were produced in fall 2013. Automated test routines for the front-end electronics were developed and the characterization measurements of all APDs were successfully accomplished in Bonn. The project is supported by the Deutsche Forschungsgemeinschaft (SFB/TR16) and Schweizerischer Nationalfonds.

NECTAR: New electronics for the Cherenkov Telescope Array

NASA Astrophysics Data System (ADS)

Naumann, Christopher Lindsay; Bolmont, J.; Corona, P.; Delagnes, E.; Dzahini, D.; Feinstein, F.; Gascon, D.; Glicenstein, J.-F.; Nayman, P.; Rarbi, F.; Ribo, M.; Sanuy, A.; Siero, X.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.; Vorobiov, S.

2012-12-01

The international CTA consortium is currently in the preparatory phase for the development of the next-generation Cherenkov Telescope Array (CTA [1]), based on the return of experience from the three major current-generation arrays H.E.S.S., MAGIC and VERITAS. To achieve an unprecedented sensitivity and energy range for TeV gamma rays, a new kind of flexible and powerful yet inexpensive front-end hardware will be required for the order of 105 channels of photodetectors in up to 100 telescopes. One possible solution is the NECTAr (New Electronics for the Cherenkov Telescope Array) system, based on the integration of as much as possible of the front-end electronics (amplifiers, fast analogue samplers, memory and ADCs) into a single ASIC for very fast readout performance and a significant reduction of the cost and the lower consumption per channel, while offering a high degree of flexibility both for the triggering and the readout of the telescope. The current status of its development is presented, along with newest results from measurements and simulation studies.

Developing Electronic Performance Support Systems for Professionals.

ERIC Educational Resources Information Center

Law, Michael P.; And Others

This paper discusses a variety of development strategies and issues involved in the development of electronic performance support systems (EPSS) for professionals. The topics of front-end analysis, development, and evaluation are explored in the context of a case study involving the development of an EPSS to support teachers in the use of…

AN INTERNET RACK MONITOR-CONTROLLER FOR APS LINAC RF ELECTRONICS UPGRADE

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ma, Hengjie; Smith, Terry; Nassiri, Alireza

To support the research and development in APS LINAC area, the existing LINAC rf control performance needs to be much improved, and thus an upgrade of the legacy LINAC rf electronics becomes necessary. The proposed upgrade plan centers on the concept of using a modern, network-attached, rackmount digital electronics platform –Internet Rack Monitor-Controller (or IRMC) to achieve the goal of modernizing the rf electronics at a lower cost. The system model of the envisioned IRMC is basically a 3-tier stack with a high-performance DSP in the mid-layer to perform the core tasks of real-time rf data processing and controls. Themore » Digital Front-End (DFE) attachment layer at bottom bridges the applicationspecific rf front-ends to the DSP. A network communication gateway, together with an embedded event receiver (EVR) in the top layer merges the Internet Rack MonitorController node into the networks of the accelerator controls infrastructure. Although the concept is very much in trend with today’s Internet-of-Things (IoT), this implementation has actually been used in the accelerators for over two decades.« less

The Phase-2 electronics upgrade of the ATLAS liquid argon calorimeter system

NASA Astrophysics Data System (ADS)

Vachon, B.

2018-03-01

The LHC high-luminosity upgrade in 2024-2026 requires the associated detectors to operate at luminosities about 5-7 times larger than assumed in their original design. The pile-up is expected to increase to up to 200 events per proton bunch-crossing. The current readout of the ATLAS liquid argon calorimeters does not provide sufficient buffering and bandwidth capabilities to accommodate the hardware triggers requirements imposed by these harsh conditions. Furthermore, the expected total radiation doses are beyond the qualification range of the current front-end electronics. For these reasons an almost complete replacement of the front-end and off-detector readout system is foreseen for the 182,468 readout channels. The new readout system will be based on a free-running architecture, where calorimeter signals are amplified, shaped and digitized by on-detector electronics, then sent at 40 MHz to the off-detector electronics for further processing. Results from the design studies on the performance of the components of the readout system are presented, as well as the results of the tests of the first prototypes.

A novel pseudo resistor structure for biomedical front-end amplifiers.

PubMed

Yu-Chieh Huang; Tzu-Sen Yang; Shun-Hsi Hsu; Xin-Zhuang Chen; Jin-Chern Chiou

2015-08-01

This study proposes a novel pseudo resistor structure with a tunable DC bias voltage for biomedical front-end amplifiers (FEAs). In the proposed FEA, the high-pass filter composed of differential difference amplifier and a pseudo resistor is implemented. The FEA is manufactured by using a standard TSMC 0.35 μm CMOS process. In this study, three types FEAs included three different pseudo resistor are simulated, fabricated and measured for comparison and electrocorticography (ECoG) measurement, and all the results show the proposed pseudo resistor is superior to other two types in bandwidth. In chip implementation, the lower and upper cutoff frequencies of the high-pass filter with the proposed pseudo resistor are 0.15 Hz and 4.98 KHz, respectively. It also demonstrates lower total harmonic distortion performance of -58 dB at 1 kHz and higher stability with wide supply range (1.8 V and 3.3 V) and control voltage range (0.9 V and 1.65 V) than others. Moreover, the FEA with the proposed pseudo successfully recorded spike-and-wave discharges of ECoG signal in in vivo experiment on rat with pentylenetetrazol-induced seizures.

A dual slope charge sampling analog front-end for a wireless neural recording system.

PubMed

Lee, Seung Bae; Lee, Byunghun; Gosselin, Benoit; Ghovanloo, Maysam

2014-01-01

This paper presents a novel dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which amplifies neural signals by taking advantage of the charge sampling concept for analog signal conditioning, such as amplification and filtering. The presented DSCS-AFE achieves amplification, filtering, and sampling in a simultaneous fashion, while consuming very small amount of power. The output of the DSCS-AFE produces a pulse width modulated (PWM) signal that is proportional to the input voltage amplitude. A circular shift register (CSR) utilizes time division multiplexing (TDM) of the PWM pulses to create a pseudo-digital TDM-PWM signal that can feed a wireless transmitter. The 8-channel system-on-a-chip was fabricated in a 0.35-μm CMOS process, occupying 2.4 × 2.1 mm(2) and consuming 255 μW from a 1.8V supply. Measured input-referred noise for the entire system, including the FPGA in order to recover PWM signal is 6.50 μV(rms) in the 288 Hz~10 kHz range. For each channel, sampling rate is 31.25 kHz, and power consumption is 31.8 μW.

A Simulation of the Front End Signal Digitization for the ATLAS Muon Spectrometer thin RPC trigger upgrade project

NASA Astrophysics Data System (ADS)

Meng, Xiangting; Chapman, John; Levin, Daniel; Dai, Tiesheng; Zhu, Junjie; Zhou, Bing; Um Atlas Group Team

2016-03-01

The ATLAS Muon Spectrometer Phase-I (and Phase-II) upgrade includes the BIS78 muon trigger detector project: two sets of eight very thin Resistive Place Chambers (tRPCs) combined with small Monitored Drift Tube (MDT) chambers in the pseudorapidity region 1<| η|<1.3. The tRPCs will be comprised of triplet readout layer in each of the eta and azimuthal phi coordinates, with about 400 readout strips per layer. The anticipated hit rate is 100-200 kHz per strip. Digitization of the strip signals will be done by 32-channel CERN HPTDC chips. The HPTDC is a highly configurable ASIC designed by the CERN Microelectronics group. It can work in both trigger and trigger-less modes, be readout in parallel or serially. For Phase-I operation, a stringent latency requirement of 43 bunch crossings (1075 ns) is imposed. The latency budget for the front end digitization must be kept to a minimal value, ideally less than 350 ns. We conducted detailed HPTDC latency simulations using the Behavioral Verilog code from the CERN group. We will report the results of these simulations run for the anticipated detector operating environment and for various HPTDC configurations.

Picosecond Resolution Time-to-Digital Converter Using Gm-C Integrator and SAR-ADC

NASA Astrophysics Data System (ADS)

Xu, Zule; Miyahara, Masaya; Matsuzawa, Akira

2014-04-01

A picosecond resolution time-to-digital converter (TDC) is presented. The resolution of a conventional delay chain TDC is limited by the delay of a logic buffer. Various types of recent TDCs are successful in breaking this limitation, but they require a significant calibration effort to achieve picosecond resolution with a sufficient linear range. To address these issues, we propose a simple method to break the resolution limitation without any calibration: a Gm-C integrator followed by a successive approximation register analog-to-digital converter (SAR-ADC). This translates the time interval into charge, and then the charge is quantized. A prototype chip was fabricated in 90 nm CMOS. The measurement results reveal a 1 ps resolution, a -0.6/0.7 LSB differential nonlinearity (DNL), a -1.1/2.3 LSB integral nonlinearity (INL), and a 9-bit range. The measured 11.74 ps single-shot precision is caused by the noise of the integrator. We analyze the noise of the integrator and propose an improved front-end circuit to reduce this noise. The proposal is verified by simulations showing the maximum single-shot precision is less than 1 ps. The proposed front-end circuit can also diminish the mismatch effects.

A Dual Slope Charge Sampling Analog Front-End for a Wireless Neural Recording System

PubMed Central

Lee, Seung Bae; Lee, Byunghun; Gosselin, Benoit

2015-01-01

This paper presents a novel dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which amplifies neural signals by taking advantage of the charge sampling concept for analog signal conditioning, such as amplification and filtering. The presented DSCS-AFE achieves amplification, filtering, and sampling in a simultaneous fashion, while consuming very small amount of power. The output of the DSCS-AFE produces a pulse width modulated (PWM) signal that is proportional to the input voltage amplitude. A circular shift register (CSR) utilizes time division multiplexing (TDM) of the PWM pulses to create a pseudo-digital TDM-PWM signal that can feed a wireless transmitter. The 8-channel system-on-a-chip was fabricated in a 0.35-µm CMOS process, occupying 2.4 × 2.1 mm2 and consuming 255 µW from a 1.8V supply. Measured input-referred noise for the entire system, including the FPGA in order to recover PWM signal is 6.50 µVrms in the 288 Hz~10 kHz range. For each channel, sampling rate is 31.25 kHz, and power consumption is 31.8 µW. PMID:25570655

Onboard calibration circuit for the DAMPE BGO calorimeter front-end electronics

NASA Astrophysics Data System (ADS)

Zhang, De-Liang; Feng, Chang-Qing; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Shen, Zhong-Tao; Jiang, Di; Gao, Shan-Shan; Zhang, Yun-Long; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

2016-05-01

DAMPE (DArk Matter Particle Explorer) is a scientific satellite which is mainly aimed at indirectly searching for dark matter in space. One critical sub-detector of the DAMPE payload is the BGO (bismuth germanium oxide) calorimeter, which contains 1848 PMT (photomultiplier tube) dynodes and 16 FEE (Front-End Electronics) boards. VA160 and VATA160, two 32-channel low power ASICs (Application Specific Integrated Circuits), are adopted as the key components on the FEEs to perform charge measurement for the PMT signals. In order to monitor the parameter drift which may be caused by temperature variation, aging, or other environmental factors, an onboard calibration circuit is designed for the VA160 and VATA160 ASICs. It is mainly composed of a 12-bit DAC (Digital to Analog Converter), an operational amplifier and an analog switch. Test results showed that a dynamic range of 0-30 pC with a precision of 5 fC (Root Meam Square, RMS) was achieved, which covers the VA160’s input range. It can be used to compensate for the temperature drift and test the trigger function of the FEEs. The calibration circuit has been implemented for the front-end electronics of the BGO Calorimeter and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite was launched at the end of 2015 and the calibration circuit will operate periodically in space. Supported by Strategic Priority Research Program on Space Science of Chinese Academy of Sciences (XDA04040202-4), and National Basic Research Program (973 Program) of China (2010CB833002) and National Natural Science Foundation of China (11273070)

Development of a 3D CZT detector prototype for Laue Lens telescope

NASA Astrophysics Data System (ADS)

Caroli, Ezio; Auricchio, Natalia; Del Sordo, Stefano; Abbene, Leonardo; Budtz-Jørgensen, Carl; Casini, Fabio; Curado da Silva, Rui M.; Kuvvetlli, Irfan; Milano, Luciano; Natalucci, Lorenzo; Quadrini, Egidio M.; Stephen, John B.; Ubertini, Pietro; Zanichelli, Massimiliano; Zappettini, Andrea

2010-07-01

We report on the development of a 3D position sensitive prototype suitable as focal plane detector for Laue lens telescope. The basic sensitive unit is a drift strip detector based on a CZT crystal, (~19×8 mm2 area, 2.4 mm thick), irradiated transversally to the electric field direction. The anode side is segmented in 64 strips, that divide the crystal in 8 independent sensor (pixel), each composed by one collecting strip and 7 (one in common) adjacent drift strips. The drift strips are biased by a voltage divider, whereas the anode strips are held at ground. Furthermore, the cathode is divided in 4 horizontal strips for the reconstruction of the third interaction position coordinate. The 3D prototype will be made by packing 8 linear modules, each composed by one basic sensitive unit, bonded on a ceramic layer. The linear modules readout is provided by a custom front end electronics implementing a set of three RENA-3 for a total of 128 channels. The front-end electronics and the operating logics (in particular coincidence logics for polarisation measurements) are handled by a versatile and modular multi-parametric back end electronics developed using FPGA technology.

Front-end circuit for position sensitive silicon and vacuum tube photomultipliers with gain control and depth of interaction measurement

NASA Astrophysics Data System (ADS)

Herrero, Vicente; Colom, Ricardo; Gadea, Rafael; Lerche, Christoph W.; Cerdá, Joaquín; Sebastiá, Ángel; Benlloch, José M.

2007-06-01

Silicon Photomultipliers, though still under development for mass production, may be an alternative to traditional Vacuum Photomultipliers Tubes (VPMT). As a consequence, electronic front-ends initially designed for VPMT will need to be modified. In this simulation, an improved architecture is presented which is able to obtain impact position and depth of interaction of a gamma ray within a continuous scintillation crystal, using either kind of PM. A current sensitive preamplifier stage with individual gain adjustment interfaces the multi-anode PM outputs with a current division resistor network. The preamplifier stage allows to improve front-end processing delay and temporal resolution behavior as well as to increase impact position calculation resolution. Depth of interaction (DOI) is calculated from the width of the scintillation light distribution, which is related to the sum of voltages in resistor network input nodes. This operation is done by means of a high-speed current mode scheme.

A new data acquisition system for the CMS Phase 1 pixel detector

NASA Astrophysics Data System (ADS)

Kornmayer, A.

2016-12-01

A new pixel detector will be installed in the CMS experiment during the extended technical stop of the LHC at the beginning of 2017. The new pixel detector, built from four layers in the barrel region and three layers on each end of the forward region, is equipped with upgraded front-end readout electronics, specifically designed to handle the high particle hit rates created in the LHC environment. The DAQ back-end was entirely redesigned to handle the increased number of readout channels, the higher data rates per channel and the new digital data format. Based entirely on the microTCA standard, new front-end controller (FEC) and front-end driver (FED) cards have been developed, prototyped and produced with custom optical link mezzanines mounted on the FC7 AMC and custom firmware. At the same time as the new detector is being assembled, the DAQ system is set up and its integration into the CMS central DAQ system tested by running the pilot blade detector already installed in CMS. This work describes the DAQ system, integration tests and gives an outline for the activities up to commissioning the final system at CMS in 2017.

FRONT DETAIL OF RIGHT ENGINE AND WING. MECHANICS CHECK METAL ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

FRONT DETAIL OF RIGHT ENGINE AND WING. MECHANICS CHECK METAL CHIP DETECTOR ON RIGHT ENGINE. THE LEADING EDGE FLAPS ON THE RIGHT WING ARE DOWN PRIOR TO LUBRICATION. - Greater Buffalo International Airport, Maintenance Hangar, Buffalo, Erie County, NY

Camera Development for the Cherenkov Telescope Array

NASA Astrophysics Data System (ADS)

Moncada, Roberto Jose

2017-01-01

With the Cherenkov Telescope Array (CTA), the very-high-energy gamma-ray universe, between 30 GeV and 300 TeV, will be probed at an unprecedented resolution, allowing deeper studies of known gamma-ray emitters and the possible discovery of new ones. This exciting project could also confirm the particle nature of dark matter by looking for the gamma rays produced by self-annihilating weakly interacting massive particles (WIMPs). The telescopes will use the imaging atmospheric Cherenkov technique (IACT) to record Cherenkov photons that are produced by the gamma-ray induced extensive air shower. One telescope design features dual-mirror Schwarzschild-Couder (SC) optics that allows the light to be finely focused on the high-resolution silicon photomultipliers of the camera modules starting from a 9.5-meter primary mirror. Each camera module will consist of a focal plane module and front-end electronics, and will have four TeV Array Readout with GSa/s Sampling and Event Trigger (TARGET) chips, giving them 64 parallel input channels. The TARGET chip has a self-trigger functionality for readout that can be used in higher logic across camera modules as well as across individual telescopes, which will each have 177 camera modules. There will be two sites, one in the northern and the other in the southern hemisphere, for full sky coverage, each spanning at least one square kilometer. A prototype SC telescope is currently under construction at the Fred Lawrence Whipple Observatory in Arizona. This work was supported by the National Science Foundation's REU program through NSF award AST-1560016.

THE POSSIBLE ROLE OF CORONAL STREAMERS AS MAGNETICALLY CLOSED STRUCTURES IN SHOCK-INDUCED ENERGETIC ELECTRONS AND METRIC TYPE II RADIO BURSTS

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kong, Xiangliang; Chen, Yao; Feng, Shiwei

2015-01-10

Two solar type II radio bursts, separated by ∼24 hr in time, are examined together. Both events are associated with coronal mass ejections (CMEs) erupting from the same active region (NOAA 11176) beneath a well-observed helmet streamer. We find that the type II emissions in both events ended once the CME/shock fronts passed the white-light streamer tip, which is presumably the magnetic cusp of the streamer. This leads us to conjecture that the closed magnetic arcades of the streamer may play a role in electron acceleration and type II excitation at coronal shocks. To examine such a conjecture, we conduct a test-particle simulationmore » for electron dynamics within a large-scale partially closed streamer magnetic configuration swept by a coronal shock. We find that the closed field lines play the role of an electron trap via which the electrons are sent back to the shock front multiple times and therefore accelerated to high energies by the shock. Electrons with an initial energy of 300 eV can be accelerated to tens of keV concentrating at the loop apex close to the shock front with a counter-streaming distribution at most locations. These electrons are energetic enough to excite Langmuir waves and radio bursts. Considering the fact that most solar eruptions originate from closed field regions, we suggest that the scenario may be important for the generation of more metric type IIs. This study also provides an explanation of the general ending frequencies of metric type IIs at or above 20-30 MHz and the disconnection issue between metric and interplanetary type IIs.« less

Thermal ink-jet device using single-chip silicon microchannels

NASA Astrophysics Data System (ADS)

Wuu, DongSing; Cheng, Chen-Yue; Horng, RayHua; Chan, G. C.; Chiu, Sao-Ling; Wu, Yi-Yung

1998-06-01

We present a new method to fabricate silicon microfluidic channels by through-hole etching with subsequent planarization. The method is based on etching out the deep grooves through a perforated silicon carbide membrane, followed by sealing the membrane with plasma-enhanced chemical vapor deposition (PECVD). Low-pressure-chemical-vapor- deposited (LPCVD) polysilicon was used as a sacrificial layer to define the channel structure and only one etching step is required. This permits the realization of planarization after a very deep etching step in silicon and offers the possibility for film deposition, resist spinning and film patterning across deep grooves. The process technology was demonstrated on the fabrication of a monolithic silicon microchannel structure for thermal inkjet printing. The Ta-Al heater arrays are integrated on the top of each microchannel, which connect to a common on-chip front-end ink reservoir. The fabrication of this device requires six masks and no active nozzle-to-chip alignment. Moreover, the present micromachining process is compatible with the addition of on-chip circuitry for multiplexing the heater control signals. Heat transfer efficiency to the ink is enhanced by the high thermal conductivity of the silicon carbide in the channel ceiling, while the bulk silicon maintains high interchannel isolation. The fabricated inkjet devices show the droplet sizes of 20 - 50 micrometer in diameter with various channel dimensions and stable ejection of ink droplets more than 1 million.

A pixelated x-ray detector for diffraction imaging at next-generation high-rate FEL sources

NASA Astrophysics Data System (ADS)

Lodola, L.; Ratti, L.; Comotti, D.; Fabris, L.; Grassi, M.; Malcovati, P.; Manghisoni, M.; Re, V.; Traversi, G.; Vacchi, C.; Batignani, G.; Bettarini, S.; Forti, F.; Casarosa, G.; Morsani, F.; Paladino, A.; Paoloni, E.; Rizzo, G.; Benkechkache, M. A.; Dalla Betta, G.-F.; Mendicino, R.; Pancheri, L.; Verzellesi, G.; Xu, H.

2017-08-01

The PixFEL collaboration has developed the building blocks for an X-ray imager to be used in applications at FELs. In particular, slim edge pixel detectors with high detection efficiency over a broad energy range, from 1 to 12 keV, have been developed. Moreover, a multichannel readout chip, called PFM2 (PixFEL front-end Matrix 2) and consisting of 32 × 32 cells, has been designed and fabricated in a 65 nm CMOS technology. The pixel pitch is 110 μm, the overall area is around 16 mm2. In the chip, different solutions have been implemented for the readout channel, which includes a charge sensitive amplifier (CSA) with dynamic signal compression, a time-variant shaper and an A-to-D converter with a 10 bit resolution. The CSA can be configured in four different gain modes, so as to comply with photon energies in the 1 to 10 keV range. The paper will describe in detail the channel architecture and present the results from the characterization of PFM2. It will discuss the design of a new version of the chip, called PFM3, suitable for post-processing with peripheral, under-pad through silicon vias (TSVs), which are needed to develop four-side buttable chips and cover large surfaces with minimum inactive area.

Noise propagation issues in Belle II pixel detector power cable

NASA Astrophysics Data System (ADS)

Iglesias, M.; Arteche, F.; Echeverria, I.; Pradas, A.; Rivetta, C.; Moser, H.-G.; Kiesling, C.; Rummel, S.; Arcega, F. J.

2018-04-01

The vertex detector used in the upgrade of High-Energy physics experiment Belle II includes DEPFET pixel detector (PXD) technology. In this complex topology the power supply units and the front-end electronics are connected through a PXD power cable bundle which may propagate the output noise from the power supplies to the vertex area. This paper presents a study of the propagation of noise caused by power converters in the PXD cable bundle based on Multi-conductor Transmission Line (MTL) theory. The work exposes the effect of the complex cable topology and shield connections on the noise propagation, which has an impact on the requirements of the power supplies. This analysis is part of the electromagnetic compatibility based design focused on functional safety to define the shield connections and power supply specifications required to ensure the successful integration of the detector and, specifically, to achieve the designed performance of the front-end electronics.

Wireless biopotential acquisition system for portable healthcare monitoring.

PubMed

Wang, W-S; Huang, H-Y; Wu, Z-C; Chen, S-C; Wang, W-F; Wu, C-F; Luo, C-H

2011-07-01

A complete biopotential acquisition system with an analogue front-end (AFE) chip is proposed for portable healthcare monitoring. A graphical user interface (GUI) is also implemented to display the extracted biopotential signals in real-time on a computer for patients or in a hospital via the internet for doctors. The AFE circuit defines the quality of the acquired biosignals. Thus, an AFE chip with low power consumption and a high common-mode rejection ratio (CMRR) was implemented in the TSMC 0.18-μm CMOS process. The measurement results show that the proposed AFE, with a core area of 0.1 mm(2), has a CMRR of 90 dB, and power consumption of 21.6 μW. Biopotential signals of electroencephalogram (EEG), electrocardiogram (ECG) and electromyogram (EMG) were measured to verify the proposed system. The board size of the proposed system is 6 cm × 2.5 cm and the weight is 30 g. The total power consumption of the proposed system is 66 mW. Copyright © 2011 Informa UK, Ltd.

ICFA Instrumentation Bulletin, Volume 20, Spring 2000 Issue (SLAC-J-ICFA-020)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Va'Vra, J.

2003-10-20

Recent years have seen much dedicated work on front end electronics for hadron colliders, with a strong emphasis on radiation hardness and low cost. This has been challenging for a number of reasons, some of which are discussed further. The developments also suggest opportunities and constraints for the development of such electronics in the future.

DOE Office of Scientific and Technical Information (OSTI.GOV)

NONE

The ATLAS collaboration at LHC has chosen the Micromegas (Micro Mesh Gaseous Structure) technology along with the small-strip Thin Gap Chambers (sTGC) for the high luminosity upgrade of the inner muon station in the high-rapidity region, the so called New Small Wheel (NSW). It employs eight layers of Micromegas detectors and eight layers of sTGC. The NSW project requires fully efficient Micromegas chambers with spatial resolution down to 100 μm in the precision coordinate for momentum reconstruction, and at mm level in the azimuthal (second) coordinate, over a total active area of 1200 m{sup 2}, with a rate capability upmore » to about 15 kHz/cm{sup 2} and operation in a moderate magnetic field up to B = 0.4 T. The required tracking capability is provided by the intrinsic space resolution combined with a mechanical precision at the level of 30 μm along the precision coordinate. Together with the precise tracking capability the Micromegas chambers should provide a trigger signal. Several tests have been performed on small (10x10 cm{sup 2}) and large (1 x 1 m{sup 2}) size single gap chambers prototypes using high energy hadron beams at CERN, low and intermediate energy (0.5-5 GeV) electron beams at Frascati and DESY, neutron beams at Demokritos (Athens) and Garching (Munich) and cosmic rays. More recently two quadruplets with dimensions 1.2 x 0.5 m{sup 2} and the same configuration and structure foreseen for the NSW upgrade have been built at CERN and tested with high energy pions/muons beam. Results obtained in the most recent tests, in different configurations and operating conditions, in dependence with the magnetic field, will be presented, along with a comparison between different read-out electronics, either based on the APV25 chips, or based on a new digital front-end ASIC developed in its second version (VMM2) as a new prototype of the final chip that will be employed in the NSW upgrade. (authors)« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kapusta, P.; Kisielewski, B.

In this paper the overvoltage protection modules (OVP) for the power supply (PS) system of the Belle II pixel detector (PXD) are described. The aim of the OVP is to protect the detector and associated electronics against overvoltage conditions. Most critical in the system are voltages supplying the front-end ASICs. The PXD detector consists of the DEPFET sensor modules with integrated chips like the Drain Current Digitizer, the Switcher and the Data Handling Processor. These chips, implemented in modern sub-micron technologies, are quite vulnerable to variations in the supply voltages. The PXD will be placed in the Belle II experimentmore » as close as possible to the interaction point, where access during experiment is very limited or even impossible, thus the PS and OVP systems exploit the remote-sensing method. Overvoltage conditions are due to failures of the PS itself, wrong setting of the output voltages or transient voltages coming out of hard noisy environment of the experiment. The OVP modules are parts of the PS modules. For powering the PXD 40 PS modules are placed 15 m outside the Belle II spectrometer. Each one is equipped with the OVP board. All voltages (22) are grouped in 4 domains: Analog, Digital, Steering and Gate which have independent grounds. The OVP boards are designed from integrated circuits from Linear Technology. All configurations were simulated with the Spice program. The control electronics is designed in a Xilinx CPLD. Two types of integrated circuits were used. LT4356 surge stopper protects loads from high voltage transients. The output voltages are limited to a safe value and also protect loads against over current faults. For less critical voltages, the LTC2912 voltage monitors are used that detect under-voltage and overvoltage events. It has to be noted that the OVP system is working independently of any other protection of the PS system, which increases its overall reliability. (authors)« less

KLauS: an ASIC for silicon photomultiplier readout and its application in a setup for production testing of scintillating tiles

NASA Astrophysics Data System (ADS)

Briggl, K.; Dorn, M.; Hagdorn, R.; Harion, T.; Schultz-Coulon, H. C.; Shen, W.

2014-02-01

KLauS is an ASIC produced in the AMS 0.35 μm SiGe process to read out the charge signals from silicon photomultipliers. Developed as an analog front-end for future calorimeters with high granularity as pursued by the AHCAL concept in the CALICE collaboration, the ASIC is designed to measure the charge signal of the sensors in a large dynamic range and with low electronic noise contributions. In order to tune the operation voltage of each sensor individually, an 8-bit DAC to tune the voltage at the input terminal within a range of 2V is implemented. Using an integrated fast comparator with low jitter, the time information can be measured with sub-nanosecond resolution. The low power consumption of the ASIC can be further decreased using power gating techniques. Future versions of KLauS are under development and will incorporate an ADC with a resolution of up to 12-bits and blocks for digital data transmission. The chip is used in a setup for mass testing and characterization of scintillator tiles for the AHCAL test beam program.

Market trends in the projection display industry

NASA Astrophysics Data System (ADS)

Dash, Sweta

2000-04-01

The projection display industry represents a multibillion- dollar market that includes four distinct technologies. High-volume consumer products and high-value business products drive the market, with different technologies being used in different application markets. The consumer market is dominated by rear CRT technology, especially in the projection television segment. But rear LCD (liquid crystal display) and rear reflective (DLP, or Digital Light ProcessingTM) televisions are slowly emerging as future competitors to rear CRT projectors. Front CRT projectors are still popular in the high-end home theater market. Front LCD technology and front DLP technology dominate the business market. Traditional light valve technology was the only solution for applications requiring high light outputs, but new three-chip DLP projectors meet the higher light output requirements at a lower price. In the last few years the strongest growth has been in the business market for multimedia presentation applications. This growth was due to the continued increase in display pixel formats, the continued reduction in projector weight, and the improved price/performance ratio. The projection display market will grow at a significant rate during the next five years, driven by the growth in ultraportable (< 10 pound) projectors and the shift in the consumer market to digital and HDTV products.

A beta-ray spectrometer based on a two-or three silicon detector coincidence telescope

NASA Astrophysics Data System (ADS)

Horowitz, Y. S.; Weizman, Y.; Hirning, C. R.

1996-02-01

This report describes the operation of a beta-ray energy spectrometer based on a silicon detector telescope using two or three elements. The front detector is a planar, totally-depleted, silicon surface barrier detector that is 97 μm thick, the back detector is a room-temperature, lithium compensated, silicon detector that is 5000 μm thick, and the intermediate detector is similar to the front detector but 72 μm thick and intended to be used only in intense photon fields. The three detectors are mounted in a light-tight aluminum housing. The capability of the spectrometer to reject photons is based upon the fact that the incident photon will have a small probability of simultaneously losing detectable energy in two detectors, and an even smaller probability of losing detectable energy in all three detectors. Electrons will, however, almost always record measurable events in either the front two or all three detectors. A coincidence requirement between the detectors thus rejects photon induced events. With a 97 μm thick detector the lower energy coincidence threshold is approximately 110 keV. With an ultra-thin 40 μm thick front detector, and operated at 15°C, the spectrometer is capable of detecting even 60-70 keV electrons with a coincidence efficiency of 60%. The spectrometer has been used to measure beta radiation fields in CANDU reactor working environments, and the spectral information is intended to support dose algorithms for the LiF TLD chips used in the Ontario Hydro dosimetry program.

Tests with beam setup of the TileCal phase-II upgrade electronics

NASA Astrophysics Data System (ADS)

Reward Hlaluku, Dingane

2017-09-01

The LHC has planned a series of upgrades culminating in the High Luminosity LHC which will have an average luminosity 5-7 times larger than the nominal Run-2 value. The ATLAS Tile calorimeter plans to introduce a new readout architecture by completely replacing the back-end and front-end electronics for the High Luminosity LHC. The photomultiplier signals will be fully digitized and transferred for every bunch crossing to the off-detector Tile PreProcessor. The Tile PreProcessor will further provide preprocessed digital data to the first level of trigger with improved spatial granularity and energy resolution in contrast to the current analog trigger signals. A single super-drawer module commissioned with the phase-II upgrade electronics is to be inserted into the real detector to evaluate and qualify the new readout and trigger concepts in the overall ATLAS data acquisition system. This new super-drawer, so-called hybrid Demonstrator, must provide analog trigger signals for backward compatibility with the current system. This Demonstrator drawer has been inserted into a Tile calorimeter module prototype to evaluate the performance in the lab. In parallel, one more module has been instrumented with two other front-end electronics options based on custom ASICs (QIE and FATALIC) which are under evaluation. These two modules together with three other modules composed of the current system electronics were exposed to different particles and energies in three test-beam campaigns during 2015 and 2016.

An undulator based soft x-ray source for microscopy on the Duke electron storage ring

NASA Astrophysics Data System (ADS)

Johnson, Lewis Elgin

1998-09-01

This dissertation describes the design, development, and installation of an undulator-based soft x-ray source on the Duke Free Electron Laser laboratory electron storage ring. Insertion device and soft x-ray beamline physics and technology are all discussed in detail. The Duke/NIST undulator is a 3.64-m long hybrid design constructed by the Brobeck Division of Maxwell Laboratories. Originally built for an FEL project at the National Institute of Standards and Technology, the undulator was acquired by Duke in 1992 for use as a soft x-ray source for the FEL laboratory. Initial Hall probe measurements on the magnetic field distribution of the undulator revealed field errors of more than 0.80%. Initial phase errors for the device were more than 11 degrees. Through a series of in situ and off-line measurements and modifications we have re-tuned the magnet field structure of the device to produce strong spectral characteristics through the 5th harmonic. A low operating K has served to reduce the effects of magnetic field errors on the harmonic spectral content. Although rms field errors remained at 0.75%, we succeeded in reducing phase errors to less than 5 degrees. Using trajectory simulations from magnetic field data, we have computed the spectral output given the interaction of the Duke storage ring electron beam and the NIST undulator. Driven by a series of concerns and constraints over maximum utility, personnel safety and funding, we have also constructed a unique front end beamline for the undulator. The front end has been designed for maximum throughput of the 1st harmonic around 40A in its standard mode of operation. The front end has an alternative mode of operation which transmits the 3rd and 5th harmonics. This compact system also allows for the extraction of some of the bend magnet produced synchrotron and transition radiation from the storage ring. As with any well designed front end system, it also provides excellent protection to personnel and to the storage ring. A diagnostic beamline consisting of a transmission grating spectrometer and scanning wire beam profile monitor was constructed to measure the spatial and spectral characteristics of the undulator radiation. Test of the system with a circulating electron beam has confirmed the magnetic and focusing properties of the undulator, and verified that it can be used without perturbing the orbit of the beam.

Electronics design of the RPC system for the OPERA muon spectrometer

NASA Astrophysics Data System (ADS)

Acquafredda, R.; Ambrosio, M.; Balsamo, E.; Barichello, G.; Bergnoli, A.; Consiglio, L.; Corradi, G.; dal Corso, F.; Felici, G.; Manea, C.; Masone, V.; Parascandolo, P.; Sorrentino, G.

2004-09-01

The present document describes the front-end electronics of the RPC system that instruments the magnet muon spectrometer of the OPERA experiment. The main task of the OPERA spectrometer is to provide particle tracking information for muon identification and simplify the matching between the Precision Trackers. As no trigger has been foreseen for the experiment, the spectrometer electronics must be self-triggered with single-plane readout capability. Moreover, precision time information must be added within each event frame for off-line reconstruction. The read-out electronics is made of three different stages: the Front-End Boards (FEBs) system, the Controller Boards (CBs) system and the Trigger Boards (TBs) system. The FEB system provides discrimination of the strip incoming signals; a FAST-OR output of the input signals is also available for trigger plane signal generation. FEB signals are acquired by the CB system that provides the zero suppression and manages the communication to the DAQ and Slow Control. A Trigger Board allows to operate in both self-trigger mode (the FEB's FAST-OR signal starts the plane acquisition) or in external-trigger mode (different conditions can be set on the FAST-OR signals generated from different planes).

Testing of Front End Electronics for 10ps Time of Flight Detectors

NASA Astrophysics Data System (ADS)

Kimball, Matthew; EIC PID Consortium Collaboration

2016-09-01

To fully achieve the physics goals of the future Electron Ion Collider (EIC), continued development of the detectors involved is needed. One area of research involves improving the timing resolution of Time of Flight (ToF) detectors from 100ps to 10ps. When the timing resolution of these ToF detectors is improved, better particle identification can be achieved. In addition, as ToF detectors are being constructed with ever improving timing resolution, the need to improve the high speed performance of the fast electronics used in their front-end electronics (FEE) increases. A series of careful measurements has been performed to investigate the performance and efficiency of each element in the FEE chain. The focus of these tests lies on the amplitude transmission efficiency of the high speed signals as a function of frequency, also known as the bandwidth. The components tested include balanced to unbalanced (balun) boards, signal pre-amps, and waveform digitizers. These tests were performed on individual components and with all elements connected over a frequency range of 1MHz to 1GHz. The results of these tests will be presented. This research was supported by US DOE MENP Grant DE-FG02-03ER41243.

The phase 1 upgrade of the CMS Pixel Front-End Driver

NASA Astrophysics Data System (ADS)

Friedl, M.; Pernicka, M.; Steininger, H.

2010-12-01

The pixel detector of the CMS experiment at the LHC is read out by analog optical links, sending the data to 9U VME Front-End Driver (FED) boards located in the electronics cavern. There are plans for the phase 1 upgrade of the pixel detector (2016) to add one more layer, while significantly cutting down the overall material budget. At the same time, the optical data transmission will be replaced by a serialized digital scheme. A plug-in board solution with a high-speed digital optical receiver has been developed for the Pixel-FED readout boards and will be presented along with first tests of the future optical link.

Flexible implementation of front-end bioelectric signal amplifier using FPAA for telemedicine system.

PubMed

Chan, U Fai; Chan, Wai Wong; Pun, Sio Hang; Vai, Mang I; Mak, Peng Un

2007-01-01

Traditional/Current electronic circuits for Telemedicine have significant performance on certain bioelectric signal detection. However, it is rarely seen that can handle multiple signals without changing of hardware. This paper introduces a general front-end amplifier for various bioelectric signals based on Field Programmable Analogy Array (FPAA) Technology. Employing FPAA technology, the implemented amplifier can be adapted for various bioelectric signals without alternating the circuitry while its compact size (core parts < 2 cm2) provides an alternative solution for miniaturized Telemedicine system and Wearable Devices. The proposed design implementation has demonstrated, through successfully ECG and EMG signal extractions, a quick way to miniaturize analog biomedical circuit in a convenient and cost effective way.

SPIDR, a general-purpose readout system for pixel ASICs

NASA Astrophysics Data System (ADS)

van der Heijden, B.; Visser, J.; van Beuzekom, M.; Boterenbrood, H.; Kulis, S.; Munneke, B.; Schreuder, F.

2017-02-01

The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a "soft core" CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four 10 Gigabit Ethernet links, and in addition provides the slow and fast control for the chip.

Front-end ASICs for high-energy astrophysics in space

NASA Astrophysics Data System (ADS)

Gevin, O.; Limousin, O.; Meuris, A.

2016-07-01

In most of embedded imaging systems for space applications, high granularity and increasing size of focal planes justify an almost systematic use of integrated circuits. . To fulfill challenging requirements for excellent spatial and energy resolution, integrated circuits must fit the sensors perfectly and interface the system such a way to optimize simultaneously noise, geometry and architecture. Moreover, very low power consumption and radiation tolerance are mandatory to envision a use onboard a payload in space. Consequently, being part of an optimized detection system for space, the integrated circuit is specifically designed for each application and becomes an Application Specific Integrated Circuits (ASIC). The paper focuses on mixed analog and digital signal ASICs for spectro-imaging systems in the keVMeV energy band. The first part of the paper summarizes the main advantages conferred by the use of front-end ASICs for highenergy astrophysics instruments in space mission. Space qualification of ASICs requires the chip to be radiation hard. The paper will shortly describe some of the typical hardening techniques and give some guidelines that an ASIC designer should follow to choose the most efficient technology for his project. The first task of the front-end electronics is to convert the charge coming from the detector into a voltage. For most of the Silicon detectors (CCD, DEPFET, SDD) this is conversion happens in the detector itself. For other sensor materials, charge preamplifiers operate the conversion. The paper shortly describes the different key parameters of charge preamplifiers and the binding parameters for the design. Filtering is generally mandatory in order to increase the signal to noise ratio or to reduce the duration of the signal. After a brief review on the main noise sources, the paper reviews noise-filtering techniques that are commonly used in Integrated circuits designs. The way sensors and ASICs are interconnected together plays a major role in the noise performances of the detection systems. The geometry of a sensor is therefore critical and drives the ASIC design. The second part of the paper takes the geometry of the detector as a story line to explore different kinds of ASIC structures and architectures. From the simple single-channel ASIC for CCDs to the most advanced 3D ASIC prototypes used to build dead-zone free imaging systems, the paper reports on different families of circuits for spectro-imaging systems. It emphasizes a variety of designer choices, all around the word, in different space missions.

Vortex nozzle for segmenting and transporting metal chips from turning operations

DOEpatents

Bieg, L.F.

1993-04-20

Apparatus for collecting, segmenting and conveying metal chips from machining operations utilizes a compressed gas driven vortex nozzle for receiving the chip and twisting it to cause the chip to segment through the application of torsional forces to the chip. The vortex nozzle is open ended and generally tubular in shape with a converging inlet end, a constant diameter throat section and a diverging exhaust end. Compressed gas is discharged through angled vortex ports in the nozzle throat section to create vortex flow in the nozzle and through an annular inlet at the entrance to the converging inlet end to create suction at the nozzle inlet and cause ambient air to enter the nozzle. The vortex flow in the nozzle causes the metal chip to segment and the segments thus formed to pass out of the discharge end of the nozzle where they are collected, cleaned and compacted as needed.

Beam dynamics performances and applications of a low-energy electron-beam magnetic bunch compressor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Prokop, C. R.; Piot, P.; Carlsten, B. E.

2013-08-01

Many front-end applications of electron linear accelerators rely on the production of temporally compressed bunches. The shortening of electron bunches is often realized with magnetic bunch compressors located in high-energy sections of accelerators. Magnetic compression is subject to collective effects including space charge and self interaction via coherent synchrotron radiation. In this paper we explore the application of magnetic compression to low-energy (~40MeV), high-charge (nC) electron bunches with low normalized transverse emittances (<5@mm).

Performance optimization of detector electronics for millimeter laser ranging

NASA Technical Reports Server (NTRS)

Cova, Sergio; Lacaita, A.; Ripamonti, Giancarlo

1993-01-01

The front-end electronic circuitry plays a fundamental role in determining the performance actually obtained from ultrafast and highly sensitive photodetectors. We deal here with electronic problems met working with microchannel plate photomultipliers (MCP-PMTs) and single photon avalanche diodes (SPADs) for detecting single optical photons and measuring their arrival time with picosecond resolution. The performance of available fast circuits is critically analyzed. Criteria for selecting the most suitable electronics are derived and solutions for exploiting the detector performance are presented and discussed.

Development of BPM Electronics at the JLAB FEL

NASA Astrophysics Data System (ADS)

Sexton, D.; Evtushenko, P.; Jordan, K.; Yan, J.; Dutton, S.; Moore, W.; Evans, R.; Coleman, J.

2006-11-01

A new version of BPM electronics based on the AD8362 RMS detector, which is a direct RF to DC converter, is under development at the JLAB FEL. Each of these new BPM electronics utilizes an embedded ColdFire Microprocessor for data processing and communication with the EPICS control system via TCP/IP. The ColdFire runs RTEMS, which is an open source real-time operating system. The JLAB FEL is a SRF Energy Recovery LINAC capable of running up to 10 mA CW beam with a 74.85 MHz micropulse frequency. For diagnostic reasons and for machine tune up, the micropulse frequency can be reduced to 1.17 MHz, which corresponds to about 160 μA of beam current. It is required that the BPM system would be functional for all micropulse frequencies. By taking into account the headroom for the beam steering and current variations the dynamic range of the RF front end is required to be about 60 dB. A BPM resolution of at least 100 μm is required, whereas better resolution is very desirable to make it possible for more accurate measurements of the electron beam optics. Some results of the RF front end development are presented as well as the first measurements made with an electron beam.

Development of BPM Electronics at the JLAB FEL

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sexton, D.; Evtushenko, P.; Jordan, K.

2006-11-20

A new version of BPM electronics based on the AD8362 RMS detector, which is a direct RF to DC converter, is under development at the JLAB FEL. Each of these new BPM electronics utilizes an embedded ColdFire Microprocessor for data processing and communication with the EPICS control system via TCP/IP. The ColdFire runs RTEMS, which is an open source real-time operating system. The JLAB FEL is a SRF Energy Recovery LINAC capable of running up to 10 mA CW beam with a 74.85 MHz micropulse frequency. For diagnostic reasons and for machine tune up, the micropulse frequency can be reducedmore » to 1.17 MHz, which corresponds to about 160 {mu}A of beam current. It is required that the BPM system would be functional for all micropulse frequencies. By taking into account the headroom for the beam steering and current variations the dynamic range of the RF front end is required to be about 60 dB. A BPM resolution of at least 100 {mu}m is required, whereas better resolution is very desirable to make it possible for more accurate measurements of the electron beam optics. Some results of the RF front end development are presented as well as the first measurements made with an electron beam.« less

Development of BPM Electronics at the JLAB FEL

DOE Office of Scientific and Technical Information (OSTI.GOV)

Daniel Sexton; Pavel Evtushenko; Kevin Jordan

2006-05-01

A new version of BPM electronics based on the AD8362 RMS detector, which is a direct RF to DC converter, is under development at the JLAB FEL. Each of these new BPM electronics utilizes an embedded ColdFire Microprocessor for data processing and communication with the EPICS control system via TCP/IP. The ColdFire runs RTEMS, which is an open source real-time operating system. The JLAB FEL is a SRF Energy Recovery LINAC capable of running up to 10 mA CW beam with the micropulse up to 74.85 MHz. For diagnostic reasons and for the machine tune up, the micropulse frequency canmore » be reduced to 1.17 MHz, which corresponds to about 160 ?A of beam current. It is required that the BPM system would be functional for all micropulse frequencies. By taking into account the headroom for the beam steering and current variations the dynamic range of the RF front end is required to be about 60 dB. A BPM resolution of at least 100 ?m is required, whereas better resolution is very desirable to make it possible for more accurate measurements of the electron beam optics. Some results of the RF front end development are presented as well as the first measurements made with an electron beam.« less

Development of a timing detector for the TOTEM experiment at the LHC

NASA Astrophysics Data System (ADS)

Minafra, Nicola

2017-09-01

The upgrade program of the TOTEM experiment will include the installation of timing detectors inside vertical Roman Pots to allow the reconstruction of the longitudinal vertex position in the presence of event pile-up in high- β^{\\ast} dedicated runs. The small available space inside the Roman Pot, optimized for high-intensity LHC runs, and the required time precision led to the study of a solution using single crystal CVD diamonds. The sensors are read out using fast low-noise front-end electronics developed by the TOTEM Collaboration, achieving a signal-to-noise ratio larger than 20 for MIPs. A prototype was designed, manufactured and tested during a test beam campaign, proving a time precision below 100ps and an efficiency above 99%. The geometry of the detector has been designed to guarantee uniform occupancy in the expected running conditions keeping, at the same time, the number of channels below 12. The read-out electronics was developed during an extensive campaign of beam tests dedicated first to the characterization of existing solution and then to the optimization of the electronics designed within the Collaboration. The detectors were designed to be read out using the SAMPIC chip, a fast sampler designed specifically for picosecond timing measurements with high-rate capabilities; later, a modified version was realized using the HPTDC to achieve the higher trigger rates required for the CT-PPS experiment. The first set of prototypes was successfully installed and tested in the LHC in November 2015; moreover the detectors modified for CT-PPS are successfully part of the global CMS data taking since October 2016.

Parallel integrated frame synchronizer chip

NASA Technical Reports Server (NTRS)

Solomon, Jeffrey Michael (Inventor); Ghuman, Parminder Singh (Inventor); Bennett, Toby Dennis (Inventor)

2000-01-01

A parallel integrated frame synchronizer which implements a sequential pipeline process wherein serial data in the form of telemetry data or weather satellite data enters the synchronizer by means of a front-end subsystem and passes to a parallel correlator subsystem or a weather satellite data processing subsystem. When in a CCSDS mode, data from the parallel correlator subsystem passes through a window subsystem, then to a data alignment subsystem and then to a bit transition density (BTD)/cyclical redundancy check (CRC) decoding subsystem. Data from the BTD/CRC decoding subsystem or data from the weather satellite data processing subsystem is then fed to an output subsystem where it is output from a data output port.

An accuracy aware low power wireless EEG unit with information content based adaptive data compression.

PubMed

Tolbert, Jeremy R; Kabali, Pratik; Brar, Simeranjit; Mukhopadhyay, Saibal

2009-01-01

We present a digital system for adaptive data compression for low power wireless transmission of Electroencephalography (EEG) data. The proposed system acts as a base-band processor between the EEG analog-to-digital front-end and RF transceiver. It performs a real-time accuracy energy trade-off for multi-channel EEG signal transmission by controlling the volume of transmitted data. We propose a multi-core digital signal processor for on-chip processing of EEG signals, to detect signal information of each channel and perform real-time adaptive compression. Our analysis shows that the proposed approach can provide significant savings in transmitter power with minimal impact on the overall signal accuracy.

A 2 Thz Schottky Solid-State Heterodyne Receiver for Atmospheric Studies

NASA Technical Reports Server (NTRS)

Treuttel, Jeanne; Schlecht, Erich; Siles, Jose; Lee, Choonsup; Lin, Robert; Thomas, Bertrand; Gonzalez-Olvero, David; Yee, Jeng-Hwa; Wu, Dong; Mehdi, Imran

2016-01-01

Obtaining temperature, pressure, and composition profiles along with wind velocities in the Earth's thermosphere/ionosphere system is a key NASA goal for understanding our planet. We report on the status of a technology development effort to build an all-solid-state heterodyne receiver at 2.06 terahertz that will allow the measurement of the 2.06 terahertz [OI] line for altitudes greater than 100 kilometers. The receiver front end features low-parasitic Schottky diode mixer chips that are driven by a local oscillator (LO) source using Schottky diode based multipliers. The multiplier chain consists of a 38 gigahertz oscillator followed by a set of three cascaded triplers at 114 gigahertz, 343 gigahertz and 1.03 terahertz.

Study on Radiation Condition in DAMPE Orbit by Analyzing the Engineering Data of BGO Calorimeter

NASA Astrophysics Data System (ADS)

Feng, Changqing; Liu, Shubin; Zhang, Yunlong; Ma, Siyuan

2016-07-01

The DAMPE (DArk Matter Particle Explorer) is a scientific satellite which was successfully launched into a 500 Km sun-synchronous orbit, on December 17th, 2015, from the Jiuquan Satellite Launch Center of China. The major scientific objectives of the DAMPE mission are primary cosmic ray, gamma ray astronomy and dark matter particles, by observing high energy primary cosmic rays, especially positrons/electrons and gamma rays with an energy range from 5 GeV to 10 TeV. The BGO calorimeter is a critical sub-detector of DAMPE payload, for measuring the energy of cosmic particles, distinguishing positrons/electrons and gamma rays from hadron background, and providing trigger information. It utilizes 308 BGO (Bismuth Germanate Oxide) crystal logs with the size of 2.5cm*2.5cm*60cm for each log, to form a total absorption electromagnetic calorimeter. All the BGO logs are stacked in 14 layers, with each layer consisting of 22 BGO crystal logs and each log is viewed by two Hamamatsu R5610A PMTs (photomultiplier tubes), from both sides respectively. In order to achieve a large dynamic range, each PMT base incorporates a three dynode (2, 5, 8) pick off, which results in 616 PMTs and 1848 signal channels. The readout electronics system, which consists of 16 FEE (Front End Electronics) modules, was developed. Its main functions are based on the Flash-based FPGA (Field Programmable Gate Array) chip and low power, 32-channel VA160 and VATA160 ASICs (Application Specific Integrated Circuits) for precisely measuring the charge of PMT signals and providing "hit" signals as well. The hit signals are sent to the trigger module of PDPU (Payload Data Process Unit) and the hit rates of each layer is real-timely recorded by counters and packed into the engineering data, which directly reflect the flux of particles which fly into or pass through the detectors. In order to mitigate the SEU (Single Event Upset) effect in radioactive space environment, certain protecting methods, such as TMR (Triple Modular Redundancy) and CRC (Cyclic Redundancy Check) for some critical registers in FPGA logic was adopted. To mitigate the SEL (Single Event Latch-up) effect for the ASICs chips, a protecting solution by monitoring the current of VA160/VATA160 chips are applied. All the SEU and SEL events are recorded by counters and transmitted to ground station in the form of engineering data. The information of hit rates, and the SEU and SEL counters in the engineering data can be used to evaluate the radiation condition and its variations in DAMPE orbit. The preliminary results are introduced in this paper, which is based on the engineering data in the first six months after launching.

An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras.

PubMed

Bolotnikov, A E; Ackley, K; Camarda, G S; Cherches, C; Cui, Y; De Geronimo, G; Fried, J; Hodges, D; Hossain, A; Lee, W; Mahler, G; Maritato, M; Petryk, M; Roy, U; Salwen, C; Vernon, E; Yang, G; James, R B

2015-07-01

We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm(3) detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays' performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.

REACH: a high-performance wireless base station front end

NASA Astrophysics Data System (ADS)

Nettleton, Ray W.

1996-01-01

The link budget determines the relationships between range, capacity and transmitted power for any wireless technology. In every case it is a key determinant of the system's performance from both an engineering and an economic point of view. Unfortunately, the new 1.9 GHz PCS systems will begin life with an inherent 7 dB disadvantage over the 800 MHz cellular due to propagation differences. Additionally, system wiring and electronics often degrade performance by a further 5 to 10 dB due to long coaxial runs and noisy front end amplification, both of which are harder issues to deal with at 1.9 GHz than at 800 MHz. SCT's REACHTM products address these shortcomings by packaging critical components--front end amplification, filtering, etc.--in a compact cryoelectronic package intended for mounting near the antennas of the base station. In a recent trial with Qualcomm in San Diego, this package improved the CDMA uplink budget by 6 dB--enough to halve the number of base stations that are needed in most areas. This paper examines the technical and economic ramifications of the REACHTM product.

An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras

DOE PAGES

Bolotnikov, A. E.; Ackley, K.; Camarda, G. S.; ...

2015-07-28

We developed a robust and low-cost array of virtual Frisch-grid CdZnTe (CZT) detectors coupled to a front-end readout ASIC for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6x6x15 mm 3 detectors grouped into 3x3 sub-arrays of 2x2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readoutmore » electronics. The further enhancement of the arrays’ performance and reduction of their cost are made possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.« less

Fully Integrated Passive UHF RFID Tag for Hash-Based Mutual Authentication Protocol.

PubMed

Mikami, Shugo; Watanabe, Dai; Li, Yang; Sakiyama, Kazuo

2015-01-01

Passive radio-frequency identification (RFID) tag has been used in many applications. While the RFID market is expected to grow, concerns about security and privacy of the RFID tag should be overcome for the future use. To overcome these issues, privacy-preserving authentication protocols based on cryptographic algorithms have been designed. However, to the best of our knowledge, evaluation of the whole tag, which includes an antenna, an analog front end, and a digital processing block, that runs authentication protocols has not been studied. In this paper, we present an implementation and evaluation of a fully integrated passive UHF RFID tag that runs a privacy-preserving mutual authentication protocol based on a hash function. We design a single chip including the analog front end and the digital processing block. We select a lightweight hash function supporting 80-bit security strength and a standard hash function supporting 128-bit security strength. We show that when the lightweight hash function is used, the tag completes the protocol with a reader-tag distance of 10 cm. Similarly, when the standard hash function is used, the tag completes the protocol with the distance of 8.5 cm. We discuss the impact of the peak power consumption of the tag on the distance of the tag due to the hash function.

Front end design of smartphone-based mobile health

NASA Astrophysics Data System (ADS)

Zhang, Changfan; He, Lingsong; Gao, Zhiqiang; Ling, Cong; Du, Jianhao

2015-02-01

Mobile health has been a new trend all over the world with the rapid development of intelligent terminals and mobile internet. It can help patients monitor health in-house and is convenient for doctors to diagnose remotely. Smart-phone-based mobile health has big advantages in cost and data sharing. Front end design of it mainly focuses on two points: one is implementation of medical sensors aimed at measuring kinds of medical signal; another is acquisition of medical signal from sensors to smart phone. In this paper, the above two aspects were both discussed. First, medical sensor implementation was proposed to refer to mature measurement solutions with ECG (electrocardiograph) sensor design taken for example. And integrated chip using can simplify design. Then second, typical data acquisition architecture of smart phones, namely Bluetooth and MIC (microphone)-based architecture, were compared. Bluetooth architecture should be equipped with an acquisition card; MIC design uses sound card of smart phone instead. Smartphone-based virtual instrument app design corresponding to above acquisition architecture was discussed. In experiments, Bluetooth and MIC architecture were used to acquire blood pressure and ECG data respectively. The results showed that Bluetooth design can guarantee high accuracy during the acquisition and transmission process, and MIC design is competitive because of low cost and convenience.

Study of the VMM1 read-out chip in a neutron irradiation environment

NASA Astrophysics Data System (ADS)

Alexopoulos, T.; Fanourakis, G.; Geralis, T.; Kokkoris, M.; Kourkoumeli-Charalampidi, A.; Papageorgiou, K.; Tsipolitis, G.

2016-05-01

Within 2015, the LHC operated close to the design energy of √s = 13-14 TeV delivering instantaneous luminosities up to Script L = 5 × 1033 cm-2s-1. The ATLAS Phase-I upgrade in 2018/19 will introduce the MicroMEGAS detectors in the area of the small wheel at the end caps. Accompanying new electronics are designed and built such as the VMM front end ASIC, which provides energy, timing and triggering information and allows fast data read-out. The first VMM version (VMM1) has been widely produced and tested in various test beams, whilst the second version (VMM2) is currently being tested. This paper focuses on the VMM1 single event upset studies and more specifically on the response of the configuration registers under harsh radiation environments. Similar conditions are expected at Run III with Script L = 2 × 1034 cm-2s-1 and a mean of 55 interactions per bunch crossing. Two VMM1s were exposed in a neutron irradiation environment using the TANDEM Van Der Graaff accelerator at NSCR Demokritos, Athens, Greece. The results showed a rate of SEU occurrences at a measured cross section of (4.1±0.8)×10-14 cm2/bit for each VMM. Consequently, when extrapolating this value to the luminosity expected in Run III, the occurrence is roughly 6 SEUs/min in all the read-out system comprising 40,000 VMMs installed during the Phase-I upgrade.

A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

NASA Technical Reports Server (NTRS)

Suarez, George; DuMonthier, Jeffrey J.; Sheikh, Salman S.; Powell, Wesley A.; King, Robyn L.

2012-01-01

Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

A front-end readout Detector Board for the OpenPET electronics system

NASA Astrophysics Data System (ADS)

Choong, W.-S.; Abu-Nimeh, F.; Moses, W. W.; Peng, Q.; Vu, C. Q.; Wu, J.-Y.

2015-08-01

We present a 16-channel front-end readout board for the OpenPET electronics system. A major task in developing a nuclear medical imaging system, such as a positron emission computed tomograph (PET) or a single-photon emission computed tomograph (SPECT), is the electronics system. While there are a wide variety of detector and camera design concepts, the relatively simple nature of the acquired data allows for a common set of electronics requirements that can be met by a flexible, scalable, and high-performance OpenPET electronics system. The analog signals from the different types of detectors used in medical imaging share similar characteristics, which allows for a common analog signal processing. The OpenPET electronics processes the analog signals with Detector Boards. Here we report on the development of a 16-channel Detector Board. Each signal is digitized by a continuously sampled analog-to-digital converter (ADC), which is processed by a field programmable gate array (FPGA) to extract pulse height information. A leading edge discriminator creates a timing edge that is ``time stamped'' by a time-to-digital converter (TDC) implemented inside the FPGA . This digital information from each channel is sent to an FPGA that services 16 analog channels, and then information from multiple channels is processed by this FPGA to perform logic for crystal lookup, DOI calculation, calibration, etc.

A front-end readout Detector Board for the OpenPET electronics system

DOE PAGES

Choong, W. -S.; Abu-Nimeh, F.; Moses, W. W.; ...

2015-08-12

Here, we present a 16-channel front-end readout board for the OpenPET electronics system. A major task in developing a nuclear medical imaging system, such as a positron emission computed tomograph (PET) or a single-photon emission computed tomograph (SPECT), is the electronics system. While there are a wide variety of detector and camera design concepts, the relatively simple nature of the acquired data allows for a common set of electronics requirements that can be met by a flexible, scalable, and high-performance OpenPET electronics system. The analog signals from the different types of detectors used in medical imaging share similar characteristics, whichmore » allows for a common analog signal processing. The OpenPET electronics processes the analog signals with Detector Boards. Here we report on the development of a 16-channel Detector Board. Each signal is digitized by a continuously sampled analog-to-digital converter (ADC), which is processed by a field programmable gate array (FPGA) to extract pulse height information. A leading edge discriminator creates a timing edge that is "time stamped" by a time-to-digital converter (TDC) implemented inside the FPGA. In conclusion, this digital information from each channel is sent to an FPGA that services 16 analog channels, and then information from multiple channels is processed by this FPGA to perform logic for crystal lookup, DOI calculation, calibration, etc.« less

Vortex Generators to Control Boundary Layer Interactions

NASA Technical Reports Server (NTRS)

Babinsky, Holger (Inventor); Loth, Eric (Inventor); Lee, Sang (Inventor)

2014-01-01

Devices for generating streamwise vorticity in a boundary includes various forms of vortex generators. One form of a split-ramp vortex generator includes a first ramp element and a second ramp element with front ends and back ends, ramp surfaces extending between the front ends and the back ends, and vertical surfaces extending between the front ends and the back ends adjacent the ramp surfaces. A flow channel is between the first ramp element and the second ramp element. The back ends of the ramp elements have a height greater than a height of the front ends, and the front ends of the ramp elements have a width greater than a width of the back ends.

DOE Office of Scientific and Technical Information (OSTI.GOV)

DE GERONIMO,G.; FRIED, J.; FROST, E.

We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detectormore » process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.« less

Noise propagation issues in Belle II pixel detector power cable

DOE PAGES

Iglesias, M.; Arteche, F.; Echeverria, I.; ...

2018-04-26

The vertex detector used in the upgrade of High-Energy physics experiment Belle II includes DEPFET pixel detector (PXD) technology. In this complex topology the power supply units and the front-end electronics are connected through a PXD power cable bundle which may propagate the output noise from the power supplies to the vertex area. This article presents a study of the propagation of noise caused by power converters in the PXD cable bundle based on Multi-conductor Transmission Line (MTL) theory. The work exposes the effect of the complex cable topology and shield connections on the noise propagation, which has an impactmore » on the requirements of the power supplies. This analysis is part of the electromagnetic compatibility based design focused on functional safety to define the shield connections and power supply specifications required to ensure the successful integration of the detector and, specifically, to achieve the designed performance of the front-end electronics.« less

Noise propagation issues in Belle II pixel detector power cable

DOE Office of Scientific and Technical Information (OSTI.GOV)

Iglesias, M.; Arteche, F.; Echeverria, I.

The vertex detector used in the upgrade of High-Energy physics experiment Belle II includes DEPFET pixel detector (PXD) technology. In this complex topology the power supply units and the front-end electronics are connected through a PXD power cable bundle which may propagate the output noise from the power supplies to the vertex area. This article presents a study of the propagation of noise caused by power converters in the PXD cable bundle based on Multi-conductor Transmission Line (MTL) theory. The work exposes the effect of the complex cable topology and shield connections on the noise propagation, which has an impactmore » on the requirements of the power supplies. This analysis is part of the electromagnetic compatibility based design focused on functional safety to define the shield connections and power supply specifications required to ensure the successful integration of the detector and, specifically, to achieve the designed performance of the front-end electronics.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shanks, Katherine S.; Philipp, Hugh T.; Weiss, Joel T.

Experiments at storage ring light sources as well as at next-generation light sources increasingly require detectors capable of high dynamic range operation, combining low-noise detection of single photons with large pixel well depth. XFEL sources in particular provide pulse intensities sufficiently high that a purely photon-counting approach is impractical. The High Dynamic Range Pixel Array Detector (HDR-PAD) project aims to provide a dynamic range extending from single-photon sensitivity to 10{sup 6} photons/pixel in a single XFEL pulse while maintaining the ability to tolerate a sustained flux of 10{sup 11} ph/s/pixel at a storage ring source. Achieving these goals involves themore » development of fast pixel front-end electronics as well as, in the XFEL case, leveraging the delayed charge collection due to plasma effects in the sensor. A first prototype of essential electronic components of the HDR-PAD readout ASIC, exploring different options for the pixel front-end, has been fabricated. Here, the HDR-PAD concept and preliminary design will be described.« less

Front-end electronics for the Muon Portal project

NASA Astrophysics Data System (ADS)

Garozzo, S.; Marano, D.; Bonanno, G.; Grillo, A.; Romeo, G.; Timpanaro, M. C.; Lo Presti, D.; Riggi, F.; Russo, V.; Bonanno, D.; La Rocca, P.; Longhitano, F.; Bongiovanni, D. G.; Fallica, G.; Valvo, G.

2016-10-01

The Muon Portal Project was born as a joint initiative between Italian research and industrial partners, aimed at the construction of a real-size working detector prototype to inspect the content of traveling containers by means of secondary cosmic-ray muon radiation and recognize potentially dangerous hidden materials. The tomographic image is obtained by reconstructing the incoming and outgoing muon trajectories when crossing the inspected volume, employing two tracker planes located above and below the container under inspection. In this paper, the design and development of the front-end electronics of the Muon Portal detector is presented, with particular emphasis being devoted to the photo-sensor devices detecting the scintillation light and to the read-out circuitry which is in charge of processing and digitizing the analog pulse signals. In addition, the remote control system, mechanical housing, and thermal cooling system of all structural blocks of the Muon Portal tracker are also discussed, demonstrating the effectiveness and functionality of the adopted design.

Development of 3He LPSDs and read-out system for the SANS spectrometer at CPHS

NASA Astrophysics Data System (ADS)

Huang, T. C.; Gong, H.; Shao, B. B.; Wang, X. W.; Zhang, Y.; Pang, B. B.

2014-01-01

The Compact Pulsed Hadron Source (CPHS) is a 13-MeV proton-linac-driven neutron source under construction in Tsinghua University. Time-of-flight (TOF) small-angle neutron scattering (SANS) spectrometer is one of the first instruments to be built. It is designed to use linear position-sensitive detectors (LPSDs) of 3He gas proportional counters to cover a 1 m×1 m area. Prototypical LPSDs (Φ = 12 mm, L=1 m) have been made and read-out system is developed based on charge division. This work describes the in-house fabrication of the prototypical LPSDs and design of the read-out system including front-end electronics and data acquisition (DAQ) system. Key factors of the front-end electronics are studied and optimized with PSPICE simulation. DAQ system is designed based on VME bus architecture and FPGA Mezzanine Card (FMC) standard with high flexibility and extendibility. Preliminary experiments are carried out and the results are present and discussed.

A digital front-end and readout microsystem for calorimetry at LHC

NASA Astrophysics Data System (ADS)

Alippi, C.; Appelquist, G.; Berglund, S.; Bohm, C.; Breveglieri, L.; Brigati, S.; Carlson, P.; Cattaneo, P.; Dadda, L.; David, J.; Del Buono, L.; Dell'Acqua, A.; Engström, M.; Fumagalli, G.; Gatti, U.; Genat, J. F.; Goggi, G.; Hansen, M.; Hentzell, H.; Höglund, I.; Inkinen, S.; Kerek, A.; Lebbolo, H.; LeDortz, O.; Lofstedt, B.; Maloberti, F.; Nayman, P.; Persson, S.-T.; Piuri, V.; Salice, F.; Sami, M.; Savoy-Navarro, A.; Stefanelli, R.; Sundblad, R.; Svensson, C.; Torelli, G.; Vanuxem, J. P.; Yamdagni, N.; Yuan, J.; Zitoun, R.

1994-04-01

A digital solution to the front-end electronics for calorimetric detectors at future supercolliders is presented. The solution is based on high speed {A}/{D} converters, a fully programmable pipeline/digital filter chain and local intelligence. Questions of error correction, fault-tolerance and system redundancy are also being considered. A system integration of a multichannel device in a multichip, Silicon-on-Silicon Microsystem hybrid, is used. This solution allows a new level of integration of complex analogue and digital functions, with an excellent flexibility in mixing technologies for the different functional blocks. It also allows a high degree of programmability at both the function and the system level, and offers the possibility of customising the microsystem with detector-specific functions.

Combined PET/MRI scanner

DOEpatents

Schlyer, David; Woody, Craig L.; Rooney, William; Vaska, Paul; Stoll, Sean; Pratte, Jean-Francois; O'Connor, Paul

2007-10-23

A combined PET/MRI scanner generally includes a magnet for producing a magnetic field suitable for magnetic resonance imaging, a radiofrequency (RF) coil disposed within the magnetic field produced by the magnet and a ring tomograph disposed within the magnetic field produced by the magnet. The ring tomograph includes a scintillator layer for outputting at least one photon in response to an annihilation event, a detection array coupled to the scintillator layer for detecting the at least one photon outputted by the scintillator layer and for outputting a detection signal in response to the detected photon and a front-end electronic array coupled to the detection array for receiving the detection signal, wherein the front-end array has a preamplifier and a shaper network for conditioning the detection signal.

Ionization Readout Electronics for SuperCDMS SNOLAB Employing a HEMT Front-End

NASA Astrophysics Data System (ADS)

Partridge, R.

2014-09-01

The SuperCDMS SNOLAB experiment seeks to deploy 200 kg of cryogenic Ge detectors employing phonon and ionization readout to identify dark matter interactions. One of the design challenges for the experiment is to provide amplification of the high impedance ionization signal while minimizing power dissipation and noise. This paper describes the design and expected performance of the ionization readout being developed for an engineering model of the SuperCDMS SNOLAB Ge Tower System. The readout features the use of a low-noise HEMT front end transistor operating at 4 K to achieve a power dissipation of 100 W per channel, local grounding to minimize noise injection, and biasing circuitry that allows precise control of the HEMT operating point.

Atom Optics for Bose-Einstein Condensates (BEC)

DTIC Science & Technology

2012-04-25

Electron Micrograph of the Top View of Test Chip A .......................................29 11. A Scanning Electron Micrograph of the Cross...Sectional View of Test Chip A .....................29 12. A Scanning Electron Micrograph of the Top View of Test Chip B...30 13. A Scanning Electron Micrograph of the Cross Sectional View of Test Chip B .....................30 14. Toner Masks for Etching

75 FR 70703 - Humana Insurance Company a Division of Carenetwork, Inc. Front End Operations and Account...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-11-18

... Division of CareNetwork, Inc., Front End Operations and Account Installation-Product Testing Groups, De... a Division of Carenetwork, Inc. Front End Operations and Account Installation-Product Testing Groups..., a Division of CareNetwork, Inc., Front End Operations and Account Installation- Product Testing...

Systematic analysis of CMOS-micromachined inductors with application to mixer matching circuits

NASA Astrophysics Data System (ADS)

Wu, Jerry Chun-Li

The growing demand for consumer voice and data communication systems and military communication applications has created a need for low-power, low-cost, high-performance radio-frequency (RF) front-end. To achieve this goal, bringing passive components, especially inductors, to silicon is imperative. On-chip passive components such as inductors and capacitors generally enhance the reliability and efficiency of silicon-integrated RF cells. They can provide circuit solutions with superior performance and contribute to a higher level of integration. With passive components on chip, there is a great opportunity to have transformers, filters, and matching networks on chip. However, inductors on silicon have a low quality factor (Q) due to both substrate and metal loss. This dissertation demonstrates the systematic analysis of inductors fabricated using standard complementary metal-oxide-semiconductor (CMOS) and micro-electro-mechanical (MEMS) system technologies. We report system-on-chip inductor modeling, simulation, and measurements of effective inductance and quality factors. In this analysis methodology, a number of systematic simulations are performed on regular and micromachined inductors with different parameters such as spiral topology, number of turns, outer diameter, thickness, and percentage of substrate removed by using micromachining technologies. Three different novel support structures of the micromachined spiral inductor are proposed, analyzed, and implemented for larger size suspended inductors. The sensitivity of the structure support and different degree of substrate etching by post-processing is illustrated. The results provide guidelines for the selection of inductor parameters, post-processing methodologies, and its spiral supports to meet the RF design specifications and the stability requirements for mobile communication. The proposed CMOS-micromachined inductor is used in a low cost-effective double-balanced Gilbert mixer with on-chip matching network. The integrated mixer inductor was implemented and tested to prove the concept.

A scalable silicon photonic chip-scale optical switch for high performance computing systems.

PubMed

Yu, Runxiang; Cheung, Stanley; Li, Yuliang; Okamoto, Katsunari; Proietti, Roberto; Yin, Yawei; Yoo, S J B

2013-12-30

This paper discusses the architecture and provides performance studies of a silicon photonic chip-scale optical switch for scalable interconnect network in high performance computing systems. The proposed switch exploits optical wavelength parallelism and wavelength routing characteristics of an Arrayed Waveguide Grating Router (AWGR) to allow contention resolution in the wavelength domain. Simulation results from a cycle-accurate network simulator indicate that, even with only two transmitter/receiver pairs per node, the switch exhibits lower end-to-end latency and higher throughput at high (>90%) input loads compared with electronic switches. On the device integration level, we propose to integrate all the components (ring modulators, photodetectors and AWGR) on a CMOS-compatible silicon photonic platform to ensure a compact, energy efficient and cost-effective device. We successfully demonstrate proof-of-concept routing functions on an 8 × 8 prototype fabricated using foundry services provided by OpSIS-IME.

Design of a Closed-Loop, Bidirectional Brain Machine Interface System With Energy Efficient Neural Feature Extraction and PID Control.

PubMed

Liu, Xilin; Zhang, Milin; Richardson, Andrew G; Lucas, Timothy H; Van der Spiegel, Jan

2017-08-01

This paper presents a bidirectional brain machine interface (BMI) microsystem designed for closed-loop neuroscience research, especially experiments in freely behaving animals. The system-on-chip (SoC) consists of 16-channel neural recording front-ends, neural feature extraction units, 16-channel programmable neural stimulator back-ends, in-channel programmable closed-loop controllers, global analog-digital converters (ADC), and peripheral circuits. The proposed neural feature extraction units includes 1) an ultra low-power neural energy extraction unit enabling a 64-step natural logarithmic domain frequency tuning, and 2) a current-mode action potential (AP) detection unit with time-amplitude window discriminator. A programmable proportional-integral-derivative (PID) controller has been integrated in each channel enabling a various of closed-loop operations. The implemented ADCs include a 10-bit voltage-mode successive approximation register (SAR) ADC for the digitization of the neural feature outputs and/or local field potential (LFP) outputs, and an 8-bit current-mode SAR ADC for the digitization of the action potential outputs. The multi-mode stimulator can be programmed to perform monopolar or bipolar, symmetrical or asymmetrical charge balanced stimulation with a maximum current of 4 mA in an arbitrary channel configuration. The chip has been fabricated in 0.18 μ m CMOS technology, occupying a silicon area of 3.7 mm 2 . The chip dissipates 56 μW/ch on average. General purpose low-power microcontroller with Bluetooth module are integrated in the system to provide wireless link and SoC configuration. Methods, circuit techniques and system topology proposed in this work can be used in a wide range of relevant neurophysiology research, especially closed-loop BMI experiments.

On-Wafer Measurement of a Multi-Stage MMIC Amplifier with 10 dB of Gain at 475 GHz

NASA Technical Reports Server (NTRS)

Samoska, Lorene A.; Fung, KingMan; Pukala, David M.; Kangaslahti, Pekka P.; Lai, Richard; Ferreira, Linda

2012-01-01

JPL has measured and calibrated a WR2.2 waveguide wafer probe from GGB Industries in order to allow for measurement of circuits in the 325-500 GHz range. Circuits were measured, and one of the circuits exhibited 10 dB of gain at 475 GHz. The MMIC circuit was fabricated at Northrop Grumman Corp. (NGC) as part of a NASA Innovative Partnerships Program, using NGC s 35-nm-gatelength InP HEMT process technology. The chip utilizes three stages of HEMT amplifiers, each having two gate fingers of 10 m in width. The circuits use grounded coplanar waveguide topology on a 50- m-thick substrate with through substrate vias. Broadband matching is achieved with coplanar waveguide transmission lines, on-chip capacitors, and open stubs. When tested with wafer probing, the chip exhibited 10 dB of gain at 475 GHz, with over 9 dB of gain from 445-490 GHz. Low-noise amplifiers in the 400-500 GHz range are useful for astrophysics receivers and earth science remote sensing instruments. In particular, molecular lines in the 400-500 GHz range include the CO 4-3 line at 460 GHz, and the CI fine structure line at 492 GHz. Future astrophysics heterodyne instruments could make use of high-gain, low-noise amplifiers such as the one described here. In addition, earth science remote sensing instruments could also make use of low-noise receivers with MMIC amplifier front ends. Present receiver technology typically employs mixers for frequency down-conversion in the 400-500 GHz band. Commercially available mixers have typical conversion loss in the range of 7-10 dB with noise figure of 1,000 K. A low-noise amplifier placed in front of such a mixer would have 10 dB of gain and lower noise figure, particularly if cooled to low temperature. Future work will involve measuring the noise figure of this amplifier.

A 0.18 μm biosensor front-end based on 1/f noise, distortion cancelation and chopper stabilization techniques.

PubMed

Balasubramanian, Viswanathan; Ruedi, Pierre-Francois; Temiz, Yuksel; Ferretti, Anna; Guiducci, Carlotta; Enz

2013-10-01

This paper presents a novel sensor front-end circuit that addresses the issues of 1/f noise and distortion in a unique way by using canceling techniques. The proposed front-end is a fully differential transimpedance amplifier (TIA) targeted for current mode electrochemical biosensing applications. In this paper, we discuss the architecture of this canceling based front-end and the optimization methods followed for achieving low noise, low distortion performance at minimum current consumption are presented. To validate the employed canceling based front-end, it has been realized in a 0.18 μm CMOS process and the characterization results are presented. The front-end has also been tested as part of a complete wireless sensing system and the cyclic voltammetry (CV) test results from electrochemical sensors are provided. Overall current consumption in the front-end is 50 μA while operating on a 1.8 V supply.

40 CFR 63.487 - Batch front-end process vents-reference control technology.

Code of Federal Regulations, 2010 CFR

2010-07-01

... § 63.487 Batch front-end process vents—reference control technology. (a) Batch front-end process vents... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents-reference control technology. 63.487 Section 63.487 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY...

A configurable electronics system for the ESS-Bilbao beam position monitors

NASA Astrophysics Data System (ADS)

Muguira, L.; Belver, D.; Etxebarria, V.; Varnasseri, S.; Arredondo, I.; del Campo, M.; Echevarria, P.; Garmendia, N.; Feuchtwanger, J.; Jugo, J.; Portilla, J.

2013-09-01

A versatile and configurable system has been developed in order to monitorize the beam position and to meet all the requirements of the future ESS-Bilbao Linac. At the same time the design has been conceived to be open and configurable so that it could eventually be used in different kinds of accelerators, independent of the charged particle, with minimal change. The design of the Beam Position Monitors (BPMs) system includes a test bench both for button-type pick-ups (PU) and striplines (SL), the electronic units and the control system. The electronic units consist of two main parts. The first part is an Analog Front-End (AFE) unit where the RF signals are filtered, conditioned and converted to base-band. The second part is a Digital Front-End (DFE) unit which is based on an FPGA board where the base-band signals are sampled in order to calculate the beam position, the amplitude and the phase. To manage the system a Multipurpose Controller (MC) developed at ESSB has been used. It includes the FPGA management, the EPICS integration and Archiver Instances. A description of the system and a comparison between the performance of both PU and SL BPM designs measured with this electronics system are fully described and discussed.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lombigit, L., E-mail: lojius@nm.gov.my; Rahman, Nur Aira Abd; Mohamad, Glam Hadzir Patai

A radioisotope identifier device based on large volume Co-planar grid CZT detector is current under development at Malaysian Nuclear Agency. This device is planned to be used for in-situ identification of radioisotopes based on their unique energies. This work reports on electronics testing performed on the front-end electronics (FEE) analog section comprising charge sensitive preamplifier-pulse shaping amplifier chain. This test involves measurement of charge sensitivity, pulse parameters and electronics noise. This report also present some preliminary results on the spectral measurement obtained from gamma emitting radioisotopes.

Electronic hardware design of electrical capacitance tomography systems.

PubMed

Saied, I; Meribout, M

2016-06-28

Electrical tomography techniques for process imaging are very prominent for industrial applications, such as the oil and gas industry and chemical refineries, owing to their ability to provide the flow regime of a flowing fluid within a relatively high throughput. Among the various techniques, electrical capacitance tomography (ECT) is gaining popularity due to its non-invasive nature and its capability to differentiate between different phases based on their permittivity distribution. In recent years, several hardware designs have been provided for ECT systems that have improved its resolution of measurements to be around attofarads (aF, 10(-18) F), or the number of channels, that is required to be large for some applications that require a significant amount of data. In terms of image acquisition time, some recent systems could achieve a throughput of a few hundred frames per second, while data processing time could be achieved in only a few milliseconds per frame. This paper outlines the concept and main features of the most recent front-end and back-end electronic circuits dedicated for ECT systems. In this paper, multiple-excitation capacitance polling, a front-end electronic technique, shows promising results for ECT systems to acquire fast data acquisition speeds. A highly parallel field-programmable gate array (FPGA) based architecture for a fast reconstruction algorithm is also described. This article is part of the themed issue 'Supersensing through industrial process tomography'. © 2016 The Author(s).

Adapting wave-front algorithms to efficiently utilize systems with deep communication hierarchies

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kerbyson, Darren J; Lang, Michael; Pakin, Scott

2009-01-01

Large-scale systems increasingly exhibit a differential between intra-chip and inter-chip communication performance. Processor-cores on the same socket are able to communicate at lower latencies, and with higher bandwidths, than cores on different sockets either within the same node or between nodes. A key challenge is to efficiently use this communication hierarchy and hence optimize performance. We consider here the class of applications that contain wave-front processing. In these applications data can only be processed after their upstream neighbors have been processed. Similar dependencies result between processors in which communication is required to pass boundary data downstream and whose cost ismore » typically impacted by the slowest communication channel in use. In this work we develop a novel hierarchical wave-front approach that reduces the use of slower communications in the hierarchy but at the cost of additional computation and higher use of on-chip communications. This tradeoff is explored using a performance model and an implementation on the Petascale Roadrunner system demonstrates a 27% performance improvement at full system-scale on a kernel application. The approach is generally applicable to large-scale multi-core and accelerated systems where a differential in system communication performance exists.« less

The front-end electronics of the LSPE-SWIPE experiment

NASA Astrophysics Data System (ADS)

Fontanelli, F.; Biasotti, M.; Bevilacqua, A.; Siccardi, F.

2016-07-01

The SWIPE detector of the Ballon Borne Mission LSPE (see e.g. the contribution of P. de Bernardis et al. in this conference) intends to measure the primordial 'B-mode' polarization of the Cosmic Microwave Background (CMB). For this scope microwave telescopes need sensitive cryogenic bolometers with an overall equivalent noise temperature in the nK range. The detector is a spiderweb bolometer based on transition edge sensor and followed by a SQUID to perform the signal readout. This contribution will concentrate on the design, description and first tests on the front-end electronics which processes the squid output (and controls it). The squid output is first amplified by a very low noise preamplifier based on a discrete JFET input differential architecture followed by a low noise CMOS operational amplifier. Equivalent input noise density is 0.6 nV/Hz and bandwidth extends up to at least 2 MHz. Both devices (JFET and CMOS amplifier) have been tested at liquid nitrogen. The second part of the contribution will discuss design and results of the control electronics, both the flux locked loop for the squid and the slow control chain to monitor and set up the system will be reviewed.

FPGA-Based Front-End Electronics for Positron Emission Tomography

PubMed Central

Haselman, Michael; DeWitt, Don; McDougald, Wendy; Lewellen, Thomas K.; Miyaoka, Robert; Hauck, Scott

2010-01-01

Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA’s low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for positron emission tomography (PET) scanners. Our laboratory is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this next generation scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilizes to add significant signal processing power to produce higher resolution images. In this paper two such processes, sub-clock rate pulse timing and event localization, will be discussed in detail. We show that timing performed in the FPGA can achieve a resolution that is suitable for small-animal scanners, and will outperform the analog version given a low enough sampling period for the ADC. We will also show that the position of events in the scanner can be determined in real time using a statistical positioning based algorithm. PMID:21961085

NECTAr: New electronics for the Cherenkov Telescope Array

NASA Astrophysics Data System (ADS)

Vorobiov, S.; Bolmont, J.; Corona, P.; Delagnes, E.; Feinstein, F.; Gascón, D.; Glicenstein, J.-F.; Naumann, C. L.; Nayman, P.; Sanuy, A.; Toussenel, F.; Vincent, P.

2011-05-01

The European astroparticle physics community aims to design and build the next generation array of Imaging Atmospheric Cherenkov Telescopes (IACTs), that will benefit from the experience of the existing H.E.S.S. and MAGIC detectors, and further expand the very-high energy astronomy domain. In order to gain an order of magnitude in sensitivity in the 10 GeV to >100TeV range, the Cherenkov Telescope Array (CTA) will employ 50-100 mirrors of various sizes equipped with 1000-4000 channels per camera, to be compared with the 6000 channels of the final H.E.S.S. array. A 3-year program, started in 2009, aims to build and test a demonstrator module of a generic CTA camera. We present here the NECTAr design of front-end electronics for the CTA, adapted to the trigger and data acquisition of a large IACTs array, with simple production and maintenance. Cost and camera performances are optimized by maximizing integration of the front-end electronics (amplifiers, fast analog samplers, ADCs) in an ASIC, achieving several GS/s and a few μs readout dead-time. We present preliminary results and extrapolated performances from Monte Carlo simulations.

Position sensitive and energy dispersive x-ray detector based on silicon strip detector technology

NASA Astrophysics Data System (ADS)

Wiącek, P.; Dąbrowski, W.; Fink, J.; Fiutowski, T.; Krane, H.-G.; Loyer, F.; Schwamberger, A.; Świentek, K.; Venanzi, C.

2015-04-01

A new position sensitive detector with a global energy resolution for the entire detector of about 380 eV FWHM for 8.04 keV line at ambient temperature is presented. The measured global energy resolution is defined by the energy spectra summed over all strips of the detector, and thus it includes electronic noise of the front-end electronics, charge sharing effects, matching of parameters across the channels and other system noise sources. The target energy resolution has been achieved by segmentation of the strips to reduce their capacitance and by careful optimization of the front-end electronics. The key design aspects and parameters of the detector are discussed briefly in the paper. Excellent noise and matching performance of the readout ASIC and negligible system noise allow us to operate the detector with a discrimination threshold as low as 1 keV and to measure fluorescence radiation lines of light elements, down to Al Kα of 1.49 keV, simultaneously with measurements of the diffraction patterns. The measurement results that demonstrate the spectrometric and count rate performance of the developed detector are presented and discussed in the paper.

Performance of the Low-Jitter High-Gain/Bandwidth Front-End Electronics of the HADES tRPC Wall

NASA Astrophysics Data System (ADS)

Belver, Daniel; Cabanelas, P.; Castro, E.; Garzon, J. A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M.

2010-10-01

A front-end electronics (FEE) chain for accurate time measurements has been developed for the new Resistive Plate Chamber (RPC)-based Time-of-Flight (TOF) wall of the High Acceptance Di-Electron Spectrometer (HADES). The wall covers an area of around 8 m2, divided in 6 sectors. In total, 1122 4-gap timing RPC cells are read-out by 2244 time and charge sensitive channels. The FEE chain consists of 2 custom-made boards: a 4-channel DaughterBOard (DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a dual high-speed discriminator. The time and charge information are encoded, respectively, in the leading edge and the width of an LVDS signal. Each MBO houses up to 8 DBOs providing them regulated voltage supply, threshold values via DACs, test signals and, additionally, routing out a signal proportional to the channel multiplicity needed for a 1st level trigger decision. The MBO delivers LVDS signals to a multi-purpose Trigger Readout Board (TRB) for data acquisition. The FEE allows achieving a system resolution around 75 ps fulfilling comfortably the requirements of the HADES upgrade .

Embedded electronics for a 64-channel wireless brain implant

NASA Astrophysics Data System (ADS)

Burgert, Johann D.; Malasek, Jan; Martel, Sylvain M.; Wiseman, Colette; Fofonoff, Timothy; Dyer, Robert; Hunter, Ian W.; Hatsopoulos, Nicholas; Donoghue, John

2001-10-01

The Telemetric Electrode Array System (TEAS) is a surgically implantable device for the study of neural activity in the brain. An 8x8 array of electrodes collects intra-cortical neural signals and connects them to an analog front end. The front end amplifies and digitizes these microvolt-level signals with 12 bits of resolution and at 31KHz per channel. Peak detection is used to extract the information carrying features of these signals, which are transmitted over a Bluetooth-based radio link at 725 Kbit/sec. The electrode array is made up of 1mm tall, 60-micron square electrodes spaced 500 microns tip-to-tip. A flex circuit connector provides mechanical isolation between the brain and the electronics, which are mounted to the cranium. Power consumption and management is a critical aspect of the design. The entire system must operate off a surgically implantable battery. With this power source, the system must provide the functionality of a wireless, 64-channel oscilloscope for several hours. The system also provides a low-power sleep mode during which the battery can be inductively charged. Power dissipation and biocompatibility issues also affect the design of the electronics for the probe. The electronics system must fit between the skull and the skin of the test subject. Thus, circuit miniaturization and microassembly techniques are essential to construct the probe's electronics.

Fractional Multistage Hydrothermal Liquefaction of Biomass and Catalytic Conversion into Hydrocarbons

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cortright, Randy; Rozmiarek, Robert; Dally, Brice

2017-08-31

The objective of this project was to develop an improved multistage process for the hydrothermal liquefaction (HTL) of biomass to serve as a new front-end, deconstruction process ideally suited to feed Virent’s well-proven catalytic technology, which is already being scaled up. This process produced water soluble, partially de-oxygenated intermediates that are ideally suited for catalytic finishing to fungible distillate hydrocarbons. Through this project, Virent, with its partners, demonstrated the conversion of pine wood chips to drop-in hydrocarbon distillate fuels using a multi-stage fractional conversion system that is integrated with Virent’s BioForming® process. The majority of work was in the liquefactionmore » task and included temperature scoping, solvent optimization, and separations.« less

Development of the swathe-felling mobile chipper

Treesearch

P. Koch; T.E. Savage

1980-01-01

A harvesting machine and auxilary equipment are being developed to recover logging residues us chips for fuel and fiber, and to deliver these chips to mills at ubout $18 per green ton including 30 percent pre-tax profit on the equipment investment. The harvester, a 575 horsepower trucked mobile chipper equipped with a front-mounted felling bar, wus field-tested on red...

Systems Librarian and Automation Review.

ERIC Educational Resources Information Center

Schuyler, Michael

1992-01-01

Discusses software sharing on computer networks and the need for proper bandwidth; and describes the technology behind FidoNet, a computer network made up of electronic bulletin boards. Network features highlighted include front-end mailers, Zone Mail Hour, Nodelist, NetMail, EchoMail, computer conferences, tosser and scanner programs, and host…

End-Users, Front Ends and Librarians.

ERIC Educational Resources Information Center

Bourne, Donna E.

1989-01-01

The increase in end-user searching, the advantages and limitations of front ends, and the role of the librarian in end-user searching are discussed. It is argued that librarians need to recognize that front ends can be of benefit to themselves and patrons, and to assume the role of advisors and educators for end-users. (37 references) (CLB)

An automatic chip structure optical inspection system for electronic components

NASA Astrophysics Data System (ADS)

Song, Zhichao; Xue, Bindang; Liang, Jiyuan; Wang, Ke; Chen, Junzhang; Liu, Yunhe

2018-01-01

An automatic chip structure inspection system based on machine vision is presented to ensure the reliability of electronic components. It consists of four major modules, including a metallographic microscope, a Gigabit Ethernet high-resolution camera, a control system and a high performance computer. An auto-focusing technique is presented to solve the problem that the chip surface is not on the same focusing surface under the high magnification of the microscope. A panoramic high-resolution image stitching algorithm is adopted to deal with the contradiction between resolution and field of view, caused by different sizes of electronic components. In addition, we establish a database to storage and callback appropriate parameters to ensure the consistency of chip images of electronic components with the same model. We use image change detection technology to realize the detection of chip images of electronic components. The system can achieve high-resolution imaging for chips of electronic components with various sizes, and clearly imaging for the surface of chip with different horizontal and standardized imaging for ones with the same model, and can recognize chip defects.

An asynchronous data-driven readout prototype for CEPC vertex detector

NASA Astrophysics Data System (ADS)

Yang, Ping; Sun, Xiangming; Huang, Guangming; Xiao, Le; Gao, Chaosong; Huang, Xing; Zhou, Wei; Ren, Weiping; Li, Yashu; Liu, Jianchao; You, Bihui; Zhang, Li

2017-12-01

The Circular Electron Positron Collider (CEPC) is proposed as a Higgs boson and/or Z boson factory for high-precision measurements on the Higgs boson. The precision of secondary vertex impact parameter plays an important role in such measurements which typically rely on flavor-tagging. Thus silicon CMOS Pixel Sensors (CPS) are the most promising technology candidate for a CEPC vertex detector, which can most likely feature a high position resolution, a low power consumption and a fast readout simultaneously. For the R&D of the CEPC vertex detector, we have developed a prototype MIC4 in the Towerjazz 180 nm CMOS Image Sensor (CIS) process. We have proposed and implemented a new architecture of asynchronous zero-suppression data-driven readout inside the matrix combined with a binary front-end inside the pixel. The matrix contains 128 rows and 64 columns with a small pixel pitch of 25 μm. The readout architecture has implemented the traditional OR-gate chain inside a super pixel combined with a priority arbiter tree between the super pixels, only reading out relevant pixels. The MIC4 architecture will be introduced in more detail in this paper. It will be taped out in May and will be characterized when the chip comes back.

A semi-implantable multichannel telemetry system for continuous electrical, mechanical and hemodynamical recordings in animal cardiac research.

PubMed

Kong, Wei; Huang, Jian; Rollins, Dennis L; Ideker, Raymond E; Smith, William M

2007-03-01

We have developed an eight-channel telemetry system for studying experimental models of chronic cardiovascular disease. The system is an extension of a previous device that has been miniaturized, reduced in power consumption and provided with increased functionality. We added sensors for ventricular dimension, and coronary artery blood flow and arterial blood pressure that are suitable for use with the system. The telemetry system consists of a front end, a backpack and a host PC. The front end is a watertight stainless steel case with all sensor electronics sealed inside; it acquires dimension, flow, pressure and five cardiac electrograms from selected locations on the heart. The backpack includes a control unit, Bluetooth radio, and batteries. The control unit digitizes eight channels of data from the front end and forwards them to the host PC via Bluetooth link. The host PC has a receiving Bluetooth radio and Labview programs to store and display data. The whole system was successfully tested on the bench and in an animal model. This telemetry system will greatly enhance the ability to study events leading to spontaneous sudden cardiac arrest.

Ultra-fast high-resolution hybrid and monolithic CMOS imagers in multi-frame radiography

NASA Astrophysics Data System (ADS)

Kwiatkowski, Kris; Douence, Vincent; Bai, Yibin; Nedrow, Paul; Mariam, Fesseha; Merrill, Frank; Morris, Christopher L.; Saunders, Andy

2014-09-01

A new burst-mode, 10-frame, hybrid Si-sensor/CMOS-ROIC FPA chip has been recently fabricated at Teledyne Imaging Sensors. The intended primary use of the sensor is in the multi-frame 800 MeV proton radiography at LANL. The basic part of the hybrid is a large (48×49 mm2) stitched CMOS chip of 1100×1100 pixel count, with a minimum shutter speed of 50 ns. The performance parameters of this chip are compared to the first generation 3-frame 0.5-Mpixel custom hybrid imager. The 3-frame cameras have been in continuous use for many years, in a variety of static and dynamic experiments at LANSCE. The cameras can operate with a per-frame adjustable integration time of ~ 120ns-to- 1s, and inter-frame time of 250ns to 2s. Given the 80 ms total readout time, the original and the new imagers can be externally synchronized to 0.1-to-5 Hz, 50-ns wide proton beam pulses, and record up to ~1000-frame radiographic movies typ. of 3-to-30 minute duration. The performance of the global electronic shutter is discussed and compared to that of a high-resolution commercial front-illuminated monolithic CMOS imager.

Self-assembly of microscopic chiplets at a liquid–liquid–solid interface forming a flexible segmented monocrystalline solar cell

PubMed Central

Knuesel, Robert J.; Jacobs, Heiko O.

2010-01-01

This paper introduces a method for self-assembling and electrically connecting small (20–60 micrometer) semiconductor chiplets at predetermined locations on flexible substrates with high speed (62500 chips/45 s), accuracy (0.9 micrometer, 0.14°), and yield (> 98%). The process takes place at the triple interface between silicone oil, water, and a penetrating solder-patterned substrate. The assembly is driven by a stepwise reduction of interfacial free energy where chips are first collected and preoriented at an oil-water interface before they assemble on a solder-patterned substrate that is pulled through the interface. Patterned transfer occurs in a progressing linear front as the liquid layers recede. The process eliminates the dependency on gravity and sedimentation of prior methods, thereby extending the minimal chip size to the sub-100 micrometer scale. It provides a new route for the field of printable electronics to enable the integration of microscopic high performance inorganic semiconductors on foreign substrates with the freedom to choose target location, pitch, and integration density. As an example we demonstrate a fault-tolerant segmented flexible monocrystalline silicon solar cell, reducing the amount of Si that is used when compared to conventional rigid cells. PMID:20080682

Wavefront image sensor chip

PubMed Central

Cui, Xiquan; Ren, Jian; Tearney, Guillermo J.; Yang, Changhuei

2010-01-01

We report the implementation of an image sensor chip, termed wavefront image sensor chip (WIS), that can measure both intensity/amplitude and phase front variations of a light wave separately and quantitatively. By monitoring the tightly confined transmitted light spots through a circular aperture grid in a high Fresnel number regime, we can measure both intensity and phase front variations with a high sampling density (11 µm) and high sensitivity (the sensitivity of normalized phase gradient measurement is 0.1 mrad under the typical working condition). By using WIS in a standard microscope, we can collect both bright-field (transmitted light intensity) and normalized phase gradient images. Our experiments further demonstrate that the normalized phase gradient images of polystyrene microspheres, unstained and stained starfish embryos, and strongly birefringent potato starch granules are improved versions of their corresponding differential interference contrast (DIC) microscope images in that they are artifact-free and quantitative. Besides phase microscopy, WIS can benefit machine recognition, object ranging, and texture assessment for a variety of applications. PMID:20721059

IMOTEPAD: A mixed-signal 64-channel front-end ASIC for small-animal PET imaging

NASA Astrophysics Data System (ADS)

Fang, Xiaochao; Ollivier-Henry, Nicolas; Gao, Wu; Hu-Guo, Christine; Colledani, Claude; Humbert, Bernard; Brasse, David; Hu, Yann

2011-04-01

This paper presents the design and characteristics of a mixed-signal 64-channel front-end readout ASIC called IMOTEPAD dedicated to multi-channel plate (MCP) photodetector coupled to LYSO scintillating crystals for small-animal PET imaging. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. As a result, both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. This dedicated ASIC IMOTEPAD comprises two parts: the analog part IMOTEPA and the digital part IMOTEPD. The IMOTEPA is dedicated to energy measurement. And the timing information is digitized by the IMOTEPD in which the key principal element is a time-to-digital converter (TDC) based on a delay-locked loop (DLL) with 32 delay cells. The chip is designed and fabricated in 0.35 μm CMOS process. The measurements show that for the analog part IMOTEPA, the energy gain is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The SNR is 39 dB and the RMS noise is 300 μV. The nonlinearity is less than 3%. The crosstalk is less than 0.2%. For the IMOTEPD, the bin size of the TDC is 625 ps with a reference clock of 50 MHz. The RMS jitter of the DLL is less than 42 ps. The DNL of the TDC is equal to about 0.17 LSB and the INL is equal to 0.31 LSB. The power dissipation of each channel is less than 16.8 mW. The design of the ASIC, especially for TDC and the measurement results of the IMOTEPAD will be presented and discussed in this paper.

Performances of the Front-End Electronics for the HADES RPC TOF wall on a 12C beam

NASA Astrophysics Data System (ADS)

Belver, D.; Cabanelas, P.; Castro, E.; Díaz, J.; Garzón, J. A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M.; Zapata, M.

2009-05-01

A Front-End Electronics (FEE) chain for timing accurate measurements has been developed for the RPC wall upgrade of the High-Acceptance DiElectron Spectrometer (HADES). The wall will cover an area of around 8 m with 1122 RPC cells (2244 electronic channels). The FEE chain consists of two boards: a four-channel DaughterBOard (DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a discriminator. The time and the charge information are encoded in the leading and the trailing edge (by a charge to width method) of an LVDS signal. Each MBO houses up to eight DBOs providing them regulated voltage supply, threshold values via DACs, test signals and collection of their trigger outputs. The MBO delivers LVDS signals to a time-to-digital converter readout board (TRB) based on HPTDC for data acquisition. In this work, we present the performance of the FEE measured using: (a) narrow electronic test pulses and (b) real signals read out in a fully instrumented RPC sextant installed in its final position at the HADES. The detector was exposed to particles coming from reactions of a 12C beam on Be and Nb targets at 2 GeV/A kinetic energy. Results for the whole electronic chain (DBO+MBO+TRB) show a timing jitter of around 40 ps/channel for pulses above 100 fC and 80 ps/channel for beam data taken with the RPC.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the first six months of this project were to lay the foundations for both the SiC front-end optical chip fabrication as well as the free-space laser beam interferometer designs and preliminary tests. In addition, a Phase I goal was to design and experimentally build the high temperature and pressure infrastructure and test systems that will be used in the next 6 months for proposed sensor experimentation and data processing. All these goals have been achieved and are described in detail in the report. Both design process and diagrams for the mechanical elements as well as the opticalmore » systems are provided. In addition, photographs of the fabricated SiC optical chips, the high temperature & pressure test chamber instrument, the optical interferometer, the SiC sample chip holder, and signal processing data are provided. The design and experimentation results are summarized to give positive conclusions on the proposed novel high temperature optical sensor technology. The goals of the second six months of this project were to conduct high temperature sensing tests using the test chamber and optical sensing instrument designs developed in the first part of the project. In addition, a Phase I goal was to develop the basic processing theory and physics for the proposed first sensor experimentation and data processing. All these goals have been achieved and are described in detail. Both optical experimental design process and sensed temperature are provided. In addition, photographs of the fabricated SiC optical chips after deployment in the high temperature test chamber are shown from a material study point-of-view.« less

High Frequency Design Considerations for the Large Detector Number and Small Form Factor Dual Electron Spectrometer of the Fast Plasma Investigation on NASA's Magnetospheric Multiscale Mission

NASA Technical Reports Server (NTRS)

Kujawski, Joseph T.; Gliese, Ulrik B.; Cao, N. T.; Zeuch, M. A.; White, D.; Chornay, D. J; Lobell, J. V.; Avanov, L. A.; Barrie, A. C.; Mariano, A. J.;

Characterization of pixel sensor designed in 180 nm SOI CMOS technology

NASA Astrophysics Data System (ADS)

Benka, T.; Havranek, M.; Hejtmanek, M.; Jakovenko, J.; Janoska, Z.; Marcisovska, M.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Vrba, V.

2018-01-01

A new type of X-ray imaging Monolithic Active Pixel Sensor (MAPS), X-CHIP-02, was developed using a 180 nm deep submicron Silicon On Insulator (SOI) CMOS commercial technology. Two pixel matrices were integrated into the prototype chip, which differ by the pixel pitch of 50 μm and 100 μm. The X-CHIP-02 contains several test structures, which are useful for characterization of individual blocks. The sensitive part of the pixel integrated in the handle wafer is one of the key structures designed for testing. The purpose of this structure is to determine the capacitance of the sensitive part (diode in the MAPS pixel). The measured capacitance is 2.9 fF for 50 μm pixel pitch and 4.8 fF for 100 μm pixel pitch at -100 V (default operational voltage). This structure was used to measure the IV characteristics of the sensitive diode. In this work, we report on a circuit designed for precise determination of sensor capacitance and IV characteristics of both pixel types with respect to X-ray irradiation. The motivation for measurement of the sensor capacitance was its importance for the design of front-end amplifier circuits. The design of pixel elements, as well as circuit simulation and laboratory measurement techniques are described. The experimental results are of great importance for further development of MAPS sensors in this technology.

Design and construction of a prototype ACTS propagation terminal

NASA Technical Reports Server (NTRS)

Stutzman, Warren; Pratt, Tim; Nunnally, Charles; Nealy, Randall; Remaklus, Will; Sylvester, Bill; Predoehl, Andrew; Gaff, Doug

1993-01-01

The launch schedule for the Advanced Communication Technology Satellite (ACTS) spacecraft did not leave sufficient time for completion of the prototype ACTS Propagation Terminals (APT) prior to initiation of the APT production phase. In fact, the approach used was to construct and test all subassemblies of the terminal with special emphasis on the technically challenging portions. These include the RF front end that uses a state-of-the-art down converter which integrates a low noise amplifier, mixer, post amplifier, filter, and local oscillator port frequency doubler into a single small package. In addition, a new digital receiver that uses the latest DSP technology was developed. Both of these subassemblies were thoroughly tested. The highest risk technology in the APT program was the digital receiver. Several candidate algorithms and DSP chips were investigated early on, primarily under JPL sponsorship. A receiver was constructed based on Texas Instruments chip. The final prototype digital receiver was one based on an Analog Devices chip. The design and test results are documented in a report prepared for this grant. A Primary Design Review (PDR) was conducted 30 May 1991, and a Critical Design Review was held 7 Jul. 1992. Final complete documentation of the APT's will appear in the form of three reports: a hardware description report, a report on the data collection code (ACTS VIEW), and a report on the preprocessing code.

An acoustic charge transport imager for high definition television applications

NASA Technical Reports Server (NTRS)

Hunt, W. D.; Brennan, K. F.; Summers, C. J.

1994-01-01

The primary goal of this research is to develop a solid-state television (HDTV) imager chip operating at a frame rate of about 170 frames/sec at 2 Megapixels/frame. This imager will offer an order of magnitude improvements in speed over CCD designs and will allow for monolithic imagers operating from the IR to UV. The technical approach of the project focuses on the development of the three basic components of the imager and their subsequent integration. The camera chip can be divided into three distinct functions: (1) image capture via an array of avalanche photodiodes (APD's); (2) charge collection, storage, and overflow control via a charge transfer transistor device (CTD); and (3) charge readout via an array of acoustic charge transport (ACT) channels. The use of APD's allows for front end gain at low noise and low operating voltages while the ACT readout enables concomitant high speed and high charge transfer efficiency. Currently work is progressing towards the optimization of each of these component devices. In addition to the development of each of the three distinct components, work towards their integration and manufacturability is also progressing. The component designs are considered not only to meet individual specifications but to provide overall system level performance suitable for HDTV operation upon integration. The ultimate manufacturability and reliability of the chip constrains the design as well. The progress made during this period is described in detail.

Status of the photomultiplier-based FlashCam camera for the Cherenkov Telescope Array

NASA Astrophysics Data System (ADS)

Pühlhofer, G.; Bauer, C.; Eisenkolb, F.; Florin, D.; Föhr, C.; Gadola, A.; Garrecht, F.; Hermann, G.; Jung, I.; Kalekin, O.; Kalkuhl, C.; Kasperek, J.; Kihm, T.; Koziol, J.; Lahmann, R.; Manalaysay, A.; Marszalek, A.; Rajda, P. J.; Reimer, O.; Romaszkan, W.; Rupinski, M.; Schanz, T.; Schwab, T.; Steiner, S.; Straumann, U.; Tenzer, C.; Vollhardt, A.; Weitzel, Q.; Winiarski, K.; Zietara, K.

2014-07-01

The FlashCam project is preparing a camera prototype around a fully digital FADC-based readout system, for the medium sized telescopes (MST) of the Cherenkov Telescope Array (CTA). The FlashCam design is the first fully digital readout system for Cherenkov cameras, based on commercial FADCs and FPGAs as key components for digitization and triggering, and a high performance camera server as back end. It provides the option to easily implement different types of trigger algorithms as well as digitization and readout scenarios using identical hardware, by simply changing the firmware on the FPGAs. The readout of the front end modules into the camera server is Ethernet-based using standard Ethernet switches and a custom, raw Ethernet protocol. In the current implementation of the system, data transfer and back end processing rates of 3.8 GB/s and 2.4 GB/s have been achieved, respectively. Together with the dead-time-free front end event buffering on the FPGAs, this permits the cameras to operate at trigger rates of up to several ten kHz. In the horizontal architecture of FlashCam, the photon detector plane (PDP), consisting of photon detectors, preamplifiers, high voltage-, control-, and monitoring systems, is a self-contained unit, mechanically detached from the front end modules. It interfaces to the digital readout system via analogue signal transmission. The horizontal integration of FlashCam is expected not only to be more cost efficient, it also allows PDPs with different types of photon detectors to be adapted to the FlashCam readout system. By now, a 144-pixel mini-camera" setup, fully equipped with photomultipliers, PDP electronics, and digitization/ trigger electronics, has been realized and extensively tested. Preparations for a full-scale, 1764 pixel camera mechanics and a cooling system are ongoing. The paper describes the status of the project.

Fully Integrated Passive UHF RFID Tag for Hash-Based Mutual Authentication Protocol

PubMed Central

Mikami, Shugo; Watanabe, Dai; Li, Yang; Sakiyama, Kazuo

2015-01-01

Passive radio-frequency identification (RFID) tag has been used in many applications. While the RFID market is expected to grow, concerns about security and privacy of the RFID tag should be overcome for the future use. To overcome these issues, privacy-preserving authentication protocols based on cryptographic algorithms have been designed. However, to the best of our knowledge, evaluation of the whole tag, which includes an antenna, an analog front end, and a digital processing block, that runs authentication protocols has not been studied. In this paper, we present an implementation and evaluation of a fully integrated passive UHF RFID tag that runs a privacy-preserving mutual authentication protocol based on a hash function. We design a single chip including the analog front end and the digital processing block. We select a lightweight hash function supporting 80-bit security strength and a standard hash function supporting 128-bit security strength. We show that when the lightweight hash function is used, the tag completes the protocol with a reader-tag distance of 10 cm. Similarly, when the standard hash function is used, the tag completes the protocol with the distance of 8.5 cm. We discuss the impact of the peak power consumption of the tag on the distance of the tag due to the hash function. PMID:26491714

A Wearable EEG-HEG-HRV Multimodal System With Simultaneous Monitoring of tES for Mental Health Management.

PubMed

Ha, Unsoo; Lee, Yongsu; Kim, Hyunki; Roh, Taehwan; Bae, Joonsung; Kim, Changhyeon; Yoo, Hoi-Jun

2015-12-01

A multimodal mental management system in the shape of the wearable headband and earplugs is proposed to monitor electroencephalography (EEG), hemoencephalography (HEG) and heart rate variability (HRV) for accurate mental health monitoring. It enables simultaneous transcranial electrical stimulation (tES) together with real-time monitoring. The total weight of the proposed system is less than 200 g. The multi-loop low-noise amplifier (MLLNA) achieves over 130 dB CMRR for EEG sensing and the capacitive correlated-double sampling transimpedance amplifier (CCTIA) has low-noise characteristics for HEG and HRV sensing. Measured three-physiology domains such as neural, vascular and autonomic domain signals are combined with canonical correlation analysis (CCA) and temporal kernel canonical correlation analysis (tkCCA) algorithm to find the neural-vascular-autonomic coupling. It supports highly accurate classification with the 19% maximum improvement with multimodal monitoring. For the multi-channel stimulation functionality, after-effects maximization monitoring and sympathetic nerve disorder monitoring, the stimulator is designed as reconfigurable. The 3.37 × 2.25 mm(2) chip has 2-channel EEG sensor front-end, 2-channel NIRS sensor front-end, NIRS current driver to drive dual-wavelength VCSEL and 6-b DAC current source for tES mode. It dissipates 24 mW with 2 mA stimulation current and 5 mA NIRS driver current.

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

NASA Astrophysics Data System (ADS)

Bartelink, Dirk J.

1998-11-01

The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must recognize—test is also performed using IC's. A system interconnection is proposed using multiple chips fabricated with conventional silicon processes, including MEMS technology. The system resembles an MCM that can be joined without committing to final assembly to perform at-speed testing. 50-Ohm test probes never load the circuit; only intended neighboring chips are ever connected. A `back-plane' chip provides the connection layers for both inter- and intra-chip signals and also serves as the probe card, in analogy with membrane probes now used for single-chip testing. Intra-chip connections, which require complicated connections during test that exactly match the product, are then properly made and all waveforms and loading conditions under test will be identical to those of the product. The major benefit is that all front-end chip technologies can be merged—logic, memory, RF, even passives. ESD protection is required only on external system connections. Manufacturing test information will accurately characterize process faults and thus avoid the Known-Good-Die problem that has slowed the arrival of conventional MCM's.

A compact, low-loss, tunable phase shifter on defect mitigated dielectrics up to 40 GHz

NASA Astrophysics Data System (ADS)

Orloff, Nathan; Long, Christian; Lu, Xifeng; Nair, Hari; Dawley, Natalie; Schlom, Darrell; Booth, James

With the emergence of the internet-of-things and increased connectivity of modern commerce, consumers have driven demand for wireless spectrum beyond current capacity and infrastructure capabilities. One way the telecommunications industry is addressing this problem is by pushing front-end electronics to higher frequencies, introducing carrier aggregation schemes, and developing spectrum-sharing techniques. Some of these solutions require frequency agile components that are vastly different from what is in today's marketplace. Perhaps the most basic and ubiquitous component in front-end electronics is the phase shifter. Phase shifters are particularly important for compact beam-forming antennas that may soon appear in commercial technology. Here, we demonstrate a compact, tunable phase shifter with very low insertion loss up to 40 GHz on a defect mitigated tunable dielectric. We demonstrate performance compared to barium-doped strontium titanate phase shifters. Such phase shifters could potentially meet the stringent size and performance characteristics demanded by telecommunications industry, readily facilitating massive multiple-input multiple-output antennas in the next-generation of mobile handsets.

Gauss-Seidel Iterative Method as a Real-Time Pile-Up Solver of Scintillation Pulses

NASA Astrophysics Data System (ADS)

Novak, Roman; Vencelj, Matja¿

2009-12-01

The pile-up rejection in nuclear spectroscopy has been confronted recently by several pile-up correction schemes that compensate for distortions of the signal and subsequent energy spectra artifacts as the counting rate increases. We study here a real-time capability of the event-by-event correction method, which at the core translates to solving many sets of linear equations. Tight time limits and constrained front-end electronics resources make well-known direct solvers inappropriate. We propose a novel approach based on the Gauss-Seidel iterative method, which turns out to be a stable and cost-efficient solution to improve spectroscopic resolution in the front-end electronics. We show the method convergence properties for a class of matrices that emerge in calorimetric processing of scintillation detector signals and demonstrate the ability of the method to support the relevant resolutions. The sole iteration-based error component can be brought below the sliding window induced errors in a reasonable number of iteration steps, thus allowing real-time operation. An area-efficient hardware implementation is proposed that fully utilizes the method's inherent parallelism.

Front End Software for Online Database Searching. Part 2: The Marketplace.

ERIC Educational Resources Information Center

Levy, Louise R.; Hawkins, Donald T.

1986-01-01

This article analyzes the front end software marketplace and discusses some of the complex forces influencing it. Discussion covers intermediary market; end users (library customers, scientific and technical professionals, corporate business specialists, consumers); marketing strategies; a British front end development firm; competitive pressures;…

EARS: Electronic Access to Reference Service.

PubMed Central

Weise, F O; Borgendale, M

1986-01-01

Electronic Access to Reference Service (EARS) is a front end to the Health Sciences Library's electronic mail system, with links to the online public catalog. EARS, which became operational in September 1984, is accessed by users at remote sites with either a terminal or microcomputer. It is menu-driven, allowing users to request: a computerized literature search, reference information, a photocopy of a journal article, or a book. This paper traces the history of EARS and discusses its use, its impact on library staff and services, and factors that influence the diffusion of new technology. PMID:3779167

EARS: Electronic Access to Reference Service.

PubMed

Weise, F O; Borgendale, M

1986-10-01

Electronic Access to Reference Service (EARS) is a front end to the Health Sciences Library's electronic mail system, with links to the online public catalog. EARS, which became operational in September 1984, is accessed by users at remote sites with either a terminal or microcomputer. It is menu-driven, allowing users to request: a computerized literature search, reference information, a photocopy of a journal article, or a book. This paper traces the history of EARS and discusses its use, its impact on library staff and services, and factors that influence the diffusion of new technology.

Electromigration and thermomigration in lead-free tin-silver-copper and eutectic tin-lead flip chip solder joints

NASA Astrophysics Data System (ADS)

Ou Yang, Fan-Yi

Phase separation and microstructure change of eutectic SnPb and SnAgCu flip chip solder joint were investigated under thermomigration, electromigration, stressmigration and the combination of these effects. Different morphological behaviors under DC and AC electromigration were seen. Phase separation with Pb rich phase migration to the anode was observed when current density is below 1.6 x 104 A/cm2 at 100°C. For some cases, phase separation of Pb-rich phase and Su-rich phase as well as refinement of lamellar microstructure has also been observed. We propose that the refinement is due to recrystallization. On the other hand, time-dependent melting of eutectic SnPb flip chip solder joints has been observed to occur frequently with current density above 1.6 x 104 A/cm 2at 100°C. It has been found that it is due to joule heating of the on-chip Al interconnects. We found that electromigration has especially generated voids at the anode of the Al. This damage has greatly increased the resistance of the Al, which produces the heat needed to melt the solder joint. Owing to the line-to-bump configuration in flip chip solder joints, current crowding occurs when electrons enters into or exits from the solder bump. At the cathode contact, current crowding induced pancake-type void formation was observed widely. Furthermore, at the anode contact, we note that hillock or whisker forms. The cross-sectioned surface in SnPb showed dimple and bulge after electromigration, while that of SnAgCu remained flat. The difference is due to a larger back stress in the SnAgCu, consequently electromigration in SnAgCu is slower than that in SnPb. For thermomigration in eutectic SnPb flip chip solder joints, phase separation of Sn and Pb occurred, with Pb moving to the cold end. Both Sn and Pb have a stepwise concentration profile across solder bump. Refinement of lamellar microstructure was observed, indicating recrystallization. Also, thermomigration in eutectic SnAgCu flip chip solder joint were presented. It seems that vacancy flux plays a dominant role in thermomigration in Pb-free solder bumps; voids formed on the cold end and Sn moved to the hot end.

The Mobile Internet -The Next Big Thing. Electrons & Photons: You Need Both! (BRIEFING CHARTS)

DTIC Science & Technology

2007-03-05

Links Network Centric Warfighting Comms Wired & Wireless Links 20th Century 21th Century The Military Comms Problem Network Centric Operationst t i ti...Small Unit Operations TEL Underwater Vehicles & Towed Arrays RC-135V Rivet Joint Tier II+ UAV Global Hawk E-2C Hawkeye Networked Manned and Unmanned...RF Front-End Solutions ● >20 DARPA/MTO RF Programs across the spectrum - RF & Mixed Signal Electronics - Analog & Digital Photonics Enables Network

The curse of invertase

USDA-ARS?s Scientific Manuscript database

Among the greatest quality concerns for chip and fry processing potato tubers are cold-induced sweetening, sugar end defects, translucent ends, stem-end chip defect and high acrylamide-forming potential. These problems all result from elevated amounts of glucose and fructose, reducing sugars produce...

Observational evidence for thermal wave fronts in solar flares

NASA Technical Reports Server (NTRS)

Rust, D. M.; Simnett, G. M.; Smith, D. F.

1985-01-01

Images in 3.5-30 keV X-rays obtained during the first few minutes of seven solar flares show rapid motions. In each case X-ray emission first appeared at one end of a magnetic field structure, and then propagated along the field at a velocity between 800 and 1700 km/s. The observed X-ray structures were 45,000-230,000 km long. Simultaneous H-alpha images were available in three cases; they showed brightenings when the fast-moving fronts arrived at the chromosphere. The fast-moving fronts are interpreted as electron thermal conduction fronts since their velocities are consistent with conduction at the observed temperatures of 1-3 x 10 to the 7th K. The inferred conductive heat flux of up to 10-billion ergs/s sq cm accounts for most of the energy released in the flares, implying that the flares were primarily thermal phenomena.

Recent advances in the front-end sources of the LMJ fusion laser

NASA Astrophysics Data System (ADS)

Gleyze, Jean-François; Hares, Jonathan; Vidal, Sebastien; Beck, Nicolas; Dubertrand, Jerome; Perrin, Arnaud

2011-03-01

LMJ is typical of lasers used for inertial confinement fusion and requires a laser of programmable parameters for injection into the main amplifier. For several years, the CEA has developed front end fiber sources, based on telecommunications fiber optics technologies. These sources meet the needs but as the technology evolves we can expect improved efficiency and reductions in size and cost. We give an up-to-date description of some present development issues, particularly in the field of temporal shaping with the use of digital system. The synchronization of such electronics has been challenging however we now obtain system jitter of less then 7ps rms. Secondly, we will present recent advance in the use of fiber based pre-comp system to avoid parasitic amplitude modulation from phase modulation used for spectral broadening.

Performance of a resistive plate chamber equipped with a new prototype of amplified front-end electronics in the ALICE detector

NASA Astrophysics Data System (ADS)

Marchisone, Massimiliano

2017-09-01

ALICE is the LHC experiment dedicated to the study of heavy-ion collisions. At forward rapidity a muon spectrometer detects muons from low mass mesons, quarkonia (c\\bar{c} and b\\bar{b} mesons), open heavy-flavor hadrons (D and B mesons) as well as from weak bosons. A muon selection based on transverse momentum is made by a trigger system composed of 72 Resistive Plate Chambers (RPCs). For the LHC Run 1 and the ongoing Run 2 the RPCs have been equipped with a non-amplified Front-End Electronics (FEE) called ADULT. However, in view of an increase in luminosity expected for Run 3 (foreseen to start in 2021) the possibility to use an amplified FEE has been explored in order to improve the counting rate limitation and to prevent the aging of the detector by reducing the charge per hit. A prototype of this new electronics (FEERIC) has been developed and tested first with cosmic rays before equipping one RPC in the ALICE cavern with it. In this proceeding the most important performance indicators (such as efficiency, dark current, dark rate, cluster size, total charge and charge per hit) of the RPC equipped with this new FEE will be reviewed and compared to the others read out with ADULT.

Charge-sensitive front-end electronics with operational amplifiers for CdZnTe detectors

NASA Astrophysics Data System (ADS)

Födisch, P.; Berthel, M.; Lange, B.; Kirschke, T.; Enghardt, W.; Kaever, P.

2016-09-01

Cadmium zinc telluride (CdZnTe, CZT) radiation detectors are suitable for a variety of applications, due to their high spatial resolution and spectroscopic energy performance at room temperature. However, state-of-the-art detector systems require high-performance readout electronics. Though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, requirements of high dynamic range and high throughput are not available in any commercial circuit. Consequently, the present study develops the analog front-end electronics with operational amplifiers for an 8×8 pixelated CZT detector. For this purpose, we modeled an electrical equivalent circuit of the CZT detector with the associated charge-sensitive amplifier (CSA). Based on a detailed network analysis, the circuit design is completed by numerical values for various features such as ballistic deficit, charge-to-voltage gain, rise time, and noise level. A verification of the performance is carried out by synthetic detector signals and a pixel detector. The experimental results with the pixel detector assembly and a 22Na radioactive source emphasize the depth dependence of the measured energy. After pulse processing with depth correction based on the fit of the weighting potential, the energy resolution is 2.2% (FWHM) for the 511 keV photopeak.

A Wearable Healthcare System With a 13.7 μA Noise Tolerant ECG Processor.

PubMed

Izumi, Shintaro; Yamashita, Ken; Nakano, Masanao; Kawaguchi, Hiroshi; Kimura, Hiromitsu; Marumoto, Kyoji; Fuchikami, Takaaki; Fujimori, Yoshikazu; Nakajima, Hiroshi; Shiga, Toshikazu; Yoshimoto, Masahiko

2015-10-01

To prevent lifestyle diseases, wearable bio-signal monitoring systems for daily life monitoring have attracted attention. Wearable systems have strict size and weight constraints, which impose significant limitations of the battery capacity and the signal-to-noise ratio of bio-signals. This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application.

Reconfigurable Multiparameter Biosignal Acquisition SoC for Low Power Wearable Platform

PubMed Central

Kim, Jongpal; Ko, Hyoungho

2016-01-01

A low power and low noise reconfigurable analog front-end (AFE) system on a chip (SoC) for biosignal acquisition is presented. The presented AFE can be reconfigured for use in electropotential, bioimpedance, electrochemical, and photoelectrical modes. The advanced healthcare services based on multiparameter physiological biosignals can be easily implemented with these multimodal and highly reconfigurable features of the proposed system. The reconfigurable gain and input referred noise of the core instrumentation amplifier block are 25 dB to 52 dB, and 1 μVRMS, respectively. The power consumption of the analog blocks in one readout channel is less than 52 μW. The reconfigurable capability among various modes of applications including electrocardiogram, blood glucose concentration, respiration, and photoplethysmography are shown experimentally. PMID:27898004

Numerical investigation of thermal performance of a water-cooled mini-channel heat sink for different chip arrangement

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tikadar, Amitav, E-mail: amitav453@gmail.com; Hossain, Md. Mahamudul; Morshed, A. K. M. M.

Heat transfer from electronic chip is always challenging and very crucial for electronic industry. Electronic chips are assembled in various manners according to the design conditions and limitationsand thus the influence of chip assembly on the overall thermal performance needs to be understand for the efficient design of electronic cooling system. Due to shrinkage of the dimension of channel and continuous increment of thermal load, conventional heat extraction techniques sometimes become inadequate. Due to high surface area to volume ratio, mini-channel have the natural advantage to enhance convective heat transfer and thus to play a vital role in the advancedmore » heat transfer devices with limited surface area and high heat flux. In this paper, a water cooled mini-channel heat sink was considered for electronic chip cooling and five different chip arrangements were designed and studied, namely: the diagonal arrangement, parallel arrangement, stacked arrangement, longitudinal arrangement and sandwiched arrangement. Temperature distribution on the chip surfaces was presented and the thermal performance of the heat sink in terms of overall thermal resistance was also compared. It is found that the sandwiched arrangement of chip provides better thermal performance compared to conventional in line chip arrangement.« less

The Design, Fabrication and Characterization of a Transparent Atom Chip

PubMed Central

Chuang, Ho-Chiao; Huang, Chia-Shiuan; Chen, Hung-Pin; Huang, Chi-Sheng; Lin, Yu-Hsin

2014-01-01

This study describes the design and fabrication of transparent atom chips for atomic physics experiments. A fabrication process was developed to define the wire patterns on a transparent glass substrate to create the desired magnetic field for atom trapping experiments. An area on the chip was reserved for the optical access, so that the laser light can penetrate directly through the glass substrate for the laser cooling process. Furthermore, since the thermal conductivity of the glass substrate is poorer than other common materials for atom chip substrate, for example silicon, silicon carbide, aluminum nitride. Thus, heat dissipation copper blocks are designed on the front and back of the glass substrate to improve the electrical current conduction. The testing results showed that a maximum burnout current of 2 A was measured from the wire pattern (with a width of 100 μm and a height of 20 μm) without any heat dissipation design and it can increase to 2.5 A with a heat dissipation design on the front side of the atom chips. Therefore, heat dissipation copper blocks were designed and fabricated on the back of the glass substrate just under the wire patterns which increases the maximum burnout current to 4.5 A. Moreover, a maximum burnout current of 6 A was achieved when the entire backside glass substrate was recessed and a thicker copper block was electroplated, which meets most requirements of atomic physics experiments. PMID:24922456

3-D readout-electronics packaging for high-bandwidth massively paralleled imager

DOEpatents

Kwiatkowski, Kris; Lyke, James

2007-12-18

Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a "mirror cube"). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a 45.degree. angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.

Single-chip microprocessor that communicates directly using light

NASA Astrophysics Data System (ADS)

Sun, Chen; Wade, Mark T.; Lee, Yunsup; Orcutt, Jason S.; Alloatti, Luca; Georgas, Michael S.; Waterman, Andrew S.; Shainline, Jeffrey M.; Avizienis, Rimas R.; Lin, Sen; Moss, Benjamin R.; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H.; Cook, Henry M.; Ou, Albert J.; Leu, Jonathan C.; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J.; Popović, Miloš A.; Stojanović, Vladimir M.

2015-12-01

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Single-chip microprocessor that communicates directly using light.

PubMed

Sun, Chen; Wade, Mark T; Lee, Yunsup; Orcutt, Jason S; Alloatti, Luca; Georgas, Michael S; Waterman, Andrew S; Shainline, Jeffrey M; Avizienis, Rimas R; Lin, Sen; Moss, Benjamin R; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H; Cook, Henry M; Ou, Albert J; Leu, Jonathan C; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J; Popović, Miloš A; Stojanović, Vladimir M

2015-12-24

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

On-chip integrated functional near infra-red spectroscopy (fNIRS) photoreceiver for portable brain imaging

NASA Astrophysics Data System (ADS)

Kamrani, Ehsan

Optical brain imaging using functional near infra-red spectroscopy (fNIRS) offers a direct and noninvasive tool for monitoring of blood oxygenation. fNIRS is a noninvasive, safe, minimally intrusive, and high temporal-resolution technique for real-time and long-term brain imaging. It allows detecting both fast-neuronal and slow-hemodynamic signals. Besides the significant advantages of fNIRS systems, they still suffer from few drawbacks including low spatial-resolution, moderately high-level noise and high-sensitivity to movement. In order to overcome the limitations of currently available non-portable fNIRS systems, we have introduced a new low-power, miniaturized on-chip photodetector front-end intended for portable fNIRS systems. It includes silicon avalanche photodiode (SiAPD), Transimpedance amplifier (TIA), and Quench- Reset circuitry implemented using standard CMOS technologies to operate in both linear and Geiger modes. So it can be applied for both continuous-wave fNIRS (CW-fNIRS) and also single-photon counting applications. Several SiAPDs have been implemented in novel structures and shapes (Rectangular, Octagonal, Dual, Nested, Netted, Quadratic and Hexadecagonal) using different premature edge breakdown prevention techniques. The main characteristics of the SiAPDs are validated and the impact of each parameter and the device simulators (TCAD, COMSOL, etc.) have been studied based on the simulation and measurement results. Proposed techniques exhibit SiAPDs with high avalanche-gain (up to 119), low breakdown-voltage (around 12V) and high photon-detection efficiency (up to 72% in NIR region) in additional to a low dark-count rate (down to 30Hz at 1V excess bias voltage). Three new high gain-bandwidth product (GBW) and low-noise TIAs are introduced and implemented based on distributed-gain concept, logarithmic-amplification and automatic noise-rejection and have been applied in linear-mode of operation. The implemented TIAs offer a power-consumption around 0.4 mW, transimpedance gain of 169 dBO, and input-output current/voltage noises in fA/pV range accompanied with ability to tune the gain, bandwidth and power-consumption in a wide range. The implemented mixed quench-reset circuit (MQC) and controllable MQC (CMQC) front-ends offer a quench-time of 10ns, a maximum power-consumption of 0.4 mW, with a controllable hold-off and reset-times. The on-chip integration of SiAPDs with TIA and photon-counting circuitries has been demonstrated showing improvement of the photodetection-efficiency, specially regarding to the sensitivity, power-consumption and signal-to-noise ratio (SNR) characteristics.

A configurable and low-power mixed signal SoC for portable ECG monitoring applications.

PubMed

Kim, Hyejung; Kim, Sunyoung; Van Helleputte, Nick; Artes, Antonio; Konijnenburg, Mario; Huisken, Jos; Van Hoof, Chris; Yazicioglu, Refet Firat

2014-04-01

This paper describes a mixed-signal ECG System-on-Chip (SoC) that is capable of implementing configurable functionality with low-power consumption for portable ECG monitoring applications. A low-voltage and high performance analog front-end extracts 3-channel ECG signals and single channel electrode-tissue-impedance (ETI) measurement with high signal quality. This can be used to evaluate the quality of the ECG measurement and to filter motion artifacts. A custom digital signal processor consisting of 4-way SIMD processor provides the configurability and advanced functionality like motion artifact removal and R peak detection. A built-in 12-bit analog-to-digital converter (ADC) is capable of adaptive sampling achieving a compression ratio of up to 7, and loop buffer integration reduces the power consumption for on-chip memory access. The SoC is implemented in 0.18 μm CMOS process and consumes 32 μ W from a 1.2 V while heart beat detection application is running, and integrated in a wireless ECG monitoring system with Bluetooth protocol. Thanks to the ECG SoC, the overall system power consumption can be reduced significantly.

A 0.7-V 17.4- μ W 3-lead wireless ECG SoC.

PubMed

Khayatzadeh, Mahmood; Zhang, Xiaoyang; Tan, Jun; Liew, Wen-Sin; Lian, Yong

2013-10-01

This paper presents a fully integrated sub-1 V 3-lead wireless ECG System-on-Chip (SoC) for wireless body sensor network applications. The SoC includes a two-channel ECG front-end with a driven-right-leg circuit, an 8-bit SAR ADC, a custom-designed 16-bit microcontroller, two banks of 16 kb SRAM, and a MICS band transceiver. The microcontroller and SRAM blocks are able to operate at sub-/near-threshold regime for the best energy consumption. The proposed SoC has been implemented in a standard 0.13- μ m CMOS process. Measurement results show the microcontroller consumes only 2.62 pJ per instruction at 0.35 V . Both microcontroller and memory blocks are functional down to 0.25 V. The entire SoC is capable of working at single 0.7-V supply. At the best case, it consumes 17.4 μ W in heart rate detection mode and 74.8 μW in raw data acquisition mode under sampling rate of 500 Hz. This makes it one of the best ECG SoCs among state-of-the-art biomedical chips.

Loran digital phase-locked loop and RF front-end system error analysis

NASA Technical Reports Server (NTRS)

Mccall, D. L.

1979-01-01

An analysis of the system performance of the digital phase locked loops (DPLL) and RF front end that are implemented in the MINI-L4 Loran receiver is presented. Three of the four experiments deal with the performance of the digital phase locked loops. The other experiment deals with the RF front end and DPLL system error which arise in the front end due to poor signal to noise ratios. The ability of the DPLLs to track the offsets is studied.

Navigating the Information Ocean: Charting the Course. Abstracts from the Academic Library Association of Ohio Annual Conference (Columbus, Ohio, November 4, 1994).

ERIC Educational Resources Information Center

Academic Library Association of Ohio.

Abstracts of 14 papers presented at the conference are provided here. Titles are: "Electronic Information Terraforming: Designing and Implementing a Front-end System Using World-Wide Web Technology" (Abbie Basile; And Others); "Characteristics of Generation X and Implications for Reference and Instructional Services" (Catherine…

Technology and design of an active-matrix OLED on crystalline silicon direct-view display for a wristwatch computer

NASA Astrophysics Data System (ADS)

Sanford, James L.; Schlig, Eugene S.; Prache, Olivier; Dove, Derek B.; Ali, Tariq A.; Howard, Webster E.

2002-02-01

The IBM Research Division and eMagin Corp. jointly have developed a low-power VGA direct view active matrix OLED display, fabricated on a crystalline silicon CMOS chip. The display is incorporated in IBM prototype wristwatch computers running the Linus operating system. IBM designed the silicon chip and eMagin developed the organic stack and performed the back-end-of line processing and packaging. Each pixel is driven by a constant current source controlled by a CMOS RAM cell, and the display receives its data from the processor memory bus. This paper describes the OLED technology and packaging, and outlines the design of the pixel and display electronics and the processor interface. Experimental results are presented.

Integrated circuits for volumetric ultrasound imaging with 2-D CMUT arrays.

PubMed

Bhuyan, Anshuman; Choe, Jung Woo; Lee, Byung Chul; Wygant, Ira O; Nikoozadeh, Amin; Oralkan, Ömer; Khuri-Yakub, Butrus T

2013-12-01

Real-time volumetric ultrasound imaging systems require transmit and receive circuitry to generate ultrasound beams and process received echo signals. The complexity of building such a system is high due to requirement of the front-end electronics needing to be very close to the transducer. A large number of elements also need to be interfaced to the back-end system and image processing of a large dataset could affect the imaging volume rate. In this work, we present a 3-D imaging system using capacitive micromachined ultrasonic transducer (CMUT) technology that addresses many of the challenges in building such a system. We demonstrate two approaches in integrating the transducer and the front-end electronics. The transducer is a 5-MHz CMUT array with an 8 mm × 8 mm aperture size. The aperture consists of 1024 elements (32 × 32) with an element pitch of 250 μm. An integrated circuit (IC) consists of a transmit beamformer and receive circuitry to improve the noise performance of the overall system. The assembly was interfaced with an FPGA and a back-end system (comprising of a data acquisition system and PC). The FPGA provided the digital I/O signals for the IC and the back-end system was used to process the received RF echo data (from the IC) and reconstruct the volume image using a phased array imaging approach. Imaging experiments were performed using wire and spring targets, a ventricle model and a human prostrate. Real-time volumetric images were captured at 5 volumes per second and are presented in this paper.

An Energy-Efficient Algorithm for Wearable Electrocardiogram Signal Processing in Ubiquitous Healthcare Applications

PubMed Central

Sodhro, Ali Hassan; Sodhro, Gul Hassan; Lohano, Sonia; Pirbhulal, Sandeep

2018-01-01

Rapid progress and emerging trends in miniaturized medical devices have enabled the un-obtrusive monitoring of physiological signals and daily activities of everyone’s life in a prominent and pervasive manner. Due to the power-constrained nature of conventional wearable sensor devices during ubiquitous sensing (US), energy-efficiency has become one of the highly demanding and debatable issues in healthcare. This paper develops a single chip-based wearable wireless electrocardiogram (ECG) monitoring system by adopting analog front end (AFE) chip model ADS1292R from Texas Instruments. The developed chip collects real-time ECG data with two adopted channels for continuous monitoring of human heart activity. Then, these two channels and the AFE are built into a right leg drive right leg drive (RLD) driver circuit with lead-off detection and medical graded test signal. Human ECG data was collected at 60 beats per minute (BPM) to 120 BPM with 60 Hz noise and considered throughout the experimental set-up. Moreover, notch filter (cutoff frequency 60 Hz), high-pass filter (cutoff frequency 0.67 Hz), and low-pass filter (cutoff frequency 100 Hz) with cut-off frequencies of 60 Hz, 0.67 Hz, and 100 Hz, respectively, were designed with bilinear transformation for rectifying the power-line noise and artifacts while extracting real-time ECG signals. Finally, a transmission power control-based energy-efficient (ETPC) algorithm is proposed, implemented on the hardware and then compared with the several conventional TPC methods. Experimental results reveal that our developed chip collects real-time ECG data efficiently, and the proposed ETPC algorithm achieves higher energy savings of 35.5% with a slightly larger packet loss ratio (PLR) as compared to conventional TPC (e.g., constant TPC, Gao’s, and Xiao’s methods). PMID:29558433

Fundamental investigation on influence of external heat on chip formation during thermal assisted machining

NASA Astrophysics Data System (ADS)

Alkali, A. U.; Ginta, T. L.; Abdulrani, A. M.; Elsiti, N. M.

2018-04-01

Various heat sources have been investigated by numerous researchers to reveal machinability benefits of thermally assisted machining (TAM) process. Fewer engineering materials have been tested. In the same vein, those researches continue to demonstrate effective performance of TAM in terms of bulk material removal rate, improved surface finish, prolong tool life and reduction of cutting forces among others. Experimental investigation on the strain-hardenability and flow stress of material removed with respect to increase in temperature in TAM has not been given attention in previous studies. This study investigated the pattern of chip morphology and segmentation giving close attention to influence of external heat source responsible for strain – hardenability of the material removed during TAM and dry machining at room temperature. Full immersion down cut milling was used throughout the machining conditions. Machining was conducted on AISI 316L using uncoated tungsten carbide end mill insert at varying cutting speeds (V) of 50, 79, and 100 m/min, and feed rates (f) of 0.15, 0.25, and 0.4 mm/tooth while the depth of cut was maintained at 0.2mm throughout the machining trials. The analyses of chip formation, segmentations and stain hardenability were carried out by using LMU light microscope, field emission microscopy and micro indentation. The study observed that build up edge is formed when a stagnation zone develops in front of tool tip which give rise to poor thermal gradient for conduction heat to be transferred within the bulk material during dry machining. This promotes varying strain – hardening of the material removed with evident high chips hardness and thickness, whereas TAM circumvents such impairment by softening the shear zone through local preheat.

An Energy-Efficient Algorithm for Wearable Electrocardiogram Signal Processing in Ubiquitous Healthcare Applications.

PubMed

Sodhro, Ali Hassan; Sangaiah, Arun Kumar; Sodhro, Gul Hassan; Lohano, Sonia; Pirbhulal, Sandeep

2018-03-20

Rapid progress and emerging trends in miniaturized medical devices have enabled the un-obtrusive monitoring of physiological signals and daily activities of everyone's life in a prominent and pervasive manner. Due to the power-constrained nature of conventional wearable sensor devices during ubiquitous sensing (US), energy-efficiency has become one of the highly demanding and debatable issues in healthcare. This paper develops a single chip-based wearable wireless electrocardiogram (ECG) monitoring system by adopting analog front end (AFE) chip model ADS1292R from Texas Instruments. The developed chip collects real-time ECG data with two adopted channels for continuous monitoring of human heart activity. Then, these two channels and the AFE are built into a right leg drive right leg drive (RLD) driver circuit with lead-off detection and medical graded test signal. Human ECG data was collected at 60 beats per minute (BPM) to 120 BPM with 60 Hz noise and considered throughout the experimental set-up. Moreover, notch filter (cutoff frequency 60 Hz), high-pass filter (cutoff frequency 0.67 Hz), and low-pass filter (cutoff frequency 100 Hz) with cut-off frequencies of 60 Hz, 0.67 Hz, and 100 Hz, respectively, were designed with bilinear transformation for rectifying the power-line noise and artifacts while extracting real-time ECG signals. Finally, a transmission power control-based energy-efficient (ETPC) algorithm is proposed, implemented on the hardware and then compared with the several conventional TPC methods. Experimental results reveal that our developed chip collects real-time ECG data efficiently, and the proposed ETPC algorithm achieves higher energy savings of 35.5% with a slightly larger packet loss ratio (PLR) as compared to conventional TPC (e.g., constant TPC, Gao's, and Xiao's methods).

Laser applications in advanced chip packaging

NASA Astrophysics Data System (ADS)

Müller, Dirk; Held, Andrew; Pätzel, Rainer; Clark, Dave; van Nunen, Joris

2016-03-01

While applications such as drilling μ-vias and laser direct imaging have been well established in the electronics industry, the mobile device industry's push for miniaturization is generating new demands for packaging technologies that allow for further reduction in feature size while reducing manufacturing cost. CO lasers have recently become available and their shorter wavelength allows for a smaller focus and drilling hole diameters down to 25μm whilst keeping the cost similar to CO2 lasers. Similarly, nanosecond UV lasers have gained significantly in power, become more reliable and lower in cost. On a separate front, the cost of ownership reduction for Excimer lasers has made this class of lasers attractive for structuring redistribution layers of IC substrates with feature sizes down to 2μm. Improvements in reliability and lower up-front cost for picosecond lasers is enabling applications that previously were only cost effective with mechanical means or long-pulsed lasers. We can now span the gamut from 100μm to 2μm for via drilling and can cost effectively structure redistribution layers with lasers instead of UV lamps or singulate packages with picosecond lasers.

Advanced system on a chip microelectronics for spacecraft and science instruments

NASA Astrophysics Data System (ADS)

Paschalidis, Nikolaos P.

2003-01-01

The explosive growth of the modern microelectronics field opens new horizons for the development of new lightweight, low power, and smart spacecraft and science instrumentation systems in the new millennium explorations. Although this growth is mostly driven by the commercial need for low power, portable and computationally intensive products, the applicability is obvious in the space sector. The additional difficulties needed to be overcome for applicability in space include radiation hardness for total ionizing dose and single event effects (SEE), and reliability. Additionally, this new capability introduces a whole new philosophy of design and R&D, with strong implications in organizational and inter-agency program management. One key component specifically developed towards low power, small size, highly autonomous spacecraft systems, is the smart sensor remote input/output (TRIO) chip. TRIO can interface to 32 transducers with current sources/sinks and voltage sensing. It includes front-end analog signal processing, a 10-bit ADC, memory, and standard serial and parallel I/Os. These functions are very useful for spacecraft and subsystems health and status monitoring, and control actions. The key contributions of the TRIO are feasibility of modular architectures, elimination of several miles of wire harnessing, and power savings by orders of magnitude. TRIO freely operates from a single power supply 2.5- 5.5 V with power dissipation <10 mW. This system on a chip device rapidly becomes a NASA and Commercial Space standard as it is already selected by thousands in several new millennium missions, including Europa Orbiter, Mars Surveyor Program, Solar Probe, Pluto Express, Stereo, Contour, Messenger, etc. In the Science Instrumentation field common instruments that can greatly take advantage of the new technologies are: energetic-particle/plasma and wave instruments, imagers, mass spectrometers, X-ray and UV spectrographs, magnetometers, laser rangefinding instruments, etc. Common measurements that apply to many of these instruments are precise time interval measurement and high resolution read-out of solid state detectors. A precise time interval measurement chip was specially developed that achieves ˜100 ps (×10 improvement) time resolution at a power dissipation ˜20 mW (×50 improvement), dead time ˜1.5 μs (×20 improvement), and chip die size 5 mm×5 mm versus two 20 cm×20 cm doubled sided boards. This device is selected as a key enabling technology for several NASA particle, delay line imaging, and laser range finding instruments onboard (NASA Image, Messenger, etc. missions). Another device with universal application is radiation energy read-out from solid state detectors. Multi-channel low-power and end-to-end sensor input—digital output is key for the new generation instruments. The readout channel comprises of a Charge Sensitive Preamplifier with a target sensitivity of ˜1 KeV FWHM at 20 pf detector capacitance, a Shaper Amplifier with programmable time constant/gain, and an ADC. The read-out chip together with the precise time interval chip comprises the essential elements of a common particle spectroscopy instrument. To mention some more applications fast-signal acquisition—and digitization is a very useful function for a category of instrument such as mass spectroscopy and profile laser rangefinding. The single chip approach includes a high bandwidth preamplifier, fast sampling ˜5 ns, analog memory ˜10K locations, 12-bit ADC and serial/parallel I/Os. The wealth of the applications proves the advanced microelectronics field as a key enabling technology for the new millennium space exploration.

Introduction: Towards Sustainable 2020 Nanoelectronics

NASA Astrophysics Data System (ADS)

Hoefflinger, Bernd

Faced with the immanent end of the nanometer roadmap at 10 nm, and with an electronics energy crisis, we have to engineer the largest strategy change in the 50-years history of microelectronics, renamed to nanoelectronics in 2000 with the first chips containing 100-nm transistors. Accepting the 10 nm-limit, the new strategy for the future growth of chip functionalities and markets has to deliver, within a decade, another 1,000× improvement in the energy per processing operation as well as in the energy per bit of memory and of communication. As a team from industry and from research, we present expectations, requirements and possible solutions for this challenging energy scenario of femto- and atto-Joule electronics. The introduction outlines the book's structure, which aims to describe the innovation eco-system needed for optimum-energy, sustainable nanoelectronics. For the benefit of the reader, chapters are grouped together into interest areas like transistors and circuits, technology, products and markets, radical innovations, as well as business and policy issues.

Design and performance of the readout electronics chain of the Delphi Forward Ring Imaging Cherenkov Detector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dam, P.; Nielsen, B.S.; Formenti, F.

1992-10-01

In this paper the Front End Readout electronics chain of the Forward Ring Imaging CHerenkov (FRICH) Detector used at the Delphi experiment of the Large Electron Positron (LEP) collider is presented. The system incorporates a wide band low noise preamplifier, mounted in the proximity of the MultiWire Proportional Chamber, an Amplifying-Discriminating-Multiple-xing FASTBUS unit for further signal amplification, discrimination and channel reduction and a LEP Time Digitizer FASTBUS unit for time digitization. The paper gives a general view of the detector and its electronics with particular emphasis on the novel characteristics and capabilities of the system.

Readout Electronics for the ATLAS LAr Calorimeter at HL-LHC

NASA Astrophysics Data System (ADS)

Chen, Hucheng; ATLAS Liquid Argon Calorimeter Group

The ATLAS Liquid Argon (LAr) calorimeters are high precision, high sensitivity and high granularity detectors designed to provide precision measurements of electrons, photons, jets and missing transverse energy. ATLAS and its LAr calorimeters have been operating and collecting proton-proton collisions at LHC since 2009. The current front-end electronics of the LAr calorimeters need to be upgraded to sustain the higher radiation levels and data rates expected at the upgraded high luminosity LHC machine (HL-LHC), which will have 5 times more luminosity than the LHC in its ultimate configuration. The complexity of the present electronics and the obsolescence of some of components of which it is made, will not allow a partial replacement of the system. A completely new readout architecture scheme is under study and many components are being developed in various R&D programs of the LAr Calorimeter Group.The new front-end readout electronics will send data continuously at each bunch crossing through high speed radiation resistant optical links. The data will be processed real-time with the possibility of implementing trigger algorithms for clusters and electron/photon identification at a higher granularity than that which is currently implemented. The new architecture will eliminate the intrinsic limitation presently existing on Level-1 trigger acceptance. This article is an overview of the R&D activities which covers architectural design aspects of the new electronics as well as some detailed progress on the development of several ASICs needed, and preliminary studies with FPGAs to cover the backend functions including part of the Level-1 trigger requirements. A recently proposed staged upgrade with hybrid Tower Builder Board (TBB) is also described.

A CMOS wireless biomolecular sensing system-on-chip based on polysilicon nanowire technology.

PubMed

Huang, C-W; Huang, Y-J; Yen, P-W; Tsai, H-H; Liao, H-H; Juang, Y-Z; Lu, S-S; Lin, C-T

2013-11-21

As developments of modern societies, an on-field and personalized diagnosis has become important for disease prevention and proper treatment. To address this need, in this work, a polysilicon nanowire (poly-Si NW) based biosensor system-on-chip (bio-SSoC) is designed and fabricated by a 0.35 μm 2-Poly-4-Metal (2P4M) complementary metal-oxide-semiconductor (CMOS) process provided by a commercialized semiconductor foundry. Because of the advantages of CMOS system-on-chip (SoC) technologies, the poly-Si NW biosensor is integrated with a chopper differential-difference amplifier (DDA) based analog-front-end (AFE), a successive approximation analog-to-digital converter (SAR ADC), and a microcontroller to have better sensing capabilities than a traditional Si NW discrete measuring system. In addition, an on-off key (OOK) wireless transceiver is also integrated to form a wireless bio-SSoC technology. This is pioneering work to harness the momentum of CMOS integrated technology into emerging bio-diagnosis technologies. This integrated technology is experimentally examined to have a label-free and low-concentration biomolecular detection for both Hepatitis B Virus DNA (10 fM) and cardiac troponin I protein (3.2 pM). Based on this work, the implemented wireless bio-SSoC has demonstrated a good biomolecular sensing characteristic and a potential for low-cost and mobile applications. As a consequence, this developed technology can be a promising candidate for on-field and personalized applications in biomedical diagnosis.

An acoustic charge transport imager for high definition television applications

NASA Technical Reports Server (NTRS)

Hunt, W. D.; Brennan, Kevin F.

1994-01-01

The primary goal of this research is to develop a solid-state high definition television (HDTV) imager chip operating at a frame rate of about 170 frames/sec at 2 Megapixels per frame. This imager offers an order of magnitude improvement in speed over CCD designs and will allow for monolithic imagers operating from the IR to the UV. The technical approach of the project focuses on the development of the three basic components of the imager and their integration. The imager chip can be divided into three distinct components: (1) image capture via an array of avalanche photodiodes (APD's), (2) charge collection, storage and overflow control via a charge transfer transistor device (CTD), and (3) charge readout via an array of acoustic charge transport (ACT) channels. The use of APD's allows for front end gain at low noise and low operating voltages while the ACT readout enables concomitant high speed and high charge transfer efficiency. Currently work is progressing towards the development of manufacturable designs for each of these component devices. In addition to the development of each of the three distinct components, work towards their integration is also progressing. The component designs are considered not only to meet individual specifications but to provide overall system level performance suitable for HDTV operation upon integration. The ultimate manufacturability and reliability of the chip constrains the design as well. The progress made during this period is described in detail in Sections 2-4.

Test beam demonstration of silicon microstrip modules with transverse momentum discrimination for the future CMS tracking detector

NASA Astrophysics Data System (ADS)

Adam, W.; Bergauer, T.; Brondolin, E.; Dragicevic, M.; Friedl, M.; Frühwirth, R.; Hoch, M.; Hrubec, J.; König, A.; Steininger, H.; Treberspurg, W.; Waltenberger, W.; Alderweireldt, S.; Beaumont, W.; Janssen, X.; Lauwers, J.; Van Mechelen, P.; Van Remortel, N.; Van Spilbeeck, A.; Beghin, D.; Brun, H.; Clerbaux, B.; De Lentdecker, G.; Delannoy, H.; Fasanella, G.; Favart, L.; Goldouzian, R.; Grebenyuk, A.; Karapostoli, G.; Lenzi, T.; Léonard, A.; Luetic, J.; Maerschalk, T.; Marinov, A.; Postiau, N.; Randle-Conde, A.; Seva, T.; Vanlaer, P.; Vannerom, D.; Yonamine, R.; Wang, Q.; Yang, Y.; Zenoni, F.; Zhang, F.; Abu Zeid, S.; Blekman, F.; De Bruyn, I.; De Clercq, J.; D'Hondt, J.; Deroover, K.; Lowette, S.; Moortgat, S.; Moreels, L.; Python, Q.; Skovpen, K.; Van Mulders, P.; Van Parijs, I.; Bakhshiansohi, H.; Bondu, O.; Brochet, S.; Bruno, G.; Caudron, A.; Delaere, C.; Delcourt, M.; De Visscher, S.; Francois, B.; Giammanco, A.; Jafari, A.; Cabrera Jamoulle, J.; De Favereau De Jeneret, J.; Komm, M.; Krintiras, G.; Lemaitre, V.; Magitteri, A.; Mertens, A.; Michotte, D.; Musich, M.; Piotrzkowski, K.; Quertenmont, L.; Szilasi, N.; Vidal Marono, M.; Wertz, S.; Beliy, N.; Caebergs, T.; Daubie, E.; Hammad, G. H.; Härkönen, J.; Lampén, T.; Luukka, P.; Peltola, T.; Tuominen, E.; Tuovinen, E.; Eerola, P.; Baulieu, G.; Boudoul, G.; Caponetto, L.; Combaret, C.; Contardo, D.; Dupasquier, T.; Gallbit, G.; Lumb, N.; Mirabito, L.; Perries, S.; Vander Donckt, M.; Viret, S.; Agram, J.-L.; Andrea, J.; Bloch, D.; Bonnin, C.; Brom, J.-M.; Chabert, E.; Chanon, N.; Charles, L.; Conte, E.; Fontaine, J.-Ch.; Gross, L.; Hosselet, J.; Jansova, M.; Tromson, D.; Autermann, C.; Feld, L.; Karpinski, W.; Kiesel, K. M.; Klein, K.; Lipinski, M.; Ostapchuk, A.; Pierschel, G.; Preuten, M.; Rauch, M.; Schael, S.; Schomakers, C.; Schulz, J.; Schwering, G.; Wlochal, M.; Zhukov, V.; Pistone, C.; Fluegge, G.; Kuensken, A.; Pooth, O.; Stahl, A.; Aldaya, M.; Asawatangtrakuldee, C.; Beernaert, K.; Bertsche, D.; Contreras-Campana, C.; Eckerlin, G.; Eckstein, D.; Eichhorn, T.; Gallo, E.; Garay Garcia, J.; Hansen, K.; Haranko, M.; Harb, A.; Hauk, J.; Keaveney, J.; Kalogeropoulos, A.; Kleinwort, C.; Lohmann, W.; Mankel, R.; Maser, H.; Mittag, G.; Muhl, C.; Mussgiller, A.; Pitzl, D.; Reichelt, O.; Savitskyi, M.; Schuetze, P.; Walsh, R.; Zuber, A.; Biskop, H.; Buhmann, P.; Centis-Vignali, M.; Garutti, E.; Haller, J.; Hoffmann, M.; Klanner, R.; Matysek, M.; Perieanu, A.; Scharf, Ch.; Schleper, P.; Schmidt, A.; Schwandt, J.; Sonneveld, J.; Steinbrück, G.; Vormwald, B.; Wellhausen, J.; Abbas, M.; Amstutz, C.; Barvich, T.; Barth, Ch.; Boegelspacher, F.; De Boer, W.; Butz, E.; Casele, M.; Colombo, F.; Dierlamm, A.; Freund, B.; Hartmann, F.; Heindl, S.; Husemann, U.; Kornmeyer, A.; Kudella, S.; Muller, Th.; Printz, M.; Simonis, H. J.; Steck, P.; Weber, M.; Weiler, Th.; Anagnostou, G.; Asenov, P.; Assiouras, P.; Daskalakis, G.; Kyriakis, A.; Loukas, D.; Paspalaki, L.; Siklér, F.; Veszprémi, V.; Bhardwaj, A.; Dalal, R.; Jain, G.; Ranjan, K.; Dutta, S.; Chowdhury, S. Roy; Bakhshiansohl, H.; Behnamian, H.; Khakzad, M.; Naseri, M.; Cariola, P.; Creanza, D.; De Palma, M.; De Robertis, G.; Fiore, L.; Franco, M.; Loddo, F.; Sala, G.; Silvestris, L.; Maggi, G.; My, S.; Selvaggi, G.; Albergo, S.; Costa, S.; Di Mattia, A.; Giordano, F.; Potenza, R.; Saizu, M. A.; Tricomi, A.; Tuve, C.; Barbagli, G.; Brianzi, M.; Ciaranfi, R.; Ciulli, V.; Civinini, C.; D'Alessandro, R.; Focardi, E.; Latino, G.; Lenzi, P.; Meschini, M.; Paoletti, S.; Russo, L.; Scarlini, E.; Sguazzoni, G.; Strom, D.; Viliani, L.; Ferro, F.; Lo Vetere, M.; Robutti, E.; Dinardo, M. E.; Fiorendi, S.; Gennai, S.; Malvezzi, S.; Manzoni, R. A.; Menasce, D.; Moroni, L.; Pedrini, D.; Azzi, P.; Bacchetta, N.; Bisello, D.; Dall'Osso, M.; Pozzobon, N.; Tosi, M.; De Canio, F.; Gaioni, L.; Manghisoni, M.; Nodari, B.; Riceputi, E.; Re, V.; Traversi, G.; Comotti, D.; Ratti, L.; Alunni Solestizi, L.; Biasini, M.; Bilei, G. M.; Cecchi, C.; Checcucci, B.; Ciangottini, D.; Fanò, L.; Gentsos, C.; Ionica, M.; Leonardi, R.; Manoni, E.; Mantovani, G.; Marconi, S.; Mariani, V.; Menichelli, M.; Modak, A.; Morozzi, A.; Moscatelli, F.; Passeri, D.; Placidi, P.; Postolache, V.; Rossi, A.; Saha, A.; Santocchia, A.; Storchi, L.; Spiga, D.; Androsov, K.; Azzurri, P.; Arezzini, S.; Bagliesi, G.; Basti, A.; Boccali, T.; Borrello, L.; Bosi, F.; Castaldi, R.; Ciampa, A.; Ciocci, M. A.; Dell'Orso, R.; Donato, S.; Fedi, G.; Giassi, A.; Grippo, M. T.; Ligabue, F.; Lomtadze, T.; Magazzu, G.; Martini, L.; Mazzoni, E.; Messineo, A.; Moggi, A.; Morsani, F.; Palla, F.; Palmonari, F.; Raffaelli, F.; Rizzi, A.; Savoy-Navarro, A.; Spagnolo, P.; Tenchini, R.; Tonelli, G.; Venturi, A.; Verdini, P. G.; Bellan, R.; Costa, M.; Covarelli, R.; Da Rocha Rolo, M.; Demaria, N.; Rivetti, A.; Dellacasa, G.; Mazza, G.; Migliore, E.; Monteil, E.; Pacher, L.; Ravera, F.; Solano, A.; Fernandez, M.; Gomez, G.; Jaramillo Echeverria, R.; Moya, D.; Gonzalez Sanchez, F. J.; Vila, I.; Virto, A. L.; Abbaneo, D.; Ahmed, I.; Albert, E.; Auzinger, G.; Berruti, G.; Bianchi, G.; Blanchot, G.; Bonnaud, J.; Caratelli, A.; Ceresa, D.; Christiansen, J.; Cichy, K.; Daguin, J.; D'Auria, A.; Detraz, S.; Deyrail, D.; Dondelewski, O.; Faccio, F.; Frank, N.; Gadek, T.; Gill, K.; Honma, A.; Hugo, G.; Jara Casas, L. M.; Kaplon, J.; Kornmayer, A.; Kottelat, L.; Kovacs, M.; Krammer, M.; Lenoir, P.; Mannelli, M.; Marchioro, A.; Marconi, S.; Mersi, S.; Martina, S.; Michelis, S.; Moll, M.; Onnela, A.; Orfanelli, S.; Pavis, S.; Peisert, A.; Pernot, J.-F.; Petagna, P.; Petrucciani, G.; Postema, H.; Rose, P.; Tropea, P.; Troska, J.; Tsirou, A.; Vasey, F.; Vichoudis, P.; Verlaat, B.; Zwalinski, L.; Bachmair, F.; Becker, R.; di Calafiori, D.; Casal, B.; Berger, P.; Djambazov, L.; Donega, M.; Grab, C.; Hits, D.; Hoss, J.; Kasieczka, G.; Lustermann, W.; Mangano, B.; Marionneau, M.; Martinez Ruiz del Arbol, P.; Masciovecchio, M.; Meinhard, M.; Perozzi, L.; Roeser, U.; Starodumov, A.; Tavolaro, V.; Wallny, R.; Zhu, D.; Amsler, C.; Bösiger, K.; Caminada, L.; Canelli, F.; Chiochia, V.; de Cosa, A.; Galloni, C.; Hreus, T.; Kilminster, B.; Lange, C.; Maier, R.; Ngadiuba, J.; Pinna, D.; Robmann, P.; Taroni, S.; Yang, Y.; Bertl, W.; Deiters, K.; Erdmann, W.; Horisberger, R.; Kaestli, H.-C.; Kotlinski, D.; Langenegger, U.; Meier, B.; Rohe, T.; Streuli, S.; Chen, P.-H.; Dietz, C.; Grundler, U.; Hou, W.-S.; Lu, R.-S.; Moya, M.; Cussans, D.; Flacher, H.; Goldstein, J.; Grimes, M.; Jacob, J.; Seif El Nasr-Storey, S.; Cole, J.; Hoad, C.; Hobson, P.; Morton, A.; Reid, I. D.; Auzinger, G.; Bainbridge, R.; Dauncey, P.; Fulcher, J.; Hall, G.; James, T.; Magnan, A.-M.; Pesaresi, M.; Raymond, D. M.; Uchida, K.; Braga, D.; Coughlan, J. A.; Harder, K.; Jones, L.; Ilic, J.; Murray, P.; Prydderch, M.; Tomalin, I. R.; Garabedian, A.; Heintz, U.; Narain, M.; Nelson, J.; Sagir, S.; Speer, T.; Swanson, J.; Tersegno, D.; Watson-Daniels, J.; Chertok, M.; Conway, J.; Conway, R.; Flores, C.; Lander, R.; Pellett, D.; Ricci-Tam, F.; Squires, M.; Thomson, J.; Yohay, R.; Burt, K.; Ellison, J.; Hanson, G.; Olmedo, M.; Si, W.; Yates, B. R.; Gerosa, R.; Sharma, V.; Vartak, A.; Yagil, A.; Zevi Della Porta, G.; Dutta, V.; Gouskos, L.; Incandela, J.; Kyre, S.; Mullin, S.; Qu, H.; White, D.; Dominguez, A.; Bartek, R.; Cumalat, J. P.; Ford, W. T.; Jensen, F.; Johnson, A.; Krohn, M.; Leontsinis, S.; Mulholland, T.; Stenson, K.; Wagner, S. R.; Apresyan, A.; Bolla, G.; Burkett, K.; Butler, J. N.; Cheung, H. W. K.; Chramowicz, J.; Christian, D.; Cooper, W. E.; Deptuch, G.; Derylo, G.; Gingu, C.; Grünendahl, S.; Hasegawa, S.; Hoff, J.; Howell, J.; Hrycyk, M.; Jindariani, S.; Johnson, M.; Kahlid, F.; Lei, C. M.; Lipton, R.; Lopes De Sá, R.; Liu, T.; Los, S.; Matulik, M.; Merkel, P.; Nahn, S.; Prosser, A.; Rivera, R.; Schneider, B.; Sellberg, G.; Shenai, A.; Spiegel, L.; Tran, N.; Uplegger, L.; Voirin, E.; Berry, D. R.; Chen, X.; Ennesser, L.; Evdokimov, A.; Evdokimov, O.; Gerber, C. E.; Hofman, D. J.; Makauda, S.; Mills, C.; Sandoval Gonzalez, I. D.; Alimena, J.; Antonelli, L. J.; Francis, B.; Hart, A.; Hill, C. S.; Parashar, N.; Stupak, J.; Bortoletto, D.; Bubna, M.; Hinton, N.; Jones, M.; Miller, D. H.; Shi, X.; Tan, P.; Baringer, P.; Bean, A.; Khalil, S.; Kropivnitskaya, A.; Majumder, D.; Wilson, G.; Ivanov, A.; Mendis, R.; Mitchell, T.; Skhirtladze, N.; Taylor, R.; Anderson, I.; Fehling, D.; Gritsan, A.; Maksimovic, P.; Martin, C.; Nash, K.; Osherson, M.; Swartz, M.; Xiao, M.; Acosta, J. G.; Cremaldi, L. M.; Oliveros, S.; Perera, L.; Summers, D.; Bloom, K.; Claes, D. R.; Fangmeier, C.; Gonzalez Suarez, R.; Monroy, J.; Siado, J.; Hahn, K.; Sevova, S.; Sung, K.; Trovato, M.; Bartz, E.; Gershtein, Y.; Halkiadakis, E.; Kyriacou, S.; Lath, A.; Nash, K.; Osherson, M.; Schnetzer, S.; Stone, R.; Walker, M.; Malik, S.; Norberg, S.; Ramirez Vargas, J. E.; Alyari, M.; Dolen, J.; Godshalk, A.; Harrington, C.; Iashvili, I.; Kharchilava, A.; Nguyen, D.; Parker, A.; Rappoccio, S.; Roozbahani, B.; Alexander, J.; Chaves, J.; Chu, J.; Dittmer, S.; McDermott, K.; Mirman, N.; Rinkevicius, A.; Ryd, A.; Salvati, E.; Skinnari, L.; Soffi, L.; Tao, Z.; Thom, J.; Tucker, J.; Zientek, M.; Akgün, B.; Ecklund, K. M.; Kilpatrick, M.; Nussbaum, T.; Zabel, J.; Betchart, B.; Covarelli, R.; Demina, R.; Hindrichs, O.; Petrillo, G.; Eusebi, R.; Patel, R.; Perloff, A.; Ulmer, K. A.; Delannoy, A. G.; D'Angelo, P.; Johns, W.

2018-03-01

A new CMS Tracker is under development for operation at the High Luminosity LHC from 2026 onwards. It includes an outer tracker based on dedicated modules that will reconstruct short track segments, called stubs, using spatially coincident clusters in two closely spaced silicon sensor layers. These modules allow the rejection of low transverse momentum track hits and reduce the data volume before transmission to the first level trigger. The inclusion of tracking information in the trigger decision is essential to limit the first level trigger accept rate. A customized front-end readout chip, the CMS Binary Chip (CBC), containing stub finding logic has been designed for this purpose. A prototype module, equipped with the CBC chip, has been constructed and operated for the first time in a 4 GeemVem/emc positron beam at DESY. The behaviour of the stub finding was studied for different angles of beam incidence on a module, which allows an estimate of the sensitivity to transverse momentum within the future CMS detector. A sharp transverse momentum threshold around 2 emVem/emc was demonstrated, which meets the requirement to reject a large fraction of low momentum tracks present in the LHC environment on-detector. This is the first realistic demonstration of a silicon tracking module that is able to select data, based on the particle's transverse momentum, for use in a first level trigger at the LHC . The results from this test are described here.

40 CFR 63.487 - Batch front-end process vents-reference control technology.

Code of Federal Regulations, 2012 CFR

2012-07-01

...-reference control technology. 63.487 Section 63.487 Protection of Environment ENVIRONMENTAL PROTECTION... SOURCE CATEGORIES National Emission Standards for Hazardous Air Pollutant Emissions: Group I Polymers and Resins § 63.487 Batch front-end process vents—reference control technology. (a) Batch front-end process...

40 CFR 63.491 - Batch front-end process vents-recordkeeping requirements.

Code of Federal Regulations, 2014 CFR

2014-07-01

... CATEGORIES National Emission Standards for Hazardous Air Pollutant Emissions: Group I Polymers and Resins § 63.491 Batch front-end process vents—recordkeeping requirements. (a) Group determination records for...) through (a)(6) of this section for each batch front-end process vent subject to the group determination...

40 CFR 63.487 - Batch front-end process vents-reference control technology.

Code of Federal Regulations, 2011 CFR

2011-07-01

... control technology. 63.487 Section 63.487 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY... CATEGORIES National Emission Standards for Hazardous Air Pollutant Emissions: Group I Polymers and Resins § 63.487 Batch front-end process vents—reference control technology. (a) Batch front-end process vents...

40 CFR 63.491 - Batch front-end process vents-recordkeeping requirements.

Code of Federal Regulations, 2013 CFR

2013-07-01

... CATEGORIES National Emission Standards for Hazardous Air Pollutant Emissions: Group I Polymers and Resins § 63.491 Batch front-end process vents—recordkeeping requirements. (a) Group determination records for...) through (a)(6) of this section for each batch front-end process vent subject to the group determination...

40 CFR 63.487 - Batch front-end process vents-reference control technology.

Code of Federal Regulations, 2013 CFR

2013-07-01

...-reference control technology. 63.487 Section 63.487 Protection of Environment ENVIRONMENTAL PROTECTION... SOURCE CATEGORIES National Emission Standards for Hazardous Air Pollutant Emissions: Group I Polymers and Resins § 63.487 Batch front-end process vents—reference control technology. (a) Batch front-end process...

40 CFR 63.487 - Batch front-end process vents-reference control technology.

Code of Federal Regulations, 2014 CFR

2014-07-01

...-reference control technology. 63.487 Section 63.487 Protection of Environment ENVIRONMENTAL PROTECTION... SOURCE CATEGORIES National Emission Standards for Hazardous Air Pollutant Emissions: Group I Polymers and Resins § 63.487 Batch front-end process vents—reference control technology. (a) Batch front-end process...

40 CFR 63.491 - Batch front-end process vents-recordkeeping requirements.

Code of Federal Regulations, 2012 CFR

2012-07-01

... CATEGORIES National Emission Standards for Hazardous Air Pollutant Emissions: Group I Polymers and Resins § 63.491 Batch front-end process vents—recordkeeping requirements. (a) Group determination records for...) through (a)(6) of this section for each batch front-end process vent subject to the group determination...

40 CFR 63.491 - Batch front-end process vents-recordkeeping requirements.

Code of Federal Regulations, 2011 CFR

2011-07-01

... CATEGORIES National Emission Standards for Hazardous Air Pollutant Emissions: Group I Polymers and Resins § 63.491 Batch front-end process vents—recordkeeping requirements. (a) Group determination records for...) through (a)(6) of this section for each batch front-end process vent subject to the group determination...

The Parkes front-end controller and noise-adding radiometer

NASA Technical Reports Server (NTRS)

Brunzie, T. J.

1990-01-01

A new front-end controller (FEC) was installed on the 64-m antenna in Parkes, Australia, to support the 1989 Voyager 2 Neptune encounter. The FEC was added to automate operation of the front-end microwave hardware as part of the Deep Space Network's Parkes-Canberra Telemetry Array. Much of the front-end hardware was refurbished and reimplemented from a front-end system installed in 1985 by the European Space Agency for the Uranus encounter; however, the FEC and its associated noise-adding radiometer (NAR) were new Jet Propulsion Laboratory (JPL) designs. Project requirements and other factors led to the development of capabilities not found in standard Deep Space Network (DSN) controllers and radiometers. The Parkes FEC/NAR performed satisfactorily throughout the Neptune encounter and was removed in October 1989.

Reconfigurable radio receiver with fractional sample rate converter and multi-rate ADC based on LO-derived sampling clock

NASA Astrophysics Data System (ADS)

Park, Sungkyung; Park, Chester Sungchung

2018-03-01

A composite radio receiver back-end and digital front-end, made up of a delta-sigma analogue-to-digital converter (ADC) with a high-speed low-noise sampling clock generator, and a fractional sample rate converter (FSRC), is proposed and designed for a multi-mode reconfigurable radio. The proposed radio receiver architecture contributes to saving the chip area and thus lowering the design cost. To enable inter-radio access technology handover and ultimately software-defined radio reception, a reconfigurable radio receiver consisting of a multi-rate ADC with its sampling clock derived from a local oscillator, followed by a rate-adjustable FSRC for decimation, is designed. Clock phase noise and timing jitter are examined to support the effectiveness of the proposed radio receiver. A FSRC is modelled and simulated with a cubic polynomial interpolator based on Lagrange method, and its spectral-domain view is examined in order to verify its effect on aliasing, nonlinearity and signal-to-noise ratio, giving insight into the design of the decimation chain. The sampling clock path and the radio receiver back-end data path are designed in a 90-nm CMOS process technology with 1.2V supply.

Millimeter-wave silicon-based ultra-wideband automotive radar transceivers

NASA Astrophysics Data System (ADS)

Jain, Vipul

Since the invention of the integrated circuit, the semiconductor industry has revolutionized the world in ways no one had ever anticipated. With the advent of silicon technologies, consumer electronics became light-weight and affordable and paved the way for an Information-Communication-Entertainment age. While silicon almost completely replaced compound semiconductors from these markets, it has been unable to compete in areas with more stringent requirements due to technology limitations. One of these areas is automotive radar sensors, which will enable next-generation collision-warning systems in automobiles. A low-cost implementation is absolutely essential for widespread use of these systems, which leads us to the subject of this dissertation---silicon-based solutions for automotive radars. This dissertation presents architectures and design techniques for mm-wave automotive radar transceivers. Several fully-integrated transceivers and receivers operating at 22-29 GHz and 77-81 GHz are demonstrated in both CMOS and SiGe BiCMOS technologies. Excellent performance is achieved indicating the suitability of silicon technologies for automotive radar sensors. The first CMOS 22-29-GHz pulse-radar receiver front-end for ultra-wideband radars is presented. The chip includes a low noise amplifier, I/Q mixers, quadrature voltage-controlled oscillators, pulse formers and variable-gain amplifiers. Fabricated in 0.18-mum CMOS, the receiver achieves a conversion gain of 35-38.1 dB and a noise figure of 5.5-7.4 dB. Integration of multi-mode multi-band transceivers on a single chip will enable next-generation low-cost automotive radar sensors. Two highly-integrated silicon ICs are designed in a 0.18-mum BiCMOS technology. These designs are also the first reported demonstrations of mm-wave circuits with high-speed digital circuits on the same chip. The first mm-wave dual-band frequency synthesizer and transceiver, operating in the 24-GHz and 77-GHz bands, are demonstrated. All circuits except the oscillators are shared between the two bands. A multi-functional injection-locked circuit is used after the oscillators to reconfigure the division ratio inside the phase-locked loop. The synthesizer is suitable for integration in automotive radar transceivers and heterodyne receivers for 94-GHz imaging applications. The transceiver chip includes a dual-band low noise amplifier, a shared downconversion chain, dual-band pulse formers, power amplifiers, a dual-band frequency synthesizer and a high-speed programmable baseband pulse generator. Radar functionality is demonstrated using loopback measurements.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bolotnikov, A. E., E-mail: bolotnik@bnl.gov; Ackley, K.; Camarda, G. S.

We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm{sup 3} detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We presentmore » the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays’ performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bolotnikov, A. E.; Ackley, K.; Camarda, G. S.

We developed a robust and low-cost array of virtual Frisch-grid CdZnTe (CZT) detectors coupled to a front-end readout ASIC for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6x6x15 mm 3 detectors grouped into 3x3 sub-arrays of 2x2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readoutmore » electronics. The further enhancement of the arrays’ performance and reduction of their cost are made possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.« less

Pseudo-differential CMOS analog front-end circuit for wide-bandwidth optical probe current sensor

NASA Astrophysics Data System (ADS)

Uekura, Takaharu; Oyanagi, Kousuke; Sonehara, Makoto; Sato, Toshiro; Miyaji, Kousuke

2018-04-01

In this paper, we present a pseudo-differential analog front-end (AFE) circuit for a novel optical probe current sensor (OPCS) aimed for high-frequency power electronics. It employs a regulated cascode transimpedance amplifier (RGC-TIA) to achieve a high gain and a large bandwidth without using an extremely high performance operational amplifier. The AFE circuit is designed in a 0.18 µm standard CMOS technology achieving a high transimpedance gain of 120 dB Ω and high cut off frequency of 16 MHz. The measured slew rate is 70 V/µs and the input referred current noise is 1.02 pA/\\sqrt{\\text{Hz}} . The magnetic resolution and bandwidth of OPCS are estimated to be 1.29 mTrms and 16 MHz, respectively; the bandwidth is higher than that of the reported Hall effect current sensor.

Proof of concept of an imaging system demonstrator for PET applications with SiPM

NASA Astrophysics Data System (ADS)

Morrocchi, Matteo; Marcatili, Sara; Belcari, Nicola; Giuseppina Bisogni, Maria; Collazuol, Gianmaria; Ambrosi, Giovanni; Santoni, Cristiano; Corsi, Francesco; Foresta, Maurizio; Marzocca, Cristoforo; Matarrese, Gianvito; Sportelli, Giancarlo; Guerra, Pedro; Santos, Andres; Del Guerra, Alberto

2013-08-01

A PET imaging system demonstrator based on LYSO crystal arrays coupled to SiPM matrices is under construction at the University and INFN of Pisa. Two SiPM matrices, composed of 8×8 SiPM pixels, and 1,5 mm pitch, have been coupled one to one to a LYSO crystals array and read out by a custom electronics system. front-end ASICs were used to read 8 channels of each matrix. Data from each front-end were multiplexed and sent to a DAQ board for the digital conversion; a motherboard collects the data and communicates with a host computer through a USB port for the storage and off-line data processing. In this paper we show the first preliminary tomographic image of a point-like radioactive source acquired with part of the two detection heads in time coincidence.

Development of FEB Test Platform for ATLAS New Small Wheel Upgrade

NASA Astrophysics Data System (ADS)

Lu, Houbing; Hu, Kun; Wang, Xu; Li, Feng; Han, Liang; Jin, Ge

2016-10-01

This concept of test platform is based on the test requirements of the front-end board (FEB) which is developed for the phase I upgrade of the small Thin Gap Chamber(sTGC) detector on New Small Wheel(NSW) of ATLAS. The front-end electronics system of sTGC consists of 1,536 FEBs with about 322,000 readout of strips, wires and pads in total. A test platform for FEB with up to 256 channels has been designed to keep the testing efficiency at a controllable level. We present the circuit model architecture of the platform, and its functions and implementation as well. The firmware based on Field Programmable Gate Array (FPGA) and the software based on PC have been developed, and basic test methods have been established. FEB readout measurements have been performed in analog injection from the test platform, which will provide a fast and efficient test method for the production of FEB.

Portable microfluidic platform for real-time, high sensitive detection and identification of trichloroethylene and other organochloride compounds

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jensen, Erik

In this successful SBIR Phase II effort, HJ Science & Technology, Inc. has designed and built a novel portable instrument capable of performing automated aqueous organochloride (chlorinated solvent) speciation analysis for environmental monitoring at DoE sites. Our technique employs performing organochloride conjugation, labeling the conjugate with an efficient fluorophore, and performing on-chip capillary electrophoresis separation with laser induced fluorescence detection. The key component of the portable instrument is a novel microfluidic chip capable of complete “end-to-end” automation of sample preparation, conjugation, labeling, and μCE separation and detection. In addition, the Phase II prototype includes key supporting instrumentation such as themore » optical module, pneumatic manifold, electronics, software, etc. As such, we have achieved all of the following 4 Phase II technical objectives: 1) Further refine and optimize the “on-chip” automation of the organochloride conjugation and labeling protocol, 2) Further improve the microfluidic chip fabrication process and the pneumatic manifold design in order to address issues related to performance consistency, product yield, performance reliability, and user friendliness, 3) Design and build the supporting components of the Phase II prototype including optical module, electronics, and software, and 4) Assemble the Phase II prototype hardware.« less

A Drift Chamber to Measure Charged Particles at COMPASS-II

NASA Astrophysics Data System (ADS)

Heitz, Robert; Compass Collaboration

2013-10-01

A new drift chamber (DC05) will be constructed to replace two tracking detector stations based on straw tubes, ST02 and ST03 in the COMPASS spectrometer. DC05 uses the designs from DC04, a previous drift chamber designed at CEA-Saclay, France, but adds the addition of more wires for improved acceptance. In addition to more wires DC05 will also change its front end electronics using a new pre-amplifier-discriminator chip (CMAD). DC05 consists of 8 layers of anode planes and 21 layers of G-10 material frames carrying cathode planes and gas windows. The wires are orientated with two layers in the vertical x-direction, two layers in the horizontal y-direction, two layers offset +10 deg of the vertical x-direction, and two layers offset -10 deg of the vertical x-direction. The wires in parallel directions are offset half a pitch to resolve left-right ambiguities. The purpose for different wire orientations is to reconstruct the 3D space particle trajectory to fit a particle track. Each layer of wires is covered on the top and bottom by a cathode plane of carbon coated mylar. All these layers are sandwiched between two steel stiffening frames for support and noise reduction. A future drift chamber, DC06, is also being designed based off of DC05. Research funded by NSF-PHY-12-05-671 Medium Energy Nuclear Physics.

Characterization of Pixelated Cadmium-Zinc-Telluride Detectors for Astrophysical Applications

NASA Technical Reports Server (NTRS)

Gaskin, Jessica; Sharma, Dharma; Ramsey, Brian; Seller, Paul

2003-01-01

Comparisons of charge sharing and charge loss measurements between two pixelated Cadmium-Zinc-Telluride (CdZnTe) detectors are discussed. These properties along with the detector geometry help to define the limiting energy resolution and spatial resolution of the detector in question. The first detector consists of a 1-mm-thick piece of CdZnTe sputtered with a 4x4 array of pixels with pixel pitch of 750 microns (inter-pixel gap is 100 microns). Signal readout is via discrete ultra-low-noise preamplifiers, one for each of the 16 pixels. The second detector consists of a 2-mm-thick piece of CdZnTe sputtered with a 16x16 array of pixels with a pixel pitch of 300 microns (inter-pixel gap is 50 microns). This crystal is bonded to a custom-built readout chip (ASIC) providing all front-end electronics to each of the 256 independent pixels. These detectors act as precursors to that which will be used at the focal plane of the High Energy Replicated Optics (HERO) telescope currently being developed at Marshall Space Flight Center. With a telescope focal length of 6 meters, the detector needs to have a spatial resolution of around 200 microns in order to take full advantage of the HERO angular resolution. We discuss to what degree charge sharing will degrade energy resolution but will improve our spatial resolution through position interpolation.

A non-contact capacitance based electrocardiograph and associated heart-rate detection using enhanced Fourier interpolation method.

PubMed

Kumar Thakur, Rupak; Anoop, C S

2015-08-01

Cardio-vascular health monitoring has gained considerable attention in the recent years. Principle of non-contact capacitive electrocardiograph (ECG) and its applicability as a valuable, low-cost, easy-to-use scheme for cardio-vascular health monitoring has been demonstrated in some recent research papers. In this paper, we develop a complete non-contact ECG system using a suitable front-end electronic circuit and a heart-rate (HR) measurement unit using enhanced Fourier interpolation technique. The front-end electronic circuit is realized using low-cost, readily available components and the proposed HR measurement unit is designed to achieve fairly accurate results. The entire system has been extensively tested to verify its efficacy and test results show that the developed system can estimate HR with an accuracy of ±2 beats. Detailed tests have been conducted to validate the performance of the system for different cloth thicknesses of the subject. Some basic tests which illustrate the application of the proposed system for heart-rate variability estimation has been conducted and results reported. The developed system can be used as a portable, reliable, long-term cardiac health monitoring device and can be extended to human drowsiness detection.

Parameter Extraction Method for the Electrical Model of a Silicon Photomultiplier

NASA Astrophysics Data System (ADS)

Licciulli, Francesco; Marzocca, Cristoforo

2016-10-01

The availability of an effective electrical model, able to accurately reproduce the signals generated by a Silicon Photo-Multiplier coupled to the front-end electronics, is mandatory when the performance of a detection system based on this kind of detector has to be evaluated by means of reliable simulations. We propose a complete extraction procedure able to provide the whole set of the parameters involved in a well-known model of the detector, which includes the substrate ohmic resistance. The technique allows achieving very good quality of the fit between simulation results provided by the model and experimental data, thanks to accurate discrimination between the quenching and substrate resistances, which results in a realistic set of extracted parameters. The extraction procedure has been applied to a commercial device considering a wide range of different conditions in terms of input resistance of the front-end electronics and interconnection parasitics. In all the considered situations, very good correspondence has been found between simulations and measurements, especially for what concerns the leading edge of the current pulses generated by the detector, which strongly affects the timing performance of the detection system, thus confirming the effectiveness of the model and the associated parameter extraction technique.

Verification of the Sentinel-4 focal plane subsystem

NASA Astrophysics Data System (ADS)

Williges, Christian; Uhlig, Mathias; Hilbert, Stefan; Rossmann, Hannes; Buchwinkler, Kevin; Babben, Steffen; Sebastian, Ilse; Hohn, Rüdiger; Reulke, Ralf

2017-09-01

The Sentinel-4 payload is a multi-spectral camera system, designed to monitor atmospheric conditions over Europe from a geostationary orbit. The German Aerospace Center, DLR Berlin, conducted the verification campaign of the Focal Plane Subsystem (FPS) during the second half of 2016. The FPS consists, of two Focal Plane Assemblies (FPAs), two Front End Electronics (FEEs), one Front End Support Electronic (FSE) and one Instrument Control Unit (ICU). The FPAs are designed for two spectral ranges: UV-VIS (305 nm - 500 nm) and NIR (750 nm - 775 nm). In this publication, we will present in detail the set-up of the verification campaign of the Sentinel-4 Qualification Model (QM). This set up will also be used for the upcoming Flight Model (FM) verification, planned for early 2018. The FPAs have to be operated at 215 K +/- 5 K, making it necessary to exploit a thermal vacuum chamber (TVC) for the test accomplishment. The test campaign consists mainly of radiometric tests. This publication focuses on the challenge to remotely illuminate both Sentinel-4 detectors as well as a reference detector homogeneously over a distance of approximately 1 m from outside the TVC. Selected test analyses and results will be presented.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Abgrall, N.; Aguayo, Estanislao; Avignone, F. T.

The MAJORANA DEMONSTRATOR will search for the neutrinoless double beta decay (ββ(0ʋ) of the isotope 76Ge with a mixed array of enriched and natural Germanium detectors. In view of the next generation of tonne-scale germanium-based (ββ(0ʋ)-decay searches, a major goal of the MAJORANA DEMONSTRATOR is to demonstrate a path forward to achieving a background rate at or below 1 cnt/(ROI-t-y) in the 4 keV region of interest (ROI) around the 2039-keV Q-value of the 76Ge (ββ(0ʋ)-decay. Such a requirement on the background level significantly constrains the design of the readout electronics, which is further driven by noise and energy resolutionmore » performances. We present here the low-noise low background front-end electronics developed for the low-capacitance p-type point contact (P-PC) germanium detectors of the MAJORANA DEMONSTRATOR. This resistive-feedback front-end, specifically designed to have low mass, is fabricated on a radioassayed fused-silica substrate where the feedback resistor consists of a sputtered thin film of high purity amorphous germanium and the feedback capacitor is based on the capacitance between gold conductive traces.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Smith, Leon E.; Conrad, Ryan C.; Keller, Daniel T.

The International Atomic Energy Agency (IAEA) deploys unattended monitoring systems to provide continuous monitoring of nuclear material within safeguarded facilities around the world. As the number of unattended monitoring instruments increases, the IAEA is challenged to become more efficient in the implementation of those systems. In 2010, the IAEA initiated the Front-End Electronics for Unattended Measurement (FEUM) project with the goals of greater flexibility in the interfaces to various sensors and data acquisition systems, and improved capabilities for remotely located sensors (e.g., where sensor and front-end electronics might be separated by tens of meters). In consultation with the IAEA, amore » technical evaluation of a candidate FEUM device produced by a commercial vendor is being performed. This evaluation is assessing the device against the IAEA’s original technical specifications and a broad range of important parameters that included sensor types, cable types, and industrial electromagnetic noise that can degrade signals from remotely located detectors. Testing has been performed in a laboratory and also in environments representative of IAEA deployments. The results are expected to inform the IAEA about where and how FEUM devices might be implemented in the field. Data and preliminary findings from the testing performed to date are presented.« less

Commissioning of the CMS Hadron Forward Calorimeters Phase I Upgrade

NASA Astrophysics Data System (ADS)

Bilki, B.; Onel, Y.

2018-03-01

The final phase of the CMS Hadron Forward Calorimeters Phase I Upgrade was performed during the Extended Year End Technical Stop of 2016-2017. In the framework of the upgrade, the PMT boxes were reworked to implement two channel readout in order to exploit the benefits of the multi-anode PMTs in background tagging and signal recovery. The front-end electronics were also upgraded to QIE10-based electronics which implement larger dynamic range and a 6-bit TDC. Following this major upgrade, the Hadron Forward Calorimeters were commissioned for operation readiness in 2017. Here we describe the details and the components of the upgrade, and discuss the operational experience and results obtained during the upgrade and commissioning.

Tevatron beam position monitor upgrade

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wolbers, Stephen; Banerjee, B.; Barker, B.

2005-05-01

The Tevatron Beam Position Monitor (BPM) readout electronics and software have been upgraded to improve measurement precision, functionality and reliability. The original system, designed and built in the early 1980's, became inadequate for current and future operations of the Tevatron. The upgraded system consists of 960 channels of new electronics to process analog signals from 240 BPMs, new front-end software, new online and controls software, and modified applications to take advantage of the improved measurements and support the new functionality. The new system reads signals from both ends of the existing directional stripline pickups to provide simultaneous proton and antiprotonmore » position measurements. Measurements using the new system are presented that demonstrate its improved resolution and overall performance.« less

CMOS Image Sensors: Electronic Camera On A Chip

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

Towards a Reduced-Wire Interface for CMUT-Based Intravascular Ultrasound Imaging Systems

PubMed Central

Lim, Jaemyung; Tekes, Coskun; Degertekin, F. Levent; Ghovanloo, Maysam

2016-01-01

Having intravascular ultrasound (IVUS) imaging capability on guide wires used in cardiovascular interventions may eliminate the need for separate IVUS catheters and expand the use of IVUS in a larger portion of the vasculature. High frequency capacitive micro machined ultrasonic transducer (CMUT) arrays should be integrated with interface electronics and placed on the guide wire for this purpose. Besides small size, this system-on-a-chip (SoC) front-end should connect to the back-end imaging system with a minimum number of wires to preserve the critical mechanical properties of the guide wire. We present a 40 MHz CMUT array interface SoC, which will eventually use only two wires for power delivery and transmits image data using a combination of analog-to-time conversion (ATC) and an impulse radio ultra-wideband (IR-UWB) wireless link. The proof-of-concept prototype ASIC consumes only 52.8 mW and occupies 4.07 mm2 in a 0.35-μm standard CMOS process. A rectifier and regulator power the rest of the SoC at 3.3 V from a 10 MHz power carrier that is supplied through a 2.4 m micro-coax cable with an overall efficiency of 49.1%. Echo signals from an 8-element CMUT array are amplified by a transimpedance amplifier (TIA) array and down-converted to baseband by quadrature sampling using a 40 MHz clock, derived from the power carrier. The ATC generates pulse-width-modulated (PWM) samples at 2 × 10 MS/s with 6 bit resolution, while the entire system achieved 5.1 ENOB. Preliminary images from the prototype system are presented, and alternative data transmission and possible future directions towards practical implementation are discussed. PMID:27662686

Towards a Reduced-Wire Interface for CMUT-Based Intravascular Ultrasound Imaging Systems.

PubMed

Lim, Jaemyung; Tekes, Coskun; Degertekin, F Levent; Ghovanloo, Maysam

2017-04-01

Having intravascular ultrasound (IVUS) imaging capability on guide wires used in cardiovascular interventions may eliminate the need for separate IVUS catheters and expand the use of IVUS in a larger portion of the vasculature. High frequency capacitive micro machined ultrasonic transducer (CMUT) arrays should be integrated with interface electronics and placed on the guide wire for this purpose. Besides small size, this system-on-a-chip (SoC) front-end should connect to the back-end imaging system with a minimum number of wires to preserve the critical mechanical properties of the guide wire. We present a 40 MHz CMUT array interface SoC, which will eventually use only two wires for power delivery and transmits image data using a combination of analog-to-time conversion (ATC) and an impulse radio ultra-wideband (IR-UWB) wireless link. The proof-of-concept prototype ASIC consumes only 52.8 mW and occupies 4.07 [Formula: see text] in a 0.35- [Formula: see text] standard CMOS process. A rectifier and regulator power the rest of the SoC at 3.3 V from a 10 MHz power carrier that is supplied through a 2.4 m micro-coax cable with an overall efficiency of 49.1%. Echo signals from an 8-element CMUT array are amplified by a transimpedance amplifier (TIA) array and down-converted to baseband by quadrature sampling using a 40 MHz clock, derived from the power carrier. The ATC generates pulse-width-modulated (PWM) samples at 2 × 10 MS/s with 6 bit resolution, while the entire system achieved 5.1 ENOB. Preliminary images from the prototype system are presented, and alternative data transmission and possible future directions towards practical implementation are discussed.

Reliability of Semiconductor Laser Packaging in Space Applications

NASA Technical Reports Server (NTRS)

Gontijo, Ivair; Qiu, Yueming; Shapiro, Andrew A.

2008-01-01

A typical set up used to perform lifetime tests of packaged, fiber pigtailed semiconductor lasers is described, as well as tests performed on a set of four pump lasers. It was found that two lasers failed after 3200, and 6100 hours under device specified bias conditions at elevated temperatures. Failure analysis of the lasers indicates imperfections and carbon contamination of the laser metallization, possibly from improperly cleaned photo resist. SEM imaging of the front facet of one of the lasers, although of poor quality due to the optical fiber charging effects, shows evidence of catastrophic damage at the facet. More stringent manufacturing controls with 100% visual inspection of laser chips are needed to prevent imperfect lasers from proceeding to packaging and ending up in space applications, where failure can result in the loss of a space flight mission.

Spectrally tunable, temporally shaped parametric front end to seed high-energy Nd:glass laser systems

DOE PAGES

Dorrer, C.; Consentino, A.; Cuffney, R.; ...

2017-10-18

Here, we describe a parametric-amplification–based front end for seeding high-energy Nd:glass laser systems. The front end delivers up to 200 mJ by parametric amplification in 2.5-ns flat-in-time pulses tunable over more than 15 nm. Spectral tunability over a range larger than what is typically achieved by laser media at similar energy levels is implemented to investigate cross-beam energy transfer in multibeam target experiments. The front-end operation is simulated to explain the amplified signal’s sensitivity to the input pump and signal. A large variety of amplified waveforms are generated by closed-loop pulse shaping. Various properties and limitations of this front endmore » are discussed.« less

Spectrally tunable, temporally shaped parametric front end to seed high-energy Nd:glass laser systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dorrer, C.; Consentino, A.; Cuffney, R.

Here, we describe a parametric-amplification–based front end for seeding high-energy Nd:glass laser systems. The front end delivers up to 200 mJ by parametric amplification in 2.5-ns flat-in-time pulses tunable over more than 15 nm. Spectral tunability over a range larger than what is typically achieved by laser media at similar energy levels is implemented to investigate cross-beam energy transfer in multibeam target experiments. The front-end operation is simulated to explain the amplified signal’s sensitivity to the input pump and signal. A large variety of amplified waveforms are generated by closed-loop pulse shaping. Various properties and limitations of this front endmore » are discussed.« less

77 FR 22760 - Proposed Information Collection; Comment Request; Southeast Region Gulf of Mexico Electronic...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-04-17

... electronic logbook memory chip will be removed from the unit and downloaded at the contractor site in College Station, Texas. A new logbook memory chip will replace the removed memory chip, a process taking less than...

Electronics for a prototype variable field of view PET camera using the PMT-quadrant-sharing detector array

NASA Astrophysics Data System (ADS)

Li, H.; Wong, Wai-Hoi; Zhang, N.; Wang, J.; Uribe, J.; Baghaei, H.; Yokoyama, S.

1999-06-01

Electronics for a prototype high-resolution PET camera with eight position-sensitive detector modules has been developed. Each module has 16 BGO (Bi/sub 4/Ge/sub 3/O/sub 12/) blocks (each block is composed of 49 crystals). The design goals are component and space reduction. The electronics is composed of five parts: front-end analog processing, digital position decoding, fast timing, coincidence processing and master data acquisition. The front-end analog circuit is a zone-based structure (each zone has 3/spl times/3 PMTs). Nine ADCs digitize integration signals of an active zone identified by eight trigger clusters; each cluster is composed of six photomultiplier tubes (PMTs). A trigger corresponding to a gamma ray is sent to a fast timing board to obtain a time-mark, and the nine digitized signals are passed to the position decoding board, where a real block (four PMTs) can be picked out from the zone for position decoding. Lookup tables are used for energy discrimination and to identify the gamma-hit crystal location. The coincidence board opens a 70-ns initial timing window, followed by two 20-ns true/accidental time-mark lookup table windows. The data output from the coincidence board can be acquired either in sinogram mode or in list mode with a Motorola/IRONICS VME-based system.

Front End Software for Online Database Searching Part 1: Definitions, System Features, and Evaluation.

ERIC Educational Resources Information Center

Hawkins, Donald T.; Levy, Louise R.

1985-01-01

This initial article in series of three discusses barriers inhibiting use of current online retrieval systems by novice users and notes reasons for front end and gateway online retrieval systems. Definitions, front end features, user interface, location (personal computer, host mainframe), evaluation, and strengths and weaknesses are covered. (16…

Thin hybrid pixel assembly with backside compensation layer on ROIC

NASA Astrophysics Data System (ADS)

Bates, R.; Buttar, C.; McMullen, T.; Cunningham, L.; Ashby, J.; Doherty, F.; Gray, C.; Pares, G.; Vignoud, L.; Kholti, B.; Vahanen, S.

2017-01-01

The entire ATLAS inner tracking system will be replaced for operation at the HL-LHC . This will include a significantly larger pixel detector of approximately 15 m2. For this project, it is critical to reduce the mass of the hybrid pixel modules and this requires thinning both the sensor and readout chips to about 150 micrometres each. The thinning of the silicon chips leads to low bump yield for SnAg bumps due to bad co-planarity of the two chips at the solder reflow stage creating dead zones within the pixel array. In the case of the ATLAS FEI4 pixel readout chip thinned to 100 micrometres, the chip is concave, with the front side in compression, with a bow of +100 micrometres at room temperature which varies to a bow of -175 micrometres at the SnAg solder reflow temperature, caused by the CTE mismatch between the materials in the CMOS stack and the silicon substrate. A new wafer level process to address the issue of low bump yield be controlling the chip bow has been developed. A back-side dielectric and metal stack of SiN and Al:Si has been deposited on the readout chip wafer to dynamically compensate the stress of the front side stack. In keeping with a 3D process the materials used are compatible with Through Silicon Via (TSV) technology with a TSV last approach which is under development for this chip. It is demonstrated that the amplitude of the correction can be manipulated by the deposition conditions and thickness of the SiN/Al:Si stack. The bow magnitude over the temperature range for the best sample to date is reduced by almost a factor of 4 and the sign of the bow (shape of the die) remains constant. Further development of the backside deposition conditions is on-going with the target of close to zero bow at the solder reflow temperature and a minimal bow magnitude throughout the temperature range. Assemblies produced from FEI4 readout wafers thinned to 100 micrometres with the backside compensation layer have been made for the first time and demonstrate bond yields close to 100%.

Multiphysical FE-analysis of a front-end bending phenomenon in a hot strip mill

NASA Astrophysics Data System (ADS)

Ilmola, Joonas; Seppälä, Oskari; Leinonen, Olli; Pohjonen, Aarne; Larkiola, Jari; Jokisaari, Juha; Putaansuu, Eero

2018-05-01

In hot steel rolling processes, a slab is generally rolled to a transfer bar in a roughing process and to a strip in a hot strip rolling process. Over several rolling passes the front-end may bend upward or downward due to asymmetrical rolling conditions causing entry problems in the next rolling pass. Many different factors may affect the front-end bending phenomenon and are very challenging to measure. Thus, a customized finite element model is designed and built to simulate the front-end bending phenomenon in a hot strip rolling process. To simulate the functioning of the hot strip mill precisely, automated controlling logic of the mill must be considered. In this paper we studied the effect of roll bite friction conditions and amount of reduction on the front-end bending phenomenon in a hot strip rolling process.

VLBI2010 Receiver Back End Comparison

NASA Technical Reports Server (NTRS)

Petrachenko, Bill

2013-01-01

VLBI2010 requires a receiver back-end to convert analog RF signals from the receiver front end into channelized digital data streams to be recorded or transmitted electronically. The back end functions are typically performed in two steps: conversion of analog RF inputs into IF bands (see Table 2), and conversion of IF bands into channelized digital data streams (see Tables 1a, 1b and 1c). The latter IF systems are now completely digital and generically referred to as digital back ends (DBEs). In Table 2 two RF conversion systems are compared, and in Tables 1a, 1b, and 1c nine DBE systems are compared. Since DBE designs are advancing rapidly, the data in these tables are only guaranteed to be current near the update date of this document.

Compact spectrometer for precision studies of multimode behavior in an extended-cavity diode laser

NASA Astrophysics Data System (ADS)

Roach, Timothy; Golemi, Josian; Krueger, Thomas

2016-05-01

We have built a compact, inexpensive, high-precision spectrometer and used it to investigate the tuning behavior of a grating stabilized extended-cavity diode laser (ECDL). A common ECDL design uses a laser chip with an uncoated (partially reflecting) front facet, and the laser output exhibits a complicated pattern of mode hops as the frequency is tuned, in some cases even showing chaotic dynamics. Our grating spectrometer (based on a design by White & Scholten) monitors a span of 4000 GHz (8 nm at 780 nm) with a linewidth of 3 GHz, which with line-splitting gives a precision of 0.02 GHz in determining the frequency of a laser mode. We have studied multimode operation of the ECDL, tracking two or three simultaneous chip cavity modes (spacing ~ 30 GHz) during tuning via current or piezo control of the external cavity. Simultaneous output on adjacent external cavity modes (spacing ~ 5 GHz) is monitored by measuring an increase in the spectral linewidth. Computer-control of the spectrometer (for line-fitting and averaging) and of the ECDL (electronic tuning) allows rapid collection of spectral data sets, which we will use to test mathematical simulation models of the non-linear laser cavity interactions.

A data transmission method for particle physics experiments based on Ethernet physical layer

NASA Astrophysics Data System (ADS)

Huang, Xi-Ru; Cao, Ping; Zheng, Jia-Jun

2015-11-01

Due to its advantages of universality, flexibility and high performance, fast Ethernet is widely used in readout system design for modern particle physics experiments. However, Ethernet is usually used together with the TCP/IP protocol stack, which makes it difficult to implement readout systems because designers have to use the operating system to process this protocol. Furthermore, TCP/IP degrades the transmission efficiency and real-time performance. To maximize the performance of Ethernet in physics experiment applications, a data readout method based on the physical layer (PHY) is proposed. In this method, TCP/IP is replaced with a customized and simple protocol, which makes it easier to implement. On each readout module, data from the front-end electronics is first fed into an FPGA for protocol processing and then sent out to a PHY chip controlled by this FPGA for transmission. This kind of data path is fully implemented by hardware. From the side of the data acquisition system (DAQ), however, the absence of a standard protocol causes problems for the network related applications. To solve this problem, in the operating system kernel space, data received by the network interface card is redirected from the traditional flow to a specified memory space by a customized program. This memory space can easily be accessed by applications in user space. For the purpose of verification, a prototype system has been designed and implemented. Preliminary test results show that this method can meet the requirements of data transmission from the readout module to the DAQ with an efficient and simple manner. Supported by National Natural Science Foundation of China (11005107) and Independent Projects of State Key Laboratory of Particle Detection and Electronics (201301)

The plastic scintillator detector calibration circuit for DAMPE

NASA Astrophysics Data System (ADS)

Yang, Haibo; Kong, Jie; Zhao, Hongyun; Su, Hong

2016-07-01

The Dark Matter Particle Explorer (DAMPE) is being constructed as a scientific satellite to observe high energy cosmic rays in space. Plastic scintillator detector array (PSD), developed by Institute of Modern Physics, Chinese Academy of Sciences (IMPCAS), is one of the most important parts in the payload of DAMPE which is mainly used for the study of dark matter. As an anti-coincidence detector, and a charged-particle identification detector, the PSD has a total of 360 electronic readout channels, which are distributed at four sides of PSD using four identical front end electronics (FEE). Each FEE reads out 90 charge signals output by the detector. A special calibration circuit is designed in FEE. FPGA is used for on-line control, enabling the calibration circuit to generate the pulse signal with known charge. The generated signal is then sent to the FEE for calibration and self-test. This circuit mainly consists of DAC, operation amplifier, analog switch, capacitance and resistance. By using controllable step pulse, the charge can be coupled to the charge measuring chip using the small capacitance. In order to fulfill the system's objective of large dynamic range, the FEE is required to have good linearity. Thus, the charge-controllable signal is needed to do sweep test on all channels in order to obtain the non-linear parameters for off-line correction. On the other hand, the FEE will run on the satellite for three years. The changes of the operational environment and the aging of devices will lead to parameter variation of the FEE, highlighting the need for regular calibration. The calibration signal generation circuit also has a compact structure and the ability to work normally, with the PSD system's voltage resolution being higher than 0.6%.

An 8.4-GHz dual-maser front-end system for Parkes reimplementation

NASA Technical Reports Server (NTRS)

Trowbridge, D. L.; Loreman, J. R.; Brunzie, T. J.; Quinn, R.

1990-01-01

An 8.4-GHz front-end system consisting of a feedhorn, a waveguide feed assembly, dual masers, and downconverters was reimplemented at Parkes as part of the Parkes Canberra Telemetry Array for the Voyager Neptune encounter. The front-end system was originally assembled by the European Space Agency and installed on the Parkes antenna for the Giotto project. It was also used on a time-sharing basis by the Deep Space Network as part of the Parkes Canberra Telemetry Array to enhance the data return from the Voyager Uranus encounter. At the conclusion of these projects in 1986, part of the system was then shipped to JPL on loan for reimplementation at Parkes for the Voyager Neptune encounter. New design and implementation required to make the system operable at Parkes included new microwave front-end control cabinets, closed-cycle refrigeration monitor system, noise-adding radiometer system, front-end controller assembly, X81 local oscillator multiplier, and refurbishment of the original dual 8.4-GHz traveling-wave masers and waveguide feed system. The front-end system met all requirements during the encounter and was disassembled in October 1989 and returned to JPL.

Biomimetic engineering of a generic cell-on-membrane architecture by microfluidic engraving for on-chip bioassays.

PubMed

Lee, Sang-Wook; Noh, Ji-Yoon; Park, Seung Chul; Chung, Jin-Ho; Lee, Byoungho; Lee, Sin-Doo

2012-05-22

We develop a biomimetic cell-on-membrane architecture in close-volume format which allows the interfacial biocompatibility and the reagent delivery capability for on-chip bioassays. The key concept lies in the microfluidic engraving of lipid membranes together with biological cells on a supported substrate with topographic patterns. The simultaneous engraving process of a different class of fluids is promoted by the front propagation of an air-water interface inside a flow-cell. This highly parallel, microfluidic cell-on-membrane approach opens a door to the natural biocompatibility in mimicking cellular stimuli-response behavior essential for diverse on-chip bioassays that can be precisely controlled in the spatial and temporal manner.

Silver flip chip interconnect technology and solid state bonding

NASA Astrophysics Data System (ADS)

Sha, Chu-Hsuan

In this dissertation, fluxless transient liquid phase (TLP) bonding and solid state bonding between thermal expansion mismatch materials have been developed using Ag-In binary systems, pure Au, Ag, and Cu-Ag composite. In contrast to the conventional soldering process, fluxless bonding technique eliminates any corrosion and contamination problems caused by flux. Without flux, it is possible to fabricate high quality joints in large bonding areas where the flux is difficult to clean entirely. High quality joints are crucial to bonding thermal expansion mismatch materials since shear stress develops in the bonded pair. Stress concentration at voids in joints could increases breakage probability. In addition, intermetallic compound (IMC) formation between solder and underbump metallurgy (UBM) is essential for interconnect joint formation in conventional soldering process. However, the interface between IMC and solder is shown to be the weak interface that tends to break first during thermal cycling and drop tests. In our solid state bonding technique, there is no IMC involved in the bonding between Au to Au, Ag and Cu, and Ag and Au. All the reliability issues related to IMC or IMC growth is not our concern. To sum up, ductile bonding media, such as Ag or Au, and proper metallic layered structure are utilized in this research to produce high quality joints. The research starts with developing a low temperature fluxless bonding process using electroplated Ag/In/Ag multilayer structures between Si chip and 304 stainless steel (304SS) substrate. Because the outer thin Ag layer effectively protects inner In layer from oxidation, In layer dissolves Ag layer and joints to Ag layer on the to-be-bonded Si chip when temperature reaches the reflow temperature of 166ºC. Joints consist of mainly Ag-rich Ag-In solid solution and Ag2In. Using this fluxless bonding technique, two 304SS substrates can be bonded together as well. From the high magnification SEM images taken at cross-section, there is no void or gap observed. The new bonding technique presented should be valuable in packaging high power electronic devices for high temperature operations. It should also be useful to bond two 304SS parts together at low bonding temperature of 190ºC. Solid state bonding technique is then introduced to bond semiconductor chips, such as Si, to common substrates, such as Cu or alumina, using pure Ag and Au at a temperature matching the typical reflow temperature used in packaging industries, 260°C. In bonding, we realize the possibilities of solid state bonding of Au to Au, Au to Ag, and Ag to Cu. The idea comes from that Cu, Ag, and Au are located in the same column on periodic table, meaning that they have similar electronic configuration. They therefore have a better chance to share electrons. Also, the crystal lattice of Cu, Ag, and Au is the same, face-centered cubic. In the project, the detailed bonding mechanism is beyond the scope and here we determine the bonding by the experimental result. Ag is chosen as the joint material because of its superior physical properties. It has the highest electrical and thermal conductivities among all metals. It has low yield strength and is relatively ductile. Au is considered as well because its excellent ductility and fatigue resistance. Thus, the Ag or Au joints can deform to accommodate the shear strain caused by CTE mismatch between Si and Cu. Ag and Au have melting temperatures higher than 950°C, so the pure Ag or Au joints are expected to sustain in high operating temperature. The resulting joints do not contain any intermetallic compound. Thus, all reliability issues associated with intermetallic growth in commonly used solder joints do not exist anymore. We finally move to the applications of solid state Ag bonding in flip chip interconnects design. At present, nearly all large-scale integrated circuit (IC) chips are packaged with flip-chip technology. This means that the chip is flipped over and the active (front) side is connected to the package using a large number of tiny solder joints, which provide mechanical support, electrical connection, and heat conduction. For chip-to-package level interconnects, a challenge is the severe mismatch in coefficient of thermal expansion (CTE) between chips and package substrates. The interconnect material thus needs to be compliant to deal with the CTE mismatch. At present, nearly all flip-chip interconnects in electronic industries are made of lead-free Sn-based solders. Soft solders are chosen due to high ductility, low yield strength, relatively low melting temperature, and reasonably good electrical and thermal conductivities. In the never ending scaling down trend, more and more transistors are placed on the same Si chip size. This results in larger pin-out numbers and smaller solder joints. According to International Technology Roadmap for Semiconductors (ITRS), by 2018, the pitch in flip-chip interconnects will become smaller than 70mum for high performance applications. Two problems occur. The first is increase in shear strain. The aspect ratio of flip-chip joints is constrained to 0.7 because it goes through molten phase in the reflow process. Therefore, smaller joints become shorter as well, resulting in larger shear strain arising from CTE mismatch between Si chips and package substrates. The second is increase in stress in the joints. Since intermetallic (IMC) thickness in the joint does not scale down with joint size, ratio of IMC thickness to joint height increases. This further enlarges the shear stress because the IMC does not deform as the soft solder does to accommodate CTE mismatch. In this research, the smallest dimension we achieve for Ag flip chip interconnect joint is 15mum in diameter. The ten advantages of Ag flip chip interconnect technology can be identified as (a) High electrical conductivity, 7.7 times of that of Pb-free solders, (b) High thermal conductivity, 5.2 times of that of Pb-free solders, (c) Completely fluxless, (d) No IMCs; all reliability issues associated with IMC and IMC growth do not exist, (e) Ag is very ductile and can manage CTE mismatch between chips and packages, (f) Ag joints can sustain at very high operation temperature because Ag has high melting temperature of 961°C, (g) No molten phase involved; the bump can better keep its shape and geometry, (h) No molten phase involved; bridging of adjacent bumps is less likely to occur, i. Aspect ratio of bumps can be made greater than 1, (j) The size of the bumps is only limited by the lithographic process. Cu-Ag composite flip chip interconnect joints is developed based on three reasons. The first is lower material cost. The second is to strengthen the columns because the yield strength of Cu is 6 times of that of Ag. The third is to avoid possible Ag migration between Ag electrodes under voltage at temperatures above 250°C. This Cu-Ag composite design presents a solution in the path to the scale down roadmap.

Percussive arc welding apparatus

DOEpatents

Hollar, Jr., Donald L.

2002-01-01

A percussive arc welding apparatus includes a generally cylindrical actuator body having front and rear end portions and defining an internal recess. The front end of the body includes an opening. A solenoid assembly is provided in the rear end portion in the internal recess of the body, and an actuator shaft assembly is provided in the front end portion in the internal recess of the actuator body. The actuator shaft assembly includes a generally cylindrical actuator block having first and second end portions, and an actuator shaft having a front end extending through the opening in the actuator body, and the rear end connected to the first end portion of the actuator block. The second end portion of the actuator block is in operational engagement with the solenoid shaft by a non-rigid connection to reduce the adverse rebound effects of the actuator shaft. A generally transversely extending pin is rigidly secured to the rear end of the shaft. One end of the pin is received in a slot in the nose housing sleeve to prevent rotation of the actuator shaft during operation of the apparatus.

[Test of thermal deformation for electronic devices of high thermal reliability].

PubMed

Li, Hai-yuan; Li, Bao-ming

2002-06-01

Thermal deformation can be caused by high partial heat flux and greatly reduce thermal reliability of electronic devices. In this paper, an attempt is made to measure the thermal deformation of high power electronic devices under working condition using laser holographic interferometry with double exposure. Laser holographic interferometry is an untouched measurement with measurement precision up to micron dimension. The electronic device chosen for measurement is a type of solid state relay which is used for ignition of rockets. The output circuit of the solid state relay is made up of a MOSFET chip and the power density of the chip can reach high value. In particular situations thermal deformation and stress may significantly influence working performance of the solid state relay. The bulk deformation of the chip and its mount is estimated by number of interferential stripes on chip surface. While thermal stress and deformation can be estimated by curvature of interferential stripes on chip surface. Experimental results indicate that there are more interferential stripes on chip surface and greater flexural degree of stripes under high power. Therefore, these results reflect large out-of-plain displacement and deformed size of the chip with the increase of load current.

Front-End Board with Cyclone V as a Test High-Resolution Platform for the Auger_Beyond_2015 Front End Electronics

NASA Astrophysics Data System (ADS)

Szadkowski, Zbigniew

2015-06-01

The surface detector (SD) array of the Pierre Auger Observatory needs an upgrade which allows space for more complex triggers with higher bandwidth and greater dynamic range. To this end this paper presents a front-end board (FEB) with the largest Cyclone V E FPGA 5CEFA9F31I7N. It supports eight channels sampled with max. 250 MSps@14-bit resolution. Considered sampling for the SD is 120 MSps; however, the FEB has been developed with external anti-aliasing filters to retain maximal flexibility. Six channels are targeted at the SD, two are reserved for other experiments like: Auger Engineering Radio Array and additional muon counters. The FEB is an intermediate design plugged into a unified board communicating with a micro-controller at 40 MHz; however, it provides 250 MSPs sampling with an 18-bit dynamic range, is equipped with a virtual NIOS processor and supports 256 MB of SDRAM as well as an implemented spectral trigger based on the discrete cosine transform for detection of very inclined “old” showers. The FEB can also support neural network development for detection of “young” showers, potentially generated by neutrinos. A single FEB was already tested in the Auger surface detector in Malargüe (Argentina) for 120 and 160 MSps. Preliminary tests showed perfect stability of data acquisition for sampling frequency three or four times greater. They allowed optimization of the design before deployment of seven or eight FEBs for several months of continuous tests in the engineering array.

Measurements of the effects of wine maceration with oak chips using an electronic tongue.

PubMed

Rudnitskaya, Alisa; Schmidtke, Leigh M; Reis, Ana; Domingues, M Rosario M; Delgadillo, Ivonne; Debus, Bruno; Kirsanov, Dmitry; Legin, Andrey

2017-08-15

The use of oak products as a cheaper alternative to expensive wood barrels was recently permitted in Europe, which led to a continuous increase in the use of oak chips and staves in winemaking. The feasibility of the potentiometric electronic tongue as a tool for monitoring the effects of wine maceration with oak chips was evaluated. Four types of commercially available oak chips subjected to different thermal treatments and washing procedures and their mixture were studied. Ethanolic extracts of the chips were analysed using electrospray mass spectrometry and 28 phenolic and furanic compounds were identified. The electronic tongue comprising 22 potentiometric chemical sensors could distinguish artificial wine solutions and Cabernet Sauvignon wine macerated with different types of oak chips, quantify total and non-flavonoid phenolic content, as well as the concentrations of added oak chips. Using measurements at two pH levels, 3.2 and 6.5, improved the accuracy of quantification. Copyright © 2017 Elsevier Ltd. All rights reserved.

A Low-Cost and Secure Solution for e-Commerce

NASA Astrophysics Data System (ADS)

Pasquet, Marc; Vacquez, Delphine; Rosenberger, Christophe

We present in this paper a new architecture for remote banking and e-commerce applications. The proposed solution is designed to be low cost and provides some good guarantees of security for a client and his bank issuer. Indeed, the main problem for an issuer is to identify and authenticate one client (a cardholder) using his personal computer through the web when this client wants to access to remote banking services or when he wants to pay on a e-commerce site equipped with 3D-secure payment solution. The proposed solution described in this paper is MasterCard Chip Authentication Program compliant and was experimented in the project called SOPAS. The main contribution of this system consists in the use of a smartcard with a I2C bus that pilots a terminal only equipped with a screen and a keyboard. During the use of services, the user types his PIN code on the keyboard and all the security part of the transaction is performed by the chip of the smartcard. None information of security stays on the personal computer and a dynamic token created by the card is sent to the bank and verified by the front end. We present first the defined methodology and we analyze the main security aspects of the proposed solution.

ISFET-based sensor signal processor chip design for environment monitoring applications

NASA Astrophysics Data System (ADS)

Chung, Wen-Yaw; Yang, Chung-Huang; Wang, Ming-Ga

2004-12-01

In recent years Ion-Sensitive Field Effect Transistor (ISFET) based transducers create valuable applications in physiological data acquisition and environment monitoring. This paper presents a mixed-mode ASIC design for potentiometric ISFET-based bio-chemical sensor applications including H+ sensing and hand-held pH meter. For battery power consideration, the proposed system consists of low voltage (3V) analog front-end readout circuits and digital processor has been developed and fabricated in a 0.5mm double-poly double-metal CMOS technology. To assure that the correct pH value can be measured, the two-point calibration circuitry based on the response of standard pH4 and pH7 buffer solution has been implemented by using algorithmic state machine hardware algorithms. The measurement accuracy of the chip is 10 bits and the measured range between pH 2 to pH 12 compared to ideal values is within the accuracy of 0.1pH. For homeland environmental applications, the system provide rapid, easy to use, and cost-effective on-site testing on the quality of water, such as drinking water, ground water and river water. The processor has a potential usage in battery-operated and portable devices in environmental monitoring applications compared to commercial hand-held pH meter.

49 CFR Appendix F to Part 238 - Alternative Dynamic Performance Requirements for Front End Structures of Cab Cars and MU Locomotives

Code of Federal Regulations, 2013 CFR

2013-10-01

... of cab cars and MU locomotives with shaped-noses or crash energy management designs, or both. In any... Front End Structures of Cab Cars and MU Locomotives F Appendix F to Part 238 Transportation Other... Performance Requirements for Front End Structures of Cab Cars and MU Locomotives As specified in § 238.209(b...

49 CFR Appendix F to Part 238 - Alternative Dynamic Performance Requirements for Front End Structures of Cab Cars and MU Locomotives

Code of Federal Regulations, 2012 CFR

2012-10-01

... of cab cars and MU locomotives with shaped-noses or crash energy management designs, or both. In any... Front End Structures of Cab Cars and MU Locomotives F Appendix F to Part 238 Transportation Other... Performance Requirements for Front End Structures of Cab Cars and MU Locomotives As specified in § 238.209(b...

49 CFR Appendix F to Part 238 - Alternative Dynamic Performance Requirements for Front End Structures of Cab Cars and MU Locomotives

Code of Federal Regulations, 2011 CFR

2011-10-01

... of cab cars and MU locomotives with shaped-noses or crash energy management designs, or both. In any... Front End Structures of Cab Cars and MU Locomotives F Appendix F to Part 238 Transportation Other... Performance Requirements for Front End Structures of Cab Cars and MU Locomotives As specified in § 238.209(b...

49 CFR Appendix F to Part 238 - Alternative Dynamic Performance Requirements for Front End Structures of Cab Cars and MU Locomotives

Code of Federal Regulations, 2014 CFR

2014-10-01

... of cab cars and MU locomotives with shaped-noses or crash energy management designs, or both. In any... Front End Structures of Cab Cars and MU Locomotives F Appendix F to Part 238 Transportation Other... Performance Requirements for Front End Structures of Cab Cars and MU Locomotives As specified in § 238.209(b...

49 CFR Appendix F to Part 238 - Alternative Dynamic Performance Requirements for Front End Structures of Cab Cars and MU Locomotives

Code of Federal Regulations, 2010 CFR

2010-10-01

... Front End Structures of Cab Cars and MU Locomotives F Appendix F to Part 238 Transportation Other... Performance Requirements for Front End Structures of Cab Cars and MU Locomotives As specified in § 238.209(b... and allow for the application of dynamic performance criteria to cab cars and MU locomotives as an...

Millimeter-wave imaging diagnostics systems on the EAST tokamak (invited)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhu, Y. L.; Xie, J. L., E-mail: jlxie@ustc.edu.cn; Yu, C. X.

2016-11-15

Millimeter-wave imaging diagnostics, with large poloidal span and wide radial range, have been developed on the EAST tokamak for visualization of 2D electron temperature and density fluctuations. A 384 channel (24 poloidal × 16 radial) Electron Cyclotron Emission Imaging (ECEI) system in F-band (90-140 GHz) was installed on the EAST tokamak in 2012 to provide 2D electron temperature fluctuation images with high spatial and temporal resolution. A co-located Microwave Imaging Reflectometry (MIR) will be installed for imaging of density fluctuations by December 2016. This “4th generation” MIR system has eight independent frequency illumination beams in W-band (75-110 GHz) driven bymore » fast tuning synthesizers and active multipliers. Both of these advanced millimeter-wave imaging diagnostic systems have applied the latest techniques. A novel design philosophy “general optics structure” has been employed for the design of the ECEI and MIR receiver optics with large aperture. The extended radial and poloidal coverage of ECEI on EAST is made possible by innovations in the design of front-end optics. The front-end optical structures of the two imaging diagnostics, ECEI and MIR, have been integrated into a compact system, including the ECEI receiver and MIR transmitter and receiver. Two imaging systems share the same mid-plane port for simultaneous, co-located 2D fluctuation measurements of electron density and temperature. An intelligent remote-control is utilized in the MIR electronics systems to maintain focusing at the desired radial region even with density variations by remotely tuning the probe frequencies in about 200 μs. A similar intelligent technique has also been applied on the ECEI IF system, with remote configuration of the attenuations for each channel.« less

Millimeter-wave imaging diagnostics systems on the EAST tokamak (invited)

NASA Astrophysics Data System (ADS)

Zhu, Y. L.; Xie, J. L.; Yu, C. X.; Zhao, Z. L.; Gao, B. X.; Chen, D. X.; Liu, W. D.; Liao, W.; Qu, C. M.; Luo, C.; Hu, X.; Spear, A. G.; Luhmann, N. C.; Domier, C. W.; Chen, M.; Ren, X.; Tobias, B. J.

2016-11-01

Millimeter-wave imaging diagnostics, with large poloidal span and wide radial range, have been developed on the EAST tokamak for visualization of 2D electron temperature and density fluctuations. A 384 channel (24 poloidal × 16 radial) Electron Cyclotron Emission Imaging (ECEI) system in F-band (90-140 GHz) was installed on the EAST tokamak in 2012 to provide 2D electron temperature fluctuation images with high spatial and temporal resolution. A co-located Microwave Imaging Reflectometry (MIR) will be installed for imaging of density fluctuations by December 2016. This "4th generation" MIR system has eight independent frequency illumination beams in W-band (75-110 GHz) driven by fast tuning synthesizers and active multipliers. Both of these advanced millimeter-wave imaging diagnostic systems have applied the latest techniques. A novel design philosophy "general optics structure" has been employed for the design of the ECEI and MIR receiver optics with large aperture. The extended radial and poloidal coverage of ECEI on EAST is made possible by innovations in the design of front-end optics. The front-end optical structures of the two imaging diagnostics, ECEI and MIR, have been integrated into a compact system, including the ECEI receiver and MIR transmitter and receiver. Two imaging systems share the same mid-plane port for simultaneous, co-located 2D fluctuation measurements of electron density and temperature. An intelligent remote-control is utilized in the MIR electronics systems to maintain focusing at the desired radial region even with density variations by remotely tuning the probe frequencies in about 200 μs. A similar intelligent technique has also been applied on the ECEI IF system, with remote configuration of the attenuations for each channel.

Repairable chip bonding/interconnect process

DOEpatents

Bernhardt, Anthony F.; Contolini, Robert J.; Malba, Vincent; Riddle, Robert A.

1997-01-01

A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.

The front-end electronics and slow control of large area SiPM for the SST-1M camera developed for the CTA experiment

NASA Astrophysics Data System (ADS)

Aguilar, J. A.; Bilnik, W.; Borkowski, J.; Cadoux, F.; Christov, A.; della Volpe, D.; Favre, Y.; Heller, M.; Kasperek, J.; Lyard, E.; Marszałek, A.; Moderski, R.; Montaruli, T.; Porcelli, A.; Prandini, E.; Rajda, P.; Rameez, M.; Schioppa, E.; Troyano Pujadas, I.; Ziȩtara, K.; Błocki, J.; Bogacz, L.; Bulik, T.; Curyło, M.; Dyrda, M.; Frankowski, A.; Grudniki, Ł.; Grudzińska, M.; Idźkowski, B.; Jamrozy, M.; Janiak, M.; Lalik, K.; Mach, E.; Mandat, D.; Michałowski, J.; Neronov, A.; Niemiec, J.; Ostrowski, M.; Paśsko, P.; Pech, M.; Schovanek, P.; Seweryn, K.; Skowron, K.; Sliusar, V.; Sowiński, M.; Stawarz, Ł.; Stodulska, M.; Stodulski, M.; Toscano, S.; Walter, R.; Wiȩcek, M.; Zagdański, A.; Żychowski, P.

2016-09-01

The single mirror Small Size Telescope (SST-1M) is one of the proposed designs for the smallest type of telescopes, SSTs that will compose the Cherenkov Telescope Array (CTA). The SST-1M camera will use Silicon PhotoMultipliers (SiPM) which are nowadays commonly used in High Energy Physics experiments and many imaging applications. However the unique pixel shape and size have required a dedicated development by the University of Geneva and Hamamatsu. The resulting sensor has a surface of ∼94 mm2 and a total capacitance of ∼3.4 nF. These unique characteristics, combined with the stringent requirements of the CTA project on timing and charge resolution have led the University of Geneva to develop custom front-end electronics. The preamplifier stage has been tailored in order to optimize the signal shape using measurement campaigns and electronic simulation of the sensor. A dedicated trans-impedance pre-amplifier topology is used resulting in a power consumption of 400 mW per pixel and a pulse width < 30 ns. The measurements that have led to the choice of the different components and the resulting performance are detailed in this paper. The slow control electronics was designed to provide the bias voltage with 6.7 mV precision and to correct for temperature variation with a forward feedback compensation with 0.17 °C resolution. It is fully configurable and can be monitored using CANbus interface. The architecture and the characterization of the various elements are presented.

CALORIC: A readout chip for high granularity calorimeter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Royer, L.; Bonnard, J.; Manen, S.

2011-07-01

A very-front-end electronics has been developed to fulfil requirements for the next generation of electromagnetic calorimeters. The compactness of this kind of detector and its large number of channels (up to several millions) impose a drastic limitation of the power consumption and a high level of integration. The electronic channel proposed is first of all composed of a low-noise Charge Sensitive Amplifier (CSA) able to amplify the charge delivered by a silicon diode up to 10 pC. Next, a two-gain shaping, based on a Gated Integration (G.I.), is implemented to cover the 15 bits dynamic range required: a high gainmore » shaper processes signals from 4 fC (charge corresponding to the MIP) up to 1 pC, and a low gain filter handles charges up to 10 pC. The G.I. performs also the analog memorization of the signal until it is digitalized. Hence, the analog-to-digital conversion is carried out through a low-power 12-bit cyclic ADC. If the signal overloads the high-gain channel dynamic range, a comparator selects the low-gain channel instead. Moreover, an auto-trigger channel has been implemented in order to select and store a valid event over the noise. The timing sequence of the channel is managed by a digital IP. It controls the G.I. switches, generates all needed clocks, drives the ADC and delivers the final result over 12 bits. The whole readout channel is power controlled, which permits to reduce the consumption according to the duty cycle of the beam collider. Simulations have been performed with Spectre simulator on the prototype chip designed with the 0.35 {mu}m CMOS technology from Austriamicrosystems. Results show a non-linearity better than 0.1% for the high-gain channel, and a non-linearity limited to 1% for the low-gain channel. The Equivalent Noise Charge referred to the input of the channel is evaluated to 0.4 fC complying with the MIP/10 limit. With the timing sequence of the International Linear Collider, which presents a duty cycle of 1%, the power consumption of the complete channel is limited to 43 {mu}W thanks to the power pulsing. The total area of the channel is 1.2 mm{sup 2} with an analog memory depth of 16. (authors)« less

A straw chambers' tracker for the high rate experiment 835 at the Fermilab accumulator

NASA Astrophysics Data System (ADS)

Bagnasco, S.; Dughera, G.; Giraudo, G.; Govi, G.; Marchetto, F.; Menichetti, E.; Pastrone, N.; Rumerio, P.; Trapani, P. P.

1998-02-01

Two layers of proportional drift tubes (aluminum mylar straws) are staggered in two cylindrical light chambers to measure charged particles' azimuthal angle. To stand the high rates (˜10 kHz/ cm2) and minimize the pile-up of the high luminosity experiment 835 at FNAL, a fast ASIC Amplifier-Shaper-Discriminator (ASD-8B) was chosen. The front-end electronics, designed exclusively with SMD components, was mounted on the downstream end plug of each chamber to avoid oscillations and noise. Design, construction and operational performances of these detectors are presented.

The modification at CSNS ion source

NASA Astrophysics Data System (ADS)

Liu, S.; Ouyang, H.; Huang, T.; Xiao, Y.; Cao, X.; Lv, Y.; Xue, K.; Chen, W.

2017-08-01

The commissioning of CSNS front end has been finished. Above 15 mA beam intensity is obtained at the end of RFQ. For CSNS ion source, it is a type of penning surface plasma ion source, similar to ISIS ion source. To improve the operation stability and reduce spark rate, some modifications have been performed, including Penning field, extraction optics and post acceleration. PBGUNS is applied to optimize beam extraction. The co-extraction electrons are considered at PBGUNS simulation and various extracted structure are simulated aiming to make the beam through the extracted electrode without loss. The stability of ion source is improved further.

Monolithic pixel development in TowerJazz 180 nm CMOS for the outer pixel layers in the ATLAS experiment

NASA Astrophysics Data System (ADS)

Berdalovic, I.; Bates, R.; Buttar, C.; Cardella, R.; Egidos Plaja, N.; Hemperek, T.; Hiti, B.; van Hoorne, J. W.; Kugathasan, T.; Mandic, I.; Maneuski, D.; Marin Tobon, C. A.; Moustakas, K.; Musa, L.; Pernegger, H.; Riedler, P.; Riegel, C.; Schaefer, D.; Schioppa, E. J.; Sharma, A.; Snoeys, W.; Solans Sanchez, C.; Wang, T.; Wermes, N.

2018-01-01

The upgrade of the ATLAS tracking detector (ITk) for the High-Luminosity Large Hadron Collider at CERN requires the development of novel radiation hard silicon sensor technologies. Latest developments in CMOS sensor processing offer the possibility of combining high-resistivity substrates with on-chip high-voltage biasing to achieve a large depleted active sensor volume. We have characterised depleted monolithic active pixel sensors (DMAPS), which were produced in a novel modified imaging process implemented in the TowerJazz 180 nm CMOS process in the framework of the monolithic sensor development for the ALICE experiment. Sensors fabricated in this modified process feature full depletion of the sensitive layer, a sensor capacitance of only a few fF and radiation tolerance up to 1015 neq/cm2. This paper summarises the measurements of charge collection properties in beam tests and in the laboratory using radioactive sources and edge TCT. The results of these measurements show significantly improved radiation hardness obtained for sensors manufactured using the modified process. This has opened the way to the design of two large scale demonstrators for the ATLAS ITk. To achieve a design compatible with the requirements of the outer pixel layers of the tracker, a charge sensitive front-end taking 500 nA from a 1.8 V supply is combined with a fast digital readout architecture. The low-power front-end with a 25 ns time resolution exploits the low sensor capacitance to reduce noise and analogue power, while the implemented readout architectures minimise power by reducing the digital activity.

Fully Integrated Biopotential Acquisition Analog Front-End IC

PubMed Central

Song, Haryong; Park, Yunjong; Kim, Hyungseup; Ko, Hyoungho

2015-01-01

A biopotential acquisition analog front-end (AFE) integrated circuit (IC) is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA) to achieve low input referred noise (IRN) and to block unwanted DC potential signals. A DC servo loop (DSL) is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL) is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL) is designed to enhance the input impedance and common mode rejection ratio (CMRR) without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL) at each CCIA stage. The biopotential AFE is fabricated using a 0.18 µm one polysilicon and six metal layers (1P6M) complementary metal oxide semiconductor (CMOS) process. The core chip size of the AFE without input/output (I/O) pads is 10.5 mm2. A fourth-order band-pass filter (BPF) with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 µVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions. PMID:26437404

Ultrahigh Frequency Nanomechanical Piezoresistive Amplifiers for Direct Channel-Selective Receiver Front-Ends.

PubMed

Ramezany, Alireza; Pourkamali, Siavash

2018-04-11

Channel-selective filtering and amplification in ultrahigh frequency (UHF) receiver front-ends are crucial for realization of cognitive radio systems and the future of wireless communication. In the past decade, there have been significant advances in the performance of microscale electromechanical resonant devices. However, such devices have not yet been able to meet the requirements for direct channel selection at RF. They also occupy a relatively large area on the chip making implementation of large arrays to cover several frequency bands challenging. On the other hand, electromechanical piezoresistive resonant devices are active devices that have recently shown the possibility of simultaneous signal amplification and channel-select filtering at lower frequencies. It has been theoretically predicted that if scaled down into the nanoscale, they can operate in the UHF range with a very low power consumption. Here, for the first time nanomechanical piezoresistive amplifiers with active element dimensions as small as 50 nm × 200 nm are demonstrated. With a device area of less than 1.5 μm 2 a piezoresistive amplifier operating at 730 MHz shows effective quality factor ( Q) of 89,000 for a 50Ω load and gains as high as 10 dB and Q of 330,000 for a 250Ω load while consuming 189 μW of power. On the basis of the measurement results, it is shown that for piezoresistor dimensions of 30 nm × 100 nm it is possible to get a similar performance at 2.4 GHz with device footprint of less than 0.2 μm 2 .

Design and Development of the SMAP Microwave Radiometer Electronics

NASA Technical Reports Server (NTRS)

Piepmeier, Jeffrey R.; Medeiros, James J.; Horgan, Kevin A.; Brambora, Clifford K.; Estep, Robert H.

2014-01-01

The SMAP microwave radiometer will measure land surface brightness temperature at L-band (1413 MHz) in the presence of radio frequency interference (RFI) for soil moisture remote sensing. The radiometer design was driven by the requirements to incorporate internal calibration, to operate synchronously with the SMAP radar, and to mitigate the deleterious effects of RFI. The system design includes a highly linear super-heterodyne microwave receiver with internal reference loads and noise sources for calibration and an innovative digital signal processor and detection system. The front-end comprises a coaxial cable-based feed network, with a pair of diplexers and a coupled noise source, and radiometer front-end (RFE) box. Internal calibration is provided by reference switches and a common noise source inside the RFE. The RF back-end (RBE) downconverts the 1413 MHz channel to an intermediate frequency (IF) of 120 MHz. The IF signals are then sampled and quantized by high-speed analog-to-digital converters in the radiometer digital electronics (RDE) box. The RBE local oscillator and RDE sampling clocks are phase-locked to a common reference to ensure coherency between the signals. The RDE performs additional filtering, sub-band channelization, cross-correlation for measuring third and fourth Stokes parameters, and detection and integration of the first four raw moments of the signals. These data are packetized and sent to the ground for calibration and further processing. Here we discuss the novel features of the radiometer hardware particularly those influenced by the need to mitigate RFI.

A 1.2-V CMOS front-end for LTE direct conversion SAW-less receiver

NASA Astrophysics Data System (ADS)

Riyan, Wang; Jiwei, Huang; Zhengping, Li; Weifeng, Zhang; Longyue, Zeng

2012-03-01

A CMOS RF front-end for the long-term evolution (LTE) direct conversion receiver is presented. With a low noise transconductance amplifier (LNA), current commutating passive mixer and transimpedance operational amplifier (TIA), the RF front-end structure enables high-integration, high linearity and simple frequency planning for LTE multi-band applications. Large variable gain is achieved using current-steering transconductance stages. A current commutating passive mixer with 25% duty-cycle LO improves gain, noise and linearity. A direct coupled current-input filter (DCF) is employed to suppress the out-of-band interferer. Fabricated in a 0.13-μm CMOS process, the RF front-end achieves a 45 dB conversion voltage gain, 2.7 dB NF, -7 dBm IIP3, and +60 dBm IIP2 with calibration from 2.3 to 2.7 GHz. The total RF front end with divider draws 40 mA from a single 1.2-V supply.

Front-end multiplexing—applied to SQUID multiplexing: Athena X-IFU and QUBIC experiments

NASA Astrophysics Data System (ADS)

Prele, D.

2015-08-01

As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device) will be described.

Heat stress during development alters post-harvest sugar contents and chip processing quality of potato tubers

USDA-ARS?s Scientific Manuscript database

Environmental stresses that increase tuber contents of the reducing sugars glucose and fructose decrease the value of chipping potatoes because such tubers produce dark-colored chips that are unacceptable to processors and consumers. Stem-end chip defect (SECD), which causes regions of dark color al...

Programmable synaptic chip for electronic neural networks

NASA Technical Reports Server (NTRS)

Moopenn, A.; Langenbacher, H.; Thakoor, A. P.; Khanna, S. K.

1988-01-01

A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.

Atom chips with free-standing two-dimensional electron gases: advantages and challenges

NASA Astrophysics Data System (ADS)

Sinuco-León, G. A.; Krüger, P.; Fromhold, T. M.

2018-03-01

In this work, we consider the advantages and challenges of using free-standing two-dimensional electron gases (2DEG) as active components in atom chips for manipulating ultracold ensembles of alkali atoms. We calculate trapping parameters achievable with typical high-mobility 2DEGs in an atom chip configuration and identify advantages of this system for trapping atoms at sub-micron distances from the atom chip. We show how the sensitivity of atomic gases to magnetic field inhomogeneity can be exploited for controlling the atoms with quantum electronic devices and, conversely, using the atoms to probe the structural and transport properties of semiconductor devices.

A digitalized silicon microgyroscope based on embedded FPGA.

PubMed

Xia, Dunzhu; Yu, Cheng; Wang, Yuliang

2012-09-27

This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high-speed 18-bit analog to digital convertor, a high-performance core Field Programmable Gate Array (FPGA) chip and other peripherals such as high-speed serial ports for transmitting data. In drive mode, the closed-loop drive circuit are implemented by automatic gain control (AGC) loop and software phase-locked loop (SPLL) based on the Coordinated Rotation Digital Computer (CORDIC) algorithm. Meanwhile, the sense demodulation module based on varying step least mean square demodulation (LMSD) are addressed in detail. All kinds of algorithms are simulated by Simulink and DSPbuilder tools, which is in good agreement with the theoretical design. The experimental results have fully demonstrated the stability and flexibility of the system.

A Digitalized Silicon Microgyroscope Based on Embedded FPGA

PubMed Central

Xia, Dunzhu; Yu, Cheng; Wang, Yuliang

2012-01-01

This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high-speed 18-bit analog to digital convertor, a high-performance core Field Programmable Gate Array (FPGA) chip and other peripherals such as high-speed serial ports for transmitting data. In drive mode, the closed-loop drive circuit are implemented by automatic gain control (AGC) loop and software phase-locked loop (SPLL) based on the Coordinated Rotation Digital Computer (CORDIC) algorithm. Meanwhile, the sense demodulation module based on varying step least mean square demodulation (LMSD) are addressed in detail. All kinds of algorithms are simulated by Simulink and DSPbuilder tools, which is in good agreement with the theoretical design. The experimental results have fully demonstrated the stability and flexibility of the system. PMID:23201990

Injection Locking Techniques for Spectrum Analysis

NASA Astrophysics Data System (ADS)

Gathma, Timothy D.; Buckwalter, James F.

2011-04-01

Wideband spectrum analysis supports future communication systems that reconfigure and adapt to the capacity of the spectral environment. While test equipment manufacturers offer wideband spectrum analyzers with excellent sensitivity and resolution, these spectrum analyzers typically cannot offer acceptable size, weight, and power (SWAP). CMOS integrated circuits offer the potential to fully integrate spectrum analysis capability with analog front-end circuitry and digital signal processing on a single chip. Unfortunately, CMOS lacks high-Q passives and wideband resonator tunability that is necessary for heterodyne implementations of spectrum analyzers. As an alternative to the heterodyne receiver architectures, two nonlinear methods for performing wideband, low-power spectrum analysis are presented. The first method involves injecting the spectrum of interest into an array of injection-locked oscillators. The second method employs the closed loop dynamics of both injection locking and phase locking to independently estimate the injected frequency and power.

[Low-power Wireless Micro Ambulatory Electrocardiogram Node].

PubMed

Cai, Zhipeng; Luo, Kan; Li, Jianqing

2016-02-01

Ambulatory electrocardiogram (ECG) monitoring can effectively reduce the risk and death rate of patients with cardiovascular diseases (CVDs). The Body Sensor Network (BSN) based ECG monitoring is a new and efficien method to protect the CVDs patients. To meet the challenges of miniaturization, low power and high signal quality of the node, we proposed a novel 50 mmX 50 mmX 10 mm, 30 g wireless ECG node, which includes the single-chip an alog front-end AD8232, ultra-low power microprocessor MSP430F1611 and Bluetooth module HM-11. The ECG signal quality is guaranteed by the on-line digital filtering. The difference threshold algorithm results in accuracy of R-wave detection and heart rate. Experiments were carried out to test the node and the results showed that the pro posed node reached the design target, and it has great potential in application of wireless ECG monitoring.

3-lead acquisition using single channel ECG device developed on AD8232 analog front end for wireless ECG application

NASA Astrophysics Data System (ADS)

Agung, Mochammad Anugrah; Basari

2017-02-01

Electrocardiogram (ECG) devices measure electrical activity of the heart muscle to determine heart conditions. ECG signal quality is the key factor in determining the diseases of the heart. This paper presents the design of 3-lead acquistion on single channel wireless ECG device developed on AD8232 chip platform using microcontroller. To make the system different from others, monopole antenna 2.4 GHz is used in order to send and receive ECG signal. The results show that the system still can receive ECG signal up to 15 meters by line of sight (LOS) condition. The shape of ECG signals is precisely similar with the expected signal, although some delays occur between two consecutive pulses. For further step, the system will be applied with on-body antenna in order to investigate body to body communication that will give variation in connectivity from the others.

Real-time multiplicity counter

DOEpatents

Rowland, Mark S [Alamo, CA; Alvarez, Raymond A [Berkeley, CA

2010-07-13

A neutron multi-detector array feeds pulses in parallel to individual inputs that are tied to individual bits in a digital word. Data is collected by loading a word at the individual bit level in parallel. The word is read at regular intervals, all bits simultaneously, to minimize latency. The electronics then pass the word to a number of storage locations for subsequent processing, thereby removing the front-end problem of pulse pileup.

Development and tests of MCP based timing and multiplicity detector for MIPs

NASA Astrophysics Data System (ADS)

Feofilov, G.; Kondratev, V.; Stolyarov, O.; Tulina, T.; Valiev, F.; Vinogradov, L.

2017-01-01

We present summary of technological developments and tests of the MCP based large area detector aimed at precise timing and charged particles multiplicity measurements. Results obtained in course of these developments of isochronous (simultaneity) precise signal readout, passive summation of 1 ns signals, fast (1 GHz) front-end electronics, miniature vacuum systems, etc. could be potentially interesting for a number of future applications in different fields.

Atom Chips on Direct Bonded Copper Substrates (Postprint)

DTIC Science & Technology

2012-01-19

joining of a thin sheet of pure copper to a ceramic substrate14 and is commonly used in power electronics due to its high current handling and heat...Squires et al. Rev. Sci. Instrum. 82, 023101 (2011) FIG. 1. A scanning electron micrograph of the top view of test chip A. the photolithographically...the etching pro- cesses and masking methods were quantified using a scanning electron microscope. Two test chips (A and B) are presented below and are

Design and Implementation of an Electronic Front-End Based on Square Wave Excitation for Ultrasonic Torsional Guided Wave Viscosity Sensor

PubMed Central

Rabani, Amir

2016-01-01

The market for process instruments generally requires low cost devices that are robust, small in size, portable, and usable in-plant. Ultrasonic torsional guided wave sensors have received much attention by researchers for measurement of viscosity and/or density of fluids in recent years. The supporting electronic systems for these sensors providing many different settings of sine-wave signals are bulky and expensive. In contrast, a system based on bursts of square waves instead of sine waves would have a considerable advantage in that respect and could be built using simple integrated circuits at a cost that is orders of magnitude lower than for a windowed sine wave device. This paper explores the possibility of using square wave bursts as the driving signal source for the ultrasonic torsional guided wave viscosity sensor. A simple design of a compact and fully automatic analogue square wave front-end for the sensor is also proposed. The successful operation of the system is demonstrated by using the sensor for measuring the viscosity in a representative fluid. This work provides the basis for design and manufacture of low cost compact standalone ultrasonic guided wave sensors and enlightens the possibility of using coded excitation techniques utilising square wave sequences in such applications. PMID:27754324

Online readout and control unit for high-speed/high resolution readout of silicon tracking detectors

NASA Astrophysics Data System (ADS)

Bürger, J.; Hansen, K.; Lange, W.; Nowak, T.; Prell, S.; Zimmermann, W.

1997-02-01

We are describing a high speed VME readout and control module developed and presently working at the H1 experiment at DESY in Hamburg. It has the capability to read out 4 × 2048 analogue data channels at sampling rates up to 10 MHz with a dynamic input range of 1 V. The nominal resolution of the A/D converters can be adjusted between 8 and 12 bit. At the latter resolution we obtain signal-to-noise ratio better than 61.4 dB at a conversion rate of 5 MSps. At this data rate all 8192 detector channels can be read out to the internal raw data memory and VME interface within about 410 μs and 510 μs, respectively. The pedestal subtracted signals can be analyzed on-line. At a raw data hit occupation of 10%, the VME readout time is 50 μs per module. Each module provides four complementary CMOS signals to control the front-end electronics and four independent sets of power supplies for analogue and digital voltages (10 V, 100 mA) to drive the front-end electronics and for the bias voltage (100 V, 1.2 mA) to assure the full functionality of the detectors and the readout.

Design and Implementation of an Electronic Front-End Based on Square Wave Excitation for Ultrasonic Torsional Guided Wave Viscosity Sensor.

PubMed

Rabani, Amir

2016-10-12

The market for process instruments generally requires low cost devices that are robust, small in size, portable, and usable in-plant. Ultrasonic torsional guided wave sensors have received much attention by researchers for measurement of viscosity and/or density of fluids in recent years. The supporting electronic systems for these sensors providing many different settings of sine-wave signals are bulky and expensive. In contrast, a system based on bursts of square waves instead of sine waves would have a considerable advantage in that respect and could be built using simple integrated circuits at a cost that is orders of magnitude lower than for a windowed sine wave device. This paper explores the possibility of using square wave bursts as the driving signal source for the ultrasonic torsional guided wave viscosity sensor. A simple design of a compact and fully automatic analogue square wave front-end for the sensor is also proposed. The successful operation of the system is demonstrated by using the sensor for measuring the viscosity in a representative fluid. This work provides the basis for design and manufacture of low cost compact standalone ultrasonic guided wave sensors and enlightens the possibility of using coded excitation techniques utilising square wave sequences in such applications.

DOE Office of Scientific and Technical Information (OSTI.GOV)

De Geronimo, G.; Li, S.; D'Andragora, A.

We present a front-end application-specific integrated circuit (ASIC) for a wire based time-projection-chamber (TPC) operating in liquid Argon (LAr). The LAr TPC will be used for long baseline neutrino oscillation experiments. The ASIC must provide a low-noise readout of the signals induced on the TPC wires, digitization of those signals at 2 MSamples/s, compression, buffering and multiplexing. A resolution of better than 1000 rms electrons at 200 pF input capacitance for an input range of 300 fC is required, along with low power and operation in LAr (at 87 K). We include the characterization of a commercial technology for operationmore » in the cryogenic environment and the first experimental results on the analog front end. The results demonstrate that complementary metal-oxide semiconductor transistors have lower noise and much improved dc characteristics at LAr temperature. Finally, we introduce the concept of '1/f equivalent' to model the low-frequency component of the noise spectral density, for use in the input metal-oxide semiconductor field-effect transistor optimization.« less

Photon beam position monitor

DOEpatents

Kuzay, Tuncer M.; Shu, Deming

1995-01-01

A photon beam position monitor for use in the front end of a beamline of a high heat flux and high energy photon source such as a synchrotron radiation storage ring detects and measures the position and, when a pair of such monitors are used in tandem, the slope of a photon beam emanating from an insertion device such as a wiggler or an undulator inserted in the straight sections of the ring. The photon beam position monitor includes a plurality of spaced blades for precisely locating the photon beam, with each blade comprised of chemical vapor deposition (CVD) diamond with an outer metal coating of a photon sensitive metal such as tungsten, molybdenum, etc., which combination emits electrons when a high energy photon beam is incident upon the blade. Two such monitors are contemplated for use in the front end of the beamline, with the two monitors having vertically and horizontally offset detector blades to avoid blade "shadowing". Provision is made for aligning the detector blades with the photon beam and limiting detector blade temperature during operation.

A fractographic study of clinically retrieved zirconia-ceramic and metal-ceramic fixed dental prostheses.

PubMed

Pang, Zhen; Chughtai, Asima; Sailer, Irena; Zhang, Yu

2015-10-01

A recent 3-year randomized controlled trial (RCT) of tooth supported three- to five-unit zirconia-ceramic and metal-ceramic posterior fixed dental prostheses (FDPs) revealed that veneer chipping and fracture in zirconia-ceramic systems occurred more frequently than those in metal-ceramic systems [1]. This study seeks to elucidate the underlying mechanisms responsible for the fracture phenomena observed in this RCT using a descriptive fractographic analysis. Vinyl-polysiloxane impressions of 12 zirconia-ceramic and 6 metal-ceramic FDPs with veneer fractures were taken from the patients at the end of a mean observation of 40.3±2.8 months. Epoxy replicas were produced from these impressions [1]. All replicas were gold coated, and inspected under the optical microscope and scanning electron microscope (SEM) for descriptive fractography. Among the 12 zirconia-ceramic FDPs, 2 had small chippings, 9 had large chippings, and 1 exhibited delamination. Out of 6 metal-ceramic FDPs, 5 had small chippings and 1 had large chipping. Descriptive fractographic analysis based on SEM observations revealed that fracture initiated from the wear facet at the occlusal surface in all cases, irrespective of the type of restoration. Zirconia-ceramic and metal-ceramic FDPs all fractured from microcracks that emanated from occlusal wear facets. The relatively low fracture toughness and high residual tensile stress in porcelain veneer of zirconia restorations may contribute to the higher chipping rate and larger chip size in zirconia-ceramic FDPs relative to their metal-ceramic counterparts. The low veneer/core interfacial fracture energy of porcelain-veneered zirconia may result in the occurrence of delamination in zirconia-ceramic FDPs. Copyright © 2015 Academy of Dental Materials. Published by Elsevier Ltd. All rights reserved.

A fractographic study of clinically retrieved zirconia–ceramic and metal–ceramic fixed dental prostheses

PubMed Central

Pang, Zhen; Chughtai, Asima; Sailer, Irena; Zhang, Yu

2015-01-01

Objectives A recent 3-year randomized controlled trial (RCT) of tooth supported three- to five-unit zirconia–ceramic and metal–ceramic posterior fixed dental prostheses (FDPs) revealed that veneer chipping and fracture in zirconia–ceramic systems occurred more frequently than those in metal–ceramic systems [1]. This study seeks to elucidate the underlying mechanisms responsible for the fracture phenomena observed in this RCT using a descriptive fractographic analysis. Methods Vinyl-polysiloxane impressions of 12 zirconia–ceramic and 6 metal–ceramic FDPs with veneer fractures were taken from the patients at the end of a mean observation of 40.3 ± 2.8 months. Epoxy replicas were produced from these impressions [1]. All replicas were gold coated, and inspected under the optical microscope and scanning electron microscope (SEM) for descriptive fractography. Results Among the 12 zirconia–ceramic FDPs, 2 had small chippings, 9 had large chippings, and 1 exhibited delamination. Out of 6 metal–ceramic FDPs, 5 had small chippings and 1 had large chipping. Descriptive fractographic analysis based on SEM observations revealed that fracture initiated from the wear facet at the occlusal surface in all cases, irrespective of the type of restoration. Significance Zirconia–ceramic and metal–ceramic FDPs all fractured from microcracks that emanated from occlusal wear facets. The relatively low fracture toughness and high residual tensile stress in porcelain veneer of zirconia restorations may contribute to the higher chipping rate and larger chip size in zirconia–ceramic FDPs relative to their metal–ceramic counterparts. The low veneer/core interfacial fracture energy of porcelain-veneered zirconia may result in the occurrence of delamination in zirconia–ceramic FDPs. PMID:26233469

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, W.; Yin, J.; Li, C.

This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by amore » FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e{sup -} to 100000 e{sup -}, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)« less

First test results from the Front-End Board with Cyclone V as a test high-resolution platform for the Auger-Beyond-2015 Front End Electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Szadkowski, Zbigniew

2015-07-01

The paper presents the first results from the Front- End Board (FEB) with the biggest Cyclone{sup R} V E FPGA 5CEFA9F31I7N, supporting 8 channels sampled up to 250 MSps at 14-bit resolution. Considered sampling for the SD is 120 MSps, however, the FEB has been developed with external anti-aliasing filters to keep a maximal flexibility. Six channels are targeted to the SD, two the rest for other experiments like: Auger Engineering Radio Array and additional muon counters. More channels and higher sampling generate larger size of registered events. We used the standard radio channel for a radio transmission from themore » detectors to the Central Data Acquisition Station (CDAS) to avoid at present a significant modification of a software in both sides: the detector and the CDAS (planned in a future for a final design). Seven FEBs have been deployed in the test detectors on a dedicated Engineering Array in a hexagon. Several variants of the FPGA code were tested for 120, 160, 200 and even 240 MSps DAQ. Tests confirmed a stability and reliability of the FEB design in real pampas conditions with more than 40 deg. C daily temperature variation and a strong sun exposition with a limited power budget only from a single solar panel. (authors)« less

Design and simulation of front end power converter for a microgrid with fuel cells and solar power sources

NASA Astrophysics Data System (ADS)

Jeevargi, Chetankumar; Lodhi, Anuj; Sateeshkumar, Allu; Elangovan, D.; Arunkumar, G.

2017-11-01

The need for Renewable Energy Sources (RES) is increasing due to increased demand for the supply of power and it is also environment friendly.In the recent few years, the cost of generation of the power from the RES has been decreased. This paper aims to design the front end power converter which is required for integrating the fuel cells and solar power sources to the micro grid. The simulation of the designed front end converter is carried out in the PSIM 9.1.1 software. The results show that the designed front end power converter is sufficient for integrating the micro grid with fuel cells and solar power sources.

Repairable chip bonding/interconnect process

DOEpatents

Bernhardt, A.F.; Contolini, R.J.; Malba, V.; Riddle, R.A.

1997-08-05

A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules is disclosed. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder. 10 figs.

Adapting Wave-front Algorithms to Efficiently Utilize Systems with Deep Communication Hierarchies

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kerbyson, Darren J.; Lang, Michael; Pakin, Scott

2011-09-30

Large-scale systems increasingly exhibit a differential between intra-chip and inter-chip communication performance especially in hybrid systems using accelerators. Processorcores on the same socket are able to communicate at lower latencies, and with higher bandwidths, than cores on different sockets either within the same node or between nodes. A key challenge is to efficiently use this communication hierarchy and hence optimize performance. We consider here the class of applications that contains wavefront processing. In these applications data can only be processed after their upstream neighbors have been processed. Similar dependencies result between processors in which communication is required to pass boundarymore » data downstream and whose cost is typically impacted by the slowest communication channel in use. In this work we develop a novel hierarchical wave-front approach that reduces the use of slower communications in the hierarchy but at the cost of additional steps in the parallel computation and higher use of on-chip communications. This tradeoff is explored using a performance model. An implementation using the Reverse-acceleration programming model on the petascale Roadrunner system demonstrates a 27% performance improvement at full system-scale on a kernel application. The approach is generally applicable to large-scale multi-core and accelerated systems where a differential in system communication performance exists.« less

On-chip magnetic cooling of a nanoelectronic device.

PubMed

Bradley, D I; Guénault, A M; Gunnarsson, D; Haley, R P; Holt, S; Jones, A T; Pashkin, Yu A; Penttilä, J; Prance, J R; Prunnila, M; Roschier, L

2017-04-04

We demonstrate significant cooling of electrons in a nanostructure below 10 mK by demagnetisation of thin-film copper on a silicon chip. Our approach overcomes the typical bottleneck of weak electron-phonon scattering by coupling the electrons directly to a bath of refrigerated nuclei, rather than cooling via phonons in the host lattice. Consequently, weak electron-phonon scattering becomes an advant- age. It allows the electrons to be cooled for an experimentally useful period of time to temperatures colder than the dilution refrigerator platform, the incoming electrical connections, and the host lattice. There are efforts worldwide to reach sub-millikelvin electron temperatures in nanostructures to study coherent electronic phenomena and improve the operation of nanoelectronic devices. On-chip magnetic cooling is a promising approach to meet this challenge. The method can be used to reach low, local electron temperatures in other nanostructures, obviating the need to adapt traditional, large demagnetisation stages. We demonstrate the technique by applying it to a nanoelectronic primary thermometer that measures its internal electron temperature. Using an optimised demagnetisation process, we demonstrate cooling of the on-chip electrons from 9 mK to below 5 mK for over 1000 seconds.

On-chip magnetic cooling of a nanoelectronic device

NASA Astrophysics Data System (ADS)

Bradley, D. I.; Guénault, A. M.; Gunnarsson, D.; Haley, R. P.; Holt, S.; Jones, A. T.; Pashkin, Yu. A.; Penttilä, J.; Prance, J. R.; Prunnila, M.; Roschier, L.

2017-04-01

We demonstrate significant cooling of electrons in a nanostructure below 10 mK by demagnetisation of thin-film copper on a silicon chip. Our approach overcomes the typical bottleneck of weak electron-phonon scattering by coupling the electrons directly to a bath of refrigerated nuclei, rather than cooling via phonons in the host lattice. Consequently, weak electron-phonon scattering becomes an advant- age. It allows the electrons to be cooled for an experimentally useful period of time to temperatures colder than the dilution refrigerator platform, the incoming electrical connections, and the host lattice. There are efforts worldwide to reach sub-millikelvin electron temperatures in nanostructures to study coherent electronic phenomena and improve the operation of nanoelectronic devices. On-chip magnetic cooling is a promising approach to meet this challenge. The method can be used to reach low, local electron temperatures in other nanostructures, obviating the need to adapt traditional, large demagnetisation stages. We demonstrate the technique by applying it to a nanoelectronic primary thermometer that measures its internal electron temperature. Using an optimised demagnetisation process, we demonstrate cooling of the on-chip electrons from 9 mK to below 5 mK for over 1000 seconds.

Ultrasensitive Label-free Electronic Chip for DNA Analysis Using Carbon Nanotube Nanoelectrode Arrays

NASA Technical Reports Server (NTRS)

Li, Jun; Koehne, Jessica; Chen, Hua; Cassell, Alan; Ng, Hou Tee; Ye, Qi; Han, Jie; Meyyappan, M.

2004-01-01

There is a strong need for faster, cheaper, and simpler methods for nucleic acid analysis in today s clinical tests. Nanotechnologies can potentially provide solutions to these requirements by integrating nanomaterials with biofunctionalities. Dramatic improvement in the sensitivity and multiplexing can be achieved through the high-degree miniaturization. Here, we present our study in the development of an ultrasensitive label-free electronic chip for DNA/RNA analysis based on carbon nanotube nanoelectrode arrays. A reliable nanoelectrode array based on vertically aligned multi-walled carbon nanotubes (MWNTs) embedded in a SiO2 matrix is fabricated using a bottom-up approach. Characteristic nanoelectrode behavior is observed with a low-density MWNT nanoelectrode array in measuring both the bulk and surface immobilized redox species. The open-end of MWNTs are found to present similar properties as graphite edge-plane electrodes, with a wide potential window, flexible chemical functionalities, and good biocompatibility. A BRCA1 related oligonucleotide probe with 18 bases is covalently functionalized at the open ends of the MWNTs and specifically hybridized with an oligonucleotide target as well as a PCR amplicon. The guanine bases in the target molecules are employed as the signal moieties for the electrochemical measurements. Ru(bpy)3(2+) mediator is used to further amplify the guanine oxidation signal. This technique has been employed for direct electrochemical detection of label-free PCR amplicon through specific hybridization with the BRCAl probe. The detection limit is estimated to be less than approximately 1000 DNA molecules, approaching the limit of the sensitivity by laser-based fluorescence techniques in DNA microarray. This system provides a general electronic platform for rapid molecular diagnostics in applications requiring ultrahigh sensitivity, high-degree of miniaturization, simple sample preparation, and low- cost operation.

Cytometer on a Chip

NASA Technical Reports Server (NTRS)

Fernandez, Salvador M.

2011-01-01

A cytometer now under development exploits spatial sorting of sampled cells on a microarray chip followed by use of grating-coupled surface-plasmon-resonance imaging (GCSPRI) to detect the sorted cells. This cytometer on a chip is a prototype of contemplated future miniature cytometers that would be suitable for rapidly identifying pathogens and other cells of interest in both field and laboratory applications and that would be attractive as alternatives to conventional flow cytometers. The basic principle of operation of a conventional flow cytometer requires fluorescent labeling of sampled cells, stringent optical alignment of a laser beam with a narrow orifice, and flow of the cells through the orifice, which is subject to clogging. In contrast, the principle of operation of the present cytometer on a chip does not require fluorescent labeling of cells, stringent optical alignment, or flow through a narrow orifice. The basic principle of operation of the cytometer on a chip also reduces the complexity, mass, and power of the associated laser and detection systems, relative to those needed in conventional flow cytometry. Instead of making cells flow in single file through a narrow flow orifice for sequential interrogation as in conventional flow cytometry, a liquid containing suspended sampled cells is made to flow over the front surface of a microarray chip on which there are many capture spots. Each capture spot is coated with a thin (approximately 50-nm) layer of gold that is, in turn, coated with antibodies that bind to cell-surface molecules characteristic of one the cell species of interest. The multiplicity of capture spots makes it possible to perform rapid, massively parallel analysis of a large cell population. The binding of cells to each capture spot gives rise to a minute change in the index of refraction at the surface of the chip. This change in the index of refraction is what is sensed in GCSPRI, as described briefly below. The identities of the various species in a sample of cells is spatially encoded in the chip by the pattern of capture spots. The number of cells of a particular species is determined from the magnitude of the GCSPRI signal from that spot. GCSPRI as used here can be summarized as follows: The cytometer chip is fabricated with a diffraction grating on its front surface. The chip is illuminated with a light emitting diode (LED) from the front. By proper choice of grating parameters and of the wavelength and the angle of incidence of a laser beam, laser light can be made to be coupled into an electromagnetic mode that resonates with surface plasmons and thus couples light into surface plasmons. Coupling of light into a surface plasmon at a given location reduces the amount of incident light reflected from that location. A change in the index of refraction at the surface of a capture spot gives rise to a change in the resonance condition. Depending on the specific design, the change in the index of refraction could manifest itself as a brightening or darkening, a change in the wavelength needed to excite the plasmon at a given angle of incidence, or a change in the angle of incidence needed to excite the plasmon at a given wavelength. Whereas a multiwavelength laser system with multichannel detection would be needed to detect multiple species in conventional flow cytometry, it suffices to use an LED and a single detector channel in the GCSPRI approach: this contributes significantly to reductions in cost, complexity, size, mass, and power. GCSPRI cytometer chips could be made of plastic and could be mass-produced cheaply by use of molding and other methods adopted from the manufacture of digital video disks. These methods are amenable to a high degree of miniaturization: such additional features as fluidic channels, reaction chambers, and fluid-coupling ports could readily be incorporated into the chips, without incurring substantial additional costs.

Cytometer on a Chip

NASA Technical Reports Server (NTRS)

Fernandez, Salvador M.

2011-01-01

A cytometer now under development exploits spatial sorting of sampled cells on a microarray chip followed by use of grating-coupled surface-plasmon-resonance imaging (GCSPRI) to detect the sorted cells. This cytometer on a chip is a prototype of contemplated future miniature cytometers that would be suitable for rapidly identifying pathogens and other cells of interest in both field and laboratory applications and that would be attractive as alternatives to conventional flow cytometers. The basic principle of operation of a conventional flow cytometer requires fluorescent labeling of sampled cells, stringent optical alignment of a laser beam with a narrow orifice, and flow of the cells through the orifice, which is subject to clogging. In contrast, the principle of operation of the present cytometer on a chip does not require fluorescent labeling of cells, stringent optical alignment, or flow through a narrow orifice. The basic principle of operation of the cytometer on a chip also reduces the complexity, mass, and power of the associated laser and detection systems, relative to those needed in conventional flow cytometry. Instead of making cells flow in single file through a narrow flow orifice for sequential interrogation as in conventional flow cytometry, a liquid containing suspended sampled cells is made to flow over the front surface of a microarray chip on which there are many capture spots. Each capture spot is coated with a thin (.50-nm) layer of gold that is, in turn, coated with antibodies that bind to cell-surface molecules characteristic of the cell species of interest. The multiplicity of capture spots makes it possible to perform rapid, massively parallel analysis of a large cell population. The binding of cells to each capture spot gives rise to a minute change in the index of refraction at the surface of the chip. This change in the index of refraction is what is sensed in GCSPRI, as described briefly below. The identities of the various species in a sample of cells is spatially encoded in the chip by the pattern of capture spots. The number of cells of a particular species is determined from the magnitude of the GCSPRI signal from that spot. GCSPRI as used here can be summarized as follows: The cytometer chip is fabricated with a diffraction grating on its front surface. The chip is illuminated with a light emitting diode (LED) from the front. By proper choice of grating parameters and of the wavelength and the angle of incidence of a laser beam, laser light can be made to be coupled into an electromagnetic mode that resonates with surface plasmons and thus couples light into surface plasmons. Coupling of light into a surface plasmon at a given location reduces the amount of incident light reflected from that location. A change in the index of refraction at the surface of a capture spot gives rise to a change in the resonance condition. Depending on the specific design, the change in the index of refraction could manifest itself as a brightening or darkening, a change in the wavelength needed to excite the plasmon at a given angle of incidence, or a change in the angle of incidence needed to excite the plasmon at a given wavelength. Whereas a multiwavelength laser system with multichannel detection would be needed to detect multiple species in conventional flow cytometry, it suffices to use an LED and a single detector channel in the GCSPRI approach: this contributes significantly to reductions in cost, complexity, size, mass, and power. GCSPRI cytometer chips could be made of plastic and could be mass-produced cheaply by use of molding and other methods adopted from the manufacture of digital video disks. These methods are amenable to a high degree of miniaturization: such additional features as fluidic channels, reaction chambers, and fluid-coupling ports could readily be incorporated into the chips, without incurring substantial additional costs.

Low-resistivity photon-transparent window attached to photo-sensitive silicon detector

DOEpatents

Holland, Stephen Edward

2000-02-15

The invention comprises a combination of a low resistivity, or electrically conducting, silicon layer that is transparent to long or short wavelength photons and is attached to the backside of a photon-sensitive layer of silicon, such as a silicon wafer or chip. The window is applied to photon sensitive silicon devices such as photodiodes, charge-coupled devices, active pixel sensors, low-energy x-ray sensors and other radiation detectors. The silicon window is applied to the back side of a photosensitive silicon wafer or chip so that photons can illuminate the device from the backside without interference from the circuit printed on the frontside. A voltage sufficient to fully deplete the high-resistivity photosensitive silicon volume of charge carriers is applied between the low-resistivity back window and the front, patterned, side of the device. This allows photon-induced charge created at the backside to reach the front side of the device and to be processed by any circuitry attached to the front side. Using the inventive combination, the photon sensitive silicon layer does not need to be thinned beyond standard fabrication methods in order to achieve full charge-depletion in the silicon volume. In one embodiment, the inventive backside window is applied to high resistivity silicon to allow backside illumination while maintaining charge isolation in CCD pixels.

Physical Modeling Techniques for Missile and Other Protective Structures

DTIC Science & Technology

1983-06-29

uniaxial load only. In general , axial thrust was applied with an: initial eccentricity of zero on the specimen end. Sixteen different combinations of Pa...conditioning electronics and cabling schemes is included. The techniques described generally represent current approaches at the Civil Engineering Research...at T- zero and stopping when a pulse is generated by the pi-ezoelectric disc on arrival of! the detonation wave front. All elapsed time data is stored

Electronic Patient Reported Outcomes in Paediatric Oncology - Applying Mobile and Near Field Communication Technology.

PubMed

Duregger, Katharina; Hayn, Dieter; Nitzlnader, Michael; Kropf, Martin; Falgenhauer, Markus; Ladenstein, Ruth; Schreier, Günter

2016-01-01

Electronic Patient Reported Outcomes (ePRO) gathered using telemonitoring solutions might be a valuable source of information in rare cancer research. The objective of this paper was to develop a concept and implement a prototype for introducing ePRO into the existing neuroblastoma research network by applying Near Field Communication and mobile technology. For physicians, an application was developed for registering patients within the research network and providing patients with an ID card and a PIN for authentication when transmitting telemonitoring data to the Electronic Data Capture system OpenClinica. For patients, a previously developed telemonitoring system was extended by a Simple Object Access Protocol (SOAP) interface for transmitting nine different health parameters and toxicities. The concept was fully implemented on the front-end side. The developed application for physicians was prototypically implemented and the mobile application of the telemonitoring system was successfully connected to OpenClinica. Future work will focus on the implementation of the back-end features.

Analysis of Photonic Networks for a Chip Multiprocessor Using Scientific Applications

DTIC Science & Technology

2009-05-01

Analysis of Photonic Networks for a Chip Multiprocessor Using Scientific Applications Gilbert Hendry†, Shoaib Kamil‡?, Aleksandr Biberman†, Johnnie...electronic networks -on-chip warrants investigating real application traces on functionally compa- rable photonic and electronic network designs. We... network can achieve 75× improvement in energy ef- ficiency for synthetic benchmarks and up to 37× improve- ment for real scientific applications

Plastic Scintillator Based Detector for Observations of Terrestrial Gamma-ray Flashes.

NASA Astrophysics Data System (ADS)

Barghi, M. R., Sr.; Delaney, N.; Forouzani, A.; Wells, E.; Parab, A.; Smith, D.; Martinez, F.; Bowers, G. S.; Sample, J.

2017-12-01

We present an overview of the concept and design of the Light and Fast TGF Recorder (LAFTR), a balloon borne gamma-ray detector designed to observe Terrestrial Gamma-Ray Flashes (TGFs). Terrestrial Gamma-Ray Flashes (TGFs) are extremely bright, sub-millisecond bursts of gamma-rays observed to originate inside thunderclouds coincident with lightning. LAFTR is joint institutional project built by undergraduates at the University of California Santa Cruz and Montana State University. It consists of a detector system fed into analog front-end electronics and digital processing. The presentation focuses specifically on the UCSC components, which consists of the detector system and analog front-end electronics. Because of the extremely high count rates observed during TGFs, speed is essential for both the detector and electronics of the instrument. The detector employs a fast plastic scintillator (BC-408) read out by a SensL Silicon Photomultiplier (SiPM). BC-408 is chosen for its speed ( 4 ns decay time) and low cost and availability. Furthermore, GEANT3 simulations confirm the scintillator is sensitive to 500 counts at 7 km horizontal distance from the TGF source (for a 13 km source altitude and 26 km balloon altitude) and to 5 counts out to 20 km. The signal from the SiPM has a long exponential decay tail and is sent to a custom shaping circuit board that amplifies and shapes the signal into a semi-Gaussian pulse with a 40 ns FWHM. The signal is then input to a 6-channel discriminator board that clamps the signal and outputs a Low Voltage Differential Signal (LVDS) for processing by the digital electronics.

An economic evaluation of a chlorhexidine chip for treating chronic periodontitis: the CHIP (chlorhexidine in periodontitis) study.

PubMed

Henke, C J; Villa, K F; Aichelmann-Reidy, M E; Armitage, G C; Eber, R M; Genco, R J; Killoy, W J; Miller, D P; Page, R C; Polson, A M; Ryder, M I; Silva, S J; Somerman, M J; Van Dyke, T E; Wolff, L F; Evans, C J; Finkelman, R D

2001-11-01

The authors previously suggested that an adjunctive, controlled-release chlorhexidine, or CHX, chip may reduce periodontal surgical needs at little additional cost. This article presents an economic analysis of the CHX chip in general dental practice. In a one-year prospective clinical trial, 484 chronic periodontitis patients in 52 general practices across the United States were treated with either scaling and root planing, or SRP, plus any therapy prescribed by treating, unblinded dentists; or SRP plus other therapy as above but including the CHX chip. Economic data were collected from bills, case report forms and 12-month treatment recommendations from blinded periodontist evaluators. Total dental charges were higher for SRP + CHX chip patients vs. SRP patients when CHX chip costs were included (P = .027) but lower when CHX chip costs were excluded (P = .012). About one-half of the CHX chip acquisition cost was offset by savings in other charges. SRP + CHX chip patients were about 50 percent less likely to undergo surgical procedures than were SRP patients (P = .021). At the end of the trial, periodontist evaluators recommended similar additional procedures for both groups: SRP, about 46 percent; maintenance, about 37 percent; surgery, 56 percent for SRP alone and 63 percent for SRP + CHX chip. Adjunctive CHX chip use for general-practice patients with periodontitis increased costs but reduced surgeries over one year. At study's end, periodontists recommended similar additional surgical treatment for both groups. In general practice, routine use of the CHX chip suggests that costs will be partially offset by reduced surgery over at least one year.

Characterization of Kilopixel TES detector arrays for PIPER

NASA Astrophysics Data System (ADS)

Datta, Rahul; Ade, Peter; Benford, Dominic; Bennett, Charles; Chuss, David; Costen, Nicholas; Coughlin, Kevin; Dotson, Jessie; Eimer, Joseph; Fixsen, Dale; Gandilo, Natalie; Halpern, Mark; Essinger-Hileman, Thomas; Hilton, Gene; Hinshaw, Gary; Irwin, Kent; Jhabvala, Christine; Kimball, Mark; Kogut, Al; Lazear, Justin; Lowe, Luke; Manos, George; McMahon, Jeff; Miller, Timothy; Mirel, Paul; Moseley, Samuel Harvey; Pawlyk, Samuel; Rodriguez, Samelys; Sharp, Elmer; Shirron, Peter; Staguhn, Johannes G.; Sullivan, Dan; Switzer, Eric; Taraschi, Peter; Tucker, Carole; Walts, Alexander; Wollack, Edward

2018-01-01

The Primordial Inflation Polarization ExploreR (PIPER) is a balloon-borne instrument optimized to measure the polarization of the Cosmic Microwave Background (CMB) at large angular scales. It will map 85% of the sky in four frequency bands centered at 200, 270, 350, and 600 GHz to characterize dust foregrounds and constrain the tensor-to-scalar ratio, r. The sky is imaged on to 32x40 pixel arrays of time-domain multiplexed Transition-Edge Sensor (TES) bolometers operating at a bath temperature of 100 mK to achieve background-limited sensitivity. Each kilopixel array is indium-bump-bonded to a 2D superconducting quantum interference device (SQUID) time-domain multiplexer (MUX) chip and read out by warm electronics. Each pixel measures total incident power over a frequency band defined by bandpass filters in front of the array, while polarization sensitivity is provided by the upstream Variable-delay Polarization Modulators (VPMs) and analyzer grids. We present measurements of the detector parameters from the laboratory characterization of the first kilopixel science array for PIPER including transition temperature, saturation power, thermal conductivity, time constant, and noise performance. We also describe the testing of the 2D MUX chips, optimization of the integrated readout parameters, and the overall pixel yield of the array. The first PIPER science flight is planned for June 2018 from Palestine, Texas.

Relativistic runaway ionization fronts.

PubMed

Luque, A

2014-01-31

We investigate the first example of self-consistent impact ionization fronts propagating at relativistic speeds and involving interacting, high-energy electrons. These fronts, which we name relativistic runaway ionization fronts, show remarkable features such as a bulk speed within less than one percent of the speed of light and the stochastic selection of high-energy electrons for further acceleration, which leads to a power-law distribution of particle energies. A simplified model explains this selection in terms of the overrun of Coulomb-scattered electrons. Appearing as the electromagnetic interaction between electrons saturates the exponential growth of a relativistic runaway electron avalanche, relativistic runaway ionization fronts may occur in conjunction with terrestrial gamma-ray flashes and thus explain recent observations of long, power-law tails in the terrestrial gamma-ray flash energy spectrum.

Electrostatically focused addressable field emission array chips (AFEA's) for high-speed massively parallel maskless digital E-beam direct write lithography and scanning electron microscopy

DOEpatents

Thomas, Clarence E.; Baylor, Larry R.; Voelkl, Edgar; Simpson, Michael L.; Paulus, Michael J.; Lowndes, Douglas H.; Whealton, John H.; Whitson, John C.; Wilgen, John B.

2002-12-24

Systems and methods are described for addressable field emission array (AFEA) chips. A method of operating an addressable field-emission array, includes: generating a plurality of electron beams from a pluralitly of emitters that compose the addressable field-emission array; and focusing at least one of the plurality of electron beams with an on-chip electrostatic focusing stack. The systems and methods provide advantages including the avoidance of space-charge blow-up.

[AFM fishing of proteins under impulse electric field].

PubMed

Ivanov, Yu D; Pleshakova, T O; Malsagova, K A; Kaysheva, A L; Kopylov, A T; Izotov, A A; Tatur, V Yu; Vesnin, S G; Ivanova, N D; Ziborov, V S; Archakov, A I

2016-05-01

A combination of (atomic force microscopy)-based fishing (AFM-fishing) and mass spectrometry allows to capture protein molecules from solutions, concentrate and visualize them on an atomically flat surface of the AFM chip and identify by subsequent mass spectrometric analysis. In order to increase the AFM-fishing efficiency we have applied pulsed voltage with the rise time of the front of about 1 ns to the AFM chip. The AFM-chip was made using a conductive material, highly oriented pyrolytic graphite (HOPG). The increased efficiency of AFM-fishing has been demonstrated using detection of cytochrome b5 protein. Selection of the stimulating pulse with a rise time of 1 ns, corresponding to the GHz frequency range, by the effect of intrinsic emission from water observed in this frequency range during water injection into the cell.

A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Man-Chia; Perez, Aldo Pena; Kothapalli, Sri-Rajasekhar

This study presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 μm by 250 μm. The proof-of-concept receiver was implemented in an STMicroelectronics's 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a 4 × 4 subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables anmore » efficient in-pixel A/D conversion. The per-pixel switched-capacitor ΔΣ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator's measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. Finally, the functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array.« less

A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI

DOE PAGES

Chen, Man-Chia; Perez, Aldo Pena; Kothapalli, Sri-Rajasekhar; ...

2017-10-16

This study presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 μm by 250 μm. The proof-of-concept receiver was implemented in an STMicroelectronics's 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a 4 × 4 subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables anmore » efficient in-pixel A/D conversion. The per-pixel switched-capacitor ΔΣ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator's measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. Finally, the functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array.« less

The optical design of 3D ICs for smartphone and optro-electronics sensing module

NASA Astrophysics Data System (ADS)

Huang, Jiun-Woei

2018-03-01

Smartphone require limit space for image system, current lens, used in smartphones are refractive type, the effective focal length is limited the thickness of phone physical size. Other, such as optro-electronics sensing chips, proximity optical sensors, and UV indexer chips are integrated into smart phone with limit space. Due to the requirement of multiple lens in smartphone, proximity optical sensors, UV indexer and other optro-electronics sensing chips in a limited space of CPU board in future smart phone, optro-electronics 3D IC's integrated with optical lens or components may be a key technology for 3 C products. A design for reflective lens is fitted to CMOS, proximity optical sensors, UV indexer and other optro-electronics sensing chips based on 3-D IC. The reflective lens can be threes times of effective focal lens, and be able to resolve small object. The system will be assembled and integrated in one 3-D IC more easily.

Front-End Analysis Cornerstone of Logistics

NASA Technical Reports Server (NTRS)

Nager, Paul J.

2000-01-01

The presentation provides an overview of Front-End Logistics Support Analysis (FELSA), when it should be performed, benefits of performing FELSA and why it should be performed, how it is conducted, and examples.

Controlling front-end electronics boards using commercial solutions

NASA Astrophysics Data System (ADS)

Beneyton, R.; Gaspar, C.; Jost, B.; Schmeling, S.

2002-04-01

LHCb is a dedicated B-physics experiment under construction at CERN's large hadron collider (LHC) accelerator. This paper will describe the novel approach LHCb is taking toward controlling and monitoring of electronics boards. Instead of using the bus in a crate to exercise control over the boards, we use credit-card sized personal computers (CCPCs) connected via Ethernet to cheap control PCs. The CCPCs will provide a simple parallel, I2C, and JTAG buses toward the electronics board. Each board will be equipped with a CCPC and, hence, will be completely independently controlled. The advantages of this scheme versus the traditional bus-based scheme will be described. Also, the integration of the controls of the electronics boards into a commercial supervisory control and data acquisition (SCADA) system will be shown.

Highly efficient on-chip direct electronic-plasmonic transducers

NASA Astrophysics Data System (ADS)

Du, Wei; Wang, Tao; Chu, Hong-Son; Nijhuis, Christian A.

2017-10-01

Photonic elements can carry information with a capacity exceeding 1,000 times that of electronic components, but, due to the optical diffraction limit, these elements are large and difficult to integrate with modern-day nanoelectronics or upcoming packages, such as three-dimensional integrated circuits or stacked high-bandwidth memories1-3. Surface plasmon polaritons can be confined to subwavelength dimensions and can carry information at high speeds (>100 THz)4-6. To combine the small dimensions of nanoelectronics with the fast operating speed of optics via plasmonics, on-chip electronic-plasmonic transducers that directly convert electrical signals into plasmonic signals (and vice versa) are required. Here, we report electronic-plasmonic transducers based on metal-insulator-metal tunnel junctions coupled to plasmonic waveguides with high-efficiency on-chip generation, manipulation and readout of plasmons. These junctions can be readily integrated into existing technologies, and we thus believe that they are promising for applications in on-chip integrated plasmonic circuits.

Urban Biomining Meets Printable Electronics: End-To-End at Destination Biological Recycling and Reprinting

NASA Technical Reports Server (NTRS)

Rothschild, Lynn J. (Principal Investigator); Koehne, Jessica; Gandhiraman, Ram; Navarrete, Jesica; Spangle, Dylan

2017-01-01

Space missions rely utterly on metallic components, from the spacecraft to electronics. Yet, metals add mass, and electronics have the additional problem of a limited lifespan. Thus, current mission architectures must compensate for replacement. In space, spent electronics are discarded; on earth, there is some recycling but current processes are toxic and environmentally hazardous. Imagine instead an end-to-end recycling of spent electronics at low mass, low cost, room temperature, and in a non-toxic manner. Here, we propose a solution that will not only enhance mission success by decreasing upmass and providing a fresh supply of electronics, but in addition has immediate applications to a serious environmental issue on the Earth. Spent electronics will be used as feedstock to make fresh electronic components, a process we will accomplish with so-called 'urban biomining' using synthetically enhanced microbes to bind metals with elemental specificity. To create new electronics, the microbes will be used as 'bioink' to print a new IC chip, using plasma jet electronics printing. The plasma jet electronics printing technology will have the potential to use martian atmospheric gas to print and to tailor the electronic and chemical properties of the materials. Our preliminary results have suggested that this process also serves as a purification step to enhance the proportion of metals in the 'bioink'. The presence of electric field and plasma can ensure printing in microgravity environment while also providing material morphology and electronic structure tunabiity and thus optimization. Here we propose to increase the TRL level of the concept by engineering microbes to dissolve the siliceous matrix in the IC, extract copper from a mixture of metals, and use the microbes as feedstock to print interconnects using mars gas simulant. To assess the ability of this concept to influence mission architecture, we will do an analysis of the infrastructure required to execute this concept on Mars, and additional opportunities it could offer mission design from the biological and printing technologies. In addition, we will do an analysis of the impact of this technology for terrestrial applications addressing in particular environmental concerns and availability of metals.

An Innovative Method of Teaching Electronic System Design with PSoC

ERIC Educational Resources Information Center

Ye, Zhaohui; Hua, Chengying

2012-01-01

Programmable system-on-chip (PSoC), which provides a microprocessor and programmable analog and digital peripheral functions in a single chip, is very convenient for mixed-signal electronic system design. This paper presents the experience of teaching contemporary mixed-signal electronic system design with PSoC in the Department of Automation,…

Concepts for a Muon Accelerator Front-End

DOE Office of Scientific and Technical Information (OSTI.GOV)

Stratakis, Diktys; Berg, Scott; Neuffer, David

2017-03-16

We present a muon capture front-end scheme for muon based applications. In this Front-End design, a proton bunch strikes a target and creates secondary pions that drift into a capture channel, decaying into muons. A series of rf cavities forms the resulting muon beams into a series of bunches of differerent energies, aligns the bunches to equal central energies, and initiates ionization cooling. We also discuss the design of a chicane system for the removal of unwanted secondary particles from the muon capture region and thus reduce activation of the machine. With the aid of numerical simulations we evaluate themore » performance of this Front-End scheme as well as study its sensitivity against key parameters such as the type of target, the number of rf cavities and the gas pressure of the channel.« less

High-Frequency Wireless Communications System: 2.45-GHz Front-End Circuit and System Integration

ERIC Educational Resources Information Center

Chen, M.-H.; Huang, M.-C.; Ting, Y.-C.; Chen, H.-H.; Li, T.-L.

2010-01-01

In this article, a course on high-frequency wireless communications systems is presented. With the 145-MHz baseband subsystem available from a prerequisite course, the present course emphasizes the design and implementation of the 2.45-GHz front-end subsystem as well as system integration issues. In this curriculum, the 2.45-GHz front-end…

A Bio-Realistic Analog CMOS Cochlea Filter With High Tunability and Ultra-Steep Roll-Off.

PubMed

Wang, Shiwei; Koickal, Thomas Jacob; Hamilton, Alister; Cheung, Rebecca; Smith, Leslie S

2015-06-01

This paper presents the design and experimental results of a cochlea filter in analog very large scale integration (VLSI) which highly resembles physiologically measured response of the mammalian cochlea. The filter consists of three specialized sub-filter stages which respectively provide passive response in low frequencies, actively tunable response in mid-band frequencies and ultra-steep roll-off at transition frequencies from pass-band to stop-band. The sub-filters are implemented in balanced ladder topology using floating active inductors. Measured results from the fabricated chip show that wide range of mid-band tuning including gain tuning of over 20 dB, Q factor tuning from 2 to 19 as well as the bio-realistic center frequency shift are achieved by adjusting only one circuit parameter. Besides, the filter has an ultra-steep roll-off reaching over 300 dB/dec. By changing biasing currents, the filter can be configured to operate with center frequencies from 31 Hz to 8 kHz. The filter is 9th order, consumes 59.5 ∼ 90.0 μW power and occupies 0.9 mm2 chip area. A parallel bank of the proposed filter can be used as the front-end in hearing prosthesis devices, speech processors as well as other bio-inspired auditory systems owing to its bio-realistic behavior, low power consumption and small size.

Single-chip photonic transceiver based on bulk-silicon, as a chip-level photonic I/O platform for optical interconnects.

PubMed

Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Kim, In Gyoo; Oh, Jin Hyuk; Kim, Sun Ae; Park, Jaegyu; Kim, Sanggi

2015-06-10

When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube, and LAN, SAN, data center and network applications.

Readout electronics for LGAD sensors

NASA Astrophysics Data System (ADS)

Alonso, O.; Franch, N.; Canals, J.; Palacio, F.; López, M.; Vilà, A.; Diéguez, A.; Carulla, M.; Flores, D.; Hidalgo, S.; Merlos, A.; Pellegrini, G.; Quirion, D.

2017-02-01

In this paper, an ASIC fabricated in 180 nm CMOS technology from AMS with the very front-end electronics used to readout LGAD sensors is presented as well as its experimental results. The front-end has the typical architecture for Si-strip readout, i.e., preamplification stage with a Charge Sensitive Amplifier (CSA) followed by a CR-RC shaper. Both amplifiers are based on a folded cascode structure with a PMOS input transistor and the shaper only uses passive elements for the feedback stage. The CSA has programmable gain and a configurable input stage in order to adapt to the different input capacitance of the LGAD sensors (pixelated, short and long strips) and to the different input signal (depending on the gain of the LGAD). The fabricated prototype has an area of 0.865 mm × 0.965 mm and includes the biasing circuit for the CSA and the shaper, 4 analog channels (CSA+shaper) and programmable charge injection circuits included for testing purposes. Noise and power analysis performed during simulation fixed the size of the input transistor to W/L = 860 μm/0.2 μm. The shaping time is fixed by design at 1 us and, in this ASIC version, the feedback elements of the shaper are passive, which means that the area of the shaper can be reduced using active elements in future versions. Finally, the different gains of the CSA have been selected to maintain an ENC below 400 electrons for a detector capacitor of 20 pF, with a power consumption of 150 μ W per channel.

United States Air Force Summer Faculty Research Program, 1988. Program Technical Report. Volume 4

DTIC Science & Technology

1988-12-01

Professor SDecialty: Gas Phase Ion-Molecule Chem. Dept. of Chemistry Assigned: Air Force Geophysics Lab. Louisiana State University Choppin Hall...For Lucid Dr. Darin DeForest 55 Pre-Sort Processor Phase Distortion Dr. Paul Dingman Evaluation 56 A PROLOG Natural Language Front End Dr. Hugh...analysis in the electron impact mode. The column used was 25m x 0.25am ID bonded phase FSOT capillary column (#952525 Alltech and Associates), coated with

View southwest, east front, interior bays, and north end ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

View southwest, east front, interior bays, and north end - Abraham Cyrus Farmstead, Equipment Shed, About 320 feet south-southwest of farmhouse at 3271 Cyrus Road (County Road 1/6), Cyrus, Wayne County, WV

4. DETAIL OF SOUTH (FRONT) ELEVATION AT EAST END OF ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

4. DETAIL OF SOUTH (FRONT) ELEVATION AT EAST END OF PORCH WITH STRUCTURAL SYSTEM OF WOOD FRAME WITH BRICK NOGGING REVEALED. - Andalusia, The Cottage, State Road vicinity (Bensalem Township), Andalusia, Bucks County, PA

5. Bombproof barracks, front elevation at southwest end. Doors and ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

5. Bomb-proof barracks, front elevation at southwest end. Doors and windows covered with plywood. Railway and car stop in foreground. - Fort Hamilton, Bomb-Proof Barracks, Rose Island, Newport, Newport County, RI

Optimization of the microcable and detector parameters towards low noise in the STS readout system

NASA Astrophysics Data System (ADS)

Kasinski, Krzysztof; Kleczek, Rafal; Schmidt, Christian J.

2015-09-01

Successful operation of the Silicon Tracking System requires charge measurement of each hit with equivalent noise charge lower than 1000 e- rms. Detector channels will not be identical, they will be constructed accordingly to the estimated occupancy, therefore for the readout electronics, detector system will exhibit various parameters. This paper presents the simulation-based study on the required microcable (trace width, dielectric material), detector (aluminum strip resistance) and external passives' (decoupling capacitors) parameters in the Silicon Tracking System. Studies will be performed using a front-end electronics (charge sensitive amplifier with shaper) designed for the power budget of 10 mA/channel.

Hybridization-based biosensor containing hairpin probes and use thereof

DOEpatents

Miller, Benjamin L.; Strohsahl, Christopher M.

2010-10-12

A sensor chip that includes: a fluorescence quenching surface; a nucleic acid probe that contains first and second ends with the first end bound to the fluorescence quenching surface, and is characterized by being able to self-anneal into a hairpin conformation; and a first fluorophore bound to the second end of the first nucleic acid molecule. When the first nucleic acid molecule is in the hairpin conformation, the fluorescence quenching surface substantially quenches fluorescent emissions by the first fluorophore; and when the first nucleic acid molecule is in a non-hairpin conformation, fluorescent emissions by the fluorophore are substantially free of quenching by the fluorescence quenching surface. Various nucleic acid probes, methods of making the sensor chip, biological sensor devices that contain the sensor chip, and their methods of use are also disclosed.

Understanding and addressing racial/ethnic disproportionality in the front end of the child welfare system.

PubMed

Osterling, Kathy Lemon; D'Andrade, Amy; Austin, Michael J

2008-01-01

Racial/ethnic disproportionality in the child welfare system is a complicated social problem that is receiving increasing amounts of attention from researchers and practitioners. This review of the literature examines disproportionality in the front-end of the child welfare system and interventions that may address it. While none of the interventions had evidence suggesting that they reduced disproportionality in child welfare front-end processes, some of the interventions may improve child welfare case processes related to disproportionality and outcomes for families of color.

Performance of High-Speed PWM Control Chips at Cryogenic Temperatures

NASA Technical Reports Server (NTRS)

Elbuluk, Malik E.; Gerber, Scott; Hammoud, Ahmad; Patterson, Richard; Overton, Eric

2001-01-01

The operation of power electronic systems at cryogenic temperatures is anticipated in many NASA space missions such as planetary exploration and deep space probes. In addition to surviving the space hostile environment, electronics capable of low temperature operation would contribute to improving circuit performance, increasing system efficiency, and reducing development and launch costs. As part of the NASA Glenn Low Temperature Electronics Program, several commercial high-speed Pulse Width Modulation (PWM) chips have been characterized in terms of their performance as a function of temperature in the range of 25 to -196 C (liquid nitrogen). These chips ranged in their electrical characteristics, modes of control, packaging options, and applications. The experimental procedures along with the experimental data obtained on the investigated chips are presented and discussed.

VIEW OF BASE END STATION BARLOW SHOWING THE SUGGESTED APPEARANCE ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

VIEW OF BASE END STATION BARLOW SHOWING THE SUGGESTED APPEARANCE DURING USE (TOP IS NOT EXTANT INDICATING POST-USE DAMAGE), PACING NORTHWEST, VIEW IS OF THE FRONT, WITH THE RIGHT FRONT CORNER EXPOSED - White's Point Reservation, Base End Stations, B"1, Bounded by Voyager Circle & Mariner Drive, San Pedro, Los Angeles County, CA

Source-Constrained Recall: Front-End and Back-End Control of Retrieval Quality

ERIC Educational Resources Information Center

Halamish, Vered; Goldsmith, Morris; Jacoby, Larry L.

2012-01-01

Research on the strategic regulation of memory accuracy has focused primarily on monitoring and control processes used to edit out incorrect information after it is retrieved (back-end control). Recent studies, however, suggest that rememberers also enhance accuracy by preventing the retrieval of incorrect information in the first place (front-end…

42 CFR 457.348 - Determinations of Children's Health Insurance Program eligibility by other insurance...

Code of Federal Regulations, 2012 CFR

2012-10-01

... insurance affordability program. (b) Provision of CHIP for individuals found eligible for CHIP by another insurance affordability program. If a State accepts final determinations of CHIP eligibility made by another... electronic account containing the determination of CHIP eligibility; and (2) Comply with the provisions of...

42 CFR 457.348 - Determinations of Children's Health Insurance Program eligibility by other insurance...

Code of Federal Regulations, 2014 CFR

2014-10-01

... insurance affordability program. (b) Provision of CHIP for individuals found eligible for CHIP by another insurance affordability program. If a State accepts final determinations of CHIP eligibility made by another... electronic account containing the determination of CHIP eligibility; and (2) Comply with the provisions of...

42 CFR 457.348 - Determinations of Children's Health Insurance Program eligibility by other insurance...

Code of Federal Regulations, 2013 CFR

2013-10-01

... insurance affordability program. (b) Provision of CHIP for individuals found eligible for CHIP by another insurance affordability program. If a State accepts final determinations of CHIP eligibility made by another... electronic account containing the determination of CHIP eligibility; and (2) Comply with the provisions of...

Noise temperature improvement for magnetic fusion plasma millimeter wave imaging systems.

PubMed

Lai, J; Domier, C W; Luhmann, N C

2014-03-01

Significant progress has been made in the imaging and visualization of magnetohydrodynamic and microturbulence phenomena in magnetic fusion plasmas [B. Tobias et al., Plasma Fusion Res. 6, 2106042 (2011)]. Of particular importance have been microwave electron cyclotron emission imaging and microwave imaging reflectometry systems for imaging T(e) and n(e) fluctuations. These instruments have employed heterodyne receiver arrays with Schottky diode mixer elements directly connected to individual antennas. Consequently, the noise temperature has been strongly determined by the conversion loss with typical noise temperatures of ~60,000 K. However, this can be significantly improved by making use of recent advances in Monolithic Microwave Integrated Circuit chip low noise amplifiers to insert a pre-amplifier in front of the Schottky diode mixer element. In a proof-of-principle design at V-Band (50-75 GHz), significant improvement of noise temperature from the current 60,000 K to measured 4000 K has been obtained.

Actuation and transduction of resonant vibrations in GaAs/AlGaAs-based nanoelectromechanical systems containing two-dimensional electron gas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shevyrin, A. A., E-mail: shevandrey@isp.nsc.ru; Pogosov, A. G.; Bakarov, A. K.

2015-05-04

Driven vibrations of a nanoelectromechanical system based on GaAs/AlGaAs heterostructure containing two-dimensional electron gas are experimentally investigated. The system represents a conductive cantilever with the free end surrounded by a side gate. We show that out-of-plane flexural vibrations of the cantilever are driven when alternating signal biased by a dc voltage is applied to the in-plane side gate. We demonstrate that these vibrations can be on-chip linearly transduced into a low-frequency electrical signal using the heterodyne down-mixing method. The obtained data indicate that the dominant physical mechanism of the vibrations actuation is capacitive interaction between the cantilever and the gate.

35. EAST FRONT OF POWERHOUSE AND CAR BARN: East front ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

35. EAST FRONT OF POWERHOUSE AND CAR BARN: East front of powerhouse and car barn. 'Annex' is right end of building. - San Francisco Cable Railway, Washington & Mason Streets, San Francisco, San Francisco County, CA

Towards an Analogue Neuromorphic VLSI Instrument for the Sensing of Complex Odours

NASA Astrophysics Data System (ADS)

Ab Aziz, Muhammad Fazli; Harun, Fauzan Khairi Che; Covington, James A.; Gardner, Julian W.

2011-09-01

Almost all electronic nose instruments reported today employ pattern recognition algorithms written in software and run on digital processors, e.g. micro-processors, microcontrollers or FPGAs. Conversely, in this paper we describe the analogue VLSI implementation of an electronic nose through the design of a neuromorphic olfactory chip. The modelling, design and fabrication of the chip have already been reported. Here a smart interface has been designed and characterised for thisneuromorphic chip. Thus we can demonstrate the functionality of the a VLSI neuromorphic chip, producing differing principal neuron firing patterns to real sensor response data. Further work is directed towards integrating 9 separate neuromorphic chips to create a large neuronal network to solve more complex olfactory problems.

Advanced integrated safeguards using front-end-triggering devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Howell, J.A.; Whitty, W.J.

This report addresses potential uses of front-end-triggering devices for enhanced safeguards. Such systems incorporate video surveillance as well as radiation and other sensors. Also covered in the report are integration issues and analysis techniques.

2. SHED, SOUTH END OF SHORTER BARRACKS, FRONT AND RIGHT ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

2. SHED, SOUTH END OF SHORTER BARRACKS, FRONT AND RIGHT SIDES, LOOKING SOUTHWEST. - NIKE Missile Base C-84, Paint & Oil Storage Shed, South of Launch Area Entrance Drive, near security fence, Barrington, Cook County, IL

2. VIEW OF NORTHWEST SIDE SHOWING NORTHEAST (GABLE END) FRONT. ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

2. VIEW OF NORTHWEST SIDE SHOWING NORTHEAST (GABLE END) FRONT. (BUILDING 114 IS VISIBLE ON RIGHT.) - Fort McPherson, World War II Station Hospital, G. U. Treatment Unit Dispensary, Thorne Avenue, Atlanta, Fulton County, GA

Chip morphology as a performance predictor during high speed end milling of soda lime glass

NASA Astrophysics Data System (ADS)

Bagum, M. N.; Konneh, M.; Abdullah, K. A.; Ali, M. Y.

2018-01-01

Soda lime glass has application in DNA arrays and lab on chip manufacturing. Although investigation revealed that machining of such brittle material is possible using ductile mode under controlled cutting parameters and tool geometry, it remains a challenging task. Furthermore, ability of ductile machining is usually assed through machined surface texture examination. Soda lime glass is a strain rate and temperature sensitive material. Hence, influence on attainment of ductile surface due to adiabatic heat generated during high speed end milling using uncoated tungsten carbide tool is investigated in this research. Experimental runs were designed using central composite design (CCD), taking spindle speed, feed rate and depth of cut as input variable and tool-chip contact point temperature (Ttc) and the surface roughness (Rt) as responses. Along with machined surface texture, Rt and chip morphology was examined to assess machinability of soda lime glass. The relation between Ttc and chip morphology was examined. Investigation showed that around glass transition temperature (Tg) ductile chip produced and subsequently clean and ductile final machined surface produced.

Assessment of a Low-Power 65 nm CMOS Technology for Analog Front-End Design

NASA Astrophysics Data System (ADS)

Manghisoni, Massimo; Gaioni, Luigi; Ratti, Lodovico; Re, Valerio; Traversi, Gianluca

2014-02-01

This work is concerned with the study of the analog properties of MOSFET devices belonging to a 65 nm CMOS technology with emphasis on intrinsic voltage gain and noise performance. This node appears to be a robust and promising solution to cope with the unprecedented requirements set by silicon vertex trackers in experiments upgrades and future colliders as well as by imaging detectors at light sources and free electron lasers. In this scaled-down technology, the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. An inversion level design methodology has been adopted to analyze data obtained from device measurements and provide a powerful tool to establish design criteria for detector front-ends in this nanoscale CMOS process. A comparison with data coming from less scaled technologies, such as 90 nm and 130 nm nodes, is also provided and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100 nm minimum feature size range.

Photon beam position monitor

DOEpatents

Kuzay, T.M.; Shu, D.

1995-02-07

A photon beam position monitor is disclosed for use in the front end of a beamline of a high heat flux and high energy photon source such as a synchrotron radiation storage ring detects and measures the position and, when a pair of such monitors are used in tandem, the slope of a photon beam emanating from an insertion device such as a wiggler or an undulator inserted in the straight sections of the ring. The photon beam position monitor includes a plurality of spaced blades for precisely locating the photon beam, with each blade comprised of chemical vapor deposition (CVD) diamond with an outer metal coating of a photon sensitive metal such as tungsten, molybdenum, etc., which combination emits electrons when a high energy photon beam is incident upon the blade. Two such monitors are contemplated for use in the front end of the beamline, with the two monitors having vertically and horizontally offset detector blades to avoid blade ''shadowing''. Provision is made for aligning the detector blades with the photon beam and limiting detector blade temperature during operation. 18 figs.