Monolithic pixel development in TowerJazz 180 nm CMOS for the outer pixel layers in the ATLAS experiment

NASA Astrophysics Data System (ADS)

Berdalovic, I.; Bates, R.; Buttar, C.; Cardella, R.; Egidos Plaja, N.; Hemperek, T.; Hiti, B.; van Hoorne, J. W.; Kugathasan, T.; Mandic, I.; Maneuski, D.; Marin Tobon, C. A.; Moustakas, K.; Musa, L.; Pernegger, H.; Riedler, P.; Riegel, C.; Schaefer, D.; Schioppa, E. J.; Sharma, A.; Snoeys, W.; Solans Sanchez, C.; Wang, T.; Wermes, N.

2018-01-01

The upgrade of the ATLAS tracking detector (ITk) for the High-Luminosity Large Hadron Collider at CERN requires the development of novel radiation hard silicon sensor technologies. Latest developments in CMOS sensor processing offer the possibility of combining high-resistivity substrates with on-chip high-voltage biasing to achieve a large depleted active sensor volume. We have characterised depleted monolithic active pixel sensors (DMAPS), which were produced in a novel modified imaging process implemented in the TowerJazz 180 nm CMOS process in the framework of the monolithic sensor development for the ALICE experiment. Sensors fabricated in this modified process feature full depletion of the sensitive layer, a sensor capacitance of only a few fF and radiation tolerance up to 1015 neq/cm2. This paper summarises the measurements of charge collection properties in beam tests and in the laboratory using radioactive sources and edge TCT. The results of these measurements show significantly improved radiation hardness obtained for sensors manufactured using the modified process. This has opened the way to the design of two large scale demonstrators for the ATLAS ITk. To achieve a design compatible with the requirements of the outer pixel layers of the tracker, a charge sensitive front-end taking 500 nA from a 1.8 V supply is combined with a fast digital readout architecture. The low-power front-end with a 25 ns time resolution exploits the low sensor capacitance to reduce noise and analogue power, while the implemented readout architectures minimise power by reducing the digital activity.

SPIDR, a general-purpose readout system for pixel ASICs

NASA Astrophysics Data System (ADS)

van der Heijden, B.; Visser, J.; van Beuzekom, M.; Boterenbrood, H.; Kulis, S.; Munneke, B.; Schreuder, F.

2017-02-01

The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a "soft core" CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four 10 Gigabit Ethernet links, and in addition provides the slow and fast control for the chip.

Potential Application of BIOMASS Technology at National Space Technology Laboratories and Mississippi Army Ammunition Plant.

DTIC Science & Technology

1980-02-01

fuel. Based on the survey data, wood chips in the NSTL area are sold for $13 to $16 per wet ton ($14 to $18 Der l03 kg wet), bark for $6 to $7 per wet...truck 3 Chip vans (initially) 1 Pickup (3/4 ton) 1 Front-end loader (for handling at chip pile) This equipment combination assumes all material ]-inch...ing sites in chip vans , preferably with live-beds to aid in unloading. At the processing site the chips would be stored in large piles. A Front-end

Characterization of Pixelated Cadmium-Zinc-Telluride Detectors for Astrophysical Applications

NASA Technical Reports Server (NTRS)

Gaskin, Jessica; Sharma, Dharma; Ramsey, Brian; Seller, Paul

2003-01-01

Comparisons of charge sharing and charge loss measurements between two pixelated Cadmium-Zinc-Telluride (CdZnTe) detectors are discussed. These properties along with the detector geometry help to define the limiting energy resolution and spatial resolution of the detector in question. The first detector consists of a 1-mm-thick piece of CdZnTe sputtered with a 4x4 array of pixels with pixel pitch of 750 microns (inter-pixel gap is 100 microns). Signal readout is via discrete ultra-low-noise preamplifiers, one for each of the 16 pixels. The second detector consists of a 2-mm-thick piece of CdZnTe sputtered with a 16x16 array of pixels with a pixel pitch of 300 microns (inter-pixel gap is 50 microns). This crystal is bonded to a custom-built readout chip (ASIC) providing all front-end electronics to each of the 256 independent pixels. These detectors act as precursors to that which will be used at the focal plane of the High Energy Replicated Optics (HERO) telescope currently being developed at Marshall Space Flight Center. With a telescope focal length of 6 meters, the detector needs to have a spatial resolution of around 200 microns in order to take full advantage of the HERO angular resolution. We discuss to what degree charge sharing will degrade energy resolution but will improve our spatial resolution through position interpolation.

The DIRC front-end electronics chain for BaBar

NASA Astrophysics Data System (ADS)

Bailly, P.; Beigbeder, C.; Bernier, R.; Breton, D.; Bonneaud, G.; Caceres, T.; Chase, R.; Chauveau, J.; Del Buono, L.; Dohou, F.; Ducorps, A.; Gastaldi, F.; Genat, J. F.; Hrisoho, A.; Imbert, P.; Lebbolo, H.; Matricon, P.; Oxoby, G.; Renard, C.; Roos, L.; Sen, S.; Thiebaux, C.; Truong, K.; Tocut, V.; Vasileiadis, G.; Va'Vra, J.; Verderi, M.; Warner, D.; Wilson, R. J.; Wormser, G.; Zhang, B.; Zomer, F.

2000-12-01

Recent results from the Front-End electronics of the Detector of Internally Reflected Cerenkov light (DIRC) for the BaBar experiment at SLAC (Stanford, USA) are presented. It measures to better than 1 ns the arrival time of Cerenkov photoelectrons detected in a 11000 phototubes array and their amplitude spectra. It mainly comprises 64-channel DIRC Front-End Boards (DFB) equipped with eight full-custom analog chips performing zero-cross discrimination with 2 mV threshold and pulse shaping, four full-custom digital time to digital chips (TDC) for timing measurements with 500 ps binning and a readout logic selecting hits in the trigger window, and DIRC Crate Controller cards (DCC) serializing the data collected front up to 16 DFBs onto a 1.2 Gb/s optical link. Extensive test results of the pre-production chips are presented, as well as system tests.

The 150 ns detector project: Prototype preamplifier results

NASA Astrophysics Data System (ADS)

Warburton, W. K.; Russell, S. R.; Kleinfelder, Stuart A.

1994-08-01

The long-term goal of the 150 ns detector project is to develop a pixel area detector capable of 6 MHz frame rates (150 ns/frame). Our milestones toward this goal are: a single pixel, 1×256 1D and 8×8 2D detectors, 256×256 2D detectors and, finally, 1024 × 1024 2D detectors. The design strategy is to supply a complete electronics chain (resetting preamp, selectable gain amplifier, analog-to-digital converter (ADC), and memory) for each pixel. In the final detectors these will all be custom integrated circuits. The front-end preamplifiers are integrated first, since their design and performance are the most unusual and also critical to the project's success. Similarly, our early work is concentrated on devising and perfecting detector structures. In this paper we demonstrate the performance of prototypes of our integrated preamplifiers. While the final design will have 64 preamps to a chip, including a switchable gain stage, the prototypes were integrated 8 channels to a "Tiny Chip" and tested in 4 configurations (feedback capacitor Cf equal 2.5 or 4.0 pF, output directly or through a source follower). These devices have been tested thoroughly for reset settling times, gain, linearity, and electronic noise. They generally work as designed, being fast enough to easily integrate detector charge, settle, and reset in 150 ns. Gain and linearity appear to be acceptable. Current values of electronic noise, in double-sampling mode, are about twice the design goal of {2}/{3} of a single photon at 6 keV. We expect this figure to improve with the addition of the onboard amplifier stage and improved packaging. Our next test chip will include these improvements and allow testing with our first detector samples, which will be 1×256 (50 μm wide pixels) and 8×8 (1 mm 2 pixels) element detector on 1 mm thick silicon.

MEDIPIX: a VLSI chip for a GaAs pixel detector for digital radiology

NASA Astrophysics Data System (ADS)

Amendolia, S. R.; Bertolucci, E.; Bisogni, M. G.; Bottigli, U.; Ceccopieri, A.; Ciocci, M. A.; Conti, M.; Delogu, P.; Fantacci, M. E.; Maestro, P.; Marzulli, V.; Pernigotti, E.; Romeo, N.; Rosso, V.; Rosso, P.; Stefanini, A.; Stumbo, S.

1999-02-01

A GaAs pixel detector designed for digital mammography, equipped with a 36-channel single photon counting discrete read-out electronics, was tested using a test object developed for quality control purposes in mammography. Each pixel was 200×200 μm 2 large, and 200 μm deep. The choice of GaAs with respect to silicon (largely used in other applications and with a more established technique) has been made because of the much better detection efficiency at mammographic energies, combined with a very good charge collection efficiency achieved thanks to new ohmic contacts. This GaAs detector is able to perform a measurement of low-contrast details, with minimum contrast lower (nearly a factor two) than that typically achievable with standard mammographic film+screen systems in the same conditions of clinical routine. This should allow for an earlier diagnosis of breast tumour masses. Due to these encouraging results, the next step in the evolution of our imaging system based on GaAs detectors has been the development of a VLSI front-end prototype chip (MEDIPIX ) in order to cover a much larger diagnostic area. The chip reads 64×64 channels in single photon counting mode, each one 170 μm wide. Each channel contains also a test input where a signal can be simulated, injecting a known charge through a 16 f F capacitor. Fake signals have been injected via the test input measuring and equalizing minimum thresholds for all the channels. On an average, in most of the performing chips available up to now, we have found that it is possible to set a threshold as low as 1800 electrons with an RMS of 150 electrons (10 standard deviations lower than the 20 keV photon signal roughly equivalent to 4500 electrons). The detector, bump-bonded to the chip, will be tested and a ladder of detectors will be prepared to be able to scan large surface objects.

An asynchronous data-driven readout prototype for CEPC vertex detector

NASA Astrophysics Data System (ADS)

Yang, Ping; Sun, Xiangming; Huang, Guangming; Xiao, Le; Gao, Chaosong; Huang, Xing; Zhou, Wei; Ren, Weiping; Li, Yashu; Liu, Jianchao; You, Bihui; Zhang, Li

2017-12-01

The Circular Electron Positron Collider (CEPC) is proposed as a Higgs boson and/or Z boson factory for high-precision measurements on the Higgs boson. The precision of secondary vertex impact parameter plays an important role in such measurements which typically rely on flavor-tagging. Thus silicon CMOS Pixel Sensors (CPS) are the most promising technology candidate for a CEPC vertex detector, which can most likely feature a high position resolution, a low power consumption and a fast readout simultaneously. For the R&D of the CEPC vertex detector, we have developed a prototype MIC4 in the Towerjazz 180 nm CMOS Image Sensor (CIS) process. We have proposed and implemented a new architecture of asynchronous zero-suppression data-driven readout inside the matrix combined with a binary front-end inside the pixel. The matrix contains 128 rows and 64 columns with a small pixel pitch of 25 μm. The readout architecture has implemented the traditional OR-gate chain inside a super pixel combined with a priority arbiter tree between the super pixels, only reading out relevant pixels. The MIC4 architecture will be introduced in more detail in this paper. It will be taped out in May and will be characterized when the chip comes back.

Continuous-time ΣΔ ADC with implicit variable gain amplifier for CMOS image sensor.

PubMed

Tang, Fang; Bermak, Amine; Abbes, Amira; Benammar, Mohieddine Amor

2014-01-01

This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

Monolithic active pixel sensor development for the upgrade of the ALICE inner tracking system

NASA Astrophysics Data System (ADS)

Aglieri, G.; Cavicchioli, C.; Chalmet, P. L.; Chanlek, N.; Collu, A.; Giubilato, P.; Hillemanns, H.; Junique, A.; Keil, M.; Kim, D.; Kim, J.; Kugathasan, T.; Lattuca, A.; Mager, M.; Marin Tobon, C. A.; Marras, D.; Martinengo, P.; Mattiazzo, S.; Mazza, G.; Mugnier, H.; Musa, L.; Pantano, D.; Puggioni, C.; Rousset, J.; Reidt, F.; Riedler, P.; Siddhanta, S.; Snoeys, W.; Usai, G.; van Hoorne, J. W.; Yang, P.; Yi, J.

2013-12-01

ALICE plans an upgrade of its Inner Tracking System for 2018. The development of a monolithic active pixel sensor for this upgrade is described. The TowerJazz 180 nm CMOS imaging sensor process has been chosen as it is possible to use full CMOS in the pixel due to the offering of a deep pwell and also to use different starting materials. The ALPIDE development is an alternative to approaches based on a rolling shutter architecture, and aims to reduce power consumption and integration time by an order of magnitude below the ALICE specifications, which would be quite beneficial in terms of material budget and background. The approach is based on an in-pixel binary front-end combined with a hit-driven architecture. Several prototypes have already been designed, submitted for fabrication and some of them tested with X-ray sources and particles in a beam. Analog power consumption has been limited by optimizing the Q/C of the sensor using Explorer chips. Promising but preliminary first results have also been obtained with a prototype ALPIDE. Radiation tolerance up to the ALICE requirements has also been verified.

The phase 1 upgrade of the CMS Pixel Front-End Driver

NASA Astrophysics Data System (ADS)

Friedl, M.; Pernicka, M.; Steininger, H.

2010-12-01

The pixel detector of the CMS experiment at the LHC is read out by analog optical links, sending the data to 9U VME Front-End Driver (FED) boards located in the electronics cavern. There are plans for the phase 1 upgrade of the pixel detector (2016) to add one more layer, while significantly cutting down the overall material budget. At the same time, the optical data transmission will be replaced by a serialized digital scheme. A plug-in board solution with a high-speed digital optical receiver has been developed for the Pixel-FED readout boards and will be presented along with first tests of the future optical link.

A time-based front-end ASIC for the silicon micro strip sensors of the bar PANDA Micro Vertex Detector

NASA Astrophysics Data System (ADS)

Di Pietro, V.; Brinkmann, K.-Th.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Zambanini, A.

2016-03-01

The bar PANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA (bar PANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels.

JFET front-end circuits integrated in a detector-grade silicon substrate

NASA Astrophysics Data System (ADS)

Manghisoni, M.; Ratti, L.; Re, V.; Speziali, V.; Traversi, G.; Dalla Betta, G. F.; Boscardin, M.; Batignani, G.; Giorgi, M.; Bosisio, L.

2003-08-01

This paper presents the design and experimental results relevant to front-end circuits integrated on detector-grade high resistivity silicon. The fabrication technology is made available by the Istituto per la Ricerca Scientifica e Tecnologica (ITC-IRST), Trento, Italy and allows using a common substrate for different kinds of active devices, such as N-channel JFETs and MOSFETs, and for pixel, microstrip, and PIN detectors. This research activity is being carried out in the framework of a project aiming at the fabrication of a multichannel mixed analog-digital chip for the readout of solid-state detectors integrated in the same substrate. Possible applications are in the field of medical and industrial imaging and space and high energy physics experiments. An all-JFET charge sensitive amplifier, which can use either a resistive or a nonresistive feedback network, has been characterized. The two configurations have been compared to each other, paying particular attention to noise performances, in view of the design of the complete readout channel. Operation capability in harsh radiation environment has been evaluated through exposure to /spl gamma/-rays from a /sup 60/Co source.

Fully 3D-Integrated Pixel Detectors for X-Rays

DOE PAGES

Deptuch, Grzegorz W.; Gabriella, Carini; Enquist, Paul; ...

2016-01-01

The vertically integrated photon imaging chip (VIPIC1) pixel detector is a stack consisting of a 500-μm-thick silicon sensor, a two-tier 34-μm-thick integrated circuit, and a host printed circuit board (PCB). The integrated circuit tiers were bonded using the direct bonding technology with copper, and each tier features 1-μm-diameter through-silicon vias that were used for connections to the sensor on one side, and to the host PCB on the other side. The 80-μm-pixel-pitch sensor was the direct bonding technology with nickel bonded to the integrated circuit. The stack was mounted on the board using Sn–Pb balls placed on a 320-μm pitch,more » yielding an entirely wire-bond-less structure. The analog front-end features a pulse response peaking at below 250 ns, and the power consumption per pixel is 25 μW. We successful completed the 3-D integration and have reported here. Additionally, all pixels in the matrix of 64 × 64 pixels were responding on well-bonded devices. Correct operation of the sparsified readout, allowing a single 153-ns bunch timing resolution, was confirmed in the tests on a synchrotron beam of 10-keV X-rays. An equivalent noise charge of 36.2 e - rms and a conversion gain of 69.5 μV/e - with 2.6 e - rms and 2.7 μV/e - rms pixel-to-pixel variations, respectively, were measured.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deptuch, Grzegorz W.; Gabriella, Carini; Enquist, Paul

The vertically integrated photon imaging chip (VIPIC1) pixel detector is a stack consisting of a 500-μm-thick silicon sensor, a two-tier 34-μm-thick integrated circuit, and a host printed circuit board (PCB). The integrated circuit tiers were bonded using the direct bonding technology with copper, and each tier features 1-μm-diameter through-silicon vias that were used for connections to the sensor on one side, and to the host PCB on the other side. The 80-μm-pixel-pitch sensor was the direct bonding technology with nickel bonded to the integrated circuit. The stack was mounted on the board using Sn–Pb balls placed on a 320-μm pitch,more » yielding an entirely wire-bond-less structure. The analog front-end features a pulse response peaking at below 250 ns, and the power consumption per pixel is 25 μW. We successful completed the 3-D integration and have reported here. Additionally, all pixels in the matrix of 64 × 64 pixels were responding on well-bonded devices. Correct operation of the sparsified readout, allowing a single 153-ns bunch timing resolution, was confirmed in the tests on a synchrotron beam of 10-keV X-rays. An equivalent noise charge of 36.2 e - rms and a conversion gain of 69.5 μV/e - with 2.6 e - rms and 2.7 μV/e - rms pixel-to-pixel variations, respectively, were measured.« less

Characterization of the Photon Counting CHASE Jr., Chip Built in a 40-nm CMOS Process With a Charge Sharing Correction Algorithm Using a Collimated X-Ray Beam

DOE Office of Scientific and Technical Information (OSTI.GOV)

Krzyżanowska, A.; Deptuch, G. W.; Maj, P.

This paper presents the detailed characterization of a single photon counting chip, named CHASE Jr., built in a CMOS 40-nm process, operating with synchrotron radiation. The chip utilizes an on-chip implementation of the C8P1 algorithm. The algorithm eliminates the charge sharing related uncertainties, namely, the dependence of the number of registered photons on the discriminator’s threshold, set for monochromatic irradiation, and errors in the assignment of an event to a certain pixel. The article presents a short description of the algorithm as well as the architecture of the CHASE Jr., chip. The analog and digital functionalities, allowing for proper operationmore » of the C8P1 algorithm are described, namely, an offset correction for two discriminators independently, two-stage gain correction, and different operation modes of the digital blocks. The results of tests of the C8P1 operation are presented for the chip bump bonded to a silicon sensor and exposed to the 3.5- μm -wide pencil beam of 8-keV photons of synchrotron radiation. It was studied how sensitive the algorithm performance is to the chip settings, as well as the uniformity of parameters of the analog front-end blocks. Presented results prove that the C8P1 algorithm enables counting all photons hitting the detector in between readout channels and retrieving the actual photon energy.« less

A new data acquisition system for the CMS Phase 1 pixel detector

NASA Astrophysics Data System (ADS)

Kornmayer, A.

2016-12-01

A new pixel detector will be installed in the CMS experiment during the extended technical stop of the LHC at the beginning of 2017. The new pixel detector, built from four layers in the barrel region and three layers on each end of the forward region, is equipped with upgraded front-end readout electronics, specifically designed to handle the high particle hit rates created in the LHC environment. The DAQ back-end was entirely redesigned to handle the increased number of readout channels, the higher data rates per channel and the new digital data format. Based entirely on the microTCA standard, new front-end controller (FEC) and front-end driver (FED) cards have been developed, prototyped and produced with custom optical link mezzanines mounted on the FC7 AMC and custom firmware. At the same time as the new detector is being assembled, the DAQ system is set up and its integration into the CMS central DAQ system tested by running the pilot blade detector already installed in CMS. This work describes the DAQ system, integration tests and gives an outline for the activities up to commissioning the final system at CMS in 2017.

Front end optimization for the monolithic active pixel sensor of the ALICE Inner Tracking System upgrade

NASA Astrophysics Data System (ADS)

Kim, D.; Aglieri Rinella, G.; Cavicchioli, C.; Chanlek, N.; Collu, A.; Degerli, Y.; Dorokhov, A.; Flouzat, C.; Gajanana, D.; Gao, C.; Guilloux, F.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kofarago, M.; Kugathasan, T.; Kwon, Y.; Lattuca, A.; Mager, M.; Sielewicz, K. M.; Marin Tobon, C. A.; Marras, D.; Martinengo, P.; Mazza, G.; Mugnier, H.; Musa, L.; Pham, T. H.; Puggioni, C.; Reidt, F.; Riedler, P.; Rousset, J.; Siddhanta, S.; Snoeys, W.; Song, M.; Usai, G.; Van Hoorne, J. W.; Yang, P.

2016-02-01

ALICE plans to replace its Inner Tracking System during the second long shut down of the LHC in 2019 with a new 10 m2 tracker constructed entirely with monolithic active pixel sensors. The TowerJazz 180 nm CMOS imaging Sensor process has been selected to produce the sensor as it offers a deep pwell allowing full CMOS in-pixel circuitry and different starting materials. First full-scale prototypes have been fabricated and tested. Radiation tolerance has also been verified. In this paper the development of the charge sensitive front end and in particular its optimization for uniformity of charge threshold and time response will be presented.

Low-resistivity photon-transparent window attached to photo-sensitive silicon detector

DOEpatents

Holland, Stephen Edward

2000-02-15

The invention comprises a combination of a low resistivity, or electrically conducting, silicon layer that is transparent to long or short wavelength photons and is attached to the backside of a photon-sensitive layer of silicon, such as a silicon wafer or chip. The window is applied to photon sensitive silicon devices such as photodiodes, charge-coupled devices, active pixel sensors, low-energy x-ray sensors and other radiation detectors. The silicon window is applied to the back side of a photosensitive silicon wafer or chip so that photons can illuminate the device from the backside without interference from the circuit printed on the frontside. A voltage sufficient to fully deplete the high-resistivity photosensitive silicon volume of charge carriers is applied between the low-resistivity back window and the front, patterned, side of the device. This allows photon-induced charge created at the backside to reach the front side of the device and to be processed by any circuitry attached to the front side. Using the inventive combination, the photon sensitive silicon layer does not need to be thinned beyond standard fabrication methods in order to achieve full charge-depletion in the silicon volume. In one embodiment, the inventive backside window is applied to high resistivity silicon to allow backside illumination while maintaining charge isolation in CCD pixels.

Single event effects on the APV25 front-end chip

NASA Astrophysics Data System (ADS)

Friedl, M.; Bauer, T.; Pernicka, M.

2003-03-01

The Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider at CERN will include a Silicon Strip Tracker covering a sensitive area of 206 m2. About ten million channels will be read out by APV25 front-end chips, fabricated in the 0.25 μm deep submicron process. Although permanent damage is not expected within CMS radiation levels, transient Single Event Upsets are inevitable. Moreover, localized ionization can also produce fake signals in the analog circuitry. Eight APV25 chips were exposed to a high-intensity pion beam at the Paul Scherrer Institute (Villigen/CH) to study the radiation induced effects in detail. The results, which are compatible to similar measurements performed with heavy ions, are used to predict the chip error rate at CMS.

Integrated Arrays on Silicon at Terahertz Frequencies

NASA Technical Reports Server (NTRS)

Chattopadhayay, Goutam; Lee, Choonsup; Jung, Cecil; Lin, Robert; Peralta, Alessandro; Mehdi, Imran; Llombert, Nuria; Thomas, Bertrand

2011-01-01

In this paper we explore various receiver font-end and antenna architecture for use in integrated arrays at terahertz frequencies. Development of wafer-level integrated terahertz receiver front-end by using advanced semiconductor fabrication technologies and use of novel integrated antennas with silicon micromachining are reported. We report novel stacking of micromachined silicon wafers which allows for the 3-dimensional integration of various terahertz receiver components in extremely small packages which easily leads to the development of 2- dimensioanl multi-pixel receiver front-ends in the terahertz frequency range. We also report an integrated micro-lens antenna that goes with the silicon micro-machined front-end. The micro-lens antenna is fed by a waveguide that excites a silicon lens antenna through a leaky-wave or electromagnetic band gap (EBG) resonant cavity. We utilized advanced semiconductor nanofabrication techniques to design, fabricate, and demonstrate a super-compact, low-mass submillimeter-wave heterodyne frontend. When the micro-lens antenna is integrated with the receiver front-end we will be able to assemble integrated heterodyne array receivers for various applications such as multi-pixel high resolution spectrometer and imaging radar at terahertz frequencies.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shanks, Katherine S.; Philipp, Hugh T.; Weiss, Joel T.

Experiments at storage ring light sources as well as at next-generation light sources increasingly require detectors capable of high dynamic range operation, combining low-noise detection of single photons with large pixel well depth. XFEL sources in particular provide pulse intensities sufficiently high that a purely photon-counting approach is impractical. The High Dynamic Range Pixel Array Detector (HDR-PAD) project aims to provide a dynamic range extending from single-photon sensitivity to 10{sup 6} photons/pixel in a single XFEL pulse while maintaining the ability to tolerate a sustained flux of 10{sup 11} ph/s/pixel at a storage ring source. Achieving these goals involves themore » development of fast pixel front-end electronics as well as, in the XFEL case, leveraging the delayed charge collection due to plasma effects in the sensor. A first prototype of essential electronic components of the HDR-PAD readout ASIC, exploring different options for the pixel front-end, has been fabricated. Here, the HDR-PAD concept and preliminary design will be described.« less

An RFID tag system-on-chip with wireless ECG monitoring for intelligent healthcare systems.

PubMed

Wang, Cheng-Pin; Lee, Shuenn-Yuh; Lai, Wei-Chih

2013-01-01

This paper presents a low-power wireless ECG acquisition system-on-chip (SoC), including an RF front-end circuit, a power unit, an analog front-end circuit, and a digital circuitry. The proposed RF front-end circuit can provide the amplitude shift keying demodulation and distance to digital conversion to accurately receive the data from the reader. The received data will wake up the power unit to provide the required supply voltages of analog front-end (AFE) and digital circuitry. The AFE, including a pre-amplifier, an analog filter, a post-amplifier, and an analog-to-digital converter, is used for the ECG acquisition. Moreover, the EPC Class I Gen 2 UHF standard is employed in the digital circuitry for the handshaking of communication and the control of the system. The proposed SoC has been implemented in 0.18-µm standard CMOS process and the measured results reveal the communication is compatible to the RFID protocol. The average power consumption for the operating chip is 12 µW. Using a Sony PR44 battery to the supply power (605mAh@1.4V), the RFID tag SoC operates continuously for about 50,000 hours (>5 years), which is appropriate for wireless wearable ECG monitoring systems.

Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gaioni, L.; Braga, D.; Christian, D.

This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided

Single-Chip CMUT-on-CMOS Front-End System for Real-Time Volumetric IVUS and ICE Imaging

PubMed Central

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F. Levent

2014-01-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of CMUT arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-µm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-µm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single-chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex-vivo chicken heart sample. The measured axial and lateral point resolutions are 92 µm and 251 µm, respectively. We successfully acquired volumetric imaging data from the ex-vivo chicken heart with 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce real-time volumetric images with image quality and speed suitable for catheter based clinical applications. PMID:24474131

Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

PubMed

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

2014-02-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

A front end readout electronics ASIC chip for position sensitive solid state detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kravis, S.D.; Tuemer, T.O.; Visser, G.J.

1998-12-31

A mixed signal Application Specific Integrated Circuit (ASIC) chip for front end readout electronics of position sensitive solid state detectors has been manufactured. It is called RENA (Readout Electronics for Nuclear Applications). This chip can be used for both medical and industrial imaging of X-rays and gamma rays. The RENA chip is a monolithic integrated circuit and has 32 channels with low noise high input impedance charge sensitive amplifiers. It works in pulse counting mode with good energy resolution. It also has a self triggering output which is essential for nuclear applications when the incident radiation arrives at random. Different,more » externally selectable, operational modes that includes a sparse readout mode is available to increase data throughput. It also has externally selectable shaping (peaking) times.« less

STIC3 - Silicon Photomultiplier Timing Chip with picosecond resolution

NASA Astrophysics Data System (ADS)

Stankova, Vera; Shen, Wei; Briggl, Konrad; Chen, Huangshan; Fischer, Peter; Gil, Alejandro; Harion, Tobias; Kiworra, Volker; Munwes, Yonathan; Ritzert, Michael; Schultz-Coulon, Hans-Christian

2015-07-01

The diagnostic of pancreas and prostate cancer is a challenging task due to the background noise coming from the closer organs. The EndoToFPET-US project aims to combine the synergy between metabolic and anatomical (ultrasound) image in order to improve the precision in the tumor localization. The goal of the project is to develop a Positron Emission Tomography (PET) system that provides a time-of-flight resolution of 200 ps FWHM for improving the signal to noise ratio and further to improve the medical image quality. In order to achieve this purpose an ASIC has been designed for very high timing resolution in time-of-flight (ToF) applications. In this paper we present the ASIC performance and the first characterization measurements with the 64-channels prototype version (STiC3). Measurements are performed with LYSO scintillator crystal and a Multi Pixel Photon Counter (MPPC). Measurements with the chip show an analog-front-end stage jitter of 35 ps for the first photo-electron equivalent charge and reach 18 ps for the third photo-electron. Coincidence time resolution (CTR) of 240 ps FWHM is measured with 3.1×3.1×15 mm3 LYSO crystal and 50 μm pixel pitch MPPC. Further optimization including the Time-to-Digital Converter (TDC) non-linearity corrections and setup fine tuning are ongoing for achieving the desired CTR of 200 ps FWHM.

The use of low resistivity substrates for optimal noise reduction, ground referencing, and current conduction in mixed signal ASICs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zimmerman, T.

1997-12-01

This paper is distilled from a talk given at the 3rd International Meeting on Front End Electronics in Taos, N.M. on Nov. 7,1997. It is based on experience gained by designing and testing the SVX3 128 channel silicon strip detector readout chip. The SVX3 chip organization is shown in Fig. 1. The Front End section consists of an integrator and analog pipeline designed at Fermilab, and the Back End section is an ADC plus sparsification and readout logic designed at LBL. SVX3 is a deadtimeless readout chip, which means that the front end is acquiring low level analog signals whilemore » the back end is digitizing and reading out digital signals. It is thus a true mixed signal chip, and demands close attention to avoid disastrous coupling from the digital to the analog sections. SVX3 is designed in a bulk CMOS process (i.e., the circuits sit in a silicon substrate). In such a process, the substrate becomes a potential coupling path. This paper discusses the effect of the substrate resistivity on coupling, and also goes into a more general discussion of grounding and referencing in mixed signal designs and how low resistivity substrates can be used to advantage. Finally, an alternative power supply current conduction method for ASICs is presented as an additional advantage which can be obtained with low resistivity substrates. 1 ref., 13 figs., 1 tab.« less

Market trends in the projection display industry

NASA Astrophysics Data System (ADS)

Dash, Sweta

2000-04-01

The projection display industry represents a multibillion- dollar market that includes four distinct technologies. High-volume consumer products and high-value business products drive the market, with different technologies being used in different application markets. The consumer market is dominated by rear CRT technology, especially in the projection television segment. But rear LCD (liquid crystal display) and rear reflective (DLP, or Digital Light ProcessingTM) televisions are slowly emerging as future competitors to rear CRT projectors. Front CRT projectors are still popular in the high-end home theater market. Front LCD technology and front DLP technology dominate the business market. Traditional light valve technology was the only solution for applications requiring high light outputs, but new three-chip DLP projectors meet the higher light output requirements at a lower price. In the last few years the strongest growth has been in the business market for multimedia presentation applications. This growth was due to the continued increase in display pixel formats, the continued reduction in projector weight, and the improved price/performance ratio. The projection display market will grow at a significant rate during the next five years, driven by the growth in ultraportable (< 10 pound) projectors and the shift in the consumer market to digital and HDTV products.

Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

NASA Technical Reports Server (NTRS)

Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.;

The DIRC front-end electronics chain for BaBar

NASA Astrophysics Data System (ADS)

Bailly, P.; Chauveau, J.; Del Buono, L.; Genat, J. F.; Lebbolo, H.; Roos, L.; Zhang, B.; Beigbeder, C.; Bernier, R.; Breton, D.; Caceres, T.; Chase, R.; Ducorps, A.; Hrisoho, A.; Imbert, P.; Sen, S.; Tocut, V.; Truong, K.; Wormser, G.; Zomer, F.; Bonneaud, G.; Dohou, F.; Gastaldi, F.; Matricon, P.; Renard, C.; Thiebaux, C.; Vasileiadis, G.; Verderi, M.; Oxoby, G.; Va'Vra, J.; Warner, D.; Wilson, R. J.

1999-08-01

The detector of Internally Reflected Cherenkov light (DIRC) of the BaBar detector (SLAC Stanford, USA) measures better than 1 ns the arrival time of Cherenkov photoelectrons, detected in a 11 000 phototubes array and their amplitude spectra. It mainly comprises of 64-channel DIRC Front-End Boards (DFB) equipped with eight full-custom Analog chips performing zero-cross discrimination with 2 mV threshold and pulse shaping, four full-custom Digital TDC chips for timing measurements with 500 ps binning and a readout logic selecting hits in the trigger window, and DIRC Crate Controller cards (DCC) serializing the data collected from up to 16 DFBs onto a 1.2 Gb/s optical link. Extensive test of the pre-production chips have been performed as well as system tests.

Front-end electronics of the Belle II drift chamber

NASA Astrophysics Data System (ADS)

Shimazaki, Shoichi; Taniguchi, Takashi; Uchida, Tomohisa; Ikeno, Masahiro; Taniguchi, Nanae; Tanaka, Manobu M.

2014-01-01

This paper describes the performance of the Belle II central drift chamber (CDC) front-end electronics. The front-end electronics consists of a current sensitive preamplifier, a 1/t cancellation circuit, baseline restorers, a comparator for timing measurement and an analog buffer for the dE/dx measurement on a CDC readout card. The CDC readout card is located on the endplate of the CDC. Mass production will be completed after the performance of the chip is verified. The electrical performance and results of a neutron/gamma-ray irradiation test are reported here.

Absolute dose calibration of an X-ray system and dead time investigations of photon-counting techniques

NASA Astrophysics Data System (ADS)

Carpentieri, C.; Schwarz, C.; Ludwig, J.; Ashfaq, A.; Fiederle, M.

2002-07-01

High precision concerning the dose calibration of X-ray sources is required when counting and integrating methods are compared. The dose calibration for a dental X-ray tube was executed with special dose calibration equipment (dosimeter) as function of exposure time and rate. Results were compared with a benchmark spectrum and agree within ±1.5%. Dead time investigations with the Medipix1 photon-counting chip (PCC) have been performed by rate variations. Two different types of dead time, paralysable and non-paralysable will be discussed. The dead time depends on settings of the front-end electronics and is a function of signal height, which might lead to systematic defects of systems. Dead time losses in excess of 30% have been found for the PCC at 200 kHz absorbed photons per pixel.

Apparatus and method for harvesting woody plantations

DOEpatents

Eggen, David L.

1988-11-15

A tree harvester for harvesting felled trees includes a wheel mounted wood chipper which moves toward the butt ends of the tree stems to be processed. The harvester includes a plurality of rotating alignment discs in front of the chipper. These discs align the tree stems to be processed with the mouth of the chipper. A chipper infeed cylinder is rotatably mounted between the discs and the front end of the chipper, and lifts the tree stem butts up from the ground into alignment with the chipper inlet port. The chips discharge from the chipper and go into a chip hopper which moves with the tree harvester.

Apparatus and method for harvesting woody plantations

DOEpatents

Eggen, D.L.

1988-11-15

A tree harvester for harvesting felled trees includes a wheel mounted wood chipper which moves toward the butt ends of the tree stems to be processed. The harvester includes a plurality of rotating alignment discs in front of the chipper. These discs align the tree stems to be processed with the mouth of the chipper. A chipper infeed cylinder is rotatably mounted between the discs and the front end of the chipper, and lifts the tree stem butts up from the ground into alignment with the chipper inlet port. The chips discharge from the chipper and go into a chip hopper which moves with the tree harvester. 8 figs.

Back-end and interface implementation of the STS-XYTER2 prototype ASIC for the CBM experiment

NASA Astrophysics Data System (ADS)

Kasinski, K.; Szczygiel, R.; Zabolotny, W.

2016-11-01

Each front-end readout ASIC for the High-Energy Physics experiments requires robust and effective hit data streaming and control mechanism. A new STS-XYTER2 full-size prototype chip for the Silicon Tracking System and Muon Chamber detectors in the Compressed Baryonic Matter experiment at Facility for Antiproton and Ion Research (FAIR, Germany) is a 128-channel time and amplitude measuring solution for silicon microstrip and gas detectors. It operates at 250 kHit/s/channel hit rate, each hit producing 27 bits of information (5-bit amplitude, 14-bit timestamp, position and diagnostics data). The chip back-end implements fast front-end channel read-out, timestamp-wise hit sorting, and data streaming via a scalable interface implementing the dedicated protocol (STS-HCTSP) for chip control and hit transfer with data bandwidth from 9.7 MHit/s up to 47 MHit/s. It also includes multiple options for link diagnostics, failure detection, and throttling features. The back-end is designed to operate with the data acquisition architecture based on the CERN GBTx transceivers. This paper presents the details of the back-end and interface design and its implementation in the UMC 180 nm CMOS process.

Towards on-chip integration of brain imaging photodetectors using standard CMOS process.

PubMed

Kamrani, Ehsan; Lesage, Frederic; Sawan, Mohamad

2013-01-01

The main effects of on-chip integration on the performance and efficiency of silicon avalanche photodiode (SiAPD) and photodetector front-end is addressed in this paper based on the simulation and fabrication experiments. Two different silicon APDs are fabricated separately and also integrated with a transimpedance amplifier (TIA) front-end using standard CMOS technology. SiAPDs are designed in p+/n-well structure with guard rings realized in different shapes. The TIA front-end has been designed using distributed-gain concept combined with resistive-feedback and common-gate topology to reach low-noise and high gain-bandwidth product (GBW) characteristics. The integrated SiAPDs show higher signal-to-noise ratio (SNR), sensitivity and detection efficiency comparing to the separate SiAPDs. The integration does not show a significant effect on the gain and preserves the low power consumption. Using APDs with p-well guard-ring is preferred due to the higher observed efficiency after integration.

Front-end electronics and DAQ for the EURITRACK tagged neutron inspection system

NASA Astrophysics Data System (ADS)

Lunardon, M.; Bottosso, C.; Fabris, D.; Moretto, S.; Nebbia, G.; Pesente, S.; Viesti, G.; Bigongiari, A.; Colonna, A.; Tintori, C.; Valkovic, V.; Sudac, D.; Peerani, P.; Sequeira, V.; Salvato, M.

2007-08-01

The EURopean Illicit TRAfficing Countermeasures Kit (EURITRACK) Front-End and Data Acquisition System is a compact set of VME boards interfaced with a standard PC. The system is part of a cargo container inspection portal based on the tagged neutrons technique. The front-end processes all detector signals and checks coincidences between any of the 64 pixels of the alpha particle detector and any gamma-ray signals in 22 NaI(Tl) scintillators. The system is capable of handling the data flow at neutron flux up to the portal limiting value of 108 neutrons/second. Some typical applications are presented.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Demaria, N.

This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. Critical building blocks and analog very front end chains have been designed, tested before and after 5–800 Mrad. Small prototypes of 64×64 pixels with complex digital architectures have been produced, and point to address the main issues of dealing with extremely high pixel rates, while operating at very small in-time thresholds in the analog front end. Lastly, the collaborationmore » is now proceeding at full speed towards the design of a large scale prototype, called RD53A, in 65 nm CMOS technology.« less

Toward Realization of 2.4 GHz Balunless Narrowband Receiver Front-End for Short Range Wireless Applications.

PubMed

El-Desouki, Munir M; Qasim, Syed Manzoor; BenSaleh, Mohammed S; Deen, M Jamal

2015-05-07

The demand for radio frequency (RF) transceivers operating at 2.4 GHz band has attracted considerable research interest due to the advancement in short range wireless technologies. The performance of RF transceivers depends heavily on the transmitter and receiver front-ends. The receiver front-end is comprised of a low-noise amplifier (LNA) and a downconversion mixer. There are very few designs that focus on connecting the single-ended output LNA to a double-balanced mixer without the use of on-chip transformer, also known as a balun. The objective of designing such a receiver front-end is to achieve high integration and low power consumption. To meet these requirements, we present the design of fully-integrated 2.4 GHz receiver front-end, consisting of a narrow-band LNA and a double balanced mixer without using a balun. Here, the single-ended RF output signal of the LNA is translated into differential signal using an NMOS-PMOS (n-channel metal-oxide-semiconductor, p-channel metal-oxide-semiconductor) transistor differential pair instead of the conventional NMOS-NMOS transistor configuration, for the RF amplification stage of the double-balanced mixer. The proposed receiver circuit fabricated using TSMC 0.18 µm CMOS technology operates at 2.4 GHz and produces an output signal at 300 MHz. The fabricated receiver achieves a gain of 16.3 dB and consumes only 6.74 mW operating at 1.5 V, while utilizing 2.08 mm2 of chip area. Measurement results demonstrate the effectiveness and suitability of the proposed receiver for short-range wireless applications, such as in wireless sensor network (WSN).

Advanced RF Front End Technology

NASA Technical Reports Server (NTRS)

Herman, M. I.; Valas, S.; Katehi, L. P. B.

2001-01-01

The ability to achieve low-mass low-cost micro/nanospacecraft for Deep Space exploration requires extensive miniaturization of all subsystems. The front end of the Telecommunication subsystem is an area in which major mass (factor of 10) and volume (factor of 100) reduction can be achieved via the development of new silicon based micromachined technology and devices. Major components that make up the front end include single-pole and double-throw switches, diplexer, and solid state power amplifier. JPL's Center For Space Microsystems - System On A Chip (SOAC) Program has addressed the challenges of front end miniaturization (switches and diplexers). Our objectives were to develop the main components that comprise a communication front end and enable integration in a single module that we refer to as a 'cube'. In this paper we will provide the latest status of our Microelectromechanical System (MEMS) switches and surface micromachined filter development. Based on the significant progress achieved we can begin to provide guidelines of the proper system insertion for these emerging technologies. Additional information is contained in the original extended abstract.

Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays.

PubMed

Ciçek, Ihsan; Bozkurt, Ayhan; Karaman, Mustafa

2005-12-01

Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMUT element, we developed an electrical CMUT model with parameters derived through finite element analysis, and performed both the pre- and postlayout verification. An experimental chip consisting of 4 X 4 array of the designed circuit cells, each cell occupying a 200 X 200 microm2 area, was formed for the initial test studies and scheduled for fabrication in 0.8 microm, 50 V CMOS technology. The designed circuit is suitable for integration with CMUT arrays through flip-chip bonding and the CMUT-on-CMOS process.

AFEII Analog Front End Board Design Specifications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rubinov, Paul; /Fermilab

2005-04-01

This document describes the design of the 2nd iteration of the Analog Front End Board (AFEII), which has the function of receiving charge signals from the Central Fiber Tracker (CFT) and providing digital hit pattern and charge amplitude information from those charge signals. This second iteration is intended to address limitations of the current AFE (referred to as AFEI in this document). These limitations become increasingly deleterious to the performance of the Central Fiber Tracker as instantaneous luminosity increases. The limitations are inherent in the design of the key front end chips on the AFEI board (the SVXIIe and themore » SIFT) and the architecture of the board itself. The key limitations of the AFEI are: (1) SVX saturation; (2) Discriminator to analog readout cross talk; (3) Tick to tick pedestal variation; and (4) Channel to channel pedestal variation. The new version of the AFE board, AFEII, addresses these limitations by use of a new chip, the TriP-t and by architectural changes, while retaining the well understood and desirable features of the AFEI board.« less

FERMI: a digital Front End and Readout MIcrosystem for high resolution calorimetry

NASA Astrophysics Data System (ADS)

Alexanian, H.; Appelquist, G.; Bailly, P.; Benetta, R.; Berglund, S.; Bezamat, J.; Blouzon, F.; Bohm, C.; Breveglieri, L.; Brigati, S.; Cattaneo, P. W.; Dadda, L.; David, J.; Engström, M.; Genat, J. F.; Givoletti, M.; Goggi, V. G.; Gong, S.; Grieco, G. M.; Hansen, M.; Hentzell, H.; Holmberg, T.; Höglund, I.; Inkinen, S. J.; Kerek, A.; Landi, C.; Ledortz, O.; Lippi, M.; Lofstedt, B.; Lund-Jensen, B.; Maloberti, F.; Mutz, S.; Nayman, P.; Piuri, V.; Polesello, G.; Sami, M.; Savoy-Navarro, A.; Schwemling, P.; Stefanelli, R.; Sundblad, R.; Svensson, C.; Torelli, G.; Vanuxem, J. P.; Yamdagni, N.; Yuan, J.; Ödmark, A.; Fermi Collaboration

1995-02-01

We present a digital solution for the front-end electronics of high resolution calorimeters at future colliders. It is based on analogue signal compression, high speed {A}/{D} converters, a fully programmable pipeline and a digital signal processing (DSP) chain with local intelligence and system supervision. This digital solution is aimed at providing maximal front-end processing power by performing waveform analysis using DSP methods. For the system integration of the multichannel device a multi-chip, silicon-on-silicon multi-chip module (MCM) has been adopted. This solution allows a high level of integration of complex analogue and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of multichip integration provides a high degree of reliability and programmability at both the function and the system level, with the additional possibility of customising the microsystem to detector-specific requirements. For enhanced reliability in high radiation environments, fault tolerance strategies, i.e. redundancy, reconfigurability, majority voting and coding for error detection and correction, are integrated into the design.

Development of radiation tolerant monolithic active pixel sensors with fast column parallel read-out

NASA Astrophysics Data System (ADS)

Koziel, M.; Dorokhov, A.; Fontaine, J.-C.; De Masi, R.; Winter, M.

2010-12-01

Monolithic active pixel sensors (MAPS) [1] (Turchetta et al., 2001) are being developed at IPHC—Strasbourg to equip the EUDET telescope [2] (Haas, 2006) and vertex detectors for future high energy physics experiments, including the STAR upgrade at RHIC [3] (T.S. Collaboration, 2005) and the CBM experiment at FAIR/GSI [4] (Heuser, 2006). High granularity, low material budget and high read-out speed are systematically required for most applications, complemented, for some of them, with high radiation tolerance. A specific column-parallel architecture, implemented in the MIMOSA-22 sensor, was developed to achieve fast read-out MAPS. Previous studies of the front-end architecture integrated in this sensor, which includes in-pixel amplification, have shown that the fixed pattern noise increase consecutive to ionizing radiation can be controlled by means of a negative feedback [5] (Hu-Guo et al., 2008). However, an unexpected rise of the temporal noise was observed. A second version of this chip (MIMOSA-22bis) was produced in order to search for possible improvements of the radiation tolerance, regarding this type of noise. In this prototype, the feedback transistor was tuned in order to mitigate the sensitivity of the pixel to ionizing radiation. The performances of the pixels after irradiation were investigated for two types of feedback transistors: enclosed layout transistor (ELT) [6] (Snoeys et al., 2000) and "standard" transistor with either large or small transconductance. The noise performance of all test structures was studied in various conditions (expected in future experiments) regarding temperature, integration time and ionizing radiation dose. Test results are presented in this paper. Based on these observations, ideas for further improvement of the radiation tolerance of column parallel MAPS are derived.

Holographic pixel super-resolution in portable lensless on-chip microscopy using a fiber-optic array.

PubMed

Bishara, Waheb; Sikora, Uzair; Mudanyali, Onur; Su, Ting-Wei; Yaglidere, Oguzhan; Luckhart, Shirley; Ozcan, Aydogan

2011-04-07

We report a portable lensless on-chip microscope that can achieve <1 µm resolution over a wide field-of-view of ∼ 24 mm(2) without the use of any mechanical scanning. This compact on-chip microscope weighs ∼ 95 g and is based on partially coherent digital in-line holography. Multiple fiber-optic waveguides are butt-coupled to light emitting diodes, which are controlled by a low-cost micro-controller to sequentially illuminate the sample. The resulting lensfree holograms are then captured by a digital sensor-array and are rapidly processed using a pixel super-resolution algorithm to generate much higher resolution holographic images (both phase and amplitude) of the objects. This wide-field and high-resolution on-chip microscope, being compact and light-weight, would be important for global health problems such as diagnosis of infectious diseases in remote locations. Toward this end, we validate the performance of this field-portable microscope by imaging human malaria parasites (Plasmodium falciparum) in thin blood smears. Our results constitute the first-time that a lensfree on-chip microscope has successfully imaged malaria parasites.

Concept Design for a 1-Lead Wearable/Implantable ECG Front-End: Power Management

PubMed Central

George, Libin; Gargiulo, Gaetano Dario; Lehmann, Torsten; Hamilton, Tara Julia

2015-01-01

Power supply quality and stability are critical for wearable and implantable biomedical applications. For this reason we have designed a reconfigurable switched-capacitor DC-DC converter that, aside from having an extremely small footprint (with an active on-chip area of only 0.04 mm2), uses a novel output voltage control method based upon a combination of adaptive gain and discrete frequency scaling control schemes. This novel DC-DC converter achieves a measured output voltage range of 1.0 to 2.2 V with power delivery up to 7.5 mW with 75% efficiency. In this paper, we present the use of this converter as a power supply for a concept design of a wearable (15 mm × 15 mm) 1-lead ECG front-end sensor device that simultaneously harvests power and communicates with external receivers when exposed to a suitable RF field. Due to voltage range limitations of the fabrication process of the current prototype chip, we focus our analysis solely on the power supply of the ECG front-end whose design is also detailed in this paper. Measurement results show not just that the power supplied is regulated, clean and does not infringe upon the ECG bandwidth, but that there is negligible difference between signals acquired using standard linear power-supplies and when the power is regulated by our power management chip. PMID:26610497

MEDUSA-32: A low noise, low power silicon strip detector front-end electronics, for space applications

NASA Astrophysics Data System (ADS)

Cicuttin, Andres; Colavita, Alberto; Cerdeira, Alberto; Fratnik, Fabio; Vacchi, Andrea

1997-02-01

In this report we describe a mixed analog-digital integrated circuit (IC) designed as the front-end electronics for silicon strip-detectors for space applications. In space power consumption, compactness and robustness become critical constraints for a pre-amplifier design. The IC is a prototype with 32 complete channels, and it is intended for a large area particle tracker of a new generation of gamma ray telescopes. Each channel contains a charge sensitive amplifier, a pulse shaper, a discriminator and two digital buffers. The reference trip point of the discriminator is adjustable. This chip also has a custom PMOSFET transistor per channel, included in order to provide the high dynamic resistance needed to reverse-bias the strip diode. The digital part of the chip is used to store and serially shift out the state of the channels. There is also a storage buffer that allows the disabling of non-functioning channels if it is required by the data acquisition system. An input capacitance of 30 pF introduced at the input of the front-end produces less than 1000 electrons of RMS equivalent noise charge (ENC), for a total power dissipation of only 60 μW per channel. The chip was made using Orbit's 1.2 μm double poly, double metal n-well low noise CMOS process. The dimensions of the IC are 2400 μm × 8840 μm.

Concept Design for a 1-Lead Wearable/Implantable ECG Front-End: Power Management.

PubMed

George, Libin; Gargiulo, Gaetano Dario; Lehmann, Torsten; Hamilton, Tara Julia

2015-11-19

Power supply quality and stability are critical for wearable and implantable biomedical applications. For this reason we have designed a reconfigurable switched-capacitor DC-DC converter that, aside from having an extremely small footprint (with an active on-chip area of only 0.04 mm²), uses a novel output voltage control method based upon a combination of adaptive gain and discrete frequency scaling control schemes. This novel DC-DC converter achieves a measured output voltage range of 1.0 to 2.2 V with power delivery up to 7.5 mW with 75% efficiency. In this paper, we present the use of this converter as a power supply for a concept design of a wearable (15 mm × 15 mm) 1-lead ECG front-end sensor device that simultaneously harvests power and communicates with external receivers when exposed to a suitable RF field. Due to voltage range limitations of the fabrication process of the current prototype chip, we focus our analysis solely on the power supply of the ECG front-end whose design is also detailed in this paper. Measurement results show not just that the power supplied is regulated, clean and does not infringe upon the ECG bandwidth, but that there is negligible difference between signals acquired using standard linear power-supplies and when the power is regulated by our power management chip.

A Front-End Electronics Prototype Based on Gigabit Ethernet for the ATLAS Small-Strip Thin Gap Chamber

NASA Astrophysics Data System (ADS)

Hu, Kun; Lu, Houbing; Wang, Xu; Li, Feng; Wang, Xinxin; Geng, Tianru; Yang, Hang; Liu, Shengquan; Han, Liang; Jin, Ge

2017-06-01

A front-end electronics prototype for the ATLAS small-strip Thin Gap Chamber (sTGC) based on gigabit Ethernet has been developed. The prototype is designed to read out signals of pads, wires, and strips of the sTGC detector. The prototype includes two VMM2 chips developed to read out the signals of the sTGC, a Xilinx Kintex-7 field-programmable gate array (FPGA) used for the VMM2 configuration and the events storage, and a gigabit Ethernet transceiver PHY chip for interfacing with a computer. The VMM2 chip is designed for the readout of the Micromegas detector and sTGC detector, which is composed of 64 linear front-end channels. Each channel integrates a charge-sensitive amplifier, a shaper, several analog-to-digital converters, and other digital functions. For a bunch-crossing interval of 25 ns, events are continuously read out by the FPGA and forwarded to the computer. The interface between the computer and the prototype has been measured to reach an error-free rate of 900 Mb/s, therefore making a very effective use of the available bandwidth. Additionally, the computer can control several prototypes of this kind simultaneously via the Ethernet interface. At present, the prototype will be used for the sTGC performance test. The features of the prototype are described in detail.

Single event effect hardness for the front-end ASICs in the DAMPE satellite BGO calorimeter

NASA Astrophysics Data System (ADS)

Gao, Shan-Shan; Jiang, Di; Feng, Chang-Qing; Xi, Kai; Liu, Shu-Bin; An, Qi

2016-01-01

The Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray studies with a primary scientific goal of indirect detection of dark matter particles. As a crucial sub-detector, the BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of more than 3 years makes single event effects (SEEs) become threats to reliability. In order to evaluate SEE sensitivities of these chips and verify the effectiveness of mitigation methods, a series of laser-induced and heavy ion-induced SEE tests were performed. Benefiting from the single event latch-up (SEL) protection circuit for power supply, the triple module redundancy (TMR) technology for the configuration registers and the optimized sequential design for the data acquisition process, 52 VA160 chips and 32 VATA160 chips have been applied in the flight model of the BGO calorimeter with radiation hardness assurance. Supported by Strategic Priority Research Program on Space Science of the Chinese Academy of Sciences (XDA04040202-4) and Fundamental Research Funds for the Central Universities (WK2030040048)

Characterisation of a novel reverse-biased PPD CMOS image sensor

NASA Astrophysics Data System (ADS)

Stefanov, K. D.; Clarke, A. S.; Ivory, J.; Holland, A. D.

2017-11-01

A new pinned photodiode (PPD) CMOS image sensor (CIS) has been developed and characterised. The sensor can be fully depleted by means of reverse bias applied to the substrate, and the principle of operation is applicable to very thick sensitive volumes. Additional n-type implants under the pixel p-wells, called Deep Depletion Extension (DDE), have been added in order to eliminate the large parasitic substrate current that would otherwise be present in a normal device. The first prototype has been manufactured on a 18 μm thick, 1000 Ω .cm epitaxial silicon wafers using 180 nm PPD image sensor process at TowerJazz Semiconductor. The chip contains arrays of 10 μm and 5.4 μm pixels, with variations of the shape, size and the depth of the DDE implant. Back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v, and characterised together with the front-side illuminated (FSI) variants. The presented results show that the devices could be reverse-biased without parasitic leakage currents, in good agreement with simulations. The new 10 μm pixels in both BSI and FSI variants exhibit nearly identical photo response to the reference non-modified pixels, as characterised with the photon transfer curve. Different techniques were used to measure the depletion depth in FSI and BSI chips, and the results are consistent with the expected full depletion.

A front-end read out chip for the OPERA scintillator tracker

NASA Astrophysics Data System (ADS)

Lucotte, A.; Bondil, S.; Borer, K.; Campagne, J. E.; Cazes, A.; Hess, M.; de La Taille, C.; Martin-Chassard, G.; Raux, L.; Repellin, J. P.

2004-04-01

Multi-anode photomultipliers H7546 are used to readout signal from the OPERA Scintillator Tracker (CERN/SPSC 2000-028, SPSC/P318, LNGSP 25/2000; CERN/SPSC 2001-025, SPSC/M668, LNGS-EXP30/2001). A 32-channel front-end Read Out Chip prototype accommodating the H7546 has been designed at LAL. This device features a low-noise, variable gain preamplifier to correct for multi-anode non-uniformity, an auto-trigger capability 100% efficient at a 0.3 photo-electron, and a charge measurement extending over a large dynamic range [0-100] photo-electrons. In this article we describe the ASIC architecture that is being implemented for the Target Tracker in OPERA, with a special emphasis put on the designs and the measured performance.

Advancements in DEPMOSFET device developments for XEUS

NASA Astrophysics Data System (ADS)

Treis, J.; Bombelli, L.; Eckart, R.; Fiorini, C.; Fischer, P.; Hälker, O.; Herrmann, S.; Lechner, P.; Lutz, G.; Peric, I.; Porro, M.; Richter, R. H.; Schaller, G.; Schopper, F.; Soltau, H.; Strüder, L.; Wölfel, S.

2006-06-01

DEPMOSFET based Active Pixel Sensor (APS) matrices are a new detector concept for X-ray imaging spectroscopy missions. They can cope with the challenging requirements of the XEUS Wide Field Imager and combine excellent energy resolution, high speed readout and low power consumption with the attractive feature of random accessibility of pixels. From the evaluation of first prototypes, new concepts have been developed to overcome the minor drawbacks and problems encountered for the older devices. The new devices will have a pixel size of 75 μm × 75 μm. Besides 64 × 64 pixel arrays, prototypes with a sizes of 256 × 256 pixels and 128 × 512 pixels and an active area of about 3.6 cm2 will be produced, a milestone on the way towards the fully grown XEUS WFI device. The production of these improved devices is currently on the way. At the same time, the development of the next generation of front-end electronics has been started, which will permit to operate the sensor devices with the readout speed required by XEUS. Here, a summary of the DEPFET capabilities, the concept of the sensors of the next generation and the new front-end electronics will be given. Additionally, prospects of new device developments using the DEPFET as a sensitive element are shown, e.g. so-called RNDR-pixels, which feature repetitive non-destructive readout to lower the readout noise below the 1 e - ENC limit.

Status and Plan for The Upgrade of The CMS Pixel Detector

NASA Astrophysics Data System (ADS)

Lu, Rong-Shyang; CMS Collaboration

2016-04-01

The silicon pixel detector is the innermost component of the CMS tracking system and plays a crucial role in the all-silicon CMS tracker. While the current pixel tracker is designed for and performing well at an instantaneous luminosity of up to 1 ×1034cm-2s-1, it can no longer be operated efficiently at significantly higher values. Based on the strong performance of the LHC accelerator, it is anticipated that peak luminosities of two times the design luminosity are likely to be reached before 2018 and perhaps significantly exceeded in the running period until 2022, referred to as LHC Run 3. Therefore, an upgraded pixel detector, referred to as the phase 1 upgrade, is planned for the year-end technical stop in 2016. With a new pixel readout chip (ROC), an additional fourth layer, two additional endcap disks, and a significantly reduced material budget the upgraded pixel detector will be able to sustain the efficiency of the pixel tracker at the increased requirements imposed by high luminosities and pile-up. The main new features of the upgraded pixel detector will be an ultra-light mechanical design, a digital readout chip with higher rate capability and a new cooling system. These and other design improvements, along with results of Monte Carlo simulation studies for the expected performance of the new pixel detector, will be discussed and compared to those of the current CMS detector.

Technology and design of an active-matrix OLED on crystalline silicon direct-view display for a wristwatch computer

NASA Astrophysics Data System (ADS)

Sanford, James L.; Schlig, Eugene S.; Prache, Olivier; Dove, Derek B.; Ali, Tariq A.; Howard, Webster E.

2002-02-01

The IBM Research Division and eMagin Corp. jointly have developed a low-power VGA direct view active matrix OLED display, fabricated on a crystalline silicon CMOS chip. The display is incorporated in IBM prototype wristwatch computers running the Linus operating system. IBM designed the silicon chip and eMagin developed the organic stack and performed the back-end-of line processing and packaging. Each pixel is driven by a constant current source controlled by a CMOS RAM cell, and the display receives its data from the processor memory bus. This paper describes the OLED technology and packaging, and outlines the design of the pixel and display electronics and the processor interface. Experimental results are presented.

Characterization of Kilopixel TES detector arrays for PIPER

NASA Astrophysics Data System (ADS)

Datta, Rahul; Ade, Peter; Benford, Dominic; Bennett, Charles; Chuss, David; Costen, Nicholas; Coughlin, Kevin; Dotson, Jessie; Eimer, Joseph; Fixsen, Dale; Gandilo, Natalie; Halpern, Mark; Essinger-Hileman, Thomas; Hilton, Gene; Hinshaw, Gary; Irwin, Kent; Jhabvala, Christine; Kimball, Mark; Kogut, Al; Lazear, Justin; Lowe, Luke; Manos, George; McMahon, Jeff; Miller, Timothy; Mirel, Paul; Moseley, Samuel Harvey; Pawlyk, Samuel; Rodriguez, Samelys; Sharp, Elmer; Shirron, Peter; Staguhn, Johannes G.; Sullivan, Dan; Switzer, Eric; Taraschi, Peter; Tucker, Carole; Walts, Alexander; Wollack, Edward

2018-01-01

The Primordial Inflation Polarization ExploreR (PIPER) is a balloon-borne instrument optimized to measure the polarization of the Cosmic Microwave Background (CMB) at large angular scales. It will map 85% of the sky in four frequency bands centered at 200, 270, 350, and 600 GHz to characterize dust foregrounds and constrain the tensor-to-scalar ratio, r. The sky is imaged on to 32x40 pixel arrays of time-domain multiplexed Transition-Edge Sensor (TES) bolometers operating at a bath temperature of 100 mK to achieve background-limited sensitivity. Each kilopixel array is indium-bump-bonded to a 2D superconducting quantum interference device (SQUID) time-domain multiplexer (MUX) chip and read out by warm electronics. Each pixel measures total incident power over a frequency band defined by bandpass filters in front of the array, while polarization sensitivity is provided by the upstream Variable-delay Polarization Modulators (VPMs) and analyzer grids. We present measurements of the detector parameters from the laboratory characterization of the first kilopixel science array for PIPER including transition temperature, saturation power, thermal conductivity, time constant, and noise performance. We also describe the testing of the 2D MUX chips, optimization of the integrated readout parameters, and the overall pixel yield of the array. The first PIPER science flight is planned for June 2018 from Palestine, Texas.

Novel x-ray silicon detector for 2D imaging and high-resolution spectroscopy

NASA Astrophysics Data System (ADS)

Castoldi, Andrea; Gatti, Emilio; Guazzoni, Chiara; Longoni, Antonio; Rehak, Pavel; Strueder, Lothar

1999-10-01

A novel x-ray silicon detector for 2D imaging has been recently proposed. The detector, called Controlled-Drift Detector, is operated in integrate-readout mode. Its basic feature is the fast transport of the integrated charge to the output electrode by means of a uniform drift field. The drift time of the charge packet identifies the pixel of incidence. A new architecture to implement the Controlled- Drift Detector concept will be presented. The potential wells for the integration of the signal charge are obtained by means of a suitable pattern of deep n-implants and deep p-implants. During the readout mode the signal electrons are transferred in the drift channel that flanks each column of potential wells where they drift towards the collecting electrode at constant velocity. The first experimental measurements demonstrate the successful integration, transfer and drift of the signal electrons. The low output capacitance of the readout electrode together with the on- chip front-end electronics allows high resolution spectroscopy of the detected photons.

ePix100 camera: Use and applications at LCLS

DOE Office of Scientific and Technical Information (OSTI.GOV)

Carini, G. A., E-mail: carini@slac.stanford.edu; Alonso-Mori, R.; Blaj, G.

2016-07-27

The ePix100 x-ray camera is a new system designed and built at SLAC for experiments at the Linac Coherent Light Source (LCLS). The camera is the first member of a family of detectors built around a single hardware and software platform, supporting a variety of front-end chips. With a readout speed of 120 Hz, matching the LCLS repetition rate, a noise lower than 80 e-rms and pixels of 50 µm × 50 µm, this camera offers a viable alternative to fast readout, direct conversion, scientific CCDs in imaging mode. The detector, designed for applications such as X-ray Photon Correlation Spectroscopymore » (XPCS) and wavelength dispersive X-ray Emission Spectroscopy (XES) in the energy range from 2 to 10 keV and above, comprises up to 0.5 Mpixels in a very compact form factor. In this paper, we report the performance of the camera during its first use at LCLS.« less

Terahertz Array Receivers with Integrated Antennas

NASA Technical Reports Server (NTRS)

Chattopadhyay, Goutam; Llombart, Nuria; Lee, Choonsup; Jung, Cecile; Lin, Robert; Cooper, Ken B.; Reck, Theodore; Siles, Jose; Schlecht, Erich; Peralta, Alessandro;

ALPIDE, the Monolithic Active Pixel Sensor for the ALICE ITS upgrade

NASA Astrophysics Data System (ADS)

Mager, M.; ALICE Collaboration

2016-07-01

A new 10 m2 inner tracking system based on seven concentric layers of Monolithic Active Pixel Sensors will be installed in the ALICE experiment during the second long shutdown of LHC in 2019-2020. The monolithic pixel sensors will be fabricated in the 180 nm CMOS Imaging Sensor process of TowerJazz. The ALPIDE design takes full advantage of a particular process feature, the deep p-well, which allows for full CMOS circuitry within the pixel matrix, while at the same time retaining the full charge collection efficiency. Together with the small feature size and the availability of six metal layers, this allowed a continuously active low-power front-end to be placed into each pixel and an in-matrix sparsification circuit to be used that sends only the addresses of hit pixels to the periphery. This approach led to a power consumption of less than 40 mWcm-2, a spatial resolution of around 5 μm, a peaking time of around 2 μs, while being radiation hard to some 1013 1 MeVneq /cm2, fulfilling or exceeding the ALICE requirements. Over the last years of R & D, several prototype circuits have been used to verify radiation hardness, and to optimize pixel geometry and in-pixel front-end circuitry. The positive results led to a submission of full-scale (3 cm×1.5 cm) sensor prototypes in 2014. They are being characterized in a comprehensive campaign that also involves several irradiation and beam tests. A summary of the results obtained and prospects towards the final sensor to instrument the ALICE Inner Tracking System are given.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lecomte, Roger; Arpin, Louis; Beaudoin, Jean-Franç

Purpose: LabPET II is a new generation APD-based PET scanner designed to achieve sub-mm spatial resolution using truly pixelated detectors and highly integrated parallel front-end processing electronics. Methods: The basic element uses a 4×8 array of 1.12×1.12 mm{sup 2} Lu{sub 1.9}Y{sub 0.1}SiO{sub 5}:Ce (LYSO) scintillator pixels with one-to-one coupling to a 4×8 pixelated monolithic APD array mounted on a ceramic carrier. Four detector arrays are mounted on a daughter board carrying two flip-chip, 64-channel, mixed-signal, application-specific integrated circuits (ASIC) on the backside interfacing to two detector arrays each. Fully parallel signal processing was implemented in silico by encoding time andmore » energy information using a dual-threshold Time-over-Threshold (ToT) scheme. The self-contained 128-channel detector module was designed as a generic component for ultra-high resolution PET imaging of small to medium-size animals. Results: Energy and timing performance were optimized by carefully setting ToT thresholds to minimize the noise/slope ratio. ToT spectra clearly show resolved 511 keV photopeak and Compton edge with ToT resolution well below 10%. After correction for nonlinear ToT response, energy resolution is typically 24±2% FWHM. Coincidence time resolution between opposing 128-channel modules is below 4 ns FWHM. Initial imaging results demonstrate that 0.8 mm hot spots of a Derenzo phantom can be resolved. Conclusion: A new generation PET scanner featuring truly pixelated detectors was developed and shown to achieve a spatial resolution approaching the physical limit of PET. Future plans are to integrate a small-bore dedicated mouse version of the scanner within a PET/CT platform.« less

Noise propagation issues in Belle II pixel detector power cable

NASA Astrophysics Data System (ADS)

Iglesias, M.; Arteche, F.; Echeverria, I.; Pradas, A.; Rivetta, C.; Moser, H.-G.; Kiesling, C.; Rummel, S.; Arcega, F. J.

2018-04-01

The vertex detector used in the upgrade of High-Energy physics experiment Belle II includes DEPFET pixel detector (PXD) technology. In this complex topology the power supply units and the front-end electronics are connected through a PXD power cable bundle which may propagate the output noise from the power supplies to the vertex area. This paper presents a study of the propagation of noise caused by power converters in the PXD cable bundle based on Multi-conductor Transmission Line (MTL) theory. The work exposes the effect of the complex cable topology and shield connections on the noise propagation, which has an impact on the requirements of the power supplies. This analysis is part of the electromagnetic compatibility based design focused on functional safety to define the shield connections and power supply specifications required to ensure the successful integration of the detector and, specifically, to achieve the designed performance of the front-end electronics.

Modeling and analysis of hybrid pixel detector deficiencies for scientific applications

NASA Astrophysics Data System (ADS)

Fahim, Farah; Deptuch, Grzegorz W.; Hoff, James R.; Mohseni, Hooman

2015-08-01

Semiconductor hybrid pixel detectors often consist of a pixellated sensor layer bump bonded to a matching pixelated readout integrated circuit (ROIC). The sensor can range from high resistivity Si to III-V materials, whereas a Si CMOS process is typically used to manufacture the ROIC. Independent, device physics and electronic design automation (EDA) tools are used to determine sensor characteristics and verify functional performance of ROICs respectively with significantly different solvers. Some physics solvers provide the capability of transferring data to the EDA tool. However, single pixel transient simulations are either not feasible due to convergence difficulties or are prohibitively long. A simplified sensor model, which includes a current pulse in parallel with detector equivalent capacitor, is often used; even then, spice type top-level (entire array) simulations range from days to weeks. In order to analyze detector deficiencies for a particular scientific application, accurately defined transient behavioral models of all the functional blocks are required. Furthermore, various simulations, such as transient, noise, Monte Carlo, inter-pixel effects, etc. of the entire array need to be performed within a reasonable time frame without trading off accuracy. The sensor and the analog front-end can be modeling using a real number modeling language, as complex mathematical functions or detailed data can be saved to text files, for further top-level digital simulations. Parasitically aware digital timing is extracted in a standard delay format (sdf) from the pixel digital back-end layout as well as the periphery of the ROIC. For any given input, detector level worst-case and best-case simulations are performed using a Verilog simulation environment to determine the output. Each top-level transient simulation takes no more than 10-15 minutes. The impact of changing key parameters such as sensor Poissonian shot noise, analog front-end bandwidth, jitter due to clock distribution etc. can be accurately analyzed to determine ROIC architectural viability and bottlenecks. Hence the impact of the detector parameters on the scientific application can be studied.

A Pixel Readout Chip in 40 nm CMOS Process for High Count Rate Imaging Systems with Minimization of Charge Sharing Effects

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maj, Piotr; Grybos, P.; Szczgiel, R.

2013-11-07

We present a prototype chip in 40 nm CMOS technology for readout of hybrid pixel detector. The prototype chip has a matrix of 18x24 pixels with a pixel pitch of 100 μm. It can operate both in single photon counting (SPC) mode and in C8P1 mode. In SPC the measured ENC is 84 e ₋rms (for the peaking time of 48 ns), while the effective offset spread is below 2 mV rms. In the C8P1 mode the chip reconstructs full charge deposited in the detector, even in the case of charge sharing, and it identifies a pixel with the largestmore » charge deposition. The chip architecture and preliminary measurements are reported.« less

SALT, a dedicated readout chip for high precision tracking silicon strip detectors at the LHCb Upgrade

NASA Astrophysics Data System (ADS)

Bugiel, Sz.; Dasgupta, R.; Firlej, M.; Fiutowski, T.; Idzik, M.; Kuczynska, M.; Moron, J.; Swientek, K.; Szumlak, T.

2016-02-01

The Upstream Tracker (UT) silicon strip detector, one of the central parts of the tracker system of the modernised LHCb experiment, will use a new 128-channel readout ASIC called SALT. It will extract and digitise analogue signals from the UT sensors, perform digital signal processing and transmit a serial output data. The SALT is being designed in CMOS 130 nm process and uses a novel architecture comprising of analog front-end and fast (40 MSps) ultra-low power (<0.5 mW) 6-bit ADC in each channel. The prototype ASICs of important functional blocks, like analogue front-end, 6-bit SAR ADC, PLL, and DLL, were designed, fabricated and tested. A prototype of an 8-channel version of the SALT chip, comprising all important functionalities was also designed and fabricated. The architecture and design of the SALT, together with the selected preliminary tests results, are presented.

A back-illuminated megapixel CMOS image sensor

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

2005-01-01

In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

Macro Pixel ASIC (MPA): the readout ASIC for the pixel-strip (PS) module of the CMS outer tracker at HL-LHC

NASA Astrophysics Data System (ADS)

Ceresa, D.; Marchioro, A.; Kloukinas, K.; Kaplon, J.; Bialas, W.; Re, V.; Traversi, G.; Gaioni, L.; Ratti, L.

2014-11-01

The CMS tracker at HL-LHC is required to provide prompt information on particles with high transverse momentum to the central Level 1 trigger. For this purpose, the innermost part of the outer tracker is based on a combination of a pixelated sensor with a short strip sensor, the so-called Pixel-Strip module (PS). The readout of these sensors is carried out by distinct ASICs, the Strip Sensor ASIC (SSA), for the strip layer, and the Macro Pixel ASIC (MPA) for the pixel layer. The processing of the data directly on the front-end module represents a design challenge due to the large data volume (30720 pixels and 1920 strips per module) and the limited power budget. This is the reason why several studies have been carried out to find the best compromise between ASICs performance and power consumption. This paper describes the current status of the MPA ASIC development where the logic for generating prompt information on particles with high transverse momentum is implemented. An overview of the readout method is presented with particular attention on the cluster reduction, position encoding and momentum discrimination logic. Concerning the architectural studies, a software test bench capable of reading physics Monte-Carlo generated events has been developed and used to validate the MPA design and to evaluate the MPA performance. The MPA-Light is scheduled to be submitted for fabrication this year and will include the full analog functions and a part of the digital logic of the final version in order to qualify the chosen VLSI technology for the analog front-end, the module assembly and the low voltage digital supply.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Becker, Julian; Tate, Mark W.; Shanks, Katherine S.

Pixel Array Detectors (PADs) consist of an x-ray sensor layer bonded pixel-by-pixel to an underlying readout chip. This approach allows both the sensor and the custom pixel electronics to be tailored independently to best match the x-ray imaging requirements. Here we describe the hybridization of CdTe sensors to two different charge-integrating readout chips, the Keck PAD and the Mixed-Mode PAD (MM-PAD), both developed previously in our laboratory. The charge-integrating architecture of each of these PADs extends the instantaneous counting rate by many orders of magnitude beyond that obtainable with photon counting architectures. The Keck PAD chip consists of rapid, 8-frame,more » in-pixel storage elements with framing periods <150 ns. The second detector, the MM-PAD, has an extended dynamic range by utilizing an in-pixel overflow counter coupled with charge removal circuitry activated at each overflow. This allows the recording of signals from the single-photon level to tens of millions of x-rays/pixel/frame while framing at 1 kHz. Both detector chips consist of a 128×128 pixel array with (150 µm){sup 2} pixels.« less

Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

NASA Astrophysics Data System (ADS)

Gao, W.; Liu, H.; Gan, B.; Hu, Y.

2014-05-01

In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e- to 180,000e-, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e- at zero farad plus 5.4 e- per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

Low-power analog integrated circuits for wireless ECG acquisition systems.

PubMed

Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

2012-09-01

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

Design of an Intelligent Front-End Signal Conditioning Circuit for IR Sensors

NASA Astrophysics Data System (ADS)

de Arcas, G.; Ruiz, M.; Lopez, J. M.; Gutierrez, R.; Villamayor, V.; Gomez, L.; Montojo, Mª. T.

2008-02-01

This paper presents the design of an intelligent front-end signal conditioning system for IR sensors. The system has been developed as an interface between a PbSe IR sensor matrix and a TMS320C67x digital signal processor. The system architecture ensures its scalability so it can be used for sensors with different matrix sizes. It includes an integrator based signal conditioning circuit, a data acquisition converter block, and a FPGA based advanced control block that permits including high level image preprocessing routines such as faulty pixel detection and sensor calibration in the signal conditioning front-end. During the design phase virtual instrumentation technologies proved to be a very valuable tool for prototyping when choosing the best A/D converter type for the application. Development time was significantly reduced due to the use of this technology.

The Gigatracker: An ultra-fast and low-mass silicon pixel detector for the NA62 experiment

NASA Astrophysics Data System (ADS)

Fiorini, M.; Carassiti, V.; Ceccucci, A.; Cortina, E.; Cotta Ramusino, A.; Dellacasa, G.; Garbolino, S.; Jarron, P.; Kaplon, J.; Kluge, A.; Mapelli, A.; Marchetto, F.; Martin, E.; Martoiu, S.; Mazza, G.; Morel, M.; Noy, M.; Nuessle, G.; Petrucci, F.; Riedler, P.; Aglieri Rinella, G.; Rivetti, A.; Tiuraniemi, S.

2011-02-01

The Gigatracker is a hybrid silicon pixel detector developed to track the highly intense NA62 hadron beam with a time resolution of 150 ps (rms). The beam spectrometer of the experiment is composed of three Gigatracker stations installed in vacuum in order to precisely measure momentum, time and direction of every traversing particle. Precise tracking demands a very low mass of the detector assembly ( <0.5% X0 per station) in order to limit multiple scattering and beam hadronic interactions. The high rate and especially the high timing precision requirements are very demanding: two R&D options are ongoing and the corresponding prototype read-out chips have been recently designed and produced in 0.13 μm CMOS technology. One solution makes use of a constant fraction discriminator and on-pixel analogue-based time-to-digital-converter (TDC); the other comprises a delay-locked loop based TDC placed at the end of each pixel column and a time-over-threshold discriminator with time-walk correction technique. The current status of the R&D program is overviewed and results from the prototype read-out chips test are presented.

A multichannel compact readout system for single photon detection: Design and performances

NASA Astrophysics Data System (ADS)

Argentieri, A. G.; Cisbani, E.; Colilli, S.; Cusanno, F.; De Leo, R.; Fratoni, R.; Garibaldi, F.; Giuliani, F.; Gricia, M.; Lucentini, M.; Marra, M.; Musico, Paolo; Santavenere, F.; Torrioli, S.

2010-05-01

Optimal exploitation of Multi Anode PhotoMultiplier Tubes (MAPMT) as imaging devices requires the acquisition of a large number of independent channels; despite the rather wide demand, on-the-shelf electronics for this purpose does not exist. A compact independent channel readout system for an array of MAPMTs has been developed and tested [1,2]. The system can handle up to 4096 independent channels, covering an area of about 20×20 cm2 with pixel size of 3×3 mm2, using Hamamatsu H-9500 devices. The front-end is based on a 64 channels VLSI custom chip called MAROC, developed by IN2P3 Orsay (France) group, controlled by means of a Field Programmable Gate Array (FPGA) which implements configuration, triggering and data conversion controls. Up to 64 front-end cards can be housed in four backplanes and a central unit collects data from all of them, communicating with a control Personal Computer (PC) using an high speed USB 2.0 connection. A complete system has been built and tested. Eight Flat MAPMTs (256 anodes Hamamatsu H-9500) have been arranged on a boundary of a 3×3 matrix for a grand total of 2048 channels. This detector has been used to verify the performances of a focusing aerogel RICH prototype using an electron beam at the Frascati (Rome) INFN National Laboratory Beam Test Facility (BTF) during the last week of January 2009. Data analysis is ongoing: the first results are encouraging, showing that the Cherenkov rings are well identified by this system.

The Belle II Silicon Vertex Detector

NASA Astrophysics Data System (ADS)

Friedl, M.; Ackermann, K.; Aihara, H.; Aziz, T.; Bergauer, T.; Bozek, A.; Campbell, A.; Dingfelder, J.; Drasal, Z.; Frankenberger, A.; Gadow, K.; Gfall, I.; Haba, J.; Hara, K.; Hara, T.; Higuchi, T.; Himori, S.; Irmler, C.; Ishikawa, A.; Joo, C.; Kah, D. H.; Kang, K. H.; Kato, E.; Kiesling, C.; Kodys, P.; Kohriki, T.; Koike, S.; Kvasnicka, P.; Marinas, C.; Mayekar, S. N.; Mibe, T.; Mohanty, G. B.; Moll, A.; Negishi, K.; Nakayama, H.; Natkaniec, Z.; Niebuhr, C.; Onuki, Y.; Ostrowicz, W.; Park, H.; Rao, K. K.; Ritter, M.; Rozanska, M.; Saito, T.; Sakai, K.; Sato, N.; Schmid, S.; Schnell, M.; Shimizu, N.; Steininger, H.; Tanaka, S.; Tanida, K.; Taylor, G.; Tsuboyama, T.; Ueno, K.; Uozumi, S.; Ushiroda, Y.; Valentan, M.; Yamamoto, H.

2013-12-01

The KEKB machine and the Belle experiment in Tsukuba (Japan) are now undergoing an upgrade, leading to an ultimate luminosity of 8×1035 cm-2 s-1 in order to measure rare decays in the B system with high statistics. The previous vertex detector cannot cope with this 40-fold increase of luminosity and thus needs to be replaced. Belle II will be equipped with a two-layer Pixel Detector surrounding the beam pipe, and four layers of double-sided silicon strip sensors at higher radii than the old detector. The Silicon Vertex Detector (SVD) will have a total sensitive area of 1.13 m2 and 223,744 channels-twice as many as its predecessor. All silicon sensors will be made from 150 mm wafers in order to maximize their size and thus to reduce the relative contribution of the support structure. The forward part has slanted sensors of trapezoidal shape to improve the measurement precision and to minimize the amount of material as seen by particles from the vertex. Fast-shaping front-end amplifiers will be used in conjunction with an online hit time reconstruction algorithm in order to reduce the occupancy to the level of a few percent at most. A novel “Origami” chip-on-sensor scheme is used to minimize both the distance between strips and amplifier (thus reducing the electronic noise) as well as the overall material budget. This report gives an overview on the status of the Belle II SVD and its components, including sensors, front-end detector ladders, mechanics, cooling and the readout electronics.

JUNGFRAU 0.2: prototype characterization of a gain-switching, high dynamic range imaging system for photon science at SwissFEL and synchrotrons

NASA Astrophysics Data System (ADS)

Jungmann-Smith, J. H.; Bergamaschi, A.; Cartier, S.; Dinapoli, R.; Greiffenberg, D.; Johnson, I.; Maliakal, D.; Mezza, D.; Mozzanica, A.; Ruder, Ch; Schaedler, L.; Schmitt, B.; Shi, X.; Tinti, G.

2014-12-01

JUNGFRAU (adJUstiNg Gain detector FoR the Aramis User station) is a two-dimensional pixel detector for photon science applications at free electron lasers and synchrotron light sources. It is developed for the SwissFEL currently under construction at the Paul Scherrer Institute, Switzerland. Characteristics of this application-specific integrating circuit readout chip include single photon sensitivity and low noise over a dynamic range of over four orders of magnitude of photon input signal. These characteristics are achieved by a three-fold gain-switching preamplifier in each pixel, which automatically adjusts its gain to the amount of charge deposited on the pixel. The final JUNGFRAU chip comprises 256 × 256 pixels of 75 × 75 μm2 each. Arrays of 2 × 4 chips are bump-bonded to monolithic detector modules of about 4 × 8 cm2. Multi-module systems up to 16 Mpixels are planned for the end stations at SwissFEL. A readout rate in excess of 2 kHz is anticipated, which serves the readout requirements of SwissFEL and enables high count rate synchrotron experiments with a linear count rate capability of > 20 MHz/pixel. Promising characterization results from a 3.6 × 3.6 mm2 prototype (JUNGFRAU 0.2) with fluorescence X-ray, infrared laser and synchrotron irradiation are shown. The results include an electronic noise as low as 100 electrons root-mean-square, which enables single photon detection down to X-ray energies of about 2 keV. Noise below the Poisson fluctuation of the photon number and a linearity error of the pixel response of about 1% are demonstrated. First imaging experiments successfully show automatic gain switching. The edge spread function of the imaging system proves to be comparable in quality to single photon counting hybrid pixel detectors.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fahim, Farah; Deptuch, Grzegorz W.; Hoff, James R.

Semiconductor hybrid pixel detectors often consist of a pixellated sensor layer bump bonded to a matching pixelated readout integrated circuit (ROIC). The sensor can range from high resistivity Si to III-V materials, whereas a Si CMOS process is typically used to manufacture the ROIC. Independent, device physics and electronic design automation (EDA) tools are used to determine sensor characteristics and verify functional performance of ROICs respectively with significantly different solvers. Some physics solvers provide the capability of transferring data to the EDA tool. However, single pixel transient simulations are either not feasible due to convergence difficulties or are prohibitively long.more » A simplified sensor model, which includes a current pulse in parallel with detector equivalent capacitor, is often used; even then, spice type top-level (entire array) simulations range from days to weeks. In order to analyze detector deficiencies for a particular scientific application, accurately defined transient behavioral models of all the functional blocks are required. Furthermore, various simulations, such as transient, noise, Monte Carlo, inter-pixel effects, etc. of the entire array need to be performed within a reasonable time frame without trading off accuracy. The sensor and the analog front-end can be modeling using a real number modeling language, as complex mathematical functions or detailed data can be saved to text files, for further top-level digital simulations. Parasitically aware digital timing is extracted in a standard delay format (sdf) from the pixel digital back-end layout as well as the periphery of the ROIC. For any given input, detector level worst-case and best-case simulations are performed using a Verilog simulation environment to determine the output. Each top-level transient simulation takes no more than 10-15 minutes. The impact of changing key parameters such as sensor Poissonian shot noise, analog front-end bandwidth, jitter due to clock distribution etc. can be accurately analyzed to determine ROIC architectural viability and bottlenecks. Hence the impact of the detector parameters on the scientific application can be studied.« less

A 16 x 16-pixel retinal-prosthesis vision chip with in-pixel digital image processing in a frequency domain by use of a pulse-frequency-modulation photosensor

NASA Astrophysics Data System (ADS)

Kagawa, Keiichiro; Furumiya, Tetsuo; Ng, David C.; Uehara, Akihiro; Ohta, Jun; Nunoshita, Masahiro

2004-06-01

We are exploring the application of pulse-frequency-modulation (PFM) photosensor to retinal prosthesis for the blind because behavior of PFM photosensors is similar to retinal ganglion cells, from which visual data are transmitted from the retina toward the brain. We have developed retinal-prosthesis vision chips that reshape the output pulses of the PFM photosensor to biphasic current pulses suitable for electric stimulation of retinal cells. In this paper, we introduce image-processing functions to the pixel circuits. We have designed a 16x16-pixel retinal-prosthesis vision chip with several kinds of in-pixel digital image processing such as edge enhancement, edge detection, and low-pass filtering. This chip is a prototype demonstrator of the retinal prosthesis vision chip applicable to in-vitro experiments. By utilizing the feature of PFM photosensor, we propose a new scheme to implement the above image processing in a frequency domain by digital circuitry. Intensity of incident light is converted to a 1-bit data stream by a PFM photosensor, and then image processing is executed by a 1-bit image processor based on joint and annihilation of pulses. The retinal prosthesis vision chip is composed of four blocks: a pixels array block, a row-parallel stimulation current amplifiers array block, a decoder block, and a base current generators block. All blocks except PFM photosensors and stimulation current amplifiers are embodied as digital circuitry. This fact contributes to robustness against noises and fluctuation of power lines. With our vision chip, we can control photosensitivity and intensity and durations of stimulus biphasic currents, which are necessary for retinal prosthesis vision chip. The designed dynamic range is more than 100 dB. The amplitude of the stimulus current is given by a base current, which is common for all pixels, multiplied by a value in an amplitude memory of pixel. Base currents of the negative and positive pulses are common for the all pixels, and they are set in a linear manner. Otherwise, the value in the amplitude memory of the pixel is presented in an exponential manner to cover the wide range. The stimulus currents are put out column by column by scanning. The pixel size is 240um x 240um. Each pixel has a bonding pad on which stimulus electrode is to be formed. We will show the experimental results of the test chip.

Integration of the ATLAS FE-I4 Pixel Chip in the Mini Time Projection Chamber

NASA Astrophysics Data System (ADS)

Lopez-Thibodeaux, Mayra; Garcia-Sciveres, Maurice; Kadyk, John; Oliver-Mallory, Kelsey

2013-04-01

This project deals with development of readout for a Time Projection Chamber (TPC) prototype. This is a type of detector proposed for direct detection of dark matter (WIMPS) with direction information. The TPC is a gaseous charged particle tracking detector composed of a field cage and a gas avalanche detector. The latter is made of two Gas Electron Multipliers in series, illuminating a pixel readout integrated circuit, which measures the distribution in position and time of the output charge. We are testing the TPC prototype, filled with ArCO2 gas, using a Fe-55 x-ray source and cosmic rays. The present prototype uses an FE-I3 chip for readout. This chip was developed about 10 years ago and is presently in use within the ATLAS pixel detector at the LHC. The aim of this work is to upgrade the TPC prototype to use an FE-I4 chip. The FE-I4 has an active area of 336 mm^2 and 26880 pixels, over nine times the number of pixels in the FE-I3 chip, and an active area about six times as much. The FE-I4 chip represents the state of the art of pixel detector readout, and is presently being used to build an upgrade of the ATLAS pixel detector.

Experimental single-chip color HDTV image acquisition system with 8M-pixel CMOS image sensor

NASA Astrophysics Data System (ADS)

Shimamoto, Hiroshi; Yamashita, Takayuki; Funatsu, Ryohei; Mitani, Kohji; Nojiri, Yuji

2006-02-01

We have developed an experimental single-chip color HDTV image acquisition system using 8M-pixel CMOS image sensor. The sensor has 3840 × 2160 effective pixels and is progressively scanned at 60 frames per second. We describe the color filter array and interpolation method to improve image quality with a high-pixel-count single-chip sensor. We also describe an experimental image acquisition system we used to measured spatial frequency characteristics in the horizontal direction. The results indicate good prospects for achieving a high quality single chip HDTV camera that reduces pseudo signals and maintains high spatial frequency characteristics within the frequency band for HDTV.

WFC3/UVIS External CTE Monitor: Single-Chip CTE Measurements

NASA Astrophysics Data System (ADS)

Gosmeyer, C. M.; Baggett, S.

2016-12-01

We present the first results of single-chip measurements of charge transfer efficiency (CTE) in the UVIS channel of the Hubble Space Telescope Wide Field Camera 3 (HST/WFC3). This test was performed in Cycle 20 in two visits. In the first visit a field in the star cluster NGC 6583 was observed. In a second visit, the telescope returned to the field, but rotated by 180 degrees and with a shift in pointing that allowed the same stars to be imaged, near and far from the amplifiers, on the same chip of the two-chip UVIS field of-view. This dataset enables a measurement of CTE loss on each separate chip. The current CTE monitor measures CTE loss as an average of the two chips because it dithers by a chip-height to obtain observations of the same sources near and far from the amplifiers, instead of the more difficult to-schedule 180-degree rotation. We find that CTE loss is worse on Chip 1 than on Chip 2 across all cases for which we had data: short and long exposures and w! ith and without the pixel-based CTE correction. In the best case, for long exposures with the CTE correction applied, the max difference between the two chip's flux losses is 3%/2048 pixels. This case should apply for most science observations where the background is 12 e-/pixel. In the worst case of low-background short exposures, e.g. those without post-flash, the max difference between the two chips is 17% flux loss/2048 pixels. Uncertainties are <0.01% flux loss/2048 pixels. Because of the two chips' different CTE loss rates, we will consider adding this test as part of the routine yearly monitor and creating a chip-specific CTE correction software.

CMOS foveal image sensor chip

NASA Technical Reports Server (NTRS)

Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Bandera, Cesar (Inventor); Xia, Shu (Inventor)

2002-01-01

A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

Noise propagation issues in Belle II pixel detector power cable

DOE PAGES

Iglesias, M.; Arteche, F.; Echeverria, I.; ...

2018-04-26

The vertex detector used in the upgrade of High-Energy physics experiment Belle II includes DEPFET pixel detector (PXD) technology. In this complex topology the power supply units and the front-end electronics are connected through a PXD power cable bundle which may propagate the output noise from the power supplies to the vertex area. This article presents a study of the propagation of noise caused by power converters in the PXD cable bundle based on Multi-conductor Transmission Line (MTL) theory. The work exposes the effect of the complex cable topology and shield connections on the noise propagation, which has an impactmore » on the requirements of the power supplies. This analysis is part of the electromagnetic compatibility based design focused on functional safety to define the shield connections and power supply specifications required to ensure the successful integration of the detector and, specifically, to achieve the designed performance of the front-end electronics.« less

Noise propagation issues in Belle II pixel detector power cable

DOE Office of Scientific and Technical Information (OSTI.GOV)

Iglesias, M.; Arteche, F.; Echeverria, I.

The vertex detector used in the upgrade of High-Energy physics experiment Belle II includes DEPFET pixel detector (PXD) technology. In this complex topology the power supply units and the front-end electronics are connected through a PXD power cable bundle which may propagate the output noise from the power supplies to the vertex area. This article presents a study of the propagation of noise caused by power converters in the PXD cable bundle based on Multi-conductor Transmission Line (MTL) theory. The work exposes the effect of the complex cable topology and shield connections on the noise propagation, which has an impactmore » on the requirements of the power supplies. This analysis is part of the electromagnetic compatibility based design focused on functional safety to define the shield connections and power supply specifications required to ensure the successful integration of the detector and, specifically, to achieve the designed performance of the front-end electronics.« less

Improving Spectral Image Classification through Band-Ratio Optimization and Pixel Clustering

NASA Astrophysics Data System (ADS)

O'Neill, M.; Burt, C.; McKenna, I.; Kimblin, C.

2017-12-01

The Underground Nuclear Explosion Signatures Experiment (UNESE) seeks to characterize non-prompt observables from underground nuclear explosions (UNE). As part of this effort, we evaluated the ability of DigitalGlobe's WorldView-3 (WV3) to detect and map UNE signatures. WV3 is the current state-of-the-art, commercial, multispectral imaging satellite; however, it has relatively limited spectral and spatial resolutions. These limitations impede image classifiers from detecting targets that are spatially small and lack distinct spectral features. In order to improve classification results, we developed custom algorithms to reduce false positive rates while increasing true positive rates via a band-ratio optimization and pixel clustering front-end. The clusters resulting from these algorithms were processed with standard spectral image classifiers such as Mixture-Tuned Matched Filter (MTMF) and Adaptive Coherence Estimator (ACE). WV3 and AVIRIS data of Cuprite, Nevada, were used as a validation data set. These data were processed with a standard classification approach using MTMF and ACE algorithms. They were also processed using the custom front-end prior to the standard approach. A comparison of the results shows that the custom front-end significantly increases the true positive rate and decreases the false positive rate.This work was done by National Security Technologies, LLC, under Contract No. DE-AC52-06NA25946 with the U.S. Department of Energy. DOE/NV/25946-3283.

32 x 16 CMOS smart pixel array for optical interconnects

NASA Astrophysics Data System (ADS)

Kim, Jongwoo; Guilfoyle, Peter S.; Stone, Richard V.; Hessenbruch, John M.; Choquette, Kent D.; Kiamilev, Fouad E.

2000-05-01

Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32 X 16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 micrometers technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 micrometers technology.

Web-based DAQ systems: connecting the user and electronics front-ends

NASA Astrophysics Data System (ADS)

Lenzi, Thomas

2016-12-01

Web technologies are quickly evolving and are gaining in computational power and flexibility, allowing for a paradigm shift in the field of Data Acquisition (DAQ) systems design. Modern web browsers offer the possibility to create intricate user interfaces and are able to process and render complex data. Furthermore, new web standards such as WebSockets allow for fast real-time communication between the server and the user with minimal overhead. Those improvements make it possible to move the control and monitoring operations from the back-end servers directly to the user and to the front-end electronics, thus reducing the complexity of the data acquisition chain. Moreover, web-based DAQ systems offer greater flexibility, accessibility, and maintainability on the user side than traditional applications which often lack portability and ease of use. As proof of concept, we implemented a simplified DAQ system on a mid-range Spartan6 Field Programmable Gate Array (FPGA) development board coupled to a digital front-end readout chip. The system is connected to the Internet and can be accessed from any web browser. It is composed of custom code to control the front-end readout and of a dual soft-core Microblaze processor to communicate with the client.

A single active nanoelectromechanical tuning fork front-end radio-frequency receiver

NASA Astrophysics Data System (ADS)

Bartsch, Sebastian T.; Rusu, A.; Ionescu, Adrian M.

2012-06-01

Nanoelectromechanical systems (NEMS) offer the potential to revolutionize fundamental methods employed for signal processing in today’s telecommunication systems, owing to their spectral purity and the prospect of integration with existing technology. In this work we present a novel, front-end receiver topology based on a single device silicon nanoelectromechanical mixer-filter. The operation is demonstrated by using the signal amplification in a field effect transistor (FET) merged into a tuning fork resonator. The combination of both a transistor and a mechanical element into a hybrid unit enables on-chip functionality and performance previously unachievable in silicon. Signal mixing, filtering and demodulation are experimentally demonstrated at very high frequencies ( > 100 MHz), maintaining a high quality factor of Q = 800 and stable operation at near ambient pressure (0.1 atm) and room temperature (T = 300 K). The results show that, ultimately miniaturized, silicon NEMS can be utilized to realize multi-band, single-chip receiver systems based on NEMS mixer-filter arrays with reduced system complexity and power consumption.

CMOS Image Sensors: Electronic Camera On A Chip

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

Front-End Processing of Cell Lysates for Enhanced Chip-Based Detection

DTIC Science & Technology

2006-07-28

manipulation used in lab-on-a-chip devices. A small unknown sample is first mixed with the PNA surfactants (“PNAA”) to tag the DNA targets, and then the...unknown sample is first mixed with the PNA surfactants (hereafter referred to as “PNA amphiphiles” or “PNAA”) to tag the DNA targets, and then the...prolate ellipsoid, and mixed PNAA/SDS micelles form spherical micelles. On addition of complementary DNA, the PNAA/DNA duplexes do not participate in

Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy

PubMed Central

Valente, Virgilio; Demosthenous, Andreas

2016-01-01

This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) channels suitable for both bipolar and tetrapolar electrical impedance spectroscopy (EIS) analysis. Each VR channel occupies an area of 0.48 mm2, is capable of an operational bandwidth of 8 MHz and a linear gain in the range between −6 dB and 42 dB. The gain of the CR channel can be set to 10 kΩ, 50 kΩ or 100 kΩ and is capable of 80-dB dynamic range, with a very linear response for input currents between 10 nA and 100 μA. Each CR channel occupies an area of 0.21 mm2. The chip consumes between 530 μA and 690 μA per channel and operates from a 1.8-V supply. The chip was used to measure the impedance of capacitive interdigitated electrodes in saline solution. Measurements show close matching with results obtained using a commercial impedance analyser. The chip will be part of a fully flexible and configurable fully-integrated dual-mode EIS system for impedance sensors and bioimpedance analysis. PMID:27463721

Charge-sensitive front-end electronics with operational amplifiers for CdZnTe detectors

NASA Astrophysics Data System (ADS)

Födisch, P.; Berthel, M.; Lange, B.; Kirschke, T.; Enghardt, W.; Kaever, P.

2016-09-01

Cadmium zinc telluride (CdZnTe, CZT) radiation detectors are suitable for a variety of applications, due to their high spatial resolution and spectroscopic energy performance at room temperature. However, state-of-the-art detector systems require high-performance readout electronics. Though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, requirements of high dynamic range and high throughput are not available in any commercial circuit. Consequently, the present study develops the analog front-end electronics with operational amplifiers for an 8×8 pixelated CZT detector. For this purpose, we modeled an electrical equivalent circuit of the CZT detector with the associated charge-sensitive amplifier (CSA). Based on a detailed network analysis, the circuit design is completed by numerical values for various features such as ballistic deficit, charge-to-voltage gain, rise time, and noise level. A verification of the performance is carried out by synthetic detector signals and a pixel detector. The experimental results with the pixel detector assembly and a 22Na radioactive source emphasize the depth dependence of the measured energy. After pulse processing with depth correction based on the fit of the weighting potential, the energy resolution is 2.2% (FWHM) for the 511 keV photopeak.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Philipp, Hugh T., E-mail: htp2@cornell.edu; Tate, Mark W.; Purohit, Prafull

Modern storage rings are readily capable of providing intense x-ray pulses, tens of picoseconds in duration, millions of times per second. Exploiting the temporal structure of these x-ray sources opens avenues for studying rapid structural changes in materials. Many processes (e.g. crack propagation, deformation on impact, turbulence, etc.) differ in detail from one sample trial to the next and would benefit from the ability to record successive x-ray images with single x-ray sensitivity while framing at 5 to 10 MHz rates. To this end, we have pursued the development of fast x-ray imaging detectors capable of collecting bursts of imagesmore » that enable the isolation of single synchrotron bunches and/or bunch trains. The detector technology used is the hybrid pixel array detector (PAD) with a charge integrating front-end, and high-speed, in-pixel signal storage elements. A 384×256 pixel version, the Keck-PAD, with 150 µm × 150 µm pixels and 8 dedicated in-pixel storage elements is operational, has been tested at CHESS, and has collected data for compression wave studies. An updated version with 27 dedicated storage capacitors and identical pixel size has been fabricated.« less

Exploration of maximum count rate capabilities for large-area photon counting arrays based on polycrystalline silicon thin-film transistors

NASA Astrophysics Data System (ADS)

Liang, Albert K.; Koniczek, Martin; Antonuk, Larry E.; El-Mohri, Youcef; Zhao, Qihua

2016-03-01

Pixelated photon counting detectors with energy discrimination capabilities are of increasing clinical interest for x-ray imaging. Such detectors, presently in clinical use for mammography and under development for breast tomosynthesis and spectral CT, usually employ in-pixel circuits based on crystalline silicon - a semiconductor material that is generally not well-suited for economic manufacture of large-area devices. One interesting alternative semiconductor is polycrystalline silicon (poly-Si), a thin-film technology capable of creating very large-area, monolithic devices. Similar to crystalline silicon, poly-Si allows implementation of the type of fast, complex, in-pixel circuitry required for photon counting - operating at processing speeds that are not possible with amorphous silicon (the material currently used for large-area, active matrix, flat-panel imagers). The pixel circuits of two-dimensional photon counting arrays are generally comprised of four stages: amplifier, comparator, clock generator and counter. The analog front-end (in particular, the amplifier) strongly influences performance and is therefore of interest to study. In this paper, the relationship between incident and output count rate of the analog front-end is explored under diagnostic imaging conditions for a promising poly-Si based design. The input to the amplifier is modeled in the time domain assuming a realistic input x-ray spectrum. Simulations of circuits based on poly-Si thin-film transistors are used to determine the resulting output count rate as a function of input count rate, energy discrimination threshold and operating conditions.

X-ray performance of 0.18 µm CMOS APS test arrays for solar observation

NASA Astrophysics Data System (ADS)

Dryer, B. J.; Holland, A. D.; Jerram, P.; Sakao, Taro

2012-07-01

Solar-C is the third generation solar observatory led by JAXA. The accepted ‘Plan-B’ payload calls for a radiation-hard solar-staring photon-counting x-ray spectrometer. CMOS APS technology offers advantages over CCDs for such an application such as increased radiation hardness and high frame rate (instrument target of 1000 fps). Looking towards the solution of a bespoke CMOS APS, this paper reports the x-ray spectroscopy performance, concentrating on charge collection efficiency and split event analysis, of two baseline e2v CMOS APSs not designed for x-ray performance, the EV76C454 and the Ocean Colour Imager (OCI) test array. The EV76C454 is an industrial 5T APS designed for machine vision, available back and front illuminated. The OCI test arrays have varying pixel design across the chips, but are 4T, back illuminated and have thin low-resistivity and thick high-resistivity variants. The OCI test arrays’ pixel variants allow understanding of how pixel design can affect x-ray performance.

A digital pixel cell for address event representation image convolution processing

NASA Astrophysics Data System (ADS)

Camunas-Mesa, Luis; Acosta-Jimenez, Antonio; Serrano-Gotarredona, Teresa; Linares-Barranco, Bernabe

2005-06-01

Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number of neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate events according to their information levels. Neurons with more information (activity, derivative of activities, contrast, motion, edges,...) generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. AER technology has been used and reported for the implementation of various type of image sensors or retinae: luminance with local agc, contrast retinae, motion retinae,... Also, there has been a proposal for realizing programmable kernel image convolution chips. Such convolution chips would contain an array of pixels that perform weighted addition of events. Once a pixel has added sufficient event contributions to reach a fixed threshold, the pixel fires an event, which is then routed out of the chip for further processing. Such convolution chips have been proposed to be implemented using pulsed current mode mixed analog and digital circuit techniques. In this paper we present a fully digital pixel implementation to perform the weighted additions and fire the events. This way, for a given technology, there is a fully digital implementation reference against which compare the mixed signal implementations. We have designed, implemented and tested a fully digital AER convolution pixel. This pixel will be used to implement a full AER convolution chip for programmable kernel image convolution processing.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jones, M.

Configuration and calibration of the front-end electronics typical of many silicon detector configurations were investigated in a lab activity based on a pair of strip sensors interfaced with FSSR2 read-out chips and an FPGA. This simple hardware configuration, originally developed for a telescope at the Fermilab Test Beam Facility, was used to measure thresholds and noise on individual readout channels and to study the influence that different configurations of the front-end electronics had on the observed levels of noise in the system. An understanding of the calibration and operation of this small detector system provided an opportunity to explore themore » architecture of larger systems such as those currently in use at LHC experiments.« less

Analog front-end design of the STS/MUCH-XYTER2—full size prototype ASIC for the CBM experiment

NASA Astrophysics Data System (ADS)

Kleczek, Rafal

2017-01-01

The design of the analog front-end of the STS/MUCH-XYTER2 ASIC, a full-size prototype chip for the Silicon Tracking System (STS, based on double-sided silicon strip sensors) and Muon Chamber (MUCH, based on gas sensors) detectors is presented. The ASIC contains 128 charge processing channels, each built of a charge sensitive amplifier, a polarity selection circuit and two pulse shaping amplifiers forming two parallel signal paths. The first path is used for timing measurement with a fast discriminator. The second path allows low-noise amplitude measurement with a 5-bit continuous-time flash ADC. Different operating conditions and constraints posed by two target detectors' applications require front-end electronics flexibility to meet extended system-wise requirements. The presented circuit implements switchable shaper peaking time, gain switching and trimming, input amplifier pulsed reset circuit, fail-safe measures. The power consumption is scalable (for the STS and the MUCH modes), but limited to 10 mW/channel.

Solid-State Photomultiplier with Integrated Front End Electronics

NASA Astrophysics Data System (ADS)

Christian, James; Stapels, Christopher; Johnson, Erik; Mukhopadhyay, Sharmistha; Jie Chen, Xiao; Miskimen, Rory

2009-10-01

The instrumentation cost of physics experiments has been reduced per channel, by the use of solid-state detectors, but these cost-effective techniques have not been translated to scintillation-based detectors. When considering photodetectors, the cost per channel is determined by the use of high-voltage, analog-to-digital converters, BNC cables, and any other ancillary devices. The overhead associated with device operation limits the number of channels for the detector system, while potentially limiting the scope of physics that can be explored. The PRIMEX experiment at JLab, which is being designed to measure the radiative widths of the η and η' pseudo-scalar mesons for a more comprehensive understanding of QCD at low energies, is an example where CMOS solid-state photomultipliers (SSPMs) can be implemented. The ubiquitous nature of CMOS allows for on-chip signal processing to provide front-end electronics within the detector package. We present the results of the device development for the PRIMEX calorimeter, discussing the characteristics of SSPMs, the potential cost savings, and experimental results of on-chip signal processing.

High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip.

PubMed

Issadore, David; Franke, Thomas; Brown, Keith A; Hunt, Thomas P; Westervelt, Robert M

2009-12-01

A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm(2) in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip's surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications.

A 0.5 cm(3) four-channel 1.1 mW wireless biosignal interface with 20 m range.

PubMed

Morrison, Tim; Nagaraju, Manohar; Winslow, Brent; Bernard, Amy; Otis, Brian P

2014-02-01

This paper presents a self-contained, single-chip biosignal monitoring system with wireless programmability and telemetry interface suitable for mainstream healthcare applications. The system consists of low-noise front end amplifiers, ADC, MICS/ISM transmitter and infrared programming capability to configure the state of the chip. An on-chip packetizer ensures easy pairing with standard off-the-shelf receivers. The chip is realized in the IBM 130 nm CMOS process with an area of 2×2 mm(2). The entire system consumes 1.07 mW from a 1.2 V supply. It weighs 0.6 g including a zinc-air battery. The system has been extensively tested in in vivo biological experiments and requires minimal human interaction or calibration.

2.5 Gbit/s Optical Receiver Front-End Circuit with High Sensitivity and Wide Dynamic Range

NASA Astrophysics Data System (ADS)

Zhu, Tiezhu; Mo, Taishan; Ye, Tianchun

2017-12-01

An optical receiver front-end circuit is designed for passive optical network and fabricated in a 0.18 um CMOS technology. The whole circuit consists of a transimpedance amplifier (TIA), a single-ended to differential amplifier and an output driver. The TIA employs a cascode stage as the input stage and auxiliary amplifier to reduce the miller effect. Current injecting technique is employed to enlarge the input transistor's transconductance, optimize the noise performance and overcome the lack of voltage headroom. To achieve a wide dynamic range, an automatic gain control circuit with self-adaptive function is proposed. Experiment results show an optical sensitivity of -28 dBm for a bit error rate of 10-10 at 2.5 Gbit/s and a maxim input optical power of 2 dBm using an external photodiode. The chip occupies an area of 1×0.9 mm2 and consumes around 30 mW from single 1.8 V supply. The front-end circuit can be used in various optical receivers.

CdTe focal plane detector for hard x-ray focusing optics

NASA Astrophysics Data System (ADS)

Seller, Paul; Wilson, Matthew D.; Veale, Matthew C.; Schneider, Andreas; Gaskin, Jessica; Wilson-Hodge, Colleen; Christe, Steven; Shih, Albert Y.; Gregory, Kyle; Inglis, Andrew; Panessa, Marco

2015-08-01

The demand for higher resolution x-ray optics (a few arcseconds or better) in the areas of astrophysics and solar science has, in turn, driven the development of complementary detectors. These detectors should have fine pixels, necessary to appropriately oversample the optics at a given focal length, and an energy response also matched to that of the optics. Rutherford Appleton Laboratory have developed a 3-side buttable, 20 mm x 20 mm CdTe-based detector with 250 μm square pixels (80x80 pixels) which achieves 1 keV FWHM @ 60 keV and gives full spectroscopy between 5 keV and 200 keV. An added advantage of these detectors is that they have a full-frame readout rate of 10 kHz. Working with NASA Goddard Space Flight Center and Marshall Space Flight Center, 4 of these 1mm-thick CdTe detectors are tiled into a 2x2 array for use at the focal plane of a balloon-borne hard-x-ray telescope, and a similar configuration could be suitable for astrophysics and solar space-based missions. This effort encompasses the fabrication and testing of flightsuitable front-end electronics and calibration of the assembled detector arrays. We explain the operation of the pixelated ASIC readout and measurements, front-end electronics development, preliminary X-ray imaging and spectral performance, and plans for full calibration of the detector assemblies. Work done in conjunction with the NASA Centers is funded through the NASA Science Mission Directorate Astrophysics Research and Analysis Program.

CdTe Focal Plane Detector for Hard X-Ray Focusing Optics

NASA Technical Reports Server (NTRS)

Seller, Paul; Wilson, Matthew D.; Veale, Matthew C.; Schneider, Andreas; Gaskin, Jessica; Wilson-Hodge, Colleen; Christe, Steven; Shih, Albert Y.; Inglis, Andrew; Panessa, Marco

2015-01-01

The demand for higher resolution x-ray optics (a few arcseconds or better) in the areas of astrophysics and solar science has, in turn, driven the development of complementary detectors. These detectors should have fine pixels, necessary to appropriately oversample the optics at a given focal length, and an energy response also matched to that of the optics. Rutherford Appleton Laboratory have developed a 3-side buttable, 20 millimeter x 20 millimeter CdTe-based detector with 250 micrometer square pixels (80 x 80 pixels) which achieves 1 kiloelectronvolt FWHM (Full-Width Half-Maximum) @ 60 kiloelectronvolts and gives full spectroscopy between 5 kiloelectronvolts and 200 kiloelectronvolts. An added advantage of these detectors is that they have a full-frame readout rate of 10 kilohertz. Working with NASA Goddard Space Flight Center and Marshall Space Flight Center, 4 of these 1 millimeter-thick CdTe detectors are tiled into a 2 x 2 array for use at the focal plane of a balloon-borne hard-x-ray telescope, and a similar configuration could be suitable for astrophysics and solar space-based missions. This effort encompasses the fabrication and testing of flight-suitable front-end electronics and calibration of the assembled detector arrays. We explain the operation of the pixelated ASIC readout and measurements, front-end electronics development, preliminary X-ray imaging and spectral performance, and plans for full calibration of the detector assemblies. Work done in conjunction with the NASA Centers is funded through the NASA Science Mission Directorate Astrophysics Research and Analysis Program.

Compact Receiver Front Ends for Submillimeter-Wave Applications

NASA Technical Reports Server (NTRS)

Mehdi, Imran; Chattopadhyay, Goutam; Schlecht, Erich T.; Lin, Robert H.; Sin, Seth; Peralta, Alejandro; Lee, Choonsup; Gill, John J.; Gulkis, Samuel; Thomas, Bertrand C.

2012-01-01

The current generation of submillimeter-wave instruments is relatively mass and power-hungry. The receiver front ends (RFEs) of a submillimeter instrument form the heart of the instrument, and any mass reduction achieved in this subsystem is propagated through the instrument. In the current implementation, the RFE consists of different blocks for the mixer and LO circuits. The motivation for this work is to reduce the mass of the RFE by integrating the mixer and LO circuits in one waveguide block. The mixer and its associated LO chips will all be packaged in a single waveguide package. This will reduce the mass of the RFE and also provide a number of other advantages. By bringing the mixer and LO circuits close together, losses in the waveguide will be reduced. Moreover, the compact nature of the block will allow for better thermal control of the block, which is important in order to reduce gain fluctuations. A single waveguide block with a 600- GHz RFE functionality (based on a subharmonically pumped Schottky diode pair) has been demonstrated. The block is about 3x3x3 cubic centimeters. The block combines the mixer and multiplier chip in a single package. 3D electromagnetic simulations were carried out to design the waveguide circuit around the mixer and multiplier chip. The circuit is optimized to provide maximum output power and maximum bandwidth. An integrated submillimeter front end featuring a 520-600-GHz sub-harmonic mixer and a 260-300-GHz frequency tripler in a single cavity was tested. Both devices used GaAs MMIC membrane planar Schottky diode technology. The sub-harmonic mixer/tripler circuit has been tested using conventional metal-machined blocks. Measurement results on the metal block give best DSB (double sideband) mixer noise temperature of 2,360 K and conversion losses of 7.7 dB at 520 GHz. The LO input power required to pump the integrated tripler/sub-harmonic mixer is between 30 and 50 mW.

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability.

PubMed

Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U

2015-03-06

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle.

An Ultra-Low Power CMOS Image Sensor with On-Chip Energy Harvesting and Power Management Capability

PubMed Central

Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U.

2015-01-01

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle. PMID:25756863

New results on diamond pixel sensors using ATLAS frontend electronics

NASA Astrophysics Data System (ADS)

Keil, M.; Adam, W.; Berdermann, E.; Bergonzo, P.; de Boer, W.; Bogani, F.; Borchi, E.; Brambilla, A.; Bruzzi, M.; Colledani, C.; Conway, J.; D'Angelo, P.; Dabrowski, W.; Delpierre, P.; Dulinski, W.; Doroshenko, J.; Doucet, M.; van Eijk, B.; Fallou, A.; Fischer, P.; Fizzotti, F.; Kania, D.; Gan, K. K.; Grigoriev, E.; Hallewell, G.; Han, S.; Hartjes, F.; Hrubec, J.; Husson, D.; Kagan, H.; Kaplon, J.; Kass, R.; Knöpfle, K. T.; Koeth, T.; Krammer, M.; Logiudice, A.; mac Lynne, L.; Manfredotti, C.; Meier, D.; Menichelli, D.; Meuser, S.; Mishina, M.; Moroni, L.; Noomen, J.; Oh, A.; Pan, L. S.; Pernicka, M.; Perera, L.; Riester, J. L.; Roe, S.; Rudge, A.; Russ, J.; Sala, S.; Sampietro, M.; Schnetzer, S.; Sciortino, S.; Stelzer, H.; Stone, R.; Suter, B.; Trischuk, W.; Tromson, D.; Vittone, E.; Weilhammer, P.; Wermes, N.; Wetstein, M.; Zeuner, W.; Zoeller, M.

2003-03-01

Diamond is a promising sensor material for future collider experiments due to its radiation hardness. Diamond pixel sensors have been bump bonded to an ATLAS pixel readout chip using PbSn solder bumps. Single chip devices have been characterised by lab measurements and in a high-energy pion beam at CERN. Results on charge collection, spatial resolution, efficiency and the charge carrier lifetime are presented.

The Level 0 Pixel Trigger system for the ALICE experiment

NASA Astrophysics Data System (ADS)

Aglieri Rinella, G.; Kluge, A.; Krivda, M.; ALICE Silicon Pixel Detector project

2007-01-01

The ALICE Silicon Pixel Detector contains 1200 readout chips. Fast-OR signals indicate the presence of at least one hit in the 8192 pixel matrix of each chip. The 1200 bits are transmitted every 100 ns on 120 data readout optical links using the G-Link protocol. The Pixel Trigger System extracts and processes them to deliver an input signal to the Level 0 trigger processor targeting a latency of 800 ns. The system is compact, modular and based on FPGA devices. The architecture allows the user to define and implement various trigger algorithms. The system uses advanced 12-channel parallel optical fiber modules operating at 1310 nm as optical receivers and 12 deserializer chips closely packed in small area receiver boards. Alternative solutions with multi-channel G-Link deserializers implemented directly in programmable hardware devices were investigated. The design of the system and the progress of the ALICE Pixel Trigger project are described in this paper.

Tracking performance of a single-crystal and a polycrystalline diamond pixel-detector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Menasce, D.; et al.

2013-06-01

We present a comparative characterization of the performance of a single-crystal and a polycrystalline diamond pixel-detector employing the standard CMS pixel readout chips. Measurements were carried out at the Fermilab Test Beam Facility, FTBF, using protons of momentum 120 GeV/c tracked by a high-resolution pixel telescope. Particular attention was directed to the study of the charge-collection, the charge-sharing among adjacent pixels and the achievable position resolution. The performance of the single-crystal detector was excellent and comparable to the best available silicon pixel-detectors. The measured average detection-efficiency was near unity, ε = 0.99860±0.00006, and the position-resolution for shared hits was aboutmore » 6 μm. On the other hand, the performance of the polycrystalline detector was hampered by its lower charge collection distance and the readout chip threshold. A new readout chip, capable of operating at much lower threshold (around 1 ke $-$), would be required to fully exploit the potential performance of the polycrystalline diamond pixel-detector.« less

Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

NASA Astrophysics Data System (ADS)

Kremastiotis, I.

2017-12-01

The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128×128 square pixels with 25μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (~20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ~20 ns for a power consumption of 5μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (~20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using future assemblies with the readout chip.

Optimizing read-out of the NECTAr front-end electronics

NASA Astrophysics Data System (ADS)

Vorobiov, S.; Feinstein, F.; Bolmont, J.; Corona, P.; Delagnes, E.; Falvard, A.; Gascón, D.; Glicenstein, J.-F.; Naumann, C. L.; Nayman, P.; Ribo, M.; Sanuy, A.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.

2012-12-01

We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

Lensfree on-chip microscopy over a wide field-of-view using pixel super-resolution

PubMed Central

Bishara, Waheb; Su, Ting-Wei; Coskun, Ahmet F.; Ozcan, Aydogan

2010-01-01

We demonstrate lensfree holographic microscopy on a chip to achieve ~0.6 µm spatial resolution corresponding to a numerical aperture of ~0.5 over a large field-of-view of ~24 mm2. By using partially coherent illumination from a large aperture (~50 µm), we acquire lower resolution lensfree in-line holograms of the objects with unit fringe magnification. For each lensfree hologram, the pixel size at the sensor chip limits the spatial resolution of the reconstructed image. To circumvent this limitation, we implement a sub-pixel shifting based super-resolution algorithm to effectively recover much higher resolution digital holograms of the objects, permitting sub-micron spatial resolution to be achieved across the entire sensor chip active area, which is also equivalent to the imaging field-of-view (24 mm2) due to unit magnification. We demonstrate the success of this pixel super-resolution approach by imaging patterned transparent substrates, blood smear samples, as well as Caenoharbditis Elegans. PMID:20588977

Towards a Chemiresistive Sensor-Integrated Electronic Nose: A Review

PubMed Central

Chiu, Shih-Wen; Tang, Kea-Tiong

2013-01-01

Electronic noses have potential applications in daily life, but are restricted by their bulky size and high price. This review focuses on the use of chemiresistive gas sensors, metal-oxide semiconductor gas sensors and conductive polymer gas sensors in an electronic nose for system integration to reduce size and cost. The review covers the system design considerations and the complementary metal-oxide-semiconductor integrated technology for a chemiresistive gas sensor electronic nose, including the integrated sensor array, its readout interface, and pattern recognition hardware. In addition, the state-of-the-art technology integrated in the electronic nose is also presented, such as the sensing front-end chip, electronic nose signal processing chip, and the electronic nose system-on-chip. PMID:24152879

On-chip copper-dielectric interference filters for manufacturing of ambient light and proximity CMOS sensors.

PubMed

Frey, Laurent; Masarotto, Lilian; D'Aillon, Patrick Gros; Pellé, Catherine; Armand, Marilyn; Marty, Michel; Jamin-Mornet, Clémence; Lhostis, Sandrine; Le Briz, Olivier

2014-07-10

Filter technologies implemented on CMOS image sensors for spectrally selective applications often use a combination of on-chip organic resists and an external substrate with multilayer dielectric coatings. The photopic-like and near-infrared bandpass filtering functions respectively required by ambient light sensing and user proximity detection through time-of-flight can be fully integrated on chip with multilayer metal-dielectric filters. Copper, silicon nitride, and silicon oxide are the materials selected for a technological proof-of-concept on functional wafers, due to their immediate availability in front-end semiconductor fabs. Filter optical designs are optimized with respect to specific performance criteria, and the robustness of the designs regarding process errors are evaluated for industrialization purposes.

First results of the front-end ASIC for the strip detector of the PANDA MVD

NASA Astrophysics Data System (ADS)

Quagli, T.; Brinkmann, K.-T.; Calvo, D.; Di Pietro, V.; Lai, A.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Wheadon, R.; Zambanini, A.

2017-03-01

PANDA is a key experiment of the future FAIR facility and the Micro Vertex Detector (MVD) is the innermost part of its tracking system. PASTA (PAnda STrip ASIC) is the readout chip for the strip part of the MVD. The chip is designed to provide high resolution timestamp and charge information with the Time over Threshold (ToT) technique. Its architecture is based on Time to Digital Converters with analog interpolators, with a time bin width of 50 ps. The chip implements Single Event Upset (SEU) protection techniques for its digital parts. A first full-size prototype with 64 channels was produced in a commercial 110 nm CMOS technology and the first characterizations of the prototype were performed.

Preliminary Results of 3D-DDTC Pixel Detectors for the ATLAS Upgrade

DOE Office of Scientific and Technical Information (OSTI.GOV)

La Rosa, Alessandro; /CERN; Boscardin, M.

2012-04-04

3D Silicon sensors fabricated at FBK-irst with the Double-side Double Type Column (DDTC) approach and columnar electrodes only partially etched through p-type substrates were tested in laboratory and in a 1.35 Tesla magnetic field with a 180 GeV pion beam at CERN SPS. The substrate thickness of the sensors is about 200 {mu}m, and different column depths are available, with overlaps between junction columns (etched from the front side) and ohmic columns (etched from the back side) in the range from 110 {mu}m to 150 {mu}m. The devices under test were bump bonded to the ATLAS Pixel readout chip (FEI3)more » at SELEX SI (Rome, Italy). We report leakage current and noise measurements, results of functional tests with Am{sup 241} {gamma}-ray sources, charge collection tests with Sr90 {beta}-source and an overview of preliminary results from the CERN beam test.« less

Time-resolved optical spectrometer based on a monolithic array of high-precision TDCs and SPADs

NASA Astrophysics Data System (ADS)

Tamborini, Davide; Markovic, Bojan; Di Sieno, Laura; Contini, Davide; Bassi, Andrea; Tisa, Simone; Tosi, Alberto; Zappa, Franco

2013-12-01

We present a compact time-resolved spectrometer suitable for optical spectroscopy from 400 nm to 1 μm wavelengths. The detector consists of a monolithic array of 16 high-precision Time-to-Digital Converters (TDC) and Single-Photon Avalanche Diodes (SPAD). The instrument has 10 ps resolution and reaches 70 ps (FWHM) timing precision over a 160 ns full-scale range with a Differential Non-Linearity (DNL) better than 1.5 % LSB. The core of the spectrometer is the application-specific integrated chip composed of 16 pixels with 250 μm pitch, containing a 20 μm diameter SPAD and an independent TDC each, fabricated in a 0.35 μm CMOS technology. In front of this array a monochromator is used to focus different wavelengths into different pixels. The spectrometer has been used for fluorescence lifetime spectroscopy: 5 nm spectral resolution over an 80 nm bandwidth is achieved. Lifetime spectroscopy of Nile blue is demonstrated.

High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip

PubMed Central

Issadore, David; Franke, Thomas; Brown, Keith A.; Hunt, Thomas P.; Westervelt, Robert M.

2010-01-01

A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm2 in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip’s surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications. PMID:20625468

A Chip and Pixel Qualification Methodology on Imaging Sensors

NASA Technical Reports Server (NTRS)

Chen, Yuan; Guertin, Steven M.; Petkov, Mihail; Nguyen, Duc N.; Novak, Frank

2004-01-01

This paper presents a qualification methodology on imaging sensors. In addition to overall chip reliability characterization based on sensor s overall figure of merit, such as Dark Rate, Linearity, Dark Current Non-Uniformity, Fixed Pattern Noise and Photon Response Non-Uniformity, a simulation technique is proposed and used to project pixel reliability. The projected pixel reliability is directly related to imaging quality and provides additional sensor reliability information and performance control.

Status of the photomultiplier-based FlashCam camera for the Cherenkov Telescope Array

NASA Astrophysics Data System (ADS)

Pühlhofer, G.; Bauer, C.; Eisenkolb, F.; Florin, D.; Föhr, C.; Gadola, A.; Garrecht, F.; Hermann, G.; Jung, I.; Kalekin, O.; Kalkuhl, C.; Kasperek, J.; Kihm, T.; Koziol, J.; Lahmann, R.; Manalaysay, A.; Marszalek, A.; Rajda, P. J.; Reimer, O.; Romaszkan, W.; Rupinski, M.; Schanz, T.; Schwab, T.; Steiner, S.; Straumann, U.; Tenzer, C.; Vollhardt, A.; Weitzel, Q.; Winiarski, K.; Zietara, K.

2014-07-01

The FlashCam project is preparing a camera prototype around a fully digital FADC-based readout system, for the medium sized telescopes (MST) of the Cherenkov Telescope Array (CTA). The FlashCam design is the first fully digital readout system for Cherenkov cameras, based on commercial FADCs and FPGAs as key components for digitization and triggering, and a high performance camera server as back end. It provides the option to easily implement different types of trigger algorithms as well as digitization and readout scenarios using identical hardware, by simply changing the firmware on the FPGAs. The readout of the front end modules into the camera server is Ethernet-based using standard Ethernet switches and a custom, raw Ethernet protocol. In the current implementation of the system, data transfer and back end processing rates of 3.8 GB/s and 2.4 GB/s have been achieved, respectively. Together with the dead-time-free front end event buffering on the FPGAs, this permits the cameras to operate at trigger rates of up to several ten kHz. In the horizontal architecture of FlashCam, the photon detector plane (PDP), consisting of photon detectors, preamplifiers, high voltage-, control-, and monitoring systems, is a self-contained unit, mechanically detached from the front end modules. It interfaces to the digital readout system via analogue signal transmission. The horizontal integration of FlashCam is expected not only to be more cost efficient, it also allows PDPs with different types of photon detectors to be adapted to the FlashCam readout system. By now, a 144-pixel mini-camera" setup, fully equipped with photomultipliers, PDP electronics, and digitization/ trigger electronics, has been realized and extensively tested. Preparations for a full-scale, 1764 pixel camera mechanics and a cooling system are ongoing. The paper describes the status of the project.

Design and characterization of novel monolithic pixel sensors for the ALICE ITS upgrade

NASA Astrophysics Data System (ADS)

Cavicchioli, C.; Chalmet, P. L.; Giubilato, P.; Hillemanns, H.; Junique, A.; Kugathasan, T.; Mager, M.; Marin Tobon, C. A.; Martinengo, P.; Mattiazzo, S.; Mugnier, H.; Musa, L.; Pantano, D.; Rousset, J.; Reidt, F.; Riedler, P.; Snoeys, W.; Van Hoorne, J. W.; Yang, P.

2014-11-01

Within the R&D activities for the upgrade of the ALICE Inner Tracking System (ITS), Monolithic Active Pixel Sensors (MAPS) are being developed and studied, due to their lower material budget ( 0.3 %X0 in total for each inner layer) and higher granularity ( 20 μm × 20 μm pixels) with respect to the present pixel detector. This paper presents the design and characterization results of the Explorer0 chip, manufactured in the TowerJazz 180 nm CMOS Imaging Sensor process, based on a wafer with high-resistivity (ρ > 1 kΩ cm) and 18 μm thick epitaxial layer. The chip is organized in two sub-matrices with different pixel pitches (20 μm and 30 μm), each of them containing several pixel designs. The collection electrode size and shape, as well as the distance between the electrode and the surrounding electronics, are varied; the chip also offers the possibility to decouple the charge integration time from the readout time, and to change the sensor bias. The charge collection properties of the different pixel variants implemented in Explorer0 have been studied using a 55Fe X-ray source and 1-5 GeV/c electrons and positrons. The sensor capacitance has been estimated, and the effect of the sensor bias has also been examined in detail. A second version of the Explorer0 chip (called Explorer1) has been submitted for production in March 2013, together with a novel circuit with in-pixel discrimination and a sparsified readout. Results from these submissions are also presented.

Active-Pixel Image Sensor With Analog-To-Digital Converters

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Mendis, Sunetra K.; Pain, Bedabrata; Nixon, Robert H.

1995-01-01

Proposed single-chip integrated-circuit image sensor contains 128 x 128 array of active pixel sensors at 50-micrometer pitch. Output terminals of all pixels in each given column connected to analog-to-digital (A/D) converter located at bottom of column. Pixels scanned in semiparallel fashion, one row at time; during time allocated to scanning row, outputs of all active pixel sensors in row fed to respective A/D converters. Design of chip based on complementary metal oxide semiconductor (CMOS) technology, and individual circuit elements fabricated according to 2-micrometer CMOS design rules. Active pixel sensors designed to operate at video rate of 30 frames/second, even at low light levels. A/D scheme based on first-order Sigma-Delta modulation.

Radiation hard analog circuits for ALICE ITS upgrade

NASA Astrophysics Data System (ADS)

Gajanana, D.; Gromov, V.; Kuijer, P.; Kugathasan, T.; Snoeys, W.

2016-03-01

The ALICE experiment is planning to upgrade the ITS (Inner Tracking System) [1] detector during the LS2 shutdown. The present ITS will be fully replaced with a new one entirely based on CMOS monolithic pixel sensor chips fabricated in TowerJazz CMOS 0.18 μ m imaging technology. The large (3 cm × 1.5 cm = 4.5 cm2) ALPIDE (ALICE PIxel DEtector) sensor chip contains about 500 Kpixels, and will be used to cover a 10 m2 area with 12.5 Gpixels distributed over seven cylindrical layers. The ALPOSE chip was designed as a test chip for the various building blocks foreseen in the ALPIDE [2] pixel chip from CERN. The building blocks include: bandgap and Temperature sensor in four different flavours, and LDOs for powering schemes. One flavour of bandgap and temperature sensor will be included in the ALPIDE chip. Power consumption numbers have dropped very significantly making the use of LDOs less interesting, but in this paper all blocks are presented including measurement results before and after irradiation with neutrons to characterize robustness against displacement damage.

Design of the low area monotonic trim DAC in 40 nm CMOS technology for pixel readout chips

NASA Astrophysics Data System (ADS)

Drozd, A.; Szczygiel, R.; Maj, P.; Satlawa, T.; Grybos, P.

2014-12-01

The recent research in hybrid pixel detectors working in single photon counting mode focuses on nanometer or 3D technologies which allow making pixels smaller and implementing more complex solutions in each of the pixels. Usually single pixel in readout electronics for X-ray detection comprises of charge amplifier, shaper and discriminator that allow classification of events occurring at the detector as true or false hits by comparing amplitude of the signal obtained with threshold voltage, which minimizes the influence of noise effects. However, making the pixel size smaller often causes problems with pixel to pixel uniformity and additional effects like charge sharing become more visible. To improve channel-to-channel uniformity or implement an algorithm for charge sharing effect minimization, small area trimming DACs working in each pixel independently are necessary. However, meeting the requirement of small area often results in poor linearity and even non-monotonicity. In this paper we present a novel low-area thermometer coded 6-bit DAC implemented in 40 nm CMOS technology. Monte Carlo simulations were performed on the described design proving that under all conditions designed DAC is inherently monotonic. Presented DAC was implemented in the prototype readout chip with 432 pixels working in single photon counting mode, with two trimming DACs in each pixel. Each DAC occupies the area of 8 μm × 18.5 μm. Measurements and chips' tests were performed to obtain reliable statistical results.

Computation of dark frames in digital imagers

NASA Astrophysics Data System (ADS)

Widenhorn, Ralf; Rest, Armin; Blouke, Morley M.; Berry, Richard L.; Bodegom, Erik

2007-02-01

Dark current is caused by electrons that are thermally exited into the conduction band. These electrons are collected by the well of the CCD and add a false signal to the chip. We will present an algorithm that automatically corrects for dark current. It uses a calibration protocol to characterize the image sensor for different temperatures. For a given exposure time, the dark current of every pixel is characteristic of a specific temperature. The dark current of every pixel can therefore be used as an indicator of the temperature. Hot pixels have the highest signal-to-noise ratio and are the best temperature sensors. We use the dark current of a several hundred hot pixels to sense the chip temperature and predict the dark current of all pixels on the chip. Dark current computation is not a new concept, but our approach is unique. Some advantages of our method include applicability for poorly temperature-controlled camera systems and the possibility of ex post facto dark current correction.

Towards Gotthard-II: development of a silicon microstrip detector for the European X-ray Free-Electron Laser

NASA Astrophysics Data System (ADS)

Zhang, J.; Andrä, M.; Barten, R.; Bergamaschi, A.; Brückner, M.; Dinapoli, R.; Fröjdh, E.; Greiffenberg, D.; Lopez-Cuenca, C.; Mezza, D.; Mozzanica, A.; Ramilli, M.; Redford, S.; Ruat, M.; Ruder, C.; Schmitt, B.; Shi, X.; Thattil, D.; Tinti, G.; Turcato, M.; Vetter, S.

2018-01-01

Gotthard-II is a 1-D microstrip detector specifically developed for the European X-ray Free-Electron Laser. It will not only be used in energy dispersive experiments but also as a beam diagnostic tool with additional logic to generate veto signals for the other 2-D detectors. Gotthard-II makes use of a silicon microstrip sensor with a pitch of either 50 μm or 25 μm and with 1280 or 2560 channels wire-bonded to adaptive gain switching readout chips. Built-in analog-to-digital converters and digital memories will be implemented in the readout chip for a continuous conversion and storage of frames for all bunches in the bunch train. The performance of analogue front-end prototypes of Gotthard has been investigated in this work. The results in terms of noise, conversion gain, dynamic range, obtained by means of infrared laser and X-rays, will be shown. In particular, the effects of the strip-to-strip coupling are studied in detail and it is found that the reduction of the coupling effects is one of the key factors for the development of the analogue front-end of Gotthard-II.

Market trends in the projection display industry

NASA Astrophysics Data System (ADS)

Dash, Sweta

2001-03-01

The projection display industry represents a multibillion- dollar market that includes four distinct technologies. High-volume consumer products and high-value business products drive the market, with different technologies being used in different application markets. The consumer market is dominated by rear CRT technology, especially in the projection TV segment. Rear LCD (liquid crystal display), MEMS/DLP (or Digital Light Processing TM) and LCOS (Liquid-crystal-on-silicon) TVs are slowly emerging as future competitors to rear CRT projectors. Front CRT projectors are also facing challenges from LCD and DLP technology for the home theater market while the business market is completely dominated by front LCD and DLP technology. Three-chip DLP projectors have replaced liquid crystal light valves in large venue applications where projectors have higher light output requirements. In recent years front LCD and LCOS projectors have been increasingly competing with 3-chip DLP projectors especially at the low end of the large venue application market. Within the next five years the projection market will experience very fast growth. Sales and presentation applications, which are the fastest growing applications in the business market, will continue to be the major driving force for the growth for front projectors, and the shift in the consumer market to digital and HDTV products will drive the rear projection market.

A 0.09 μW low power front-end biopotential amplifier for biosignal recording.

PubMed

Tseng, Yuhwai; Ho, Yingchieh; Kao, Shuoting; Su, Chauchin

2012-10-01

This work presents a biopotential front-end amplifier in which the MOS transistors are biased in subthreshold region with a supply voltage and current of 0.4-0.8 V and 0.23-1.86 μA, respectively, to reduce the system power. Flicker noise is then removed using a chopping technique, and differential interference produced by electrode impedance imbalance is suppressed using a Gm-C filter. Additionally, the circuit is fabricated using TSMC 0.18 μm CMOS technology with a core area of 0.77 × 0.36 mm². With a minimum supply voltage of 0.4 V, the measured SNR and power consumption of the proposed IC chip are 54.1 dB and 0.09μW, respectively.

JPL CMOS Active Pixel Sensor Technology

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

A front-end readout mixed chip for high-efficiency small animal PET imaging

NASA Astrophysics Data System (ADS)

Ollivier-Henry, N.; Berst, J. D.; Colledani, C.; Hu-Guo, Ch.; Mbow, N. A.; Staub, D.; Guyonnet, J. L.; Hu, Y.

2007-02-01

Today, the main challenge of Positron Emission Tomography (PET) systems dedicated to small animal imaging is to obtain high detection efficiency and a highly accurate localization of radioisotopes. If we focus only on the PET characteristics such as the spatial resolution, its accuracy depends on the design of detector and on the electronics readout system as well. In this paper, we present a new design of such readout system with full custom submicrometer CMOS implementation. The front end chip consists of two main blocks from which the energy information and the time stamp with subnanosecond resolution can be obtained. In our A Multi-Modality Imaging System for Small Animal (AMISSA) PET system design, a matrix of LYSO crystals has to be read at each end by a 64 channels multianode photomultiplier tube. A specific readout electronic has been developed at the Hubert Curien Multidisciplinary Institute (IPHC, France). The architecture of this readout for the energy information detection is composed of a low-noise preamplifier, a CR-RC shaper and an analogue memory. In order to obtain the required dynamic range from 15 to 650 photoelectrons with good linearity, a current mode approach has been chosen for the preamplifier. To detect the signal with a temporal resolution of 1 ns, a comparator with a very low threshold (˜0.3 photoelectron) has been implemented. It gives the time reference of arrival signal coming from the detector. In order to obtain the time coincidence with a temporal resolution of 1 ns, a Time-to-Digital Converter (TDC) based on a Delay-Locked-Loop (DLL) has been designed. The chip is fabricated with AMS 0.35 μm process. The ASIC architecture and some simulation results will be presented in the paper.

Gossip: Gaseous pixels

NASA Astrophysics Data System (ADS)

Koffeman, E. N.

2007-12-01

Several years ago a revolutionary miniature TPC was developed using a pixel chip with a Micromegas foil spanned over it. To overcome the mechanical stability problems and improve the positioning accuracy while spanning a foil on top of a small readout chip a process has been developed in which a Micromegas-like grid is applied on a CMOS wafer in a post-processing step. This aluminum grid is supported on insulating pillars that are created by etching after the grid has been made. The energy resolution (measured on the absorption of the X-rays from a 55Fe source) was remarkably good. Several geometries have since been tested and we now believe that a Gas On Slimmed Silicon Pixel chip' (Gossip) may be realized. The drift region of such a gaseous pixel detector would be reduced to a millimeter. Such a detector is potentially very radiation hard (SLHC vertexing) but aging and sparking must be eliminated.

The realization of an SVGA OLED-on-silicon microdisplay driving circuit

NASA Astrophysics Data System (ADS)

Bohua, Zhao; Ran, Huang; Fei, Ma; Guohua, Xie; Zhensong, Zhang; Huan, Du; Jiajun, Luo; Yi, Zhao

2012-03-01

An 800 × 600 pixel organic light-emitting diode-on-silicon (OLEDoS) driving circuit is proposed. The pixel cell circuit utilizes a subthreshold-voltage-scaling structure which can modulate the pixel current between 170 pA and 11.4 nA. In order to keep the voltage of the column bus at a relatively high level, the sample-and-hold circuits adopt a ping-pong operation. The driving circuit is fabricated in a commercially available 0.35 μm two-poly four-metal 3.3 V mixed-signal CMOS process. The pixel cell area is 15 × 15 μm2 and the total chip occupies 15.5 × 12.3 mm2. Experimental results show that the chip can work properly at a frame frequency of 60 Hz and has a 64 grayscale (monochrome) display. The total power consumption of the chip is about 85 mW with a 3.3V supply voltage.

Wavelength scanning achieves pixel super-resolution in holographic on-chip microscopy

NASA Astrophysics Data System (ADS)

Luo, Wei; Göröcs, Zoltan; Zhang, Yibo; Feizi, Alborz; Greenbaum, Alon; Ozcan, Aydogan

2016-03-01

Lensfree holographic on-chip imaging is a potent solution for high-resolution and field-portable bright-field imaging over a wide field-of-view. Previous lensfree imaging approaches utilize a pixel super-resolution technique, which relies on sub-pixel lateral displacements between the lensfree diffraction patterns and the image sensor's pixel-array, to achieve sub-micron resolution under unit magnification using state-of-the-art CMOS imager chips, commonly used in e.g., mobile-phones. Here we report, for the first time, a wavelength scanning based pixel super-resolution technique in lensfree holographic imaging. We developed an iterative super-resolution algorithm, which generates high-resolution reconstructions of the specimen from low-resolution (i.e., under-sampled) diffraction patterns recorded at multiple wavelengths within a narrow spectral range (e.g., 10-30 nm). Compared with lateral shift-based pixel super-resolution, this wavelength scanning approach does not require any physical shifts in the imaging setup, and the resolution improvement is uniform in all directions across the sensor-array. Our wavelength scanning super-resolution approach can also be integrated with multi-height and/or multi-angle on-chip imaging techniques to obtain even higher resolution reconstructions. For example, using wavelength scanning together with multi-angle illumination, we achieved a halfpitch resolution of 250 nm, corresponding to a numerical aperture of 1. In addition to pixel super-resolution, the small scanning steps in wavelength also enable us to robustly unwrap phase, revealing the specimen's optical path length in our reconstructed images. We believe that this new wavelength scanning based pixel super-resolution approach can provide competitive microscopy solutions for high-resolution and field-portable imaging needs, potentially impacting tele-pathology applications in resource-limited-settings.

Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

NASA Astrophysics Data System (ADS)

Kremastiotis, I.; Ballabriga, R.; Campbell, M.; Dannheim, D.; Fiergolski, A.; Hynds, D.; Kulis, S.; Peric, I.

2017-09-01

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial 180 nm HV-CMOS process and contains a matrix of 128×128 square pixels with 25μm pitch. First prototypes have been produced with a standard resistivity of ~20 Ωcm for the substrate and tested in standalone mode. The results show a rise time of ~20 ns, charge gain of 190 mV/ke- and ~40 e- RMS noise for a power consumption of 4.8μW/pixel. The main design aspects, as well as standalone measurement results, are presented.

Design methodology: edgeless 3D ASICs with complex in-pixel processing for pixel detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fahim Farah, Fahim Farah; Deptuch, Grzegorz W.; Hoff, James R.

The design methodology for the development of 3D integrated edgeless pixel detectors with in-pixel processing using Electronic Design Automation (EDA) tools is presented. A large area 3 tier 3D detector with one sensor layer and two ASIC layers containing one analog and one digital tier, is built for x-ray photon time of arrival measurement and imaging. A full custom analog pixel is 65μm x 65μm. It is connected to a sensor pixel of the same size on one side, and on the other side it has approximately 40 connections to the digital pixel. A 32 x 32 edgeless array withoutmore » any peripheral functional blocks constitutes a sub-chip. The sub-chip is an indivisible unit, which is further arranged in a 6 x 6 array to create the entire 1.248cm x 1.248cm ASIC. Each chip has 720 bump-bond I/O connections, on the back of the digital tier to the ceramic PCB. All the analog tier power and biasing is conveyed through the digital tier from the PCB. The assembly has no peripheral functional blocks, and hence the active area extends to the edge of the detector. This was achieved by using a few flavors of almost identical analog pixels (minimal variation in layout) to allow for peripheral biasing blocks to be placed within pixels. The 1024 pixels within a digital sub-chip array have a variety of full custom, semi-custom and automated timing driven functional blocks placed together. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout. The methodology uses the Cadence design platform, however it is not limited to this tool.« less

Design methodology: edgeless 3D ASICs with complex in-pixel processing for pixel detectors

NASA Astrophysics Data System (ADS)

Fahim, Farah; Deptuch, Grzegorz W.; Hoff, James R.; Mohseni, Hooman

2015-08-01

The design methodology for the development of 3D integrated edgeless pixel detectors with in-pixel processing using Electronic Design Automation (EDA) tools is presented. A large area 3 tier 3D detector with one sensor layer and two ASIC layers containing one analog and one digital tier, is built for x-ray photon time of arrival measurement and imaging. A full custom analog pixel is 65μm x 65μm. It is connected to a sensor pixel of the same size on one side, and on the other side it has approximately 40 connections to the digital pixel. A 32 x 32 edgeless array without any peripheral functional blocks constitutes a sub-chip. The sub-chip is an indivisible unit, which is further arranged in a 6 x 6 array to create the entire 1.248cm x 1.248cm ASIC. Each chip has 720 bump-bond I/O connections, on the back of the digital tier to the ceramic PCB. All the analog tier power and biasing is conveyed through the digital tier from the PCB. The assembly has no peripheral functional blocks, and hence the active area extends to the edge of the detector. This was achieved by using a few flavors of almost identical analog pixels (minimal variation in layout) to allow for peripheral biasing blocks to be placed within pixels. The 1024 pixels within a digital sub-chip array have a variety of full custom, semi-custom and automated timing driven functional blocks placed together. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout. The methodology uses the Cadence design platform, however it is not limited to this tool.

Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

NASA Technical Reports Server (NTRS)

Fossum, E.; Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Zhou, Z.;

Mega-pixel PQR laser chips for interconnect, display ITS, and biocell-tweezers OEIC

NASA Astrophysics Data System (ADS)

Kwon, O'Dae; Yoon, J. H.; Kim, D. K.; Kim, Y. C.; Lee, S. E.; Kim, S. S.

2008-02-01

We describe a photonic quantum ring (PQR) laser device of three dimensional toroidal whispering gallery cavity. We have succeeded in fabricating the first genuine mega-pixel laser chips via regular semiconductor technology. This has been realized since the present injection laser emitting surface-normal dominant 3D whispering gallery modes (WGMs) can be operated CW with extremely low operating currents (μA-nA per pixel), together with the lasing temperature stabilities well above 140 deg C with minimal redshifts, which solves the well-known integration problems facing the conventional VCSEL. Such properties unusual for quantum well lasers become usual because the active region, involving vertically confining DBR structure in addition to the 2D concave WGM geometry, induces a 'photonic quantum ring (PQR)-like' carrier distribution through a photonic quantum corral effect. A few applications of such mega-pixel PQR chips are explained as follows: (A) Next-generation 3D semiconductor technologies demand a strategy on the inter-chip and intra-chip optical interconnect schemes with a key to the high-density emitter array. (B) Due to mounting traffic problems and fatalities ITS technology today is looking for a revolutionary change in the technology. We will thus outline how 'SLEEP-ITS' can emerge with the PQR's position-sensing capability. (C) We describe a recent PQR 'hole' laser of convex WGM: Mega-pixel PQR 'hole' laser chips are even easier to fabricate than PQR 'mesa' lasers. Genuine Laguerre-Gaussian (LG) beam patterns of PQR holes are very promising for biocell manipulations like sorting mouse myeloid leukemia (M1s) cells. (D) Energy saving and 3D speckle-free POR laser can outdo LEDs in view of red GaAs and blue GaN devices fabricated recently.

A low-power CMOS operational amplifier IC for a heterogeneous paper-based potentiostat

NASA Astrophysics Data System (ADS)

Bezuidenhout, P.; Land, K.; Joubert, T.-H.

2016-02-01

Electrochemical biosensing is used to detect specific analytes in fluids, such as bacterial and chemical contaminants. A common implementation of an electrochemical readout is a potentiostat, which usually includes potentiometric, amperometric, and impedimetric detection. Recently several researchers have developed small, low-cost, single-chip silicon-based potentiostats. With the advances in heterogeneous integration technology, low-power potentiostats can be implemented on paper and similar low cost substrates. This paper deals with the design of a low-power paper-based amperometric front-end for a low-cost and rapid detection environment. In amperometric detection a voltage signal is provided to a sensor system, while a small current value generated by an electrochemical redox reaction in the system is measured. In order to measure low current values, the noise of the circuit must be minimized, which is accomplished with a pre-amplification front-end stage, typically designed around an operational amplifier core. An appropriate circuit design for a low-power and low-cost amperometric front-end is identified, taking the heterogeneous integration of various components into account. The operational amplifier core is on a bare custom CMOS chip, which will be integrated onto the paper substrate alongside commercial off-the-shelf electronic components. A general-purpose low-power two-stage CMOS amplifier circuit is designed and simulated for the ams 350 nm 5 V process. After the layout design and verification, the IC was submitted for a multi-project wafer manufacturing run. The simulated results are a bandwidth of 2.4 MHz, a common-mode rejection ratio of 70.04 dB, and power dissipation of 0.154 mW, which are comparable with the analytical values.

CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology

NASA Technical Reports Server (NTRS)

Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

2006-01-01

This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

A microfluidic microprocessor: controlling biomimetic containers and cells using hybrid integrated circuit/microfluidic chips.

PubMed

Issadore, David; Franke, Thomas; Brown, Keith A; Westervelt, Robert M

2010-11-07

We present an integrated platform for performing biological and chemical experiments on a chip based on standard CMOS technology. We have developed a hybrid integrated circuit (IC)/microfluidic chip that can simultaneously control thousands of living cells and pL volumes of fluid, enabling a wide variety of chemical and biological tasks. Taking inspiration from cellular biology, phospholipid bilayer vesicles are used as robust picolitre containers for reagents on the chip. The hybrid chip can be programmed to trap, move, and porate individual living cells and vesicles and fuse and deform vesicles using electric fields. The IC spatially patterns electric fields in a microfluidic chamber using 128 × 256 (32,768) 11 × 11 μm(2) metal pixels, each of which can be individually driven with a radio frequency (RF) voltage. The chip's basic functions can be combined in series to perform complex biological and chemical tasks and can be performed in parallel on the chip's many pixels for high-throughput operations. The hybrid chip operates in two distinct modes, defined by the frequency of the RF voltage applied to the pixels: Voltages at MHz frequencies are used to trap, move, and deform objects using dielectrophoresis and voltages at frequencies below 1 kHz are used for electroporation and electrofusion. This work represents an important step towards miniaturizing the complex chemical and biological experiments used for diagnostics and research onto automated and inexpensive chips.

Pixel super resolution using wavelength scanning

DTIC Science & Technology

2016-04-08

the light source is adjusted to ~20 μW. The image sensor chip is a color CMOS sensor chip with a pixel size of 1.12 μm manufactured for cellphone...pitch (that is, ~ 1 μm in Figure 3a, using a CMOS sensor that has a 1.12-μm pixel pitch). For the same configuration depicted in Figure 3, utilizing...section). The a Lens-free raw holograms captured by 1.12 μm CMOS image sensor Field of view ≈ 20.5 mm2 Angle change directions for synthetic aperture

Chip-scale fluorescence microscope based on a silo-filter complementary metal-oxide semiconductor image sensor.

PubMed

Ah Lee, Seung; Ou, Xiaoze; Lee, J Eugene; Yang, Changhuei

2013-06-01

We demonstrate a silo-filter (SF) complementary metal-oxide semiconductor (CMOS) image sensor for a chip-scale fluorescence microscope. The extruded pixel design with metal walls between neighboring pixels guides fluorescence emission through the thick absorptive filter to the photodiode of a pixel. Our prototype device achieves 13 μm resolution over a wide field of view (4.8 mm × 4.4 mm). We demonstrate bright-field and fluorescence longitudinal imaging of living cells in a compact, low-cost configuration.

Low Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

A second generation image sensor technology has been developed at the NASA Jet Propulsion Laboratory as a result of the continuing need to miniaturize space science imaging instruments. Implemented using standard CMOS, the active pixel sensor (APS) technology permits the integration of the detector array with on-chip timing, control and signal chain electronics, including analog-to-digital conversion.

Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications.

PubMed

Tokuda, Takashi; Noda, Toshihiko; Sasagawa, Kiyotaka; Ohta, Jun

2010-12-29

In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS) image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors' architecture on the basis of the type of electric measurement or imaging functionalities.

Single chip camera active pixel sensor

NASA Technical Reports Server (NTRS)

Shaw, Timothy (Inventor); Pain, Bedabrata (Inventor); Olson, Brita (Inventor); Nixon, Robert H. (Inventor); Fossum, Eric R. (Inventor); Panicacci, Roger A. (Inventor); Mansoorian, Barmak (Inventor)

2003-01-01

A totally digital single chip camera includes communications to operate most of its structure in serial communication mode. The digital single chip camera include a D/A converter for converting an input digital word into an analog reference signal. The chip includes all of the necessary circuitry for operating the chip using a single pin.

A CMOS Front-End With Integrated Magnetoresistive Sensors for Biomolecular Recognition Detection Applications.

PubMed

Costa, Tiago; Cardoso, Filipe A; Germano, Jose; Freitas, Paulo P; Piedade, Moises S

2017-10-01

The development of giant magnetoresistive (GMR) sensors has demonstrated significant advantages in nanomedicine, particularly for ultrasensitive point-of-care diagnostics. To this end, the detection system is required to be compact, portable, and low power consuming at the same time that a maximum signal to noise ratio is maintained. This paper reports a CMOS front-end with integrated magnetoresistive sensors for biomolecular recognition detection applications. Based on the characterization of the GMR sensor's signal and noise, CMOS building blocks (i.e., current source, multiplexers, and preamplifier) were designed targeting a negligible noise when compared with the GMR sensor's noise and a low power consumption. The CMOS front-end was fabricated using AMS [Formula: see text] technology and the magnetoresistive sensors were post-fabricated on top of the CMOS chip with high yield ( [Formula: see text]). Due to its low circuit noise (16 [Formula: see text]) and overall equivalent magnetic noise ([Formula: see text]), the full system was able to detect 250 nm magnetic nanoparticles with a circuit imposed signal-to-noise ratio degradation of only -1.4 dB. Furthermore, the low power consumption (6.5 mW) and small dimensions ([Formula: see text] ) of the presented solution guarantees the portability of the detection system allowing its usage at the point-of-care.

The charge pump PLL clock generator designed for the 1.56 ns bin size time-to-digital converter pixel array of the Timepix3 readout ASIC

NASA Astrophysics Data System (ADS)

Fu, Y.; Brezina, C.; Desch, K.; Poikela, T.; Llopart, X.; Campbell, M.; Massimiliano, D.; Gromov, V.; Kluit, R.; van Beauzekom, M.; Zappon, F.; Zivkovic, V.

2014-01-01

Timepix3 is a newly developed pixel readout chip which is expected to be operated in a wide range of gaseous and silicon detectors. It is made of 256 × 256 pixels organized in a square pixel-array with 55 μm pitch. Oscillators running at 640 MHz are distributed across the pixel-array and allow for a highly accurate measurement of the arrival time of a hit. This paper concentrates on a low-jitter phase locked loop (PLL) that is located in the chip periphery. This PLL provides a control voltage which regulates the actual frequency of the individual oscillators, allowing for compensation of process, voltage, and temperature variations.

Tests of UFXC32k chip with CdTe pixel detector

NASA Astrophysics Data System (ADS)

Maj, P.; Taguchi, T.; Nakaye, Y.

2018-02-01

The paper presents the performance of the UFXC32K—a hybrid pixel detector readout chip working with CdTe detectors. The UFXC32K has a pixel pitch of 75 μm and can cope with both input signal polarities. This functionality allows operating with widely used silicon sensors collecting holes and CdTe sensors collecting electrons. This article describes the chip focusing on solving the issues connected to high-Z sensor material, namely high leakage currents, slow charge collection time and thick material resulting in increased charge-sharring effects. The measurements were conducted with higher X-ray energies including 17.4 keV from molybdenum. Conclusions drawn inside the paper show the UFXC32K's usability for CdTe sensors in high X-ray energy applications.

Ultra-fast high-resolution hybrid and monolithic CMOS imagers in multi-frame radiography

NASA Astrophysics Data System (ADS)

Kwiatkowski, Kris; Douence, Vincent; Bai, Yibin; Nedrow, Paul; Mariam, Fesseha; Merrill, Frank; Morris, Christopher L.; Saunders, Andy

2014-09-01

A new burst-mode, 10-frame, hybrid Si-sensor/CMOS-ROIC FPA chip has been recently fabricated at Teledyne Imaging Sensors. The intended primary use of the sensor is in the multi-frame 800 MeV proton radiography at LANL. The basic part of the hybrid is a large (48×49 mm2) stitched CMOS chip of 1100×1100 pixel count, with a minimum shutter speed of 50 ns. The performance parameters of this chip are compared to the first generation 3-frame 0.5-Mpixel custom hybrid imager. The 3-frame cameras have been in continuous use for many years, in a variety of static and dynamic experiments at LANSCE. The cameras can operate with a per-frame adjustable integration time of ~ 120ns-to- 1s, and inter-frame time of 250ns to 2s. Given the 80 ms total readout time, the original and the new imagers can be externally synchronized to 0.1-to-5 Hz, 50-ns wide proton beam pulses, and record up to ~1000-frame radiographic movies typ. of 3-to-30 minute duration. The performance of the global electronic shutter is discussed and compared to that of a high-resolution commercial front-illuminated monolithic CMOS imager.

SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades

NASA Astrophysics Data System (ADS)

Adolfsson, J.; Ayala Pabon, A.; Bregant, M.; Britton, C.; Brulin, G.; Carvalho, D.; Chambert, V.; Chinellato, D.; Espagnon, B.; Hernandez Herrera, H. D.; Ljubicic, T.; Mahmood, S. M.; Mjörnmark, U.; Moraes, D.; Munhoz, M. G.; Noël, G.; Oskarsson, A.; Osterman, L.; Pilyar, A.; Read, K.; Ruette, A.; Russo, P.; Sanches, B. C. S.; Severo, L.; Silvermyr, D.; Suire, C.; Tambave, G. J.; Tun-Lanoë, K. M. M.; van Noije, W.; Velure, A.; Vereschagin, S.; Wanlin, E.; Weber, T. O.; Zaporozhets, S.

2017-04-01

This paper presents the test results of the second prototype of SAMPA, the ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chamber (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply and provides 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel consists of a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC; a Digital Signal Processor provides digital filtering and compression capability. In the second prototype run both full chip and single test blocks were fabricated, allowing block characterization and full system behaviour studies. Experimental results are here presented showing agreement with requirements for both the blocks and the full chip.

Automated Inspection of Defects in Optical Fiber Connector End Face Using Novel Morphology Approaches.

PubMed

Mei, Shuang; Wang, Yudan; Wen, Guojun; Hu, Yang

2018-05-03

Increasing deployment of optical fiber networks and the need for reliable high bandwidth make the task of inspecting optical fiber connector end faces a crucial process that must not be neglected. Traditional end face inspections are usually performed by manual visual methods, which are low in efficiency and poor in precision for long-term industrial applications. More seriously, the inspection results cannot be quantified for subsequent analysis. Aiming at the characteristics of typical defects in the inspection process for optical fiber end faces, we propose a novel method, “difference of min-max ranking filtering” (DO2MR), for detection of region-based defects, e.g., dirt, oil, contamination, pits, and chips, and a special model, a “linear enhancement inspector” (LEI), for the detection of scratches. The DO2MR is a morphology method that intends to determine whether a pixel belongs to a defective region by comparing the difference of gray values of pixels in the neighborhood around the pixel. The LEI is also a morphology method that is designed to search for scratches at different orientations with a special linear detector. These two approaches can be easily integrated into optical inspection equipment for automatic quality verification. As far as we know, this is the first time that complete defect detection methods for optical fiber end faces are available in the literature. Experimental results demonstrate that the proposed DO2MR and LEI models yield good comprehensive performance with high precision and accepted recall rates, and the image-level detection accuracies reach 96.0 and 89.3%, respectively.

Characterization of the ePix100 prototype: a front-end ASIC for second-generation LCLS integrating hybrid pixel detectors

NASA Astrophysics Data System (ADS)

Caragiulo, P.; Dragone, A.; Markovic, B.; Herbst, R.; Nishimura, K.; Reese, B.; Herrmann, S.; Hart, P.; Blaj, G.; Segal, J.; Tomada, A.; Hasi, J.; Carini, G.; Kenney, C.; Haller, G.

2014-09-01

ePix100 is the first variant of a novel class of integrating pixel ASICs architectures optimized for the processing of signals in second generation LINAC Coherent Light Source (LCLS) X-Ray cameras. ePix100 is optimized for ultra-low noise application requiring high spatial resolution. ePix ASICs are based on a common platform composed of a random access analog matrix of pixel with global shutter, fast parallel column readout, and dedicated sigma-delta analog to digital converters per column. The ePix100 variant has 50μmx50μm pixels arranged in a 352x384 matrix, a resolution of 50e- r.m.s. and a signal range of 35fC (100 photons at 8keV). In its final version it will be able to sustain a frame rate of 1kHz. A first prototype has been fabricated and characterized and the measurement results are reported here.

1024-Pixel CMOS Multimodality Joint Cellular Sensor/Stimulator Array for Real-Time Holistic Cellular Characterization and Cell-Based Drug Screening.

PubMed

Park, Jong Seok; Aziz, Moez Karim; Li, Sensen; Chi, Taiyun; Grijalva, Sandra Ivonne; Sung, Jung Hoon; Cho, Hee Cheol; Wang, Hua

2018-02-01

This paper presents a fully integrated CMOS multimodality joint sensor/stimulator array with 1024 pixels for real-time holistic cellular characterization and drug screening. The proposed system consists of four pixel groups and four parallel signal-conditioning blocks. Every pixel group contains 16 × 16 pixels, and each pixel includes one gold-plated electrode, four photodiodes, and in-pixel circuits, within a pixel footprint. Each pixel supports real-time extracellular potential recording, optical detection, charge-balanced biphasic current stimulation, and cellular impedance measurement for the same cellular sample. The proposed system is fabricated in a standard 130-nm CMOS process. Rat cardiomyocytes are successfully cultured on-chip. Measured high-resolution optical opacity images, extracellular potential recordings, biphasic current stimulations, and cellular impedance images demonstrate the unique advantages of the system for holistic cell characterization and drug screening. Furthermore, this paper demonstrates the use of optical detection on the on-chip cultured cardiomyocytes to real-time track their cyclic beating pattern and beating rate.

Buried plastic scintillator muon telescope

NASA Astrophysics Data System (ADS)

Sanchez, F.; Medina-Tanco, G.A.; D'Olivo, J.C.; Paic, G.; Patino Salazar, M.E.; Nahmad-Achar, E.; Valdes Galicia, J.F.; Sandoval, A.; Alfaro Molina, R.; Salazar Ibarguen, H.; Diozcora Vargas Trevino, M.A.; Vergara Limon, S.; Villasenor, L.M.

Muon telescopes can have several applications, ranging from astrophysical to solar-terrestrial interaction studies, and fundamental particle physics. We show the design parameters, characterization and end-to-end simulations of a detector composed by a set of three parallel dual-layer scintillator planes, buried at fix depths ranging from 0.30 m to 3 m. Each layer is 4 m2 and is composed by 50 rectangular pixels of 4cm x 2 m, oriented at a 90 deg angle with respect to its companion layer. The scintillators are MINOS extruded polystyrene strips with two Bicron wavelength shifting fibers mounted on machined grooves. Scintillation light is collected by multi-anode PMTs of 64 pixels, accommodating two fibers per pixel. The front-end electronics has a time resolution of 7.5 nsec. Any strip signal above threshold opens a GPS-tagged 2 micro-seconds data collection window. All data, including signal and background, are saved to hard disk. Separation of extensive air shower signals from secondary cosmic-ray background muons and electrons is done offline using the GPS-tagged threefold coincidence signal from surface water cerenkov detectors located nearby in a triangular array. Cosmic-ray showers above 6 PeV are selected. The data acquisition system is designed to keep both, background and signals from extensive air showers for a detailed offline data.

Proof of concept of an imaging system demonstrator for PET applications with SiPM

NASA Astrophysics Data System (ADS)

Morrocchi, Matteo; Marcatili, Sara; Belcari, Nicola; Giuseppina Bisogni, Maria; Collazuol, Gianmaria; Ambrosi, Giovanni; Santoni, Cristiano; Corsi, Francesco; Foresta, Maurizio; Marzocca, Cristoforo; Matarrese, Gianvito; Sportelli, Giancarlo; Guerra, Pedro; Santos, Andres; Del Guerra, Alberto

2013-08-01

A PET imaging system demonstrator based on LYSO crystal arrays coupled to SiPM matrices is under construction at the University and INFN of Pisa. Two SiPM matrices, composed of 8×8 SiPM pixels, and 1,5 mm pitch, have been coupled one to one to a LYSO crystals array and read out by a custom electronics system. front-end ASICs were used to read 8 channels of each matrix. Data from each front-end were multiplexed and sent to a DAQ board for the digital conversion; a motherboard collects the data and communicates with a host computer through a USB port for the storage and off-line data processing. In this paper we show the first preliminary tomographic image of a point-like radioactive source acquired with part of the two detection heads in time coincidence.

Design and demonstration of ultra-fast W-band photonic transmitter-mixer and detectors for 25 Gbits/sec error-free wireless linking.

PubMed

Chen, Nan-Wei; Shi, Jin-Wei; Tsai, Hsuan-Ju; Wun, Jhih-Min; Kuo, Fong-Ming; Hesler, Jeffery; Crowe, Thomas W; Bowers, John E

2012-09-10

A 25 Gbits/s error-free on-off-keying (OOK) wireless link between an ultra high-speed W-band photonic transmitter-mixer (PTM) and a fast W-band envelope detector is demonstrated. At the transmission end, the high-speed PTM is developed with an active near-ballistic uni-traveling carrier photodiode (NBUTC-PD) integrated with broadband front-end circuitry via the flip-chip bonding technique. Compared to our previous work, the wireless data rate is significantly increased through the improvement on the bandwidth of the front-end circuitry together with the reduction of the intermediate-frequency (IF) driving voltage of the active NBUTC-PD. The demonstrated PTM has a record-wide IF modulation (DC-25 GHz) and optical-to-electrical fractional bandwidths (68-128 GHz, ~67%). At the receiver end, the demodulation is realized with an ultra-fast W-band envelope detector built with a zero-bias Schottky barrier diode with a record wide video bandwidth (37 GHz) and excellent sensitivity. The demonstrated PTM is expected to find applications in multi-gigabit short-range wireless communication.

Simulation and Measurement of Absorbed Dose from 137 Cs Gammas Using a Si Timepix Detector

NASA Technical Reports Server (NTRS)

Stoffle, Nicholas; Pinsky, Lawrence; Empl, Anton; Semones, Edward

2011-01-01

The TimePix readout chip is a hybrid pixel detector with over 65k independent pixel elements. Each pixel contains its own circuitry for charge collection, counting logic, and readout. When coupled with a Silicon detector layer, the Timepix chip is capable of measuring the charge, and thus energy, deposited in the Silicon. Measurements using a NIST traceable 137Cs gamma source have been made at Johnson Space Center using such a Si Timepix detector, and this data is compared to simulations of energy deposition in the Si layer carried out using FLUKA.

Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

PubMed Central

Tokuda, Takashi; Noda, Toshihiko; Sasagawa, Kiyotaka; Ohta, Jun

2010-01-01

In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS) image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities. PMID:28879978

A pixel read-out architecture implementing a two-stage token ring, zero suppression and compression

NASA Astrophysics Data System (ADS)

Heuvelmans, S.; Boerrigter, M.

2011-01-01

Increasing luminosity in high energy physics experiments leads to new challenges in the design of data acquisition systems for pixel detectors. With the upgrade of the LHCb experiment, the data processing will be changed; hit data from every collision will be transported off the pixel chip, without any trigger selection. A read-out architecture is proposed which is able to obtain low hit data loss on limited silicon area by using the logic beneath the pixels as a data buffer. Zero suppression and redundancy reduction ensure that the data rate off chip is minimized. A C++ model has been created for simulation of functionality and data loss, and for system development. A VHDL implementation has been derived from this model.

A low power low noise analog front end for portable healthcare system

NASA Astrophysics Data System (ADS)

Yanchao, Wang; Keren, Ke; Wenhui, Qin; Yajie, Qin; Ting, Yi; Zhiliang, Hong

2015-10-01

The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5-100 Hz) and the achieved noise efficient factor is 6.48. Project supported by the Science and Technology Commission of Shanghai Municipality (No. 13511501100), the State Key Laboratory Project of China (No. 11MS002), and the State Key Laboratory of ASIC & System, Fudan University.

Camera-on-a-Chip

NASA Technical Reports Server (NTRS)

1999-01-01

Jet Propulsion Laboratory's research on a second generation, solid-state image sensor technology has resulted in the Complementary Metal- Oxide Semiconductor Active Pixel Sensor (CMOS), establishing an alternative to the Charged Coupled Device (CCD). Photobit Corporation, the leading supplier of CMOS image sensors, has commercialized two products of their own based on this technology: the PB-100 and PB-300. These devices are cameras on a chip, combining all camera functions. CMOS "active-pixel" digital image sensors offer several advantages over CCDs, a technology used in video and still-camera applications for 30 years. The CMOS sensors draw less energy, they use the same manufacturing platform as most microprocessors and memory chips, and they allow on-chip programming of frame size, exposure, and other parameters.

Radiation Hardening of Digital Color CMOS Camera-on-a-Chip Building Blocks for Multi-MGy Total Ionizing Dose Environments

NASA Astrophysics Data System (ADS)

Goiffon, Vincent; Rolando, Sébastien; Corbière, Franck; Rizzolo, Serena; Chabane, Aziouz; Girard, Sylvain; Baer, Jérémy; Estribeau, Magali; Magnan, Pierre; Paillet, Philippe; Van Uffelen, Marco; Mont Casellas, Laura; Scott, Robin; Gaillardin, Marc; Marcandella, Claude; Marcelot, Olivier; Allanche, Timothé

2017-01-01

The Total Ionizing Dose (TID) hardness of digital color Camera-on-a-Chip (CoC) building blocks is explored in the Multi-MGy range using 60Co gamma-ray irradiations. The performances of the following CoC subcomponents are studied: radiation hardened (RH) pixel and photodiode designs, RH readout chain, Color Filter Arrays (CFA) and column RH Analog-to-Digital Converters (ADC). Several radiation hardness improvements are reported (on the readout chain and on dark current). CFAs and ADCs degradations appear to be very weak at the maximum TID of 6 MGy(SiO2), 600 Mrad. In the end, this study demonstrates the feasibility of a MGy rad-hard CMOS color digital camera-on-a-chip, illustrated by a color image captured after 6 MGy(SiO2) with no obvious degradation. An original dark current reduction mechanism in irradiated CMOS Image Sensors is also reported and discussed.

SVGA and XGA LCOS microdisplays for HMD applications

NASA Astrophysics Data System (ADS)

Bolotski, Michael; Alvelda, Phillip

1999-07-01

MicroDisplay liquid crystal on silicon (LCOS) display devices are based on a combination of technologies combined with the extreme integration capability of conventionally fabricated CMOS substrates. Two recent SVGA (800 X 600) pixel resolution designs were demonstrated based on 10 micron and 12.5-micron pixel pitch architectures. The resulting microdisplays measure approximately 10 mm and 12 mm in diagonal respectively. Further, an XGA (1024 X 768) resolution display fabricated with a 12.5-micron pixel pitch with a 16-mm diagonal was also demonstrated. Both the larger SVGA and the XGA design were based on the same 12.5-micron pixel-pitch design, demonstrating a quickly scalable design architecture for rapid prototyping life-cycles. All three microdisplay designs described above function in grayscale and high-performance Field-Sequential-Color (FSC) operating modes. The fast liquid crystal operating modes and new scalable high- performance pixel addressing architectures presented in this paper enable substantially improved color, contrast, and brightness while still satisfying the optical, packaging, and power requirements of portable commercial and defense applications including ultra-portable helmet, eyeglass, and heat-mounted systems. The entire suite of The MicroDisplay Corporation's technologies was devised to create a line of mixed-signal application-specific integrated circuits (ASIC) in single-chip display systems. Mixed-signal circuits can integrate computing, memory, and communication circuitry on the same substrate as the display drivers and pixel array for a multifunctional complete system-on-a-chip. For helmet and head-mounted displays this can include capabilities such as the incorporation of customized symbology and information storage directly on the display substrate. System-on-a-chip benefits also include reduced head supported weight requirements through the elimination of off-chip drive electronics.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the first six months of this project were to lay the foundations for both the SiC front-end optical chip fabrication as well as the free-space laser beam interferometer designs and preliminary tests. In addition, a Phase I goal was to design and experimentally build the high temperature and pressure infrastructure and test systems that will be used in the next 6 months for proposed sensor experimentation and data processing. All these goals have been achieved and are described in detail in the report. Both design process and diagrams for the mechanical elements as well as the opticalmore » systems are provided. In addition, photographs of the fabricated SiC optical chips, the high temperature & pressure test chamber instrument, the optical interferometer, the SiC sample chip holder, and signal processing data are provided. The design and experimentation results are summarized to give positive conclusions on the proposed novel high temperature optical sensor technology.« less

A 30 GHz monolithic receive module technology assessment

NASA Technical Reports Server (NTRS)

Geddes, J.; Sokolov, V.; Bauhahn, P.; Contolatis, T.

1988-01-01

This report is a technology assessment relevant to the 30 GHz Monolithic Receive Module development. It is based on results obtained on the present NASA Contract (NAS3-23356) as well as on information gathered from literature and other industry sources. To date the on-going Honeywell program has concentrated on demonstrating the so-called interconnected receive module which consists of four monolithic chips - the low noise front-end amplifier (LNA), the five bit phase shifter (PS), the gain control amplifier (GC), and the RF to IF downconverter (RF/IF). Results on all four individual chips have been obtained and interconnection of the first three functions has been accomplished. Future work on this contract is aimed at a higher level of integration, i.e., integration of the first three functions (LNA + PS + GC) on a single GaAs chip. The report presents the status of this technology and projections of its future directions.

MuTRiG: a mixed signal Silicon Photomultiplier readout ASIC with high timing resolution and gigabit data link

NASA Astrophysics Data System (ADS)

Chen, H.; Briggl, K.; Eckert, P.; Harion, T.; Munwes, Y.; Shen, W.; Stankova, V.; Schultz-Coulon, H. C.

2017-01-01

MuTRiG is a mixed signal Silicon Photomultiplier readout ASIC designed in UMC 180 nm CMOS technology for precise timing and high event rate applications in high energy physics experiments and medical imaging. It is dedicated to the readout of the scintillating fiber detector and the scintillating tile detector of the Mu3e experiment. The MuTRiG chip extends the excellent timing performance of the STiCv3 chip with a fast digital readout for high rate applications. The high timing performance of the fully differential SiPM readout channels and 50 ps time binning TDCs are complemented by an upgraded digital readout logic and a 1.28 Gbps LVDS serial data link. The design of the chip and the characterization results of the analog front-end, TDC and the LVDS data link are presented.

Implementation of the Timepix ASIC in the Scalable Readout System

NASA Astrophysics Data System (ADS)

Lupberger, M.; Desch, K.; Kaminski, J.

2016-09-01

We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

Design of 90×8 ROIC with pixel level digital TDI implementation for scanning type LWIR FPAs

NASA Astrophysics Data System (ADS)

Ceylan, Omer; Kayahan, Huseyin; Yazici, Melik; Gurbuz, Yasar

2013-06-01

Design of a 90×8 CMOS readout integrated circuit (ROIC) based on pixel level digital time delay integration (TDI) for scanning type LWIR focal plane arrays (FPAs) is presented. TDI is implemented on 8 pixels which improves the SNR of the system with a factor of √8. Oversampling rate of 3 improves the spatial resolution of the system. TDI operation is realized with a novel under-pixel analog-to-digital converter, which improves the noise performance of ROIC with a lower quantization noise. Since analog signal is converted to digital domain in-pixel, non-uniformities and inaccuracies due to analog signal routing over large chip area is eliminated. Contributions of each pixel for proper TDI operation are added in summation counters, no op-amps are used for summation, hence power consumption of ROIC is lower than its analog counterparts. Due to lack of multiple capacitors or summation amplifiers, ROIC occupies smaller chip area compared to its analog counterparts. ROIC is also superior to its digital counterparts due to novel digital TDI implementation in terms of power consumption, noise and chip area. ROIC supports bi-directional scan, multiple gain settings, bypass operation, automatic gain adjustment, pixel select/deselect, and is programmable through serial or parallel interface. Input referred noise of ROIC is less than 750 rms electrons, while power consumption is less than 20mW. ROIC is designed to perform both in room and cryogenic temperatures.

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

NASA Astrophysics Data System (ADS)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Prototype of a gigabit data transmitter in 65 nm CMOS for DEPFET pixel detectors at Belle-II

NASA Astrophysics Data System (ADS)

Kishishita, T.; Krüger, H.; Hemperek, T.; Lemarenko, M.; Koch, M.; Gronewald, M.; Wermes, N.

2013-08-01

This paper describes the recent development of a gigabit data transmitter for the Belle-II pixel detector (PXD). The PXD is an innermost detector currently under development for the upgraded KEK-B factory in Japan. The PXD consists of two layers of DEPFET sensor modules located at 1.8 and 2.2 cm radii. Each module is equipped with three different ASIC types mounted on the detector substrate with a flip-chip technique: (a) SWITCHER for generating steering signals for the DEPFET sensors, (b) DCD for digitizing the signal currents, and (c) DHP for performing data processing and sending the data off the module to the back-end data handling hybrid via ∼ 40 cm Kapton flex and 12-15 m twisted pair (TWP) cables. To meet the requirements of the PXD data transmission, a prototype of the DHP data transmitter has been developed in a 65-nm standard CMOS technology. The transmitter test chip consists of current-mode logic (CML) drivers and a phase-locked loop (PLL) which generates a clock signal for a 1.6 Gbit/s output data stream from an 80 cm reference clock. A programmable pre-emphasis circuit is also implemented in the CML driver to compensate signal losses in the long cable by shaping the transmitted pulse response. The jitter performance was measured as 25 ps (1 σ distribution) by connecting the chip with 38 cm flex and 10 m TWP cables.

Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

NASA Astrophysics Data System (ADS)

Zeng, Huiming; Wei, Tingcun; Wang, Jia

2017-03-01

A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal-oxide-semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 μm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e-+16.3e-/pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

Detector Sampling of Optical/IR Spectra: How Many Pixels per FWHM?

NASA Astrophysics Data System (ADS)

Robertson, J. Gordon

2017-08-01

Most optical and IR spectra are now acquired using detectors with finite-width pixels in a square array. Each pixel records the received intensity integrated over its own area, and pixels are separated by the array pitch. This paper examines the effects of such pixellation, using computed simulations to illustrate the effects which most concern the astronomer end-user. It is shown that coarse sampling increases the random noise errors in wavelength by typically 10-20 % at 2 pixels per Full Width at Half Maximum, but with wide variation depending on the functional form of the instrumental Line Spread Function (i.e. the instrumental response to a monochromatic input) and on the pixel phase. If line widths are determined, they are even more strongly affected at low sampling frequencies. However, the noise in fitted peak amplitudes is minimally affected by pixellation, with increases less than about 5%. Pixellation has a substantial but complex effect on the ability to see a relative minimum between two closely spaced peaks (or relative maximum between two absorption lines). The consistent scale of resolving power presented by Robertson to overcome the inadequacy of the Full Width at Half Maximum as a resolution measure is here extended to cover pixellated spectra. The systematic bias errors in wavelength introduced by pixellation, independent of signal/noise ratio, are examined. While they may be negligible for smooth well-sampled symmetric Line Spread Functions, they are very sensitive to asymmetry and high spatial frequency sub-structure. The Modulation Transfer Function for sampled data is shown to give a useful indication of the extent of improperly sampled signal in an Line Spread Function. The common maxim that 2 pixels per Full Width at Half Maximum is the Nyquist limit is incorrect and most Line Spread Functions will exhibit some aliasing at this sample frequency. While 2 pixels per Full Width at Half Maximum is nevertheless often an acceptable minimum for moderate signal/noise work, it is preferable to carry out simulations for any actual or proposed Line Spread Function to find the effects of various sampling frequencies. Where spectrograph end-users have a choice of sampling frequencies, through on-chip binning and/or spectrograph configurations, it is desirable that the instrument user manual should include an examination of the effects of the various choices.

The Zero-Degree Detector System

NASA Technical Reports Server (NTRS)

Adams, James H.; Christl, Mark J.; Howell, Leonard W.; Kouznetsov, Evgueni

2006-01-01

We will report on a detector system used for accelerator measurement of nuclear fragmentation cross sections. This system consists of two detector planes, each carrying a ring of 8 detectors. Each detector has 64 pads. These two detector planes are arranged facing each other so that the matching detector pads on each plane form a two element charged particle telescope. Each of these telescopes is capable of determining the elemental identity of nuclear fragments passing through it. The system is used to measure light fragment production in the presence of heavier fragments. We will present a detailed discussion of the 64-pad detector design, the substrate design. The front-end electronics used to read out the signals is based on a custom VLSI chip developed for the Advanced Thin Ionization Calorimeter experiment which has been flown successfully twice in Antarctica. Each of these chips has 16 channels and each channel consists of a charge-sensitive preamplifier followed by a shaping amplifier and a track-and-hold circuit. The track-and-hold circuits are connected via a multiplexer to an output line driver. This allows the held signals to be presented, one-by-one via a common data line to a analog-to-digital converter. Because the output line driver can be placed in a high input impedance state when not in use, it is possible to daisy-change many chips on the same common data line. The front-end electronics and data readout scheme will be discussed in detail. The Zero Degree Detector has been used in several accelerator experiments conducted at the NASA Space Radiation Laboratory and the Alternating Gradient Synchrotron at Brookhaven National Laboratory as well as at the HIMAC accelerator in Japan. We will show examples of data taken at these accelerator runs to demonstrate how the system works.

A Monolithic Multisensor Microchip with Complete On-Chip RF Front-End

PubMed Central

Felini, Corrado; Della Corte, Francesco G.

2018-01-01

In this paper, a new wireless sensor, designed for a 0.35 µm CMOS technology, is presented. The microchip was designed to be placed on an object for the continuous remote monitoring of its temperature and illumination state. The temperature sensor is based on the temperature dependence of the I-V characteristics of bipolar transistors available in CMOS technology, while the illumination sensor is an integrated p-n junction photodiode. An on-chip 2.5 GHz transmitter, coupled to a mm-sized dipole radiating element fabricated on the same microchip and made in the top metal layer of the same die, sends the collected data wirelessly to a radio receiver using an On-Off Keying (OOK) modulation pattern. PMID:29301297

Subpixel mapping and test beam studies with a HV2FEI4v2 CMOS-Sensor-Hybrid Module for the ATLAS inner detector upgrade

NASA Astrophysics Data System (ADS)

Bisanz, T.; Große-Knetter, J.; Quadt, A.; Rieger, J.; Weingarten, J.

2017-08-01

The upgrade to the High Luminosity Large Hadron Collider will increase the instantaneous luminosity by more than a factor of 5, thus creating significant challenges to the tracking systems of all experiments. Recent advancement of active pixel detectors designed in CMOS processes provide attractive alternatives to the well-established hybrid design using passive sensors since they allow for smaller pixel sizes and cost effective production. This article presents studies of a high-voltage CMOS active pixel sensor designed for the ATLAS tracker upgrade. The sensor is glued to the read-out chip of the Insertable B-Layer, forming a capacitively coupled pixel detector. The pixel pitch of the device under test is 33× 125 μm2, while the pixels of the read-out chip have a pitch of 50× 250 μm2. Three pixels of the CMOS device are connected to one read-out pixel, the information of which of these subpixels is hit is encoded in the amplitude of the output signal (subpixel encoding). Test beam measurements are presented that demonstrate the usability of this subpixel encoding scheme.

Propagating gene expression fronts in a one-dimensional coupled system of artificial cells

NASA Astrophysics Data System (ADS)

Tayar, Alexandra M.; Karzbrun, Eyal; Noireaux, Vincent; Bar-Ziv, Roy H.

2015-12-01

Living systems employ front propagation and spatiotemporal patterns encoded in biochemical reactions for communication, self-organization and computation. Emulating such dynamics in minimal systems is important for understanding physical principles in living cells and in vitro. Here, we report a one-dimensional array of DNA compartments in a silicon chip as a coupled system of artificial cells, offering the means to implement reaction-diffusion dynamics by integrated genetic circuits and chip geometry. Using a bistable circuit we programmed a front of protein synthesis propagating in the array as a cascade of signal amplification and short-range diffusion. The front velocity is maximal at a saddle-node bifurcation from a bistable regime with travelling fronts to a monostable regime that is spatially homogeneous. Near the bifurcation the system exhibits large variability between compartments, providing a possible mechanism for population diversity. This demonstrates that on-chip integrated gene circuits are dynamical systems driving spatiotemporal patterns, cellular variability and symmetry breaking.

Multi-Step Deep Reactive Ion Etching Fabrication Process for Silicon-Based Terahertz Components

NASA Technical Reports Server (NTRS)

Reck, Theodore (Inventor); Perez, Jose Vicente Siles (Inventor); Lee, Choonsup (Inventor); Cooper, Ken B. (Inventor); Jung-Kubiak, Cecile (Inventor); Mehdi, Imran (Inventor); Chattopadhyay, Goutam (Inventor); Lin, Robert H. (Inventor); Peralta, Alejandro (Inventor)

2016-01-01

A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range.

Mechanism of Void Prediction in Flip Chip Packages with Molded Underfill

NASA Astrophysics Data System (ADS)

Wu, Kuo-Tsai; Hwang, Sheng-Jye; Lee, Huei-Huang

2017-08-01

Voids have always been present using the molded underfill (MUF) package process, which is a problem that needs further investigation. In this study, the process was studied using the Moldex3D numerical analysis software. The effects of gas (air vent effect) on the overall melt front were also considered. In this isothermal process containing two fluids, the gas and melt colloid interact in the mold cavity. Simulation enabled an appropriate understanding of the actual situation to be gained, and, through analysis, the void region and exact location of voids were predicted. First, the global flow end area was observed to predict the void movement trend, and then the local flow ends were observed to predict the location and size of voids. In the MUF 518 case study, simulations predicted the void region as well as the location and size of the voids. The void phenomenon in a flip chip ball grid array underfill is discussed as part of the study.

IDeF-X ECLAIRs: A CMOS ASIC for the Readout of CdTe and CdZnTe Detectors for High Resolution Spectroscopy

NASA Astrophysics Data System (ADS)

Gevin, Olivier; Baron, Pascal; Coppolani, Xavier; Daly, FranÇois; Delagnes, Eric; Limousin, Olivier; Lugiez, Francis; Meuris, Aline; Pinsard, FrÉdÉric; Renaud, Diana

2009-08-01

The very last member of the IDeF-X ASIC family is presented: IDeF-X ECLAIRs is a 32-channel front end ASIC designed for the readout of Cadmium Telluride (CdTe) and Cadmium Zinc Telluride (CdZnTe) Detectors. Thanks to its noise performance (Equivalent Noise Charge floor of 33 e- rms) and to its radiation hardened design (Single Event Latchup Linear Energy Transfer threshold of 56 MeV.cm2.mg-1), the chip is well suited for soft X-rays energy discrimination and high energy resolution, ldquospace proof,rdquo hard X-ray spectroscopy. We measured an energy low threshold of less than 4 keV with a 10 pF input capacitor and a minimal reachable sensitivity of the Equivalent Noise Charge (ENC) to input capacitance of less than 7 e-/pF obtained with a 6 mus peak time. IDeF-X ECLAIRs will be used for the readout of 6400 CdTe Schottky monopixel detectors of the 2D coded mask imaging telescope ECLAIRs aboard the SVOM satellite. IDeF-X ECLAIRs (or IDeF-X V2) has also been designed for the readout of a pixelated CdTe detector in the miniature spectro-imager prototype Caliste 256 that is currently foreseen for the high energy detector module of the Simbol-X mission.

SVGA and XGA active matrix microdisplays for head-mounted applications

NASA Astrophysics Data System (ADS)

Alvelda, Phillip; Bolotski, Michael; Brown, Imani L.

2000-03-01

The MicroDisplay Corporation's liquid crystal on silicon (LCOS) display devices are based on the union of several technologies with the extreme integration capability of conventionally fabricated CMOS substrates. The fast liquid crystal operation modes and new scalable high-performance pixel addressing architectures presented in this paper enable substantially improved color, contrast, and brightness while still satisfying the optical, packaging, and power requirements of portable applications. The entire suite of MicroDisplay's technologies was devised to create a line of mixed-signal application-specific integrated circuits (ASICs) in single-chip display systems. Mixed-signal circuits can integrate computing, memory, and communication circuitry on the same substrate as the display drivers and pixel array for a multifunctional complete system-on-a-chip. System-on-a-chip benefits also include reduced head supported weight requirements through the elimination of off-chip drive electronics.

CCD and photon-counting photometric observations of peculiar asteroids

NASA Astrophysics Data System (ADS)

Fulvio, D.; Blanco, C.; Cigna, M.; Gandolfi, D.

The photometric observational programme of main-belt asteroids undertaken, since 1980, at the Physics and Astronomy Department of Catania University, mainly by using photoelectric acquisition, has been extended to the Near-Earth Objects, because of the importance of their study to improve the knowledge of the mechanics and the physics of the inner Solar System. The wideness of the observational programme was pursued by using an expressly built CCD camera having a Kodak 4200 detector 2048x2048 pixel class 1, front-illuminated chip with 9 mu m pixel-size, equipped with BVRI Johnson filters. New observations of 4 Vesta, 27 Euterpe, 173 Ino, 182 Elsa, 849 Ara (carried out at M.G. Fracastoro Station of Catania Astrophysical Observatory), 984 Gretia, 3199 Nefertiti and 2004 UE (carried out at Asiago Station of Padova Astronomical Observatory) are presented. The improvement of the rotational period value (for 182 Elsa and 2004 UE it is the first determination), of the lightcurve amplitude and of the B-V colour index was obtained. For 4 Vesta indications on surface mineralogic morphology are deduced from the UBV photometric behaviour while for 182 Elsa, the H-G magnitude relation was carried out.

Design and test of data acquisition systems for the Medipix2 chip based on PC standard interfaces

NASA Astrophysics Data System (ADS)

Fanti, Viviana; Marzeddu, Roberto; Piredda, Giuseppina; Randaccio, Paolo

2005-07-01

We describe two readout systems for hybrid detectors using the Medipix2 single photon counting chip, developed within the Medipix Collaboration. The Medipix2 chip (256×256 pixels, 55 μm pitch) has an active area of about 2 cm 2 and is bump-bonded to a pixel semiconductor array of silicon or other semiconductor material. The readout systems we are developing are based on two widespread standard PC interfaces: parallel port and USB (Universal Serial Bus) version 1.1. The parallel port is the simplest PC interface even if slow and the USB is a serial bus interface present nowadays on all PCs and offering good performances.

Charge Loss and Charge Sharing Measurements for Two Different Pixelated Cadmium-Zinc-Telluride Detectors

NASA Technical Reports Server (NTRS)

Gaskin, Jessica; Sharma, Dharma; Ramsey, Brian; Seller, Paul

2003-01-01

As part of ongoing research at Marshall Space Flight Center, Cadmium-Zinc- Telluride (CdZnTe) pixilated detectors are being developed for use at the focal plane of the High Energy Replicated Optics (HERO) telescope. HERO requires a 64x64 pixel array with a spatial resolution of around 200 microns (with a 6m focal length) and high energy resolution (< 2% at 60keV). We are currently testing smaller arrays as a necessary first step towards this goal. In this presentation, we compare charge sharing and charge loss measurements between two devices that differ both electronically and geometrically. The first device consists of a 1-mm-thick piece of CdZnTe that is sputtered with a 4x4 array of pixels with pixel pitch of 750 microns (inter-pixel gap is 100 microns). The signal is read out using discrete ultra-low-noise preamplifiers, one for each of the 16 pixels. The second detector consists of a 2-mm-thick piece of CdZnTe that is sputtered with a 16x16 array of pixels with a pixel pitch of 300 microns (inter-pixel gap is 50 microns). Instead of using discrete preamplifiers, the crystal is bonded to an ASIC that provides all of the front-end electronics to each of the 256 pixels. what degree the bias voltage (i.e. the electric field) and hence the drift and diffusion coefficients affect our measurements. Further, we compare the measured results with simulated results and discuss to

Development of n+-in-p planar pixel quadsensor flip-chipped with FE-I4 readout ASICs

NASA Astrophysics Data System (ADS)

Unno, Y.; Kamada, S.; Yamamura, K.; Yamamoto, H.; Hanagaki, K.; Hori, R.; Ikegami, Y.; Nakamura, K.; Takubo, Y.; Takashima, R.; Tojo, J.; Kono, T.; Nagai, R.; Saito, S.; Sugibayashi, K.; Hirose, M.; Jinnouchi, O.; Sato, S.; Sawai, H.; Hara, K.; Sato, Kz.; Sato, Kj.; Iwabuchi, S.; Suzuki, J.

2017-01-01

We have developed flip-chip modules applicable to the pixel detector for the HL-LHC. New radiation-tolerant n+-in-p planar pixel sensors of a size of four FE-I4 application-specific integrated circuits (ASICs) are laid out in a 6-in wafer. Variation in readout connection for the pixels at the boundary of ASICs is implemented in the design of quadsensors. Bump bonding technology is developed for four ASICs onto one quadsensor. Both sensors and ASICs are thinned to 150 μm before bump bonding, and are held flat with vacuum chucks. Using lead-free SnAg solder bumps, we encounter deficiency with large areas of disconnected bumps after thermal stress treatment, including irradiation. Surface oxidation of the solder bumps is identified as a critical source of this deficiency after bump bonding trials, using SnAg bumps with solder flux, indium bumps, and SnAg bumps with a newly-introduced hydrogen-reflow process. With hydrogen-reflow, we establish flux-less bump bonding technology with SnAg bumps, appropriate for mass production of the flip-chip modules with thin sensors and thin ASICs.

Bioinspired architecture approach for a one-billion transistor smart CMOS camera chip

NASA Astrophysics Data System (ADS)

Fey, Dietmar; Komann, Marcus

2007-05-01

In the paper we present a massively parallel VLSI architecture for future smart CMOS camera chips with up to one billion transistors. To exploit efficiently the potential offered by future micro- or nanoelectronic devices traditional on central structures oriented parallel architectures based on MIMD or SIMD approaches will fail. They require too long and too many global interconnects for the distribution of code or the access to common memory. On the other hand nature developed self-organising and emergent principles to manage successfully complex structures based on lots of interacting simple elements. Therefore we developed a new as Marching Pixels denoted emergent computing paradigm based on a mixture of bio-inspired computing models like cellular automaton and artificial ants. In the paper we present different Marching Pixels algorithms and the corresponding VLSI array architecture. A detailed synthesis result for a 0.18 μm CMOS process shows that a 256×256 pixel image is processed in less than 10 ms assuming a moderate 100 MHz clock rate for the processor array. Future higher integration densities and a 3D chip stacking technology will allow the integration and processing of Mega pixels within the same time since our architecture is fully scalable.

Particle identification using the time-over-threshold measurements in straw tube detectors

NASA Astrophysics Data System (ADS)

Jowzaee, S.; Fioravanti, E.; Gianotti, P.; Idzik, M.; Korcyl, G.; Palka, M.; Przyborowski, D.; Pysz, K.; Ritman, J.; Salabura, P.; Savrie, M.; Smyrski, J.; Strzempek, P.; Wintz, P.

2013-08-01

The identification of charged particles based on energy losses in straw tube detectors has been simulated. The response of a new front-end chip developed for the PANDA straw tube tracker was implemented in the simulations and corrections for track distance to sense wire were included. Separation power for p - K, p - π and K - π pairs obtained using the time-over-threshold technique was compared with the one based on the measurement of collected charge.

Asymmetric Multilevel Outphasing (AMO): A New Architecture for All-Silicon mm-Wave Transmitter ICs

DTIC Science & Technology

2015-06-12

power-amplifiers for mobile basestation infrastructure and handsets. NanoSemi Inc. designs linearization solutions for analog front-ends such as...ward flexible, multi-standard radio chips, increases the need for high-precision, high-throughput and energy-efficient backend processing. The desire...peak PAE is affected by less than 1% (46 mW/(46 mW 1.8 W/0.4)) by this 64-QAM capable AMO SCS backend . 378 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48

Satellite-On-A-Chip Feasibility for Distributed Space Missions

DTIC Science & Technology

2006-07-10

S.pdf Satellite Systems Conference and Exhibit, Monterey, [33] H . Helvajian and S. W. Janson, "The Fabrication of a CA, 2004, Paper AIAA-2004-3152. 100...pp. 12-15. 700. [52]0. Yadid-Pecht and R. Etienne-Cummings, CMOS [64]S. W. Janson, H . Helvajian , S. Amimoto, G. Smit, D. Imagers: From...Janson, H . Helvajian , and K. Breuer "MEMS, Hasler, "A 80 p W/frame 104x128 CMOS Imager Microengineering and Aerospace Systems," in Proc. Front End for

High Dynamic Range Imaging at the Quantum Limit with Single Photon Avalanche Diode-Based Image Sensors †

PubMed Central

Mattioli Della Rocca, Francescopaolo

2018-01-01

This paper examines methods to best exploit the High Dynamic Range (HDR) of the single photon avalanche diode (SPAD) in a high fill-factor HDR photon counting pixel that is scalable to megapixel arrays. The proposed method combines multi-exposure HDR with temporal oversampling in-pixel. We present a silicon demonstration IC with 96 × 40 array of 8.25 µm pitch 66% fill-factor SPAD-based pixels achieving >100 dB dynamic range with 3 back-to-back exposures (short, mid, long). Each pixel sums 15 bit-planes or binary field images internally to constitute one frame providing 3.75× data compression, hence the 1k frames per second (FPS) output off-chip represents 45,000 individual field images per second on chip. Two future projections of this work are described: scaling SPAD-based image sensors to HDR 1 MPixel formats and shrinking the pixel pitch to 1–3 µm. PMID:29641479

A system for characterization of DEPFET silicon pixel matrices and test beam results

NASA Astrophysics Data System (ADS)

Furletov, Sergey; DEPFET Collaboration

2011-02-01

The DEPFET pixel detector offers first stage in-pixel amplification by incorporating a field effect transistor in the high resistivity silicon substrate. In this concept, a very small input capacitance can be realized thus allowing for low noise measurements. This makes DEPFET sensors a favorable technology for tracking in particle physics. Therefore a system with a DEPFET pixel matrix was developed to test DEPFET performance for an application as a vertex detector for the Belle II experiment. The system features a current based, row-wise readout of a DEPFET pixel matrix with a designated readout chip, steering chips for matrix control, a FPGA based data acquisition board, and a dedicated software package. The system was successfully operated in both test beam and lab environment. In 2009 new DEPFET matrices have been characterized in a 120 GeV pion beam at the CERN SPS. The current status of the DEPFET system and test beam results are presented.

Transparent Fingerprint Sensor System for Large Flat Panel Display.

PubMed

Seo, Wonkuk; Pi, Jae-Eun; Cho, Sung Haeung; Kang, Seung-Youl; Ahn, Seong-Deok; Hwang, Chi-Sun; Jeon, Ho-Sik; Kim, Jong-Uk; Lee, Myunghee

2018-01-19

In this paper, we introduce a transparent fingerprint sensing system using a thin film transistor (TFT) sensor panel, based on a self-capacitive sensing scheme. An armorphousindium gallium zinc oxide (a-IGZO) TFT sensor array and associated custom Read-Out IC (ROIC) are implemented for the system. The sensor panel has a 200 × 200 pixel array and each pixel size is as small as 50 μm × 50 μm. The ROIC uses only eight analog front-end (AFE) amplifier stages along with a successive approximation analog-to-digital converter (SAR ADC). To get the fingerprint image data from the sensor array, the ROIC senses a capacitance, which is formed by a cover glass material between a human finger and an electrode of each pixel of the sensor array. Three methods are reviewed for estimating the self-capacitance. The measurement result demonstrates that the transparent fingerprint sensor system has an ability to differentiate a human finger's ridges and valleys through the fingerprint sensor array.

ePix: a class of architectures for second generation LCLS cameras

DOE PAGES

Dragone, A.; Caragiulo, P.; Markovic, B.; ...

2014-03-31

ePix is a novel class of ASIC architectures, based on a common platform, optimized to build modular scalable detectors for LCLS. The platform architecture is composed of a random access analog matrix of pixel with global shutter, fast parallel column readout, and dedicated sigma-delta analog-to-digital converters per column. It also implements a dedicated control interface and all the required support electronics to perform configuration, calibration and readout of the matrix. Based on this platform a class of front-end ASICs and several camera modules, meeting different requirements, can be developed by designing specific pixel architectures. This approach reduces development time andmore » expands the possibility of integration of detector modules with different size, shape or functionality in the same camera. The ePix platform is currently under development together with the first two integrating pixel architectures: ePix100 dedicated to ultra low noise applications and ePix10k for high dynamic range applications.« less

Transparent Fingerprint Sensor System for Large Flat Panel Display

PubMed Central

Seo, Wonkuk; Pi, Jae-Eun; Cho, Sung Haeung; Kang, Seung-Youl; Ahn, Seong-Deok; Hwang, Chi-Sun; Jeon, Ho-Sik; Kim, Jong-Uk

2018-01-01

In this paper, we introduce a transparent fingerprint sensing system using a thin film transistor (TFT) sensor panel, based on a self-capacitive sensing scheme. An armorphousindium gallium zinc oxide (a-IGZO) TFT sensor array and associated custom Read-Out IC (ROIC) are implemented for the system. The sensor panel has a 200 × 200 pixel array and each pixel size is as small as 50 μm × 50 μm. The ROIC uses only eight analog front-end (AFE) amplifier stages along with a successive approximation analog-to-digital converter (SAR ADC). To get the fingerprint image data from the sensor array, the ROIC senses a capacitance, which is formed by a cover glass material between a human finger and an electrode of each pixel of the sensor array. Three methods are reviewed for estimating the self-capacitance. The measurement result demonstrates that the transparent fingerprint sensor system has an ability to differentiate a human finger’s ridges and valleys through the fingerprint sensor array. PMID:29351218

Smart image sensors: an emerging key technology for advanced optical measurement and microsystems

NASA Astrophysics Data System (ADS)

Seitz, Peter

1996-08-01

Optical microsystems typically include photosensitive devices, analog preprocessing circuitry and digital signal processing electronics. The advances in semiconductor technology have made it possible today to integrate all photosensitive and electronical devices on one 'smart image sensor' or photo-ASIC (application-specific integrated circuits containing photosensitive elements). It is even possible to provide each 'smart pixel' with additional photoelectronic functionality, without compromising the fill factor substantially. This technological capability is the basis for advanced cameras and optical microsystems showing novel on-chip functionality: Single-chip cameras with on- chip analog-to-digital converters for less than $10 are advertised; image sensors have been developed including novel functionality such as real-time selectable pixel size and shape, the capability of performing arbitrary convolutions simultaneously with the exposure, as well as variable, programmable offset and sensitivity of the pixels leading to image sensors with a dynamic range exceeding 150 dB. Smart image sensors have been demonstrated offering synchronous detection and demodulation capabilities in each pixel (lock-in CCD), and conventional image sensors are combined with an on-chip digital processor for complete, single-chip image acquisition and processing systems. Technological problems of the monolithic integration of smart image sensors include offset non-uniformities, temperature variations of electronic properties, imperfect matching of circuit parameters, etc. These problems can often be overcome either by designing additional compensation circuitry or by providing digital correction routines. Where necessary for technological or economic reasons, smart image sensors can also be combined with or realized as hybrids, making use of commercially available electronic components. It is concluded that the possibilities offered by custom smart image sensors will influence the design and the performance of future electronic imaging systems in many disciplines, reaching from optical metrology to machine vision on the factory floor and in robotics applications.

GridPix detectors: Production and beam test results

NASA Astrophysics Data System (ADS)

Koppert, W. J. C.; van Bakel, N.; Bilevych, Y.; Colas, P.; Desch, K.; Fransen, M.; van der Graaf, H.; Hartjes, F.; Hessey, N. P.; Kaminski, J.; Schmitz, J.; Schön, R.; Zappon, F.

2013-12-01

The innovative GridPix detector is a Time Projection Chamber (TPC) that is read out with a Timepix-1 pixel chip. By using wafer post-processing techniques an aluminium grid is placed on top of the chip. When operated, the electric field between the grid and the chip is sufficient to create electron induced avalanches which are detected by the pixels. The time-to-digital converter (TDC) records the drift time enabling the reconstruction of high precision 3D track segments. Recently GridPixes were produced on full wafer scale, to meet the demand for more reliable and cheaper devices in large quantities. In a recent beam test the contribution of both diffusion and time walk to the spatial and angular resolutions of a GridPix detector with a 1.2 mm drift gap are studied in detail. In addition long term tests show that in a significant fraction of the chips the protection layer successfully quenches discharges, preventing harm to the chip.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fahim, Farah; Deptuch, Grzegorz; Shenai, Alpana

The Vertically Integrated Photon Imaging Chip - Large, (VIPIC-L), is a large area, small pixel (65μm), 3D integrated, photon counting ASIC with zero-suppressed or full frame dead-time-less data readout. It features data throughput of 14.4 Gbps per chip with a full frame readout speed of 56kframes/s in the imaging mode. VIPIC-L contain 192 x 192 pixel array and the total size of the chip is 1.248cm x 1.248cm with only a 5μm periphery. It contains about 120M transistors. A 1.3M pixel camera module will be developed by arranging a 6 x 6 array of 3D VIPIC-L’s bonded to a largemore » area silicon sensor on the analog side and to a readout board on the digital side. The readout board hosts a bank of FPGA’s, one per VIPIC-L to allow processing of up to 0.7 Tbps of raw data produced by the camera.« less

Radiation hardness studies of AMS HV-CMOS 350 nm prototype chip HVStripV1

DOE PAGES

Kanisauskas, K.; Affolder, A.; Arndt, K.; ...

2017-02-15

CMOS active pixel sensors are being investigated for their potential use in the ATLAS inner tracker upgrade at the HL-LHC. The new inner tracker will have to handle a significant increase in luminosity while maintaining a sufficient signal-to-noise ratio and pulse shaping times. This paper focuses on the prototype chip "HVStripV1" (manufactured in the AMS HV-CMOS 350nm process) characterization before and after irradiation up to fluence levels expected for the strip region in the HL-LHC environment. The results indicate an increase of depletion region after irradiation for the same bias voltage by a factor of ≈2.4 and ≈2.8 for twomore » active pixels on the test chip. As a result, there was also a notable increase in noise levels from 85 e – to 386 e – and from 75 e – to 277 e – for the corresponding pixels.« less

Radiation hardness studies of AMS HV-CMOS 350 nm prototype chip HVStripV1

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kanisauskas, K.; Affolder, A.; Arndt, K.

CMOS active pixel sensors are being investigated for their potential use in the ATLAS inner tracker upgrade at the HL-LHC. The new inner tracker will have to handle a significant increase in luminosity while maintaining a sufficient signal-to-noise ratio and pulse shaping times. This paper focuses on the prototype chip "HVStripV1" (manufactured in the AMS HV-CMOS 350nm process) characterization before and after irradiation up to fluence levels expected for the strip region in the HL-LHC environment. The results indicate an increase of depletion region after irradiation for the same bias voltage by a factor of ≈2.4 and ≈2.8 for twomore » active pixels on the test chip. As a result, there was also a notable increase in noise levels from 85 e – to 386 e – and from 75 e – to 277 e – for the corresponding pixels.« less

High-contrast X-ray micro-tomography of low attenuation samples using large area hybrid semiconductor pixel detector array of 10 × 5 Timepix chips

NASA Astrophysics Data System (ADS)

Karch, J.; Krejci, F.; Bartl, B.; Dudak, J.; Kuba, J.; Kvacek, J.; Zemlicka, J.

2016-01-01

State-of-the-art hybrid pixel semiconductor detectors provide excellent imaging properties such as unlimited dynamic range, high spatial resolution, high frame rate and energy sensitivity. Nevertheless, a limitation in the use of these devices for imaging has been the small sensitive area of a few square centimetres. In the field of microtomography we make use of a large area pixel detector assembled from 50 Timepix edgeless chips providing fully sensitive area of 14.3 × 7.15 cm2. We have successfully demonstrated that the enlargement of the sensitive area enables high-quality tomographic measurements of whole objects with high geometrical magnification without any significant degradation in resulting reconstructions related to the chip tilling and edgeless sensor technology properties. The technique of micro-tomography with the newly developed large area detector is applied for samples formed by low attenuation, low contrast materials such a seed from Phacelia tanacetifolia, a charcoalified wood sample and a beeswax seal sample.

Methodology for interpretation of SST retrievals using the AVHRR split window algorithm

NASA Technical Reports Server (NTRS)

Barbieri, R. W.; Mcclain, C. R.; Endres, D. L.

1983-01-01

Intercomparisons of sea surface temperature (SST) products derived from the operational NOAA-7 AVHRR-II algorithm and in situ observations are made. The 1982 data sets consist of ship survey data during the winter from the Mid-Atlantic Bight (MAB), ship and buoy measurements during April and September in the Gulf of Mexico and shipboard observations during April off the N.W. Spanish coast. The analyses included single pixel comparisons and the warmest pixel technique for 2 x 2 pixel and 10 x 10 pixel areas. The reason for using multi-pixel areas was for avoiding cloud contaminated pixels in the vicinity of the field measurements. Care must be taken when applying the warmest pixel technique near oceanic fronts. The Gulf of Mexico results clearly indicate a persistent degradation in algorithm accuracy due to El Chichon aerosols. The MAB and Spanish data sets indicate that very accurate estimates can be achieved if care is taken to avoid clouds and oceanic fronts.

Ultrafast-laser dicing of thin silicon wafers: strategies to improve front- and backside breaking strength

NASA Astrophysics Data System (ADS)

Domke, Matthias; Egle, Bernadette; Stroj, Sandra; Bodea, Marius; Schwarz, Elisabeth; Fasching, Gernot

2017-12-01

Thin 50-µm silicon wafers are used to improve heat dissipation of chips with high power densities. However, mechanical dicing methods cause chipping at the edges of the separated dies that reduce the mechanical stability. Thermal load changes may then lead to sudden chip failure. Recent investigations showed that the mechanical stability of the cut chips could be increased using ultrashort-pulsed lasers, but only at the laser entrance (front) side and not at the exit (back) side. The goal of this study was to find strategies to improve both front- and backside breaking strength of chips that were cut out of an 8″ wafer with power metallization using an ultrafast laser. In a first experiment, chips were cut by scanning the laser beam in single lines across the wafer using varying fluencies and scan speeds. Three-point bending tests of the cut chips were performed to measure front and backside breaking strengths. The results showed that the breaking strength of both sides increased with decreasing accumulated fluence per scan. Maximum breaking strengths of about 1100 MPa were achieved at the front side, but only below 600 MPa were measured for the backside. A second experiment was carried out to optimize the backside breaking strength. Here, parallel line scans to increase the distance between separated dies and step cuts to minimize the effect of decreasing fluence during scribing were performed. Bending tests revealed that breaking strengths of about 1100 MPa could be achieved also on the backside using the step cut. A reason for the superior performance could be found by calculating the fluence absorbed by the sidewalls. The calculations suggested that an optimal fluence level to minimize thermal side effects and periodic surface structures was achieved due to the step cut. Remarkably, the best breaking strengths values achieved in this study were even higher than the values obtained on state of the art ns-laser and mechanical dicing machines. This is the first study to the knowledge of the authors, which demonstrates that ultrafast-laser dicing improves the mechanical stability of thin silicon chips.

Advanced processing of CdTe pixel radiation detectors

NASA Astrophysics Data System (ADS)

Gädda, A.; Winkler, A.; Ott, J.; Härkönen, J.; Karadzhinova-Ferrer, A.; Koponen, P.; Luukka, P.; Tikkanen, J.; Vähänen, S.

2017-12-01

We report a fabrication process of pixel detectors made of bulk cadmium telluride (CdTe) crystals. Prior to processing, the quality and defect density in CdTe material was characterized by infrared (IR) spectroscopy. The semiconductor detector and Flip-Chip (FC) interconnection processing was carried out in the clean room premises of Micronova Nanofabrication Centre in Espoo, Finland. The chip scale processes consist of the aluminum oxide (Al2O3) low temperature thermal Atomic Layer Deposition (ALD), titanium tungsten (TiW) metal sputtering depositions and an electroless Nickel growth. CdTe crystals with the size of 10×10×0.5 mm3 were patterned with several photo-lithography techniques. In this study, gold (Au) was chosen as the material for the wettable Under Bump Metalization (UBM) pads. Indium (In) based solder bumps were grown on PSI46dig read out chips (ROC) having 4160 pixels within an area of 1 cm2. CdTe sensor and ROC were hybridized using a low temperature flip-chip (FC) interconnection technique. The In-Au cold weld bonding connections were successfully connecting both elements. After the processing the detector packages were wire bonded into associated read out electronics. The pixel detectors were tested at the premises of Finnish Radiation Safety Authority (STUK). During the measurement campaign, the modules were tested by exposure to a 137Cs source of 1.5 TBq for 8 minutes. We detected at the room temperature a photopeak at 662 keV with about 2 % energy resolution.

An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit.

PubMed

Tao Tang; Wang Ling Goh; Lei Yao; Jia Hao Cheong; Yuan Gao

2017-07-01

This paper describes an integrated multichannel neural recording analog front end (AFE) with a novel area-efficient driven right leg (DRL) circuit to improve the system common mode rejection ratio (CMRR). The proposed AFE consists of an AC-coupled low-noise programmable-gain amplifier, an area-efficient DRL block and a 10-bit SAR ADC. Compared to conventional DRL circuit, the proposed capacitor-less DRL design achieves 90% chip area reduction with enhanced CMRR performance, making it ideal for multichannel biomedical recording applications. The AFE circuit has been designed in a standard 0.18-μm CMOS process. Post-layout simulation results show that the AFE provides two gain settings of 54dB/60dB while consuming 1 μA per channel under a supply voltage of 1 V. The input-referred noise of the AFE integrated from 1 Hz to 10k Hz is only 4 μVrms and the CMRR is 110 dB.

CMOS Rad-Hard Front-End Electronics for Precise Sensors Measurements

NASA Astrophysics Data System (ADS)

Sordo-Ibáñez, Samuel; Piñero-García, Blanca; Muñoz-Díaz, Manuel; Ragel-Morales, Antonio; Ceballos-Cáceres, Joaquín; Carranza-González, Luis; Espejo-Meana, Servando; Arias-Drake, Alberto; Ramos-Martos, Juan; Mora-Gutiérrez, José Miguel; Lagos-Florido, Miguel Angel

2016-08-01

This paper reports a single-chip solution for the implementation of radiation-tolerant CMOS front-end electronics (FEE) for applications requiring the acquisition of base-band sensor signals. The FEE has been designed in a 0.35μm CMOS process, and implements a set of parallel conversion channels with high levels of configurability to adapt the resolution, conversion rate, as well as the dynamic input range for the required application. Each conversion channel has been designed with a fully-differential implementation of a configurable-gain instrumentation amplifier, followed by an also configurable dual-slope ADC (DS ADC) up to 16 bits. The ASIC also incorporates precise thermal monitoring, sensor conditioning and error detection functionalities to ensure proper operation in extreme environments. Experimental results confirm that the proposed topologies, in conjunction with the applied radiation-hardening techniques, are reliable enough to be used without loss in the performance in environments with an extended temperature range (between -25 and 125 °C) and a total dose beyond 300 krad.

A low power wearable transceiver for human body communication.

PubMed

Huang, Jin; Chen, Lian-Kang; Zhang, Yuan-Ting

2009-01-01

This paper reports a low power transceiver designed for wearable medical healthcare system. Based on a novel energy-efficient wideband wireless communication scheme that uses human body as a transmission medium, the transceiver can achieve a maximum 15 Mbps data rate with total receiver sensitivity of -30 dBm. The chip measures only 0.56 mm(2) and was fabricated in the SMIC 0.18um 1P6M RF CMOS process. The RX consumes 5mW and TX dissipates 1mW with delivering power up to 10uW, which is suitable for the body area network short range application. Real-time medical information collecting through the human body is fully simulated. Architecture of the chip together with the detail characterizes from its wireless analog front-end are presented.

Heavy Ion Transient Characterization of a Photobit Hardened-by-Design Active Pixel Sensor Array

NASA Technical Reports Server (NTRS)

Marshall, Paul W.; Byers, Wheaton B.; Conger, Christopher; Eid, El-Sayed; Gee, George; Jones, Michael R.; Marshall, Cheryl J.; Reed, Robert; Pickel, Jim; Kniffin, Scott

2002-01-01

This paper presents heavy ion data on the single event transient (SET) response of a Photobit active pixel sensor (APS) four quadrant test chip with different radiation tolerant designs in a standard 0.35 micron CMOS process. The physical design techniques of enclosed geometry and P-channel guard rings are used to design the four N-type active photodiode pixels as described in a previous paper. Argon transient measurements on the 256 x 256 chip array as a function of incident angle show a significant variation in the amount of charge collected as well as the charge spreading dependent on the pixel type. The results are correlated with processing and design information provided by Photobit. In addition, there is a large degree of statistical variability between individual ion strikes. No latch-up is observed up to an LET of 106 MeV/mg/sq cm.

Hit efficiency study of CMS prototype forward pixel detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Dongwook; /Johns Hopkins U.

2006-01-01

In this paper the author describes the measurement of the hit efficiency of a prototype pixel device for the CMS forward pixel detector. These pixel detectors were FM type sensors with PSI46V1 chip readout. The data were taken with the 120 GeV proton beam at Fermilab during the period of December 2004 to February 2005. The detectors proved to be highly efficient (99.27 {+-} 0.02%). The inefficiency was primarily located near the corners of the individual pixels.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bolotnikov, A. E.; Camarda, G. S.; Cui, Y.

Following our successful demonstration of the position-sensitive virtual Frisch-grid detectors, we investigated the feasibility of using high-granularity position sensing to correct response non-uniformities caused by the crystal defects in CdZnTe (CZT) pixelated detectors. The development of high-granularity detectors able to correct response non-uniformities on a scale comparable to the size of electron clouds opens the opportunity of using unselected off-the-shelf CZT material, whilst still assuring high spectral resolution for the majority of the detectors fabricated from an ingot. Here, we present the results from testing 3D position-sensitive 15×15×10 mm 3 pixelated detectors, fabricated with conventional pixel patterns with progressively smallermore » pixel sizes: 1.4, 0.8, and 0.5 mm. We employed the readout system based on the H3D front-end multi-channel ASIC developed by BNL's Instrumentation Division in collaboration with the University of Michigan. We use the sharing of electron clouds among several adjacent pixels to measure locations of interaction points with sub-pixel resolution. By using the detectors with small-pixel sizes and a high probability of the charge-sharing events, we were able to improve their spectral resolutions in comparison to the baseline levels, measured for the 1.4-mm pixel size detectors with small fractions of charge-sharing events. These results demonstrate that further enhancement of the performance of CZT pixelated detectors and reduction of costs are possible by using high spatial-resolution position information of interaction points to correct the small-scale response non-uniformities caused by crystal defects present in most devices.« less

Programmable optical processor chips: toward photonic RF filters with DSP-level flexibility and MHz-band selectivity

NASA Astrophysics Data System (ADS)

Xie, Yiwei; Geng, Zihan; Zhuang, Leimeng; Burla, Maurizio; Taddei, Caterina; Hoekman, Marcel; Leinse, Arne; Roeloffzen, Chris G. H.; Boller, Klaus-J.; Lowery, Arthur J.

2017-12-01

Integrated optical signal processors have been identified as a powerful engine for optical processing of microwave signals. They enable wideband and stable signal processing operations on miniaturized chips with ultimate control precision. As a promising application, such processors enables photonic implementations of reconfigurable radio frequency (RF) filters with wide design flexibility, large bandwidth, and high-frequency selectivity. This is a key technology for photonic-assisted RF front ends that opens a path to overcoming the bandwidth limitation of current digital electronics. Here, the recent progress of integrated optical signal processors for implementing such RF filters is reviewed. We highlight the use of a low-loss, high-index-contrast stoichiometric silicon nitride waveguide which promises to serve as a practical material platform for realizing high-performance optical signal processors and points toward photonic RF filters with digital signal processing (DSP)-level flexibility, hundreds-GHz bandwidth, MHz-band frequency selectivity, and full system integration on a chip scale.

The Panda Strip Asic: Pasta

NASA Astrophysics Data System (ADS)

Lai, A.

2018-01-01

PASTA is the 64 channel front-end chip, designed in a 110 nm CMOS technology to read out the strip sensors of the Micro Vertex Detector (MVD) of the PANDA experiment. This chip provides high resolution timestamp and deposited charge information by means of the time-over-threshold technique. Its working principle is based on a predecessor, the TOFPET ASIC, that was designed for medical applications. A general restructuring of the architecture was needed, in order to meet the specific requirements imposed by the physics programme of PANDA, especially in terms of radiation tolerance, spatial constraints, and readout in absence of a first level hardware trigger. The first revision of PASTA is currently under evaluation at the Forschungszentrum Jülich, where a data acquisition system dedicated to the MVD prototypes has been developed. This paper describes the main aspect of the chip design, gives an overview of the data acquisition system used for the verification, and shows the first results regarding the performance of PASTA.

Digital front end electronics design for the EUSO photon detector

NASA Astrophysics Data System (ADS)

Musico, P.; Pallavicini, M.; Petrolini, A.; Pratolongo, F.

2003-09-01

In this paper we will present the design status of the Digital Front End Electronic system (DFEE), that will be used for the EUSO photon detector. The DFEE is able to count the single photoelectrons coming form the detector for a given time period, store the numbers in a memory buffer and read them out after a trigger, using a serial communication line. Because of space, mass and power consumption constraints, the system will be implemented in an ASIC using a deep submicron technology. The actual design follows the original ideas of the system, though adding several new functionalities. A fully functional prototype chip has been submitted for fabrication in fall 2002. Extensive tests will be performed on it both with bench instrumentations and with the real sensor (the multi anode photomultiplier Hamamatsu R7600-M64), expecting significant results by early Summer 2003. Future work is needed to convert the design into a more robust RAD-hard technology, suitable for space applications and to include in the final die an additional circuit used to optimize the performances at high photons rates: the Analog Front End Electronics (AFEE). Moreover the base board used to house the multi anode photomultipliers is presented: it is the back-bone of the microcell and will be the basic block used to build up the EUSO focal surface.

A SAR-ADC using unit bridge capacitor and with calibration for the front-end electronics of PET imaging

NASA Astrophysics Data System (ADS)

Liu, Wei; Wei, Tingcun; Li, Bo; Yang, Lifeng; Xue, Feifei; Hu, Yongcai

2016-05-01

This paper presents a 12-bit 1 MS/s successive approximation register-analog to digital converter (SAR-ADC) for the 32-channel front-end electronics of CZT-based PET imaging system. To reduce the capacitance mismatch, instead of the fractional capacitor, the unit capacitor is used as the bridge capacitor in the split-capacitor digital to analog converter (DAC) circuit. In addition, in order to eliminate the periodical DNL errors of -1 LSB which often exists in the SAR-ADC using the charge-redistributed DAC, a calibration algorithm is proposed and verified by the experiments. The proposed 12-bit 1 MS/s SAR-ADC is designed and implemented using a 0.35 μm CMOS technology, it occupies only an active area of 986×956 μm2. The measurement results show that, at the power supply of 3.3/5.0 V and the sampling rate of 1 MS/s, the ADC with calibration has a signal-to-noise-and-distortion ratio (SINAD) of 67.98 dB, the power dissipation of 5 mW, and a figure of merit (FOM) of 2.44 pJ/conv.-step. This ADC is with the features of high accuracy, low power and small layout area, it is especially suitable to the one-chip integration of the front-end readout electronics.

Geometric correction methods for Timepix based large area detectors

NASA Astrophysics Data System (ADS)

Zemlicka, J.; Dudak, J.; Karch, J.; Krejci, F.

2017-01-01

X-ray micro radiography with the hybrid pixel detectors provides versatile tool for the object inspection in various fields of science. It has proven itself especially suitable for the samples with low intrinsic attenuation contrast (e.g. soft tissue in biology, plastics in material sciences, thin paint layers in cultural heritage, etc.). The limited size of single Medipix type detector (1.96 cm2) was recently overcome by the construction of large area detectors WidePIX assembled of Timepix chips equipped with edgeless silicon sensors. The largest already built device consists of 100 chips and provides fully sensitive area of 14.3 × 14.3 cm2 without any physical gaps between sensors. The pixel resolution of this device is 2560 × 2560 pixels (6.5 Mpix). The unique modular detector layout requires special processing of acquired data to avoid occurring image distortions. It is necessary to use several geometric compensations after standard corrections methods typical for this type of pixel detectors (i.e. flat-field, beam hardening correction). The proposed geometric compensations cover both concept features and particular detector assembly misalignment of individual chip rows of large area detectors based on Timepix assemblies. The former deals with larger border pixels in individual edgeless sensors and their behaviour while the latter grapple with shifts, tilts and steps between detector rows. The real position of all pixels is defined in Cartesian coordinate system and together with non-binary reliability mask it is used for the final image interpolation. The results of geometric corrections for test wire phantoms and paleo botanic material are presented in this article.

Imaging Spectrometer on a Chip

NASA Technical Reports Server (NTRS)

Wang, Yu; Pain, Bedabrata; Cunningham, Thomas; Zheng, Xinyu

2007-01-01

A proposed visible-light imaging spectrometer on a chip would be based on the concept of a heterostructure comprising multiple layers of silicon-based photodetectors interspersed with long-wavelength-pass optical filters. In a typical application, this heterostructure would be replicated in each pixel of an image-detecting integrated circuit of the active-pixel-sensor type (see figure). The design of the heterostructure would exploit the fact that within the visible portion of the spectrum, the characteristic depth of penetration of photons increases with wavelength. Proceeding from the front toward the back, each successive long-wavelength-pass filter would have a longer cutoff wavelength, and each successive photodetector would be made thicker to enable it to absorb a greater proportion of incident longer-wavelength photons. Incident light would pass through the first photodetector and encounter the first filter, which would reflect light having wavelengths shorter than its cutoff wavelength and pass light of longer wavelengths. A large portion of the incident and reflected shorter-wavelength light would be absorbed in the first photodetector. The light that had passed through the first photodetector/filter pair of layers would pass through the second photodetector and encounter the second filter, which would reflect light having wavelengths shorter than its cutoff wavelength while passing light of longer wavelengths. Thus, most of the light reflected by the second filter would lie in the wavelength band between the cutoff wavelengths of the first and second filters. Thus, further, most of the light absorbed in the second photodetector would lie in this wavelength band. In a similar manner, each successive photodetector would detect, predominantly, light in a successively longer wavelength band bounded by the shorter cutoff wavelength of the preceding filter and the longer cutoff wavelength of the following filter.

Maximizing Computational Capability with Minimal Power

DTIC Science & Technology

2009-03-01

Chip -Scale Energy and Power... and Heat Report Documentation Page Form ApprovedOMB No. 0704-0188 Public reporting burden for the collection of...OpticalBench Mounting Posts Imager Chip LCDinterfaced withthecomputer P o l a r i z e r P o l a r i z e r XYZ Translator Optical Slide VMM Computational Pixel...Signal routing power / memory: ? Power does not include comm off chip (i.e. accessing memory) Power = ½ C Vdd2 f for CMOS Chip to Chip (10pF load min

An Inductively-Powered Wireless Neural Recording System with a Charge Sampling Analog Front-End

PubMed Central

Lee, Seung Bae; Lee, Byunghun; Kiani, Mehdi; Mahmoudi, Babak; Gross, Robert; Ghovanloo, Maysam

2015-01-01

An inductively-powered wireless integrated neural recording system (WINeR-7) is presented for wireless and battery less neural recording from freely-behaving animal subjects inside a wirelessly-powered standard homecage. The WINeR-7 system employs a novel wide-swing dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which performs amplification, filtering, sampling, and analog-to-time conversion (ATC) with minimal interference and small amount of power. The output of the DSCS-AFE produces a pseudo-digital pulse width modulated (PWM) signal. A circular shift register (CSR) time division multiplexes (TDM) the PWM pulses to create a TDM-PWM signal, which is fed into an on-chip 915 MHz transmitter (Tx). The AFE and Tx are supplied at 1.8 V and 4.2 V, respectively, by a power management block, which includes a high efficiency active rectifier and automatic resonance tuning (ART), operating at 13.56 MHz. The 8-ch system-on-a-chip (SoC) was fabricated in a 0.35-μm CMOS process, occupying 5.0 × 2.5 mm2 and consumed 51.4 mW. For each channel, the sampling rate is 21.48 kHz and the power consumption is 19.3 μW. In vivo experiments were conducted on freely behaving rats in an energized homecage by continuously delivering 51.4 mW to the WINeR-7 system in a closed-loop fashion and recording local field potentials (LFP). PMID:27069422

An Inductively-Powered Wireless Neural Recording System with a Charge Sampling Analog Front-End.

PubMed

Lee, Seung Bae; Lee, Byunghun; Kiani, Mehdi; Mahmoudi, Babak; Gross, Robert; Ghovanloo, Maysam

2016-01-15

An inductively-powered wireless integrated neural recording system (WINeR-7) is presented for wireless and battery less neural recording from freely-behaving animal subjects inside a wirelessly-powered standard homecage. The WINeR-7 system employs a novel wide-swing dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which performs amplification, filtering, sampling, and analog-to-time conversion (ATC) with minimal interference and small amount of power. The output of the DSCS-AFE produces a pseudo-digital pulse width modulated (PWM) signal. A circular shift register (CSR) time division multiplexes (TDM) the PWM pulses to create a TDM-PWM signal, which is fed into an on-chip 915 MHz transmitter (Tx). The AFE and Tx are supplied at 1.8 V and 4.2 V, respectively, by a power management block, which includes a high efficiency active rectifier and automatic resonance tuning (ART), operating at 13.56 MHz. The 8-ch system-on-a-chip (SoC) was fabricated in a 0.35-μm CMOS process, occupying 5.0 × 2.5 mm 2 and consumed 51.4 mW. For each channel, the sampling rate is 21.48 kHz and the power consumption is 19.3 μW. In vivo experiments were conducted on freely behaving rats in an energized homecage by continuously delivering 51.4 mW to the WINeR-7 system in a closed-loop fashion and recording local field potentials (LFP).

Design and Measurement of a Low-Noise 64-Channels Front-End Readout ASIC for CdZnTe Detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gan, Bo; Wei, Tingcun; Gao, Wu

Cadmium zinc telluride (CdZnTe) detectors, as one of the principal detectors for the next-generation X-ray and γ-ray imagers, have high energy resolution and supporting electrode patterning in the radiation environment at room-temperature. In the present, a number of internationally renowned research institutions and universities are actively using these detector systems to carry out researches of energy spectrum analysis, medical imaging, materials characterization, high-energy physics, nuclear plant monitoring, and astrophysics. As the most important part of the readout system for the CdZnTe detector, the front-end readout application specific integrated circuit (ASIC) would have an important impact on the performances of themore » whole detector system. In order to ensure the small signal to noise ratio (SNR) and sufficient range of the output signal, it is necessary to design a front-end readout ASIC with very low noise and very high dynamic range. In addition, radiation hardness should be considered when the detectors are utilized in the space applications and high energy physics experiments. In this paper, we present measurements and performances of a novel multi-channel radiation-hardness low-noise front-end readout ASIC for CdZnTe detectors. The readout circuits in each channel consist of charge sensitive amplifier, leakage current compensation circuit (LCC), CR-RC shaper, S-K filter, inverse proportional amplifier, peak detect and hold circuit (PDH), discriminator and trigger logic, time sequence control circuit and driving buffer. All of 64 readout channels' outputs enter corresponding inputs of a 64 channel multiplexer. The output of the mux goes directly out of the chip via the output buffer. The 64-channel readout ASIC is implemented using the TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 2.7 mm x 8 mm. At room temperature, the equivalent noise level of a typical channel reaches 66 e{sup -} (rms) at zero farad for a power consumption of 8 mW per channel. The linearity error is lower than 1% and the overall gain of the readout channel is 165 V/pC. The crosstalk between the channels is less than 3%. By connecting the readout ASIC to a CdZnTe detector, we obtained a γ-ray spectrum, the energy resolution is 5.1% at the 59.5-keV line of {sup 241}Am source. (authors)« less

Direct reading of charge multipliers with a self-triggering CMOS analog chip with 105 k pixels at 50 μm pitch

NASA Astrophysics Data System (ADS)

Bellazzini, R.; Spandre, G.; Minuti, M.; Baldini, L.; Brez, A.; Cavalca, F.; Latronico, L.; Omodei, N.; Massai, M. M.; Sgro', C.; Costa, E.; Soffitta, P.; Krummenacher, F.; de Oliveira, R.

2006-10-01

We report on a large area (15×15 mm2), high channel density (470 pixel/mm2), self-triggering CMOS analog chip that we have developed as a pixelized charge collecting electrode of a Micropattern Gas Detector. This device represents a big step forward both in terms of size and performance, and is in fact the last version of three generations of custom ASICs of increasing complexity. The top metal layer of the CMOS pixel array is patterned in a matrix of 105,600 hexagonal pixels with a 50 μm pitch. Each pixel is directly connected to the underlying full electronics chain which has been realized in the remaining five metal and single poly-silicon layers of a 0.18 μm VLSI technology. The chip, which has customizable self-triggering capabilities, also includes a signal pre-processing function for the automatic localization of the event coordinates. Thanks to these advances it is possible to significantly reduce the read-out time and the data volume by limiting the signal output only to those pixels belonging to the region of interest. In addition to the reduced read-out time and data volume, the very small pixel area and the use of a deep sub-micron CMOS technology has allowed bringing the noise down to 50 electrons ENC. Results from in depth tests of this device when coupled to a fine pitch (50 μm on a triangular pattern) Gas Electron Multiplier are presented. It was found that matching the read-out and gas amplification pitch allows getting optimal results. The experimental detector response to polarized and unpolarized X-ray radiation when working with two gas mixtures and two different photon energies is shown and the application of this detector for Astronomical X-ray Polarimetry is discussed. Results from a full Monte-Carlo simulation for several galactic and extragalactic astronomical sources are also reported.

Use of high-granularity CdZnTe pixelated detectors to correct response non-uniformities caused by defects in crystals

DOE PAGES

Bolotnikov, A. E.; Camarda, G. S.; Cui, Y.; ...

2015-09-06

Following our successful demonstration of the position-sensitive virtual Frisch-grid detectors, we investigated the feasibility of using high-granularity position sensing to correct response non-uniformities caused by the crystal defects in CdZnTe (CZT) pixelated detectors. The development of high-granularity detectors able to correct response non-uniformities on a scale comparable to the size of electron clouds opens the opportunity of using unselected off-the-shelf CZT material, whilst still assuring high spectral resolution for the majority of the detectors fabricated from an ingot. Here, we present the results from testing 3D position-sensitive 15×15×10 mm 3 pixelated detectors, fabricated with conventional pixel patterns with progressively smallermore » pixel sizes: 1.4, 0.8, and 0.5 mm. We employed the readout system based on the H3D front-end multi-channel ASIC developed by BNL's Instrumentation Division in collaboration with the University of Michigan. We use the sharing of electron clouds among several adjacent pixels to measure locations of interaction points with sub-pixel resolution. By using the detectors with small-pixel sizes and a high probability of the charge-sharing events, we were able to improve their spectral resolutions in comparison to the baseline levels, measured for the 1.4-mm pixel size detectors with small fractions of charge-sharing events. These results demonstrate that further enhancement of the performance of CZT pixelated detectors and reduction of costs are possible by using high spatial-resolution position information of interaction points to correct the small-scale response non-uniformities caused by crystal defects present in most devices.« less

Ultrasound phase rotation beamforming on multi-core DSP.

PubMed

Ma, Jieming; Karadayi, Kerem; Ali, Murtaza; Kim, Yongmin

2014-01-01

Phase rotation beamforming (PRBF) is a commonly-used digital receive beamforming technique. However, due to its high computational requirement, it has traditionally been supported by hardwired architectures, e.g., application-specific integrated circuits (ASICs) or more recently field-programmable gate arrays (FPGAs). In this study, we investigated the feasibility of supporting software-based PRBF on a multi-core DSP. To alleviate the high computing requirement, the analog front-end (AFE) chips integrating quadrature demodulation in addition to analog-to-digital conversion were defined and used. With these new AFE chips, only delay alignment and phase rotation need to be performed by DSP, substantially reducing the computational load. We implemented the delay alignment and phase rotation modules on a Texas Instruments C6678 DSP with 8 cores. We found it takes 200 μs to beamform 2048 samples from 64 channels using 2 cores. With 4 cores, 20 million samples can be beamformed in one second. Therefore, ADC frequencies up to 40 MHz with 2:1 decimation in AFE chips or up to 20 MHz with no decimation can be supported as long as the ADC-to-DSP I/O requirement can be met. The remaining 4 cores can work on back-end processing tasks and applications, e.g., color Doppler or ultrasound elastography. One DSP being able to handle both beamforming and back-end processing could lead to low-power and low-cost ultrasound machines, benefiting ultrasound imaging in general, particularly portable ultrasound machines. Copyright © 2013 Elsevier B.V. All rights reserved.

High responsivity CMOS imager pixel implemented in SOI technology

NASA Technical Reports Server (NTRS)

Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

2000-01-01

Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

Readout of the upgraded ALICE-ITS

NASA Astrophysics Data System (ADS)

Szczepankiewicz, A.; ALICE Collaboration

2016-07-01

The ALICE experiment will undergo a major upgrade during the second long shutdown of the CERN LHC. As part of this program, the present Inner Tracking System (ITS), which employs different layers of hybrid pixels, silicon drift and strip detectors, will be replaced by a completely new tracker composed of seven layers of monolithic active pixel sensors. The upgraded ITS will have more than twelve billion pixels in total, producing 300 Gbit/s of data when tracking 50 kHz Pb-Pb events. Two families of pixel chips realized with the TowerJazz CMOS imaging process have been developed as candidate sensors: the ALPIDE, which uses a proprietary readout and sparsification mechanism and the MISTRAL-O, based on a proven rolling shutter architecture. Both chips can operate in continuous mode, with the ALPIDE also supporting triggered operations. As the communication IP blocks are shared among the two chip families, it has been possible to develop a common Readout Electronics. All the sensor components (analog stages, state machines, buffers, FIFOs, etc.) have been modelled in a system level simulation, which has been extensively used to optimize both the sensor and the whole readout chain design in an iterative process. This contribution covers the progress of the R&D efforts and the overall expected performance of the ALICE-ITS readout system.

Radiation hardness and timing studies of a monolithic TowerJazz pixel design for the new ATLAS Inner Tracker

NASA Astrophysics Data System (ADS)

Riegel, C.; Backhaus, M.; Van Hoorne, J. W.; Kugathasan, T.; Musa, L.; Pernegger, H.; Riedler, P.; Schaefer, D.; Snoeys, W.; Wagner, W.

2017-01-01

A part of the upcoming HL-LHC upgrade of the ATLAS Detector is the construction of a new Inner Tracker. This upgrade opens new possibilities, but also presents challenges in terms of occupancy and radiation tolerance. For the pixel detector inside the inner tracker, hybrid modules containing passive silicon sensors and connected readout chips are presently used, but require expensive assembly techniques like fine-pitch bump bonding. Silicon devices fabricated in standard commercial CMOS technologies, which include part or all of the readout chain, are also investigated offering a reduced cost as they are cheaper per unit area than traditional silicon detectors. If they contain the full readout chain, as for a fully monolithic approach, there is no need for the expensive flip-chip assembly, resulting in a further cost reduction and material savings. In the outer pixel layers of the ATLAS Inner Tracker, the pixel sensors must withstand non-ionising energy losses of up to 1015 n/cm2 and offer a timing resolution of 25 ns or less. This paper presents test results obtained on a monolithic test chip, the TowerJazz 180nm Investigator, towards these specifications. The presented program of radiation hardness and timing studies has been launched to investigate this technology's potential for the new ATLAS Inner Tracker.

Hybrid UV Imager Containing Face-Up AlGaN/GaN Photodiodes

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Pain, Bedabrata

2005-01-01

A proposed hybrid ultraviolet (UV) image sensor would comprise a planar membrane array of face-up AlGaN/GaN photodiodes integrated with a complementary metal oxide/semiconductor (CMOS) readout-circuit chip. Each pixel in the hybrid image sensor would contain a UV photodiode on the AlGaN/GaN membrane, metal oxide/semiconductor field-effect transistor (MOSFET) readout circuitry on the CMOS chip underneath the photodiode, and a metal via connection between the photodiode and the readout circuitry (see figure). The proposed sensor design would offer all the advantages of comparable prior CMOS active-pixel sensors and AlGaN UV detectors while overcoming some of the limitations of prior (AlGaN/sapphire)/CMOS hybrid image sensors that have been designed and fabricated according to the methodology of flip-chip integration. AlGaN is a nearly ideal UV-detector material because its bandgap is wide and adjustable and it offers the potential to attain extremely low dark current. Integration of AlGaN with CMOS is necessary because at present there are no practical means of realizing readout circuitry in the AlGaN/GaN material system, whereas the means of realizing readout circuitry in CMOS are well established. In one variant of the flip-chip approach to integration, an AlGaN chip on a sapphire substrate is inverted (flipped) and then bump-bonded to a CMOS readout circuit chip; this variant results in poor quantum efficiency. In another variant of the flip-chip approach, an AlGaN chip on a crystalline AlN substrate would be bonded to a CMOS readout circuit chip; this variant is expected to result in narrow spectral response, which would be undesirable in many applications. Two other major disadvantages of flip-chip integration are large pixel size (a consequence of the need to devote sufficient area to each bump bond) and severe restriction on the photodetector structure. The membrane array of AlGaN/GaN photodiodes and the CMOS readout circuit for the proposed image sensor would be fabricated separately.

Laser doppler blood flow imaging using a CMOS imaging sensor with on-chip signal processing.

PubMed

He, Diwei; Nguyen, Hoang C; Hayes-Gill, Barrie R; Zhu, Yiqun; Crowe, John A; Gill, Cally; Clough, Geraldine F; Morgan, Stephen P

2013-09-18

The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue.

High-speed high-resolution epifluorescence imaging system using CCD sensor and digital storage for neurobiological research

NASA Astrophysics Data System (ADS)

Takashima, Ichiro; Kajiwara, Riichi; Murano, Kiyo; Iijima, Toshio; Morinaka, Yasuhiro; Komobuchi, Hiroyoshi

2001-04-01

We have designed and built a high-speed CCD imaging system for monitoring neural activity in an exposed animal cortex stained with a voltage-sensitive dye. Two types of custom-made CCD sensors were developed for this system. The type I chip has a resolution of 2664 (H) X 1200 (V) pixels and a wide imaging area of 28.1 X 13.8 mm, while the type II chip has 1776 X 1626 pixels and an active imaging area of 20.4 X 18.7 mm. The CCD arrays were constructed with multiple output amplifiers in order to accelerate the readout rate. The two chips were divided into either 24 (I) or 16 (II) distinct areas that were driven in parallel. The parallel CCD outputs were digitized by 12-bit A/D converters and then stored in the frame memory. The frame memory was constructed with synchronous DRAM modules, which provided a capacity of 128 MB per channel. On-chip and on-memory binning methods were incorporated into the system, e.g., this enabled us to capture 444 X 200 pixel-images for periods of 36 seconds at a rate of 500 frames/second. This system was successfully used to visualize neural activity in the cortices of rats, guinea pigs, and monkeys.

A 256×256 low-light-level CMOS imaging sensor with digital CDS

NASA Astrophysics Data System (ADS)

Zou, Mei; Chen, Nan; Zhong, Shengyou; Li, Zhengfen; Zhang, Jicun; Yao, Li-bin

2016-10-01

In order to achieve high sensitivity for low-light-level CMOS image sensors (CIS), a capacitive transimpedance amplifier (CTIA) pixel circuit with a small integration capacitor is used. As the pixel and the column area are highly constrained, it is difficult to achieve analog correlated double sampling (CDS) to remove the noise for low-light-level CIS. So a digital CDS is adopted, which realizes the subtraction algorithm between the reset signal and pixel signal off-chip. The pixel reset noise and part of the column fixed-pattern noise (FPN) can be greatly reduced. A 256×256 CIS with CTIA array and digital CDS is implemented in the 0.35μm CMOS technology. The chip size is 7.7mm×6.75mm, and the pixel size is 15μm×15μm with a fill factor of 20.6%. The measured pixel noise is 24LSB with digital CDS in RMS value at dark condition, which shows 7.8× reduction compared to the image sensor without digital CDS. Running at 7fps, this low-light-level CIS can capture recognizable images with the illumination down to 0.1lux.

A new high dynamic range ROIC with smart light intensity control unit

NASA Astrophysics Data System (ADS)

Yazici, Melik; Ceylan, Omer; Shafique, Atia; Abbasi, Shahbaz; Galioglu, Arman; Gurbuz, Yasar

2017-05-01

This journal presents a new high dynamic range ROIC with smart pixel which consists of two pre-amplifiers that are controlled by a circuit inside the pixel. Each pixel automatically decides which pre-amplifier is used according to the incoming illumination level. Instead of using single pre-amplifier, two input pre-amplifiers, which are optimized for different signal levels, are placed inside each pixel. The smart circuit mechanism, which decides the best input circuit according to the incoming light level, is also designed for each pixel. In short, an individual pixel has the ability to select the best input amplifier circuit that performs the best/highest SNR for the incoming signal level. A 32 × 32 ROIC prototype chip is designed to demonstrate the concept in 0.18 μ m CMOS technology. The prototype is optimized for NIR and SWIR bands. Instead of a detector, process variation optimized current sources are placed inside the ROIC. The chip achieves minimum 8.6 e- input referred noise and 98.9 dB dynamic range. It has the highest dynamic range in the literature in terms of analog ROICs for SWIR band. It is operating in room temperature and power consumption is 2.8 μ W per pixel.

Development of a 3D CZT detector prototype for Laue Lens telescope

NASA Astrophysics Data System (ADS)

Caroli, Ezio; Auricchio, Natalia; Del Sordo, Stefano; Abbene, Leonardo; Budtz-Jørgensen, Carl; Casini, Fabio; Curado da Silva, Rui M.; Kuvvetlli, Irfan; Milano, Luciano; Natalucci, Lorenzo; Quadrini, Egidio M.; Stephen, John B.; Ubertini, Pietro; Zanichelli, Massimiliano; Zappettini, Andrea

2010-07-01

We report on the development of a 3D position sensitive prototype suitable as focal plane detector for Laue lens telescope. The basic sensitive unit is a drift strip detector based on a CZT crystal, (~19×8 mm2 area, 2.4 mm thick), irradiated transversally to the electric field direction. The anode side is segmented in 64 strips, that divide the crystal in 8 independent sensor (pixel), each composed by one collecting strip and 7 (one in common) adjacent drift strips. The drift strips are biased by a voltage divider, whereas the anode strips are held at ground. Furthermore, the cathode is divided in 4 horizontal strips for the reconstruction of the third interaction position coordinate. The 3D prototype will be made by packing 8 linear modules, each composed by one basic sensitive unit, bonded on a ceramic layer. The linear modules readout is provided by a custom front end electronics implementing a set of three RENA-3 for a total of 128 channels. The front-end electronics and the operating logics (in particular coincidence logics for polarisation measurements) are handled by a versatile and modular multi-parametric back end electronics developed using FPGA technology.

A CMOS pixel sensor prototype for the outer layers of linear collider vertex detector

NASA Astrophysics Data System (ADS)

Zhang, L.; Morel, F.; Hu-Guo, C.; Himmi, A.; Dorokhov, A.; Hu, Y.

2015-01-01

The International Linear Collider (ILC) expresses a stringent requirement for high precision vertex detectors (VXD). CMOS pixel sensors (CPS) have been considered as an option for the VXD of the International Large Detector (ILD), one of the detector concepts proposed for the ILC. MIMOSA-31 developed at IPHC-Strasbourg is the first CPS integrated with 4-bit column-level ADC for the outer layers of the VXD, adapted to an original concept minimizing the power consumption. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal noise and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with a self-triggered analog-to-digital converter (ADC). The ADC design was optimized for power saving at a sampling frequency of 6.25 MS/s. The prototype chip is fabricated in a 0.35 μm CMOS technology. This paper presents the details of the prototype chip and its test results.

Pixel parallel localized driver design for a 128 x 256 pixel array 3D 1Gfps image sensor

NASA Astrophysics Data System (ADS)

Zhang, C.; Dao, V. T. S.; Etoh, T. G.; Charbon, E.

2017-02-01

In this paper, a 3D 1Gfps BSI image sensor is proposed, where 128 × 256 pixels are located in the top-tier chip and a 32 × 32 localized driver array in the bottom-tier chip. Pixels are designed with Multiple Collection Gates (MCG), which collects photons selectively with different collection gates being active at intervals of 1ns to achieve 1Gfps. For the drivers, a global PLL is designed, which consists of a ring oscillator with 6-stage current starved differential inverters, achieving a wide frequency tuning range from 40MHz to 360MHz (20ps rms jitter). The drivers are the replicas of the ring oscillator that operates within a PLL. Together with level shifters and XNOR gates, continuous 3.3V pulses are generated with desired pulse width, which is 1/12 of the PLL clock period. The driver array is activated by a START signal, which propagates through a highly balanced clock tree, to activate all the pixels at the same time with virtually negligible skew.

A multichip aVLSI system emulating orientation selectivity of primary visual cortical cells.

PubMed

Shimonomura, Kazuhiro; Yagi, Tetsuya

2005-07-01

In this paper, we designed and fabricated a multichip neuromorphic analog very large scale integrated (aVLSI) system, which emulates the orientation selective response of the simple cell in the primary visual cortex. The system consists of a silicon retina and an orientation chip. An image, which is filtered by a concentric center-surround (CS) antagonistic receptive field of the silicon retina, is transferred to the orientation chip. The image transfer from the silicon retina to the orientation chip is carried out with analog signals. The orientation chip selectively aggregates multiple pixels of the silicon retina, mimicking the feedforward model proposed by Hubel and Wiesel. The chip provides the orientation-selective (OS) outputs which are tuned to 0 degrees, 60 degrees, and 120 degrees. The feed-forward aggregation reduces the fixed pattern noise that is due to the mismatch of the transistors in the orientation chip. The spatial properties of the orientation selective response were examined in terms of the adjustable parameters of the chip, i.e., the number of aggregated pixels and size of the receptive field of the silicon retina. The multichip aVLSI architecture used in the present study can be applied to implement higher order cells such as the complex cell of the primary visual cortex.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kapusta, P.; Kisielewski, B.

In this paper the overvoltage protection modules (OVP) for the power supply (PS) system of the Belle II pixel detector (PXD) are described. The aim of the OVP is to protect the detector and associated electronics against overvoltage conditions. Most critical in the system are voltages supplying the front-end ASICs. The PXD detector consists of the DEPFET sensor modules with integrated chips like the Drain Current Digitizer, the Switcher and the Data Handling Processor. These chips, implemented in modern sub-micron technologies, are quite vulnerable to variations in the supply voltages. The PXD will be placed in the Belle II experimentmore » as close as possible to the interaction point, where access during experiment is very limited or even impossible, thus the PS and OVP systems exploit the remote-sensing method. Overvoltage conditions are due to failures of the PS itself, wrong setting of the output voltages or transient voltages coming out of hard noisy environment of the experiment. The OVP modules are parts of the PS modules. For powering the PXD 40 PS modules are placed 15 m outside the Belle II spectrometer. Each one is equipped with the OVP board. All voltages (22) are grouped in 4 domains: Analog, Digital, Steering and Gate which have independent grounds. The OVP boards are designed from integrated circuits from Linear Technology. All configurations were simulated with the Spice program. The control electronics is designed in a Xilinx CPLD. Two types of integrated circuits were used. LT4356 surge stopper protects loads from high voltage transients. The output voltages are limited to a safe value and also protect loads against over current faults. For less critical voltages, the LTC2912 voltage monitors are used that detect under-voltage and overvoltage events. It has to be noted that the OVP system is working independently of any other protection of the PS system, which increases its overall reliability. (authors)« less

A Medipix3 readout system based on the National Instruments FlexRIO card and using the LabVIEW programming environment

NASA Astrophysics Data System (ADS)

Horswell, I.; Gimenez, E. N.; Marchal, J.; Tartoni, N.

2011-01-01

Hybrid silicon photon-counting detectors are becoming standard equipment for many synchrotron applications. The latest in the Medipix family of read-out chips designed as part of the Medipix Collaboration at CERN is the Medipix3, which while maintaining the same pixel size as its predecessor, offers increased functionality and operating modes. The active area of the Medipix3 chip is approx 14mm × 14mm (containing 256 × 256 pixels) which is not large enough for many detector applications, this results in the need to tile many sensors and chips. As a first step on the road to develop such a detector, it was decided to build a prototype single chip readout system to gain the necessary experience in operating a Medipix3 chip. To provide a flexible learning and development tool it was decided to build an interface based on the recently released FlexRIOTM system from National Instruments and to use the LabVIEWTM graphical programming environment. This system and the achieved performance are described in this paper.

Artificial brains. A million spiking-neuron integrated circuit with a scalable communication network and interface.

PubMed

Merolla, Paul A; Arthur, John V; Alvarez-Icaza, Rodrigo; Cassidy, Andrew S; Sawada, Jun; Akopyan, Filipp; Jackson, Bryan L; Imam, Nabil; Guo, Chen; Nakamura, Yutaka; Brezzo, Bernard; Vo, Ivan; Esser, Steven K; Appuswamy, Rathinakumar; Taba, Brian; Amir, Arnon; Flickner, Myron D; Risk, William P; Manohar, Rajit; Modha, Dharmendra S

2014-08-08

Inspired by the brain's structure, we have developed an efficient, scalable, and flexible non-von Neumann architecture that leverages contemporary silicon technology. To demonstrate, we built a 5.4-billion-transistor chip with 4096 neurosynaptic cores interconnected via an intrachip network that integrates 1 million programmable spiking neurons and 256 million configurable synapses. Chips can be tiled in two dimensions via an interchip communication interface, seamlessly scaling the architecture to a cortexlike sheet of arbitrary size. The architecture is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification. With 400-pixel-by-240-pixel video input at 30 frames per second, the chip consumes 63 milliwatts. Copyright © 2014, American Association for the Advancement of Science.

Design of integrated eye tracker-display device for head mounted systems

NASA Astrophysics Data System (ADS)

David, Y.; Apter, B.; Thirer, N.; Baal-Zedaka, I.; Efron, U.

2009-08-01

We propose an Eye Tracker/Display system, based on a novel, dual function device termed ETD, which allows sharing the optical paths of the Eye tracker and the display and on-chip processing. The proposed ETD design is based on a CMOS chip combining a Liquid-Crystal-on-Silicon (LCoS) micro-display technology with near infrared (NIR) Active Pixel Sensor imager. The ET operation allows capturing the Near IR (NIR) light, back-reflected from the eye's retina. The retinal image is then used for the detection of the current direction of eye's gaze. The design of the eye tracking imager is based on the "deep p-well" pixel technology, providing low crosstalk while shielding the active pixel circuitry, which serves the imaging and the display drivers, from the photo charges generated in the substrate. The use of the ETD in the HMD Design enables a very compact design suitable for Smart Goggle applications. A preliminary optical, electronic and digital design of the goggle and its associated ETD chip and digital control, are presented.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chumacero, E. Miguel; De Celis Alonso, B.; Martínez Hernández, M. I.

The development in semiconductor CMOS technology has enabled the creation of sensitive detectors for a wide range of ionizing radiation. These devices are suitable for photon counting and can be used in imaging and tomography X-ray diagnostics. The Medipix[1] radiation detection system is a hybrid silicon pixel chip developed for particle tracking applications in High Energy Physics. Its exceptional features (high spatial and energy resolution, embedded ultra fast readout, different operation modes, etc.) make the Medipix an attractive device for applications in medical imaging. In this work the energy characterization of a third-generation Medipix chip (Medipix3) coupled to a siliconmore » sensor is presented. We used different radiation sources (strontium 90, iron 55 and americium 241) to obtain the response curve of the hybrid detector as a function of energy. We also studied the contrast of the Medipix as a measure of pixel noise. Finally we studied the response to fluorescence X rays from different target materials (In, Pd and Cd) for the two data acquisition modes of the chip; single pixel mode and charge summing mode.« less

A proposed STAR microvertex detector using Active Pixel Sensors with some relevant studies on APS performance

NASA Astrophysics Data System (ADS)

Kleinfelder, S.; Li, S.; Bieser, F.; Gareus, R.; Greiner, L.; King, J.; Levesque, J.; Matis, H. S.; Oldenburg, M.; Ritter, H. G.; Retiere, F.; Rose, A.; Schweda, K.; Shabetai, A.; Sichtermann, E.; Thomas, J. H.; Wieman, H. H.; Bichsel, H.

2006-09-01

A vertex detector that can measure particles with charm or bottom quarks would dramatically expand the physics capability of the STAR detector at RHIC. To accomplish this, we are proposing to build the Heavy Flavor Tracker (HFT) using 2×2 cm Active Pixels Sensors (APS). Ten of these APS chips will be arranged on a ladder (0.28% of a radiation length) at radii of 1.5 and at 5.0 cm. We have examined several properties of APS chips, so that we can characterize the performance of this detector. Using 1.5 GeV/ c electrons, we have measured the charge collected and compared it to the expected charge. To achieve high efficiency, we have considered two different cluster finding algorithms and found that the choice of algorithm is dependent on noise level. We have demonstrated that a Scanning Electron Microscope can probe properties of an APS chip. In particular, we studied several position resolution algorithms. Finally, we studied the properties of pixel pitches from 5 to 30 μm.

Radiation hard programmable delay line for LHCb calorimeter upgrade

NASA Astrophysics Data System (ADS)

Mauricio, J.; Gascón, D.; Vilasís, X.; Picatoste, E.; Machefert, F.; Lefrancois, J.; Duarte, O.; Beigbeder, C.

2014-01-01

This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with less than 5 ps jitter and 23 ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end analog signal processing ASIC in the near future. The stringent noise requirements on the ASIC imply minimizing the noise contribution of digital components. This is accomplished by implementing the DLL in differential mode. To achieve the required radiation tolerance several techniques are applied: double guard rings between PMOS and NMOS transistors as well as glitch suppressors and TMR Registers. This 5.7 mm2 chip has been implemented in CMOS 0.35 μm technology.

Electronic readout system for the Belle II imaging Time-Of-Propagation detector

NASA Astrophysics Data System (ADS)

Kotchetkov, Dmitri

2017-07-01

The imaging Time-Of-Propagation (iTOP) detector, constructed for the Belle II experiment at the SuperKEKB e+e- collider, is an 8192-channel high precision Cherenkov particle identification detector with timing resolution below 50 ps. To acquire data from the iTOP, a novel front-end electronic readout system was designed, built, and integrated. Switched-capacitor array application-specific integrated circuits are used to sample analog signals. Triggering, digitization, readout, and data transfer are controlled by Xilinx Zynq-7000 system on a chip devices.

A Fully Implantable, NFC Enabled, Continuous Interstitial Glucose Monitor

PubMed Central

Anabtawi, Nijad; Freeman, Sabrina; Ferzli, Rony

2017-01-01

This work presents an integrated system-on-chip (SoC) that forms the core of a long-term, fully implantable, battery assisted, passive continuous glucose monitor. It integrates an amperometric glucose sensor interface, a near field communication (NFC) wireless front-end and a fully digital switched mode power management unit for supply regulation and on board battery charging. It uses 13.56 MHz (ISM) band to harvest energy and backscatter data to an NFC reader. System was implemented in 14nm CMOS technology and validated with post layout simulations. PMID:28702512

A Fully Implantable, NFC Enabled, Continuous Interstitial Glucose Monitor.

PubMed

Anabtawi, Nijad; Freeman, Sabrina; Ferzli, Rony

2016-02-01

This work presents an integrated system-on-chip (SoC) that forms the core of a long-term, fully implantable, battery assisted, passive continuous glucose monitor. It integrates an amperometric glucose sensor interface, a near field communication (NFC) wireless front-end and a fully digital switched mode power management unit for supply regulation and on board battery charging. It uses 13.56 MHz (ISM) band to harvest energy and backscatter data to an NFC reader. System was implemented in 14nm CMOS technology and validated with post layout simulations.

A novel model for simulating the racing effect in capillary-driven underfill process in flip chip

NASA Astrophysics Data System (ADS)

Zhu, Wenhui; Wang, Kanglun; Wang, Yan

2018-04-01

Underfill is typically applied in flip chips to increase the reliability of the electronic packagings. In this paper, the evolution of the melt-front shape of the capillary-driven underfill flow is studied through 3D numerical analysis. Two different models, the prevailing surface force model and the capillary model based on the wetted wall boundary condition, are introduced to test their applicability, where level set method is used to track the interface of the two phase flow. The comparison between the simulation results and experimental data indicates that, the surface force model produces better prediction on the melt-front shape, especially in the central area of the flip chip. Nevertheless, the two above models cannot simulate properly the racing effect phenomenon that appears during underfill encapsulation. A novel ‘dynamic pressure boundary condition’ method is proposed based on the validated surface force model. Utilizing this approach, the racing effect phenomenon is simulated with high precision. In addition, a linear relationship is derived from this model between the flow front location at the edge of the flip chip and the filling time. Using the proposed approach, the impact of the underfill-dispensing length on the melt-front shape is also studied.

Flight Qualified Micro Sun Sensor

NASA Technical Reports Server (NTRS)

Liebe, Carl Christian; Mobasser, Sohrab; Wrigley, Chris; Schroeder, Jeffrey; Bae, Youngsam; Naegle, James; Katanyoutanant, Sunant; Jerebets, Sergei; Schatzel, Donald; Lee, Choonsup

2007-01-01

A prototype small, lightweight micro Sun sensor (MSS) has been flight qualified as part of the attitude-determination system of a spacecraft or for Mars surface operations. The MSS has previously been reported at a very early stage of development in NASA Tech Briefs, Vol. 28, No. 1 (January 2004). An MSS is essentially a miniature multiple-pinhole electronic camera combined with digital processing electronics that functions analogously to a sundial. A micromachined mask containing a number of microscopic pinholes is mounted in front of an active-pixel sensor (APS). Electronic circuits for controlling the operation of the APS, readout from the pixel photodetectors, and analog-to-digital conversion are all integrated onto the same chip along with the APS. The digital processing includes computation of the centroids of the pinhole Sun images on the APS. The spacecraft computer has the task of converting the Sun centroids into Sun angles utilizing a calibration polynomial. The micromachined mask comprises a 500-micron-thick silicon wafer, onto which is deposited a 57-nm-thick chromium adhesion- promotion layer followed by a 200-nm-thick gold light-absorption layer. The pinholes, 50 microns in diameter, are formed in the gold layer by photolithography. The chromium layer is thin enough to be penetrable by an amount of Sunlight adequate to form measurable pinhole images. A spacer frame between the mask and the APS maintains a gap of .1 mm between the pinhole plane and the photodetector plane of the APS. To minimize data volume, mass, and power consumption, the digital processing of the APS readouts takes place in a single field-programmable gate array (FPGA). The particular FPGA is a radiation- tolerant unit that contains .32,000 gates. No external memory is used so the FPGA calculates the centroids in real time as pixels are read off the APS with minimal internal memory. To enable the MSS to fit into a small package, the APS, the FPGA, and other components are mounted on a single two-sided board following chip-on-board design practices

Germanium ``hexa'' detector: production and testing

NASA Astrophysics Data System (ADS)

Sarajlić, M.; Pennicard, D.; Smoljanin, S.; Hirsemann, H.; Struth, B.; Fritzsch, T.; Rothermund, M.; Zuvic, M.; Lampert, M. O.; Askar, M.; Graafsma, H.

2017-01-01

Here we present new result on the testing of a Germanium sensor for X-ray radiation. The system is made of 3 × 2 Medipix3RX chips, bump-bonded to a monolithic sensor, and is called ``hexa''. Its dimensions are 45 × 30 mm2 and the sensor thickness was 1.5 mm. The total number of the pixels is 393216 in the matrix 768 × 512 with pixel pitch 55 μ m. Medipix3RX read-out chip provides photon counting read-out with single photon sensitivity. The sensor is cooled to -126°C and noise levels together with flat field response are measured. For -200 V polarization bias, leakage current was 4.4 mA (3.2 μ A/mm2). Due to higher leakage around 2.5% of all pixels stay non-responsive. More than 99% of all pixels are bump bonded correctly. In this paper we present the experimental set-up, threshold equalization procedure, image acquisition and the technique for bump bond quality estimate.

A Compact Polarization Imager

NASA Technical Reports Server (NTRS)

Thompson, Karl E.; Rust, David M.; Chen, Hua

1995-01-01

A new type of image detector has been designed to analyze the polarization of light simultaneously at all picture elements (pixels) in a scene. The Integrated Dual Imaging Detector (IDID) consists of a polarizing beamsplitter bonded to a custom-designed charge-coupled device with signal-analysis circuitry, all integrated on a silicon chip. The IDID should simplify the design and operation of imaging polarimeters and spectroscopic imagers used, for example, in atmospheric and solar research. Other applications include environmental monitoring and robot vision. Innovations in the IDID include two interleaved 512 x 1024 pixel imaging arrays (one for each polarization plane), large dynamic range (well depth of 10(exp 6) electrons per pixel), simultaneous readout and display of both images at 10(exp 6) pixels per second, and on-chip analog signal processing to produce polarization maps in real time. When used with a lithium niobate Fabry-Perot etalon or other color filter that can encode spectral information as polarization, the IDID can reveal tiny differences between simultaneous images at two wavelengths.

CMOS active pixel sensor type imaging system on a chip

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Nixon, Robert (Inventor)

2011-01-01

A single chip camera which includes an .[.intergrated.]. .Iadd.integrated .Iaddend.image acquisition portion and control portion and which has double sampling/noise reduction capabilities thereon. Part of the .[.intergrated.]. .Iadd.integrated .Iaddend.structure reduces the noise that is picked up during imaging.

Sparsely-Bonded CMOS Hybrid Imager

NASA Technical Reports Server (NTRS)

Sun, Chao (Inventor); Jones, Todd J. (Inventor); Nikzad, Shouleh (Inventor); Newton, Kenneth W. (Inventor); Cunningham, Thomas J. (Inventor); Hancock, Bruce R. (Inventor); Dickie, Matthew R. (Inventor); Hoenk, Michael E. (Inventor); Wrigley, Christopher J. (Inventor); Pain, Bedabrata (Inventor)

2015-01-01

A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.

The front-end electronics and slow control of large area SiPM for the SST-1M camera developed for the CTA experiment

NASA Astrophysics Data System (ADS)

Aguilar, J. A.; Bilnik, W.; Borkowski, J.; Cadoux, F.; Christov, A.; della Volpe, D.; Favre, Y.; Heller, M.; Kasperek, J.; Lyard, E.; Marszałek, A.; Moderski, R.; Montaruli, T.; Porcelli, A.; Prandini, E.; Rajda, P.; Rameez, M.; Schioppa, E.; Troyano Pujadas, I.; Ziȩtara, K.; Błocki, J.; Bogacz, L.; Bulik, T.; Curyło, M.; Dyrda, M.; Frankowski, A.; Grudniki, Ł.; Grudzińska, M.; Idźkowski, B.; Jamrozy, M.; Janiak, M.; Lalik, K.; Mach, E.; Mandat, D.; Michałowski, J.; Neronov, A.; Niemiec, J.; Ostrowski, M.; Paśsko, P.; Pech, M.; Schovanek, P.; Seweryn, K.; Skowron, K.; Sliusar, V.; Sowiński, M.; Stawarz, Ł.; Stodulska, M.; Stodulski, M.; Toscano, S.; Walter, R.; Wiȩcek, M.; Zagdański, A.; Żychowski, P.

2016-09-01

The single mirror Small Size Telescope (SST-1M) is one of the proposed designs for the smallest type of telescopes, SSTs that will compose the Cherenkov Telescope Array (CTA). The SST-1M camera will use Silicon PhotoMultipliers (SiPM) which are nowadays commonly used in High Energy Physics experiments and many imaging applications. However the unique pixel shape and size have required a dedicated development by the University of Geneva and Hamamatsu. The resulting sensor has a surface of ∼94 mm2 and a total capacitance of ∼3.4 nF. These unique characteristics, combined with the stringent requirements of the CTA project on timing and charge resolution have led the University of Geneva to develop custom front-end electronics. The preamplifier stage has been tailored in order to optimize the signal shape using measurement campaigns and electronic simulation of the sensor. A dedicated trans-impedance pre-amplifier topology is used resulting in a power consumption of 400 mW per pixel and a pulse width < 30 ns. The measurements that have led to the choice of the different components and the resulting performance are detailed in this paper. The slow control electronics was designed to provide the bias voltage with 6.7 mV precision and to correct for temperature variation with a forward feedback compensation with 0.17 °C resolution. It is fully configurable and can be monitored using CANbus interface. The architecture and the characterization of the various elements are presented.

A radiation detector design mitigating problems related to sawed edges

NASA Astrophysics Data System (ADS)

Aurola, A.; Marochkin, V.; Tuuva, T.

2014-12-01

In pixelated silicon radiation detectors that are utilized for the detection of UV, visible, and in particular Near Infra-Red (NIR) light it is desirable to utilize a relatively thick fully depleted Back-Side Illuminated (BSI) detector design providing 100% Fill Factor (FF), low Cross-Talk (CT), and high Quantum Efficiency (QE). The optimal thickness of such detectors is typically less than 300μm and above 40μm and thus it is more or less mandatory to thin the detector wafer from the backside after the front side of the detector has been processed and before a conductive layer is formed on the backside. A TAIKO thinning process is optimal for such a thickness range since neither a support substrate on the front side nor lithographic steps on the backside are required. The conductive backside layer should, however, be homogenous throughout the wafer and it should be biased from the front side of the detector. In order to provide good QE for blue and UV light the conductive backside layer should be of opposite doping type than the substrate. The problem with a homogeneous backside layer being of opposite doping type than the substrate is that a lot of leakage current is typically generated at the sawed chip edges, which may increase the dark noise and the power consumption. These problems are substantially mitigated with a proposed detector edge arrangement which 2D simulation results are presented in this paper.

A multi-year survey of stem-end chip defect in chipping potatoes (Solanum tuberosum L.)

USDA-ARS?s Scientific Manuscript database

One of the most serious tuber quality concerns of US chip potato growers is stem-end chip defect, which is defined as a localized post-fry discoloration in and adjacent to the vasculature on the stem end portion of potato chips. The incidence and severity of stem-end chip defect vary with growing lo...

Tritium autoradiography with thinned and back-side illuminated monolithic active pixel sensor device

NASA Astrophysics Data System (ADS)

Deptuch, G.

2005-05-01

The first autoradiographic results of the tritium ( 3H) marked source obtained with monolithic active pixel sensors are presented. The detector is a high-resolution, back-side illuminated imager, developed within the SUCIMA collaboration for low-energy (<30 keV) electrons detection. The sensitivity to these energies is obtained by thinning the detector, originally fabricated in the form of a standard VLSI chip, down to the thickness of the epitaxial layer. The detector used is the 1×10 6 pixel, thinned MIMOSA V chip. The low noise performance and thin (˜160 nm) entrance window provide the sensitivity of the device to energies as low as ˜4 keV. A polymer tritium source was parked directly atop the detector in open-air conditions. A real-time image of the source was obtained.

Design of a Low-Light-Level Image Sensor with On-Chip Sigma-Delta Analog-to- Digital Conversion

NASA Technical Reports Server (NTRS)

Mendis, Sunetra K.; Pain, Bedabrata; Nixon, Robert H.; Fossum, Eric R.

1993-01-01

The design and projected performance of a low-light-level active-pixel-sensor (APS) chip with semi-parallel analog-to-digital (A/D) conversion is presented. The individual elements have been fabricated and tested using MOSIS* 2 micrometer CMOS technology, although the integrated system has not yet been fabricated. The imager consists of a 128 x 128 array of active pixels at a 50 micrometer pitch. Each column of pixels shares a 10-bit A/D converter based on first-order oversampled sigma-delta (Sigma-Delta) modulation. The 10-bit outputs of each converter are multiplexed and read out through a single set of outputs. A semi-parallel architecture is chosen to achieve 30 frames/second operation even at low light levels. The sensor is designed for less than 12 e^- rms noise performance.

iPadPix—A novel educational tool to visualise radioactivity measured by a hybrid pixel detector

NASA Astrophysics Data System (ADS)

Keller, O.; Schmeling, S.; Müller, A.; Benoit, M.

2016-11-01

With the ability to attribute signatures of ionising radiation to certain particle types, pixel detectors offer a unique advantage over the traditional use of Geiger-Müller tubes also in educational settings. We demonstrate in this work how a Timepix readout chip combined with a standard 300μm pixelated silicon sensor can be used to visualise radioactivity in real-time and by means of augmented reality. The chip family is the result of technology transfer from High Energy Physics at CERN and facilitated by the Medipix Collaboration. This article summarises the development of a prototype based on an iPad mini and open source software detailed in ref. [1]. Appropriate experimental activities that explore natural radioactivity and everyday objects are given to demonstrate the use of this new tool in educational settings.

Section 1: Interfacial reactions and grain growth in ferroelectric SrBi{sub 2}Ta{sub 2}O (SBT) thin films on Si substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dickerson, B.D.; Zhang, X.; Desu, S.B.

1997-04-01

Much of the cost of traditional infrared cameras based on narrow-bandgap photoelectric semiconductors comes from the cryogenic cooling systems required to achieve high detectivity. Detectivity is inversely proportional to noise. Generation-recombination noise in photoelectric detectors increases roughly exponentially with temperature, but thermal noise in photoelectric detectors increases only linearly with temperature. Therefore `thermal detectors perform far better at room temperature than 8-14 {mu}m photon detectors.` Although potentially more affordable, uncooled pyroelectric cameras are less sensitive than cryogenic photoelectric cameras. One way to improve the sensitivity to cost ratio is to deposit ferroelectric pixels with good electrical properties directly on mass-produced,more » image-processing chips. `Good` properties include a strong temperature dependence of the remanent polarization, P{sub r}, or the relative dielectric constant, {epsilon}{sub r}, for sensitive operation in pyroelectric or dielectric mode, respectively, below or above the Curie temperature, which is 320 C for SBT. When incident infrared radiation is chopped, small oscillations in pixel temperature produce pyroelectric or dielectric alternating currents. The sensitivity of ferroelectric thermal detectors depends strongly on pixel microstructure, since P{sub r} and {epsilon}{sub r} increase with grain size during annealing. To manufacture SBT pixels on Si chips, acceptable SBT grain growth must be achieved at the lowest possible oxygen annealing temperature, to avoid damaging the Si chip below. Therefore current technical progress describes how grain size, reaction layer thickness, and electrical properties develop during the annealing of SBT pixels deposited on Si.« less

A UVM simulation environment for the study, optimization and verification of HL-LHC digital pixel readout chips

NASA Astrophysics Data System (ADS)

Marconi, S.; Conti, E.; Christiansen, J.; Placidi, P.

2018-05-01

The operating conditions of the High Luminosity upgrade of the Large Hadron Collider are very demanding for the design of next generation hybrid pixel readout chips in terms of particle rate, radiation level and data bandwidth. To this purpose, the RD53 Collaboration has developed for the ATLAS and CMS experiments a dedicated simulation and verification environment using industry-consolidated tools and methodologies, such as SystemVerilog and the Universal Verification Methodology (UVM). This paper presents how the so-called VEPIX53 environment has first guided the design of digital architectures, optimized for processing and buffering very high particle rates, and secondly how it has been reused for the functional verification of the first large scale demonstrator chip designed by the collaboration, which has recently been submitted.

Characterization and correction of charge-induced pixel shifts in DECam

DOE PAGES

Gruen, D.; Bernstein, G. M.; Jarvis, M.; ...

2015-05-28

Interaction of charges in CCDs with the already accumulated charge distribution causes both a flux dependence of the point-spread function (an increase of observed size with flux, also known as the brighter/fatter effect) and pixel-to-pixel correlations of the Poissonian noise in flat fields. We describe these effects in the Dark Energy Camera (DECam) with charge dependent shifts of effective pixel borders, i.e. the Antilogus et al. (2014) model, which we fit to measurements of flat-field Poissonian noise correlations. The latter fall off approximately as a power-law r -2.5 with pixel separation r, are isotropic except for an asymmetry in themore » direct neighbors along rows and columns, are stable in time, and are weakly dependent on wavelength. They show variations from chip to chip at the 20% level that correlate with the silicon resistivity. The charge shifts predicted by the model cause biased shape measurements, primarily due to their effect on bright stars, at levels exceeding weak lensing science requirements. We measure the flux dependence of star images and show that the effect can be mitigated by applying the reverse charge shifts at the pixel level during image processing. Differences in stellar size, however, remain significant due to residuals at larger distance from the centroid.« less

Development of monolithic pixel detector with SOI technology for the ILC vertex detector

NASA Astrophysics Data System (ADS)

Yamada, M.; Ono, S.; Tsuboyama, T.; Arai, Y.; Haba, J.; Ikegami, Y.; Kurachi, I.; Togawa, M.; Mori, T.; Aoyagi, W.; Endo, S.; Hara, K.; Honda, S.; Sekigawa, D.

2018-01-01

We have been developing a monolithic pixel sensor for the International Linear Collider (ILC) vertex detector with the 0.2 μm FD-SOI CMOS process by LAPIS Semiconductor Co., Ltd. We aim to achieve a 3 μm single-point resolution required for the ILC with a 20×20 μm2 pixel. Beam bunch crossing at the ILC occurs every 554 ns in 1-msec-long bunch trains with an interval of 200 ms. Each pixel must record the charge and time stamp of a hit to identify a collision bunch for event reconstruction. Necessary functions include the amplifier, comparator, shift register, analog memory and time stamp implementation in each pixel, and column ADC and Zero-suppression logic on the chip. We tested the first prototype sensor, SOFIST ver.1, with a 120 GeV proton beam at the Fermilab Test Beam Facility in January 2017. SOFIST ver.1 has a charge sensitive amplifier and two analog memories in each pixel, and an 8-bit Wilkinson-type ADC is implemented for each column on the chip. We measured the residual of the hit position to the reconstructed track. The standard deviation of the residual distribution fitted by a Gaussian is better than 3 μm.

The design of CMOS general-purpose analog front-end circuit with tunable gain and bandwidth for biopotential signal recording systems.

PubMed

Chen, Wei-Ming; Yang, Wen-Chia; Tsai, Tzung-Yun; Chiueh, Herming; Wu, Chung-Yu

2011-01-01

In this paper an 8-channel CMOS general-purpose analog front-end (AFE) circuit with tunable gain and bandwidth for biopotential signal recording systems is presented. The proposed AFE consists of eight chopper stabilized pre-amplifiers, an 8-to-1 analog multiplexer, and a programmable gain amplifier. It can be used to sense and amplify different kinds of biopotential signals, such as electrocorticogram (ECoG), electrocardiogram (ECG) and electromyogram (EMG). The AFE chip is designed and fabricated in 0.18-μm CMOS technology. The measured maximum gain of AFE is 60.8 dB. The low cutoff frequency can achieve as low as 0.8 Hz and high cutoff frequency can be adjusted from 200 Hz to 10 kHz to suit for different kinds of biopotential signals. The measured input-referred noise is 0.9 μV(rms), with the power consumption of 18μW per channel at 1.8-V power supply. And the noise efficiency factor (NEF) is only 1.3 for pre-amplifier.

The GBT-SCA, a radiation tolerant ASIC for detector control and monitoring applications in HEP experiments

NASA Astrophysics Data System (ADS)

Caratelli, A.; Bonacini, S.; Kloukinas, K.; Marchioro, A.; Moreira, P.; De Oliveira, R.; Paillard, C.

2015-03-01

The future upgrades of the LHC experiments will increase the beam luminosity leading to a corresponding growth of the amounts of data to be treated by the data acquisition systems. To address these needs, the GBT (Giga-Bit Transceiver optical link [1,2]) architecture was developed to provide the simultaneous transfer of readout data, timing and trigger signals as well as slow control and monitoring data. The GBT-SCA ASIC, part of the GBT chip-set, has the purpose to distribute control and monitoring signals to the on-detector front-end electronics and perform monitoring operations of detector environmental parameters. In order to meet the requirements of different front-end ASICs used in the experiments, it provides various user-configurable interfaces capable to perform simultaneous operations. It is designed employing radiation tolerant design techniques to ensure robustness against SEUs and TID radiation effects and is implemented in a commercial 130 nm CMOS technology. This work presents the GBT-SCA architecture, the ASIC interfaces, the data transfer protocol, and its integration with the GBT optical link.

Reset noise suppression in two-dimensional CMOS photodiode pixels through column-based feedback-reset

NASA Technical Reports Server (NTRS)

Pain, B.; Cunningham, T. J.; Hancock, B.; Yang, G.; Seshadri, S.; Ortiz, M.

2002-01-01

We present new CMOS photodiode imager pixel with ultra-low read noise through on-chip suppression of reset noise via column-based feedback circuitry. The noise reduction is achieved without introducing any image lag, and with insignificant reduction in quantum efficiency and full well.

An Implantable RFID Sensor Tag toward Continuous Glucose Monitoring.

PubMed

Xiao, Zhibin; Tan, Xi; Chen, Xianliang; Chen, Sizheng; Zhang, Zijian; Zhang, Hualei; Wang, Junyu; Huang, Yue; Zhang, Peng; Zheng, Lirong; Min, Hao

2015-05-01

This paper presents a wirelessly powered implantable electrochemical sensor tag for continuous blood glucose monitoring. The system is remotely powered by a 13.56-MHz inductive link and utilizes an ISO 15693 radio frequency identification (RFID) standard for communication. This paper provides reliable and accurate measurement for changing glucose level. The sensor tag employs a long-term glucose sensor, a winding ferrite antenna, an RFID front-end, a potentiostat, a 10-bit sigma-delta analog to digital converter, an on-chip temperature sensor, and a digital baseband for protocol processing and control. A high-frequency external reader is used to power, command, and configure the sensor tag. The only off-chip support circuitry required is a tuned antenna and a glucose microsensor. The integrated chip fabricated in SMIC 0.13-μm CMOS process occupies an area of 1.2 mm ×2 mm and consumes 50 μW. The power sensitivity of the whole system is -4 dBm. The sensor tag achieves a measured glucose range of 0-30 mM with a sensitivity of 0.75 nA/mM.

Planar MEMS bio-chip for recording ion-channel currents in biological cells

NASA Astrophysics Data System (ADS)

Pandey, Santosh; Ferdous, Zannatul; White, Marvin H.

2003-10-01

We describe a planar MEMS silicon structure to record ion-channel currents in biological cells. The conventional method of performing an electrophysiological experiment, 'patch-clamping,' employs a glass micropipette. Despite careful treatments of the micropipette tip, such as fire polishing and surface coating, the latter is a source of thermal noise because of its inherent, tapered, conical structure, which gives rise to a large pipette resistance. This pipette resistance, when coupled with the self-capacitance of the biological cell, limits the available bandwidth and processing of fast transient, ion channel current pulses. In this work, we reduce considerably the pipette resistance with a planar micropipette on a silicon chip to permit the resolution of sub-millisecond, ion-channel pulses. We discuss the design topology of the device, describe the fabrication sequence, and highlight important critical issues. The design of an integrated on-chip CMOS instrumentation amplifier is described, which has a low-noise front-end, input-offset cancellation, correlated double sampling (CDS), and an ultra-high gain in the order of 1012V/A.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the first six months of this project were to begin laying the foundations for both the SiC front-end optical chip fabrication techniques for high pressure gas species sensing as well as the design, assembly, and test of a portable high pressure high temperature calibration test cell chamber for introducing gas species. This calibration cell will be used in the remaining months for proposed first stage high pressure high temperature gas species sensor experimentation and data processing. All these goals have been achieved and are described in detail in the report. Both design process and diagrams for themore » mechanical elements as well as the optical systems are provided. Photographs of the fabricated calibration test chamber cell, the optical sensor setup with the calibration cell, the SiC sample chip holder, and relevant signal processing mathematics are provided. Initial experimental data from both the optical sensor and fabricated test gas species SiC chips is provided. The design and experimentation results are summarized to give positive conclusions on the proposed novel high temperature high pressure gas species detection optical sensor technology.« less

On-chip skin color detection using a triple-well CMOS process

NASA Astrophysics Data System (ADS)

Boussaid, Farid; Chai, Douglas; Bouzerdoum, Abdesselam

2004-03-01

In this paper, a current-mode VLSI architecture enabling on read-out skin detection without the need for any on-chip memory elements is proposed. An important feature of the proposed architecture is that it removes the need for demosaicing. Color separation is achieved using the strong wavelength dependence of the absorption coefficient in silicon. This wavelength dependence causes a very shallow absorption of blue light and enables red light to penetrate deeply in silicon. A triple-well process, allowing a P-well to be placed inside an N-well, is chosen to fabricate three vertically integrated photodiodes acting as the RGB color detector for each pixel. Pixels of an input RGB image are classified as skin or non-skin pixels using a statistical skin color model, chosen to offer an acceptable trade-off between skin detection performance and implementation complexity. A single processing unit is used to classify all pixels of the input RGB image. This results in reduced mismatch and also in an increased pixel fill-factor. Furthermore, the proposed current-mode architecture is programmable, allowing external control of all classifier parameters to compensate for mismatch and changing lighting conditions.

Characterization of Sphinx1 ASIC X-ray detector using photon counting and charge integration

NASA Astrophysics Data System (ADS)

Habib, A.; Arques, M.; Moro, J.-L.; Accensi, M.; Stanchina, S.; Dupont, B.; Rohr, P.; Sicard, G.; Tchagaspanian, M.; Verger, L.

2018-01-01

Sphinx1 is a novel pixel architecture adapted for X-ray imaging, it detects radiation by photon counting and charge integration. In photon counting mode, each photon is compensated by one or more counter-charges typically consisting of 100 electrons (e-) each. The number of counter-charges required gives a measure of the incoming photon energy, thus allowing spectrometric detection. Pixels can also detect radiation by integrating the charges deposited by all incoming photons during one image frame and converting this analog value into a digital response with a 100 electrons least significant bit (LSB), based on the counter-charge concept. A proof of concept test chip measuring 5 mm × 5 mm, with 200 μm × 200 μm pixels has been produced and characterized. This paper provides details on the architecture and the counter-charge design; it also describes the two modes of operation: photon counting and charge integration. The first performance measurements for this test chip are presented. Noise was found to be ~80 e-rms in photon counting mode with a power consumption of only 0.9 μW/pixel for the static analog part and 0.3 μW/pixel for the static digital part.

A fully integrated direct-conversion digital satellite tuner in 0.18 μm CMOS

NASA Astrophysics Data System (ADS)

Si, Chen; Zengwang, Yang; Mingliang, Gu

2011-04-01

A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented. A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end, while the synthesizer integrated the loop filter to reduce the solution cost and system debug time. Fabricated in 0.18 μm CMOS, the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector. The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1 °C integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.

A Binary Offset Effect in CCD Readout and Its Impact on Astronomical Data

NASA Astrophysics Data System (ADS)

Boone, K.; Aldering, G.; Copin, Y.; Dixon, S.; Domagalski, R. S.; Gangler, E.; Pecontal, E.; Perlmutter, S.

2018-06-01

We have discovered an anomalous behavior of CCD readout electronics that affects their use in many astronomical applications. An offset in the digitization of the CCD output voltage that depends on the binary encoding of one pixel is added to pixels that are read out one, two, and/or three pixels later. One result of this effect is the introduction of a differential offset in the background when comparing regions with and without flux from science targets. Conventional data reduction methods do not correct for this offset. We find this effect in 16 of 22 instruments investigated, covering a variety of telescopes and many different front-end electronics systems. The affected instruments include LRIS and DEIMOS on the Keck telescopes, WFC3 UVIS and STIS on HST, MegaCam on CFHT, SNIFS on the UH88 telescope, GMOS on the Gemini telescopes, HSC on Subaru, and FORS on VLT. The amplitude of the introduced offset is up to 4.5 ADU per pixel, and it is not directly proportional to the measured ADU level. We have developed a model that can be used to detect this “binary offset effect” in data, and correct for it. Understanding how data are affected and applying a correction for the effect is essential for precise astronomical measurements.

Development of n-in-p pixel modules for the ATLAS upgrade at HL-LHC

NASA Astrophysics Data System (ADS)

Macchiolo, A.; Nisius, R.; Savic, N.; Terzo, S.

2016-09-01

Thin planar pixel modules are promising candidates to instrument the inner layers of the new ATLAS pixel detector for HL-LHC, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. 100-200 μm thick sensors, interconnected to FE-I4 read-out chips, have been characterized with radioactive sources and beam tests at the CERN-SPS and DESY. The results of these measurements are reported for devices before and after irradiation up to a fluence of 14 ×1015 neq /cm2 . The charge collection and tracking efficiency of the different sensor thicknesses are compared. The outlook for future planar pixel sensor production is discussed, with a focus on sensor design with the pixel pitches (50×50 and 25×100 μm2) foreseen for the RD53 Collaboration read-out chip in 65 nm CMOS technology. An optimization of the biasing structures in the pixel cells is required to avoid the hit efficiency loss presently observed in the punch-through region after irradiation. For this purpose the performance of different layouts have been compared in FE-I4 compatible sensors at various fluence levels by using beam test data. Highly segmented sensors will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. In order to reproduce the performance of 50×50 μm2 pixels at high pseudo-rapidity values, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angle (80°) with respect to the short pixel direction. Results on cluster shapes, charge collection and hit efficiency will be shown.

Design of analog pixels front-end active feedback

NASA Astrophysics Data System (ADS)

Kmon, P.; Kadlubowski, L. A.; Kaczmarczyk, P.

2018-01-01

The paper presents the design of the active feedback used in a charge-sensitive amplifier. The predominant advantages of the presented circuit are its ability for setting wide range of pulse-time widths, small silicon area occupation and low power consumption. The feedback also allows sensor leakage current compensation and, thanks to an additional DC amplifier, it minimizes the output DC voltage variations, which is especially important in the DC coupled recording chain and for processes with limited supply voltage. The paper provides feedback description and its operation principle. The proposed circuit was designed in the CMOS 130nm technology.

Multiocular image sensor with on-chip beam-splitter and inner meta-micro-lens for single-main-lens stereo camera.

PubMed

Koyama, Shinzo; Onozawa, Kazutoshi; Tanaka, Keisuke; Saito, Shigeru; Kourkouss, Sahim Mohamed; Kato, Yoshihisa

2016-08-08

We developed multiocular 1/3-inch 2.75-μm-pixel-size 2.1M- pixel image sensors by co-design of both on-chip beam-splitter and 100-nm-width 800-nm-depth patterned inner meta-micro-lens for single-main-lens stereo camera systems. A camera with the multiocular image sensor can capture horizontally one-dimensional light filed by both the on-chip beam-splitter horizontally dividing ray according to incident angle, and the inner meta-micro-lens collecting the divided ray into pixel with small optical loss. Cross-talks between adjacent light field images of a fabricated binocular image sensor and of a quad-ocular image sensor are as low as 6% and 7% respectively. With the selection of two images from one-dimensional light filed images, a selective baseline for stereo vision is realized to view close objects with single-main-lens. In addition, by adding multiple light field images with different ratios, baseline distance can be tuned within an aperture of a main lens. We suggest the electrically selective or tunable baseline stereo vision to reduce 3D fatigue of viewers.

Low-power low-noise mixed-mode VLSI ASIC for infinite dynamic range imaging applications

NASA Astrophysics Data System (ADS)

Turchetta, Renato; Hu, Y.; Zinzius, Y.; Colledani, C.; Loge, A.

1998-11-01

Solid state solutions for imaging are mainly represented by CCDs and, more recently, by CMOS imagers. Both devices are based on the integration of the total charge generated by the impinging radiation, with no processing of the single photon information. The dynamic range of these devices is intrinsically limited by the finite value of noise. Here we present the design of an architecture which allows efficient, in-pixel, noise reduction to a practically zero level, thus allowing infinite dynamic range imaging. A detailed calculation of the dynamic range is worked out, showing that noise is efficiently suppressed. This architecture is based on the concept of single-photon counting. In each pixel, we integrate both the front-end, low-noise, low-power analog part and the digital part. The former consists of a charge preamplifier, an active filter for optimal noise bandwidth reduction, a buffer and a threshold comparator, and the latter is simply a counter, which can be programmed to act as a normal shift register for the readout of the counters' contents. Two different ASIC's based on this concept have been designed for different applications. The first one has been optimized for silicon edge-on microstrips detectors, used in a digital mammography R and D project. It is a 32-channel circuit, with a 16-bit binary static counter.It has been optimized for a relatively large detector capacitance of 5 pF. Noise has been measured to be equal to 100 + 7*Cd (pF) electron rms with the digital part, showing no degradation of the noise performances with respect to the design values. The power consumption is 3.8mW/channel for a peaking time of about 1 microsecond(s) . The second circuit is a prototype for pixel imaging. The total active area is about (250 micrometers )**2. The main differences of the electronic architecture with respect to the first prototype are: i) different optimization of the analog front-end part for low-capacitance detectors, ii) in- pixel 4-bit comparator-offset compensation, iii) 15-bit pseudo-random counter. The power consumption is 255 (mu) W/channel for a peaking time of 300 ns and an equivalent noise charge of 185 + 97*Cd electrons rms. Simulation and experimental result as well as imaging results will be presented.

Smart CMOS image sensor for lightning detection and imaging.

PubMed

Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

2013-03-01

We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 μm pixel pitch has been fabricated using a 0.35 μm 2P 5M technology and tested to validate the selected detection approach.

A free-running, time-based readout method for particle detectors

NASA Astrophysics Data System (ADS)

Goerres, A.; Bugalho, R.; Di Francesco, A.; Gastón, C.; Gonçalves, F.; Mazza, G.; Mignone, M.; Di Pietro, V.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; da Silva, J. C.; Silva, R.; Stockmanns, T.; Varela, J.; Veckalns, V.; Wheadon, R.

2014-03-01

For the EndoTOFPET-US experiment, the TOFPET ASIC has been developed as a front-end chip to read out data from silicon photomultipliers (SiPM) [1]. It introduces a time of flight information into the measurement of a PET scanner and hence reduces radiation exposure of the patient [2]. The chip is designed to work with a high event rate up to 100 kHz and a time resolution of 50 ps LSB. Using two threshold levels, it can measure the leading edge of the event pulse precisely while successfully suppressing dark counts from the SiPM. This also enables a time over threshold determination, leading to a charge measurement of the signal's pulse. The same, time-based concept is chosen for the PASTA chip used in the PANDA experiment. This high-energy particle detector contains sub-systems for specific measurement goals. The innermost of these is the Micro Vertex Detector, a silicon-based tracking system. The PASTA chip's approach is much like the TOFPET ASIC with some differences. The most significant ones are a changed amplifying part for different input signals as well as protection for radiation effects of the high-radiation environment. Apart from that, the simple and general concept combined with a small area and low power consumption support the choice for using this approach.

A novel high electrode count spike recording array using an 81,920 pixel transimpedance amplifier-based imaging chip.

PubMed

Johnson, Lee J; Cohen, Ethan; Ilg, Doug; Klein, Richard; Skeath, Perry; Scribner, Dean A

2012-04-15

Microelectrode recording arrays of 60-100 electrodes are commonly used to record neuronal biopotentials, and these have aided our understanding of brain function, development and pathology. However, higher density microelectrode recording arrays of larger area are needed to study neuronal function over broader brain regions such as in cerebral cortex or hippocampal slices. Here, we present a novel design of a high electrode count picocurrent imaging array (PIA), based on an 81,920 pixel Indigo ISC9809 readout integrated circuit camera chip. While originally developed for interfacing to infrared photodetector arrays, we have adapted the chip for neuron recording by bonding it to microwire glass resulting in an array with an inter-electrode pixel spacing of 30 μm. In a high density electrode array, the ability to selectively record neural regions at high speed and with good signal to noise ratio are both functionally important. A critical feature of our PIA is that each pixel contains a dedicated low noise transimpedance amplifier (∼0.32 pA rms) which allows recording high signal to noise ratio biocurrents comparable to single electrode voltage amplifier recordings. Using selective sampling of 256 pixel subarray regions, we recorded the extracellular biocurrents of rabbit retinal ganglion cell spikes at sampling rates up to 7.2 kHz. Full array local electroretinogram currents could also be recorded at frame rates up to 100 Hz. A PIA with a full complement of 4 readout circuits would span 1cm and could acquire simultaneous data from selected regions of 1024 electrodes at sampling rates up to 9.3 kHz. Published by Elsevier B.V.

Demosaiced pixel super-resolution in digital holography for multiplexed computational color imaging on-a-chip (Conference Presentation)

NASA Astrophysics Data System (ADS)

Wu, Yichen; Zhang, Yibo; Luo, Wei; Ozcan, Aydogan

2017-03-01

Digital holographic on-chip microscopy achieves large space-bandwidth-products (e.g., >1 billion) by making use of pixel super-resolution techniques. To synthesize a digital holographic color image, one can take three sets of holograms representing the red (R), green (G) and blue (B) parts of the spectrum and digitally combine them to synthesize a color image. The data acquisition efficiency of this sequential illumination process can be improved by 3-fold using wavelength-multiplexed R, G and B illumination that simultaneously illuminates the sample, and using a Bayer color image sensor with known or calibrated transmission spectra to digitally demultiplex these three wavelength channels. This demultiplexing step is conventionally used with interpolation-based Bayer demosaicing methods. However, because the pixels of different color channels on a Bayer image sensor chip are not at the same physical location, conventional interpolation-based demosaicing process generates strong color artifacts, especially at rapidly oscillating hologram fringes, which become even more pronounced through digital wave propagation and phase retrieval processes. Here, we demonstrate that by merging the pixel super-resolution framework into the demultiplexing process, such color artifacts can be greatly suppressed. This novel technique, termed demosaiced pixel super-resolution (D-PSR) for digital holographic imaging, achieves very similar color imaging performance compared to conventional sequential R,G,B illumination, with 3-fold improvement in image acquisition time and data-efficiency. We successfully demonstrated the color imaging performance of this approach by imaging stained Pap smears. The D-PSR technique is broadly applicable to high-throughput, high-resolution digital holographic color microscopy techniques that can be used in resource-limited-settings and point-of-care offices.

Low-power priority Address-Encoder and Reset-Decoder data-driven readout for Monolithic Active Pixel Sensors for tracker system

NASA Astrophysics Data System (ADS)

Yang, P.; Aglieri, G.; Cavicchioli, C.; Chalmet, P. L.; Chanlek, N.; Collu, A.; Gao, C.; Hillemanns, H.; Junique, A.; Kofarago, M.; Keil, M.; Kugathasan, T.; Kim, D.; Kim, J.; Lattuca, A.; Marin Tobon, C. A.; Marras, D.; Mager, M.; Martinengo, P.; Mazza, G.; Mugnier, H.; Musa, L.; Puggioni, C.; Rousset, J.; Reidt, F.; Riedler, P.; Snoeys, W.; Siddhanta, S.; Usai, G.; van Hoorne, J. W.; Yi, J.

2015-06-01

Active Pixel Sensors used in High Energy Particle Physics require low power consumption to reduce the detector material budget, low integration time to reduce the possibilities of pile-up and fast readout to improve the detector data capability. To satisfy these requirements, a novel Address-Encoder and Reset-Decoder (AERD) asynchronous circuit for a fast readout of a pixel matrix has been developed. The AERD data-driven readout architecture operates the address encoding and reset decoding based on an arbitration tree, and allows us to readout only the hit pixels. Compared to the traditional readout structure of the rolling shutter scheme in Monolithic Active Pixel Sensors (MAPS), AERD can achieve a low readout time and a low power consumption especially for low hit occupancies. The readout is controlled at the chip periphery with a signal synchronous with the clock, allows a good digital and analogue signal separation in the matrix and a reduction of the power consumption. The AERD circuit has been implemented in the TowerJazz 180 nm CMOS Imaging Sensor (CIS) process with full complementary CMOS logic in the pixel. It works at 10 MHz with a matrix height of 15 mm. The energy consumed to read out one pixel is around 72 pJ. A scheme to boost the readout speed to 40 MHz is also discussed. The sensor chip equipped with AERD has been produced and characterised. Test results including electrical beam measurement are presented.

Internal monitoring of GBTx emulator using IPbus for CBM experiment

NASA Astrophysics Data System (ADS)

Mandal, Swagata; Zabolotny, Wojciech; Sau, Suman; Chkrabarti, Amlan; Saini, Jogender; Chattopadhyay, Subhasis; Pal, Sushanta Kumar

2015-09-01

The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) in Darmstadt at GSI. In CBM experiment a precisely time synchronized fault tolerant self-triggered electronics is required for Data Acquisition (DAQ) system in CBM experiments which can support high data rate (up to several TB/s). As a part of the implementation of the DAQ system of Muon Chamber (MUCH) which is one of the important detectors in CBM experiment, a FPGA based Gigabit Transceiver (GBTx) emulator is implemented. Readout chain for MUCH consists of XYTER chips (Front end electronics) which will be directly connected to detector, GBTx emulator, Data Processing Board (DPB) and First level event selector board (FLIB) with backend software interface. GBTx emulator will be connected with the XYTER emulator through LVDS (Low Voltage Differential Signalling) line in the front end and in the back end it is connected with DPB through 4.8 Gbps optical link. IPBus over Ethernet is used for internal monitoring of the registers within the GBTx. In IPbus implementation User Datagram Protocol (UDP) stack is used in transport layer of OSI model so that GBTx can be controlled remotely. A Python script is used at computer side to drive IPbus controller.

A 400 KHz line rate 2048-pixel stitched SWIR linear array

NASA Astrophysics Data System (ADS)

Anchlia, Ankur; Vinella, Rosa M.; Gielen, Daphne; Wouters, Kristof; Vervenne, Vincent; Hooylaerts, Peter; Deroo, Pieter; Ruythooren, Wouter; De Gaspari, Danny; Das, Jo; Merken, Patrick

2016-05-01

Xenics has developed a family of stitched SWIR long linear arrays that operate up to 400 KHz of line rate. These arrays serve medical and industrial applications that require high line rates as well as space applications that require long linear arrays. The arrays are based on a modular ROIC design concept: modules of 512 pixels are stitched during fabrication to achieve 512, 1024 and 2048 pixel arrays. Each 512-pixel module has its own on-chip digital sequencer, analog readout chain and 4 output buffers. This modular concept enables a long array to run at a high line rates irrespective of the array length, which limits the line rate in a traditional linear array. The ROIC is flip-chipped with InGaAs detector arrays. The FPA has a pixel pitch of 12.5μm and has two pixel flavors: square (12.5μm) and rectangular (250μm). The frontend circuit is based on Capacitive Trans-impedance Amplifier (CTIA) to attain stable detector bias, and good linearity and signal integrity, especially at high speeds. The CTIA has an input auto-zero mechanism that allows to have low detector bias (<20mV). An on-chip Correlated Double Sample (CDS) facilitates removal of CTIA KTC and 1/f noise, and other offsets, achieving low noise performance. There are five gain modes in the FPA giving the full well range from 85Ke- to 40Me-. The measured input referred noise is 35e-rms in the highest gain mode. The FPA operates in Integrate While Read mode and, at a master clock rate of 60MHz and a minimum integration time of 1.4μs, achieves the highest line rate of 400 KHz. In this paper, design details and measurements results are presented in order to demonstrate the array performance.

Molded underfill (MUF) encapsulation for flip-chip package: A numerical investigation

NASA Astrophysics Data System (ADS)

Azmi, M. A.; Abdullah, M. K.; Abdullah, M. Z.; Ariff, Z. M.; Saad, Abdullah Aziz; Hamid, M. F.; Ismail, M. A.

2017-07-01

This paper presents the numerical simulation of epoxy molding compound (EMC) filling in multi flip-chip packages during encapsulation process. The empty and a group flip chip packages were considered in the mold cavity in order to study the flow profile of the EMC. SOLIDWORKS software was used for three-dimensional modeling and it was incorporated into fluid analysis software namely as ANSYS FLUENT. The volume of fluid (VOF) technique was used for capturing the flow front profiles and Power Law model was applied for its rheology model. The numerical result are compared and discussed with previous experimental and it was shown a good conformity for model validation. The prediction of flow front was observed and analyzed at different filling time. The possibility and visual of void formation in the package is captured and the number of flip-chip is one factor that contributed to the void formation.

Design of a Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

NASA Astrophysics Data System (ADS)

Gao, W.; Liu, H.; Gan, B.; Wei, T.; Gao, D.; Hu, Y.

2014-10-01

In this paper, we present the design and preliminary results of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for a PET imaging system whose objective is to achieve the following performances: the spatial resolution of 1 mm3, the detection efficiency of 15% and the time resolution of 1 ns. A cascode amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuits is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. An eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm ×2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy level of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC. The tested result of ENC is 86.5 e- at zero farad plus 9.3 e- per picofarad. The nonlinearity is less than 3%. The crosstalk is less than 2%. The power dissipation is about 3 mW/channel.

Portable and cost-effective pixel super-resolution on-chip microscope for telemedicine applications.

PubMed

Bishara, Waheb; Sikora, Uzair; Mudanyali, Onur; Su, Ting-Wei; Yaglidere, Oguzhan; Luckhart, Shirley; Ozcan, Aydogan

2011-01-01

We report a field-portable lensless on-chip microscope with a lateral resolution of <1 μm and a large field-of-view of ~24 mm(2). This microscope is based on digital in-line holography and a pixel super-resolution algorithm to process multiple lensfree holograms and obtain a single high-resolution hologram. In its compact and cost-effective design, we utilize 23 light emitting diodes butt-coupled to 23 multi-mode optical fibers, and a simple optical filter, with no moving parts. Weighing only ~95 grams, we demonstrate the performance of this field-portable microscope by imaging various objects including human malaria parasites in thin blood smears.

Recent Results on Gridpix Detectors:. AN Integrated Micromegas Grid and a Micromegas Ageing Test

NASA Astrophysics Data System (ADS)

Chefdeville, M.; Aarts, A.; van der Graaf, H.; van der Putten, S.

2006-04-01

A new gas-filled detector combining a Micromegas with a CMOS pixel chip has been recently tested. A procedure to integrate the Micromegas grid onto silicon wafers (‘wafer post processing’) has been developed. We aim to eventually integrate the grid on top of wafers of CMOS pixel chips. The first part of this contribution describes an application in vertex detection (GOSSIP). Then tests of the first detector prototype of a grid integrated on a bare silicon wafer are shown. Finally an ageing test of a Micromegas chamber is presented. After verifying the chambers' proportionality at a very high dose rates, the device was irradiated until ageing became apparent.

SPAD array based TOF SoC design for unmanned vehicle

NASA Astrophysics Data System (ADS)

Pan, An; Xu, Yuan; Xie, Gang; Huang, Zhiyu; Zheng, Yanghao; Shi, Weiwei

2018-03-01

As for the requirement of unmanned-vehicle mobile Lidar system, this paper presents a SoC design based on pulsed TOF depth image sensor. This SoC has a detection range of 300m and detecting resolution of 1.5cm. Pixels are made of SPAD. Meanwhile, SoC adopts a structure of multi-pixel sharing TDC, which significantly reduces chip area and improve the fill factor of light-sensing surface area. SoC integrates a TCSPC module to achieve the functionality of receiving each photon, measuring photon flight time and processing depth information in one chip. The SOC is designed in the SMIC 0.13μm CIS CMOS technology

Advanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering system

NASA Astrophysics Data System (ADS)

Marconi, S.; Orfanelli, S.; Karagounis, M.; Hemperek, T.; Christiansen, J.; Placidi, P.

2017-02-01

A dedicated power analysis methodology, based on modern digital design tools and integrated with the VEPIX53 simulation framework developed within RD53 collaboration, is being used to guide vital choices for the design and optimization of the next generation ATLAS and CMS pixel chips and their critical serial powering circuit (shunt-LDO). Power consumption is studied at different stages of the design flow under different operating conditions. Significant effort is put into extensive investigations of dynamic power variations in relation with the decoupling seen by the powering network. Shunt-LDO simulations are also reported to prove the reliability at the system level.

A 65k pixel, 150k frames-per-second camera with global gating and micro-lenses suitable for fluorescence lifetime imaging

NASA Astrophysics Data System (ADS)

Burri, Samuel; Powolny, François; Bruschini, Claudio E.; Michalet, Xavier; Regazzoni, Francesco; Charbon, Edoardo

2014-05-01

This paper presents our work on a 65k pixel single-photon avalanche diode (SPAD) based imaging sensor realized in a 0.35μm standard CMOS process. At a resolution of 512 by 128 pixels the sensor is read out in 6.4μs to deliver over 150k monochrome frames per second. The individual pixel has a size of 24μm2 and contains the SPAD with a 12T quenching and gating circuitry along with a memory element. The gating signals are distributed across the chip through a balanced tree to minimize the signal skew between the pixels. The array of pixels is row-addressable and data is sent out of the chip on 128 lines in parallel at a frequency of 80MHz. The system is controlled by an FPGA which generates the gating and readout signals and can be used for arbitrary real-time computation on the frames from the sensor. The communication protocol between the camera and a conventional PC is USB2. The active area of the chip is 5% and can be significantly improved with the application of a micro-lens array. A micro-lens array, for use with collimated light, has been designed and its performance is reviewed in the paper. Among other high-speed phenomena the gating circuitry capable of generating illumination periods shorter than 5ns can be used for Fluorescence Lifetime Imaging (FLIM). In order to measure the lifetime of fluorophores excited by a picosecond laser, the sensor's illumination period is synchronized with the excitation laser pulses. A histogram of the photon arrival times relative to the excitation is then constructed by counting the photons arriving during the sensitive time for several positions of the illumination window. The histogram for each pixel is transferred afterwards to a computer where software routines extract the lifetime at each location with an accuracy better than 100ps. We show results for fluorescence lifetime measurements using different fluorophores with lifetimes ranging from 150ps to 5ns.

Tests of monolithic active pixel sensors at national synchrotron light source

NASA Astrophysics Data System (ADS)

Deptuch, G.; Besson, A.; Carini, G. A.; Siddons, D. P.; Szelezniak, M.; Winter, M.

2007-01-01

The paper discusses basic characterization of Monolithic Active Pixel Sensors (MAPS) carried out at the X12A beam-line at National Synchrotron Light Source (NSLS), Upton, NY, USA. The tested device was a MIMOSA V (MV) chip, back-thinned down to the epitaxial layer. This 1M pixels device features a pixel size of 17×17 μm2 and was designed in a 0.6 μm CMOS process. The X-ray beam energies used range from 5 to 12 keV. Examples of direct X-ray imaging capabilities are presented.

Effects of Verticillium dahliae infection on stem-end chip defect development in potatoes (Solanum tuberosum L.)

USDA-ARS?s Scientific Manuscript database

Potato chips are America's favorite snack food with annual retail sales of over $6 billion. Stem-end chip defect, which is characterized by discoloration of the vasculature and surrounding tissues at the tuber stem end portion of chips, is an important tuber quality concern for US chip production. T...

The PixFEL project: Progress towards a fine pitch X-ray imaging camera for next generation FEL facilities

NASA Astrophysics Data System (ADS)

Rizzo, G.; Batignani, G.; Benkechkache, M. A.; Bettarini, S.; Casarosa, G.; Comotti, D.; Dalla Betta, G.-F.; Fabris, L.; Forti, F.; Grassi, M.; Lodola, L.; Malcovati, P.; Manghisoni, M.; Mendicino, R.; Morsani, F.; Paladino, A.; Pancheri, L.; Paoloni, E.; Ratti, L.; Re, V.; Traversi, G.; Vacchi, C.; Verzellesi, G.; Xu, H.

2016-07-01

The INFN PixFEL project is developing the fundamental building blocks for a large area X-ray imaging camera to be deployed at next generation free electron laser (FEL) facilities with unprecedented intensity. Improvement in performance beyond the state of art in imaging instrumentation will be explored adopting advanced technologies like active edge sensors, a 65 nm node CMOS process and vertical integration. These are the key ingredients of the PixFEL project to realize a seamless large area focal plane instrument composed by a matrix of multilayer four-side buttable tiles. In order to minimize the dead area and reduce ambiguities in image reconstruction, a fine pitch active edge thick sensor is being optimized to cope with very high intensity photon flux, up to 104 photons per pixel, in the range from 1 to 10 keV. A low noise analog front-end channel with this wide dynamic range and a novel dynamic compression feature, together with a low power 10 bit analog to digital conversion up to 5 MHz, has been realized in a 110 μm pitch with a 65 nm CMOS process. Vertical interconnection of two CMOS tiers will be also explored in the future to build a four-side buttable readout chip with high density memories. In the long run the objective of the PixFEL project is to build a flexible X-ray imaging camera for operation both in burst mode, like at the European X-FEL, or in continuous mode with the high frame rates anticipated for future FEL facilities.

High performance digital read out integrated circuit (DROIC) for infrared imaging

NASA Astrophysics Data System (ADS)

Mizuno, Genki; Olah, Robert; Oduor, Patrick; Dutta, Achyut K.; Dhar, Nibir K.

2016-05-01

Banpil Photonics has developed a high-performance Digital Read-Out Integrated Circuit (DROIC) for image sensors and camera systems targeting various military, industrial and commercial Infrared (IR) imaging applications. The on-chip digitization of the pixel output eliminates the necessity for an external analog-to-digital converter (ADC), which not only cuts costs, but also enables miniaturization of packaging to achieve SWaP-C camera systems. In addition, the DROIC offers new opportunities for greater on-chip processing intelligence that are not possible in conventional analog ROICs prevalent today. Conventional ROICs, which typically can enhance only one high performance attribute such as frame rate, power consumption or noise level, fail when simultaneously targeting the most aggressive performance requirements demanded in imaging applications today. Additionally, scaling analog readout circuits to meet such requirements leads to expensive, high-power consumption with large and complex systems that are untenable in the trend towards SWaP-C. We present the implementation of a VGA format (640x512 pixels 15μm pitch) capacitivetransimpedance amplifier (CTIA) DROIC architecture that incorporates a 12-bit ADC at the pixel level. The CTIA pixel input circuitry has two gain modes with programmable full-well capacity values of 100K e- and 500K e-. The DROIC has been developed with a system-on-chip architecture in mind, where all the timing and biasing are generated internally without requiring any critical external inputs. The chip is configurable with many parameters programmable through a serial programmable interface (SPI). It features a global shutter, low power, and high frame rates programmable from 30 up 500 frames per second in full VGA format supported through 24 LVDS outputs. This DROIC, suitable for hybridization with focal plane arrays (FPA) is ideal for high-performance uncooled camera applications ranging from near IR (NIR) and shortwave IR (SWIR) to mid-wave IR (MWIR) and long-wave IR (LWIR) spectral bands.

Optical and electrical interfacing technologies for living cell bio-chips.

PubMed

Shacham-Diamand, Y; Belkin, S; Rishpon, J; Elad, T; Melamed, S; Biran, A; Yagur-Kroll, S; Almog, R; Daniel, R; Ben-Yoav, H; Rabner, A; Vernick, S; Elman, N; Popovtzer, R

2010-06-01

Whole-cell bio-chips for functional sensing integrate living cells on miniaturized platforms made by micro-system-technologies (MST). The cells are integrated, deposited or immersed in a media which is in contact with the chip. The cells behavior is monitored via electrical, electrochemical or optical methods. In this paper we describe such whole-cell biochips where the signal is generated due to the genetic response of the cells. The solid-state platform hosts the biological component, i.e. the living cells, and integrates all the required micro-system technologies, i.e. the micro-electronics, micro-electro optics, micro-electro or magneto mechanics and micro-fluidics. The genetic response of the cells expresses proteins that generate: a. light by photo-luminescence or bioluminescence, b. electrochemical signal by interaction with a substrate, or c. change in the cell impedance. The cell response is detected by a front end unit that converts it to current or voltage amplifies and filters it. The resultant signal is analyzed and stored for further processing. In this paper we describe three examples of whole-cell bio chips, photo-luminescent, bioluminescent and electrochemical, which are based on the genetic response of genetically modified E. coli microbes integrated on a micro-fluidics MEMS platform. We describe the chip outline as well as the basic modeling scheme of such sensors. We discuss the highlights and problems of such system, from the point of view of micro-system-technology.

3-D readout-electronics packaging for high-bandwidth massively paralleled imager

DOEpatents

Kwiatkowski, Kris; Lyke, James

2007-12-18

Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a "mirror cube"). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a 45.degree. angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.

First light from a very large area pixel array for high-throughput x-ray polarimetry

NASA Astrophysics Data System (ADS)

Bellazzini, R.; Spandre, G.; Minuti, M.; Baldini, L.; Brez, A.; Cavalca, F.; Latronico, L.; Omodei, N.; Massai, M. M.; Sgrò, C.; Costa, E.; Soffitta, P.; Krummenacher, F.; de Oliveira, R.

2006-06-01

We report on a large active area (15x15mm2), high channel density (470 pixels/mm2), self-triggering CMOS analog chip that we have developed as pixelized charge collecting electrode of a Micropattern Gas Detector. This device, which represents a big step forward both in terms of size and performance, is the last version of three generations of custom ASICs of increasing complexity. The CMOS pixel array has the top metal layer patterned in a matrix of 105600 hexagonal pixels at 50μm pitch. Each pixel is directly connected to the underneath full electronics chain which has been realized in the remaining five metal and single poly-silicon layers of a standard 0.18μm CMOS VLSI technology. The chip has customizable self-triggering capability and includes a signal pre-processing function for the automatic localization of the event coordinates. In this way it is possible to reduce significantly the readout time and the data volume by limiting the signal output only to those pixels belonging to the region of interest. The very small pixel area and the use of a deep sub-micron CMOS technology has brought the noise down to 50 electrons ENC. Results from in depth tests of this device when coupled to a fine pitch (50μm on a triangular pattern) Gas Electron Multiplier are presented. The matching of readout and gas amplification pitch allows getting optimal results. The application of this detector for Astronomical X-Ray Polarimetry is discussed. The experimental detector response to polarized and unpolarized X-ray radiation when working with two gas mixtures and two different photon energies is shown. Results from a full MonteCarlo simulation for several galactic and extragalactic astronomical sources are also reported.

Front-end receiver electronics for a matrix transducer for 3-D transesophageal echocardiography.

PubMed

Yu, Zili; Blaak, Sandra; Chang, Zu-yao; Yao, Jiajian; Bosch, Johan G; Prins, Christian; Lancée, Charles T; de Jong, Nico; Pertijs, Michiel A P; Meijer, Gerard C M

2012-07-01

There is a clear clinical need for creating 3-D images of the heart. One promising technique is the use of transesophageal echocardiography (TEE). To enable 3-D TEE, we are developing a miniature ultrasound probe containing a matrix piezoelectric transducer with more than 2000 elements. Because a gastroscopic tube cannot accommodate the cables needed to connect all transducer elements directly to an imaging system, a major challenge is to locally reduce the number of channels, while maintaining a sufficient signal-to-noise ratio. This can be achieved by using front-end receiver electronics bonded to the transducers to provide appropriate signal conditioning in the tip of the probe. This paper presents the design of such electronics, realizing time-gain compensation (TGC) and micro-beamforming using simple, low-power circuits. Prototypes of TGC amplifiers and micro-beamforming cells have been fabricated in 0.35-μm CMOS technology. These prototype chips have been combined on a printed circuit board (PCB) to form an ultrasound-receiver system capable of reading and combining the signals of three transducer elements. Experimental results show that this design is a suitable candidate for 3-D TEE.

A novel pseudo resistor structure for biomedical front-end amplifiers.

PubMed

Yu-Chieh Huang; Tzu-Sen Yang; Shun-Hsi Hsu; Xin-Zhuang Chen; Jin-Chern Chiou

2015-08-01

This study proposes a novel pseudo resistor structure with a tunable DC bias voltage for biomedical front-end amplifiers (FEAs). In the proposed FEA, the high-pass filter composed of differential difference amplifier and a pseudo resistor is implemented. The FEA is manufactured by using a standard TSMC 0.35 μm CMOS process. In this study, three types FEAs included three different pseudo resistor are simulated, fabricated and measured for comparison and electrocorticography (ECoG) measurement, and all the results show the proposed pseudo resistor is superior to other two types in bandwidth. In chip implementation, the lower and upper cutoff frequencies of the high-pass filter with the proposed pseudo resistor are 0.15 Hz and 4.98 KHz, respectively. It also demonstrates lower total harmonic distortion performance of -58 dB at 1 kHz and higher stability with wide supply range (1.8 V and 3.3 V) and control voltage range (0.9 V and 1.65 V) than others. Moreover, the FEA with the proposed pseudo successfully recorded spike-and-wave discharges of ECoG signal in in vivo experiment on rat with pentylenetetrazol-induced seizures.

A dual slope charge sampling analog front-end for a wireless neural recording system.

PubMed

Lee, Seung Bae; Lee, Byunghun; Gosselin, Benoit; Ghovanloo, Maysam

2014-01-01

This paper presents a novel dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which amplifies neural signals by taking advantage of the charge sampling concept for analog signal conditioning, such as amplification and filtering. The presented DSCS-AFE achieves amplification, filtering, and sampling in a simultaneous fashion, while consuming very small amount of power. The output of the DSCS-AFE produces a pulse width modulated (PWM) signal that is proportional to the input voltage amplitude. A circular shift register (CSR) utilizes time division multiplexing (TDM) of the PWM pulses to create a pseudo-digital TDM-PWM signal that can feed a wireless transmitter. The 8-channel system-on-a-chip was fabricated in a 0.35-μm CMOS process, occupying 2.4 × 2.1 mm(2) and consuming 255 μW from a 1.8V supply. Measured input-referred noise for the entire system, including the FPGA in order to recover PWM signal is 6.50 μV(rms) in the 288 Hz~10 kHz range. For each channel, sampling rate is 31.25 kHz, and power consumption is 31.8 μW.

A Simulation of the Front End Signal Digitization for the ATLAS Muon Spectrometer thin RPC trigger upgrade project

NASA Astrophysics Data System (ADS)

Meng, Xiangting; Chapman, John; Levin, Daniel; Dai, Tiesheng; Zhu, Junjie; Zhou, Bing; Um Atlas Group Team

2016-03-01

The ATLAS Muon Spectrometer Phase-I (and Phase-II) upgrade includes the BIS78 muon trigger detector project: two sets of eight very thin Resistive Place Chambers (tRPCs) combined with small Monitored Drift Tube (MDT) chambers in the pseudorapidity region 1<| η|<1.3. The tRPCs will be comprised of triplet readout layer in each of the eta and azimuthal phi coordinates, with about 400 readout strips per layer. The anticipated hit rate is 100-200 kHz per strip. Digitization of the strip signals will be done by 32-channel CERN HPTDC chips. The HPTDC is a highly configurable ASIC designed by the CERN Microelectronics group. It can work in both trigger and trigger-less modes, be readout in parallel or serially. For Phase-I operation, a stringent latency requirement of 43 bunch crossings (1075 ns) is imposed. The latency budget for the front end digitization must be kept to a minimal value, ideally less than 350 ns. We conducted detailed HPTDC latency simulations using the Behavioral Verilog code from the CERN group. We will report the results of these simulations run for the anticipated detector operating environment and for various HPTDC configurations.

Picosecond Resolution Time-to-Digital Converter Using Gm-C Integrator and SAR-ADC

NASA Astrophysics Data System (ADS)

Xu, Zule; Miyahara, Masaya; Matsuzawa, Akira

2014-04-01

A picosecond resolution time-to-digital converter (TDC) is presented. The resolution of a conventional delay chain TDC is limited by the delay of a logic buffer. Various types of recent TDCs are successful in breaking this limitation, but they require a significant calibration effort to achieve picosecond resolution with a sufficient linear range. To address these issues, we propose a simple method to break the resolution limitation without any calibration: a Gm-C integrator followed by a successive approximation register analog-to-digital converter (SAR-ADC). This translates the time interval into charge, and then the charge is quantized. A prototype chip was fabricated in 90 nm CMOS. The measurement results reveal a 1 ps resolution, a -0.6/0.7 LSB differential nonlinearity (DNL), a -1.1/2.3 LSB integral nonlinearity (INL), and a 9-bit range. The measured 11.74 ps single-shot precision is caused by the noise of the integrator. We analyze the noise of the integrator and propose an improved front-end circuit to reduce this noise. The proposal is verified by simulations showing the maximum single-shot precision is less than 1 ps. The proposed front-end circuit can also diminish the mismatch effects.

A Dual Slope Charge Sampling Analog Front-End for a Wireless Neural Recording System

PubMed Central

Lee, Seung Bae; Lee, Byunghun; Gosselin, Benoit

2015-01-01

This paper presents a novel dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which amplifies neural signals by taking advantage of the charge sampling concept for analog signal conditioning, such as amplification and filtering. The presented DSCS-AFE achieves amplification, filtering, and sampling in a simultaneous fashion, while consuming very small amount of power. The output of the DSCS-AFE produces a pulse width modulated (PWM) signal that is proportional to the input voltage amplitude. A circular shift register (CSR) utilizes time division multiplexing (TDM) of the PWM pulses to create a pseudo-digital TDM-PWM signal that can feed a wireless transmitter. The 8-channel system-on-a-chip was fabricated in a 0.35-µm CMOS process, occupying 2.4 × 2.1 mm2 and consuming 255 µW from a 1.8V supply. Measured input-referred noise for the entire system, including the FPGA in order to recover PWM signal is 6.50 µVrms in the 288 Hz~10 kHz range. For each channel, sampling rate is 31.25 kHz, and power consumption is 31.8 µW. PMID:25570655

Construction and first beam-tests of silicon-tungsten prototype modules for the CMS High Granularity Calorimeter for HL-LHC

NASA Astrophysics Data System (ADS)

Jain, S.

2017-03-01

The High Granularity Calorimeter (HGCAL) is the technology choice of the CMS collaboration for the endcap calorimetry upgrade planned to cope with the harsh radiation and pileup environment at the High Luminosity-LHC . The HGCAL is realized as a sampling calorimeter, including an electromagnetic compartment comprising 28 layers of silicon pad detectors with pad areas of 0.5-01. cm2 interspersed with absorbers made from tungsten and copper to form a highly compact and granular device. Prototype modules, based on hexagonal silicon pad sensors, with 128 channels, have been constructed and tested in beams at FNAL and at CERN. The modules include many of the features required for this challenging detector, including a PCB glued directly to the sensor, using through-hole wire-bonding for signal readout and 5 mm spacing between layers—including the front-end electronics and all services. Tests in 2016 have used an existing front-end chip —Skiroc2 (designed for the CALICE experiment for ILC). We present results from first tests of these modules both in the laboratory and with beams of electrons, pions and protons, including noise performance, calibration with mips and electron signals.

Path planning on cellular nonlinear network using active wave computing technique

NASA Astrophysics Data System (ADS)

Yeniçeri, Ramazan; Yalçın, Müstak E.

2009-05-01

This paper introduces a simple algorithm to solve robot path finding problem using active wave computing techniques. A two-dimensional Cellular Neural/Nonlinear Network (CNN), consist of relaxation oscillators, has been used to generate active waves and to process the visual information. The network, which has been implemented on a Field Programmable Gate Array (FPGA) chip, has the feature of being programmed, controlled and observed by a host computer. The arena of the robot is modelled as the medium of the active waves on the network. Active waves are employed to cover the whole medium with their own dynamics, by starting from an initial point. The proposed algorithm is achieved by observing the motion of the wave-front of the active waves. Host program first loads the arena model onto the active wave generator network and command to start the generation. Then periodically pulls the network image from the generator hardware to analyze evolution of the active waves. When the algorithm is completed, vectorial data image is generated. The path from any of the pixel on this image to the active wave generating pixel is drawn by the vectors on this image. The robot arena may be a complicated labyrinth or may have a simple geometry. But, the arena surface always must be flat. Our Autowave Generator CNN implementation which is settled on the Xilinx University Program Virtex-II Pro Development System is operated by a MATLAB program running on the host computer. As the active wave generator hardware has 16, 384 neurons, an arena with 128 × 128 pixels can be modeled and solved by the algorithm. The system also has a monitor and network image is depicted on the monitor simultaneously.

A Charge Sensitive Pre-Amplifier for Smart Point-of-Care Devices Employing Polymer Based Lab-on-a-Chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Hanfeng; Britton, Charles; Quaiyum, Farhan

With increasing emphasis on implantable and portable medical devices, low-power, small-chip-area sensor readout system realized in lab-on-a-chip (LOC) platform is gaining more and more importance these days. The main building blocks of the LOC system include a front-end transducer that generates an electrical signal in response to the presence of an analyte of interest, signal processing electronics to process the signal to comply with a specific transmission protocol and a low-power transmitter, all realized in a single integrated circuit platform. Low power consumption and compactness of the components are essential requirements of the LOC system. This paper presents a novelmore » charge sensitive pre-amplifier developed in a standard 180-nm CMOS process suitable for implementing in an LOC platform. The pre-amplifier converts the charge generated by a pyroelectric transducer into a voltage signal, which provides a measurement of the temperature variation in biological fluids. The proposed design is capable of providing 0.8-mV/pC gain while consuming only 2.1 μW of power. Finally, the pre-amplifier composed of integrated components occupies an area of 0.038 mm 2.« less

A Charge Sensitive Pre-Amplifier for Smart Point-of-Care Devices Employing Polymer Based Lab-on-a-Chip

DOE PAGES

Wang, Hanfeng; Britton, Charles; Quaiyum, Farhan; ...

2018-01-01

With increasing emphasis on implantable and portable medical devices, low-power, small-chip-area sensor readout system realized in lab-on-a-chip (LOC) platform is gaining more and more importance these days. The main building blocks of the LOC system include a front-end transducer that generates an electrical signal in response to the presence of an analyte of interest, signal processing electronics to process the signal to comply with a specific transmission protocol and a low-power transmitter, all realized in a single integrated circuit platform. Low power consumption and compactness of the components are essential requirements of the LOC system. This paper presents a novelmore » charge sensitive pre-amplifier developed in a standard 180-nm CMOS process suitable for implementing in an LOC platform. The pre-amplifier converts the charge generated by a pyroelectric transducer into a voltage signal, which provides a measurement of the temperature variation in biological fluids. The proposed design is capable of providing 0.8-mV/pC gain while consuming only 2.1 μW of power. Finally, the pre-amplifier composed of integrated components occupies an area of 0.038 mm 2.« less

Readout Electronics for the Forward Vertex Detector at PHENIX

NASA Astrophysics Data System (ADS)

Phillips, Michael

2010-11-01

The PHENIX experiment at RHIC at Brookhaven National Laboratory has been providing high quality physics data for over 10 years. The current PHENIX physics program will be significantly enhanced by addition of the Forward Silicon Vertex upgrade detector (FVTX) in the acceptance of existing muon arm detectors. The proposed tracker is planned to be put into operation in 2012. Each arm of the FVTX detector consist of 4 discs of silicon strip sensors combined with FPHX readout chips, designed at FNAL. The full detector consists of over 1 million active mini-strip channels with instantaneous bandwidth topping 3.4 Tb/s. The FPHX chip utilizes data push architecture with 2 serial output streams at 200 MHz. The readout electronics design consists of Read-Out Cards (ROC) located in the vicinity of the detector and Front End Modules (FEM) located in the Counting House. ROC boards combine the data from several chips, synchronizes data streams and send them to FEM over a Fiber Optics Link. The data are buffered in the FEM and then sent to a standard PHENIX DAQ interface upon Level-1 trigger request. We will present the current status of the readout electronics development and testing, including tests with data from production wedges.

Backside illuminated CMOS-TDI line scan sensor for space applications

NASA Astrophysics Data System (ADS)

Cohen, Omer; Ofer, Oren; Abramovich, Gil; Ben-Ari, Nimrod; Gershon, Gal; Brumer, Maya; Shay, Adi; Shamay, Yaron

2018-05-01

A multi-spectral backside illuminated Time Delayed Integration Radiation Hardened line scan sensor utilizing CMOS technology was designed for continuous scanning Low Earth Orbit small satellite applications. The sensor comprises a single silicon chip with 4 independent arrays of pixels where each array is arranged in 2600 columns with 64 TDI levels. A multispectral optical filter whose spectral responses per array are adjustable per system requirement is assembled at the package level. A custom 4T Pixel design provides the required readout speed, low-noise, very low dark current, and high conversion gains. A 2-phase internally controlled exposure mechanism improves the sensor's dynamic MTF. The sensor high level of integration includes on-chip 12 bit per pixel analog to digital converters, on-chip controller, and CMOS compatible voltage levels. Thus, the power consumption and the weight of the supporting electronics are reduced, and a simple electrical interface is provided. An adjustable gain provides a Full Well Capacity ranging from 150,000 electrons up to 500,000 electrons per column and an overall readout noise per column of less than 120 electrons. The imager supports line rates ranging from 50 to 10,000 lines/sec, with power consumption of less than 0.5W per array. Thus, the sensor is characterized by a high pixel rate, a high dynamic range and a very low power. To meet a Latch-up free requirement RadHard architecture and design rules were utilized. In this paper recent electrical and electro-optical measurements of the sensor's Flight Models will be presented for the first time.

A noiseless, kHz frame rate imaging detector for AO wavefront sensors based on MCPs read out with the Medipix2 CMOS pixel chip

NASA Astrophysics Data System (ADS)

Vallerga, J. V.; McPhate, J. B.; Tremsin, A. S.; Siegmund, O. H. W.; Mikulec, B.; Clark, A. G.

2004-12-01

Future wavefront sensors in adaptive optics (AO) systems for the next generation of large telescopes (> 30 m diameter) will require large formats (512x512) , kHz frame rates, low readout noise (<3 electrons) and high optical QE. The current generation of CCDs cannot achieve the first three of these specifications simultaneously. We present a detector scheme that can meet the first three requirements with an optical QE > 40%. This detector consists of a vacuum tube with a proximity focused GaAs photocathode whose photoelectrons are amplified by microchannel plates and the resulting output charge cloud counted by a pixelated CMOS application specific integrated circuit (ASIC) called the Medipix2 (http://medipix.web.cern.ch/MEDIPIX/). Each 55 micron square pixel of the Medipix2 chip has an amplifier, discriminator and 14 bit counter and the 256x256 array can be read out in 287 microseconds. The chip is 3 side abuttable so a 512x512 array is feasible in one vacuum tube. We will present the first results with an open-faced, demountable version of the detector where we have mounted a pair of MCPs 500 microns above a Medipix2 readout inside a vacuum chamber and illuminated it with UV light. The results include: flat field response, spatial resolution, spatial linearity on the sub-pixel level and global event counting rate. We will also discuss the vacuum tube design and the fabrication issues associated with the Medipix2 surviving the tube making process.

Lossless compression techniques for maskless lithography data

NASA Astrophysics Data System (ADS)

Dai, Vito; Zakhor, Avideh

2002-07-01

Future lithography systems must produce more dense chips with smaller feature sizes, while maintaining the throughput of one wafer per sixty seconds per layer achieved by today's optical lithography systems. To achieve this throughput with a direct-write maskless lithography system, using 25 nm pixels for 50 nm feature sizes, requires data rates of about 10 Tb/s. In a previous paper, we presented an architecture which achieves this data rate contingent on consistent 25 to 1 compression of lithography data, and on implementation of a decoder-writer chip with a real-time decompressor fabricated on the same chip as the massively parallel array of lithography writers. In this paper, we examine the compression efficiency of a spectrum of techniques suitable for lithography data, including two industry standards JBIG and JPEG-LS, a wavelet based technique SPIHT, general file compression techniques ZIP and BZIP2, our own 2D-LZ technique, and a simple list-of-rectangles representation RECT. Layouts rasterized both to black-and-white pixels, and to 32 level gray pixels are considered. Based on compression efficiency, JBIG, ZIP, 2D-LZ, and BZIP2 are found to be strong candidates for application to maskless lithography data, in many cases far exceeding the required compression ratio of 25. To demonstrate the feasibility of implementing the decoder-writer chip, we consider the design of a hardware decoder based on ZIP, the simplest of the four candidate techniques. The basic algorithm behind ZIP compression is Lempel-Ziv 1977 (LZ77), and the design parameters of LZ77 decompression are optimized to minimize circuit usage while maintaining compression efficiency.

Characterization of total ionizing dose damage in COTS pinned photodiode CMOS image sensors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Zujun, E-mail: wangzujun@nint.ac.cn; Ma, Wuying; Huang, Shaoyan

The characterization of total ionizing dose (TID) damage in COTS pinned photodiode (PPD) CMOS image sensors (CISs) is investigated. The radiation experiments are carried out at a {sup 60}Co γ-ray source. The CISs are produced by 0.18-μm CMOS technology and the pixel architecture is 8T global shutter pixel with correlated double sampling (CDS) based on a 4T PPD front end. The parameters of CISs such as temporal domain, spatial domain, and spectral domain are measured at the CIS test system as the EMVA 1288 standard before and after irradiation. The dark current, random noise, dark signal non-uniformity (DSNU), photo responsemore » non-uniformity (PRNU), overall system gain, saturation output, dynamic range (DR), signal to noise ratio (SNR), quantum efficiency (QE), and responsivity versus the TID are reported. The behaviors of the tested CISs show remarkable degradations after radiation. The degradation mechanisms of CISs induced by TID damage are also analyzed.« less

Characterization of total ionizing dose damage in COTS pinned photodiode CMOS image sensors

NASA Astrophysics Data System (ADS)

Wang, Zujun; Ma, Wuying; Huang, Shaoyan; Yao, Zhibin; Liu, Minbo; He, Baoping; Liu, Jing; Sheng, Jiangkun; Xue, Yuan

2016-03-01

The characterization of total ionizing dose (TID) damage in COTS pinned photodiode (PPD) CMOS image sensors (CISs) is investigated. The radiation experiments are carried out at a 60Co γ-ray source. The CISs are produced by 0.18-μm CMOS technology and the pixel architecture is 8T global shutter pixel with correlated double sampling (CDS) based on a 4T PPD front end. The parameters of CISs such as temporal domain, spatial domain, and spectral domain are measured at the CIS test system as the EMVA 1288 standard before and after irradiation. The dark current, random noise, dark signal non-uniformity (DSNU), photo response non-uniformity (PRNU), overall system gain, saturation output, dynamic range (DR), signal to noise ratio (SNR), quantum efficiency (QE), and responsivity versus the TID are reported. The behaviors of the tested CISs show remarkable degradations after radiation. The degradation mechanisms of CISs induced by TID damage are also analyzed.

Analog pixel array detectors.

PubMed

Ercan, A; Tate, M W; Gruner, S M

2006-03-01

X-ray pixel array detectors (PADs) are generally thought of as either digital photon counters (DPADs) or X-ray analog-integrating pixel array detectors (APADs). Experiences with APADs, which are especially well suited for X-ray imaging experiments where transient or high instantaneous flux events must be recorded, are reported. The design, characterization and experimental applications of several APAD designs developed at Cornell University are discussed. The simplest design is a ;flash' architecture, wherein successive integrated X-ray images, as short as several hundred nanoseconds in duration, are stored in the detector chips for later off-chip digitization. Radiography experiments using a prototype flash APAD are summarized. Another design has been implemented that combines flash capability with the ability to continuously stream X-ray images at slower (e.g. milliseconds) rates. Progress is described towards radiation-hardened APADs that can be tiled to cover a large area. A mixed-mode PAD, design by combining many of the attractive features of both APADs and DPADs, is also described.

Life test of the InGaAs focal plane arrays detector for space applications

NASA Astrophysics Data System (ADS)

Zhu, Xian-Liang; Zhang, Hai-Yan; Li, Xue; Huang, Zhang-Cheng; Gong, Hai-Mei

2017-08-01

The short-wavelength infrared (SWIR) InGaAs focal plane array (FPA) detector consists of infrared detector chip, readout integrated circuit (ROIC), and flip-chip bonding interconnection by Indium bump. In order to satisfy space application requirements for failure rates or Mean Time to Failure (MTTF), which can only be demonstrated with the large number of detectors manufactured, the single pixel in InGaAs FPAs was chosen as the research object in this paper. The constant-stress accelerated life tests were carried out at 70°C 80°C 90°C and100°C. The failed pixels increased gradually during more than 14000 hours at each elevated temperatures. From the random failure data the activation energy was estimated to be 0.46eV, and the average lifetime of a single pixel in InGaAs FPAs was estimated to be longer than 1E+7h at the practical operating temperature (5°C).

Capacitively coupled hybrid pixel assemblies for the CLIC vertex detector

NASA Astrophysics Data System (ADS)

Tehrani, N. Alipour; Arfaoui, S.; Benoit, M.; Dannheim, D.; Dette, K.; Hynds, D.; Kulis, S.; Perić, I.; Petrič, M.; Redford, S.; Sicking, E.; Valerio, P.

2016-07-01

The vertex detector at the proposed CLIC multi-TeV linear e+e- collider must have minimal material content and high spatial resolution, combined with accurate time-stamping to cope with the expected high rate of beam-induced backgrounds. One of the options being considered is the use of active sensors implemented in a commercial high-voltage CMOS process, capacitively coupled to hybrid pixel ASICs. A prototype of such an assembly, using two custom designed chips (CCPDv3 as active sensor glued to a CLICpix readout chip), has been characterised both in the lab and in beam tests at the CERN SPS using 120 GeV/c positively charged hadrons. Results of these characterisation studies are presented both for single and dual amplification stages in the active sensor, where efficiencies of greater than 99% have been achieved at -60 V substrate bias, with a single hit resolution of 6.1 μm . Pixel cross-coupling results are also presented, showing the sensitivity to placement precision and planarity of the glue layer.

Dose-dependent X-ray measurements using a 64×64 hybrid GaAs pixel detector with photon counting

NASA Astrophysics Data System (ADS)

Schwarz, C.; Campbell, M.; Goeppert, R.; Ludwig, J.; Mikulec, B.; Rogalla, M.; Runge, K.; Soeldner-Rembold, A.; Smith, K. M.; Snoeys, W.; Watt, J.

2001-03-01

New developments in medical imaging head towards semiconductor detectors flip-chip bonded to CMOS readout chips. In this work, detectors fabricated on SI-GaAs bulk material were bonded to Photon Counting Chips. This PCC consists of a matrix of 64×64 identical square pixels (170 μm×170 μm) with a 15-bit counter in each cell. We investigated the imaging properties of these detector systems under exposure of a dental X-ray tube. First, a dose calibration of the X-ray tube was performed. Fixed pattern noise in flood exposure images was determined for a fixed dose and an image correction method, which uses a gain map, was applied. For characterising the imaging properties, the signal-to-noise ratio (SNR) was calculated as function of exposure dose. Finally, the dynamic range of the system was estimated. Developed in the framework of the MEDIPIX collaboration: CERN, Universities of Freiburg, Glasgow, Naples and Pisa.

MAPS development for the ALICE ITS upgrade

NASA Astrophysics Data System (ADS)

Yang, P.; Aglieri, G.; Cavicchioli, C.; Chalmet, P. L.; Chanlek, N.; Collu, A.; Gao, C.; Hillemanns, H.; Junique, A.; Kofarago, M.; Keil, M.; Kugathasan, T.; Kim, D.; Kim, J.; Lattuca, A.; Marin Tobon, C. A.; Marras, D.; Mager, M.; Martinengo, P.; Mazza, G.; Mugnier, H.; Musa, L.; Puggioni, C.; Rousset, J.; Reidt, F.; Riedler, P.; Snoeys, W.; Siddhanta, S.; Usai, G.; van Hoorne, J. W.; Yi, J.

2015-03-01

Monolithic Active Pixel Sensors (MAPS) offer the possibility to build pixel detectors and tracking layers with high spatial resolution and low material budget in commercial CMOS processes. Significant progress has been made in the field of MAPS in recent years, and they are now considered for the upgrades of the LHC experiments. This contribution will focus on MAPS detectors developed for the ALICE Inner Tracking System (ITS) upgrade and manufactured in the TowerJazz 180 nm CMOS imaging sensor process on wafers with a high resistivity epitaxial layer. Several sensor chip prototypes have been developed and produced to optimise both charge collection and readout circuitry. The chips have been characterised using electrical measurements, radioactive sources and particle beams. The tests indicate that the sensors satisfy the ALICE requirements and first prototypes with the final size of 1.5 × 3 cm2 have been produced in the first half of 2014. This contribution summarises the characterisation measurements and presents first results from the full-scale chips.

The Phase-II ATLAS ITk pixel upgrade

NASA Astrophysics Data System (ADS)

Terzo, S.

2017-07-01

The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase-II shutdown (foreseen to take place around 2025) by an all-silicon detector called the ``ITk'' (Inner Tracker). The innermost portion of ITk will consist of a pixel detector with five layers in the barrel region and ring-shaped supports in the end-cap regions. It will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation levels. The new pixel system could include up to 14 m2 of silicon, depending on the final layout, which is expected to be decided in 2017. Several layout options are being investigated at the moment, including some with novel inclined support structures in the barrel end-cap overlap region and others with very long innermost barrel layers. Forward coverage could be as high as |eta| <4. Supporting structures will be based on low mass, highly stable and highly thermally conductive carbon-based materials cooled by evaporative carbon dioxide circulated in thin-walled titanium pipes embedded in the structures. Planar, 3D, and CMOS sensors are being investigated to identify the optimal technology, which may be different for the various layers. The RD53 Collaboration is developing the new readout chip. The pixel off-detector readout electronics will be implemented in the framework of the general ATLAS trigger and DAQ system. A readout speed of up to 5 Gb/s per data link will be needed in the innermost layers going down to 640 Mb/s for the outermost. Because of the very high radiation level inside the detector, the first part of the transmission has to be implemented electrically, with signals converted for optical transmission at larger radii. Extensive tests are being carried out to prove the feasibility of implementing serial powering, which has been chosen as the baseline for the ITk pixel system due to the reduced material in the servicing cables foreseen for this option.

CMOS VLSI Active-Pixel Sensor for Tracking

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The diagonal-switch and memory addresses would be generated by the on-chip controller. The memory array would be large enough to hold differential signals acquired from all 8 windows during a frame period. Following the rapid sampling from all the windows, the contents of the memory array would be read out sequentially by use of a capacitive transimpedance amplifier (CTIA) at a maximum data rate of 10 MHz. This data rate is compatible with an update rate of almost 10 Hz, even in full-frame operation

Beam test results of the BTeV silicon pixel detector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gabriele Chiodini et al.

2000-09-28

The authors have described the results of the BTeV silicon pixel detector beam test. The pixel detectors under test used samples of the first two generations of Fermilab pixel readout chips, FPIX0 and FPIX1, (indium bump-bonded to ATLAS sensor prototypes). The spatial resolution achieved using analog charge information is excellent for a large range of track inclination. The resolution is still very good using only 2-bit charge information. A relatively small dependence of the resolution on bias voltage is observed. The resolution is observed to depend dramatically on the discriminator threshold, and it deteriorates rapidly for threshold above 4000e{sup {minus}}.

Cryogenic bolometric systems

NASA Astrophysics Data System (ADS)

Kangas, Miikka Matias

The big bang, early galaxy formation, the interstellar medium, and high z galaxy cluster evolution are all science objectives that are studied in the far infrared (FIR). The cosmological parameters that describe the universe are encoded in anisotropies in the Cosmic Microwave Background (CMB), and can be extracted from precision subdegree angular resolution FIR maps. Cryogenic bolometers are well suited for these science objectives, and are evolving rapidly today. A cryogenic bolometric system is made up of a few building blocks, which can be modularized or integrated depending on the maturity of the scientific field they are used for. Integration of systems increases with the maturity of the technology. The basic building blocks are the bolometer, the cryogenics, the dewar, the optics, the filters, and electronics. The electronics can be further subdivided into room temperature back-end and cryogenic front-end electronics. The electronics are often partly integrated into the dewar. The dewar is part of the support structure, and only the subkelvin portion the dewar is referred to as cryogenics here. Each of these can be a sophisticated engineering feat on their own, and this dissertation revolves around the development of several of these elements. The microfabrication sequence for a free standing micromesh detector was developed. Polarization preserving photometer optics and filters were constructed and tested. A test dewar mechanical and optical structure was created to test single pixel photometers prior to mounting in the flight dewar. A modular flight dewar capable of holding an array of photometers and adaptable to a number of different cryogenics schemes and detector arrays was engineered and constructed. A zero gravity dilution refrigerator coil was constructed and tested. A corrugated platelet array concept was designed and tested. Metal mesh filter design and fabrication techniques were developed. Kevlar isolator structures were improved to work in subkelvin dewars, and detector modules that mounted the bolometer chips to the photometer tubes were created. These subsystems underwent testing to compare the predicted behavior and actual performance.

FRONT DETAIL OF RIGHT ENGINE AND WING. MECHANICS CHECK METAL ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

FRONT DETAIL OF RIGHT ENGINE AND WING. MECHANICS CHECK METAL CHIP DETECTOR ON RIGHT ENGINE. THE LEADING EDGE FLAPS ON THE RIGHT WING ARE DOWN PRIOR TO LUBRICATION. - Greater Buffalo International Airport, Maintenance Hangar, Buffalo, Erie County, NY

Thermal ink-jet device using single-chip silicon microchannels

NASA Astrophysics Data System (ADS)

Wuu, DongSing; Cheng, Chen-Yue; Horng, RayHua; Chan, G. C.; Chiu, Sao-Ling; Wu, Yi-Yung

1998-06-01

We present a new method to fabricate silicon microfluidic channels by through-hole etching with subsequent planarization. The method is based on etching out the deep grooves through a perforated silicon carbide membrane, followed by sealing the membrane with plasma-enhanced chemical vapor deposition (PECVD). Low-pressure-chemical-vapor- deposited (LPCVD) polysilicon was used as a sacrificial layer to define the channel structure and only one etching step is required. This permits the realization of planarization after a very deep etching step in silicon and offers the possibility for film deposition, resist spinning and film patterning across deep grooves. The process technology was demonstrated on the fabrication of a monolithic silicon microchannel structure for thermal inkjet printing. The Ta-Al heater arrays are integrated on the top of each microchannel, which connect to a common on-chip front-end ink reservoir. The fabrication of this device requires six masks and no active nozzle-to-chip alignment. Moreover, the present micromachining process is compatible with the addition of on-chip circuitry for multiplexing the heater control signals. Heat transfer efficiency to the ink is enhanced by the high thermal conductivity of the silicon carbide in the channel ceiling, while the bulk silicon maintains high interchannel isolation. The fabricated inkjet devices show the droplet sizes of 20 - 50 micrometer in diameter with various channel dimensions and stable ejection of ink droplets more than 1 million.

Giga-pixel lensfree holographic microscopy and tomography using color image sensors.

PubMed

Isikman, Serhan O; Greenbaum, Alon; Luo, Wei; Coskun, Ahmet F; Ozcan, Aydogan

2012-01-01

We report Giga-pixel lensfree holographic microscopy and tomography using color sensor-arrays such as CMOS imagers that exhibit Bayer color filter patterns. Without physically removing these color filters coated on the sensor chip, we synthesize pixel super-resolved lensfree holograms, which are then reconstructed to achieve ~350 nm lateral resolution, corresponding to a numerical aperture of ~0.8, across a field-of-view of ~20.5 mm(2). This constitutes a digital image with ~0.7 Billion effective pixels in both amplitude and phase channels (i.e., ~1.4 Giga-pixels total). Furthermore, by changing the illumination angle (e.g., ± 50°) and scanning a partially-coherent light source across two orthogonal axes, super-resolved images of the same specimen from different viewing angles are created, which are then digitally combined to synthesize tomographic images of the object. Using this dual-axis lensfree tomographic imager running on a color sensor-chip, we achieve a 3D spatial resolution of ~0.35 µm × 0.35 µm × ~2 µm, in x, y and z, respectively, creating an effective voxel size of ~0.03 µm(3) across a sample volume of ~5 mm(3), which is equivalent to >150 Billion voxels. We demonstrate the proof-of-concept of this lensfree optical tomographic microscopy platform on a color CMOS image sensor by creating tomograms of micro-particles as well as a wild-type C. elegans nematode.

Wireless biopotential acquisition system for portable healthcare monitoring.

PubMed

Wang, W-S; Huang, H-Y; Wu, Z-C; Chen, S-C; Wang, W-F; Wu, C-F; Luo, C-H

2011-07-01

A complete biopotential acquisition system with an analogue front-end (AFE) chip is proposed for portable healthcare monitoring. A graphical user interface (GUI) is also implemented to display the extracted biopotential signals in real-time on a computer for patients or in a hospital via the internet for doctors. The AFE circuit defines the quality of the acquired biosignals. Thus, an AFE chip with low power consumption and a high common-mode rejection ratio (CMRR) was implemented in the TSMC 0.18-μm CMOS process. The measurement results show that the proposed AFE, with a core area of 0.1 mm(2), has a CMRR of 90 dB, and power consumption of 21.6 μW. Biopotential signals of electroencephalogram (EEG), electrocardiogram (ECG) and electromyogram (EMG) were measured to verify the proposed system. The board size of the proposed system is 6 cm × 2.5 cm and the weight is 30 g. The total power consumption of the proposed system is 66 mW. Copyright © 2011 Informa UK, Ltd.

Silicon drift detectors with on-chip electronics for x-ray spectroscopy.

PubMed

Fiorini, C; Longoni, A; Hartmann, R; Lechner, P; Strüder, L

1997-01-01

The silicon drift detector (SDD) is a semiconductor device based on high resistivity silicon fully depleted through junctions implanted on both sides of the semiconductor wafer. The electrons generated by the ionizing radiation are driven by means of a suitable electric field from the point of interaction toward a collecting anode of small capacitance, independent of the active area of the detector. A suitably designed front-end JFET has been directly integrated on the detector chip close to the anode region, in order to obtain a nearly ideal capacitive matching between detector and transistor and to minimize the stray capacitances of the connections. This feature allows it to reach high energy resolution also at high count rates and near room temperature. The present work describes the structure and the performance of SDDs specially designed for high resolution spectroscopy with soft x rays at high detection rate. Experimental results of SDDs used in spectroscopy applications are also reported.

MICROROC: MICRO-mesh gaseous structure Read-Out Chip

NASA Astrophysics Data System (ADS)

Adloff, C.; Blaha, J.; Chefdeville, M.; Dalmaz, A.; Drancourt, C.; Dulucq, F.; Espargilière, A.; Gaglione, R.; Geffroy, N.; Jacquemier, J.; Karyotakis, Y.; Martin-Chassard, G.; Prast, J.; Seguin-Moreau, N.; de La Taille, Ch; Vouters, G.

2012-01-01

MICRO MEsh GAseous Structure (MICROMEGAS) and Gas Electron Multipliers (GEM) detectors are two candidates for the active medium of a Digital Hadronic CALorimeter (DHCAL) as part of a high energy physics experiment at a future linear collider (ILC/CLIC). Physics requirements lead to a highly granular hadronic calorimeter with up to thirty million channels with probably only hit information (digital readout calorimeter). To validate the concept of digital hadronic calorimetry with such small cell size, the construction and test of a cubic meter technological prototype, made of 40 planes of one square meter each, is necessary. This technological prototype would contain about 400 000 electronic channels, thus requiring the development of front-end ASIC. Based on the experience gained with previous ASIC that were mounted on detectors and tested in particle beams, a new ASIC called MICROROC has been developped. This paper summarizes the caracterisation campaign that was conducted on this new chip as well as its integration into a large area Micromegas chamber of one square meter.

Report on recent results of the PERCIVAL soft X-ray imager

NASA Astrophysics Data System (ADS)

Khromova, A.; Cautero, G.; Giuressi, D.; Menk, R.; Pinaroli, G.; Stebel, L.; Correa, J.; Marras, A.; Wunderer, C. B.; Lange, S.; Tennert, M.; Niemann, M.; Hirsemann, H.; Smoljanin, S.; Reza, S.; Graafsma, H.; Göttlicher, P.; Shevyakov, I.; Supra, J.; Xia, Q.; Zimmer, M.; Guerrini, N.; Marsh, B.; Sedgwick, I.; Nicholls, T.; Turchetta, R.; Pedersen, U.; Tartoni, N.; Hyun, H. J.; Kim, K. S.; Rah, S. Y.; Hoenk, M. E.; Jewell, A. D.; Jones, T. J.; Nikzad, S.

2016-11-01

The PERCIVAL (Pixelated Energy Resolving CMOS Imager, Versatile And Large) soft X-ray 2D imaging detector is based on stitched, wafer-scale sensors possessing a thick epi-layer, which together with back-thinning and back-side illumination yields elevated quantum efficiency in the photon energy range of 125-1000 eV. Main application fields of PERCIVAL are foreseen in photon science with FELs and synchrotron radiation. This requires high dynamic range up to 105 ph @ 250 eV paired with single photon sensitivity with high confidence at moderate frame rates in the range of 10-120 Hz. These figures imply the availability of dynamic gain switching on a pixel-by-pixel basis and a highly parallel, low noise analog and digital readout, which has been realized in the PERCIVAL sensor layout. Different aspects of the detector performance have been assessed using prototype sensors with different pixel and ADC types. This work will report on the recent test results performed on the newest chip prototypes with the improved pixel and ADC architecture. For the target frame rates in the 10-120 Hz range an average noise floor of 14e- has been determined, indicating the ability of detecting single photons with energies above 250 eV. Owing to the successfully implemented adaptive 3-stage multiple-gain switching, the integrated charge level exceeds 4 · 106 e- or 57000 X-ray photons at 250 eV per frame at 120 Hz. For all gains the noise level remains below the Poisson limit also in high-flux conditions. Additionally, a short overview over the updates on an oncoming 2 Mpixel (P2M) detector system (expected at the end of 2016) will be reported.

A custom readout electronics for the BESIII CGEM detector

NASA Astrophysics Data System (ADS)

Da Rocha Rolo, M.; Alexeev, M.; Amoroso, A.; Baldini Ferroli, R.; Bertani, M.; Bettoni, D.; Bianchi, F.; Bugalho, R.; Calcaterra, A.; Canale, N.; Capodiferro, M.; Carassiti, V.; Cerioni, S.; Chai, J. Y.; Chiozzi, S.; Cibinetto, G.; Cossio, F.; Cotta Ramusino, A.; De Mori, F.; Destefanis, M.; Di Francesco, A.; Dong, J.; Evangelisti, F.; Farinelli, R.; Fava, L.; Felici, G.; Fioravanti, E.; Garzia, I.; Gatta, M.; Greco, M.; Lavezzi, L.; Leng, C. Y.; Li, H.; Maggiora, M.; Malaguti, R.; Marcello, S.; Marciniewski, P.; Melchiorri, M.; Mezzadri, G.; Mignone, M.; Morello, G.; Pacetti, S.; Patteri, P.; Pellegrino, J.; Pelosi, A.; Rivetti, A.; Savrié, M.; Scodeggio, M.; Soldani, E.; Sosio, S.; Spataro, S.; Tskhadadze, E.; Varela, J.; Verma, S.; Wheadon, R.; Yan, L.

2017-07-01

For the upgrade of the inner tracker of the BESIII spectrometer, planned for 2018, a lightweight tracker based on an innovative Cylindrical Gas Electron Multiplier (CGEM) detector is now under development. The analogue readout of the CGEM enables the use of a charge centroid algorithm to improve the spatial resolution to better than 130 μm while loosening the pitch strip to 650 μm, which allows to reduce the total number of channels to about 10 000. The channels are readout by 160 dedicated integrated 64-channel front-end ASICs, providing a time and charge measurement and featuring a fully-digital output. The energy measurement is extracted either from the time-over-threshold (ToT) or the 10-bit digitisation of the peak amplitude of the signal. The time of the event is generated by quad-buffered low-power TDCs, allowing for rates in excess of 60 kHz per channel. The TDCs are based on analogue interpolation techniques and produce a time stamp (or two, if working in ToT mode) of the event with a time resolution better than 50 ps. The front-end noise, based on a CSA and a two-stage complex conjugated pole shapers, dominate the channel intrinsic time jitter, which is less than 5 ns r.m.s. The time information of the hit can be used to reconstruct the track path, operating the detector as a small TPC and hence improving the position resolution when the distribution of the cloud, due to large incident angle or magnetic field, is very broad. Event data is collected by an off-detector motherboard, where each GEM-ROC readout card handles 4 ASIC carrier FEBs (512 channels). Configuration upload and data readout between the off-detector electronics and the VME-based data collector cards are managed by bi-directional fibre optical links. This paper covers the design of a custom front-end electronics for the readout of the new inner tracker of the BESIII experiment, addressing the relevant design aspects of the detector electronics and the front-end ASIC for the CGEM readout, and reviewing the first silicon results of the chip prototype.

Fast wire per wire X-ray data acquisition system for time-resolved small angle scattering experiments

NASA Astrophysics Data System (ADS)

Epstein, A.; Briquet-Laugier, F.; Sheldon, S.; Boulin, C.

2000-04-01

Most of the X-ray multi-wire gas detectors used at the EMBL Hamburg outstation for time-resolved studies of biological samples are readout, using the delay line method. The main disadvantage of such readout systems is their event rate limitation introduced by the delay line and the required time to digital conversion step. They also lack the possibility to deal with multiple events. To overcome these limitations, a new approach for the complete readout system was introduced. The new linear detection system is based on the wire per wire approach where each individual wire is associated to preamplifier/discriminator/counter electronics channel. High-density, front-end electronics were designed around a fast current sensitive preamplifier. An eight-channel board was designed to include the preamplifiers-discriminators and the differential ECL drivers output stages. The detector front-end consists of 25 boards directly mounted inside the detector assembly. To achieve a time framing resolution as short as 10 /spl mu/s, very fast histogramming is required. The only way to implement this for a high number of channels (200 in our case) is by using a distributed system. The digital part of the system consists of a crate controller, up to 16 acquisition boards (capable of handling fast histogramming for up to 32-channels each) and an optical-link board (based on the Cypress "Hot-Link" chip set). Both the crate controller and the acquisition boards are based on a standard RISC microcontroller (IDT R3081) plug-in board. At present, a dedicated CAMAC module which we developed is used to interface the digital front-end acquisition crate to the host via the optical link.

All-digital full waveform recording photon counting flash lidar

NASA Astrophysics Data System (ADS)

Grund, Christian J.; Harwit, Alex

2010-08-01

Current generation analog and photon counting flash lidar approaches suffer from limitation in waveform depth, dynamic range, sensitivity, false alarm rates, optical acceptance angle (f/#), optical and electronic cross talk, and pixel density. To address these issues Ball Aerospace is developing a new approach to flash lidar that employs direct coupling of a photocathode and microchannel plate front end to a high-speed, pipelined, all-digital Read Out Integrated Circuit (ROIC) to achieve photon-counting temporal waveform capture in each pixel on each laser return pulse. A unique characteristic is the absence of performance-limiting analog or mixed signal components. When implemented in 65nm CMOS technology, the Ball Intensified Imaging Photon Counting (I2PC) flash lidar FPA technology can record up to 300 photon arrivals in each pixel with 100 ps resolution on each photon return, with up to 6000 range bins in each pixel. The architecture supports near 100% fill factor and fast optical system designs (f/#<1), and array sizes to 3000×3000 pixels. Compared to existing technologies, >60 dB ultimate dynamic range improvement, and >104 reductions in false alarm rates are anticipated, while achieving single photon range precision better than 1cm. I2PC significantly extends long-range and low-power hard target imaging capabilities useful for autonomous hazard avoidance (ALHAT), navigation, imaging vibrometry, and inspection applications, and enables scannerless 3D imaging for distributed target applications such as range-resolved atmospheric remote sensing, vegetation canopies, and camouflage penetration from terrestrial, airborne, GEO, and LEO platforms. We discuss the I2PC architecture, development status, anticipated performance advantages, and limitations.

Development of a 750x750 pixels CMOS imager sensor for tracking applications

NASA Astrophysics Data System (ADS)

Larnaudie, Franck; Guardiola, Nicolas; Saint-Pé, Olivier; Vignon, Bruno; Tulet, Michel; Davancens, Robert; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Estribeau, Magali

2017-11-01

Solid-state optical sensors are now commonly used in space applications (navigation cameras, astronomy imagers, tracking sensors...). Although the charge-coupled devices are still widely used, the CMOS image sensor (CIS), which performances are continuously improving, is a strong challenger for Guidance, Navigation and Control (GNC) systems. This paper describes a 750x750 pixels CMOS image sensor that has been specially designed and developed for star tracker and tracking sensor applications. Such detector, that is featuring smart architecture enabling very simple and powerful operations, is built using the AMIS 0.5μm CMOS technology. It contains 750x750 rectangular pixels with 20μm pitch. The geometry of the pixel sensitive zone is optimized for applications based on centroiding measurements. The main feature of this device is the on-chip control and timing function that makes the device operation easier by drastically reducing the number of clocks to be applied. This powerful function allows the user to operate the sensor with high flexibility: measurement of dark level from masked lines, direct access to the windows of interest… A temperature probe is also integrated within the CMOS chip allowing a very precise measurement through the video stream. A complete electro-optical characterization of the sensor has been performed. The major parameters have been evaluated: dark current and its uniformity, read-out noise, conversion gain, Fixed Pattern Noise, Photo Response Non Uniformity, quantum efficiency, Modulation Transfer Function, intra-pixel scanning. The characterization tests are detailed in the paper. Co60 and protons irradiation tests have been also carried out on the image sensor and the results are presented. The specific features of the 750x750 image sensor such as low power CMOS design (3.3V, power consumption<100mW), natural windowing (that allows efficient and robust tracking algorithms), simple proximity electronics (because of the on-chip control and timing function) enabling a high flexibility architecture, make this imager a good candidate for high performance tracking applications.

An Integrated Imaging Detector of Polarization and Spectral Content

NASA Technical Reports Server (NTRS)

Rust, D. M.; Thompson, K. E.

1993-01-01

A new type of image detector has been designed to simultaneously analyze the polarization of light at all picture elements in a scene. The Integrated Dual Imaging Detector (IDID) consists of a polarizing beamsplitter bonded to a charge-coupled device (CCD), with signal-analysis circuitry and analog-to-digital converters, all integrated on a silicon chip. It should be capable of 1:10(exp 4) polarization discrimination. The IDID should simplify the design and operation of imaging polarimeters and spectroscopic imagers used, for example, in atmospheric and solar research. Innovations in the IDID include (1) two interleaved 512 x 1024-pixel imaging arrays (one for each polarization plane); (2) large dynamic range (well depth of 10(exp 6) electrons per pixel); (3) simultaneous readout of both images at 10 million pixels per second each; (4) on-chip analog signal processing to produce polarization maps in real time; (5) on-chip 10-bit A/D conversion. When used with a lithium-niobate Fabry-Perot etalon or other color filter that can encode spectral information as polarization, the IDID can collect and analyze simultaneous images at two wavelengths. Precise photometric analysis of molecular or atomic concentrations in the atmosphere is one suggested application. When used in a solar telescope, the IDID will charge the polarization, which can then be converted to maps of the vector magnetic fields on the solar surface.

Printing Peptide arrays with a complementary metal oxide semiconductor chip.

PubMed

Loeffler, Felix F; Cheng, Yun-Chien; Muenster, Bastian; Striffler, Jakob; Liu, Fanny C; Ralf Bischoff, F; Doersam, Edgar; Breitling, Frank; Nesterov-Mueller, Alexander

2013-01-01

: In this chapter, we discuss the state-of-the-art peptide array technologies, comparing the spot technique, lithographical methods, and microelectronic chip-based approaches. Based on this analysis, we describe a novel peptide array synthesis method with a microelectronic chip printer. By means of a complementary metal oxide semiconductor chip, charged bioparticles can be patterned on its surface. The bioparticles serve as vehicles to transfer molecule monomers to specific synthesis spots. Our chip offers 16,384 pixel electrodes on its surface with a spot-to-spot pitch of 100 μm. By switching the voltage of each pixel between 0 and 100 V separately, it is possible to generate arbitrary particle patterns for combinatorial molecule synthesis. Afterwards, the patterned chip surface serves as a printing head to transfer the particle pattern from its surface to a synthesis substrate. We conducted a series of proof-of-principle experiments to synthesize high-density peptide arrays. Our solid phase synthesis approach is based on the 9-fluorenylmethoxycarbonyl protection group strategy. After melting the particles, embedded monomers diffuse to the surface and participate in the coupling reaction to the surface. The method demonstrated herein can be easily extended to the synthesis of more complicated artificial molecules by using bioparticles with artificial molecular building blocks. The possibility of synthesizing artificial peptides was also shown in an experiment in which we patterned biotin particles in a high-density array format. These results open the road to the development of peptide-based functional modules for diverse applications in biotechnology.

CdTe Based Hard X-ray Imager Technology For Space Borne Missions

NASA Astrophysics Data System (ADS)

Limousin, Olivier; Delagnes, E.; Laurent, P.; Lugiez, F.; Gevin, O.; Meuris, A.

2009-01-01

CEA Saclay has recently developed an innovative technology for CdTe based Pixelated Hard X-Ray Imagers with high spectral performance and high timing resolution for efficient background rejection when the camera is coupled to an active veto shield. This development has been done in a R&D program supported by CNES (French National Space Agency) and has been optimized towards the Simbol-X mission requirements. In the latter telescope, the hard X-Ray imager is 64 cm² and is equipped with 625µm pitch pixels (16384 independent channels) operating at -40°C in the range of 4 to 80 keV. The camera we demonstrate in this paper consists of a mosaic of 64 independent cameras, divided in 8 independent sectors. Each elementary detection unit, called Caliste, is the hybridization of a 256-pixel Cadmium Telluride (CdTe) detector with full custom front-end electronics into a unique 1 cm² component, juxtaposable on its four sides. Recently, promising results have been obtained from the first micro-camera prototypes called Caliste 64 and will be presented to illustrate the capabilities of the device as well as the expected performance of an instrument based on it. The modular design of Caliste enables to consider extended developments toward IXO type mission, according to its specific scientific requirements.

A 1.2 Gb/s Data Transmission Unit in CMOS 0.18 μm technology for the ALICE Inner Tracking System front-end ASIC

NASA Astrophysics Data System (ADS)

Mazza, G.; Aglieri Rinella, G.; Benotto, F.; Corrales Morales, Y.; Kugathasan, T.; Lattuca, A.; Lupi, M.; Ravasenga, I.

2017-02-01

The upgrade of the ALICE Inner Tracking System is based on a Monolithic Active Pixel Sensor and ASIC designed in a CMOS 0.18 μ m process. In order to provide the required output bandwidth (1.2 Gb/s for the inner layers and 400 Mb/s for the outer ones) on a single high speed serial link, a custom Data Transmission Unit (DTU) has been developed in the same process. The DTU includes a clock multiplier PLL, a double data rate serializer and a pseudo-LVDS driver with pre-emphasis and is designed to be SEU tolerant.

The High Energy Detector of Simbol-X

NASA Astrophysics Data System (ADS)

Meuris, A.; Limousin, O.; Lugiez, F.; Gevin, O.; Blondel, C.; Le Mer, I.; Pinsard, F.; Cara, C.; Goetschy, A.; Martignac, J.; Tauzin, G.; Hervé, S.; Laurent, P.; Chipaux, R.; Rio, Y.; Fontignie, J.; Horeau, B.; Authier, M.; Ferrando, P.

2009-05-01

The High Energy Detector (HED) is one of the three detection units on board the Simbol-X detector spacecraft. It is placed below the Low Energy Detector so as to collect focused photons in the energy range from 8 to 80 keV. It consists of a mosaic of 64 independent cameras, divided in 8 sectors. Each elementary detection unit, called Caliste, is the hybridization of a 256-pixel Cadmium Telluride (CdTe) detector with full custom front-end electronics into a unique component. The status of the HED design will be reported. The promising results obtained from the first micro-camera prototypes called Caliste 64 and Caliste 256 will be presented to illustrate the expected performance of the instrument.

Photovoltaic Retinal Prosthesis for Restoring Sight to Patients Blinded by Retinal Injury or Degeneration

DTIC Science & Technology

2016-02-01

are rapidly expanding [1][2]. Cochlear implants [3] have seen the most remarkable success in sensory neuroprosthetics, while retinal implants [4][5...intensities: Imax (bright pixels) and Imin (dark pixels). In the common return configurations (connected and monopolar), the current flowing through the...array forces the injected current to flow to the back side, which results in a potential build-up in front of the device. Near each pixel (within

High-resolution CCD imaging alternatives

NASA Astrophysics Data System (ADS)

Brown, D. L.; Acker, D. E.

1992-08-01

High resolution CCD color cameras have recently stimulated the interest of a large number of potential end-users for a wide range of practical applications. Real-time High Definition Television (HDTV) systems are now being used or considered for use in applications ranging from entertainment program origination through digital image storage to medical and scientific research. HDTV generation of electronic images offers significant cost and time-saving advantages over the use of film in such applications. Further in still image systems electronic image capture is faster and more efficient than conventional image scanners. The CCD still camera can capture 3-dimensional objects into the computing environment directly without having to shoot a picture on film develop it and then scan the image into a computer. 2. EXTENDING CCD TECHNOLOGY BEYOND BROADCAST Most standard production CCD sensor chips are made for broadcast-compatible systems. One popular CCD and the basis for this discussion offers arrays of roughly 750 x 580 picture elements (pixels) or a total array of approximately 435 pixels (see Fig. 1). FOR. A has developed a technique to increase the number of available pixels for a given image compared to that produced by the standard CCD itself. Using an inter-lined CCD with an overall spatial structure several times larger than the photo-sensitive sensor areas each of the CCD sensors is shifted in two dimensions in order to fill in spatial gaps between adjacent sensors.

Tracking Detectors in the STAR Experiment at RHIC

NASA Astrophysics Data System (ADS)

Wieman, Howard

2015-04-01

The STAR experiment at RHIC is designed to measure and identify the thousands of particles produced in 200 Gev/nucleon Au on Au collisions. This talk will focus on the design and construction of two of the main tracking detectors in the experiment, the TPC and the Heavy Flavor Tracker (HFT) pixel detector. The TPC is a solenoidal gas filled detector 4 meters in diameter and 4.2 meters long. It provides precise, continuous tracking and rate of energy loss in the gas (dE/dx) for particles at + - 1 units of pseudo rapidity. The tracking in a half Tesla magnetic field measures momentum and dE/dX provides particle ID. To detect short lived particles tracking close to the point of interaction is required. The HFT pixel detector is a two-layered, high resolution vertex detector located at a few centimeters radius from the collision point. It determines origins of the tracks to a few tens of microns for the purpose of extracting displaced vertices, allowing the identification of D mesons and other short-lived particles. The HFT pixel detector uses detector chips developed by the IPHC group at Strasbourg that are based on standard IC Complementary Metal-Oxide-Semiconductor (CMOS) technology. This is the first time that CMOS pixel chips have been incorporated in a collider application.

Identification, characteristics and seasonal evolution of surface thermal fronts in the Argentinean Continental Shelf

NASA Astrophysics Data System (ADS)

Rivas, Andrés L.; Pisoni, Juan Pablo

2010-01-01

The location and seasonal variability of surface thermal fronts along the Argentinean Continental Shelf (38-55°S) were studied using 18 years (1985-2002) of sea surface temperature (SST) satellite data. Monthly SST gradients were calculated and a threshold was used to identify frontal pixels. Frontal areas were classified into 4 zones according to their seasonal evolution and the main forcings leading to the front's formation were identified for each group. The shelf break front was easily detected due to the large number of frontal pixels in the region and its high mean gradient values. This front showed a marked annual cycle and relatively constant position associated to the bottom slope; it tended to be located where the core of the Malvinas current is closest to the shelf. Tidal fronts also showed a strong annual cycle, being detected in three well-defined regions during spring and summer. Along the coasts of Tierra del Fuego and Santa Cruz, the combination of strong tidal mixing and low-salinity coastal plumes led to semi-annual seasonal cycles of frontal intensity and persistence that showed a relative maximum in winter. A similar behavior (semi-annual) was found at the coast off the Buenos Aires Province. There, the coastal dilution and the bathymetric gradient generated near-coastal fronts that changed direction seasonally. In the northern mid-shelf, a front linked to the intrusion of warm waters formed in the San Matías Gulf was identified during the winter.

Vortex nozzle for segmenting and transporting metal chips from turning operations

DOEpatents

Bieg, L.F.

1993-04-20

Apparatus for collecting, segmenting and conveying metal chips from machining operations utilizes a compressed gas driven vortex nozzle for receiving the chip and twisting it to cause the chip to segment through the application of torsional forces to the chip. The vortex nozzle is open ended and generally tubular in shape with a converging inlet end, a constant diameter throat section and a diverging exhaust end. Compressed gas is discharged through angled vortex ports in the nozzle throat section to create vortex flow in the nozzle and through an annular inlet at the entrance to the converging inlet end to create suction at the nozzle inlet and cause ambient air to enter the nozzle. The vortex flow in the nozzle causes the metal chip to segment and the segments thus formed to pass out of the discharge end of the nozzle where they are collected, cleaned and compacted as needed.

Conception and characterization of a virtual coplanar grid for a 11×11 pixelated CZT detector

NASA Astrophysics Data System (ADS)

Espagnet, Romain; Frezza, Andrea; Martin, Jean-Pierre; Hamel, Louis-André; Després, Philippe

2017-07-01

Due to the low mobility of holes in CZT, commercially available detectors with a relatively large volume typically use a pixelated anode structure. They are mostly used in imaging applications and often require a dense electronic readout scheme. These large volume detectors are also interesting for high-sensitivity applications and a CZT-based blood gamma counter was developed from a 20×20×15 mm3 crystal available commercially and having a 11×11 pixelated readout scheme. A method is proposed here to reduce the number of channels required to use the crystal in a high-sensitivity counting application, dedicated to pharmacokinetic modelling in PET and SPECT. Inspired by a classic coplanar anode, an implementation of a virtual coplanar grid was done by connecting the 121 pixels of the detector to form intercalated bands. The layout, the front-end electronics and the characterization of the detector in this 2-channel anode geometry is presented. The coefficients required to compensate for electron trapping in CZT were determined experimentally to improve the performance. The resulting virtual coplanar detector has an intrinsic efficiency of 34% and an energy resolution of 8% at 662 keV. The detector's response was linear between 80 keV and 1372 keV. This suggests that large CZT crystals offer an excellent alternative to scintillation detectors for some applications, especially those where high-sensitivity and compactness are required.

Smart-Pixel Array Processors Based on Optimal Cellular Neural Networks for Space Sensor Applications

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi; Sheu, Bing J.; Venus, Holger; Sandau, Rainer

1997-01-01

A smart-pixel cellular neural network (CNN) with hardware annealing capability, digitally programmable synaptic weights, and multisensor parallel interface has been under development for advanced space sensor applications. The smart-pixel CNN architecture is a programmable multi-dimensional array of optoelectronic neurons which are locally connected with their local neurons and associated active-pixel sensors. Integration of the neuroprocessor in each processor node of a scalable multiprocessor system offers orders-of-magnitude computing performance enhancements for on-board real-time intelligent multisensor processing and control tasks of advanced small satellites. The smart-pixel CNN operation theory, architecture, design and implementation, and system applications are investigated in detail. The VLSI (Very Large Scale Integration) implementation feasibility was illustrated by a prototype smart-pixel 5x5 neuroprocessor array chip of active dimensions 1380 micron x 746 micron in a 2-micron CMOS technology.

Image sensor pixel with on-chip high extinction ratio polarizer based on 65-nm standard CMOS technology.

PubMed

Sasagawa, Kiyotaka; Shishido, Sanshiro; Ando, Keisuke; Matsuoka, Hitoshi; Noda, Toshihiko; Tokuda, Takashi; Kakiuchi, Kiyomi; Ohta, Jun

2013-05-06

In this study, we demonstrate a polarization sensitive pixel for a complementary metal-oxide-semiconductor (CMOS) image sensor based on 65-nm standard CMOS technology. Using such a deep-submicron CMOS technology, it is possible to design fine metal patterns smaller than the wavelengths of visible light by using a metal wire layer. We designed and fabricated a metal wire grid polarizer on a 20 × 20 μm(2) pixel for image sensor. An extinction ratio of 19.7 dB was observed at a wavelength 750 nm.

A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

NASA Technical Reports Server (NTRS)

Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

1993-01-01

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

Characterisation of Vanilla—A novel active pixel sensor for radiation detection

NASA Astrophysics Data System (ADS)

Blue, A.; Bates, R.; Laing, A.; Maneuski, D.; O'Shea, V.; Clark, A.; Prydderch, M.; Turchetta, R.; Arvanitis, C.; Bohndiek, S.

2007-10-01

Novel features of a new monolithic active pixel sensor, Vanilla, with 520×520 pixels ( 25 μm square) has been characterised for the first time. Optimisation of the sensor operation was made through variation of frame rates, integration times and on-chip biases and voltages. Features such as flushed reset operation, ROI capturing and readout modes have been fully tested. Stability measurements were performed to test its suitablility for long-term applications. These results suggest the Vanilla sensor—along with bio-medical and space applications—is suitable for use in particle physics experiments.

High-speed on-chip windowed centroiding using photodiode-based CMOS imager

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Cunningham, Thomas J. (Inventor); Hancock, Bruce (Inventor)

2003-01-01

A centroid computation system is disclosed. The system has an imager array, a switching network, computation elements, and a divider circuit. The imager array has columns and rows of pixels. The switching network is adapted to receive pixel signals from the image array. The plurality of computation elements operates to compute inner products for at least x and y centroids. The plurality of computation elements has only passive elements to provide inner products of pixel signals the switching network. The divider circuit is adapted to receive the inner products and compute the x and y centroids.

High-speed on-chip windowed centroiding using photodiode-based CMOS imager

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Cunningham, Thomas J. (Inventor); Hancock, Bruce (Inventor)

2004-01-01

A centroid computation system is disclosed. The system has an imager array, a switching network, computation elements, and a divider circuit. The imager array has columns and rows of pixels. The switching network is adapted to receive pixel signals from the image array. The plurality of computation elements operates to compute inner products for at least x and y centroids. The plurality of computation elements has only passive elements to provide inner products of pixel signals the switching network. The divider circuit is adapted to receive the inner products and compute the x and y centroids.

A 176×144 148dB adaptive tone-mapping imager

NASA Astrophysics Data System (ADS)

Vargas-Sierra, S.; Liñán-Cembrano, G.; Rodríguez-Vázquez, A.

2012-03-01

This paper presents a 176x144 (QCIF) HDR image sensor where visual information is simultaneously captured and adaptively compressed by means of an in-pixel tone mapping scheme. The tone mapping curve (TMC) is calculated from the histogram of a Time Stamp image captured in the previous frame, which serves as a probability indicator of the distribution of illuminations within the present frame. The chip produces 7-bit/pixel images that can map illuminations from 311μlux to 55.3 klux in a single frame in a way that each pixel decides when to stop observing photocurrent integration -with extreme values captured at 8s and 2.34μs respectively. Pixels size is 33x33μm2, which includes a 3x3μm2 Nwell- Psubstrate photodiode and an autozeroing technique for establishing the reset voltage, which cancels most of the offset contributions created by the analog processing circuitry. Dark signal (10.8 mV/s ) effects in the final image are attenuated by an automatic programming of the DAC top voltage. Measured characteristics are Sensitivity 5.79 V/lux.s , FWC 12.2ke-, Conversion Factor 129(e-/DN), and Read Noise 25e-. The chip has been designed in the 0.35μm OPTO technology from Austriamicrosystems (AMS). Due to the focal plane operation, this architecture is especially well suited to be implemented in a 3D (vertical stacking) technology using per-pixel TSVs.

Parallel integrated frame synchronizer chip

NASA Technical Reports Server (NTRS)

Solomon, Jeffrey Michael (Inventor); Ghuman, Parminder Singh (Inventor); Bennett, Toby Dennis (Inventor)

2000-01-01

A parallel integrated frame synchronizer which implements a sequential pipeline process wherein serial data in the form of telemetry data or weather satellite data enters the synchronizer by means of a front-end subsystem and passes to a parallel correlator subsystem or a weather satellite data processing subsystem. When in a CCSDS mode, data from the parallel correlator subsystem passes through a window subsystem, then to a data alignment subsystem and then to a bit transition density (BTD)/cyclical redundancy check (CRC) decoding subsystem. Data from the BTD/CRC decoding subsystem or data from the weather satellite data processing subsystem is then fed to an output subsystem where it is output from a data output port.

An accuracy aware low power wireless EEG unit with information content based adaptive data compression.

PubMed

Tolbert, Jeremy R; Kabali, Pratik; Brar, Simeranjit; Mukhopadhyay, Saibal

2009-01-01

We present a digital system for adaptive data compression for low power wireless transmission of Electroencephalography (EEG) data. The proposed system acts as a base-band processor between the EEG analog-to-digital front-end and RF transceiver. It performs a real-time accuracy energy trade-off for multi-channel EEG signal transmission by controlling the volume of transmitted data. We propose a multi-core digital signal processor for on-chip processing of EEG signals, to detect signal information of each channel and perform real-time adaptive compression. Our analysis shows that the proposed approach can provide significant savings in transmitter power with minimal impact on the overall signal accuracy.

SYRMEP front-end and read-out electronics

NASA Astrophysics Data System (ADS)

Arfelli, F.; Bonvicini, V.; Bravin, A.; Cantatore, G.; Castelli, E.; Cristaudo, P.; Di Michiel, M.; Longo, R.; Olivo, A.; Pani, S.; Pontoni, D.; Poropat, P.; Prest, M.; Rashevsky, A.; Tomasini, F.; Tromba, G.; Vacchi, A.; Vallazza, E.

1998-02-01

The SYRMEP approach to digital mammography implies the use of a monochromatic X-ray beam from a synchrotron source and a slot of superimposed silicon microstrip detectors as a scanning image receptor. The microstrips are read by 32-channel chips mounted on 7-layer hybrid circuits which receive control signals and operating voltages from a MASTER-SLAVE configuration of cards. The MASTER card is driven by the CIRM, a dedicated CAMAC module whose timing function can be easily excluded to obtain data-storage-only units connected to different MASTERs: this second-level modular expansion capability fully achieves the tasks of an electronics system able to follow the SYRMEP detector growth till the final size of seven thousands of channels.

A 2 Thz Schottky Solid-State Heterodyne Receiver for Atmospheric Studies

NASA Technical Reports Server (NTRS)

Treuttel, Jeanne; Schlecht, Erich; Siles, Jose; Lee, Choonsup; Lin, Robert; Thomas, Bertrand; Gonzalez-Olvero, David; Yee, Jeng-Hwa; Wu, Dong; Mehdi, Imran

2016-01-01

Obtaining temperature, pressure, and composition profiles along with wind velocities in the Earth's thermosphere/ionosphere system is a key NASA goal for understanding our planet. We report on the status of a technology development effort to build an all-solid-state heterodyne receiver at 2.06 terahertz that will allow the measurement of the 2.06 terahertz [OI] line for altitudes greater than 100 kilometers. The receiver front end features low-parasitic Schottky diode mixer chips that are driven by a local oscillator (LO) source using Schottky diode based multipliers. The multiplier chain consists of a 38 gigahertz oscillator followed by a set of three cascaded triplers at 114 gigahertz, 343 gigahertz and 1.03 terahertz.

GET: A generic electronics system for TPCs and nuclear physics instrumentation

NASA Astrophysics Data System (ADS)

Pollacco, E. C.; Grinyer, G. F.; Abu-Nimeh, F.; Ahn, T.; Anvar, S.; Arokiaraj, A.; Ayyad, Y.; Baba, H.; Babo, M.; Baron, P.; Bazin, D.; Beceiro-Novo, S.; Belkhiria, C.; Blaizot, M.; Blank, B.; Bradt, J.; Cardella, G.; Carpenter, L.; Ceruti, S.; De Filippo, E.; Delagnes, E.; De Luca, S.; De Witte, H.; Druillole, F.; Duclos, B.; Favela, F.; Fritsch, A.; Giovinazzo, J.; Gueye, C.; Isobe, T.; Hellmuth, P.; Huss, C.; Lachacinski, B.; Laffoley, A. T.; Lebertre, G.; Legeard, L.; Lynch, W. G.; Marchi, T.; Martina, L.; Maugeais, C.; Mittig, W.; Nalpas, L.; Pagano, E. V.; Pancin, J.; Poleshchuk, O.; Pedroza, J. L.; Pibernat, J.; Primault, S.; Raabe, R.; Raine, B.; Rebii, A.; Renaud, M.; Roger, T.; Roussel-Chomaz, P.; Russotto, P.; Saccà, G.; Saillant, F.; Sizun, P.; Suzuki, D.; Swartz, J. A.; Tizon, A.; Usher, N.; Wittwer, G.; Yang, J. C.

2018-04-01

General Electronics for TPCs (GET) is a generic, reconfigurable and comprehensive electronics and data-acquisition system for nuclear physics instrumentation of up to 33792 channels. The system consists of a custom-designed ASIC for signal processing, front-end cards that each house 4 ASIC chips and digitize the data in parallel through 12-bit ADCs, concentration boards to read and process the digital data from up to 16 ASICs, a 3-level trigger and master clock module to trigger the system and synchronize the data, as well as all of the associated firmware, communication and data-acquisition software. An overview of the system including its specifications and measured performances are presented.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ianakiev, Kiril Dimitrov; Iliev, Metodi; Swinhoe, Martyn Thomas

The KM200 device is a versatile, configurable front-end electronics boards that can be used as a functional replacement for Canberra’s JAB-01 boards based on the Amptek A-111 hybrid chip, which continues to be the preferred choice of electronics for large number of the boards in junction boxes of multiplicity counters that process the signal from an array of 3He detectors. Unlike the A-111 chip’s fixed time constants and sensitivity range, the shaping time and sensitivity of the new KM200 can be optimized for demanding applications such as spent fuel, and thus could improve the safeguards measurements of existing systems wheremore » the A-111 or PDT electronics does not perform well.« less

Monitoring the CMS strip tracker readout system

NASA Astrophysics Data System (ADS)

Mersi, S.; Bainbridge, R.; Baulieu, G.; Bel, S.; Cole, J.; Cripps, N.; Delaere, C.; Drouhin, F.; Fulcher, J.; Giassi, A.; Gross, L.; Hahn, K.; Mirabito, L.; Nikolic, M.; Tkaczyk, S.; Wingham, M.

2008-07-01

The CMS Silicon Strip Tracker at the LHC comprises a sensitive area of approximately 200 m2 and 10 million readout channels. Its data acquisition system is based around a custom analogue front-end chip. Both the control and the readout of the front-end electronics are performed by off-detector VME boards in the counting room, which digitise the raw event data and perform zero-suppression and formatting. The data acquisition system uses the CMS online software framework to configure, control and monitor the hardware components and steer the data acquisition. The first data analysis is performed online within the official CMS reconstruction framework, which provides many services, such as distributed analysis, access to geometry and conditions data, and a Data Quality Monitoring tool based on the online physics reconstruction. The data acquisition monitoring of the Strip Tracker uses both the data acquisition and the reconstruction software frameworks in order to provide real-time feedback to shifters on the operational state of the detector, archiving for later analysis and possibly trigger automatic recovery actions in case of errors. Here we review the proposed architecture of the monitoring system and we describe its software components, which are already in place, the various monitoring streams available, and our experiences of operating and monitoring a large-scale system.

Fully Integrated Passive UHF RFID Tag for Hash-Based Mutual Authentication Protocol.

PubMed

Mikami, Shugo; Watanabe, Dai; Li, Yang; Sakiyama, Kazuo

2015-01-01

Passive radio-frequency identification (RFID) tag has been used in many applications. While the RFID market is expected to grow, concerns about security and privacy of the RFID tag should be overcome for the future use. To overcome these issues, privacy-preserving authentication protocols based on cryptographic algorithms have been designed. However, to the best of our knowledge, evaluation of the whole tag, which includes an antenna, an analog front end, and a digital processing block, that runs authentication protocols has not been studied. In this paper, we present an implementation and evaluation of a fully integrated passive UHF RFID tag that runs a privacy-preserving mutual authentication protocol based on a hash function. We design a single chip including the analog front end and the digital processing block. We select a lightweight hash function supporting 80-bit security strength and a standard hash function supporting 128-bit security strength. We show that when the lightweight hash function is used, the tag completes the protocol with a reader-tag distance of 10 cm. Similarly, when the standard hash function is used, the tag completes the protocol with the distance of 8.5 cm. We discuss the impact of the peak power consumption of the tag on the distance of the tag due to the hash function.

Front end design of smartphone-based mobile health

NASA Astrophysics Data System (ADS)

Zhang, Changfan; He, Lingsong; Gao, Zhiqiang; Ling, Cong; Du, Jianhao

2015-02-01

Mobile health has been a new trend all over the world with the rapid development of intelligent terminals and mobile internet. It can help patients monitor health in-house and is convenient for doctors to diagnose remotely. Smart-phone-based mobile health has big advantages in cost and data sharing. Front end design of it mainly focuses on two points: one is implementation of medical sensors aimed at measuring kinds of medical signal; another is acquisition of medical signal from sensors to smart phone. In this paper, the above two aspects were both discussed. First, medical sensor implementation was proposed to refer to mature measurement solutions with ECG (electrocardiograph) sensor design taken for example. And integrated chip using can simplify design. Then second, typical data acquisition architecture of smart phones, namely Bluetooth and MIC (microphone)-based architecture, were compared. Bluetooth architecture should be equipped with an acquisition card; MIC design uses sound card of smart phone instead. Smartphone-based virtual instrument app design corresponding to above acquisition architecture was discussed. In experiments, Bluetooth and MIC architecture were used to acquire blood pressure and ECG data respectively. The results showed that Bluetooth design can guarantee high accuracy during the acquisition and transmission process, and MIC design is competitive because of low cost and convenience.

Mathematical Simulation for Integrated Linear Fresnel Spectrometer Chip

NASA Technical Reports Server (NTRS)

Park, Yeonjoon; Yoon, Hargoon; Lee, Uhn; King, Glen C.; Choi, Sang H.

2012-01-01

A miniaturized solid-state optical spectrometer chip was designed with a linear gradient-gap Fresnel grating which was mounted perpendicularly to a sensor array surface and simulated for its performance and functionality. Unlike common spectrometers which are based on Fraunhoffer diffraction with a regular periodic line grating, the new linear gradient grating Fresnel spectrometer chip can be miniaturized to a much smaller form-factor into the Fresnel regime exceeding the limit of conventional spectrometers. This mathematical calculation shows that building a tiny motionless multi-pixel microspectrometer chip which is smaller than 1 cubic millimter of optical path volume is possible. The new Fresnel spectrometer chip is proportional to the energy scale (hc/lambda), while the conventional spectrometers are proportional to the wavelength scale (lambda). We report the theoretical optical working principle and new data collection algorithm of the new Fresnel spectrometer to build a compact integrated optical chip.

VizieR Online Data Catalog: Equivalent widths and atomic data for GCs (Lamb+, 2015)

NASA Astrophysics Data System (ADS)

Lamb, M. P.; Venn, K. A.; Shetrone, M. D.; Sakari, C. M.; Pritzl, B. J.

2017-11-01

Optical spectra were gathered with the High Resolution Spectrograph (HRS; Tull 1998, Proc. SPIE, 3355, 387) on the HET. The HRS was configured at resolution R=30000 with 2x2 pixel binning using the 2 arcsec fibre. The HRS splits the incoming beam on to two CCD chips, from which the spectral regions 6000-7000 Å (red chip) and 4800-5900 Å (blue chip) were extracted for this work. Two standard stars were also observed, RGB stars with previously published spectral analyses in each of the GCs M3 and M13. (2 data files).

MT3825BA: a 384×288-25µm ROIC for uncooled microbolometer FPAs

NASA Astrophysics Data System (ADS)

Eminoglu, Selim; Gulden, M. Ali; Bayhan, Nusret; Incedere, O. Samet; Soyer, S. Tuncer; Ustundag, Cem M. B.; Isikhan, Murat; Kocak, Serhat; Turan, Ozge; Yalcin, Cem; Akin, Tayfun

2014-06-01

This paper reports the development of a new microbolometer Readout Integrated Circuit (ROIC) called MT3825BA. It has a format of 384 × 288 and a pixel pitch of 25μm. MT3825BA is Mikro-Tasarim's second microbolometer ROIC product, which is developed specifically for resistive surface micro-machined microbolometer detector arrays using high-TCR pixel materials, such as VOx and a-Si. MT3825BA has a system-on-chip architecture, where all the timing, biasing, and pixel non-uniformity correction (NUC) operations in the ROIC are applied using on-chip circuitry simplifying the use and system integration of this ROIC. The ROIC is designed to support pixel resistance values ranging from 30 KΩ to 100 KΩ. MT3825BA is operated using conventional row based readout method, where pixels in the array are read out in a row-by-row basis, where the applied bias for each pixel in a given row is updated at the beginning of each line period according to the applied line based NUC data. The NUC data is applied continuously in a row-by-row basis using the serial programming interface, which is also used to program user configurable features of the ROIC, such as readout gain, integration time, and number of analog video outputs. MT3825BA has a total of 4 analog video outputs and 2 analog reference outputs, placed at the top and bottom of the ROIC, which can be programmed to operate in the 1, 2, and 4-output modes, supporting frames rates well above 60 fps at a 3 MHz pixel output rate. The pixels in the array are read out with respect to reference pixels implemented above and below actual array pixels. The bias voltage of the pixels can be programmed over a 1.0 V range to compensate for the changes in the detector resistance values due to the variations coming from the manufacturing process or changes in the operating temperature. The ROIC has an on-chip integrated temperature sensor with a sensitivity of better than 5 mV / K, and the output of the temperature sensor can be read out the output as part of the analog video stream. MT3825BA can be used to build a microbolometer FPAs with an NETD value below 100 mK using a microbolometer detector array fabrication technology with a detector resistance value up to 100 KΩ, a high TCR value (< 2 % / K), and a sufficiently low pixel thermal conductance (Gth ≤ 20 nW / K). MT3825BA measures 13.0 mm × 13.5 mm and is fabricated on 200 mm CMOS wafers. The microbolometer ROIC wafers are engineered to have flat surface finish to simplify the wafer level detector fabrication and wafer level vacuum packaging (WLVP). The ROIC runs on 3.3 V analog and 1.8 V digital supplies, and dissipates less than 85 mW in the 2-output mode at 30 fps. Mikro-Tasarim provides tested ROIC wafers and offers compact test electronics and software for its ROIC customers to shorten their FPA and camera development cycles.

Qualification and Reliability for MEMS and IC Packages

NASA Technical Reports Server (NTRS)

Ghaffarian, Reza

2004-01-01

Advanced IC electronic packages are moving toward miniaturization from two key different approaches, front and back-end processes, each with their own challenges. Successful use of more of the back-end process front-end, e.g. microelectromechanical systems (MEMS) Wafer Level Package (WLP), enable reducing size and cost. Use of direct flip chip die is the most efficient approach if and when the issues of know good die and board/assembly are resolved. Wafer level package solve the issue of known good die by enabling package test, but it has its own limitation, e.g., the I/O limitation, additional cost, and reliability. From the back-end approach, system-in-a-package (SIAP/SIP) development is a response to an increasing demand for package and die integration of different functions into one unit to reduce size and cost and improve functionality. MEMS add another challenging dimension to electronic packaging since they include moving mechanical elements. Conventional qualification and reliability need to be modified and expanded in most cases in order to detect new unknown failures. This paper will review four standards that already released or being developed that specifically address the issues on qualification and reliability of assembled packages. Exposures to thermal cycles, monotonic bend test, mechanical shock and drop are covered in these specifications. Finally, mechanical and thermal cycle qualification data generated for MEMS accelerometer will be presented. The MEMS was an element of an inertial measurement unit (IMU) qualified for NASA Mars Exploration Rovers (MERs), Spirit and Opportunity that successfully is currently roaring the Martian surface

A CMOS image sensor with programmable pixel-level analog processing.

PubMed

Massari, Nicola; Gottardi, Massimo; Gonzo, Lorenzo; Stoppa, David; Simoni, Andrea

2005-11-01

A prototype of a 34 x 34 pixel image sensor, implementing real-time analog image processing, is presented. Edge detection, motion detection, image amplification, and dynamic-range boosting are executed at pixel level by means of a highly interconnected pixel architecture based on the absolute value of the difference among neighbor pixels. The analog operations are performed over a kernel of 3 x 3 pixels. The square pixel, consisting of 30 transistors, has a pitch of 35 microm with a fill-factor of 20%. The chip was fabricated in a 0.35 microm CMOS technology, and its power consumption is 6 mW with 3.3 V power supply. The device was fully characterized and achieves a dynamic range of 50 dB with a light power density of 150 nW/mm2 and a frame rate of 30 frame/s. The measured fixed pattern noise corresponds to 1.1% of the saturation level. The sensor's dynamic range can be extended up to 96 dB using the double-sampling technique.

A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

NASA Technical Reports Server (NTRS)

Suarez, George; DuMonthier, Jeffrey J.; Sheikh, Salman S.; Powell, Wesley A.; King, Robyn L.

2012-01-01

Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

Optical sectioning in wide-field microscopy obtained by dynamic structured light illumination and detection based on a smart pixel detector array.

PubMed

Mitić, Jelena; Anhut, Tiemo; Meier, Matthias; Ducros, Mathieu; Serov, Alexander; Lasser, Theo

2003-05-01

Optical sectioning in wide-field microscopy is achieved by illumination of the object with a continuously moving single-spatial-frequency pattern and detecting the image with a smart pixel detector array. This detector performs an on-chip electronic signal processing that extracts the optically sectioned image. The optically sectioned image is directly observed in real time without any additional postprocessing.

Thermal analysis of the WFI on the ATHENA observatory

NASA Astrophysics Data System (ADS)

Fürmetz, Maria; Pietschner, Daniel; Meidinger, Norbert

2016-07-01

The WFI (Wide-Field Imager) instrument is one of two instruments of the ATHENA (Advanced Telescope for High- ENergy Astrophysics) mission. ATHENA is the second L-class mission in ESA's Cosmic Vision plan with launch in 2028 and will address the science theme "The Hot and Energetic Universe" by measuring hot gas in clusters and groups of galaxies as well as matter flow in black holes. A moveable mirror assembly focusses the X-ray light to the focal plane of the WFI. The instrument consists of two separate detectors, one with a large DEPFET array of 512x512 pixels and one small and fast detector with 64x64 DEPFET pixels and a readout time of only 80 μs. The mirror system will achieve an angular resolution of 5" HEW. The rather large field of view of 40'x40' in combination with rather high power consumption is challenging not only for the thermal control system. DEPFET sensors as well as front-end electronics and electronics boxes have to be cooled, where a completely passive cooling system with radiators and heat pipes is highly favored. In order to reduce the necessary radiator area, three separate cooling chains with three different temperature levels have been foreseen. So only the DEPFET sensors are cooled down to the lowest temperature of about 190K, while the front-end electronics is supposed to be operated between 250K and 290K. The electronics boxes can be operated at room temperature, nevertheless the excess heat has to be removed. After first estimations of heat loads and radiator areas, a more detailed model of the camera head has been used to identify gradients between the cooling interfaces and the components to be cooled. This information is used within phase A1 of the project to further optimize the design of the instrument, e.g. material selection.

Computational Challenges in Processing the Q1-Q16 Kepler Data Set

NASA Astrophysics Data System (ADS)

Klaus, Todd C.; Henze, C.; Twicken, J. D.; Hall, J.; McCauliff, S. D.; Girouard, F.; Cote, M.; Morris, R. L.; Clarke, B.; Jenkins, J. M.; Caldwell, D.; Kepler Science Operations Center

2013-10-01

Since launch on March 6th, 2009, NASA’s Kepler Space Telescope has collected 48 months of data on over 195,000 targets. The raw data are rife with instrumental and astrophysical noise that must be removed in order to detect and model the transit-like signals present in the data. Calibrating the raw pixels, generating and correcting the flux light curves, and detecting and characterizing the signals require significant computational power. In addition, the algorithms that make up the Kepler Science Pipeline and their parameters are still undergoing changes (most of which increase the computational cost), creating the need to reprocess the entire data set on a regular basis. We discuss how we have ported all of the core elements of the pipeline to the Pleiades cluster at the NASA Advanced Supercomputing (NAS) Division, the needs driving the port, and the technical challenges we faced. In 2011 we ported the Transiting Planet Search (TPS) and Data Validation (DV) modules to Pleiades. These pipeline modules operate on the full data set and the computational complexity increases roughly by the square of the number of data points. At the time of the port it had become infeasible to run these modules on our local hardware, necessitating the move to Pleiades. In 2012 and 2013 we turned our attention to the front end of the pipeline; Pixel-level Calibration (CAL), Photometric Analysis (PA), and Pre-Search Data Conditioning (PDC). Porting these modules to Pleiades will allow us to reprocess the complete data set on a more frequent basis. The last time we reprocessed all data for the front end we only had 24 months of data. We estimate that the full 48-month data set would take over 200 days to complete on local hardware. When the port is complete we expect to reprocess this data set on Pleiades in about a month. The NASA Science Mission Directorate provided funding for the Kepler Mission.

Design and fabrication of AlGaInP-based micro-light-emitting-diode array devices

NASA Astrophysics Data System (ADS)

Bao, Xingzhen; Liang, Jingqiu; Liang, Zhongzhu; Wang, Weibiao; Tian, Chao; Qin, Yuxin; Lü, Jinguang

2016-04-01

An integrated high-resolution (individual pixel size 80 μm×80 μm) solid-state self-emissive active matrix programmed with 320×240 micro-light-emitting-diode arrays structure was designed and fabricated on an AlGaInP semiconductor chip using micro electro-mechanical systems, microstructure and semiconductor fabricating techniques. Row pixels share a p-electrode and line pixels share an n-electrode. We experimentally investigated GaAs substrate thickness affects the electrical and optical characteristics of the pixels. For a 150-μm-thick GaAs substrate, the single pixel output power was 167.4 μW at 5 mA, and increased to 326.4 μW when current increase to 10 mA. The device investigated potentially plays an important role in many fields.

A novel digital image sensor with row wise gain compensation for Hyper Spectral Imager (HySI) application

NASA Astrophysics Data System (ADS)

Lin, Shengmin; Lin, Chi-Pin; Wang, Weng-Lyang; Hsiao, Feng-Ke; Sikora, Robert

2009-08-01

A 256x512 element digital image sensor has been developed which has a large pixel size, slow scan and low power consumption for Hyper Spectral Imager (HySI) applications. The device is a mixed mode, silicon on chip (SOC) IC. It combines analog circuitry, digital circuitry and optical sensor circuitry into a single chip. This chip integrates a 256x512 active pixel sensor array, a programming gain amplifier (PGA) for row wise gain setting, I2C interface, SRAM, 12 bit analog to digital convertor (ADC), voltage regulator, low voltage differential signal (LVDS) and timing generator. The device can be used for 256 pixels of spatial resolution and 512 bands of spectral resolution ranged from 400 nm to 950 nm in wavelength. In row wise gain readout mode, one can set a different gain on each row of the photo detector by storing the gain setting data on the SRAM thru the I2C interface. This unique row wise gain setting can be used to compensate the silicon spectral response non-uniformity problem. Due to this unique function, the device is suitable for hyper-spectral imager applications. The HySI camera located on-board the Chandrayaan-1 satellite, was successfully launched to the moon on Oct. 22, 2008. The device is currently mapping the moon and sending back excellent images of the moon surface. The device design and the moon image data will be presented in the paper.

Vortex Generators to Control Boundary Layer Interactions

NASA Technical Reports Server (NTRS)

Babinsky, Holger (Inventor); Loth, Eric (Inventor); Lee, Sang (Inventor)

2014-01-01

Devices for generating streamwise vorticity in a boundary includes various forms of vortex generators. One form of a split-ramp vortex generator includes a first ramp element and a second ramp element with front ends and back ends, ramp surfaces extending between the front ends and the back ends, and vertical surfaces extending between the front ends and the back ends adjacent the ramp surfaces. A flow channel is between the first ramp element and the second ramp element. The back ends of the ramp elements have a height greater than a height of the front ends, and the front ends of the ramp elements have a width greater than a width of the back ends.

A SPAD-based 3D imager with in-pixel TDC for 145ps-accuracy ToF measurement

NASA Astrophysics Data System (ADS)

Vornicu, I.; Carmona-Galán, R.; Rodríguez-Vázquez, Á.

2015-03-01

The design and measurements of a CMOS 64 × 64 Single-Photon Avalanche-Diode (SPAD) array with in-pixel Time-to-Digital Converter (TDC) are presented. This paper thoroughly describes the imager at architectural and circuit level with particular emphasis on the characterization of the SPAD-detector ensemble. It is aimed to 2D imaging and 3D image reconstruction in low light environments. It has been fabricated in a standard 0.18μm CMOS process, i. e. without high voltage or low noise features. In these circumstances, we are facing a high number of dark counts and low photon detection efficiency. Several techniques have been applied to ensure proper functionality, namely: i) time-gated SPAD front-end with fast active-quenching/recharge circuit featuring tunable dead-time, ii) reverse start-stop scheme, iii) programmable time resolution of the TDC based on a novel pseudo-differential voltage controlled ring oscillator with fast start-up, iv) a global calibration scheme against temperature and process variation. Measurements results of individual SPAD-TDC ensemble jitter, array uniformity and time resolution programmability are also provided.

Caliste 64, a new CdTe micro-camera for hard X-ray spectro-imaging

NASA Astrophysics Data System (ADS)

Meuris, A.; Limousin, O.; Lugiez, F.; Gevin, O.; Blondel, C.; Pinsard, F.; Vassal, M. C.; Soufflet, F.; Le Mer, I.

2009-10-01

In the frame of the Simbol-X mission of hard X-ray astrophysics, a prototype of micro-camera with 64 pixels called Caliste 64 has been designed and several samples have been tested. The device integrates ultra-low-noise IDeF-X V1.1 ASICs from CEA and a 1 cm 2 Al Schottky CdTe detector from Acrorad because of its high uniformity and spectroscopic performance. The process of hybridization, mastered by the 3D Plus company, respects space applications standards. The camera is a spectro-imager with time-tagging capability. Each photon interacting in the semiconductor is tagged with a time, a position and an energy. Time resolution is better than 100 ns rms for energy deposits greater than 20 keV, taking into account electronic noise and technological dispersal of the front-end electronics. The spectrum summed across the 64 pixels results in an energy resolution of 664 eV fwhm at 13.94 keV and 842 eV fwhm at 59.54 keV, when the detector is cooled down to -10 °C and biased at -500 V.

Direct-phase and amplitude digitalization based on free-space interferometry

NASA Astrophysics Data System (ADS)

Kleiner, Vladimir; Rudnitsky, Arkady; Zalevsky, Zeev

2017-12-01

A novel ADC configuration that can be characterized as a photonic-domain flash analog-to-digital convertor operating based upon free-space interferometry is proposed and analysed. The structure can be used as the front-end of a coherent receiver as well as for other applications. Two configurations are considered: the first, ‘direct free-space interference’, allows simultaneous measuring of the optical phase and amplitude; the second, ‘extraction of the ac component of interference by means of pixel-by-pixel balanced photodetection’, allows only phase digitization but with significantly higher sensitivity. For both proposed configurations, we present Monte Carlo estimations of the performance limitations, due to optical noise and photo-current noise, at sampling rates of 60 giga-samples per second. In terms of bit resolution, we simulated multiple cases with growing complexity of up to 4 bits for the amplitude and up to 6 bits for the phase. The simulations show that the digitization errors in the optical domain can be reduced to levels close to the quantization noise limits. Preliminary experimental results validate the fundamentals of the proposed idea.

Conceptual design of front ends for the advanced photon source multi-bend achromats upgrade

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jaski, Y., E-mail: jaskiy@aps.anl.gov; Westferro, F., E-mail: westferr@aps.anl.gov; Lee, S. H., E-mail: shlee@aps.anl.gov

2016-07-27

The proposed Advanced Photon Source (APS) upgrade from a double-bend achromats (DBA) to multi-bend achromats (MBA) lattice with ring energy change from 7 GeV to 6 GeV and beam current from 100 mA to 200 mA poses new challenges for front ends. All front ends must be upgraded to fulfill the following requirements: 1) handle the high heat load from two insertion devices in either inline or canted configuration, 2) include a clearing magnet in the front end to deflect and dump any electrons in case the electrons escape from the storage ring during swap-out injection with the safety shuttersmore » open, 3) incorporate the next generation x-ray beam position monitors (XBPMs) into the front end to meet the new stringent beam stability requirements. This paper presents the evaluation of the existing APS front ends and standardizes the insertion device (ID) front ends into two types: one for the single beam and one for the canted beams. The conceptual design of high heat load front end (HHLFE) and canted undulator front end (CUFE) for APS MBA upgrade is presented.« less

Conceptual Design of Front Ends for the Advanced Photon Source Multi-bend Achromats Upgrade

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jaski, Y.; Westferro, F.; Lee, S. H.

2016-07-27

The proposed Advanced Photon Source (APS) upgrade from a double-bend achromats (DBA) to multi-bend achromats (MBA) lattice with ring energy change from 7 GeV to 6 GeV and beam current from 100 mA to 200 mA poses new challenges for front ends. All front ends must be upgraded to fulfill the following requirements: 1) handle the high heat load from two insertion devices in either inline or canted configuration, 2) include a clearing magnet in the front end to deflect and dump any electrons in case the electrons escape from the storage ring during swap-out injection with the safety shuttersmore » open, 3) incorporate the next generation x-ray beam position monitors (XBPMs) into the front end to meet the new stringent beam stability requirements. This paper presents the evaluation of the existing APS front ends and standardizes the insertion device (ID) front ends into two types: one for the single beam and one for the canted beams. The conceptual design of high heat load front end (HHLFE) and canted undulator front end (CUFE) for APS MBA upgrade is presented.« less

Improved Space Object Orbit Determination Using CMOS Detectors

NASA Astrophysics Data System (ADS)

Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

2014-09-01

CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario a sensor in a sun-synchronous LEO orbit, always pointing in the anti-sun direction to achieve optimum illumination conditions for small LEO debris, was simulated. For the space-based scenario the simulations showed a 20 130 % improvement of the accuracy of all orbital parameters when varying the frame rate from 1/3 fps, which is the fastest rate for a typical CCD detector, to 50 fps, which represents the highest rate of scientific CMOS cameras. Changing the epoch registration accuracy from a typical 20.0 ms for a mechanical shutter to 0.025 ms, the theoretical value for the electronic shutter of a CMOS camera, improved the orbit accuracy by 4 to 190 %. The ground-based scenario also benefit from the specific CMOS characteristics, but to a lesser extent.

Deep-Sea Video Cameras Without Pressure Housings

NASA Technical Reports Server (NTRS)

Cunningham, Thomas

2004-01-01

Underwater video cameras of a proposed type (and, optionally, their light sources) would not be housed in pressure vessels. Conventional underwater cameras and their light sources are housed in pods that keep the contents dry and maintain interior pressures of about 1 atmosphere (.0.1 MPa). Pods strong enough to withstand the pressures at great ocean depths are bulky, heavy, and expensive. Elimination of the pods would make it possible to build camera/light-source units that would be significantly smaller, lighter, and less expensive. The depth ratings of the proposed camera/light source units would be essentially unlimited because the strengths of their housings would no longer be an issue. A camera according to the proposal would contain an active-pixel image sensor and readout circuits, all in the form of a single silicon-based complementary metal oxide/semiconductor (CMOS) integrated- circuit chip. As long as none of the circuitry and none of the electrical leads were exposed to seawater, which is electrically conductive, silicon integrated- circuit chips could withstand the hydrostatic pressure of even the deepest ocean. The pressure would change the semiconductor band gap by only a slight amount . not enough to degrade imaging performance significantly. Electrical contact with seawater would be prevented by potting the integrated-circuit chip in a transparent plastic case. The electrical leads for supplying power to the chip and extracting the video signal would also be potted, though not necessarily in the same transparent plastic. The hydrostatic pressure would tend to compress the plastic case and the chip equally on all sides; there would be no need for great strength because there would be no need to hold back high pressure on one side against low pressure on the other side. A light source suitable for use with the camera could consist of light-emitting diodes (LEDs). Like integrated- circuit chips, LEDs can withstand very large hydrostatic pressures. If power-supply regulators or filter capacitors were needed, these could be attached in chip form directly onto the back of, and potted with, the imager chip. Because CMOS imagers dissipate little power, the potting would not result in overheating. To minimize the cost of the camera, a fixed lens could be fabricated as part of the plastic case. For improved optical performance at greater cost, an adjustable glass achromatic lens would be mounted in a reservoir that would be filled with transparent oil and subject to the full hydrostatic pressure, and the reservoir would be mounted on the case to position the lens in front of the image sensor. The lens would by adjusted for focus by use of a motor inside the reservoir (oil-filled motors already exist).

A compressed sensing X-ray camera with a multilayer architecture

NASA Astrophysics Data System (ADS)

Wang, Zhehui; Iaroshenko, O.; Li, S.; Liu, T.; Parab, N.; Chen, W. W.; Chu, P.; Kenyon, G. T.; Lipton, R.; Sun, K.-X.

2018-01-01

Recent advances in compressed sensing theory and algorithms offer new possibilities for high-speed X-ray camera design. In many CMOS cameras, each pixel has an independent on-board circuit that includes an amplifier, noise rejection, signal shaper, an analog-to-digital converter (ADC), and optional in-pixel storage. When X-ray images are sparse, i.e., when one of the following cases is true: (a.) The number of pixels with true X-ray hits is much smaller than the total number of pixels; (b.) The X-ray information is redundant; or (c.) Some prior knowledge about the X-ray images exists, sparse sampling may be allowed. Here we first illustrate the feasibility of random on-board pixel sampling (ROPS) using an existing set of X-ray images, followed by a discussion about signal to noise as a function of pixel size. Next, we describe a possible circuit architecture to achieve random pixel access and in-pixel storage. The combination of a multilayer architecture, sparse on-chip sampling, and computational image techniques, is expected to facilitate the development and applications of high-speed X-ray camera technology.

75 FR 70703 - Humana Insurance Company a Division of Carenetwork, Inc. Front End Operations and Account...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-11-18

... Division of CareNetwork, Inc., Front End Operations and Account Installation-Product Testing Groups, De... a Division of Carenetwork, Inc. Front End Operations and Account Installation-Product Testing Groups..., a Division of CareNetwork, Inc., Front End Operations and Account Installation- Product Testing...

Large Format, Background Limited Arrays of Kinetic Inductance Detectors for Sub-mm Astronomy

NASA Astrophysics Data System (ADS)

Baselmans, Jochem

2018-01-01

We present the development of large format imaging arrays for sub-mm astronomy based upon microwave Kinetic Inductance detectors and their read-out. In particular we focus on the arrays developed for the A-MKID instrument for the APEX telescope. AMKID contains 2 focal plane arrays, covering a field of view of 15?x15?. One array is optimized for the 350 GHz telluric window, the other for the 850 GHz window. Both arrays are constructed from four 61 x 61 mm detector chips, each of which contains up to 3400 detectors and up to 880 detectors per readout line. The detectors are lens antenna coupled MKIDs made from NbTiN and Aluminium that reach photon noise limited sensitivity in combination with a high optical coupling. The lens-antenna radiation coupling enables the use of 4K optics and Lyot stop due to the intrinsic directivity of the detector beam, allowing a simple cryogenic architecture. We discuss the pixel design and verification, detector packaging and the array performance. We will also discuss the readout system, which is a combination of a digital and analog back-end that can read-out up to 4000 pixels simultaneously using frequency division multiplexing.

Systematic analysis of CMOS-micromachined inductors with application to mixer matching circuits

NASA Astrophysics Data System (ADS)

Wu, Jerry Chun-Li

The growing demand for consumer voice and data communication systems and military communication applications has created a need for low-power, low-cost, high-performance radio-frequency (RF) front-end. To achieve this goal, bringing passive components, especially inductors, to silicon is imperative. On-chip passive components such as inductors and capacitors generally enhance the reliability and efficiency of silicon-integrated RF cells. They can provide circuit solutions with superior performance and contribute to a higher level of integration. With passive components on chip, there is a great opportunity to have transformers, filters, and matching networks on chip. However, inductors on silicon have a low quality factor (Q) due to both substrate and metal loss. This dissertation demonstrates the systematic analysis of inductors fabricated using standard complementary metal-oxide-semiconductor (CMOS) and micro-electro-mechanical (MEMS) system technologies. We report system-on-chip inductor modeling, simulation, and measurements of effective inductance and quality factors. In this analysis methodology, a number of systematic simulations are performed on regular and micromachined inductors with different parameters such as spiral topology, number of turns, outer diameter, thickness, and percentage of substrate removed by using micromachining technologies. Three different novel support structures of the micromachined spiral inductor are proposed, analyzed, and implemented for larger size suspended inductors. The sensitivity of the structure support and different degree of substrate etching by post-processing is illustrated. The results provide guidelines for the selection of inductor parameters, post-processing methodologies, and its spiral supports to meet the RF design specifications and the stability requirements for mobile communication. The proposed CMOS-micromachined inductor is used in a low cost-effective double-balanced Gilbert mixer with on-chip matching network. The integrated mixer inductor was implemented and tested to prove the concept.

Development of a High Dynamic Range Pixel Array Detector for Synchrotrons and XFELs

NASA Astrophysics Data System (ADS)

Weiss, Joel Todd

Advances in synchrotron radiation light source technology have opened new lines of inquiry in material science, biology, and everything in between. However, x-ray detector capabilities must advance in concert with light source technology to fully realize experimental possibilities. X-ray free electron lasers (XFELs) place particularly large demands on the capabilities of detectors, and developments towards diffraction-limited storage ring sources also necessitate detectors capable of measuring very high flux [1-3]. The detector described herein builds on the Mixed Mode Pixel Array Detector (MM-PAD) framework, developed previously by our group to perform high dynamic range imaging, and the Adaptive Gain Integrating Pixel Detector (AGIPD) developed for the European XFEL by a collaboration between Deustsches Elektronen-Synchrotron (DESY), the Paul-Scherrer-Institute (PSI), the University of Hamburg, and the University of Bonn, led by Heinz Graafsma [4, 5]. The feasibility of combining adaptive gain with charge removal techniques to increase dynamic range in XFEL experiments is assessed by simulating XFEL scatter with a pulsed infrared laser. The strategy is incorporated into pixel prototypes which are evaluated with direct current injection to simulate very high incident x-ray flux. A fully functional 16x16 pixel hybrid integrating x-ray detector featuring several different pixel architectures based on the prototypes was developed. This dissertation describes its operation and characterization. To extend dynamic range, charge is removed from the integration node of the front-end amplifier without interrupting integration. The number of times this process occurs is recorded by a digital counter in the pixel. The parameter limiting full well is thereby shifted from the size of an integration capacitor to the depth of a digital counter. The result is similar to that achieved by counting pixel array detectors, but the integrators presented here are designed to tolerate a sustained flux >1011 x-rays/pixel/second. In addition, digitization of residual analog signals allows sensitivity for single x-rays or low flux signals. Pixel high flux linearity is evaluated by direct exposure to an unattenuated synchrotron source x-ray beam and flux measurements of more than 1010 9.52 keV x-rays/pixel/s are made. Detector sensitivity to small signals is evaluated and dominant sources of error are identified. These new pixels boast multiple orders of magnitude improvement in maximum sustained flux over the MM-PAD, which is capable of measuring a sustained flux in excess of 108 x-rays/pixel/second while maintaining sensitivity to smaller signals, down to single x-rays.

ALPIDE: the Monolithic Active Pixel Sensor for the ALICE ITS upgrade

NASA Astrophysics Data System (ADS)

Šuljić, M.

2016-11-01

The upgrade of the ALICE vertex detector, the Inner Tracking System (ITS), is scheduled to be installed during the next long shutdown period (2019-2020) of the CERN Large Hadron Collider (LHC) . The current ITS will be replaced by seven concentric layers of Monolithic Active Pixel Sensors (MAPS) with total active surface of ~10 m2, thus making ALICE the first LHC experiment implementing MAPS detector technology on a large scale. The ALPIDE chip, based on TowerJazz 180 nm CMOS Imaging Process, is being developed for this purpose. A particular process feature, the deep p-well, is exploited so the full CMOS logic can be implemented over the active sensor area without impinging on the deposited charge collection. ALPIDE is implemented on silicon wafers with a high resistivity epitaxial layer. A single chip measures 15 mm by 30 mm and contains half a million pixels distributed in 512 rows and 1024 columns. In-pixel circuitry features amplification, shaping, discrimination and multi-event buffering. The readout is hit driven i.e. only addresses of hit pixels are sent to the periphery. The upgrade of the ITS presents two different sets of requirements for sensors of the inner and of the outer layers due to the significantly different track density, radiation level and active detector surface. The ALPIDE chip fulfils the stringent requirements in both cases. The detection efficiency is higher than 99%, fake-hit probability is orders of magnitude lower than the required 10-6 and spatial resolution within the required 5 μm. This performance is to be maintained even after a total ionising does (TID) of 2.7 Mrad and a non-ionising energy loss (NIEL) fluence of 1.7 × 1013 1 MeV neq/cm2, which is above what is expected during the detector lifetime. Readout rate of 100 kHz is provided and the power density of ALPIDE is less than 40 mW/cm2. This contribution will provide a summary of the ALPIDE features and main test results.

Development of a driving method suitable for ultrahigh-speed shooting in a 2M-fps 300k-pixel single-chip color camera

NASA Astrophysics Data System (ADS)

Yonai, J.; Arai, T.; Hayashida, T.; Ohtake, H.; Namiki, J.; Yoshida, T.; Etoh, T. Goji

2012-03-01

We have developed an ultrahigh-speed CCD camera that can capture instantaneous phenomena not visible to the human eye and impossible to capture with a regular video camera. The ultrahigh-speed CCD was specially constructed so that the CCD memory between the photodiode and the vertical transfer path of each pixel can store 144 frames each. For every one-frame shot, the electric charges generated from the photodiodes are transferred in one step to the memory of all the parallel pixels, making ultrahigh-speed shooting possible. Earlier, we experimentally manufactured a 1M-fps ultrahigh-speed camera and tested it for broadcasting applications. Through those tests, we learned that there are cases that require shooting speeds (frame rate) of more than 1M fps; hence we aimed to develop a new ultrahigh-speed camera that will enable much faster shooting speeds than what is currently possible. Since shooting at speeds of more than 200,000 fps results in decreased image quality and abrupt heating of the image sensor and drive circuit board, faster speeds cannot be achieved merely by increasing the drive frequency. We therefore had to improve the image sensor wiring layout and the driving method to develop a new 2M-fps, 300k-pixel ultrahigh-speed single-chip color camera for broadcasting purposes.

Design of a Closed-Loop, Bidirectional Brain Machine Interface System With Energy Efficient Neural Feature Extraction and PID Control.

PubMed

Liu, Xilin; Zhang, Milin; Richardson, Andrew G; Lucas, Timothy H; Van der Spiegel, Jan

2017-08-01

This paper presents a bidirectional brain machine interface (BMI) microsystem designed for closed-loop neuroscience research, especially experiments in freely behaving animals. The system-on-chip (SoC) consists of 16-channel neural recording front-ends, neural feature extraction units, 16-channel programmable neural stimulator back-ends, in-channel programmable closed-loop controllers, global analog-digital converters (ADC), and peripheral circuits. The proposed neural feature extraction units includes 1) an ultra low-power neural energy extraction unit enabling a 64-step natural logarithmic domain frequency tuning, and 2) a current-mode action potential (AP) detection unit with time-amplitude window discriminator. A programmable proportional-integral-derivative (PID) controller has been integrated in each channel enabling a various of closed-loop operations. The implemented ADCs include a 10-bit voltage-mode successive approximation register (SAR) ADC for the digitization of the neural feature outputs and/or local field potential (LFP) outputs, and an 8-bit current-mode SAR ADC for the digitization of the action potential outputs. The multi-mode stimulator can be programmed to perform monopolar or bipolar, symmetrical or asymmetrical charge balanced stimulation with a maximum current of 4 mA in an arbitrary channel configuration. The chip has been fabricated in 0.18 μ m CMOS technology, occupying a silicon area of 3.7 mm 2 . The chip dissipates 56 μW/ch on average. General purpose low-power microcontroller with Bluetooth module are integrated in the system to provide wireless link and SoC configuration. Methods, circuit techniques and system topology proposed in this work can be used in a wide range of relevant neurophysiology research, especially closed-loop BMI experiments.

Advancing the Technology of Monolithic CMOS detectors for their use as X-ray Imaging Spectrometers

NASA Astrophysics Data System (ADS)

Kenter, Almus

The Smithsonian Astrophysical Observatory (SAO) proposes a two year program to further advance the scientific capabilities of monolithic CMOS detectors for use as x-ray imaging spectrometers. This proposal will build upon the progress achieved with funding from a previous APRA proposal that ended in 2013. As part of that previous proposal, x- ray optimized, highly versatile, monolithic CMOS imaging detectors and technology were developed and tested. The performance and capabilities of these devices were then demonstrated, with an emphasis on the performance advantages these devices have over CCDs and other technologies. The developed SAO/SRI-Sarnoff CMOS devices incorporate: Low noise, high sensitivity ("gain") pixels; Highly parallel on-chip signal chains; Standard and very high resistivity (30,000Ohm-cm) Si; Back-Side thinning and passivation. SAO demonstrated the performance benefits of each of these features in these devices. This new proposal high-lights the performance of this previous generation of devices, and segues into new technology and capability. The high sensitivity ( 135uV/e) 6 Transistor (6T) Pinned Photo Diode (PPD) pixels provided a large charge to voltage conversion gain to the detect and resolve even small numbers of photo electrons produced by x-rays. The on-chip, parallel signal chain processed an entire row of pixels in the same time that a CCD requires to processes a single pixel. The resulting high speed operation ( 1000 times faster than CCD) provide temporal resolution while mitigating dark current and allowed room temperature operation. The high resistivity Si provided full (over) depletion for thicker devices which increased QE for higher energy x-rays. In this proposal, SAO will investigate existing NMOS and existing PMOS devices as xray imaging spectrometers. Conventional CMOS imagers are NMOS. NMOS devices collect and measure photo-electrons. In contrast, PMOS devices collect and measure photo-holes. PMOS devices have various attributes that would make them superior for use in X-ray astronomy. In particular, PMOS has: "no" photo-charge recombination; "no" Random Telegraph Signal noise (RTS); and lower read noise. The existing SRI/Sarnoff PMOS devices are small and have been developed for non-intensified night vision applications, however, no x-ray evaluation of a monolithic PMOS device has ever been made. In addition to these PMOS devices, SAO will also evaluate existing NMOS scale-able format devices that can be fabricated in any rectangular size/shape using stitchable reticles. These "Mk by Nk" devices would be ideal for large X-ray focal planes or long grating readouts. The Sarnoff/SRI Mk by Nk format devices have been designed, with foresight, so that they can be fabricated in either PMOS or NMOS by changing a single fabrication reticle and by changing the type of Si substrate. If X-ray performance results are expected, this proposal will lead the way to future fabrication of Mk by Nk PMOS devices that would be ideal for X-ray astronomy missions such as "X-ray Surveyor". SAO will also investigate the interaction of directly deposited Optical Blocking Filters (OBFs) on various back side passivated devices, and their resultant effects on very "soft" x-ray response. The latest CMOS processes and very fast on-chip, and off-chip digital readout signal chains and camera systems will be demonstrated.

On-Wafer Measurement of a Multi-Stage MMIC Amplifier with 10 dB of Gain at 475 GHz

NASA Technical Reports Server (NTRS)

Samoska, Lorene A.; Fung, KingMan; Pukala, David M.; Kangaslahti, Pekka P.; Lai, Richard; Ferreira, Linda

2012-01-01

JPL has measured and calibrated a WR2.2 waveguide wafer probe from GGB Industries in order to allow for measurement of circuits in the 325-500 GHz range. Circuits were measured, and one of the circuits exhibited 10 dB of gain at 475 GHz. The MMIC circuit was fabricated at Northrop Grumman Corp. (NGC) as part of a NASA Innovative Partnerships Program, using NGC s 35-nm-gatelength InP HEMT process technology. The chip utilizes three stages of HEMT amplifiers, each having two gate fingers of 10 m in width. The circuits use grounded coplanar waveguide topology on a 50- m-thick substrate with through substrate vias. Broadband matching is achieved with coplanar waveguide transmission lines, on-chip capacitors, and open stubs. When tested with wafer probing, the chip exhibited 10 dB of gain at 475 GHz, with over 9 dB of gain from 445-490 GHz. Low-noise amplifiers in the 400-500 GHz range are useful for astrophysics receivers and earth science remote sensing instruments. In particular, molecular lines in the 400-500 GHz range include the CO 4-3 line at 460 GHz, and the CI fine structure line at 492 GHz. Future astrophysics heterodyne instruments could make use of high-gain, low-noise amplifiers such as the one described here. In addition, earth science remote sensing instruments could also make use of low-noise receivers with MMIC amplifier front ends. Present receiver technology typically employs mixers for frequency down-conversion in the 400-500 GHz band. Commercially available mixers have typical conversion loss in the range of 7-10 dB with noise figure of 1,000 K. A low-noise amplifier placed in front of such a mixer would have 10 dB of gain and lower noise figure, particularly if cooled to low temperature. Future work will involve measuring the noise figure of this amplifier.

A 0.18 μm biosensor front-end based on 1/f noise, distortion cancelation and chopper stabilization techniques.

PubMed

Balasubramanian, Viswanathan; Ruedi, Pierre-Francois; Temiz, Yuksel; Ferretti, Anna; Guiducci, Carlotta; Enz

2013-10-01

This paper presents a novel sensor front-end circuit that addresses the issues of 1/f noise and distortion in a unique way by using canceling techniques. The proposed front-end is a fully differential transimpedance amplifier (TIA) targeted for current mode electrochemical biosensing applications. In this paper, we discuss the architecture of this canceling based front-end and the optimization methods followed for achieving low noise, low distortion performance at minimum current consumption are presented. To validate the employed canceling based front-end, it has been realized in a 0.18 μm CMOS process and the characterization results are presented. The front-end has also been tested as part of a complete wireless sensing system and the cyclic voltammetry (CV) test results from electrochemical sensors are provided. Overall current consumption in the front-end is 50 μA while operating on a 1.8 V supply.

Ultra-Low-Noise W-Band MMIC Detector Modules

NASA Technical Reports Server (NTRS)

Gaier, Todd C.; Samoska, Lorene A.; Kangaslahti, Pekka P.; Van Vinkle, Dan; Tantawi, Sami; Fox, John; Church, Sarah E.; Lau, Jusy M.; Sieth, Matthew M.; Voll, Patricia E.;

40 CFR 63.487 - Batch front-end process vents-reference control technology.

Code of Federal Regulations, 2010 CFR

2010-07-01

... § 63.487 Batch front-end process vents—reference control technology. (a) Batch front-end process vents... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents-reference control technology. 63.487 Section 63.487 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY...

A 400 KHz line rate 2048 pixel modular SWIR linear array for earth observation applications

NASA Astrophysics Data System (ADS)

Anchlia, Ankur; Vinella, Rosa M.; Wouters, Kristof; Gielen, Daphne; Hooylaerts, Peter; Deroo, Pieter; Ruythooren, Wouter; van der Zanden, Koen; Vermeiren, Jan; Merken, Patrick

2015-10-01

In this paper, we report about a family of linear imaging FPAs sensitive in the [0.9 - 1.7um] band, developed for high speed applications such as LIDAR, wavelength references and OCT analyzers and also for earth observation applications. Fast linear FPAs can also be used in a wide variety of terrestrial applications, including high speed sorting, electro- and photo-luminesce and medical applications. The arrays are based on a modular ROIC design concept: modules of 512 pixels are stitched during fabrication to achieve 512, 1024 and 2048 pixel arrays. In principle, this concept can be extended to any multiple of 512 pixels, the limiting factor being the pixel yield of long InGaAs arrays and the CTE differences in the hybrid setup. Each 512-pixel module has its own on-chip digital sequencer, analog readout chain and 4 output buffers. This modular concept enables a long-linear array to run at a high line rate of 400 KHz irrespective of the array length, which limits the line rate in a traditional linear array. The pixel has a pitch of 12.5um. The detector frontend is based on CTIA (Capacitor Trans-impedance Amplifier), having 5 selectable integration capacitors giving full well from 62x103e- (gain0) to 40x106e- (gain4). An auto-zero circuit limits the detector bias non-uniformity to 5-10mV across broad intensity levels, limiting the input referred dark signal noise to 20e-rms for Tint=3ms at room temperature. An on-chip CDS that follows the CTIA facilitates removal of Reset/KTC noise, CTIA offsets and most of the 1/f noise. The measured noise of the ROIC is 35e-rms in gain0. At a master clock rate of 60MHz and a minimum integration time of 1.4us, the FPAs reach the highest line rate of 400 KHz.

Toward giga-pixel nanoscopy on a chip: a computational wide-field look at the nano-scale without the use of lenses

PubMed Central

McLeod, Euan; Luo, Wei; Mudanyali, Onur; Greenbaum, Alon

2013-01-01

The development of lensfree on-chip microscopy in the past decade has opened up various new possibilities for biomedical imaging across ultra-large fields of view using compact, portable, and cost-effective devices. However, until recently, its ability to resolve fine features and detect ultra-small particles has not rivalled the capabilities of the more expensive and bulky laboratory-grade optical microscopes. In this Frontier Review, we highlight the developments over the last two years that have enabled computational lensfree holographic on-chip microscopy to compete with and, in some cases, surpass conventional bright-field microscopy in its ability to image nano-scale objects across large fields of view, yielding giga-pixel phase and amplitude images. Lensfree microscopy has now achieved a numerical aperture as high as 0.92, with a spatial resolution as small as 225 nm across a large field of view e.g., >20 mm2. Furthermore, the combination of lensfree microscopy with self-assembled nanolenses, forming nano-catenoid minimal surfaces around individual nanoparticles has boosted the image contrast to levels high enough to permit bright-field imaging of individual particles smaller than 100 nm. These capabilities support a number of new applications, including, for example, the detection and sizing of individual virus particles using field-portable computational on-chip microscopes. PMID:23592185

Toward giga-pixel nanoscopy on a chip: a computational wide-field look at the nano-scale without the use of lenses.

PubMed

McLeod, Euan; Luo, Wei; Mudanyali, Onur; Greenbaum, Alon; Ozcan, Aydogan

2013-06-07

The development of lensfree on-chip microscopy in the past decade has opened up various new possibilities for biomedical imaging across ultra-large fields of view using compact, portable, and cost-effective devices. However, until recently, its ability to resolve fine features and detect ultra-small particles has not rivalled the capabilities of the more expensive and bulky laboratory-grade optical microscopes. In this Frontier Review, we highlight the developments over the last two years that have enabled computational lensfree holographic on-chip microscopy to compete with and, in some cases, surpass conventional bright-field microscopy in its ability to image nano-scale objects across large fields of view, yielding giga-pixel phase and amplitude images. Lensfree microscopy has now achieved a numerical aperture as high as 0.92, with a spatial resolution as small as 225 nm across a large field of view e.g., >20 mm(2). Furthermore, the combination of lensfree microscopy with self-assembled nanolenses, forming nano-catenoid minimal surfaces around individual nanoparticles has boosted the image contrast to levels high enough to permit bright-field imaging of individual particles smaller than 100 nm. These capabilities support a number of new applications, including, for example, the detection and sizing of individual virus particles using field-portable computational on-chip microscopes.

Multiple-Event, Single-Photon Counting Imaging Sensor

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Cunningham, Thomas J.; Sun, Chao; Wang, Kang L.

2011-01-01

The single-photon counting imaging sensor is typically an array of silicon Geiger-mode avalanche photodiodes that are monolithically integrated with CMOS (complementary metal oxide semiconductor) readout, signal processing, and addressing circuits located in each pixel and the peripheral area of the chip. The major problem is its single-event method for photon count number registration. A single-event single-photon counting imaging array only allows registration of up to one photon count in each of its pixels during a frame time, i.e., the interval between two successive pixel reset operations. Since the frame time can t be too short, this will lead to very low dynamic range and make the sensor merely useful for very low flux environments. The second problem of the prior technique is a limited fill factor resulting from consumption of chip area by the monolithically integrated CMOS readout in pixels. The resulting low photon collection efficiency will substantially ruin any benefit gained from the very sensitive single-photon counting detection. The single-photon counting imaging sensor developed in this work has a novel multiple-event architecture, which allows each of its pixels to register as more than one million (or more) photon-counting events during a frame time. Because of a consequently boosted dynamic range, the imaging array of the invention is capable of performing single-photon counting under ultra-low light through high-flux environments. On the other hand, since the multiple-event architecture is implemented in a hybrid structure, back-illumination and close-to-unity fill factor can be realized, and maximized quantum efficiency can also be achieved in the detector array.

High resolution 1280×1024, 15 μm pitch compact InSb IR detector with on-chip ADC

NASA Astrophysics Data System (ADS)

Nesher, O.; Pivnik, I.; Ilan, E.; Calalhorra, Z.; Koifman, A.; Vaserman, I.; Oiknine Schlesinger, J.; Gazit, R.; Hirsh, I.

2009-05-01

Over the last decade, SCD has developed and manufactured high quality InSb Focal Plane Arrays (FPAs), which are currently used in many applications worldwide. SCD's production line includes many different types of InSb FPA with formats of 320x256, 480x384 and 640x512 elements and with pitch sizes in the range of 15 to 30 μm. All these FPAs are available in various packaging configurations, including fully integrated Detector-Dewar-Cooler Assemblies (DDCA) with either closed-cycle Sterling or open-loop Joule-Thomson coolers. With an increasing need for higher resolution, SCD has recently developed a new large format 2-D InSb detector with 1280x1024 elements and a pixel size of 15μm. The InSb 15μm pixel technology has already been proven at SCD with the "Pelican" detector (640x512 elements), which was introduced at the Orlando conference in 2006. A new signal processor was developed at SCD for use in this mega-pixel detector. This Readout Integrated Circuit (ROIC) is designed for, and manufactured with, 0.18 μm CMOS technology. The migration from 0.5 to 0.18 μm CMOS technology supports SCD's roadmap for the reduction of pixel size and power consumption and is in line with the increasing demand for improved performance and on-chip functionality. Consequently, the new ROIC maintains the same level of performance and functionality with a 15 μm pitch, as exists in our 20 μm-pitch ROICs based on 0.5μm CMOS technology. Similar to Sebastian (SCD ROIC with A/D on chip), this signal processor also includes A/D converters on the chip and demonstrates the same level of performance, but with reduced power consumption. The pixel readout rate has been increased up to 160 MHz in order to support a high frame rate, resulting in 120 Hz operation with a window of 1024×1024 elements at ~130 mW. These A/D converters on chip save the need for using 16 A/D channels on board (in the case of an analog ROIC) which would operate at 10 MHz and consume about 8Watts A Dewar has been designed with a stiffened detector support to withstand harsh environmental conditions with a minimal contribution to the heat load of the detector. The combination of the 0.18μm-based low power CMOS technology for the ROIC and the stiffening of the detector support within the Dewar has enabled the use of the Ricor K508 cryo-cooler (0.5 W). This has created a high-resolution detector in a very compact package. In this paper we present the basic concept of the new detector. We will describe its construction and will present electrical and radiometric characterization results.

Associative Pattern Recognition In Analog VLSI Circuits

NASA Technical Reports Server (NTRS)

Tawel, Raoul

1995-01-01

Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

Argus: a 16-pixel millimeter-wave spectrometer for the Green Bank Telescope

NASA Astrophysics Data System (ADS)

Sieth, Matthew; Devaraj, Kiruthika; Voll, Patricia; Church, Sarah; Gawande, Rohit; Cleary, Kieran; Readhead, Anthony C. S.; Kangaslahti, Pekka; Samoska, Lorene; Gaier, Todd; Goldsmith, Paul F.; Harris, Andrew I.; Gundersen, Joshua O.; Frayer, David; White, Steve; Egan, Dennis; Reeves, Rodrigo

2014-07-01

We report on the development of Argus, a 16-pixel spectrometer, which will enable fast astronomical imaging over the 85-116 GHz band. Each pixel includes a compact heterodyne receiver module, which integrates two InP MMIC low-noise amplifiers, a coupled-line bandpass filter and a sub-harmonic Schottky diode mixer. The receiver signals are routed to and from the multi-chip MMIC modules with multilayer high frequency printed circuit boards, which includes LO splitters and IF amplifiers. Microstrip lines on flexible circuitry are used to transport signals between temperature stages. The spectrometer frontend is designed to be scalable, so that the array design can be reconfigured for future instruments with hundreds of pixels. Argus is scheduled to be commissioned at the Robert C. Byrd Green Bank Telescope in late 2014. Preliminary data for the first Argus pixels are presented.

Bio-Inspired Asynchronous Pixel Event Tricolor Vision Sensor.

PubMed

Lenero-Bardallo, Juan Antonio; Bryn, D H; Hafliger, Philipp

2014-06-01

This article investigates the potential of the first ever prototype of a vision sensor that combines tricolor stacked photo diodes with the bio-inspired asynchronous pixel event communication protocol known as Address Event Representation (AER). The stacked photo diodes are implemented in a 22 × 22 pixel array in a standard STM 90 nm CMOS process. Dynamic range is larger than 60 dB and pixels fill factor is 28%. The pixels employ either simple pulse frequency modulation (PFM) or a Time-to-First-Spike (TFS) mode. A heuristic linear combination of the chip's inherent pseudo colors serves to approximate RGB color representation. Furthermore, the sensor outputs can be processed to represent the radiation in the near infrared (NIR) band without employing external filters, and to color-encode direction of motion due to an asymmetry in the update rates of the different diode layers.

Deep Space Network, Cryogenic HEMT LNAs

NASA Technical Reports Server (NTRS)

Bautista, J. Javier

2006-01-01

Exploration of the Solar System with automated spacecraft that are more than ten astronomical units (1 AU = 149,597,870.691 km) from earth requires very large antennae employing extremely sensitive receivers. A key figure of merit in the specification of the spacecraft-to-earth telecommunications link is the ratio of the antenna gain to operatio nal noise temperature (G/Top) of the system. The Deep Space Network (DSN) receivers are cryogenic, low-noise amplifiers (LNAs) which addres s the need to maintain Top as low as technology permits. Historicall y, the extra-ordinarily sensitive receive systems operated by the DSN have required ctyogenically cooled, ruby masers, operating at a physi cal temperature near the boiling point of helium, as the LNA. Althoug h masers continue to be used today, they are hand crafted at JPL and expensive to manufacture and maintain. Recent advances in the developm ent of indium phosphide (InP) based high electron mobility transistor s (HEMTs) combined with cryogenic cooling near the boiling point of h ydrogen have made this alternate technology comparable with and a fraction of the cost of maser technology. InP HEMT LNA modules are demons trating noise temperatures less than ten times the quantum noise limi t (10hf/k) from 1 to 100 GHz. To date, the lowest noise LNA modules developed for the DSN have demonstrated noise temperatures of 3.5 K and 8.5 K at 8.5 K at 32 GHz, respectively. Front-end receiver packages employing these modules have demonstrated operating system noise temperatures of 17 K at 8.4 GHz (on a 70m antenna at zenith) and 39 K at 3 2 GHz (on a 34m antenna at zenith). The development and demonstration of cryogenic, InP HEMT based front-end amplifiers for the DSN requir es accurate component and module characterization, and modeling from 1 to 100 GHz at physical temperatures down to 12 K. The characterizati on and modeling begins with the HEMT chip, proceeds to the multi-stag e HEMT LNA module, and culminates with the complete front-end cryogenic receiver package for the antenna. This presentation will provide a n overview of this development process. Examples will be shown for de vices, LNA modules, front-end receiver packages, antennae employing these packages and the improvements to the down-link capacity.

Adapting wave-front algorithms to efficiently utilize systems with deep communication hierarchies

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kerbyson, Darren J; Lang, Michael; Pakin, Scott

2009-01-01

Large-scale systems increasingly exhibit a differential between intra-chip and inter-chip communication performance. Processor-cores on the same socket are able to communicate at lower latencies, and with higher bandwidths, than cores on different sockets either within the same node or between nodes. A key challenge is to efficiently use this communication hierarchy and hence optimize performance. We consider here the class of applications that contain wave-front processing. In these applications data can only be processed after their upstream neighbors have been processed. Similar dependencies result between processors in which communication is required to pass boundary data downstream and whose cost ismore » typically impacted by the slowest communication channel in use. In this work we develop a novel hierarchical wave-front approach that reduces the use of slower communications in the hierarchy but at the cost of additional computation and higher use of on-chip communications. This tradeoff is explored using a performance model and an implementation on the Petascale Roadrunner system demonstrates a 27% performance improvement at full system-scale on a kernel application. The approach is generally applicable to large-scale multi-core and accelerated systems where a differential in system communication performance exists.« less

Random On-Board Pixel Sampling (ROPS) X-Ray Camera

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Zhehui; Iaroshenko, O.; Li, S.

Recent advances in compressed sensing theory and algorithms offer new possibilities for high-speed X-ray camera design. In many CMOS cameras, each pixel has an independent on-board circuit that includes an amplifier, noise rejection, signal shaper, an analog-to-digital converter (ADC), and optional in-pixel storage. When X-ray images are sparse, i.e., when one of the following cases is true: (a.) The number of pixels with true X-ray hits is much smaller than the total number of pixels; (b.) The X-ray information is redundant; or (c.) Some prior knowledge about the X-ray images exists, sparse sampling may be allowed. Here we first illustratemore » the feasibility of random on-board pixel sampling (ROPS) using an existing set of X-ray images, followed by a discussion about signal to noise as a function of pixel size. Next, we describe a possible circuit architecture to achieve random pixel access and in-pixel storage. The combination of a multilayer architecture, sparse on-chip sampling, and computational image techniques, is expected to facilitate the development and applications of high-speed X-ray camera technology.« less

Angular resolution of the gaseous micro-pixel detector Gossip

NASA Astrophysics Data System (ADS)

Bilevych, Y.; Blanco Carballo, V.; van Dijk, M.; Fransen, M.; van der Graaf, H.; Hartjes, F.; Hessey, N.; Koppert, W.; Nauta, S.; Rogers, M.; Romaniouk, A.; Veenhof, R.

2011-06-01

Gossip is a gaseous micro-pixel detector with a very thin drift gap intended for a high rate environment like at the pixel layers of ATLAS at the sLHC. The detector outputs not only the crossing point of a traversing MIP, but also the angle of the track, thus greatly simplifying track reconstruction. In this paper we describe a testbeam experiment to examine the angular resolution of the reconstructed track segments in Gossip. We used here the low diffusion gas mixture DME/CO 2 50/50. An angular resolution of 20 mrad for perpendicular tracks could be obtained from a 1.5 mm thin drift volume. However, for the prototype detector used at the testbeam experiment, the resolution of slanting tracks was worsened by poor time resolution of the pixel chip used.

Velocity map imaging using an in-vacuum pixel detector.

PubMed

Gademann, Georg; Huismans, Ymkje; Gijsbertsen, Arjan; Jungmann, Julia; Visschers, Jan; Vrakking, Marc J J

2009-10-01

The use of a new type in-vacuum pixel detector in velocity map imaging (VMI) is introduced. The Medipix2 and Timepix semiconductor pixel detectors (256 x 256 square pixels, 55 x 55 microm2) are well suited for charged particle detection. They offer high resolution, low noise, and high quantum efficiency. The Medipix2 chip allows double energy discrimination by offering a low and a high energy threshold. The Timepix detector allows to record the incidence time of a particle with a temporal resolution of 10 ns and a dynamic range of 160 micros. Results of the first time application of the Medipix2 detector to VMI are presented, investigating the quantum efficiency as well as the possibility to operate at increased background pressure in the vacuum chamber.

A 7 ke-SD-FWC 1.2 e-RMS Temporal Random Noise 128×256 Time-Resolved CMOS Image Sensor With Two In-Pixel SDs for Biomedical Applications.

PubMed

Seo, Min-Woong; Kawahito, Shoji

2017-12-01

A large full well capacity (FWC) for wide signal detection range and low temporal random noise for high sensitivity lock-in pixel CMOS image sensor (CIS) embedded with two in-pixel storage diodes (SDs) has been developed and presented in this paper. For fast charge transfer from photodiode to SDs, a lateral electric field charge modulator (LEFM) is used for the developed lock-in pixel. As a result, the time-resolved CIS achieves a very large SD-FWC of approximately 7ke-, low temporal random noise of 1.2e-rms at 20 fps with true correlated double sampling operation and fast intrinsic response less than 500 ps at 635 nm. The proposed imager has an effective pixel array of and a pixel size of . The sensor chip is fabricated by Dongbu HiTek 1P4M 0.11 CIS process.

CMOS imager for pointing and tracking applications

NASA Technical Reports Server (NTRS)

Sun, Chao (Inventor); Pain, Bedabrata (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

2006-01-01

Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

X-ray metrology of an array of active edge pixel sensors for use at synchrotron light sources

NASA Astrophysics Data System (ADS)

Plackett, R.; Arndt, K.; Bortoletto, D.; Horswell, I.; Lockwood, G.; Shipsey, I.; Tartoni, N.; Williams, S.

2018-01-01

We report on the production and testing of an array of active edge silicon sensors as a prototype of a large array. Four Medipix3RX.1 chips were bump bonded to four single chip sized Advacam active edge n-on-n sensors. These detectors were then mounted into a 2 by 2 array and tested on B16 at Diamond Light Source with an x-ray beam spot of 2um. The results from these tests, compared with optical metrology demonstrate that this type of sensor is sensitive to the physical edge of the silicon, with only a modest loss of efficiency in the final two rows of pixels. We present the efficiency maps recorded with the microfocus beam and a sample powder diffraction measurement. These results give confidence that this sensor technology can be used effectively in larger arrays of detectors at synchrotron light sources.

Model of Image Artifacts from Dust Particles

NASA Technical Reports Server (NTRS)

Willson, Reg

2008-01-01

A mathematical model of image artifacts produced by dust particles on lenses has been derived. Machine-vision systems often have to work with camera lenses that become dusty during use. Dust particles on the front surface of a lens produce image artifacts that can potentially affect the performance of a machine-vision algorithm. The present model satisfies a need for a means of synthesizing dust image artifacts for testing machine-vision algorithms for robustness (or the lack thereof) in the presence of dust on lenses. A dust particle can absorb light or scatter light out of some pixels, thereby giving rise to a dark dust artifact. It can also scatter light into other pixels, thereby giving rise to a bright dust artifact. For the sake of simplicity, this model deals only with dark dust artifacts. The model effectively represents dark dust artifacts as an attenuation image consisting of an array of diffuse darkened spots centered at image locations corresponding to the locations of dust particles. The dust artifacts are computationally incorporated into a given test image by simply multiplying the brightness value of each pixel by a transmission factor that incorporates the factor of attenuation, by dust particles, of the light incident on that pixel. With respect to computation of the attenuation and transmission factors, the model is based on a first-order geometric (ray)-optics treatment of the shadows cast by dust particles on the image detector. In this model, the light collected by a pixel is deemed to be confined to a pair of cones defined by the location of the pixel s image in object space, the entrance pupil of the lens, and the location of the pixel in the image plane (see Figure 1). For simplicity, it is assumed that the size of a dust particle is somewhat less than the diameter, at the front surface of the lens, of any collection cone containing all or part of that dust particle. Under this assumption, the shape of any individual dust particle artifact is the shape (typically, circular) of the aperture, and the contribution of the particle to the attenuation factor for a given pixel is the fraction of the cross-sectional area of the collection cone occupied by the particle. Assuming that dust particles do not overlap, the net transmission factor for a given pixel is calculated as one minus the sum of attenuation factors contributed by all dust particles affecting that pixel. In a test, the model was used to synthesize attenuation images for random distributions of dust particles on the front surface of a lens at various relative aperture (F-number) settings. As shown in Figure 2, the attenuation images resembled dust artifacts in real test images recorded while the lens was aimed at a white target.

Convolving optically addressed VLSI liquid crystal SLM

NASA Astrophysics Data System (ADS)

Jared, David A.; Stirk, Charles W.

1994-03-01

We designed, fabricated, and tested an optically addressed spatial light modulator (SLM) that performs a 3 X 3 kernel image convolution using ferroelectric liquid crystal on VLSI technology. The chip contains a 16 X 16 array of current-mirror-based convolvers with a fixed kernel for finding edges. The pixels are located on 75 micron centers, and the modulators are 20 microns on a side. The array successfully enhanced edges in illumination patterns. We developed a high-level simulation tool (CON) for analyzing the performance of convolving SLM designs. CON has a graphical interface and simulates SLM functions using SPICE-like device models. The user specifies the pixel function along with the device parameters and nonuniformities. We discovered through analysis, simulation and experiment that the operation of current-mirror-based convolver pixels is degraded at low light levels by the variation of transistor threshold voltages inherent to CMOS chips. To function acceptable, the test SLM required the input image to have an minimum irradiance of 10 (mu) W/cm2. The minimum required irradiance can be further reduced by adding a photodarlington near the photodetector or by increasing the size of the transistors used to calculate the convolution.

Compact, Miniature MMIC Receiver Modules for an MMIC Array Spectrograph

NASA Technical Reports Server (NTRS)

Kangaslahti, Pekka P.; Gaier, Todd C.; Cooperrider, Joelle T.; Samoska, Lorene A.; Soria, Mary M.; ODwyer, Ian J.; Weinreb, Sander; Custodero, Brian; Owen, Heahter; Grainge, Keith;

Fractional Multistage Hydrothermal Liquefaction of Biomass and Catalytic Conversion into Hydrocarbons

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cortright, Randy; Rozmiarek, Robert; Dally, Brice

2017-08-31

The objective of this project was to develop an improved multistage process for the hydrothermal liquefaction (HTL) of biomass to serve as a new front-end, deconstruction process ideally suited to feed Virent’s well-proven catalytic technology, which is already being scaled up. This process produced water soluble, partially de-oxygenated intermediates that are ideally suited for catalytic finishing to fungible distillate hydrocarbons. Through this project, Virent, with its partners, demonstrated the conversion of pine wood chips to drop-in hydrocarbon distillate fuels using a multi-stage fractional conversion system that is integrated with Virent’s BioForming® process. The majority of work was in the liquefactionmore » task and included temperature scoping, solvent optimization, and separations.« less

Development of the swathe-felling mobile chipper

Treesearch

P. Koch; T.E. Savage

1980-01-01

A harvesting machine and auxilary equipment are being developed to recover logging residues us chips for fuel and fiber, and to deliver these chips to mills at ubout $18 per green ton including 30 percent pre-tax profit on the equipment investment. The harvester, a 575 horsepower trucked mobile chipper equipped with a front-mounted felling bar, wus field-tested on red...

A smartphone-based chip-scale microscope using ambient illumination.

PubMed

Lee, Seung Ah; Yang, Changhuei

2014-08-21

Portable chip-scale microscopy devices can potentially address various imaging needs in mobile healthcare and environmental monitoring. Here, we demonstrate the adaptation of a smartphone's camera to function as a compact lensless microscope. Unlike other chip-scale microscopy schemes, this method uses ambient illumination as its light source and does not require the incorporation of a dedicated light source. The method is based on the shadow imaging technique where the sample is placed on the surface of the image sensor, which captures direct shadow images under illumination. To improve the image resolution beyond the pixel size, we perform pixel super-resolution reconstruction with multiple images at different angles of illumination, which are captured while the user is manually tilting the device around any ambient light source, such as the sun or a lamp. The lensless imaging scheme allows for sub-micron resolution imaging over an ultra-wide field-of-view (FOV). Image acquisition and reconstruction are performed on the device using a custom-built Android application, constructing a stand-alone imaging device for field applications. We discuss the construction of the device using a commercial smartphone and demonstrate the imaging capabilities of our system.

A smartphone-based chip-scale microscope using ambient illumination

PubMed Central

Lee, Seung Ah; Yang, Changhuei

2014-01-01

Portable chip-scale microscopy devices can potentially address various imaging needs in mobile healthcare and environmental monitoring. Here, we demonstrate the adaptation of a smartphone’s camera to function as a compact lensless microscope. Unlike other chip-scale microscopy schemes, this method uses ambient illumination as its light source and does not require the incorporation of a dedicated light source. The method is based on the shadow imaging technique where the sample is placed on the surface of the image sensor, which captures direct shadow images under illumination. To improve the imaging resolution beyond the pixel size, we perform pixel super-resolution reconstruction with multiple images at different angles of illumination, which are captured while the user is manually tilting the device around any ambient light source, such as the sun or a lamp. The lensless imaging scheme allows for sub-micron resolution imaging over an ultra-wide field-of-view (FOV). Image acquisition and reconstruction is performed on the device using a custom-built android application, constructing a stand-alone imaging device for field applications. We discuss the construction of the device using a commercial smartphone and demonstrate the imaging capabilities of our system. PMID:24964209

SAD-Based Stereo Vision Machine on a System-on-Programmable-Chip (SoPC)

PubMed Central

Zhang, Xiang; Chen, Zhangwei

2013-01-01

This paper, proposes a novel solution for a stereo vision machine based on the System-on-Programmable-Chip (SoPC) architecture. The SOPC technology provides great convenience for accessing many hardware devices such as DDRII, SSRAM, Flash, etc., by IP reuse. The system hardware is implemented in a single FPGA chip involving a 32-bit Nios II microprocessor, which is a configurable soft IP core in charge of managing the image buffer and users' configuration data. The Sum of Absolute Differences (SAD) algorithm is used for dense disparity map computation. The circuits of the algorithmic module are modeled by the Matlab-based DSP Builder. With a set of configuration interfaces, the machine can process many different sizes of stereo pair images. The maximum image size is up to 512 K pixels. This machine is designed to focus on real time stereo vision applications. The stereo vision machine offers good performance and high efficiency in real time. Considering a hardware FPGA clock of 90 MHz, 23 frames of 640 × 480 disparity maps can be obtained in one second with 5 × 5 matching window and maximum 64 disparity pixels. PMID:23459385

End-Users, Front Ends and Librarians.

ERIC Educational Resources Information Center

Bourne, Donna E.

1989-01-01

The increase in end-user searching, the advantages and limitations of front ends, and the role of the librarian in end-user searching are discussed. It is argued that librarians need to recognize that front ends can be of benefit to themselves and patrons, and to assume the role of advisors and educators for end-users. (37 references) (CLB)

Wavefront image sensor chip

PubMed Central

Cui, Xiquan; Ren, Jian; Tearney, Guillermo J.; Yang, Changhuei

2010-01-01

We report the implementation of an image sensor chip, termed wavefront image sensor chip (WIS), that can measure both intensity/amplitude and phase front variations of a light wave separately and quantitatively. By monitoring the tightly confined transmitted light spots through a circular aperture grid in a high Fresnel number regime, we can measure both intensity and phase front variations with a high sampling density (11 µm) and high sensitivity (the sensitivity of normalized phase gradient measurement is 0.1 mrad under the typical working condition). By using WIS in a standard microscope, we can collect both bright-field (transmitted light intensity) and normalized phase gradient images. Our experiments further demonstrate that the normalized phase gradient images of polystyrene microspheres, unstained and stained starfish embryos, and strongly birefringent potato starch granules are improved versions of their corresponding differential interference contrast (DIC) microscope images in that they are artifact-free and quantitative. Besides phase microscopy, WIS can benefit machine recognition, object ranging, and texture assessment for a variety of applications. PMID:20721059

VizieR Online Data Catalog: BVR light curves of UZ Leo (Lee+, 2018)

NASA Astrophysics Data System (ADS)

Lee, J. W.; Park, J.-H.

2018-04-01

We performed new CCD photometry of UZ Leo during two observing seasons between 2012 February and 2013 April, using a PIXIS: 2048B CCD and a BVR filter set attached to the 61 cm reflector at Sobaeksan Optical Astronomy Observatory (SOAO) in Korea. The CCD chip has 2048x2048pixels and a pixel size of 13.5um, so the field of view of a CCD frame is 17.6'x17.6'. (1 data file).

WFC3/UVIS Updated 2017 Chip-Dependent Inverse Sensitivity Values

NASA Astrophysics Data System (ADS)

Deustua, S. E.; Mack, J.; Bajaj, V.; Khandrika, H.

2017-06-01

We present chip-dependent inverse sensitivity values recomputed for the 42 full frame filters based on the analysis of standard star observations with the WFC3/UVIS imager obtained between 2009 and 2015. Chip-dependent inverse sensitivities reported in the image header are now for the 'infinite' aperture, which is defined to have a radius of 6 arcseconds (151 pixels), and supercede the 2016 photometry header keyword values (PHOTFLAM, PHTFLAM1, PHTFLAM2), which correspond to a 0.3962 arcsecond (10 pixel) aperture. These new values are implemented in the June 2017 IMPHTTAB delivery and are concordant with the current synthetic photometry tables in the reference file database (CRDS). Since approximately 90% of the light is enclosed within 10 pixels, the new keyword values are 10% smaller. We also compute inverse sensitivities for an aperture with radius of 0.3962 arcseconds. Compared to the 2016 implementation, these new inverse sensitivity values differ by less than 0.5%, on average, for the same aperture. Values for the filters F200LP, F350LP, F600LP and F487N changed by more than 1% for UVIS1. UVIS2 values that changed by more than 1% are for the filters F350LP, F600LP, F850LP, F487N, and F814W. The 2017 VEGAmag zeropoint values in the UV change by up to 0.1 mag compared to 2016 and are calculated using the CALPSEC STIS spectrum for Vega. In 2016, the zeropoints were calculated with the CALSPEC Vega model.

Junction-side illuminated silicon detector arrays

DOEpatents

Iwanczyk, Jan S.; Patt, Bradley E.; Tull, Carolyn

2004-03-30

A junction-side illuminated detector array of pixelated detectors is constructed on a silicon wafer. A junction contact on the front-side may cover the whole detector array, and may be used as an entrance window for light, x-ray, gamma ray and/or other particles. The back-side has an array of individual ohmic contact pixels. Each of the ohmic contact pixels on the back-side may be surrounded by a grid or a ring of junction separation implants. Effective pixel size may be changed by separately biasing different sections of the grid. A scintillator may be coupled directly to the entrance window while readout electronics may be coupled directly to the ohmic contact pixels. The detector array may be used as a radiation hardened detector for high-energy physics research or as avalanche imaging arrays.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Britton, C.L.; Jagadish, U.; Bryan, W.L.

An Integrated Circuit (IC) readout chip with four channels arranged so as to receive input charge from the corners of the chip was designed for use with 5- to 7-mm pixel detectors. This Application Specific IC (ASIC) can be used for cold neutron imaging, for study of structural order in materials using cold neutron scattering or for particle physics experiments. The ASIC is fabricated in a 0.5-{micro}m n-well AMI process. The design of the ASIC and the test measurements made is reported. Noise measurements are also reported.

Flip Chip Bonding of 68 x 68 MWIR LED Arrays

DTIC Science & Technology

2009-01-01

transmission of IR light through GaSb material varies between 5%–30% and depends on the type of substrate dopants (n- or p-type). Hence, for bottom...emission regions (8.9/16 monolayer’s (ml) InAs/GaSb) separated by (n InAs/GaSb super lattice grade)/(p+ GaSb) tunnel junctions. Graded super lattices were...flip chip bonding process. Besides four corner LED test pads, there are 296 bonding pads in the CMOS driver to bias each LED pixel independently. The

IMOTEPAD: A mixed-signal 64-channel front-end ASIC for small-animal PET imaging

NASA Astrophysics Data System (ADS)

Fang, Xiaochao; Ollivier-Henry, Nicolas; Gao, Wu; Hu-Guo, Christine; Colledani, Claude; Humbert, Bernard; Brasse, David; Hu, Yann

2011-04-01

This paper presents the design and characteristics of a mixed-signal 64-channel front-end readout ASIC called IMOTEPAD dedicated to multi-channel plate (MCP) photodetector coupled to LYSO scintillating crystals for small-animal PET imaging. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. As a result, both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. This dedicated ASIC IMOTEPAD comprises two parts: the analog part IMOTEPA and the digital part IMOTEPD. The IMOTEPA is dedicated to energy measurement. And the timing information is digitized by the IMOTEPD in which the key principal element is a time-to-digital converter (TDC) based on a delay-locked loop (DLL) with 32 delay cells. The chip is designed and fabricated in 0.35 μm CMOS process. The measurements show that for the analog part IMOTEPA, the energy gain is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The SNR is 39 dB and the RMS noise is 300 μV. The nonlinearity is less than 3%. The crosstalk is less than 0.2%. For the IMOTEPD, the bin size of the TDC is 625 ps with a reference clock of 50 MHz. The RMS jitter of the DLL is less than 42 ps. The DNL of the TDC is equal to about 0.17 LSB and the INL is equal to 0.31 LSB. The power dissipation of each channel is less than 16.8 mW. The design of the ASIC, especially for TDC and the measurement results of the IMOTEPAD will be presented and discussed in this paper.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the first six months of this project were to lay the foundations for both the SiC front-end optical chip fabrication as well as the free-space laser beam interferometer designs and preliminary tests. In addition, a Phase I goal was to design and experimentally build the high temperature and pressure infrastructure and test systems that will be used in the next 6 months for proposed sensor experimentation and data processing. All these goals have been achieved and are described in detail in the report. Both design process and diagrams for the mechanical elements as well as the opticalmore » systems are provided. In addition, photographs of the fabricated SiC optical chips, the high temperature & pressure test chamber instrument, the optical interferometer, the SiC sample chip holder, and signal processing data are provided. The design and experimentation results are summarized to give positive conclusions on the proposed novel high temperature optical sensor technology. The goals of the second six months of this project were to conduct high temperature sensing tests using the test chamber and optical sensing instrument designs developed in the first part of the project. In addition, a Phase I goal was to develop the basic processing theory and physics for the proposed first sensor experimentation and data processing. All these goals have been achieved and are described in detail. Both optical experimental design process and sensed temperature are provided. In addition, photographs of the fabricated SiC optical chips after deployment in the high temperature test chamber are shown from a material study point-of-view.« less

Design and construction of a prototype ACTS propagation terminal

NASA Technical Reports Server (NTRS)

Stutzman, Warren; Pratt, Tim; Nunnally, Charles; Nealy, Randall; Remaklus, Will; Sylvester, Bill; Predoehl, Andrew; Gaff, Doug

1993-01-01

The launch schedule for the Advanced Communication Technology Satellite (ACTS) spacecraft did not leave sufficient time for completion of the prototype ACTS Propagation Terminals (APT) prior to initiation of the APT production phase. In fact, the approach used was to construct and test all subassemblies of the terminal with special emphasis on the technically challenging portions. These include the RF front end that uses a state-of-the-art down converter which integrates a low noise amplifier, mixer, post amplifier, filter, and local oscillator port frequency doubler into a single small package. In addition, a new digital receiver that uses the latest DSP technology was developed. Both of these subassemblies were thoroughly tested. The highest risk technology in the APT program was the digital receiver. Several candidate algorithms and DSP chips were investigated early on, primarily under JPL sponsorship. A receiver was constructed based on Texas Instruments chip. The final prototype digital receiver was one based on an Analog Devices chip. The design and test results are documented in a report prepared for this grant. A Primary Design Review (PDR) was conducted 30 May 1991, and a Critical Design Review was held 7 Jul. 1992. Final complete documentation of the APT's will appear in the form of three reports: a hardware description report, a report on the data collection code (ACTS VIEW), and a report on the preprocessing code.

An acoustic charge transport imager for high definition television applications

NASA Technical Reports Server (NTRS)

Hunt, W. D.; Brennan, K. F.; Summers, C. J.

1994-01-01

The primary goal of this research is to develop a solid-state television (HDTV) imager chip operating at a frame rate of about 170 frames/sec at 2 Megapixels/frame. This imager will offer an order of magnitude improvements in speed over CCD designs and will allow for monolithic imagers operating from the IR to UV. The technical approach of the project focuses on the development of the three basic components of the imager and their subsequent integration. The camera chip can be divided into three distinct functions: (1) image capture via an array of avalanche photodiodes (APD's); (2) charge collection, storage, and overflow control via a charge transfer transistor device (CTD); and (3) charge readout via an array of acoustic charge transport (ACT) channels. The use of APD's allows for front end gain at low noise and low operating voltages while the ACT readout enables concomitant high speed and high charge transfer efficiency. Currently work is progressing towards the optimization of each of these component devices. In addition to the development of each of the three distinct components, work towards their integration and manufacturability is also progressing. The component designs are considered not only to meet individual specifications but to provide overall system level performance suitable for HDTV operation upon integration. The ultimate manufacturability and reliability of the chip constrains the design as well. The progress made during this period is described in detail.

Progress on the upgrade of the CMS Hadron Calorimeter Front-End electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Anderson, Jake; Whitmore, Juliana; /Fermilab

2011-11-01

We present a scheme to upgrade the CMS HCAL front-end electronics in the second long shutdown to upgrade the LHC (LS2), which is expected to occur around 2018. The HCAL electronics upgrade is required to handle the major instantaneous luminosity increase (up to 5 * 10{sup 34} cm{sup -2} s{sup -1}) and an expected integrated luminosity of {approx}3000 fb{sup -1}. A key aspect of the HCAL upgrade is to read out longitudinal segmentation information to improve background rejection, energy resolution, and electron isolation at the L1 trigger. This paper focuses on the requirements for the new electronics and on themore » proposed solutions. The requirements include increased channel count, additional timing capabilities, and additional redundancy. The electronics are required to operate in a harsh environment and are constrained by the existing infrastructure. The proposed solutions span from chip level to system level. They include the development of a new ASIC ADC, the design and testing of higher speed transmitters to handle the increased data volume, the evaluation and use of circuits from other developments, evaluation of commercial FPGAs, better thermal design, and improvements in the overall readout architecture. We will report on the progress of the designs for these upgraded systems, along with performance requirements and initial design studies.« less

Fully Integrated Passive UHF RFID Tag for Hash-Based Mutual Authentication Protocol

PubMed Central

Mikami, Shugo; Watanabe, Dai; Li, Yang; Sakiyama, Kazuo

2015-01-01

Passive radio-frequency identification (RFID) tag has been used in many applications. While the RFID market is expected to grow, concerns about security and privacy of the RFID tag should be overcome for the future use. To overcome these issues, privacy-preserving authentication protocols based on cryptographic algorithms have been designed. However, to the best of our knowledge, evaluation of the whole tag, which includes an antenna, an analog front end, and a digital processing block, that runs authentication protocols has not been studied. In this paper, we present an implementation and evaluation of a fully integrated passive UHF RFID tag that runs a privacy-preserving mutual authentication protocol based on a hash function. We design a single chip including the analog front end and the digital processing block. We select a lightweight hash function supporting 80-bit security strength and a standard hash function supporting 128-bit security strength. We show that when the lightweight hash function is used, the tag completes the protocol with a reader-tag distance of 10 cm. Similarly, when the standard hash function is used, the tag completes the protocol with the distance of 8.5 cm. We discuss the impact of the peak power consumption of the tag on the distance of the tag due to the hash function. PMID:26491714

A Wearable EEG-HEG-HRV Multimodal System With Simultaneous Monitoring of tES for Mental Health Management.

PubMed

Ha, Unsoo; Lee, Yongsu; Kim, Hyunki; Roh, Taehwan; Bae, Joonsung; Kim, Changhyeon; Yoo, Hoi-Jun

2015-12-01

A multimodal mental management system in the shape of the wearable headband and earplugs is proposed to monitor electroencephalography (EEG), hemoencephalography (HEG) and heart rate variability (HRV) for accurate mental health monitoring. It enables simultaneous transcranial electrical stimulation (tES) together with real-time monitoring. The total weight of the proposed system is less than 200 g. The multi-loop low-noise amplifier (MLLNA) achieves over 130 dB CMRR for EEG sensing and the capacitive correlated-double sampling transimpedance amplifier (CCTIA) has low-noise characteristics for HEG and HRV sensing. Measured three-physiology domains such as neural, vascular and autonomic domain signals are combined with canonical correlation analysis (CCA) and temporal kernel canonical correlation analysis (tkCCA) algorithm to find the neural-vascular-autonomic coupling. It supports highly accurate classification with the 19% maximum improvement with multimodal monitoring. For the multi-channel stimulation functionality, after-effects maximization monitoring and sympathetic nerve disorder monitoring, the stimulator is designed as reconfigurable. The 3.37 × 2.25 mm(2) chip has 2-channel EEG sensor front-end, 2-channel NIRS sensor front-end, NIRS current driver to drive dual-wavelength VCSEL and 6-b DAC current source for tES mode. It dissipates 24 mW with 2 mA stimulation current and 5 mA NIRS driver current.

A compressed sensing X-ray camera with a multilayer architecture

DOE PAGES

Wang, Zhehui; Laroshenko, O.; Li, S.; ...

2018-01-25

Recent advances in compressed sensing theory and algorithms offer new possibilities for high-speed X-ray camera design. In many CMOS cameras, each pixel has an independent on-board circuit that includes an amplifier, noise rejection, signal shaper, an analog-to-digital converter (ADC), and optional in-pixel storage. When X-ray images are sparse, i.e., when one of the following cases is true: (a.) The number of pixels with true X-ray hits is much smaller than the total number of pixels; (b.) The X-ray information is redundant; or (c.) Some prior knowledge about the X-ray images exists, sparse sampling may be allowed. In this work, wemore » first illustrate the feasibility of random on-board pixel sampling (ROPS) using an existing set of X-ray images, followed by a discussion about signal to noise as a function of pixel size. Next, we describe a possible circuit architecture to achieve random pixel access and in-pixel storage. The combination of a multilayer architecture, sparse on-chip sampling, and computational image techniques, is expected to facilitate the development and applications of high-speed X-ray camera technology.« less

A compressed sensing X-ray camera with a multilayer architecture

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Zhehui; Laroshenko, O.; Li, S.

Recent advances in compressed sensing theory and algorithms offer new possibilities for high-speed X-ray camera design. In many CMOS cameras, each pixel has an independent on-board circuit that includes an amplifier, noise rejection, signal shaper, an analog-to-digital converter (ADC), and optional in-pixel storage. When X-ray images are sparse, i.e., when one of the following cases is true: (a.) The number of pixels with true X-ray hits is much smaller than the total number of pixels; (b.) The X-ray information is redundant; or (c.) Some prior knowledge about the X-ray images exists, sparse sampling may be allowed. In this work, wemore » first illustrate the feasibility of random on-board pixel sampling (ROPS) using an existing set of X-ray images, followed by a discussion about signal to noise as a function of pixel size. Next, we describe a possible circuit architecture to achieve random pixel access and in-pixel storage. The combination of a multilayer architecture, sparse on-chip sampling, and computational image techniques, is expected to facilitate the development and applications of high-speed X-ray camera technology.« less

Chromatic Modulator for a High-Resolution CCD or APS

NASA Technical Reports Server (NTRS)

Hartley, Frank; Hull, Anthony

2008-01-01

A chromatic modulator has been proposed to enable the separate detection of the red, green, and blue (RGB) color components of the same scene by a single charge-coupled device (CCD), active-pixel sensor (APS), or similar electronic image detector. Traditionally, the RGB color-separation problem in an electronic camera has been solved by use of either (1) fixed color filters over three separate image detectors; (2) a filter wheel that repeatedly imposes a red, then a green, then a blue filter over a single image detector; or (3) different fixed color filters over adjacent pixels. The use of separate image detectors necessitates precise registration of the detectors and the use of complicated optics; filter wheels are expensive and add considerably to the bulk of the camera; and fixed pixelated color filters reduce spatial resolution and introduce color-aliasing effects. The proposed chromatic modulator would not exhibit any of these shortcomings. The proposed chromatic modulator would be an electromechanical device fabricated by micromachining. It would include a filter having a spatially periodic pattern of RGB strips at a pitch equal to that of the pixels of the image detector. The filter would be placed in front of the image detector, supported at its periphery by a spring suspension and electrostatic comb drive. The spring suspension would bias the filter toward a middle position in which each filter strip would be registered with a row of pixels of the image detector. Hard stops would limit the excursion of the spring suspension to precisely one pixel row above and one pixel row below the middle position. In operation, the electrostatic comb drive would be actuated to repeatedly snap the filter to the upper extreme, middle, and lower extreme positions. This action would repeatedly place a succession of the differently colored filter strips in front of each pixel of the image detector. To simplify the processing, it would be desirable to encode information on the color of the filter strip over each row (or at least over some representative rows) of pixels at a given instant of time in synchronism with the pixel output at that instant.

Virus based Full Colour Pixels using a Microheater

NASA Astrophysics Data System (ADS)

Kim, Won-Geun; Kim, Kyujung; Ha, Sung-Hun; Song, Hyerin; Yu, Hyun-Woo; Kim, Chuntae; Kim, Jong-Man; Oh, Jin-Woo

2015-09-01

Mimicking natural structures has been received considerable attentions, and there have been a few practical advances. Tremendous efforts based on a self-assembly technique have been contributed to the development of the novel photonic structures which are mimicking nature’s inventions. We emulate the photonic structures from an origin of colour generation of mammalian skins and avian skin/feathers using M13 phage. The structures can be generated a full range of RGB colours that can be sensitively switched by temperature and substrate materials. Consequently, we developed an M13 phage-based temperature-dependent actively controllable colour pixels platform on a microheater chip. Given the simplicity of the fabrication process, the low voltage requirements and cycling stability, the virus colour pixels enable us to substitute for conventional colour pixels for the development of various implantable, wearable and flexible devices in future.

On the possibility to use semiconductive hybrid pixel detectors for study of radiation belt of the Earth.

NASA Astrophysics Data System (ADS)

Guskov, A.; Shelkov, G.; Smolyanskiy, P.; Zhemchugov, A.

2016-02-01

The scientific apparatus GAMMA-400 designed for study of electromagnetic and hadron components of cosmic rays will be launched to an elliptic orbit with the apogee of about 300 000 km and the perigee of about 500 km. Such a configuration of the orbit allows it to cross periodically the radiation belt and the outer part of magnetosphere. We discuss the possibility to use hybrid pixel detecters based on the Timepix chip and semiconductive sensors on board the GAMMA-400 apparatus. Due to high granularity of the sensor (pixel size is 55 mum) and possibility to measure independently an energy deposition in each pixel, such compact and lightweight detector could be a unique instrument for study of spatial, energy and time structure of electron and proton components of the radiation belt.

Velocity map imaging using an in-vacuum pixel detector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gademann, Georg; Huismans, Ymkje; Gijsbertsen, Arjan

The use of a new type in-vacuum pixel detector in velocity map imaging (VMI) is introduced. The Medipix2 and Timepix semiconductor pixel detectors (256x256 square pixels, 55x55 {mu}m{sup 2}) are well suited for charged particle detection. They offer high resolution, low noise, and high quantum efficiency. The Medipix2 chip allows double energy discrimination by offering a low and a high energy threshold. The Timepix detector allows to record the incidence time of a particle with a temporal resolution of 10 ns and a dynamic range of 160 {mu}s. Results of the first time application of the Medipix2 detector to VMImore » are presented, investigating the quantum efficiency as well as the possibility to operate at increased background pressure in the vacuum chamber.« less

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

NASA Astrophysics Data System (ADS)

Bartelink, Dirk J.

1998-11-01

The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must recognize—test is also performed using IC's. A system interconnection is proposed using multiple chips fabricated with conventional silicon processes, including MEMS technology. The system resembles an MCM that can be joined without committing to final assembly to perform at-speed testing. 50-Ohm test probes never load the circuit; only intended neighboring chips are ever connected. A `back-plane' chip provides the connection layers for both inter- and intra-chip signals and also serves as the probe card, in analogy with membrane probes now used for single-chip testing. Intra-chip connections, which require complicated connections during test that exactly match the product, are then properly made and all waveforms and loading conditions under test will be identical to those of the product. The major benefit is that all front-end chip technologies can be merged—logic, memory, RF, even passives. ESD protection is required only on external system connections. Manufacturing test information will accurately characterize process faults and thus avoid the Known-Good-Die problem that has slowed the arrival of conventional MCM's.

A 1024×768-12μm Digital ROIC for uncooled microbolometer FPAs

NASA Astrophysics Data System (ADS)

Eminoglu, Selim

2017-02-01

This paper reports the development of a new digital microbolometer Readout Integrated Circuit (D-ROIC), called MT10212BD. It has a format of 1024 × 768 (XGA) and a pixel pitch of 12μm. MT10212BD is Mikro Tasarim's second 12μm pitch microbolometer ROIC, which is developed specifically for surface micro machined microbolometer detector arrays with small pixel pitch using high-TCR pixel materials, such as VOx and a Si. MT10212BD has an alldigital system on-chip architecture, which generates programmable timing and biasing, and performs 14-bit analog to digital conversion (ADC). The signal processing chain in the ROIC is composed of pixel bias circuitry, integrator based programmable gain amplifier followed by column parallel ADC circuitry. MT10212BD has a serial programming interface that can be used to configure the programmable ROIC features and to load the Non-Uniformity-Correction (NUC) date to the ROIC. MT10212BD has a total of 8 high-speed serial digital video outputs, which can be programmed to operate in the 2, 4, and 8-output modes and can support frames rates above 60 fps. The high-speed serial digital outputs supports data rates as high as 400 Mega-bits/s, when operated at 50 MHz system clock frequency. There is an on-chip phase-locked-loop (PLL) based timing circuitry to generate the high speed clocks used in the ROIC. The ROIC is designed to support pixel resistance values ranging from 30KΩ to 90kΩ, with a nominal value of 60KΩ. The ROIC has a globally programmable gain in the column readout, which can be adjusted based on the detector resistance value.

A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager.

PubMed

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2011-10-01

Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm(2) at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm(2). Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm(2) while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt.

A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager

PubMed Central

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2012-01-01

Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm2 at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm2. Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm2 while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt. PMID:23136624

High dynamic range vision sensor for automotive applications

NASA Astrophysics Data System (ADS)

Grenet, Eric; Gyger, Steve; Heim, Pascal; Heitger, Friedrich; Kaess, Francois; Nussbaum, Pascal; Ruedi, Pierre-Francois

2005-02-01

A 128 x 128 pixels, 120 dB vision sensor extracting at the pixel level the contrast magnitude and direction of local image features is used to implement a lane tracking system. The contrast representation (relative change of illumination) delivered by the sensor is independent of the illumination level. Together with the high dynamic range of the sensor, it ensures a very stable image feature representation even with high spatial and temporal inhomogeneities of the illumination. Dispatching off chip image feature is done according to the contrast magnitude, prioritizing features with high contrast magnitude. This allows to reduce drastically the amount of data transmitted out of the chip, hence the processing power required for subsequent processing stages. To compensate for the low fill factor (9%) of the sensor, micro-lenses have been deposited which increase the sensitivity by a factor of 5, corresponding to an equivalent of 2000 ASA. An algorithm exploiting the contrast representation output by the vision sensor has been developed to estimate the position of a vehicle relative to the road markings. The algorithm first detects the road markings based on the contrast direction map. Then, it performs quadratic fits on selected kernel of 3 by 3 pixels to achieve sub-pixel accuracy on the estimation of the lane marking positions. The resulting precision on the estimation of the vehicle lateral position is 1 cm. The algorithm performs efficiently under a wide variety of environmental conditions, including night and rainy conditions.

Detector motion method to increase spatial resolution in photon-counting detectors

NASA Astrophysics Data System (ADS)

Lee, Daehee; Park, Kyeongjin; Lim, Kyung Taek; Cho, Gyuseong

2017-03-01

Medical imaging requires high spatial resolution of an image to identify fine lesions. Photon-counting detectors in medical imaging have recently been rapidly replacing energy-integrating detectors due to the former`s high spatial resolution, high efficiency and low noise. Spatial resolution in a photon counting image is determined by the pixel size. Therefore, the smaller the pixel size, the higher the spatial resolution that can be obtained in an image. However, detector redesigning is required to reduce pixel size, and an expensive fine process is required to integrate a signal processing unit with reduced pixel size. Furthermore, as the pixel size decreases, charge sharing severely deteriorates spatial resolution. To increase spatial resolution, we propose a detector motion method using a large pixel detector that is less affected by charge sharing. To verify the proposed method, we utilized a UNO-XRI photon-counting detector (1-mm CdTe, Timepix chip) at the maximum X-ray tube voltage of 80 kVp. A similar spatial resolution of a 55- μm-pixel image was achieved by application of the proposed method to a 110- μm-pixel detector with a higher signal-to-noise ratio. The proposed method could be a way to increase spatial resolution without a pixel redesign when pixels severely suffer from charge sharing as pixel size is reduced.

From Motion to Photons in 80 Microseconds: Towards Minimal Latency for Virtual and Augmented Reality.

PubMed

Lincoln, Peter; Blate, Alex; Singh, Montek; Whitted, Turner; State, Andrei; Lastra, Anselmo; Fuchs, Henry

2016-04-01

We describe an augmented reality, optical see-through display based on a DMD chip with an extremely fast (16 kHz) binary update rate. We combine the techniques of post-rendering 2-D offsets and just-in-time tracking updates with a novel modulation technique for turning binary pixels into perceived gray scale. These processing elements, implemented in an FPGA, are physically mounted along with the optical display elements in a head tracked rig through which users view synthetic imagery superimposed on their real environment. The combination of mechanical tracking at near-zero latency with reconfigurable display processing has given us a measured average of 80 µs of end-to-end latency (from head motion to change in photons from the display) and also a versatile test platform for extremely-low-latency display systems. We have used it to examine the trade-offs between image quality and cost (i.e. power and logical complexity) and have found that quality can be maintained with a fairly simple display modulation scheme.

Front End Software for Online Database Searching. Part 2: The Marketplace.

ERIC Educational Resources Information Center

Levy, Louise R.; Hawkins, Donald T.

1986-01-01

This article analyzes the front end software marketplace and discusses some of the complex forces influencing it. Discussion covers intermediary market; end users (library customers, scientific and technical professionals, corporate business specialists, consumers); marketing strategies; a British front end development firm; competitive pressures;…

Architecture of a general purpose embedded Slow-Control Adapter ASIC for future high-energy physics experiments

NASA Astrophysics Data System (ADS)

Gabrielli, Alessandro; Loddo, Flavio; Ranieri, Antonio; De Robertis, Giuseppe

2008-10-01

This work is aimed at defining the architecture of a new digital ASIC, namely Slow-Control Adapter (SCA), which will be designed in a commercial 130-nm CMOS technology. This chip will be embedded within a high-speed data acquisition optical link (GBT) to control and monitor the front-end electronics in future high-energy physics experiments. The GBT link provides a transparent transport layer between the SCA and control electronics in the counting room. The proposed SCA supports a variety of common bus protocols to interface with end-user general-purpose electronics. Between the GBT and the SCA a standard 100 Mb/s IEEE-802.3 compatible protocol will be implemented. This standard protocol allows off-line tests of the prototypes using commercial components that support the same standard. The project is justified because embedded applications in modern large HEP experiments require particular care to assure the lowest possible power consumption, still offering the highest reliability demanded by very large particle detectors.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deptuch, G. W.; Fahim, F.; Grybos, P.

An on-chip implementable algorithm for allocation of an X-ray photon imprint, called a hit, to a single pixel in the presence of charge sharing in a highly segmented pixel detector is described. Its proof-of-principle implementation is also given supported by the results of tests using a highly collimated X-ray photon beam from a synchrotron source. The algorithm handles asynchronous arrivals of X-ray photons. Activation of groups of pixels, comparisons of peak amplitudes of pulses within an active neighborhood and finally latching of the results of these comparisons constitute the three procedural steps of the algorithm. A grouping of pixels tomore » one virtual pixel that recovers composite signals and event driven strobes to control comparisons of fractional signals between neighboring pixels are the actuators of the algorithm. The circuitry necessary to implement the algorithm requires an extensive inter-pixel connection grid of analog and digital signals that are exchanged between pixels. A test-circuit implementation of the algorithm was achieved with a small array of 32×32 pixels and the device was exposed to an 8 keV highly collimated to a diameter of 3 μm X-ray beam. The results of these tests are given in the paper assessing physical implementation of the algorithm.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deptuch, Grzegorz W.; Fahim, Farah; Grybos, Pawel

An on-chip implementable algorithm for allocation of an X-ray photon imprint, called a hit, to a single pixel in the presence of charge sharing in a highly segmented pixel detector is described. Its proof-of-principle implementation is also given supported by the results of tests using a highly collimated X-ray photon beam from a synchrotron source. The algorithm handles asynchronous arrivals of X-ray photons. Activation of groups of pixels, comparisons of peak amplitudes of pulses within an active neighborhood and finally latching of the results of these comparisons constitute the three procedural steps of the algorithm. A grouping of pixels tomore » one virtual pixel, that recovers composite signals and event driven strobes, to control comparisons of fractional signals between neighboring pixels are the actuators of the algorithm. The circuitry necessary to implement the algorithm requires an extensive inter-pixel connection grid of analog and digital signals, that are exchanged between pixels. A test-circuit implementation of the algorithm was achieved with a small array of 32 × 32 pixels and the device was exposed to an 8 keV highly collimated to a diameter of 3-μm X-ray beam. Furthermore, the results of these tests are given in this paper assessing physical implementation of the algorithm.« less

The curse of invertase

USDA-ARS?s Scientific Manuscript database

Among the greatest quality concerns for chip and fry processing potato tubers are cold-induced sweetening, sugar end defects, translucent ends, stem-end chip defect and high acrylamide-forming potential. These problems all result from elevated amounts of glucose and fructose, reducing sugars produce...

Exploring NASA OMI Level 2 Data With Visualization

NASA Technical Reports Server (NTRS)

Wei, Jennifer; Yang, Wenli; Johnson, James; Zhao, Peisheng; Gerasimov, Irina; Pham, Long; Vicente, Gilberto

2014-01-01

Satellite data products are important for a wide variety of applications that can bring far-reaching benefits to the science community and the broader society. These benefits can best be achieved if the satellite data are well utilized and interpreted, such as model inputs from satellite, or extreme events (such as volcano eruptions, dust storms,... etc.). Unfortunately, this is not always the case, despite the abundance and relative maturity of numerous satellite data products provided by NASA and other organizations. Such obstacles may be avoided by allowing users to visualize satellite data as "images", with accurate pixel-level (Level-2) information, including pixel coverage area delineation and science team recommended quality screening for individual geophysical parameters. We present a prototype service from the Goddard Earth Sciences Data and Information Services Center (GES DISC) supporting Aura OMI Level-2 Data with GIS-like capabilities. Functionality includes selecting data sources (e.g., multiple parameters under the same scene, like NO2 and SO2, or the same parameter with different aggregation methods, like NO2 in OMNO2G and OMNO2D products), user-defined area-of-interest and temporal extents, zooming, panning, overlaying, sliding, and data subsetting, reformatting, and reprojection. The system will allow any user-defined portal interface (front-end) to connect to our backend server with OGC standard-compliant Web Mapping Service (WMS) and Web Coverage Service (WCS) calls. This back-end service should greatly enhance its expandability to integrate additional outside data/map sources.

Exploring NASA OMI Level 2 Data With Visualization

NASA Technical Reports Server (NTRS)

Wei, Jennifer C.; Yang, Wenli; Johnson, James; Zhao, Peisheng; Gerasimov, Irina; Pham, Long; Vincente, Gilbert

2014-01-01

Satellite data products are important for a wide variety of applications that can bring far-reaching benefits to the science community and the broader society. These benefits can best be achieved if the satellite data are well utilized and interpreted, such as model inputs from satellite, or extreme events (such as volcano eruptions, dust storms, etc.).Unfortunately, this is not always the case, despite the abundance and relative maturity of numerous satellite data products provided by NASA and other organizations. Such obstacles may be avoided by allowing users to visualize satellite data as images, with accurate pixel-level (Level-2) information, including pixel coverage area delineation and science team recommended quality screening for individual geophysical parameters. We present a prototype service from the Goddard Earth Sciences Data and Information Services Center (GES DISC) supporting Aura OMI Level-2 Data with GIS-like capabilities. Functionality includes selecting data sources (e.g., multiple parameters under the same scene, like NO2 and SO2, or the same parameter with different aggregation methods, like NO2 in OMNO2G and OMNO2D products), user-defined area-of-interest and temporal extents, zooming, panning, overlaying, sliding, and data subsetting, reformatting, and reprojection. The system will allow any user-defined portal interface (front-end) to connect to our backend server with OGC standard-compliant Web Mapping Service (WMS) and Web Coverage Service (WCS) calls. This back-end service should greatly enhance its expandability to integrate additional outside data-map sources.

Measuring ionizing radiation with a mobile device

NASA Astrophysics Data System (ADS)

Michelsburg, Matthias; Fehrenbach, Thomas; Puente León, Fernando

2012-02-01

In cases of nuclear disasters it is desirable to know one's personal exposure to radioactivity and the related health risk. Usually, Geiger-Mueller tubes are used to assess the situation. Equipping everyone with such a device in a short period of time is very expensive. We propose a method to detect ionizing radiation using the integrated camera of a mobile consumer device, e.g., a cell phone. In emergency cases, millions of existing mobile devices could then be used to monitor the exposure of its owners. In combination with internet access and GPS, measured data can be collected by a central server to get an overview of the situation. During a measurement, the CMOS sensor of a mobile device is shielded from surrounding light by an attachment in front of the lens or an internal shutter. The high-energy radiation produces free electrons on the sensor chip resulting in an image signal. By image analysis by means of the mobile device, signal components due to incident ionizing radiation are separated from the sensor noise. With radioactive sources present significant increases in detected pixels can be seen. Furthermore, the cell phone application can make a preliminary estimate on the collected dose of an individual and the associated health risks.

Development of a Real-Time Pulse Processing Algorithm for TES-Based X-Ray Microcalorimeters

NASA Technical Reports Server (NTRS)

Tan, Hui; Hennig, Wolfgang; Warburton, William K.; Doriese, W. Bertrand; Kilbourne, Caroline A.

2011-01-01

We report here a real-time pulse processing algorithm for superconducting transition-edge sensor (TES) based x-ray microcalorimeters. TES-based. microca1orimeters offer ultra-high energy resolutions, but the small volume of each pixel requires that large arrays of identical microcalorimeter pixe1s be built to achieve sufficient detection efficiency. That in turn requires as much pulse processing as possible must be performed at the front end of readout electronics to avoid transferring large amounts of data to a host computer for post-processing. Therefore, a real-time pulse processing algorithm that not only can be implemented in the readout electronics but also achieve satisfactory energy resolutions is desired. We have developed an algorithm that can be easily implemented. in hardware. We then tested the algorithm offline using several data sets acquired with an 8 x 8 Goddard TES x-ray calorimeter array and 2x16 NIST time-division SQUID multiplexer. We obtained an average energy resolution of close to 3.0 eV at 6 keV for the multiplexed pixels while preserving over 99% of the events in the data sets.

Evaluation of Matrix9 silicon photomultiplier array for small-animal PET.

PubMed

Du, Junwei; Schmall, Jeffrey P; Yang, Yongfeng; Di, Kun; Roncali, Emilie; Mitchell, Gregory S; Buckley, Steve; Jackson, Carl; Cherry, Simon R

2015-02-01

The MatrixSL-9-30035-OEM (Matrix9) from SensL is a large-area silicon photomultiplier (SiPM) photodetector module consisting of a 3 × 3 array of 4 × 4 element SiPM arrays (total of 144 SiPM pixels) and incorporates SensL's front-end electronics board and coincidence board. Each SiPM pixel measures 3.16 × 3.16 mm(2) and the total size of the detector head is 47.8 × 46.3 mm(2). Using 8 × 8 polished LSO/LYSO arrays (pitch 1.5 mm) the performance of this detector system (SiPM array and readout electronics) was evaluated with a view for its eventual use in small-animal positron emission tomography (PET). Measurements of noise, signal, signal-to-noise ratio, energy resolution, flood histogram quality, timing resolution, and array trigger error were obtained at different bias voltages (28.0-32.5 V in 0.5 V intervals) and at different temperatures (5 °C-25 °C in 5 °C degree steps) to find the optimal operating conditions. The best measured signal-to-noise ratio and flood histogram quality for 511 keV gamma photons were obtained at a bias voltage of 30.0 V and a temperature of 5 °C. The energy resolution and timing resolution under these conditions were 14.2% ± 0.1% and 4.2 ± 0.1 ns, respectively. The flood histograms show that all the crystals in the 1.5 mm pitch LSO array can be clearly identified and that smaller crystal pitches can also be resolved. Flood histogram quality was also calculated using different center of gravity based positioning algorithms. Improved and more robust results were achieved using the local 9 pixels for positioning along with an energy offset calibration. To evaluate the front-end detector readout, and multiplexing efficiency, an array trigger error metric is introduced and measured at different lower energy thresholds. Using a lower energy threshold greater than 150 keV effectively eliminates any mispositioning between SiPM arrays. In summary, the Matrix9 detector system can resolve high-resolution scintillator arrays common in small-animal PET with adequate energy resolution and timing resolution over a large detector area. The modular design of the Matrix9 detector allows it to be used as a building block for simple, low channel-count, yet high performance, small animal PET or PET/MRI systems.

Evaluation of Matrix9 silicon photomultiplier array for small-animal PET

PubMed Central

Du, Junwei; Schmall, Jeffrey P.; Yang, Yongfeng; Di, Kun; Roncali, Emilie; Mitchell, Gregory S.; Buckley, Steve; Jackson, Carl; Cherry, Simon R.

2015-01-01

Purpose: The MatrixSL-9-30035-OEM (Matrix9) from SensL is a large-area silicon photomultiplier (SiPM) photodetector module consisting of a 3 × 3 array of 4 × 4 element SiPM arrays (total of 144 SiPM pixels) and incorporates SensL’s front-end electronics board and coincidence board. Each SiPM pixel measures 3.16 × 3.16 mm2 and the total size of the detector head is 47.8 × 46.3 mm2. Using 8 × 8 polished LSO/LYSO arrays (pitch 1.5 mm) the performance of this detector system (SiPM array and readout electronics) was evaluated with a view for its eventual use in small-animal positron emission tomography (PET). Methods: Measurements of noise, signal, signal-to-noise ratio, energy resolution, flood histogram quality, timing resolution, and array trigger error were obtained at different bias voltages (28.0–32.5 V in 0.5 V intervals) and at different temperatures (5 °C–25 °C in 5 °C degree steps) to find the optimal operating conditions. Results: The best measured signal-to-noise ratio and flood histogram quality for 511 keV gamma photons were obtained at a bias voltage of 30.0 V and a temperature of 5 °C. The energy resolution and timing resolution under these conditions were 14.2% ± 0.1% and 4.2 ± 0.1 ns, respectively. The flood histograms show that all the crystals in the 1.5 mm pitch LSO array can be clearly identified and that smaller crystal pitches can also be resolved. Flood histogram quality was also calculated using different center of gravity based positioning algorithms. Improved and more robust results were achieved using the local 9 pixels for positioning along with an energy offset calibration. To evaluate the front-end detector readout, and multiplexing efficiency, an array trigger error metric is introduced and measured at different lower energy thresholds. Using a lower energy threshold greater than 150 keV effectively eliminates any mispositioning between SiPM arrays. Conclusions: In summary, the Matrix9 detector system can resolve high-resolution scintillator arrays common in small-animal PET with adequate energy resolution and timing resolution over a large detector area. The modular design of the Matrix9 detector allows it to be used as a building block for simple, low channel-count, yet high performance, small animal PET or PET/MRI systems. PMID:25652479

Evaluation of Matrix9 silicon photomultiplier array for small-animal PET

DOE Office of Scientific and Technical Information (OSTI.GOV)

Du, Junwei, E-mail: jwdu@ucdavis.edu; Schmall, Jeffrey P.; Yang, Yongfeng

Purpose: The MatrixSL-9-30035-OEM (Matrix9) from SensL is a large-area silicon photomultiplier (SiPM) photodetector module consisting of a 3 × 3 array of 4 × 4 element SiPM arrays (total of 144 SiPM pixels) and incorporates SensL’s front-end electronics board and coincidence board. Each SiPM pixel measures 3.16 × 3.16 mm{sup 2} and the total size of the detector head is 47.8 × 46.3 mm{sup 2}. Using 8 × 8 polished LSO/LYSO arrays (pitch 1.5 mm) the performance of this detector system (SiPM array and readout electronics) was evaluated with a view for its eventual use in small-animal positron emission tomographymore » (PET). Methods: Measurements of noise, signal, signal-to-noise ratio, energy resolution, flood histogram quality, timing resolution, and array trigger error were obtained at different bias voltages (28.0–32.5 V in 0.5 V intervals) and at different temperatures (5 °C–25 °C in 5 °C degree steps) to find the optimal operating conditions. Results: The best measured signal-to-noise ratio and flood histogram quality for 511 keV gamma photons were obtained at a bias voltage of 30.0 V and a temperature of 5 °C. The energy resolution and timing resolution under these conditions were 14.2% ± 0.1% and 4.2 ± 0.1 ns, respectively. The flood histograms show that all the crystals in the 1.5 mm pitch LSO array can be clearly identified and that smaller crystal pitches can also be resolved. Flood histogram quality was also calculated using different center of gravity based positioning algorithms. Improved and more robust results were achieved using the local 9 pixels for positioning along with an energy offset calibration. To evaluate the front-end detector readout, and multiplexing efficiency, an array trigger error metric is introduced and measured at different lower energy thresholds. Using a lower energy threshold greater than 150 keV effectively eliminates any mispositioning between SiPM arrays. Conclusions: In summary, the Matrix9 detector system can resolve high-resolution scintillator arrays common in small-animal PET with adequate energy resolution and timing resolution over a large detector area. The modular design of the Matrix9 detector allows it to be used as a building block for simple, low channel-count, yet high performance, small animal PET or PET/MRI systems.« less

Self-adjusting threshold mechanism for pixel detectors

NASA Astrophysics Data System (ADS)

Heim, Timon; Garcia-Sciveres, Maurice

2017-09-01

Readout chips of hybrid pixel detectors use a low power amplifier and threshold discrimination to process charge deposited in semiconductor sensors. Due to transistor mismatch each pixel circuit needs to be calibrated individually to achieve response uniformity. Traditionally this is addressed by programmable threshold trimming in each pixel, but requires robustness against radiation effects, temperature, and time. In this paper a self-adjusting threshold mechanism is presented, which corrects the threshold for both spatial inequality and time variation and maintains a constant response. It exploits the electrical noise as relative measure for the threshold and automatically adjust the threshold of each pixel to always achieve a uniform frequency of noise hits. A digital implementation of the method in the form of an up/down counter and combinatorial logic filter is presented. The behavior of this circuit has been simulated to evaluate its performance and compare it to traditional calibration results. The simulation results show that this mechanism can perform equally well, but eliminates instability over time and is immune to single event upsets.

CMOS image sensor with lateral electric field modulation pixels for fluorescence lifetime imaging with sub-nanosecond time response

NASA Astrophysics Data System (ADS)

Li, Zhuo; Seo, Min-Woong; Kagawa, Keiichiro; Yasutomi, Keita; Kawahito, Shoji

2016-04-01

This paper presents the design and implementation of a time-resolved CMOS image sensor with a high-speed lateral electric field modulation (LEFM) gating structure for time domain fluorescence lifetime measurement. Time-windowed signal charge can be transferred from a pinned photodiode (PPD) to a pinned storage diode (PSD) by turning on a pair of transfer gates, which are situated beside the channel. Unwanted signal charge can be drained from the PPD to the drain by turning on another pair of gates. The pixel array contains 512 (V) × 310 (H) pixels with 5.6 × 5.6 µm2 pixel size. The imager chip was fabricated using 0.11 µm CMOS image sensor process technology. The prototype sensor has a time response of 150 ps at 374 nm. The fill factor of the pixels is 5.6%. The usefulness of the prototype sensor is demonstrated for fluorescence lifetime imaging through simulation and measurement results.

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity

PubMed Central

Zhang, Fan; Niu, Hanben

2016-01-01

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 107 when illuminated by a 405-nm diode laser and 1/1.4 × 104 when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e− rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena. PMID:27367699

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity.

PubMed

Zhang, Fan; Niu, Hanben

2016-06-29

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 10⁷ when illuminated by a 405-nm diode laser and 1/1.4 × 10⁴ when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e(-) rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena.

Performance verification and system integration tests of the pulse shape processor for the soft x-ray spectrometer onboard ASTRO-H

NASA Astrophysics Data System (ADS)

Takeda, Sawako; Tashiro, Makoto S.; Ishisaki, Yoshitaka; Tsujimoto, Masahiro; Seta, Hiromi; Shimoda, Yuya; Yamaguchi, Sunao; Uehara, Sho; Terada, Yukikatsu; Fujimoto, Ryuichi; Mitsuda, Kazuhisa

2014-07-01

The soft X-ray spectrometer (SXS) aboard ASTRO-H is equipped with dedicated digital signal processing units called pulse shape processors (PSPs). The X-ray microcalorimeter system SXS has 36 sensor pixels, which are operated at 50 mK to measure heat input of X-ray photons and realize an energy resolution of 7 eV FWHM in the range 0.3-12.0 keV. Front-end signal processing electronics are used to filter and amplify the electrical pulse output from the sensor and for analog-to-digital conversion. The digitized pulses from the 36 pixels are multiplexed and are sent to the PSP over low-voltage differential signaling lines. Each of two identical PSP units consists of an FPGA board, which assists the hardware logic, and two CPU boards, which assist the onboard software. The FPGA board triggers at every pixel event and stores the triggering information as a pulse waveform in the installed memory. The CPU boards read the event data to evaluate pulse heights by an optimal filtering algorithm. The evaluated X-ray photon data (including the pixel ID, energy, and arrival time information) are transferred to the satellite data recorder along with event quality information. The PSP units have been developed and tested with the engineering model (EM) and the flight model. Utilizing the EM PSP, we successfully verified the entire hardware system and the basic software design of the PSPs, including their communication capability and signal processing performance. In this paper, we show the key metrics of the EM test, such as accuracy and synchronicity of sampling clocks, event grading capability, and resultant energy resolution.

A MAPS Based Micro-Vertex Detector for the STAR Experiment

DOE PAGES

Schambach, Joachim; Anderssen, Eric; Contin, Giacomo; ...

2015-06-18

For the 2014 heavy ion run of RHIC a new micro-vertex detector called the Heavy Flavor Tracker (HFT) was installed in the STAR experiment. The HFT consists of three detector subsystems with various silicon technologies arranged in 4 approximately concentric cylinders close to the STAR interaction point designed to improve the STAR detector’s vertex resolution and extend its measurement capabilities in the heavy flavor domain. The two innermost HFT layers are placed at radii of 2.8 cm and 8 cm from the beam line. These layers are constructed with 400 high resolution sensors based on CMOS Monolithic Active Pixel Sensormore » (MAPS) technology arranged in 10-sensor ladders mounted on 10 thin carbon fiber sectors to cover a total silicon area of 0.16 m 2. Each sensor of this PiXeL (“PXL”) sub-detector combines a pixel array of 928 rows and 960 columns with a 20.7 μm pixel pitch together with front-end electronics and zero-suppression circuitry in one silicon die providing a sensitive area of ~3.8 cm 2. This sensor architecture features 185.6 μs readout time and 170 mW/cm 2 power dissipation. This low power dissipation allows the PXL detector to be air-cooled, and with the sensors thinned down to 50 μm results in a global material budget of only 0.4% radiation length per layer. A novel mechanical approach to detector insertion allows us to effectively install and integrate the PXL sub-detector within a 12 hour period during an on-going multi-month data taking period. The detector requirements, architecture and design, as well as the performance after installation, are presented in this paper.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schambach, Joachim; Anderssen, Eric; Contin, Giacomo

For the 2014 heavy ion run of RHIC a new micro-vertex detector called the Heavy Flavor Tracker (HFT) was installed in the STAR experiment. The HFT consists of three detector subsystems with various silicon technologies arranged in 4 approximately concentric cylinders close to the STAR interaction point designed to improve the STAR detector’s vertex resolution and extend its measurement capabilities in the heavy flavor domain. The two innermost HFT layers are placed at radii of 2.8 cm and 8 cm from the beam line. These layers are constructed with 400 high resolution sensors based on CMOS Monolithic Active Pixel Sensormore » (MAPS) technology arranged in 10-sensor ladders mounted on 10 thin carbon fiber sectors to cover a total silicon area of 0.16 m 2. Each sensor of this PiXeL (“PXL”) sub-detector combines a pixel array of 928 rows and 960 columns with a 20.7 μm pixel pitch together with front-end electronics and zero-suppression circuitry in one silicon die providing a sensitive area of ~3.8 cm 2. This sensor architecture features 185.6 μs readout time and 170 mW/cm 2 power dissipation. This low power dissipation allows the PXL detector to be air-cooled, and with the sensors thinned down to 50 μm results in a global material budget of only 0.4% radiation length per layer. A novel mechanical approach to detector insertion allows us to effectively install and integrate the PXL sub-detector within a 12 hour period during an on-going multi-month data taking period. The detector requirements, architecture and design, as well as the performance after installation, are presented in this paper.« less

Proton irradiation of the CIS115 for the JUICE mission

NASA Astrophysics Data System (ADS)

Soman, M. R.; Allanwood, E. A. H.; Holland, A. D.; Winstone, G. P.; Gow, J. P. D.; Stefanov, K.; Leese, M.

2015-09-01

The CIS115 is one of the latest CMOS Imaging Sensors designed by e2v technologies, with 1504x2000 pixels on a 7 μm pitch. Each pixel in the array is a pinned photodiode with a 4T architecture, achieving an average dark current of 22 electrons pixel-1 s-1 at 21°C measured in a front-faced device. The sensor aims for high optical sensitivity by utilising e2v's back-thinning and processing capabilities, providing a sensitive silicon thickness approximately 9 μm to 12 μm thick with a tuned anti-reflective coating. The sensor operates in a rolling shutter mode incorporating reset level subtraction resulting in a mean pixel readout noise of 4.25 electrons rms. The full well has been measured to be 34000 electrons in a previous study, resulting in a dynamic range of up to 8000. These performance characteristics have led to the CIS115 being chosen for JANUS, the high-resolution and wide-angle optical camera on the JUpiter ICy moon Explorer (JUICE). The three year science phase of JUICE is in the harsh radiation environment of the Jovian magnetosphere, primarily studying Jupiter and its icy moons. Analysis of the expected radiation environment and shielding levels from the spacecraft and instrument design predict the End Of Life (EOL) displacement and ionising damage for the CIS115 to be equivalent to 1010 10 MeV protons cm-2 and 100 krad(Si) respectively. Dark current and image lag characterisation results following initial proton irradiations are presented, detailing the initial phase of space qualification of the CIS115. Results are compared to the pre-irradiation performance and the instrument specifications and further qualification plans are outlined.

Development of an imaging method for quantifying a large digital PCR droplet

NASA Astrophysics Data System (ADS)

Huang, Jen-Yu; Lee, Shu-Sheng; Hsu, Yu-Hsiang

2017-02-01

Portable devices have been recognized as the future linkage between end-users and lab-on-a-chip devices. It has a user friendly interface and provides apps to interface headphones, cameras, and communication duct, etc. In particular, the digital resolution of cameras installed in smartphones or pads already has a high imaging resolution with a high number of pixels. This unique feature has triggered researches to integrate optical fixtures with smartphone to provide microscopic imaging capabilities. In this paper, we report our study on developing a portable diagnostic tool based on the imaging system of a smartphone and a digital PCR biochip. A computational algorithm is developed to processing optical images taken from a digital PCR biochip with a smartphone in a black box. Each reaction droplet is recorded in pixels and is analyzed in a sRGB (red, green, and blue) color space. Multistep filtering algorithm and auto-threshold algorithm are adopted to minimize background noise contributed from ccd cameras and rule out false positive droplets, respectively. Finally, a size-filtering method is applied to identify the number of positive droplets to quantify target's concentration. Statistical analysis is then performed for diagnostic purpose. This process can be integrated in an app and can provide a user friendly interface without professional training.

An Algorithm of an X-ray Hit Allocation to a Single Pixel in a Cluster and Its Test-Circuit Implementation

DOE PAGES

Deptuch, Grzegorz W.; Fahim, Farah; Grybos, Pawel; ...

2017-06-28

An on-chip implementable algorithm for allocation of an X-ray photon imprint, called a hit, to a single pixel in the presence of charge sharing in a highly segmented pixel detector is described. Its proof-of-principle implementation is also given supported by the results of tests using a highly collimated X-ray photon beam from a synchrotron source. The algorithm handles asynchronous arrivals of X-ray photons. Activation of groups of pixels, comparisons of peak amplitudes of pulses within an active neighborhood and finally latching of the results of these comparisons constitute the three procedural steps of the algorithm. A grouping of pixels tomore » one virtual pixel, that recovers composite signals and event driven strobes, to control comparisons of fractional signals between neighboring pixels are the actuators of the algorithm. The circuitry necessary to implement the algorithm requires an extensive inter-pixel connection grid of analog and digital signals, that are exchanged between pixels. A test-circuit implementation of the algorithm was achieved with a small array of 32 × 32 pixels and the device was exposed to an 8 keV highly collimated to a diameter of 3-μm X-ray beam. Furthermore, the results of these tests are given in this paper assessing physical implementation of the algorithm.« less

Application of the Medipix2 technology to space radiation dosimetry and hadron therapy beam monitoring

NASA Astrophysics Data System (ADS)

Pinsky, Lawrence; Stoffle, Nicholas; Jakubek, Jan; Pospisil, Stanislav; Leroy, Claude; Gutierrez, Andrea; Kitamura, Hisashi; Yasuda, Nakahiro; Uchihori, Yulio

2011-02-01

The Medipix2 Collaboration, based at CERN, has developed the TimePix version of the Medipix pixel readout chip, which has the ability to provide either an ADC or TDC capability separately in each of its 256×256 pixels. When coupled to a Si detector layer, the device is an excellent candidate for application as an active dosimeter for use in space radiation environments. In order to facilitate such a development, data have been taken with heavy ions at the HIMAC facility in Chiba, Japan. In particular, the problem of determining the resolution of such a detector system with respect to heavy ions of differing charges and energies, but with similar d E/d x values has been explored for several ions. The ultimate problem is to parse the information in the pixel "footprint" images from the drift of the charge cloud produced in the detector layer. In addition, with the use of convertor materials, the detector can be used as a neutron detector, and it has been used both as a charged particle and neutron detector to evaluate the detailed properties of the radiation fields produced by hadron therapy beams. New versions of the basic chip design are ongoing.

Characterisation of GaAs:Cr pixel sensors coupled to Timepix chips in view of synchrotron applications

NASA Astrophysics Data System (ADS)

Ponchut, C.; Cotte, M.; Lozinskaya, A.; Zarubin, A.; Tolbanov, O.; Tyazhev, A.

2017-12-01

In order to meet the needs of some ESRF beamlines for highly efficient 2D X-ray detectors in the 20-50 keV range, GaAs:Cr pixel sensors coupled to TIMEPIX readout chips were implemented into a MAXIPIX detector. Use of GaAs:Cr sensor material is intended to overcome the limitations of Si (low absorption) and of CdTe (fluorescence) in this energy range The GaAs:Cr sensor assemblies were characterised with both laboratory X-ray sources and monochromatic synchrotron X-ray beams. The sensor response as a function of bias voltage was compared to a theoretical model, leading to an estimation of the μτ product of electrons in GaAs:Cr sensor material of 1.6×10-4 cm2/V. The spatial homogeneity of X-ray images obtained with the sensors was measured in different irradiation conditions, showing a particular sensitivity to small variations in the incident beam spectrum. 2D-resolved elemental mapping of the sensor surface was carried out to investigate a possible relation between the noise pattern observed in X-ray images and local fluctuations in chemical composition. A scanning of the sensor response at subpixel scale revealed that these irregularities can be correlated with a distortion of the effective pixel shapes.

A Wearable Healthcare System With a 13.7 μA Noise Tolerant ECG Processor.

PubMed

Izumi, Shintaro; Yamashita, Ken; Nakano, Masanao; Kawaguchi, Hiroshi; Kimura, Hiromitsu; Marumoto, Kyoji; Fuchikami, Takaaki; Fujimori, Yoshikazu; Nakajima, Hiroshi; Shiga, Toshikazu; Yoshimoto, Masahiko

2015-10-01

To prevent lifestyle diseases, wearable bio-signal monitoring systems for daily life monitoring have attracted attention. Wearable systems have strict size and weight constraints, which impose significant limitations of the battery capacity and the signal-to-noise ratio of bio-signals. This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application.

Reconfigurable Multiparameter Biosignal Acquisition SoC for Low Power Wearable Platform

PubMed Central

Kim, Jongpal; Ko, Hyoungho

2016-01-01

A low power and low noise reconfigurable analog front-end (AFE) system on a chip (SoC) for biosignal acquisition is presented. The presented AFE can be reconfigured for use in electropotential, bioimpedance, electrochemical, and photoelectrical modes. The advanced healthcare services based on multiparameter physiological biosignals can be easily implemented with these multimodal and highly reconfigurable features of the proposed system. The reconfigurable gain and input referred noise of the core instrumentation amplifier block are 25 dB to 52 dB, and 1 μVRMS, respectively. The power consumption of the analog blocks in one readout channel is less than 52 μW. The reconfigurable capability among various modes of applications including electrocardiogram, blood glucose concentration, respiration, and photoplethysmography are shown experimentally. PMID:27898004

CMOS minimal array

NASA Astrophysics Data System (ADS)

Janesick, James; Cheng, John; Bishop, Jeanne; Andrews, James T.; Tower, John; Walker, Jeff; Grygon, Mark; Elliot, Tom

2006-08-01

A high performance prototype CMOS imager is introduced. Test data is reviewed for different array formats that utilize 3T photo diode, 5T pinned photo diode and 6T photo gate CMOS pixel architectures. The imager allows several readout modes including progressive scan, snap and windowed operation. The new imager is built on different silicon substrates including very high resistivity epitaxial wafers for deep depletion operation. Data products contained in this paper focus on sensor's read noise, charge capacity, charge transfer efficiency, thermal dark current, RTS dark spikes, QE, pixel cross- talk and on-chip analog circuitry performance.

Imaging visible light with Medipix2.

PubMed

Mac Raighne, Aaron; Brownlee, Colin; Gebert, Ulrike; Maneuski, Dzmitry; Milnes, James; O'Shea, Val; Rügheimer, Tilman K

2010-11-01

A need exists for high-speed single-photon counting optical imaging detectors. Single-photon counting high-speed detection of x rays is possible by using Medipix2 with pixelated silicon photodiodes. In this article, we report on a device that exploits the Medipix2 chip for optical imaging. The fabricated device is capable of imaging at >3000 frames/s over a 256×256 pixel matrix. The imaging performance of the detector device via the modulation transfer function is measured, and the presence of ion feedback and its degradation of the imaging properties are discussed.

The Design, Fabrication and Characterization of a Transparent Atom Chip

PubMed Central

Chuang, Ho-Chiao; Huang, Chia-Shiuan; Chen, Hung-Pin; Huang, Chi-Sheng; Lin, Yu-Hsin

2014-01-01

This study describes the design and fabrication of transparent atom chips for atomic physics experiments. A fabrication process was developed to define the wire patterns on a transparent glass substrate to create the desired magnetic field for atom trapping experiments. An area on the chip was reserved for the optical access, so that the laser light can penetrate directly through the glass substrate for the laser cooling process. Furthermore, since the thermal conductivity of the glass substrate is poorer than other common materials for atom chip substrate, for example silicon, silicon carbide, aluminum nitride. Thus, heat dissipation copper blocks are designed on the front and back of the glass substrate to improve the electrical current conduction. The testing results showed that a maximum burnout current of 2 A was measured from the wire pattern (with a width of 100 μm and a height of 20 μm) without any heat dissipation design and it can increase to 2.5 A with a heat dissipation design on the front side of the atom chips. Therefore, heat dissipation copper blocks were designed and fabricated on the back of the glass substrate just under the wire patterns which increases the maximum burnout current to 4.5 A. Moreover, a maximum burnout current of 6 A was achieved when the entire backside glass substrate was recessed and a thicker copper block was electroplated, which meets most requirements of atomic physics experiments. PMID:24922456

A CMOS One-chip Wireless Camera with Digital Image Transmission Function for Capsule Endoscopes

NASA Astrophysics Data System (ADS)

Itoh, Shinya; Kawahito, Shoji; Terakawa, Susumu

This paper presents the design and implementation of a one-chip camera device for capsule endoscopes. This experimental chip integrates functional circuits required for capsule endoscopes and digital image transmission function. The integrated functional blocks include an image array, a timing generator, a clock generator, a voltage regulator, a 10b cyclic A/D converter, and a BPSK modulator. It can be operated autonomously with 3 pins (VDD, GND, and DATAOUT). A prototype image sensor chip which has 320x240 effective pixels was fabricated using 0.25μm CMOS image sensor process and the autonomous imaging was demonstrated. The chip size is 4.84mmx4.34mm. With a 2.0 V power supply, the analog part consumes 950μW and the total power consumption at 2 frames per second (fps) is 2.6mW. Error-free image transmission over a distance of 48cm at 2.5Mbps corresponding to 2fps has been succeeded with inductive coupling.

High-Speed Binary-Output Image Sensor

NASA Technical Reports Server (NTRS)

Fossum, Eric; Panicacci, Roger A.; Kemeny, Sabrina E.; Jones, Peter D.

1996-01-01

Photodetector outputs digitized by circuitry on same integrated-circuit chip. Developmental special-purpose binary-output image sensor designed to capture up to 1,000 images per second, with resolution greater than 10 to the 6th power pixels per image. Lower-resolution but higher-frame-rate prototype of sensor contains 128 x 128 array of photodiodes on complementary metal oxide/semiconductor (CMOS) integrated-circuit chip. In application for which it is being developed, sensor used to examine helicopter oil to determine whether amount of metal and sand in oil sufficient to warrant replacement.

Orientation-selective aVLSI spiking neurons.

PubMed

Liu, S C; Kramer, J; Indiveri, G; Delbrück, T; Burg, T; Douglas, R

2001-01-01

We describe a programmable multi-chip VLSI neuronal system that can be used for exploring spike-based information processing models. The system consists of a silicon retina, a PIC microcontroller, and a transceiver chip whose integrate-and-fire neurons are connected in a soft winner-take-all architecture. The circuit on this multi-neuron chip approximates a cortical microcircuit. The neurons can be configured for different computational properties by the virtual connections of a selected set of pixels on the silicon retina. The virtual wiring between the different chips is effected by an event-driven communication protocol that uses asynchronous digital pulses, similar to spikes in a neuronal system. We used the multi-chip spike-based system to synthesize orientation-tuned neurons using both a feedforward model and a feedback model. The performance of our analog hardware spiking model matched the experimental observations and digital simulations of continuous-valued neurons. The multi-chip VLSI system has advantages over computer neuronal models in that it is real-time, and the computational time does not scale with the size of the neuronal network.

Optimization of CMOS image sensor utilizing variable temporal multisampling partial transfer technique to achieve full-frame high dynamic range with superior low light and stop motion capability

NASA Astrophysics Data System (ADS)

Kabir, Salman; Smith, Craig; Armstrong, Frank; Barnard, Gerrit; Schneider, Alex; Guidash, Michael; Vogelsang, Thomas; Endsley, Jay

2018-03-01

Differential binary pixel technology is a threshold-based timing, readout, and image reconstruction method that utilizes the subframe partial charge transfer technique in a standard four-transistor (4T) pixel CMOS image sensor to achieve a high dynamic range video with stop motion. This technology improves low light signal-to-noise ratio (SNR) by up to 21 dB. The method is verified in silicon using a Taiwan Semiconductor Manufacturing Company's 65 nm 1.1 μm pixel technology 1 megapixel test chip array and is compared with a traditional 4 × oversampling technique using full charge transfer to show low light SNR superiority of the presented technology.

Photon counting readout pixel array in 0.18-μm CMOS technology for on-line gamma-ray imaging of 103palladium seeds for permanent breast seed implant (PBSI) brachytherapy

NASA Astrophysics Data System (ADS)

Goldan, A. H.; Karim, K. S.; Reznik, A.; Caldwell, C. B.; Rowlands, J. A.

2008-03-01

Permanent breast seed implant (PBSI) brachytherapy technique was recently introduced as an alternative to high dose rate (HDR) brachytherapy and involves the permanent implantation of radioactive 103Palladium seeds into the surgical cavity of the breast for cancer treatment. To enable accurate seed implantation, this research introduces a gamma camera based on a hybrid amorphous selenium detector and CMOS readout pixel architecture for real-time imaging of 103Palladium seeds during the PBSI procedure. A prototype chip was designed and fabricated in 0.18-μm n-well CMOS process. We present the experimental results obtained from this integrated photon counting readout pixel.

Active Pixel Sensors: Are CCD's Dinosaurs?

NASA Technical Reports Server (NTRS)

Fossum, Eric R.

1993-01-01

Charge-coupled devices (CCD's) are presently the technology of choice for most imaging applications. In the 23 years since their invention in 1970, they have evolved to a sophisticated level of performance. However, as with all technologies, we can be certain that they will be supplanted someday. In this paper, the Active Pixel Sensor (APS) technology is explored as a possible successor to the CCD. An active pixel is defined as a detector array technology that has at least one active transistor within the pixel unit cell. The APS eliminates the need for nearly perfect charge transfer -- the Achilles' heel of CCDs. This perfect charge transfer makes CCD's radiation 'soft,' difficult to use under low light conditions, difficult to manufacture in large array sizes, difficult to integrate with on-chip electronics, difficult to use at low temperatures, difficult to use at high frame rates, and difficult to manufacture in non-silicon materials that extend wavelength response.

A review of advances in pixel detectors for experiments with high rate and radiation

NASA Astrophysics Data System (ADS)

Garcia-Sciveres, Maurice; Wermes, Norbert

2018-06-01

The large Hadron collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the high luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.

A 10MHz Fiber-Coupled Photodiode Imaging Array for Plasma Diagnostics

NASA Astrophysics Data System (ADS)

Brockington, Samuel; Case, Andrew; Witherspoon, F. Douglas

2013-10-01

HyperV Technologies has been developing an imaging diagnostic comprised of arrays of fast, low-cost, long-record-length, fiber-optically-coupled photodiode channels to investigate plasma dynamics and other fast, bright events. By coupling an imaging fiber bundle to a bank of amplified photodiode channels, imagers and streak imagers of 100 to 10,000 pixels can be constructed. By interfacing analog photodiode systems directly to commercial analog to digital convertors and modern memory chips, a prototype pixel with an extremely deep record length (128 k points at 40 Msamples/s) has been achieved for a 10 bit resolution system with signal bandwidths of at least 10 MHz. Progress on a prototype 100 Pixel streak camera employing this technique is discussed along with preliminary experimental results and plans for a 10,000 pixel imager. Work supported by USDOE Phase 1 SBIR Grant DE-SC0009492.