Messiah College Biodiesel Fuel Generation Project Final Technical Report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zummo, Michael M; Munson, J; Derr, A

Many obvious and significant concerns arise when considering the concept of small-scale biodiesel production. Does the fuel produced meet the stringent requirements set by the commercial biodiesel industry? Is the process safe? How are small-scale producers collecting and transporting waste vegetable oil? How is waste from the biodiesel production process handled by small-scale producers? These concerns and many others were the focus of the research preformed in the Messiah College Biodiesel Fuel Generation project over the last three years. This project was a unique research program in which undergraduate engineering students at Messiah College set out to research the feasibilitymore » of small-biodiesel production for application on a campus of approximately 3000 students. This Department of Energy (DOE) funded research program developed out of almost a decade of small-scale biodiesel research and development work performed by students at Messiah College. Over the course of the last three years the research team focused on four key areas related to small-scale biodiesel production: Quality Testing and Assurance, Process and Processor Research, Process and Processor Development, and Community Education. The objectives for the Messiah College Biodiesel Fuel Generation Project included the following: 1. Preparing a laboratory facility for the development and optimization of processors and processes, ASTM quality assurance, and performance testing of biodiesel fuels. 2. Developing scalable processor and process designs suitable for ASTM certifiable small-scale biodiesel production, with the goals of cost reduction and increased quality. 3. Conduct research into biodiesel process improvement and cost optimization using various biodiesel feedstocks and production ingredients.« less

A diesel fuel processor for fuel-cell-based auxiliary power unit applications

NASA Astrophysics Data System (ADS)

Samsun, Remzi Can; Krekel, Daniel; Pasel, Joachim; Prawitz, Matthias; Peters, Ralf; Stolten, Detlef

2017-07-01

Producing a hydrogen-rich gas from diesel fuel enables the efficient generation of electricity in a fuel-cell-based auxiliary power unit. In recent years, significant progress has been achieved in diesel reforming. One issue encountered is the stable operation of water-gas shift reactors with real reformates. A new fuel processor is developed using a commercial shift catalyst. The system is operated using optimized start-up and shut-down strategies. Experiments with diesel and kerosene fuels show slight performance drops in the shift reactor during continuous operation for 100 h. CO concentrations much lower than the target value are achieved during system operation in auxiliary power unit mode at partial loads of up to 60%. The regeneration leads to full recovery of the shift activity. Finally, a new operation strategy is developed whereby the gas hourly space velocity of the shift stages is re-designed. This strategy is validated using different diesel and kerosene fuels, showing a maximum CO concentration of 1.5% at the fuel processor outlet under extreme conditions, which can be tolerated by a high-temperature PEFC. The proposed operation strategy solves the issue of strong performance drop in the shift reactor and makes this technology available for reducing emissions in the transportation sector.

Methanol tailgas combustor control method

DOEpatents

Hart-Predmore, David J.; Pettit, William H.

2002-01-01

A method for controlling the power and temperature and fuel source of a combustor in a fuel cell apparatus to supply heat to a fuel processor where the combustor has dual fuel inlet streams including a first fuel stream, and a second fuel stream of anode effluent from the fuel cell and reformate from the fuel processor. In all operating modes, an enthalpy balance is determined by regulating the amount of the first and/or second fuel streams and the quantity of the first air flow stream to support fuel processor power requirements.

Method for operating a combustor in a fuel cell system

DOEpatents

Chalfant, Robert W.; Clingerman, Bruce J.

2002-01-01

A method of operating a combustor to heat a fuel processor in a fuel cell system, in which the fuel processor generates a hydrogen-rich stream a portion of which is consumed in a fuel cell stack and a portion of which is discharged from the fuel cell stack and supplied to the combustor, and wherein first and second streams are supplied to the combustor, the first stream being a hydrocarbon fuel stream and the second stream consisting of said hydrogen-rich stream, the method comprising the steps of monitoring the temperature of the fuel processor; regulating the quantity of the first stream to the combustor according to the temperature of the fuel processor; and comparing said quantity of said first stream to a predetermined value or range of predetermined values.

35-We polymer electrolyte membrane fuel cell system for notebook computer using a compact fuel processor

NASA Astrophysics Data System (ADS)

Son, In-Hyuk; Shin, Woo-Cheol; Lee, Yong-Kul; Lee, Sung-Chul; Ahn, Jin-Gu; Han, Sang-Il; kweon, Ho-Jin; Kim, Ju-Yong; Kim, Moon-Chan; Park, Jun-Yong

A polymer electrolyte membrane fuel cell (PEMFC) system is developed to power a notebook computer. The system consists of a compact methanol-reforming system with a CO preferential oxidation unit, a 16-cell PEMFC stack, and a control unit for the management of the system with a d.c.-d.c. converter. The compact fuel-processor system (260 cm 3) generates about 1.2 L min -1 of reformate, which corresponds to 35 We, with a low CO concentration (<30 ppm, typically 0 ppm), and is thus proven to be capable of being targetted at notebook computers.

Methanol Fuel Cell

NASA Technical Reports Server (NTRS)

Voecks, G. E.

1985-01-01

In proposed fuel-cell system, methanol converted to hydrogen in two places. External fuel processor converts only part of methanol. Remaining methanol converted in fuel cell itself, in reaction at anode. As result, size of fuel processor reduced, system efficiency increased, and cost lowered.

Miniature Fuel Processors for Portable Fuel Cell Power Supplies

DOE Office of Scientific and Technical Information (OSTI.GOV)

Holladay, Jamie D.; Jones, Evan O.; Palo, Daniel R.

2003-06-02

Miniature and micro-scale fuel processors are discussed. The enabling technologies for these devices are the novel catalysts and the micro-technology-based designs. The novel catalyst allows for methanol reforming at high gas hourly space velocities of 50,000 hr-1 or higher, while maintaining a carbon monoxide levels at 1% or less. The micro-technology-based designs enable the devices to be extremely compact and lightweight. The miniature fuel processors can nominally provide between 25-50 watts equivalent of hydrogen which is ample for soldier or personal portable power supplies. The integrated processors have a volume less than 50 cm3, a mass less than 150 grams,more » and thermal efficiencies of up to 83%. With reasonable assumptions on fuel cell efficiencies, anode gas and water management, parasitic power loss, etc., the energy density was estimated at 1700 Whr/kg. The miniature processors have been demonstrated with a carbon monoxide clean-up method and a fuel cell stack. The micro-scale fuel processors have been designed to provide up to 0.3 watt equivalent of power with efficiencies over 20%. They have a volume of less than 0.25 cm3 and a mass of less than 1 gram.« less

Method for operating a combustor in a fuel cell system

DOEpatents

Clingerman, Bruce J.; Mowery, Kenneth D.

2002-01-01

In one aspect, the invention provides a method of operating a combustor to heat a fuel processor to a desired temperature in a fuel cell system, wherein the fuel processor generates hydrogen (H.sub.2) from a hydrocarbon for reaction within a fuel cell to generate electricity. More particularly, the invention provides a method and select system design features which cooperate to provide a start up mode of operation and a smooth transition from start-up of the combustor and fuel processor to a running mode.

Solid Oxide Fuel Cells Operating on Alternative and Renewable Fuels

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Xiaoxing; Quan, Wenying; Xiao, Jing

2014-09-30

This DOE project at the Pennsylvania State University (Penn State) initially involved Siemens Energy, Inc. to (1) develop new fuel processing approaches for using selected alternative and renewable fuels – anaerobic digester gas (ADG) and commercial diesel fuel (with 15 ppm sulfur) – in solid oxide fuel cell (SOFC) power generation systems; and (2) conduct integrated fuel processor – SOFC system tests to evaluate the performance of the fuel processors and overall systems. Siemens Energy Inc. was to provide SOFC system to Penn State for testing. The Siemens work was carried out at Siemens Energy Inc. in Pittsburgh, PA. Themore » unexpected restructuring in Siemens organization, however, led to the elimination of the Siemens Stationary Fuel Cell Division within the company. Unfortunately, this led to the Siemens subcontract with Penn State ending on September 23rd, 2010. SOFC system was never delivered to Penn State. With the assistance of NETL project manager, the Penn State team has since developed a collaborative research with Delphi as the new subcontractor and this work involved the testing of a stack of planar solid oxide fuel cells from Delphi.« less

Control apparatus and method for efficiently heating a fuel processor in a fuel cell system

DOEpatents

Doan, Tien M.; Clingerman, Bruce J.

2003-08-05

A control apparatus and method for efficiently controlling the amount of heat generated by a fuel cell processor in a fuel cell system by determining a temperature error between actual and desired fuel processor temperatures. The temperature error is converted to a combustor fuel injector command signal or a heat dump valve position command signal depending upon the type of temperature error. Logic controls are responsive to the combustor fuel injector command signals and the heat dump valve position command signal to prevent the combustor fuel injector command signal from being generated if the heat dump valve is opened or, alternately, from preventing the heat dump valve position command signal from being generated if the combustor fuel injector is opened.

The 40-kw field test power plant modification and development, phase 2

NASA Technical Reports Server (NTRS)

1980-01-01

Progression on the design and development of a 40 KW fuel cell system for on-site installation for providing both thermal and electrical power is reported. Development of the steam reformer fuel processor, power section, inverter, control system, and thermal management and water treatment systems is described.

Autothermal and partial oxidation reformer-based fuel processor, method for improving catalyst function in autothermal and partial oxidation reformer-based processors

DOEpatents

Ahmed, Shabbir; Papadias, Dionissios D.; Lee, Sheldon H. D.; Ahluwalia, Rajesh K.

2013-01-08

The invention provides a fuel processor comprising a linear flow structure having an upstream portion and a downstream portion; a first catalyst supported at the upstream portion; and a second catalyst supported at the downstream portion, wherein the first catalyst is in fluid communication with the second catalyst. Also provided is a method for reforming fuel, the method comprising contacting the fuel to an oxidation catalyst so as to partially oxidize the fuel and generate heat; warming incoming fuel with the heat while simultaneously warming a reforming catalyst with the heat; and reacting the partially oxidized fuel with steam using the reforming catalyst.

Method for fast start of a fuel processor

DOEpatents

Ahluwalia, Rajesh K [Burr Ridge, IL; Ahmed, Shabbir [Naperville, IL; Lee, Sheldon H. D. [Willowbrook, IL

2008-01-29

An improved fuel processor for fuel cells is provided whereby the startup time of the processor is less than sixty seconds and can be as low as 30 seconds, if not less. A rapid startup time is achieved by either igniting or allowing a small mixture of air and fuel to react over and warm up the catalyst of an autothermal reformer (ATR). The ATR then produces combustible gases to be subsequently oxidized on and simultaneously warm up water-gas shift zone catalysts. After normal operating temperature has been achieved, the proportion of air included with the fuel is greatly diminished.

Multi-fuel reformers for fuel cells used in transportation. Phase 1: Multi-fuel reformers

NASA Astrophysics Data System (ADS)

1994-05-01

DOE has established the goal, through the Fuel Cells in Transportation Program, of fostering the rapid development and commercialization of fuel cells as economic competitors for the internal combustion engine. Central to this goal is a safe feasible means of supplying hydrogen of the required purity to the vehicular fuel cell system. Two basic strategies are being considered: (1) on-board fuel processing whereby alternative fuels such as methanol, ethanol or natural gas stored on the vehicle undergo reformation and subsequent processing to produce hydrogen, and (2) on-board storage of pure hydrogen provided by stationary fuel processing plants. This report analyzes fuel processor technologies, types of fuel and fuel cell options for on-board reformation. As the Phase 1 of a multi-phased program to develop a prototype multi-fuel reformer system for a fuel cell powered vehicle, the objective of this program was to evaluate the feasibility of a multi-fuel reformer concept and to select a reforming technology for further development in the Phase 2 program, with the ultimate goal of integration with a DOE-designated fuel cell and vehicle configuration. The basic reformer processes examined in this study included catalytic steam reforming (SR), non-catalytic partial oxidation (POX) and catalytic partial oxidation (also known as Autothermal Reforming, or ATR). Fuels under consideration in this study included methanol, ethanol, and natural gas. A systematic evaluation of reforming technologies, fuels, and transportation fuel cell applications was conducted for the purpose of selecting a suitable multi-fuel processor for further development and demonstration in a transportation application.

A light hydrocarbon fuel processor producing high-purity hydrogen

NASA Astrophysics Data System (ADS)

Löffler, Daniel G.; Taylor, Kyle; Mason, Dylan

This paper discusses the design process and presents performance data for a dual fuel (natural gas and LPG) fuel processor for PEM fuel cells delivering between 2 and 8 kW electric power in stationary applications. The fuel processor resulted from a series of design compromises made to address different design constraints. First, the product quality was selected; then, the unit operations needed to achieve that product quality were chosen from the pool of available technologies. Next, the specific equipment needed for each unit operation was selected. Finally, the unit operations were thermally integrated to achieve high thermal efficiency. Early in the design process, it was decided that the fuel processor would deliver high-purity hydrogen. Hydrogen can be separated from other gases by pressure-driven processes based on either selective adsorption or permeation. The pressure requirement made steam reforming (SR) the preferred reforming technology because it does not require compression of combustion air; therefore, steam reforming is more efficient in a high-pressure fuel processor than alternative technologies like autothermal reforming (ATR) or partial oxidation (POX), where the combustion occurs at the pressure of the process stream. A low-temperature pre-reformer reactor is needed upstream of a steam reformer to suppress coke formation; yet, low temperatures facilitate the formation of metal sulfides that deactivate the catalyst. For this reason, a desulfurization unit is needed upstream of the pre-reformer. Hydrogen separation was implemented using a palladium alloy membrane. Packed beds were chosen for the pre-reformer and reformer reactors primarily because of their low cost, relatively simple operation and low maintenance. Commercial, off-the-shelf balance of plant (BOP) components (pumps, valves, and heat exchangers) were used to integrate the unit operations. The fuel processor delivers up to 100 slm hydrogen >99.9% pure with <1 ppm CO, <3 ppm CO 2. The thermal efficiency is better than 67% operating at full load. This fuel processor has been integrated with a 5-kW fuel cell producing electricity and hot water.

Fuel processing in integrated micro-structured heat-exchanger reactors

NASA Astrophysics Data System (ADS)

Kolb, G.; Schürer, J.; Tiemann, D.; Wichert, M.; Zapf, R.; Hessel, V.; Löwe, H.

Micro-structured fuel processors are under development at IMM for different fuels such as methanol, ethanol, propane/butane (LPG), gasoline and diesel. The target application are mobile, portable and small scale stationary auxiliary power units (APU) based upon fuel cell technology. The key feature of the systems is an integrated plate heat-exchanger technology which allows for the thermal integration of several functions in a single device. Steam reforming may be coupled with catalytic combustion in separate flow paths of a heat-exchanger. Reactors and complete fuel processors are tested up to the size range of 5 kW power output of a corresponding fuel cell. On top of reactor and system prototyping and testing, catalyst coatings are under development at IMM for numerous reactions such as steam reforming of LPG, ethanol and methanol, catalytic combustion of LPG and methanol, and for CO clean-up reactions, namely water-gas shift, methanation and the preferential oxidation of carbon monoxide. These catalysts are investigated in specially developed testing reactors. In selected cases 1000 h stability testing is performed on catalyst coatings at weight hourly space velocities, which are sufficiently high to meet the demands of future fuel processing reactors.

An integrated MEMS infrastructure for fuel processing: hydrogen generation and separation for portable power generation

NASA Astrophysics Data System (ADS)

Varady, M. J.; McLeod, L.; Meacham, J. M.; Degertekin, F. L.; Fedorov, A. G.

2007-09-01

Portable fuel cells are an enabling technology for high efficiency and ultra-high density distributed power generation, which is essential for many terrestrial and aerospace applications. A key element of fuel cell power sources is the fuel processor, which should have the capability to efficiently reform liquid fuels and produce high purity hydrogen that is consumed by the fuel cells. To this end, we are reporting on the development of two novel MEMS hydrogen generators with improved functionality achieved through an innovative process organization and system integration approach that exploits the advantages of transport and catalysis on the micro/nano scale. One fuel processor design utilizes transient, reverse-flow operation of an autothermal MEMS microreactor with an intimately integrated, micromachined ultrasonic fuel atomizer and a Pd/Ag membrane for in situ hydrogen separation from the product stream. The other design features a simpler, more compact planar structure with the atomized fuel ejected directly onto the catalyst layer, which is coupled to an integrated hydrogen selective membrane.

Diesel fuel to dc power: Navy & Marine Corps Applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bloomfield, D.P.

1996-12-31

During the past year Analytic Power has tested fuel cell stacks and diesel fuel processors for US Navy and Marine Corps applications. The units are 10 kW demonstration power plants. The USN power plant was built to demonstrate the feasibility of diesel fueled PEM fuel cell power plants for 250 kW and 2.5 MW shipboard power systems. We designed and tested a ten cell, 1 kW USMC substack and fuel processor. The complete 10 kW prototype power plant, which has application to both power and hydrogen generation, is now under construction. The USN and USMC fuel cell stacks have beenmore » tested on both actual and simulated reformate. Analytic Power has accumulated operating experience with autothermal reforming based fuel processors operating on sulfur bearing diesel fuel, jet fuel, propane and natural gas. We have also completed the design and fabrication of an advanced regenerative ATR for the USMC. One of the significant problems with small fuel processors is heat loss which limits its ability to operate with the high steam to carbon ratios required for coke free high efficiency operation. The new USMC unit specifically addresses these heat transfer issues. The advances in the mill programs have been incorporated into Analytic Power`s commercial units which are now under test.« less

On-board diesel autothermal reforming for PEM fuel cells: Simulation and optimization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cozzolino, Raffaello, E-mail: raffaello.cozzolino@unicusano.it; Tribioli, Laura

2015-03-10

Alternative power sources are nowadays the only option to provide a quick response to the current regulations on automotive pollutant emissions. Hydrogen fuel cell is one promising solution, but the nature of the gas is such that the in-vehicle conversion of other fuels into hydrogen is necessary. In this paper, autothermal reforming, for Diesel on-board conversion into a hydrogen-rich gas suitable for PEM fuel cells, has investigated using the simulation tool Aspen Plus. A steady-state model has been developed to analyze the fuel processor and the overall system performance. The components of the fuel processor are: the fuel reforming reactor,more » two water gas shift reactors, a preferential oxidation reactor and H{sub 2} separation unit. The influence of various operating parameters such as oxygen to carbon ratio, steam to carbon ratio, and temperature on the process components has been analyzed in-depth and results are presented.« less

77 FR 75868 - Regulation of Fuels and Fuel Additives: Modifications to the Transmix Provisions Under the Diesel...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-12-26

...EPA is amending the requirements under EPA's diesel sulfur program related to the sulfur content of locomotive and marine (LM) diesel fuel produced by transmix processors and pipeline facilities. These amendments will reinstate the ability of locomotive and marine diesel fuel produced from transmix by transmix processors and pipeline operators to meet a maximum 500 parts per million (ppm) sulfur standard outside of the Northeast Mid-Atlantic Area and Alaska and expand this ability to within the Northeast Mid-Atlantic Area provided that: the fuel is used in older technology locomotive and marine engines that do not require 15 ppm sulfur diesel fuel, and the fuel is kept segregated from other fuel. These amendments will provide significant regulatory relief for transmix processors and pipeline operators to allow the petroleum distribution system to function efficiently while continuing to transition the market to virtually all ultra-low sulfur diesel fuel (ULSD, i.e. 15 ppm sulfur diesel fuel) and the environmental benefits it provides.

Dynamic behavior of gasoline fuel cell electric vehicles

NASA Astrophysics Data System (ADS)

Mitchell, William; Bowers, Brian J.; Garnier, Christophe; Boudjemaa, Fabien

As we begin the 21st century, society is continuing efforts towards finding clean power sources and alternative forms of energy. In the automotive sector, reduction of pollutants and greenhouse gas emissions from the power plant is one of the main objectives of car manufacturers and innovative technologies are under active consideration to achieve this goal. One technology that has been proposed and vigorously pursued in the past decade is the proton exchange membrane (PEM) fuel cell, an electrochemical device that reacts hydrogen with oxygen to produce water, electricity and heat. Since today there is no existing extensive hydrogen infrastructure and no commercially viable hydrogen storage technology for vehicles, there is a continuing debate as to how the hydrogen for these advanced vehicles will be supplied. In order to circumvent the above issues, power systems based on PEM fuel cells can employ an on-board fuel processor that has the ability to convert conventional fuels such as gasoline into hydrogen for the fuel cell. This option could thereby remove the fuel infrastructure and storage issues. However, for these fuel processor/fuel cell vehicles to be commercially successful, issues such as start time and transient response must be addressed. This paper discusses the role of transient response of the fuel processor power plant and how it relates to the battery sizing for a gasoline fuel cell vehicle. In addition, results of fuel processor testing from a current Renault/Nuvera Fuel Cells project are presented to show the progress in transient performance.

Incorporating landscape fuel treatment modeling into the Forest Vegetation Simulator

Treesearch

Robert C. Seli; Alan A. Ager; Nicholas L. Crookston; Mark A. Finney; Berni Bahro; James K. Agee; Charles W. McHugh

2008-01-01

A simulation system was developed to explore how fuel treatments placed in random and optimal spatial patterns affect the growth and behavior of large fires when implemented at different rates over the course of five decades. The system consists of several command line programs linked together: (1) FVS with the Parallel Processor (PPE) and Fire and Fuels (FFE)...

Hydrogen Generation Via Fuel Reforming

NASA Astrophysics Data System (ADS)

Krebs, John F.

2003-07-01

Reforming is the conversion of a hydrocarbon based fuel to a gas mixture that contains hydrogen. The H2 that is produced by reforming can then be used to produce electricity via fuel cells. The realization of H2-based power generation, via reforming, is facilitated by the existence of the liquid fuel and natural gas distribution infrastructures. Coupling these same infrastructures with more portable reforming technology facilitates the realization of fuel cell powered vehicles. The reformer is the first component in a fuel processor. Contaminants in the H2-enriched product stream, such as carbon monoxide (CO) and hydrogen sulfide (H2S), can significantly degrade the performance of current polymer electrolyte membrane fuel cells (PEMFC's). Removal of such contaminants requires extensive processing of the H2-rich product stream prior to utilization by the fuel cell to generate electricity. The remaining components of the fuel processor remove the contaminants in the H2 product stream. For transportation applications the entire fuel processing system must be as small and lightweight as possible to achieve desirable performance requirements. Current efforts at Argonne National Laboratory are focused on catalyst development and reactor engineering of the autothermal processing train for transportation applications.

Electrical start-up for diesel fuel processing in a fuel-cell-based auxiliary power unit

NASA Astrophysics Data System (ADS)

Samsun, Remzi Can; Krupp, Carsten; Tschauder, Andreas; Peters, Ralf; Stolten, Detlef

2016-01-01

As auxiliary power units in trucks and aircraft, fuel cell systems with a diesel and kerosene reforming capacity offer the dual benefit of reduced emissions and fuel consumption. In order to be commercially viable, these systems require a quick start-up time with low energy input. In pursuit of this end, this paper reports an electrical start-up strategy for diesel fuel processing. A transient computational fluid dynamics model is developed to optimize the start-up procedure of the fuel processor in the 28 kWth power class. The temperature trend observed in the experiments is reproducible to a high degree of accuracy using a dual-cell approach in ANSYS Fluent. Starting from a basic strategy, different options are considered for accelerating system start-up. The start-up time is reduced from 22 min in the basic case to 9.5 min, at an energy consumption of 0.4 kW h. Furthermore, an electrical wire is installed in the reformer to test the steam generation during start-up. The experimental results reveal that the generation of steam at 450 °C is possible within seconds after water addition to the reformer. As a result, the fuel processor can be started in autothermal reformer mode using the electrical concept developed in this work.

Configuring a fuel cell based residential combined heat and power system

NASA Astrophysics Data System (ADS)

Ahmed, Shabbir; Papadias, Dionissios D.; Ahluwalia, Rajesh K.

2013-11-01

The design and performance of a fuel cell based residential combined heat and power (CHP) system operating on natural gas has been analyzed. The natural gas is first converted to a hydrogen-rich reformate in a steam reformer based fuel processor, and the hydrogen is then electrochemically oxidized in a low temperature polymer electrolyte fuel cell to generate electric power. The heat generated in the fuel cell and the available heat in the exhaust gas is recovered to meet residential needs for hot water and space heating. Two fuel processor configurations have been studied. One of the configurations was explored to quantify the effects of design and operating parameters, which include pressure, temperature, and steam-to-carbon ratio in the fuel processor, and fuel utilization in the fuel cell. The second configuration applied the lessons from the study of the first configuration to increase the CHP efficiency. Results from the two configurations allow a quantitative comparison of the design alternatives. The analyses showed that these systems can operate at electrical efficiencies of ∼46% and combined heat and power efficiencies of ∼90%.

Fuel processing device

DOEpatents

Ahluwalia, Rajesh K [Burr Ridge, IL; Ahmed, Shabbir [Naperville, IL; Lee, Sheldon H. D. [Willowbrook, IL

2011-08-02

An improved fuel processor for fuel cells is provided whereby the startup time of the processor is less than sixty seconds and can be as low as 30 seconds, if not less. A rapid startup time is achieved by either igniting or allowing a small mixture of air and fuel to react over and warm up the catalyst of an autothermal reformer (ATR). The ATR then produces combustible gases to be subsequently oxidized on and simultaneously warm up water-gas shift zone catalysts. After normal operating temperature has been achieved, the proportion of air included with the fuel is greatly diminished.

Fuels processing for transportation fuel cell systems

NASA Astrophysics Data System (ADS)

Kumar, R.; Ahmed, S.

Fuel cells primarily use hydrogen as the fuel. This hydrogen must be produced from other fuels such as natural gas or methanol. The fuel processor requirements are affected by the fuel to be converted, the type of fuel cell to be supplied, and the fuel cell application. The conventional fuel processing technology has been reexamined to determine how it must be adapted for use in demanding applications such as transportation. The two major fuel conversion processes are steam reforming and partial oxidation reforming. The former is established practice for stationary applications; the latter offers certain advantages for mobile systems and is presently in various stages of development. This paper discusses these fuel processing technologies and the more recent developments for fuel cell systems used in transportation. The need for new materials in fuels processing, particularly in the area of reforming catalysis and hydrogen purification, is discussed.

Efficiency of a solid polymer fuel cell operating on ethanol

NASA Astrophysics Data System (ADS)

Ioannides, Theophilos; Neophytides, Stylianos

The efficiency of a solid polymer fuel cell (SPFC) system operating on ethanol fuel has been analyzed as a function of operating parameters focusing on vehicle and stationary applications. Two types of ethanol processors — employing either steam reforming or partial oxidation (POX) steps — have been considered and their performance has been investigated by thermodynamic analysis. SPFC operation has been analyzed by an available parametric model. It has been found that dilute ethanol-water mixtures (˜55% v/v EtOH) are the most suitable for stationary applications with a steam reformer (SR)-SPFC system. Regarding vehicle applications, pure ethanol (˜95% v/v EtOH) appears to be the best fuel with a POX-SPFC system. Efficiencies in the case of an ideal ethanol processor can be of the order of 60% under low load conditions and 30-35% at peak power, while efficiencies with an actual processor are 80-85% of the above values.

Fuel processor and method for generating hydrogen for fuel cells

DOEpatents

Ahmed, Shabbir [Naperville, IL; Lee, Sheldon H. D. [Willowbrook, IL; Carter, John David [Bolingbrook, IL; Krumpelt, Michael [Naperville, IL; Myers, Deborah J [Lisle, IL

2009-07-21

A method of producing a H.sub.2 rich gas stream includes supplying an O.sub.2 rich gas, steam, and fuel to an inner reforming zone of a fuel processor that includes a partial oxidation catalyst and a steam reforming catalyst or a combined partial oxidation and stream reforming catalyst. The method also includes contacting the O.sub.2 rich gas, steam, and fuel with the partial oxidation catalyst and the steam reforming catalyst or the combined partial oxidation and stream reforming catalyst in the inner reforming zone to generate a hot reformate stream. The method still further includes cooling the hot reformate stream in a cooling zone to produce a cooled reformate stream. Additionally, the method includes removing sulfur-containing compounds from the cooled reformate stream by contacting the cooled reformate stream with a sulfur removal agent. The method still further includes contacting the cooled reformate stream with a catalyst that converts water and carbon monoxide to carbon dioxide and H.sub.2 in a water-gas-shift zone to produce a final reformate stream in the fuel processor.

Development of new UV-I. I. Cerenkov Viewing Device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kuribara, Masayuki; Nemoto, Koshichi

1994-02-01

The Cerenkov glow images from boiling-water reactors (BWR) and pressurized-water reactors (PWR) irradiated fuel assemblies are generally used for inspections. However, sometimes it is difficult or impossible to identify the image by the conventional Cerenkov Viewing Device (CVD), because of the long cooling time and/or low burnup. Now a new UV-I.I. (Ultra-Violet light Image Intensifier) CVD has been developed, which can detect the very weak Cerenkov glow from spent fuel assemblies. As this new device uses the newly developed proximity focused type UV-I.I., Cerenkov photons are used efficiently, producing better quality Cerenkov glow images. Moreover, since the image is convertedmore » to a video signal, it is easy to improve the signal to noise ratio (S/N) by an image processor. The new CVD was tested at BWR and PWR power plants in Japan, with fuel burnups ranging from 6,200--33,000 MWD/MTU (megawatt days per metric ton of uranium) and cooling times ranging from 370 to 6,200 d. The tests showed that the new CVD is superior to the conventional STA/CRIEPI CVD, and could detect very feeble Cerenkov glow images using an image processor.« less

Hybrid fuel cell/diesel generation total energy system, part 2

NASA Astrophysics Data System (ADS)

Blazek, C. F.

1982-11-01

Meeting the Goldstone Deep Space Communications Complex (DGSCC) electrical and thermal requirements with the existing system was compared with using fuel cells. Fuel cell technology selection was based on a 1985 time frame for installation. The most cost-effective fuel feedstock for fuel cell application was identified. Fuels considered included diesel oil, natural gas, methanol and coal. These fuel feedstocks were considered not only on the cost and efficiency of the fuel conversion process, but also on complexity and integration of the fuel processor on system operation and thermal energy availability. After a review of fuel processor technology, catalytic steam reformer technology was selected based on the ease of integration and the economics of hydrogen production. The phosphoric acid fuel cell was selected for application at the GDSCC due to its commercial readiness for near term application. Fuel cell systems were analyzed for both natural gas and methanol feedstock. The subsequent economic analysis indicated that a natural gas fueled system was the most cost effective of the cases analyzed.

Hybrid fuel cell/diesel generation total energy system, part 2

NASA Technical Reports Server (NTRS)

Blazek, C. F.

1982-01-01

Meeting the Goldstone Deep Space Communications Complex (DGSCC) electrical and thermal requirements with the existing system was compared with using fuel cells. Fuel cell technology selection was based on a 1985 time frame for installation. The most cost-effective fuel feedstock for fuel cell application was identified. Fuels considered included diesel oil, natural gas, methanol and coal. These fuel feedstocks were considered not only on the cost and efficiency of the fuel conversion process, but also on complexity and integration of the fuel processor on system operation and thermal energy availability. After a review of fuel processor technology, catalytic steam reformer technology was selected based on the ease of integration and the economics of hydrogen production. The phosphoric acid fuel cell was selected for application at the GDSCC due to its commercial readiness for near term application. Fuel cell systems were analyzed for both natural gas and methanol feedstock. The subsequent economic analysis indicated that a natural gas fueled system was the most cost effective of the cases analyzed.

System and method for controlling a combustor assembly

DOEpatents

York, William David; Ziminsky, Willy Steve; Johnson, Thomas Edward; Stevenson, Christian Xavier

2013-03-05

A system and method for controlling a combustor assembly are disclosed. The system includes a combustor assembly. The combustor assembly includes a combustor and a fuel nozzle assembly. The combustor includes a casing. The fuel nozzle assembly is positioned at least partially within the casing and includes a fuel nozzle. The fuel nozzle assembly further defines a head end. The system further includes a viewing device configured for capturing an image of at least a portion of the head end, and a processor communicatively coupled to the viewing device, the processor configured to compare the image to a standard image for the head end.

Extended Durability Testing of an External Fuel Processor for a Solid Oxide Fuel Cell (SOFC)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mark Perna; Anant Upadhyayula; Mark Scotto

2012-11-05

Durability testing was performed on an external fuel processor (EFP) for a solid oxide fuel cell (SOFC) power plant. The EFP enables the SOFC to reach high system efficiency (electrical efficiency up to 60%) using pipeline natural gas and eliminates the need for large quantities of bottled gases. LG Fuel Cell Systems Inc. (formerly known as Rolls-Royce Fuel Cell Systems (US) Inc.) (LGFCS) is developing natural gas-fired SOFC power plants for stationary power applications. These power plants will greatly benefit the public by reducing the cost of electricity while reducing the amount of gaseous emissions of carbon dioxide, sulfur oxides,more » and nitrogen oxides compared to conventional power plants. The EFP uses pipeline natural gas and air to provide all the gas streams required by the SOFC power plant; specifically those needed for start-up, normal operation, and shutdown. It includes a natural gas desulfurizer, a synthesis-gas generator and a start-gas generator. The research in this project demonstrated that the EFP could meet its performance and durability targets. The data generated helped assess the impact of long-term operation on system performance and system hardware. The research also showed the negative impact of ambient weather (both hot and cold conditions) on system operation and performance.« less

Development and test fuel cell powered on-site integrated total energy systems. Phase 3: Full-scale power plant development

NASA Technical Reports Server (NTRS)

Kaufman, A.

1982-01-01

The on-site system application analysis is summarized. Preparations were completed for the first test of a full-sized single cell. Emphasis of the methanol fuel processor development program shifted toward the use of commercial shell-and-tube heat exchangers. An improved method for predicting the carbon-monoxide tolerance of anode catalysts is described. Other stack support areas reported include improved ABA bipolar plate bonding technology, improved electrical measurement techniques for specification-testing of stack components, and anodic corrosion behavior of carbon materials.

Real-time trajectory optimization on parallel processors

NASA Technical Reports Server (NTRS)

Psiaki, Mark L.

1993-01-01

A parallel algorithm has been developed for rapidly solving trajectory optimization problems. The goal of the work has been to develop an algorithm that is suitable to do real-time, on-line optimal guidance through repeated solution of a trajectory optimization problem. The algorithm has been developed on an INTEL iPSC/860 message passing parallel processor. It uses a zero-order-hold discretization of a continuous-time problem and solves the resulting nonlinear programming problem using a custom-designed augmented Lagrangian nonlinear programming algorithm. The algorithm achieves parallelism of function, derivative, and search direction calculations through the principle of domain decomposition applied along the time axis. It has been encoded and tested on 3 example problems, the Goddard problem, the acceleration-limited, planar minimum-time to the origin problem, and a National Aerospace Plane minimum-fuel ascent guidance problem. Execution times as fast as 118 sec of wall clock time have been achieved for a 128-stage Goddard problem solved on 32 processors. A 32-stage minimum-time problem has been solved in 151 sec on 32 processors. A 32-stage National Aerospace Plane problem required 2 hours when solved on 32 processors. A speed-up factor of 7.2 has been achieved by using 32-nodes instead of 1-node to solve a 64-stage Goddard problem.

Unmixed fuel processors and methods for using the same

DOEpatents

Kulkarni, Parag Prakash; Cui, Zhe

2010-08-24

Disclosed herein are unmixed fuel processors and methods for using the same. In one embodiment, an unmixed fuel processor comprises: an oxidation reactor comprising an oxidation portion and a gasifier, a CO.sub.2 acceptor reactor, and a regeneration reactor. The oxidation portion comprises an air inlet, effluent outlet, and an oxygen transfer material. The gasifier comprises a solid hydrocarbon fuel inlet, a solids outlet, and a syngas outlet. The CO.sub.2 acceptor reactor comprises a water inlet, a hydrogen outlet, and a CO.sub.2 sorbent, and is configured to receive syngas from the gasifier. The regeneration reactor comprises a water inlet and a CO.sub.2 stream outlet. The regeneration reactor is configured to receive spent CO.sub.2 adsorption material from the gasification reactor and to return regenerated CO.sub.2 adsorption material to the gasification reactor, and configured to receive oxidized oxygen transfer material from the oxidation reactor and to return reduced oxygen transfer material to the oxidation reactor.

Fiber optic sensors for gas turbine control

NASA Technical Reports Server (NTRS)

Shu, Emily Yixie (Inventor); Petrucco, Louis Jacob (Inventor); Daum, Wolfgang (Inventor)

2005-01-01

An apparatus for detecting flashback occurrences in a premixed combustor system having at least one fuel nozzle includes at least one photodetector and at least one fiber optic element coupled between the at least one photodetector and a test region of the combustor system wherein a respective flame of the fuel nozzle is not present under normal operating conditions. A signal processor monitors a signal of the photodetector. The fiber optic element can include at least one optical fiber positioned within a protective tube. The fiber optic element can include two fiber optic elements coupled to the test region. The optical fiber and the protective tube can have lengths sufficient to situate the photodetector outside of an engine compartment. A plurality of fuel nozzles and a plurality of fiber optic elements can be used with the fiber optic elements being coupled to respective fuel nozzles and either to the photodetector or, wherein a plurality of photodetectors are used, to respective ones of the plurality of photodetectors. The signal processor can include a digital signal processor.

Fiber optic sensors for gas turbine control

NASA Technical Reports Server (NTRS)

Shu, Emily Yixie (Inventor); Brown, Dale Marius (Inventor); Petrucco, Louis Jacob (Inventor); Lovett, Jeffery Allan (Inventor); Daum, Wolfgang (Inventor); Dunki-Jacobs, Robert John (Inventor)

2003-01-01

An apparatus for detecting flashback occurrences in a premixed combustor system having at least one fuel nozzle includes at least one photodetector and at least one fiber optic element coupled between the at least one photodetector and a test region of the combustor system wherein a respective flame of the fuel nozzle is not present under normal operating conditions. A signal processor monitors a signal of the photodetector. The fiber optic element can include at least one optical fiber positioned within a protective tube. The fiber optic element can include two fiber optic elements coupled to the test region. The optical fiber and the protective tube can have lengths sufficient to situate the photodetector outside of an engine compartment. A plurality of fuel nozzles and a plurality of fiber optic elements can be used with the fiber optic elements being coupled to respective fuel nozzles and either to the photodetector or, wherein a plurality of photodetectors are used, to respective ones of the plurality of photodetectors. The signal processor can include a digital signal processor.

Fiber optic sensors for gas turbine control

NASA Technical Reports Server (NTRS)

Shu, Emily Yixie (Inventor); Brown, Dale Marius (Inventor); Petrucco, Louis Jacob (Inventor); Lovett, Jeffery Allan (Inventor); Daum, Wolfgang (Inventor); Dunki-Jacobs, Robert John (Inventor)

1999-01-01

An apparatus for detecting flashback occurrences in a premixed combustor system having at least one fuel nozzle includes at least one photodetector and at least one fiber optic element coupled between the at least one photodetector and a test region of the combustor system wherein a respective flame of the fuel nozzle is not present under normal operating conditions. A signal processor monitors a signal of the photodetector. The fiber optic element can include at least one optical fiber positioned within a protective tube. The fiber optic element can include two fiber optic elements coupled to the test region. The optical fiber and the protective tube can have lengths sufficient to situate the photodetector outside of an engine compartment. A plurality of fuel nozzles and a plurality of fiber optic elements can be used with the fiber optic elements being coupled to respective fuel nozzles and either to the photodetector or, wherein a plurality of photodetectors are used, to respective ones of the plurality of photodetectors. The signal processor can include a digital signal processor.

A comparison of hydrogen, methanol and gasoline as fuels for fuel cell vehicles: implications for vehicle design and infrastructure development

NASA Astrophysics Data System (ADS)

Ogden, Joan M.; Steinbugler, Margaret M.; Kreutz, Thomas G.

All fuel cells currently being developed for near term use in electric vehicles require hydrogen as a fuel. Hydrogen can be stored directly or produced onboard the vehicle by reforming methanol, or hydrocarbon fuels derived from crude oil (e.g., gasoline, diesel, or middle distillates). The vehicle design is simpler with direct hydrogen storage, but requires developing a more complex refueling infrastructure. In this paper, we present modeling results comparing three leading options for fuel storage onboard fuel cell vehicles: (a) compressed gas hydrogen storage, (b) onboard steam reforming of methanol, (c) onboard partial oxidation (POX) of hydrocarbon fuels derived from crude oil. We have developed a fuel cell vehicle model, including detailed models of onboard fuel processors. This allows us to compare the vehicle performance, fuel economy, weight, and cost for various vehicle parameters, fuel storage choices and driving cycles. The infrastructure requirements are also compared for gaseous hydrogen, methanol and gasoline, including the added costs of fuel production, storage, distribution and refueling stations. The delivered fuel cost, total lifecycle cost of transportation, and capital cost of infrastructure development are estimated for each alternative. Considering both vehicle and infrastructure issues, possible fuel strategies leading to the commercialization of fuel cell vehicles are discussed.

MEMS-based fuel cells with integrated catalytic fuel processor and method thereof

DOEpatents

Jankowski, Alan F [Livermore, CA; Morse, Jeffrey D [Martinez, CA; Upadhye, Ravindra S [Pleasanton, CA; Havstad, Mark A [Davis, CA

2011-08-09

Described herein is a means to incorporate catalytic materials into the fuel flow field structures of MEMS-based fuel cells, which enable catalytic reforming of a hydrocarbon based fuel, such as methane, methanol, or butane. Methods of fabrication are also disclosed.

Integral Fast Reactor fuel pin processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Levinskas, D.

1993-01-01

This report discusses the pin processor which receives metal alloy pins cast from recycled Integral Fast Reactor (IFR) fuel and prepares them for assembly into new IFR fuel elements. Either full length as-cast or precut pins are fed to the machine from a magazine, cut if necessary, and measured for length, weight, diameter and deviation from straightness. Accepted pins are loaded into cladding jackets located in a magazine, while rejects and cutting scraps are separated into trays. The magazines, trays, and the individual modules that perform the different machine functions are assembled and removed using remote manipulators and master-slaves.

Integral Fast Reactor fuel pin processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Levinskas, D.

1993-03-01

This report discusses the pin processor which receives metal alloy pins cast from recycled Integral Fast Reactor (IFR) fuel and prepares them for assembly into new IFR fuel elements. Either full length as-cast or precut pins are fed to the machine from a magazine, cut if necessary, and measured for length, weight, diameter and deviation from straightness. Accepted pins are loaded into cladding jackets located in a magazine, while rejects and cutting scraps are separated into trays. The magazines, trays, and the individual modules that perform the different machine functions are assembled and removed using remote manipulators and master-slaves.

75 FR 68177 - Airworthiness Directives; The Boeing Company Model 757 and 767 Airplanes

Federal Register 2010, 2011, 2012, 2013, 2014

2010-11-05

... and FUEL CONFIG discrete signals from the fuel quantity processor unit, and alerts the flightcrew of a... the FUEL CONFIG discrete signal, which disables both the FUEL CONFIG and LOW FUEL messages. Such... depleted below the minimum of 2,200 pounds. The EICAS receives both the LOW FUEL and FUEL CONFIG discrete...

Advanced Diesel Oil Fuel Processor Development

DTIC Science & Technology

1986-06-01

water exit 29 sample quencher: gas sample line inlet 30 sample quencher: gas sample line exit 31 sample quencher: cooling water inlet 32 desulfuriser ...exit line 33, 34 desulfurimer 35 heat exchanger: process gas exit (to desulfuriser ) 38 shift reactor inlet (top) 37 shift reactor: cooling air exit

Development of a Solid-Oxide Fuel Cell/Gas Turbine Hybrid System Model for Aerospace Applications

NASA Technical Reports Server (NTRS)

Freeh, Joshua E.; Pratt, Joseph W.; Brouwer, Jacob

2004-01-01

Recent interest in fuel cell-gas turbine hybrid applications for the aerospace industry has led to the need for accurate computer simulation models to aid in system design and performance evaluation. To meet this requirement, solid oxide fuel cell (SOFC) and fuel processor models have been developed and incorporated into the Numerical Propulsion Systems Simulation (NPSS) software package. The SOFC and reformer models solve systems of equations governing steady-state performance using common theoretical and semi-empirical terms. An example hybrid configuration is presented that demonstrates the new capability as well as the interaction with pre-existing gas turbine and heat exchanger models. Finally, a comparison of calculated SOFC performance with experimental data is presented to demonstrate model validity. Keywords: Solid Oxide Fuel Cell, Reformer, System Model, Aerospace, Hybrid System, NPSS

Combustor air flow control method for fuel cell apparatus

DOEpatents

Clingerman, Bruce J.; Mowery, Kenneth D.; Ripley, Eugene V.

2001-01-01

A method for controlling the heat output of a combustor in a fuel cell apparatus to a fuel processor where the combustor has dual air inlet streams including atmospheric air and fuel cell cathode effluent containing oxygen depleted air. In all operating modes, an enthalpy balance is provided by regulating the quantity of the air flow stream to the combustor to support fuel cell processor heat requirements. A control provides a quick fast forward change in an air valve orifice cross section in response to a calculated predetermined air flow, the molar constituents of the air stream to the combustor, the pressure drop across the air valve, and a look up table of the orifice cross sectional area and valve steps. A feedback loop fine tunes any error between the measured air flow to the combustor and the predetermined air flow.

40 CFR 279.72 - On-specification used oil fuel.

Code of Federal Regulations, 2014 CFR

2014-07-01

... 40 Protection of Environment 27 2014-07-01 2014-07-01 false On-specification used oil fuel. 279.72... (CONTINUED) STANDARDS FOR THE MANAGEMENT OF USED OIL Standards for Used Oil Fuel Marketers § 279.72 On-specification used oil fuel. (a) Analysis of used oil fuel. A generator, transporter, processor/re-refiner, or...

Analysis of the energy efficiency of an integrated ethanol processor for PEM fuel cell systems

NASA Astrophysics Data System (ADS)

Francesconi, Javier A.; Mussati, Miguel C.; Mato, Roberto O.; Aguirre, Pio A.

The aim of this work is to investigate the energy integration and to determine the maximum efficiency of an ethanol processor for hydrogen production and fuel cell operation. Ethanol, which can be produced from renewable feedstocks or agriculture residues, is an attractive option as feed to a fuel processor. The fuel processor investigated is based on steam reforming, followed by high- and low-temperature shift reactors and preferential oxidation, which are coupled to a polymeric fuel cell. Applying simulation techniques and using thermodynamic models the performance of the complete system has been evaluated for a variety of operating conditions and possible reforming reactions pathways. These models involve mass and energy balances, chemical equilibrium and feasible heat transfer conditions (Δ T min). The main operating variables were determined for those conditions. The endothermic nature of the reformer has a significant effect on the overall system efficiency. The highest energy consumption is demanded by the reforming reactor, the evaporator and re-heater operations. To obtain an efficient integration, the heat exchanged between the reformer outgoing streams of higher thermal level (reforming and combustion gases) and the feed stream should be maximized. Another process variable that affects the process efficiency is the water-to-fuel ratio fed to the reformer. Large amounts of water involve large heat exchangers and the associated heat losses. A net electric efficiency around 35% was calculated based on the ethanol HHV. The responsibilities for the remaining 65% are: dissipation as heat in the PEMFC cooling system (38%), energy in the flue gases (10%) and irreversibilities in compression and expansion of gases. In addition, it has been possible to determine the self-sufficient limit conditions, and to analyze the effect on the net efficiency of the input temperatures of the clean-up system reactors, combustion preheating, expander unit and crude ethanol as fuel.

System Design of a Natural Gas PEM Fuel Cell Power Plant for Buildings

DOE Office of Scientific and Technical Information (OSTI.GOV)

Joe Ferrall, Tim Rehg, Vesna Stanic

2000-09-30

The following conclusions are made based on this analysis effort: (1) High-temperature PEM data are not available; (2) Stack development effort for Phase II is required; (3) System results are by definition preliminary, mostly due to the immaturity of the high-temperature stack; other components of the system are relatively well defined; (4) The Grotthuss conduction mechanism yields the preferred system characteristics; the Grotthuss conduction mechanism is also much less technically mature than the vehicle mechanism; (5) Fuel processor technology is available today and can be procured for Phase II (steam or ATR); (6) The immaturity of high-temperature membrane technology requiresmore » that a robust system design be developed in Phase II that is capable of operating over a wide temperature and pressure range - (a) Unpressurized or Pressurized PEM (Grotthuss mechanism) at 140 C, Highest temperature most favorable, Lowest water requirement most favorable, Pressurized recommended for base loaded operation, Unpressurized may be preferred for load following; (b) Pressurized PEM (vehicle mechanism) at about 100 C, Pressure required for saturation, Fuel cell technology currently available, stack development required. The system analysis and screening evaluation resulted in the identification of the following components for the most promising system: (1) Steam reforming fuel processor; (2) Grotthuss mechanism fuel cell stack operating at 140 C; (3) Means to deliver system waste heat to a cogeneration unit; (4) Pressurized system utilizing a turbocompressor for a base-load power application. If duty cycling is anticipated, the benefits of compression may be offset due to complexity of control. In this case (and even in the base loaded case), the turbocompressor can be replaced with a blower for low-pressure operation.« less

40 CFR 279.72 - On-specification used oil fuel.

Code of Federal Regulations, 2012 CFR

2012-07-01

... of § 279.11 by performing analyses or obtaining copies of analyses or other information documenting...-specification used oil fuel. (a) Analysis of used oil fuel. A generator, transporter, processor/re-refiner, or... meets the specifications for used oil fuel under § 279.11, must keep copies of analyses of the used oil...

Fuel processing for PEM fuel cells: transport and kinetic issues of system design

NASA Astrophysics Data System (ADS)

Zalc, J. M.; Löffler, D. G.

In light of the distribution and storage issues associated with hydrogen, efficient on-board fuel processing will be a significant factor in the implementation of PEM fuel cells for automotive applications. Here, we apply basic chemical engineering principles to gain insight into the factors that limit performance in each component of a fuel processor. A system consisting of a plate reactor steam reformer, water-gas shift unit, and preferential oxidation reactor is used as a case study. It is found that for a steam reformer based on catalyst-coated foils, mass transfer from the bulk gas to the catalyst surface is the limiting process. The water-gas shift reactor is expected to be the largest component of the fuel processor and is limited by intrinsic catalyst activity, while a successful preferential oxidation unit depends on strict temperature control in order to minimize parasitic hydrogen oxidation. This stepwise approach of sequentially eliminating rate-limiting processes can be used to identify possible means of performance enhancement in a broad range of applications.

Method for improving catalyst function in auto-thermal and partial oxidation reformer-based processors

DOEpatents

Ahmed, Shabbir; Papadias, Dionissios D.; Lee, Sheldon H.D.; Ahluwalia, Rajesh K.

2014-08-26

The invention provides a method for reforming fuel, the method comprising contacting the fuel to an oxidation catalyst so as to partially oxidize the fuel and generate heat; warming incoming fuel with the heat while simultaneously warming a reforming catalyst with the heat; and reacting the partially oxidized fuel with steam using the reforming catalyst.

Comparison of the CENTRM resonance processor to the NITAWL resonance processor in SCALE

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hollenbach, D.F.; Petrie, L.M.

1998-01-01

This report compares the MTAWL and CENTRM resonance processors in the SCALE code system. The cases examined consist of the International OECD/NEA Criticality Working Group Benchmark 20 problem. These cases represent fuel pellets partially dissolved in a borated solution. The assumptions inherent to the Nordheim Integral Treatment, used in MTAWL, are not valid for these problems. CENTRM resolves this limitation by explicitly calculating a problem dependent point flux from point cross sections, which is then used to create group cross sections.

Effects of fuel processing methods on industrial scale biogas-fuelled solid oxide fuel cell system for operating in wastewater treatment plants

NASA Astrophysics Data System (ADS)

Farhad, Siamak; Yoo, Yeong; Hamdullahpur, Feridun

The performance of three solid oxide fuel cell (SOFC) systems, fuelled by biogas produced through anaerobic digestion (AD) process, for heat and electricity generation in wastewater treatment plants (WWTPs) is studied. Each system has a different fuel processing method to prevent carbon deposition over the anode catalyst under biogas fuelling. Anode gas recirculation (AGR), steam reforming (SR), and partial oxidation (POX) are the methods employed in systems I-III, respectively. A planar SOFC stack used in these systems is based on the anode-supported cells with Ni-YSZ anode, YSZ electrolyte and YSZ-LSM cathode, operated at 800 °C. A computer code has been developed for the simulation of the planar SOFC in cell, stack and system levels and applied for the performance prediction of the SOFC systems. The key operational parameters affecting the performance of the SOFC systems are identified. The effect of these parameters on the electrical and CHP efficiencies, the generated electricity and heat, the total exergy destruction, and the number of cells in SOFC stack of the systems are studied. The results show that among the SOFC systems investigated in this study, the AGR and SR fuel processor-based systems with electrical efficiency of 45.1% and 43%, respectively, are suitable to be applied in WWTPs. If the entire biogas produced in a WWTP is used in the AGR or SR fuel processor-based SOFC system, the electricity and heat required to operate the WWTP can be completely self-supplied and the extra electricity generated can be sold to the electrical grid.

A techno-economic comparison of fuel processors utilizing diesel for solid oxide fuel cell auxiliary power units

NASA Astrophysics Data System (ADS)

Nehter, Pedro; Hansen, John Bøgild; Larsen, Peter Koch

Ultra-low sulphur diesel (ULSD) is the preferred fuel for mobile auxiliary power units (APU). The commercial available technologies in the kW-range are combustion engine based gensets, achieving system efficiencies about 20%. Solid oxide fuel cells (SOFC) promise improvements with respect to efficiency and emission, particularly for the low power range. Fuel processing methods i.e., catalytic partial oxidation, autothermal reforming and steam reforming have been demonstrated to operate on diesel with various sulphur contents. The choice of fuel processing method strongly affects the SOFC's system efficiency and power density. This paper investigates the impact of fuel processing methods on the economical potential in SOFC APUs, taking variable and capital cost into account. Autonomous concepts without any external water supply are compared with anode recycle configurations. The cost of electricity is very sensitive on the choice of the O/C ratio and the temperature conditions of the fuel processor. A sensitivity analysis is applied to identify the most cost effective concept for different economic boundary conditions. The favourite concepts are discussed with respect to technical challenges and requirements operating in the presence of sulphur.

Fuel Cell Power Plant Initiative. Volume 2; Preliminary Design of a Fixed-Base LFP/SOFC Power System

NASA Technical Reports Server (NTRS)

Veyo, S.E.

1997-01-01

This report documents the preliminary design for a military fixed-base power system of 3 MWe nominal capacity using Westinghouse's tubular Solid Oxide Fuel Cell [SOFC] and Haldor Topsoe's logistic fuels processor [LFP]. The LFP provides to the fuel cell a methane rich sulfur free fuel stream derived from either DF-2 diesel fuel, or JP-8 turbine fuel. Fuel cells are electrochemical devices that directly convert the chemical energy contained in fuels such as hydrogen, natural gas, or coal gas into electricity at high efficiency with no intermediate heat engine or dynamo. The SOFC is distinguished from other fuel cell types by its solid state ceramic structure and its high operating temperature, nominally 1000'C. The SOFC pioneered by Westinghouse has a tubular geometry closed at one end. A power generation stack is formed by aggregating many cells in an ordered array. The Westinghouse stack design is distinguished from other fuel cell stacks by the complete absence of high integrity seals between cell elements, cells, and between stack and manifolds. Further, the reformer for natural gas [predominantly methane] and the stack are thermally and hydraulically integrated with no requirement for process water. The technical viability of combining the tubular SOFC and a logistic fuels processor was demonstrated at 27 kWe scale in a test program sponsored by the Advanced Research Projects Agency [ARPA) and carried out at the Southern California Edison's [SCE] Highgrove generating station near San Bernardino, California in 1994/95. The LFP was a breadboard design supplied by Haldor Topsoe, Inc. under subcontract to Westinghouse. The test program was completely successful. The LFP fueled the SOFC for 766 hours on JP-8 and 1555 hours of DF-2. In addition, the fuel cell operated for 3261 hours on pipeline natural gas. Over the 5582 hours of operation, the SOFC generated 118 MVVH of electricity with no perceptible degradation in performance. The LFP processed military specification JP-8 and DF-2 removing the sulfur and reforming these liquid fuels to a methane rich gaseous fuel. Results of this program are documented in a companion report titled 'Final Report-Solid Oxide Fuel Cell/ Logistic Fuels Processor 27 kWe Power System'.

Stability of lanthanum oxide-based H 2S sorbents in realistic fuel processor/fuel cell operation

NASA Astrophysics Data System (ADS)

Valsamakis, Ioannis; Si, Rui; Flytzani-Stephanopoulos, Maria

We report that lanthana-based sulfur sorbents are an excellent choice as once-through chemical filters for the removal of trace amounts of H 2S and COS from any fuel gas at temperatures matching those of solid oxide fuel cells. We have examined sorbents based on lanthana and Pr-doped lanthana with up to 30 at.% praseodymium, having high desulfurization efficiency, as measured by their ability to remove H 2S from simulated reformate gas streams to below 50 ppbv with corresponding sulfur capacity exceeding 50 mg S g sorbent -1 at 800 °C. Intermittent sorbent operation with air-rich boiler exhaust-type gas mixtures and with frequent shutdowns and restarts is possible without formation of lanthanide oxycarbonate phases. Upon restart, desulfurization continues from where it left at the end of the previous cycle. These findings are important for practical applications of these sorbents as sulfur polishing units of fuel gases in the presence of small or large amounts of water vapor, and with the regular shutdown/start-up operation practiced in fuel processors/fuel cell systems, both stationary and mobile, and of any size/scale.

Science& Technology Review November 2003

DOE Office of Scientific and Technical Information (OSTI.GOV)

McMahon, D

2003-11-01

This issue of Science & Technology Review covers the following topics: (1) We Will Always Need Basic Science--Commentary by Tomas Diaz de la Rubia; (2) When Semiconductors Go Nano--experiments and computer simulations reveal some surprising behavior of semiconductors at the nanoscale; (3) Retinal Prosthesis Provides Hope for Restoring Sight--A microelectrode array is being developed for a retinal prosthesis; (4) Maglev on the Development Track for Urban Transportation--Inductrack, a Livermore concept to levitate train cars using permanent magnets, will be demonstrated on a 120-meter-long test track; and (5) Power Plant on a Chip Moves Closer to Reality--Laboratory-designed fuel processor gives powermore » boost to dime-size fuel cell.« less

Conceptual study of on orbit production of cryogenic propellants by water electrolysis

NASA Technical Reports Server (NTRS)

Moran, Matthew E.

1991-01-01

The feasibility is assessed of producing cryogenic propellants on orbit by water electrolysis in support of NASA's proposed Space Exploration Initiative (SEI) missions. Using this method, water launched into low earth orbit (LEO) would be split into gaseous hydrogen and oxygen by electrolysis in an orbiting propellant processor spacecraft. The resulting gases would then be liquified and stored in cryogenic tanks. Supplying liquid hydrogen and oxygen fuel to space vehicles by this technique has some possible advantages over conventional methods. The potential benefits are derived from the characteristics of water as a payload, and include reduced ground handling and launch risk, denser packaging, and reduced tankage and piping requirements. A conceptual design of a water processor was generated based on related previous studies, and contemporary or near term technologies required. Extensive development efforts would be required to adapt the various subsystems needed for the propellant processor for use in space. Based on the cumulative results, propellant production by on orbit water electrolysis for support of SEI missions is not recommended.

Controlled shutdown of a fuel cell

DOEpatents

Clingerman, Bruce J.; Keskula, Donald H.

2002-01-01

A method is provided for the shutdown of a fuel cell system to relieve system overpressure while maintaining air compressor operation, and corresponding vent valving and control arrangement. The method and venting arrangement are employed in a fuel cell system, for instance a vehicle propulsion system, comprising, in fluid communication, an air compressor having an outlet for providing air to the system, a combustor operative to provide combustor exhaust to the fuel processor.

Deployable Fuel Cell Power Generator - Multi-Fuel Processor

DTIC Science & Technology

2009-02-01

and the system operating pressure, while the separation efficiency depends on the evaporator design. Desulfurizer – A flow-through gas -solid or gas ...meeting the Executive Order (EO) 13423 and the Energy Policy Act of 2005 to improve energy efficiency and reduce greenhouse gas emissions 3 percent...use available fuel such as natural gas (methane) or propane. The ability to reform multitude of fuels can accelerate the introduction of more

Zeolites Remove Sulfur From Fuels

NASA Technical Reports Server (NTRS)

Voecks, Gerald E.; Sharma, Pramod K.

1991-01-01

Zeolites remove substantial amounts of sulfur compounds from diesel fuel under relatively mild conditions - atmospheric pressure below 300 degrees C. Extracts up to 60 percent of sulfur content of high-sulfur fuel. Applicable to petroleum refineries, natural-gas processors, electric powerplants, and chemical-processing plants. Method simpler and uses considerably lower pressure than current industrial method, hydro-desulfurization. Yields cleaner emissions from combustion of petroleum fuels, and protects catalysts from poisoning by sulfur.

Purifier-integrated methanol reformer for fuel cell vehicles

NASA Astrophysics Data System (ADS)

Han, Jaesung; Kim, Il-soo; Choi, Keun-Sup

We developed a compact, 3-kW, purifier-integrated modular reformer which becomes the building block of full-scale 30-kW or 50-kW methanol fuel processors for fuel cell vehicles. Our proprietary technologies regarding hydrogen purification by composite metal membrane and catalytic combustion by washcoated wire-mesh catalyst were combined with the conventional methanol steam-reforming technology, resulting in higher conversion, excellent quality of product hydrogen, and better thermal efficiency than any other systems using preferential oxidation. In this system, steam reforming, hydrogen purification, and catalytic combustion all take place in a single reactor so that the whole system is compact and easy to operate. Hydrogen from the module is ultrahigh pure (99.9999% or better), hence there is no power degradation of PEMFC stack due to contamination by CO. Also, since only pure hydrogen is supplied to the anode of the PEMFC stack, 100% hydrogen utilization is possible in the stack. The module produces 2.3 Nm 3/h of hydrogen, which is equivalent to 3 kW when PEMFC has 43% efficiency. Thermal efficiency (HHV of product H 2/HHV of MeOH in) of the module is 89% and the power density of the module is 0.77 kW/l. This work was conducted in cooperation with Hyundai Motor Company in the form of a Korean national project. Currently the module is under test with an actual fuel cell stack in order to verify its performance. Sooner or later a full-scale 30-kW system will be constructed by connecting these modules in series and parallel and will serve as the fuel processor for the Korean first fuel cell hybrid vehicle.

Waste Vegetable Oil as an Alternative Fuel for Diesel Vehicles

DTIC Science & Technology

2009-03-01

processor has a 160 gallon capacity, a fuel dryer , and features automatic mixing of the chemicals. The chemicals needed consist of lye (sodium...to distinguish it as tax-exempt. Fuel taxes are reported to the Internal Revenue Service ( IRS ) when the fuel is distributed to the “Service...collected in the commercial market. The refiner will pay the tax per gallon directly to the 22 IRS . When the fuel is sold, the end user pays the tax

Method for generating hydrogen for fuel cells

DOEpatents

Ahmed, Shabbir; Lee, Sheldon H. D.; Carter, John David; Krumpelt, Michael

2004-03-30

A method of producing a H.sub.2 rich gas stream includes supplying an O.sub.2 rich gas, steam, and fuel to an inner reforming zone of a fuel processor that includes a partial oxidation catalyst and a steam reforming catalyst or a combined partial oxidation and stream reforming catalyst. The method also includes contacting the O.sub.2 rich gas, steam, and fuel with the partial oxidation catalyst and the steam reforming catalyst or the combined partial oxidation and stream reforming catalyst in the inner reforming zone to generate a hot reformate stream. The method still further includes cooling the hot reformate stream in a cooling zone to produce a cooled reformate stream. Additionally, the method includes removing sulfur-containing compounds from the cooled reformate stream by contacting the cooled reformate stream with a sulfur removal agent. The method still further includes contacting the cooled reformate stream with a catalyst that converts water and carbon monoxide to carbon dioxide and H.sub.2 in a water-gas-shift zone to produce a final reformate stream in the fuel processor.

Analysis of the control structures for an integrated ethanol processor for proton exchange membrane fuel cell systems

NASA Astrophysics Data System (ADS)

Biset, S.; Nieto Deglioumini, L.; Basualdo, M.; Garcia, V. M.; Serra, M.

The aim of this work is to investigate which would be a good preliminary plantwide control structure for the process of Hydrogen production from bioethanol to be used in a proton exchange membrane (PEM) accounting only steady-state information. The objective is to keep the process under optimal operation point, that is doing energy integration to achieve the maximum efficiency. Ethanol, produced from renewable feedstocks, feeds a fuel processor investigated for steam reforming, followed by high- and low-temperature shift reactors and preferential oxidation, which are coupled to a polymeric fuel cell. Applying steady-state simulation techniques and using thermodynamic models the performance of the complete system with two different control structures have been evaluated for the most typical perturbations. A sensitivity analysis for the key process variables together with the rigorous operability requirements for the fuel cell are taking into account for defining acceptable plantwide control structure. This is the first work showing an alternative control structure applied to this kind of process.

Fuzzy Logic Based Controller for a Grid-Connected Solid Oxide Fuel Cell Power Plant.

PubMed

Chatterjee, Kalyan; Shankar, Ravi; Kumar, Amit

2014-10-01

This paper describes a mathematical model of a solid oxide fuel cell (SOFC) power plant integrated in a multimachine power system. The utilization factor of a fuel stack maintains steady state by tuning the fuel valve in the fuel processor at a rate proportional to a current drawn from the fuel stack. A suitable fuzzy logic control is used for the overall system, its objective being controlling the current drawn by the power conditioning unit and meet a desirable output power demand. The proposed control scheme is verified through computer simulations.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sargent, S.A.

Apple pomace or presscake, was evaluated for suitability as a boiler feedstock for Michigan firms processing apple juice. Based upon the physical and chemical characteristics of pomace, handling/direct combustion systems were selected to conform with operating parameters typical of the industry. Fresh pomace flow rates of 29,030 and 88,998 kg/day (64,000 and 194,000 lb/day) were considered as representative of small and large processors, respectively, and the material was assumed to be dried to 15% moisture content (wet basis) prior to storage and combustion. Boilers utilizing pile-burning, fluidized-bed-combustion, and suspension-firing technologies were sized for each flow rate, resulting in energy productionmore » of 2930 and 8790 kW (10 and 30 million Btu/h), respectively. A life-cycle cost analysis was performed giving Average Annual Costs for the three handling/combustion system combinations (based on the Uniform Capital Recovery factor). An investment loan at 16% interest with a 5-year payback period was assumed. The break-even period for annual costs was calculated by anticipated savings incurred through reduction of fossil-fuel costs during a 5-month processing season. Large processors, producing more than 88,998 kg pomace/day, could economically convert to a suspension-fired system substituting for fuel oil, with break-even occurring after 4 months of operation of pomace per year. Small processors, producing less than 29,030 kg/day, could not currently convert to pomace combustion systems given these economic circumstances. A doubling of electrical-utility costs and changes in interest rates from 10 to 20% per year had only slight effects on the recovery of Average Annual Costs. Increases in fossil-fuel prices and the necessity to pay for pomace disposal reduced the cost-recovery period for all systems, making some systems feasible for small processors. 39 references, 13 figures, 10 tables.« less

Plant That Makes Fuel Out Of Garbage and Waste Called A Success

Science.gov Websites

, to run a turbine to generate electricity or as a transportation fuel. Pathogens in the food municipal solid waste and food processing wastes. The plant was operated close to neighbors in a light market of $1 billion. Other potential customers include food processors and waste haulers, who must now

Fuel processor for fuel cell power system

DOEpatents

Vanderborgh, Nicholas E.; Springer, Thomas E.; Huff, James R.

1987-01-01

A catalytic organic fuel processing apparatus, which can be used in a fuel cell power system, contains within a housing a catalyst chamber, a variable speed fan, and a combustion chamber. Vaporized organic fuel is circulated by the fan past the combustion chamber with which it is in indirect heat exchange relationship. The heated vaporized organic fuel enters a catalyst bed where it is converted into a desired product such as hydrogen needed to power the fuel cell. During periods of high demand, air is injected upstream of the combustion chamber and organic fuel injection means to burn with some of the organic fuel on the outside of the combustion chamber, and thus be in direct heat exchange relation with the organic fuel going into the catalyst bed.

DIissolution of low enriched uranium from the experimental breeder reactor-II fuel stored at the Idaho National Laboratory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Daniel, G.; Rudisill, T.; Almond, P.

The Idaho National Laboratory (INL) is actively engaged in the development of electrochemical processing technology for the treatment of fast reactor fuels using irradiated fuel from the Experimental Breeder Reactor-II (EBR-II) as the primary test material. The research and development (R&D) activities generate a low enriched uranium (LEU) metal product from the electrorefining of the EBR-II fuel and the subsequent consolidation and removal of chloride salts by the cathode processor. The LEU metal ingots from past R&D activities are currently stored at INL awaiting disposition. One potential disposition pathway is the shipment of the ingots to the Savannah River Sitemore » (SRS) for dissolution in H-Canyon. Carbon steel cans containing the LEU metal would be loaded into reusable charging bundles in the H-Canyon Crane Maintenance Area and charged to the 6.4D or 6.1D dissolver. The LEU dissolution would be accomplished as the final charge in a dissolver batch (following the dissolution of multiple charges of spent nuclear fuel (SNF)). The solution would then be purified and the 235U enrichment downblended to allow use of the U in commercial reactor fuel. To support this potential disposition path, the Savannah River National Laboratory (SRNL) developed a dissolution flowsheet for the LEU using samples of the material received from INL.« less

Performance and economic assessments of a solid oxide fuel cell system with a two-step ethanol-steam-reforming process using CaO sorbent

NASA Astrophysics Data System (ADS)

Tippawan, Phanicha; Arpornwichanop, Amornchai

2016-02-01

The hydrogen production process is known to be important to a fuel cell system. In this study, a carbon-free hydrogen production process is proposed by using a two-step ethanol-steam-reforming procedure, which consists of ethanol dehydrogenation and steam reforming, as a fuel processor in the solid oxide fuel cell (SOFC) system. An addition of CaO in the reformer for CO2 capture is also considered to enhance the hydrogen production. The performance of the SOFC system is analyzed under thermally self-sufficient conditions in terms of the technical and economic aspects. The simulation results show that the two-step reforming process can be run in the operating window without carbon formation. The addition of CaO in the steam reformer, which runs at a steam-to-ethanol ratio of 5, temperature of 900 K and atmospheric pressure, minimizes the presence of CO2; 93% CO2 is removed from the steam-reforming environment. This factor causes an increase in the SOFC power density of 6.62%. Although the economic analysis shows that the proposed fuel processor provides a higher capital cost, it offers a reducing active area of the SOFC stack and the most favorable process economics in term of net cost saving.

Compact hydrogen production systems for solid polymer fuel cells

NASA Astrophysics Data System (ADS)

Ledjeff-Hey, K.; Formanski, V.; Kalk, Th.; Roes, J.

Generally there are several ways to produce hydrogen gas from carbonaceous fuels like natural gas, oil or alcohols. Most of these processes are designed for large-scale industrial production and are not suitable for a compact hydrogen production system (CHYPS) in the power range of 1 kW. In order to supply solid polymer fuel cells (SPFC) with hydrogen, a compact fuel processor is required for mobile applications. The produced hydrogen-rich gas has to have a low level of harmful impurities; in particular the carbon monoxide content has to be lower than 20 ppmv. Integrating the reaction step, the gas purification and the heat supply leads to small-scale hydrogen production systems. The steam reforming of methanol is feasible at copper catalysts in a low temperature range of 200-350°C. The combination of a small-scale methanol reformer and a metal membrane as purification step forms a compact system producing high-purity hydrogen. The generation of a SPFC hydrogen fuel gas can also be performed by thermal or catalytic cracking of liquid hydrocarbons such as propane. At a temperature of 900°C the decomposition of propane into carbon and hydrogen takes place. A fuel processor based on this simple concept produces a gas stream with a hydrogen content of more than 90 vol.% and without CO and CO2.

Design of a Fuel Processor System for Generating Hydrogen for Automotive Applications

ERIC Educational Resources Information Center

Kolavennu, Panini K.; Telotte, John C.; Palanki, Srinivas

2006-01-01

The objective of this paper is to design a train of tubular reactors that use a methane feed to produce hydrogen of the desired purity so that it can be utilized by a fuel cell for automotive applications. Reaction engineering principles, which are typically covered at the undergraduate level, are utilized to design this reactor train. It is shown…

Fuel processor for fuel cell power system. [Conversion of methanol into hydrogen

DOEpatents

Vanderborgh, N.E.; Springer, T.E.; Huff, J.R.

1986-01-28

A catalytic organic fuel processing apparatus, which can be used in a fuel cell power system, contains within a housing a catalyst chamber, a variable speed fan, and a combustion chamber. Vaporized organic fuel is circulated by the fan past the combustion chamber with which it is in indirect heat exchange relationship. The heated vaporized organic fuel enters a catalyst bed where it is converted into a desired product such as hydrogen needed to power the fuel cell. During periods of high demand, air is injected upstream of the combustion chamber and organic fuel injection means to burn with some of the organic fuel on the outside of the combustion chamber, and thus be in direct heat exchange relation with the organic fuel going into the catalyst bed.

Assessment and comparison of 100-MW coal gasification phosphoric acid fuel cell power plants

NASA Technical Reports Server (NTRS)

Lu, Cheng-Yi

1988-01-01

One of the advantages of fuel cell (FC) power plants is fuel versatility. With changes only in the fuel processor, the power plant will be able to accept a variety of fuels. This study was performed to design process diagrams, evaluate performance, and to estimate cost of 100 MW coal gasifier (CG)/phosphoric acid fuel cell (PAFC) power plant systems utilizing coal, which is the largest single potential source of alternate hydrocarbon liquids and gases in the United States, as the fuel. Results of this study will identify the most promising integrated CG/PAFC design and its near-optimal operating conditions. The comparison is based on the performance and cost of electricity which is calculated under consistent financial assumptions.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sargent, S.A.; Pierson, T.R.; Steffe, J.F.

Apple juice processors generating up to 100 ton/day (90,718 kg/day) of pomace and incurring no disposal costs could not economically invest in a pile burning, fluidized-bed or suspension-fired system at present fossil fuel costs. Cost analysis is warranted for situations in which disposal costs are greater than $9.15/ton ($8.30/1000 kg) or in which fossil fuel price increases are expected in excess of 25%.

Fuel Cell/Reformers Technology Development

NASA Technical Reports Server (NTRS)

2004-01-01

NASA Glenn Research Center is interested in developing Solid Oxide Fuel Cell for use in aerospace applications. Solid oxide fuel cell requires hydrogen rich feed stream by converting commercial aviation jet fuel in a fuel processing process. The grantee's primary research activities center on designing and constructing a test facility for evaluating injector concepts to provide optimum feeds to fuel processor; collecting and analyzing literature information on fuel processing and desulfurization technologies; establishing industry and academic contacts in related areas; providing technical support to in-house SOFC-based system studies. Fuel processing is a chemical reaction process that requires efficient delivery of reactants to reactor beds for optimum performance, i.e., high conversion efficiency and maximum hydrogen production, and reliable continuous operation. Feed delivery and vaporization quality can be improved by applying NASA's expertise in combustor injector design. A 10 KWe injector rig has been designed, procured, and constructed to provide a tool to employ laser diagnostic capability to evaluate various injector concepts for fuel processing reactor feed delivery application. This injector rig facility is now undergoing mechanical and system check-out with an anticipated actual operation in July 2004. Multiple injector concepts including impinging jet, venturi mixing, discrete jet, will be tested and evaluated with actual fuel mixture compatible with reforming catalyst requirement. Research activities from September 2002 to the closing of this collaborative agreement have been in the following areas: compiling literature information on jet fuel reforming; conducting autothermal reforming catalyst screening; establishing contacts with other government agencies for collaborative research in jet fuel reforming and desulfurization; providing process design basis for the build-up of injector rig facility and individual injector design.

The computational structural mechanics testbed generic structural-element processor manual

NASA Technical Reports Server (NTRS)

Stanley, Gary M.; Nour-Omid, Shahram

1990-01-01

The usage and development of structural finite element processors based on the CSM Testbed's Generic Element Processor (GEP) template is documented. By convention, such processors have names of the form ESi, where i is an integer. This manual is therefore intended for both Testbed users who wish to invoke ES processors during the course of a structural analysis, and Testbed developers who wish to construct new element processors (or modify existing ones).

Graphics enhanced computer emulation for improved timing-race and fault tolerance control system analysis. [of Centaur liquid-fuel booster

NASA Technical Reports Server (NTRS)

Szatkowski, G. P.

1983-01-01

A computer simulation system has been developed for the Space Shuttle's advanced Centaur liquid fuel booster rocket, in order to conduct systems safety verification and flight operations training. This simulation utility is designed to analyze functional system behavior by integrating control avionics with mechanical and fluid elements, and is able to emulate any system operation, from simple relay logic to complex VLSI components, with wire-by-wire detail. A novel graphics data entry system offers a pseudo-wire wrap data base that can be easily updated. Visual subsystem operations can be selected and displayed in color on a six-monitor graphics processor. System timing and fault verification analyses are conducted by injecting component fault modes and min/max timing delays, and then observing system operation through a red line monitor.

Processing of thermionic power on an electrically propelled spacecraft

NASA Technical Reports Server (NTRS)

Macie, T. W.

1973-01-01

A study to define the power processing equipment required between a thermionic reactor and an array of mercury-ion thrusters for a nuclear electric propulsion system is reported. Observations and recommendations that resulted from this study were: (1) the preferred thermionic-fuel-element source voltages are 23 V or higher; (2) transistor characteristics exert a strong effect on power processor mass; (3) the power processor mass could be considerably reduced should the magnetic materials that exhibit low losses at high frequencies, that have a high Curie point, and that can operate at 15 to 20 kG become avaliable; (4) electrical component packaging on the radiator could reduce the area that is sensitive to meteoroid penetration, thereby reducing the meteoroid shielding mass requirement; (5) an experimental model of the power processor design should be built and tested to verify the efficiencies, masses, and all the automatic operational aspects of the design.

A Methodology for Distributing the Corporate Database.

ERIC Educational Resources Information Center

McFadden, Fred R.

The trend to distributed processing is being fueled by numerous forces, including advances in technology, corporate downsizing, increasing user sophistication, and acquisitions and mergers. Increasingly, the trend in corporate information systems (IS) departments is toward sharing resources over a network of multiple types of processors, operating…

77 FR 72746 - Regulation of Fuels and Fuel Additives: Modifications to Renewable Fuel Standard and Diesel...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-12-06

...EPA published a direct final rule on October 9, 2012 to amend the definition of heating oil in 40 CFR 80.1401 in the Renewable Fuel Standard (``RFS'') program under section 211(o) of the Clean Air Act. The direct final rule also amended requirements under EPA's diesel sulfur program related to the sulfur content of locomotive and marine diesel fuel produced by transmix processors, and the fuel marker requirements for 500 ppm sulfur locomotive and marine (LM) diesel fuel to allow for solvent yellow 124 marker to transition out of the distribution system. Because EPA received adverse comments on the heating oil definition and transmix amendments, we are withdrawing those portions of the direct final rule. Because EPA did not receive adverse comments with respect to the yellow marker amendments, those amendments will become effective as indicated in the direct final rule.

Simulink/PARS Integration Support

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vacaliuc, B.; Nakhaee, N.

2013-12-18

The state of the art for signal processor hardware has far out-paced the development tools for placing applications on that hardware. In addition, signal processors are available in a variety of architectures, each uniquely capable of handling specific types of signal processing efficiently. With these processors becoming smaller and demanding less power, it has become possible to group multiple processors, a heterogeneous set of processors, into single systems. Different portions of the desired problem set can be assigned to different processor types as appropriate. As software development tools do not keep pace with these processors, especially when multiple processors ofmore » different types are used, a method is needed to enable software code portability among multiple processors and multiple types of processors along with their respective software environments. Sundance DSP, Inc. has developed a software toolkit called “PARS”, whose objective is to provide a framework that uses suites of tools provided by different vendors, along with modeling tools and a real time operating system, to build an application that spans different processor types. The software language used to express the behavior of the system is a very high level modeling language, “Simulink”, a MathWorks product. ORNL has used this toolkit to effectively implement several deliverables. This CRADA describes this collaboration between ORNL and Sundance DSP, Inc.« less

Baseband processor development for the Advanced Communications Satellite Program

NASA Technical Reports Server (NTRS)

Moat, D.; Sabourin, D.; Stilwell, J.; Mccallister, R.; Borota, M.

1982-01-01

An onboard-baseband-processor concept for a satellite-switched time-division-multiple-access (SS-TDMA) communication system was developed for NASA Lewis Research Center. The baseband processor routes and controls traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband-processor design are being verified in a baseband-processor proof-of-concept model. These technology developments include serial MSK modems, Clos-type baseband routing switch, a single-chip CMOS maximum-likelihood convolutional decoder, and custom LSL implementation of high-speed, low-power ECL building blocks.

Effect of poor control of film processors on mammographic image quality.

PubMed

Kimme-Smith, C; Sun, H; Bassett, L W; Gold, R H

1992-11-01

With the increasingly stringent standards of image quality in mammography, film processor quality control is especially important. Current methods are not sufficient for ensuring good processing. The authors used a sensitometer and densitometer system to evaluate the performance of 22 processors at 16 mammographic facilities. Standard sensitometric values of two films were established, and processor performance was assessed for variations from these standards. Developer chemistry of each processor was analyzed and correlated with its sensitometric values. Ten processors were retested, and nine were found to be out of calibration. The developer components of hydroquinone, sulfites, bromide, and alkalinity varied the most, and low concentrations of hydroquinone were associated with lower average gradients at two facilities. Use of the sensitometer and densitometer system helps identify out-of-calibration processors, but further study is needed to correlate sensitometric values with developer component values. The authors believe that present quality control would be improved if sensitometric or other tests could be used to identify developer components that are out of calibration.

40 CFR 279.70 - Applicability.

Code of Federal Regulations, 2010 CFR

2010-07-01

... THE MANAGEMENT OF USED OIL Standards for Used Oil Fuel Marketers § 279.70 Applicability. (a) Any... forth in § 279.11. (b) The following persons are not marketers subject to this subpart: (1) Used oil... oil to processor/re-refiners who incidentally burn used oil are not marketers subject to this Subpart...

Onboard fuel reformers for fuel cell vehicles: Equilibrium, kinetic and system modeling

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kreutz, T.G.; Steinbugler, M.M.; Ogden, J.M.

1996-12-31

On-board reforming of liquid fuels to hydrogen for use in proton exchange membrane (PEM) fuel cell electric vehicles (FCEVs) has been the subject of numerous investigations. In many respects, liquid fuels represent a more attractive method of carrying hydrogen than compressed hydrogen itself, promising greater vehicle range, shorter refilling times, increased safety, and perhaps most importantly, utilization of the current fuel distribution infrastructure. The drawbacks of on-board reformers include their inherent complexity [for example a POX reactor includes: a fuel vaporizer, a reformer, water-gas shift reactors, a preferential oxidation (PROX) unit for CO cleanup, heat exchangers for thermal integration, sensorsmore » and controls, etc.], weight, and expense relative to compressed H{sub 2}, as well as degraded fuel cell performance due to the presence of inert gases and impurities in the reformate. Partial oxidation (POX) of automotive fuels is another alternative for hydrogen production. This paper provides an analysis of POX reformers and a fuel economy comparison of vehicles powered by on-board POX and SRM fuel processors.« less

Fuel-rich catalytic combustion: A fuel processor for high-speed propulsion

NASA Technical Reports Server (NTRS)

Brabbs, Theodore A.; Rollbuhler, R. James; Lezberg, Erwin A.

1990-01-01

Fuel-rich catalytic combustion of Jet-A fuel was studied over the equivalence ratio range 4.7 to 7.8, which yielded combustion temperatures of 1250 to 1060 K. The process was soot-free and the gaseous products were similar to those obtained in the iso-octane study. A carbon atom balance across the catalyst bed calculated for the gaseous products accounted for about 70 to 90 percent of the fuel carbon; the balance was condensed as a liquid in the cold trap. It was shown that 52 to 77 percent of the fuel carbon was C1, C2, and C3 molecules. The viability of using fuel-rich catalytic combustion as a technique for preheating a practical fuel to very high temperatures was demonstrated. Preliminary results from the scaled up version of the catalytic combustor produced a high-temperature fuel containing large amounts of hydrogen and carbon monoxide. The balance of the fuel was completely vaporized and in various stages of pyrolysis and oxidation. Visual observations indicate that there was no soot present.

Present Status and Extensions of the Monte Carlo Performance Benchmark

NASA Astrophysics Data System (ADS)

Hoogenboom, J. Eduard; Petrovic, Bojan; Martin, William R.

2014-06-01

The NEA Monte Carlo Performance benchmark started in 2011 aiming to monitor over the years the abilities to perform a full-size Monte Carlo reactor core calculation with a detailed power production for each fuel pin with axial distribution. This paper gives an overview of the contributed results thus far. It shows that reaching a statistical accuracy of 1 % for most of the small fuel zones requires about 100 billion neutron histories. The efficiency of parallel execution of Monte Carlo codes on a large number of processor cores shows clear limitations for computer clusters with common type computer nodes. However, using true supercomputers the speedup of parallel calculations is increasing up to large numbers of processor cores. More experience is needed from calculations on true supercomputers using large numbers of processors in order to predict if the requested calculations can be done in a short time. As the specifications of the reactor geometry for this benchmark test are well suited for further investigations of full-core Monte Carlo calculations and a need is felt for testing other issues than its computational performance, proposals are presented for extending the benchmark to a suite of benchmark problems for evaluating fission source convergence for a system with a high dominance ratio, for coupling with thermal-hydraulics calculations to evaluate the use of different temperatures and coolant densities and to study the correctness and effectiveness of burnup calculations. Moreover, other contemporary proposals for a full-core calculation with realistic geometry and material composition will be discussed.

Reactant gas composition for fuel cell potential control

DOEpatents

Bushnell, Calvin L.; Davis, Christopher L.

1991-01-01

A fuel cell (10) system in which a nitrogen (N.sub.2) gas is used on the anode section (11) and a nitrogen/oxygen (N.sub.2 /O.sub.2) gaseous mix is used on the cathode section (12) to maintain the cathode at an acceptable voltage potential during adverse conditions occurring particularly during off-power conditions, for example, during power plant shutdown, start-up and hot holds. During power plant shutdown, the cathode section is purged with a gaseous mixture of, for example, one-half percent (0.5%) oxygen (O.sub.2) and ninety-nine and a half percent (99.5%) nitrogen (N.sub.2) supplied from an ejector (21) bleeding in air (24/28) into a high pressure stream (27) of nitrogen (N.sub.2) as the primary or majority gas. Thereafter the fuel gas in the fuel processor (31) and the anode section (11) is purged with nitrogen gas to prevent nickel (Ni) carbonyl from forming from the shift catalyst. A switched dummy electrical load (30) is used to bring the cathode potential down rapidly during the start of the purges. The 0.5%/99.5% O.sub.2 /N.sub.2 mixture maintains the cathode potential between 0.3 and 0.7 volts, and this is sufficient to maintain the cathode potential at 0.3 volts for the case of H.sub.2 diffusing to the cathode through a 2 mil thick electrolyte filled matrix and below 0.8 volts for no diffusion at open circuit conditions. The same high pressure gas source (20) is used via a "T" juncture ("T") to purge the anode section and its associated fuel processor (31).

Yes! An object-oriented compiler compiler (YOOCC)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Avotins, J.; Mingins, C.; Schmidt, H.

1995-12-31

Grammar-based processor generation is one of the most widely studied areas in language processor construction. However, there have been very few approaches to date that reconcile object-oriented principles, processor generation, and an object-oriented language. Pertinent here also. is that currently to develop a processor using the Eiffel Parse libraries requires far too much time to be expended on tasks that can be automated. For these reasons, we have developed YOOCC (Yes! an Object-Oriented Compiler Compiler), which produces a processor framework from a grammar using an enhanced version of the Eiffel Parse libraries, incorporating the ideas hypothesized by Meyer, and Grapemore » and Walden, as well as many others. Various essential changes have been made to the Eiffel Parse libraries. Examples are presented to illustrate the development of a processor using YOOCC, and it is concluded that the Eiffel Parse libraries are now not only an intelligent, but also a productive option for processor construction.« less

Towards implementation of cellular automata in Microbial Fuel Cells.

PubMed

Tsompanas, Michail-Antisthenis I; Adamatzky, Andrew; Sirakoulis, Georgios Ch; Greenman, John; Ieropoulos, Ioannis

2017-01-01

The Microbial Fuel Cell (MFC) is a bio-electrochemical transducer converting waste products into electricity using microbial communities. Cellular Automaton (CA) is a uniform array of finite-state machines that update their states in discrete time depending on states of their closest neighbors by the same rule. Arrays of MFCs could, in principle, act as massive-parallel computing devices with local connectivity between elementary processors. We provide a theoretical design of such a parallel processor by implementing CA in MFCs. We have chosen Conway's Game of Life as the 'benchmark' CA because this is the most popular CA which also exhibits an enormously rich spectrum of patterns. Each cell of the Game of Life CA is realized using two MFCs. The MFCs are linked electrically and hydraulically. The model is verified via simulation of an electrical circuit demonstrating equivalent behaviours. The design is a first step towards future implementations of fully autonomous biological computing devices with massive parallelism. The energy independence of such devices counteracts their somewhat slow transitions-compared to silicon circuitry-between the different states during computation.

Towards implementation of cellular automata in Microbial Fuel Cells

PubMed Central

Adamatzky, Andrew; Sirakoulis, Georgios Ch.; Greenman, John; Ieropoulos, Ioannis

2017-01-01

The Microbial Fuel Cell (MFC) is a bio-electrochemical transducer converting waste products into electricity using microbial communities. Cellular Automaton (CA) is a uniform array of finite-state machines that update their states in discrete time depending on states of their closest neighbors by the same rule. Arrays of MFCs could, in principle, act as massive-parallel computing devices with local connectivity between elementary processors. We provide a theoretical design of such a parallel processor by implementing CA in MFCs. We have chosen Conway’s Game of Life as the ‘benchmark’ CA because this is the most popular CA which also exhibits an enormously rich spectrum of patterns. Each cell of the Game of Life CA is realized using two MFCs. The MFCs are linked electrically and hydraulically. The model is verified via simulation of an electrical circuit demonstrating equivalent behaviours. The design is a first step towards future implementations of fully autonomous biological computing devices with massive parallelism. The energy independence of such devices counteracts their somewhat slow transitions—compared to silicon circuitry—between the different states during computation. PMID:28498871

Flood replenishment: a new method of processor control.

PubMed

Frank, E D; Gray, J E; Wilken, D A

1980-01-01

In mechanized radiographic film processors that process medium to low volumes of film, roll films, and those that process single-emulsion films from nuclear medicine scans, computed tomography, and ultrasound, it is difficult to maintain the developer solution at a stable processing level. We describe our experience using flood replenishment, which is a method in which developer replenisher containing starter solution is introduced in the processor at timed intervals, independent of the number of films being processed. By this process, a stable level of developer activity is maintained in a processor used to develop a medium to low volume of single-emulsion film.

Hypercluster - Parallel processing for computational mechanics

NASA Technical Reports Server (NTRS)

Blech, Richard A.

1988-01-01

An account is given of the development status, performance capabilities and implications for further development of NASA-Lewis' testbed 'hypercluster' parallel computer network, in which multiple processors communicate through a shared memory. Processors have local as well as shared memory; the hypercluster is expanded in the same manner as the hypercube, with processor clusters replacing the normal single processor node. The NASA-Lewis machine has three nodes with a vector personality and one node with a scalar personality. Each of the vector nodes uses four board-level vector processors, while the scalar node uses four general-purpose microcomputer boards.

System support software for the Space Ultrareliable Modular Computer (SUMC)

NASA Technical Reports Server (NTRS)

Hill, T. E.; Hintze, G. C.; Hodges, B. C.; Austin, F. A.; Buckles, B. P.; Curran, R. T.; Lackey, J. D.; Payne, R. E.

1974-01-01

The highly transportable programming system designed and implemented to support the development of software for the Space Ultrareliable Modular Computer (SUMC) is described. The SUMC system support software consists of program modules called processors. The initial set of processors consists of the supervisor, the general purpose assembler for SUMC instruction and microcode input, linkage editors, an instruction level simulator, a microcode grid print processor, and user oriented utility programs. A FORTRAN 4 compiler is undergoing development. The design facilitates the addition of new processors with a minimum effort and provides the user quasi host independence on the ground based operational software development computer. Additional capability is provided to accommodate variations in the SUMC architecture without consequent major modifications in the initial processors.

Energy and exergy analysis of an ethanol reforming process for solid oxide fuel cell applications.

PubMed

Tippawan, Phanicha; Arpornwichanop, Amornchai

2014-04-01

The fuel processor in which hydrogen is produced from fuels is an important unit in a fuel cell system. The aim of this study is to apply a thermodynamic concept to identify a suitable reforming process for an ethanol-fueled solid oxide fuel cell (SOFC). Three different reforming technologies, i.e., steam reforming, partial oxidation and autothermal reforming, are considered. The first and second laws of thermodynamics are employed to determine an energy demand and to describe how efficiently the energy is supplied to the reforming process. Effect of key operating parameters on the distribution of reforming products, such as H2, CO, CO2 and CH4, and the possibility of carbon formation in different ethanol reformings are examined as a function of steam-to-ethanol ratio, oxygen-to-ethanol ratio and temperatures at atmospheric pressure. Energy and exergy analysis are performed to identify the best ethanol reforming process for SOFC applications. Copyright © 2014 Elsevier Ltd. All rights reserved.

The software system development for the TAMU real-time fan beam scatterometer data processors

NASA Technical Reports Server (NTRS)

Clark, B. V.; Jean, B. R.

1980-01-01

A software package was designed and written to process in real-time any one quadrature channel pair of radar scatterometer signals form the NASA L- or C-Band radar scatterometer systems. The software was successfully tested in the C-Band processor breadboard hardware using recorded radar and NERDAS (NASA Earth Resources Data Annotation System) signals as the input data sources. The processor development program and the overall processor theory of operation and design are described. The real-time processor software system is documented and the results of the laboratory software tests, and recommendations for the efficient application of the data processing capabilities are presented.

40 CFR 86.107-98 - Sampling and analytical system.

Code of Federal Regulations, 2010 CFR

2010-07-01

... automatic sealing opening of the boot during fueling. There shall be no loss in the gas tightness of the... system (recorder and sensor) shall have an accuracy of ±3 °F (±1.7 °C). The recorder (data processor... ambient temperature sensors, connected to provide one average output, located 3 feet above the floor at...

40 CFR 86.107-98 - Sampling and analytical system.

Code of Federal Regulations, 2011 CFR

2011-07-01

... automatic sealing opening of the boot during fueling. There shall be no loss in the gas tightness of the... system (recorder and sensor) shall have an accuracy of ±3 °F (±1.7 °C). The recorder (data processor... ambient temperature sensors, connected to provide one average output, located 3 feet above the floor at...

Comparison of mechanized systems for thinning Ponderosa pine and mixed conifer stands

Treesearch

Bruce R. Hartsough; Joseph F. McNeel; Thomas A. Durston; Bryce J. Stokes

1994-01-01

We studied three systems for thinning pine plantations and naturally-regenerated stands on the Stanislaus National Forest, California. All three produced small sawlogs and fuel chips. The whole tree system consisted of a feller buncher, skidder, stroke processor, loader and chipper. The cut-to-length system included a harvester, forwarder, loader and chipper. A hybrid...

Comparison of mechanized systems for thinning Ponderosa pine and mixed conifer stands

Treesearch

Bruce R. Hartsough; Joseph F. McNeel; Thomas A. Durston; Bryce J. Stokes

1994-01-01

Three systems for thinning pine plantations and naturally-regenerated stands were studied. All three produced small sawlogs and fuel chips. The whole-tree system consisted of a feller buncher, skidder, stroke processor, loader, and chipper. The cut-to-length system included a harvester, forwarder, loader, and chipper. A hybrid system combined a feller buncher,...

Effect of high oleic acid soybean on seed oil, protein concentration, and yield

USDA-ARS?s Scientific Manuscript database

Soybeans with high oleic acid content are desired by oil processors because of their improved oxidative stability for broader use in food, fuel and other products. However, non-GMO high-oleic soybeans have tended to have low seed yield. The objective of this study was to test non-GMO, high-oleic s...

Extended performance electric propulsion power processor design study. Volume 1: Executive summary

NASA Technical Reports Server (NTRS)

Biess, J. J.; Inouye, L. Y.; Schoenfeld, A. D.

1977-01-01

Several power processor design concepts were evaluated and compared. Emphasis was placed on a 30cm ion thruster power processor with a beam supply rating of 2.2kW to 10kW. Extensions in power processor performance were defined and were designed in sufficient detail to determine efficiency, component weight, part count, reliability and thermal control. Preliminary electrical design, mechanical design, and thermal analysis were performed on a 6kW power transformer for the beam supply. Bi-Mod mechanical, structural, and thermal control configurations were evaluated for the power processor, and preliminary estimates of mechanical weight were determined. A program development plan was formulated that outlines the work breakdown structure for the development, qualification and fabrication of the power processor flight hardware.

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

NASA Astrophysics Data System (ADS)

Barr, David R. W.; Dudek, Piotr

2009-12-01

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

Rapid prototyping and evaluation of programmable SIMD SDR processors in LISA

NASA Astrophysics Data System (ADS)

Chen, Ting; Liu, Hengzhu; Zhang, Botao; Liu, Dongpei

2013-03-01

With the development of international wireless communication standards, there is an increase in computational requirement for baseband signal processors. Time-to-market pressure makes it impossible to completely redesign new processors for the evolving standards. Due to its high flexibility and low power, software defined radio (SDR) digital signal processors have been proposed as promising technology to replace traditional ASIC and FPGA fashions. In addition, there are large numbers of parallel data processed in computation-intensive functions, which fosters the development of single instruction multiple data (SIMD) architecture in SDR platform. So a new way must be found to prototype the SDR processors efficiently. In this paper we present a bit-and-cycle accurate model of programmable SIMD SDR processors in a machine description language LISA. LISA is a language for instruction set architecture which can gain rapid model at architectural level. In order to evaluate the availability of our proposed processor, three common baseband functions, FFT, FIR digital filter and matrix multiplication have been mapped on the SDR platform. Analytical results showed that the SDR processor achieved the maximum of 47.1% performance boost relative to the opponent processor.

New Modular Ultrasonic Signal Processing Building Blocks for Real-Time Data Acquisition and Post Processing

NASA Astrophysics Data System (ADS)

Weber, Walter H.; Mair, H. Douglas; Jansen, Dion

2003-03-01

A suite of basic signal processors has been developed. These basic building blocks can be cascaded together to form more complex processors without the need for programming. The data structures between each of the processors are handled automatically. This allows a processor built for one purpose to be applied to any type of data such as images, waveform arrays and single values. The processors are part of Winspect Data Acquisition software. The new processors are fast enough to work on A-scan signals live while scanning. Their primary use is to extract features, reduce noise or to calculate material properties. The cascaded processors work equally well on live A-scan displays, live gated data or as a post-processing engine on saved data. Researchers are able to call their own MATLAB or C-code from anywhere within the processor structure. A built-in formula node processor that uses a simple algebraic editor may make external user programs unnecessary. This paper also discusses the problems associated with ad hoc software development and how graphical programming languages can tie up researchers writing software rather than designing experiments.

Enabling Future Robotic Missions with Multicore Processors

NASA Technical Reports Server (NTRS)

Powell, Wesley A.; Johnson, Michael A.; Wilmot, Jonathan; Some, Raphael; Gostelow, Kim P.; Reeves, Glenn; Doyle, Richard J.

2011-01-01

Recent commercial developments in multicore processors (e.g. Tilera, Clearspeed, HyperX) have provided an option for high performance embedded computing that rivals the performance attainable with FPGA-based reconfigurable computing architectures. Furthermore, these processors offer more straightforward and streamlined application development by allowing the use of conventional programming languages and software tools in lieu of hardware design languages such as VHDL and Verilog. With these advantages, multicore processors can significantly enhance the capabilities of future robotic space missions. This paper will discuss these benefits, along with onboard processing applications where multicore processing can offer advantages over existing or competing approaches. This paper will also discuss the key artchitecural features of current commercial multicore processors. In comparison to the current art, the features and advancements necessary for spaceflight multicore processors will be identified. These include power reduction, radiation hardening, inherent fault tolerance, and support for common spacecraft bus interfaces. Lastly, this paper will explore how multicore processors might evolve with advances in electronics technology and how avionics architectures might evolve once multicore processors are inserted into NASA robotic spacecraft.

Multiprocessing on supercomputers for computational aerodynamics

NASA Technical Reports Server (NTRS)

Yarrow, Maurice; Mehta, Unmeel B.

1990-01-01

Very little use is made of multiple processors available on current supercomputers (computers with a theoretical peak performance capability equal to 100 MFLOPs or more) in computational aerodynamics to significantly improve turnaround time. The productivity of a computer user is directly related to this turnaround time. In a time-sharing environment, the improvement in this speed is achieved when multiple processors are used efficiently to execute an algorithm. The concept of multiple instructions and multiple data (MIMD) through multi-tasking is applied via a strategy which requires relatively minor modifications to an existing code for a single processor. Essentially, this approach maps the available memory to multiple processors, exploiting the C-FORTRAN-Unix interface. The existing single processor code is mapped without the need for developing a new algorithm. The procedure for building a code utilizing this approach is automated with the Unix stream editor. As a demonstration of this approach, a Multiple Processor Multiple Grid (MPMG) code is developed. It is capable of using nine processors, and can be easily extended to a larger number of processors. This code solves the three-dimensional, Reynolds averaged, thin-layer and slender-layer Navier-Stokes equations with an implicit, approximately factored and diagonalized method. The solver is applied to generic oblique-wing aircraft problem on a four processor Cray-2 computer. A tricubic interpolation scheme is developed to increase the accuracy of coupling of overlapped grids. For the oblique-wing aircraft problem, a speedup of two in elapsed (turnaround) time is observed in a saturated time-sharing environment.

Automatic film processors' quality control test in Greek military hospitals.

PubMed

Lymberis, C; Efstathopoulos, E P; Manetou, A; Poudridis, G

1993-04-01

The two major military radiology installations (Athens, Greece) using a total of 15 automatic film processors were assessed using the 21-step-wedge method. The results of quality control in all these processors are presented. The parameters measured under actual working conditions were base and fog, contrast and speed. Base and fog as well as speed displayed large variations with average values generally higher than acceptable, whilst contrast displayed greater stability. Developer temperature was measured daily during the test and was found to be outside the film manufacturers' recommended limits in nine of the 15 processors. In only one processor did film passing time vary on an every day basis and this was due to maloperation. Developer pH test was not part of the daily monitoring service being performed every 5 days for each film processor and found to be in the range 9-12; 10 of the 15 processors presented pH values outside the limits specified by the film manufacturers.

Evaluation of gasification and novel thermal processes for the treatment of municipal solid waste

DOE Office of Scientific and Technical Information (OSTI.GOV)

Niessen, W.R.; Marks, C.H.; Sommerlad, R.E.

1996-08-01

This report identifies seven developers whose gasification technologies can be used to treat the organic constituents of municipal solid waste: Energy Products of Idaho; TPS Termiska Processor AB; Proler International Corporation; Thermoselect Inc.; Battelle; Pedco Incorporated; and ThermoChem, Incorporated. Their processes recover heat directly, produce a fuel product, or produce a feedstock for chemical processes. The technologies are on the brink of commercial availability. This report evaluates, for each technology, several kinds of issues. Technical considerations were material balance, energy balance, plant thermal efficiency, and effect of feedstock contaminants. Environmental considerations were the regulatory context, and such things as composition,more » mass rate, and treatability of pollutants. Business issues were related to likelihood of commercialization. Finally, cost and economic issues such as capital and operating costs, and the refuse-derived fuel preparation and energy c onversion costs, were considered. The final section of the report reviews and summarizes the information gathered during the study.« less

75 FR 39892 - Fisheries of the Exclusive Economic Zone Off Alaska; Community Development Quota Program

Federal Register 2010, 2011, 2012, 2013, 2014

2010-07-13

... Fisheries Act (AFA) trawl catcher/processor sector (otherwise known as the Amendment 80 sector... catcher/processors. Hook-and-line catcher/processors are allocated 48.7 percent of the annual BSAI Pacific... harvest of Pacific cod by hook-and-line catcher/processors, although this is one of the major groundfish...

Advanced Avionics and Processor Systems for a Flexible Space Exploration Architecture

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Adams, James H.; Smith, Leigh M.; Johnson, Michael A.; Cressler, John D.

2010-01-01

The Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to develop advanced avionic and processor technologies anticipated to be used by NASA s currently evolving space exploration architectures. The AAPS project is a part of the Exploration Technology Development Program, which funds an entire suite of technologies that are aimed at enabling NASA s ability to explore beyond low earth orbit. NASA s Marshall Space Flight Center (MSFC) manages the AAPS project. AAPS uses a broad-scoped approach to developing avionic and processor systems. Investment areas include advanced electronic designs and technologies capable of providing environmental hardness, reconfigurable computing techniques, software tools for radiation effects assessment, and radiation environment modeling tools. Near-term emphasis within the multiple AAPS tasks focuses on developing prototype components using semiconductor processes and materials (such as Silicon-Germanium (SiGe)) to enhance a device s tolerance to radiation events and low temperature environments. As the SiGe technology will culminate in a delivered prototype this fiscal year, the project emphasis shifts its focus to developing low-power, high efficiency total processor hardening techniques. In addition to processor development, the project endeavors to demonstrate techniques applicable to reconfigurable computing and partially reconfigurable Field Programmable Gate Arrays (FPGAs). This capability enables avionic architectures the ability to develop FPGA-based, radiation tolerant processor boards that can serve in multiple physical locations throughout the spacecraft and perform multiple functions during the course of the mission. The individual tasks that comprise AAPS are diverse, yet united in the common endeavor to develop electronics capable of operating within the harsh environment of space. Specifically, the AAPS tasks for the Federal fiscal year of 2010 are: Silicon-Germanium (SiGe) Integrated Electronics for Extreme Environments, Modeling of Radiation Effects on Electronics, Radiation Hardened High Performance Processors (HPP), and and Reconfigurable Computing.

Ice Storm Supercomputer

ScienceCinema

None

2018-05-01

A new Idaho National Laboratory supercomputer is helping scientists create more realistic simulations of nuclear fuel. Dubbed "Ice Storm" this 2048-processor machine allows researchers to model and predict the complex physics behind nuclear reactor behavior. And with a new visualization lab, the team can see the results of its simulations on the big screen. For more information about INL research, visit http://www.facebook.com/idahonationallaboratory.

South Carolina's timber industry-an assessment of timber product output and use, 1991

Treesearch

Tony G. Johnson; Edgar L. Davenport

1991-01-01

In 1991, roundwood output from South Carolina's forests totaled 508 million cubic feet, down 13 percent from 1989. Mill byproducts generated from primary processors declined an equal rate to 170 million cubic feet. Almost 100 percent of the residues were used, mostly for fuel and fiber products. Pulpwood remained the leading roundwood product at 250 million cubic...

Framework Programmable Platform for the advanced software development workstation: Framework processor design document

NASA Technical Reports Server (NTRS)

Mayer, Richard J.; Blinn, Thomas M.; Mayer, Paula S. D.; Ackley, Keith A.; Crump, Wes; Sanders, Les

1991-01-01

The design of the Framework Processor (FP) component of the Framework Programmable Software Development Platform (FFP) is described. The FFP is a project aimed at combining effective tool and data integration mechanisms with a model of the software development process in an intelligent integrated software development environment. Guided by the model, this Framework Processor will take advantage of an integrated operating environment to provide automated support for the management and control of the software development process so that costly mistakes during the development phase can be eliminated.

Development and analysis of the Software Implemented Fault-Tolerance (SIFT) computer

NASA Technical Reports Server (NTRS)

Goldberg, J.; Kautz, W. H.; Melliar-Smith, P. M.; Green, M. W.; Levitt, K. N.; Schwartz, R. L.; Weinstock, C. B.

1984-01-01

SIFT (Software Implemented Fault Tolerance) is an experimental, fault-tolerant computer system designed to meet the extreme reliability requirements for safety-critical functions in advanced aircraft. Errors are masked by performing a majority voting operation over the results of identical computations, and faulty processors are removed from service by reassigning computations to the nonfaulty processors. This scheme has been implemented in a special architecture using a set of standard Bendix BDX930 processors, augmented by a special asynchronous-broadcast communication interface that provides direct, processor to processor communication among all processors. Fault isolation is accomplished in hardware; all other fault-tolerance functions, together with scheduling and synchronization are implemented exclusively by executive system software. The system reliability is predicted by a Markov model. Mathematical consistency of the system software with respect to the reliability model has been partially verified, using recently developed tools for machine-aided proof of program correctness.

Processor architecture for airborne SAR systems

NASA Technical Reports Server (NTRS)

Glass, C. M.

1983-01-01

Digital processors for spaceborne imaging radars and application of the technology developed for airborne SAR systems are considered. Transferring algorithms and implementation techniques from airborne to spaceborne SAR processors offers obvious advantages. The following topics are discussed: (1) a quantification of the differences in processing algorithms for airborne and spaceborne SARs; and (2) an overview of three processors for airborne SAR systems.

Space Tug Avionics Definition Study. Volume 5: Cost and Programmatics

NASA Technical Reports Server (NTRS)

1975-01-01

The baseline avionics system features a central digital computer that integrates the functions of all the space tug subsystems by means of a redundant digital data bus. The central computer consists of dual central processor units, dual input/output processors, and a fault tolerant memory, utilizing internal redundancy and error checking. Three electronically steerable phased arrays provide downlink transmission from any tug attitude directly to ground or via TDRS. Six laser gyros and six accelerometers in a dodecahedron configuration make up the inertial measurement unit. Both a scanning laser radar and a TV system, employing strobe lamps, are required as acquisition and docking sensors. Primary dc power at a nominal 28 volts is supplied from dual lightweight, thermally integrated fuel cells which operate from propellant grade reactants out of the main tanks.

Stanford Hardware Development Program

NASA Technical Reports Server (NTRS)

Peterson, A.; Linscott, I.; Burr, J.

1986-01-01

Architectures for high performance, digital signal processing, particularly for high resolution, wide band spectrum analysis were developed. These developments are intended to provide instrumentation for NASA's Search for Extraterrestrial Intelligence (SETI) program. The real time signal processing is both formal and experimental. The efficient organization and optimal scheduling of signal processing algorithms were investigated. The work is complemented by efforts in processor architecture design and implementation. A high resolution, multichannel spectrometer that incorporates special purpose microcoded signal processors is being tested. A general purpose signal processor for the data from the multichannel spectrometer was designed to function as the processing element in a highly concurrent machine. The processor performance required for the spectrometer is in the range of 1000 to 10,000 million instructions per second (MIPS). Multiple node processor configurations, where each node performs at 100 MIPS, are sought. The nodes are microprogrammable and are interconnected through a network with high bandwidth for neighboring nodes, and medium bandwidth for nodes at larger distance. The implementation of both the current mutlichannel spectrometer and the signal processor as Very Large Scale Integration CMOS chip sets was commenced.

HANSF 1.3 Users Manual FAI/98-40-R2 Hanford Spent Nuclear Fuel (SNF) Safety Analysis Model [SEC 1 and 2

DOE Office of Scientific and Technical Information (OSTI.GOV)

DUNCAN, D.R.

The HANSF analysis tool is an integrated model considering phenomena inside a multi-canister overpack (MCO) spent nuclear fuel container such as fuel oxidation, convective and radiative heat transfer, and the potential for fission product release. This manual reflects the HANSF version 1.3.2, a revised version of 1.3.1. HANSF 1.3.2 was written to correct minor errors and to allow modeling of condensate flow on the MCO inner surface. HANSF 1.3.2 is intended for use on personal computers such as IBM-compatible machines with Intel processors running under Lahey TI or digital Visual FORTRAN, Version 6.0, but this does not preclude operation inmore » other environments.« less

Accelerating molecular dynamic simulation on the cell processor and Playstation 3.

PubMed

Luttmann, Edgar; Ensign, Daniel L; Vaidyanathan, Vishal; Houston, Mike; Rimon, Noam; Øland, Jeppe; Jayachandran, Guha; Friedrichs, Mark; Pande, Vijay S

2009-01-30

Implementation of molecular dynamics (MD) calculations on novel architectures will vastly increase its power to calculate the physical properties of complex systems. Herein, we detail algorithmic advances developed to accelerate MD simulations on the Cell processor, a commodity processor found in PlayStation 3 (PS3). In particular, we discuss issues regarding memory access versus computation and the types of calculations which are best suited for streaming processors such as the Cell, focusing on implicit solvation models. We conclude with a comparison of improved performance on the PS3's Cell processor over more traditional processors. (c) 2008 Wiley Periodicals, Inc.

Axisymmetric whole pin life modelling of advanced gas-cooled reactor nuclear fuel

NASA Astrophysics Data System (ADS)

Mella, R.; Wenman, M. R.

2013-06-01

Thermo-mechanical contributions to pellet-clad interaction (PCI) in advanced gas-cooled reactors (AGRs) are modelled in the ABAQUS finite element (FE) code. User supplied sub-routines permit the modelling of the non-linear behaviour of AGR fuel through life. Through utilisation of ABAQUS's well-developed pre- and post-processing ability, the behaviour of the axially constrained steel clad fuel was modelled. The 2D axisymmetric model includes thermo-mechanical behaviour of the fuel with time and condition dependent material properties. Pellet cladding gap dynamics and thermal behaviour are also modelled. The model treats heat up as a fully coupled temperature-displacement study. Dwell time and direct power cycling was applied to model the impact of online refuelling, a key feature of the AGR. The model includes the visco-plastic behaviour of the fuel under the stress and irradiation conditions within an AGR core and a non-linear heat transfer model. A multiscale fission gas release model is applied to compute pin pressure; this model is coupled to the PCI gap model through an explicit fission gas inventory code. Whole pin, whole life, models are able to show the impact of the fuel on all segments of cladding including weld end caps and cladding pellet locking mechanisms (unique to AGR fuel). The development of this model in a commercial FE package shows that the development of a potentially verified and future-proof fuel performance code can be created and used. The usability of a FE based fuel performance code would be an enhancement over past codes. Pre- and post-processors have lowered the entry barrier for the development of a fuel performance model to permit the ability to model complicated systems. Typical runtimes for a 5 year axisymmetric model takes less than one hour on a single core workstation. The current model has implemented: Non-linear fuel thermal behaviour, including a complex description of heat flow in the fuel. Coupled with a variety of different FE and finite difference models. Non-linear mechanical behaviour of the fuel and cladding including, fuel creep and swelling and cladding creep and plasticity each with dependencies on a variety of different properties. A fission gas release model which takes inputs from first principles calculations. Explicitly integrated inventory calculations performed in a coupled manner. Freedom to model steady state and transient behaviour using implicit time integration. The whole pin geometry is considered over an entire typical fuel life. The model showed by examination of normal operation and a subsequent transient chosen for software demonstration purposes: ABAQUS may be a sufficiently flexible platform to develop a complete and verified fuel performance code. The importance and effectiveness of the geometry of the fuel spacer pellets was characterised. The fuels performance under normal conditions (high friction no power spikes) would not suggest serious degradation of the cladding in fuel life. Large plastic strains were found when pellet bonding was strong, these would appear at all pellets cladding triple points and all pellet radial crack and cladding interfaces thus showing a possible axial direction to cracks forming from ductility exhaustion.

DFT algorithms for bit-serial GaAs array processor architectures

NASA Technical Reports Server (NTRS)

Mcmillan, Gary B.

1988-01-01

Systems and Processes Engineering Corporation (SPEC) has developed an innovative array processor architecture for computing Fourier transforms and other commonly used signal processing algorithms. This architecture is designed to extract the highest possible array performance from state-of-the-art GaAs technology. SPEC's architectural design includes a high performance RISC processor implemented in GaAs, along with a Floating Point Coprocessor and a unique Array Communications Coprocessor, also implemented in GaAs technology. Together, these data processors represent the latest in technology, both from an architectural and implementation viewpoint. SPEC has examined numerous algorithms and parallel processing architectures to determine the optimum array processor architecture. SPEC has developed an array processor architecture with integral communications ability to provide maximum node connectivity. The Array Communications Coprocessor embeds communications operations directly in the core of the processor architecture. A Floating Point Coprocessor architecture has been defined that utilizes Bit-Serial arithmetic units, operating at very high frequency, to perform floating point operations. These Bit-Serial devices reduce the device integration level and complexity to a level compatible with state-of-the-art GaAs device technology.

A Medical Language Processor for Two Indo-European Languages

PubMed Central

Nhan, Ngo Thanh; Sager, Naomi; Lyman, Margaret; Tick, Leo J.; Borst, François; Su, Yun

1989-01-01

The syntax and semantics of clinical narrative across Indo-European languages are quite similar, making it possible to envison a single medical language processor that can be adapted for different European languages. The Linguistic String Project of New York University is continuing the development of its Medical Language Processor in this direction. The paper describes how the processor operates on English and French.

Programming for 1.6 Millon cores: Early experiences with IBM's BG/Q SMP architecture

NASA Astrophysics Data System (ADS)

Glosli, James

2013-03-01

With the stall in clock cycle improvements a decade ago, the drive for computational performance has continues along a path of increasing core counts on a processor. The multi-core evolution has been expressed in both a symmetric multi processor (SMP) architecture and cpu/GPU architecture. Debates rage in the high performance computing (HPC) community which architecture best serves HPC. In this talk I will not attempt to resolve that debate but perhaps fuel it. I will discuss the experience of exploiting Sequoia, a 98304 node IBM Blue Gene/Q SMP at Lawrence Livermore National Laboratory. The advantages and challenges of leveraging the computational power BG/Q will be detailed through the discussion of two applications. The first application is a Molecular Dynamics code called ddcMD. This is a code developed over the last decade at LLNL and ported to BG/Q. The second application is a cardiac modeling code called Cardioid. This is a code that was recently designed and developed at LLNL to exploit the fine scale parallelism of BG/Q's SMP architecture. Through the lenses of these efforts I'll illustrate the need to rethink how we express and implement our computational approaches. This work was performed under the auspices of the U.S. Department of Energy by Lawrence Livermore National Laboratory under Contract DE-AC52-07NA27344.

Soft-core processor study for node-based architectures.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Van Houten, Jonathan Roger; Jarosz, Jason P.; Welch, Benjamin James

2008-09-01

Node-based architecture (NBA) designs for future satellite projects hold the promise of decreasing system development time and costs, size, weight, and power and positioning the laboratory to address other emerging mission opportunities quickly. Reconfigurable Field Programmable Gate Array (FPGA) based modules will comprise the core of several of the NBA nodes. Microprocessing capabilities will be necessary with varying degrees of mission-specific performance requirements on these nodes. To enable the flexibility of these reconfigurable nodes, it is advantageous to incorporate the microprocessor into the FPGA itself, either as a hardcore processor built into the FPGA or as a soft-core processor builtmore » out of FPGA elements. This document describes the evaluation of three reconfigurable FPGA based processors for use in future NBA systems--two soft cores (MicroBlaze and non-fault-tolerant LEON) and one hard core (PowerPC 405). Two standard performance benchmark applications were developed for each processor. The first, Dhrystone, is a fixed-point operation metric. The second, Whetstone, is a floating-point operation metric. Several trials were run at varying code locations, loop counts, processor speeds, and cache configurations. FPGA resource utilization was recorded for each configuration. Cache configurations impacted the results greatly; for optimal processor efficiency it is necessary to enable caches on the processors. Processor caches carry a penalty; cache error mitigation is necessary when operating in a radiation environment.« less

Development of small scale cluster computer for numerical analysis

NASA Astrophysics Data System (ADS)

Zulkifli, N. H. N.; Sapit, A.; Mohammed, A. N.

2017-09-01

In this study, two units of personal computer were successfully networked together to form a small scale cluster. Each of the processor involved are multicore processor which has four cores in it, thus made this cluster to have eight processors. Here, the cluster incorporate Ubuntu 14.04 LINUX environment with MPI implementation (MPICH2). Two main tests were conducted in order to test the cluster, which is communication test and performance test. The communication test was done to make sure that the computers are able to pass the required information without any problem and were done by using simple MPI Hello Program where the program written in C language. Additional, performance test was also done to prove that this cluster calculation performance is much better than single CPU computer. In this performance test, four tests were done by running the same code by using single node, 2 processors, 4 processors, and 8 processors. The result shows that with additional processors, the time required to solve the problem decrease. Time required for the calculation shorten to half when we double the processors. To conclude, we successfully develop a small scale cluster computer using common hardware which capable of higher computing power when compare to single CPU processor, and this can be beneficial for research that require high computing power especially numerical analysis such as finite element analysis, computational fluid dynamics, and computational physics analysis.

Fighter Aircraft OBIGGS (On-Board Inert Gas Generator System) Study. Volume 2

DTIC Science & Technology

1987-06-01

UNCLASSIFIED.UNLIMITED L SAME AS RPT. 0 OTIC USERS 0 UNCLASSIFIED 22m. NAME Or RESPONSIBLE INOIVIOUAL 22b TELEPHONE NUJN lER 22c OFFICE SYMBOL IflncI.de A C...Pressure Air System 53 3.2.1.6.11.3 Fuel Tank Vent System 54 3.2.1.6.11.4 Fuel Scrubbing System 54 3.2.1.6.12 Control/ Interface Processor 55 3.2.1.6.12.1...Flowmeters 60, 3.2.1.6.13.6 Motion Transducer 61 3.2.1.7 Interface Requirements 61 3.2.1.7.1 External Interfaces 61 3.2.1.7.1.1 External Systems

The computational structural mechanics testbed architecture. Volume 2: The interface

NASA Technical Reports Server (NTRS)

Felippa, Carlos A.

1988-01-01

This is the third set of five volumes which describe the software architecture for the Computational Structural Mechanics Testbed. Derived from NICE, an integrated software system developed at Lockheed Palo Alto Research Laboratory, the architecture is composed of the command language CLAMP, the command language interpreter CLIP, and the data manager GAL. Volumes 1, 2, and 3 (NASA CR's 178384, 178385, and 178386, respectively) describe CLAMP and CLIP and the CLIP-processor interface. Volumes 4 and 5 (NASA CR's 178387 and 178388, respectively) describe GAL and its low-level I/O. CLAMP, an acronym for Command Language for Applied Mechanics Processors, is designed to control the flow of execution of processors written for NICE. Volume 3 describes the CLIP-Processor interface and related topics. It is intended only for processor developers.

Performance of WPA Conductivity Sensor during Two-Phase Fluid Flow in Microgravity

NASA Technical Reports Server (NTRS)

Carter, Layne; O'Connor, Edward W.; Snowdon, Doug

2003-01-01

The Conductivity Sensor designed for use in the Node 3 Water Processor Assembly (WPA) was based on the existing Space Shuttle application for the fuel cell water system. However, engineering analysis has determined that this sensor design is potentially sensitive to two-phase fluid flow (gadliquid) in microgravity. The source for this sensitivity is the fact that gas bubbles will become lodged between the sensor probe and the wall of the housing without the aid of buoyancy in l-g. Once gas becomes lodged in the housing, the measured conductivity will be offset based on the volume of occluded gas. A development conductivity sensor was flown on the NASA Microgravity Plan to measure the offset, which was determined to range between 0 and 50%. Based on these findings, a development program was initiated at the sensor s manufacturer to develop a sensor design fully compatible with two-phase fluid flow in microgravity.

A model for tracking concentration of chemical compounds within a tank of an automatic film processor.

PubMed

Sobol, Wlad T

2002-01-01

A simple kinetic model that describes the time evolution of the chemical concentration of an arbitrary compound within the tank of an automatic film processor is presented. It provides insights into the kinetics of chemistry concentration inside the processor's tank; the results facilitate the tasks of processor tuning and quality control (QC). The model has successfully been used in several troubleshooting sessions of low-volume mammography processors for which maintaining consistent QC tracking was difficult due to fluctuations of bromide levels in the developer tank.

Onboard processor technology review

NASA Technical Reports Server (NTRS)

Benz, Harry F.

1990-01-01

The general need and requirements for the onboard embedded processors necessary to control and manipulate data in spacecraft systems are discussed. The current known requirements are reviewed from a user perspective, based on current practices in the spacecraft development process. The current capabilities of available processor technologies are then discussed, and these are projected to the generation of spacecraft computers currently under identified, funded development. An appraisal is provided for the current national developmental effort.

Design of RISC Processor Using VHDL and Cadence

NASA Astrophysics Data System (ADS)

Moslehpour, Saeid; Puliroju, Chandrasekhar; Abu-Aisheh, Akram

The project deals about development of a basic RISC processor. The processor is designed with basic architecture consisting of internal modules like clock generator, memory, program counter, instruction register, accumulator, arithmetic and logic unit and decoder. This processor is mainly used for simple general purpose like arithmetic operations and which can be further developed for general purpose processor by increasing the size of the instruction register. The processor is designed in VHDL by using Xilinx 8.1i version. The present project also serves as an application of the knowledge gained from past studies of the PSPICE program. The study will show how PSPICE can be used to simplify massive complex circuits designed in VHDL Synthesis. The purpose of the project is to explore the designed RISC model piece by piece, examine and understand the Input/ Output pins, and to show how the VHDL synthesis code can be converted to a simplified PSPICE model. The project will also serve as a collection of various research materials about the pieces of the circuit.

The ISS Water Processor Catalytic Reactor as a Post Processor for Advanced Water Reclamation Systems

NASA Technical Reports Server (NTRS)

Nalette, Tim; Snowdon, Doug; Pickering, Karen D.; Callahan, Michael

2007-01-01

Advanced water processors being developed for NASA s Exploration Initiative rely on phase change technologies and/or biological processes as the primary means of water reclamation. As a result of the phase change, volatile compounds will also be transported into the distillate product stream. The catalytic reactor assembly used in the International Space Station (ISS) water processor assembly, referred to as Volatile Removal Assembly (VRA), has demonstrated high efficiency oxidation of many of these volatile contaminants, such as low molecular weight alcohols and acetic acid, and is considered a viable post treatment system for all advanced water processors. To support this investigation, two ersatz solutions were defined to be used for further evaluation of the VRA. The first solution was developed as part of an internal research and development project at Hamilton Sundstrand (HS) and is based primarily on ISS experience related to the development of the VRA. The second ersatz solution was defined by NASA in support of a study contract to Hamilton Sundstrand to evaluate the VRA as a potential post processor for the Cascade Distillation system being developed by Honeywell. This second ersatz solution contains several low molecular weight alcohols, organic acids, and several inorganic species. A range of residence times, oxygen concentrations and operating temperatures have been studied with both ersatz solutions to provide addition performance capability of the VRA catalyst.

Performance evaluation of throughput computing workloads using multi-core processors and graphics processors

NASA Astrophysics Data System (ADS)

Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.

2017-11-01

Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.

Multi-processing on supercomputers for computational aerodynamics

NASA Technical Reports Server (NTRS)

Yarrow, Maurice; Mehta, Unmeel B.

1990-01-01

The MIMD concept is applied, through multitasking, with relatively minor modifications to an existing code for a single processor. This approach maps the available memory to multiple processors, exploiting the C-FORTRAN-Unix interface. An existing single processor algorithm is mapped without the need for developing a new algorithm. The procedure of designing a code utilizing this approach is automated with the Unix stream editor. A Multiple Processor Multiple Grid (MPMG) code is developed as a demonstration of this approach. This code solves the three-dimensional, Reynolds-averaged, thin-layer and slender-layer Navier-Stokes equations with an implicit, approximately factored and diagonalized method. This solver is applied to a generic, oblique-wing aircraft problem on a four-processor computer using one process for data management and nonparallel computations and three processes for pseudotime advance on three different grid systems.

Glycerol Production and Transformation: A Critical Review with Particular Emphasis on Glycerol Reforming Reaction for Producing Hydrogen in Conventional and Membrane Reactors.

PubMed

Bagnato, Giuseppe; Iulianelli, Adolfo; Sanna, Aimaro; Basile, Angelo

2017-03-23

Glycerol represents an emerging renewable bio-derived feedstock, which could be used as a source for producing hydrogen through steam reforming reaction. In this review, the state-of-the-art about glycerol production processes is reviewed, with particular focus on glycerol reforming reactions and on the main catalysts under development. Furthermore, the use of membrane catalytic reactors instead of conventional reactors for steam reforming is discussed. Finally, the review describes the utilization of the Pd-based membrane reactor technology, pointing out the ability of these alternative fuel processors to simultaneously extract high purity hydrogen and enhance the whole performances of the reaction system in terms of glycerol conversion and hydrogen yield.

Glycerol Production and Transformation: A Critical Review with Particular Emphasis on Glycerol Reforming Reaction for Producing Hydrogen in Conventional and Membrane Reactors

PubMed Central

Bagnato, Giuseppe; Iulianelli, Adolfo; Sanna, Aimaro; Basile, Angelo

2017-01-01

Glycerol represents an emerging renewable bio-derived feedstock, which could be used as a source for producing hydrogen through steam reforming reaction. In this review, the state-of-the-art about glycerol production processes is reviewed, with particular focus on glycerol reforming reactions and on the main catalysts under development. Furthermore, the use of membrane catalytic reactors instead of conventional reactors for steam reforming is discussed. Finally, the review describes the utilization of the Pd-based membrane reactor technology, pointing out the ability of these alternative fuel processors to simultaneously extract high purity hydrogen and enhance the whole performances of the reaction system in terms of glycerol conversion and hydrogen yield. PMID:28333121

Research and evaluation of biomass resources/conversion/utilization systems (market/experimental analysis for development of a data base for a fuels from biomass model. Volume I. Biomass allocation model. Technical progress report for the period ending September 30, 1980

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ahn, Y.K.; Chen, H.T.; Helm, R.W.

1980-01-01

A biomass allocation model has been developed to show the most profitable combination of biomass feedstocks thermochemical conversion processes, and fuel products to serve the seasonal conditions in a regional market. This optimization model provides a tool for quickly calculating the most profitable biomass missions from a large number of potential biomass missions. Other components of the system serve as a convenient storage and retrieval mechanism for biomass marketing and thermochemical conversion processing data. The system can be accessed through the use of a computer terminal, or it could be adapted to a portable micro-processor. A User's Manual for themore » system has been included in Appendix A of the report. The validity of any biomass allocation solution provided by the allocation model is dependent on the accuracy of the data base. The initial data base was constructed from values obtained from the literature, and, consequently, as more current thermochemical conversion processing and manufacturing costs and efficiencies become available, the data base should be revised. Biomass derived fuels included in the data base are the following: medium Btu gas low Btu gas, substitute natural gas, ammonia, methanol, electricity, gasoline, and fuel oil. The market sectors served by the fuels include: residential, electric utility, chemical (industrial), and transportation. Regional/seasonal costs and availabilities and heating values for 61 woody and non-woody biomass species are included. The study has included four regions in the United States which were selected because there was both an availability of biomass and a commercial demand for the derived fuels: Region I: NY, WV, PA; Region II: GA, AL, MS; Region III: IN, IL, IA; and Region IV: OR, WA.« less

Development of a Novel, Two-Processor Architecture for a Small UAV Autopilot System,

DTIC Science & Technology

2006-07-26

is, and the control laws the user implements to control it. The flight control system board will contain the processor selected for this system...Unit (IMU). The IMU contains solid-state gyros and accelerometers and uses these to determine the attitude of the UAV within the three dimensions of...multiple-UAV swarming for combat support operations. The mission processor board will contain the processor selected to execute the mission

Communications Processor Operating System Study. Executive Summary,

DTIC Science & Technology

1980-11-01

AD-A095 b36 ROME AIR DEVELOPMENT CENTER GRIFFISS AFB NY F/e 17/2 COMMUNICATIONS PROCESSOR OPERATING SYSTEM STUDY. EXECUTIVE SUMM—ETC(U) NOV 80 J...COMMUNICATIONS PROCESSOR OPERATING SYSTEM STUDY Julian Gitlih SPTIC ELECTE«^ FEfi 2 6 1981^ - E APPROVED FOR PUBLIC RELEASE; DISTRIBUTION UNLIMITED "a O...Subtitle) EXECUTIVE^SUMMARY 0F> COMMUNICATIONS PROCESSOR OPERATING SYSTEM $t - • >X W tdLl - ’•• • 7 AUTHORf«! ! , Julian

Dynamic modeling, experimental evaluation, optimal design and control of integrated fuel cell system and hybrid energy systems for building demands

NASA Astrophysics Data System (ADS)

Nguyen, Gia Luong Huu

Fuel cells can produce electricity with high efficiency, low pollutants, and low noise. With the advent of fuel cell technologies, fuel cell systems have since been demonstrated as reliable power generators with power outputs from a few watts to a few megawatts. With proper equipment, fuel cell systems can produce heating and cooling, thus increased its overall efficiency. To increase the acceptance from electrical utilities and building owners, fuel cell systems must operate more dynamically and integrate well with renewable energy resources. This research studies the dynamic performance of fuel cells and the integration of fuel cells with other equipment in three levels: (i) the fuel cell stack operating on hydrogen and reformate gases, (ii) the fuel cell system consisting of a fuel reformer, a fuel cell stack, and a heat recovery unit, and (iii) the hybrid energy system consisting of photovoltaic panels, fuel cell system, and energy storage. In the first part, this research studied the steady-state and dynamic performance of a high temperature PEM fuel cell stack. Collaborators at Aalborg University (Aalborg, Denmark) conducted experiments on a high temperature PEM fuel cell short stack at steady-state and transients. Along with the experimental activities, this research developed a first-principles dynamic model of a fuel cell stack. The dynamic model developed in this research was compared to the experimental results when operating on different reformate concentrations. Finally, the dynamic performance of the fuel cell stack for a rapid increase and rapid decrease in power was evaluated. The dynamic model well predicted the performance of the well-performing cells in the experimental fuel cell stack. The second part of the research studied the dynamic response of a high temperature PEM fuel cell system consisting of a fuel reformer, a fuel cell stack, and a heat recovery unit with high thermal integration. After verifying the model performance with the obtained experimental data, the research studied the control of airflow to regulate the temperature of reactors within the fuel processor. The dynamic model provided a platform to test the dynamic response for different control gains. With sufficient sensing and appropriate control, a rapid response to maintain the temperature of the reactor despite an increase in power was possible. The third part of the research studied the use of a fuel cell in conjunction with photovoltaic panels, and energy storage to provide electricity for buildings. This research developed an optimization framework to determine the size of each device in the hybrid energy system to satisfy the electrical demands of buildings and yield the lowest cost. The advantage of having the fuel cell with photovoltaic and energy storage was the ability to operate the fuel cell at baseload at night, thus reducing the need for large battery systems to shift the solar power produced in the day to the night. In addition, the dispatchability of the fuel cell provided an extra degree of freedom necessary for unforeseen disturbances. An operation framework based on model predictive control showed that the method is suitable for optimizing the dispatch of the hybrid energy system.

European Science Notes Information Bulletin Reports on Current European/ Middle Eastern Science

DTIC Science & Technology

1988-08-01

problems, and infrastructure and in- terfacing requirements. Development of Finite Element Software for Transputer-Based Parallel Processors ...Introduction will it be possible to harness these processors together to work on a common problem. The feasibility study at the UK’s Kent University for One of...the many problems in harnessing the power development of a distributed supercomputer is being of a large number of processors on a single problem is

PREMAQ: A NEW PRE-PROCESSOR TO CMAQ FOR AIR-QUALITY FORECASTING

EPA Science Inventory

A new pre-processor to CMAQ (PREMAQ) has been developed as part of the national air-quality forecasting system. PREMAQ combines the functionality of MCIP and parts of SMOKE in a single real-time processor. PREMAQ was specifically designed to link NCEP's Eta model with CMAQ, and...

SAPIENS: Spreading Activation Processor for Information Encoded in Network Structures. Technical Report No. 296.

ERIC Educational Resources Information Center

Ortony, Andrew; Radin, Dean I.

The product of researchers' efforts to develop a computer processor which distinguishes between relevant and irrelevant information in the database, Spreading Activation Processor for Information Encoded in Network Structures (SAPIENS) exhibits (1) context sensitivity, (2) efficiency, (3) decreasing activation over time, (4) summation of…

Formulation of consumables management models. Development approach for the mission planning processor working model

NASA Technical Reports Server (NTRS)

Connelly, L. C.

1977-01-01

The mission planning processor is a user oriented tool for consumables management and is part of the total consumables subsystem management concept. The approach to be used in developing a working model of the mission planning processor is documented. The approach includes top-down design, structured programming techniques, and application of NASA approved software development standards. This development approach: (1) promotes cost effective software development, (2) enhances the quality and reliability of the working model, (3) encourages the sharing of the working model through a standard approach, and (4) promotes portability of the working model to other computer systems.

Analysis on electronic control unit of continuously variable transmission

NASA Astrophysics Data System (ADS)

Cao, Shuanggui

Continuously variable transmission system can ensure that the engine work along the line of best fuel economy, improve fuel economy, save fuel and reduce harmful gas emissions. At the same time, continuously variable transmission allows the vehicle speed is more smooth and improves the ride comfort. Although the CVT technology has made great development, but there are many shortcomings in the CVT. The CVT system of ordinary vehicles now is still low efficiency, poor starting performance, low transmission power, and is not ideal controlling, high cost and other issues. Therefore, many scholars began to study some new type of continuously variable transmission. The transmission system with electronic systems control can achieve automatic control of power transmission, give full play to the characteristics of the engine to achieve optimal control of powertrain, so the vehicle is always traveling around the best condition. Electronic control unit is composed of the core processor, input and output circuit module and other auxiliary circuit module. Input module collects and process many signals sent by sensor and , such as throttle angle, brake signals, engine speed signal, speed signal of input and output shaft of transmission, manual shift signals, mode selection signals, gear position signal and the speed ratio signal, so as to provide its corresponding processing for the controller core.

Interpreter composition issues in the formal verification of a processor-memory module

NASA Technical Reports Server (NTRS)

Fura, David A.; Cohen, Gerald C.

1994-01-01

This report describes interpreter composition techniques suitable for the formal specification and verification of a processor-memory module using the HOL theorem proving system. The processor-memory module is a multichip subsystem within a fault-tolerant embedded system under development within the Boeing Defense and Space Group. Modeling and verification methods were developed that permit provably secure composition at the transaction-level of specification, significantly reducing the complexity of the hierarchical verification of the system.

Automatic Dynamic Aircraft Modeler (ADAM) for the Computer Program NASTRAN

NASA Technical Reports Server (NTRS)

Griffis, H.

1985-01-01

Large general purpose finite element programs require users to develop large quantities of input data. General purpose pre-processors are used to decrease the effort required to develop structural models. Further reduction of effort can be achieved by specific application pre-processors. Automatic Dynamic Aircraft Modeler (ADAM) is one such application specific pre-processor. General purpose pre-processors use points, lines and surfaces to describe geometric shapes. Specifying that ADAM is used only for aircraft structures allows generic structural sections, wing boxes and bodies, to be pre-defined. Hence with only gross dimensions, thicknesses, material properties and pre-defined boundary conditions a complete model of an aircraft can be created.

In-ground operation of Geothermic Fuel Cells for unconventional oil and gas recovery

NASA Astrophysics Data System (ADS)

Sullivan, Neal; Anyenya, Gladys; Haun, Buddy; Daubenspeck, Mark; Bonadies, Joseph; Kerr, Rick; Fischer, Bernhard; Wright, Adam; Jones, Gerald; Li, Robert; Wall, Mark; Forbes, Alan; Savage, Marshall

2016-01-01

This paper presents operating and performance characteristics of a nine-stack solid-oxide fuel cell combined-heat-and-power system. Integrated with a natural-gas fuel processor, air compressor, reactant-gas preheater, and diagnostics and control equipment, the system is designed for use in unconventional oil-and-gas processing. Termed a ;Geothermic Fuel Cell; (GFC), the heat liberated by the fuel cell during electricity generation is harnessed to process oil shale into high-quality crude oil and natural gas. The 1.5-kWe SOFC stacks are packaged within three-stack GFC modules. Three GFC modules are mechanically and electrically coupled to a reactant-gas preheater and installed within the earth. During operation, significant heat is conducted from the Geothermic Fuel Cell to the surrounding geology. The complete system was continuously operated on hydrogen and natural-gas fuels for ∼600 h. A quasi-steady operating point was established to favor heat generation (29.1 kWth) over electricity production (4.4 kWe). Thermodynamic analysis reveals a combined-heat-and-power efficiency of 55% at this condition. Heat flux to the geology averaged 3.2 kW m-1 across the 9-m length of the Geothermic Fuel Cell-preheater assembly. System performance is reviewed; some suggestions for improvement are proposed.

Method and apparatus for real-time measurement of fuel gas compositions and heating values

DOEpatents

Zelepouga, Serguei; Pratapas, John M.; Saveliev, Alexei V.; Jangale, Vilas V.

2016-03-22

An exemplary embodiment can be an apparatus for real-time, in situ measurement of gas compositions and heating values. The apparatus includes a near infrared sensor for measuring concentrations of hydrocarbons and carbon dioxide, a mid infrared sensor for measuring concentrations of carbon monoxide and a semiconductor based sensor for measuring concentrations of hydrogen gas. A data processor having a computer program for reducing the effects of cross-sensitivities of the sensors to components other than target components of the sensors is also included. Also provided are corresponding or associated methods for real-time, in situ determination of a composition and heating value of a fuel gas.

75 FR 14015 - Fisheries of the Exclusive Economic Zone Off Alaska; Chinook Salmon Bycatch Management in the...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-03-23

... Pollock Fishery This proposed rule applies to owners and operators of catcher vessels, catcher/processors, motherships, inshore processors, and the six Western Alaska Community Development Quota (CDQ) Program groups... fishery by identifying the vessels and processors eligible to participate in the fishery and allocating...

On board processor development for NASA's spaceborne imaging radar with system-on-chip technology

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi

2004-01-01

This paper reports a preliminary study result of an on-board spaceborne SAR processor. It consists of a processing requirement analysis, functional specifications, and implementation with system-on-chip technology. Finally, a minimum version of this on-board processor designed for performance evaluation and for partial demonstration is illustrated.

A high performance linear equation solver on the VPP500 parallel supercomputer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nakanishi, Makoto; Ina, Hiroshi; Miura, Kenichi

1994-12-31

This paper describes the implementation of two high performance linear equation solvers developed for the Fujitsu VPP500, a distributed memory parallel supercomputer system. The solvers take advantage of the key architectural features of VPP500--(1) scalability for an arbitrary number of processors up to 222 processors, (2) flexible data transfer among processors provided by a crossbar interconnection network, (3) vector processing capability on each processor, and (4) overlapped computation and transfer. The general linear equation solver based on the blocked LU decomposition method achieves 120.0 GFLOPS performance with 100 processors in the LIN-PACK Highly Parallel Computing benchmark.

Rapid Damage Assessment. Volume II. Development and Testing of Rapid Damage Assessment System.

DTIC Science & Technology

1981-02-01

pixels/s Camera Line Rate 732.4 lines/s Pixels per Line 1728 video 314 blank 4 line number (binary) 2 run number (BCD) 2048 total Pixel Resolution 8 bits...sists of an LSI-ll microprocessor, a VDI -200 video display processor, an FD-2 dual floppy diskette subsystem, an FT-I function key-trackball module...COMPONENT LIST FOR IMAGE PROCESSOR SYSTEM IMAGE PROCESSOR SYSTEM VIEWS I VDI -200 Display Processor Racks, Table FD-2 Dual Floppy Diskette Subsystem FT-l

Onboard Radar Processing Development for Rapid Response Applications

NASA Technical Reports Server (NTRS)

Lou, Yunling; Chien, Steve; Clark, Duane; Doubleday, Josh; Muellerschoen, Ron; Wang, Charles C.

2011-01-01

We are developing onboard processor (OBP) technology to streamline data acquisition on-demand and explore the potential of the L-band SAR instrument onboard the proposed DESDynI mission and UAVSAR for rapid response applications. The technology would enable the observation and use of surface change data over rapidly evolving natural hazards, both as an aid to scientific understanding and to provide timely data to agencies responsible for the management and mitigation of natural disasters. We are adapting complex science algorithms for surface water extent to detect flooding, snow/water/ice classification to assist in transportation/ shipping forecasts, and repeat-pass change detection to detect disturbances. We are near completion of the development of a custom FPGA board to meet the specific memory and processing needs of L-band SAR processor algorithms and high speed interfaces to reformat and route raw radar data to/from the FPGA processor board. We have also developed a high fidelity Matlab model of the SAR processor that is modularized and parameterized for ease to prototype various SAR processor algorithms targeted for the FPGA. We will be testing the OBP and rapid response algorithms with UAVSAR data to determine the fidelity of the products.

PixonVision real-time video processor

NASA Astrophysics Data System (ADS)

Puetter, R. C.; Hier, R. G.

2007-09-01

PixonImaging LLC and DigiVision, Inc. have developed a real-time video processor, the PixonVision PV-200, based on the patented Pixon method for image deblurring and denoising, and DigiVision's spatially adaptive contrast enhancement processor, the DV1000. The PV-200 can process NTSC and PAL video in real time with a latency of 1 field (1/60 th of a second), remove the effects of aerosol scattering from haze, mist, smoke, and dust, improve spatial resolution by up to 2x, decrease noise by up to 6x, and increase local contrast by up to 8x. A newer version of the processor, the PV-300, is now in prototype form and can handle high definition video. Both the PV-200 and PV-300 are FPGA-based processors, which could be spun into ASICs if desired. Obvious applications of these processors include applications in the DOD (tanks, aircraft, and ships), homeland security, intelligence, surveillance, and law enforcement. If developed into an ASIC, these processors will be suitable for a variety of portable applications, including gun sights, night vision goggles, binoculars, and guided munitions. This paper presents a variety of examples of PV-200 processing, including examples appropriate to border security, battlefield applications, port security, and surveillance from unmanned aerial vehicles.

Implicit, nonswitching, vector-oriented algorithm for steady transonic flow

NASA Technical Reports Server (NTRS)

Lottati, I.

1983-01-01

A rapid computation of a sequence of transonic flow solutions has to be performed in many areas of aerodynamic technology. The employment of low-cost vector array processors makes the conduction of such calculations economically feasible. However, for a full utilization of the new hardware, the developed algorithms must take advantage of the special characteristics of the vector array processor. The present investigation has the objective to develop an efficient algorithm for solving transonic flow problems governed by mixed partial differential equations on an array processor.

Computer Aided Grid Interface: An Interactive CFD Pre-Processor

NASA Technical Reports Server (NTRS)

Soni, Bharat K.

1997-01-01

NASA maintains an applications oriented computational fluid dynamics (CFD) efforts complementary to and in support of the aerodynamic-propulsion design and test activities. This is especially true at NASA/MSFC where the goal is to advance and optimize present and future liquid-fueled rocket engines. Numerical grid generation plays a significant role in the fluid flow simulations utilizing CFD. An overall goal of the current project was to develop a geometry-grid generation tool that will help engineers, scientists and CFD practitioners to analyze design problems involving complex geometries in a timely fashion. This goal is accomplished by developing the CAGI: Computer Aided Grid Interface system. The CAGI system is developed by integrating CAD/CAM (Computer Aided Design/Computer Aided Manufacturing) geometric system output and/or Initial Graphics Exchange Specification (IGES) files (including all the NASA-IGES entities), geometry manipulations and generations associated with grid constructions, and robust grid generation methodologies. This report describes the development process of the CAGI system.

Computer Aided Grid Interface: An Interactive CFD Pre-Processor

NASA Technical Reports Server (NTRS)

Soni, Bharat K.

1996-01-01

NASA maintains an applications oriented computational fluid dynamics (CFD) efforts complementary to and in support of the aerodynamic-propulsion design and test activities. This is especially true at NASA/MSFC where the goal is to advance and optimize present and future liquid-fueled rocket engines. Numerical grid generation plays a significant role in the fluid flow simulations utilizing CFD. An overall goal of the current project was to develop a geometry-grid generation tool that will help engineers, scientists and CFD practitioners to analyze design problems involving complex geometries in a timely fashion. This goal is accomplished by developing the Computer Aided Grid Interface system (CAGI). The CAGI system is developed by integrating CAD/CAM (Computer Aided Design/Computer Aided Manufacturing) geometric system output and / or Initial Graphics Exchange Specification (IGES) files (including all the NASA-IGES entities), geometry manipulations and generations associated with grid constructions, and robust grid generation methodologies. This report describes the development process of the CAGI system.

Parallel processor for real-time structural control

NASA Astrophysics Data System (ADS)

Tise, Bert L.

1993-07-01

A parallel processor that is optimized for real-time linear control has been developed. This modular system consists of A/D modules, D/A modules, and floating-point processor modules. The scalable processor uses up to 1,000 Motorola DSP96002 floating-point processors for a peak computational rate of 60 GFLOPS. Sampling rates up to 625 kHz are supported by this analog-in to analog-out controller. The high processing rate and parallel architecture make this processor suitable for computing state-space equations and other multiply/accumulate-intensive digital filters. Processor features include 14-bit conversion devices, low input-to-output latency, 240 Mbyte/s synchronous backplane bus, low-skew clock distribution circuit, VME connection to host computer, parallelizing code generator, and look- up-tables for actuator linearization. This processor was designed primarily for experiments in structural control. The A/D modules sample sensors mounted on the structure and the floating- point processor modules compute the outputs using the programmed control equations. The outputs are sent through the D/A module to the power amps used to drive the structure's actuators. The host computer is a Sun workstation. An OpenWindows-based control panel is provided to facilitate data transfer to and from the processor, as well as to control the operating mode of the processor. A diagnostic mode is provided to allow stimulation of the structure and acquisition of the structural response via sensor inputs.

Advanced satellite communication system

NASA Technical Reports Server (NTRS)

Staples, Edward J.; Lie, Sen

1992-01-01

The objective of this research program was to develop an innovative advanced satellite receiver/demodulator utilizing surface acoustic wave (SAW) chirp transform processor and coherent BPSK demodulation. The algorithm of this SAW chirp Fourier transformer is of the Convolve - Multiply - Convolve (CMC) type, utilizing off-the-shelf reflective array compressor (RAC) chirp filters. This satellite receiver, if fully developed, was intended to be used as an on-board multichannel communications repeater. The Advanced Communications Receiver consists of four units: (1) CMC processor, (2) single sideband modulator, (3) demodulator, and (4) chirp waveform generator and individual channel processors. The input signal is composed of multiple user transmission frequencies operating independently from remotely located ground terminals. This signal is Fourier transformed by the CMC Processor into a unique time slot for each user frequency. The CMC processor is driven by a waveform generator through a single sideband (SSB) modulator. The output of the coherent demodulator is composed of positive and negative pulses, which are the envelopes of the chirp transform processor output. These pulses correspond to the data symbols. Following the demodulator, a logic circuit reconstructs the pulses into data, which are subsequently differentially decoded to form the transmitted data. The coherent demodulation and detection of BPSK signals derived from a CMC chirp transform processor were experimentally demonstrated and bit error rate (BER) testing was performed. To assess the feasibility of such advanced receiver, the results were compared with the theoretical analysis and plotted for an average BER as a function of signal-to-noise ratio. Another goal of this SBIR program was the development of a commercial product. The commercial product developed was an arbitrary waveform generator. The successful sales have begun with the delivery of the first arbitrary waveform generator.

30/20 GHz communications systems baseband processor development

NASA Astrophysics Data System (ADS)

Brown, L.; Sabourin, D.; Stilwell, J.; McCallister, R.; Borota, M.

The architecture and system design concepts for a commercial satellite communications system planned for the 1990's has been developed. The system provides data communications between the individual users via trunking and customer premise service terminals utilizing a central switching satellite operating in a time-division multiple-access mode. Baseband processing is employed to route and control traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband processor design are being verified in the baseband processor proof-of-concept model described herein.

30/20 GHz communications systems baseband processor development

NASA Technical Reports Server (NTRS)

Brown, L.; Sabourin, D.; Stilwell, J.; Mccallister, R.; Borota, M.

1982-01-01

The architecture and system design concepts for a commercial satellite communications system planned for the 1990's has been developed. The system provides data communications between the individual users via trunking and customer premise service terminals utilizing a central switching satellite operating in a time-division multiple-access mode. Baseband processing is employed to route and control traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband processor design are being verified in the baseband processor proof-of-concept model described herein.

SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Optoelectronic processor in the form of a hybrid microcircuit

NASA Astrophysics Data System (ADS)

Evtikhiev, N. N.; Esepkina, N. A.; Dolgii, V. A.; Lavrov, A. P.; Khotyanov, B. M.; Chernokozhin, V. V.; Shestak, S. A.

1995-10-01

An optoelectronic processor in the form of a hybrid microcircuit is described. An analysis is made of the feasibility of developing a new class of optoelectronic processors which are hybrid microcircuits and can operate both as self-contained specialised computers and also as functional components of computing systems.

High Fidelity Simulations of Unsteady Flow through Turbopumps and Flowliners

NASA Technical Reports Server (NTRS)

Kiris, Cetin C.; Kwak, dochan; Chan, William; Housman, Jeff

2006-01-01

High fidelity computations were carried out to analyze the orbiter LH2 feedline flowliner. Computations were performed on the Columbia platform which is a 10,240-processor supercluster consisting of 20 Altix nodes with 512 processor each. Various computational models were used to characterize the unsteady flow features in the turbopump, including the orbiter Low-Pressure-Fuel-Turbopump (LPFTP) inducer, the orbiter manifold and a test article used to represent the manifold. Unsteady flow originating from the orbiter LPFTP inducer is one of the major contributors to the high frequency cyclic loading that results in high cycle fatigue damage to the gimbal flowliners just upstream of the LPFTP. The flow fields for the orbiter manifold and representative test article are computed and analyzed for similarities and differences. The incompressible Navier-Stokes flow solver INS3D, based on the artificial compressibility method, was used to compute the flow of liquid hydrogen in each test article.

Modular chemiresistive sensor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Alam, Maksudul M.; Sampathkumaran, Uma

The present invention relates to a modular chemiresistive sensor. In particular, a modular chemiresistive sensor for hypergolic fuel and oxidizer leak detection, carbon dioxide monitoring and detection of disease biomarkers. The sensor preferably has two gold or platinum electrodes mounted on a silicon substrate where the electrodes are connected to a power source and are separated by a gap of 0.5 to 4.0 .mu.M. A polymer nanowire or carbon nanotube spans the gap between the electrodes and connects the electrodes electrically. The electrodes are further connected to a circuit board having a processor and data storage, where the processor canmore » measure current and voltage values between the electrodes and compare the current and voltage values with current and voltage values stored in the data storage and assigned to particular concentrations of a pre-determined substance such as those listed above or a variety of other substances.« less

An enhanced Ada run-time system for real-time embedded processors

NASA Technical Reports Server (NTRS)

Sims, J. T.

1991-01-01

An enhanced Ada run-time system has been developed to support real-time embedded processor applications. The primary focus of this development effort has been on the tasking system and the memory management facilities of the run-time system. The tasking system has been extended to support efficient and precise periodic task execution as required for control applications. Event-driven task execution providing a means of task-asynchronous control and communication among Ada tasks is supported in this system. Inter-task control is even provided among tasks distributed on separate physical processors. The memory management system has been enhanced to provide object allocation and protected access support for memory shared between disjoint processors, each of which is executing a distinct Ada program.

Fuel Cell Power Plant Initiative. Volume 1; Solid Oxide Fuel Cell/Logistics Fuel Processor 27 kWe Power System Demonstration for ARPA

NASA Technical Reports Server (NTRS)

Veyo, S.E.

1997-01-01

This report describes the successful testing of a 27 kWe Solid Oxide Fuel Cell (SOFC) generator fueled by natural gas and/or a fuel gas produced by a brassboard logistics fuel preprocessor (LFP). The test period began on May 24, 1995 and ended on February 26, 1996 with the successful completion of all program requirements and objectives. During this time period, this power system produced 118.2 MWh of electric power. No degradation of the generator's performance was measured after 5582 accumulated hours of operation on these fuels: local natural gas - 3261 hours, jet fuel reformate gas - 766 hours, and diesel fuel reformate gas - 1555 hours. This SOFC generator was thermally cycled from full operating temperature to room temperature and back to operating temperature six times, because of failures of support system components and the occasional loss of test site power, without measurable cell degradation. Numerous outages of the LFP did not interrupt the generator's operation because the fuel control system quickly switched to local natural gas when an alarm indicated that the LFP reformate fuel supply had been interrupted. The report presents the measured electrical performance of the generator on all three fuel types and notes the small differences due to fuel type. Operational difficulties due to component failures are well documented even though they did not affect the overall excellent performance of this SOFC power generator. The final two appendices describe in detail the LFP design and the operating history of the tested brassboard LFP.

Concept of a programmable maintenance processor applicable to multiprocessing systems

NASA Technical Reports Server (NTRS)

Glover, Richard D.

1988-01-01

A programmable maintenance processor concept applicable to multiprocessing systems has been developed at the NASA Ames Research Center's Dryden Flight Research Facility. This stand-alone-processor is intended to provide support for system and application software testing as well as hardware diagnostics. An initial machanization has been incorporated into the extended aircraft interrogation and display system (XAIDS) which is multiprocessing general-purpose ground support equipment. The XAIDS maintenance processor has independent terminal and printer interfaces and a dedicated magnetic bubble memory that stores system test sequences entered from the terminal. This report describes the hardware and software embodied in this processor and shows a typical application in the check-out of a new XAIDS.

Ultra-Reliable Digital Avionics (URDA) processor

NASA Astrophysics Data System (ADS)

Branstetter, Reagan; Ruszczyk, William; Miville, Frank

1994-10-01

Texas Instruments Incorporated (TI) developed the URDA processor design under contract with the U.S. Air Force Wright Laboratory and the U.S. Army Night Vision and Electro-Sensors Directorate. TI's approach couples advanced packaging solutions with advanced integrated circuit (IC) technology to provide a high-performance (200 MIPS/800 MFLOPS) modular avionics processor module for a wide range of avionics applications. TI's processor design integrates two Ada-programmable, URDA basic processor modules (BPM's) with a JIAWG-compatible PiBus and TMBus on a single F-22 common integrated processor-compatible form-factor SEM-E avionics card. A separate, high-speed (25-MWord/second 32-bit word) input/output bus is provided for sensor data. Each BPM provides a peak throughput of 100 MIPS scalar concurrent with 400-MFLOPS vector processing in a removable multichip module (MCM) mounted to a liquid-flowthrough (LFT) core and interfacing to a processor interface module printed wiring board (PWB). Commercial RISC technology coupled with TI's advanced bipolar complementary metal oxide semiconductor (BiCMOS) application specific integrated circuit (ASIC) and silicon-on-silicon packaging technologies are used to achieve the high performance in a miniaturized package. A Mips R4000-family reduced instruction set computer (RISC) processor and a TI 100-MHz BiCMOS vector coprocessor (VCP) ASIC provide, respectively, the 100 MIPS of a scalar processor throughput and 400 MFLOPS of vector processing throughput for each BPM. The TI Aladdim ASIC chipset was developed on the TI Aladdin Program under contract with the U.S. Army Communications and Electronics Command and was sponsored by the Advanced Research Projects Agency with technical direction from the U.S. Army Night Vision and Electro-Sensors Directorate.

Sentinel-2 Level 2A Prototype Processor: Architecture, Algorithms And First Results

NASA Astrophysics Data System (ADS)

Muller-Wilm, Uwe; Louis, Jerome; Richter, Rudolf; Gascon, Ferran; Niezette, Marc

2013-12-01

Sen2Core is a prototype processor for Sentinel-2 Level 2A product processing and formatting. The processor is developed for and with ESA and performs the tasks of Atmospheric Correction and Scene Classification of Level 1C input data. Level 2A outputs are: Bottom-Of- Atmosphere (BOA) corrected reflectance images, Aerosol Optical Thickness-, Water Vapour-, Scene Classification maps and Quality indicators, including cloud and snow probabilities. The Level 2A Product Formatting performed by the processor follows the specification of the Level 1C User Product.

Optimal processor assignment for pipeline computations

NASA Technical Reports Server (NTRS)

Nicol, David M.; Simha, Rahul; Choudhury, Alok N.; Narahari, Bhagirath

1991-01-01

The availability of large scale multitasked parallel architectures introduces the following processor assignment problem for pipelined computations. Given a set of tasks and their precedence constraints, along with their experimentally determined individual responses times for different processor sizes, find an assignment of processor to tasks. Two objectives are of interest: minimal response given a throughput requirement, and maximal throughput given a response time requirement. These assignment problems differ considerably from the classical mapping problem in which several tasks share a processor; instead, it is assumed that a large number of processors are to be assigned to a relatively small number of tasks. Efficient assignment algorithms were developed for different classes of task structures. For a p processor system and a series parallel precedence graph with n constituent tasks, an O(np2) algorithm is provided that finds the optimal assignment for the response time optimization problem; it was found that the assignment optimizing the constrained throughput in O(np2log p) time. Special cases of linear, independent, and tree graphs are also considered.

Development of a new signal processor for tetralateral position sensitive detector based on single-chip microcomputer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Huang Meizhen; Shi Longzhao; Wang Yuxing

2006-08-15

An inherently nonlinear relation between the output current of the tetralateral position sensitive detector (PSD) and the position of the incident light spot has been found theoretically. Based on single-chip microcomputer and the theoretical relation between output current and position, a new signal processor capable of correcting nonlinearity and reducing position measurement deviation of tetralateral PSD was developed. A tetralateral PSD (S1200, 13x13 mm{sup 2}, Hamamatsu Photonics K.K.) was measured with the new signal processor, a linear relation between the output position of the PSD, and the incident position of the light spot was obtained. In the 60% range ofmore » a 13x13 mm{sup 2} active area, the position nonlinearity (rms) was 0.15% and the position measurement deviation (rms) was {+-}20 {mu}m. Compared with traditional analog signal processor, the new signal processor is of better compatibility, lower cost, higher precision, and easier to be interfaced.« less

Development of a new signal processor for tetralateral position sensitive detector based on single-chip microcomputer

NASA Astrophysics Data System (ADS)

Huang, Mei-Zhen; Shi, Long-Zhao; Wang, Yu-Xing; Ni, Yi; Li, Zhen-Qing; Ding, Hai-Feng

2006-08-01

An inherently nonlinear relation between the output current of the tetralateral position sensitive detector (PSD) and the position of the incident light spot has been found theoretically. Based on single-chip microcomputer and the theoretical relation between output current and position, a new signal processor capable of correcting nonlinearity and reducing position measurement deviation of tetralateral PSD was developed. A tetralateral PSD (S1200, 13×13mm2, Hamamatsu Photonics K.K.) was measured with the new signal processor, a linear relation between the output position of the PSD, and the incident position of the light spot was obtained. In the 60% range of a 13×13mm2 active area, the position nonlinearity (rms) was 0.15% and the position measurement deviation (rms) was ±20μm. Compared with traditional analog signal processor, the new signal processor is of better compatibility, lower cost, higher precision, and easier to be interfaced.

Parallel processor for real-time structural control

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tise, B.L.

1992-01-01

A parallel processor that is optimized for real-time linear control has been developed. This modular system consists of A/D modules, D/A modules, and floating-point processor modules. The scalable processor uses up to 1,000 Motorola DSP96002 floating-point processors for a peak computational rate of 60 GFLOPS. Sampling rates up to 625 kHz are supported by this analog-in to analog-out controller. The high processing rate and parallel architecture make this processor suitable for computing state-space equations and other multiply/accumulate-intensive digital filters. Processor features include 14-bit conversion devices, low input-output latency, 240 Mbyte/s synchronous backplane bus, low-skew clock distribution circuit, VME connection tomore » host computer, parallelizing code generator, and look-up-tables for actuator linearization. This processor was designed primarily for experiments in structural control. The A/D modules sample sensors mounted on the structure and the floating-point processor modules compute the outputs using the programmed control equations. The outputs are sent through the D/A module to the power amps used to drive the structure's actuators. The host computer is a Sun workstation. An Open Windows-based control panel is provided to facilitate data transfer to and from the processor, as well as to control the operating mode of the processor. A diagnostic mode is provided to allow stimulation of the structure and acquisition of the structural response via sensor inputs.« less

Development of flame resistant treatment for nomex fibrous structures

NASA Technical Reports Server (NTRS)

Toy, M. S.

1978-01-01

Technology which renders aramid fibrous structures flame resistant through chemical modification was developed. The project scaled up flame resistant treatment from laboratory fabric swatches of a few inches to efficiently producing ten yards of commercial width (41 inches) aromatic polyamide. The radiation intensity problem of the processor was resolved. Further improvement of the processor cooling system was recommended for two reasons: (1) To advance current technology of flame proofing Nomex fabric to higher oxygen enriched atmospheres; and (2) To adapt the processor for direct applicability to low cost commercial fabrics.

Architectures for reasoning in parallel

NASA Technical Reports Server (NTRS)

Hall, Lawrence O.

1989-01-01

The research conducted has dealt with rule-based expert systems. The algorithms that may lead to effective parallelization of them were investigated. Both the forward and backward chained control paradigms were investigated in the course of this work. The best computer architecture for the developed and investigated algorithms has been researched. Two experimental vehicles were developed to facilitate this research. They are Backpac, a parallel backward chained rule-based reasoning system and Datapac, a parallel forward chained rule-based reasoning system. Both systems have been written in Multilisp, a version of Lisp which contains the parallel construct, future. Applying the future function to a function causes the function to become a task parallel to the spawning task. Additionally, Backpac and Datapac have been run on several disparate parallel processors. The machines are an Encore Multimax with 10 processors, the Concert Multiprocessor with 64 processors, and a 32 processor BBN GP1000. Both the Concert and the GP1000 are switch-based machines. The Multimax has all its processors hung off a common bus. All are shared memory machines, but have different schemes for sharing the memory and different locales for the shared memory. The main results of the investigations come from experiments on the 10 processor Encore and the Concert with partitions of 32 or less processors. Additionally, experiments have been run with a stripped down version of EMYCIN.

Fault-tolerant onboard digital information switching and routing for communications satellites

NASA Technical Reports Server (NTRS)

Shalkhauser, Mary JO; Quintana, Jorge A.; Soni, Nitin J.; Kim, Heechul

1993-01-01

The NASA Lewis Research Center is developing an information-switching processor for future meshed very-small-aperture terminal (VSAT) communications satellites. The information-switching processor will switch and route baseband user data onboard the VSAT satellite to connect thousands of Earth terminals. Fault tolerance is a critical issue in developing information-switching processor circuitry that will provide and maintain reliable communications services. In parallel with the conceptual development of the meshed VSAT satellite network architecture, NASA designed and built a simple test bed for developing and demonstrating baseband switch architectures and fault-tolerance techniques. The meshed VSAT architecture and the switching demonstration test bed are described, and the initial switching architecture and the fault-tolerance techniques that were developed and tested are discussed.

Fuel-Flexible Gasification-Combustion Technology for Production of H2 and Sequestration-Ready CO2

DOE Office of Scientific and Technical Information (OSTI.GOV)

George Rizeq; Janice West; Raul Subia

GE Global Research is developing an innovative energy technology for coal gasification with high efficiency and near-zero pollution. This Unmixed Fuel Processor (UFP) technology simultaneously converts coal, steam and air into three separate streams of hydrogen-rich gas, sequestration-ready CO{sub 2}, and high-temperature, high-pressure vitiated air to produce electricity in gas turbines. This is the draft final report for the first stage of the DOE-funded Vision 21 program. The UFP technology development program encompassed lab-, bench- and pilot-scale studies to demonstrate the UFP concept. Modeling and economic assessments were also key parts of this program. The chemical and mechanical feasibility weremore » established via lab and bench-scale testing, and a pilot plant was designed, constructed and operated, demonstrating the major UFP features. Experimental and preliminary modeling results showed that 80% H{sub 2} purity could be achieved, and that a UFP-based energy plant is projected to meet DOE efficiency targets. Future work will include additional pilot plant testing to optimize performance and reduce environmental, operability and combined cycle integration risks. Results obtained to date have confirmed that this technology has the potential to economically meet future efficiency and environmental performance goals.« less

DEMONSTRATION BULLETIN: AOSTRA-SOILTECH ANAEROBIC THERMAL PROCESSOR: WIDE BEACH DEVELOPMENT SITE

EPA Science Inventory

The anaerobic thermal processor (ATP) was developed by UMATAC Industrial Processes under the sponsorship of the Alberta Oil Sands Technology and Research Authority (AOSTRA) and is licensed by SoilTech ATP Systems, Inc., a U.S. corporation. The ATP technology involves a physi...

Production of an environmentally friendly fuel with the aid of ultrasonic waves from a new plant source, and the investigation of its effect on pollutants reduction in a CI engine.

PubMed

Saraee, Hossein Soukht; Jafarmadar, Samad; Kheyrollahi, Javad; Hosseinpour, Alireza

2018-03-01

In this study, methyl ester of Sisymbrium plant seed oil with the chemical formula of C 18 H 34 O 2 is produced for the first time, with the aid of ultrasonic waves and in the presence of a nanocatalyst. After measuring its characteristics and comparing with ASTM standard, it is tested and evaluated with different ratios of diesel fuel in a single-cylinder diesel engine. The reactions are accomplished in a flask by an ultrasonic processor unit and in the presence of CaO-MgO nanocatalyst. The engine tests were conducted based on the engine short time experiment. The results showed that with the increment of biodiesel ratio in the fuel blend, pollutants level of CO, HC, and smoke opacity are decreased comparing diesel fuel due to the improvement of the combustion process, and the amount of NOx emission is increased owing to high pressure and temperature of the combustion chamber. Also, produced biodiesel fuel causes an increment in the fuel consumption and exhaust gasses temperature. Overall, with regard to its effects on the engine and also being a native and easy cultivation plant, it can be resulted that Sisymbrium oil biodiesel and its blends with diesel fuel can be applied as an alternative fuel.

Electric Fuel Pump Condition Monitor System Using Electricalsignature Analysis

DOEpatents

Haynes, Howard D [Knoxville, TN; Cox, Daryl F [Knoxville, TN; Welch, Donald E [Oak Ridge, TN

2005-09-13

A pump diagnostic system and method comprising current sensing probes clamped on electrical motor leads of a pump for sensing only current signals on incoming motor power, a signal processor having a means for buffering and anti-aliasing current signals into a pump motor current signal, and a computer having a means for analyzing, displaying, and reporting motor current signatures from the motor current signal to determine pump health using integrated motor and pump diagnostic parameters.

Joint Long-Range Energy Study for Greater Fairbanks Military Complex

DTIC Science & Technology

2005-02-01

be viewed as a two - stage processor of a fuel or feedstock. The feedstock is first gasified using high-temperature plasma heating sys- tems at...Coal-Fired Boilers with New Circulating Fluidized- Bed Boilers (CFBs). EAFB anticipates replacing two current boilers with two new boilers. This...definition to support DD Form 1391 budget level cost estimates for new coal-fired CHPPs at FWA and EAFB and for two new coal-fired CFBs at EAFB • update

Metal Oxide/Zeolite Combination Absorbs H2S

NASA Technical Reports Server (NTRS)

Voecks, Gerald E.; Sharma, Pramod K.

1989-01-01

Mixed copper and molybdenum oxides supported in pores of zeolite found to remove H2S from mixture of gases rich in hydrogen and steam, at temperatures from 256 to 538 degree C. Absorber of H2S needed to clean up gas streams from fuel processors that incorporate high-temperature steam reformers or hydrodesulfurizing units. Zeolites chosen as supporting materials because of their high porosity, rigidity, alumina content, and variety of both composition and form.

A Scalable, Parallel Approach for Multi-Point, High-Fidelity Aerostructural Optimization of Aircraft Configurations

NASA Astrophysics Data System (ADS)

Kenway, Gaetan K. W.

This thesis presents new tools and techniques developed to address the challenging problem of high-fidelity aerostructural optimization with respect to large numbers of design variables. A new mesh-movement scheme is developed that is both computationally efficient and sufficiently robust to accommodate large geometric design changes and aerostructural deformations. A fully coupled Newton-Krylov method is presented that accelerates the convergence of aerostructural systems and provides a 20% performance improvement over the traditional nonlinear block Gauss-Seidel approach and can handle more exible structures. A coupled adjoint method is used that efficiently computes derivatives for a gradient-based optimization algorithm. The implementation uses only machine accurate derivative techniques and is verified to yield fully consistent derivatives by comparing against the complex step method. The fully-coupled large-scale coupled adjoint solution method is shown to have 30% better performance than the segregated approach. The parallel scalability of the coupled adjoint technique is demonstrated on an Euler Computational Fluid Dynamics (CFD) model with more than 80 million state variables coupled to a detailed structural finite-element model of the wing with more than 1 million degrees of freedom. Multi-point high-fidelity aerostructural optimizations of a long-range wide-body, transonic transport aircraft configuration are performed using the developed techniques. The aerostructural analysis employs Euler CFD with a 2 million cell mesh and a structural finite element model with 300 000 DOF. Two design optimization problems are solved: one where takeoff gross weight is minimized, and another where fuel burn is minimized. Each optimization uses a multi-point formulation with 5 cruise conditions and 2 maneuver conditions. The optimization problems have 476 design variables are optimal results are obtained within 36 hours of wall time using 435 processors. The TOGW minimization results in a 4.2% reduction in TOGW with a 6.6% fuel burn reduction, while the fuel burn optimization resulted in a 11.2% fuel burn reduction with no change to the takeoff gross weight.

Thinking Like a Human

NASA Technical Reports Server (NTRS)

1999-01-01

Accurate Automation Corporation (AAC) of Chattanooga, TN, developed a neural network processor (NNP) for use onboard the NASA- and Air Force-sponsored LoFLYTE aircraft. The processor is modeled after connections in the brain.

Food Processors Skills Building Project. Evaluation Report.

ERIC Educational Resources Information Center

White, Eileen Casey

The Food Processors Skills Building project was undertaken by four Oregon community colleges, with funds from the Oregon Economic Development Department and 11 local food processing companies, to address basic skills needs in the food processing industry through the development and implementation of an industry-specific curriculum. Based on…

A microprocessor based high speed packet switch for satellite communications

NASA Technical Reports Server (NTRS)

Arozullah, M.; Crist, S. C.

1980-01-01

The architectures of a single processor, a three processor, and a multiple processor system are described. The hardware circuits, and software routines required for implementing the three and multiple processor designs are presented. A bit-slice microprocessor was designed and microprogrammed. Maximum throughput was calculated for all three designs. Queue theoretic models for these three designs were developed and utilized to obtain analytical expressions for the average waiting times, overall average response times and average queue sizes. From these expressions, graphs were obtained showing the effect on the system performance of a number of design parameters.

High-throughput label-free screening of euglena gracilis with optofluidic time-stretch quantitative phase microscopy

NASA Astrophysics Data System (ADS)

Guo, Baoshan; Lei, Cheng; Ito, Takuro; Yaxiaer, Yalikun; Kobayashi, Hirofumi; Jiang, Yiyue; Tanaka, Yo; Ozeki, Yasuyuki; Goda, Keisuke

2017-02-01

The development of reliable, sustainable, and economical sources of alternative fuels is an important, but challenging goal for the world. As an alternative to liquid fossil fuels, microalgal biofuel is expected to play a key role in reducing the detrimental effects of global warming since microalgae absorb atmospheric CO2 via photosynthesis. Unfortunately, conventional analytical methods only provide population-averaged lipid contents and fail to characterize a diverse population of microalgal cells with single-cell resolution in a noninvasive and interference-free manner. Here we demonstrate high-throughput label-free single-cell screening of lipid-producing microalgal cells with optofluidic time-stretch quantitative phase microscopy. In particular, we use Euglena gracilis - an attractive microalgal species that produces wax esters (suitable for biodiesel and aviation fuel after refinement) within lipid droplets. Our optofluidic time-stretch quantitative phase microscope is based on an integration of a hydrodynamic-focusing microfluidic chip, an optical time-stretch phase-contrast microscope, and a digital image processor equipped with machine learning. As a result, it provides both the opacity and phase contents of every single cell at a high throughput of 10,000 cells/s. We characterize heterogeneous populations of E. gracilis cells under two different culture conditions to evaluate their lipid production efficiency. Our method holds promise as an effective analytical tool for microalgaebased biofuel production.

FUEL-FLEXIBLE GASIFICATION-COMBUSTION TECHNOLOGY FOR PRODUCTION OF H2 AND SEQUESTRATION-READY CO2

DOE Office of Scientific and Technical Information (OSTI.GOV)

George Rizeq; Janice West; Arnaldo Frydman

It is expected that in the 21st century the Nation will continue to rely on fossil fuels for electricity, transportation, and chemicals. It will be necessary to improve both the process efficiency and environmental impact performance of fossil fuel utilization. GE Energy and Environmental Research Corporation (GE EER) has developed an innovative fuel-flexible Unmixed Fuel Processor (UFP) technology to produce H{sub 2}, power, and sequestration-ready CO{sub 2} from coal and other solid fuels. The UFP module offers the potential for reduced cost, increased process efficiency relative to conventional gasification and combustion systems, and near-zero pollutant emissions including NO{sub x}. GEmore » EER (prime contractor) was awarded a Vision 21 program from U.S. DOE NETL to develop the UFP technology. Work on this Phase I program started on October 1, 2000. The project team includes GE EER, Southern Illinois University at Carbondale (SIU-C), California Energy Commission (CEC), and T. R. Miles, Technical Consultants, Inc. In the UFP technology, coal/opportunity fuels and air are simultaneously converted into separate streams of (1) pure hydrogen that can be utilized in fuel cells, (2) sequestration-ready CO{sub 2}, and (3) high temperature/pressure oxygen-depleted air to produce electricity in a gas turbine. The process produces near-zero emissions and, based on process modeling work, has an estimated process efficiency of 68%, based on electrical and H{sub 2} energy outputs relative to the higher heating value of coal, and an estimated equivalent electrical efficiency of 60%. The Phase I R&D program will determine the operating conditions that maximize separation of CO{sub 2} and pollutants from the vent gas, while simultaneously maximizing coal conversion efficiency and hydrogen production. The program integrates lab-, bench- and pilot-scale studies to demonstrate the UFP technology. This is the tenth quarterly technical progress report for the Vision 21 UFP program supported by U.S. DOE NETL (Contract No. DE-FC26-00FT40974). This report summarizes program accomplishments for the period starting January 1, 2003 and ending March 31, 2003. The report includes an introduction summarizing the UFP technology, main program tasks, and program objectives; it also provides a summary of program activities and accomplishments covering progress in tasks including lab-scale experimental testing, pilot-scale assembly, and program management.« less

FUEL-FLEXIBLE GASIFICATION-COMBUSTION TECHNOLOGY FOR PRODUCTION OF H2 AND SEQUESTRATION-READY CO2

DOE Office of Scientific and Technical Information (OSTI.GOV)

George Rizeq; Janice West; Arnaldo Frydman

It is expected that in the 21st century the Nation will continue to rely on fossil fuels for electricity, transportation, and chemicals. It will be necessary to improve both the process efficiency and environmental impact performance of fossil fuel utilization. GE Energy and Environmental Research Corporation (GE EER) has developed an innovative fuel-flexible Unmixed Fuel Processor (UFP) technology to produce H{sub 2}, power, and sequestration-ready CO{sub 2} from coal and other solid fuels. The UFP module offers the potential for reduced cost, increased process efficiency relative to conventional gasification and combustion systems, and near-zero pollutant emissions including NO{sub x}. GEmore » EER was awarded a Vision 21 program from U.S. DOE NETL to develop the UFP technology. Work on this Phase I program started on October 1, 2000. The project team includes GE EER, California Energy Commission, Southern Illinois University at Carbondale, and T. R. Miles, Technical Consultants, Inc. In the UFP technology, coal/opportunity fuels and air are simultaneously converted into separate streams of (1) pure hydrogen that can be utilized in fuel cells, (2) sequestration-ready CO{sub 2}, and (3) high temperature/pressure oxygen-depleted air to produce electricity in a gas turbine. The process produces near-zero emissions and, based on process modeling work, has an estimated process efficiency of 68%, based on electrical and H{sub 2} energy outputs relative to the higher heating value of coal, and an estimated equivalent electrical efficiency of 60%. The Phase I R&D program will determine the operating conditions that maximize separation of CO{sub 2} and pollutants from the vent gas, while simultaneously maximizing coal conversion efficiency and hydrogen production. The program integrates lab-, bench- and pilot-scale studies to demonstrate the UFP technology. This is the ninth quarterly technical progress report for the Vision 21 UFP program supported by U.S. DOE NETL (Contract No. DE-FC26-00FT40974). This report summarizes program accomplishments for the period starting October 1, 2002 and ending December 31, 2002. The report includes an introduction summarizing the UFP technology, main program tasks, and program objectives; it also provides a summary of program activities and accomplishments covering progress in tasks including lab- and bench-scale experimental testing, pilot-scale design and assembly, and program management.« less

FUEL-FLEXIBLE GASIFICATION-COMBUSTION TECHNOLOGY FOR PRODUCTION OF H2 AND SEQUESTRATION-READY CO2

DOE Office of Scientific and Technical Information (OSTI.GOV)

George Rizeq; Janice West; Arnaldo Frydman

It is expected that in the 21st century the Nation will continue to rely on fossil fuels for electricity, transportation, and chemicals. It will be necessary to improve both the process efficiency and environmental impact performance of fossil fuel utilization. GE Global Research (GEGR) has developed an innovative fuel-flexible Unmixed Fuel Processor (UFP) technology to produce H{sub 2}, power, and sequestration-ready CO{sub 2} from coal and other solid fuels. The UFP module offers the potential for reduced cost, increased process efficiency relative to conventional gasification and combustion systems, and near-zero pollutant emissions including NO{sub x}. GEGR (prime contractor) was awardedmore » a Vision 21 program from U.S. DOE NETL to develop the UFP technology. Work on this Phase I program started on October 1, 2000. The project team includes GEGR, Southern Illinois University at Carbondale (SIU-C), California Energy Commission (CEC), and T. R. Miles, Technical Consultants, Inc. In the UFP technology, coal/opportunity fuels and air are simultaneously converted into separate streams of (1) pure hydrogen that can be utilized in fuel cells, (2) sequestration-ready CO{sub 2}, and (3) high temperature/pressure oxygen-depleted air to produce electricity in a gas turbine. The process produces near-zero emissions and, based on process modeling with best-case scenario assumptions, has an estimated process efficiency of 68%, based on electrical and H{sub 2} energy outputs relative to the higher heating value of coal, and an estimated equivalent electrical efficiency of 60%. The Phase I R&D program will determine the operating conditions that maximize separation of CO{sub 2} and pollutants from the vent gas, while simultaneously maximizing coal conversion efficiency and hydrogen production. The program integrates lab-, bench- and pilot-scale studies to demonstrate the UFP technology. This is the eleventh quarterly technical progress report for the Vision 21 UFP program supported by U.S. DOE NETL (Contract No. DE-FC26-00FT40974). This report summarizes program accomplishments for the period starting April 1, 2003 and ending June 30, 2003. The report includes an introduction summarizing the UFP technology, main program tasks, and program objectives; it also provides a summary of program activities and accomplishments covering progress in tasks including lab-scale experimental testing, pilot-scale assembly, and program management.« less

Mechanically verified hardware implementing an 8-bit parallel IO Byzantine agreement processor

NASA Technical Reports Server (NTRS)

Moore, J. Strother

1992-01-01

Consider a network of four processors that use the Oral Messages (Byzantine Generals) Algorithm of Pease, Shostak, and Lamport to achieve agreement in the presence of faults. Bevier and Young have published a functional description of a single processor that, when interconnected appropriately with three identical others, implements this network under the assumption that the four processors step in synchrony. By formalizing the original Pease, et al work, Bevier and Young mechanically proved that such a network achieves fault tolerance. We develop, formalize, and discuss a hardware design that has been mechanically proven to implement their processor. In particular, we formally define mapping functions from the abstract state space of the Bevier-Young processor to a concrete state space of a hardware module and state a theorem that expresses the claim that the hardware correctly implements the processor. We briefly discuss the Brock-Hunt Formal Hardware Description Language which permits designs both to be proved correct with the Boyer-Moore theorem prover and to be expressed in a commercially supported hardware description language for additional electrical analysis and layout. We briefly describe our implementation.

Towards the formal verification of the requirements and design of a processor interface unit

NASA Technical Reports Server (NTRS)

Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

1993-01-01

The formal verification of the design and partial requirements for a Processor Interface Unit (PIU) using the Higher Order Logic (HOL) theorem-proving system is described. The processor interface unit is a single-chip subsystem within a fault-tolerant embedded system under development within the Boeing Defense and Space Group. It provides the opportunity to investigate the specification and verification of a real-world subsystem within a commercially-developed fault-tolerant computer. An overview of the PIU verification effort is given. The actual HOL listing from the verification effort are documented in a companion NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit - HOL Listings' including the general-purpose HOL theories and definitions that support the PIU verification as well as tactics used in the proofs.

Advanced Avionics and Processor Systems for Space and Lunar Exploration

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Adams, James H.; Ray, Robert E.; Johnson, Michael A.; Cressler, John D.

2009-01-01

NASA's newly named Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to mature and develop the avionic and processor technologies required to fulfill NASA's goals for future space and lunar exploration. Over the past year, multiple advancements have been made within each of the individual AAPS technology development tasks that will facilitate the success of the Constellation program elements. This paper provides a brief review of the project's recent technology advancements, discusses their application to Constellation projects, and addresses the project's plans for the coming year.

An innovative on-board processor for lightsats

NASA Technical Reports Server (NTRS)

Henshaw, R. M.; Ballard, B. W.; Hayes, J. R.; Lohr, D. A.

1990-01-01

The Applied Physics Laboratory (APL) has developed a flightworthy custom microprocessor that increases capability and reduces development costs of lightsat science instruments. This device, called the FRISC (FORTH Reduced Instruction Set Computer), directly executes the high-level language called FORTH, which is ideally suited to the multitasking control and data processing environment of a spaceborne instrument processor. The FRISC will be flown as the onboard processor in the Magnetic Field Experiment on the Freja satllite. APL has achieved a significant increase in onboard processing capability with no increase in cost when compared to the magnetometer instrument on Freja's predecessor, the Viking satellite.

Study of a programmable high speed processor for use on-board satellites

NASA Astrophysics Data System (ADS)

Degavre, J. Cl.; Okkes, R.; Gaillat, G.

The availability of VLSI programmable devices will significantly enhance satellite on-board data processing capabilities. A case study is presented which indicates that computation-intensive processing applications requiring the execution of 100 megainstructions/sec are within the CD power constraints of satellites. It is noted that the current progress in semicustom design technique development and in achievable gate array densities, together with the recent announcement of improved monochip processors, are encouraging the development of an on-board programmable processor architecture able to associate the devices that will appear in communication and military markets.

The PEMFC-integrated CO oxidation — a novel method of simplifying the fuel cell plant

NASA Astrophysics Data System (ADS)

Rohland, Bernd; Plzak, Vojtech

Natural gas and methanol are the most economical fuels for residential fuel cell power generators as well as for mobile PEM-fuel cells. However, they have to be reformed with steam into hydrogen, which is to be cleaned from CO by shift-reaction and by partial oxidation to a level of no more than 30 ppm CO. This level is set by the Pt/Ru-C-anode of the PEMFC. A higher partial oxidation reaction rate for CO than those of Pt/Ru-C can be achieved in an oxidic Au-catalyst system. In the Fe 2O 3-Au system, a reaction rate of 2·10 -3 mol CO/s g Au at 1000 ppm CO and 5% "air bleed" at 80°C is achieved. This high rate allows to construct a catalyst-sheet for each cell within a PEMFC-stack. Practical and theoretical current/voltage characteristics of PEMFCs with catalyst-sheet are presented at 1000 ppm CO in hydrogen with 5% "air bleed". This gives the possibility of simplifying the gas processor of the plant.

Analysis of DuPont and Kodak duplicating films and chemistries in a Fultron spray processor

NASA Technical Reports Server (NTRS)

Weinstein, M. S.

1972-01-01

A test program was conducted with duPont duplicating film type SR 112 and SCOLOR developer and Kodak duplicating film types 2430, 2422, and FE 2628 (SO-467) and MX-641 developer to determine sensitometric and image quality characteristics of these materials when used with a fultron spray processor. The test results show that the SCOLOR developer foams excessively in the fultron processor when used with or without the addition of an antifoaming agent. The Kodak type FE 2628 film with MX-641 chemistry had the longest linear Log E range at a 1.0 gamma. Sensitometric curves and granularity traces for all film process combinations tested are included.

Transient Finite Element Computations on a Variable Transputer System

NASA Technical Reports Server (NTRS)

Smolinski, Patrick J.; Lapczyk, Ireneusz

1993-01-01

A parallel program to analyze transient finite element problems was written and implemented on a system of transputer processors. The program uses the explicit time integration algorithm which eliminates the need for equation solving, making it more suitable for parallel computations. An interprocessor communication scheme was developed for arbitrary two dimensional grid processor configurations. Several 3-D problems were analyzed on a system with a small number of processors.

ELIPS: Toward a Sensor Fusion Processor on a Chip

NASA Technical Reports Server (NTRS)

Daud, Taher; Stoica, Adrian; Tyson, Thomas; Li, Wei-te; Fabunmi, James

1998-01-01

The paper presents the concept and initial tests from the hardware implementation of a low-power, high-speed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) processor is developed to seamlessly combine rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor in compact low power VLSI. The first demonstration of the ELIPS concept targets interceptor functionality; other applications, mainly in robotics and autonomous systems are considered for the future. The main assumption behind ELIPS is that fuzzy, rule-based and neural forms of computation can serve as the main primitives of an "intelligent" processor. Thus, in the same way classic processors are designed to optimize the hardware implementation of a set of fundamental operations, ELIPS is developed as an efficient implementation of computational intelligence primitives, and relies on a set of fuzzy set, fuzzy inference and neural modules, built in programmable analog hardware. The hardware programmability allows the processor to reconfigure into different machines, taking the most efficient hardware implementation during each phase of information processing. Following software demonstrations on several interceptor data, three important ELIPS building blocks (a fuzzy set preprocessor, a rule-based fuzzy system and a neural network) have been fabricated in analog VLSI hardware and demonstrated microsecond-processing times.

Environmentally adaptive processing for shallow ocean applications: A sequential Bayesian approach.

PubMed

Candy, J V

2015-09-01

The shallow ocean is a changing environment primarily due to temperature variations in its upper layers directly affecting sound propagation throughout. The need to develop processors capable of tracking these changes implies a stochastic as well as an environmentally adaptive design. Bayesian techniques have evolved to enable a class of processors capable of performing in such an uncertain, nonstationary (varying statistics), non-Gaussian, variable shallow ocean environment. A solution to this problem is addressed by developing a sequential Bayesian processor capable of providing a joint solution to the modal function tracking and environmental adaptivity problem. Here, the focus is on the development of both a particle filter and an unscented Kalman filter capable of providing reasonable performance for this problem. These processors are applied to hydrophone measurements obtained from a vertical array. The adaptivity problem is attacked by allowing the modal coefficients and/or wavenumbers to be jointly estimated from the noisy measurement data along with tracking of the modal functions while simultaneously enhancing the noisy pressure-field measurements.

Software-Reconfigurable Processors for Spacecraft

NASA Technical Reports Server (NTRS)

Farrington, Allen; Gray, Andrew; Bell, Bryan; Stanton, Valerie; Chong, Yong; Peters, Kenneth; Lee, Clement; Srinivasan, Jeffrey

2005-01-01

A report presents an overview of an architecture for a software-reconfigurable network data processor for a spacecraft engaged in scientific exploration. When executed on suitable electronic hardware, the software performs the functions of a physical layer (in effect, acts as a software radio in that it performs modulation, demodulation, pulse-shaping, error correction, coding, and decoding), a data-link layer, a network layer, a transport layer, and application-layer processing of scientific data. The software-reconfigurable network processor is undergoing development to enable rapid prototyping and rapid implementation of communication, navigation, and scientific signal-processing functions; to provide a long-lived communication infrastructure; and to provide greatly improved scientific-instrumentation and scientific-data-processing functions by enabling science-driven in-flight reconfiguration of computing resources devoted to these functions. This development is an extension of terrestrial radio and network developments (e.g., in the cellular-telephone industry) implemented in software running on such hardware as field-programmable gate arrays, digital signal processors, traditional digital circuits, and mixed-signal application-specific integrated circuits (ASICs).

Software design and implementation of ship heave motion monitoring system based on MBD method

NASA Astrophysics Data System (ADS)

Yu, Yan; Li, Yuhan; Zhang, Chunwei; Kang, Won-Hee; Ou, Jinping

2015-03-01

Marine transportation plays a significant role in the modern transport sector due to its advantage of low cost, large capacity. It is being attached enormous importance to all over the world. Nowadays the related areas of product development have become an existing hot spot. DSP signal processors feature micro volume, low cost, high precision, fast processing speed, which has been widely used in all kinds of monitoring systems. But traditional DSP code development process is time-consuming, inefficiency, costly and difficult. MathWorks company proposed Model-based Design (MBD) to overcome these defects. By calling the target board modules in simulink library to compile and generate the corresponding code for the target processor. And then automatically call DSP integrated development environment CCS for algorithm validation on the target processor. This paper uses the MDB to design the algorithm for the ship heave motion monitoring system. It proves the effectiveness of the MBD run successfully on the processor.

Space Station Water Processor Process Pump

NASA Technical Reports Server (NTRS)

Parker, David

1995-01-01

This report presents the results of the development program conducted under contract NAS8-38250-12 related to the International Space Station (ISS) Water Processor (WP) Process Pump. The results of the Process Pumps evaluation conducted on this program indicates that further development is required in order to achieve the performance and life requirements for the ISSWP.

Design of a massively parallel computer using bit serial processing elements

NASA Technical Reports Server (NTRS)

Aburdene, Maurice F.; Khouri, Kamal S.; Piatt, Jason E.; Zheng, Jianqing

1995-01-01

A 1-bit serial processor designed for a parallel computer architecture is described. This processor is used to develop a massively parallel computational engine, with a single instruction-multiple data (SIMD) architecture. The computer is simulated and tested to verify its operation and to measure its performance for further development.

a Real-Time Computer Music Synthesis System

NASA Astrophysics Data System (ADS)

Lent, Keith Henry

A real time sound synthesis system has been developed at the Computer Music Center of The University of Texas at Austin. This system consists of several stand alone processors that were constructed jointly with White Instruments in Austin. These processors can be programmed as general purpose computers, but are provided with a number of specialized interfaces including: MIDI, 8 bit parallel, high speed serial, 2 channels analog input (18 bit A/Ds, 48kHz sample rate), and 4 channels analog output (18 bit D/As). In addition, a basic music synthesis language (Music56000) has been written in assembly code. On top of this, a symbolic compiler (PatchWork) has been developed to enable algorithms which run in these processors to be created graphically. And finally, a number of efficient time domain numerical models have been developed to enable the construction, simulation, control, and synthesis of many musical acoustics systems in real time on these processors. Specifically, assembly language models for cylindrical and conical horn sections, dissipative losses, tone holes, bells, and a number of linear and nonlinear boundary conditions have been developed.

3-D parallel program for numerical calculation of gas dynamics problems with heat conductivity on distributed memory computational systems (CS)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sofronov, I.D.; Voronin, B.L.; Butnev, O.I.

1997-12-31

The aim of the work performed is to develop a 3D parallel program for numerical calculation of gas dynamics problem with heat conductivity on distributed memory computational systems (CS), satisfying the condition of numerical result independence from the number of processors involved. Two basically different approaches to the structure of massive parallel computations have been developed. The first approach uses the 3D data matrix decomposition reconstructed at temporal cycle and is a development of parallelization algorithms for multiprocessor CS with shareable memory. The second approach is based on using a 3D data matrix decomposition not reconstructed during a temporal cycle.more » The program was developed on 8-processor CS MP-3 made in VNIIEF and was adapted to a massive parallel CS Meiko-2 in LLNL by joint efforts of VNIIEF and LLNL staffs. A large number of numerical experiments has been carried out with different number of processors up to 256 and the efficiency of parallelization has been evaluated in dependence on processor number and their parameters.« less

Proximity Operations Nano-Satellite Flight Demonstration (PONSFD) Rendezvous Proximity Operations Design and Trade Studies

NASA Astrophysics Data System (ADS)

Griesbach, J.; Westphal, J. J.; Roscoe, C.; Hawes, D. R.; Carrico, J. P.

2013-09-01

The Proximity Operations Nano-Satellite Flight Demonstration (PONSFD) program is to demonstrate rendezvous proximity operations (RPO), formation flying, and docking with a pair of 3U CubeSats. The program is sponsored by NASA Ames via the Office of the Chief Technologist (OCT) in support of its Small Spacecraft Technology Program (SSTP). The goal of the mission is to demonstrate complex RPO and docking operations with a pair of low-cost 3U CubeSat satellites using passive navigation sensors. The program encompasses the entire system evolution including system design, acquisition, satellite construction, launch, mission operations, and final disposal. The satellite is scheduled for launch in Fall 2015 with a 1-year mission lifetime. This paper provides a brief mission overview but will then focus on the current design and driving trade study results for the RPO mission specific processor and relevant ground software. The current design involves multiple on-board processors, each specifically tasked with providing mission critical capabilities. These capabilities range from attitude determination and control to image processing. The RPO system processor is responsible for absolute and relative navigation, maneuver planning, attitude commanding, and abort monitoring for mission safety. A low power processor running a Linux operating system has been selected for implementation. Navigation is one of the RPO processor's key tasks. This entails processing data obtained from the on-board GPS unit as well as the on-board imaging sensors. To do this, Kalman filters will be hosted on the processor to ingest and process measurements for maintenance of position and velocity estimates with associated uncertainties. While each satellite carries a GPS unit, it will be used sparsely to conserve power. As such, absolute navigation will mainly consist of propagating past known states, and relative navigation will be considered to be of greater importance. For relative observations, each spacecraft hosts 3 electro-optical sensors dedicated to imaging the companion satellite. The image processor will analyze the images to obtain estimates for range, bearing, and pose, with associated rates and uncertainties. These observations will be fed to the RPO processor's relative Kalman filter to perform relative navigation updates. This paper includes estimates for expected navigation accuracies for both absolute and relative position and velocity. Another key task for the RPO processor is maneuver planning. This includes automation to plan maneuvers to achieve a desired formation configuration or trajectory (including docking), as well as automation to safely react to potentially dangerous situations. This will allow each spacecraft to autonomously plan fuel-efficient maneuvers to achieve a desired trajectory as well as compute adjustment maneuvers to correct for thrusting errors. This paper discusses results from a trade study that has been conducted to examine maneuver targeting algorithms required on-board the spacecraft. Ground software will also work in conjunction with the on-board software to validate and approve maneuvers as necessary.

Spacewire on Earth orbiting scatterometers

NASA Technical Reports Server (NTRS)

Bachmann, Alex; Lang, Minh; Lux, James; Steffke, Richard

2002-01-01

The need for a high speed, reliable and easy to implement communication link has led to the development of a space flight oriented version of IEEE 1355 called SpaceWire. SpaceWire is based on high-speed (200 Mbps) serial point-to-point links using Low Voltage Differential Signaling (LVDS). SpaceWIre has provisions for routing messages between a large network of processors, using wormhole routing for low overhead and latency. {additionally, there are available space qualified hybrids, which provide the Link layer to the user's bus}. A test bed of multiple digital signal processor breadboards, demonstrating the ability to meet signal processing requirements for an orbiting scatterometer has been implemented using three Astrium MCM-DSPs, each breadboard consists of a Multi Chip Module (MCM) that combines a space qualified Digital Signal Processor and peripherals, including IEEE-1355 links. With the addition of appropriate physical layer interfaces and software on the DSP, the SpaceWire link is used to communicate between processors on the test bed, e.g. sending timing references, commands, status, and science data among the processors. Results are presented on development issues surrounding the use of SpaceWire in this environment, from physical layer implementation (cables, connectors, LVDS drivers) to diagnostic tools, driver firmware, and development methodology. The tools, methods, and hardware, software challenges and preliminary performance are investigated and discussed.

Fault tolerant, radiation hard, high performance digital signal processor

NASA Technical Reports Server (NTRS)

Holmann, Edgar; Linscott, Ivan R.; Maurer, Michael J.; Tyler, G. L.; Libby, Vibeke

1990-01-01

An architecture has been developed for a high-performance VLSI digital signal processor that is highly reliable, fault-tolerant, and radiation-hard. The signal processor, part of a spacecraft receiver designed to support uplink radio science experiments at the outer planets, organizes the connections between redundant arithmetic resources, register files, and memory through a shuffle exchange communication network. The configuration of the network and the state of the processor resources are all under microprogram control, which both maps the resources according to algorithmic needs and reconfigures the processing should a failure occur. In addition, the microprogram is reloadable through the uplink to accommodate changes in the science objectives throughout the course of the mission. The processor will be implemented with silicon compiler tools, and its design will be verified through silicon compilation simulation at all levels from the resources to full functionality. By blending reconfiguration with redundancy the processor implementation is fault-tolerant and reliable, and possesses the long expected lifetime needed for a spacecraft mission to the outer planets.

Digital system for structural dynamics simulation

NASA Technical Reports Server (NTRS)

Krauter, A. I.; Lagace, L. J.; Wojnar, M. K.; Glor, C.

1982-01-01

State-of-the-art digital hardware and software for the simulation of complex structural dynamic interactions, such as those which occur in rotating structures (engine systems). System were incorporated in a designed to use an array of processors in which the computation for each physical subelement or functional subsystem would be assigned to a single specific processor in the simulator. These node processors are microprogrammed bit-slice microcomputers which function autonomously and can communicate with each other and a central control minicomputer over parallel digital lines. Inter-processor nearest neighbor communications busses pass the constants which represent physical constraints and boundary conditions. The node processors are connected to the six nearest neighbor node processors to simulate the actual physical interface of real substructures. Computer generated finite element mesh and force models can be developed with the aid of the central control minicomputer. The control computer also oversees the animation of a graphics display system, disk-based mass storage along with the individual processing elements.

The GF-3 SAR Data Processor

PubMed Central

Han, Bing; Ding, Chibiao; Zhong, Lihua; Liu, Jiayin; Qiu, Xiaolan; Hu, Yuxin; Lei, Bin

2018-01-01

The Gaofen-3 (GF-3) data processor was developed as a workstation-based GF-3 synthetic aperture radar (SAR) data processing system. The processor consists of two vital subsystems of the GF-3 ground segment, which are referred to as data ingesting subsystem (DIS) and product generation subsystem (PGS). The primary purpose of DIS is to record and catalogue GF-3 raw data with a transferring format, and PGS is to produce slant range or geocoded imagery from the signal data. This paper presents a brief introduction of the GF-3 data processor, including descriptions of the system architecture, the processing algorithms and its output format. PMID:29534464

Parallel processing in a host plus multiple array processor system for radar

NASA Technical Reports Server (NTRS)

Barkan, B. Z.

1983-01-01

Host plus multiple array processor architecture is demonstrated to yield a modular, fast, and cost-effective system for radar processing. Software methodology for programming such a system is developed. Parallel processing with pipelined data flow among the host, array processors, and discs is implemented. Theoretical analysis of performance is made and experimentally verified. The broad class of problems to which the architecture and methodology can be applied is indicated.

Combined Grinding and Drying of Biomass in One Operation Phase I

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sokhansanj, S

2008-06-26

First American Scientific Corporation (FASC) has developed a unique and innovative grinder/dryer called KDS Micronex. The KS (Kinetic Disintegration System) combines two operations of grinding and drying into a single operation which reduces dependence on external heat input. The machine captures the heat of comminution and combines it will centrifugal forces to expedite moisture extraction from wet biomass. Because it uses mechanical forces rather than providing direct heat to perform the drying operation, it is a simpler machine and uses less energy than conventional grinding and drying operations which occur as two separate steps. The entire compact unit can bemore » transported on a flatbed trailer to the site where biomass is available. Hence, the KDS Micronex is a technology that enables inexpensive pretreatment of waste materials and biomass. A well prepared biomass can be used as feed, fuel or fertilizer instead of being discarded. Electricity and chemical feedstock produced from such biomass would displace the use of fossil fuels and no net greenhouse gas emissions would result from such bio-based operations. Organic fertilizers resulting from the KS Micronex grinding/drying process will be pathogen-free unlike raw animal manures. The feasibility tests on KS during Phase I showed that a prototype machine can be developed, field tested and the technology demonstrated for commercial applications. The present KDS machine can remove up to 400 kg/h of water from a wet feed material. Since biomass processors demand a finished product that is only 10% moist and most raw materials like corn stover, bagasse, layer manure, cow dung, and waste wood have moisture contents of the order of 50%, this water removal rate translates to a production rate of roughly half a ton per hour. this is too small for most processors who are unwilling to acquire multiple machines because of the added complexity to the feed and product removal systems. The economics suffer due to small production rates, because the labor costs are a much larger fraction of the production cost. The goal for further research and development work is to scale up the KDS technology incorporating findings from Phase I into a machine that has superior performance characteristics.« less

Using Modern Design Tools for Digital Avionics Development

NASA Technical Reports Server (NTRS)

Hyde, David W.; Lakin, David R., II; Asquith, Thomas E.

2000-01-01

Using Modem Design Tools for Digital Avionics Development Shrinking development time and increased complexity of new avionics forces the designer to use modem tools and methods during hardware development. Engineers at the Marshall Space Flight Center have successfully upgraded their design flow and used it to develop a Mongoose V based radiation tolerant processor board for the International Space Station's Water Recovery System. The design flow, based on hardware description languages, simulation, synthesis, hardware models, and full functional software model libraries, allowed designers to fully simulate the processor board from reset, through initialization before any boards were built. The fidelity of a digital simulation is limited to the accuracy of the models used and how realistically the designer drives the circuit's inputs during simulation. By using the actual silicon during simulation, device modeling errors are reduced. Numerous design flaws were discovered early in the design phase when they could be easily fixed. The use of hardware models and actual MIPS software loaded into full functional memory models also provided checkout of the software development environment. This paper will describe the design flow used to develop the processor board and give examples of errors that were found using the tools. An overview of the processor board firmware will also be covered.

Extraction of Volatiles from Regolith or Soil on Mars, the Moon, and Asteroids

NASA Technical Reports Server (NTRS)

Linne, Diane; Kleinhenz, Julie; Trunek, Andrew; Hoffman, Stephen; Collins, Jacob

2017-01-01

NASA's Advanced Exploration Systems ISRU Technology Project is evaluating concepts to extract water from all resource types Near-term objectives: Produce high-fidelity mass, power, and volume estimates for mining and processing systems Identify critical challenges for development focus Begin demonstration of component and subsystem technologies in relevant environment Several processor types: Closed processors either partially or completely sealed during processing Open air processors operates at Mars ambient conditions In-situ processors Extract product directly without excavation of raw resource Design features Elimination of sweep gas reduces dust particles in water condensate Pressure maintained by height of soil in hopper Model developed to evaluate key design parameters Geometry: conveyor diameter, screw diameter, shaft diameter, flight spacing and pitch Operational: screw speed vs. screw length (residence time) Thermal: Heat flux, heat transfer to soil Testing to demonstrate feasibility and performance Agglomeration, clogging Pressure rise forced flow to condenser.

Evaluation of pH monitoring as a method of processor control.

PubMed

Stears, J G; Gray, J E; Winkler, N T

1979-01-01

Sensitometry and pH values of the developer solution were compared in controlled over-replenishment, developer depletion, fixer contamination experiments, and on a daily quality control basis. The purpose of these comparisons was to evaluate the potential of pH monitoring as a method of processor control, or a supplement to sensitometry as a method of quality control. Reasonable correlation was found between pH values and film density in two of the three experiments but little or no correlation was found in the third experiment and on a day-to-day basis. The conclusion drawn from these comparisons is that pH monitoring has several limitations which render it unsuitable as a method of daily processor quality control as either a primary or supplementary technique. Sensitometry takes into account all the variables encountered in film processing and is the clear method of choice for processor quality control.

CPU architecture for a fast and energy-saving calculation of convolution neural networks

NASA Astrophysics Data System (ADS)

Knoll, Florian J.; Grelcke, Michael; Czymmek, Vitali; Holtorf, Tim; Hussmann, Stephan

2017-06-01

One of the most difficult problem in the use of artificial neural networks is the computational capacity. Although large search engine companies own specially developed hardware to provide the necessary computing power, for the conventional user only remains the state of the art method, which is the use of a graphic processing unit (GPU) as a computational basis. Although these processors are well suited for large matrix computations, they need massive energy. Therefore a new processor on the basis of a field programmable gate array (FPGA) has been developed and is optimized for the application of deep learning. This processor is presented in this paper. The processor can be adapted for a particular application (in this paper to an organic farming application). The power consumption is only a fraction of a GPU application and should therefore be well suited for energy-saving applications.

A Bayesian sequential processor approach to spectroscopic portal system decisions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sale, K; Candy, J; Breitfeller, E

The development of faster more reliable techniques to detect radioactive contraband in a portal type scenario is an extremely important problem especially in this era of constant terrorist threats. Towards this goal the development of a model-based, Bayesian sequential data processor for the detection problem is discussed. In the sequential processor each datum (detector energy deposit and pulse arrival time) is used to update the posterior probability distribution over the space of model parameters. The nature of the sequential processor approach is that a detection is produced as soon as it is statistically justified by the data rather than waitingmore » for a fixed counting interval before any analysis is performed. In this paper the Bayesian model-based approach, physics and signal processing models and decision functions are discussed along with the first results of our research.« less

A GaAs vector processor based on parallel RISC microprocessors

NASA Astrophysics Data System (ADS)

Misko, Tim A.; Rasset, Terry L.

A vector processor architecture based on the development of a 32-bit microprocessor using gallium arsenide (GaAs) technology has been developed. The McDonnell Douglas vector processor (MVP) will be fabricated completely from GaAs digital integrated circuits. The MVP architecture includes a vector memory of 1 megabyte, a parallel bus architecture with eight processing elements connected in parallel, and a control processor. The processing elements consist of a reduced instruction set CPU (RISC) with four floating-point coprocessor units and necessary memory interface functions. This architecture has been simulated for several benchmark programs including complex fast Fourier transform (FFT), complex inner product, trigonometric functions, and sort-merge routine. The results of this study indicate that the MVP can process a 1024-point complex FFT at a speed of 112 microsec (389 megaflops) while consuming approximately 618 W of power in a volume of approximately 0.1 ft-cubed.

A digital video tracking system

NASA Astrophysics Data System (ADS)

Giles, M. K.

1980-01-01

The Real-Time Videotheodolite (RTV) was developed in connection with the requirement to replace film as a recording medium to obtain the real-time location of an object in the field-of-view (FOV) of a long focal length theodolite. Design philosophy called for a system capable of discriminatory judgment in identifying the object to be tracked with 60 independent observations per second, capable of locating the center of mass of the object projection on the image plane within about 2% of the FOV in rapidly changing background/foreground situations, and able to generate a predicted observation angle for the next observation. A description is given of a number of subsystems of the RTV, taking into account the processor configuration, the video processor, the projection processor, the tracker processor, the control processor, and the optics interface and imaging subsystem.

New developments for SAW channelization for mobile satellite payloads

NASA Technical Reports Server (NTRS)

Peach, R. C.; Mabson, P.

1995-01-01

The use of SAW technology in mobile communication payloads is becoming widely accepted by the industry since being pioneered by Inmarsat for its third generation of satellites. This paper presents new developments in this area, including broadband processors of the Inmarsat 3 type, and the use of SAW filters at L-band. It is demonstrated that SAW processors have considerable potential for increasing the capacity of future communications payloads, while allowing fully transparent operation without any restriction on traffic type or modulation format. In addition to the evolutionary development of Inmarsat type processors, new SAW applications have also emerged recently. Therefore, despite the rapid changes in the industry, it is predicted that SAW processing has a strong future in satellite communications.

Word Processors and the Teaching of Writing.

ERIC Educational Resources Information Center

Crozier, D. S. R.

1986-01-01

Word processors can assist teachers and students by focusing on writing as a process, rather than a product. Word processing breaks writing up into manageable chunks that permit writing skills to develop in an integraged manner. (10 references) (CJH)

Scan line graphics generation on the massively parallel processor

NASA Technical Reports Server (NTRS)

Dorband, John E.

1988-01-01

Described here is how researchers implemented a scan line graphics generation algorithm on the Massively Parallel Processor (MPP). Pixels are computed in parallel and their results are applied to the Z buffer in large groups. To perform pixel value calculations, facilitate load balancing across the processors and apply the results to the Z buffer efficiently in parallel requires special virtual routing (sort computation) techniques developed by the author especially for use on single-instruction multiple-data (SIMD) architectures.

Optical systolic array processor using residue arithmetic

NASA Technical Reports Server (NTRS)

Jackson, J.; Casasent, D.

1983-01-01

The use of residue arithmetic to increase the accuracy and reduce the dynamic range requirements of optical matrix-vector processors is evaluated. It is determined that matrix-vector operations and iterative algorithms can be performed totally in residue notation. A new parallel residue quantizer circuit is developed which significantly improves the performance of the systolic array feedback processor. Results are presented of a computer simulation of this system used to solve a set of three simultaneous equations.

FUEL-FLEXIBLE GASIFICATION-COMBUSTION TECHNOLOGY FOR PRODUCTION OF H2 AND SEQUESTRATION-READY CO2

DOE Office of Scientific and Technical Information (OSTI.GOV)

George Rizeq; Janice West; Arnaldo Frydman

It is expected that in the 21st century the Nation will continue to rely on fossil fuels for electricity, transportation, and chemicals. It will be necessary to improve both the process efficiency and environmental impact performance of fossil fuel utilization. GE Global Research has developed an innovative fuel-flexible Unmixed Fuel Processor (UFP) technology to produce H{sub 2}, power, and sequestration-ready CO{sub 2} from coal and other solid fuels. The UFP module offers the potential for reduced cost, increased process efficiency relative to conventional gasification and combustion systems, and near-zero pollutant emissions including NO{sub x}. GE Global Research (prime contractor) wasmore » awarded a contract from U.S. DOE NETL to develop the UFP technology. Work on this Phase I program started on October 1, 2000. The project team includes GE Global Research, Southern Illinois University at Carbondale (SIU-C), California Energy Commission (CEC), and T. R. Miles, Technical Consultants, Inc. In the UFP technology, coal and air are simultaneously converted into separate streams of (1) high-purity hydrogen that can be utilized in fuel cells or turbines, (2) sequestration-ready CO{sub 2}, and (3) high temperature/pressure vitiated air to produce electricity in a gas turbine. The process produces near-zero emissions and, based on ASPEN Plus process modeling, has an estimated process efficiency of 6 percentage points higher than IGCC with conventional CO{sub 2} separation. The current R&D program will determine the feasibility of the integrated UFP technology through pilot-scale testing, and will investigate operating conditions that maximize separation of CO{sub 2} and pollutants from the vent gas, while simultaneously maximizing coal conversion efficiency and hydrogen production. The program integrates experimental testing, modeling and economic studies to demonstrate the UFP technology. This is the fourteenth quarterly technical progress report for the UFP program, which is supported by U.S. DOE NETL (Contract No. DE-FC26-00FT40974) and GE. This report summarizes program accomplishments for the period starting January 1, 2004 and ending March 31, 2004. The report includes an introduction summarizing the UFP technology, main program tasks, and program objectives; it also provides a summary of program activities and accomplishments covering progress in tasks including lab-scale experimental testing, pilot-scale shakedown and performance testing, program management and technology transfer.« less

FUEL-FLEXIBLE GASIFICATION-COMBUSTION TECHNOLOGY FOR PRODUCTION OF H2 AND SEQUESTRATION-READY CO2

DOE Office of Scientific and Technical Information (OSTI.GOV)

George Rizeq; Janice West; Arnaldo Frydman

It is expected that in the 21st century the Nation will continue to rely on fossil fuels for electricity, transportation, and chemicals. It will be necessary to improve both the process efficiency and environmental impact performance of fossil fuel utilization. GE Global Research (GEGR) has developed an innovative fuel-flexible Unmixed Fuel Processor (UFP) technology to produce H{sub 2}, power, and sequestration-ready CO{sub 2} from coal and other solid fuels. The UFP module offers the potential for reduced cost, increased process efficiency relative to conventional gasification and combustion systems, and near-zero pollutant emissions including NO{sub x}. GEGR (prime contractor) was awardedmore » a contract from U.S. DOE NETL to develop the UFP technology. Work on this Phase I program started on October 1, 2000. The project team includes GEGR, Southern Illinois University at Carbondale (SIU-C), California Energy Commission (CEC), and T. R. Miles, Technical Consultants, Inc. In the UFP technology, coal and air are simultaneously converted into separate streams of (1) high-purity hydrogen that can be utilized in fuel cells or turbines, (2) sequestration-ready CO{sub 2}, and (3) high temperature/pressure vitiated air to produce electricity in a gas turbine. The process produces near-zero emissions and, based on Aspen Plus process modeling, has an estimated process efficiency of 6% higher than IGCC with conventional CO{sub 2} separation. The current R&D program will determine the feasibility of the integrated UFP technology through pilot-scale testing, and will investigate operating conditions that maximize separation of CO{sub 2} and pollutants from the vent gas, while simultaneously maximizing coal conversion efficiency and hydrogen production. The program integrates experimental testing, modeling and economic studies to demonstrate the UFP technology. This is the third annual technical progress report for the UFP program supported by U.S. DOE NETL (Contract No. DE-FC26-00FT40974). This report summarizes program accomplishments for the period starting October 1, 2002 and ending September 30, 2003. The report includes an introduction summarizing the UFP technology, main program tasks, and program objectives; it also provides a summary of program activities and accomplishments covering progress in tasks including lab-scale experimental testing, bench-scale experimental testing, process modeling, pilot-scale system design and assembly, and program management.« less

FUEL-FLEXIBLE GASIFICATION-COMBUSTION TECHNOLOGY FOR PRODUCTION OF H2 AND SEQUESTRATION-READY CO2

DOE Office of Scientific and Technical Information (OSTI.GOV)

George Rizeq; Janice West; Arnaldo Frydman

It is expected that in the 21st century the Nation will continue to rely on fossil fuels for electricity, transportation, and chemicals. It will be necessary to improve both the process efficiency and environmental impact performance of fossil fuel utilization. GE Global Research has developed an innovative fuel-flexible Unmixed Fuel Processor (UFP) technology to produce H{sub 2}, power, and sequestration-ready CO{sub 2} from coal and other solid fuels. The UFP module offers the potential for reduced cost, increased process efficiency relative to conventional gasification and combustion systems, and near-zero pollutant emissions including NO{sub x}. GE Global Research (prime contractor) wasmore » awarded a contract from U.S. DOE NETL to develop the UFP technology. Work on this Phase I program started on October 1, 2000. The project team includes GE Global Research, Southern Illinois University at Carbondale (SIU-C), California Energy Commission (CEC), and T. R. Miles, Technical Consultants, Inc. In the UFP technology, coal and air are simultaneously converted into separate streams of (1) high-purity hydrogen that can be utilized in fuel cells or turbines, (2) sequestration-ready CO{sub 2}, and (3) high temperature/pressure vitiated air to produce electricity in a gas turbine. The process produces near-zero emissions and, based on ASPEN Plus process modeling, has an estimated process efficiency of 6% higher than IGCC with conventional CO{sub 2} separation. The current R&D program will determine the feasibility of the integrated UFP technology through pilot-scale testing, and will investigate operating conditions that maximize separation of CO{sub 2} and pollutants from the vent gas, while simultaneously maximizing coal conversion efficiency and hydrogen production. The program integrates experimental testing, modeling and economic studies to demonstrate the UFP technology. This is the thirteenth quarterly technical progress report for the UFP program, which is supported by U.S. DOE NETL under Contract No. DE-FC26-00FT40974. This report summarizes program accomplishments for the period starting October 1, 2003 and ending December 31, 2003. The report includes an introduction summarizing the UFP technology, main program tasks, and program objectives; it also provides a summary of program activities and accomplishments covering progress in tasks including lab-scale experimental testing, pilot-scale assembly, pilot-scale demonstration and program management and technology transfer.« less

FUEL-FLEXIBLE GASIFICATION-COMBUSTION TECHNOLOGY FOR PRODUCTION OF H2 AND SEQUESTRATION-READY CO2

DOE Office of Scientific and Technical Information (OSTI.GOV)

George Rizeq; Janice West; Arnaldo Frydman

It is expected that in the 21st century the Nation will continue to rely on fossil fuels for electricity, transportation, and chemicals. It will be necessary to improve both the process efficiency and environmental impact performance of fossil fuel utilization. GE Global Research has developed an innovative fuel-flexible Unmixed Fuel Processor (UFP) technology to produce H{sub 2}, power, and sequestration-ready CO{sub 2} from coal and other solid fuels. The UFP module offers the potential for reduced cost, increased process efficiency relative to conventional gasification and combustion systems, and near-zero pollutant emissions including NO{sub x}. GE Global Research (prime contractor) wasmore » awarded a contract from U.S. DOE NETL to develop the UFP technology. Work on this Phase I program started on October 1, 2000. The project team includes GE Global Research, Southern Illinois University at Carbondale (SIU-C), California Energy Commission (CEC), and T. R. Miles, Technical Consultants, Inc. In the UFP technology, coal and air are simultaneously converted into separate streams of (1) high-purity hydrogen that can be utilized in fuel cells or turbines, (2) sequestration-ready CO{sub 2}, and (3) high temperature/pressure vitiated air to produce electricity in a gas turbine. The process produces near-zero emissions and, based on ASPEN Plus process modeling, has an estimated process efficiency of 6 percentage points higher than IGCC with conventional CO{sub 2} separation. The current R&D program has determined the feasibility of the integrated UFP technology through pilot-scale testing, and investigated operating conditions that maximize separation of CO{sub 2} and pollutants from the vent gas, while simultaneously maximizing coal conversion efficiency and hydrogen production. The program integrated experimental testing, modeling and economic studies to demonstrate the UFP technology. This is the fifteenth quarterly technical progress report for the UFP program, which is supported by U.S. DOE NETL (Contract No. DE-FC26-00FT40974) and GE. This report summarizes program accomplishments for the period starting April 1, 2004 and ending June 30, 2004. The report includes an introduction summarizing the UFP technology, main program tasks, and program objectives; it also provides a summary of program activities and accomplishments covering progress in tasks including lab-scale experimental testing, pilot-scale testing, kinetic modeling, program management and technology transfer.« less

A fully integrated mixed-signal neural processor for implantable multichannel cortical recording.

PubMed

Sodagar, Amir M; Wise, Kensall D; Najafi, Khalil

2007-06-01

A 64-channel neural processor has been developed for use in an implantable neural recording microsystem. In the Scan Mode, the processor is capable of detecting neural spikes by programmable positive, negative, or window thresholding. Spikes are tagged with their associated channel addresses and formed into 18-bit data words that are sent serially to the external host. In the Monitor Mode, two channels can be selected and viewed at high resolution for studies where the entire signal is of interest. The processor runs from a 3-V supply and a 2-MHz clock, with a channel scan rate of 64 kS/s and an output bit rate of 2 Mbps.

FPGA-based multiprocessor system for injection molding control.

PubMed

Muñoz-Barron, Benigno; Morales-Velazquez, Luis; Romero-Troncoso, Rene J; Rodriguez-Donate, Carlos; Trejo-Hernandez, Miguel; Benitez-Rangel, Juan P; Osornio-Rios, Roque A

2012-10-18

The plastic industry is a very important manufacturing sector and injection molding is a widely used forming method in that industry. The contribution of this work is the development of a strategy to retrofit control of an injection molding machine based on an embedded system microprocessors sensor network on a field programmable gate array (FPGA) device. Six types of embedded processors are included in the system: a smart-sensor processor, a micro fuzzy logic controller, a programmable logic controller, a system manager, an IO processor and a communication processor. Temperature, pressure and position are controlled by the proposed system and experimentation results show its feasibility and robustness. As validation of the present work, a particular sample was successfully injected.

Development Status of the International Space Station Urine Processor Assembly

NASA Technical Reports Server (NTRS)

Holder, Donald W.; Hutchens, Cindy F.

2003-01-01

NASA, Marshall Space Flight Center (MSFC) is developing a Urine Processor Assembly (UPA) for the International Space Station (ISS). The UPA uses Vapor Compression Distillation (VCD) technology to reclaim water from pre-treated urine. This water is further processed by the Water Processor Assembly (WPA) to potable quality standards for use on the ISS. NASA has developed this technology over the last 25-30 years. Over this history, many technical issues were solved with thousands of hours of ground testing that demonstrate the ability of the UPA technology to reclaim water from urine. In recent years, NASA MSFC has been responsible for taking the UPA technology to "flight design" maturity. This paper will give a brief overview of the UPA design and a status of the major design and development efforts completed recently to mature the UPA to a flight level.

Developing infrared array controller with software real time operating system

NASA Astrophysics Data System (ADS)

Sako, Shigeyuki; Miyata, Takashi; Nakamura, Tomohiko; Motohara, Kentaro; Uchimoto, Yuka Katsuno; Onaka, Takashi; Kataza, Hirokazu

2008-07-01

Real-time capabilities are required for a controller of a large format array to reduce a dead-time attributed by readout and data transfer. The real-time processing has been achieved by dedicated processors including DSP, CPLD, and FPGA devices. However, the dedicated processors have problems with memory resources, inflexibility, and high cost. Meanwhile, a recent PC has sufficient resources of CPUs and memories to control the infrared array and to process a large amount of frame data in real-time. In this study, we have developed an infrared array controller with a software real-time operating system (RTOS) instead of the dedicated processors. A Linux PC equipped with a RTAI extension and a dual-core CPU is used as a main computer, and one of the CPU cores is allocated to the real-time processing. A digital I/O board with DMA functions is used for an I/O interface. The signal-processing cores are integrated in the OS kernel as a real-time driver module, which is composed of two virtual devices of the clock processor and the frame processor tasks. The array controller with the RTOS realizes complicated operations easily, flexibly, and at a low cost.

Replication of Space-Shuttle Computers in FPGAs and ASICs

NASA Technical Reports Server (NTRS)

Ferguson, Roscoe C.

2008-01-01

A document discusses the replication of the functionality of the onboard space-shuttle general-purpose computers (GPCs) in field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The purpose of the replication effort is to enable utilization of proven space-shuttle flight software and software-development facilities to the extent possible during development of software for flight computers for a new generation of launch vehicles derived from the space shuttles. The replication involves specifying the instruction set of the central processing unit and the input/output processor (IOP) of the space-shuttle GPC in a hardware description language (HDL). The HDL is synthesized to form a "core" processor in an FPGA or, less preferably, in an ASIC. The core processor can be used to create a flight-control card to be inserted into a new avionics computer. The IOP of the GPC as implemented in the core processor could be designed to support data-bus protocols other than that of a multiplexer interface adapter (MIA) used in the space shuttle. Hence, a computer containing the core processor could be tailored to communicate via the space-shuttle GPC bus and/or one or more other buses.

FPGA wavelet processor design using language for instruction-set architectures (LISA)

NASA Astrophysics Data System (ADS)

Meyer-Bäse, Uwe; Vera, Alonzo; Rao, Suhasini; Lenk, Karl; Pattichis, Marios

2007-04-01

The design of an microprocessor is a long, tedious, and error-prone task consisting of typically three design phases: architecture exploration, software design (assembler, linker, loader, profiler), architecture implementation (RTL generation for FPGA or cell-based ASIC) and verification. The Language for instruction-set architectures (LISA) allows to model a microprocessor not only from instruction-set but also from architecture description including pipelining behavior that allows a design and development tool consistency over all levels of the design. To explore the capability of the LISA processor design platform a.k.a. CoWare Processor Designer we present in this paper three microprocessor designs that implement a 8/8 wavelet transform processor that is typically used in today's FBI fingerprint compression scheme. We have designed a 3 stage pipelined 16 bit RISC processor (NanoBlaze). Although RISC μPs are usually considered "fast" processors due to design concept like constant instruction word size, deep pipelines and many general purpose registers, it turns out that DSP operations consume essential processing time in a RISC processor. In a second step we have used design principles from programmable digital signal processor (PDSP) to improve the throughput of the DWT processor. A multiply-accumulate operation along with indirect addressing operation were the key to achieve higher throughput. A further improvement is possible with today's FPGA technology. Today's FPGAs offer a large number of embedded array multipliers and it is now feasible to design a "true" vector processor (TVP). A multiplication of two vectors can be done in just one clock cycle with our TVP, a complete scalar product in two clock cycles. Code profiling and Xilinx FPGA ISE synthesis results are provided that demonstrate the essential improvement that a TVP has compared with traditional RISC or PDSP designs.

Landsat image registration for agricultural applications

NASA Technical Reports Server (NTRS)

Wolfe, R. H., Jr.; Juday, R. D.; Wacker, A. G.; Kaneko, T.

1982-01-01

An image registration system has been developed at the NASA Johnson Space Center (JSC) to spatially align multi-temporal Landsat acquisitions for use in agriculture and forestry research. Working in conjunction with the Master Data Processor (MDP) at the Goddard Space Flight Center, it functionally replaces the long-standing LACIE Registration Processor as JSC's data supplier. The system represents an expansion of the techniques developed for the MDP and LACIE Registration Processor, and it utilizes the experience gained in an IBM/JSC effort evaluating the performance of the latter. These techniques are discussed in detail. Several tests were developed to evaluate the registration performance of the system. The results indicate that 1/15-pixel accuracy (about 4m for Landsat MSS) is achievable in ideal circumstances, sub-pixel accuracy (often to 0.2 pixel or better) was attained on a representative set of U.S. acquisitions, and a success rate commensurate with the LACIE Registration Processor was realized. The system has been employed in a production mode on U.S. and foreign data, and a performance similar to the earlier tests has been noted.

Limit characteristics of digital optoelectronic processor

NASA Astrophysics Data System (ADS)

Kolobrodov, V. G.; Tymchik, G. S.; Kolobrodov, M. S.

2018-01-01

In this article, the limiting characteristics of a digital optoelectronic processor are explored. The limits are defined by diffraction effects and a matrix structure of the devices for input and output of optical signals. The purpose of a present research is to optimize the parameters of the processor's components. The developed physical and mathematical model of DOEP allowed to establish the limit characteristics of the processor, restricted by diffraction effects and an array structure of the equipment for input and output of optical signals, as well as to optimize the parameters of the processor's components. The diameter of the entrance pupil of the Fourier lens is determined by the size of SLM and the pixel size of the modulator. To determine the spectral resolution, it is offered to use a concept of an optimum phase when the resolved diffraction maxima coincide with the pixel centers of the radiation detector.

Design of a dataway processor for a parallel image signal processing system

NASA Astrophysics Data System (ADS)

Nomura, Mitsuru; Fujii, Tetsuro; Ono, Sadayasu

1995-04-01

Recently, demands for high-speed signal processing have been increasing especially in the field of image data compression, computer graphics, and medical imaging. To achieve sufficient power for real-time image processing, we have been developing parallel signal-processing systems. This paper describes a communication processor called 'dataway processor' designed for a new scalable parallel signal-processing system. The processor has six high-speed communication links (Dataways), a data-packet routing controller, a RISC CORE, and a DMA controller. Each communication link operates at 8-bit parallel in a full duplex mode at 50 MHz. Moreover, data routing, DMA, and CORE operations are processed in parallel. Therefore, sufficient throughput is available for high-speed digital video signals. The processor is designed in a top- down fashion using a CAD system called 'PARTHENON.' The hardware is fabricated using 0.5-micrometers CMOS technology, and its hardware is about 200 K gates.

Safe and Efficient Support for Embeded Multi-Processors in ADA

NASA Astrophysics Data System (ADS)

Ruiz, Jose F.

2010-08-01

New software demands increasing processing power, and multi-processor platforms are spreading as the answer to achieve the required performance. Embedded real-time systems are also subject to this trend, but in the case of real-time mission-critical systems, the properties of reliability, predictability and analyzability are also paramount. The Ada 2005 language defined a subset of its tasking model, the Ravenscar profile, that provides the basis for the implementation of deterministic and time analyzable applications on top of a streamlined run-time system. This Ravenscar tasking profile, originally designed for single processors, has proven remarkably useful for modelling verifiable real-time single-processor systems. This paper proposes a simple extension to the Ravenscar profile to support multi-processor systems using a fully partitioned approach. The implementation of this scheme is simple, and it can be used to develop applications amenable to schedulability analysis.

Developing a Contemporary Dairy Foods Extension Program: A Training and Technical Resource Needs Assessment of Pennsylvania Dairy Foods Processors

ERIC Educational Resources Information Center

Syrko, Joseph; Kaylegian, Kerry E.

2015-01-01

Growth in the dairy industry and the passage of the Food Safety Modernization Act have renewed interest in dairy foods processing extension positions. A needs assessment survey was sent to Pennsylvania dairy processors and raw milk providers to guide priorities for a dairy foods extension program. The successful development and delivery of…

High Performance Processors for Space Environments: A Subproject of the NASA Exploration Missions Systems Directorate "Radiation Hardened Electronics for Space Environments" Technology Development Program

NASA Technical Reports Server (NTRS)

Johnson, M.; Label, K.; McCabe, J.; Powell, W.; Bolotin, G.; Kolawa, E.; Ng, T.; Hyde, D.

2007-01-01

Implementation of challenging Exploration Systems Missions Directorate objectives and strategies can be constrained by onboard computing capabilities and power efficiencies. The Radiation Hardened Electronics for Space Environments (RHESE) High Performance Processors for Space Environments project will address this challenge by significantly advancing the sustained throughput and processing efficiency of high-per$ormance radiation-hardened processors, targeting delivery of products by the end of FY12.

Design and Analysis of Scheduling Policies for Real-Time Computer Systems

DTIC Science & Technology

1992-01-01

C. M. Krishna, "The Impact of Workload on the Reliability of Real-Time Processor Triads," to appear in Micro . Rel. [17] J.F. Kurose, "Performance... Processor Triads", to appear in Micro . Rel. "* J.F. Kurose. "Performance Analysis of Minimum Laxity Scheduling in Discrete Time Queue- ing Systems", to...exponentially distributed service times and deadlines. A similar model was developed for the ED policy for a single processor system under identical

The 3D laser radar vision processor system

NASA Astrophysics Data System (ADS)

Sebok, T. M.

1990-10-01

Loral Defense Systems (LDS) developed a 3D Laser Radar Vision Processor system capable of detecting, classifying, and identifying small mobile targets as well as larger fixed targets using three dimensional laser radar imagery for use with a robotic type system. This processor system is designed to interface with the NASA Johnson Space Center in-house Extra Vehicular Activity (EVA) Retriever robot program and provide to it needed information so it can fetch and grasp targets in a space-type scenario.

Backend Control Processor for a Multi-Processor Relational Database Computer System.

DTIC Science & Technology

1984-12-01

SCHOOL OF ENGI. UNCRSIFID MPONTIFF DEC 84 AFXT/GCS/ENG/84D-22 F/O 9/2 L ommhhhhmhhml mhhhommhhhhhm i-2 8 -- U0. 11111= Q. 2 111.8IIII- 1111111..6...THESIS Presented to the Faculty of the School of Engineering of the Air Force Institute of Technology Air University In Partial Fulfillment of the...development of a Backend Multi-Processor Relational Database Computer System. This thesis addresses a single component of this system, the Backend Control

The 3D laser radar vision processor system

NASA Technical Reports Server (NTRS)

Sebok, T. M.

1990-01-01

Loral Defense Systems (LDS) developed a 3D Laser Radar Vision Processor system capable of detecting, classifying, and identifying small mobile targets as well as larger fixed targets using three dimensional laser radar imagery for use with a robotic type system. This processor system is designed to interface with the NASA Johnson Space Center in-house Extra Vehicular Activity (EVA) Retriever robot program and provide to it needed information so it can fetch and grasp targets in a space-type scenario.

SPROC: A multiple-processor DSP IC

NASA Technical Reports Server (NTRS)

Davis, R.

1991-01-01

A large, single-chip, multiple-processor, digital signal processing (DSP) integrated circuit (IC) fabricated in HP-Cmos34 is presented. The innovative architecture is best suited for analog and real-time systems characterized by both parallel signal data flows and concurrent logic processing. The IC is supported by a powerful development system that transforms graphical signal flow graphs into production-ready systems in minutes. Automatic compiler partitioning of tasks among four on-chip processors gives the IC the signal processing power of several conventional DSP chips.

Multi-Core Programming Design Patterns: Stream Processing Algorithms for Dynamic Scene Perceptions

DTIC Science & Technology

2014-05-01

processor developed by IBM and other companies , incorpo- rates the verb—POWER5— processor as the Power Processor Element (PPE), one of the early general...deliver an power efficient single-precision peak performance of more than 256 GFlops. Substantially more raw power became available later, when nVIDIA ...algorithms, including IBM’s Cell/B.E., GPUs from NVidia and AMD and many-core CPUs from Intel.27 The vast growth of digital video content has been a

Parallel computing on Unix workstation arrays

NASA Astrophysics Data System (ADS)

Reale, F.; Bocchino, F.; Sciortino, S.

1994-12-01

We have tested arrays of general-purpose Unix workstations used as MIMD systems for massive parallel computations. In particular we have solved numerically a demanding test problem with a 2D hydrodynamic code, generally developed to study astrophysical flows, by exucuting it on arrays either of DECstations 5000/200 on Ethernet LAN, or of DECstations 3000/400, equipped with powerful Alpha processors, on FDDI LAN. The code is appropriate for data-domain decomposition, and we have used a library for parallelization previously developed in our Institute, and easily extended to work on Unix workstation arrays by using the PVM software toolset. We have compared the parallel efficiencies obtained on arrays of several processors to those obtained on a dedicated MIMD parallel system, namely a Meiko Computing Surface (CS-1), equipped with Intel i860 processors. We discuss the feasibility of using non-dedicated parallel systems and conclude that the convenience depends essentially on the size of the computational domain as compared to the relative processor power and network bandwidth. We point out that for future perspectives a parallel development of processor and network technology is important, and that the software still offers great opportunities of improvement, especially in terms of latency times in the message-passing protocols. In conditions of significant gain in terms of speedup, such workstation arrays represent a cost-effective approach to massive parallel computations.

Advanced development of a programmable power processor

NASA Technical Reports Server (NTRS)

Lukens, F. E.; Lanier, J. R., Jr.; Kapustka, R. E.; Graves, J.

1980-01-01

The need for the development of a multipurpose flexible programmable power processor (PPP) has increased significantly in recent years to reduce ever rising development costs. One of the program requirements the PPP specification will cover is the 25 kW power module power conversion needs. The 25 kW power module could support the Space Shuttle program during the 1980s and 1990s and could be the stepping stone to future large space programs. Trades that led to selection of a microprocessor controlled power processor are briefly discussed. Emphasis is given to the power processing equipment that uses a microprocessor to provide versatility that allows multiple use and to provide for future growth by reprogramming output voltage to a higher level (to 120 V from 30 V). Component selection and design considerations are also discussed.

Direct RF A-O Processor Spectrum Analyzer.

DTIC Science & Technology

1981-08-01

The primary objective was to develop and demonstrate design approach, along with the associated processing technologies, for a wideband acousto optic Bragg...cell spectrum analyzer. The signal processor used to demonstrate feasibility of the technical approach consisted of two bulk wave acousto optic deflectors

Optimization of Particle-in-Cell Codes on RISC Processors

NASA Technical Reports Server (NTRS)

Decyk, Viktor K.; Karmesin, Steve Roy; Boer, Aeint de; Liewer, Paulette C.

1996-01-01

General strategies are developed to optimize particle-cell-codes written in Fortran for RISC processors which are commonly used on massively parallel computers. These strategies include data reorganization to improve cache utilization and code reorganization to improve efficiency of arithmetic pipelines.

Human factors considerations in the evaluation of processor-based signal and train control systems

DOT National Transportation Integrated Search

2007-06-01

In August 2001, the Federal Railroad Administration issued the notice of proposed rulemaking: Standards for Development and : Use of Processor-Based Signal and Train Control Systems (49 Code of Federal Regulations Part 236). This proposed rule addres...

Technology Developments in Radiation-Hardened Electronics for Space Environments

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Howell, Joe T.

2008-01-01

The Radiation Hardened Electronics for Space Environments (RHESE) project consists of a series of tasks designed to develop and mature a broad spectrum of radiation hardened and low temperature electronics technologies. Three approaches are being taken to address radiation hardening: improved material hardness, design techniques to improve radiation tolerance, and software methods to improve radiation tolerance. Within these approaches various technology products are being addressed including Field Programmable Gate Arrays (FPGA), Field Programmable Analog Arrays (FPAA), MEMS, Serial Processors, Reconfigurable Processors, and Parallel Processors. In addition to radiation hardening, low temperature extremes are addressed with a focus on material and design approaches. System level applications for the RHESE technology products are discussed.

A Parallel Algorithm for Contact in a Finite Element Hydrocode

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pierce, Timothy G.

A parallel algorithm is developed for contact/impact of multiple three dimensional bodies undergoing large deformation. As time progresses the relative positions of contact between the multiple bodies changes as collision and sliding occurs. The parallel algorithm is capable of tracking these changes and enforcing an impenetrability constraint and momentum transfer across the surfaces in contact. Portions of the various surfaces of the bodies are assigned to the processors of a distributed-memory parallel machine in an arbitrary fashion, known as the primary decomposition. A secondary, dynamic decomposition is utilized to bring opposing sections of the contacting surfaces together on the samemore » processors, so that opposing forces may be balanced and the resultant deformation of the bodies calculated. The secondary decomposition is accomplished and updated using only local communication with a limited subset of neighbor processors. Each processor represents both a domain of the primary decomposition and a domain of the secondary, or contact, decomposition. Thus each processor has four sets of neighbor processors: (a) those processors which represent regions adjacent to it in the primary decomposition, (b) those processors which represent regions adjacent to it in the contact decomposition, (c) those processors which send it the data from which it constructs its contact domain, and (d) those processors to which it sends its primary domain data, from which they construct their contact domains. The latter three of these neighbor sets change dynamically as the simulation progresses. By constraining all communication to these sets of neighbors, all global communication, with its attendant nonscalable performance, is avoided. A set of tests are provided to measure the degree of scalability achieved by this algorithm on up to 1024 processors. Issues related to the operating system of the test platform which lead to some degradation of the results are analyzed. This algorithm has been implemented as the contact capability of the ALE3D multiphysics code, and is currently in production use.« less

RTEMS SMP and MTAPI for Efficient Multi-Core Space Applications on LEON3/LEON4 Processors

NASA Astrophysics Data System (ADS)

Cederman, Daniel; Hellstrom, Daniel; Sherrill, Joel; Bloom, Gedare; Patte, Mathieu; Zulianello, Marco

2015-09-01

This paper presents the final result of an European Space Agency (ESA) activity aimed at improving the software support for LEON processors used in SMP configurations. One of the benefits of using a multicore system in a SMP configuration is that in many instances it is possible to better utilize the available processing resources by load balancing between cores. This however comes with the cost of having to synchronize operations between cores, leading to increased complexity. While in an AMP system one can use multiple instances of operating systems that are only uni-processor capable, a SMP system requires the operating system to be written to support multicore systems. In this activity we have improved and extended the SMP support of the RTEMS real-time operating system and ensured that it fully supports the multicore capable LEON processors. The targeted hardware in the activity has been the GR712RC, a dual-core core LEON3FT processor, and the functional prototype of ESA's Next Generation Multiprocessor (NGMP), a quad core LEON4 processor. The final version of the NGMP is now available as a product under the name GR740. An implementation of the Multicore Task Management API (MTAPI) has been developed as part of this activity to aid in the parallelization of applications for RTEMS SMP. It allows for simplified development of parallel applications using the task-based programming model. An existing space application, the Gaia Video Processing Unit, has been ported to RTEMS SMP using the MTAPI implementation to demonstrate the feasibility and usefulness of multicore processors for space payload software. The activity is funded by ESA under contract 4000108560/13/NL/JK. Gedare Bloom is supported in part by NSF CNS-0934725.

NCC Simulation Model: Simulating the operations of the network control center, phase 2

NASA Technical Reports Server (NTRS)

Benjamin, Norman M.; Paul, Arthur S.; Gill, Tepper L.

1992-01-01

The simulation of the network control center (NCC) is in the second phase of development. This phase seeks to further develop the work performed in phase one. Phase one concentrated on the computer systems and interconnecting network. The focus of phase two will be the implementation of the network message dialogues and the resources controlled by the NCC. These resources are requested, initiated, monitored and analyzed via network messages. In the NCC network messages are presented in the form of packets that are routed across the network. These packets are generated, encoded, decoded and processed by the network host processors that generate and service the message traffic on the network that connects these hosts. As a result, the message traffic is used to characterize the work done by the NCC and the connected network. Phase one of the model development represented the NCC as a network of bi-directional single server queues and message generating sources. The generators represented the external segment processors. The served based queues represented the host processors. The NCC model consists of the internal and external processors which generate message traffic on the network that links these hosts. To fully realize the objective of phase two it is necessary to identify and model the processes in each internal processor. These processes live in the operating system of the internal host computers and handle tasks such as high speed message exchanging, ISN and NFE interface, event monitoring, network monitoring, and message logging. Inter process communication is achieved through the operating system facilities. The overall performance of the host is determined by its ability to service messages generated by both internal and external processors.

Baseband processor development/test performance for 30/20 GHz SS-TDMA communication system

NASA Technical Reports Server (NTRS)

Brown, L.; Sabourin, D.; Attwood, S.

1984-01-01

The baseband processor (BBP) development for the 30/20 GHz Satellite Communication System is described. The SS-TDMA concept for future satellite communications is reviewed, describing the overall system, the satellite payload, and the frequency plan. A brief general description of the BBP is given, and the proof-of-concept model of the BBP is summarized. Key technologies and custom LSI developed for the BBP are listed. Finally, key technology developments and test data are reported for the BBP.

A demonstration of pig lard as an industrial boiler fuel

DOE Office of Scientific and Technical Information (OSTI.GOV)

Miller, B.G.; Badger, M.; Larsen, J.

Hatfield Quality Meats is a family owned regional meat processor and vendor and has multiple facilities in Pennsylvania. The main plant and corporate offices are located in Hatfield, Pennsylvania where they process 7,000 hogs per day. Two of Hatfield's by-products are lard and choice white grease (CWG), both of which are produced in large quantities. The lard, which is stored warm and liquid, is sold by tanker truck to veal producers, by 55-gallon drums to commercial bakeries, in 5-gallon pails to a variety of restaurants, and periodically in 1-pound tins to grocery stores. The CWG, which is a rendered product,more » is also sold to veal producers. A decrease in sales could leave the company with large excess of these products and difficult disposal problems. Hatfield Quality Meats, Lehigh University, and Penn State's the Energy Institute evaluated the liquid lard as an industrial boiler fuel and obtained the necessary handleability and combustion data to allow for its use as a supplemental fuel in Hatfield's process, were burned in Penn State's research boiler. The boiler, which has a nominal firing rate of two million Btu/h, is a 150 psig working pressure, A-frame watertube boiler. In addition to the lard samples, No.6 fuel oil was fired for baseline comparison. This paper discusses the comparison of lard and No.6 fuel oil as boiler fuels. Issues discussed include fuel characterization, material handling, combustion performance, flame character and stability, and emissions.« less

Mobile Thread Task Manager

NASA Technical Reports Server (NTRS)

Clement, Bradley J.; Estlin, Tara A.; Bornstein, Benjamin J.

2013-01-01

The Mobile Thread Task Manager (MTTM) is being applied to parallelizing existing flight software to understand the benefits and to develop new techniques and architectural concepts for adapting software to multicore architectures. It allocates and load-balances tasks for a group of threads that migrate across processors to improve cache performance. In order to balance-load across threads, the MTTM augments a basic map-reduce strategy to draw jobs from a global queue. In a multicore processor, memory may be "homed" to the cache of a specific processor and must be accessed from that processor. The MTTB architecture wraps access to data with thread management to move threads to the home processor for that data so that the computation follows the data in an attempt to avoid L2 cache misses. Cache homing is also handled by a memory manager that translates identifiers to processor IDs where the data will be homed (according to rules defined by the user). The user can also specify the number of threads and processors separately, which is important for tuning performance for different patterns of computation and memory access. MTTM efficiently processes tasks in parallel on a multiprocessor computer. It also provides an interface to make it easier to adapt existing software to a multiprocessor environment.

Reconfigurable signal processor designs for advanced digital array radar systems

NASA Astrophysics Data System (ADS)

Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

2017-05-01

The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

Parallelization of KENO-Va Monte Carlo code

NASA Astrophysics Data System (ADS)

Ramón, Javier; Peña, Jorge

1995-07-01

KENO-Va is a code integrated within the SCALE system developed by Oak Ridge that solves the transport equation through the Monte Carlo Method. It is being used at the Consejo de Seguridad Nuclear (CSN) to perform criticality calculations for fuel storage pools and shipping casks. Two parallel versions of the code: one for shared memory machines and other for distributed memory systems using the message-passing interface PVM have been generated. In both versions the neutrons of each generation are tracked in parallel. In order to preserve the reproducibility of the results in both versions, advanced seeds for random numbers were used. The CONVEX C3440 with four processors and shared memory at CSN was used to implement the shared memory version. A FDDI network of 6 HP9000/735 was employed to implement the message-passing version using proprietary PVM. The speedup obtained was 3.6 in both cases.

PHANTOM: Practical Oblivious Computation in a Secure Processor

DTIC Science & Technology

2014-05-16

Utilizing Multiple FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6 Implementation on the HC-2ex 50 6.1 Integration with a RISC -V...development of Phantom, Mohit also contributed to the code base, in particular with regard to the integration between the ORAM controller and the RISC -V...well. v Tremendous thanks is owed to the team that developed the RISC -V processor Phantom is using: among other contributors, this includes

ASR-9 processor augmentation card (9-PAC) phase II scan-scan correlator algorithms

DOT National Transportation Integrated Search

2001-04-26

The report documents the scan-scan correlator (tracker) algorithm developed for Phase II of the ASR-9 Processor Augmentation Card (9-PAC) project. The improved correlation and tracking algorithms in 9-PAC Phase II decrease the incidence of false-alar...

Impact of diet on the design of waste processors in CELSS

NASA Technical Reports Server (NTRS)

Waleh, Ahmad; Kanevsky, Valery; Nguyen, Thoi K.; Upadhye, Ravi; Wydeven, Theodore

1991-01-01

The preliminary results of a design analysis for a waste processor which employs existing technologies and takes into account the constraints of human diet are presented. The impact of diet is determined by using a model and an algorithm developed for the control and management of diet in a Controlled Ecological Life Support System (CELSS). A material and energy balance model for thermal oxidation of waste is developed which is consistent with both physical/chemical methods of incineration and supercritical water oxidation. The two models yield quantitative analysis of the diet and waste streams and the specific design parameters for waste processors, respectively. The results demonstrate that existing technologies can meet the demands of waste processing, but the choice and design of the processors or processing methods will be sensitive to the constraints of diet. The numerical examples are chosen to display the nature and extent of the gap in the available experiment information about CELSS requirements.

Reconfigurable L-Band Radar

NASA Technical Reports Server (NTRS)

Rincon, Rafael F.

2008-01-01

The reconfigurable L-Band radar is an ongoing development at NASA/GSFC that exploits the capability inherently in phased array radar systems with a state-of-the-art data acquisition and real-time processor in order to enable multi-mode measurement techniques in a single radar architecture. The development leverages on the L-Band Imaging Scatterometer, a radar system designed for the development and testing of new radar techniques; and the custom-built DBSAR processor, a highly reconfigurable, high speed data acquisition and processing system. The radar modes currently implemented include scatterometer, synthetic aperture radar, and altimetry; and plans to add new modes such as radiometry and bi-static GNSS signals are being formulated. This development is aimed at enhancing the radar remote sensing capabilities for airborne and spaceborne applications in support of Earth Science and planetary exploration This paper describes the design of the radar and processor systems, explains the operational modes, and discusses preliminary measurements and future plans.

FPGA-Based Multiprocessor System for Injection Molding Control

PubMed Central

Muñoz-Barron, Benigno; Morales-Velazquez, Luis; Romero-Troncoso, Rene J.; Rodriguez-Donate, Carlos; Trejo-Hernandez, Miguel; Benitez-Rangel, Juan P.; Osornio-Rios, Roque A.

2012-01-01

The plastic industry is a very important manufacturing sector and injection molding is a widely used forming method in that industry. The contribution of this work is the development of a strategy to retrofit control of an injection molding machine based on an embedded system microprocessors sensor network on a field programmable gate array (FPGA) device. Six types of embedded processors are included in the system: a smart-sensor processor, a micro fuzzy logic controller, a programmable logic controller, a system manager, an IO processor and a communication processor. Temperature, pressure and position are controlled by the proposed system and experimentation results show its feasibility and robustness. As validation of the present work, a particular sample was successfully injected. PMID:23202036

Development for SSV on a parallel processing system (PARAGON)

NASA Astrophysics Data System (ADS)

Gothard, Benny M.; Allmen, Mark; Carroll, Michael J.; Rich, Dan

1995-12-01

A goal of the surrogate semi-autonomous vehicle (SSV) program is to have multiple vehicles navigate autonomously and cooperatively with other vehicles. This paper describes the process and tools used in porting UGV/SSV (unmanned ground vehicle) autonomous mobility and target recognition algorithms from a SISD (single instruction single data) processor architecture (i.e., a Sun SPARC workstation running C/UNIX) to a MIMD (multiple instruction multiple data) parallel processor architecture (i.e., PARAGON-a parallel set of i860 processors running C/UNIX). It discusses the gains in performance and the pitfalls of such a venture. It also examines the merits of this processor architecture (based on this conceptual prototyping effort) and programming paradigm to meet the final SSV demonstration requirements.

Environmental Control and Life Support System, Water Recovery System

NASA Technical Reports Server (NTRS)

2000-01-01

The Environmental Control and Life Support System (ECLSS) Group of the Flight Projects Directorate at the Marshall Space Flight Center (MSFC) is responsible for designing and building the life support systems that will provide the crew of the International Space Station (ISS) a comfortable environment in which to live and work. This is a close-up view of ECLSS Water Recovery System (WRS) racks. The MSFC's ECLSS Group overseas much of the development of the hardware that will allow a constant supply of clean water for four to six crewmembers aboard the ISS. The WRS provides clean water through the reclamation of wastewaters, including water obtained from the Space Shuttle's fuel cells, crewmember urine, used shower, handwash and oral hygiene water cabin humidity condensate, and Extravehicular Activity (EVA) wastes. The WRS is comprised of a Urine Processor Assembly (UPA), and a Water Processor Assembly (WPA). The UPA accepts and processes pretreated crewmember urine to allow it to be processed along with other wastewaters in the WPA, which removes free gas, organic, and nonorganic constituents before the water goes through a series of multifiltration beds for further purification. Product water quality is monitored primarily through conductivity measurements. Unacceptable water is sent back through the WPA for reprocessing. Clean water is sent to a storage tank. The water must meet stringent purity standards before consumption by the crew. The UPA provided by the MSFC and the WRA is provided by the prime contractor, Hamilton Sundstrand Space Systems, International (HSSSI) from Cornecticut.

Bench-Scale Monolith Autothermal Reformer Catalyst Screening Evaluations in a Micro-Reactor With Jet-A Fuel

NASA Technical Reports Server (NTRS)

Tomsik, Thomas M.; Yen, Judy C.H.; Budge, John R.

2006-01-01

Solid oxide fuel cell systems used in the aerospace or commercial aviation environment require a compact, light-weight and highly durable catalytic fuel processor. The fuel processing method considered here is an autothermal reforming (ATR) step. The ATR converts Jet-A fuel by a reaction with steam and air forming hydrogen (H2) and carbon monoxide (CO) to be used for production of electrical power in the fuel cell. This paper addresses the first phase of an experimental catalyst screening study, looking at the relative effectiveness of several monolith catalyst types when operating with untreated Jet-A fuel. Six monolith catalyst materials were selected for preliminary evaluation and experimental bench-scale screening in a small 0.05 kWe micro-reactor test apparatus. These tests were conducted to assess relative catalyst performance under atmospheric pressure ATR conditions and processing Jet-A fuel at a steam-to-carbon ratio of 3.5, a value higher than anticipated to be run in an optimized system. The average reformer efficiencies for the six catalysts tested ranged from 75 to 83 percent at a constant gas-hourly space velocity of 12,000 hr 1. The corresponding hydrocarbon conversion efficiency varied from 86 to 95 percent during experiments run at reaction temperatures between 750 to 830 C. Based on the results of the short-duration 100 hr tests reported herein, two of the highest performing catalysts were selected for further evaluation in a follow-on 1000 hr life durability study in Phase II.

Parallel optical information, concept, and response evolver: POINCARE

NASA Astrophysics Data System (ADS)

Caulfield, H. John; Caulfield, Kimberly

1991-08-01

It is now possible to build a nonlinear adaptive system which will incorporate many of the properties of the human mind, such as true originality in such skills as reasoning by analogy and reasoning by retrodiction, including literally unpredictable thoughts; and development of individual styles, personalities, expertise, etc. Like humans, these optical processors will have a rich `subconscious'' experience. Like humans, they will be clonable, but clones will develop differently as they experience the world differently, make different decisions, develop different habits, etc. In short, powerful optical processors with some of the properties normally associated with human intelligence can be made. This approach can result in a powerful optical processor with those properties. A demonstration chosen for simplicity of implementation is suggested. This could be the first computer of any type which uses quantum indeterminacy in an integral and important way.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Learn, Mark Walter

Sandia National Laboratories is currently developing new processing and data communication architectures for use in future satellite payloads. These architectures will leverage the flexibility and performance of state-of-the-art static-random-access-memory-based Field Programmable Gate Arrays (FPGAs). One such FPGA is the radiation-hardened version of the Virtex-5 being developed by Xilinx. However, not all features of this FPGA are being radiation-hardened by design and could still be susceptible to on-orbit upsets. One such feature is the embedded hard-core PPC440 processor. Since this processor is implemented in the FPGA as a hard-core, traditional mitigation approaches such as Triple Modular Redundancy (TMR) are not availablemore » to improve the processor's on-orbit reliability. The goal of this work is to investigate techniques that can help mitigate the embedded hard-core PPC440 processor within the Virtex-5 FPGA other than TMR. Implementing various mitigation schemes reliably within the PPC440 offers a powerful reconfigurable computing resource to these node-based processing architectures. This document summarizes the work done on the cache mitigation scheme for the embedded hard-core PPC440 processor within the Virtex-5 FPGAs, and describes in detail the design of the cache mitigation scheme and the testing conducted at the radiation effects facility on the Texas A&M campus.« less

Scheduling time-critical graphics on multiple processors

NASA Technical Reports Server (NTRS)

Meyer, Tom W.; Hughes, John F.

1995-01-01

This paper describes an algorithm for the scheduling of time-critical rendering and computation tasks on single- and multiple-processor architectures, with minimal pipelining. It was developed to manage scientific visualization scenes consisting of hundreds of objects, each of which can be computed and displayed at thousands of possible resolution levels. The algorithm generates the time-critical schedule using progressive-refinement techniques; it always returns a feasible schedule and, when allowed to run to completion, produces a near-optimal schedule which takes advantage of almost the entire multiple-processor system.

Formulation of consumables management models: Mission planning processor payload interface definition

NASA Technical Reports Server (NTRS)

Torian, J. G.

1977-01-01

Consumables models required for the mission planning and scheduling function are formulated. The relation of the models to prelaunch, onboard, ground support, and postmission functions for the space transportation systems is established. Analytical models consisting of an orbiter planning processor with consumables data base is developed. A method of recognizing potential constraint violations in both the planning and flight operations functions, and a flight data file storage/retrieval of information over an extended period which interfaces with a flight operations processor for monitoring of the actual flights is presented.

Conceptual design of an on-board optical processor with components

NASA Technical Reports Server (NTRS)

Walsh, J. R.; Shackelford, R. G.

1977-01-01

The specification of components for a spacecraft on-board optical processor was investigated. A space oriented application of optical data processing and the investigation of certain aspects of optical correlators were examined. The investigation confirmed that real-time optical processing has made significant advances over the past few years, but that there are still critical components which will require further development for use in an on-board optical processor. The devices evaluated were the coherent light valve, the readout optical modulator, the liquid crystal modulator, and the image forming light modulator.

Reduction of solar vector magnetograph data using a microMSP array processor

NASA Technical Reports Server (NTRS)

Kineke, Jack

1990-01-01

The processing of raw data obtained by the solar vector magnetograph at NASA-Marshall requires extensive arithmetic operations on large arrays of real numbers. The objectives of this summer faculty fellowship study are to: (1) learn the programming language of the MicroMSP Array Processor and adapt some existing data reduction routines to exploit its capabilities; and (2) identify other applications and/or existing programs which lend themselves to array processor utilization which can be developed by undergraduate student programmers under the provisions of project JOVE.

Image Matrix Processor for Volumetric Computations Final Report CRADA No. TSB-1148-95

DOE Office of Scientific and Technical Information (OSTI.GOV)

Roberson, G. Patrick; Browne, Jolyon

The development of an Image Matrix Processor (IMP) was proposed that would provide an economical means to perform rapid ray-tracing processes on volume "Giga Voxel" data sets. This was a multi-phased project. The objective of the first phase of the IMP project was to evaluate the practicality of implementing a workstation-based Image Matrix Processor for use in volumetric reconstruction and rendering using hardware simulation techniques. Additionally, ARACOR and LLNL worked together to identify and pursue further funding sources to complete a second phase of this project.

A Conformance Test Suite for Arden Syntax Compilers and Interpreters.

PubMed

Wolf, Klaus-Hendrik; Klimek, Mike

2016-01-01

The Arden Syntax for Medical Logic Modules is a standardized and well-established programming language to represent medical knowledge. To test the compliance level of existing compilers and interpreters no public test suite exists. This paper presents the research to transform the specification into a set of unit tests, represented in JUnit. It further reports on the utilization of the test suite testing four different Arden Syntax processors. The presented and compared results reveal the status conformance of the tested processors. How test driven development of Arden Syntax processors can help increasing the compliance with the standard is described with two examples. In the end some considerations how an open source test suite can improve the development and distribution of the Arden Syntax are presented.

Optoelectronic Technology Consortium: Precompetitive Consortium for Optoelectronic Interconnect Technology

DTIC Science & Technology

1992-09-01

demonstrating the producibility of optoelectronic components for high-density/high-data-rate processors and accelerating the insertion of this technology...technology development stage, OETC will advance the development of optical components, produce links for a multiboard processor testbed demonstration, and...components that are affordable, initially at <$100 per line, and reliable, with a li~e BER᝺-15 and MTTF >10 6 hours. Under the OETC program, Honeywell will

Implementation of a Configurable Fault Tolerant Processor (CFTP) Using Internal Triple Modular Redundancy (TMR)

DTIC Science & Technology

2005-12-01

Upsets in SRAM FPGAs,” Military and Aerospace Applications of Programmable Logic Devices, September 2002. 8. Wakerly , John F,. “Microcomputer...change. The goal of the Configurable Fault Tolerant Processor (CFTP) Project is to explore, develop and demonstrate the applicability of using off-the...develop and demonstrate the applicability of using commercial-of-the-shelf (COTS) Field Programmable Gate Arrays (FPGA) in the design of

A comparison of five methods for monitoring the precision of automated x-ray film processors.

PubMed

Nickoloff, E L; Leo, F; Reese, M

1978-11-01

Five different methods for preparing sensitometric strips used to monitor the precision of automated film processors are compared. A method for determining the sensitivity of each system to processor variations is presented; the observed statistical variability is multiplied by the system response to temperature or chemical changes. Pre-exposed sensitometric strips required the use of accurate densitometers and stringent control limits to be effective. X-ray exposed sensitometric strips demonstrated large variations in the x-ray output (2 omega approximately equal to 8.0%) over a period of one month. Some light sensitometers were capable of detecting +/- 1.0 degrees F (+/- 0.6 degrees C) variations in developer temperature in the processor and/or about 10.0 ml of chemical contamination in the processor. Nevertheless, even the light sensitometers were susceptible to problems, e.g. film emulsion selection, line voltage variations, and latent image fading. Advantages and disadvantages of the various sensitometric methods are discussed.

Emergency product generation for disaster management using RISAT and DMSAR quick look SAR processors

NASA Astrophysics Data System (ADS)

Desai, Nilesh; Sharma, Ritesh; Kumar, Saravana; Misra, Tapan; Gujraty, Virendra; Rana, SurinderSingh

2006-12-01

Since last few years, ISRO has embarked upon the development of two complex Synthetic Aperture Radar (SAR) missions, viz. Spaceborne Radar Imaging Satellite (RISAT) and Airborne SAR for Disaster Mangement (DMSAR), as a capacity building measure under country's Disaster Management Support (DMS) Program, for estimating the extent of damage over large areas (~75 Km) and also assess the effectiveness of the relief measures undertaken during natural disasters such as cyclones, epidemics, earthquakes, floods and landslides, forest fires, crop diseases etc. Synthetic Aperture Radar (SAR) has an unique role to play in mapping and monitoring of large areas affected by natural disasters especially floods, owing to its unique capability to see through clouds as well as all-weather imaging capability. The generation of SAR images with quick turn around time is very essential to meet the above DMS objectives. Thus the development of SAR Processors, for these two SAR systems poses considerable challenges and design efforts. Considering the growing user demand and inevitable necessity for a full-fledged high throughput processor, to process SAR data and generate image in real or near-real time, the design and development of a generic SAR Processor has been taken up and evolved, which will meet the SAR processing requirements for both Airborne and Spaceborne SAR systems. This hardware SAR processor is being built, to the extent possible, using only Commercial-Off-The-Shelf (COTS) DSP and other hardware plug-in modules on a Compact PCI (cPCI) platform. Thus, the major thrust has been on working out Multi-processor Digital Signal Processor (DSP) architecture and algorithm development and optimization rather than hardware design and fabrication. For DMSAR, this generic SAR Processor operates as a Quick Look SAR Processor (QLP) on-board the aircraft to produce real time full swath DMSAR images and as a ground based Near-Real Time high precision full swath Processor (NRTP). It will generate full-swath (6 to 75 Kms) DMSAR images in 1m / 3m / 5m / 10m / 30m resolution SAR operating modes. For RISAT mission, this generic Quick Look SAR Processor will be mainly used for browse product generation at NRSA-Shadnagar (SAN) ground receive station. RISAT QLP/NRTP is also proposed to provide an alternative emergency SAR product generation chain. For this, the S/C aux data appended in Onboard SAR Frame Format (x, y, z, x', y', z', roll, pitch, yaw) and predicted orbit from previous days Orbit Determination data will be used. The QLP / NRTP will produce ground range images in real / near real time. For emergency data product generation, additional Off-line tasks like geo-tagging, masking, QC etc needs to be performed on the processed image. The QLP / NRTP would generate geo-tagged images from the annotation data available from the SAR P/L data itself. Since the orbit & attitude information are taken as it is, the location accuracy will be poorer compared to the product generated using ADIF, where smoothened attitude and orbit are made available. Additional tasks like masking, output formatting and Quality checking of the data product will be carried out at Balanagar, NRSA after the image annotated data from QLP / NRTP is sent to Balanagar. The necessary interfaces to the QLP/NRTP for Emergency product generation are also being worked out. As is widely acknowledged, QLP/NRTP for RISAT and DMSAR is an ambitious effort and the technology of future. It is expected that by the middle of next decade, the next generation SAR missions worldwide will have onboard SAR Processors of varying capabilities and generate SAR Data products and Information products onboard instead of SAR raw data. Thus, it is also envisaged that these activities related to QLP/NRTP implementation for RISAT ground segment and DMSAR will be a significant step which will directly feed into the development of onboard real time processing systems for ISRO's future space borne SAR missions. This paper describes the design requirements, configuration details and salient features, apart from highlighting the utility of these Quick Look SAR processors for RISAT and DMSAR, for generation of emergency products for Disaster management.

Navy Budget: Potential Reductions for Research, Development, Test, and Evaluation

DTIC Science & Technology

1990-11-01

available for use in future Navy programs, including the MK-50 tor- pedo and Vertical Launch Antisubmarine Rocket. A total of $49.9 million of fiscal...346 Travel 03 07 + 04 Support 224 225 + 01 Total Requested $122.61 $122.61 -0- In addition, the Navy plans to acquire six Acoustic Video Processor...units at $2.4 million in fiscal year 1991. The Acoustic Video Processor pro- gram is experiencing development problems, and the full-scale develop- ment

Floating-Point Modules Targeted for Use with RC Compilation Tools

NASA Technical Reports Server (NTRS)

Sahin, Ibrahin; Gloster, Clay S.

2000-01-01

Reconfigurable Computing (RC) has emerged as a viable computing solution for computationally intensive applications. Several applications have been mapped to RC system and in most cases, they provided the smallest published execution time. Although RC systems offer significant performance advantages over general-purpose processors, they require more application development time than general-purpose processors. This increased development time of RC systems provides the motivation to develop an optimized module library with an assembly language instruction format interface for use with future RC system that will reduce development time significantly. In this paper, we present area/performance metrics for several different types of floating point (FP) modules that can be utilized to develop complex FP applications. These modules are highly pipelined and optimized for both speed and area. Using these modules, and example application, FP matrix multiplication, is also presented. Our results and experiences show, that with these modules, 8-10X speedup over general-purpose processors can be achieved.

Accuracy of the lattice-Boltzmann method using the Cell processor

NASA Astrophysics Data System (ADS)

Harvey, M. J.; de Fabritiis, G.; Giupponi, G.

2008-11-01

Accelerator processors like the new Cell processor are extending the traditional platforms for scientific computation, allowing orders of magnitude more floating-point operations per second (flops) compared to standard central processing units. However, they currently lack double-precision support and support for some IEEE 754 capabilities. In this work, we develop a lattice-Boltzmann (LB) code to run on the Cell processor and test the accuracy of this lattice method on this platform. We run tests for different flow topologies, boundary conditions, and Reynolds numbers in the range Re=6 350 . In one case, simulation results show a reduced mass and momentum conservation compared to an equivalent double-precision LB implementation. All other cases demonstrate the utility of the Cell processor for fluid dynamics simulations. Benchmarks on two Cell-based platforms are performed, the Sony Playstation3 and the QS20/QS21 IBM blade, obtaining a speed-up factor of 7 and 21, respectively, compared to the original PC version of the code, and a conservative sustained performance of 28 gigaflops per single Cell processor. Our results suggest that choice of IEEE 754 rounding mode is possibly as important as double-precision support for this specific scientific application.

Towards the formal specification of the requirements and design of a processor interface unit

NASA Technical Reports Server (NTRS)

Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

1993-01-01

Work to formally specify the requirements and design of a Processor Interface Unit (PIU), a single-chip subsystem providing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system, is described. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance free operation, or both. The approaches that were developed for modeling the PIU requirements and for composition of the PIU subcomponents at high levels of abstraction are described. These approaches were used to specify and verify a nontrivial subset of the PIU behavior. The PIU specification in Higher Order Logic (HOL) is documented in a companion NASA contractor report entitled 'Towards the Formal Specification of the Requirements and Design of a Processor Interfacs Unit - HOL Listings.' The subsequent verification approach and HOL listings are documented in NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit' and NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit - HOL Listings.'

Distributed processor allocation for launching applications in a massively connected processors complex

DOEpatents

Pedretti, Kevin

2008-11-18

A compute processor allocator architecture for allocating compute processors to run applications in a multiple processor computing apparatus is distributed among a subset of processors within the computing apparatus. Each processor of the subset includes a compute processor allocator. The compute processor allocators can share a common database of information pertinent to compute processor allocation. A communication path permits retrieval of information from the database independently of the compute processor allocators.

Microbiologic contamination during dental radiographic film processing.

PubMed

Stanczyk, D A; Paunovich, E D; Broome, J C; Fatone, M A

1993-07-01

This study investigated microbiologic contamination of an automatic dental radiograph processor and daylight loader during a week of simulated clinical use. Pure cultures of Candida albicans, Streptococcus pneumoniae, Staphylococcus aureus, or Klebsiella pneumoniae were used to contaminate 320 vinyl intraoral radiograph packets. Each end of the films was deliberately contaminated during opening. These films and 24 uncontaminated control films were processed. Daylight loader ports, inlet and outlet rollers, fixer and developer samples, and 12 processed films were cultured daily. To simulate a weekend, the processor sites were cultured during 72 hours of inactivity after the contaminated runs. The results showed that contamination of the processor and daylight loader occurred and remained even after 48 hours of inactivity. Films remained contaminated after processing. In addition, cross-contamination of films occurred in the processor.

Processing techniques for software based SAR processors

NASA Technical Reports Server (NTRS)

Leung, K.; Wu, C.

1983-01-01

Software SAR processing techniques defined to treat Shuttle Imaging Radar-B (SIR-B) data are reviewed. The algorithms are devised for the data processing procedure selection, SAR correlation function implementation, multiple array processors utilization, cornerturning, variable reference length azimuth processing, and range migration handling. The Interim Digital Processor (IDP) originally implemented for handling Seasat SAR data has been adapted for the SIR-B, and offers a resolution of 100 km using a processing procedure based on the Fast Fourier Transformation fast correlation approach. Peculiarities of the Seasat SAR data processing requirements are reviewed, along with modifications introduced for the SIR-B. An Advanced Digital SAR Processor (ADSP) is under development for use with the SIR-B in the 1986 time frame as an upgrade for the IDP, which will be in service in 1984-5.

Parallel processing approach to transform-based image coding

NASA Astrophysics Data System (ADS)

Normile, James O.; Wright, Dan; Chu, Ken; Yeh, Chia L.

1991-06-01

This paper describes a flexible parallel processing architecture designed for use in real time video processing. The system consists of floating point DSP processors connected to each other via fast serial links, each processor has access to a globally shared memory. A multiple bus architecture in combination with a dual ported memory allows communication with a host control processor. The system has been applied to prototyping of video compression and decompression algorithms. The decomposition of transform based algorithms for decompression into a form suitable for parallel processing is described. A technique for automatic load balancing among the processors is developed and discussed, results ar presented with image statistics and data rates. Finally techniques for accelerating the system throughput are analyzed and results from the application of one such modification described.

A message passing kernel for the hypercluster parallel processing test bed

NASA Technical Reports Server (NTRS)

Blech, Richard A.; Quealy, Angela; Cole, Gary L.

1989-01-01

A Message-Passing Kernel (MPK) for the Hypercluster parallel-processing test bed is described. The Hypercluster is being developed at the NASA Lewis Research Center to support investigations of parallel algorithms and architectures for computational fluid and structural mechanics applications. The Hypercluster resembles the hypercube architecture except that each node consists of multiple processors communicating through shared memory. The MPK efficiently routes information through the Hypercluster, using a message-passing protocol when necessary and faster shared-memory communication whenever possible. The MPK also interfaces all of the processors with the Hypercluster operating system (HYCLOPS), which runs on a Front-End Processor (FEP). This approach distributes many of the I/O tasks to the Hypercluster processors and eliminates the need for a separate I/O support program on the FEP.

MULTI-CORE AND OPTICAL PROCESSOR RELATED APPLICATIONS RESEARCH AT OAK RIDGE NATIONAL LABORATORY

DOE Office of Scientific and Technical Information (OSTI.GOV)

Barhen, Jacob; Kerekes, Ryan A; ST Charles, Jesse Lee

2008-01-01

High-speed parallelization of common tasks holds great promise as a low-risk approach to achieving the significant increases in signal processing and computational performance required for next generation innovations in reconfigurable radio systems. Researchers at the Oak Ridge National Laboratory have been working on exploiting the parallelization offered by this emerging technology and applying it to a variety of problems. This paper will highlight recent experience with four different parallel processors applied to signal processing tasks that are directly relevant to signal processing required for SDR/CR waveforms. The first is the EnLight Optical Core Processor applied to matched filter (MF) correlationmore » processing via fast Fourier transform (FFT) of broadband Dopplersensitive waveforms (DSW) using active sonar arrays for target tracking. The second is the IBM CELL Broadband Engine applied to 2-D discrete Fourier transform (DFT) kernel for image processing and frequency domain processing. And the third is the NVIDIA graphical processor applied to document feature clustering. EnLight Optical Core Processor. Optical processing is inherently capable of high-parallelism that can be translated to very high performance, low power dissipation computing. The EnLight 256 is a small form factor signal processing chip (5x5 cm2) with a digital optical core that is being developed by an Israeli startup company. As part of its evaluation of foreign technology, ORNL's Center for Engineering Science Advanced Research (CESAR) had access to a precursor EnLight 64 Alpha hardware for a preliminary assessment of capabilities in terms of large Fourier transforms for matched filter banks and on applications related to Doppler-sensitive waveforms. This processor is optimized for array operations, which it performs in fixed-point arithmetic at the rate of 16 TeraOPS at 8-bit precision. This is approximately 1000 times faster than the fastest DSP available today. The optical core performs the matrix-vector multiplications, where the nominal matrix size is 256x256. The system clock is 125MHz. At each clock cycle, 128K multiply-and-add operations per second (OPS) are carried out, which yields a peak performance of 16 TeraOPS. IBM Cell Broadband Engine. The Cell processor is the extraordinary resulting product of 5 years of sustained, intensive R&D collaboration (involving over $400M investment) between IBM, Sony, and Toshiba. Its architecture comprises one multithreaded 64-bit PowerPC processor element (PPE) with VMX capabilities and two levels of globally coherent cache, and 8 synergistic processor elements (SPEs). Each SPE consists of a processor (SPU) designed for streaming workloads, local memory, and a globally coherent direct memory access (DMA) engine. Computations are performed in 128-bit wide single instruction multiple data streams (SIMD). An integrated high-bandwidth element interconnect bus (EIB) connects the nine processors and their ports to external memory and to system I/O. The Applied Software Engineering Research (ASER) Group at the ORNL is applying the Cell to a variety of text and image analysis applications. Research on Cell-equipped PlayStation3 (PS3) consoles has led to the development of a correlation-based image recognition engine that enables a single PS3 to process images at more than 10X the speed of state-of-the-art single-core processors. NVIDIA Graphics Processing Units. The ASER group is also employing the latest NVIDIA graphical processing units (GPUs) to accelerate clustering of thousands of text documents using recently developed clustering algorithms such as document flocking and affinity propagation.« less

Air-Lubricated Thermal Processor For Dry Silver Film

NASA Astrophysics Data System (ADS)

Siryj, B. W.

1980-09-01

Since dry silver film is processed by heat, it may be viewed on a light table only seconds after exposure. On the other hand, wet films require both bulky chemicals and substantial time before an image can be analyzed. Processing of dry silver film, although simple in concept, is not so simple when reduced to practice. The main concern is the effect of film temperature gradients on uniformity of optical film density. RCA has developed two thermal processors, different in implementation but based on the same philosophy. Pressurized air is directed to both sides of the film to support the film and to conduct the heat to the film. Porous graphite is used as the medium through which heat and air are introduced. The initial thermal processor was designed to process 9.5-inch-wide film moving at speeds ranging from 0.0034 to 0.008 inch per second. The processor configuration was curved to match the plane generated by the laser recording beam. The second thermal processor was configured to process 5-inch-wide film moving at a continuously variable rate ranging from 0.15 to 3.5 inches per second. Due to field flattening optics used in this laser recorder, the required film processing area was plane. In addition, this processor was sectioned in the direction of film motion, giving the processor the capability of varying both temperature and effective processing area.

Ion Thruster Development at NASA Lewis Research Center

NASA Technical Reports Server (NTRS)

Sovey, James S.; Hamley, John A.; Patterson, Michael J.; Rawlin, Vincent K.; Sarver-Verhey, Timothy R.

1992-01-01

Recent ion propulsion technology efforts at NASA's Lewis Research Center including development of kW-class xenon ion thrusters, high power xenon and krypton ion thrusters, and power processors are reviewed. Thruster physical characteristics, performance data, life projections, and power processor component technology are summarized. The ion propulsion technology program is structured to address a broad set of mission applications from satellite stationkeeping and repositioning to primary propulsion using solar or nuclear power systems.

Integration, Development and Performance of the 500 TFLOPS Heterogeneous Cluster (Condor)

DTIC Science & Technology

2012-08-01

PlayStation 3 for High Performance Cluster Computing” LAPACK Working Note 185, 2007. [ 4 ] Feng, W., X. Feng, and R. Ge, “Green Supercomputing Comes of...CONFERENCE PAPER (Post Print) 3. DATES COVERED (From - To) JUN 2010 – MAY 2013 4 . TITLE AND SUBTITLE INTEGRATION, DEVELOPMENT AND PERFORMANCE OF...and streaming processing; the PlayStation 3 uses the IBM Cell BE processor, which adopts the multi-processor, single-instruction-multiple- data (SIMD

Multisensor data fusion for integrated maritime surveillance

NASA Astrophysics Data System (ADS)

Premji, A.; Ponsford, A. M.

1995-01-01

A prototype Integrated Coastal Surveillance system has been developed on Canada's East Coast to provide effective surveillance out to and beyond the 200 nautical mile Exclusive Economic Zone. The system has been designed to protect Canada's natural resources, and to monitor and control the coastline for smuggling, drug trafficking, and similar illegal activity. This paper describes the Multiple Sensor - Multiple Target data fusion system that has been developed. The fusion processor has been developed around the celebrated Multiple Hypothesis Tracking algorithm which accommodates multiple targets, new targets, false alarms, and missed detections. This processor performs four major functions: plot-to-track association to form individual radar tracks; fusion of radar tracks with secondary sensor reports; track identification and tagging using secondary reports; and track level fusion to form common tracks. Radar data from coherent and non-coherent radars has been used to evaluate the performance of the processor. This paper presents preliminary results.

QERx- A Faster than Real-Time Emulator for Space Processors

NASA Astrophysics Data System (ADS)

Carvalho, B.; Pidgeon, A.; Robinson, P.

2012-08-01

Developing software for space systems is challenging. Especially because, in order to be sure it can cope with the harshness of the environment and the imperative requirements and constrains imposed by the platform were it will run, it needs to be tested exhaustively. Software Validation Facilities (SVF) are known to the industry and developers, and provide the means to run the On-Board Software (OBSW) in a realistic environment, allowing the development team to debug and test the software.But the challenge is to be able to keep up with the performance of the new processors (LEON2 and LEON3), which need to be emulated within the SVF. Such processor emulators are also used in Operational Simulators, used to support mission preparation and train mission operators. These simulators mimic the satellite and its behaviour, as realistically as possible. For test/operational efficiency reasons and because they will need to interact with external systems, both these uses cases require the processor emulators to provide real-time, or faster, performance.It is known to the industry that the performance of previously available emulators is not enough to cope with the performance of the new processors available in the market. SciSys approached this problem with dynamic translation technology trying to keep costs down by avoiding a hardware solution and keeping the integration flexibility of full software emulation.SciSys presented “QERx: A High Performance Emulator for Software Validation and Simulations” [1], in a previous DASIA event. Since then that idea has evolved and QERx has been successfully validated. SciSys is now presenting QERx as a product that can be tailored to fit different emulation needs. This paper will present QERx latest developments and current status.

Pressurized diesel fuel processing using hydrogen peroxide for the fuel cell power unit in low-oxygen environments

NASA Astrophysics Data System (ADS)

Lee, Kwangho; Han, Gwangwoo; Cho, Sungbaek; Bae, Joongmyeon

2018-03-01

A novel concept for diesel fuel processing utilizing H2O2 is suggested to obtain the high-purity H2 required for air-independent propulsion using polymer electrolyte membrane fuel cells for use in submarines and unmanned underwater vehicles. The core components include 1) a diesel-H2O2 autothermal reforming (ATR) reactor to produce H2-rich gas, 2) a water-gas shift (WGS) reactor to convert CO to H2, and 3) a H2 separation membrane to separate only high-purity H2. Diesel and H2O2 can easily be pressurized as they are liquids. The application of the H2 separation membrane without a compressor in the middle of the process is thus advantageous. In this paper, the characteristics of pressurized ATR and WGS reactions are investigated according to the operating conditions. In both reactors, the methanation reaction is enhanced as the pressure increases. Then, permeation experiments with a H2 separation membrane are performed while varying the temperature, pressure difference, and inlet gas composition. In particular, approximately 90% of the H2 is recovered when the steam-separated rear gas of the WGS reactor is used in the H2 separation membrane. Finally, based on the experimental results, design points are suggested for maximizing the efficiency of the diesel-H2O2 fuel processor.

High pressure autothermal reforming in low oxygen environments

NASA Astrophysics Data System (ADS)

Reese, Mark A.; Turn, Scott Q.; Cui, Hong

Recent interest in fuel cells has led to the conceptual design of an ocean floor, fuel cell-based, power generating station fueled by methane from natural gas seeps or from the controlled decomposition of methane hydrates. Because the dissolved oxygen concentration in deep ocean water is too low to provide adequate supplies to a fuel processor and fuel cell, oxygen must be stored onboard the generating station. A lab scale catalytic autothermal reformer capable of operating at pressures of 6-50 bar was constructed and tested. The objective of the experimental program was to maximize H 2 production per mole of O 2 supplied (H 2(out)/O 2(in)). Optimization, using oxygen-to-carbon (O 2/C) and water-to-carbon (S/C) ratios as independent variables, was conducted at three pressures using bottled O 2. Surface response methodology was employed using a 2 2 factorial design. Optimal points were validated using H 2O 2 as both a stored oxidizer and steam source. The optimal experimental conditions for maximizing the moles of H 2(out)/O 2(in) occurred at a S/C ratio of 3.00-3.35 and an O 2/C ratio of 0.44-0.48. When using H 2O 2 as the oxidizer, the moles of H 2(out)/O 2(in) increased ≤14%. An equilibrium model was also used to compare experimental and theoretical results.

Processor Emulator with Benchmark Applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lloyd, G. Scott; Pearce, Roger; Gokhale, Maya

2015-11-13

A processor emulator and a suite of benchmark applications have been developed to assist in characterizing the performance of data-centric workloads on current and future computer architectures. Some of the applications have been collected from other open source projects. For more details on the emulator and an example of its usage, see reference [1].

Space Station Water Processor Mostly Liquid Separator (MLS)

NASA Technical Reports Server (NTRS)

Lanzarone, Anthony

1995-01-01

This report presents the results of the development testing conducted under this contract to the Space Station Water Processor (WP) Mostly Liquid Separator (MLS). The MLS units built and modified during this testing demonstrated acceptable air/water separation results in a variety of water conditions with inlet flow rates ranging from 60 - 960 LB/hr.

The scaling issue: scientific opportunities

NASA Astrophysics Data System (ADS)

Orbach, Raymond L.

2009-07-01

A brief history of the Leadership Computing Facility (LCF) initiative is presented, along with the importance of SciDAC to the initiative. The initiative led to the initiation of the Innovative and Novel Computational Impact on Theory and Experiment program (INCITE), open to all researchers in the US and abroad, and based solely on scientific merit through peer review, awarding sizeable allocations (typically millions of processor-hours per project). The development of the nation's LCFs has enabled available INCITE processor-hours to double roughly every eight months since its inception in 2004. The 'top ten' LCF accomplishments in 2009 illustrate the breadth of the scientific program, while the 75 million processor hours allocated to American business since 2006 highlight INCITE contributions to US competitiveness. The extrapolation of INCITE processor hours into the future brings new possibilities for many 'classic' scaling problems. Complex systems and atomic displacements to cracks are but two examples. However, even with increasing computational speeds, the development of theory, numerical representations, algorithms, and efficient implementation are required for substantial success, exhibiting the crucial role that SciDAC will play.

A measurement-based study of concurrency in a multiprocessor

NASA Technical Reports Server (NTRS)

Mcguire, Patrick John

1987-01-01

A systematic measurement-based methodology for characterizing the amount of concurrency present in a workload, and the effect of concurrency on system performance indices such as cache miss rate and bus activity are developed. Hardware and software instrumentation of an Alliant FX/8 was used to obtain data from a real workload environment. Results show that 35% of the workload is concurrent, with the concurrent periods typically using all available processors. Measurements of periods of change in concurrency show uneven usage of processors during these times. Other system measures, including cache miss rate and processor bus activity, are analyzed with respect to the concurrency measures. Probability of a cache miss is seen to increase with concurrency. The change in cache miss rate is much more sensitive to the fraction of concurrent code in the worklaod than the number of processors active during concurrency. Regression models are developed to quantify the relationships between cache miss rate, bus activity, and the concurrency measures. The model for cache miss rate predicts an increase in the median miss rate value as much as 300% for a 100% increase in concurrency in the workload.

New Developments in the SCIAMACHY L2 Ground Processor

NASA Astrophysics Data System (ADS)

Gretschany, S.; Lichtenberg, G.; Meringer, M.; Theys, N.; Lerot, C.; Eichmann, K.-U.; Liebing, P.; Noel, S.; Dehn, A.; Fehr, T.

2016-08-01

SCIAMACHY (SCanning Imaging Absorption spectroMeter for Atmospheric ChartographY) aboard ESA's environmental satellite ENVISAT observed the Earth's atmosphere in limb, nadir, and solar/lunar occultation geometries covering the UV-Visible to NIR spectral range. It is a joint project of Germany, the Netherlands and Belgium and was launched in February 2002. SCIAMACHY doubled its originally planned in-orbit lifetime of five years before the communication to ENVISAT was severed in April 2012, and the mission entered its post- operational phase F.The SCIAMACHY Quality Working Group (SQWG) was established in 2007. The group coordinates evolution of algorithms and processors, aiming at improving the quality of the operational data products. University of Bremen (IUP), BIRA, DLR-IMF, SRON (Netherlands Institute for Space Research) and KNMI (The Royal Netherlands Meteorological Institute) are the members providing expertise in this group.In order to preserve the best quality of the outstanding data obtained by SCIAMACHY, data processors are still being updated. This presentation will highlight new developments that are currently being incorporated into the forthcoming Version 7 of ESA's operational Level 2 processor.

Multibus-based parallel processor for simulation

NASA Technical Reports Server (NTRS)

Ogrady, E. P.; Wang, C.-H.

1983-01-01

A Multibus-based parallel processor simulation system is described. The system is intended to serve as a vehicle for gaining hands-on experience, testing system and application software, and evaluating parallel processor performance during development of a larger system based on the horizontal/vertical-bus interprocessor communication mechanism. The prototype system consists of up to seven Intel iSBC 86/12A single-board computers which serve as processing elements, a multiple transmission controller (MTC) designed to support system operation, and an Intel Model 225 Microcomputer Development System which serves as the user interface and input/output processor. All components are interconnected by a Multibus/IEEE 796 bus. An important characteristic of the system is that it provides a mechanism for a processing element to broadcast data to other selected processing elements. This parallel transfer capability is provided through the design of the MTC and a minor modification to the iSBC 86/12A board. The operation of the MTC, the basic hardware-level operation of the system, and pertinent details about the iSBC 86/12A and the Multibus are described.

Assessing the Progress of Trapped-Ion Processors Towards Fault-Tolerant Quantum Computation

NASA Astrophysics Data System (ADS)

Bermudez, A.; Xu, X.; Nigmatullin, R.; O'Gorman, J.; Negnevitsky, V.; Schindler, P.; Monz, T.; Poschinger, U. G.; Hempel, C.; Home, J.; Schmidt-Kaler, F.; Biercuk, M.; Blatt, R.; Benjamin, S.; Müller, M.

2017-10-01

A quantitative assessment of the progress of small prototype quantum processors towards fault-tolerant quantum computation is a problem of current interest in experimental and theoretical quantum information science. We introduce a necessary and fair criterion for quantum error correction (QEC), which must be achieved in the development of these quantum processors before their sizes are sufficiently big to consider the well-known QEC threshold. We apply this criterion to benchmark the ongoing effort in implementing QEC with topological color codes using trapped-ion quantum processors and, more importantly, to guide the future hardware developments that will be required in order to demonstrate beneficial QEC with small topological quantum codes. In doing so, we present a thorough description of a realistic trapped-ion toolbox for QEC and a physically motivated error model that goes beyond standard simplifications in the QEC literature. We focus on laser-based quantum gates realized in two-species trapped-ion crystals in high-optical aperture segmented traps. Our large-scale numerical analysis shows that, with the foreseen technological improvements described here, this platform is a very promising candidate for fault-tolerant quantum computation.

Multi-level Hierarchical Poly Tree computer architectures

NASA Technical Reports Server (NTRS)

Padovan, Joe; Gute, Doug

1990-01-01

Based on the concept of hierarchical substructuring, this paper develops an optimal multi-level Hierarchical Poly Tree (HPT) parallel computer architecture scheme which is applicable to the solution of finite element and difference simulations. Emphasis is given to minimizing computational effort, in-core/out-of-core memory requirements, and the data transfer between processors. In addition, a simplified communications network that reduces the number of I/O channels between processors is presented. HPT configurations that yield optimal superlinearities are also demonstrated. Moreover, to generalize the scope of applicability, special attention is given to developing: (1) multi-level reduction trees which provide an orderly/optimal procedure by which model densification/simplification can be achieved, as well as (2) methodologies enabling processor grading that yields architectures with varying types of multi-level granularity.

The automatic control system and stand-by facilities of the TDMA-40 equipment

NASA Astrophysics Data System (ADS)

Gudenko, D. V.; Pankov, G. Kh.; Pauk, A. G.; Tsirlin, V. M.

1980-10-01

When a controlling station in a satellite communications system is out of order, a complex algorithm must be carried out for automatic operation of the stand-by equipment. A processor has been developed to perform this algorithm, as well as operations involving the stand-by facilities of the receiving-transmitting equipment of the station. The design principles and solutions to problems in developing the equipment for the monitoring and controlling systems are described. These systems are based on multistation access using time division multiplexing. Algorithms are presented for the operation of the synchronizing processor and the control processor of the equipment. The automatic control system and stand-by facilities make it possible to reduce the service personnel and to design an unattended station.

The development of a power spectral density processor for C and L band airborne radar scatterometer sensor systems

NASA Technical Reports Server (NTRS)

Harrison, D. A., III; Chladek, J. T.

1983-01-01

A real-time signal processor was developed for the NASA/JSC L-and C-band airborne radar scatterometer sensor systems. The purpose of the effort was to reduce ground data processing costs. Conversion of two quadrature channels of data (like and cross polarized) was made to obtain Power Spectral Density (PSD) values. A chirp-z transform (CZT) approach was used to filter the Doppler return signal and improved high frequency and angular resolution was realized. The processors have been tested with record signals and excellent results were obtained. CZT filtering can be readily applied to scatterometers operating at other wavelengths by altering the sample frequency. The design of the hardware and software and the results of the performance tests are described in detail.

Embedded Data Processor and Portable Computer Technology testbeds

NASA Technical Reports Server (NTRS)

Alena, Richard; Liu, Yuan-Kwei; Goforth, Andre; Fernquist, Alan R.

1993-01-01

Attention is given to current activities in the Embedded Data Processor and Portable Computer Technology testbed configurations that are part of the Advanced Data Systems Architectures Testbed at the Information Sciences Division at NASA Ames Research Center. The Embedded Data Processor Testbed evaluates advanced microprocessors for potential use in mission and payload applications within the Space Station Freedom Program. The Portable Computer Technology (PCT) Testbed integrates and demonstrates advanced portable computing devices and data system architectures. The PCT Testbed uses both commercial and custom-developed devices to demonstrate the feasibility of functional expansion and networking for portable computers in flight missions.

Software design and documentation language, revision 1

NASA Technical Reports Server (NTRS)

Kleine, H.

1979-01-01

The Software Design and Documentation Language (SDDL) developed to provide an effective communications medium to support the design and documentation of complex software applications is described. Features of the system include: (1) a processor which can convert design specifications into an intelligible, informative machine-reproducible document; (2) a design and documentation language with forms and syntax that are simple, unrestrictive, and communicative; and (3) methodology for effective use of the language and processor. The SDDL processor is written in the SIMSCRIPT II programming language and is implemented on the UNIVAC 1108, the IBM 360/370, and Control Data machines.

SPAR improved structural-fluid dynamic analysis capability

NASA Technical Reports Server (NTRS)

Pearson, M. L.

1985-01-01

The results of a study whose objective was to improve the operation of the SPAR computer code by improving efficiency, user features, and documentation is presented. Additional capability was added to the SPAR arithmetic utility system, including trigonometric functions, numerical integration, interpolation, and matrix combinations. Improvements were made in the EIG processor. A processor was created to compute and store principal stresses in table-format data sets. An additional capability was developed and incorporated into the plot processor which permits plotting directly from table-format data sets. Documentation of all these features is provided in the form of updates to the SPAR users manual.

Radiation Hardened Electronics for Extreme Environments

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Watson, Michael D.

2007-01-01

The Radiation Hardened Electronics for Space Environments (RHESE) project consists of a series of tasks designed to develop and mature a broad spectrum of radiation hardened and low temperature electronics technologies. Three approaches are being taken to address radiation hardening: improved material hardness, design techniques to improve radiation tolerance, and software methods to improve radiation tolerance. Within these approaches various technology products are being addressed including Field Programmable Gate Arrays (FPGA), Field Programmable Analog Arrays (FPAA), MEMS Serial Processors, Reconfigurable Processors, and Parallel Processors. In addition to radiation hardening, low temperature extremes are addressed with a focus on material and design approaches.

Network Coding on Heterogeneous Multi-Core Processors for Wireless Sensor Networks

PubMed Central

Kim, Deokho; Park, Karam; Ro, Won W.

2011-01-01

While network coding is well known for its efficiency and usefulness in wireless sensor networks, the excessive costs associated with decoding computation and complexity still hinder its adoption into practical use. On the other hand, high-performance microprocessors with heterogeneous multi-cores would be used as processing nodes of the wireless sensor networks in the near future. To this end, this paper introduces an efficient network coding algorithm developed for the heterogenous multi-core processors. The proposed idea is fully tested on one of the currently available heterogeneous multi-core processors referred to as the Cell Broadband Engine. PMID:22164053

Status of a Power Processor for the Prometheus-1 Electric Propulsion System

NASA Technical Reports Server (NTRS)

Pinero, Luis R.; Hill, Gerald M.; Aulisio, Michael; Gerber, Scott; Griebeler, Elmer; Hewitt, Frank; Scina, Joseph

2006-01-01

NASA is developing technologies for nuclear electric propulsion for proposed deep space missions in support of the Exploration initiative under Project Prometheus. Electrical power produced by the combination of a fission-based power source and a Brayton power conversion and distribution system is used by a high specific impulse ion propulsion system to propel the spaceship. The ion propulsion system include the thruster, power processor and propellant feed system. A power processor technology development effort was initiated under Project Prometheus to develop high performance and lightweight power-processing technologies suitable for the application. This effort faces multiple challenges including developing radiation hardened power modules and converters with very high power capability and efficiency to minimize the impact on the power conversion and distribution system as well as the heat rejection system. This paper documents the design and test results of the first version of the beam supply, the design of a second version of the beam supply and the design and test results of the ancillary supplies.

Reconfigurable Very Long Instruction Word (VLIW) Processor

NASA Technical Reports Server (NTRS)

Velev, Miroslav N.

2015-01-01

Future NASA missions will depend on radiation-hardened, power-efficient processing systems-on-a-chip (SOCs) that consist of a range of processor cores custom tailored for space applications. Aries Design Automation, LLC, has developed a processing SOC that is optimized for software-defined radio (SDR) uses. The innovation implements the Institute of Electrical and Electronics Engineers (IEEE) RazorII voltage management technique, a microarchitectural mechanism that allows processor cores to self-monitor, self-analyze, and selfheal after timing errors, regardless of their cause (e.g., radiation; chip aging; variations in the voltage, frequency, temperature, or manufacturing process). This highly automated SOC can also execute legacy PowerPC 750 binary code instruction set architecture (ISA), which is used in the flight-control computers of many previous NASA space missions. In developing this innovation, Aries Design Automation has made significant contributions to the fields of formal verification of complex pipelined microprocessors and Boolean satisfiability (SAT) and has developed highly efficient electronic design automation tools that hold promise for future developments.

Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures

PubMed Central

Manolakos, Elias S.

2015-01-01

Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub. PMID:26605332

Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures.

PubMed

Sharma, Anuj; Manolakos, Elias S

2015-01-01

Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub.

An architecture for real-time vision processing

NASA Technical Reports Server (NTRS)

Chien, Chiun-Hong

1994-01-01

To study the feasibility of developing an architecture for real time vision processing, a task queue server and parallel algorithms for two vision operations were designed and implemented on an i860-based Mercury Computing System 860VS array processor. The proposed architecture treats each vision function as a task or set of tasks which may be recursively divided into subtasks and processed by multiple processors coordinated by a task queue server accessible by all processors. Each idle processor subsequently fetches a task and associated data from the task queue server for processing and posts the result to shared memory for later use. Load balancing can be carried out within the processing system without the requirement for a centralized controller. The author concludes that real time vision processing cannot be achieved without both sequential and parallel vision algorithms and a good parallel vision architecture.

Multiprocessing on supercomputers for computational aerodynamics

NASA Technical Reports Server (NTRS)

Yarrow, Maurice; Mehta, Unmeel B.

1991-01-01

Little use is made of multiple processors available on current supercomputers (computers with a theoretical peak performance capability equal to 100 MFLOPS or more) to improve turnaround time in computational aerodynamics. The productivity of a computer user is directly related to this turnaround time. In a time-sharing environment, such improvement in this speed is achieved when multiple processors are used efficiently to execute an algorithm. The concept of multiple instructions and multiple data (MIMD) is applied through multitasking via a strategy that requires relatively minor modifications to an existing code for a single processor. This approach maps the available memory to multiple processors, exploiting the C-Fortran-Unix interface. The existing code is mapped without the need for developing a new algorithm. The procedure for building a code utilizing this approach is automated with the Unix stream editor.

SATNET Development and Operation. Pluribus Satellite IMP Development, Remote Site Maintenance. Internet Development. Mobile Access Terminal Network, TCP for the HP3000, TCP-TAC.

DTIC Science & Technology

1980-08-01

reduce I/O latency. Periodically, the polling processor would hand off the polling task to a different processor which would then become the active...DMA (2 X 1.5 microsecond/word) since both halves of the SKI carry on simultaneous DMA transfers in a looped configuration. The difference between 3.0...intelligent DMA. The only difference between this approach and the intelligent DNA is that the true intelligent DNA (approach (1)) would not use up I

CH4 IPDA Lidar mission data simulator and processor for MERLIN: prototype development at LMD/CNRS/Ecole Polytechnique

NASA Astrophysics Data System (ADS)

Olivier, Chomette; Armante, Raymond; Crevoisier, Cyril; Delahaye, Thibault; Edouart, Dimitri; Gibert, Fabien; Nahan, Frédéric; Tellier, Yoann

2018-04-01

The MEthane Remote sensing Lidar missioN (MERLIN), currently in phase C, is a joint cooperation between France and Germany on the development of a spatial Integrated Path Differential Absorption (IPDA) LIDAR (LIght Detecting And Ranging) to conduct global observations of atmospheric methane. This presentation will focus on the status of a LIDAR mission data simulator and processor developed at LMD (Laboratoire de Météorologie Dynamique), Ecole Polytechnique, France, for MERLIN to assess the performances in realistic observational situations.

Low latency messages on distributed memory multiprocessors

NASA Technical Reports Server (NTRS)

Rosing, Matthew; Saltz, Joel

1993-01-01

Many of the issues in developing an efficient interface for communication on distributed memory machines are described and a portable interface is proposed. Although the hardware component of message latency is less than one microsecond on many distributed memory machines, the software latency associated with sending and receiving typed messages is on the order of 50 microseconds. The reason for this imbalance is that the software interface does not match the hardware. By changing the interface to match the hardware more closely, applications with fine grained communication can be put on these machines. Based on several tests that were run on the iPSC/860, an interface that will better match current distributed memory machines is proposed. The model used in the proposed interface consists of a computation processor and a communication processor on each node. Communication between these processors and other nodes in the system is done through a buffered network. Information that is transmitted is either data or procedures to be executed on the remote processor. The dual processor system is better suited for efficiently handling asynchronous communications compared to a single processor system. The ability to send data or procedure is very flexible for minimizing message latency, based on the type of communication being performed. The test performed and the proposed interface are described.

A general natural-language text processor for clinical radiology.

PubMed Central

Friedman, C; Alderson, P O; Austin, J H; Cimino, J J; Johnson, S B

1994-01-01

OBJECTIVE: Development of a general natural-language processor that identifies clinical information in narrative reports and maps that information into a structured representation containing clinical terms. DESIGN: The natural-language processor provides three phases of processing, all of which are driven by different knowledge sources. The first phase performs the parsing. It identifies the structure of the text through use of a grammar that defines semantic patterns and a target form. The second phase, regularization, standardizes the terms in the initial target structure via a compositional mapping of multi-word phrases. The third phase, encoding, maps the terms to a controlled vocabulary. Radiology is the test domain for the processor and the target structure is a formal model for representing clinical information in that domain. MEASUREMENTS: The impression sections of 230 radiology reports were encoded by the processor. Results of an automated query of the resultant database for the occurrences of four diseases were compared with the analysis of a panel of three physicians to determine recall and precision. RESULTS: Without training specific to the four diseases, recall and precision of the system (combined effect of the processor and query generator) were 70% and 87%. Training of the query component increased recall to 85% without changing precision. PMID:7719797

Right-Brain/Left-Brain Integrated Associative Processor Employing Convertible Multiple-Instruction-Stream Multiple-Data-Stream Elements

NASA Astrophysics Data System (ADS)

Hayakawa, Hitoshi; Ogawa, Makoto; Shibata, Tadashi

2005-04-01

A very large scale integrated circuit (VLSI) architecture for a multiple-instruction-stream multiple-data-stream (MIMD) associative processor has been proposed. The processor employs an architecture that enables seamless switching from associative operations to arithmetic operations. The MIMD element is convertible to a regular central processing unit (CPU) while maintaining its high performance as an associative processor. Therefore, the MIMD associative processor can perform not only on-chip perception, i.e., searching for the vector most similar to an input vector throughout the on-chip cache memory, but also arithmetic and logic operations similar to those in ordinary CPUs, both simultaneously in parallel processing. Three key technologies have been developed to generate the MIMD element: associative-operation-and-arithmetic-operation switchable calculation units, a versatile register control scheme within the MIMD element for flexible operations, and a short instruction set for minimizing the memory size for program storage. Key circuit blocks were designed and fabricated using 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology. As a result, the full-featured MIMD element is estimated to be 3 mm2, showing the feasibility of an 8-parallel-MIMD-element associative processor in a single chip of 5 mm× 5 mm.

Feasibility study of microprocessor systems suitable for use in developing a real-time for the 4.75 GHz scatterometer

NASA Technical Reports Server (NTRS)

1977-01-01

A class of signal processors suitable for the reduction of radar scatterometer data in real time was developed. The systems were applied to the reduction of single polarized 13.3 GHz scatterometer data and provided a real time output of radar scattering coefficient as a function of incident angle. It was proposed that a system for processing of C band radar data be constructed to support scatterometer system currently under development. The establishment of a feasible design approach to the development of this processor system utilizing microprocessor technology was emphasized.

Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores

NASA Astrophysics Data System (ADS)

Hayashi, Akihiro; Wada, Yasutaka; Watanabe, Takeshi; Sekiguchi, Takeshi; Mase, Masayoshi; Shirako, Jun; Kimura, Keiji; Kasahara, Hironori

Heterogeneous multicores have been attracting much attention to attain high performance keeping power consumption low in wide spread of areas. However, heterogeneous multicores force programmers very difficult programming. The long application program development period lowers product competitiveness. In order to overcome such a situation, this paper proposes a compilation framework which bridges a gap between programmers and heterogeneous multicores. In particular, this paper describes the compilation framework based on OSCAR compiler. It realizes coarse grain task parallel processing, data transfer using a DMA controller, power reduction control from user programs with DVFS and clock gating on various heterogeneous multicores from different vendors. This paper also evaluates processing performance and the power reduction by the proposed framework on a newly developed 15 core heterogeneous multicore chip named RP-X integrating 8 general purpose processor cores and 3 types of accelerator cores which was developed by Renesas Electronics, Hitachi, Tokyo Institute of Technology and Waseda University. The framework attains speedups up to 32x for an optical flow program with eight general purpose processor cores and four DRP(Dynamically Reconfigurable Processor) accelerator cores against sequential execution by a single processor core and 80% of power reduction for the real-time AAC encoding.

Onboard Interferometric SAR Processor for the Ka-Band Radar Interferometer (KaRIn)

NASA Technical Reports Server (NTRS)

Esteban-Fernandez, Daniel; Rodriquez, Ernesto; Peral, Eva; Clark, Duane I.; Wu, Xiaoqing

2011-01-01

An interferometric synthetic aperture radar (SAR) onboard processor concept and algorithm has been developed for the Ka-band radar interferometer (KaRIn) instrument on the Surface and Ocean Topography (SWOT) mission. This is a mission- critical subsystem that will perform interferometric SAR processing and multi-look averaging over the oceans to decrease the data rate by three orders of magnitude, and therefore enable the downlink of the radar data to the ground. The onboard processor performs demodulation, range compression, coregistration, and re-sampling, and forms nine azimuth squinted beams. For each of them, an interferogram is generated, including common-band spectral filtering to improve correlation, followed by averaging to the final 1 1-km ground resolution pixel. The onboard processor has been prototyped on a custom FPGA-based cPCI board, which will be part of the radar s digital subsystem. The level of complexity of this technology, dictated by the implementation of interferometric SAR processing at high resolution, the extremely tight level of accuracy required, and its implementation on FPGAs are unprecedented at the time of this reporting for an onboard processor for flight applications.

Test Platform for Advanced Digital Control of Brushless DC Motors (MSFC Center Director's Discretionary Fund)

NASA Technical Reports Server (NTRS)

Gwaltney, D. A.

2002-01-01

A FY 2001 Center Director's Discretionary Fund task to develop a test platform for the development, implementation. and evaluation of adaptive and other advanced control techniques for brushless DC (BLDC) motor-driven mechanisms is described. Important applications for BLDC motor-driven mechanisms are the translation of specimens in microgravity experiments and electromechanical actuation of nozzle and fuel valves in propulsion systems. Motor-driven aerocontrol surfaces are also being utilized in developmental X vehicles. The experimental test platform employs a linear translation stage that is mounted vertically and driven by a BLDC motor. Control approaches are implemented on a digital signal processor-based controller for real-time, closed-loop control of the stage carriage position. The goal of the effort is to explore the application of advanced control approaches that can enhance the performance of a motor-driven actuator over the performance obtained using linear control approaches with fixed gains. Adaptive controllers utilizing an exact model knowledge controller and a self-tuning controller are implemented and the control system performance is illustrated through the presentation of experimental results.

Conjugate-Gradient Algorithms For Dynamics Of Manipulators

NASA Technical Reports Server (NTRS)

Fijany, Amir; Scheid, Robert E.

1993-01-01

Algorithms for serial and parallel computation of forward dynamics of multiple-link robotic manipulators by conjugate-gradient method developed. Parallel algorithms have potential for speedup of computations on multiple linked, specialized processors implemented in very-large-scale integrated circuits. Such processors used to stimulate dynamics, possibly faster than in real time, for purposes of planning and control.

76 FR 7788 - Fisheries of the Exclusive Economic Zone off Alaska; Western Alaska Community Development Quota...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-02-11

... record in eLandings the region in which the stationary floating processor is located at time of crab... miscellaneous edits and corrections to regulatory text and tables, including standardizing the use of the terms... fishery management, resulting in fewer disruptions of the fleets and processors. The December 15, 2008...

Dynamic overset grid communication on distributed memory parallel processors

NASA Technical Reports Server (NTRS)

Barszcz, Eric; Weeratunga, Sisira K.; Meakin, Robert L.

1993-01-01

A parallel distributed memory implementation of intergrid communication for dynamic overset grids is presented. Included are discussions of various options considered during development. Results are presented comparing an Intel iPSC/860 to a single processor Cray Y-MP. Results for grids in relative motion show the iPSC/860 implementation to be faster than the Cray implementation.

A post-processor for the PEST code

DOE Office of Scientific and Technical Information (OSTI.GOV)

Priesche, S.; Manickam, J.; Johnson, J.L.

1992-01-01

A new post-processor has been developed for use with output from the PEST tokamak stability code. It allows us to use quantities calculated by PEST and take better advantage of the physical picture of the plasma instability which they can provide. This will improve comparison with experimentally measured quantities as well as facilitate understanding of theoretical studies.

Designing systems to satisfy their users - The coming changes in aviation weather and the development of a central weather processor

NASA Technical Reports Server (NTRS)

Bush, M. W.

1984-01-01

Attention is given to the development history of the Central Weather Processor (CWP) program of the Federal Aviation Administration. The CWP will interface with high speed digital communications links, accept data and information products from new sources, generate data processing products, and provide meteorologists with the capability to automate data retrieval and dissemination. The CWP's users are operational (air traffic controllers, meteorologists and pilots), institutional (logistics, maintenance, testing and evaluation personnel), and administrative.

Processor farming in two-level analysis of historical bridge

NASA Astrophysics Data System (ADS)

Krejčí, T.; Kruis, J.; Koudelka, T.; Šejnoha, M.

2017-11-01

This contribution presents a processor farming method in connection with a multi-scale analysis. In this method, each macro-scopic integration point or each finite element is connected with a certain meso-scopic problem represented by an appropriate representative volume element (RVE). The solution of a meso-scale problem provides then effective parameters needed on the macro-scale. Such an analysis is suitable for parallel computing because the meso-scale problems can be distributed among many processors. The application of the processor farming method to a real world masonry structure is illustrated by an analysis of Charles bridge in Prague. The three-dimensional numerical model simulates the coupled heat and moisture transfer of one half of arch No. 3. and it is a part of a complex hygro-thermo-mechanical analysis which has been developed to determine the influence of climatic loading on the current state of the bridge.

Control structures for high speed processors

NASA Technical Reports Server (NTRS)

Maki, G. K.; Mankin, R.; Owsley, P. A.; Kim, G. M.

1982-01-01

A special processor was designed to function as a Reed Solomon decoder with throughput data rate in the Mhz range. This data rate is significantly greater than is possible with conventional digital architectures. To achieve this rate, the processor design includes sequential, pipelined, distributed, and parallel processing. The processor was designed using a high level language register transfer language. The RTL can be used to describe how the different processes are implemented by the hardware. One problem of special interest was the development of dependent processes which are analogous to software subroutines. For greater flexibility, the RTL control structure was implemented in ROM. The special purpose hardware required approximately 1000 SSI and MSI components. The data rate throughput is 2.5 megabits/second. This data rate is achieved through the use of pipelined and distributed processing. This data rate can be compared with 800 kilobits/second in a recently proposed very large scale integration design of a Reed Solomon encoder.

Vectorization with SIMD extensions speeds up reconstruction in electron tomography.

PubMed

Agulleiro, J I; Garzón, E M; García, I; Fernández, J J

2010-06-01

Electron tomography allows structural studies of cellular structures at molecular detail. Large 3D reconstructions are needed to meet the resolution requirements. The processing time to compute these large volumes may be considerable and so, high performance computing techniques have been used traditionally. This work presents a vector approach to tomographic reconstruction that relies on the exploitation of the SIMD extensions available in modern processors in combination to other single processor optimization techniques. This approach succeeds in producing full resolution tomograms with an important reduction in processing time, as evaluated with the most common reconstruction algorithms, namely WBP and SIRT. The main advantage stems from the fact that this approach is to be run on standard computers without the need of specialized hardware, which facilitates the development, use and management of programs. Future trends in processor design open excellent opportunities for vector processing with processor's SIMD extensions in the field of 3D electron microscopy.

Hyperswitch Communication Network Computer

NASA Technical Reports Server (NTRS)

Peterson, John C.; Chow, Edward T.; Priel, Moshe; Upchurch, Edwin T.

1993-01-01

Hyperswitch Communications Network (HCN) computer is prototype multiple-processor computer being developed. Incorporates improved version of hyperswitch communication network described in "Hyperswitch Network For Hypercube Computer" (NPO-16905). Designed to support high-level software and expansion of itself. HCN computer is message-passing, multiple-instruction/multiple-data computer offering significant advantages over older single-processor and bus-based multiple-processor computers, with respect to price/performance ratio, reliability, availability, and manufacturing. Design of HCN operating-system software provides flexible computing environment accommodating both parallel and distributed processing. Also achieves balance among following competing factors; performance in processing and communications, ease of use, and tolerance of (and recovery from) faults.

Extended Logic Intelligent Processing System for a Sensor Fusion Processor Hardware

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Thomas, Tyson; Li, Wei-Te; Daud, Taher; Fabunmi, James

2000-01-01

The paper presents the hardware implementation and initial tests from a low-power, highspeed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) is described, which combines rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor signals in compact low power VLSI. The development of the ELIPS concept is being done to demonstrate the interceptor functionality which particularly underlines the high speed and low power requirements. The hardware programmability allows the processor to reconfigure into different machines, taking the most efficient hardware implementation during each phase of information processing. Processing speeds of microseconds have been demonstrated using our test hardware.

Evaluation of Natural Language Processors.

DTIC Science & Technology

1980-11-01

techniques described. Common practice in describing natural language processors is to describe the programs, then give about 20 examples of correctly...make a decision based on performance as to which approaches are most promising for further research and development. The lack of evaluation leaves...successively more difficult problems. This approach might be compared to children taking achievement tests in school. A 90% score on problems involving

77 FR 21065 - Certain High Production Volume Chemicals; Test Rule and Significant New Use Rule; Fourth Group of...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-04-09

... Substances Control Act (TSCA). The test rule would require manufacturers and processors to develop screening... in 40 CFR 799.5090(j) or 40 CFR 721.10228(a) of the proposed rule's regulatory text published in the... petroleum refineries. Processors of one or more of the subject chemical substances (NAICS codes 325 and...

CALL in the Zone of Proximal Development: Novelty Effects and Teacher Guidance

ERIC Educational Resources Information Center

Karlström, Petter; Lundin, Eva

2013-01-01

Digital tools are not always used in the manner their designers had in mind. Therefore, it is not enough to assume that learning through CALL tools occurs in intended ways, if at all. We have studied the use of an enhanced word processor for writing essays in Swedish as a second language. The word processor contained natural language processing…

Development of a 30-cm ion thruster thermal-vacuum power processor

NASA Technical Reports Server (NTRS)

Herron, B. G.

1976-01-01

The 30-cm Hg electron-bombardment ion thruster presently under development has reached engineering model status and is generally accepted as the prime propulsion thruster module to be used on the earliest solar electric propulsion missions. This paper presents the results of a related program to develop a transistorized 3-kW Thermal-Vacuum Breadboard (TVBB) Power Processor for this thruster. Emphasized in the paper are the implemented electrical and mechanical designs as well as the resultant system performance achieved over a range of test conditions. In addition, design modifications affording improved performance are identified and discussed.

Development of a software interface for optical disk archival storage for a new life sciences flight experiments computer

NASA Technical Reports Server (NTRS)

Bartram, Peter N.

1989-01-01

The current Life Sciences Laboratory Equipment (LSLE) microcomputer for life sciences experiment data acquisition is now obsolete. Among the weaknesses of the current microcomputer are small memory size, relatively slow analog data sampling rates, and the lack of a bulk data storage device. While life science investigators normally prefer data to be transmitted to Earth as it is taken, this is not always possible. No down-link exists for experiments performed in the Shuttle middeck region. One important aspect of a replacement microcomputer is provision for in-flight storage of experimental data. The Write Once, Read Many (WORM) optical disk was studied because of its high storage density, data integrity, and the availability of a space-qualified unit. In keeping with the goals for a replacement microcomputer based upon commercially available components and standard interfaces, the system studied includes a Small Computer System Interface (SCSI) for interfacing the WORM drive. The system itself is designed around the STD bus, using readily available boards. Configurations examined were: (1) master processor board and slave processor board with the SCSI interface; (2) master processor with SCSI interface; (3) master processor with SCSI and Direct Memory Access (DMA); (4) master processor controlling a separate STD bus SCSI board; and (5) master processor controlling a separate STD bus SCSI board with DMA.

Integrated circuit for SAW and MEMS sensors

NASA Astrophysics Data System (ADS)

Fischer, Wolf-Joachim; Koenig, Peter; Ploetner, Matthias; Hermann, Rudiger; Stab, Helmut

2001-11-01

The sensor processor circuit has been developed for hand-held devices used in industrial and environmental applications, such as on-line process monitoring. Thereby devices with SAW sensors or MEMS resonators will benefit from this processor especially. Up to 8 sensors can be connected to the circuit as multisensors or sensor arrays. Two sensor processors SP1 and SP2 for different applications are presented in this paper. The SP-1 chip has a PCMCIA interface which can be used for the program and data transfer. SAW sensors which are working in the frequency range from 80 MHz to 160 MHz can be connected to the processor directly. It is possible to use the new SP-2 chip fabricated in a 0.5(mu) CMOS process for SAW devices with a maximum frequency of 600 MHz. An on-chip analog-digital-converter (ADC) and 6 PWM modules support the development of high-miniaturized intelligent sensor systems We have developed a multi-SAW sensor system with this ASIC that manages the requirements on control as well as signal generation and storage and provides an interface to the PC and electronic devices on the board. Its low power consumption and its PCMCIA plug fulfil the requirements of small size and mobility. For this application sensors have been developed to detect hazardous gases in ambient air. Sensors with differently modified copper-phthalocyanine films are capable of detecting NO2 and O3, whereas those with a hyperbranched polyester film respond to NH3.

Efficiency of static core turn-off in a system-on-a-chip with variation

DOEpatents

Cher, Chen-Yong; Coteus, Paul W; Gara, Alan; Kursun, Eren; Paulsen, David P; Schuelke, Brian A; Sheets, II, John E; Tian, Shurong

2013-10-29

A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.

Greenhouse gas emissions and land use change from Jatropha curcas-based jet fuel in Brazil.

PubMed

Bailis, Robert E; Baka, Jennifer E

2010-11-15

This analysis presents a comparison of life-cycle GHG emissions from synthetic paraffinic kerosene (SPK) produced as jet fuel substitute from jatropha curcas feedstock cultivated in Brazil against a reference scenario of conventional jet fuel. Life cycle inventory data are derived from surveys of actual Jatropha growers and processors. Results indicate that a baseline scenario, which assumes a medium yield of 4 tons of dry fruit per hectare under drip irrigation with existing logistical conditions using energy-based coproduct allocation methodology, and assumes a 20-year plantation lifetime with no direct land use change (dLUC), results in the emissions of 40 kg CO₂e per GJ of fuel produced, a 55% reduction relative to conventional jet fuel. However, dLUC based on observations of land-use transitions leads to widely varying changes in carbon stocks ranging from losses in excess of 50 tons of carbon per hectare when Jatropha is planted in native cerrado woodlands to gains of 10-15 tons of carbon per hectare when Jatropha is planted in former agro-pastoral land. Thus, aggregate emissions vary from a low of 13 kg CO₂e per GJ when Jatropha is planted in former agro-pastoral lands, an 85% decrease from the reference scenario, to 141 kg CO₂e per GJ when Jatropha is planted in cerrado woodlands, a 60% increase over the reference scenario. Additional sensitivities are also explored, including changes in yield, exclusion of irrigation, shortened supply chains, and alternative allocation methodologies.

Calibrating thermal behavior of electronics

DOEpatents

Chainer, Timothy J.; Parida, Pritish R.; Schultz, Mark D.

2017-07-11

A method includes determining a relationship between indirect thermal data for a processor and a measured temperature associated with the processor, during a calibration process, obtaining the indirect thermal data for the processor during actual operation of the processor, and determining an actual significant temperature associated with the processor during the actual operation using the indirect thermal data for the processor during actual operation of the processor and the relationship.

Calibrating thermal behavior of electronics

DOEpatents

Chainer, Timothy J.; Parida, Pritish R.; Schultz, Mark D.

2016-05-31

A method includes determining a relationship between indirect thermal data for a processor and a measured temperature associated with the processor, during a calibration process, obtaining the indirect thermal data for the processor during actual operation of the processor, and determining an actual significant temperature associated with the processor during the actual operation using the indirect thermal data for the processor during actual operation of the processor and the relationship.

Calibrating thermal behavior of electronics

DOEpatents

Chainer, Timothy J.; Parida, Pritish R.; Schultz, Mark D.

2017-01-03

A method includes determining a relationship between indirect thermal data for a processor and a measured temperature associated with the processor, during a calibration process, obtaining the indirect thermal data for the processor during actual operation of the processor, and determining an actual significant temperature associated with the processor during the actual operation using the indirect thermal data for the processor during actual operation of the processor and the relationship.

Web surveillance system using platform-based design

NASA Astrophysics Data System (ADS)

Lin, Shin-Yo; Tsai, Tsung-Han

2004-04-01

A revolutionary methodology of SOPC platform-based design environment for multimedia communications will be developed. We embed a softcore processor to perform the image compression in FPGA. Then, we plug-in an Ethernet daughter board in the SOPC development platform system. Afterward, a web surveillance platform system is presented. The web surveillance system consists of three parts: image capture, web server and JPEG compression. In this architecture, user can control the surveillance system by remote. By the IP address configures to Ethernet daughter board, the user can access the surveillance system via browser. When user access the surveillance system, the CMOS sensor presently capture the remote image. After that, it will feed the captured image with the embedded processor. The embedded processor immediately performs the JPEG compression. Afterward, the user receives the compressed data via Ethernet. To sum up of the above mentioned, the all system will be implemented on APEX20K200E484-2X device.

Image-Based Focusing

NASA Astrophysics Data System (ADS)

Selker, Ted

1983-05-01

Lens focusing using a hardware model of a retina (Reticon RL256 light sensitive array) with a low cost processor (8085 with 512 bytes of ROM and 512 bytes of RAM) was built. This system was developed and tested on a variety of visual stimuli to demonstrate that: a)an algorithm which moves a lens to maximize the sum of the difference of light level on adjacent light sensors will converge to best focus in all but contrived situations. This is a simpler algorithm than any previously suggested; b) it is feasible to use unmodified video sensor arrays with in-expensive processors to aid video camera use. In the future, software could be developed to extend the processor's usefulness, possibly to track an actor by panning and zooming to give a earners operator increased ease of framing; c) lateral inhibition is an adequate basis for determining best focus. This supports a simple anatomically motivated model of how our brain focuses our eyes.

Design and Development of a Baseband Processor for the Advanced Communications Technology Satellite

NASA Technical Reports Server (NTRS)

Lee, Kerry D.

1996-01-01

This paper describes the implementation of the operational baseband processor (BBP) subsystem on board the NASA Advanced Communications Technology Satellite (ACTS). The BBP supports the network consisting of the NASA ground station (NGS) low burst rate (LBR) terminals, and the T1 very small aperture terminals (VSAT's), to provide flexible, demand assigned satellite switched (SS), baseband processed frequency division modulated (FDM)/time division multiple access (TDMA) operations. This paper presents an overview of the baseband processor and includes a description of the data flow, functional block diagrams, and a discussion of the implementation of BBP. A discussion of the supporting technologies for the BBP is presented. A brief summary of BBP-level performance testing is also presented. Finally, a discussion of the implications of current technology on the BBP design, if it were to be developed today, is presented.

VLSI processors for signal detection in SETI

NASA Technical Reports Server (NTRS)

Duluk, J. F.; Linscott, I. R.; Peterson, A. M.; Burr, J.; Ekroot, B.; Twicken, J.

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

VLSI processors for signal detection in SETI.

PubMed

Duluk, J F; Linscott, I R; Peterson, A M; Burr, J; Ekroot, B; Twicken, J

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

Dedicated hardware processor and corresponding system-on-chip design for real-time laser speckle imaging.

PubMed

Jiang, Chao; Zhang, Hongyan; Wang, Jia; Wang, Yaru; He, Heng; Liu, Rui; Zhou, Fangyuan; Deng, Jialiang; Li, Pengcheng; Luo, Qingming

2011-11-01

Laser speckle imaging (LSI) is a noninvasive and full-field optical imaging technique which produces two-dimensional blood flow maps of tissues from the raw laser speckle images captured by a CCD camera without scanning. We present a hardware-friendly algorithm for the real-time processing of laser speckle imaging. The algorithm is developed and optimized specifically for LSI processing in the field programmable gate array (FPGA). Based on this algorithm, we designed a dedicated hardware processor for real-time LSI in FPGA. The pipeline processing scheme and parallel computing architecture are introduced into the design of this LSI hardware processor. When the LSI hardware processor is implemented in the FPGA running at the maximum frequency of 130 MHz, up to 85 raw images with the resolution of 640×480 pixels can be processed per second. Meanwhile, we also present a system on chip (SOC) solution for LSI processing by integrating the CCD controller, memory controller, LSI hardware processor, and LCD display controller into a single FPGA chip. This SOC solution also can be used to produce an application specific integrated circuit for LSI processing.

Scalable Multiprocessor for High-Speed Computing in Space

NASA Technical Reports Server (NTRS)

Lux, James; Lang, Minh; Nishimoto, Kouji; Clark, Douglas; Stosic, Dorothy; Bachmann, Alex; Wilkinson, William; Steffke, Richard

2004-01-01

A report discusses the continuing development of a scalable multiprocessor computing system for hard real-time applications aboard a spacecraft. "Hard realtime applications" signifies applications, like real-time radar signal processing, in which the data to be processed are generated at "hundreds" of pulses per second, each pulse "requiring" millions of arithmetic operations. In these applications, the digital processors must be tightly integrated with analog instrumentation (e.g., radar equipment), and data input/output must be synchronized with analog instrumentation, controlled to within fractions of a microsecond. The scalable multiprocessor is a cluster of identical commercial-off-the-shelf generic DSP (digital-signal-processing) computers plus generic interface circuits, including analog-to-digital converters, all controlled by software. The processors are computers interconnected by high-speed serial links. Performance can be increased by adding hardware modules and correspondingly modifying the software. Work is distributed among the processors in a parallel or pipeline fashion by means of a flexible master/slave control and timing scheme. Each processor operates under its own local clock; synchronization is achieved by broadcasting master time signals to all the processors, which compute offsets between the master clock and their local clocks.

Assessment of directionality performances: comparison between Freedom and CP810 sound processors.

PubMed

Razza, Sergio; Albanese, Greta; Ermoli, Lucilla; Zaccone, Monica; Cristofari, Eliana

2013-10-01

To compare speech recognition in noise for the Nucleus Freedom and CP810 sound processors using different directional settings among those available in the SmartSound portfolio. Single-subject, repeated measures study. Tertiary care referral center. Thirty-one monoaurally and binaurally implanted subjects (24 children and 7 adults) were enrolled. They were all experienced Nucleus Freedom sound processor users and achieved a 100% open set word recognition score in quiet listening conditions. Each patient was fitted with the Freedom and the CP810 processor. The program setting incorporated Adaptive Dynamic Range Optimization (ADRO) and adopted the directional algorithm BEAM (both devices) and ZOOM (only on CP810). Speech reception threshold (SRT) was assessed in a free-field layout, with disyllabic word list and interfering multilevel babble noise in the 3 different pre-processing configurations. On average, CP810 improved significantly patients' SRTs as compared to Freedom SP after 1 hour of use. Instead, no significant difference was observed in patients' SRT between the BEAM and the ZOOM algorithm fitted in the CP810 processor. The results suggest that hardware developments achieved in the design of CP810 allow an immediate and relevant directional advantage as compared to the previous-generation Freedom device.

Analyses on Cost Reduction and CO2 Mitigation by Penetration of Fuel Cells to Residential Houses

NASA Astrophysics Data System (ADS)

Aki, Hirohisa; Yamamoto, Shigeo; Kondoh, Junji; Murata, Akinobu; Ishii, Itaru; Maeda, Tetsuhiko

This paper presents analyses on the penetration of polymer electrolyte fuel cells (PEFC) into a group of 10 residential houses and its effects of CO2 emission mitigation and consumers’ cost reduction in next 30 years. The price is considered to be reduced as the penetration progress which is expected to begin in near future. An experimental curve is assumed to express the decrease of the price. Installation of energy interchange systems which involve electricity, gas and hydrogen between a house which has a FC and contiguous houses is assumed to utilize both electricity and heat more efficiently, and to avoid start-stop operation of fuel processor (reformer) as much as possible. A multi-objective model which considers CO2 mitigation and consumers’ cost reduction is constructed and provided a Pareto optimum solution. A solution which simultaneously realizes both CO2 mitigation and consumers’ cost reduction appeared in the Pareto optimum solution. Strategies to reduce CO2 emission and consumers’ cost are suggested from the results of the analyses. The analyses also revealed that the energy interchange systems are effective especially in the early stage of the penetration.

Missile signal processing common computer architecture for rapid technology upgrade

NASA Astrophysics Data System (ADS)

Rabinkin, Daniel V.; Rutledge, Edward; Monticciolo, Paul

2004-10-01

Interceptor missiles process IR images to locate an intended target and guide the interceptor towards it. Signal processing requirements have increased as the sensor bandwidth increases and interceptors operate against more sophisticated targets. A typical interceptor signal processing chain is comprised of two parts. Front-end video processing operates on all pixels of the image and performs such operations as non-uniformity correction (NUC), image stabilization, frame integration and detection. Back-end target processing, which tracks and classifies targets detected in the image, performs such algorithms as Kalman tracking, spectral feature extraction and target discrimination. In the past, video processing was implemented using ASIC components or FPGAs because computation requirements exceeded the throughput of general-purpose processors. Target processing was performed using hybrid architectures that included ASICs, DSPs and general-purpose processors. The resulting systems tended to be function-specific, and required custom software development. They were developed using non-integrated toolsets and test equipment was developed along with the processor platform. The lifespan of a system utilizing the signal processing platform often spans decades, while the specialized nature of processor hardware and software makes it difficult and costly to upgrade. As a result, the signal processing systems often run on outdated technology, algorithms are difficult to update, and system effectiveness is impaired by the inability to rapidly respond to new threats. A new design approach is made possible three developments; Moore's Law - driven improvement in computational throughput; a newly introduced vector computing capability in general purpose processors; and a modern set of open interface software standards. Today's multiprocessor commercial-off-the-shelf (COTS) platforms have sufficient throughput to support interceptor signal processing requirements. This application may be programmed under existing real-time operating systems using parallel processing software libraries, resulting in highly portable code that can be rapidly migrated to new platforms as processor technology evolves. Use of standardized development tools and 3rd party software upgrades are enabled as well as rapid upgrade of processing components as improved algorithms are developed. The resulting weapon system will have a superior processing capability over a custom approach at the time of deployment as a result of a shorter development cycles and use of newer technology. The signal processing computer may be upgraded over the lifecycle of the weapon system, and can migrate between weapon system variants enabled by modification simplicity. This paper presents a reference design using the new approach that utilizes an Altivec PowerPC parallel COTS platform. It uses a VxWorks-based real-time operating system (RTOS), and application code developed using an efficient parallel vector library (PVL). A quantification of computing requirements and demonstration of interceptor algorithm operating on this real-time platform are provided.

Document Image Parsing and Understanding using Neuromorphic Architecture

DTIC Science & Technology

2015-03-01

processing speed at different layers. In the pattern matching layer, the computing power of multicore processors is explored to reduce the processing...developed to reduce the processing speed at different layers. In the pattern matching layer, the computing power of multicore processors is explored... cortex where the complex data is reduced to abstract representations. The abstract representation is compared to stored patterns in massively parallel

A unified approach to VLSI layout automation and algorithm mapping on processor arrays

NASA Technical Reports Server (NTRS)

Venkateswaran, N.; Pattabiraman, S.; Srinivasan, Vinoo N.

1993-01-01

Development of software tools for designing supercomputing systems is highly complex and cost ineffective. To tackle this a special purpose PAcube silicon compiler which integrates different design levels from cell to processor arrays has been proposed. As a part of this, we present in this paper a novel methodology which unifies the problems of Layout Automation and Algorithm Mapping.

Recent developments of NASTRAN pre- amd post-processors: Response spectrum analysis (RESPAN) and interactive graphics (GIFTS)

NASA Technical Reports Server (NTRS)

Hirt, E. F.; Fox, G. L.

1982-01-01

Two specific NASTRAN preprocessors and postprocessors are examined. A postprocessor for dynamic analysis and a graphical interactive package for model generation and review of resuls are presented. A computer program that provides response spectrum analysis capability based on data from NASTRAN finite element model is described and the GIFTS system, a graphic processor to augment NASTRAN is introduced.

Vascular system modeling in parallel environment - distributed and shared memory approaches

PubMed Central

Jurczuk, Krzysztof; Kretowski, Marek; Bezy-Wendling, Johanne

2011-01-01

The paper presents two approaches in parallel modeling of vascular system development in internal organs. In the first approach, new parts of tissue are distributed among processors and each processor is responsible for perfusing its assigned parts of tissue to all vascular trees. Communication between processors is accomplished by passing messages and therefore this algorithm is perfectly suited for distributed memory architectures. The second approach is designed for shared memory machines. It parallelizes the perfusion process during which individual processing units perform calculations concerning different vascular trees. The experimental results, performed on a computing cluster and multi-core machines, show that both algorithms provide a significant speedup. PMID:21550891

Ssip-a processor interconnection simulator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Navaux, P.; Weber, R.; Prezzi, J.

1982-01-01

Recent growing interest in multiple processor architectures has given rise to the study of procesor-memory interconnections for the determination of better architectures. This paper concerns the development of the SSIP-sistema simulador de interconexao de processadores (processor interconnection simulating system) which allows the evaluation of different interconnection structures comparing its performance in order to provide parameters which would help the designer to define an architcture. A wide spectrum of systems may be evaluated, and their behaviour observed due to the features incorporated into the simulator program. The system modelling and the simulator program implementation are described. Some results that can bemore » obtained are shown, along with the discussion of their usefulness. 12 references.« less

Radiation-Hardened Electronics for Advanced Communications Systems

NASA Technical Reports Server (NTRS)

Whitaker, Sterling

2015-01-01

Novel approach enables high-speed special-purpose processors Advanced reconfigurable and reprogrammable communication systems will require sub-130-nanometer electronics. Legacy single event upset (SEU) radiation-tolerant circuits are ineffective at speeds greater than 125 megahertz. In Phase I of this project, ICs, LLC, demonstrated new base-level logic circuits that provide SEU immunity for sub-130-nanometer high-speed circuits. In Phase II, the company developed an innovative self-restoring logic (SRL) circuit and a system approach that provides high-speed, SEU-tolerant solutions that are effective for sub-130-nanometer electronics scalable to at least 22-nanometer processes. The SRL system can be used in the design of NASA's next-generation special-purpose processors, especially reconfigurable communication processors.

MILC Code Performance on High End CPU and GPU Supercomputer Clusters

NASA Astrophysics Data System (ADS)

DeTar, Carleton; Gottlieb, Steven; Li, Ruizi; Toussaint, Doug

2018-03-01

With recent developments in parallel supercomputing architecture, many core, multi-core, and GPU processors are now commonplace, resulting in more levels of parallelism, memory hierarchy, and programming complexity. It has been necessary to adapt the MILC code to these new processors starting with NVIDIA GPUs, and more recently, the Intel Xeon Phi processors. We report on our efforts to port and optimize our code for the Intel Knights Landing architecture. We consider performance of the MILC code with MPI and OpenMP, and optimizations with QOPQDP and QPhiX. For the latter approach, we concentrate on the staggered conjugate gradient and gauge force. We also consider performance on recent NVIDIA GPUs using the QUDA library.

The development of an engineering computer graphics laboratory

NASA Technical Reports Server (NTRS)

Anderson, D. C.; Garrett, R. E.

1975-01-01

Hardware and software systems developed to further research and education in interactive computer graphics were described, as well as several of the ongoing application-oriented projects, educational graphics programs, and graduate research projects. The software system consists of a FORTRAN 4 subroutine package, in conjunction with a PDP 11/40 minicomputer as the primary computation processor and the Imlac PDS-1 as an intelligent display processor. The package comprises a comprehensive set of graphics routines for dynamic, structured two-dimensional display manipulation, and numerous routines to handle a variety of input devices at the Imlac.

Satellite on-board real-time SAR processor prototype

NASA Astrophysics Data System (ADS)

Bergeron, Alain; Doucet, Michel; Harnisch, Bernd; Suess, Martin; Marchese, Linda; Bourqui, Pascal; Desnoyers, Nicholas; Legros, Mathieu; Guillot, Ludovic; Mercier, Luc; Châteauneuf, François

2017-11-01

A Compact Real-Time Optronic SAR Processor has been successfully developed and tested up to a Technology Readiness Level of 4 (TRL4), the breadboard validation in a laboratory environment. SAR, or Synthetic Aperture Radar, is an active system allowing day and night imaging independent of the cloud coverage of the planet. The SAR raw data is a set of complex data for range and azimuth, which cannot be compressed. Specifically, for planetary missions and unmanned aerial vehicle (UAV) systems with limited communication data rates this is a clear disadvantage. SAR images are typically processed electronically applying dedicated Fourier transformations. This, however, can also be performed optically in real-time. Originally the first SAR images were optically processed. The optical Fourier processor architecture provides inherent parallel computing capabilities allowing real-time SAR data processing and thus the ability for compression and strongly reduced communication bandwidth requirements for the satellite. SAR signal return data are in general complex data. Both amplitude and phase must be combined optically in the SAR processor for each range and azimuth pixel. Amplitude and phase are generated by dedicated spatial light modulators and superimposed by an optical relay set-up. The spatial light modulators display the full complex raw data information over a two-dimensional format, one for the azimuth and one for the range. Since the entire signal history is displayed at once, the processor operates in parallel yielding real-time performances, i.e. without resulting bottleneck. Processing of both azimuth and range information is performed in a single pass. This paper focuses on the onboard capabilities of the compact optical SAR processor prototype that allows in-orbit processing of SAR images. Examples of processed ENVISAT ASAR images are presented. Various SAR processor parameters such as processing capabilities, image quality (point target analysis), weight and size are reviewed.

Space Station Environmental Control and Life Support Systems: An Update on Waste Water Reclamation

NASA Technical Reports Server (NTRS)

Ferner, Kathleen M.

1994-01-01

Since the mid-1980's, work has been ongoing In the development of the various environmental control and life support systems (ECLSS) for the space station. Part of this effort has been focused on the development of a new subsystem to reclaim waste water that had not been previously required for shuttle missions. Because of the extended manned missions proposed, reclamation of waste water becomes imperative to avoid the weight penalties associated with resupplying a crew's entire water needs for consumption and daily hygiene. Hamilton Standard, under contract to Boeing Aerospace and Electronics, has been designing the water reclamation system for space station use. Since June of 1991, Hamilton Standard has developed a combined water processor capable of reclaiming potable quality water from waste hygiene water, used laundry water, processed urine, Shuttle fuel cell water, humidity condensate and other minor waste water sources. The system was assembled and then tested with over 27,700 pounds of 'real' waste water. During the 1700 hours of system operation required to process this waste water, potable quality water meeting NASA and Boeing specifications was produced. This paper gives a schematic overview of the system, describes the test conditions and test results and outlines the next steps for system development.

Methods and systems for providing reconfigurable and recoverable computing resources

NASA Technical Reports Server (NTRS)

Stange, Kent (Inventor); Hess, Richard (Inventor); Kelley, Gerald B (Inventor); Rogers, Randy (Inventor)

2010-01-01

A method for optimizing the use of digital computing resources to achieve reliability and availability of the computing resources is disclosed. The method comprises providing one or more processors with a recovery mechanism, the one or more processors executing one or more applications. A determination is made whether the one or more processors needs to be reconfigured. A rapid recovery is employed to reconfigure the one or more processors when needed. A computing system that provides reconfigurable and recoverable computing resources is also disclosed. The system comprises one or more processors with a recovery mechanism, with the one or more processors configured to execute a first application, and an additional processor configured to execute a second application different than the first application. The additional processor is reconfigurable with rapid recovery such that the additional processor can execute the first application when one of the one more processors fails.

Second International Workshop on Software Engineering and Code Design in Parallel Meteorological and Oceanographic Applications

NASA Technical Reports Server (NTRS)

OKeefe, Matthew (Editor); Kerr, Christopher L. (Editor)

1998-01-01

This report contains the abstracts and technical papers from the Second International Workshop on Software Engineering and Code Design in Parallel Meteorological and Oceanographic Applications, held June 15-18, 1998, in Scottsdale, Arizona. The purpose of the workshop is to bring together software developers in meteorology and oceanography to discuss software engineering and code design issues for parallel architectures, including Massively Parallel Processors (MPP's), Parallel Vector Processors (PVP's), Symmetric Multi-Processors (SMP's), Distributed Shared Memory (DSM) multi-processors, and clusters. Issues to be discussed include: (1) code architectures for current parallel models, including basic data structures, storage allocation, variable naming conventions, coding rules and styles, i/o and pre/post-processing of data; (2) designing modular code; (3) load balancing and domain decomposition; (4) techniques that exploit parallelism efficiently yet hide the machine-related details from the programmer; (5) tools for making the programmer more productive; and (6) the proliferation of programming models (F--, OpenMP, MPI, and HPF).

A case study for the real-time experimental evaluation of the VIPER microprocessor

NASA Astrophysics Data System (ADS)

Carreno, Victor A.; Angellatta, Rob K.

1991-09-01

An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.

Implementing An Image Understanding System Architecture Using Pipe

NASA Astrophysics Data System (ADS)

Luck, Randall L.

1988-03-01

This paper will describe PIPE and how it can be used to implement an image understanding system. Image understanding is the process of developing a description of an image in order to make decisions about its contents. The tasks of image understanding are generally split into low level vision and high level vision. Low level vision is performed by PIPE -a high performance parallel processor with an architecture specifically designed for processing video images at up to 60 fields per second. High level vision is performed by one of several types of serial or parallel computers - depending on the application. An additional processor called ISMAP performs the conversion from iconic image space to symbolic feature space. ISMAP plugs into one of PIPE's slots and is memory mapped into the high level processor. Thus it forms the high speed link between the low and high level vision processors. The mechanisms for bottom-up, data driven processing and top-down, model driven processing are discussed.

Optical interconnection using polyimide waveguide for multichip module

NASA Astrophysics Data System (ADS)

Koyanagi, Mitsumasa

1996-01-01

We have developed a parallel processor system with 152 RISC processor chips specific for Monte-Carlo analysis. This system has the ring-bus architecture. The performance of several Gflops is expected in this system according to the computer simulation. However, it was revealed that the data transfer speed of the bus has to be increased more dramatically in order to further increase the performance. Then, we propose to introduce the optical interconnection into the parallel processor system to increase the data transfer speed of the buses. The double ringbus architecture is employed in this new parallel processor system with optical interconnection. The free-space optical interconnection arid the optical waveguide are used for the optical ring-bus. Thin polyimide film was used to form the optical waveguide. A relatively low propagation loss was achieved in the polyimide optical waveguide. In addition, it was confirmed that the propagation direction of signal light can be easily changed by using a micro-mirror.

Optical interconnection using polyimide waveguide for multichip module

NASA Astrophysics Data System (ADS)

Koyanagi, Mitsumasa

1996-01-01

We have developed a parallel processor system with 152 RISC processor chips specific for Monte-Carlo analysis. This system has the ring-bus architecture. The performance of several Gflops is expected in this system according to the computer simulation. However, it was revealed that the data transfer speed of the bus has to be increased more dramatically in order to further increase the performance. Then, we propose to introduce the optical interconnection into the parallel processor system to increase the data transfer speed of the buses. The double ring-bus architecture is employed in this new parallel processor system with optical interconnection. The free-space optical interconnection and the optical waveguide are used for the optical ring-bus. Thin polyimide film was used to form the optical waveguide. A relatively low propagation loss was achieved in the polyimide optical waveguide. In addition, it was confirmed that the propagation direction of signal light can be easily changed by using a micro-mirror.

Study of a unified hardware and software fault-tolerant architecture

NASA Technical Reports Server (NTRS)

Lala, Jaynarayan; Alger, Linda; Friend, Steven; Greeley, Gregory; Sacco, Stephen; Adams, Stuart

1989-01-01

A unified architectural concept, called the Fault Tolerant Processor Attached Processor (FTP-AP), that can tolerate hardware as well as software faults is proposed for applications requiring ultrareliable computation capability. An emulation of the FTP-AP architecture, consisting of a breadboard Motorola 68010-based quadruply redundant Fault Tolerant Processor, four VAX 750s as attached processors, and four versions of a transport aircraft yaw damper control law, is used as a testbed in the AIRLAB to examine a number of critical issues. Solutions of several basic problems associated with N-Version software are proposed and implemented on the testbed. This includes a confidence voter to resolve coincident errors in N-Version software. A reliability model of N-Version software that is based upon the recent understanding of software failure mechanisms is also developed. The basic FTP-AP architectural concept appears suitable for hosting N-Version application software while at the same time tolerating hardware failures. Architectural enhancements for greater efficiency, software reliability modeling, and N-Version issues that merit further research are identified.

A case study for the real-time experimental evaluation of the VIPER microprocessor

NASA Technical Reports Server (NTRS)

Carreno, Victor A.; Angellatta, Rob K.

1991-01-01

An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.

RASSP signal processing architectures

NASA Astrophysics Data System (ADS)

Shirley, Fred; Bassett, Bob; Letellier, J. P.

1995-06-01

The rapid prototyping of application specific signal processors (RASSP) program is an ARPA/tri-service effort to dramatically improve the process by which complex digital systems, particularly embedded signal processors, are specified, designed, documented, manufactured, and supported. The domain of embedded signal processing was chosen because it is important to a variety of military and commercial applications as well as for the challenge it presents in terms of complexity and performance demands. The principal effort is being performed by two major contractors, Lockheed Sanders (Nashua, NH) and Martin Marietta (Camden, NJ). For both, improvements in methodology are to be exercised and refined through the performance of individual 'Demonstration' efforts. The Lockheed Sanders' Demonstration effort is to develop an infrared search and track (IRST) processor. In addition, both contractors' results are being measured by a series of externally administered (by Lincoln Labs) six-month Benchmark programs that measure process improvement as a function of time. The first two Benchmark programs are designing and implementing a synthetic aperture radar (SAR) processor. Our demonstration team is using commercially available VME modules from Mercury Computer to assemble a multiprocessor system scalable from one to hundreds of Intel i860 microprocessors. Custom modules for the sensor interface and display driver are also being developed. This system implements either proprietary or Navy owned algorithms to perform the compute-intensive IRST function in real time in an avionics environment. Our Benchmark team is designing custom modules using commercially available processor ship sets, communication submodules, and reconfigurable logic devices. One of the modules contains multiple vector processors optimized for fast Fourier transform processing. Another module is a fiberoptic interface that accepts high-rate input data from the sensors and provides video-rate output data to a display. This paper discusses the impact of simulation on choosing signal processing algorithms and architectures, drawing from the experiences of the Demonstration and Benchmark inter-company teams at Lockhhed Sanders, Motorola, Hughes, and ISX.

Goals of thermionic program for space power

NASA Technical Reports Server (NTRS)

English, R. E.

1981-01-01

The thermionic and Brayton reactor concepts were compared for application to space power. For a turbine inlet temperature of 15000 K the Brayton powerplant weighted 5 to 40% less than the thermionic concept. The out of core concept separates the thermionic converters from their reactor. Technical risks are diminished by: (1) moving the insolator out of the reactor; (2) allowing a higher thermal flux for the thermionic converters than is required of the reactor fuel; and (3) eliminating fuel swelling's threat against lifetime of the thermionic converters. Overall performance can be improved by including power processing in system optimization for design and technology on more efficient, higher temperature power processors. The thermionic reactors will be larger than those for competitive systems with higher conversion efficiency and lower reactor operating temperatures. It is concluded that although the effect of reactor size on shield weight will be modest for unmanned spacecraft, the penalty in shield weight will be large for manned or man-tended spacecraft.

Rectangular Array Of Digital Processors For Planning Paths

NASA Technical Reports Server (NTRS)

Kemeny, Sabrina E.; Fossum, Eric R.; Nixon, Robert H.

1993-01-01

Prototype 24 x 25 rectangular array of asynchronous parallel digital processors rapidly finds best path across two-dimensional field, which could be patch of terrain traversed by robotic or military vehicle. Implemented as single-chip very-large-scale integrated circuit. Excepting processors on edges, each processor communicates with four nearest neighbors along paths representing travel to north, south, east, and west. Each processor contains delay generator in form of 8-bit ripple counter, preset to 1 of 256 possible values. Operation begins with choice of processor representing starting point. Transmits signals to nearest neighbor processors, which retransmits to other neighboring processors, and process repeats until signals propagated across entire field.

Development of Improved Modeling and Analysis Techniques for Dynamics of Shell Structures

DTIC Science & Technology

1991-07-24

Engineering Sciences and Center for Space Structures and Control University of Colorado,Campus Box 429 Boulder, Colorado 80309 Accesion :or -.... ... i...system architecture ; third, to implement a decomposi- tion/mapping procedure that matches as far as possible the layout of the processors to the...element computations. In particular. we address issues that are related to the processor memory size. to the SIMD architecture and to the fast

Development and Use of Visual Explanations: Harnessing the Power of the "Seeing" Brain to Enhance Student Learning

ERIC Educational Resources Information Center

Schmidt, Shelly J.

2009-01-01

When students come to class, they bring with them the most powerful processor known to man--the human brain! Our job as teachers is to discover and implement practices that will make the most effective use of those brains. The human brain is a very powerful processor of sensory information, especially with regard to the sense of vision. We can…

EMCS Installation Follow-Up Study. Volume 2.

DTIC Science & Technology

1984-03-01

softwaLe is currently being developed by Power;. 4. The system includc;s an equation processor which p~ovi,.’ arithmetic, logicaL, and timing...packages are actually written using the equation processor. 5. The system colorgraphics capability was demonstrated. The system can be operated...extremely important. The AsteroAI drawings were reviewed by the Navy only on a cursory basis. This proved to be inad- equate . 15. The specifications

High speed optical object recognition processor with massive holographic memory

NASA Technical Reports Server (NTRS)

Chao, T.; Zhou, H.; Reyes, G.

2002-01-01

Real-time object recognition using a compact grayscale optical correlator will be introduced. A holographic memory module for storing a large bank of optimum correlation filters, to accommodate the large data throughput rate needed for many real-world applications, has also been developed. System architecture of the optical processor and the holographic memory will be presented. Application examples of this object recognition technology will also be demonstrated.

Benchmarking hypercube hardware and software

NASA Technical Reports Server (NTRS)

Grunwald, Dirk C.; Reed, Daniel A.

1986-01-01

It was long a truism in computer systems design that balanced systems achieve the best performance. Message passing parallel processors are no different. To quantify the balance of a hypercube design, an experimental methodology was developed and the associated suite of benchmarks was applied to several existing hypercubes. The benchmark suite includes tests of both processor speed in the absence of internode communication and message transmission speed as a function of communication patterns.

Molybdenum dioxide-based anode for solid oxide fuel cell applications

NASA Astrophysics Data System (ADS)

Kwon, Byeong Wan; Ellefson, Caleb; Breit, Joe; Kim, Jinsoo; Grant Norton, M.; Ha, Su

2013-12-01

The present paper describes the fabrication and performance of a molybdenum dioxide (MoO2)-based anode for liquid hydrocarbon/oxygenated hydrocarbon-fueled solid oxide fuel cells (SOFCs). These fuel cells first internally reform the complex liquid fuel into carbon fragments and hydrogen, which are then electrochemically oxidized to produce electrical energy without external fuel processors. The MoO2-based anode was fabricated on to an yttria-stabilized zirconia (YSZ) electrolyte via combined electrostatic spray deposition (ESD) and direct painting methods. The cell performance was measured by directly feeding liquid fuels such as n-dodecane (i.e., a model diesel/kerosene fuel) or biodiesel (i.e., a future biomass-based liquid fuel) to the MoO2-based anode at 850 °C. The maximum initial power densities obtained from our MoO2-based SOFC were 34 mW cm-2 and 45 mW cm-2 using n-dodecane and biodiesel, respectively. The initial power density of the MoO2-based SOFC was improved up to 2500 mW cm-2 by optimizing the porosity of the MoO2-based anode. To test the long-term stability of the MoO2-based anode SOFC against coking, n-dodecane was continuously fed into the cell for 24 h at the open circuit voltage (OCV). During long-term testing, voltage-current density (V-I) plots were periodically obtained and they showed no significant changes over the operation time. Microstructural examination of the tested cells indicated that the MoO2-based anode displayed negligible coke formation, which explains its stability. On the other hand, SOFCs with conventional nickel (Ni)-based anodes under the same operating conditions showed a significant amount of coke formation on the metal surface, which led to a rapid drop in cell performance. Hence, the present work demonstrates that MoO2-based anodes exhibit outstanding tolerance to coke formation. This result opens up the opportunity for more efficiently generating electrical energy from both existing transportation and next generation biomass-derived liquid fuels using liquid hydrocarbon/oxygenated hydrocarbon-fueled SOFCs.

Buffered coscheduling for parallel programming and enhanced fault tolerance

DOEpatents

Petrini, Fabrizio [Los Alamos, NM; Feng, Wu-chun [Los Alamos, NM

2006-01-31

A computer implemented method schedules processor jobs on a network of parallel machine processors or distributed system processors. Control information communications generated by each process performed by each processor during a defined time interval is accumulated in buffers, where adjacent time intervals are separated by strobe intervals for a global exchange of control information. A global exchange of the control information communications at the end of each defined time interval is performed during an intervening strobe interval so that each processor is informed by all of the other processors of the number of incoming jobs to be received by each processor in a subsequent time interval. The buffered coscheduling method of this invention also enhances the fault tolerance of a network of parallel machine processors or distributed system processors

Design and implementation of projects with Xilinx Zynq FPGA: a practical case

NASA Astrophysics Data System (ADS)

Travaglini, R.; D'Antone, I.; Meneghini, S.; Rignanese, L.; Zuffa, M.

The main advantage when using FPGAs with embedded processors is the availability of additional several high-performance resources in the same physical device. Moreover, the FPGA programmability allows for connect custom peripherals. Xilinx have designed a programmable device named Zynq-7000 (simply called Zynq in the following), which integrates programmable logic (identical to the other Xilinx "serie 7" devices) with a System on Chip (SOC) based on two embedded ARM processors. Since both parts are deeply connected, the designers benefit from performance of hardware SOC and flexibility of programmability as well. In this paper a design developed by the Electronic Design Department at the Bologna Division of INFN will be presented as a practical case of project based on Zynq device. It is developed by using a commercial board called ZedBoard hosting a FMC mezzanine with a 12-bit 500 MS/s ADC. The Zynq FPGA on the ZedBoard receives digital outputs from the ADC and send them to the acquisition PC, after proper formatting, through a Gigabit Ethernet link. The major focus of the paper will be about the methodology to develop a Zynq-based design with the Xilinx Vivado software, enlightening how to configure the SOC and connect it with the programmable logic. Firmware design techniques will be presented: in particular both VHDL and IP core based strategies will be discussed. Further, the procedure to develop software for the embedded processor will be presented. Finally, some debugging tools, like the embedded Logic Analyzer, will be shown. Advantages and disadvantages with respect to adopting FPGA without embedded processors will be discussed.

The evaluation of a clinical thermometer for measuring developer temperature in automatic film processors.

PubMed

Wilson, W B; Haus, A G; Nierman, C; Lillie, R; Batz, T; Moore, R

1993-01-01

In medical imaging, the temperature of the developer solution in the film processor affects film speed (radiation dose), film contrast, and film base plus fog. The National Council on Radiation Protection and Measurement (NCRP) Report 99 on Quality Assurance, and the American College of Radiology (ACR) Mammography Quality Control Manual for Radiologic Technologists, indicate that the developer temperature should be within +/- 0.5 degree F (+/- 0.3 degree C) of that recommended by the manufacturer for the specific film/developer combination being used. The accuracy and repeatability of the thermometer is most important. This paper describes the requirements of a thermometer for measuring the temperature of the developer solution and suggests an inexpensive but accurate device for doing so.

Flight design system level C requirements. Solid rocket booster and external tank impact prediction processors. [space transportation system

NASA Technical Reports Server (NTRS)

Seale, R. H.

1979-01-01

The prediction of the SRB and ET impact areas requires six separate processors. The SRB impact prediction processor computes the impact areas and related trajectory data for each SRB element. Output from this processor is stored on a secure file accessible by the SRB impact plot processor which generates the required plots. Similarly the ET RTLS impact prediction processor and the ET RTLS impact plot processor generates the ET impact footprints for return-to-launch-site (RTLS) profiles. The ET nominal/AOA/ATO impact prediction processor and the ET nominal/AOA/ATO impact plot processor generate the ET impact footprints for non-RTLS profiles. The SRB and ET impact processors compute the size and shape of the impact footprints by tabular lookup in a stored footprint dispersion data base. The location of each footprint is determined by simulating a reference trajectory and computing the reference impact point location. To insure consistency among all flight design system (FDS) users, much input required by these processors will be obtained from the FDS master data base.

Technology transfer of military space microprocessor developments

NASA Astrophysics Data System (ADS)

Gorden, C.; King, D.; Byington, L.; Lanza, D.

1999-01-01

Over the past 13 years the Air Force Research Laboratory (AFRL) has led the development of microprocessors and computers for USAF space and strategic missile applications. As a result of these Air Force development programs, advanced computer technology is available for use by civil and commercial space customers as well. The Generic VHSIC Spaceborne Computer (GVSC) program began in 1985 at AFRL to fulfill a deficiency in the availability of space-qualified data and control processors. GVSC developed a radiation hardened multi-chip version of the 16-bit, Mil-Std 1750A microprocessor. The follow-on to GVSC, the Advanced Spaceborne Computer Module (ASCM) program, was initiated by AFRL to establish two industrial sources for complete, radiation-hardened 16-bit and 32-bit computers and microelectronic components. Development of the Control Processor Module (CPM), the first of two ASCM contract phases, concluded in 1994 with the availability of two sources for space-qualified, 16-bit Mil-Std-1750A computers, cards, multi-chip modules, and integrated circuits. The second phase of the program, the Advanced Technology Insertion Module (ATIM), was completed in December 1997. ATIM developed two single board computers based on 32-bit reduced instruction set computer (RISC) processors. GVSC, CPM, and ATIM technologies are flying or baselined into the majority of today's DoD, NASA, and commercial satellite systems.

Alternative Water Processor Test Development

NASA Technical Reports Server (NTRS)

Pickering, Karen D.; Mitchell, Julie L.; Adam, Niklas M.; Barta, Daniel; Meyer, Caitlin E.; Pensinger, Stuart; Vega, Leticia M.; Callahan, Michael R.; Flynn, Michael; Wheeler, Ray;

Alternative Water Processor Test Development

NASA Technical Reports Server (NTRS)

Pickering, Karen D.; Mitchell, Julie; Vega, Leticia; Adam, Niklas; Flynn, Michael; Wjee (er. Rau); Lunn, Griffin; Jackson, Andrew

2012-01-01

The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrogen and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

Research in Parallel Algorithms and Software for Computational Aerosciences

NASA Technical Reports Server (NTRS)

Domel, Neal D.

1996-01-01

Phase I is complete for the development of a Computational Fluid Dynamics parallel code with automatic grid generation and adaptation for the Euler analysis of flow over complex geometries. SPLITFLOW, an unstructured Cartesian grid code developed at Lockheed Martin Tactical Aircraft Systems, has been modified for a distributed memory/massively parallel computing environment. The parallel code is operational on an SGI network, Cray J90 and C90 vector machines, SGI Power Challenge, and Cray T3D and IBM SP2 massively parallel machines. Parallel Virtual Machine (PVM) is the message passing protocol for portability to various architectures. A domain decomposition technique was developed which enforces dynamic load balancing to improve solution speed and memory requirements. A host/node algorithm distributes the tasks. The solver parallelizes very well, and scales with the number of processors. Partially parallelized and non-parallelized tasks consume most of the wall clock time in a very fine grain environment. Timing comparisons on a Cray C90 demonstrate that Parallel SPLITFLOW runs 2.4 times faster on 8 processors than its non-parallel counterpart autotasked over 8 processors.

Transputer parallel processing at NASA Lewis Research Center

NASA Technical Reports Server (NTRS)

Ellis, Graham K.

1989-01-01

The transputer parallel processing lab at NASA Lewis Research Center (LeRC) consists of 69 processors (transputers) that can be connected into various networks for use in general purpose concurrent processing applications. The main goal of the lab is to develop concurrent scientific and engineering application programs that will take advantage of the computational speed increases available on a parallel processor over the traditional sequential processor. Current research involves the development of basic programming tools. These tools will help standardize program interfaces to specific hardware by providing a set of common libraries for applications programmers. The thrust of the current effort is in developing a set of tools for graphics rendering/animation. The applications programmer currently has two options for on-screen plotting. One option can be used for static graphics displays and the other can be used for animated motion. The option for static display involves the use of 2-D graphics primitives that can be called from within an application program. These routines perform the standard 2-D geometric graphics operations in real-coordinate space as well as allowing multiple windows on a single screen.

Research in Parallel Algorithms and Software for Computational Aerosciences

NASA Technical Reports Server (NTRS)

Domel, Neal D.

1996-01-01

Phase 1 is complete for the development of a computational fluid dynamics CFD) parallel code with automatic grid generation and adaptation for the Euler analysis of flow over complex geometries. SPLITFLOW, an unstructured Cartesian grid code developed at Lockheed Martin Tactical Aircraft Systems, has been modified for a distributed memory/massively parallel computing environment. The parallel code is operational on an SGI network, Cray J90 and C90 vector machines, SGI Power Challenge, and Cray T3D and IBM SP2 massively parallel machines. Parallel Virtual Machine (PVM) is the message passing protocol for portability to various architectures. A domain decomposition technique was developed which enforces dynamic load balancing to improve solution speed and memory requirements. A host/node algorithm distributes the tasks. The solver parallelizes very well, and scales with the number of processors. Partially parallelized and non-parallelized tasks consume most of the wall clock time in a very fine grain environment. Timing comparisons on a Cray C90 demonstrate that Parallel SPLITFLOW runs 2.4 times faster on 8 processors than its non-parallel counterpart autotasked over 8 processors.

Design of stationary PEFC system configurations to meet heat and power demands

NASA Astrophysics Data System (ADS)

Wallmark, Cecilia; Alvfors, Per

This paper presents heat and power efficiencies of a modeled PEFC system and the methods used to create the system configuration. The paper also includes an example of a simulated fuel cell system supplying a building in Sweden with heat and power. The main method used to create an applicable fuel cell system configuration is pinch technology. This technology is used to evaluate and design a heat exchanger network for a PEFC system working under stationary conditions, in order to find a solution with high heat utilization. The heat exchanger network in the system connecting the reformer, the burner, gas cleaning, hot-water storage and the PEFC stack will affect the heat transferred to the hot-water storage and thereby the heating of the building. The fuel, natural gas, is reformed to a hydrogen-rich gas within a slightly pressurized system. The fuel processor investigated is steam reforming, followed by high- and low-temperature shift reactors and preferential oxidation. The system is connected to the electrical grid for backup and peak demands and to a hot-water storage to meet the varying heat demand for the building. The procedure for designing the fuel cell system installation as co-generation system is described, and the system is simulated for a specific building in Sweden during 1 year. The results show that the fuel cell system in combination with a burner and hot-water storage could supply the building with the required heat without exceeding any of the given limitations. The designed co-generation system will provide the building with most of its power requirements and would further generate income by sale of electricity to the power grid.

Thermo-mechanical properties of carbon nanotubes and applications in thermal management

NASA Astrophysics Data System (ADS)

Nguyen, Manh Hong; Thang Bui, Hung; Trinh Pham, Van; Phan, Ngoc Hong; Nguyen, Tuan Hong; Chuc Nguyen, Van; Quang Le, Dinh; Khoi Phan, Hong; Phan, Ngoc Minh

2016-06-01

Thanks to their very high thermal conductivity, high Young’s modulus and unique tensile strength, carbon nanotubes (CNTs) have become one of the most suitable nano additives for heat conductive materials. In this work, we present results obtained for the synthesis of heat conductive materials containing CNT based thermal greases, nanoliquids and lubricating oils. These synthesized heat conductive materials were applied to thermal management for high power electronic devices (CPUs, LEDs) and internal combustion engines. The simulation and experimental results on thermal greases for an Intel Pentium IV processor showed that the thermal conductivity of greases increases 1.4 times and the saturation temperature of the CPU decreased by 5 °C by using thermal grease containing 2 wt% CNTs. Nanoliquids containing CNT based distilled water/ethylene glycol were successfully applied in heat dissipation for an Intel Core i5 processor and a 450 W floodlight LED. The experimental results showed that the saturation temperature of the Intel Core i5 processor and the 450 W floodlight LED decreased by about 6 °C and 3.5 °C, respectively, when using nanoliquids containing 1 g l-1 of CNTs. The CNTs were also effectively utilized additive materials for the synthesis of lubricating oils to improve the thermal conductivity, heat dissipation efficiency and performance efficiency of engines. The experimental results show that the thermal conductivity of lubricating oils increased by 12.5%, the engine saved 15% fuel consumption, and the longevity of the lubricating oil increased up to 20 000 km by using 0.1% vol. CNTs in the lubricating oils. All above results have confirmed the tremendous application potential of heat conductive materials containing CNTs in thermal management for high power electronic devices, internal combustion engines and other high power apparatus.

Formal design specification of a Processor Interface Unit

NASA Technical Reports Server (NTRS)

Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

1992-01-01

This report describes work to formally specify the requirements and design of a processor interface unit (PIU), a single-chip subsystem providing memory-interface bus-interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. The need for high-quality design assurance in such applications is an undisputed fact, given the disastrous consequences that even a single design flaw can produce. Thus, the further development and application of formal methods to fault-tolerant systems is of critical importance as these systems see increasing use in modern society.

Hardware accuracy counters for application precision and quality feedback

DOE Office of Scientific and Technical Information (OSTI.GOV)

de Paula Rosa Piga, Leonardo; Majumdar, Abhinandan; Paul, Indrani

Methods, devices, and systems for capturing an accuracy of an instruction executing on a processor. An instruction may be executed on the processor, and the accuracy of the instruction may be captured using a hardware counter circuit. The accuracy of the instruction may be captured by analyzing bits of at least one value of the instruction to determine a minimum or maximum precision datatype for representing the field, and determining whether to adjust a value of the hardware counter circuit accordingly. The representation may be output to a debugger or logfile for use by a developer, or may be outputmore » to a runtime or virtual machine to automatically adjust instruction precision or gating of portions of the processor datapath.« less

Developing software to use parallel processing effectively. Final report, June-December 1987

DOE Office of Scientific and Technical Information (OSTI.GOV)

Center, J.

1988-10-01

This report describes the difficulties involved in writing efficient parallel programs and describes the hardware and software support currently available for generating software that utilizes processing effectively. Historically, the processing rate of single-processor computers has increased by one order of magnitude every five years. However, this pace is slowing since electronic circuitry is coming up against physical barriers. Unfortunately, the complexity of engineering and research problems continues to require ever more processing power (far in excess of the maximum estimated 3 Gflops achievable by single-processor computers). For this reason, parallel-processing architectures are receiving considerable interest, since they offer high performancemore » more cheaply than a single-processor supercomputer, such as the Cray.« less

Compiler analysis for irregular problems in FORTRAN D

NASA Technical Reports Server (NTRS)

Vonhanxleden, Reinhard; Kennedy, Ken; Koelbel, Charles; Das, Raja; Saltz, Joel

1992-01-01

We developed a dataflow framework which provides a basis for rigorously defining strategies to make use of runtime preprocessing methods for distributed memory multiprocessors. In many programs, several loops access the same off-processor memory locations. Our runtime support gives us a mechanism for tracking and reusing copies of off-processor data. A key aspect of our compiler analysis strategy is to determine when it is safe to reuse copies of off-processor data. Another crucial function of the compiler analysis is to identify situations which allow runtime preprocessing overheads to be amortized. This dataflow analysis will make it possible to effectively use the results of interprocedural analysis in our efforts to reduce interprocessor communication and the need for runtime preprocessing.

A Diagnostic System for Studying Energy Partitioning and Assessing the Response of the Ionosphere during HAARP Modification Experiments

NASA Technical Reports Server (NTRS)

Djuth, Frank T.; Elder, John H.; Williams, Kenneth L.

1996-01-01

This research program focused on the construction of several key radio wave diagnostics in support of the HF Active Auroral Ionospheric Research Program (HAARP). Project activities led to the design, development, and fabrication of a variety of hardware units and to the development of several menu-driven software packages for data acquisition and analysis. The principal instrumentation includes an HF (28 MHz) radar system, a VHF (50 MHz) radar system, and a high-speed radar processor consisting of three separable processing units. The processor system supports the HF and VHF radars and is capable of acquiring very detailed data with large incoherent scatter radars. In addition, a tunable HF receiver system having high dynamic range was developed primarily for measurements of stimulated electromagnetic emissions (SEE). A separate processor unit was constructed for the SEE receiver. Finally, a large amount of support instrumentation was developed to accommodate complex field experiments. Overall, the HAARP diagnostics are powerful tools for studying diverse ionospheric modification phenomena. They are also flexible enough to support a host of other missions beyond the scope of HAARP. Many new research programs have been initiated by applying the HAARP diagnostics to studies of natural atmospheric processes.

Generic element processor (application to nonlinear analysis)

NASA Technical Reports Server (NTRS)

Stanley, Gary

1989-01-01

The focus here is on one aspect of the Computational Structural Mechanics (CSM) Testbed: finite element technology. The approach involves a Generic Element Processor: a command-driven, database-oriented software shell that facilitates introduction of new elements into the testbed. This shell features an element-independent corotational capability that upgrades linear elements to geometrically nonlinear analysis, and corrects the rigid-body errors that plague many contemporary plate and shell elements. Specific elements that have been implemented in the Testbed via this mechanism include the Assumed Natural-Coordinate Strain (ANS) shell elements, developed with Professor K. C. Park (University of Colorado, Boulder), a new class of curved hybrid shell elements, developed by Dr. David Kang of LPARL (formerly a student of Professor T. Pian), other shell and solid hybrid elements developed by NASA personnel, and recently a repackaged version of the workhorse shell element used in the traditional STAGS nonlinear shell analysis code. The presentation covers: (1) user and developer interfaces to the generic element processor, (2) an explanation of the built-in corotational option, (3) a description of some of the shell-elements currently implemented, and (4) application to sample nonlinear shell postbuckling problems.

Assessment of mammographic film processor performance in a hospital and mobile screening unit.

PubMed

Murray, J G; Dowsett, D J; Laird, O; Ennis, J T

1992-12-01

In contrast to the majority of mammographic breast screening programmes, film processing at this centre occurs on site in both hospital and mobile trailer units. Initial (1989) quality control (QC) sensitometric tests revealed a large variation in film processor performance in the mobile unit. The clinical significance of these variations was assessed and acceptance limits for processor performance determined. Abnormal mammograms were used as reference material and copied using high definition 35 mm film over a range of exposure settings. The copies were than matched with QC film density variation from the mobile unit. All films were subsequently ranked for spatial and contrast resolution. Optimal values for processing time of 2 min (equivalent to film transit time 3 min and developer time 46 s) and temperature of 36 degrees C were obtained. The widespread anomaly of reporting film transit time as processing time is highlighted. Use of mammogram copies as a means of measuring the influence of film processor variation is advocated. Careful monitoring of the mobile unit film processor performance has produced stable quality comparable with the hospital based unit. The advantages of on site film processing are outlined. The addition of a sensitometric step wedge to all mammography film stock as a means of assessing image quality is recommended.

The Forest Method as a New Parallel Tree Method with the Sectional Voronoi Tessellation

NASA Astrophysics Data System (ADS)

Yahagi, Hideki; Mori, Masao; Yoshii, Yuzuru

1999-09-01

We have developed a new parallel tree method which will be called the forest method hereafter. This new method uses the sectional Voronoi tessellation (SVT) for the domain decomposition. The SVT decomposes a whole space into polyhedra and allows their flat borders to move by assigning different weights. The forest method determines these weights based on the load balancing among processors by means of the overload diffusion (OLD). Moreover, since all the borders are flat, before receiving the data from other processors, each processor can collect enough data to calculate the gravity force with precision. Both the SVT and the OLD are coded in a highly vectorizable manner to accommodate on vector parallel processors. The parallel code based on the forest method with the Message Passing Interface is run on various platforms so that a wide portability is guaranteed. Extensive calculations with 15 processors of Fujitsu VPP300/16R indicate that the code can calculate the gravity force exerted on 105 particles in each second for some ideal dark halo. This code is found to enable an N-body simulation with 107 or more particles for a wide dynamic range and is therefore a very powerful tool for the study of galaxy formation and large-scale structure in the universe.

Advanced computer architecture specification for automated weld systems

NASA Technical Reports Server (NTRS)

Katsinis, Constantine

1994-01-01

This report describes the requirements for an advanced automated weld system and the associated computer architecture, and defines the overall system specification from a broad perspective. According to the requirements of welding procedures as they relate to an integrated multiaxis motion control and sensor architecture, the computer system requirements are developed based on a proven multiple-processor architecture with an expandable, distributed-memory, single global bus architecture, containing individual processors which are assigned to specific tasks that support sensor or control processes. The specified architecture is sufficiently flexible to integrate previously developed equipment, be upgradable and allow on-site modifications.

Advanced flight computers for planetary exploration

NASA Technical Reports Server (NTRS)

Stephenson, R. Rhoads

1988-01-01

Research concerning flight computers for use on interplanetary probes is reviewed. The history of these computers from the Viking mission to the present is outlined. The differences between ground commercial computers and computers for planetary exploration are listed. The development of a computer for the Mariner Mark II comet rendezvous asteroid flyby mission is described. Various aspects of recently developed computer systems are examined, including the Max real time, embedded computer, a hypercube distributed supercomputer, a SAR data processor, a processor for the High Resolution IR Imaging Spectrometer, and a robotic vision multiresolution pyramid machine for processsing images obtained by a Mars Rover.

A class of parallel algorithms for computation of the manipulator inertia matrix

NASA Technical Reports Server (NTRS)

Fijany, Amir; Bejczy, Antal K.

1989-01-01

Parallel and parallel/pipeline algorithms for computation of the manipulator inertia matrix are presented. An algorithm based on composite rigid-body spatial inertia method, which provides better features for parallelization, is used for the computation of the inertia matrix. Two parallel algorithms are developed which achieve the time lower bound in computation. Also described is the mapping of these algorithms with topological variation on a two-dimensional processor array, with nearest-neighbor connection, and with cardinality variation on a linear processor array. An efficient parallel/pipeline algorithm for the linear array was also developed, but at significantly higher efficiency.

AFOSR BRI: Co-Design of Hardware/Software for Predicting MAV Aerodynamics

DTIC Science & Technology

2016-09-27

DOCUMENTATION PAGE Form ApprovedOMB No. 0704-0188 1. REPORT DATE (DD-MM-YYYY) 2. REPORT TYPE 4. TITLE AND SUBTITLE 5a. CONTRACT NUMBER 6. AUTHOR(S) 7...703-588-8494 AFOSR BRI While Moore’s Law theoretically doubles processor performance every 24 months, much of the realizable performance remains...past efforts to develop such CFD codes on accelerated processors showed limited success, our hardware/software co-design approach created malleable

Construction of a parallel processor for simulating manipulators and other mechanical systems

NASA Technical Reports Server (NTRS)

Hannauer, George

1991-01-01

This report summarizes the results of NASA Contract NAS5-30905, awarded under phase 2 of the SBIR Program, for a demonstration of the feasibility of a new high-speed parallel simulation processor, called the Real-Time Accelerator (RTA). The principal goals were met, and EAI is now proceeding with phase 3: development of a commercial product. This product is scheduled for commercial introduction in the second quarter of 1992.

Integración automatizada de las ecuaciones de Lagrange en el movimiento orbital.

NASA Astrophysics Data System (ADS)

Abad, A.; San Juan, J. F.

The new techniques of algebraic manipulation, especially the Poisson Series Processor, permit the analytical integration of the more and more complex problems of celestial mechanics. The authors are developing a new Poisson Series Processor, PSPC, and they use it to solve the Lagrange equation of the orbital motion. They integrate the Lagrange equation by using the stroboscopic method, and apply it to the main problem of the artificial satellite theory.

Control Circuitry for High Speed VLSI (Very Large Scale Integration) Winograd Fourier Transform Processors.

DTIC Science & Technology

1985-12-01

Office of Scientific Research , and Air Force Space Division are sponsoring research for the development of a high speed DFT processor. This DFT...to the arithmetic circuitry through a master/slave 11-15 %v OPR ONESHOT OUTPUT OUTPUT .., ~ INITIALIZATION COLUMN’ 00 N DONE CUTRPLANE PLAtNE Figure...Since the TSP is an NP-complete problem, many mathematicians, operations researchers , computer scientists and the like have proposed heuristic

Coding, testing and documentation of processors for the flight design system

NASA Technical Reports Server (NTRS)

1980-01-01

The general functional design and implementation of processors for a space flight design system are briefly described. Discussions of a basetime initialization processor; conic, analytical, and precision coasting flight processors; and an orbit lifetime processor are included. The functions of several utility routines are also discussed.

Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors

NASA Technical Reports Server (NTRS)

Fijany, Amir (Inventor); Bejczy, Antal K. (Inventor)

1994-01-01

In a computer having a large number of single-instruction multiple data (SIMD) processors, each of the SIMD processors has two sets of three individual processor elements controlled by a master control unit and interconnected among a plurality of register file units where data is stored. The register files input and output data in synchronism with a minor cycle clock under control of two slave control units controlling the register file units connected to respective ones of the two sets of processor elements. Depending upon which ones of the register file units are enabled to store or transmit data during a particular minor clock cycle, the processor elements within an SIMD processor are connected in rings or in pipeline arrays, and may exchange data with the internal bus or with neighboring SIMD processors through interface units controlled by respective ones of the two slave control units.

System and method for representing and manipulating three-dimensional objects on massively parallel architectures

DOEpatents

Karasick, Michael S.; Strip, David R.

1996-01-01

A parallel computing system is described that comprises a plurality of uniquely labeled, parallel processors, each processor capable of modelling a three-dimensional object that includes a plurality of vertices, faces and edges. The system comprises a front-end processor for issuing a modelling command to the parallel processors, relating to a three-dimensional object. Each parallel processor, in response to the command and through the use of its own unique label, creates a directed-edge (d-edge) data structure that uniquely relates an edge of the three-dimensional object to one face of the object. Each d-edge data structure at least includes vertex descriptions of the edge and a description of the one face. As a result, each processor, in response to the modelling command, operates upon a small component of the model and generates results, in parallel with all other processors, without the need for processor-to-processor intercommunication.

Switch for serial or parallel communication networks

DOEpatents

Crosette, D.B.

1994-07-19

A communication switch apparatus and a method for use in a geographically extensive serial, parallel or hybrid communication network linking a multi-processor or parallel processing system has a very low software processing overhead in order to accommodate random burst of high density data. Associated with each processor is a communication switch. A data source and a data destination, a sensor suite or robot for example, may also be associated with a switch. The configuration of the switches in the network are coordinated through a master processor node and depends on the operational phase of the multi-processor network: data acquisition, data processing, and data exchange. The master processor node passes information on the state to be assumed by each switch to the processor node associated with the switch. The processor node then operates a series of multi-state switches internal to each communication switch. The communication switch does not parse and interpret communication protocol and message routing information. During a data acquisition phase, the communication switch couples sensors producing data to the processor node associated with the switch, to a downlink destination on the communications network, or to both. It also may couple an uplink data source to its processor node. During the data exchange phase, the switch couples its processor node or an uplink data source to a downlink destination (which may include a processor node or a robot), or couples an uplink source to its processor node and its processor node to a downlink destination. 9 figs.

Switch for serial or parallel communication networks

DOEpatents

Crosette, Dario B.

1994-01-01

A communication switch apparatus and a method for use in a geographically extensive serial, parallel or hybrid communication network linking a multi-processor or parallel processing system has a very low software processing overhead in order to accommodate random burst of high density data. Associated with each processor is a communication switch. A data source and a data destination, a sensor suite or robot for example, may also be associated with a switch. The configuration of the switches in the network are coordinated through a master processor node and depends on the operational phase of the multi-processor network: data acquisition, data processing, and data exchange. The master processor node passes information on the state to be assumed by each switch to the processor node associated with the switch. The processor node then operates a series of multi-state switches internal to each communication switch. The communication switch does not parse and interpret communication protocol and message routing information. During a data acquisition phase, the communication switch couples sensors producing data to the processor node associated with the switch, to a downlink destination on the communications network, or to both. It also may couple an uplink data source to its processor node. During the data exchange phase, the switch couples its processor node or an uplink data source to a downlink destination (which may include a processor node or a robot), or couples an uplink source to its processor node and its processor node to a downlink destination.

Processor and method for developing a set of admissible fixture designs for a workpiece

DOEpatents

Brost, R.C.; Goldberg, K.Y.; Wallack, A.S.; Canny, J.

1996-08-13

A fixture process and method is provided for developing a complete set of all admissible fixture designs for a workpiece which prevents the workpiece from translating or rotating. The fixture processor generates the set of all admissible designs based on geometric access constraints and expected applied forces on the workpiece. For instance, the fixture processor may generate a set of admissible fixture designs for first, second and third locators placed in an array of holes on a fixture plate and a translating clamp attached to the fixture plate for contacting the workpiece. In another instance, a fixture vice is used in which first, second, third and fourth locators are used and first and second fixture jaws are tightened to secure the workpiece. The fixture process also ranks the set of admissible fixture designs according to a predetermined quality metric so that the optimal fixture design for the desired purpose may be identified from the set of all admissible fixture designs. 27 figs.

Processor and method for developing a set of admissible fixture designs for a workpiece

DOEpatents

Brost, Randolph C.; Goldberg, Kenneth Y.; Canny, John; Wallack, Aaron S.

1999-01-01

Methods and apparatus are provided for developing a complete set of all admissible Type I and Type II fixture designs for a workpiece. The fixture processor generates the set of all admissible designs based on geometric access constraints and expected applied forces on the workpiece. For instance, the fixture processor may generate a set of admissible fixture designs for first, second and third locators placed in an array of holes on a fixture plate and a translating clamp attached to the fixture plate for contacting the workpiece. In another instance, a fixture vise is used in which first, second, third and fourth locators are used and first and second fixture jaws are tightened to secure the workpiece. The fixture process also ranks the set of admissible fixture designs according to a predetermined quality metric so that the optimal fixture design for the desired purpose may be identified from the set of all admissible fixture designs.

Processor and method for developing a set of admissible fixture designs for a workpiece

DOEpatents

Brost, Randolph C.; Goldberg, Kenneth Y.; Wallack, Aaron S.; Canny, John

1996-01-01

A fixture process and method is provided for developing a complete set of all admissible fixture designs for a workpiece which prevents the workpiece from translating or rotating. The fixture processor generates the set of all admissible designs based on geometric access constraints and expected applied forces on the workpiece. For instance, the fixture processor may generate a set of admissible fixture designs for first, second and third locators placed in an array of holes on a fixture plate and a translating clamp attached to the fixture plate for contacting the workpiece. In another instance, a fixture vice is used in which first, second, third and fourth locators are used and first and second fixture jaws are tightened to secure the workpiece. The fixture process also ranks the set of admissible fixture designs according to a predetermined quality metric so that the optimal fixture design for the desired purpose may be identified from the set of all admissible fixture designs.

Processor and method for developing a set of admissible fixture designs for a workpiece

DOEpatents

Brost, R.C.; Goldberg, K.Y.; Canny, J.; Wallack, A.S.

1999-01-05

Methods and apparatus are provided for developing a complete set of all admissible Type 1 and Type 2 fixture designs for a workpiece. The fixture processor generates the set of all admissible designs based on geometric access constraints and expected applied forces on the workpiece. For instance, the fixture processor may generate a set of admissible fixture designs for first, second and third locators placed in an array of holes on a fixture plate and a translating clamp attached to the fixture plate for contacting the workpiece. In another instance, a fixture vise is used in which first, second, third and fourth locators are used and first and second fixture jaws are tightened to secure the workpiece. The fixture process also ranks the set of admissible fixture designs according to a predetermined quality metric so that the optimal fixture design for the desired purpose may be identified from the set of all admissible fixture designs. 44 figs.

Design of an Ada expert system shell for the VHSIC avionic modular flight processor

NASA Technical Reports Server (NTRS)

Fanning, F. Jesse

1992-01-01

The Embedded Computer System Expert System Shell (ES Shell) is an Ada-based expert system shell developed at the Avionics Laboratory for use on the VHSIC Avionic Modular Processor (VAMP) running under the Ada Avionics Real-Time Software (AARTS) Operating System. The ES Shell provides the interface between the expert system and the avionics environment, and controls execution of the expert system. Testing of the ES Shell in the Avionics Laboratory's Integrated Test Bed (ITB) has demonstrated its ability to control a non-deterministic software application executing on the VAMP's which can control the ITB's real-time closed-loop aircraft simulation. The results of these tests and the conclusions reached in the design and development of the ES Shell have played an important role in the formulation of the requirements for a production-quality expert system inference engine, an ingredient necessary for the successful use of expert systems on the VAMP embedded avionic flight processor.

Fundamental physics issues of multilevel logic in developing a parallel processor.

NASA Astrophysics Data System (ADS)

Bandyopadhyay, Anirban; Miki, Kazushi

2007-06-01

In the last century, On and Off physical switches, were equated with two decisions 0 and 1 to express every information in terms of binary digits and physically realize it in terms of switches connected in a circuit. Apart from memory-density increase significantly, more possible choices in particular space enables pattern-logic a reality, and manipulation of pattern would allow controlling logic, generating a new kind of processor. Neumann's computer is based on sequential logic, processing bits one by one. But as pattern-logic is generated on a surface, viewing whole pattern at a time is a truly parallel processing. Following Neumann's and Shannons fundamental thermodynamical approaches we have built compatible model based on series of single molecule based multibit logic systems of 4-12 bits in an UHV-STM. On their monolayer multilevel communication and pattern formation is experimentally verified. Furthermore, the developed intelligent monolayer is trained by Artificial Neural Network. Therefore fundamental weak interactions for the building of truly parallel processor are explored here physically and theoretically.

Cache Energy Optimization Techniques For Modern Processors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh

2013-01-01

Modern multicore processors are employing large last-level caches, for example Intel's E7-8800 processor uses 24MB L3 cache. Further, with each CMOS technology generation, leakage energy has been dramatically increasing and hence, leakage energy is expected to become a major source of energy dissipation, especially in last-level caches (LLCs). The conventional schemes of cache energy saving either aim at saving dynamic energy or are based on properties specific to first-level caches, and thus these schemes have limited utility for last-level caches. Further, several other techniques require offline profiling or per-application tuning and hence are not suitable for product systems. In thismore » book, we present novel cache leakage energy saving schemes for single-core and multicore systems; desktop, QoS, real-time and server systems. Also, we present cache energy saving techniques for caches designed with both conventional SRAM devices and emerging non-volatile devices such as STT-RAM (spin-torque transfer RAM). We present software-controlled, hardware-assisted techniques which use dynamic cache reconfiguration to configure the cache to the most energy efficient configuration while keeping the performance loss bounded. To profile and test a large number of potential configurations, we utilize low-overhead, micro-architecture components, which can be easily integrated into modern processor chips. We adopt a system-wide approach to save energy to ensure that cache reconfiguration does not increase energy consumption of other components of the processor. We have compared our techniques with state-of-the-art techniques and have found that our techniques outperform them in terms of energy efficiency and other relevant metrics. The techniques presented in this book have important applications in improving energy-efficiency of higher-end embedded, desktop, QoS, real-time, server processors and multitasking systems. This book is intended to be a valuable guide for both newcomers and veterans in the field of cache power management. It will help graduate students, CAD tool developers and designers in understanding the need of energy efficiency in modern computing systems. Further, it will be useful for researchers in gaining insights into algorithms and techniques for micro-architectural and system-level energy optimization using dynamic cache reconfiguration. We sincerely believe that the ``food for thought'' presented in this book will inspire the readers to develop even better ideas for designing ``green'' processors of tomorrow.« less

NSWC-NADC interactive communication links for AN/UYS-1 loadtape creation and retrieval

NASA Astrophysics Data System (ADS)

Greathouse, D. M.

1984-09-01

This report contains an alternative method of communication (interactive vs. remote batch) with the Naval Air Development Center for the creation and retrieval of AN/UYS-1 Advanced Signal Processor (ASP) operational software loadtapes. Operational software for the Digital Acoustic Sensor Simulator (DASS) program is developed and maintained at the Naval Air Development Center (NADC). The Facility for Automated Software Production (FASP), an NADC-resident software generation facility, provides the support tools necessary for data base creation, software development and maintenance, and loadtape generation. Once a loadtape file is generated at NADC, it must be retrieved via telephone transmission and placed in a format suitable for loading into the AN/UYS-1 Advanced Signal Processor (ASP).

Algorithms and Libraries

NASA Technical Reports Server (NTRS)

Dongarra, Jack

1998-01-01

This exploratory study initiated our inquiry into algorithms and applications that would benefit by latency tolerant approach to algorithm building, including the construction of new algorithms where appropriate. In a multithreaded execution, when a processor reaches a point where remote memory access is necessary, the request is sent out on the network and a context--switch occurs to a new thread of computation. This effectively masks a long and unpredictable latency due to remote loads, thereby providing tolerance to remote access latency. We began to develop standards to profile various algorithm and application parameters, such as the degree of parallelism, granularity, precision, instruction set mix, interprocessor communication, latency etc. These tools will continue to develop and evolve as the Information Power Grid environment matures. To provide a richer context for this research, the project also focused on issues of fault-tolerance and computation migration of numerical algorithms and software. During the initial phase we tried to increase our understanding of the bottlenecks in single processor performance. Our work began by developing an approach for the automatic generation and optimization of numerical software for processors with deep memory hierarchies and pipelined functional units. Based on the results we achieved in this study we are planning to study other architectures of interest, including development of cost models, and developing code generators appropriate to these architectures.

Fast Fourier Transform Co-Processor (FFTC)- Towards Embedded GFLOPs

NASA Astrophysics Data System (ADS)

Kuehl, Christopher; Liebstueckel, Uwe; Tejerina, Isaac; Uemminghaus, Michael; Wite, Felix; Kolb, Michael; Suess, Martin; Weigand, Roland

2012-08-01

Many signal processing applications and algorithms perform their operations on the data in the transform domain to gain efficiency. The Fourier Transform Co- Processor has been developed with the aim to offload General Purpose Processors from performing these transformations and therefore to boast the overall performance of a processing module. The IP of the commercial PowerFFT processor has been selected and adapted to meet the constraints of the space environment.In frame of the ESA activity “Fast Fourier Transform DSP Co-processor (FFTC)” (ESTEC/Contract No. 15314/07/NL/LvH/ma) the objectives were the following:Production of prototypes of a space qualified version of the commercial PowerFFT chip called FFTC based on the PowerFFT IP.The development of a stand-alone FFTC Accelerator Board (FTAB) based on the FFTC including the Controller FPGA and SpaceWire Interfaces to verify the FFTC function and performance.The FFTC chip performs its calculations with floating point precision. Stand alone it is capable computing FFTs of up to 1K complex samples in length in only 10μsec. This corresponds to an equivalent processing performance of 4.7 GFlops. In this mode the maximum sustained data throughput reaches 6.4Gbit/s. When connected to up to 4 EDAC protected SDRAM memory banks the FFTC can perform long FFTs with up to 1M complex samples in length or multidimensional FFT- based processing tasks.A Controller FPGA on the FTAB takes care of the SDRAM addressing. The instructions commanded via the Controller FPGA are used to set up the data flow and generate the memory addresses.The presentation will give and overview on the project, including the results of the validation of the FFTC ASIC prototypes.

Fast Fourier Transform Co-processor (FFTC), towards embedded GFLOPs

NASA Astrophysics Data System (ADS)

Kuehl, Christopher; Liebstueckel, Uwe; Tejerina, Isaac; Uemminghaus, Michael; Witte, Felix; Kolb, Michael; Suess, Martin; Weigand, Roland; Kopp, Nicholas

2012-10-01

Many signal processing applications and algorithms perform their operations on the data in the transform domain to gain efficiency. The Fourier Transform Co-Processor has been developed with the aim to offload General Purpose Processors from performing these transformations and therefore to boast the overall performance of a processing module. The IP of the commercial PowerFFT processor has been selected and adapted to meet the constraints of the space environment. In frame of the ESA activity "Fast Fourier Transform DSP Co-processor (FFTC)" (ESTEC/Contract No. 15314/07/NL/LvH/ma) the objectives were the following: • Production of prototypes of a space qualified version of the commercial PowerFFT chip called FFTC based on the PowerFFT IP. • The development of a stand-alone FFTC Accelerator Board (FTAB) based on the FFTC including the Controller FPGA and SpaceWire Interfaces to verify the FFTC function and performance. The FFTC chip performs its calculations with floating point precision. Stand alone it is capable computing FFTs of up to 1K complex samples in length in only 10μsec. This corresponds to an equivalent processing performance of 4.7 GFlops. In this mode the maximum sustained data throughput reaches 6.4Gbit/s. When connected to up to 4 EDAC protected SDRAM memory banks the FFTC can perform long FFTs with up to 1M complex samples in length or multidimensional FFT-based processing tasks. A Controller FPGA on the FTAB takes care of the SDRAM addressing. The instructions commanded via the Controller FPGA are used to set up the data flow and generate the memory addresses. The paper will give an overview on the project, including the results of the validation of the FFTC ASIC prototypes.

Conditions for space invariance in optical data processors used with coherent or noncoherent light.

PubMed

Arsenault, H R

1972-10-01

The conditions for space invariance in coherent and noncoherent optical processors are considered. All linear optical processors are shown to belong to one of two types. The conditions for space invariance are more stringent for noncoherent processors than for coherent processors, so that a system that is linear in coherent light may be nonlinear in noncoherent light. However, any processor that is linear in noncoherent light is also linear in the coherent limit.

Fast and Accurate Simulation of the Cray XMT Multithreaded Supercomputer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Villa, Oreste; Tumeo, Antonino; Secchi, Simone

Irregular applications, such as data mining and analysis or graph-based computations, show unpredictable memory/network access patterns and control structures. Highly multithreaded architectures with large processor counts, like the Cray MTA-1, MTA-2 and XMT, appear to address their requirements better than commodity clusters. However, the research on highly multithreaded systems is currently limited by the lack of adequate architectural simulation infrastructures due to issues such as size of the machines, memory footprint, simulation speed, accuracy and customization. At the same time, Shared-memory MultiProcessors (SMPs) with multi-core processors have become an attractive platform to simulate large scale machines. In this paper, wemore » introduce a cycle-level simulator of the highly multithreaded Cray XMT supercomputer. The simulator runs unmodified XMT applications. We discuss how we tackled the challenges posed by its development, detailing the techniques introduced to make the simulation as fast as possible while maintaining a high accuracy. By mapping XMT processors (ThreadStorm with 128 hardware threads) to host computing cores, the simulation speed remains constant as the number of simulated processors increases, up to the number of available host cores. The simulator supports zero-overhead switching among different accuracy levels at run-time and includes a network model that takes into account contention. On a modern 48-core SMP host, our infrastructure simulates a large set of irregular applications 500 to 2000 times slower than real time when compared to a 128-processor XMT, while remaining within 10\\% of accuracy. Emulation is only from 25 to 200 times slower than real time.« less

Broadcasting collective operation contributions throughout a parallel computer

DOEpatents

Faraj, Ahmad [Rochester, MN

2012-02-21

Methods, systems, and products are disclosed for broadcasting collective operation contributions throughout a parallel computer. The parallel computer includes a plurality of compute nodes connected together through a data communications network. Each compute node has a plurality of processors for use in collective parallel operations on the parallel computer. Broadcasting collective operation contributions throughout a parallel computer according to embodiments of the present invention includes: transmitting, by each processor on each compute node, that processor's collective operation contribution to the other processors on that compute node using intra-node communications; and transmitting on a designated network link, by each processor on each compute node according to a serial processor transmission sequence, that processor's collective operation contribution to the other processors on the other compute nodes using inter-node communications.

High speed packet switching

NASA Technical Reports Server (NTRS)

1991-01-01

This document constitutes the final report prepared by Proteon, Inc. of Westborough, Massachusetts under contract NAS 5-30629 entitled High-Speed Packet Switching (SBIR 87-1, Phase 2) prepared for NASA-Greenbelt, Maryland. The primary goal of this research project is to use the results of the SBIR Phase 1 effort to develop a sound, expandable hardware and software router architecture capable of forwarding 25,000 packets per second through the router and passing 300 megabits per second on the router's internal busses. The work being delivered under this contract received its funding from three different sources: the SNIPE/RIG contract (Contract Number F30602-89-C-0014, CDRL Sequence Number A002), the SBIR contract, and Proteon. The SNIPE/RIG and SBIR contracts had many overlapping requirements, which allowed the research done under SNIPE/RIG to be applied to SBIR. Proteon funded all of the work to develop new router interfaces other than FDDI, in addition to funding the productization of the router itself. The router being delivered under SBIR will be a fully product-quality machine. The work done during this contract produced many significant findings and results, summarized here and explained in detail in later sections of this report. The SNIPE/RIG contract was completed. That contract had many overlapping requirements with the SBIR contract, and resulted in the successful demonstration and delivery of a high speed router. The development that took place during the SNIPE/RIG contract produced findings that included the choice of processor and an understanding of the issues surrounding inter processor communications in a multiprocessor environment. Many significant speed enhancements to the router software were made during that time. Under the SBIR contract (and with help from Proteon-funded work), it was found that a single processor router achieved a throughput significantly higher than originally anticipated. For this reason, a single processor router was developed and the final delivery under this contract will include a single processor CNX-500 router. The router and its interface boards (2 FDDIs and 2 dual-ethernets) are all product-quality components.

LANDSAT-D flight segment operations manual. Appendix B: OBC software operations

NASA Technical Reports Server (NTRS)

Talipsky, R.

1981-01-01

The LANDSAT 4 satellite contains two NASA standard spacecraft computers and 65,536 words of memory. Onboard computer software is divided into flight executive and applications processors. Both applications processors and the flight executive use one or more of 67 system tables to obtain variables, constants, and software flags. Output from the software for monitoring operation is via 49 OBC telemetry reports subcommutated in the spacecraft telemetry. Information is provided about the flight software as it is used to control the various spacecraft operations and interpret operational OBC telemetry. Processor function descriptions, processor operation, software constraints, processor system tables, processor telemetry, and processor flow charts are presented.

Managing Power Heterogeneity

NASA Astrophysics Data System (ADS)

Pruhs, Kirk

A particularly important emergent technology is heterogeneous processors (or cores), which many computer architects believe will be the dominant architectural design in the future. The main advantage of a heterogeneous architecture, relative to an architecture of identical processors, is that it allows for the inclusion of processors whose design is specialized for particular types of jobs, and for jobs to be assigned to a processor best suited for that job. Most notably, it is envisioned that these heterogeneous architectures will consist of a small number of high-power high-performance processors for critical jobs, and a larger number of lower-power lower-performance processors for less critical jobs. Naturally, the lower-power processors would be more energy efficient in terms of the computation performed per unit of energy expended, and would generate less heat per unit of computation. For a given area and power budget, heterogeneous designs can give significantly better performance for standard workloads. Moreover, even processors that were designed to be homogeneous, are increasingly likely to be heterogeneous at run time: the dominant underlying cause is the increasing variability in the fabrication process as the feature size is scaled down (although run time faults will also play a role). Since manufacturing yields would be unacceptably low if every processor/core was required to be perfect, and since there would be significant performance loss from derating the entire chip to the functioning of the least functional processor (which is what would be required in order to attain processor homogeneity), some processor heterogeneity seems inevitable in chips with many processors/cores.

Atmospheric Correction Inter-comparison Exercise (ACIX)

NASA Astrophysics Data System (ADS)

Vermote, E.; Doxani, G.; Gascon, F.; Roger, J. C.; Skakun, S.

2017-12-01

The free and open data access policy to Landsat-8 (L-8) and Sentinel-2 (S-2) satellite imagery has encouraged the development of atmospheric correction (AC) approaches for generating Bottom-of-Atmosphere (BOA) products. Several entities have started to generate (or plan to generate in the short term) BOA reflectance products at global scale for L-8 and S-2 missions. To this end, the European Space Agency (ESA) and National Aeronautics and Space Administration (NASA) have initiated an exercise on the inter-comparison of the available AC processors. The results of the exercise are expected to point out the strengths and weaknesses, as well as communalities and discrepancies of various AC processors, in order to suggest and define ways for their further improvement. In particular, 11 atmospheric processors from five different countries participate in ACIX with the aim to inter-compare their performance when applied to L-8 and S-2 data. All the processors should be operational without requiring parametrization when applied on different areas. A protocol describing in details the inter-comparison metrics and the test dataset based on the AERONET sites has been agreed unanimously during the 1st ACIX workshop in June 2016. In particular, a basic and an advanced run of each of the processor were requested in the frame of ACIX, with the aim to draw robust and reliable conclusions on the processors' performance. The protocol also describes the comparison metrics of the aerosol optical thickness and water vapour products of the processors with the corresponding AERONET measurements. Moreover, concerning the surface reflectances, the inter-comparison among the processors is defined, as well as the comparison with the MODIS surface reflectance and with a reference surface reflectance product. Such a reference product will be obtained using the AERONET characterization of the aerosol (size distribution and refractive indices) and an accurate radiative transfer code. The inter-comparison outcomes were presented and discussed among the ACIX participants in the 2nd ACIX workshop, which was held on 11-12 April 2017 (ESRIN/ESA) and a detailed report was compiled. The proposed presentation is an opportunity for the user community to be informed about the ACIX results and conclusions.

Multi-Core Processor Memory Contention Benchmark Analysis Case Study

NASA Technical Reports Server (NTRS)

Simon, Tyler; McGalliard, James

2009-01-01

Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

Automatic maintenance payload on board of a Mexican LEO microsatellite

NASA Astrophysics Data System (ADS)

Vicente-Vivas, Esaú; García-Nocetti, Fabián; Mendieta-Jiménez, Francisco

2006-02-01

Few research institutions from Mexico work together to finalize the integration of a technological demonstration microsatellite called Satex, aiming the launching of the first ever fully designed and manufactured domestic space vehicle. The project is based on technical knowledge gained in previous space experiences, particularly in developing GASCAN automatic experiments for NASA's space shuttle, and in some support obtained from the local team which assembled the México-OSCAR-30 microsatellites. Satex includes three autonomous payloads and a power subsystem, each one with a local microcomputer to provide intelligent and dedicated control. It also contains a flight computer (FC) with a pair of full redundancies. This enables the remote maintenance of processing boards from the ground station. A fourth communications payload depends on the flight computer for control purposes. A fifth payload was decided to be developed for the satellite. It adds value to the available on-board computers and extends the opportunity for a developing country to learn and to generate domestic space technology. Its aim is to provide automatic maintenance capabilities for the most critical on-board computer in order to achieve continuous satellite operations. This paper presents the virtual computer architecture specially developed to provide maintenance capabilities to the flight computer. The architecture is periodically implemented by software with a small amount of physical processors (FC processors) and virtual redundancies (payload processors) to emulate a hybrid redundancy computer. Communications among processors are accomplished over a fault-tolerant LAN. This allows a versatile operating behavior in terms of data communication as well as in terms of distributed fault tolerance. Obtained results, payload validation and reliability results are also presented.

The computational structural mechanics testbed architecture. Volume 1: The language

NASA Technical Reports Server (NTRS)

Felippa, Carlos A.

1988-01-01

This is the first set of five volumes which describe the software architecture for the Computational Structural Mechanics Testbed. Derived from NICE, an integrated software system developed at Lockheed Palo Alto Research Laboratory, the architecture is composed of the command language CLAMP, the command language interpreter CLIP, and the data manager GAL. Volumes 1, 2, and 3 (NASA CR's 178384, 178385, and 178386, respectively) describe CLAMP and CLIP, and the CLIP-processor interface. Volumes 4 and 5 (NASA CR's 178387 and 178388, respectively) describe GAL and its low-level I/O. CLAMP, an acronym for Command Language for Applied Mechanics Processors, is designed to control the flow of execution of processors written for NICE. Volume 1 presents the basic elements of the CLAMP language and is intended for all users.

A High-Throughput Processor for Flight Control Research Using Small UAVs

NASA Technical Reports Server (NTRS)

Klenke, Robert H.; Sleeman, W. C., IV; Motter, Mark A.

2006-01-01

There are numerous autopilot systems that are commercially available for small (<100 lbs) UAVs. However, they all share several key disadvantages for conducting aerodynamic research, chief amongst which is the fact that most utilize older, slower, 8- or 16-bit microcontroller technologies. This paper describes the development and testing of a flight control system (FCS) for small UAV s based on a modern, high throughput, embedded processor. In addition, this FCS platform contains user-configurable hardware resources in the form of a Field Programmable Gate Array (FPGA) that can be used to implement custom, application-specific hardware. This hardware can be used to off-load routine tasks such as sensor data collection, from the FCS processor thereby further increasing the computational throughput of the system.

Simulation analysis of a microcomputer-based, low-cost Omega navigation system

NASA Technical Reports Server (NTRS)

Lilley, R. W.; Salter, R. J., Jr.

1976-01-01

The current status of research on a proposed micro-computer-based, low-cost Omega Navigation System (ONS) is described. The design approach emphasizes minimum hardware, maximum software, and the use of a low-cost, commercially-available microcomputer. Currently under investigation is the implementation of a low-cost navigation processor and its interface with an omega sensor to complete the hardware-based ONS. Sensor processor functions are simulated to determine how many of the sensor processor functions can be handled by innovative software. An input data base of live Omega ground and flight test data was created. The Omega sensor and microcomputer interface modules used to collect the data are functionally described. Automatic synchronization to the Omega transmission pattern is described as an example of the algorithms developed using this data base.

Database interfaces on NASA's heterogeneous distributed database system

NASA Technical Reports Server (NTRS)

Huang, Shou-Hsuan Stephen

1987-01-01

The purpose of Distributed Access View Integrated Database (DAVID) interface module (Module 9: Resident Primitive Processing Package) is to provide data transfer between local DAVID systems and resident Data Base Management Systems (DBMSs). The result of current research is summarized. A detailed description of the interface module is provided. Several Pascal templates were constructed. The Resident Processor program was also developed. Even though it is designed for the Pascal templates, it can be modified for templates in other languages, such as C, without much difficulty. The Resident Processor itself can be written in any programming language. Since Module 5 routines are not ready yet, there is no way to test the interface module. However, simulation shows that the data base access programs produced by the Resident Processor do work according to the specifications.

Moving target, distributed, real-time simulation using Ada

NASA Technical Reports Server (NTRS)

Collins, W. R.; Feyock, S.; King, L. A.; Morell, L. J.

1985-01-01

Research on a precompiler solution is described for the moving target compiler problem encountered when trying to run parallel simulation algorithms on several microcomputers. The precompiler is under development at NASA-Lewis for simulating jet engines. Since the behavior of any component of a jet engine, e.g., the fan inlet, rear duct, forward sensor, etc., depends on the previous behaviors and not the current behaviors of other components, the behaviors can be modeled on different processors provided the outputs of the processors reach other processors in appropriate time intervals. The simulator works in compute and transfer modes. The Ada procedure sets for the behaviors of different components are divided up and routed by the precompiler, which essentially receives a multitasking program. The subroutines are synchronized after each computation cycle.

The computational structural mechanics testbed architecture. Volume 2: Directives

NASA Technical Reports Server (NTRS)

Felippa, Carlos A.

1989-01-01

This is the second of a set of five volumes which describe the software architecture for the Computational Structural Mechanics Testbed. Derived from NICE, an integrated software system developed at Lockheed Palo Alto Research Laboratory, the architecture is composed of the command language (CLAMP), the command language interpreter (CLIP), and the data manager (GAL). Volumes 1, 2, and 3 (NASA CR's 178384, 178385, and 178386, respectively) describe CLAMP and CLIP and the CLIP-processor interface. Volumes 4 and 5 (NASA CR's 178387 and 178388, respectively) describe GAL and its low-level I/O. CLAMP, an acronym for Command Language for Applied Mechanics Processors, is designed to control the flow of execution of processors written for NICE. Volume 2 describes the CLIP directives in detail. It is intended for intermediate and advanced users.

Formal design and verification of a reliable computing platform for real-time control. Phase 1: Results

NASA Technical Reports Server (NTRS)

Divito, Ben L.; Butler, Ricky W.; Caldwell, James L.

1990-01-01

A high-level design is presented for a reliable computing platform for real-time control applications. Design tradeoffs and analyses related to the development of the fault-tolerant computing platform are discussed. The architecture is formalized and shown to satisfy a key correctness property. The reliable computing platform uses replicated processors and majority voting to achieve fault tolerance. Under the assumption of a majority of processors working in each frame, it is shown that the replicated system computes the same results as a single processor system not subject to failures. Sufficient conditions are obtained to establish that the replicated system recovers from transient faults within a bounded amount of time. Three different voting schemes are examined and proved to satisfy the bounded recovery time conditions.

Emerging Radio and Manet Technology Study: Research Support for a Survey of State-of-the-art Commercial and Military Hardware/Software for Mobile Ad Hoc Networks

DTIC Science & Technology

2014-10-01

44 Table 19: Raspberry Pi Information...boards – These are single board devices targeted to education and embedding, the best known being the Raspberry Pi ; and 3. Development boards – These...popular, as it has high performance processor (perhaps 4 times the power of a Raspberry Pi ) with dual core processors running at 1.6 GHz and the cost is

Multicore: Fallout from a Computing Evolution

ScienceCinema

Yelick, Kathy [Director, NERSC

2017-12-09

July 22, 2008 Berkeley Lab lecture: Parallel computing used to be reserved for big science and engineering projects, but in two years that's all changed. Even laptops and hand-helds use parallel processors. Unfortunately, the software hasn't kept pace. Kathy Yelick, Director of the National Energy Research Scientific Computing Center at Berkeley Lab, describes the resulting chaos and the computing community's efforts to develop exciting applications that take advantage of tens or hundreds of processors on a single chip.

ROSE::FTTransform - A Source-to-Source Translation Framework for Exascale Fault-Tolerance Research

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lidman, J; Quinlan, D; Liao, C

2012-03-26

Exascale computing systems will require sufficient resilience to tolerate numerous types of hardware faults while still assuring correct program execution. Such extreme-scale machines are expected to be dominated by processors driven at lower voltages (near the minimum 0.5 volts for current transistors). At these voltage levels, the rate of transient errors increases dramatically due to the sensitivity to transient and geographically localized voltage drops on parts of the processor chip. To achieve power efficiency, these processors are likely to be streamlined and minimal, and thus they cannot be expected to handle transient errors entirely in hardware. Here we present anmore » open, compiler-based framework to automate the armoring of High Performance Computing (HPC) software to protect it from these types of transient processor errors. We develop an open infrastructure to support research work in this area, and we define tools that, in the future, may provide more complete automated and/or semi-automated solutions to support software resiliency on future exascale architectures. Results demonstrate that our approach is feasible, pragmatic in how it can be separated from the software development process, and reasonably efficient (0% to 30% overhead for the Jacobi iteration on common hardware; and 20%, 40%, 26%, and 2% overhead for a randomly selected subset of benchmarks from the Livermore Loops [1]).« less

Parallel processors and nonlinear structural dynamics algorithms and software

NASA Technical Reports Server (NTRS)

Belytschko, Ted

1990-01-01

Techniques are discussed for the implementation and improvement of vectorization and concurrency in nonlinear explicit structural finite element codes. In explicit integration methods, the computation of the element internal force vector consumes the bulk of the computer time. The program can be efficiently vectorized by subdividing the elements into blocks and executing all computations in vector mode. The structuring of elements into blocks also provides a convenient way to implement concurrency by creating tasks which can be assigned to available processors for evaluation. The techniques were implemented in a 3-D nonlinear program with one-point quadrature shell elements. Concurrency and vectorization were first implemented in a single time step version of the program. Techniques were developed to minimize processor idle time and to select the optimal vector length. A comparison of run times between the program executed in scalar, serial mode and the fully vectorized code executed concurrently using eight processors shows speed-ups of over 25. Conjugate gradient methods for solving nonlinear algebraic equations are also readily adapted to a parallel environment. A new technique for improving convergence properties of conjugate gradients in nonlinear problems is developed in conjunction with other techniques such as diagonal scaling. A significant reduction in the number of iterations required for convergence is shown for a statically loaded rigid bar suspended by three equally spaced springs.

SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Optoelectronic processors with scanning CCD photodetectors

NASA Astrophysics Data System (ADS)

Esepkina, N. A.; Lavrov, A. P.; Anan'ev, M. N.; Blagodarnyi, V. S.; Ivanov, S. I.; Mansyrev, M. I.; Molodyakov, S. A.

1995-10-01

Two new types of optoelectronic radio-signal processors were investigated. Charge-coupled device (CCD) photodetectors are used in these processors under continuous scanning conditions, i.e. in a time delay and storage mode. One of these processors is based on a CCD photodetector array with a reference-signal amplitude transparency and the other is an adaptive acousto-optical signal processor with linear frequency modulation. The processor with the transparency performs multichannel discrete—analogue convolution of an input signal with a corresponding kernel of the transformation determined by the transparency. If a light source is an array of light-emitting diodes of special (stripe) geometry, the optical stages of the processor can be made from optical fibre components and the whole processor then becomes a rigid 'sandwich' (a compact hybrid optoelectronic microcircuit). A report is given also of a study of a prototype processor with optical fibre components for the reception of signals from a system with antenna aperture synthesis, which forms a radio image of the Earth.

System and method for representing and manipulating three-dimensional objects on massively parallel architectures

DOEpatents

Karasick, M.S.; Strip, D.R.

1996-01-30

A parallel computing system is described that comprises a plurality of uniquely labeled, parallel processors, each processor capable of modeling a three-dimensional object that includes a plurality of vertices, faces and edges. The system comprises a front-end processor for issuing a modeling command to the parallel processors, relating to a three-dimensional object. Each parallel processor, in response to the command and through the use of its own unique label, creates a directed-edge (d-edge) data structure that uniquely relates an edge of the three-dimensional object to one face of the object. Each d-edge data structure at least includes vertex descriptions of the edge and a description of the one face. As a result, each processor, in response to the modeling command, operates upon a small component of the model and generates results, in parallel with all other processors, without the need for processor-to-processor intercommunication. 8 figs.

Shared performance monitor in a multiprocessor system

DOEpatents

Chiu, George; Gara, Alan G.; Salapura, Valentina

2012-07-24

A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU comprises: a plurality of performance counters each for counting signals representing occurrences of events from one or more the plurality of processor units in the multiprocessor system; and, a plurality of input devices for receiving the event signals from one or more processor devices of the plurality of processor units, the plurality of input devices programmable to select event signals for receipt by one or more of the plurality of performance counters for counting, wherein the PMU is shared between multiple processing units, or within a group of processors in the multiprocessing system. The PMU is further programmed to monitor event signals issued from non-processor devices.

A modular BLSS simulation model

NASA Technical Reports Server (NTRS)

Rummel, John D.; Volk, Tyler

1987-01-01

A bioregenerative life support system (BLSS) for extraterrestrial use will be faced with coordination problems more acute than those in any ecosystem found on Earth. A related problem in BLSS design is providing an interface between the various life support processors, one that will allow for their coordination while still allowing for system expansion. A modular model is presented of a BLSS that interfaces system processors only with the material storage reservoirs, allowing those reservoirs to act as the principal buffers in the system and thus minimizing difficulties with processor coordination. The modular nature of the model allows independent development of the detailed submodels that exist within the model framework. Using this model, BLSS dynamics were investigated under normal conditions and under various failure modes. Partial and complete failures of various components, such as the waste processors or the plants themselves, drive transient responses in the model system, allowing the examination of the effectiveness of the system reservoirs as buffers. The results from simulations help to determine control strategies and BLSS design requirements. An evolved version could be used as an interactive control aid in a future BLSS.

Parallel Directionally Split Solver Based on Reformulation of Pipelined Thomas Algorithm

NASA Technical Reports Server (NTRS)

Povitsky, A.

1998-01-01

In this research an efficient parallel algorithm for 3-D directionally split problems is developed. The proposed algorithm is based on a reformulated version of the pipelined Thomas algorithm that starts the backward step computations immediately after the completion of the forward step computations for the first portion of lines This algorithm has data available for other computational tasks while processors are idle from the Thomas algorithm. The proposed 3-D directionally split solver is based on the static scheduling of processors where local and non-local, data-dependent and data-independent computations are scheduled while processors are idle. A theoretical model of parallelization efficiency is used to define optimal parameters of the algorithm, to show an asymptotic parallelization penalty and to obtain an optimal cover of a global domain with subdomains. It is shown by computational experiments and by the theoretical model that the proposed algorithm reduces the parallelization penalty about two times over the basic algorithm for the range of the number of processors (subdomains) considered and the number of grid nodes per subdomain.

Noise Analysis of Spatial Phase coding in analog Acoustooptic Processors

NASA Technical Reports Server (NTRS)

Gary, Charles K.; Lum, Henry, Jr. (Technical Monitor)

1994-01-01

Optical beams can carry information in their amplitude and phase; however, optical analog numerical calculators such as an optical matrix processor use incoherent light to achieve linear operation. Thus, the phase information is lost and only the magnitude can be used. This limits such processors to the representation of positive real numbers. Many systems have been devised to overcome this deficit through the use of digital number representations, but they all operate at a greatly reduced efficiency in contrast to analog systems. The most widely accepted method to achieve sign coding in analog optical systems has been the use of an offset for the zero level. Unfortunately, this results in increased noise sensitivity for small numbers. In this paper, we examine the use of spatially coherent sign coding in acoustooptical processors, a method first developed for digital calculations by D. V. Tigin. This coding technique uses spatial coherence for the representation of signed numbers, while temporal incoherence allows for linear analog processing of the optical information. We show how spatial phase coding reduces noise sensitivity for signed analog calculations.

Parallel text rendering by a PostScript interpreter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kritskii, S.P.; Zastavnoi, B.A.

1994-11-01

The most radical method of increasing the performance of devices controlled by PostScript interpreters may be the use of multiprocessor controllers. This paper presents a method for parallelizing the operation of a PostScript interpreter for rendering text. The proposed method is based on decomposition of the outlines of letters into horizontal strips covering equal areas. The subroutines thus obtained are distributed to the processors in a network and then filled in by conventional sequential algorithms. A special algorithm has been developed for dividing the outlines of characters into subroutines so that each may be colored independently of the others. Themore » algorithm uses special estimates for estimating the correct partition so that the corresponding outlines are divided into horizontal strips. A method is presented for finding such estimates. Two different processing approaches are presented. In the first, one of the processors performs the decomposition of the outlines and distributes the strips to the remaining processors, which are responsible for the rendering. In the second approach, the decomposition process is itself distributed among the processors in the network.« less

Control Software for Advanced Video Guidance Sensor

NASA Technical Reports Server (NTRS)

Howard, Richard T.; Book, Michael L.; Bryan, Thomas C.

2006-01-01

Embedded software has been developed specifically for controlling an Advanced Video Guidance Sensor (AVGS). A Video Guidance Sensor is an optoelectronic system that provides guidance for automated docking of two vehicles. Such a system includes pulsed laser diodes and a video camera, the output of which is digitized. From the positions of digitized target images and known geometric relationships, the relative position and orientation of the vehicles are computed. The present software consists of two subprograms running in two processors that are parts of the AVGS. The subprogram in the first processor receives commands from an external source, checks the commands for correctness, performs commanded non-image-data-processing control functions, and sends image data processing parts of commands to the second processor. The subprogram in the second processor processes image data as commanded. Upon power-up, the software performs basic tests of functionality, then effects a transition to a standby mode. When a command is received, the software goes into one of several operational modes (e.g. acquisition or tracking). The software then returns, to the external source, the data appropriate to the command.

Vehicle safety telemetry for automated highways

NASA Technical Reports Server (NTRS)

Hansen, G. R.

1977-01-01

The emphasis in current, automatic vehicle testing and diagnosis is primarily centered on the proper operation of the engine. Lateral and longitudinal guidance technologies, including speed control and headway sensing for collision avoidance, are reviewed. The principal guidance technique remains the buried wire. Speed control and headway sensing, even though they show the same basic elements in braking and fuel systems, are proceeding independently. The applications of on-board electronic and microprocessor techniques were investigated; each application (emission control, spark advance, or anti-slip braking) is being treated as an independent problem is proposed. A unified bus system of distributed processors for accomplishing the various functions and testing required for vehicles equipped to use automated highways.

Implementation of kernels on the Maestro processor

NASA Astrophysics Data System (ADS)

Suh, Jinwoo; Kang, D. I. D.; Crago, S. P.

Currently, most microprocessors use multiple cores to increase performance while limiting power usage. Some processors use not just a few cores, but tens of cores or even 100 cores. One such many-core microprocessor is the Maestro processor, which is based on Tilera's TILE64 processor. The Maestro chip is a 49-core, general-purpose, radiation-hardened processor designed for space applications. The Maestro processor, unlike the TILE64, has a floating point unit (FPU) in each core for improved floating point performance. The Maestro processor runs at 342 MHz clock frequency. On the Maestro processor, we implemented several widely used kernels: matrix multiplication, vector add, FIR filter, and FFT. We measured and analyzed the performance of these kernels. The achieved performance was up to 5.7 GFLOPS, and the speedup compared to single tile was up to 49 using 49 tiles.

Ordering of guarded and unguarded stores for no-sync I/O

DOEpatents

Gara, Alan; Ohmacht, Martin

2013-06-25

A parallel computing system processes at least one store instruction. A first processor core issues a store instruction. A first queue, associated with the first processor core, stores the store instruction. A second queue, associated with a first local cache memory device of the first processor core, stores the store instruction. The first processor core updates first data in the first local cache memory device according to the store instruction. The third queue, associated with at least one shared cache memory device, stores the store instruction. The first processor core invalidates second data, associated with the store instruction, in the at least one shared cache memory. The first processor core invalidates third data, associated with the store instruction, in other local cache memory devices of other processor cores. The first processor core flushing only the first queue.

Fast particles identification in programmable form at level-0 trigger by means of the 3D-Flow system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Crosetto, Dario B.

1998-10-30

The 3D-Flow Processor system is a new, technology-independent concept in very fast, real-time system architectures. Based on either an FPGA or an ASIC implementation, it can address, in a fully programmable manner, applications where commercially available processors would fail because of throughput requirements. Possible applications include filtering-algorithms (pattern recognition) from the input of multiple sensors, as well as moving any input validated by these filtering-algorithms to a single output channel. Both operations can easily be implemented on a 3D-Flow system to achieve a real-time processing system with a very short lag time. This system can be built either with off-the-shelfmore » FPGAs or, for higher data rates, with CMOS chips containing 4 to 16 processors each. The basic building block of the system, a 3D-Flow processor, has been successfully designed in VHDL code written in ''Generic HDL'' (mostly made of reusable blocks that are synthesizable in different technologies, or FPGAs), to produce a netlist for a four-processor ASIC featuring 0.35 micron CBA (Ceil Base Array) technology at 3.3 Volts, 884 mW power dissipation at 60 MHz and 63.75 mm sq. die size. The same VHDL code has been targeted to three FPGA manufacturers (Altera EPF10K250A, ORCA-Lucent Technologies 0R3T165 and Xilinx XCV1000). A complete set of software tools, the 3D-Flow System Manager, equally applicable to ASIC or FPGA implementations, has been produced to provide full system simulation, application development, real-time monitoring, and run-time fault recovery. Today's technology can accommodate 16 processors per chip in a medium size die, at a cost per processor of less than $5 based on the current silicon die/size technology cost.« less

NASA Tech Briefs, January 2005

NASA Technical Reports Server (NTRS)

2005-01-01

Topics covered include: Fiber-Optic Sensor Would Monitor Growth of Polymer Film; Sensors for Pointing Moving Instruments Toward Each Other; Pd/CeO2/SiC Chemical Sensors; Microparticle Flow Sensor; Scattering-Type Surface-Plasmon-Resonance Biosensors; Diode-Laser-Based Spectrometer for Sensing Gases; Improved Cathode Structure for a Direct Methanol Fuel Cell; X-Band, 17-Watt Solid-State Power Amplifier; Improved Anode for a Direct Methanol Fuel Cell; Tools for Designing and Analyzing Structures; Interactive Display of Scenes with Annotations; Solving Common Mathematical Problems; Tools for Basic Statistical Analysis; Program Calculates Forces in Bolted Structural Joints; Integrated Structural Analysis and Test Program; Molybdate Coatings for Protecting Aluminum Against Corrosion; Synthesizing Diamond from Liquid Feedstock; Modifying Silicates for Better Dispersion in Nanocomposites; Powder-Collection System for Ultrasonic/Sonic Drill/Corer; Semiautomated, Reproducible Batch Processing of Soy; Hydrogen Peroxide Enhances Removal of NOx from Flue Gases; Subsurface Ice Probe; Real-Time Simulation of Aeroheating of the Hyper-X Airplane; Using Laser-Induced Incandescence To Measure Soot in Exhaust; Method of Real-Time Principal-Component Analysis; Insect-Inspired Flight Control for Unmanned Aerial Vehicles; Domain Compilation for Embedded Real-Time Planning; Semantic Metrics for Analysis of Software; Simulation of Laser Cooling and Trapping in Engineering Applications; Large Fluvial Fans and Exploration for Hydrocarbons; Doping-Induced Interband Gain in InAs/AlSb Quantum Wells; Development of Software for a Lidar-Altimeter Processor; Upgrading the Space Shuttle Caution and Warning System; and Fractal Reference Signals in Pulse-Width Modulation.

Electrochemical sensing using voltage-current time differential

DOE Office of Scientific and Technical Information (OSTI.GOV)

Woo, Leta Yar-Li; Glass, Robert Scott; Fitzpatrick, Joseph Jay

2017-02-28

A device for signal processing. The device includes a signal generator, a signal detector, and a processor. The signal generator generates an original waveform. The signal detector detects an affected waveform. The processor is coupled to the signal detector. The processor receives the affected waveform from the signal detector. The processor also compares at least one portion of the affected waveform with the original waveform. The processor also determines a difference between the affected waveform and the original waveform. The processor also determines a value corresponding to a unique portion of the determined difference between the original and affected waveforms.more » The processor also outputs the determined value.« less

Accuracy requirements of optical linear algebra processors in adaptive optics imaging systems

NASA Technical Reports Server (NTRS)

Downie, John D.; Goodman, Joseph W.

1989-01-01

The accuracy requirements of optical processors in adaptive optics systems are determined by estimating the required accuracy in a general optical linear algebra processor (OLAP) that results in a smaller average residual aberration than that achieved with a conventional electronic digital processor with some specific computation speed. Special attention is given to an error analysis of a general OLAP with regard to the residual aberration that is created in an adaptive mirror system by the inaccuracies of the processor, and to the effect of computational speed of an electronic processor on the correction. Results are presented on the ability of an OLAP to compete with a digital processor in various situations.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Burge, S.W.

This report describes the FORCE2 flow program input, output, and the graphical post-processor. The manual describes the steps for creating the model, executing the programs and processing the results into graphical form. The FORCE2 post-processor was developed as an interactive program written in FORTRAN-77. It uses the Graphical Kernel System (GKS) graphics standard recently adopted by International Organization for Standardization, ISO, and American National Standards Institute, ANSI, and, therefore, can be used with many terminals. The post-processor vas written with Calcomp subroutine calls and is compatible with Tektkonix terminals and Calcomp and Nicolet pen plotters. B&W has been developing themore » FORCE2 code as a general-purpose tool for flow analysis of B&W equipment. The version of FORCE2 described in this manual was developed under the sponsorship of ASEA-Babcock as part of their participation in the joint R&D venture, ``Erosion of FBC Heat Transfer Tubes,`` and is applicable to the analyses of bubbling fluid beds. This manual is the principal documentation for program usage and is segmented into several sections to facilitate usage. In Section 2.0 the program is described, including assumptions, capabilities, limitations and uses, program status and location, related programs and program hardware and software requirements. Section 3.0 is a quick user`s reference guide for preparing input, executing FORCE2, and using the post-processor. Section 4.0 is a detailed description of the FORCE2 input. In Section 5.0, FORCE2 output is summarized. Section 6.0 contains a sample application, and Section 7.0 is a detailed reference guide.« less

Analysis on burnup step effect for evaluating reactor criticality and fuel breeding ratio

DOE Office of Scientific and Technical Information (OSTI.GOV)

Saputra, Geby; Purnama, Aditya Rizki; Permana, Sidik

Criticality condition of the reactors is one of the important factors for evaluating reactor operation and nuclear fuel breeding ratio is another factor to show nuclear fuel sustainability. This study analyzes the effect of burnup steps and cycle operation step for evaluating the criticality condition of the reactor as well as the performance of nuclear fuel breeding or breeding ratio (BR). Burnup step is performed based on a day step analysis which is varied from 10 days up to 800 days and for cycle operation from 1 cycle up to 8 cycles reactor operations. In addition, calculation efficiency based onmore » the variation of computer processors to run the analysis in term of time (time efficiency in the calculation) have been also investigated. Optimization method for reactor design analysis which is used a large fast breeder reactor type as a reference case was performed by adopting an established reactor design code of JOINT-FR. The results show a criticality condition becomes higher for smaller burnup step (day) and for breeding ratio becomes less for smaller burnup step (day). Some nuclides contribute to make better criticality when smaller burnup step due to individul nuclide half-live. Calculation time for different burnup step shows a correlation with the time consuming requirement for more details step calculation, although the consuming time is not directly equivalent with the how many time the burnup time step is divided.« less

Fast 2D FWI on a multi and many-cores workstation.

NASA Astrophysics Data System (ADS)

Thierry, Philippe; Donno, Daniela; Noble, Mark

2014-05-01

Following the introduction of x86 co-processors (Xeon Phi) and the performance increase of standard 2-socket workstations using the latest 12 cores E5-v2 x86-64 CPU, we present here a MPI + OpenMP implementation of an acoustic 2D FWI (full waveform inversion) code which simultaneously runs on the CPUs and on the co-processors installed in a workstation. The main advantage of running a 2D FWI on a workstation is to be able to quickly evaluate new features such as more complicated wave equations, new cost functions, finite-difference stencils or boundary conditions. Since the co-processor is made of 61 in-order x86 cores, each of them having up to 4 threads, this many-core can be seen as a shared memory SMP (symmetric multiprocessing) machine with its own IP address. Depending on the vendor, a single workstation can handle several co-processors making the workstation as a personal cluster under the desk. The original Fortran 90 CPU version of the 2D FWI code is just recompiled to get a Xeon Phi x86 binary. This multi and many-core configuration uses standard compilers and associated MPI as well as math libraries under Linux; therefore, the cost of code development remains constant, while improving computation time. We choose to implement the code with the so-called symmetric mode to fully use the capacity of the workstation, but we also evaluate the scalability of the code in native mode (i.e running only on the co-processor) thanks to the Linux ssh and NFS capabilities. Usual care of optimization and SIMD vectorization is used to ensure optimal performances, and to analyze the application performances and bottlenecks on both platforms. The 2D FWI implementation uses finite-difference time-domain forward modeling and a quasi-Newton (with L-BFGS algorithm) optimization scheme for the model parameters update. Parallelization is achieved through standard MPI shot gathers distribution and OpenMP for domain decomposition within the co-processor. Taking advantage of the 16 GB of memory available on the co-processor we are able to keep wavefields in memory to achieve the gradient computation by cross-correlation of forward and back-propagated wavefields needed by our time-domain FWI scheme, without heavy traffic on the i/o subsystem and PCIe bus. In this presentation we will also review some simple methodologies to determine performance expectation compared to real performances in order to get optimization effort estimation before starting any huge modification or rewriting of research codes. The key message is the ease of use and development of this hybrid configuration to reach not the absolute peak performance value but the optimal one that ensures the best balance between geophysical and computer developments.

Improved multi-stage neonatal seizure detection using a heuristic classifier and a data-driven post-processor.

PubMed

Ansari, A H; Cherian, P J; Dereymaeker, A; Matic, V; Jansen, K; De Wispelaere, L; Dielman, C; Vervisch, J; Swarte, R M; Govaert, P; Naulaers, G; De Vos, M; Van Huffel, S

2016-09-01

After identifying the most seizure-relevant characteristics by a previously developed heuristic classifier, a data-driven post-processor using a novel set of features is applied to improve the performance. The main characteristics of the outputs of the heuristic algorithm are extracted by five sets of features including synchronization, evolution, retention, segment, and signal features. Then, a support vector machine and a decision making layer remove the falsely detected segments. Four datasets including 71 neonates (1023h, 3493 seizures) recorded in two different university hospitals, are used to train and test the algorithm without removing the dubious seizures. The heuristic method resulted in a false alarm rate of 3.81 per hour and good detection rate of 88% on the entire test databases. The post-processor, effectively reduces the false alarm rate by 34% while the good detection rate decreases by 2%. This post-processing technique improves the performance of the heuristic algorithm. The structure of this post-processor is generic, improves our understanding of the core visually determined EEG features of neonatal seizures and is applicable for other neonatal seizure detectors. The post-processor significantly decreases the false alarm rate at the expense of a small reduction of the good detection rate. Copyright © 2016 International Federation of Clinical Neurophysiology. Published by Elsevier Ireland Ltd. All rights reserved.

Gigaflop performance on a CRAY-2: Multitasking a computational fluid dynamics application

NASA Technical Reports Server (NTRS)

Tennille, Geoffrey M.; Overman, Andrea L.; Lambiotte, Jules J.; Streett, Craig L.

1991-01-01

The methodology is described for converting a large, long-running applications code that executed on a single processor of a CRAY-2 supercomputer to a version that executed efficiently on multiple processors. Although the conversion of every application is different, a discussion of the types of modification used to achieve gigaflop performance is included to assist others in the parallelization of applications for CRAY computers, especially those that were developed for other computers. An existing application, from the discipline of computational fluid dynamics, that had utilized over 2000 hrs of CPU time on CRAY-2 during the previous year was chosen as a test case to study the effectiveness of multitasking on a CRAY-2. The nature of dominant calculations within the application indicated that a sustained computational rate of 1 billion floating-point operations per second, or 1 gigaflop, might be achieved. The code was first analyzed and modified for optimal performance on a single processor in a batch environment. After optimal performance on a single CPU was achieved, the code was modified to use multiple processors in a dedicated environment. The results of these two efforts were merged into a single code that had a sustained computational rate of over 1 gigaflop on a CRAY-2. Timings and analysis of performance are given for both single- and multiple-processor runs.

Modeling heterogeneous processor scheduling for real time systems

NASA Technical Reports Server (NTRS)

Leathrum, J. F.; Mielke, R. R.; Stoughton, J. W.

1994-01-01

A new model is presented to describe dataflow algorithms implemented in a multiprocessing system. Called the resource/data flow graph (RDFG), the model explicitly represents cyclo-static processor schedules as circuits of processor arcs which reflect the order that processors execute graph nodes. The model also allows the guarantee of meeting hard real-time deadlines. When unfolded, the model identifies statically the processor schedule. The model therefore is useful for determining the throughput and latency of systems with heterogeneous processors. The applicability of the model is demonstrated using a space surveillance algorithm.

SDDL- SOFTWARE DESIGN AND DOCUMENTATION LANGUAGE

NASA Technical Reports Server (NTRS)

Kleine, H.

1994-01-01

Effective, efficient communication is an essential element of the software development process. The Software Design and Documentation Language (SDDL) provides an effective communication medium to support the design and documentation of complex software applications. SDDL supports communication between all the members of a software design team and provides for the production of informative documentation on the design effort. Even when an entire development task is performed by a single individual, it is important to explicitly express and document communication between the various aspects of the design effort including concept development, program specification, program development, and program maintenance. SDDL ensures that accurate documentation will be available throughout the entire software life cycle. SDDL offers an extremely valuable capability for the design and documentation of complex programming efforts ranging from scientific and engineering applications to data management and business sytems. Throughout the development of a software design, the SDDL generated Software Design Document always represents the definitive word on the current status of the ongoing, dynamic design development process. The document is easily updated and readily accessible in a familiar, informative form to all members of the development team. This makes the Software Design Document an effective instrument for reconciling misunderstandings and disagreements in the development of design specifications, engineering support concepts, and the software design itself. Using the SDDL generated document to analyze the design makes it possible to eliminate many errors that might not be detected until coding and testing is attempted. As a project management aid, the Software Design Document is useful for monitoring progress and for recording task responsibilities. SDDL is a combination of language, processor, and methodology. The SDDL syntax consists of keywords to invoke design structures and a collection of directives which control processor actions. The designer has complete control over the choice of keywords, commanding the capabilities of the processor in a way which is best suited to communicating the intent of the design. The SDDL processor translates the designer's creative thinking into an effective document for communication. The processor performs as many automatic functions as possible, thereby freeing the designer's energy for the creative effort. Document formatting includes graphical highlighting of structure logic, accentuation of structure escapes and module invocations, logic error detection, and special handling of title pages and text segments. The SDDL generated document contains software design summary information including module invocation hierarchy, module cross reference, and cross reference tables of user selected words or phrases appearing in the document. The basic forms of the methodology are module and block structures and the module invocation statement. A design is stated in terms of modules that represent problem abstractions which are complete and independent enough to be treated as separate problem entities. Blocks are lower-level structures used to build the modules. Both kinds of structures may have an initiator part, a terminator part, an escape segment, or a substructure. The SDDL processor is written in PASCAL for batch execution on a DEC VAX series computer under VMS. SDDL was developed in 1981 and last updated in 1984.

Testing and operating a multiprocessor chip with processor redundancy

DOEpatents

Bellofatto, Ralph E; Douskey, Steven M; Haring, Rudolf A; McManus, Moyra K; Ohmacht, Martin; Schmunkamp, Dietmar; Sugavanam, Krishnan; Weatherford, Bryan J

2014-10-21

A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Reed, D.A.; Grunwald, D.C.

The spectrum of parallel processor designs can be divided into three sections according to the number and complexity of the processors. At one end there are simple, bit-serial processors. Any one of thee processors is of little value, but when it is coupled with many others, the aggregate computing power can be large. This approach to parallel processing can be likened to a colony of termites devouring a log. The most notable examples of this approach are the NASA/Goodyear Massively Parallel Processor, which has 16K one-bit processors, and the Thinking Machines Connection Machine, which has 64K one-bit processors. At themore » other end of the spectrum, a small number of processors, each built using the fastest available technology and the most sophisticated architecture, are combined. An example of this approach is the Cray X-MP. This type of parallel processing is akin to four woodmen attacking the log with chainsaws.« less

Parallel conjugate gradient algorithms for manipulator dynamic simulation

NASA Technical Reports Server (NTRS)

Fijany, Amir; Scheld, Robert E.

1989-01-01

Parallel conjugate gradient algorithms for the computation of multibody dynamics are developed for the specialized case of a robot manipulator. For an n-dimensional positive-definite linear system, the Classical Conjugate Gradient (CCG) algorithms are guaranteed to converge in n iterations, each with a computation cost of O(n); this leads to a total computational cost of O(n sq) on a serial processor. A conjugate gradient algorithms is presented that provide greater efficiency using a preconditioner, which reduces the number of iterations required, and by exploiting parallelism, which reduces the cost of each iteration. Two Preconditioned Conjugate Gradient (PCG) algorithms are proposed which respectively use a diagonal and a tridiagonal matrix, composed of the diagonal and tridiagonal elements of the mass matrix, as preconditioners. Parallel algorithms are developed to compute the preconditioners and their inversions in O(log sub 2 n) steps using n processors. A parallel algorithm is also presented which, on the same architecture, achieves the computational time of O(log sub 2 n) for each iteration. Simulation results for a seven degree-of-freedom manipulator are presented. Variants of the proposed algorithms are also developed which can be efficiently implemented on the Robot Mathematics Processor (RMP).