Scalability of carbon-nanotube-based thin film transistors for flexible electronic devices manufactured using an all roll-to-roll gravure printing system

PubMed Central

Koo, Hyunmo; Lee, Wookyu; Choi, Younchang; Sun, Junfeng; Bak, Jina; Noh, Jinsoo; Subramanian, Vivek; Azuma, Yasuo; Majima, Yutaka; Cho, Gyoujin

2015-01-01

To demonstrate that roll-to-roll (R2R) gravure printing is a suitable advanced manufacturing method for flexible thin film transistor (TFT)-based electronic circuits, three different nanomaterial-based inks (silver nanoparticles, BaTiO3 nanoparticles and single-walled carbon nanotubes (SWNTs)) were selected and optimized to enable the realization of fully printed SWNT-based TFTs (SWNT-TFTs) on 150-m-long rolls of 0.25-m-wide poly(ethylene terephthalate) (PET). SWNT-TFTs with 5 different channel lengths, namely, 30, 80, 130, 180, and 230 μm, were fabricated using a printing speed of 8 m/min. These SWNT-TFTs were characterized, and the obtained electrical parameters were related to major mechanical factors such as web tension, registration accuracy, impression roll pressure and printing speed to determine whether these mechanical factors were the sources of the observed device-to-device variations. By utilizing the electrical parameters from the SWNT-TFTs, a Monte Carlo simulation for a 1-bit adder circuit, as a reference, was conducted to demonstrate that functional circuits with reasonable complexity can indeed be manufactured using R2R gravure printing. The simulation results suggest that circuits with complexity, similar to the full adder circuit, can be printed with a 76% circuit yield if threshold voltage (Vth) variations of less than 30% can be maintained. PMID:26411839

Single instruction computer architecture and its application in image processing

NASA Astrophysics Data System (ADS)

Laplante, Phillip A.

1992-03-01

A single processing computer system using only half-adder circuits is described. In addition, it is shown that only a single hard-wired instruction is needed in the control unit to obtain a complete instruction set for this general purpose computer. Such a system has several advantages. First it is intrinsically a RISC machine--in fact the 'ultimate RISC' machine. Second, because only a single type of logic element is employed the entire computer system can be easily realized on a single, highly integrated chip. Finally, due to the homogeneous nature of the computer's logic elements, the computer has possible implementations as an optical or chemical machine. This in turn suggests possible paradigms for neural computing and artificial intelligence. After showing how we can implement a full-adder, min, max and other operations using the half-adder, we use an array of such full-adders to implement the dilation operation for two black and white images. Next we implement the erosion operation of two black and white images using a relative complement function and the properties of erosion and dilation. This approach was inspired by papers by van der Poel in which a single instruction is used to furnish a complete set of general purpose instructions and by Bohm- Jacopini where it is shown that any problem can be solved using a Turing machine with one entry and one exit.

Development of an optical parallel logic device and a half-adder circuit for digital optical processing

NASA Technical Reports Server (NTRS)

Athale, R. A.; Lee, S. H.

1978-01-01

The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.

ARC length control for plasma welding

NASA Technical Reports Server (NTRS)

Iceland, William F. (Inventor)

1988-01-01

A control system to be used with a plasma arc welding apparatus is disclosed. The plasma arc welding apparatus includes a plasma arc power supply, a contactor, and an electrode assembly for moving the electrode relative to a work piece. The electrode assembly is raised or lowered by a drive motor. The present apparatus includes a plasma arc adapter connected across the power supply to measure the voltage across the plasma arc. The plasma arc adapter forms a dc output signal input to a differential amplifier. A second input is defined by an adjustable resistor connected to a dc voltage supply to permit operator control. The differential amplifier forms an output difference signal provided to an adder circuit. The adder circuit then connects with a power amplifier which forms the driving signal for the motor. In addition, the motor connects to a tachometor which forms a feedback signal delivered to the adder to provide damping, therby avoiding servo loop overshoot.

Low-latency optical parallel adder based on a binary decision diagram with wavelength division multiplexing scheme

NASA Astrophysics Data System (ADS)

Shinya, A.; Ishihara, T.; Inoue, K.; Nozaki, K.; Kita, S.; Notomi, M.

2018-02-01

We propose an optical parallel adder based on a binary decision diagram that can calculate simply by propagating light through electrically controlled optical pass gates. The CARRY and CARRY operations are multiplexed in one circuit by a wavelength division multiplexing scheme to reduce the number of optical elements, and only a single gate constitutes the critical path for one digit calculation. The processing time reaches picoseconds per digit when we use a 100-μm-long optical path gates, which is ten times faster than a CMOS circuit.

A single-layer platform for Boolean logic and arithmetic through DNA excision in mammalian cells

PubMed Central

Weinberg, Benjamin H.; Hang Pham, N. T.; Caraballo, Leidy D.; Lozanoski, Thomas; Engel, Adrien; Bhatia, Swapnil; Wong, Wilson W.

2017-01-01

Genetic circuits engineered for mammalian cells often require extensive fine-tuning to perform their intended functions. To overcome this problem, we present a generalizable biocomputing platform that can engineer genetic circuits which function in human cells with minimal optimization. We used our Boolean Logic and Arithmetic through DNA Excision (BLADE) platform to build more than 100 multi-input-multi-output circuits. We devised a quantitative metric to evaluate the performance of the circuits in human embryonic kidney and Jurkat T cells. Of 113 circuits analysed, 109 functioned (96.5%) with the correct specified behavior without any optimization. We used our platform to build a three-input, two-output Full Adder and six-input, one-output Boolean Logic Look Up Table. We also used BLADE to design circuits with temporal small molecule-mediated inducible control and circuits that incorporate CRISPR/Cas9 to regulate endogenous mammalian genes. PMID:28346402

All-optical negabinary adders using Mach-Zehnder interferometer

NASA Astrophysics Data System (ADS)

Cherri, A. K.

2011-02-01

In contrast to optoelectronics, all-optical adders are proposed where all-optical signals are used to represent the input numbers and the control signals. In addition, the all-optical adders use the negabinary modified signed-digit number representation (an extension of the negabinary number system) to represent the input digits. Further, the ultra-speed of the designed circuits is achieved due to the use of ultra-fast all-optical switching property of the semiconductor optical amplifier and Mach-Zehnder interferometer (SOA-MZI). Furthermore, two-bit per digit binary encoding scheme is employed to represent the trinary values of the negabinary modified signed-digits.

Design and implementation of an efficient single layer five input majority voter gate in quantum-dot cellular automata.

PubMed

Bahar, Ali Newaz; Waheed, Sajjad

2016-01-01

The fundamental logical element of a quantum-dot cellular automata (QCA) circuit is majority voter gate (MV). The efficiency of a QCA circuit is depends on the efficiency of the MV. This paper presents an efficient single layer five-input majority voter gate (MV5). The structure of proposed MV5 is very simple and easy to implement in any logical circuit. This proposed MV5 reduce number of cells and use conventional QCA cells. However, using MV5 a multilayer 1-bit full-adder (FA) is designed. The functional accuracy of the proposed MV5 and FA are confirmed by QCADesigner a well-known QCA layout design and verification tools. Furthermore, the power dissipation of proposed circuits are estimated, which shows that those circuits dissipate extremely small amount of energy and suitable for reversible computing. The simulation outcomes demonstrate the superiority of the proposed circuit.

Two-bit trinary full adder design based on restricted signed-digit numbers

NASA Astrophysics Data System (ADS)

Ahmed, J. U.; Awwal, A. A. S.; Karim, M. A.

1994-08-01

A 2-bit trinary full adder using a restricted set of a modified signed-digit trinary numeric system is designed. When cascaded together to design a multi-bit adder machine, the resulting system is able to operate at a speed independent of the size of the operands. An optical non-holographic content addressable memory based on binary coded arithmetic is considered for implementing the proposed adder.

The symmetric MSD encoder for one-step adder of ternary optical computer

NASA Astrophysics Data System (ADS)

Kai, Song; LiPing, Yan

2016-08-01

The symmetric Modified Signed-Digit (MSD) encoding is important for achieving the one-step MSD adder of Ternary Optical Computer (TOC). The paper described the symmetric MSD encoding algorithm in detail, and developed its truth table which has nine rows and nine columns. According to the truth table, the state table was developed, and the optical-path structure and circuit-implementation scheme of the symmetric MSD encoder (SME) for one-step adder of TOC were proposed. Finally, a series of experiments were designed and performed. The observed results of the experiments showed that the scheme to implement SME was correct, feasible and efficient.

Integrated logic circuits using single-atom transistors

PubMed Central

Mol, J. A.; Verduijn, J.; Levine, R. D.; Remacle, F.

2011-01-01

Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal–oxide–semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050

Catalytic nucleic acids (DNAzymes) as functional units for logic gates and computing circuits: from basic principles to practical applications.

PubMed

Orbach, Ron; Willner, Bilha; Willner, Itamar

2015-03-11

This feature article addresses the implementation of catalytic nucleic acids as functional units for the construction of logic gates and computing circuits, and discusses the future applications of these systems. The assembly of computational modules composed of DNAzymes has led to the operation of a universal set of logic gates, to field programmable logic gates and computing circuits, to the development of multiplexers/demultiplexers, and to full-adder systems. Also, DNAzyme cascades operating as logic gates and computing circuits were demonstrated. DNAzyme logic systems find important practical applications. These include the use of DNAzyme-based systems for sensing and multiplexed analyses, for the development of controlled release and drug delivery systems, for regulating intracellular biosynthetic pathways, and for the programmed synthesis and operation of cascades.

High speed capacitor-inverter based carbon nanotube full adder.

PubMed

Navi, K; Rashtian, M; Khatir, A; Keshavarzian, P; Hashemipour, O

2010-03-18

Carbon Nanotube filed-effect transistor (CNFET) is one of the promising alternatives to the MOS transistors. The geometry-dependent threshold voltage is one of the CNFET characteristics, which is used in the proposed Full Adder cell. In this paper, we present a high speed Full Adder cell using CNFETs based on majority-not (Minority) function. Presented design uses eight transistors and eight capacitors. Simulation results show significant improvement in terms of delay and power-delay product in comparison to contemporary CNFET Adder Cells. Simulations were carried out using HSPICE based on CNFET model with 0.6 V VDD.

Research, Development and Testing of a Fault-Tolerant FPGA-Based Sequencer for CubeSat Launching Applications

DTIC Science & Technology

2013-03-01

amounts of time and effort to implement. Future testing with commercial, fault-tolerant synthesis software, under a radiation environment, will yield ...initial viewpoint of the author is to take the flash-based FPGA route. This will yield a simple, reconfigurable circuit while providing the added...structure seen in Figure 30. Each of these full adder blocks were replaced in subsequent iterations to yield proper comparison with this baseline

Design and implementation of the one-step MSD adder of optical computer.

PubMed

Song, Kai; Yan, Liping

2012-03-01

On the basis of the symmetric encoding algorithm for the modified signed-digit (MSD), a 7*7 truth table that can be realized with optical methods was developed. And based on the truth table, the optical path structures and circuit implementations of the one-step MSD adder of ternary optical computer (TOC) were designed. Experiments show that the scheme is correct, feasible, and efficient. © 2012 Optical Society of America

Pipeline active filter utilizing a booth type multiplier

NASA Technical Reports Server (NTRS)

Nathan, Robert (Inventor)

1987-01-01

Multiplier units of the modified Booth decoder and carry-save adder/full adder combination are used to implement a pipeline active filter wherein pixel data is processed sequentially, and each pixel need only be accessed once and multiplied by a predetermined number of weights simultaneously, one multiplier unit for each weight. Each multiplier unit uses only one row of carry-save adders, and the results are shifted to less significant multiplier positions and one row of full adders to add the carry to the sum in order to provide the correct binary number for the product Wp. The full adder is also used to add this product Wp to the sum of products .SIGMA.Wp from preceding multiply units. If m.times.m multiplier units are pipelined, the system would be capable of processing a kernel array of m.times.m weighting factors.

Universal programmable logic gate and routing method

NASA Technical Reports Server (NTRS)

Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Mojarradi, Mohammad M. (Inventor); Fijany, Amir (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Toomarian, Nikzad (Inventor)

2009-01-01

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

CMOS-based carbon nanotube pass-transistor logic integrated circuits

PubMed Central

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Dual Brushless Resolver Rate Sensor

NASA Technical Reports Server (NTRS)

Howard, David E. (Inventor)

1997-01-01

A resolver rate sensor is disclosed in which dual brushless resolvers are mechanically coupled to the same output shaft. Diverse inputs are provided to each resolver by providing the first resolver with a DC input and the second resolver with an AC sinusoidal input. A trigonometric identity in which the sum of the squares of the sin and cosine components equal one is used to advantage in providing a sensor of increased accuracy. The first resolver may have a fixed or variable DC input to permit dynamic adjustment of resolver sensitivity thus permitting a wide range of coverage. In one embodiment of the invention the outputs of the first resolver are directly inputted into two separate multipliers and the outputs of the second resolver are inputted into the two separate multipliers, after being demodulated in a pair of demodulator circuits. The multiplied signals are then added in an adder circuit to provide a directional sensitive output. In another embodiment the outputs from the first resolver is modulated in separate modulator circuits and the output from the modulator circuits are used to excite the second resolver. The outputs from the second resolver are demodulated in separate demodulator circuit and added in an adder circuit to provide a direction sensitive rate output.

Electro-optical full-adder/full-subtractor based on graphene-silicon switches

NASA Astrophysics Data System (ADS)

Zivarian, Hossein; Zarifkar, Abbas; Miri, Mehdi

2018-01-01

A compact footprint, low-power consumption, and high-speed operation electro-optical full-adder/full-subtractor based on graphene-silicon electro-optical switches is demonstrated. Each switch consists of a Mach-Zehnder interferometer in which few-layer graphene is embedded in a silicon slot waveguide to construct phase shifters. The presented structure can be used as full-adder and full-subtractor simultaneously. The analysis of various factors such as extinction ratio, power consumption, and operation speed has been presented. As will be shown, the proposed electro-optical switch has a minimum extinction ratio of 36.21 dB, maximum insertion loss about 0.18 dB, high operation speed of 180 GHz, and is able to work with a low applied voltage about 1.4 V. Also, the extinction ratio and insertion loss of the full-adder/full-subtractor are about 30 and 1.5 dB, respectively, for transfer electric modes at telecommunication wavelength of 1.55 μm.

Probing and exploiting the chaotic dynamics of a hydrodynamic photochemical oscillator to implement all the basic binary logic functions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hayashi, Kenta; Department of Chemistry, Biology, and Biotechnology, University of Perugia, 06123 Perugia; Gotoda, Hiroshi

2016-05-15

The convective motions within a solution of a photochromic spiro-oxazine being irradiated by UV only on the bottom part of its volume, give rise to aperiodic spectrophotometric dynamics. In this paper, we study three nonlinear properties of the aperiodic time series: permutation entropy, short-term predictability and long-term unpredictability, and degree distribution of the visibility graph networks. After ascertaining the extracted chaotic features, we show how the aperiodic time series can be exploited to implement all the fundamental two-inputs binary logic functions (AND, OR, NAND, NOR, XOR, and XNOR) and some basic arithmetic operations (half-adder, full-adder, half-subtractor). This is possible duemore » to the wide range of states a nonlinear system accesses in the course of its evolution. Therefore, the solution of the convective photochemical oscillator results in hardware for chaos-computing alternative to conventional complementary metal-oxide semiconductor-based integrated circuits.« less

DENA: A Configurable Microarchitecture and Design Flow for Biomedical DNA-Based Logic Design.

PubMed

Beiki, Zohre; Jahanian, Ali

2017-10-01

DNA is known as the building block for storing the life codes and transferring the genetic features through the generations. However, it is found that DNA strands can be used for a new type of computation that opens fascinating horizons in computational medicine. Significant contributions are addressed on design of DNA-based logic gates for medical and computational applications but there are serious challenges for designing the medium and large-scale DNA circuits. In this paper, a new microarchitecture and corresponding design flow is proposed to facilitate the design of multistage large-scale DNA logic systems. Feasibility and efficiency of the proposed microarchitecture are evaluated by implementing a full adder and, then, its cascadability is determined by implementing a multistage 8-bit adder. Simulation results show the highlight features of the proposed design style and microarchitecture in terms of the scalability, implementation cost, and signal integrity of the DNA-based logic system compared to the traditional approaches.

Design of Arithmetic Circuits for Complex Binary Number System

NASA Astrophysics Data System (ADS)

Jamil, Tariq

2011-08-01

Complex numbers play important role in various engineering applications. To represent these numbers efficiently for storage and manipulation, a (-1+j)-base complex binary number system (CBNS) has been proposed in the literature. In this paper, designs of nibble-size arithmetic circuits (adder, subtractor, multiplier, divider) have been presented. These circuits can be incorporated within von Neumann and associative dataflow processors to achieve higher performance in both sequential and parallel computing paradigms.

Automatic oscillator frequency control system

NASA Technical Reports Server (NTRS)

Smith, S. F. (Inventor)

1985-01-01

A frequency control system makes an initial correction of the frequency of its own timing circuit after comparison against a frequency of known accuracy and then sequentially checks and corrects the frequencies of several voltage controlled local oscillator circuits. The timing circuit initiates the machine cycles of a central processing unit which applies a frequency index to an input register in a modulo-sum frequency divider stage and enables a multiplexer to clock an accumulator register in the divider stage with a cyclical signal derived from the oscillator circuit being checked. Upon expiration of the interval, the processing unit compares the remainder held as the contents of the accumulator against a stored zero error constant and applies an appropriate correction word to a correction stage to shift the frequency of the oscillator being checked. A signal from the accumulator register may be used to drive a phase plane ROM and, with periodic shifts in the applied frequency index, to provide frequency shift keying of the resultant output signal. Interposition of a phase adder between the accumulator register and phase plane ROM permits phase shift keying of the output signal by periodic variation in the value of a phase index applied to one input of the phase adder.

Silicon microdisk-based full adders for optical computing.

PubMed

Ying, Zhoufeng; Wang, Zheng; Zhao, Zheng; Dhar, Shounak; Pan, David Z; Soref, Richard; Chen, Ray T

2018-03-01

Due to the projected saturation of Moore's law, as well as the drastically increasing trend of bandwidth with lower power consumption, silicon photonics has emerged as one of the most promising alternatives that has attracted a lasting interest due to the accessibility and maturity of ultra-compact passive and active integrated photonic components. In this Letter, we demonstrate a ripple-carry electro-optic 2-bit full adder using microdisks, which replaces the core part of an electrical full adder by optical counterparts and uses light to carry signals from one bit to the next with high bandwidth and low power consumption per bit. All control signals of the operands are applied simultaneously within each clock cycle. Thus, the severe latency issue that accumulates as the size of the full adder increases can be circumvented, allowing for an improvement in computing speed and a reduction in power consumption. This approach paves the way for future high-speed optical computing systems in the post-Moore's law era.

Towards constructing multi-bit binary adder based on Belousov-Zhabotinsky reaction

NASA Astrophysics Data System (ADS)

Zhang, Guo-Mao; Wong, Ieong; Chou, Meng-Ta; Zhao, Xin

2012-04-01

It has been proposed that the spatial excitable media can perform a wide range of computational operations, from image processing, to path planning, to logical and arithmetic computations. The realizations in the field of chemical logical and arithmetic computations are mainly concerned with single simple logical functions in experiments. In this study, based on Belousov-Zhabotinsky reaction, we performed simulations toward the realization of a more complex operation, the binary adder. Combining with some of the existing functional structures that have been verified experimentally, we designed a planar geometrical binary adder chemical device. Through numerical simulations, we first demonstrated that the device can implement the function of a single-bit full binary adder. Then we show that the binary adder units can be further extended in plane, and coupled together to realize a two-bit, or even multi-bit binary adder. The realization of chemical adders can guide the constructions of other sophisticated arithmetic functions, ultimately leading to the implementation of chemical computer and other intelligent systems.

Parallelizing quantum circuit synthesis

NASA Astrophysics Data System (ADS)

Di Matteo, Olivia; Mosca, Michele

2016-03-01

Quantum circuit synthesis is the process in which an arbitrary unitary operation is decomposed into a sequence of gates from a universal set, typically one which a quantum computer can implement both efficiently and fault-tolerantly. As physical implementations of quantum computers improve, the need is growing for tools that can effectively synthesize components of the circuits and algorithms they will run. Existing algorithms for exact, multi-qubit circuit synthesis scale exponentially in the number of qubits and circuit depth, leaving synthesis intractable for circuits on more than a handful of qubits. Even modest improvements in circuit synthesis procedures may lead to significant advances, pushing forward the boundaries of not only the size of solvable circuit synthesis problems, but also in what can be realized physically as a result of having more efficient circuits. We present a method for quantum circuit synthesis using deterministic walks. Also termed pseudorandom walks, these are walks in which once a starting point is chosen, its path is completely determined. We apply our method to construct a parallel framework for circuit synthesis, and implement one such version performing optimal T-count synthesis over the Clifford+T gate set. We use our software to present examples where parallelization offers a significant speedup on the runtime, as well as directly confirm that the 4-qubit 1-bit full adder has optimal T-count 7 and T-depth 3.

Bit-Serial Adder Based on Quantum Dots

NASA Technical Reports Server (NTRS)

Fijany, Amir; Toomarian, Nikzad; Modarress, Katayoon; Spotnitz, Mathew

2003-01-01

A proposed integrated circuit based on quantum-dot cellular automata (QCA) would function as a bit-serial adder. This circuit would serve as a prototype building block for demonstrating the feasibility of quantum-dots computing and for the further development of increasingly complex and increasingly capable quantum-dots computing circuits. QCA-based bit-serial adders would be especially useful in that they would enable the development of highly parallel and systolic processors for implementing fast Fourier, cosine, Hartley, and wavelet transforms. The proposed circuit would complement the QCA-based circuits described in "Implementing Permutation Matrices by Use of Quantum Dots" (NPO-20801), NASA Tech Briefs, Vol. 25, No. 10 (October 2001), page 42 and "Compact Interconnection Networks Based on Quantum Dots" (NPO-20855), which appears elsewhere in this issue. Those articles described the limitations of very-large-scale-integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCA-based signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes. To enable a meaningful description of the proposed bit-serial adder, it is necessary to further recapitulate the description of a quantum-dot cellular automation from the first-mentioned prior article: A quantum-dot cellular automaton contains four quantum dots positioned at the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the quantum-mechanical sense) between neighboring dots within the cell. The Coulomb repulsion between the two electrons tends to make them occupy antipodal dots in the cell. For an isolated cell, there are two energetically equivalent arrangements (denoted polarization states) of the extra electrons. The cell polarization is used to encode binary information. Because the polarization of a nonisolated cell depends on Coulomb-repulsion interactions with neighboring cells, universal logic gates and binary wires could be constructed, in principle, by arraying QCA of suitable design in suitable patterns. Again, for reasons too complex to describe here, in order to ensure accuracy and timeliness of the output of a QCA array, it is necessary to resort to an adiabatic switching scheme in which the QCA array is divided into subarrays, each controlled by a different phase of a multiphase clock signal. In this scheme, each subarray is given time to perform its computation, then its state is frozen by raising its inter-dot potential barriers and its output is fed as the input to the successor subarray. The successor subarray is kept in an unpolarized state so it does not influence the calculation of preceding subarray. Such a clocking scheme is consistent with pipeline computation in the sense that each different subarray can perform a different part of an overall computation. In other words, QCA arrays are inherently suitable for pipeline and, moreover, systolic computations. This sequential or pipeline aspect of QCA would be utilized in the proposed bit-serial adders.

Architecture Framework for Trapped-Ion Quantum Computer based on Performance Simulation Tool

NASA Astrophysics Data System (ADS)

Ahsan, Muhammad

The challenge of building scalable quantum computer lies in striking appropriate balance between designing a reliable system architecture from large number of faulty computational resources and improving the physical quality of system components. The detailed investigation of performance variation with physics of the components and the system architecture requires adequate performance simulation tool. In this thesis we demonstrate a software tool capable of (1) mapping and scheduling the quantum circuit on a realistic quantum hardware architecture with physical resource constraints, (2) evaluating the performance metrics such as the execution time and the success probability of the algorithm execution, and (3) analyzing the constituents of these metrics and visualizing resource utilization to identify system components which crucially define the overall performance. Using this versatile tool, we explore vast design space for modular quantum computer architecture based on trapped ions. We find that while success probability is uniformly determined by the fidelity of physical quantum operation, the execution time is a function of system resources invested at various layers of design hierarchy. At physical level, the number of lasers performing quantum gates, impact the latency of the fault-tolerant circuit blocks execution. When these blocks are used to construct meaningful arithmetic circuit such as quantum adders, the number of ancilla qubits for complicated non-clifford gates and entanglement resources to establish long-distance communication channels, become major performance limiting factors. Next, in order to factorize large integers, these adders are assembled into modular exponentiation circuit comprising bulk of Shor's algorithm. At this stage, the overall scaling of resource-constraint performance with the size of problem, describes the effectiveness of chosen design. By matching the resource investment with the pace of advancement in hardware technology, we find optimal designs for different types of quantum adders. Conclusively, we show that 2,048-bit Shor's algorithm can be reliably executed within the resource budget of 1.5 million qubits.

Formal Verification of Digital Logic

DTIC Science & Technology

1991-12-01

INVERT circuit was based upon VHDL code provided in the Zycad Reference Manual [32:Ch 10,73]. The other circuits were based upon VHtDL code written...HALFADD.PL /* This file implements a simple half-adder that * /* is built from inverters and 2 input nand gates. * /* It is based upon a Zycad VHDL file...It is based upon a Zycad VHDL file written by * /* Capt Dave Banton, which is attached below the * /* Prolog code . *load..in(primitive). %h get nor2

Pneumatic binary encoder replaces multiple solenoid system

NASA Technical Reports Server (NTRS)

1966-01-01

Pneumatic binary encoder replaces solenoid system in the pilot stage of a digital actuator. The encoder operates in flip-flop manner to valve gas at either high or low pressures. By rotating the disk in a pinion-to-encoding gear ratio, six to eight adder circuits may be operated from single encoder.

Energy-Efficient Wide Datapath Integer Arithmetic Logic Units Using Superconductor Logic

NASA Astrophysics Data System (ADS)

Ayala, Christopher Lawrence

Complementary Metal-Oxide-Semiconductor (CMOS) technology is currently the most widely used integrated circuit technology today. As CMOS approaches the physical limitations of scaling, it is unclear whether or not it can provide long-term support for niche areas such as high-performance computing and telecommunication infrastructure, particularly with the emergence of cloud computing. Alternatively, superconductor technologies based on Josephson junction (JJ) switching elements such as Rapid Single Flux Quantum (RSFQ) logic and especially its new variant, Energy-Efficient Rapid Single Flux Quantum (ERSFQ) logic have the capability to provide an ultra-high-speed, low power platform for digital systems. The objective of this research is to design and evaluate energy-efficient, high-speed 32-bit integer Arithmetic Logic Units (ALUs) implemented using RSFQ and ERSFQ logic as the first steps towards achieving practical Very-Large-Scale-Integration (VLSI) complexity in digital superconductor electronics. First, a tunable VHDL superconductor cell library is created to provide a mechanism to conduct design exploration and evaluation of superconductor digital circuits from the perspectives of functionality, complexity, performance, and energy-efficiency. Second, hybrid wave-pipelining techniques developed earlier for wide datapath RSFQ designs have been used for efficient arithmetic and logic circuit implementations. To develop the core foundation of the ALU, the ripple-carry adder and the Kogge-Stone parallel prefix carry look-ahead adder are studied as representative candidates on opposite ends of the design spectrum. By combining the high-performance features of the Kogge-Stone structure and the low complexity of the ripple-carry adder, a 32-bit asynchronous wave-pipelined hybrid sparse-tree ALU has been designed and evaluated using the VHDL cell library tuned to HYPRES' gate-level characteristics. The designs and techniques from this research have been implemented using RSFQ logic and prototype chips have been fabricated. As a joint work with HYPRES, a 20 GHz 8-bit Kogge-Stone ALU consisting of 7,950 JJs total has been fabricated using a 1.5 μm 4.5 kA/cm2 process and fully demonstrated. An 8-bit sparse-tree ALU (8,832 JJs total) and a 16-bit sparse-tree adder (12,785 JJs total) have also been fabricated using a 1.0 μm 10 kA/cm 2 process and demonstrated under collaboration with Yokohama National University and Nagoya University (Japan).

VLSI (Very Large Scale Integrated) Design of a 16 Bit Very Fast Pipelined Carry Look Ahead Adder.

DTIC Science & Technology

1983-09-01

the ability for systems engineers to custom design digital integrated circuits. Until recently, the design of integrated circuits has been...traditionally carried out by a select group of logic designers working in semiconductor laboratories. Systems engineers had to "make do" or "fit in" the...products of these labs to realize their designs. The systems engineers had little participation in the actual design of the chip. The MED and CONWAY design

Application of Semiconductor Devices in Computer Technique.

DTIC Science & Technology

1960-10-14

large number of circuits v&th point-contact triod.es are used in practice f’^J" - £"i? 7° Yfe shall consider below only sojae of 7 «. -X... la a number of devices, for example in adders and registersj for the control and for connection with other circuits it is necessary to pick up... la discontin tied the voltage on the collector remains the saaaes fox’ some tiae and passing through •’the has© and collector is the space

Demonstration of optical computing logics based on binary decision diagram.

PubMed

Lin, Shiyun; Ishikawa, Yasuhiko; Wada, Kazumi

2012-01-16

Optical circuits are low power consumption and fast speed alternatives for the current information processing based on transistor circuits. However, because of no transistor function available in optics, the architecture for optical computing should be chosen that optics prefers. One of which is Binary Decision Diagram (BDD), where signal is processed by sending an optical signal from the root through a serial of switching nodes to the leaf (terminal). Speed of optical computing is limited by either transmission time of optical signals from the root to the leaf or switching time of a node. We have designed and experimentally demonstrated 1-bit and 2-bit adders based on the BDD architecture. The switching nodes are silicon ring resonators with a modulation depth of 10 dB and the states are changed by the plasma dispersion effect. The quality, Q of the rings designed is 1500, which allows fast transmission of signal, e.g., 1.3 ps calculated by a photon escaping time. A total processing time is thus analyzed to be ~9 ps for a 2-bit adder and would scales linearly with the number of bit. It is two orders of magnitude faster than the conventional CMOS circuitry, ~ns scale of delay. The presented results show the potential of fast speed optical computing circuits.

High-Speed Rapid-Single-Flux-Quantum Multiplexer and Demultiplexer Design and Testing

DTIC Science & Technology

2007-08-22

Herr, N. Vukovic , C. A. Mancini, M. F. Bocko, and M. J . Feldman, "High speed testing of a four-bit RSFQ decimation digital filter," IEEE Trans. Appl...61] A. M. Herr, C. A. Mancini, N. Vukovic , M. F. Bocko, and M. J . Feldman, "High-speed operation of a 64-bit circular shift register," IEEE Trans...10-19 J . A rich library of basic cells such as flip-flops, buffers, adders, multipliers, clock generator circuits, and phase-locking circuits have been

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

PubMed

Kwon, Jimin; Takeda, Yasunori; Fukuda, Kenjiro; Cho, Kilwon; Tokito, Shizuo; Jung, Sungjune

2016-11-22

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Design and implementation of low power clock gated 64-bit ALU on ultra scale FPGA

NASA Astrophysics Data System (ADS)

Gupta, Ashutosh; Murgai, Shruti; Gulati, Anmol; Kumar, Pradeep

2016-03-01

64-bit energy efficient Arithmetic and Logic Unit using negative latch based clock gating technique is designed in this paper. The 64-bit ALU is designed using multiplexer based full adder cell. We have designed a 64-bit ALU with a gated clock. We have used negative latch based circuit for generating gated clock. This gated clock is used to control the multiplexer based 64-bit ALU. The circuit has been synthesized on kintex FPGA through Xilinx ISE Design Suite 14.7 using 28 nm technology in Verilog HDL. The circuit has been simulated on Modelsim 10.3c. The design is verified using System Verilog on QuestaSim in UVM environment. We have achieved 74.07%, 92. 93% and 95.53% reduction in total clock power, 89.73%, 91.35% and 92.85% reduction in I/Os power, 67.14%, 62.84% and 74.34% reduction in dynamic power and 25.47%, 29.05% and 46.13% reduction in total supply power at 20 MHz, 200 MHz and 2 GHz frequency respectively. The power has been calculated using XPower Analyzer tool of Xilinx ISE Design Suite 14.3.

Design of the Detector II: A CMOS Gate Array for the Study of Concurrent Error Detection Techniques.

DTIC Science & Technology

1987-07-01

detection schemes and temporary failures. The circuit consists- or of six different adders with concurrent error detection schemes . The error detection... schemes are - simple duplication, duplication with functional dual implementation, duplication with different &I [] .6implementations, two-rail encoding...THE SYSTEM. .. .... ...... ...... ...... 5 7. DESIGN OF CED SCHEMES .. ... ...... ...... ........ 7 7.1 Simple Duplication

Programmable nanowire circuits for nanoprocessors.

PubMed

Yan, Hao; Choe, Hwan Sung; Nam, SungWoo; Hu, Yongjie; Das, Shamik; Klemic, James F; Ellenbogen, James C; Lieber, Charles M

2011-02-10

A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm(2). The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input-output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Complementary code and digital filtering for detection of weak VHF radar signals from the mesoscale. [SOUSY-VHF radar, Harz Mountains, Germany

NASA Technical Reports Server (NTRS)

Schmidt, G.; Ruster, R.; Czechowsky, P.

1983-01-01

The SOUSY-VHF-Radar operates at a frequency of 53.5 MHz in a valley in the Harz mountains, Germany, 90 km from Hanover. The radar controller, which is programmed by a 16-bit computer holds 1024 program steps in core and controls, via 8 channels, the whole radar system: in particular the master oscillator, the transmitter, the transmit-receive-switch, the receiver, the analog to digital converter, and the hardware adder. The high-sensitivity receiver has a dynamic range of 70 dB and a video bandwidth of 1 MHz. Phase coding schemes are applied, in particular for investigations at mesospheric heights, in order to carry out measurements with the maximum duty cycle and the maximum height resolution. The computer takes the data from the adder to store it in magnetic tape or disc. The radar controller is programmed by the computer using simple FORTRAN IV statements. After the program has been loaded and the computer has started the radar controller, it runs automatically, stopping at the program end. In case of errors or failures occurring during the radar operation, the radar controller is shut off caused either by a safety circuit or by a power failure circuit or by a parity check system.

Off-line, built-in test techniques for VLSI circuits

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Sievers, M. W.

1982-01-01

It is shown that the use of redundant on-chip circuitry improves the testability of an entire VLSI circuit. In the study described here, five techniques applied to a two-bit ripple carry adder are compared. The techniques considered are self-oscillation, self-comparison, partition, scan path, and built-in logic block observer. It is noted that both classical stuck-at faults and nonclassical faults, such as bridging faults (shorts), stuck-on x faults where x may be 0, 1, or vary between the two, and parasitic flip-flop faults occur in IC structures. To simplify the analysis of the testing techniques, however, a stuck-at fault model is assumed.

Optimized 4-bit Quantum Reversible Arithmetic Logic Unit

NASA Astrophysics Data System (ADS)

Ayyoub, Slimani; Achour, Benslama

2017-08-01

Reversible logic has received a great attention in the recent years due to its ability to reduce the power dissipation. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. The arithmetic logic unit (ALU) is an important part of central processing unit (CPU) as the execution unit. This paper presents a complete design of a new reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The proposed ALU based on a reversible low power control unit and small performance parameters full adder named double Peres gates. The presented ALU can produce the largest number (28) of arithmetic and logic functions and have the smallest number of quantum cost and delay compared with existing designs.

Implementation of trinary logic in a polarization encoded optical shadow-casting scheme.

PubMed

Rizvi, R A; Zaheer, K; Zubairy, M S

1991-03-10

The design of various multioutput trinary combinational logic units by a polarization encoded optical shadow-casting (POSC) technique is presented. The POSC modified algorithm is employed to design and implement these logic elements in a trinary number system with separate and simultaneous generation of outputs. A detailed solution of the POSC logic equations for a fixed source plane and a fixed decoding mask is given to obtain input pixel coding for a trinary half-adder, full adder, and subtractor.

Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits.

PubMed

Chen, Bingyan; Zhang, Panpan; Ding, Li; Han, Jie; Qiu, Song; Li, Qingwen; Zhang, Zhiyong; Peng, Lian-Mao

2016-08-10

Top-gated p-type field-effect transistors (FETs) have been fabricated in batch based on carbon nanotube (CNT) network thin films prepared from CNT solution and present high yield and highly uniform performance with small threshold voltage distribution with standard deviation of 34 mV. According to the property of FETs, various logical and arithmetical gates, shifters, and d-latch circuits were designed and demonstrated with rail-to-rail output. In particular, a 4-bit adder consisting of 140 p-type CNT FETs was demonstrated with higher packing density and lower supply voltage than other published integrated circuits based on CNT films, which indicates that CNT based integrated circuits can reach to medium scale. In addition, a 2-bit multiplier has been realized for the first time. Benefitted from the high uniformity and suitable threshold voltage of CNT FETs, all of the fabricated circuits based on CNT FETs can be driven by a single voltage as small as 2 V.

On fast carry select adders

NASA Technical Reports Server (NTRS)

Shamanna, M.; Whitaker, S.

1992-01-01

This paper presents an architecture for a high-speed carry select adder with very long bit lengths utilizing a conflict-free bypass scheme. The proposed scheme has almost half the number of transistors and is faster than a conventional carry select adder. A comparative study is also made between the proposed adder and a Manchester carry chain adder which shows that the proposed scheme has the same transistor count, without suffering any performance degradation, compared to the Manchester carry chain adder.

Complex logic functions implemented with quantum dot bionanophotonic circuits.

PubMed

Claussen, Jonathan C; Hildebrandt, Niko; Susumu, Kimihiro; Ancona, Mario G; Medintz, Igor L

2014-03-26

We combine quantum dots (QDs) with long-lifetime terbium complexes (Tb), a near-IR Alexa Fluor dye (A647), and self-assembling peptides to demonstrate combinatorial and sequential bionanophotonic logic devices that function by time-gated Förster resonance energy transfer (FRET). Upon excitation, the Tb-QD-A647 FRET-complex produces time-dependent photoluminescent signatures from multi-FRET pathways enabled by the capacitor-like behavior of the Tb. The unique photoluminescent signatures are manipulated by ratiometrically varying dye/Tb inputs and collection time. Fluorescent output is converted into Boolean logic states to create complex arithmetic circuits including the half-adder/half-subtractor, 2:1 multiplexer/1:2 demultiplexer, and a 3-digit, 16-combination keypad lock.

A Novel Reconfigurable Logic Unit Based on the DNA-Templated Potassium-Concentration-Dependent Supramolecular Assembly.

PubMed

Yang, Chunrong; Zou, Dan; Chen, Jianchi; Zhang, Linyan; Miao, Jiarong; Huang, Dan; Du, Yuanyuan; Yang, Shu; Yang, Qianfan; Tang, Yalin

2018-03-15

Plenty of molecular circuits with specific functions have been developed; however, logic units with reconfigurability, which could simplify the circuits and speed up the information process, are rarely reported. In this work, we designed a novel reconfigurable logic unit based on a DNA-templated, potassium-concentration-dependent, supramolecular assembly, which could respond to the input stimuli of H + and K + . By inputting different concentrations of K + , the logic unit could implement three significant functions, including a half adder, a half subtractor, and a 2-to-4 decoder. Considering its reconfigurable ability and good performance, the novel prototypes developed here may serve as a promising proof of principle in molecular computers. © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Evolutionary Based Techniques for Fault Tolerant Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Larchev, Gregory V.; Lohn, Jason D.

2006-01-01

The use of SRAM-based Field Programmable Gate Arrays (FPGAs) is becoming more and more prevalent in space applications. Commercial-grade FPGAs are potentially susceptible to permanently debilitating Single-Event Latchups (SELs). Repair methods based on Evolutionary Algorithms may be applied to FPGA circuits to enable successful fault recovery. This paper presents the experimental results of applying such methods to repair four commonly used circuits (quadrature decoder, 3-by-3-bit multiplier, 3-by-3-bit adder, 440-7 decoder) into which a number of simulated faults have been introduced. The results suggest that evolutionary repair techniques can improve the process of fault recovery when used instead of or as a supplement to Triple Modular Redundancy (TMR), which is currently the predominant method for mitigating FPGA faults.

Demonstration of Inexact Computing Implemented in the JPEG Compression Algorithm using Probabilistic Boolean Logic applied to CMOS Components

DTIC Science & Technology

2015-12-24

Ripple-Carry RCA Ripple-Carry Adder RF Radio Frequency RMS Root-Mean-Square SEU Single Event Upset SIPI Signal and Image Processing Institute SNR...correctness, where 0.5 < p < 1, and a probability (1−p) of error. Errors could be caused by noise, radio frequency (RF) interference, crosstalk...utilized in the Apollo Guidance Computer is the three input NOR Gate. . . At the time that the decision was made to use in- 11 tegrated circuits, the

Demonstration of Inexact Computing Implemented in the JPEG Compression Algorithm Using Probabilistic Boolean Logic Applied to CMOS Components

DTIC Science & Technology

2015-12-24

Ripple-Carry RCA Ripple-Carry Adder RF Radio Frequency RMS Root-Mean-Square SEU Single Event Upset SIPI Signal and Image Processing Institute SNR...correctness, where 0.5 < p < 1, and a probability (1−p) of error. Errors could be caused by noise, radio frequency (RF) interference, crosstalk...utilized in the Apollo Guidance Computer is the three input NOR Gate. . . At the time that the decision was made to use in- 11 tegrated circuits, the

Nanowire nanocomputer as a finite-state machine.

PubMed

Yao, Jun; Yan, Hao; Das, Shamik; Klemic, James F; Ellenbogen, James C; Lieber, Charles M

2014-02-18

Implementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly organized, integrated computational circuits. We describe how such a strategy has led to the design, construction, and demonstration of a nanoelectronic finite-state machine. The system was fabricated using a design-oriented approach enabled by a deterministic, bottom-up assembly process that does not require individual nanowire registration. This methodology allowed construction of the nanoelectronic finite-state machine through modular design using a multitile architecture. Each tile/module consists of two interconnected crossbar nanowire arrays, with each cross-point consisting of a programmable nanowire transistor node. The nanoelectronic finite-state machine integrates 180 programmable nanowire transistor nodes in three tiles or six total crossbar arrays, and incorporates both sequential and arithmetic logic, with extensive intertile and intratile communication that exhibits rigorous input/output matching. Our system realizes the complete 2-bit logic flow and clocked control over state registration that are required for a finite-state machine or computer. The programmable multitile circuit was also reprogrammed to a functionally distinct 2-bit full adder with 32-set matched and complete logic output. These steps forward and the ability of our unique design-oriented deterministic methodology to yield more extensive multitile systems suggest that proposed general-purpose nanocomputers can be realized in the near future.

Nanowire nanocomputer as a finite-state machine

PubMed Central

Yao, Jun; Yan, Hao; Das, Shamik; Klemic, James F.; Ellenbogen, James C.; Lieber, Charles M.

2014-01-01

Implementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly organized, integrated computational circuits. We describe how such a strategy has led to the design, construction, and demonstration of a nanoelectronic finite-state machine. The system was fabricated using a design-oriented approach enabled by a deterministic, bottom–up assembly process that does not require individual nanowire registration. This methodology allowed construction of the nanoelectronic finite-state machine through modular design using a multitile architecture. Each tile/module consists of two interconnected crossbar nanowire arrays, with each cross-point consisting of a programmable nanowire transistor node. The nanoelectronic finite-state machine integrates 180 programmable nanowire transistor nodes in three tiles or six total crossbar arrays, and incorporates both sequential and arithmetic logic, with extensive intertile and intratile communication that exhibits rigorous input/output matching. Our system realizes the complete 2-bit logic flow and clocked control over state registration that are required for a finite-state machine or computer. The programmable multitile circuit was also reprogrammed to a functionally distinct 2-bit full adder with 32-set matched and complete logic output. These steps forward and the ability of our unique design-oriented deterministic methodology to yield more extensive multitile systems suggest that proposed general-purpose nanocomputers can be realized in the near future. PMID:24469812

High performance pipelined multiplier with fast carry-save adder

NASA Technical Reports Server (NTRS)

Wu, Angus

1990-01-01

A high-performance pipelined multiplier is described. Its high performance results from the fast carry-save adder basic cell which has a simple structure and is suitable for the Gate Forest semi-custom environment. The carry-save adder computes the sum and carry within two gate delay. Results show that the proposed adder can operate at 200 MHz for a 2-micron CMOS process; better performance is expected in a Gate Forest realization.

Computational investigation and experimental considerations for the classical implementation of a full adder on SO2 by optical pump-probe schemes.

PubMed

Bomble, L; Lavorel, B; Remacle, F; Desouter-Lecomte, M

2008-05-21

Following the scheme recently proposed by Remacle and Levine [Phys. Rev. A 73, 033820 (2006)], we investigate the concrete implementation of a classical full adder on two electronic states (X 1A1 and C 1B2) of the SO2 molecule by optical pump-probe laser pulses using intuitive and counterintuitive (stimulated Raman adiabatic passage) excitation schemes. The resources needed for providing the inputs and reading out are discussed, as well as the conditions for achieving robustness in both the intuitive and counterintuitive pump-dump sequences. The fidelity of the scheme is analyzed with respect to experimental noise and two kinds of perturbations: The coupling to the neighboring rovibrational states and a finite rotational temperature that leads to a mixture for the initial state. It is shown that the logic processing of a full addition cycle can be realistically experimentally implemented on a picosecond time scale while the readout takes a few nanoseconds.

Plasmonic integrated circuits comprising metal waveguides, multiplexer/demultiplexer, detectors, and logic circuits on a silicon substrate

NASA Astrophysics Data System (ADS)

Fukuda, M.; Ota, M.; Sumimura, A.; Okahisa, S.; Ito, M.; Ishii, Y.; Ishiyama, T.

2017-05-01

A plasmonic integrated circuit configuration comprising plasmonic and electronic components is presented and the feasibility for high-speed signal processing applications is discussed. In integrated circuits, plasmonic signals transmit data at high transfer rates with light velocity. Plasmonic and electronic components such as wavelength-divisionmultiplexing (WDM) networks comprising metal wires, plasmonic multiplexers/demultiplexers, and crossing metal wires are connected via plasmonic waveguides on the nanometer or micrometer scales. To merge plasmonic and electronic components, several types of plasmonic components were developed. To ensure that the plasmonic components could be easily fabricated and monolithically integrated onto a silicon substrate using silicon complementary metal-oxide-semiconductor (CMOS)-compatible processes, the components were fabricated on a Si substrate and made from silicon, silicon oxides, and metal; no other materials were used in the fabrication. The plasmonic components operated in the 1300- and 1550-nm-wavelength bands, which are typically employed in optical fiber communication systems. The plasmonic logic circuits were formed by patterning a silicon oxide film on a metal film, and the operation as a half adder was confirmed. The computed plasmonic signals can propagate through the plasmonic WDM networks and be connected to electronic integrated circuits at high data-transfer rates.

Death Adder Envenoming Causes Neurotoxicity Not Reversed by Antivenom - Australian Snakebite Project (ASP-16)

PubMed Central

Johnston, Christopher I.; O'Leary, Margaret A.; Brown, Simon G. A.; Currie, Bart J.; Halkidis, Lambros; Whitaker, Richard; Close, Benjamin; Isbister, Geoffrey K.

2012-01-01

Background Death adders (Acanthophis spp) are found in Australia, Papua New Guinea and parts of eastern Indonesia. This study aimed to investigate the clinical syndrome of death adder envenoming and response to antivenom treatment. Methodology/Principal Findings Definite death adder bites were recruited from the Australian Snakebite Project (ASP) as defined by expert identification or detection of death adder venom in blood. Clinical effects and laboratory results were collected prospectively, including the time course of neurotoxicity and response to treatment. Enzyme immunoassay was used to measure venom concentrations. Twenty nine patients had definite death adder bites; median age 45 yr (5–74 yr); 25 were male. Envenoming occurred in 14 patients. Two further patients had allergic reactions without envenoming, both snake handlers with previous death adder bites. Of 14 envenomed patients, 12 developed neurotoxicity characterised by ptosis (12), diplopia (9), bulbar weakness (7), intercostal muscle weakness (2) and limb weakness (2). Intubation and mechanical ventilation were required for two patients for 17 and 83 hours. The median time to onset of neurotoxicity was 4 hours (0.5–15.5 hr). One patient bitten by a northern death adder developed myotoxicity and one patient only developed systemic symptoms without neurotoxicity. No patient developed venom induced consumption coagulopathy. Antivenom was administered to 13 patients, all receiving one vial initially. The median time for resolution of neurotoxicity post-antivenom was 21 hours (5–168). The median peak venom concentration in 13 envenomed patients with blood samples was 22 ng/mL (4.4–245 ng/mL). In eight patients where post-antivenom bloods were available, no venom was detected after one vial of antivenom. Conclusions/Significance Death adder envenoming is characterised by neurotoxicity, which is mild in most cases. One vial of death adder antivenom was sufficient to bind all circulating venom. The persistent neurological effects despite antivenom, suggests that neurotoxicity is not reversed by antivenom. PMID:23029595

Death adder envenoming causes neurotoxicity not reversed by antivenom--Australian Snakebite Project (ASP-16).

PubMed

Johnston, Christopher I; O'Leary, Margaret A; Brown, Simon G A; Currie, Bart J; Halkidis, Lambros; Whitaker, Richard; Close, Benjamin; Isbister, Geoffrey K

2012-01-01

Death adders (Acanthophis spp) are found in Australia, Papua New Guinea and parts of eastern Indonesia. This study aimed to investigate the clinical syndrome of death adder envenoming and response to antivenom treatment. Definite death adder bites were recruited from the Australian Snakebite Project (ASP) as defined by expert identification or detection of death adder venom in blood. Clinical effects and laboratory results were collected prospectively, including the time course of neurotoxicity and response to treatment. Enzyme immunoassay was used to measure venom concentrations. Twenty nine patients had definite death adder bites; median age 45 yr (5-74 yr); 25 were male. Envenoming occurred in 14 patients. Two further patients had allergic reactions without envenoming, both snake handlers with previous death adder bites. Of 14 envenomed patients, 12 developed neurotoxicity characterised by ptosis (12), diplopia (9), bulbar weakness (7), intercostal muscle weakness (2) and limb weakness (2). Intubation and mechanical ventilation were required for two patients for 17 and 83 hours. The median time to onset of neurotoxicity was 4 hours (0.5-15.5 hr). One patient bitten by a northern death adder developed myotoxicity and one patient only developed systemic symptoms without neurotoxicity. No patient developed venom induced consumption coagulopathy. Antivenom was administered to 13 patients, all receiving one vial initially. The median time for resolution of neurotoxicity post-antivenom was 21 hours (5-168). The median peak venom concentration in 13 envenomed patients with blood samples was 22 ng/mL (4.4-245 ng/mL). In eight patients where post-antivenom bloods were available, no venom was detected after one vial of antivenom. Death adder envenoming is characterised by neurotoxicity, which is mild in most cases. One vial of death adder antivenom was sufficient to bind all circulating venom. The persistent neurological effects despite antivenom, suggests that neurotoxicity is not reversed by antivenom.

Modeling and Optimization of Optical Half Adder in Two Dimensional Photonic Crystals

NASA Astrophysics Data System (ADS)

Sonth, Mahesh V.; Soma, Savita; Gowre, Sanjaykumar C.; Biradar, Nagashettappa

2018-05-01

The output of photonic integrated devices is enhanced using crystal waveguides and cavities but optimization of these devices is a topic of research. In this paper, optimization of the optical half adder in two-dimensional (2-D) linear photonic crystals using four symmetric T-shaped waveguides with 180° phase shift inputs is proposed. The input section of a T-waveguide acts as a beam splitter, and the output section acts as a power combiner. The constructive and destructive interference phenomenon will provide an output optical power. Output port Cout will receive in-phase power through the 180° phase shifter cavity designed near the junction. The optical half adder is modeled in a 2-D photonic crystal using the finite difference time domain method (FDTD). It consists of a cubic lattice with an array of 39 × 43 silicon rods of radius r 0.12 μm and 0.6 μm lattice constant a. The extinction ratio r e of 11.67 dB and 12.51 dB are achieved at output ports using the RSoft FullWAVE-6.1 software package.

Hydraulic logic gates: building a digital water computer

NASA Astrophysics Data System (ADS)

Taberlet, Nicolas; Marsal, Quentin; Ferrand, Jérémy; Plihon, Nicolas

2018-03-01

In this article, we propose an easy-to-build hydraulic machine which serves as a digital binary computer. We first explain how an elementary adder can be built from test tubes and pipes (a cup filled with water representing a 1, and empty cup a 0). Using a siphon and a slow drain, the proposed setup combines AND and XOR logical gates in a single device which can add two binary digits. We then show how these elementary units can be combined to construct a full 4-bit adder. The sequencing of the computation is discussed and a water clock can be incorporated so that the machine can run without any exterior intervention.

Logic gates based all-optical binary half adder using triple core photonic crystal fiber

NASA Astrophysics Data System (ADS)

Uthayakumar, T.; Vasantha Jayakantha Raja, R.

2018-06-01

This study presents the implementation of an all-optical binary logic half adder by employing a triple core photonic crystal fiber (TPCF). The noteworthy feature of the present investigation is that an identical set of TPCF schemes, which demonstrated all-optical logic functions in our previous report, has revealed the ability to demonstrate the successful half adder operation. The control signal (CS) power defining the extinction ratios of the output ports for the considered symmetric planar and triangular TPCFs is evaluated through a numerical algorithm. Through suitable CS power and input combinations, the logic outputs are generated from extinction ratios to demonstrate the half adder operation. The results obtained display the significant influence of the input conditions on the delivery of half adder operation for different TPCF schemes considered. Furthermore, chloroform filled TPCF structures demonstrated the efficient low power half adder operation with a significant figure of merit, compared to that of the silica counterpart.

Incidence, pathology, and treatment of adder (Vipera berus L.) bites in man.

PubMed Central

Reading, C J

1996-01-01

A review of published reports on the incidence, pathology, and treatment of adder (Vipera berus) bites in man in the United Kingdom and Europe produced numerous case studies but little information about the impact od adders as a threat to public health. Adder bites in man are not uncommon (at least 44/year and probably more than 90/year in the United Kingdom) and, although they have been recorded for every month of the year between February and October, envenoming is most likely to occur during June, July, and August. Most adder bites are on the hand (51.6%) or foot (38.2%). The effects of adder bite envenoming are now know. Effective treatment protocols can reduce both the length of time victims spend in hospital and the morbidity in the affected areas: they have resulted in a decline in the death rate over the last 30 years, so that deaths are now rare. PMID:8894864

Charge Coupled Devices in Signal Processing Systems. Volume V. Final Report.

DTIC Science & Technology

1979-12-01

the Phase III program. At that time, mutual customer /contractor interest arose in a unique application area, involving manipulation of lists of...using half adders and "or" circuits. 4-35 3 b 2 b3 01 b *3b, *2 b 1 b2b 1 0 1 b, + + + + + + ++ r T 7 7 r* 7FA +-0j FA 147 7 7 1 77 7 7 TL NO.6 NO. 5...which the cell could be step-and- repeated into an array in the CAD system. In practice we found that the attendent custom skewing delay layout

Qubits and quantum Hamiltonian computing performances for operating a digital Boolean 1/2-adder

NASA Astrophysics Data System (ADS)

Dridi, Ghassen; Faizy Namarvar, Omid; Joachim, Christian

2018-04-01

Quantum Boolean (1 + 1) digits 1/2-adders are designed with 3 qubits for the quantum computing (Qubits) and 4 quantum states for the quantum Hamiltonian computing (QHC) approaches. Detailed analytical solutions are provided to analyse the time operation of those different 1/2-adder gates. QHC is more robust to noise than Qubits and requires about the same amount of energy for running its 1/2-adder logical operations. QHC is faster in time than Qubits but its logical output measurement takes longer.

MULTI-CHANNEL ELECTRIC PULSE HEIGHT ANALYZER

DOEpatents

Gallagher, J.D. et al.

1960-11-22

An apparatus is given for converting binary information into coded decimal form comprising means, in combination with a binary adder, a live memory and a source of bigit pulses, for synchronizing the bigit pulses and the adder output pulses; a source of digit pulses synchronized with every fourth bigit pulse; means for generating a conversion pulse in response to the time coincidence of the adder output pulse and a digit pulse: means having a delay equal to two bigit pulse periods coupling the adder output with the memory; means for promptly impressing said conversion pulse on the input of said memory: and means having a delay equal to one bigit pulse period for again impressing the conversion pulse on the input of the memory whereby a fourth bigit adder pulse results in the insertion into the memory of second, third and fourth bigits.

Quantum realization of the bilinear interpolation method for NEQR.

PubMed

Zhou, Ri-Gui; Hu, Wenwen; Fan, Ping; Ian, Hou

2017-05-31

In recent years, quantum image processing is one of the most active fields in quantum computation and quantum information. Image scaling as a kind of image geometric transformation has been widely studied and applied in the classical image processing, however, the quantum version of which does not exist. This paper is concerned with the feasibility of the classical bilinear interpolation based on novel enhanced quantum image representation (NEQR). Firstly, the feasibility of the bilinear interpolation for NEQR is proven. Then the concrete quantum circuits of the bilinear interpolation including scaling up and scaling down for NEQR are given by using the multiply Control-Not operation, special adding one operation, the reverse parallel adder, parallel subtractor, multiplier and division operations. Finally, the complexity analysis of the quantum network circuit based on the basic quantum gates is deduced. Simulation result shows that the scaled-up image using bilinear interpolation is clearer and less distorted than nearest interpolation.

Adiabatic quantum-flux-parametron cell library adopting minimalist design

DOE Office of Scientific and Technical Information (OSTI.GOV)

Takeuchi, Naoki, E-mail: takeuchi-naoki-kx@ynu.jp; Yamanashi, Yuki; Yoshikawa, Nobuyuki

We herein build an adiabatic quantum-flux-parametron (AQFP) cell library adopting minimalist design and a symmetric layout. In the proposed minimalist design, every logic cell is designed by arraying four types of building block cells: buffer, NOT, constant, and branch cells. Therefore, minimalist design enables us to effectively build and customize an AQFP cell library. The symmetric layout reduces unwanted parasitic magnetic coupling and ensures a large mutual inductance in an output transformer, which enables very long wiring between logic cells. We design and fabricate several logic circuits using the minimal AQFP cell library so as to test logic cells inmore » the library. Moreover, we experimentally investigate the maximum wiring length between logic cells. Finally, we present an experimental demonstration of an 8-bit carry look-ahead adder designed using the minimal AQFP cell library and demonstrate that the proposed cell library is sufficiently robust to realize large-scale digital circuits.« less

Adiabatic quantum-flux-parametron cell library adopting minimalist design

NASA Astrophysics Data System (ADS)

Takeuchi, Naoki; Yamanashi, Yuki; Yoshikawa, Nobuyuki

2015-05-01

We herein build an adiabatic quantum-flux-parametron (AQFP) cell library adopting minimalist design and a symmetric layout. In the proposed minimalist design, every logic cell is designed by arraying four types of building block cells: buffer, NOT, constant, and branch cells. Therefore, minimalist design enables us to effectively build and customize an AQFP cell library. The symmetric layout reduces unwanted parasitic magnetic coupling and ensures a large mutual inductance in an output transformer, which enables very long wiring between logic cells. We design and fabricate several logic circuits using the minimal AQFP cell library so as to test logic cells in the library. Moreover, we experimentally investigate the maximum wiring length between logic cells. Finally, we present an experimental demonstration of an 8-bit carry look-ahead adder designed using the minimal AQFP cell library and demonstrate that the proposed cell library is sufficiently robust to realize large-scale digital circuits.

Recoded and nonrecoded trinary signed-digit adders and multipliers with redundant-bit representations

NASA Astrophysics Data System (ADS)

Cherri, Abdallah K.; Alam, Mohammed S.

1998-07-01

Highly-efficient two-step recoded and one-step nonrecoded trinary signed-digit (TSD) carry-free adders subtracters are presented on the basis of redundant-bit representation for the operands digits. It has been shown that only 24 (30) minterms are needed to implement the two-step recoded (the one-step nonrecoded) TSD addition for any operand length. Optical implementation of the proposed arithmetic can be carried out by use of correlation- or matrix-multiplication-based schemes, saving 50% of the system memory. Furthermore, we present four different multiplication designs based on our proposed recoded and nonrecoded TSD adders. Our multiplication designs require a small number of reduced minterms to generate the multiplication partial products. Finally, a recently proposed pipelined iterative-tree algorithm can be used in the TSD adders multipliers; consequently, efficient use of all available adders can be made.

Recoded and nonrecoded trinary signed-digit adders and multipliers with redundant-bit representations.

PubMed

Cherri, A K; Alam, M S

1998-07-10

Highly-efficient two-step recoded and one-step nonrecoded trinary signed-digit (TSD) carry-free adders-subtracters are presented on the basis of redundant-bit representation for the operands' digits. It has been shown that only 24 (30) minterms are needed to implement the two-step recoded (the one-step nonrecoded) TSD addition for any operand length. Optical implementation of the proposed arithmetic can be carried out by use of correlation- or matrix-multiplication-based schemes, saving 50% of the system memory. Furthermore, we present four different multiplication designs based on our proposed recoded and nonrecoded TSD adders. Our multiplication designs require a small number of reduced minterms to generate the multiplication partial products. Finally, a recently proposed pipelined iterative-tree algorithm can be used in the TSD adders-multipliers; consequently, efficient use of all available adders can be made.

Serial multiplier arrays for parallel computation

NASA Technical Reports Server (NTRS)

Winters, Kel

1990-01-01

Arrays of systolic serial-parallel multiplier elements are proposed as an alternative to conventional SIMD mesh serial adder arrays for applications that are multiplication intensive and require few stored operands. The design and operation of a number of multiplier and array configurations featuring locality of connection, modularity, and regularity of structure are discussed. A design methodology combining top-down and bottom-up techniques is described to facilitate development of custom high-performance CMOS multiplier element arrays as well as rapid synthesis of simulation models and semicustom prototype CMOS components. Finally, a differential version of NORA dynamic circuits requiring a single-phase uncomplemented clock signal introduced for this application.

Pencil-like mm-size electron beams produced with linear inductive voltage adders

NASA Astrophysics Data System (ADS)

Mazarakis, M. G.; Poukey, J. W.; Rovang, D. C.; Maenchen, J. E.; Cordova, S. R.; Menge, P. R.; Pepping, R.; Bennett, L.; Mikkelson, K.; Smith, D. L.; Halbleib, J.; Stygar, W. A.; Welch, D. R.

1997-02-01

We present the design, analysis, and results of the high brightness electron beam experiments currently under investigation at Sandia National Laboratories. The anticipated beam parameters are the following: energy 12 MeV, current 35-40 kA, rms radius 0.5 mm, and pulse duration 40 ns full width at half-maximum. The accelerator is SABRE, a pulsed linear inductive voltage adder modified to higher impedance, and the electron source is a magnetically immersed foilless electron diode. 20-30 T solenoidal magnets are required to insulate the diode and contain the beam to its extremely small-sized (1 mm) envelope. These experiments are designed to push the technology to produce the highest possible electron current in a submillimeter radius beam. Design, numerical simulations, and experimental results are presented.

Linear induction accelerator

DOEpatents

Buttram, M.T.; Ginn, J.W.

1988-06-21

A linear induction accelerator includes a plurality of adder cavities arranged in a series and provided in a structure which is evacuated so that a vacuum inductance is provided between each adder cavity and the structure. An energy storage system for the adder cavities includes a pulsed current source and a respective plurality of bipolar converting networks connected thereto. The bipolar high-voltage, high-repetition-rate square pulse train sets and resets the cavities. 4 figs.

The Adder Phenomenon Emerges from Independent Control of Pre- and Post-Start Phases of the Budding Yeast Cell Cycle.

PubMed

Chandler-Brown, Devon; Schmoller, Kurt M; Winetraub, Yonatan; Skotheim, Jan M

2017-09-25

Although it has long been clear that cells actively regulate their size, the molecular mechanisms underlying this regulation have remained poorly understood. In budding yeast, cell size primarily modulates the duration of the cell-division cycle by controlling the G1/S transition known as Start. We have recently shown that the rate of progression through Start increases with cell size, because cell growth dilutes the cell-cycle inhibitor Whi5 in G1. Recent phenomenological studies in yeast and bacteria have shown that these cells add an approximately constant volume during each complete cell cycle, independent of their size at birth. These results seem to be in conflict, as the phenomenological studies suggest that cells measure the amount they grow, rather than their size, and that size control acts over the whole cell cycle, rather than specifically in G1. Here, we propose an integrated model that unifies the adder phenomenology with the molecular mechanism of G1/S cell-size control. We use single-cell microscopy to parameterize a full cell-cycle model based on independent control of pre- and post-Start cell-cycle periods. We find that our model predicts the size-independent amount of cell growth during the full cell cycle. This suggests that the adder phenomenon is an emergent property of the independent regulation of pre- and post-Start cell-cycle periods rather than the consequence of an underlying molecular mechanism measuring a fixed amount of growth. Copyright © 2017 Elsevier Ltd. All rights reserved.

Linear induction accelerator and pulse forming networks therefor

DOEpatents

Buttram, Malcolm T.; Ginn, Jerry W.

1989-01-01

A linear induction accelerator includes a plurality of adder cavities arranged in a series and provided in a structure which is evacuated so that a vacuum inductance is provided between each adder cavity and the structure. An energy storage system for the adder cavities includes a pulsed current source and a respective plurality of bipolar converting networks connected thereto. The bipolar high-voltage, high-repetition-rate square pulse train sets and resets the cavities.

Global and Local Translation Designs of Quantum Image Based on FRQI

NASA Astrophysics Data System (ADS)

Zhou, Ri-Gui; Tan, Canyun; Ian, Hou

2017-04-01

In this paper, two kinds of quantum image translation are designed based on FRQI, including global translation and local translation. Firstly, global translation is realized by employing adder modulo N, where all pixels in the image will be moved, and the circuit of right translation is designed. Meanwhile, left translation can also be implemented by using right translation. Complexity analysis shows that the circuits of global translation in this paper have lower complexity and cost less qubits. Secondly, local translation, consisted of single-column translation, multiple-columns translation and translation in the restricted area, is designed by adopting Gray code. In local translation, any parts of pixels in the image can be translated while other pixels remain unchanged. In order to lower complexity when the number of columns needing to be translated are more than one, multiple-columns translation is proposed, which has the approximate complexity with single-column translation. To perform multiple-columns translation, three conditions must be satisfied. In addition, all translations in this paper are cyclic.

Large-area formation of self-aligned crystalline domains of organic semiconductors on transistor channels using CONNECT

PubMed Central

Park, Steve; Giri, Gaurav; Shaw, Leo; Pitner, Gregory; Ha, Jewook; Koo, Ja Hoon; Gu, Xiaodan; Park, Joonsuk; Lee, Tae Hoon; Nam, Ji Hyun; Hong, Yongtaek; Bao, Zhenan

2015-01-01

The electronic properties of solution-processable small-molecule organic semiconductors (OSCs) have rapidly improved in recent years, rendering them highly promising for various low-cost large-area electronic applications. However, practical applications of organic electronics require patterned and precisely registered OSC films within the transistor channel region with uniform electrical properties over a large area, a task that remains a significant challenge. Here, we present a technique termed “controlled OSC nucleation and extension for circuits” (CONNECT), which uses differential surface energy and solution shearing to simultaneously generate patterned and precisely registered OSC thin films within the channel region and with aligned crystalline domains, resulting in low device-to-device variability. We have fabricated transistor density as high as 840 dpi, with a yield of 99%. We have successfully built various logic gates and a 2-bit half-adder circuit, demonstrating the practical applicability of our technique for large-scale circuit fabrication. PMID:25902502

Cross-neutralisation of Australian brown snake, taipan and death adder venoms by monovalent antibodies.

PubMed

Isbister, Geoffrey K; O'Leary, Margaret A; Hagan, Jessica; Nichols, Kearney; Jacoby, Tammy; Davern, Kathleen; Hodgson, Wayne C; Schneider, Jennifer J

2010-01-08

An understanding of the cross-neutralisation of snake venoms by antibodies is important for snake antivenom development. We investigated the cross-neutralisation of brown snake (Pseudonaja textilis) venom, taipan (Oxyuranus scutellatus) venom and death adder (Acanthophis antarcticus) with commercial antivenoms and monovalent anti-snake IgG, using enzyme immunoassays, in vitro clotting and neurotoxicity assays. Each commercial antivenom bound all three venoms, and neutralised clotting activity of brown snake and taipan venoms and neurotoxicity of death adder venom. The 'in-house' monovalent anti-snake venom IgG raised against procoagulant brown snake and taipan venoms, did not neutralise the neurotoxic effects of death adder venom. However, they did cross-neutralise the procoagulant effects of both procoagulant venoms. This supports the idea of developing antivenoms against groups of snake toxins rather than individual snake venoms.

Encoding Schemes For A Digital Optical Multiplier Using The Modified Signed-Digit Number Representation

NASA Astrophysics Data System (ADS)

Lasher, Mark E.; Henderson, Thomas B.; Drake, Barry L.; Bocker, Richard P.

1986-09-01

The modified signed-digit (MSD) number representation offers full parallel, carry-free addition. A MSD adder has been described by the authors. This paper describes how the adder can be used in a tree structure to implement an optical multiply algorithm. Three different optical schemes, involving position, polarization, and intensity encoding, are proposed for realizing the trinary logic system. When configured in the generic multiplier architecture, these schemes yield the combinatorial logic necessary to carry out the multiplication algorithm. The optical systems are essentially three dimensional arrangements composed of modular units. Of course, this modularity is important for design considerations, while the parallelism and noninterfering communication channels of optical systems are important from the standpoint of reduced complexity. The authors have also designed electronic hardware to demonstrate and model the combinatorial logic required to carry out the algorithm. The electronic and proposed optical systems will be compared in terms of complexity and speed.

Inductive voltage adder (IVA) for submillimeter radius electron beam

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mazarakis, M.G.; Poukey, J.W.; Maenchen, J.E.

The authors have already demonstrated the utility of inductive voltage adder accelerators for production of small-size electron beams. In this approach, the inductive voltage adder drives a magnetically immersed foilless diode to produce high-energy (10--20 MeV), high-brightness pencil electron beams. This concept was first demonstrated with the successful experiments which converted the linear induction accelerator RADLAC II into an IVA fitted with a small 1-cm radius cathode magnetically immersed foilless diode (RADLAC II/SMILE). They present here first validations of extending this idea to mm-scale electron beams using the SABRE and HERMES-III inductive voltage adders as test beds. The SABRE experimentsmore » are already completed and have produced 30-kA, 9-MeV electron beams with envelope diameter of 1.5-mm FWHM. The HERMES-III experiments are currently underway.« less

Demonstration of an optoelectronic interconnect architecture for a parallel modified signed-digit adder and subtracter

NASA Astrophysics Data System (ADS)

Sun, Degui; Wang, Na-Xin; He, Li-Ming; Weng, Zhao-Heng; Wang, Daheng; Chen, Ray T.

1996-06-01

A space-position-logic-encoding scheme is proposed and demonstrated. This encoding scheme not only makes the best use of the convenience of binary logic operation, but is also suitable for the trinary property of modified signed- digit (MSD) numbers. Based on the space-position-logic-encoding scheme, a fully parallel modified signed-digit adder and subtractor is built using optoelectronic switch technologies in conjunction with fiber-multistage 3D optoelectronic interconnects. Thus an effective combination of a parallel algorithm and a parallel architecture is implemented. In addition, the performance of the optoelectronic switches used in this system is experimentally studied and verified. Both the 3-bit experimental model and the experimental results of a parallel addition and a parallel subtraction are provided and discussed. Finally, the speed ratio between the MSD adder and binary adders is discussed and the advantage of the MSD in operating speed is demonstrated.

The adder (Vipera berus) in Southern Altay Mountains: population characteristics, distribution, morphology and phylogenetic position

PubMed Central

Cui, Shaopeng; Luo, Xiao; Chen, Daiqiang; Sun, Jizhou; Chu, Hongjun

2016-01-01

As the most widely distributed snake in Eurasia, the adder (Vipera berus) has been extensively investigated in Europe but poorly understood in Asia. The Southern Altay Mountains represent the adder’s southern distribution limit in Central Asia, whereas its population status has never been assessed. We conducted, for the first time, field surveys for the adder at two areas of Southern Altay Mountains using a combination of line transects and random searches. We also described the morphological characteristics of the collected specimens and conducted analyses of external morphology and molecular phylogeny. The results showed that the adder distributed in both survey sites and we recorded a total of 34 sightings. In Kanas river valley, the estimated encounter rate over a total of 137 km transects was 0.15 ± 0.05 sightings/km. The occurrence of melanism was only 17%. The small size was typical for the adders in Southern Altay Mountains in contrast to other geographic populations of the nominate subspecies. A phylogenetic tree obtained by Bayesian Inference based on DNA sequences of the mitochondrial cytochrome b (1,023 bp) grouped them within the Northern clade of the species but failed to separate them from the subspecies V. b. sachalinensis. Our discovery extends the distribution range of V. berus and provides a basis for further researches. We discuss the hypothesis that the adder expands its distribution border to the southwest along the mountains’ elevation gradient, but the population abundance declines gradually due to a drying climate. PMID:27602300

Morphology, Reproduction and Diet in Australian and Papuan Death Adders (Acanthophis, Elapidae)

PubMed Central

Shine, Richard; Spencer, Carol L.; Keogh, J. Scott

2014-01-01

Death adders (genus Acanthophis) differ from most other elapid snakes, and resemble many viperid snakes, in their thickset morphology and ambush foraging mode. Although these snakes are widely distributed through Australia and Papua New Guinea, their basic biology remains poorly known. We report morphological and ecological data based upon dissection of >750 museum specimens drawn from most of the range of the genus. Female death adders grow larger than conspecific males, to about the same extent in all taxa (20% in mean adult snout-vent length,  =  SVL). Most museum specimens were adult rather than juvenile animals, and adult males outnumbered females in all taxa except A. pyrrhus. Females have shorter tails (relative to SVL) than males, and longer narrower heads (relative to head length) in some but not all species. The southern A. antarcticus is wider-bodied (relative to SVL) than the other Australian species. Fecundity of these viviparous snakes was similar among taxa (mean litter sizes 8 to 14). Death adders encompass a broad range of ecological attributes, taking a wide variety of vertebrate prey, mostly lizards (55%), frogs and mammals (each 21%; based on 217 records). Dietary composition differed among species (e.g. frogs were more common in tropical than temperate-zone species), and shifted with snake body size (endotherms were taken by larger snakes) and sex (male death adders took more lizards than did females). Overall, death adders take a broader array of prey types, including active fast-moving taxa such as endotherms and large diurnal skinks, than do most other Australian elapids of similar body sizes. Ambush foraging is the key to capturing such elusive prey. PMID:24718608

Morphology, reproduction and diet in Australian and Papuan death adders (Acanthophis, Elapidae).

PubMed

Shine, Richard; Spencer, Carol L; Keogh, J Scott

2014-01-01

Death adders (genus Acanthophis) differ from most other elapid snakes, and resemble many viperid snakes, in their thickset morphology and ambush foraging mode. Although these snakes are widely distributed through Australia and Papua New Guinea, their basic biology remains poorly known. We report morphological and ecological data based upon dissection of >750 museum specimens drawn from most of the range of the genus. Female death adders grow larger than conspecific males, to about the same extent in all taxa (20% in mean adult snout-vent length,  =  SVL). Most museum specimens were adult rather than juvenile animals, and adult males outnumbered females in all taxa except A. pyrrhus. Females have shorter tails (relative to SVL) than males, and longer narrower heads (relative to head length) in some but not all species. The southern A. antarcticus is wider-bodied (relative to SVL) than the other Australian species. Fecundity of these viviparous snakes was similar among taxa (mean litter sizes 8 to 14). Death adders encompass a broad range of ecological attributes, taking a wide variety of vertebrate prey, mostly lizards (55%), frogs and mammals (each 21%; based on 217 records). Dietary composition differed among species (e.g. frogs were more common in tropical than temperate-zone species), and shifted with snake body size (endotherms were taken by larger snakes) and sex (male death adders took more lizards than did females). Overall, death adders take a broader array of prey types, including active fast-moving taxa such as endotherms and large diurnal skinks, than do most other Australian elapids of similar body sizes. Ambush foraging is the key to capturing such elusive prey.

Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits

PubMed Central

Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

2014-01-01

Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits. PMID:24463956

Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits.

PubMed

Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

2014-01-27

Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.

A decimal carry-free adder

NASA Astrophysics Data System (ADS)

Nikmehr, Hooman; Phillips, Braden; Lim, Cheng-Chew

2005-02-01

Recently, decimal arithmetic has become attractive in the financial and commercial world including banking, tax calculation, currency conversion, insurance and accounting. Although computers are still carrying out decimal calculation using software libraries and binary floating-point numbers, it is likely that in the near future, all processors will be equipped with units performing decimal operations directly on decimal operands. One critical building block for some complex decimal operations is the decimal carry-free adder. This paper discusses the mathematical framework of the addition, introduces a new signed-digit format for representing decimal numbers and presents an efficient architectural implementation. Delay estimation analysis shows that the adder offers improved performance over earlier designs.

Fatal attraction: adaptations to prey on native frogs imperil snakes after invasion of toxic toads.

PubMed

Hagman, Mattias; Phillips, Benjamin L; Shine, Richard

2009-08-07

Adaptations that enhance fitness in one situation can become liabilities if circumstances change. In tropical Australia, native snake species are vulnerable to the invasion of toxic cane toads. Death adders (Acanthophis praelongus) are ambush foragers that (i) attract vertebrate prey by caudal luring and (ii) handle anuran prey by killing the frog then waiting until the frog's chemical defences degrade before ingesting it. These tactics render death adders vulnerable to toxic cane toads (Bufo marinus), because toads elicit caudal luring more effectively than do native frogs, and are more readily attracted to the lure. Moreover, the strategy of delaying ingestion of a toad after the strike does not prevent fatal poisoning, because toad toxins (unlike those of native frogs) do not degrade shortly after the prey dies. In our laboratory and field trials, half of the death adders died after ingesting a toad, showing that the specialized predatory behaviours death adders use to capture and process prey render them vulnerable to this novel prey type. The toads' strong response to caudal luring also renders them less fit than native anurans (which largely ignored the lure): all toads bitten by adders died. Together, these results illustrate the dissonance in behavioural adaptations that can arise following the arrival of invasive species, and reveal the strong selection that occurs when mutually naive species first interact.

8-Channel acquisition system for Time-Correlated Single-Photon Counting.

PubMed

Antonioli, S; Miari, L; Cuccato, A; Crotti, M; Rech, I; Ghioni, M

2013-06-01

Nowadays, an increasing number of applications require high-performance analytical instruments capable to detect the temporal trend of weak and fast light signals with picosecond time resolution. The Time-Correlated Single-Photon Counting (TCSPC) technique is currently one of the preferable solutions when such critical optical signals have to be analyzed and it is fully exploited in biomedical and chemical research fields, as well as in security and space applications. Recent progress in the field of single-photon detector arrays is pushing research towards the development of high performance multichannel TCSPC systems, opening the way to modern time-resolved multi-dimensional optical analysis. In this paper we describe a new 8-channel high-performance TCSPC acquisition system, designed to be compact and versatile, to be used in modern TCSPC measurement setups. We designed a novel integrated circuit including a multichannel Time-to-Amplitude Converter with variable full-scale range, a D∕A converter, and a parallel adder stage. The latter is used to adapt each converter output to the input dynamic range of a commercial 8-channel Analog-to-Digital Converter, while the integrated DAC implements the dithering technique with as small as possible area occupation. The use of this monolithic circuit made the design of a scalable system of very small dimensions (95 × 40 mm) and low power consumption (6 W) possible. Data acquired from the TCSPC measurement are digitally processed and stored inside an FPGA (Field-Programmable Gate Array), while a USB transceiver allows real-time transmission of up to eight TCSPC histograms to a remote PC. Eventually, the experimental results demonstrate that the acquisition system performs TCSPC measurements with high conversion rate (up to 5 MHz/channel), extremely low differential nonlinearity (<0.04 peak-to-peak of the time bin width), high time resolution (down to 20 ps Full-Width Half-Maximum), and very low crosstalk between channels.

Digital high speed programmable convolver

NASA Astrophysics Data System (ADS)

Rearick, T. C.

1984-12-01

A circuit module for rapidly calculating a discrete numerical convolution is described. A convolution such as finding the sum of the products of a 16 bit constant and a 16 bit variable is performed by a module which is programmable so that the constant may be changed for a new problem. In addition, the module may be programmed to find the sum of the products of 4 and 8 bit constants and variables. RAM (Random Access Memories) are loaded with partial products of the selected constant and all possible variables. Then, when the actual variable is loaded, it acts as an address to find the correct partial product in the particular RAM. The partial products from all of the RAMs are shifted to the appropriate numerical power position (if necessary) and then added in adder elements.

Design and Performance Investigation for the Optical Combinational Networks at High Data Rate

NASA Astrophysics Data System (ADS)

Tripathi, Devendra Kr.

2017-05-01

This article explores performance study for optical combinational designs based on nonlinear characteristics with semiconductor optical amplifier (SOA). Two configurations for optical half-adder with non-return-to-zero modulation pattern altogether with Mach-Zehnder modulator, interferometer at 50-Gbps data rate have been successfully realized. Accordingly, SUM and CARRY outputs have been concurrently executed and verified for their output waveforms. Numerical simulations for variation of data rate and key design parameters have been effectively executed outcome with optimum performance. Investigations depict overall good performance of the design in terms of the extinction factor. It also inferred that all-optical realization based on SOA is competent scheme, as it circumvents costly optoelectronic translation. This could be well supportive to erect larger complex optical combinational circuits.

Mise en oeuvre et caracterisation d'une methode d'injection de pannes a haut niveau d'abstraction

NASA Astrophysics Data System (ADS)

Robache, Remi

Nowadays, the effects of cosmic rays on electronics are well known. Different studies have demonstrated that neutrons are the main cause of non-destructive errors in embedded circuits on airplanes. Moreover, the reduction of transistor sizes is making all circuits more sensitive to those effects. Radiation tolerant circuits are sometimes used in order to improve the robustness of circuits. However, those circuits are expensive and their technologies often lag a few generations behind compared to non-tolerant circuits. Designers prefer to use conventional circuits with mitigation techniques to improve the tolerance to soft errors. It is necessary to analyse and verify the dependability of a circuit throughout its design process. Conventional design methodologies need to be adapted in order to evaluate the tolerance to non-destructive errors caused by radiations. Nowadays, designers need new tools and new methodologies to validate their mitigation strategies if they are to meet system requirements. In this thesis, we are proposing a new methodology allowing to capture the faulty behavior of a circuit at a low level of abstraction and to apply it at a higher level. In order to do that, we are introducing the new concept of faulty behavior Signatures that allows creating, at a high level of abstraction (system level) models that reflect with high fidelity the faulty behavior of a circuit learned at a low level of abstraction, at gate level. We successfully replicated the faulty behavior of an 8 bit adder and multiplier with Simulink, with respectively a correlation coefficient of 98.53% and 99.86%. We are proposing a methodology that permits to generate a library of faulty components, with Simulink, allowing designers to verify the dependability of their models early in the design flow. We are presenting and analyzing our results obtained for three different circuits throughout this thesis. Within the framework of this project a paper was published at the NEWCAS 2013 conference (Robache et al., 2013). This works presents the new concept of faulty behavior Signature, the methodology for generating Signatures we developed and also our experiments with an 8bit multiplier.

Adder bite: an uncommon cause of compartment syndrome in northern hemisphere

PubMed Central

2010-01-01

Snakebite envenomation is an uncommon condition in the northern hemisphere, but requires high vigilance with regard to both the systemic effects of the venom and the locoregional impact on the soft tissues. Bites from the adder, Vipera Berus, may have serious clinical consequences due to systemic effects. A case of a 44-year-old man is reported. The patient was bitten in the right hand. He developed fasciotomy-requiring compartment syndrome of the upper limb. Recognition of this most seldom complication of an adder bite is vital to save the limb. We recommend that the classical signs and symptoms of compartment syndrome serve as indication for surgical decompression. PMID:20854675

Estimating the circuit delay of FPGA with a transfer learning method

NASA Astrophysics Data System (ADS)

Cui, Xiuhai; Liu, Datong; Peng, Yu; Peng, Xiyuan

2017-10-01

With the increase of FPGA (Field Programmable Gate Array, FPGA) functionality, FPGA has become an on-chip system platform. Due to increase the complexity of FPGA, estimating the delay of FPGA is a very challenge work. To solve the problems, we propose a transfer learning estimation delay (TLED) method to simplify the delay estimation of different speed grade FPGA. In fact, the same style different speed grade FPGA comes from the same process and layout. The delay has some correlation among different speed grade FPGA. Therefore, one kind of speed grade FPGA is chosen as a basic training sample in this paper. Other training samples of different speed grade can get from the basic training samples through of transfer learning. At the same time, we also select a few target FPGA samples as training samples. A general predictive model is trained by these samples. Thus one kind of estimation model is used to estimate different speed grade FPGA circuit delay. The framework of TRED includes three phases: 1) Building a basic circuit delay library which includes multipliers, adders, shifters, and so on. These circuits are used to train and build the predictive model. 2) By contrasting experiments among different algorithms, the forest random algorithm is selected to train predictive model. 3) The target circuit delay is predicted by the predictive model. The Artix-7, Kintex-7, and Virtex-7 are selected to do experiments. Each of them includes -1, -2, -2l, and -3 different speed grade. The experiments show the delay estimation accuracy score is more than 92% with the TLED method. This result shows that the TLED method is a feasible delay assessment method, especially in the high-level synthesis stage of FPGA tool, which is an efficient and effective delay assessment method.

A design method for high performance seismic data acquisition based on oversampling delta-sigma modulation

NASA Astrophysics Data System (ADS)

Gao, Shanghua; Xue, Bing

2017-04-01

The dynamic range of the currently most widely used 24-bit seismic data acquisition devices is 10-20 dB lower than that of broadband seismometers, and this can affect the completeness of seismic waveform recordings under certain conditions. However, this problem is not easy to solve because of the lack of analog to digital converter (ADC) chips with more than 24 bits in the market. So the key difficulties for higher-resolution data acquisition devices lie in achieving more than 24-bit ADC circuit. In the paper, we propose a method in which an adder, an integrator, a digital to analog converter chip, a field-programmable gate array, and an existing low-resolution ADC chip are used to build a third-order 16-bit oversampling delta-sigma modulator. This modulator is equipped with a digital decimation filter, thus forming a complete analog to digital converting circuit. Experimental results show that, within the 0.1-40 Hz frequency range, the circuit board's dynamic range reaches 158.2 dB, its resolution reaches 25.99 dB, and its linearity error is below 2.5 ppm, which is better than what is achieved by the commercial 24-bit ADC chips ADS1281 and CS5371. This demonstrates that the proposed method may alleviate or even solve the amplitude-limitation problem that broadband observation systems so commonly have to face during strong earthquakes.

Hybrid VLSI/QCA Architecture for Computing FFTs

NASA Technical Reports Server (NTRS)

Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

2003-01-01

A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

DNA-programmed dynamic assembly of quantum dots for molecular computation.

PubMed

He, Xuewen; Li, Zhi; Chen, Muzi; Ma, Nan

2014-12-22

Despite the widespread use of quantum dots (QDs) for biosensing and bioimaging, QD-based bio-interfaceable and reconfigurable molecular computing systems have not yet been realized. DNA-programmed dynamic assembly of multi-color QDs is presented for the construction of a new class of fluorescence resonance energy transfer (FRET)-based QD computing systems. A complete set of seven elementary logic gates (OR, AND, NOR, NAND, INH, XOR, XNOR) are realized using a series of binary and ternary QD complexes operated by strand displacement reactions. The integration of different logic gates into a half-adder circuit for molecular computation is also demonstrated. This strategy is quite versatile and straightforward for logical operations and would pave the way for QD-biocomputing-based intelligent molecular diagnostics. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Highly efficient hybrid energy generator: coupled organic photovoltaic device and randomly oriented electrospun poly(vinylidene fluoride) nanofiber.

PubMed

Park, Boongik; Lee, Kihwan; Park, Jongjin; Kim, Jongmin; Kim, Ohyun

2013-03-01

A hybrid architecture consisting of an inverted organic photovoltaic device and a randomly-oriented electrospun PVDF piezoelectric device was fabricated as a highly-efficient energy generator. It uses the inverted photovoltaic device with coupled electrospun PVDF nanofibers as tandem structure to convert solar and mechanical vibrations energy to electricity simultaneously or individually. The power conversion efficiency of the photovoltaic device was also significantly improved up to 4.72% by optimized processes such as intrinsic ZnO, MoO3 and active layer. A simple electrospinning method with the two electrode technique was adopted to achieve a high voltage of - 300 mV in PVDF piezoelectric fibers. Highly-efficient HEG using voltage adder circuit provides the conceptual possibility of realizing multi-functional energy generator whenever and wherever various energy sources are available.

Mississippi | Midmarket Solar Policies in the United States | Solar

Science.gov Websites

DG adder of $0.025/kWh (total estimated 7 to 7.5 cents per kWh) RECs: The customer retains ownership of RECs. If the customer receives benefits from the DG adder while selling electricity to the utility , then the RECs are transferred from the customer to the utility. Meter aggregation: Not specified

A learnable parallel processing architecture towards unity of memory and computing

NASA Astrophysics Data System (ADS)

Li, H.; Gao, B.; Chen, Z.; Zhao, Y.; Huang, P.; Ye, H.; Liu, L.; Liu, X.; Kang, J.

2015-08-01

Developing energy-efficient parallel information processing systems beyond von Neumann architecture is a long-standing goal of modern information technologies. The widely used von Neumann computer architecture separates memory and computing units, which leads to energy-hungry data movement when computers work. In order to meet the need of efficient information processing for the data-driven applications such as big data and Internet of Things, an energy-efficient processing architecture beyond von Neumann is critical for the information society. Here we show a non-von Neumann architecture built of resistive switching (RS) devices named “iMemComp”, where memory and logic are unified with single-type devices. Leveraging nonvolatile nature and structural parallelism of crossbar RS arrays, we have equipped “iMemComp” with capabilities of computing in parallel and learning user-defined logic functions for large-scale information processing tasks. Such architecture eliminates the energy-hungry data movement in von Neumann computers. Compared with contemporary silicon technology, adder circuits based on “iMemComp” can improve the speed by 76.8% and the power dissipation by 60.3%, together with a 700 times aggressive reduction in the circuit area.

Programmable single-cell mammalian biocomputers.

PubMed

Ausländer, Simon; Ausländer, David; Müller, Marius; Wieland, Markus; Fussenegger, Martin

2012-07-05

Synthetic biology has advanced the design of standardized control devices that program cellular functions and metabolic activities in living organisms. Rational interconnection of these synthetic switches resulted in increasingly complex designer networks that execute input-triggered genetic instructions with precision, robustness and computational logic reminiscent of electronic circuits. Using trigger-controlled transcription factors, which independently control gene expression, and RNA-binding proteins that inhibit the translation of transcripts harbouring specific RNA target motifs, we have designed a set of synthetic transcription–translation control devices that could be rewired in a plug-and-play manner. Here we show that these combinatorial circuits integrated a two-molecule input and performed digital computations with NOT, AND, NAND and N-IMPLY expression logic in single mammalian cells. Functional interconnection of two N-IMPLY variants resulted in bitwise intracellular XOR operations, and a combinatorial arrangement of three logic gates enabled independent cells to perform programmable half-subtractor and half-adder calculations. Individual mammalian cells capable of executing basic molecular arithmetic functions isolated or coordinated to metabolic activities in a predictable, precise and robust manner may provide new treatment strategies and bio-electronic interfaces in future gene-based and cell-based therapies.

A learnable parallel processing architecture towards unity of memory and computing.

PubMed

Li, H; Gao, B; Chen, Z; Zhao, Y; Huang, P; Ye, H; Liu, L; Liu, X; Kang, J

2015-08-14

Developing energy-efficient parallel information processing systems beyond von Neumann architecture is a long-standing goal of modern information technologies. The widely used von Neumann computer architecture separates memory and computing units, which leads to energy-hungry data movement when computers work. In order to meet the need of efficient information processing for the data-driven applications such as big data and Internet of Things, an energy-efficient processing architecture beyond von Neumann is critical for the information society. Here we show a non-von Neumann architecture built of resistive switching (RS) devices named "iMemComp", where memory and logic are unified with single-type devices. Leveraging nonvolatile nature and structural parallelism of crossbar RS arrays, we have equipped "iMemComp" with capabilities of computing in parallel and learning user-defined logic functions for large-scale information processing tasks. Such architecture eliminates the energy-hungry data movement in von Neumann computers. Compared with contemporary silicon technology, adder circuits based on "iMemComp" can improve the speed by 76.8% and the power dissipation by 60.3%, together with a 700 times aggressive reduction in the circuit area.

Design of a Radiographic Integrated Test Stand (RITS) Based on a Voltage Adder, To Drive a Diode Immersed in a High Magnetic Field

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bailey, V.L.; Corcoran, P.; Droemer, D.

Recent experiments (1) have adapted existing magne-tically insulated induction voltage adders (Sabre, Hermes III) to drive a 10 MV diode immersed in magnetic fields as high as 50 T. In such a diode, an electron beam of tens of kA can be confined by the magnetic field to a diameter of about 1 mm, and when it strikes a high-Z anode it can create a bremsstrahlung x-ray source intense enough to radiograph massive objects with high resolution. RITS is an adder system designed specially to drive such diodes, and it will be used to develop and exploit them. As inmore » other adder-based pulsers such as Sabre, Hermes III, and Kalif-Heliq the induction cells have amorphous- iron cores, and the pulse-forming system consists of water dielectric pulse lines and self-closing water switches that are pulse-charged from Marx-charged intermediate water capacitors through laser-triggered Rimfire switches. An oil prepulse switch in series with each pulse line is designed to reduce cathode prepulse to less than ± 5 kV, and a means is provided to bias the cathode and avoid negative prepulse entirely. The RITS pulse-forming system consists of two modules. Each module has one Marx that charges two 3 MV intermediate stores, each of which charges three 7.8 ohm pulselines, making six pulselines per module. The two modules in concert can supply 1.35 MV, 50 ns pulses to a twelve-cell adder and thus drive a 16 MV diode with a single pulse. The 1.35 MV induction cells each have a single-point feed, from which a single, slotted azimuthal oil transmission line distributes energy uniformly around the cell. The modules can also be pulsed separately at different times, either to power two 8 MV adders that each drive one of two closely-spaced cathodes immersed in a common magnetic field, or to provide two separate pulses to a common six- cell adder and a single 8 NIV diode; in these two-pulse modes, the spacing of the two 50 ns pulses may be chosen to be anything from a few hundred ns upward. The use of only one pulse line per cell has been shown to increase the extent to which the cell voltages can vary with the timing of closure of the water switches. This and all other functions of RITS have been simulated in detail, and a conservative electrical design has been developed. This will be illustrated, along with the conceptual design of a pulse-sorting network that can couple two pulselines efilciently to one cell when the two RITS modules drive a common adder in two-pulse mode.« less

Exploring hurdles to transfer : student experiences of applying knowledge across disciplines

NASA Astrophysics Data System (ADS)

Lappalainen, Jouni; Rosqvist, Juho

2015-04-01

This paper explores the ways students perceive the transfer of learned knowledge to new situations - often a surprisingly difficult prospect. The novel aspect compared to the traditional transfer studies is that the learning phase is not a part of the experiment itself. The intention was only to activate acquired knowledge relevant to the transfer target using a short primer immediately prior to the situation where the knowledge was to be applied. Eight volunteer students from either mathematics or computer science curricula were given a task of designing an adder circuit using logic gates: a new context in which to apply knowledge of binary arithmetic and Boolean algebra. The results of a phenomenographic classification of the views presented by the students in their post-experiment interviews are reported. The degree to which the students were conscious of the acquired knowledge they employed and how they applied it in a new context emerged as the differentiating factors.

Graphene barristor, a triode device with a gate-controlled Schottky barrier.

PubMed

Yang, Heejun; Heo, Jinseong; Park, Seongjun; Song, Hyun Jae; Seo, David H; Byun, Kyung-Eun; Kim, Philip; Yoo, InKyeong; Chung, Hyun-Jong; Kim, Kinam

2012-06-01

Despite several years of research into graphene electronics, sufficient on/off current ratio I(on)/I(off) in graphene transistors with conventional device structures has been impossible to obtain. We report on a three-terminal active device, a graphene variable-barrier "barristor" (GB), in which the key is an atomically sharp interface between graphene and hydrogenated silicon. Large modulation on the device current (on/off ratio of 10(5)) is achieved by adjusting the gate voltage to control the graphene-silicon Schottky barrier. The absence of Fermi-level pinning at the interface allows the barrier's height to be tuned to 0.2 electron volt by adjusting graphene's work function, which results in large shifts of diode threshold voltages. Fabricating GBs on respective 150-mm wafers and combining complementary p- and n-type GBs, we demonstrate inverter and half-adder logic circuits.

VLSI processors for signal detection in SETI

NASA Technical Reports Server (NTRS)

Duluk, J. F.; Linscott, I. R.; Peterson, A. M.; Burr, J.; Ekroot, B.; Twicken, J.

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

VLSI processors for signal detection in SETI.

PubMed

Duluk, J F; Linscott, I R; Peterson, A M; Burr, J; Ekroot, B; Twicken, J

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

Reconfigurable logic in nanosecond Cu/GeTe/TiN filamentary memristors for energy-efficient in-memory computing.

PubMed

Jin, Miaomiao; Cheng, Long; Li, Yi; Hu, Siyu; Lu, Ke; Chen, Jia; Duan, Nian; Wang, Zhuorui; Zhou, Yaxiong; Chang, Ting-Chang; Miao, Xiangshui

2018-06-27

Owing to the capability of integrating the information storage and computing in the same physical location, in-memory computing with memristors has become a research hotspot as a promising route for non von Neumann architecture. However, it is still a challenge to develop high performance devices as well as optimized logic methodologies to realize energy-efficient computing. Herein, filamentary Cu/GeTe/TiN memristor is reported to show satisfactory properties with nanosecond switching speed (< 60 ns), low voltage operation (< 2 V), high endurance (>104 cycles) and good retention (>104 s @85℃). It is revealed that the charge carrier conduction mechanisms in high resistance and low resistance states are Schottky emission and hopping transport between the adjacent Cu clusters, respectively, based on the analysis of current-voltage behaviors and resistance-temperature characteristics. An intuitive picture is given to describe the dynamic processes of resistive switching. Moreover, based on the basic material implication (IMP) logic circuit, we proposed a reconfigurable logic method and experimentally implemented IMP, NOT, OR, and COPY logic functions. Design of a one-bit full adder with reduction in computational sequences and its validation in simulation further demonstrate the potential practical application. The results provide important progress towards understanding of resistive switching mechanism and realization of energy-efficient in-memory computing architecture. © 2018 IOP Publishing Ltd.

A 16X16 Discrete Cosine Transform Chip

NASA Astrophysics Data System (ADS)

Sun, M. T.; Chen, T. C.; Gottlieb, A.; Wu, L.; Liou, M. L.

1987-10-01

Among various transform coding techniques for image compression the Discrete Cosine Transform (DCT) is considered to be the most effective method and has been widely used in the laboratory as well as in the market, place. DCT is computationally intensive. For video application at 14.3 MHz sample rate, a direct implementation of a 16x16 DCT requires a throughput, rate of approximately half a billion multiplications per second. In order to reduce the cost of hardware implementation, a single chip DCT implementation is highly desirable. In this paper, the implementation of a 16x16 DCT chip using a concurrent architecture will be presented. The chip is designed for real-time processing of 14.3 MHz sampled video data. It uses row-column decomposition to implement the two-dimensional transform. Distributed arithmetic combined with hit-serial and hit-parallel structures is used to implement the required vector inner products concurrently. Several schemes are utilized to reduce the size of required memory. The resultant circuit only uses memory, shift registers, and adders. No multipliers are required. It achieves high speed performance with a very regular and efficient integrated circuit realization. The chip accepts 0-bit input and produces 14-bit DCT coefficients. 12 bits are maintained after the first one-dimensional transform. The circuit has been laid out using a 2-μm CMOS technology with a symbolic design tool MULGA. The core contains approximately 73,000 transistors in an area of 7.2 x 7.0

Multi-valued logic gates based on ballistic transport in quantum point contacts.

PubMed

Seo, M; Hong, C; Lee, S-Y; Choi, H K; Kim, N; Chung, Y; Umansky, V; Mahalu, D

2014-01-22

Multi-valued logic gates, which can handle quaternary numbers as inputs, are developed by exploiting the ballistic transport properties of quantum point contacts in series. The principle of a logic gate that finds the minimum of two quaternary number inputs is demonstrated. The device is scalable to allow multiple inputs, which makes it possible to find the minimum of multiple inputs in a single gate operation. Also, the principle of a half-adder for quaternary number inputs is demonstrated. First, an adder that adds up two quaternary numbers and outputs the sum of inputs is demonstrated. Second, a device to express the sum of the adder into two quaternary digits [Carry (first digit) and Sum (second digit)] is demonstrated. All the logic gates presented in this paper can in principle be extended to allow decimal number inputs with high quality QPCs.

Self-Assembly of Large Amyloid Fibers

NASA Astrophysics Data System (ADS)

Ridgley, Devin M.

Functional amyloids found throughout nature have demonstrated that amyloid fibers are potential industrial biomaterials. This work introduces a new "template plus adder" cooperative mechanism for the spontaneous self-assembly of micrometer sized amyloid fibers. A short hydrophobic template peptide induces a conformation change within a highly alpha-helical adder protein to form beta-sheets that continue to assemble into micrometer sized amyloid fibers. This study utilizes a variety of proteins that have template or adder characteristics which suggests that this mechanism may be employed throughout nature. Depending on the amino acid composition of the proteins used the mixtures form amyloid fibers of a cylindrical ( 10 mum diameter, 2 GPa Young's modulus) or tape (5- 10 mum height, 10-20 mum width and 100-200 MPa Young's modulus) morphology. Processing conditions are altered to manipulate the morphology and structural characteristics of the fibers. Spectroscopy is utilized to identify certain amino acid groups that contribute to the self-assembly process. Aliphatic amino acids (A, I, V and L) are responsible for initiating conformation change of the adder proteins to assemble into amyloid tapes. Additional polyglutamine segments (Q-blocks) within the protein mixtures will form Q hydrogen bonds to reinforce the amyloid structure and form a cylindrical fiber of higher modulus. Atomic force microscopy is utilized to delineate the self-assembly of amyloid tapes and cylindrical fibers from protofibrils (15-30 nm width) to fibers (10-20 mum width) spanning three orders of magnitude. The aliphatic amino acid content of the adder proteins' alpha-helices is a good predictor of high density beta-sheet formation within the protein mixture. Thus, it is possible to predict the propensity of a protein to undergo conformation change into amyloid structures. Finally, Escherichia coli is genetically engineered to express a template protein which self-assembles into large amyloid fibers when combined with extracellular myoglobin, an adder protein. The goal of this thesis is to produce, manipulate and characterize the self-assembly of large amyloid fibers for their potential industrial biomaterial applications. The techniques used throughout this study outline various methods to design and engineer amyloid fibers of a tailored modulus and morphology. Furthermore, the mechanisms described here may offer some insight into naturally occurring amyloid forming systems.

An optimal adder-based hardware architecture for the DCT/SA-DCT

NASA Astrophysics Data System (ADS)

Kinane, Andrew; Muresan, Valentin; O'Connor, Noel

2005-07-01

The explosive growth of the mobile multimedia industry has accentuated the need for ecient VLSI implemen- tations of the associated computationally demanding signal processing algorithms. This need becomes greater as end-users demand increasingly enhanced features and more advanced underpinning video analysis. One such feature is object-based video processing as supported by MPEG-4 core profile, which allows content-based in- teractivity. MPEG-4 has many computationally demanding underlying algorithms, an example of which is the Shape Adaptive Discrete Cosine Transform (SA-DCT). The dynamic nature of the SA-DCT processing steps pose significant VLSI implementation challenges and many of the previously proposed approaches use area and power consumptive multipliers. Most also ignore the subtleties of the packing steps and manipulation of the shape information. We propose a new multiplier-less serial datapath based solely on adders and multiplexers to improve area and power. The adder cost is minimised by employing resource re-use methods. The number of (physical) adders used has been derived using a common sub-expression elimination algorithm. Additional energy eciency is factored into the design by employing guarded evaluation and local clock gating. Our design implements the SA-DCT packing with minimal switching using ecient addressing logic with a transpose mem- ory RAM. The entire design has been synthesized using TSMC 0.09µm TCBN90LP technology yielding a gate count of 12028 for the datapath and its control logic.

Quantum dot ternary-valued full-adder: Logic synthesis by a multiobjective design optimization based on a genetic algorithm

DOE Office of Scientific and Technical Information (OSTI.GOV)

Klymenko, M. V.; Remacle, F., E-mail: fremacle@ulg.ac.be

2014-10-28

A methodology is proposed for designing a low-energy consuming ternary-valued full adder based on a quantum dot (QD) electrostatically coupled with a single electron transistor operating as a charge sensor. The methodology is based on design optimization: the values of the physical parameters of the system required for implementing the logic operations are optimized using a multiobjective genetic algorithm. The searching space is determined by elements of the capacitance matrix describing the electrostatic couplings in the entire device. The objective functions are defined as the maximal absolute error over actual device logic outputs relative to the ideal truth tables formore » the sum and the carry-out in base 3. The logic units are implemented on the same device: a single dual-gate quantum dot and a charge sensor. Their physical parameters are optimized to compute either the sum or the carry out outputs and are compatible with current experimental capabilities. The outputs are encoded in the value of the electric current passing through the charge sensor, while the logic inputs are supplied by the voltage levels on the two gate electrodes attached to the QD. The complex logic ternary operations are directly implemented on an extremely simple device, characterized by small sizes and low-energy consumption compared to devices based on switching single-electron transistors. The design methodology is general and provides a rational approach for realizing non-switching logic operations on QD devices.« less

An approach to the optical MSD adder

NASA Astrophysics Data System (ADS)

Takahashi, Hideya; Matsushita, Kenji; Shimizu, Eiji

1990-07-01

The intrinsic parallelism of optical elements for computation is presently taken fuller advantage of than heretofore possible through an optical implementation of the modified signed digit (MSD) number system, which yields carry-free addition and subtraction. In the present optical implementation of the MSD system, optical phase data are used to preclude negative value representation. Attention is given to an MSD adder array for addition operations on two n-digit trinary numbers; the output is composed of n + 1 trinary digits.

[An overview on envenomings inflicted by the Common adder (Vipera berus) and their treatment in Hungary. Facts and beliefs -- part I].

PubMed

Malina, Tamás; Babocsay, Gergely; Krecsák, László; Schuller, Péter; Zacher, Gábor; Vasas, Gábor

2012-07-15

Consequences of bites by the Common adder (Vipera berus) were reviewed in this study. Patients bitten by snakes from different populations may develop variable symptoms due to geographical venom variation. The correct diagnosis of snake bites and the knowledge of the distribution of venomous snake taxa have a crucial impact on snake bite therapy. The characteristic symptoms of patients bitten by V. berus in Hungary are highlighted. The habitat characteristics, seasonal activity and the Hungarian distribution of the adder are described based on literature data, museum specimens and field observations. However, envenomings are uncommon in Hungary, the annual 3 to 4 incidents have to be taken seriously, regardless of the age and actual health condition of the patients. Contrary to beliefs persisting both among laymen and professionals, the venom of V. berus is powerful. Medical observation of the patients is necessary in the first 5 to 6 hours. Any systemic symptom or progression of the edema requires hospital admission.

Optical Computing. Organization of the 1993 Photonics Science Topical Meetings Held in Palm Springs, California on March 16 - 19, 1993. Technical Digest Series, Volume 7

DTIC Science & Technology

1993-03-19

network Implementation using 9:20 am asymmetric Fabry-Perot modulators, Andrew Jennings, Brian OWA3 Multiwavelength optical half adder, Pochi Yeh... multiwavelength optical half adder. (p. 68) nects. (p. 96) 9:40 am 2:50 pm OWA4 Wavelength multiplexed computer-generated volume OWC3 Content addramble...ATMOS and OSCAR are RACE projects, mentioned in the text shape this into new systems architectures, ("optical ether"). Broadly speaking, this has led to

Light-Gated Memristor with Integrated Logic and Memory Functions.

PubMed

Tan, Hongwei; Liu, Gang; Yang, Huali; Yi, Xiaohui; Pan, Liang; Shang, Jie; Long, Shibing; Liu, Ming; Wu, Yihong; Li, Run-Wei

2017-11-28

Memristive devices are able to store and process information, which offers several key advantages over the transistor-based architectures. However, most of the two-terminal memristive devices have fixed functions once made and cannot be reconfigured for other situations. Here, we propose and demonstrate a memristive device "memlogic" (memory logic) as a nonvolatile switch of logic operations integrated with memory function in a single light-gated memristor. Based on nonvolatile light-modulated memristive switching behavior, a single memlogic cell is able to achieve optical and electrical mixed basic Boolean logic of reconfigurable "AND", "OR", and "NOT" operations. Furthermore, the single memlogic cell is also capable of functioning as an optical adder and digital-to-analog converter. All the memlogic outputs are memristive for in situ data storage due to the nonvolatile resistive switching and persistent photoconductivity effects. Thus, as a memdevice, the memlogic has potential for not only simplifying the programmable logic circuits but also building memristive multifunctional optoelectronics.

Submicrosecond linear pulse transformer for 800 kV voltage with modular low-inductance primary power supply

NASA Astrophysics Data System (ADS)

Bykov, Yu. A.; Krastelev, E. G.; Popov, G. V.; Sedin, A. A.; Feduschak, V. F.

2016-12-01

A pulsed power source with voltage amplitude up to 800 kV for fast charging (350-400 ns) of the forming line of a high-current nanosecond accelerator is developed. The source includes capacitive energy storage and a linear pulse transformer. The linear transformer consists of a set of 20 inductors with circular ferromagnetic cores surrounded by primary windings inside of which a common stock adder of voltage with film-glycerol insulation is placed. The primary energy storage consists of ten modules, each of which is a low-inductance assembly of two capacitors with a capacitance of 0.35 μF and one gas switch mounted in the same frame. The total energy stored in capacitors is 5.5 kJ at the operating voltage of 40 kV. According to test results, the parameters of the equivalent circuit of the source are the following: shock capacitance = 17.5 nF, inductance = 2 μH, resistance = 3.2 Ω.

Submicrosecond linear pulse transformer for 800 kV voltage with modular low-inductance primary power supply

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bykov, Yu. A.; Krastelev, E. G., E-mail: ekrastelev@yandex.ru; Popov, G. V.

A pulsed power source with voltage amplitude up to 800 kV for fast charging (350–400 ns) of the forming line of a high-current nanosecond accelerator is developed. The source includes capacitive energy storage and a linear pulse transformer. The linear transformer consists of a set of 20 inductors with circular ferromagnetic cores surrounded by primary windings inside of which a common stock adder of voltage with film-glycerol insulation is placed. The primary energy storage consists of ten modules, each of which is a low-inductance assembly of two capacitors with a capacitance of 0.35 μF and one gas switch mounted inmore » the same frame. The total energy stored in capacitors is 5.5 kJ at the operating voltage of 40 kV. According to test results, the parameters of the equivalent circuit of the source are the following: shock capacitance = 17.5 nF, inductance = 2 μH, resistance = 3.2 Ω.« less

Multi-Agent Methods for the Configuration of Random Nanocomputers

NASA Technical Reports Server (NTRS)

Lawson, John W.

2004-01-01

As computational devices continue to shrink, the cost of manufacturing such devices is expected to grow exponentially. One alternative to the costly, detailed design and assembly of conventional computers is to place the nano-electronic components randomly on a chip. The price for such a trivial assembly process is that the resulting chip would not be programmable by conventional means. In this work, we show that such random nanocomputers can be adaptively programmed using multi-agent methods. This is accomplished through the optimization of an associated high dimensional error function. By representing each of the independent variables as a reinforcement learning agent, we are able to achieve convergence must faster than with other methods, including simulated annealing. Standard combinational logic circuits such as adders and multipliers are implemented in a straightforward manner. In addition, we show that the intrinsic flexibility of these adaptive methods allows the random computers to be reconfigured easily, making them reusable. Recovery from faults is also demonstrated.

Stochastic p -Bits for Invertible Logic

NASA Astrophysics Data System (ADS)

Camsari, Kerem Yunus; Faria, Rafatul; Sutton, Brian M.; Datta, Supriyo

2017-07-01

Conventional semiconductor-based logic and nanomagnet-based memory devices are built out of stable, deterministic units such as standard metal-oxide semiconductor transistors, or nanomagnets with energy barriers in excess of ≈40 - 60 kT . In this paper, we show that unstable, stochastic units, which we call "p -bits," can be interconnected to create robust correlations that implement precise Boolean functions with impressive accuracy, comparable to standard digital circuits. At the same time, they are invertible, a unique property that is absent in standard digital circuits. When operated in the direct mode, the input is clamped, and the network provides the correct output. In the inverted mode, the output is clamped, and the network fluctuates among all possible inputs that are consistent with that output. First, we present a detailed implementation of an invertible gate to bring out the key role of a single three-terminal transistorlike building block to enable the construction of correlated p -bit networks. The results for this specific, CMOS-assisted nanomagnet-based hardware implementation agree well with those from a universal model for p -bits, showing that p -bits need not be magnet based: any three-terminal tunable random bit generator should be suitable. We present a general algorithm for designing a Boltzmann machine (BM) with a symmetric connection matrix [J ] (Ji j=Jj i) that implements a given truth table with p -bits. The [J ] matrices are relatively sparse with a few unique weights for convenient hardware implementation. We then show how BM full adders can be interconnected in a partially directed manner (Ji j≠Jj i) to implement large logic operations such as 32-bit binary addition. Hundreds of stochastic p -bits get precisely correlated such that the correct answer out of 233 (≈8 ×1 09) possibilities can be extracted by looking at the statistical mode or majority vote of a number of time samples. With perfect directivity (Jj i=0 ) a small number of samples is enough, while for less directed connections more samples are needed, but even in the former case logical invertibility is largely preserved. This combination of digital accuracy and logical invertibility is enabled by the hybrid design that uses bidirectional BM units to construct circuits with partially directed interunit connections. We establish this key result with extensive examples including a 4-bit multiplier which in inverted mode functions as a factorizer.

The mathematics of a quantum Hamiltonian computing half adder Boolean logic gate.

PubMed

Dridi, G; Julien, R; Hliwa, M; Joachim, C

2015-08-28

The mathematics behind the quantum Hamiltonian computing (QHC) approach of designing Boolean logic gates with a quantum system are given. Using the quantum eigenvalue repulsion effect, the QHC AND, NAND, OR, NOR, XOR, and NXOR Hamiltonian Boolean matrices are constructed. This is applied to the construction of a QHC half adder Hamiltonian matrix requiring only six quantum states to fullfil a half Boolean logical truth table. The QHC design rules open a nano-architectronic way of constructing Boolean logic gates inside a single molecule or atom by atom at the surface of a passivated semi-conductor.

An ambusher's arsenal: chemical crypsis in the puff adder (Bitis arietans)

PubMed Central

Miller, Ashadee Kay; Maritz, Bryan; McKay, Shannon; Glaudas, Xavier; Alexander, Graham J.

2015-01-01

Ambush foragers use a hunting strategy that places them at risk of predation by both visual and olfaction-oriented predators. Resulting selective pressures have driven the evolution of impressive visual crypsis in many ambushing species, and may have led to the development of chemical crypsis. However, unlike for visual crypsis, few studies have attempted to demonstrate chemical crypsis. Field observations of puff adders (Bitis arietans) going undetected by several scent-orientated predator and prey species led us to investigate chemical crypsis in this ambushing species. We trained dogs (Canis familiaris) and meerkats (Suricata suricatta) to test whether a canid and a herpestid predator could detect B. arietans using olfaction. We also tested for chemical crypsis in five species of active foraging snakes, predicted to be easily detectable. Dogs and meerkats unambiguously indicated active foraging species, but failed to correctly indicate puff adder, confirming that B. arietans employs chemical crypsis. This is the first demonstration of chemical crypsis anti-predatory behaviour, though the phenomenon may be widespread among ambushers, especially those that experience high mortality rates owing to predation. Our study provides additional evidence for the existence of an ongoing chemically mediated arms race between predator and prey species. PMID:26674950

Observation of reflected waves on the SABRE positive polarity inductive adder MITL

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cuneo, M.E.; Poukey, J.W.; Mendel, C.W.

We are studying the coupling of extraction applied-B ion diodes to Magnetically Insulated Transmission Line (MITLs) on the SABRE (Sandia Accelerator and Beam Research Experiment, 6 MV, 300 kA) positive polarity inductive voltage adder. Our goal is to determine conditions under which efficient coupling occurs. The best total power efficiency for an ideal ion diode load (i.e., without parasitic losses) is obtained by maximizing the product of cathode current and gap voltage. MITLs require that the load impedance be undermatched to the self-limited line operating impedance for efficient transfer of power to ion diodes, independent of transit time isolation, andmore » even in the case of multiple cathode system with significant vacuum electron flow. We observe that this undermatched condition results in a reflected wave which decreases the line voltage and gap electron sheath current, and increases the anode and cathode current in a time-dependent way. The MITL diode coupling is determined by the flow impedance at the adder exit. We also show that the flow impedance increases along the extension MITL on SABRE. Experimental measurements of current and peak voltage are compared to analytical models and TWOQUICK 2.5-D PIC code simulations.« less

An ambusher's arsenal: chemical crypsis in the puff adder (Bitis arietans).

PubMed

Miller, Ashadee Kay; Maritz, Bryan; McKay, Shannon; Glaudas, Xavier; Alexander, Graham J

2015-12-22

Ambush foragers use a hunting strategy that places them at risk of predation by both visual and olfaction-oriented predators. Resulting selective pressures have driven the evolution of impressive visual crypsis in many ambushing species, and may have led to the development of chemical crypsis. However, unlike for visual crypsis, few studies have attempted to demonstrate chemical crypsis. Field observations of puff adders (Bitis arietans) going undetected by several scent-orientated predator and prey species led us to investigate chemical crypsis in this ambushing species. We trained dogs (Canis familiaris) and meerkats (Suricata suricatta) to test whether a canid and a herpestid predator could detect B. arietans using olfaction. We also tested for chemical crypsis in five species of active foraging snakes, predicted to be easily detectable. Dogs and meerkats unambiguously indicated active foraging species, but failed to correctly indicate puff adder, confirming that B. arietans employs chemical crypsis. This is the first demonstration of chemical crypsis anti-predatory behaviour, though the phenomenon may be widespread among ambushers, especially those that experience high mortality rates owing to predation. Our study provides additional evidence for the existence of an ongoing chemically mediated arms race between predator and prey species. © 2015 The Author(s).

A hardware implementation of the discrete Pascal transform for image processing

NASA Astrophysics Data System (ADS)

Goodman, Thomas J.; Aburdene, Maurice F.

2006-02-01

The discrete Pascal transform is a polynomial transform with applications in pattern recognition, digital filtering, and digital image processing. It already has been shown that the Pascal transform matrix can be decomposed into a product of binary matrices. Such a factorization leads to a fast and efficient hardware implementation without the use of multipliers, which consume large amounts of hardware. We recently developed a field-programmable gate array (FPGA) implementation to compute the Pascal transform. Our goal was to demonstrate the computational efficiency of the transform while keeping hardware requirements at a minimum. Images are uploaded into memory from a remote computer prior to processing, and the transform coefficients can be offloaded from the FPGA board for analysis. Design techniques like as-soon-as-possible scheduling and adder sharing allowed us to develop a fast and efficient system. An eight-point, one-dimensional transform completes in 13 clock cycles and requires only four adders. An 8x8 two-dimensional transform completes in 240 cycles and requires only a top-level controller in addition to the one-dimensional transform hardware. Finally, through minor modifications to the controller, the transform operations can be pipelined to achieve 100% utilization of the four adders, allowing one eight-point transform to complete every seven clock cycles.

Mycobacteria Modify Their Cell Size Control under Sub-Optimal Carbon Sources

PubMed Central

Priestman, Miles; Thomas, Philipp; Robertson, Brian D.; Shahrezaei, Vahid

2017-01-01

The decision to divide is the most important one that any cell must make. Recent single cell studies suggest that most bacteria follow an “adder” model of cell size control, incorporating a fixed amount of cell wall material before dividing. Mycobacteria, including the causative agent of tuberculosis Mycobacterium tuberculosis, are known to divide asymmetrically resulting in heterogeneity in growth rate, doubling time, and other growth characteristics in daughter cells. The interplay between asymmetric cell division and adder size control has not been extensively investigated. Moreover, the impact of changes in the environment on growth rate and cell size control have not been addressed for mycobacteria. Here, we utilize time-lapse microscopy coupled with microfluidics to track live Mycobacterium smegmatis cells as they grow and divide over multiple generations, under a variety of growth conditions. We demonstrate that, under optimal conditions, M. smegmatis cells robustly follow the adder principle, with constant added length per generation independent of birth size, growth rate, and inherited pole age. However, the nature of the carbon source induces deviations from the adder model in a manner that is dependent on pole age. Understanding how mycobacteria maintain cell size homoeostasis may provide crucial targets for the development of drugs for the treatment of tuberculosis, which remains a leading cause of global mortality. PMID:28748182

Postglacial recolonization in a cold climate specialist in western Europe: patterns of genetic diversity in the adder (Vipera berus) support the central-marginal hypothesis.

PubMed

Ursenbacher, Sylvain; Guillon, Michaël; Cubizolle, Hervé; Dupoué, Andréaz; Blouin-Demers, Gabriel; Lourdais, Olivier

2015-07-01

Understanding the impact of postglacial recolonization on genetic diversity is essential in explaining current patterns of genetic variation. The central-marginal hypothesis (CMH) predicts a reduction in genetic diversity from the core of the distribution to peripheral populations, as well as reduced connectivity between peripheral populations. While the CMH has received considerable empirical support, its broad applicability is still debated and alternative hypotheses predict different spatial patterns of genetic diversity. Using microsatellite markers, we analysed the genetic diversity of the adder (Vipera berus) in western Europe to reconstruct postglacial recolonization. Approximate Bayesian Computation (ABC) analyses suggested a postglacial recolonization from two routes: a western route from the Atlantic Coast up to Belgium and a central route from the Massif Central to the Alps. This cold-adapted species likely used two isolated glacial refugia in southern France, in permafrost-free areas during the last glacial maximum. Adder populations further from putative glacial refugia had lower genetic diversity and reduced connectivity; therefore, our results support the predictions of the CMH. Our study also illustrates the utility of highly variable nuclear markers, such as microsatellites, and ABC to test competing recolonization hypotheses. © 2015 John Wiley & Sons Ltd.

Further clinical evidence for the existence of neurotoxicity in a population of the European adder (Vipera berus berus) in eastern Hungary: second authenticated case.

PubMed

Malina, Tamás; Babocsay, Gergely; Krecsák, László; Erdész, Csaba

2013-12-01

We report a recent case of common adder (Vipera berus) envenoming causing paralytic signs and symptoms. A 12-year-old girl was bitten by the nominate subspecies of the common adder (V. berus berus) in eastern Hungary on May 2, 2012, 22 km away from where the first neurotoxic V. berus berus envenoming was reported in 2008. The patient developed unambiguous cranial nerve disturbances, manifested in bilateral impairment characterized by oculomotor paralysis with partial ptosis, gaze paresis, and diplopia. Drowsiness and photophobia were her additional symptoms; both occurred only during the first day of envenoming. Until now among viper envenomings in Europe, photophobia has only been documented by victims of Vipera aspis. Supportive and symptomatic treatments were administered during 3 days of hospitalization. Although case reports of V. berus berus envenomings are often published, clinical experience with neurotoxicity by this subspecies still remains rare. Population-based and geographic variation of venom composition in V. berus berus seems to include neurotoxic envenomings in certain populations. This second authenticated case provides new clinical evidence for the existence of a possible neurotoxic V. berus berus population in a restricted geographical area in eastern Hungary. Wilderness Medical Society.

Analysis of Noise Mechanisms in Cell-Size Control.

PubMed

Modi, Saurabh; Vargas-Garcia, Cesar Augusto; Ghusinga, Khem Raj; Singh, Abhyudai

2017-06-06

At the single-cell level, noise arises from multiple sources, such as inherent stochasticity of biomolecular processes, random partitioning of resources at division, and fluctuations in cellular growth rates. How these diverse noise mechanisms combine to drive variations in cell size within an isoclonal population is not well understood. Here, we investigate the contributions of different noise sources in well-known paradigms of cell-size control, such as adder (division occurs after adding a fixed size from birth), sizer (division occurs after reaching a size threshold), and timer (division occurs after a fixed time from birth). Analysis reveals that variation in cell size is most sensitive to errors in partitioning of volume among daughter cells, and not surprisingly, this process is well regulated among microbes. Moreover, depending on the dominant noise mechanism, different size-control strategies (or a combination of them) provide efficient buffering of size variations. We further explore mixer models of size control, where a timer phase precedes/follows an adder, as has been proposed in Caulobacter crescentus. Although mixing a timer and an adder can sometimes attenuate size variations, it invariably leads to higher-order moments growing unboundedly over time. This results in a power-law distribution for the cell size, with an exponent that depends inversely on the noise in the timer phase. Consistent with theory, we find evidence of power-law statistics in the tail of C. crescentus cell-size distribution, although there is a discrepancy between the observed power-law exponent and that predicted from the noise parameters. The discrepancy, however, is removed after data reveal that the size added by individual newborns in the adder phase itself exhibits power-law statistics. Taken together, this study provides key insights into the role of noise mechanisms in size homeostasis, and suggests an inextricable link between timer-based models of size control and heavy-tailed cell-size distributions. Copyright © 2017 Biophysical Society. Published by Elsevier Inc. All rights reserved.

First Results from the Cornell COBRA Accelerator for Light Ion ICF Research

NASA Astrophysics Data System (ADS)

Lindholm, F.; Krastelev, E. G.; Greenly, J. B.; Kusse, B. R.

1996-11-01

COBRA, the Cornell Beam Research Accelerator, is a four-stage linear induction adder based on the Sandia National Laboratories SABRE accelerator design. The full 4 × 1 MV, 200 kA, 40 ns COBRA was completed in June 1996, after a year of initial operation with a single stage. Accelerator operation will be described, and first experimental results of power coupling and ion beam generation using a closely-coupled (short MITL) applied-B extraction ion diode load will be presented. A diagnostic package for beam optics including local microdivergence and aiming measurements is being developed, and results from both the single-stage experiments and new experiments on the full accelerator will be presented. A 20 ns, 15% voltage precursor to the main pulse resulting from coupling through the nonlinear magnetization characteristic of the Metglas^circR core at high magnetization rate was seen in the single-cell experiments. This mechanism will be discussed and its consequences on the full accelerator will be investigated.

Different Amounts of DNA in Newborn Cells of Escherichia coli Preclude a Role for the Chromosome in Size Control According to the "Adder" Model.

PubMed

Huls, Peter G; Vischer, Norbert O E; Woldringh, Conrad L

2018-01-01

According to the recently-revived adder model for cell size control, newborn cells of Escherichia coli will grow and divide after having added a constant size or length, ΔL , irrespective of their size at birth. Assuming exponential elongation, this implies that large newborns will divide earlier than small ones. The molecular basis for the constant size increment is still unknown. As DNA replication and cell growth are coordinated, the constant ΔL could be based on duplication of an equal amount of DNA, ΔG , present in newborn cells. To test this idea, we measured amounts of DNA and lengths of nucleoids in DAPI-stained cells growing in batch culture at slow and fast rates. Deeply-constricted cells were divided in two subpopulations of longer and shorter lengths than average; these were considered to represent large and small prospective daughter cells, respectively. While at slow growth, large and small prospective daughter cells contained similar amounts of DNA, fast growing cells with multiforked replicating chromosomes, showed a significantly higher amount of DNA (20%) in the larger cells. This observation precludes the hypothesis that Δ L is based on the synthesis of a constant ΔG . Growth curves were constructed for siblings generated by asymmetric division and growing according to the adder model. Under the assumption that all cells at the same growth rate exhibit the same time between initiation of DNA replication and cell division (i.e., constant C+D -period), the constructions predict that initiation occurs at different sizes ( Li ) and that, at fast growth, large newborn cells transiently contain more DNA than small newborns, in accordance with the observations. Because the state of segregation, measured as the distance between separated nucleoids, was found to be more advanced in larger deeply-constricted cells, we propose that in larger newborns nucleoid separation occurs faster and at a shorter length, allowing them to divide earlier. We propose a composite model in which both differential initiation and segregation leads to an adder-like behavior of large and small newborn cells.

Dual circuit embossed sheet heat transfer panel

DOEpatents

Morgan, G.D.

1984-02-21

A heat transfer panel provides redundant cooling for fusion reactors or the like environment requiring low-mass construction. Redundant cooling is provided by two independent cooling circuits, each circuit consisting of a series of channels joined to inlet and outlet headers. The panel comprises a welded joinder of two full-size and two much smaller partial-size sheets. The first full-size sheet is embossed to form first portions of channels for the first and second circuits, as well as a header for the first circuit. The second full-sized sheet is then laid over and welded to the first full-size sheet. The first and second partial-size sheets are then overlaid on separate portions of the second full-sized sheet, and are welded thereto. The first and second partial-sized sheets are embossed to form inlet and outlet headers, which communicate with channels of the second circuit through apertures formed in the second full-sized sheet. 6 figs.

Dual-circuit embossed-sheet heat-transfer panel

DOEpatents

Morgan, G.D.

1982-08-23

A heat transfer panel provides redundant cooling for fusion reactors or the like environment requiring low-mass construction. Redundant cooling is provided by two independent cooling circuits, each circuit consisting of a series of channels joined to inlet and outlet headers. The panel comprises a welded joinder of two full-size and two much smaller partial-size sheets. The first full-size sheet is embossed for form first portions of channels for the first and second circuits, as well as a header for the first circuit. The second full-sized sheet is then laid over and welded to the first full-size sheet. The first and second partial-size sheets are then overlaid on separate portions of the second full-sized sheet, and are welded thereto. The first and second partial-sized sheets are embossed to form inlet and outlet headers, which communicate with channels of the second circuit through apertures formed in the second full-sized sheet.

Dual circuit embossed sheet heat transfer panel

DOEpatents

Morgan, Grover D.

1984-01-01

A heat transfer panel provides redundant cooling for fusion reactors or the like environment requiring low-mass construction. Redundant cooling is provided by two independent cooling circuits, each circuit consisting of a series of channels joined to inlet and outlet headers. The panel comprises a welded joinder of two full-size and two much smaller partial-size sheets. The first full-size sheet is embossed to form first portions of channels for the first and second circuits, as well as a header for the first circuit. The second full-sized sheet is then laid over and welded to the first full-size sheet. The first and second partial-size sheets are then overlaid on separate portions of the second full-sized sheet, and are welded thereto. The first and second partial-sized sheets are embossed to form inlet and outlet headers, which communicate with channels of the second circuit through apertures formed in the second full-sized sheet.

Universal computing by DNA origami robots in a living animal

PubMed Central

Levner, Daniel; Ittah, Shmulik; Abu-Horowitz, Almogit; Bachelet, Ido

2014-01-01

Biological systems are collections of discrete molecular objects that move around and collide with each other. Cells carry out elaborate processes by precisely controlling these collisions, but developing artificial machines that can interface with and control such interactions remains a significant challenge. DNA is a natural substrate for computing and has been used to implement a diverse set of mathematical problems1-3, logic circuits4-6 and robotics7-9. The molecule also naturally interfaces with living systems, and different forms of DNA-based biocomputing have previously been demonstrated10-13. Here we show that DNA origami14-16 can be used to fabricate nanoscale robots that are capable of dynamically interacting with each other17-18 in a living animal. The interactions generate logical outputs, which are relayed to switch molecular payloads on or off. As a proof-of-principle, we use the system to create architectures that emulate various logic gates (AND, OR, XOR, NAND, NOT, CNOT, and a half adder). Following an ex vivo prototyping phase, we successfully employed the DNA origami robots in living cockroaches (Blaberus discoidalis) to control a molecule that targets the cells of the animal. PMID:24705510

A Path to Discovery

ERIC Educational Resources Information Center

Stegemoller, William; Stegemoller, Rebecca

2004-01-01

The path taken and the turns made as a turtle traces a polygon are examined to discover an important theorem in geometry. A unique tool, the Angle Adder, is implemented in the investigation. (Contains 9 figures.)

Amplitude Control of Solid-State Modulators for Precision Fast Kicker Applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Watson, J A; Anaya, R M; Caporaso, G C

2002-11-15

A solid-state modulator with very fast rise and fall times, pulse width agility, and multi-pulse burst and intra-pulse amplitude adjustment capability for use with high speed electron beam kickers has been designed and tested at LLNL. The modulator uses multiple solid-state modules stacked in an inductive-adder configuration. Amplitude adjustment is provided by controlling individual modules in the adder, and is used to compensate for transverse e-beam motion as well as the dynamic response and beam-induced steering effects associated with the kicker structure. A control algorithm calculates a voltage based on measured e-beam displacement and adjusts the modulator to regulate beammore » centroid position. This paper presents design details of amplitude control along with measured performance data from kicker operation on the ETA-II accelerator at LLNL.« less

Design and Testing of a Fast, 50 kV Solid-State Kicker Pulser

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cook, E G; Hickman, B C; Lee, B S

2002-06-24

The ability to extract particle beam bunches from a ring accelerator in arbitrary order can greatly extend an accelerator's capabilities and applications. A prototype solid-state kicker pulser capable of generating asynchronous bursts of 50 kV pulses has been designed and tested into a 50{Omega} load. The pulser features fast rise and fall times and is capable of generating an arbitrary pattern of pulses with a maximum burst frequency exceeding 5 MHz If required, the pulse-width of each pulse in the burst is independently adjustable. This kicker modulator uses multiple solid-state modules stacked in an inductive-adder configuration where the energy ismore » switched into each section of the adder by a parallel array of MOSFETs. Test data, capabilities, and limitations of the prototype pulser are described.« less

Hybridizing triboelectrification and electromagnetic induction effects for high-efficient mechanical energy harvesting.

PubMed

Hu, Youfan; Yang, Jin; Niu, Simiao; Wu, Wenzhuo; Wang, Zhong Lin

2014-07-22

The recently introduced triboelectric nanogenerator (TENG) and the traditional electromagnetic induction generator (EMIG) are coherently integrated in one structure for energy harvesting and vibration sensing/isolation. The suspended structure is based on two oppositely oriented magnets that are enclosed by hollow cubes surrounded with coils, which oscillates in response to external disturbance and harvests mechanical energy simultaneously from triboelectrification and electromagnetic induction. It extends the previous definition of hybrid cell to harvest the same type of energy with multiple approaches. Both the sliding-mode TENG and contact-mode TENG can be achieved in the same structure. In order to make the TENG and EMIG work together, transformers are used to match the output impedance between these two power sources with very different characteristics. The maximum output power of 7.7 and 1.9 mW on the same load of 5 kΩ was obtained for the TENG and EMIG, respectively, after impedance matching. Benefiting from the rational design, the output signal from the TENG and the EMIG are in phase. They can be added up directly to get an output voltage of 4.6 V and an output current of 2.2 mA in parallel connection. A power management circuit was connected to the hybrid cell, and a regulated voltage of 3.3 V with constant current was achieved. For the first time, a logic operation was carried out on a half-adder circuit by using the hybrid cell working as both the power source and the input digit signals. We also demonstrated that the hybrid cell can serve as a vibration isolator. Further applications as vibration dampers, triggers, and sensors are all promising.

Low power adder based auditory filter architecture.

PubMed

Rahiman, P F Khaleelur; Jayanthi, V S

2014-01-01

Cochlea devices are powered up with the help of batteries and they should possess long working life to avoid replacing of devices at regular interval of years. Hence the devices with low power consumptions are required. In cochlea devices there are numerous filters, each responsible for frequency variant signals, which helps in identifying speech signals of different audible range. In this paper, multiplierless lookup table (LUT) based auditory filter is implemented. Power aware adder architectures are utilized to add the output samples of the LUT, available at every clock cycle. The design is developed and modeled using Verilog HDL, simulated using Mentor Graphics Model-Sim Simulator, and synthesized using Synopsys Design Compiler tool. The design was mapped to TSMC 65 nm technological node. The standard ASIC design methodology has been adapted to carry out the power analysis. The proposed FIR filter architecture has reduced the leakage power by 15% and increased its performance by 2.76%.

System for adjusting frequency of electrical output pulses derived from an oscillator

DOEpatents

Bartholomew, David B.

2006-11-14

A system for setting and adjusting a frequency of electrical output pulses derived from an oscillator in a network is disclosed. The system comprises an accumulator module configured to receive pulses from an oscillator and to output an accumulated value. An adjustor module is configured to store an adjustor value used to correct local oscillator drift. A digital adder adds values from the accumulator module to values stored in the adjustor module and outputs their sums to the accumulator module, where they are stored. The digital adder also outputs an electrical pulse to a logic module. The logic module is in electrical communication with the adjustor module and the network. The logic module may change the value stored in the adjustor module to compensate for local oscillator drift or change the frequency of output pulses. The logic module may also keep time and calculate drift.

Can Australians identify snakes?

PubMed

Morrison, J J; Pearn, J H; Covacevich, J; Nixon, J

1983-07-23

A study of the ability of Australians to identify snakes was undertaken, in which 558 volunteers (primary and secondary schoolchildren, doctors and university science and medical students) took part. Over all, subjects correctly identified an average of 19% of snakes; 28% of subjects could identify a taipan, 59% could identify a death adder, 18% a tiger snake, 23% an eastern (or common) brown snake, and 0.5% a rough-scaled snake. Eighty-six per cent of subjects who grew up in rural areas could identify a death adder; only 4% of those who grew up in an Australian capital city could identify a nonvenomous python. Male subjects identified snakes more accurately than did female subjects. Doctors and medical students correctly identified an average of 25% of snakes. The ability to identify medically significant Australian snakes was classified according to the observer's background, education, sex, and according to the individual snake species. Australians need to be better educated about snakes indigenous to this country.

EUVL mask dual pods to be used for mask shipping and handling in exposure tools

NASA Astrophysics Data System (ADS)

Gomei, Yoshio; Ota, Kazuya; Lystad, John; Halbmair, Dave; He, Long

2007-03-01

The concept of Extreme Ultra-Violet Lithography (EUVL) mask dual pods is proposed for use in both mask shipping and handling in exposure tools. The inner pod was specially designed to protect masks from particle contamination during shipping from mask houses to wafer factories. It can be installed in a load-lock chamber of exposure tools and evacuated while holding the mask inside. The inner pod upper cover is removed just before the mask is installed to a mask stage. Prototypes were manufactured and tested for shipping and for vacuum cycling. We counted particle adders through these actions with a detectable level of 54 nm and up. The adder count was close to zero, or we can say that the obtained result is within the noise level of our present evaluation environment. This indicates that the present concept is highly feasible for EUVL mask shipping and handling in exposure tools.

Circuit-based versus full-wave modelling of active microwave circuits

NASA Astrophysics Data System (ADS)

Bukvić, Branko; Ilić, Andjelija Ž.; Ilić, Milan M.

2018-03-01

Modern full-wave computational tools enable rigorous simulations of linear parts of complex microwave circuits within minutes, taking into account all physical electromagnetic (EM) phenomena. Non-linear components and other discrete elements of the hybrid microwave circuit are then easily added within the circuit simulator. This combined full-wave and circuit-based analysis is a must in the final stages of the circuit design, although initial designs and optimisations are still faster and more comfortably done completely in the circuit-based environment, which offers real-time solutions at the expense of accuracy. However, due to insufficient information and general lack of specific case studies, practitioners still struggle when choosing an appropriate analysis method, or a component model, because different choices lead to different solutions, often with uncertain accuracy and unexplained discrepancies arising between the simulations and measurements. We here design a reconfigurable power amplifier, as a case study, using both circuit-based solver and a full-wave EM solver. We compare numerical simulations with measurements on the manufactured prototypes, discussing the obtained differences, pointing out the importance of measured parameters de-embedding, appropriate modelling of discrete components and giving specific recipes for good modelling practices.

Characteristics of a large vacuum wave precursor on the SABRE voltage adder MITL and extraction ion diode

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cuneo, M.E.; Hanson, D.L.; Menge, P.R.

SABRE (Sandia Accelerator and Beam Research Experiment) is a ten-cavity linear induction magnetically insulated voltage adder (6 MV, 300 kA) operated in positive polarity to investigate issues relevant to ion beam production and propagation for inertial confinement fusion. The voltage adder section is coupled to an applied-B extraction ion diode via a long coaxial output transmission line. Observations indicate that the power propagates in a vacuum wave prior to electron emission. After the electron emission threshold is reached, power propagates in a magnetically insulated wave. The precursor is observed to have a dominant impact on he turn-on, impedance history, andmore » beam characteristics of applied-B ion diodes since the precursor voltage is large enough to cause electron emission at the diode from both the cathode feed and cathode tips. The amplitude of the precursor at the load (3--4.5 MV) is a significant fraction of the maximum load voltage (5--6 MV) because (1) the transmission line gaps ( {approx} 9 cm at output) and therefore impedances are relatively large, and hence the electric field threshold for electron emission (200 to 300 kV/cm) is not reached until well into the power pulse rise time; and (2) the rapidly falling forward wave and diode impedance reduces the ratio of main pulse voltage to precursor voltage. Experimental voltage and current data from the transmission line and the ion diode will be presented and compared with TWOQUICK (2-D electromagnetic PIC code) simulations and analytic models.« less

Inductive voltage adder advanced hydrodynamic radiographic technology demonstration

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mazarakis, M.G.; Poukey, J.W.; Maenchen

This paper presents the design, results, and analysis of a high-brightness electron beam technology demonstration experiment completed at Sandia National Laboratories, performed in collaboration with Los Alamos National Laboratory. The anticipated electron beam parameters were: 12 MeV, 35-40 kA, 0.5-mm rms radius, and 40-ns full width half maximum (FWHM) pulse duration. This beam, on an optimum thickness tantalum converter, should produce a very intense x-ray source of {approximately} 1.5-mm spot size and 1 kR dose @ 1 m. The accelerator utilized was SABRE, a pulsed inductive voltage adder, and the electron source was a magnetically immersed foilless electron diode. Formore » these experiments, SABRE was modified to high-impedance negative-polarity operation. A new 100-ohm magnetically insulated transmission line cathode electrode was designed and constructed; the cavities were rotated 180{degrees} poloidally to invert the central electrode polarity to negative; and only one of the two pulse forming lines per cavity was energized. A twenty- to thirty-Tesla solenoidal magnet insulated the diode and contained the beam at its extremely small size. These experiments were designed to demonstrate high electron currents in submillimeter radius beams resulting in a high-brightness high-intensity flash x-ray source for high-resolution thick-object hydrodynamic radiography. The SABRE facility high-impedance performance was less than what was hoped. The modifications resulted in a lower amplitude (9 MV), narrower-than-anticipated triangular voltage pulse, which limited the dose to {approximately} 20% of the expected value. In addition, halo and ion-hose instabilities increased the electron beam spot size to > 1.5 mm. Subsequent, more detailed calculations explain these reduced output parameters. An accelerator designed (versus retrofit) for this purpose would provide the desired voltage and pulse shape.« less

Full circuit calculation for electromagnetic pulse transmission in a high current facility

NASA Astrophysics Data System (ADS)

Zou, Wenkang; Guo, Fan; Chen, Lin; Song, Shengyi; Wang, Meng; Xie, Weiping; Deng, Jianjun

2014-11-01

We describe herein for the first time a full circuit model for electromagnetic pulse transmission in the Primary Test Stand (PTS)—the first TW class pulsed power driver in China. The PTS is designed to generate 8-10 MA current into a z -pinch load in nearly 90 ns rise time for inertial confinement fusion and other high energy density physics research. The PTS facility has four conical magnetic insulation transmission lines, in which electron current loss exists during the establishment of magnetic insulation. At the same time, equivalent resistance of switches and equivalent inductance of pinch changes with time. However, none of these models are included in a commercially developed circuit code so far. Therefore, in order to characterize the electromagnetic transmission process in the PTS, a full circuit model, in which switch resistance, magnetic insulation transmission line current loss and a time-dependent load can be taken into account, was developed. Circuit topology and an equivalent circuit model of the facility were introduced. Pulse transmission calculation of shot 0057 was demonstrated with the corresponding code FAST (full-circuit analysis and simulation tool) by setting controllable parameters the same as in the experiment. Preliminary full circuit simulation results for electromagnetic pulse transmission to the load are presented. Although divergences exist between calculated and experimentally obtained waveforms before the vacuum section, consistency with load current is satisfactory, especially at the rising edge.

Multiple advanced logic gates made of DNA-Ag nanocluster and the application for intelligent detection of pathogenic bacterial genes.

PubMed

Lin, Xiaodong; Liu, Yaqing; Deng, Jiankang; Lyu, Yanlong; Qian, Pengcheng; Li, Yunfei; Wang, Shuo

2018-02-21

The integration of multiple DNA logic gates on a universal platform to implement advance logic functions is a critical challenge for DNA computing. Herein, a straightforward and powerful strategy in which a guanine-rich DNA sequence lighting up a silver nanocluster and fluorophore was developed to construct a library of logic gates on a simple DNA-templated silver nanoclusters (DNA-AgNCs) platform. This library included basic logic gates, YES, AND, OR, INHIBIT, and XOR, which were further integrated into complex logic circuits to implement diverse advanced arithmetic/non-arithmetic functions including half-adder, half-subtractor, multiplexer, and demultiplexer. Under UV irradiation, all the logic functions could be instantly visualized, confirming an excellent repeatability. The logic operations were entirely based on DNA hybridization in an enzyme-free and label-free condition, avoiding waste accumulation and reducing cost consumption. Interestingly, a DNA-AgNCs-based multiplexer was, for the first time, used as an intelligent biosensor to identify pathogenic genes, E. coli and S. aureus genes, with a high sensitivity. The investigation provides a prototype for the wireless integration of multiple devices on even the simplest single-strand DNA platform to perform diverse complex functions in a straightforward and cost-effective way.

A Low Power and High Throughput Self Synchronous FPGA Using 65nm CMOS with Throughput Optimization by Pipeline Alignment

NASA Astrophysics Data System (ADS)

Stefan Devlin, Benjamin; Nakura, Toru; Ikeda, Makoto; Asada, Kunihiro

We detail a self synchronous field programmable gate array (SSFPGA) with dual-pipeline (DP) architecture to conceal pre-charge time for dynamic logic, and its throughput optimization by using pipeline alignment implemented on benchmark circuits. A self synchronous LUT (SSLUT) consists of a three input tree-type structure with 8bits of SRAM for programming. A self synchronous switch box (SSSB) consists of both pass transistors and buffers to route signals, with 12bits of SRAM. One common block with one SSLUT and one SSSB occupies 2.2Mλ2 area with 35bits of SRAM, and the prototype SSFPGA with 34 × 30 (1020) blocks is designed and fabricated using 65nm CMOS. Measured results show at 1.2V 430MHz and 647MHz operation for a 3bit ripple carry adder, without and with throughput optimization, respectively. We find that using the proposed pipeline alignment techniques we can perform at maximum throughput of 647MHz in various benchmarks on the SSFPGA. We demonstrate up to 56.1 times throughput improvement with our pipeline alignment techniques. The pipeline alignment is carried out within the number of logic elements in the array and pipeline buffers in the switching matrix.

Individual variability of venom from the European adder (Vipera berus berus) from one locality in Eastern Hungary.

PubMed

Malina, Tamás; Krecsák, László; Westerström, Alexander; Szemán-Nagy, Gábor; Gyémánt, Gyöngyi; M-Hamvas, Márta; Rowan, Edward G; Harvey, Alan L; Warrell, David A; Pál, Balázs; Rusznák, Zoltán; Vasas, Gábor

2017-09-01

We have revealed intra-population variability among venom samples from several individual European adders (Vipera berus berus) within a defined population in Eastern Hungary. Individual differences in venom pattern were noticed, both gender-specific and age-related, by one-dimensional electrophoresis. Gelatin zymography demonstrated that these individual venoms have different degradation profiles indicating varying protease activity in the specimens from adders of different ages and genders. Some specimens shared a conserved region of substrate degradation, while others had lower or extremely low protease activity. Phospholipase A 2 activity of venoms was similar but not identical. Interspecimen diversity of the venom phospholipase A 2 -spectra (based on the components' molecular masses) was detected by MALDI-TOF MS. The lethal toxicity of venoms (LD 50 ) also showed differences among individual snakes. Extracted venom samples had varying neuromuscular paralysing effect on chick biventer cervicis nerve-muscle preparations. The paralysing effect of venom was lost when calcium in the physiological salt solution was replaced by strontium; indicating that the block of twitch responses to nerve stimulation is associated with the activity of a phospholipase-dependent neurotoxin. In contrast to the studied V. b. berus venoms from different geographical regions so far, this is the first V. b. berus population discovered to have predominantly neurotoxic neuromuscular activity. The relevance of varying venom yields is also discussed. This study demonstrates that individual venom variation among V. b. berus living in particular area of Eastern Hungary might contribute to a wider range of clinical manifestations of V. b. berus envenoming than elsewhere in Europe. Copyright © 2017 Elsevier Ltd. All rights reserved.

Design of Improved Arithmetic Logic Unit in Quantum-Dot Cellular Automata

NASA Astrophysics Data System (ADS)

Heikalabad, Saeed Rasouli; Gadim, Mahya Rahimpour

2018-06-01

The quantum-dot cellular automata (QCA) can be replaced to overcome the limitation of CMOS technology. An arithmetic logic unit (ALU) is a basic structure of any computer devices. In this paper, design of improved single-bit arithmetic logic unit in quantum dot cellular automata is presented. The proposed structure for ALU has AND, OR, XOR and ADD operations. A unique 2:1 multiplexer, an ultra-efficient two-input XOR and a low complexity full adder are used in the proposed structure. Also, an extended design of this structure is provided for two-bit ALU in this paper. The proposed structure of ALU is simulated by QCADesigner and simulation result is evaluated. Evaluation results show that the proposed design has best performance in terms of area, complexity and delay compared to the previous designs.

Design of Improved Arithmetic Logic Unit in Quantum-Dot Cellular Automata

NASA Astrophysics Data System (ADS)

Heikalabad, Saeed Rasouli; Gadim, Mahya Rahimpour

2018-03-01

The quantum-dot cellular automata (QCA) can be replaced to overcome the limitation of CMOS technology. An arithmetic logic unit (ALU) is a basic structure of any computer devices. In this paper, design of improved single-bit arithmetic logic unit in quantum dot cellular automata is presented. The proposed structure for ALU has AND, OR, XOR and ADD operations. A unique 2:1 multiplexer, an ultra-efficient two-input XOR and a low complexity full adder are used in the proposed structure. Also, an extended design of this structure is provided for two-bit ALU in this paper. The proposed structure of ALU is simulated by QCADesigner and simulation result is evaluated. Evaluation results show that the proposed design has best performance in terms of area, complexity and delay compared to the previous designs.

Hardware Implementation of 32-Bit High-Speed Direct Digital Frequency Synthesizer

PubMed Central

Ibrahim, Salah Hasan; Ali, Sawal Hamid Md.; Islam, Md. Shabiul

2014-01-01

The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2 : 1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz. These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications. PMID:24991635

Non-linear dynamic compensation system

NASA Technical Reports Server (NTRS)

Lin, Yu-Hwan (Inventor); Lurie, Boris J. (Inventor)

1992-01-01

A non-linear dynamic compensation subsystem is added in the feedback loop of a high precision optical mirror positioning control system to smoothly alter the control system response bandwidth from a relatively wide response bandwidth optimized for speed of control system response to a bandwidth sufficiently narrow to reduce position errors resulting from the quantization noise inherent in the inductosyn used to measure mirror position. The non-linear dynamic compensation system includes a limiter for limiting the error signal within preselected limits, a compensator for modifying the limiter output to achieve the reduced bandwidth response, and an adder for combining the modified error signal with the difference between the limited and unlimited error signals. The adder output is applied to control system motor so that the system response is optimized for accuracy when the error signal is within the preselected limits, optimized for speed of response when the error signal is substantially beyond the preselected limits and smoothly varied therebetween as the error signal approaches the preselected limits.

Design of an Inductive Adder for the FCC injection kicker pulse generator

NASA Astrophysics Data System (ADS)

Woog, D.; Barnes, M. J.; Ducimetière, L.; Holma, J.; Kramer, T.

2017-07-01

The injection system for a 100 TeV centre-of-mass collider is an important part of the Future Circular Collider (FCC) study. Due to issues with conventional kicker systems, such as self-triggering and long term availability of thyratrons and limitations of HV-cables, innovative design changes are planned for the FCC injection kicker pulse generator. An inductive adder (IA) based on semiconductor (SC) switches is a promising technology for kicker systems. Its modular design, and the possibility of an active ripple suppression are significant advantages. Since the IA is a complex device, with multiple components whose characteristics are important, a detailed design study and construction of a prototype is necessary. This paper summarizes the system requirements and constraints, and describes the main components and design challenges of the prototype IA. It outlines the results from simulations and measurements on different magnetic core materials as well as on SC switches. The paper concludes on the design choices and progress for the prototype to be built at CERN.

Full wave modulator-demodulator amplifier apparatus. [for generating rectified output signal

NASA Technical Reports Server (NTRS)

Black, J. M. (Inventor)

1974-01-01

A full-wave modulator-demodulator apparatus is described including an operational amplifier having a first input terminal coupled to a circuit input terminal, and a second input terminal alternately coupled to the circuit input terminal. A circuit is ground by a switching circuit responsive to a phase reference signal and the operational amplifier is alternately switched between a non-inverting mode and an inverting mode. The switching circuit includes three field-effect transistors operatively associated to provide the desired switching function in response to an alternating reference signal of the same frequency as an AC input signal applied to the circuit input terminal.

Nonvolatile reconfigurable sequential logic in a HfO2 resistive random access memory array.

PubMed

Zhou, Ya-Xiong; Li, Yi; Su, Yu-Ting; Wang, Zhuo-Rui; Shih, Ling-Yi; Chang, Ting-Chang; Chang, Kuan-Chang; Long, Shi-Bing; Sze, Simon M; Miao, Xiang-Shui

2017-05-25

Resistive random access memory (RRAM) based reconfigurable logic provides a temporal programmable dimension to realize Boolean logic functions and is regarded as a promising route to build non-von Neumann computing architecture. In this work, a reconfigurable operation method is proposed to perform nonvolatile sequential logic in a HfO 2 -based RRAM array. Eight kinds of Boolean logic functions can be implemented within the same hardware fabrics. During the logic computing processes, the RRAM devices in an array are flexibly configured in a bipolar or complementary structure. The validity was demonstrated by experimentally implemented NAND and XOR logic functions and a theoretically designed 1-bit full adder. With the trade-off between temporal and spatial computing complexity, our method makes better use of limited computing resources, thus provides an attractive scheme for the construction of logic-in-memory systems.

Design of an improved RCD buffer circuit for full bridge circuit

NASA Astrophysics Data System (ADS)

Yang, Wenyan; Wei, Xueye; Du, Yongbo; Hu, Liang; Zhang, Liwei; Zhang, Ou

2017-05-01

In the full bridge inverter circuit, when the switch tube suddenly opened or closed, the inductor current changes rapidly. Due to the existence of parasitic inductance of the main circuit. Therefore, the surge voltage between drain and source of the switch tube can be generated, which will have an impact on the switch and the output voltage. In order to ab sorb the surge voltage. An improve RCD buffer circuit is proposed in the paper. The peak energy will be absorbed through the buffer capacitor of the circuit. The part energy feedback to the power supply, another part release through the resistor in the form of heat, and the circuit can absorb the voltage spikes. This paper analyzes the process of the improved RCD snubber circuit, According to the specific parameters of the main circuit, a reasonable formula for calculating the resistance capacitance is given. A simulation model will be modulated in Multisim, which compared the waveform of tube voltage and the output waveform of the circuit without snubber circuit with the improved RCD snubber circuit. By comparing and analyzing, it is proved that the improved buffer circuit can absorb surge voltage. Finally, experiments are demonstrated to validate that the correctness of the RC formula and the improved RCD snubber circuit.

Area- and energy-efficient CORDIC accelerators in deep sub-micron CMOS technologies

NASA Astrophysics Data System (ADS)

Vishnoi, U.; Noll, T. G.

2012-09-01

The COordinate Rotate DIgital Computer (CORDIC) algorithm is a well known versatile approach and is widely applied in today's SoCs for especially but not restricted to digital communications. Dedicated CORDIC blocks can be implemented in deep sub-micron CMOS technologies at very low area and energy costs and are attractive to be used as hardware accelerators for Application Specific Instruction Processors (ASIPs). Thereby, overcoming the well known energy vs. flexibility conflict. Optimizing Global Navigation Satellite System (GNSS) receivers to reduce the hardware complexity is an important research topic at present. In such receivers CORDIC accelerators can be used for digital baseband processing (fixed-point) and in Position-Velocity-Time estimation (floating-point). A micro architecture well suited to such applications is presented. This architecture is parameterized according to the wordlengths as well as the number of iterations and can be easily extended for floating point data format. Moreover, area can be traded for throughput by partially or even fully unrolling the iterations, whereby the degree of pipelining is organized with one CORDIC iteration per cycle. From the architectural description, the macro layout can be generated fully automatically using an in-house datapath generator tool. Since the adders and shifters play an important role in optimizing the CORDIC block, they must be carefully optimized for high area and energy efficiency in the underlying technology. So, for this purpose carry-select adders and logarithmic shifters have been chosen. Device dimensioning was automatically optimized with respect to dynamic and static power, area and performance using the in-house tool. The fully sequential CORDIC block for fixed-point digital baseband processing features a wordlength of 16 bits, requires 5232 transistors, which is implemented in a 40-nm CMOS technology and occupies a silicon area of 1560 μm2 only. Maximum clock frequency from circuit simulation of extracted netlist is 768 MHz under typical, and 463 MHz under worst case technology and application corner conditions, respectively. Simulated dynamic power dissipation is 0.24 uW MHz-1 at 0.9 V; static power is 38 uW in slow corner, 65 uW in typical corner and 518 uW in fast corner, respectively. The latter can be reduced by 43% in a 40-nm CMOS technology using 0.5 V reverse-backbias. These features are compared with the results from different design styles as well as with an implementation in 28-nm CMOS technology. It is interesting that in the latter case area scales as expected, but worst case performance and energy do not scale well anymore.

Resembling a viper: implications of mimicry for conservation of the endangered smooth snake.

PubMed

Valkonen, Janne K; Mappes, Johanna

2014-12-01

The phenomenon of Batesian mimicry, where a palatable animal gains protection against predation by resembling an unpalatable model, has been a core interest of evolutionary biologists for 150 years. An extensive range of studies has focused on revealing mechanistic aspects of mimicry (shared education and generalization of predators) and the evolutionary dynamics of mimicry systems (co-operation vs. conflict) and revealed that protective mimicry is widespread and is important for individual fitness. However, according to our knowledge, there are no case studies where mimicry theories have been applied to conservation of mimetic species. Theoretically, mimicry affects, for example, frequency dependency of predator avoidance learning and human induced mortality. We examined the case of the protected, endangered, nonvenomous smooth snake (Coronella austriaca) that mimics the nonprotected venomous adder (Vipera berus), both of which occur in the Åland archipelago, Finland. To quantify the added predation risk on smooth snakes caused by the rarity of vipers, we calculated risk estimates from experimental data. Resemblance of vipers enhances survival of smooth snakes against bird predation because many predators avoid touching venomous vipers. Mimetic resemblance is however disadvantageous against human predators, who kill venomous vipers and accidentally kill endangered, protected smooth snakes. We found that the effective population size of the adders in Åland is very low relative to its smooth snake mimic (28.93 and 41.35, respectively).Because Batesian mimicry is advantageous for the mimic only if model species exist in sufficiently high numbers, it is likely that the conservation program for smooth snakes will fail if adders continue to be destroyed. Understanding the population consequences of mimetic species may be crucial to the success of endangered species conservation. We suggest that when a Batesian mimic requires protection, conservation planners should not ignore the model species (or co-mimic in Mullerian mimicry rings) even if it is not itself endangered. © 2014 Society for Conservation Biology.

Design of a Sixteen Bit Pipelined Adder Using CMOS Bulk P-Well Technology.

DTIC Science & Technology

1984-12-01

node’s current value. These rules are based on the assumption that the event that was last calculated reflects the latest configuraticn of the network...Lines beginning with - are treated as ll comment. The parameter names and their default values are: ;configuration file for ’standard’ MPC procem capm .2a

Iterative color-multiplexed, electro-optical processor.

PubMed

Psaltis, D; Casasent, D; Carlotto, M

1979-11-01

A noncoherent optical vector-matrix multiplier using a linear LED source array and a linear P-I-N photodiode detector array has been combined with a 1-D adder in a feedback loop. The resultant iterative optical processor and its use in solving simultaneous linear equations are described. Operation on complex data is provided by a novel color-multiplexing system.

Solid state circuit controls direction, speed, and braking of dc motor

NASA Technical Reports Server (NTRS)

Hanna, M. F.

1966-01-01

Full-wave bridge rectifier circuit controls the direction, speed, and braking of a dc motor. Gating in the circuit of Silicon Controlled Rectifiers /SCRS/ controls output polarity and braking is provided by an SCR that is gated to short circuit the reverse voltage generated by reversal of motor rotation.

49 CFR 234.237 - Reverse switch cut-out circuit.

Code of Federal Regulations, 2013 CFR

2013-10-01

... 49 Transportation 4 2013-10-01 2013-10-01 false Reverse switch cut-out circuit. 234.237 Section....237 Reverse switch cut-out circuit. A switch, when equipped with a switch circuit controller connected... warning system can only be cut out when the switch point is within one-half inch of full reverse position. ...

49 CFR 234.237 - Reverse switch cut-out circuit.

Code of Federal Regulations, 2014 CFR

2014-10-01

... 49 Transportation 4 2014-10-01 2014-10-01 false Reverse switch cut-out circuit. 234.237 Section....237 Reverse switch cut-out circuit. A switch, when equipped with a switch circuit controller connected... warning system can only be cut out when the switch point is within one-half inch of full reverse position. ...

49 CFR 234.237 - Reverse switch cut-out circuit.

Code of Federal Regulations, 2012 CFR

2012-10-01

... 49 Transportation 4 2012-10-01 2012-10-01 false Reverse switch cut-out circuit. 234.237 Section....237 Reverse switch cut-out circuit. A switch, when equipped with a switch circuit controller connected... warning system can only be cut out when the switch point is within one-half inch of full reverse position. ...

Driver Circuit For High-Power MOSFET's

NASA Technical Reports Server (NTRS)

Letzer, Kevin A.

1991-01-01

Driver circuit generates rapid-voltage-transition pulses needed to switch high-power metal oxide/semiconductor field-effect transistor (MOSFET) modules rapidly between full "on" and full "off". Rapid switching reduces time of overlap between appreciable current through and appreciable voltage across such modules, thereby increasing power efficiency.

Digital circuits using universal logic gates

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Donohoe, Gregory W. (Inventor); Gambles, Jody W. (Inventor)

2004-01-01

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

When dinner is dangerous: toxic frogs elicit species-specific responses from a generalist snake predator.

PubMed

Phillips, Ben; Shine, Richard

2007-12-01

In arms races between predators and prey, some evolved tactics are unbeatable by the other player. For example, many types of prey are inedible because they have evolved chemical defenses. In this case, prey death removes any selective advantage of toxicity to the prey but not the selective advantage to a predator of being able to consume the prey. In the absence of effective selection for postmortem persistence of the toxicity then, some chemical defenses probably break down rapidly after prey death. If so, predators can overcome the toxic defense simply by waiting for that breakdown before consuming the prey. Floodplain death adders (Acanthophis praelongus) are highly venomous frog-eating elapid snakes native to northern Australia. Some of the frogs they eat are nontoxic (Litoria nasuta), others produce gluelike mucus when seized by a predator (Limnodynastes convexiusculus), and one species (Litoria dahlii) is dangerously toxic to snakes. Both the glue and the toxin degrade within about 20 min of prey death. Adders deal with these prey types in different and highly stereotyped ways: they consume nontoxic frogs directly but envenomate and release the other taxa, waiting until the chemical defense loses its potency before consuming the prey.

ASIC implementation of recursive scaled discrete cosine transform algorithm

NASA Astrophysics Data System (ADS)

On, Bill N.; Narasimhan, Sam; Huang, Victor K.

1994-05-01

A program to implement the Recursive Scaled Discrete Cosine Transform (DCT) algorithm as proposed by H. S. Hou has been undertaken at the Institute of Microelectronics. Implementation of the design was done using top-down design methodology with VHDL (VHSIC Hardware Description Language) for chip modeling. When the VHDL simulation has been satisfactorily completed, the design is synthesized into gates using a synthesis tool. The architecture of the design consists of two processing units together with a memory module for data storage and transpose. Each processing unit is composed of four pipelined stages which allow the internal clock to run at one-eighth (1/8) the speed of the pixel clock. Each stage operates on eight pixels in parallel. As the data flows through each stage, there are various adders and multipliers to transform them into the desired coefficients. The Scaled IDCT was implemented in a similar fashion with the adders and multipliers rearranged to perform the inverse DCT algorithm. The chip has been verified using Field Programmable Gate Array devices. The design is operational. The combination of fewer multiplications required and pipelined architecture give Hou's Recursive Scaled DCT good potential of achieving high performance at a low cost in using Very Large Scale Integration implementation.

Application of magnetically insulated transmission lines for high current, high voltage electron beam accelerators

NASA Astrophysics Data System (ADS)

Shope, S. L.; Mazarakis, M. G.; Frost, C. A.; Poukey, J. W.; Turman, B. N.

Self Magnetically Insulated Transmission Lines (MITL) adders were used successfully in a number of Sandia accelerators such as HELIA, HERMES III, and SABRE. Most recently we used at MITL adder in the RADLAC/SMILE electron beam accelerator to produce high quality, small radius (r(sub rho) less than 2 cm), 11 - 15 MeV, 50 - 100-kA beams with a small transverse velocity v(perpendicular)/c = beta(perpendicular) less than or equal to 0.1. In RADLAC/SMILE, a coaxial MITL passed through the eight, 2 MV vacuum envelopes. The MITL summed the voltages of all eight feeds to a single foilless diode. The experimental results are in good agreement with code simulations. Our success with the MITL technology led us to investigate the application to higher energy accelerator designs. We have a conceptual design for a cavity-fed MITL that sums the voltages from 100 identical, inductively-isolated cavities. Each cavity is a toroidal structure that is driven simultaneously by four 8-ohm pulse-forming lines, providing a 1-MV voltage pulse to each of the 100 cavities. The point design accelerator is 100 MV, 500 kA, with a 30 - 50 ns FWHM output pulse.

Detector for flow abnormalities in gaseous diffusion plant compressors

DOEpatents

Smith, Stephen F.; Castleberry, Kim N.

1998-01-01

A detector detects a flow abnormality in a plant compressor which outputs a motor current signal. The detector includes a demodulator/lowpass filter demodulating and filtering the motor current signal producing a demodulated signal, and first, second, third and fourth bandpass filters connected to the demodulator/lowpass filter, and filtering the demodulated signal in accordance with first, second, third and fourth bandpass frequencies generating first, second, third and fourth filtered signals having first, second, third and fourth amplitudes. The detector also includes first, second, third and fourth amplitude detectors connected to the first, second, third and fourth bandpass filters respectively, and detecting the first, second, third and fourth amplitudes, and first and second adders connected to the first and fourth amplitude detectors and the second and third amplitude detectors respectively, and adding the first and fourth amplitudes and the second and third amplitudes respectively generating first and second added signals. Finally, the detector includes a comparator, connected to the first and second adders, and comparing the first and second added signals and detecting the abnormal condition in the plant compressor when the second added signal exceeds the first added signal by a predetermined value.

Detector for flow abnormalities in gaseous diffusion plant compressors

DOEpatents

Smith, S.F.; Castleberry, K.N.

1998-06-16

A detector detects a flow abnormality in a plant compressor which outputs a motor current signal. The detector includes a demodulator/lowpass filter demodulating and filtering the motor current signal producing a demodulated signal, and first, second, third and fourth bandpass filters connected to the demodulator/lowpass filter, and filtering the demodulated signal in accordance with first, second, third and fourth bandpass frequencies generating first, second, third and fourth filtered signals having first, second, third and fourth amplitudes. The detector also includes first, second, third and fourth amplitude detectors connected to the first, second, third and fourth bandpass filters respectively, and detecting the first, second, third and fourth amplitudes, and first and second adders connected to the first and fourth amplitude detectors and the second and third amplitude detectors respectively, and adding the first and fourth amplitudes and the second and third amplitudes respectively generating first and second added signals. Finally, the detector includes a comparator, connected to the first and second adders, and comparing the first and second added signals and detecting the abnormal condition in the plant compressor when the second added signal exceeds the first added signal by a predetermined value. 6 figs.

Experiments investigating the generation and transport of 10--12 MeV, 30-kA, mm-size electron beams with linear inductive voltage adders

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mazarakis, M.G.; Poukey, J.W.; Maenchen, J.E.

The authors present the design, analysis, and results of the high-brightness electron beam experiments currently under investigation at Sandia National Laboratories. The anticipated beam parameters are the following: 8--12 MeV, 35--50 kA, 30--60 ns FWHM, and 0.5-mm rms beam radius. The accelerators utilized are SABRE and HERMES III. Both are linear inductive voltage adders modified to higher impedance and fitted with magnetically immersed foil less electron diodes. In the strong 20--50 Tesla solenoidal magnetic field of the diode, mm-size electron beams are generated and propagated to a beam stop. The electron beam is field emitted from mm-diameter needle-shaped cathode electrodemore » and is contained in a similar size envelop by the strong magnetic field. These extremely space charge dominated beams provide the opportunity to study beam dynamics and possible instabilities in a unique parameter space. The SABRE experiments are already completed and have produced 30-kA, 1.5-mm FWHM electron beams, while the HERMES-III experiments are on-going.« less

Promiscuity in sand lizards (Lacerta agilis) and adder snakes (Vipera berus): causes and consequences.

PubMed

Olsson, M; Madsen, T

2001-01-01

We review postcopulatory phenomena in the Swedish sand lizard (Lacerta agilis) and adder (Vipera berus), and in particular, links between female promiscuity, determinants of paternity, and offspring viability. In both species, females mate multiply and exhibit a positive relationship between the number of partners and offspring viability. We conclude that this relationship is most likely the result of variable genetic compatibility between mates arising from postcopulatory phenomena, predominantly assortative fertilization with respect to parental genotypes. However, males who were more successful at mate acquisition were also more successful in situations of sperm competition, suggesting a possible link between male (diploid and haploid) genetic quality per se and probability of fertilization. Neither the number of partners nor the number of matings influenced the risk of infertility in sand lizards, suggesting that selection for reduced risk of infertility is not a sufficient explanation for maintaining female promiscuity in this population. Finally, we conclude that the relatively low genetic variability exhibited by our study populations may have facilitated detection of genetic benefits compared to more outbred ones. However, recent work derived from outbred populations in other taxa suggest a greater generality of the principles we discuss than previously may have been appreciated.

30 CFR 75.815 - Disconnect devices.

Code of Federal Regulations, 2011 CFR

2011-07-01

... phase-to-phase voltage of the circuit in which they are installed, and for the full-load current of the... explosion-proof enclosures, must be capable of interrupting the full-load current of the circuit or designed and installed to cause the current to be interrupted automatically prior to the opening of the...

30 CFR 75.815 - Disconnect devices.

Code of Federal Regulations, 2010 CFR

2010-07-01

... phase-to-phase voltage of the circuit in which they are installed, and for the full-load current of the... explosion-proof enclosures, must be capable of interrupting the full-load current of the circuit or designed and installed to cause the current to be interrupted automatically prior to the opening of the...

Development of a digital solar simulator based on full-bridge converter

NASA Astrophysics Data System (ADS)

Liu, Chen; Feng, Jian; Liu, Zhilong; Tong, Weichao; Ji, Yibo

2014-02-01

With the development of solar photovoltaic, distribution schemes utilized in power grid had been commonly application, and photovoltaic (PV) inverter is an essential equipment in grid. In this paper, a digital solar simulator based on full-bridge structure is presented. The output characteristic curve of system is electrically similar to silicon solar cells, which can greatly simplify research methods of PV inverter, improve the efficiency of research and development. The proposed simulator consists on a main control board based on TM320F28335, phase-shifted zero-voltage-switching (ZVS) DC-DC full-bridge converter and voltage and current sampling circuit, that allows emulating the voltage-current curve with the open-circuit voltage (Voc) of 900V and the short-circuit current (Isc) of 18A .When the system connected to a PV inverter, the inverter can quickly track from the open-circuit to the maximum power point and keep stability.

Reliability Assessment of Critical Electronic Components

DTIC Science & Technology

1992-07-01

Failures FLHP - Full Horse Power FSN - Federal Stock Number I Current IC - Integrated Circuit IPB - Illustrated Parts Breakdown K - Boltzmans Constant L...Classified P - Power PC - Printed Circuit PCB - Printed Circuit Board PGA - Pin Grid Array PPM - Parts Per Million PWB - Printed Wiring Board 0...4-59 4.4.3.2.3 Circuit Brcakers ......................................................... 4-59 4.4.3.2.4 Thermal

Multiple advanced logic gates made of DNA-Ag nanocluster and the application for intelligent detection of pathogenic bacterial genes† †Electronic supplementary information (ESI) available: Chemicals, materials and DNA sequences used in the investigation, the construction of YES, AND, OR, XOR and INH logic gates, CD and PAGE experimental results. See DOI: 10.1039/c7sc05246d

PubMed Central

Lin, Xiaodong; Deng, Jiankang; Lyu, Yanlong; Qian, Pengcheng; Li, Yunfei

2018-01-01

The integration of multiple DNA logic gates on a universal platform to implement advance logic functions is a critical challenge for DNA computing. Herein, a straightforward and powerful strategy in which a guanine-rich DNA sequence lighting up a silver nanocluster and fluorophore was developed to construct a library of logic gates on a simple DNA-templated silver nanoclusters (DNA-AgNCs) platform. This library included basic logic gates, YES, AND, OR, INHIBIT, and XOR, which were further integrated into complex logic circuits to implement diverse advanced arithmetic/non-arithmetic functions including half-adder, half-subtractor, multiplexer, and demultiplexer. Under UV irradiation, all the logic functions could be instantly visualized, confirming an excellent repeatability. The logic operations were entirely based on DNA hybridization in an enzyme-free and label-free condition, avoiding waste accumulation and reducing cost consumption. Interestingly, a DNA-AgNCs-based multiplexer was, for the first time, used as an intelligent biosensor to identify pathogenic genes, E. coli and S. aureus genes, with a high sensitivity. The investigation provides a prototype for the wireless integration of multiple devices on even the simplest single-strand DNA platform to perform diverse complex functions in a straightforward and cost-effective way. PMID:29675221

Functional Circuitry on Commercial Fabric via Textile-Compatible Nanoscale Film Coating Process for Fibertronics.

PubMed

Bae, Hagyoul; Jang, Byung Chul; Park, Hongkeun; Jung, Soo-Ho; Lee, Hye Moon; Park, Jun-Young; Jeon, Seung-Bae; Son, Gyeongho; Tcho, Il-Woong; Yu, Kyoungsik; Im, Sung Gap; Choi, Sung-Yool; Choi, Yang-Kyu

2017-10-11

Fabric-based electronic textiles (e-textiles) are the fundamental components of wearable electronic systems, which can provide convenient hand-free access to computer and electronics applications. However, e-textile technologies presently face significant technical challenges. These challenges include difficulties of fabrication due to the delicate nature of the materials, and limited operating time, a consequence of the conventional normally on computing architecture, with volatile power-hungry electronic components, and modest battery storage. Here, we report a novel poly(ethylene glycol dimethacrylate) (pEGDMA)-textile memristive nonvolatile logic-in-memory circuit, enabling normally off computing, that can overcome those challenges. To form the metal electrode and resistive switching layer, strands of cotton yarn were coated with aluminum (Al) using a solution dip coating method, and the pEGDMA was conformally applied using an initiated chemical vapor deposition process. The intersection of two Al/pEGDMA coated yarns becomes a unit memristor in the lattice structure. The pEGDMA-Textile Memristor (ETM), a form of crossbar array, was interwoven using a grid of Al/pEGDMA coated yarns and untreated yarns. The former were employed in the active memristor and the latter suppressed cell-to-cell disturbance. We experimentally demonstrated for the first time that the basic Boolean functions, including a half adder as well as NOT, NOR, OR, AND, and NAND logic gates, are successfully implemented with the ETM crossbar array on a fabric substrate. This research may represent a breakthrough development for practical wearable and smart fibertronics.

A procedural method for the efficient implementation of full-custom VLSI designs

NASA Technical Reports Server (NTRS)

Belk, P.; Hickey, N.

1987-01-01

An imbedded language system for the layout of very large scale integration (VLSI) circuits is examined. It is shown that through the judicious use of this system, a large variety of circuits can be designed with circuit density and performance comparable to traditional full-custom design methods, but with design costs more comparable to semi-custom design methods. The high performance of this methodology is attributable to the flexibility of procedural descriptions of VLSI layouts and to a number of automatic and semi-automatic tools within the system.

Ka-Band Wide-Bandgap Solid-State Power Amplifier: Prototype Combiner Spurious Mode Suppression and Power Constraints

NASA Technical Reports Server (NTRS)

Khan, P.; Epp, L.

2006-01-01

Results of prototype hardware activities related to a 120-W, 32-GHz (Ka-band) solid-state power amplifier (SSPA) architecture study are presented. Spurious mode suppression and the power-handling capability of a prototype 24-way radial combiner and a prototype 2-way septum binary combiner were investigated. Experimental data indicate that a commercial absorptive filter, designed to pass the circular TE01 mode, effectively suppressed the higher-order modes generated by a narrowband, flower-petal-type mode transducer. However, the same filter was not effective in suppressing higher-order modes generated by the broadband Marie mode transducer that is used in the prototype waveguide radial combiner. Should greater filtering be required by a particular SSPA application, a broadband mode filter that can suppress specifically those higher-order modes that are generated by the Marie transducer will need to be developed. A back-to-back configuration of the prototype radial combiner was tested with drive power up to approximately 50 W. No anomalous behavior was observed. Power measurements of the septum combiner indicate that up to 10-W radio frequency (RF) can be dissipated in the integrated resistive element before a permanent performance shift is observed. Thus, a given adder (a single-stage, 2-way combiner) can safely combine two 20-W sources, and the adder will not be damaged in the event of a source failure. This result is used to calculate the maximum source power that can be safely combined as a function of the number of sources combined and the number of source failures allowed in a multi-stage combiner. The analysis shows that SSPA power >140 W can be generated by power combining 16 sources producing 10 W each. In this configuration, up to three sources could fail with the guarantee that the combiner would not be damaged. Finally, a modified prototype septum combiner design was verified. The improved design reduced the assembly time from over 2 hours to about 15 minutes per adder.

Multiphase soft switched DC/DC converter and active control technique for fuel cell ripple current elimination

DOEpatents

Lai, Jih-Sheng; Liu, Changrong; Ridenour, Amy

2009-04-14

DC/DC converter has a transformer having primary coils connected to an input side and secondary coils connected to an output side. Each primary coil connects a full-bridge circuit comprising two switches on two legs, the primary coil being connected between the switches on each leg, each full-bridge circuit being connected in parallel wherein each leg is disposed parallel to one another, and the secondary coils connected to a rectifying circuit. An outer loop control circuit that reduces ripple in a voltage reference has a first resistor connected in series with a second resistor connected in series with a first capacitor which are connected in parallel with a second capacitor. An inner loop control circuit that reduces ripple in a current reference has a third resistor connected in series with a fourth resistor connected in series with a third capacitor which are connected in parallel with a fourth capacitor.

A Generalized Fast Frequency Sweep Algorithm for Coupled Circuit-EM Simulations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rockway, J D; Champagne, N J; Sharpe, R M

2004-01-14

Frequency domain techniques are popular for analyzing electromagnetics (EM) and coupled circuit-EM problems. These techniques, such as the method of moments (MoM) and the finite element method (FEM), are used to determine the response of the EM portion of the problem at a single frequency. Since only one frequency is solved at a time, it may take a long time to calculate the parameters for wideband devices. In this paper, a fast frequency sweep based on the Asymptotic Wave Expansion (AWE) method is developed and applied to generalized mixed circuit-EM problems. The AWE method, which was originally developed for lumped-loadmore » circuit simulations, has recently been shown to be effective at quasi-static and low frequency full-wave simulations. Here it is applied to a full-wave MoM solver, capable of solving for metals, dielectrics, and coupled circuit-EM problems.« less

30 CFR 75.825 - Power centers.

Code of Federal Regulations, 2011 CFR

2011-07-01

..., and be designed and installed as follows: (1) Rated for the maximum phase-to-phase voltage of the circuit; (2) Rated for the full-load current of the circuit that is supplied power through the device. (3... current of the circuit or causes the current to be interrupted automatically before the disconnecting...

Structure theorems and the dynamics of nitrogen catabolite repression in yeast

PubMed Central

Boczko, Erik M.; Cooper, Terrance G.; Gedeon, Tomas; Mischaikow, Konstantin; Murdock, Deborah G.; Pratap, Siddharth; Wells, K. Sam

2005-01-01

By using current biological understanding, a conceptually simple, but mathematically complex, model is proposed for the dynamics of the gene circuit responsible for regulating nitrogen catabolite repression (NCR) in yeast. A variety of mathematical “structure” theorems are described that allow one to determine the asymptotic dynamics of complicated systems under very weak hypotheses. It is shown that these theorems apply to several subcircuits of the full NCR circuit, most importantly to the URE2–GLN3 subcircuit that is independent of the other constituents but governs the switching behavior of the full NCR circuit under changes in nitrogen source. Under hypotheses that are fully consistent with biological data, it is proven that the dynamics of this subcircuit is simple periodic behavior in synchrony with the cell cycle. Although the current mathematical structure theorems do not apply to the full NCR circuit, extensive simulations suggest that the dynamics is constrained in much the same way as that of the URE2–GLN3 subcircuit. This finding leads to the proposal that mathematicians study genetic circuits to find new geometries for which structure theorems may exist. PMID:15814615

A 30 Mbps in-plane full-duplex light communication using a monolithic GaN photonic circuit

NASA Astrophysics Data System (ADS)

Gao, Xumin; Yuan, Jialei; Yang, Yongchao; Li, Yuanhang; Yuan, Wei; Zhu, Guixia; Zhu, Hongbo; Feng, Meixin; Sun, Qian; Liu, Yuhuai; Wang, Yongjin

2017-07-01

We propose, fabricate and characterize photonic integration of a InGaN/GaN multiple-quantum-well light-emitting diode (MQW-LED), waveguide, ring resonator and InGaN/GaN MQW-photodiode on a single chip, in which the photonic circuit is suspended by the support beams. Both experimental observations and simulation results illustrate the manipulation of in-plane light coupling and propagation by the waveguide and the ring resonator. The monolithic photonic circuit forms an in-plane data communication system using visible light. When the two suspended InGaN/GaN MQW-diodes simultaneously serve as the transmitter and the receiver, an in-plane full-duplex light communication is experimentally demonstrated with a transmission rate of 30 Mbps, and the superimposed signals are extracted using the self-interference cancellation method. The suspended photonic circuit creates new possibilities for exploring the in-plane full-duplex light communication and manufacturing complex GaN-based monolithic photonic integrations.

Surface-confined assemblies and polymers for molecular logic.

PubMed

de Ruiter, Graham; van der Boom, Milko E

2011-08-16

Stimuli responsive materials are capable of mimicking the operation characteristics of logic gates such as AND, OR, NOR, and even flip-flops. Since the development of molecular sensors and the introduction of the first AND gate in solution by de Silva in 1993, Molecular (Boolean) Logic and Computing (MBLC) has become increasingly popular. In this Account, we present recent research activities that focus on MBLC with electrochromic polymers and metal polypyridyl complexes on a solid support. Metal polypyridyl complexes act as useful sensors to a variety of analytes in solution (i.e., H(2)O, Fe(2+/3+), Cr(6+), NO(+)) and in the gas phase (NO(x) in air). This information transfer, whether the analyte is present, is based on the reversible redox chemistry of the metal complexes, which are stable up to 200 °C in air. The concurrent changes in the optical properties are nondestructive and fast. In such a setup, the input is directly related to the output and, therefore, can be represented by one-input logic gates. These input-output relationships are extendable for mimicking the diverse functions of essential molecular logic gates and circuits within a set of Boolean algebraic operations. Such a molecular approach towards Boolean logic has yielded a series of proof-of-concept devices: logic gates, multiplexers, half-adders, and flip-flop logic circuits. MBLC is a versatile and, potentially, a parallel approach to silicon circuits: assemblies of these molecular gates can perform a wide variety of logic tasks through reconfiguration of their inputs. Although these developments do not require a semiconductor blueprint, similar guidelines such as signal propagation, gate-to-gate communication, propagation delay, and combinatorial and sequential logic will play a critical role in allowing this field to mature. For instance, gate-to-gate communication by chemical wiring of the gates with metal ions as electron carriers results in the integration of stand-alone systems: the output of one gate is used as the input for another gate. Using the same setup, we were able to display both combinatorial and sequential logic. We have demonstrated MBLC by coupling electrochemical inputs with optical readout, which resulted in various logic architectures built on a redox-active, functionalized surface. Electrochemically operated sequential logic systems such as flip-flops, multivalued logic, and multistate memory could enhance computational power without increasing spatial requirements. Applying multivalued digits in data storage could exponentially increase memory capacity. Furthermore, we evaluate the pros and cons of MBLC and identify targets for future research in this Account. © 2011 American Chemical Society

Phlebotomus Sandflies of the Paloich Area in the Sudan (Diptera, Psychodidae)

DTIC Science & Technology

1964-10-01

Hamster, Cricetus auratus Toad, Bufo regularis (?) Gecko, H. turicus Skink, M. striata Puff adder Snake, CMNH HH-9111’ Snake, CMNH HH-9112’ Hedgehog ...Pharynx unarmed distally or only with few, smail spines ; pigment patch not dark enough to obscure teeth .................. 8 Pharynx heavily...armed distally with numerous, dark spines ; pigment patch very dark, 1964 Quate: Sudanese sandflies 237 often obscuring teeth unless specimen well

A time-domain digitally controlled oscillator composed of a free running ring oscillator and flying-adder

NASA Astrophysics Data System (ADS)

Wei, Liu; Wei, Li; Peng, Ren; Qinglong, Lin; Shengdong, Zhang; Yangyuan, Wang

2009-09-01

A time-domain digitally controlled oscillator (DCO) is proposed. The DCO is composed of a free-running ring oscillator (FRO) and a two lap-selectors integrated flying-adder (FA). With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13 μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.

The probabilistic convolution tree: efficient exact Bayesian inference for faster LC-MS/MS protein inference.

PubMed

Serang, Oliver

2014-01-01

Exact Bayesian inference can sometimes be performed efficiently for special cases where a function has commutative and associative symmetry of its inputs (called "causal independence"). For this reason, it is desirable to exploit such symmetry on big data sets. Here we present a method to exploit a general form of this symmetry on probabilistic adder nodes by transforming those probabilistic adder nodes into a probabilistic convolution tree with which dynamic programming computes exact probabilities. A substantial speedup is demonstrated using an illustration example that can arise when identifying splice forms with bottom-up mass spectrometry-based proteomics. On this example, even state-of-the-art exact inference algorithms require a runtime more than exponential in the number of splice forms considered. By using the probabilistic convolution tree, we reduce the runtime to O(k log(k)2) and the space to O(k log(k)) where k is the number of variables joined by an additive or cardinal operator. This approach, which can also be used with junction tree inference, is applicable to graphs with arbitrary dependency on counting variables or cardinalities and can be used on diverse problems and fields like forward error correcting codes, elemental decomposition, and spectral demixing. The approach also trivially generalizes to multiple dimensions.

The Probabilistic Convolution Tree: Efficient Exact Bayesian Inference for Faster LC-MS/MS Protein Inference

PubMed Central

Serang, Oliver

2014-01-01

Exact Bayesian inference can sometimes be performed efficiently for special cases where a function has commutative and associative symmetry of its inputs (called “causal independence”). For this reason, it is desirable to exploit such symmetry on big data sets. Here we present a method to exploit a general form of this symmetry on probabilistic adder nodes by transforming those probabilistic adder nodes into a probabilistic convolution tree with which dynamic programming computes exact probabilities. A substantial speedup is demonstrated using an illustration example that can arise when identifying splice forms with bottom-up mass spectrometry-based proteomics. On this example, even state-of-the-art exact inference algorithms require a runtime more than exponential in the number of splice forms considered. By using the probabilistic convolution tree, we reduce the runtime to and the space to where is the number of variables joined by an additive or cardinal operator. This approach, which can also be used with junction tree inference, is applicable to graphs with arbitrary dependency on counting variables or cardinalities and can be used on diverse problems and fields like forward error correcting codes, elemental decomposition, and spectral demixing. The approach also trivially generalizes to multiple dimensions. PMID:24626234

The effect of CO2 regulations on the cost of corn ethanol production

NASA Astrophysics Data System (ADS)

Plevin, R. J.; Mueller, S.

2008-04-01

To explore the effect of CO2 price on the effective cost of ethanol production we have developed a model that integrates financial and emissions accounting for dry-mill corn ethanol plants. Three policy options are modeled: (1) a charge per unit of life cycle CO2 emissions, (2) a charge per unit of direct biorefinery emissions only, and (3) a low carbon fuel standard (LCFS). A CO2 charge on life cycle emissions increases production costs by between 0.005 and 0.008 l-1 per 10 Mg-1 CO2 price increment, across all modeled plant energy systems, with increases under direct emissions somewhat lower in all cases. In contrast, a LCFS increases the cost of production for selected plant energy systems only: a LCFS requiring reductions in average fuel global warming intensity (GWI) with a target of 10% below the 2005 baseline increases the production costs for coal-fired plants only. For all other plant types, the LCFS operates as a subsidy. The findings depend strongly on the magnitude of a land use change adder. Some land use change adders currently discussed in the literature will push the GWI of all modeled production systems above the LCFS target, flipping the CO2 price from a subsidy to a tax.

Linear inductive voltage adders (IVA) for advanced hydrodynamic radiography

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mazarakis, M.G.; Boyes, J.D.; Johnson, D.L.

The electron beam which drifts through the multiple cavities of conventional induction linacs (LIA) is replaced in an IVA by a cylindrical metal conductor which extends along the entire length of the device and effectuates the addition of the accelerator cavity voltages. In the approach to radiography, the linear inductive voltage adder drives a magnetically immersed electron diode with a millimeter diameter cathode electrode and a planar anode/bremsstrahlung converter. Both anode and cathode electrodes are immersed in a strong (15--50 T) solenoidal magnetic field. The electron beam cross section is approximately of the same size as the cathode needle andmore » generates a similar size, very intense x-ray beam when it strikes the anode converter. An IVA driven diode can produce electron beams of equal size and energy as a LIA but with much higher currents (40--50 kA versus 4--5 kA), simpler hardware and thus lower cost. The authors present here first experimental validations of the technology utilizing HERMES 3 and SABRE IVA accelerators. The electron beam voltage and current were respectively of the order of 10 MV and 40 kA. X-ray doses of up to 1 kR {at} 1 m and spot sizes as small as 1.7 mm (at 200 R doses) were measured.« less

Experiments Investigating the Generation and Transport of 10--12 MeV, 30-kA, mm-size Electron Beams with Linear Inductive Voltage Adders.

NASA Astrophysics Data System (ADS)

Mazarakis, M. G.; Poukey, J. W.; Maenchen, J. E.; Rovang, D. C.; Menge, P. R.; Lash, J. S.; Smith, D. L.; Halbleib, J. A.; Cordova, S. R.; Mikkelson, K.; Gustwiller, J.; Stygar, W. A.; Welch, D. R.; Smith, I.; Corcoran, P.

1997-05-01

We present the design, analysis, and results of the high-brightness electron beam experiments currently under investigation at Sandia National Laboratories. The anticipated beam parameters are the following: energy 8-12 MeV, current 35-50 kA, rms radius 0.5 mm, and pulse duration 30-60 ns FWHM. The accelerators utilized are SABRE and Hermes-III. Both are linear inductive voltage adders (IVA) modified to higher impedance and fitted with magnetically immersed foilless electron diodes. In the strong 20-50 Tesla solenoidal magnetic field of the diode, mm-size electron beams are generated and propagated to a beam stop. The electron beam is field emitted from mm-diameter needle-shaped cathode electrode and is contained in a similar size envelope by the strong magnetic field. These extremely space charge dominated beams provide the opportunity to study beam dynamics and possible instabilities in a unique parameter space. The SABRE experiments are already completed and have produced 30 kA, 1.5-2.5 FWHM electron beams, while the Hermes-III experiments are currently under way. Results and analysis of the SABRE experimentation and a progress report on Hermes-III experiments will be presented.

Low-noise pulse conditioner

DOEpatents

Bird, David A.

1983-01-01

A low-noise pulse conditioner is provided for driving electronic digital processing circuitry directly from differentially induced input pulses. The circuit uses a unique differential-to-peak detector circuit to generate a dynamic reference signal proportional to the input peak voltage. The input pulses are compared with the reference signal in an input network which operates in full differential mode with only a passive input filter. This reduces the introduction of circuit-induced noise, or jitter, generated in ground referenced input elements normally used in pulse conditioning circuits, especially speed transducer processing circuits.

Equivalent circuit simulation of HPEM-induced transient responses at nonlinear loads

NASA Astrophysics Data System (ADS)

Kotzev, Miroslav; Bi, Xiaotang; Kreitlow, Matthias; Gronwald, Frank

2017-09-01

In this paper the equivalent circuit modeling of a nonlinearly loaded loop antenna and its transient responses to HPEM field excitations are investigated. For the circuit modeling the general strategy to characterize the nonlinearly loaded antenna by a linear and a nonlinear circuit part is pursued. The linear circuit part can be determined by standard methods of antenna theory and numerical field computation. The modeling of the nonlinear circuit part requires realistic circuit models of the nonlinear loads that are given by Schottky diodes. Combining both parts, appropriate circuit models are obtained and analyzed by means of a standard SPICE circuit simulator. It is the main result that in this way full-wave simulation results can be reproduced. Furthermore it is clearly seen that the equivalent circuit modeling offers considerable advantages with respect to computation speed and also leads to improved physical insights regarding the coupling between HPEM field excitation and nonlinearly loaded loop antenna.

Cost optimization in low volume VLSI circuits

NASA Technical Reports Server (NTRS)

Cook, K. B., Jr.; Kerns, D. V., Jr.

1982-01-01

The relationship of integrated circuit (IC) cost to electronic system cost is developed using models for integrated circuit cost which are based on design/fabrication approach. Emphasis is on understanding the relationship between cost and volume for custom circuits suitable for NASA applications. In this report, reliability is a major consideration in the models developed. Results are given for several typical IC designs using off the shelf, full custom, and semicustom IC's with single and double level metallization.

46 CFR 169.683 - Overcurrent protection, general.

Code of Federal Regulations, 2013 CFR

2013-10-01

... time delay; (2) Instantaneous short circuit protection; and (3) Repeated opening of the circuit in... above the full-load rating for continuous rated machines or the overload rating for special rated machines. ...

46 CFR 169.683 - Overcurrent protection, general.

Code of Federal Regulations, 2014 CFR

2014-10-01

... time delay; (2) Instantaneous short circuit protection; and (3) Repeated opening of the circuit in... above the full-load rating for continuous rated machines or the overload rating for special rated machines. ...

46 CFR 169.683 - Overcurrent protection, general.

Code of Federal Regulations, 2012 CFR

2012-10-01

... time delay; (2) Instantaneous short circuit protection; and (3) Repeated opening of the circuit in... above the full-load rating for continuous rated machines or the overload rating for special rated machines. ...

Studying the secondary coolant circuit rupture protection algorithm for the Novovoronezh NPP Unit 5 on a full-scale training simulator

NASA Astrophysics Data System (ADS)

Kharchenko, K. S.; Vitkovskii, I. L.

2014-02-01

Performance of the secondary coolant circuit rupture algorithm in different operating modes of the Novovoronezh NPP Unit 5 is considered by carrying out studies on a full-scale training simulator. The revealed shortcomings of the algorithm causing excessive actuations of the protection are pointed out, and recommendations for removing them are outlined.

Low pressure EGR system having full range capability

DOEpatents

Easley, Jr., William Lanier; Milam, David Michael; Roozenboom, Stephan Donald; Bond, Michael Steven; Kapic, Amir

2009-09-22

An exhaust treatment system for an engine is disclosed and may have an air induction circuit, an exhaust circuit, and an exhaust recirculation circuit. The air induction circuit may be configured to direct air into the engine. The exhaust circuit may be configured to direct exhaust from the engine and include a turbine driven by the exhaust, a particulate filter disposed in series with and downstream of the turbine, and a catalytic device disposed in series with and downstream of the particulate filter. The exhaust recirculation circuit may be configured to selectively redirect at least some of the exhaust from between the particulate filter and the catalytic device to the air induction circuit. The catalytic device is selected to create backpressure within the exhaust circuit sufficient to ensure that, under normal engine operating conditions above low idle, exhaust can flow into the air induction circuit without throttling of the air.

Numeric Function Generators Using Decision Diagrams for Discrete Functions

DTIC Science & Technology

2009-05-01

Taylor series and Chebyshev series. Since polynomial functions can be realized with multipliers and adders, any numeric functions can be realized in...NFGs from the decision diagrams. Since nu- meric functions can be expanded into polynomial functions, such as a Taylor series, in this section, we use...pp. 107–114, July 1995. [13] T. Kam, T. Villa, R. K. Brayton , and A. L. Sangiovanni- Vincentelli, “Multi-valued decision diagrams: Theory and appli

Deterministic Execution of Ptides Programs

DTIC Science & Technology

2013-05-15

at a time no later than 30+1+5 = 36. Assume the maximum clock synchronization error is . Therefore, the AddSubtract adder must delay processing the...the synchronization of the platform real- time clock to its peers in other system platforms. The portions of PtidyOS code that implement access to the...interesting opportunities for future research. References [1] Y. Zhao, E. A. Lee, and J. Liu, “A programming model for time - synchronized distributed real

Assembly of Ultra-Dense Nanowire-Based Computing Systems

DTIC Science & Technology

2006-06-30

34* characterized basic device element properties and statistics "* demonstrated product of sums (POS) validating assembled 2-bit adder structures " Demonstrated...linear region (Vds= 10 mV) from the peak g = 3 jiS at IVg -VTI= 0.13 V using the charge control model, representsmore than a factor of 10 improvement over...disrupted by ionizing particles or thermal fluctuation. Further, when working with such small charges, it is statistically possible that logic

Low-noise pulse conditioner

DOEpatents

Bird, D.A.

1981-06-16

A low-noise pulse conditioner is provided for driving electronic digital processing circuitry directly from differentially induced input pulses. The circuit uses a unique differential-to-peak detector circuit to generate a dynamic reference signal proportional to the input peak voltage. The input pulses are compared with the reference signal in an input network which operates in full differential mode with only a passive input filter. This reduces the introduction of circuit-induced noise, or jitter, generated in ground referenced input elements normally used in pulse conditioning circuits, especially speed transducer processing circuits. This circuit may be used for conditioning the sensor signal from the Fidler coil in a gas centrifuge for separation of isotopic gaseous mixtures.

Technologies for converter topologies

DOEpatents

Zhou, Yan; Zhang, Haiyu

2017-02-28

In some embodiments of the disclosed inverter topologies, an inverter may include a full bridge LLC resonant converter, a first boost converter, and a second boost converter. In such embodiments, the first and second boost converters operate in an interleaved manner. In other disclosed embodiments, the inverter may include a half-bridge inverter circuit, a resonant circuit, a capacitor divider circuit, and a transformer.

Energy saving in ac generators

NASA Technical Reports Server (NTRS)

Nola, F. J.

1980-01-01

Circuit cuts no-load losses, without sacrificing full-load power. Phase-contro circuit includes gate-controlled semiconductor switch that cuts off applied voltage for most of ac cycle if generator idling. Switch "on" time increases when generator is in operation.

Design and implementation of the modified signed digit multiplication routine on a ternary optical computer.

PubMed

Xu, Qun; Wang, Xianchao; Xu, Chao

2017-06-01

Multiplication with traditional electronic computers is faced with a low calculating accuracy and a long computation time delay. To overcome these problems, the modified signed digit (MSD) multiplication routine is established based on the MSD system and the carry-free adder. Also, its parallel algorithm and optimization techniques are studied in detail. With the help of a ternary optical computer's characteristics, the structured data processor is designed especially for the multiplication routine. Several ternary optical operators are constructed to perform M transformations and summations in parallel, which has accelerated the iterative process of multiplication. In particular, the routine allocates data bits of the ternary optical processor based on digits of multiplication input, so the accuracy of the calculation results can always satisfy the users. Finally, the routine is verified by simulation experiments, and the results are in full compliance with the expectations. Compared with an electronic computer, the MSD multiplication routine is not only good at dealing with large-value data and high-precision arithmetic, but also maintains lower power consumption and fewer calculating delays.

Reprogrammable logic in memristive crossbar for in-memory computing

NASA Astrophysics Data System (ADS)

Cheng, Long; Zhang, Mei-Yun; Li, Yi; Zhou, Ya-Xiong; Wang, Zhuo-Rui; Hu, Si-Yu; Long, Shi-Bing; Liu, Ming; Miao, Xiang-Shui

2017-12-01

Memristive stateful logic has emerged as a promising next-generation in-memory computing paradigm to address escalating computing-performance pressures in traditional von Neumann architecture. Here, we present a nonvolatile reprogrammable logic method that can process data between different rows and columns in a memristive crossbar array based on material implication (IMP) logic. Arbitrary Boolean logic can be executed with a reprogrammable cell containing four memristors in a crossbar array. In the fabricated Ti/HfO2/W memristive array, some fundamental functions, such as universal NAND logic and data transfer, were experimentally implemented. Moreover, using eight memristors in a 2  ×  4 array, a one-bit full adder was theoretically designed and verified by simulation to exhibit the feasibility of our method to accomplish complex computing tasks. In addition, some critical logic-related performances were further discussed, such as the flexibility of data processing, cascading problem and bit error rate. Such a method could be a step forward in developing IMP-based memristive nonvolatile logic for large-scale in-memory computing architecture.

Ionization tube simmer current circuit

DOEpatents

Steinkraus, R.F. Jr.

1994-12-13

A highly efficient flash lamp simmer current circuit utilizes a fifty percent duty cycle square wave pulse generator to pass a current over a current limiting inductor to a full wave rectifier. The DC output of the rectifier is then passed over a voltage smoothing capacitor through a reverse current blocking diode to a flash lamp tube to sustain ionization in the tube between discharges via a small simmer current. An alternate embodiment of the circuit combines the pulse generator and inductor in the form of an FET off line square wave generator with an impedance limited step up output transformer which is then applied to the full wave rectifier as before to yield a similar simmer current. 6 figures.

Ionization tube simmer current circuit

DOEpatents

Steinkraus, Jr., Robert F.

1994-01-01

A highly efficient flash lamp simmer current circuit utilizes a fifty percent duty cycle square wave pulse generator to pass a current over a current limiting inductor to a full wave rectifier. The DC output of the rectifier is then passed over a voltage smoothing capacitor through a reverse current blocking diode to a flash lamp tube to sustain ionization in the tube between discharges via a small simmer current. An alternate embodiment of the circuit combines the pulse generator and inductor in the form of an FET off line square wave generator with an impedance limited step up output transformer which is then applied to the full wave rectifier as before to yield a similar simmer current.

Simple constant-current-regulated power supply

NASA Technical Reports Server (NTRS)

Priebe, D. H. E.; Sturman, J. C.

1977-01-01

Supply incorporates soft-start circuit that slowly ramps current up to set point at turn-on. Supply consists of full-wave rectifier, regulating pass transistor, current feedback circuit, and quad single-supply operational-amplifier circuit providing control. Technique is applicable to any system requiring constant dc current, such as vacuum tube equipment, heaters, or battery charges; it has been used to supply constant current for instrument calibration.

DUMPING COOLED MOLDS FROM THE SHAKE OUT RAILS ONTO A ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

DUMPING COOLED MOLDS FROM THE SHAKE OUT RAILS ONTO A VIBRATING CONVEYOR WHICH TRANSPORTS CASTINGS AND SAND TO A SEPARATION SCREEN WHICH SIFTS SAND ONTO BELT CONVEYORS BELOW THAT CARRY IT PAST SWITCH-ACTIVATED WATER INJECTORS TO SIMILAR SWITCH-ACTIVATED FRESH SAND ADDERS BEFORE TRANSPORTING IT TO THE SAND STORAGE BIN WHILE CASTINGS ARE EITHER MANUALLY OR SMALL CRANE LIFTED TO DEGATING AREAS. - Southern Ductile Casting Company, Centerville Foundry, 101 Airport Road, Centreville, Bibb County, AL

Back-streaming ion beam measurements in a Self Magnetic Insulated (SMP) electron diode

NASA Astrophysics Data System (ADS)

Mazarakis, Michael; Johnston, Mark; Kiefer, Mark; Leckbee, Josh; Webb, Timothy; Bennett, Nichelle; Droemer, Darryl; Welch, Dale; Nielsen, Dan; Ziska, Derek; Wilkins, Frank; Advance radiography department Team

2014-10-01

A self-magnetic pinch diode (SMP) is presently the electron diode of choice for high energy flash x-ray radiography utilizing pulsed power drivers. The Sandia National Laboratories RITS accelerator is presently fit with an SMP diode that generates very small electron beam spots. RITS is a Self-Magnetically Insulated Transmission Line (MITL) voltage adder that adds the voltage pulse of six 1.3 MV inductively insulated cavities. The diode's anode is made of high Z metal in order to produce copious and energetic flash x-rays for radiographic imaging of high areal density objects. In any high voltage inductive voltage adder (IVA) utilizing MITLs to transmit the power to the diode load, the precise knowledge of the accelerating voltage applied on the anode-cathode (A-K) gap is problematic. This is even more difficult in an SMP diode where the A-K gap is very small (~1 cm) and the diode region very hostile. We are currently measuring the back-streaming ion currents emitted from the anode and propagating through a hollow cathode tip. We then are evaluating the A-K gap voltage by ion time of flight measurements supplemented with filtered Rogowski coils. Sandia is a multiprogram laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Company, for the United States Department of Energy's National Nuclear Security Administration under Contract No. DE- AC04-94AL850.

KIM-1 interface adapter to 3-wire teletype systems

NASA Technical Reports Server (NTRS)

Burhans, R. W.

1976-01-01

The KIM-1 circuit designed for use with a full duplex isolated 4 terminal system is described. Operation of the circuit with a 3 wire system in conjunction with a single +5v supply interface is discussed.

Feedback loop compensates for rectifier nonlinearity

NASA Technical Reports Server (NTRS)

1966-01-01

Signal processing circuit with two negative feedback loops rectifies two sinusoidal signals which are 180 degrees out of phase and produces a single full-wave rectified output signal. Each feedback loop incorporates a feedback rectifier to compensate for the nonlinearity of the circuit.

Energy Harvesting from Energetic Porous Silicon

DTIC Science & Technology

2016-07-01

ignition. Here we investigate a means to convert this mechanical energy to electrical energy via a piezoelectric cantilever and rectifying circuit. This...mechanical energy to electrical energy via a piezoelectric cantilever and an associated rectifying circuit. A small PSi sample is placed on the...cantilever is wired to a direct current (DC) full-bridge rectifier circuit (EHE001NC) also purchased from Midé. Test points have been added at the

Identification of cDNAs encoding viper venom hyaluronidases: cross-generic sequence conservation of full-length and unusually short variant transcripts.

PubMed

Harrison, Robert A; Ibison, Frances; Wilbraham, Davina; Wagstaff, Simon C

2007-05-01

The immobilisation of prey by snakes is most efficiently achieved by the rapid dissemination of venom from its site of injection into the blood stream. Hyaluronidase is a common component of snake venoms and has been termed the "venom spreading factor". In the absence of nucleotide or protein sequence data to confirm the functional identity of this venom component, we interrogated a venom gland EST database for the saw-scaled viper, Echis ocellatus (Nigeria), using the gene ontology (GO) term "carbohydrate metabolism". A single hyalurononglucosaminadase-activity matching sequence (EOC00242) was found and used to design PCR primers to acquire the full-length cDNA sequence. Although very different from the bee venom and mammalian hyaluronidase sequences, the E. ocellatus sequence retained all the catalytic, positional and structural residues that characterise this class of carbohydrate metabolising hydrolases. An extraordinarily high level of sequence identity (>95%) was observed in analogous venom gland cDNA sequences isolated (by PCR) from another saw-scaled viper species, E. pyramidum leakeyi (Kenya), and from the sahara horned viper, Cerastes cerastes cerastes (Egypt) and the puff adder, Bitis arietans (Nigeria). Smaller amplicons, lacking hyaluronidase catalytic residues because of 768 bp or 855 bp central deletions, appear to encode either truncated peptides without hyaluronidase activity, or are non-translated transcripts because they lack consensus translation initiating motifs.

Performance Analysis of IEEE 802.11g Waveform Transmitted Over a Fading Channel with Pulse-Noise Interference

DTIC Science & Technology

2006-06-01

called packet binary convolutional code (PBCC), was included as an option for performance at rate of either 5.5 or 11 Mpbs. The second offshoot...and the code rate is r k n= . A general convolutional encoder can be implemented with k shift-registers and n modulo-2 adders. Higher rates can be...derived from lower rate codes by employing “ puncturing .” Puncturing is a procedure for omitting some of the encoded bits in the transmitter (thus

Smart molecules at work--mimicking advanced logic operations.

PubMed

Andréasson, Joakim; Pischel, Uwe

2010-01-01

Molecular logic is an interdisciplinary research field, which has captured worldwide interest. This tutorial review gives a brief introduction into molecular logic and Boolean algebra. This serves as the basis for a discussion of the state-of-the-art and future challenges in the field. Representative examples from the most recent literature including adders/subtractors, multiplexers/demultiplexers, encoders/decoders, and sequential logic devices (keypad locks) are highlighted. Other horizons, such as the utility of molecular logic in bio-related applications, are discussed as well.

Maximum Temperature Detection System for Integrated Circuits

NASA Astrophysics Data System (ADS)

Frankiewicz, Maciej; Kos, Andrzej

2015-03-01

The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

PCSIM: A Parallel Simulation Environment for Neural Circuits Fully Integrated with Python

PubMed Central

Pecevski, Dejan; Natschläger, Thomas; Schuch, Klaus

2008-01-01

The Parallel Circuit SIMulator (PCSIM) is a software package for simulation of neural circuits. It is primarily designed for distributed simulation of large scale networks of spiking point neurons. Although its computational core is written in C++, PCSIM's primary interface is implemented in the Python programming language, which is a powerful programming environment and allows the user to easily integrate the neural circuit simulator with data analysis and visualization tools to manage the full neural modeling life cycle. The main focus of this paper is to describe PCSIM's full integration into Python and the benefits thereof. In particular we will investigate how the automatically generated bidirectional interface and PCSIM's object-oriented modular framework enable the user to adopt a hybrid modeling approach: using and extending PCSIM's functionality either employing pure Python or C++ and thus combining the advantages of both worlds. Furthermore, we describe several supplementary PCSIM packages written in pure Python and tailored towards setting up and analyzing neural simulations. PMID:19543450

The 25 kW resonant dc/dc power converter

NASA Technical Reports Server (NTRS)

Robson, R. R.

1983-01-01

The feasibility of processing 25-kW of power with a single, transistorized, series resonant converter stage was demonstrated by the successful design, development, fabrication, and testing of such a device which employs four Westinghouse D7ST transistors in a full-bridge configuration and operates from a 250-to-350 Vdc input bus. The unit has an overall worst-case efficiency of 93.5% at its full rated output of 1000 V and 25 A dc. A solid-state dc input circuit breaker and output-transient-current limiters are included in and integrated into the design. Full circuit details of the converter are presented along with the test data.

Direct Digital Boiler Control Systems for the Navy Small Boiler Equipment.

DTIC Science & Technology

1983-02-01

Hardware. Each full-size ACU a 6 caculation modules 30 arrme, modufes sation for dead time lag contains input/output circuit a 16 control mo uies a...along with lather modules of the DCS-1000 family. ’The complete instrument consists of plug-in circuit boards that allow easy Teplacement of a...Maintenance-Most systems indicate trouble areas with diagnostic routines or integral LED indicators so that circuit boards can be replaced to correct

Initial Testing of the Stainless Steel NaK-Cooled Circuit (SNaKC)

NASA Technical Reports Server (NTRS)

Garber, Anne; Godfroy, Thomas

2007-01-01

An actively pumped alkali metal flow circuit, designed and fabricated at the NASA Marshall Space Flight Center, is currently undergoing testing in the Early Flight Fission Test Facility (EFF-TF). Sodium potassium (NaK) was selected as the primary coolant. Basic circuit components include: simulated reactor core, NaK to gas heat exchanger, electromagnetic liquid metal pump, liquid metal flowmeter, load/drain reservoir, expansion reservoir, test section, and instrumentation. Operation of the circuit is based around the 37-pin partial-array core (pin and flow path dimensions are the same as those in a full core), designed to operate at 33 kWt. This presentation addresses the construction, fill and initial testing of the Stainless Steel NaK-Cooled Circuit (SNaKC).

Interneuronal mechanisms of hippocampal theta oscillations in a full-scale model of the rodent CA1 circuit

PubMed Central

Bezaire, Marianne J; Raikov, Ivan; Burk, Kelly; Vyas, Dhrumil; Soltesz, Ivan

2016-01-01

The hippocampal theta rhythm plays important roles in information processing; however, the mechanisms of its generation are not well understood. We developed a data-driven, supercomputer-based, full-scale (1:1) model of the rodent CA1 area and studied its interneurons during theta oscillations. Theta rhythm with phase-locked gamma oscillations and phase-preferential discharges of distinct interneuronal types spontaneously emerged from the isolated CA1 circuit without rhythmic inputs. Perturbation experiments identified parvalbumin-expressing interneurons and neurogliaform cells, as well as interneuronal diversity itself, as important factors in theta generation. These simulations reveal new insights into the spatiotemporal organization of the CA1 circuit during theta oscillations. DOI: http://dx.doi.org/10.7554/eLife.18566.001 PMID:28009257

Circuit for high resolution decoding of multi-anode microchannel array detectors

NASA Technical Reports Server (NTRS)

Kasle, David B. (Inventor)

1995-01-01

A circuit for high resolution decoding of multi-anode microchannel array detectors consisting of input registers accepting transient inputs from the anode array; anode encoding logic circuits connected to the input registers; midpoint pipeline registers connected to the anode encoding logic circuits; and pixel decoding logic circuits connected to the midpoint pipeline registers is described. A high resolution algorithm circuit operates in parallel with the pixel decoding logic circuit and computes a high resolution least significant bit to enhance the multianode microchannel array detector's spatial resolution by halving the pixel size and doubling the number of pixels in each axis of the anode array. A multiplexer is connected to the pixel decoding logic circuit and allows a user selectable pixel address output according to the actual multi-anode microchannel array detector anode array size. An output register concatenates the high resolution least significant bit onto the standard ten bit pixel address location to provide an eleven bit pixel address, and also stores the full eleven bit pixel address. A timing and control state machine is connected to the input registers, the anode encoding logic circuits, and the output register for managing the overall operation of the circuit.

Isolation and characterization at cholinergic nicotinic receptors of a neurotoxin from the venom of the Acanthophis sp. Seram death adder.

PubMed

Wickramaratna, Janith C; Fry, Bryan G; Loiacono, Richard E; Aguilar, Marie-Isabel; Alewood, Paul F; Hodgson, Wayne C

2004-07-15

The present study describes the isolation of the first neurotoxin (acantoxin IVa) from Acanthophis sp. Seram death adder venom and an examination of its activity at nicotinic acetylcholine receptor (nAChR) subtypes. Acantoxin IVa (MW 6815; 0.1-1.0 microM) caused concentration-dependent inhibition of indirect twitches (0.1 Hz, 0.2 ms, supramaximal V) and inhibited contractile responses to exogenous nicotinic agonists in the chick biventer cervicis nerve-muscle, confirming that this toxin is a postsynaptic neurotoxin. Acantoxin IVa (1-10 nM) caused pseudo-irreversible antagonism at skeletal muscle nAChR with an estimated pA2 of 8.36+/-0.17. Acantoxin IVa was approximately two-fold less potent than the long-chain (Type II) neurotoxin, alpha-bungarotoxin. With a pKi value of 4.48, acantoxin IVa was approximately 25,000 times less potent than alpha-bungarotoxin at alpha7-type neuronal nAChR. However, in contrast to alpha-bungarotoxin, acantoxin IVa completely inhibited specific [3H]-methyllycaconitine (MLA) binding in rat hippocampus homogenate. Acantoxin IVa had no activity at ganglionic nAChR, alpha4beta2 subtype neuronal nAChR or cytisine-resistant [3H]-epibatidine binding sites. While long-chain neurotoxin resistant [3H]-MLA binding in hippocampus homogenate requires further investigation, we have shown that a short-chain (Type I) neurotoxin is capable of fully inhibiting specific [3H]-MLA binding.

SABRE modification to a higher voltage high impedance inductive voltage adder (IVA)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mazarakis, M.G.; Smith, D.L.; Poukey, J.W.

The SABRE accelerator was originally designed to operate as low impedance voltage adder with 40-ohm maximum output impedance in negative polarity operation and approximately 20 ohm in positive polarity. Because of the low impedance and higher than expected energy losses in the pulse forming network, the operating input cavity voltage is of the order of 800 kV which limits the total output voltage to {approximately} 8 MV for negative polarity and 5 to 6 MV for positive polarity. The modifications presented here aim to increase the output voltage in both polarities. A new high impedance central electrode was designed capablemore » of operating both in negative and positive polarities, and the number of pulse forming lines feeding the inductively isolated cavities was reduced to half. These modifications were recently tested in positive polarity. An increase in the total accelerating voltage from 5.5 MV to 9 MV was observed while stressing all components to the level required to achieve 12 MV in negative polarity. In these experiments only 65% of the usual operating intermediate store capacitor voltage was necessary (1.7 MV instead of 2.6 MV). Currently, the device is reconfigured for negative polarity tests. The cavities are rotated by 180{degree} and a 17-inch spool is added at the base of the cantilevered center electrode (cathode electrode). Positive and negative polarity results are presented and compared with simulations.« less

Optimization of current waveform tailoring for magnetically driven isentropic compression experiments

NASA Astrophysics Data System (ADS)

Waisman, E. M.; Reisman, D. B.; Stoltzfus, B. S.; Stygar, W. A.; Cuneo, M. E.; Haill, T. A.; Davis, J.-P.; Brown, J. L.; Seagle, C. T.; Spielman, R. B.

2016-06-01

The Thor pulsed power generator is being developed at Sandia National Laboratories. The design consists of up to 288 decoupled and transit time isolated capacitor-switch units, called "bricks," that can be individually triggered to achieve a high degree of pulse tailoring for magnetically driven isentropic compression experiments (ICE) [D. B. Reisman et al., Phys. Rev. Spec. Top.-Accel. Beams 18, 090401 (2015)]. The connecting transmission lines are impedance matched to the bricks, allowing the capacitor energy to be efficiently delivered to an ICE strip-line load with peak pressures of over 100 GPa. Thor will drive experiments to explore equation of state, material strength, and phase transition properties of a wide variety of materials. We present an optimization process for producing tailored current pulses, a requirement for many material studies, on the Thor generator. This technique, which is unique to the novel "current-adder" architecture used by Thor, entirely avoids the iterative use of complex circuit models to converge to the desired electrical pulse. We begin with magnetohydrodynamic simulations for a given material to determine its time dependent pressure and thus the desired strip-line load current and voltage. Because the bricks are connected to a central power flow section through transit-time isolated coaxial cables of constant impedance, the brick forward-going pulses are independent of each other. We observe that the desired equivalent forward-going current driving the pulse must be equal to the sum of the individual brick forward-going currents. We find a set of optimal brick delay times by requiring that the L2 norm of the difference between the brick-sum current and the desired forward-going current be a minimum. We describe the optimization procedure for the Thor design and show results for various materials of interest.

Comparison between Frame-Constrained Fix-Pixel-Value and Frame-Free Spiking-Dynamic-Pixel ConvNets for Visual Processing

PubMed Central

Farabet, Clément; Paz, Rafael; Pérez-Carrasco, Jose; Zamarreño-Ramos, Carlos; Linares-Barranco, Alejandro; LeCun, Yann; Culurciello, Eugenio; Serrano-Gotarredona, Teresa; Linares-Barranco, Bernabe

2012-01-01

Most scene segmentation and categorization architectures for the extraction of features in images and patches make exhaustive use of 2D convolution operations for template matching, template search, and denoising. Convolutional Neural Networks (ConvNets) are one example of such architectures that can implement general-purpose bio-inspired vision systems. In standard digital computers 2D convolutions are usually expensive in terms of resource consumption and impose severe limitations for efficient real-time applications. Nevertheless, neuro-cortex inspired solutions, like dedicated Frame-Based or Frame-Free Spiking ConvNet Convolution Processors, are advancing real-time visual processing. These two approaches share the neural inspiration, but each of them solves the problem in different ways. Frame-Based ConvNets process frame by frame video information in a very robust and fast way that requires to use and share the available hardware resources (such as: multipliers, adders). Hardware resources are fixed- and time-multiplexed by fetching data in and out. Thus memory bandwidth and size is important for good performance. On the other hand, spike-based convolution processors are a frame-free alternative that is able to perform convolution of a spike-based source of visual information with very low latency, which makes ideal for very high-speed applications. However, hardware resources need to be available all the time and cannot be time-multiplexed. Thus, hardware should be modular, reconfigurable, and expansible. Hardware implementations in both VLSI custom integrated circuits (digital and analog) and FPGA have been already used to demonstrate the performance of these systems. In this paper we present a comparison study of these two neuro-inspired solutions. A brief description of both systems is presented and also discussions about their differences, pros and cons. PMID:22518097

Optimization of current waveform tailoring for magnetically driven isentropic compression experiments.

PubMed

Waisman, E M; Reisman, D B; Stoltzfus, B S; Stygar, W A; Cuneo, M E; Haill, T A; Davis, J-P; Brown, J L; Seagle, C T; Spielman, R B

2016-06-01

The Thor pulsed power generator is being developed at Sandia National Laboratories. The design consists of up to 288 decoupled and transit time isolated capacitor-switch units, called "bricks," that can be individually triggered to achieve a high degree of pulse tailoring for magnetically driven isentropic compression experiments (ICE) [D. B. Reisman et al., Phys. Rev. Spec. Top.-Accel. Beams 18, 090401 (2015)]. The connecting transmission lines are impedance matched to the bricks, allowing the capacitor energy to be efficiently delivered to an ICE strip-line load with peak pressures of over 100 GPa. Thor will drive experiments to explore equation of state, material strength, and phase transition properties of a wide variety of materials. We present an optimization process for producing tailored current pulses, a requirement for many material studies, on the Thor generator. This technique, which is unique to the novel "current-adder" architecture used by Thor, entirely avoids the iterative use of complex circuit models to converge to the desired electrical pulse. We begin with magnetohydrodynamic simulations for a given material to determine its time dependent pressure and thus the desired strip-line load current and voltage. Because the bricks are connected to a central power flow section through transit-time isolated coaxial cables of constant impedance, the brick forward-going pulses are independent of each other. We observe that the desired equivalent forward-going current driving the pulse must be equal to the sum of the individual brick forward-going currents. We find a set of optimal brick delay times by requiring that the L2 norm of the difference between the brick-sum current and the desired forward-going current be a minimum. We describe the optimization procedure for the Thor design and show results for various materials of interest.

Comparison between Frame-Constrained Fix-Pixel-Value and Frame-Free Spiking-Dynamic-Pixel ConvNets for Visual Processing.

PubMed

Farabet, Clément; Paz, Rafael; Pérez-Carrasco, Jose; Zamarreño-Ramos, Carlos; Linares-Barranco, Alejandro; Lecun, Yann; Culurciello, Eugenio; Serrano-Gotarredona, Teresa; Linares-Barranco, Bernabe

2012-01-01

Most scene segmentation and categorization architectures for the extraction of features in images and patches make exhaustive use of 2D convolution operations for template matching, template search, and denoising. Convolutional Neural Networks (ConvNets) are one example of such architectures that can implement general-purpose bio-inspired vision systems. In standard digital computers 2D convolutions are usually expensive in terms of resource consumption and impose severe limitations for efficient real-time applications. Nevertheless, neuro-cortex inspired solutions, like dedicated Frame-Based or Frame-Free Spiking ConvNet Convolution Processors, are advancing real-time visual processing. These two approaches share the neural inspiration, but each of them solves the problem in different ways. Frame-Based ConvNets process frame by frame video information in a very robust and fast way that requires to use and share the available hardware resources (such as: multipliers, adders). Hardware resources are fixed- and time-multiplexed by fetching data in and out. Thus memory bandwidth and size is important for good performance. On the other hand, spike-based convolution processors are a frame-free alternative that is able to perform convolution of a spike-based source of visual information with very low latency, which makes ideal for very high-speed applications. However, hardware resources need to be available all the time and cannot be time-multiplexed. Thus, hardware should be modular, reconfigurable, and expansible. Hardware implementations in both VLSI custom integrated circuits (digital and analog) and FPGA have been already used to demonstrate the performance of these systems. In this paper we present a comparison study of these two neuro-inspired solutions. A brief description of both systems is presented and also discussions about their differences, pros and cons.

Peptides from puff adder Bitis arietans venom, novel inhibitors of nicotinic acetylcholine receptors.

PubMed

Vulfius, Catherine A; Spirova, Ekaterina N; Serebryakova, Marina V; Shelukhina, Irina V; Kudryavtsev, Denis S; Kryukova, Elena V; Starkov, Vladislav G; Kopylova, Nina V; Zhmak, Maxim N; Ivanov, Igor A; Kudryashova, Ksenia S; Andreeva, Tatyana V; Tsetlin, Victor I; Utkin, Yuri N

2016-10-01

Phospholipase A 2 (named bitanarin) possessing capability to block nicotinic acetylcholine receptors (nAChRs) was isolated earlier (Vulfius et al., 2011) from puff adder Bitis arietans venom. Further studies indicated that low molecular weight fractions of puff adder venom inhibit nAChRs as well. In this paper, we report on isolation from this venom and characterization of three novel peptides called baptides 1, 2 and 3 that reversibly block nAChRs. To isolate the peptides, the venom of B. arietans was fractionated by gel-filtration and reversed phase chromatography. The amino acid sequences of peptides were established by de novo sequencing using MALDI mass spectrometry. Baptide 1 comprised 7, baptides 2 and 3-10 amino acid residues, the latter being acetylated at the N-terminus. This is the first indication for the presence of such post-translational modification in snake venom proteins. None of the peptides contain cysteine residues. For biological activity studies the peptides were prepared by solid phase peptide synthesis. Baptide 3 and 2 blocked acetylcholine-elicited currents in isolated Lymnaea stagnalis neurons with IC 50 of about 50 μM and 250 μM, respectively. In addition baptide 2 blocked acetylcholine-induced currents in muscle nAChR heterologously expressed in Xenopus oocytes with IC 50 of about 3 μM. The peptides did not compete with radioactive α-bungarotoxin for binding to Torpedo and α7 nAChRs at concentration up to 200 μM that suggests non-competitive mode of inhibition. Calcium imaging studies on α7 and muscle nAChRs heterologously expressed in mouse neuroblastoma Neuro2a cells showed that on α7 receptor baptide 2 inhibited acetylcholine-induced increasing intracellular calcium concentration with IC 50 of 20.6 ± 3.93 μM. On both α7 and muscle nAChRs the suppression of maximal response to acetylcholine by about 50% was observed at baptide 2 concentration of 25 μM, the value being close to IC 50 on α7 nAChR. These data are in accord with non-competitive inhibition as follows from α-bungarotoxin binding experiments. The described peptides are the shortest peptides without disulfide bridges isolated from animal venom and capable to inhibit nAChR by non-competitive way. Copyright © 2016. Published by Elsevier Ltd.

Designing Novel Quaternary Quantum Reversible Subtractor Circuits

NASA Astrophysics Data System (ADS)

Haghparast, Majid; Monfared, Asma Taheri

2018-01-01

Reversible logic synthesis is an important area of current research because of its ability to reduce energy dissipation. In recent years, multiple valued logic has received great attention due to its ability to reduce the width of the reversible circuit which is a main requirement in quantum technology. Subtractor circuits are between major components used in quantum computers. In this paper, we will discuss the design of a quaternary quantum reversible half subtractor circuit using quaternary 1-qudit, 2-qudit Muthukrishnan-Stroud and 3-qudit controlled gates and a 2-qudit Generalized quaternary gate. Then a design of a quaternary quantum reversible full subtractor circuit based on the quaternary half subtractor will be presenting. The designs shall then be evaluated in terms of quantum cost, constant input, garbage output, and hardware complexity. The proposed quaternary quantum reversible circuits are the first attempt in the designing of the aforementioned subtractor.

Control method for mixed refrigerant based natural gas liquefier

DOEpatents

Kountz, Kenneth J.; Bishop, Patrick M.

2003-01-01

In a natural gas liquefaction system having a refrigerant storage circuit, a refrigerant circulation circuit in fluid communication with the refrigerant storage circuit, and a natural gas liquefaction circuit in thermal communication with the refrigerant circulation circuit, a method for liquefaction of natural gas in which pressure in the refrigerant circulation circuit is adjusted to below about 175 psig by exchange of refrigerant with the refrigerant storage circuit. A variable speed motor is started whereby operation of a compressor is initiated. The compressor is operated at full discharge capacity. Operation of an expansion valve is initiated whereby suction pressure at the suction pressure port of the compressor is maintained below about 30 psig and discharge pressure at the discharge pressure port of the compressor is maintained below about 350 psig. Refrigerant vapor is introduced from the refrigerant holding tank into the refrigerant circulation circuit until the suction pressure is reduced to below about 15 psig, after which flow of the refrigerant vapor from the refrigerant holding tank is terminated. Natural gas is then introduced into a natural gas liquefier, resulting in liquefaction of the natural gas.

ZERO SUPPRESSION FOR RECORDERS

DOEpatents

Fort, W.G.S.

1958-12-30

A zero-suppression circuit for self-balancing recorder instruments is presented. The essential elements of the circuit include a converter-amplifier having two inputs, one for a reference voltage and the other for the signal voltage under analysis, and a servomotor with two control windings, one coupled to the a-c output of the converter-amplifier and the other receiving a reference input. Each input circuit to the converter-amplifier has a variable potentiometer and the sliders of the potentiometer are ganged together for movement by the servoinotor. The particular noveity of the circuit resides in the selection of resistance values for the potentiometer and a resistor in series with the potentiometer of the signal circuit to ensure the full value of signal voltage variation is impressed on a recorder mechanism driven by servomotor.

46 CFR 58.25-65 - Feeder circuits.

Code of Federal Regulations, 2013 CFR

2013-10-01

... seconds of loss of power from the vessel's service switchboard; (2) Comes from an independent source of power in the steering-gear compartment; (3) Is used for no other purpose; and (4) Has a capacity for one... feeder circuit must have a current-carrying capacity of— (1) 125% of the rated full-load current rating...

46 CFR 58.25-65 - Feeder circuits.

Code of Federal Regulations, 2011 CFR

2011-10-01

... seconds of loss of power from the vessel's service switchboard; (2) Comes from an independent source of power in the steering-gear compartment; (3) Is used for no other purpose; and (4) Has a capacity for one... feeder circuit must have a current-carrying capacity of— (1) 125% of the rated full-load current rating...

46 CFR 58.25-65 - Feeder circuits.

Code of Federal Regulations, 2014 CFR

2014-10-01

... seconds of loss of power from the vessel's service switchboard; (2) Comes from an independent source of power in the steering-gear compartment; (3) Is used for no other purpose; and (4) Has a capacity for one... feeder circuit must have a current-carrying capacity of— (1) 125% of the rated full-load current rating...

46 CFR 58.25-65 - Feeder circuits.

Code of Federal Regulations, 2012 CFR

2012-10-01

... seconds of loss of power from the vessel's service switchboard; (2) Comes from an independent source of power in the steering-gear compartment; (3) Is used for no other purpose; and (4) Has a capacity for one... feeder circuit must have a current-carrying capacity of— (1) 125% of the rated full-load current rating...

46 CFR 58.25-65 - Feeder circuits.

Code of Federal Regulations, 2010 CFR

2010-10-01

... seconds of loss of power from the vessel's service switchboard; (2) Comes from an independent source of power in the steering-gear compartment; (3) Is used for no other purpose; and (4) Has a capacity for one... feeder circuit must have a current-carrying capacity of— (1) 125% of the rated full-load current rating...

Microwatt power consumption maximum power point tracking circuit using an analogue differentiator for piezoelectric energy harvesting

NASA Astrophysics Data System (ADS)

Chew, Z. J.; Zhu, M.

2015-12-01

A maximum power point tracking (MPPT) scheme by tracking the open-circuit voltage from a piezoelectric energy harvester using a differentiator is presented in this paper. The MPPT controller is implemented by using a low-power analogue differentiator and comparators without the need of a sensing circuitry and a power hungry controller. This proposed MPPT circuit is used to control a buck converter which serves as a power management module in conjunction with a full-wave bridge diode rectifier. Performance of this MPPT control scheme is verified by using the prototyped circuit to track the maximum power point of a macro-fiber composite (MFC) as the piezoelectric energy harvester. The MFC was bonded on a composite material and the whole specimen was subjected to various strain levels at frequency from 10 to 100 Hz. Experimental results showed that the implemented full analogue MPPT controller has a tracking efficiency between 81% and 98.66% independent of the load, and consumes an average power of 3.187 μW at 3 V during operation.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pfeffer, H.; Saewert, G.

This paper reports on a 6 kV modulator built and installed at Fermilab to drive the electron gun anode for the Tevatron Electron Lens (TEL). The TEL was built with the intention of shifting the individual (anti)proton bunch tunes to even out the tune spread among all 36 bunches with the desire of improving Tevatron integrated luminosity. This modulator is essentially a 6 kV arbitrary waveform generator that enables the TEL to define the electron beam intensity on a bunch-by-bunch basis. A voltage waveform is constructed having a 7 μs duration that corresponds to the tune shift requirements of amore » 12-bunch (anti)proton beam pulse train. This waveform is played out for any one or all three bunch trains in the Tevatron. The programmed waveform voltages transition to different levels at time intervals corresponding to the 395 ns bunch spacing. In addition, complex voltage waveforms can be played out at a sustained rate of 143 kHz over the full 6 kV output range. This paper describes the novel design of the inductive adder topology employing five transformers. It describes the design aspects that minimize switching losses for this multi-kilovolt, high repetition rate and high duty factor application.« less

A Solid-State Modulator for High Speed Kickers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Watson, J A; Cook, E G; Chen, Y J

2001-06-11

An all solid-state modulator with multi-pulse burst capability, very fast rise and fall times, pulse width agility, and amplitude modulation capability for use with high-speed beam kickers has been designed and tested at LLNL. The modulator uses multiple solid-state modules stacked in an inductive-adder configuration. It provides a nominal 18kV pulse with {+-} 10% amplitude modulation on the order of several MHz, rise times on the order of 10nS, and can be configured for either positive or negative polarity. The presentation will include measured performance data.

Evaluation of floating-point sum or difference of products in carry-save domain

NASA Technical Reports Server (NTRS)

Wahab, A.; Erdogan, S.; Premkumar, A. B.

1992-01-01

An architecture to evaluate a 24-bit floating-point sum or difference of products using modified sequential carry-save multipliers with extensive pipelining is described. The basic building block of the architecture is a carry-save multiplier with built-in mantissa alignment for the summation during the multiplication cycles. A carry-save adder, capable of mantissa alignment, correctly positions products with the current carry-save sum. Carry propagation in individual multipliers is avoided and is only required once to produce the final result.

A Prototype Silicon Compiler in Prolog

DTIC Science & Technology

1988-12-01

A Prototype Silicon Compiler in Prolog 04 William Bush Gino Cheng Partrick C. McGeer Alvin M. Despain DTIC ELECTV JUL 281989 B Report No. UCB/CSD 88...the same register to variables in the same positions in invo- cation and head. Thus in ... g(A, B ),.. and g(X, Y) A and X share one register, and B ...example for a one-bit adder is given below. x = compl(or(and(c,or(a, b )),and(a, b ))). y = compl(or(and(x,or(a, b ,c)),and(a2b,c))). sum = compl(y). carry

Optical Carry Adder.

DTIC Science & Technology

1987-03-01

AOM’s) with the deflected beam as the modulator "on" state. These AOM’s ( TeO2 crystals, manufactured by Newport E.O. Systems) have high deflection...caused by the slow acoustic propagation (4.2 - 105 cm/s for TeO2 ), but this delay can be minimized by placing the laser beam close to the acoustic...dependent jitter in the optical carry to below 1 ns, the total carry path must be less than 30 cm long (or 20 cm in glass , 14 cm in LiNbO 3). Thus, a 32

Equivalent circuit for VO{sub 2} phase change material film in reconfigurable frequency selective surfaces

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sanphuang, Varittha; Ghalichechian, Nima; Nahar, Niru K.

We developed equivalent circuits of phase change materials based on vanadium dioxide (VO{sub 2}) thin films. These circuits are used to model VO{sub 2} thin films for reconfigurable frequency selective surfaces (FSSs). This is important as it provides a way for designing complex structures. A reconfigurable FSS filter using VO{sub 2} ON/OFF switches is designed demonstrating −60 dB isolation between the states. This filter is used to provide the transmission and reflection responses of the FSS in the frequency range of 0.1–0.6 THz. The comparison between equivalent circuit and full-wave simulation shows excellent agreement.

Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

NASA Astrophysics Data System (ADS)

Elsobky, Mourad; Mahsereci, Yigit; Keck, Jürgen; Richter, Harald; Burghartz, Joachim N.

2017-09-01

Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

Sub-millimeter-Wave Equivalent Circuit Model for External Parasitics in Double-Finger HEMT Topologies

NASA Astrophysics Data System (ADS)

Karisan, Yasir; Caglayan, Cosan; Sertel, Kubilay

2018-02-01

We present a novel distributed equivalent circuit that incorporates a three-way-coupled transmission line to accurately capture the external parasitics of double-finger high electron mobility transistor (HEMT) topologies up to 750 GHz. A six-step systematic parameter extraction procedure is used to determine the equivalent circuit elements for a representative device layout. The accuracy of the proposed approach is validated in the 90-750 GHz band through comparisons between measured data (via non-contact probing) and full-wave simulations, as well as the equivalent circuit response. Subsequently, a semi-distributed active device model is incorporated into the proposed parasitic circuit to demonstrate that the three-way-coupled transmission line model effectively predicts the adverse effect of parasitic components on the sub-mmW performance in an amplifier setting.

High-voltage crowbar circuit with cascade-triggered series ignitrons

DOEpatents

Baker, William R. [Orinda, CA

1980-11-04

A series string of ignitrons for switching a large current at high voltage to ground. Switching is initiated by means of a negative trigger pulse applied to the cathode of the lowest voltage level ignitron next to ground to draw ground current through diodes in the ignitor circuit. The trigger pulse is applied thereby to the next higher ignitron cathode and sequentially to the remainder of the ignitrons in the string through diodes in respective ignitor circuits. Full line voltage is held off of nonconducting diodes and ignitrons by means of varistors.

High-voltage crowbar circuit with cascade-triggered series ignitrons

DOEpatents

Baker, W.R.

A series string of ignitrons for switching a large current at high voltage to ground is discussed. Switching is initiated by means of a negative trigger pulse applied to the cathode of the lowest voltage level ignitron next to ground to draw ground current through diodes in the ignitor circuit. The trigger pulse is applied thereby to the next higher ignitron cathode and sequentially to the remainder of the ignitrons in the string through diodes in respective ignitor circuits. Full line voltage is held off of nonconducting diodes and ignitrons by means of varistors.

High-voltage crowbar circuit with cascade-triggered series ignitrons

DOEpatents

Baker, W.R.

1980-11-04

A series string of ignitrons for switching a large current at high voltage to ground. Switching is initiated by means of a negative trigger pulse applied to the cathode of the lowest voltage level ignitron next to ground to draw ground current through diodes in the ignitor circuit. The trigger pulse is applied thereby to the next higher ignitron cathode and sequentially to the remainder of the ignitrons in the string through diodes in respective ignitor circuits. Full line voltage is held off of nonconducting diodes and ignitrons by means of varistors. 1 fig.

Full Wave Analysis of Passive Microwave Monolithic Integrated Circuit Devices Using a Generalized Finite Difference Time Domain (GFDTD) Algorithm

NASA Technical Reports Server (NTRS)

Lansing, Faiza S.; Rascoe, Daniel L.

1993-01-01

This paper presents a modified Finite-Difference Time-Domain (FDTD) technique using a generalized conformed orthogonal grid. The use of the Conformed Orthogonal Grid, Finite Difference Time Domain (GFDTD) enables the designer to match all the circuit dimensions, hence eliminating a major source o error in the analysis.

[Not Available].

PubMed

Pecevski, Dejan; Natschläger, Thomas; Schuch, Klaus

2009-01-01

The Parallel Circuit SIMulator (PCSIM) is a software package for simulation of neural circuits. It is primarily designed for distributed simulation of large scale networks of spiking point neurons. Although its computational core is written in C++, PCSIM's primary interface is implemented in the Python programming language, which is a powerful programming environment and allows the user to easily integrate the neural circuit simulator with data analysis and visualization tools to manage the full neural modeling life cycle. The main focus of this paper is to describe PCSIM's full integration into Python and the benefits thereof. In particular we will investigate how the automatically generated bidirectional interface and PCSIM's object-oriented modular framework enable the user to adopt a hybrid modeling approach: using and extending PCSIM's functionality either employing pure Python or C++ and thus combining the advantages of both worlds. Furthermore, we describe several supplementary PCSIM packages written in pure Python and tailored towards setting up and analyzing neural simulations.

60 V tolerance full symmetrical switch for battery monitor IC

NASA Astrophysics Data System (ADS)

Zhang, Qidong; Yang, Yintang; Chai, Changchun

2017-06-01

For stacked battery monitoring IC high speed and high precision voltage acquisition requirements, this paper introduces a kind of symmetrical type high voltage switch circuit. This kind of switch circuit uses the voltage following structure, which eliminates the leakage path of input signals. At the same time, this circuit adopts a high speed charge pump structure, in any case the input signal voltage is higher than the supply voltage, it can fast and accurately turn on high voltage MOS devices, and convert the battery voltage to an analog to digital converter. The proposed high voltage full symmetry switch has been implemented in a 0.18 μm BCD process; simulated and measured results show that the proposed switch can always work properly regardless of the polarity of the voltage difference between the input signal ports and an input signal higher than the power supply. Project supported by the National Natural Science Foundation of China (No. 61334003).

Snakebite enquiries to the UK National Poisons Information Service: 2004-2010.

PubMed

Coulson, James Michael; Cooper, Gillian; Krishna, Channarayapatna; Thompson, John Paul

2013-11-01

To describe trends regarding snakebite enquiries to the UK National Poisons Information Service (NPIS) from 2004 to 2010. The NPIS telephone enquiry database, the UK Poisons Information Database, was interrogated for enquiries to the four NPIS units from 2004 to 2010. Search terms used were 'snake' and 'snakebite'. Information from the national dataset was available from Cardiff and Edinburgh units from 2004 onwards, Birmingham from June 2005 and Newcastle from September 2006. Five hundred and ten cases were identified, of which 69% were male and 31% female. Average age of cases was 32 years (±1 95% CI). The snake was identified as follows: British Adder in 52% of cases, an exotic species in 26%, unknown in 18% and another UK snake in 4%. 82% of cases occurred between the months of April and September. Cases peaked during August (19%). Forty-two per cent of enquiries involved features of envenoming. Eighty-five cases were assessed as requiring antivenom. Eighty-four cases received treatment with antivenom. No adverse reactions to the antivenom were reported and resolution of clinical features was reported in all treated cases. Advice to use an antidote was followed in 98.8% of cases. Snakebites account for one to two NPIS cases per week. Adder bites account for over half of cases. A quarter of cases were due to non-UK snakes kept in captivity within the UK. Envenoming was said to have occurred in just under half of all cases. Advice given by the NPIS appears to closely reflect national practice guidelines.

Defect reduction for semiconductor memory applications using jet and flash imprint lithography

NASA Astrophysics Data System (ADS)

Ye, Zhengmao; Luo, Kang; Irving, J. W.; Lu, Xiaoming; Zhang, Wei; Fletcher, Brian; Liu, Weijun; Xu, Frank; LaBrake, Dwayne; Resnick, Douglas; Sreenivasan, S. V.

2013-03-01

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography (J-FIL) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned resist on the substrate. Acceptance of imprint lithography for manufacturing will require demonstration that it can attain defect levels commensurate with the defect specifications of high end memory devices. Typical defectivity targets are on the order of 0.10/cm2. In previous studies, we have focused on defects such as random non-fill defects occurring during the resist filling process and repeater defects caused by interactions with particles on the substrate. In this work, we attempted to identify the critical imprint defect types using a mask with NAND Flash-like patterns at dimensions as small as 26nm. The two key defect types identified were line break defects induced by small particulates and airborne contaminants which result in local adhesion failure. After identification, the root cause of the defect was determined, and corrective measures were taken to either eliminate or reduce the defect source. As a result, we have been able to reduce defectivity levels by more than three orders of magnitude in only 12 months and are now achieving defectivity adders as small as 2 adders per lot of wafers.

Amorphous In-Ga-Zn-O Thin Film Transistor Current-Scaling Pixel Electrode Circuit for Active-Matrix Organic Light-Emitting Displays

NASA Astrophysics Data System (ADS)

Chen, Charlene; Abe, Katsumi; Fung, Tze-Ching; Kumomi, Hideya; Kanicki, Jerzy

2009-03-01

In this paper, we analyze application of amorphous In-Ga-Zn-O thin film transistors (a-InGaZnO TFTs) to current-scaling pixel electrode circuit that could be used for 3-in. quarter video graphics array (QVGA) full color active-matrix organic light-emitting displays (AM-OLEDs). Simulation results, based on a-InGaZnO TFT and OLED experimental data, show that both device sizes and operational voltages can be reduced when compare to the same circuit using hydrogenated amorphous silicon (a-Si:H) TFTs. Moreover, the a-InGaZnO TFT pixel circuit can compensate for the drive TFT threshold voltage variation (ΔVT) within acceptable operating error range.

An optimized routing algorithm for the automated assembly of standard multimode ribbon fibers in a full-mesh optical backplane

NASA Astrophysics Data System (ADS)

Basile, Vito; Guadagno, Gianluca; Ferrario, Maddalena; Fassi, Irene

2018-03-01

In this paper a parametric, modular and scalable algorithm allowing a fully automated assembly of a backplane fiber-optic interconnection circuit is presented. This approach guarantees the optimization of the optical fiber routing inside the backplane with respect to specific criteria (i.e. bending power losses), addressing both transmission performance and overall costs issues. Graph theory has been exploited to simplify the complexity of the NxN full-mesh backplane interconnection topology, firstly, into N independent sub-circuits and then, recursively, into a limited number of loops easier to be generated. Afterwards, the proposed algorithm selects a set of geometrical and architectural parameters whose optimization allows to identify the optimal fiber optic routing for each sub-circuit of the backplane. The topological and numerical information provided by the algorithm are then exploited to control a robot which performs the automated assembly of the backplane sub-circuits. The proposed routing algorithm can be extended to any array architecture and number of connections thanks to its modularity and scalability. Finally, the algorithm has been exploited for the automated assembly of an 8x8 optical backplane realized with standard multimode (MM) 12-fiber ribbons.

Simulation and measurement of a Ka-band HTS MMIC Josephson junction mixer

NASA Astrophysics Data System (ADS)

Zhang, Ting; Pegrum, Colin; Du, Jia; Guo, Yingjie Jay

2017-01-01

We report modeling and simulation results for a Ka band high-temperature superconducting (HTS) monolithic microwave integrated circuit (MMIC) Josephson junction mixer. A Verilog-A model of a Josephson junction is established and imported into the system simulator to realize a full HTS MMIC circuit simulation containing the HTS passive circuit models. Impedance matching optimization between the junction and passive devices is investigated. Junction DC I-V characteristics, current and local oscillator bias conditions and mixing performance are simulated and compared with the experimental results. Good agreement is obtained between the simulation and measurement results.

Techniques for Computing the DFT Using the Residue Fermat Number Systems and VLSI

NASA Technical Reports Server (NTRS)

Truong, T. K.; Chang, J. J.; Hsu, I. S.; Pei, D. Y.; Reed, I. S.

1985-01-01

The integer complex multiplier and adder over the direct sum of two copies of a finite field is specialized to the direct sum of the rings of integers modulo Fermat numbers. Such multiplications and additions can be used in the implementation of a discrete Fourier transform (DFT) of a sequence of complex numbers. The advantage of the present approach is that the number of multiplications needed for the DFT can be reduced substantially over the previous approach. The architectural designs using this approach are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

Modified signed-digit trinary addition using synthetic wavelet filter

NASA Astrophysics Data System (ADS)

Iftekharuddin, K. M.; Razzaque, M. A.

2000-09-01

The modified signed-digit (MSD) number system has been a topic of interest as it allows for parallel carry-free addition of two numbers for digital optical computing. In this paper, harmonic wavelet joint transform (HWJT)-based correlation technique is introduced for optical implementation of MSD trinary adder implementation. The realization of the carry-propagation-free addition of MSD trinary numerals is demonstrated using synthetic HWJT correlator model. It is also shown that the proposed synthetic wavelet filter-based correlator shows high performance in logic processing. Simulation results are presented to validate the performance of the proposed technique.

Venomous snakebites.

PubMed

Adukauskienė, Dalia; Varanauskienė, Eglė; Adukauskaitė, Agnė

2011-01-01

More than 5 million people are bitten by venomous snakes annually and more than 100,000 of them die. In Europe, one person dies due to envenomation every 3 years. There is only one venomous snake species in Lithuania--the common adder (Vipera berus)--which belongs to the Viperidae family; however, there are some exotic poisonous snakes in the zoos and private collections, such as those belonging to the Elapidae family (cobras, mambas, coral snakes, etc.) and the Crotalidae subfamily of the Viperidae family (pit vipers, such as rattlesnakes). Snake venom can be classified into hemotoxic, neurotoxic, necrotoxic, cardiotoxic, and nephrotoxic according to the different predominant effects depending on the family (i.e., venom of Crotalidae and Viperidae snakes is more hemotoxic and necrotoxic, whereas venom of Elapidae family is mainly neurotoxic). The intoxication degree is estimated according to the appearance of these symptoms: 1) no intoxication ("dry" bite); 2) mild intoxication (local edema and pain); 3) moderate intoxication (pain, edema spreading out of the bite zone, and systemic signs); 4) severe intoxication (shock, severe coagulopathy, and massive edemas). This topic is relevant because people tend to make major mistakes providing first aid (e.g., mouth suction, wound incision, and application of ice or heat). Therefore, this article presents the essential tips on how first aid should be performed properly according to the "Guidelines for the Management of Snake-Bites" by the World Health Organization (2010). Firstly, the victim should be reassured. Rings or other things must be removed preventing constriction of the swelling limb. Airway/breathing must be maintained. The bitten limb should be immobilized and kept below heart level to prevent venom absorption and systemic spread. Usage of pressure bandage is controversial since people usually apply it improperly. Incision, mouth suction, or excision should not be performed; neither a tourniquet nor ice or heat should be applied. A doctor must monitor respiratory rate, blood pressure, heart rate, renal function, fluid balance, and coagulation status. The only specific treatment method is antivenin--serum with antibodies against antigens of snake venom. Antivenins against pit vipers used in the United States are Antivenin Crotalidae Polyvalent (ACP) and a more purified and hence causing less adverse reactions--Crotalidae Polyvalent Immune Fab (CroFab). In Europe, a polyvalent antiserum against Viperidae family snakes (including the common adder) can be used. Antivenins often may cause severe hypersensitivity reactions because of their protein nature. The bite of the common adder (the only poisonous snake in such countries as Lithuania and Great Britain) relatively rarely results in death; thus, considering the risk of dangerous reactions the antivenin causes itself, the usage of it is recommended to be limited only to life-threatening conditions.

Improved Short-Circuit Protection for Power Cells in Series

NASA Technical Reports Server (NTRS)

Davies, Francis

2008-01-01

A scheme for protection against short circuits has been devised for series strings of lithium electrochemical cells that contain built-in short-circuit protection devices, which go into a high-resistance, current-limiting state when heated by excessive current. If cells are simply connected in a long series string to obtain a high voltage and a short circuit occurs, whichever short-circuit protection device trips first is exposed to nearly the full string voltage, which, typically, is large enough to damage the device. Depending on the specific cell design, the damage can defeat the protective function, cause a dangerous internal short circuit in the affected cell, and/or cascade to other cells. In the present scheme, reverse diodes rated at a suitably high current are connected across short series sub-strings, the lengths of which are chosen so that when a short-circuit protection device is tripped, the voltage across it does not exceed its rated voltage. This scheme preserves the resetting properties of the protective devices. It provides for bypassing of cells that fail open and limits cell reversal, though not as well as does the more-expensive scheme of connecting a diode across every cell.

Integrated circuits and logic operations based on single-layer MoS2.

PubMed

Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

2011-12-27

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

Documentation of Stainless Steel Lithium Circuit Test Section Design. Suppl

NASA Technical Reports Server (NTRS)

Godfroy, Thomas J. (Compiler); Martin, James J.

2010-01-01

The Early Flight Fission-Test Facilities (EFF-TF) team was tasked by Naval Reactors Prime Contract Team (NRPCT) to design, fabricate, and test an actively pumped lithium (Li) flow circuit. This Li circuit takes advantage of work in progress at the EFF TF on a stainless steel sodium/potassium (NaK) circuit. The effort involved modifying the original stainless steel NaK circuit such that it could be operated with Li in place of NaK. This new design considered freeze/thaw issues and required the addition of an expansion tank and expansion/extrusion volumes in the circuit plumbing. Instrumentation has been specified for Li and circuit heaters have been placed throughout the design to ensure adequate operational temperatures and no uncontrolled freezing of the Li. All major components have been designed and fabricated prior to circuit redesign for Li and were not modified. Basic circuit components include: reactor segment, Li to gas heat exchanger, electromagnetic liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. The reactor segment, based on a Los Alamos National Laboratory 100-kW design study with 120 fuel pins, is the only prototypic component in the circuit. However, due to earlier funding constraints, a 37-pin partial-array of the core, including the central three rings of fuel pins (pin and flow path dimensions are the same as those in the full design), was selected for fabrication and test. This Technical Publication summarizes the design and integration of the pumped liquid metal Li flow circuit as of May 1, 2005. This supplement contains drawings, analysis, and calculations

Documentation of Stainless Steel Lithium Circuit Test Section Design

NASA Technical Reports Server (NTRS)

Godfroy, T. J.; Martin, J. J.; Stewart, E. T.; Rhys, N. O.

2010-01-01

The Early Flight Fission-Test Facilities (EFF-TF) team was tasked by Naval Reactors Prime Contract Team (NRPCT) to design, fabricate, and test an actively pumped lithium (Li) flow circuit. This Li circuit takes advantage of work in progress at the EFF TF on a stainless steel sodium/potassium (NaK) circuit. The effort involved modifying the original stainless steel NaK circuit such that it could be operated with Li in place of NaK. This new design considered freeze/thaw issues and required the addition of an expansion tank and expansion/extrusion volumes in the circuit plumbing. Instrumentation has been specified for Li and circuit heaters have been placed throughout the design to ensure adequate operational temperatures and no uncontrolled freezing of the Li. All major components have been designed and fabricated prior to circuit redesign for Li and were not modified. Basic circuit components include: reactor segment, Li to gas heat exchanger, electromagnetic liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. The reactor segment, based on a Los Alamos National Laboratory 100-kW design study with 120 fuel pins, is the only prototypic component in the circuit. However, due to earlier funding constraints, a 37-pin partial-array of the core, including the central three rings of fuel pins (pin and flow path dimensions are the same as those in the full design), was selected for fabrication and test. This Technical Publication summarizes the design and integration of the pumped liquid metal Li flow circuit as of May 1, 2005.

A Integrated Circuit for a Biomedical Capacitive Pressure Transducer

NASA Astrophysics Data System (ADS)

Smith, Michael John Sebastian

Medical research has an urgent need for a small, accurate, stable, low-power, biocompatible and inexpensive pressure sensor with a zero to full-scale range of 0-300 mmHg. An integrated circuit (IC) for use with a capacitive pressure transducer was designed, built and tested. The random pressure measurement error due to resolution and non-linearity is (+OR-)0.4 mmHg (at mid-range with a full -scale of 300 mmHg). The long-term systematic error due to falling battery voltage is (+OR-)0.6 mmHg. These figures were calculated from measurements of temperature, supply dependence and non-linearity on completed integrated circuits. The sensor IC allows measurement of temperature to (+OR-)0.1(DEGREES)C to allow for temperature compensation of the transducer. Novel micropower circuit design of the system components enabled these levels of accuracy to be reached. Capacitance is measured by a new ratiometric scheme employing an on -chip reference capacitor. This method greatly reduces the effects of voltage supply, temperature and manufacturing variations on the sensor circuit performance. The limits on performance of the bandgap reference circuit fabricated with a standard bipolar process using ion-implanted resistors were determined. Measurements confirm the limits of temperature stability as approximately (+OR-)300 ppm/(DEGREES)C. An exact analytical expression for the period of the Schmitt trigger oscillator, accounting for non-constant capacitor charging current, was formulated. Experiments to test agreement with theory showed that prediction of the oscillator period was very accurate. The interaction of fundamental and practical limits on the scaling of the transducer size was investigated including a correction to previous theoretical analysis of jitter in an RC oscillator. An areal reduction of 4 times should be achievable.

Resistive pressure of a condenser humidifier in mechanically ventilated patients.

PubMed

Manthous, C A; Schmidt, G A

1994-11-01

Heat and moisture exchangers (or "nose" humidifiers) are commonly used to aid in the humidification of inspired gases of mechanically ventilated patients. These devices add resistance to the ventilator circuit that has heretofore not been quantified in critically ill patients. Accordingly, we determined the resistive pressures associated with new and old (but < 24 hrs in the circuit) humidifiers in 23 critically ill, mechanically ventilated patients. Prospective study. Adult medical and surgical intensive care units at a university center. Twenty-three critically ill, mechanically ventilated patients using a condenser humidifier between the wye and the endotracheal tube. Peak and plateau airway pressures were determined with the humidifier in place. These measurements were repeated without the humidifier, then after insertion of a fresh humidifier into the circuit. In five patients, measurements were repeated after humidifiers had remained in place for a full 24 hrs. The new humidifiers increased the resistive pressure of the ventilator circuit by 4.8 +/- 2.6 cm H2O compared with no humidifier (p < .01) and had a mean resistance of 4.2 +/- 1.5 cm H2O/L/sec. Old humidifiers increased resistive pressure by 6.3 +/- 3.6 cm H2O compared with no humidifier (p < .01) and had a mean resistance of 5.1 +/- 1.8 cm H2O/L/sec. The resistive pressure doubled from 3.4 +/- 1.2 to 7.0 +/- 1.8 cm H2O (p < .01) in five patients in whom the humidifiers were left in the ventilator circuit for a full 24 hrs. The humidifier adds a significant resistance to the ventilator circuit which may lead to incorrect assessment of respiratory system mechanics, to inappropriate therapy (e.g., bronchodilators), or to difficulty in weaning from mechanical ventilation.

Measuring User Similarity Using Electric Circuit Analysis: Application to Collaborative Filtering

PubMed Central

Yang, Joonhyuk; Kim, Jinwook; Kim, Wonjoon; Kim, Young Hwan

2012-01-01

We propose a new technique of measuring user similarity in collaborative filtering using electric circuit analysis. Electric circuit analysis is used to measure the potential differences between nodes on an electric circuit. In this paper, by applying this method to transaction networks comprising users and items, i.e., user–item matrix, and by using the full information about the relationship structure of users in the perspective of item adoption, we overcome the limitations of one-to-one similarity calculation approach, such as the Pearson correlation, Tanimoto coefficient, and Hamming distance, in collaborative filtering. We found that electric circuit analysis can be successfully incorporated into recommender systems and has the potential to significantly enhance predictability, especially when combined with user-based collaborative filtering. We also propose four types of hybrid algorithms that combine the Pearson correlation method and electric circuit analysis. One of the algorithms exceeds the performance of the traditional collaborative filtering by 37.5% at most. This work opens new opportunities for interdisciplinary research between physics and computer science and the development of new recommendation systems PMID:23145095

Measuring user similarity using electric circuit analysis: application to collaborative filtering.

PubMed

Yang, Joonhyuk; Kim, Jinwook; Kim, Wonjoon; Kim, Young Hwan

2012-01-01

We propose a new technique of measuring user similarity in collaborative filtering using electric circuit analysis. Electric circuit analysis is used to measure the potential differences between nodes on an electric circuit. In this paper, by applying this method to transaction networks comprising users and items, i.e., user-item matrix, and by using the full information about the relationship structure of users in the perspective of item adoption, we overcome the limitations of one-to-one similarity calculation approach, such as the Pearson correlation, Tanimoto coefficient, and Hamming distance, in collaborative filtering. We found that electric circuit analysis can be successfully incorporated into recommender systems and has the potential to significantly enhance predictability, especially when combined with user-based collaborative filtering. We also propose four types of hybrid algorithms that combine the Pearson correlation method and electric circuit analysis. One of the algorithms exceeds the performance of the traditional collaborative filtering by 37.5% at most. This work opens new opportunities for interdisciplinary research between physics and computer science and the development of new recommendation systems.

Benefits of Compression Garments Worn During Handball-Specific Circuit on Short-Term Fatigue in Professional Players.

PubMed

Ravier, Gilles; Bouzigon, Romain; Beliard, Samuel; Tordi, Nicolas; Grappe, Frederic

2018-04-04

Ravier, G, Bouzigon, R, Beliard, S, Tordi, N, and Grappe, F. Benefits of compression garments worn during handball-specific circuit on short-term fatigue in professional players. J Strength Cond Res XX(X): 000-000, 2016-The purpose of this study was to investigate the benefits of full-leg length compression garments (CGs) worn during a handball-specific circuit exercises on athletic performance and acute fatigue-induced changes in strength and muscle soreness in professional handball players. Eighteen men (mean ± SD: age 23.22 ± 4.97 years; body mass: 82.06 ± 9.69 kg; height: 184.61 ± 4.78 cm) completed 2 identical sessions either wearing regular gym short or CGs in a randomized crossover design. Exercise circuits of explosive activities included 3 periods of 12 minutes of sprints, jumps, and agility drills every 25 seconds. Before, immediately after and 24 hours postexercise, maximal voluntary knee extension (maximal voluntary contraction, MVC), rate of force development (RFD), and muscle soreness were assessed. During the handball-specific circuit sprint and jump performances were unchanged in both conditions. Immediately after performing the circuit exercises MVC, RFD, and PPT decreased significantly compared with preexercise with CGs and noncompression clothes. Decrement was similar in both conditions for RFD (effect size, ES = 0.40) and PPT for the soleus (ES = 0.86). However, wearing CGs attenuated decrement in MVC (p < 0.001) with a smaller decrease (ES = 1.53) in CGs compared with regular gym shorts condition (-5.4 vs. -18.7%, respectively). Full recovery was observed 24 hours postexercise in both conditions for muscle soreness, MVC, and RFD. These findings suggest that wearing CGs during a handball-specific circuit provides benefits on the impairment of the maximal muscle force characteristics and is likely to be worthwhile for handball players involved in activities such as tackles.

Analog front-end design of the STS/MUCH-XYTER2—full size prototype ASIC for the CBM experiment

NASA Astrophysics Data System (ADS)

Kleczek, Rafal

2017-01-01

The design of the analog front-end of the STS/MUCH-XYTER2 ASIC, a full-size prototype chip for the Silicon Tracking System (STS, based on double-sided silicon strip sensors) and Muon Chamber (MUCH, based on gas sensors) detectors is presented. The ASIC contains 128 charge processing channels, each built of a charge sensitive amplifier, a polarity selection circuit and two pulse shaping amplifiers forming two parallel signal paths. The first path is used for timing measurement with a fast discriminator. The second path allows low-noise amplitude measurement with a 5-bit continuous-time flash ADC. Different operating conditions and constraints posed by two target detectors' applications require front-end electronics flexibility to meet extended system-wise requirements. The presented circuit implements switchable shaper peaking time, gain switching and trimming, input amplifier pulsed reset circuit, fail-safe measures. The power consumption is scalable (for the STS and the MUCH modes), but limited to 10 mW/channel.

Operating scheme for the light-emitting diode array of a volumetric display that exhibits multiple full-color dynamic images

NASA Astrophysics Data System (ADS)

Hirayama, Ryuji; Shiraki, Atsushi; Nakayama, Hirotaka; Kakue, Takashi; Shimobaba, Tomoyoshi; Ito, Tomoyoshi

2017-07-01

We designed and developed a control circuit for a three-dimensional (3-D) light-emitting diode (LED) array to be used in volumetric displays exhibiting full-color dynamic 3-D images. The circuit was implemented on a field-programmable gate array; therefore, pulse-width modulation, which requires high-speed processing, could be operated in real time. We experimentally evaluated the developed system by measuring the luminance of an LED with varying input and confirmed that the system works appropriately. In addition, we demonstrated that the volumetric display exhibits different full-color dynamic two-dimensional images in two orthogonal directions. Each of the exhibited images could be obtained only from the prescribed viewpoint. Such directional characteristics of the system are beneficial for applications, including digital signage, security systems, art, and amusement.

A 6 kV arbitrary waveform generator for the Tevatron Electron Lens

DOE PAGES

Pfeffer, H.; Saewert, G.

2011-11-09

This paper reports on a 6 kV modulator built and installed at Fermilab to drive the electron gun anode for the Tevatron Electron Lens (TEL). The TEL was built with the intention of shifting the individual (anti)proton bunch tunes to even out the tune spread among all 36 bunches with the desire of improving Tevatron integrated luminosity. This modulator is essentially a 6 kV arbitrary waveform generator that enables the TEL to define the electron beam intensity on a bunch-by-bunch basis. A voltage waveform is constructed having a 7 μs duration that corresponds to the tune shift requirements of amore » 12-bunch (anti)proton beam pulse train. This waveform is played out for any one or all three bunch trains in the Tevatron. The programmed waveform voltages transition to different levels at time intervals corresponding to the 395 ns bunch spacing. In addition, complex voltage waveforms can be played out at a sustained rate of 143 kHz over the full 6 kV output range. This paper describes the novel design of the inductive adder topology employing five transformers. It describes the design aspects that minimize switching losses for this multi-kilovolt, high repetition rate and high duty factor application.« less

A compact physical model for the simulation of pNML-based architectures

NASA Astrophysics Data System (ADS)

Turvani, G.; Riente, F.; Plozner, E.; Schmitt-Landsiedel, D.; Breitkreutz-v. Gamm, S.

2017-05-01

Among emerging technologies, perpendicular Nanomagnetic Logic (pNML) seems to be very promising because of its capability of combining logic and memory onto the same device, scalability, 3D-integration and low power consumption. Recently, Full Adder (FA) structures clocked by a global magnetic field have been experimentally demonstrated and detailed characterizations of the switching process governing the domain wall (DW) nucleation probability Pnuc and time tnuc have been performed. However, the design of pNML architectures represent a crucial point in the study of this technology; this can have a remarkable impact on the reliability of pNML structures. Here, we present a compact model developed in VHDL which enables to simulate complex pNML architectures while keeping into account critical physical parameters. Therefore, such parameters have been extracted from the experiments, fitted by the corresponding physical equations and encapsulated into the proposed model. Within this, magnetic structures are decomposed into a few basic elements (nucleation centers, nanowires, inverters etc.) represented by the according physical description. To validate the model, we redesigned a FA and compared our simulation results to the experiment. With this compact model of pNML devices we have envisioned a new methodology which makes it possible to simulate and test the physical behavior of complex architectures with very low computational costs.

Reliability assessment and improvement for a fast corrector power supply in TPS

NASA Astrophysics Data System (ADS)

Liu, Kuo-Bin; Liu, Chen-Yao; Wang, Bao-Sheng; Wong, Yong Seng

2018-07-01

Fast Orbit Feedback System (FOFB) can be installed in a synchrotron light source to eliminate undesired disturbances and to improve the stability of beam orbit. The design and implementation of an accurate and reliable Fast Corrector Power Supply (FCPS) is essential to realize the effectiveness and availability of the FOFB. A reliability assessment for the FCPSs in the FOFB of Taiwan Photon Source (TPS) considering MOSFETs' temperatures is represented in this paper. The FCPS is composed of a full-bridge topology and a low-pass filter. A Hybrid Pulse Width Modulation (HPWM) requiring two MOSFETs in the full-bridge circuit to be operated at high frequency and the other two be operated at the output frequency is adopted to control the implemented FCPS. Due the characteristic of HPWM, the conduction loss and switching loss of each MOSFET in the FCPS is not same. Two of the MOSFETs in the full-bridge circuit will suffer higher temperatures and therefore the circuit reliability of FCPS is reduced. A Modified PWM Scheme (MPWMS) designed to average MOSFETs' temperatures and to improve circuit reliability is proposed in this paper. Experimental results measure the MOSFETs' temperatures of FCPS controlled by the HPWM and the proposed MPWMS. The reliability indices under different PWM controls are then assessed. From the experimental results, it can be observed that the reliability of FCPS using the proposed MPWMS can be improved because the MOSFETs' temperatures are closer. Since the reliability of FCPS can be enhanced, the availability of FOFB can also be improved.

Two stage kickdown control system for a motor vehicle automatic transmission

DOE Office of Scientific and Technical Information (OSTI.GOV)

Higashi, H.; Waki, K.; Fukuiri, M.

This patent describes a vehicle automatic transmission including a hydraulic torque converter and a transmission gear mechanism connected with the torque converter and having at least three gear stages of different gear ratios for forward drive. A principal feature of this system as described is a friction means for selecting one of the gear stages as well as a kickdown control means consisting of the first shift down circuit means for control of the friction means so that the transmission gear mechanism is shifted downward. A solenoid kick down means within the modality of the first shift down circuit andmore » a kick down switch means actuated by an engine control member when it is moved to a full power position provides control of the kick down solenoid and the effecting of a down shift. The shift down control means is composed of a second shift down circuit means for controlling the friction means so shift down occurs. The shift down solenoid contained in the second shift down circuit means in conjunction with a shift down switch actuated by engine control member movement to a position spaced a predetermined distance from the full power position control the shift down solenoid to effect a shift down. Thus this mechanism is actuated earlier than the kickdown switch means when the engine control member is moved toward the full power position. A time delay means from the time of actuation of the shift down switch means and controlling kickdown switch activation is also described.« less

Equivalent-circuit model for stacked slot-based 2D periodic arrays of arbitrary geometry for broadband analysis

NASA Astrophysics Data System (ADS)

Astorino, Maria Denise; Frezza, Fabrizio; Tedeschi, Nicola

2018-03-01

The analysis of the transmission and reflection spectra of stacked slot-based 2D periodic structures of arbitrary geometry and the ability to devise and control their electromagnetic responses have been a matter of extensive research for many decades. The purpose of this paper is to develop an equivalent Π circuit model based on the transmission-line theory and Floquet harmonic interactions, for broadband and short longitudinal period analysis. The proposed circuit model overcomes the limits of identical and symmetrical configurations imposed by the even/odd excitation approach, exploiting both the circuit topology of a single 2D periodic array of apertures and the ABCD matrix formalism. The transmission spectra obtained through the equivalent-circuit model have been validated by comparison with full-wave simulations carried out with a finite-element commercial electromagnetic solver. This allowed for a physical insight into the spectral and angular responses of multilayer devices with arbitrary aperture shapes, guaranteeing a noticeable saving of computational resources.

TFT-Directed Electroplating of RGB Luminescent Films without a Vacuum or Mask toward a Full-Color AMOLED Pixel Matrix.

PubMed

Wang, Rong; Zhang, Donglian; Xiong, You; Zhou, Xuehong; Liu, Cao; Chen, Weifeng; Wu, Weijing; Zhou, Lei; Xu, Miao; Wang, Lei; Liu, Linlin; Peng, Junbiao; Ma, Yuguang; Cao, Yong

2018-05-30

The thin-film transistor (TFT) driving circuit is a separate electronic component embedded within the panel itself to switch the current for each pixel in active-matrix organic light-emitting diode displays. We reported a TFT-directed dye electroplating method to fabricate pixels; this would be a new method to deposit films on prepatterned electrode for organic full-color display, where TFT driving circuit provide a switching current signal to drive and direct dye depositing on selected RGB pixels. A prototype patterned color pixel matrix was achieved, as high-quality light-emitting films with uniform morphology, pure RGB chromaticity, and stable output.

Designing a 25-kilowatt high frequency series resonant

NASA Technical Reports Server (NTRS)

Robson, R. R.

1984-01-01

The feasibility of processing 25 kW of power with a single, transistorized, 20 kHz, series resonant converter stage has been demonstrated by the successful design, development, fabrication, and testing of such a device. It employs four Westinghouse D7ST transistors in a full-bridge configuration and operates from a 250-to-350-Vdc input bus. The unit has an overall worst-case efficiency of 93.5% at its full rated output of 1000 V and 25 A dc. A solid-state dc input circuit breaker and output-transient-current limiters are included in and integrated into the design. Circuit details of the converter are presented along with test data.

Assembly and Thermal Hydraulic Test of a Stainless Steel Sodium-Potassium Circuit

NASA Technical Reports Server (NTRS)

Garber, A.; Godfroy, T.; Webster, K.

2007-01-01

Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the NASA Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system was originally built for use with lithium, but due to a shift in focus, it was redesigned for use with a eutectic mixture of sodium potassium (NaK). Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This paper summarizes the first fill and checkout testing of the Stainless Steel NaK-Cooled Circuit (SNaKC).

Capabilities and Testing of the Fission Surface Power Primary Test Circuit (FSP-PTC)

NASA Technical Reports Server (NTRS)

Garber, Anne E.

2007-01-01

An actively pumped alkali metal flow circuit, designed and fabricated at the NASA Marshall Space Flight Center, is currently undergoing testing in the Early Flight Fission Test Facility (EFF-TF). Sodium potassium (NaK), which was used in the SNAP-10A fission reactor, was selected as the primary coolant. Basic circuit components include: simulated reactor core, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, liquid metal flowmeter, load/drain reservoir, expansion reservoir, test section, and instrumentation. Operation of the circuit is based around a 37-pin partial-array core (pin and flow path dimensions are the same as those in a full core), designed to operate at 33 kWt. NaK flow rates of greater than 1 kg/sec may be achieved, depending upon the power applied to the EM pump. The heat exchanger provides for the removal of thermal energy from the circuit, simulating the presence of an energy conversion system. The presence of the test section increases the versatility of the circuit. A second liquid metal pump, an energy conversion system, and highly instrumented thermal simulators are all being considered for inclusion within the test section. This paper summarizes the capabilities and ongoing testing of the Fission Surface Power Primary Test Circuit (FSP-PTC).

Operateurs et engins de calcul en virgule flottante et leur application a la simulation en temps reel sur FPGA

NASA Astrophysics Data System (ADS)

Ould Bachir, Tarek

The real-time simulation of electrical networks gained a vivid industrial interest during recent years, motivated by the substantial development cost reduction that such a prototyping approach can offer. Real-time simulation allows the progressive inclusion of real hardware during its development, allowing its testing under realistic conditions. However, CPU-based simulations suffer from certain limitations such as the difficulty to reach time-steps of a few microsecond, an important challenge brought by modern power converters. Hence, industrial practitioners adopted the FPGA as a platform of choice for the implementation of calculation engines dedicated to the rapid real-time simulation of electrical networks. The reconfigurable technology broke the 5 kHz switching frequency barrier that is characteristic of CPU-based simulations. Moreover, FPGA-based real-time simulation offers many advantages, including the reduced latency of the simulation loop that is obtained thanks to a direct access to sensors and actuators. The fixed-point format is paradigmatic to FPGA-based digital signal processing. However, the format imposes a time penalty in the development process since the designer has to asses the required precision for all model variables. This fact brought an import research effort on the use of the floating-point format for the simulation of electrical networks. One of the main challenges in the use of the floating-point format are the long latencies required by the elementary arithmetic operators, particularly when an adder is used as an accumulator, an important building bloc for the implementation of integration rules such as the trapezoidal method. Hence, single-cycle floating-point accumulation forms the core of this research work. Our results help building such operators as accumulators, multiply-accumulators (MACs), and dot-product (DP) operators. These operators play a key role in the implementation of the proposed calculation engines. Therefore, this thesis contributes to the realm of FPGA-based real-time simulation in many ways. The research work proposes a new summation algorithm, which is a generalization of the so-called self-alignment technique. The new formulation is broader, simpler in its expression and hardware implementation. Our research helps formulating criteria to guarantee good accuracy, the criteria being established on a theoretical, as well as empirical basis. Moreover, the thesis offers a comprehensive analysis on the use of the redundant high radix carry-save (HRCS) format. The HRCS format is used to perform rapid additions of large mantissas. Two new HRCS operators are also proposed, namely an endomorphic adder and a HRCS to conventional converter. Once the mean to single-cycle accumulation is defined as a combination of the self-alignment technique and the HRCS format, the research focuses on the FPGA implementation of SIMD calculation engines using parallel floating-point MACs or DPs. The proposed operators are characterized by low latencies, allowing the engines to reach very low time-steps. The document finally discusses power electronic circuits modelling, and concludes with the presentation of a versatile calculation engine capable of simulating power converter with arbitrary topologies and up to 24 switches, while achieving time steps below 1 mus and allowing switching frequencies in the range of tens kilohertz. The latter realization has led to commercialization of a product by our industrial partner.

A Design Methodology for Switched-Capacitor DC-DC Converters

DTIC Science & Technology

2009-05-21

phase piezoelectric energy harvesters ,” IEEE International Solid-State Circuits Conference, pp. 302–303, Feb. 2008. [20] P. Hazucha, G. Schrom, J. Hahn...2007. [42] Y. K. Ramadass and A. P. Chandrakasan, “An efficient piezoelectric energy- harvesting interface circuit using a bias-flip rectifier and...made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to

VHDL Modeling and Simulation of a Digital Image Synthesizer for Countering ISAR

DTIC Science & Technology

2003-06-01

This thesis discusses VHDL modeling and simulation of a full custom Application Specific Integrated Circuit (ASIC) for a Digital Image Synthesizer...necessary for a given application . With such a digital method, it is possible for a small ship to appear as large as an aircraft carrier or any high...INTRODUCTION TO DIGITAL IMAGE SYNTHESIZER (DIS) A. BACKGROUND The Digital Image Synthesizer (DIS) is an Application Specific Integrated Circuit

A simple second-order digital phase-locked loop.

NASA Technical Reports Server (NTRS)

Tegnelia, C. R.

1972-01-01

A simple second-order digital phase-locked loop has been designed for the Viking Orbiter 1975 command system. Excluding analog-to-digital conversion, implementation of the loop requires only an adder/subtractor, two registers, and a correctable counter with control logic. The loop considers only the polarity of phase error and corrects system clocks according to a filtered sequence of this polarity. The loop is insensitive to input gain variation, and therefore offers the advantage of stable performance over long life. Predictable performance is guaranteed by extreme reliability of acquisition, yet in the steady state the loop produces only a slight degradation with respect to analog loop performance.

Implementation of Arithmetic and Nonarithmetic Functions on a Label-free and DNA-based Platform

NASA Astrophysics Data System (ADS)

Wang, Kun; He, Mengqi; Wang, Jin; He, Ronghuan; Wang, Jianhua

2016-10-01

A series of complex logic gates were constructed based on graphene oxide and DNA-templated silver nanoclusters to perform both arithmetic and nonarithmetic functions. For the purpose of satisfying the requirements of progressive computational complexity and cost-effectiveness, a label-free and universal platform was developed by integration of various functions, including half adder, half subtractor, multiplexer and demultiplexer. The label-free system avoided laborious modification of biomolecules. The designed DNA-based logic gates can be implemented with readout of near-infrared fluorescence, and exhibit great potential applications in the field of bioimaging as well as disease diagnosis.

Note: A pulsed laser ion source for linear induction accelerators

NASA Astrophysics Data System (ADS)

Zhang, H.; Zhang, K.; Shen, Y.; Jiang, X.; Dong, P.; Liu, Y.; Wang, Y.; Chen, D.; Pan, H.; Wang, W.; Jiang, W.; Long, J.; Xia, L.; Shi, J.; Zhang, L.; Deng, J.

2015-01-01

We have developed a high-current laser ion source for induction accelerators. A copper target was irradiated by a frequency-quadrupled Nd:YAG laser (266 nm) with relatively low intensities of 108 W/cm2. The laser-produced plasma supplied a large number of Cu+ ions (˜1012 ions/pulse) during several microseconds. Emission spectra of the plasma were observed and the calculated electron temperature was about 1 eV. An induction voltage adder extracted high-current ion beams over 0.5 A/cm2 from a plasma-prefilled gap. The normalized beam emittance measured by a pepper-pot method was smaller than 1 π mm mrad.

A Low-Complexity and High-Performance 2D Look-Up Table for LDPC Hardware Implementation

NASA Astrophysics Data System (ADS)

Chen, Jung-Chieh; Yang, Po-Hui; Lain, Jenn-Kaie; Chung, Tzu-Wen

In this paper, we propose a low-complexity, high-efficiency two-dimensional look-up table (2D LUT) for carrying out the sum-product algorithm in the decoding of low-density parity-check (LDPC) codes. Instead of employing adders for the core operation when updating check node messages, in the proposed scheme, the main term and correction factor of the core operation are successfully merged into a compact 2D LUT. Simulation results indicate that the proposed 2D LUT not only attains close-to-optimal bit error rate performance but also enjoys a low complexity advantage that is suitable for hardware implementation.

Factors affecting the output pulse flatness of the linear transformer driver cavity systems with 5th harmonics

DOE PAGES

Alexeenko, V. M.; Mazarakis, M. G.; Kim, A. A.; ...

2016-09-19

Here, we describe the study we have undertaken to evaluate the effect of component tolerances in obtaining a voltage output flat top for a linear transformer driver (LTD) cavity containing 3rd and 5th harmonic bricks [A. A. Kim et al., in Proc. IEEE Pulsed Power and Plasma Science PPPS2013 (San Francisco, California, USA, 2013), pp. 1354–1356.] and for 30 cavity voltage adder. Our goal was to define the necessary component value precision in order to obtain a voltage output flat top with no more than ±0.5% amplitude variation.

Factors affecting the output pulse flatness of the linear transformer driver cavity systems with 5th harmonics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Alexeenko, V. M.; Mazarakis, M. G.; Kim, A. A.

Here, we describe the study we have undertaken to evaluate the effect of component tolerances in obtaining a voltage output flat top for a linear transformer driver (LTD) cavity containing 3rd and 5th harmonic bricks [A. A. Kim et al., in Proc. IEEE Pulsed Power and Plasma Science PPPS2013 (San Francisco, California, USA, 2013), pp. 1354–1356.] and for 30 cavity voltage adder. Our goal was to define the necessary component value precision in order to obtain a voltage output flat top with no more than ±0.5% amplitude variation.

A Hybrid Circuit for Spoof Surface Plasmons and Spatial Waveguide Modes to Reach Controllable Band-Pass Filters

PubMed Central

Zhang, Qian; Zhang, Hao Chi; Wu, Han; Cui, Tie Jun

2015-01-01

We propose a hybrid circuit for spoof surface plasmon polaritons (SPPs) and spatial waveguide modes to develop new microwave devices. The hybrid circuit includes a spoof SPP waveguide made of two anti-symmetric corrugated metallic strips and a traditional substrate integrated waveguide (SIW). From dispersion relations, we show that the electromagnetic waves only can propagate through the hybrid circuit when the operating frequency is less than the cut-off frequency of the SPP waveguide and greater than the cut-off frequency of SIW, generating efficient band-pass filters. We demonstrate that the pass band is controllable in a large range by designing the geometrical parameters of SPP waveguide and SIW. Full-wave simulations are provided to show the large adjustability of filters, including ultra wideband and narrowband filters. We fabricate a sample of the new hybrid device in the microwave frequencies, and measurement results have excellent agreements to numerical simulations, demonstrating excellent filtering characteristics such as low loss, high efficiency, and good square ratio. The proposed hybrid circuit gives important potential to accelerate the development of plasmonic integrated functional devices and circuits in both microwave and terahertz frequencies. PMID:26552584

Multi-mode ultra-strong coupling (I): spectroscopic experiments using a vacuum-gap transmon circuit architecture

NASA Astrophysics Data System (ADS)

Bosman, Sal J.; Gely, Mario F.; Singh, Vibhor; Bruno, Alessandro; Bothner, Daniel; Steele, Gary A.

In circuit QED, multi-mode extensions of the quantum Rabi model suffer from divergence problems. Here, we spectroscopically study multi-mode ultra-strong coupling using a transmon circuit architecture, which provides no clear guidelines on how many modes play a role in the dynamics of the system. As our transmon qubit, we employ a suspended island above the voltage anti-node of a λ / 4 coplanar microwave resonator, thereby realising a circuit where 88% of the qubit capacitance is formed by a vacuum-gap capacitor with the center conductor of the resonator. We measure vacuum Rabi splitting over multiple modes up to 2 GHz, reaching coupling ratios of g / ω = 0 . 18 , well within the ultra-strong coupling regime. We observe a qubit-mediated mode coupling, measurable up to the fifth mode at 38 GHz. Using a novel analytical quantum circuit model of this architecture, which includes all modes without introducing divergencies, we are able to fit the full spectrum and extract a vacuum fluctuations induced Bloch-Siegert shift of up to 62 MHz. This circuit architecture expands the versatility of the transmon technology platform and opens many possibilities in multi-mode physics in the ultra-strong coupling regime.

A Hybrid Circuit for Spoof Surface Plasmons and Spatial Waveguide Modes to Reach Controllable Band-Pass Filters.

PubMed

Zhang, Qian; Zhang, Hao Chi; Wu, Han; Cui, Tie Jun

2015-11-10

We propose a hybrid circuit for spoof surface plasmon polaritons (SPPs) and spatial waveguide modes to develop new microwave devices. The hybrid circuit includes a spoof SPP waveguide made of two anti-symmetric corrugated metallic strips and a traditional substrate integrated waveguide (SIW). From dispersion relations, we show that the electromagnetic waves only can propagate through the hybrid circuit when the operating frequency is less than the cut-off frequency of the SPP waveguide and greater than the cut-off frequency of SIW, generating efficient band-pass filters. We demonstrate that the pass band is controllable in a large range by designing the geometrical parameters of SPP waveguide and SIW. Full-wave simulations are provided to show the large adjustability of filters, including ultra wideband and narrowband filters. We fabricate a sample of the new hybrid device in the microwave frequencies, and measurement results have excellent agreements to numerical simulations, demonstrating excellent filtering characteristics such as low loss, high efficiency, and good square ratio. The proposed hybrid circuit gives important potential to accelerate the development of plasmonic integrated functional devices and circuits in both microwave and terahertz frequencies.

Artifact Noise Removal Techniques on Seismocardiogram Using Two Tri-Axial Accelerometers

PubMed Central

Luu, Loc; Dinh, Anh

2018-01-01

The aim of this study is on the investigation of motion noise removal techniques using two-accelerometer sensor system and various placements of the sensors on gentle movement and walking of the patients. A Wi-Fi based data acquisition system and a framework on Matlab are developed to collect and process data while the subjects are in motion. The tests include eight volunteers who have no record of heart disease. The walking and running data on the subjects are analyzed to find the minimal-noise bandwidth of the SCG signal. This bandwidth is used to design filters in the motion noise removal techniques and peak signal detection. There are two main techniques of combining signals from the two sensors to mitigate the motion artifact: analog processing and digital processing. The analog processing comprises analog circuits performing adding or subtracting functions and bandpass filter to remove artifact noises before entering the data acquisition system. The digital processing processes all the data using combinations of total acceleration and z-axis only acceleration. The two techniques are tested on three placements of accelerometer sensors including horizontal, vertical, and diagonal on gentle motion and walking. In general, the total acceleration and z-axis acceleration are the best techniques to deal with gentle motion on all sensor placements which improve average systolic signal-noise-ratio (SNR) around 2 times and average diastolic SNR around 3 times comparing to traditional methods using only one accelerometer. With walking motion, ADDER and z-axis acceleration are the best techniques on all placements of the sensors on the body which enhance about 7 times of average systolic SNR and about 11 times of average diastolic SNR comparing to only one accelerometer method. Among the sensor placements, the performance of horizontal placement of the sensors is outstanding comparing with other positions on all motions. PMID:29614821

MULTIPLE INPUT BINARY ADDER EMPLOYING MAGNETIC DRUM DIGITAL COMPUTING APPARATUS

DOEpatents

Cooke-Yarborough, E.H.

1960-12-01

A digital computing apparatus is described for adding a plurality of multi-digit binary numbers. The apparatus comprises a rotating magnetic drum, a recording head, first and second reading heads disposed adjacent to the first and second recording tracks, and a series of timing signals recorded on the first track. A series of N groups of digit-representing signals is delivered to the recording head at time intervals corresponding to the timing signals, each group consisting of digits of the same significance in the numbers, and the signal series is recorded on the second track of the drum in synchronism with the timing signals on the first track. The multistage registers are stepped cyclically through all positions, and each of the multistage registers is coupled to the control lead of a separate gate circuit to open the corresponding gate at only one selected position in each cycle. One of the gates has its input coupled to the bistable element to receive the sum digit, and the output lead of this gate is coupled to the recording device. The inputs of the other gates receive the digits to be added from the second reading head, and the outputs of these gates are coupled to the adding register. A phase-setting pulse source is connected to each of the multistage registers individually to step the multistage registers to different initial positions in the cycle, and the phase-setting pulse source is actuated each N time interval to shift a sum digit to the bistable element, where the multistage register coupled to bistable element is operated by the phase- setting pulse source to that position in its cycle N steps before opening the first gate, so that this gate opens in synchronism with each of the shifts to pass the sum digits to the recording head.

3-D printed 2.4 GHz rectifying antenna for wireless power transfer applications

NASA Astrophysics Data System (ADS)

Skinner, Matthew

In this work, a 3D printed rectifying antenna that operates at the 2.4GHz WiFi band was designed and manufactured. The printed material did not have the same properties of bulk material, so the printed materials needed to be characterized. The antenna and rectifying circuit was printed out of Acrylonitrile Butadiene Styrene (ABS) filament and a conductive silver paste, with electrical components integrated into the circuit. Before printing the full rectifying antenna, each component was printed and evaluated. The printed antenna operated at the desired frequency with a return loss of -16 dBm with a bandwidth of 70MHz. The radiation pattern was measured in an anechoic chamber with good matching to the model. The rectifying circuit was designed in Ansys Circuit Simulation using Schottky diodes to enable the circuit to operate at lower input power levels. Two rectifying circuits were manufactured, one by printing the conductive traces with silver ink, and one with traces made from copper. The printed silver ink is less conductive than the bulk copper and therefore the output voltage of the printed rectifier was lower than the copper circuit. The copper circuit had an efficiency of 60% at 0dBm and the printed silver circuit had an efficiency of 28.6% at 0dBm. The antenna and rectifying circuits were then connected to each other and the performance was compared to a fully printed integrated rectifying antenna. The rectifying antennas were placed in front of a horn antenna while changing the power levels at the antenna. The efficiency of the whole system was lower than the individual components but an efficiency of 11% at 10dBm was measured.

SEMICONDUCTOR INTEGRATED CIRCUITS: A quasi-3-dimensional simulation method for a high-voltage level-shifting circuit structure

NASA Astrophysics Data System (ADS)

Jizhi, Liu; Xingbi, Chen

2009-12-01

A new quasi-three-dimensional (quasi-3D) numeric simulation method for a high-voltage level-shifting circuit structure is proposed. The performances of the 3D structure are analyzed by combining some 2D device structures; the 2D devices are in two planes perpendicular to each other and to the surface of the semiconductor. In comparison with Davinci, the full 3D device simulation tool, the quasi-3D simulation method can give results for the potential and current distribution of the 3D high-voltage level-shifting circuit structure with appropriate accuracy and the total CPU time for simulation is significantly reduced. The quasi-3D simulation technique can be used in many cases with advantages such as saving computing time, making no demands on the high-end computer terminals, and being easy to operate.

Phase-synchroniser based on gm-C all-pass filter chain with sliding mode control

NASA Astrophysics Data System (ADS)

Mitić, Darko B.; Jovanović, Goran S.; Stojčev, Mile K.; Antić, Dragan S.

2015-03-01

Phase-synchronisers have many applications in VLSI circuit designs. They are used in CMOS RF circuits including phase (de)modulators, phase recovery circuits, multiphase synthesis, etc. In this article, a phase-synchroniser based on gm-C all-pass filter chain with sliding mode control is presented. The filter chain provides good controllable delay characteristics over the full range of phase and frequency regulation, without deterioration of input signal amplitude and waveform, while the sliding mode control enables us to achieve fast and predetermined finite locking time. IHP 0.25 µm SiGe BiCMOS technology has been used in design and verification processes. The circuit operates in the frequency range from 33 MHz up to 150 MHz. Simulation results indicate that it is possible to achieve very fast synchronisation time period, which is approximately four time intervals of the input signal during normal operation, and 20 time intervals during power-on.

Measuring Accurately Single-Phase Sinusoidal and Non-Sinusoidal Power.

DTIC Science & Technology

1983-01-01

current component. Since the induction watthour meter is designed for measuring ac variations only, the creation of a dc component in an ac circuit due...available and the basic principle of measurement used in each. 3.1 Power Measuring Meters Instruments designed to measure the amount of average power...1.0 percent of full scale and + 0.5% of reading. 3.2 Encrgy Measuring Meters Instruments designed to measure the amount of power consumed in a circuit

Gallium arsenide pilot line for high performance components

NASA Astrophysics Data System (ADS)

1990-01-01

The Gallium Arsenide Pilot Line for High Performance Components (Pilot Line III) is to develop a facility for the fabrication of GaAs logic and memory chips. The first thirty months of this contract are now complete, and this report covers the period from March 27 through September 24, 1989. Similar to the PT-2M SRAM function for memories, the six logic circuits of PT-2L and PT-2M have served their functions as stepping stones toward the custom, standard cell, and cell array logic circuits. All but one of these circuits was right first time; the remaining circuit had a layout error due to a bug in the design rule checker that has since been fixed. The working devices all function over the full temperature range from -55 to 125 C. They all comfortably meet the 200 MHz requirement. They do not solidly conform to the required input and output voltage levels, particularly Vih. It is known that these circuits were designed with the older design models and that they came from an era where the DFET thresholds were often not on target.

Soft switching resonant converter with duty-cycle control in DC micro-grid system

NASA Astrophysics Data System (ADS)

Lin, Bor-Ren

2018-01-01

Resonant converter has been widely used for the benefits of low switching losses and high circuit efficiency. However, the wide frequency variation is the main drawback of resonant converter. This paper studies a new modular resonant converter with duty-cycle control to overcome this problem and realise the advantages of low switching losses, no reverse recovery current loss, balance input split voltages and constant frequency operation for medium voltage direct currentgrid or system network. Series full-bridge (FB) converters are used in the studied circuit in order to reduce the voltage stresses and power rating on power semiconductors. Flying capacitor is used between two FB converters to balance input split voltages. Two circuit modules are paralleled on the secondary side to lessen the current rating of rectifier diodes and the size of magnetic components. The resonant tank is operated at inductive load circuit to help power switches to be turned on at zero voltage with wide load range. The pulse-width modulation scheme is used to regulate output voltage. Experimental verifications are provided to show the performance of the proposed circuit.

Apollo 13 Mission: Cryogenic Oxygen Tank 2 Anomaly Report

NASA Technical Reports Server (NTRS)

1970-01-01

There were two investigative aspects associated with the loss of the cryogenic oxygen tank pressure during the Apollo 13 flight. First, what was the cause of the flight failure of cryogenic oxygen tank 2. Second, what possible contributing factors during the ground history of the tank could have led to the ultimate failure in flight. The first flight indication of a problem occurred when the quantity measurement in the tank went full scale about 9 hours before the incident. This condition in itself could not have contributed to ignition in the tank, since the energy in the circuit is restricted to about 7 milli-joules. Data from the electrical system provided the second indication of a problem when the fans in tank 2 were activated to reduce any stratification which might have been present in the supercritical oxygen in the tank. Several short-circuits were detected and have been isolated to the fan circuits of tank 2. The first short-circuit could have contained as much as 160 joules of energy, which is within the current-protection level of the fan circuits. Tests have shown that two orders of magnitude less energy than this is sufficient to ignite the polytetrafluoroethylene insulation on the fan circuits in the tank. Consequently, the evidence indicates that the insulation on the fan wiring was ignited by the energy in the short-circuit.

Biocompatible circuit-breaker chip for thermal management of biomedical microsystems

NASA Astrophysics Data System (ADS)

Luo, Yi; Dahmardeh, Masoud; Takahata, Kenichi

2015-05-01

This paper presents a thermoresponsive micro circuit breaker for biomedical applications specifically targeted at electronic intelligent implants. The circuit breaker is micromachined to have a shape-memory-alloy cantilever actuator as a normally closed temperature-sensitive switch to protect the device of interest from overheating, a critical safety feature for smart implants including those that are electrothermally driven with wireless micro heaters. The device is fabricated in a size of 1.5  ×  2.0  ×  0.46 mm3 using biocompatible materials and a chip-based titanium package, exhibiting a nominal cold-state resistance of 14 Ω. The breaker rapidly enters the full open condition when the chip temperature exceeds 63 °C, temporarily breaking the circuit of interest to lower its temperature until chip temperature drops to 51 °C, at which the breaker closes the circuit to allow current to flow through it again, physically limiting the maximum temperature of the circuit. This functionality is tested in combination with a wireless resonant heater powered by radio-frequency electromagnetic radiation, demonstrating self-regulation of heater temperature. The developed circuit-breaker chip operates in a fully passive manner that removes the need for active sensor and circuitry to achieve temperature regulation in a target device, contributing to the miniaturization of biomedical microsystems including electronic smart implants where thermal management is essential.

Monolithic optical integrated control circuitry for GaAs MMIC-based phased arrays

NASA Technical Reports Server (NTRS)

Bhasin, K. B.; Ponchak, G. E.; Kascak, T. J.

1985-01-01

Gallium arsenide (GaAs) monolithic microwave integrated circuits (MMIC's) show promise in phased-array antenna applications for future space communications systems. Their efficient usage will depend on the control of amplitude and phase signals for each MMIC element in the phased array and in the low-loss radiofrequency feed. For a phased array contining several MMIC elements a complex system is required to control and feed each element. The characteristics of GaAs MMIC's for 20/30-GHz phased-array systems are discussed. The optical/MMIC interface and the desired characteristics of optical integrated circuits (OIC's) for such an interface are described. Anticipated fabrication considerations for eventual full monolithic integration of optical integrated circuits with MMIC's on a GaAs substrate are presented.

Full analogue electronic realisation of the Hodgkin-Huxley neuronal dynamics in weak-inversion CMOS.

PubMed

Lazaridis, E; Drakakis, E M; Barahona, M

2007-01-01

This paper presents a non-linear analog synthesis path towards the modeling and full implementation of the Hodgkin-Huxley neuronal dynamics in silicon. The proposed circuits have been realized in weak-inversion CMOS technology and take advantage of both log-domain and translinear transistor-level techniques.

Note: Fully integrated active quenching circuit achieving 100 MHz count rate with custom technology single photon avalanche diodes.

PubMed

Acconcia, G; Labanca, I; Rech, I; Gulinatti, A; Ghioni, M

2017-02-01

The minimization of Single Photon Avalanche Diodes (SPADs) dead time is a key factor to speed up photon counting and timing measurements. We present a fully integrated Active Quenching Circuit (AQC) able to provide a count rate as high as 100 MHz with custom technology SPAD detectors. The AQC can also operate the new red enhanced SPAD and provide the timing information with a timing jitter Full Width at Half Maximum (FWHM) as low as 160 ps.

1982 International Symposium on Fault-Tolerant Computing (FTCS-12) Preprints.

DTIC Science & Technology

1982-04-01

fixed figure. This is a big refered to as full weight generators. Circuit NM2 advantage for those applications where the circuits in Fig.2 is a two...codes _ 20__A_ very attractive for practical applications . -- : 12 S1 I--- SACKNOWLEDGMENTS --(2 This work Was supported in part by a research S261-1...Grant --I MCS-790864. The author wishes to thank Professor -: E. J. McCluskey and Professor J. F. Wakerly for their valuable comments. REFERENCES i

Study of Piezoelectric Vibration Energy Harvester with non-linear conditioning circuit using an integrated model

NASA Astrophysics Data System (ADS)

Manzoor, Ali; Rafique, Sajid; Usman Iftikhar, Muhammad; Mahmood Ul Hassan, Khalid; Nasir, Ali

2017-08-01

Piezoelectric vibration energy harvester (PVEH) consists of a cantilever bimorph with piezoelectric layers pasted on its top and bottom, which can harvest power from vibrations and feed to low power wireless sensor nodes through some power conditioning circuit. In this paper, a non-linear conditioning circuit, consisting of a full-bridge rectifier followed by a buck-boost converter, is employed to investigate the issues of electrical side of the energy harvesting system. An integrated mathematical model of complete electromechanical system has been developed. Previously, researchers have studied PVEH with sophisticated piezo-beam models but employed simplistic linear circuits, such as resistor, as electrical load. In contrast, other researchers have worked on more complex non-linear circuits but with over-simplified piezo-beam models. Such models neglect different aspects of the system which result from complex interactions of its electrical and mechanical subsystems. In this work, authors have integrated the distributed parameter-based model of piezo-beam presented in literature with a real world non-linear electrical load. Then, the developed integrated model is employed to analyse the stability of complete energy harvesting system. This work provides a more realistic and useful electromechanical model having realistic non-linear electrical load unlike the simplistic linear circuit elements employed by many researchers.

Optical information-processing systems and architectures II; Proceedings of the Meeting, San Diego, CA, July 9-13, 1990

NASA Astrophysics Data System (ADS)

Javidi, Bahram

The present conference discusses topics in the fields of neural networks, acoustooptic signal processing, pattern recognition, phase-only processing, nonlinear signal processing, image processing, optical computing, and optical information processing. Attention is given to the optical implementation of an inner-product neural associative memory, optoelectronic associative recall via motionless-head/parallel-readout optical disk, a compact real-time acoustooptic image correlator, a multidimensional synthetic estimation filter, and a light-efficient joint transform optical correlator. Also discussed are a high-resolution spatial light modulator, compact real-time interferometric Fourier-transform processors, a fast decorrelation algorithm for permutation arrays, the optical interconnection of optical modules, and carry-free optical binary adders.

Learning to segment mouse embryo cells

NASA Astrophysics Data System (ADS)

León, Juan; Pardo, Alejandro; Arbeláez, Pablo

2017-11-01

Recent advances in microscopy enable the capture of temporal sequences during cell development stages. However, the study of such sequences is a complex task and time consuming task. In this paper we propose an automatic strategy to adders the problem of semantic and instance segmentation of mouse embryos using NYU's Mouse Embryo Tracking Database. We obtain our instance proposals as refined predictions from the generalized hough transform, using prior knowledge of the embryo's locations and their current cell stage. We use two main approaches to learn the priors: Hand crafted features and automatic learned features. Our strategy increases the baseline jaccard index from 0.12 up to 0.24 using hand crafted features and 0.28 by using automatic learned ones.

Multi-input and binary reproducible, high bandwidth floating point adder in a collective network

DOEpatents

Chen, Dong; Eisley, Noel A.; Heidelberger, Philip; Steinmacher-Burow, Burkhard

2016-11-15

To add floating point numbers in a parallel computing system, a collective logic device receives the floating point numbers from computing nodes. The collective logic devices converts the floating point numbers to integer numbers. The collective logic device adds the integer numbers and generating a summation of the integer numbers. The collective logic device converts the summation to a floating point number. The collective logic device performs the receiving, the converting the floating point numbers, the adding, the generating and the converting the summation in one pass. One pass indicates that the computing nodes send inputs only once to the collective logic device and receive outputs only once from the collective logic device.

[Bites of venomous snakes in Switzerland].

PubMed

Plate, Andreas; Kupferschmidt, Hugo; Schneemann, Markus

2016-06-08

Although snake bites are rare in Europe, there are a constant number of snake bites in Switzerland. There are two domestic venomous snakes in Switzerland: the aspic viper (Vipera aspis) and the common European adder (Vipera berus). Bites from venomous snakes are caused either by one of the two domestic venomous snakes or by an exotic venomous snake kept in a terrarium. Snake- bites can cause both a local and/or a systemic envenoming. Potentially fatal systemic complications are related to disturbances of the hemostatic- and cardiovascular system as well as the central or peripheral nervous system. Beside a symptomatic therapy the administration of antivenom is the only causal therapy to neutralize the venomous toxins.

Note: A pulsed laser ion source for linear induction accelerators

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, H., E-mail: bamboobbu@hotmail.com; School of Physics, Peking University, Beijing 100871; Zhang, K.

2015-01-15

We have developed a high-current laser ion source for induction accelerators. A copper target was irradiated by a frequency-quadrupled Nd:YAG laser (266 nm) with relatively low intensities of 10{sup 8} W/cm{sup 2}. The laser-produced plasma supplied a large number of Cu{sup +} ions (∼10{sup 12} ions/pulse) during several microseconds. Emission spectra of the plasma were observed and the calculated electron temperature was about 1 eV. An induction voltage adder extracted high-current ion beams over 0.5 A/cm{sup 2} from a plasma-prefilled gap. The normalized beam emittance measured by a pepper-pot method was smaller than 1 π mm mrad.

Quantum cellular automata

NASA Astrophysics Data System (ADS)

Porod, Wolfgang; Lent, Craig S.; Bernstein, Gary H.

1994-06-01

The Notre Dame group has developed a new paradigm for ultra-dense and ultra-fast information processing in nanoelectronic systems. These Quantum Cellular Automata (QCA's) are the first concrete proposal for a technology based on arrays of coupled quantum dots. The basic building block of these cellular arrays is the Notre Dame Logic Cell, as it has been called in the literature. The phenomenon of Coulomb exclusion, which is a synergistic interplay of quantum confinement and Coulomb interaction, leads to a bistable behavior of each cell which makes possible their use in large-scale cellular arrays. The physical interaction between neighboring cells has been exploited to implement logic functions. New functionality may be achieved in this fashion, and the Notre Dame group invented a versatile majority logic gate. In a series of papers, the feasibility of QCA wires, wire crossing, inverters, and Boolean logic gates was demonstrated. A major finding is that all logic functions may be integrated in a hierarchial fashion which allows the design of complicated QCA structures. The most complicated system which was simulated to date is a one-bit full adder consisting of some 200 cells. In addition to exploring these new concepts, efforts are under way to physically realize such structures both in semiconductor and metal systems. Extensive modeling work of semiconductor quantum dot structures has helped identify optimum design parameters for QCA experimental implementations.

Stainless Steel NaK Circuit Integration and Fill Submission

NASA Technical Reports Server (NTRS)

Garber, Anne E.

2006-01-01

The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed to hold a eutectic mixture of sodium potassium (NaK), was redesigned to hold lithium; but due to a shift in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature loop include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This document summarizes the integration and fill of the pumped liquid metal NaK flow circuit.

Performance of an SOI Boot-Strapped Full-Bridge MOSFET Driver, Type CHT-FBDR, under Extreme Temperatures

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad

2009-01-01

Electronic systems designed for use in deep space and planetary exploration missions are expected to encounter extreme temperatures and wide thermal swings. Silicon-based devices are limited in their wide-temperature capability and usually require extra measures, such as cooling or heating mechanisms, to provide adequate ambient temperature for proper operation. Silicon-On-Insulator (SOI) technology, on the other hand, lately has been gaining wide spread use in applications where high temperatures are encountered. Due to their inherent design, SOI-based integrated circuit chips are able to operate at temperatures higher than those of the silicon devices by virtue of reducing leakage currents, eliminating parasitic junctions, and limiting internal heating. In addition, SOI devices provide faster switching, consume less power, and offer improved radiation-tolerance. Very little data, however, exist on the performance of such devices and circuits under cryogenic temperatures. In this work, the performance of an SOI bootstrapped, full-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Study of mathematical modeling of communication systems transponders and receivers

NASA Technical Reports Server (NTRS)

Walsh, J. R.

1972-01-01

The modeling of communication receivers is described at both the circuit detail level and at the block level. The largest effort was devoted to developing new models at the block modeling level. The available effort did not permit full development of all of the block modeling concepts envisioned, but idealized blocks were developed for signal sources, a variety of filters, limiters, amplifiers, mixers, and demodulators. These blocks were organized into an operational computer simulation of communications receiver circuits identified as the frequency and time circuit analysis technique (FATCAT). The simulation operates in both the time and frequency domains, and permits output plots or listings of either frequency spectra or time waveforms from any model block. Transfer between domains is handled with a fast Fourier transform algorithm.

A 5GHz Band Low Noise and Wide Tuning Range Si-CMOS VCO with a Novel Varactors Pair Circuit

NASA Astrophysics Data System (ADS)

Ta, Tuan Thanh; Kameda, Suguru; Takagi, Tadashi; Tsubouchi, Kazuo

In this paper, a fully integrated 5GHz voltage controlled oscillator (VCO) is presented. The VCO is designed with 0.18µm silicon complementary metal oxide semiconductor (Si-CMOS) process. To achieve low phase noise, a novel varactors pair circuit is proposed to cancel effects of capacitance fluctuation that makes harmonic currents which increase phase noise of VCO. The VCO with the proposed varactor circuit has tuning range from 5.1GHz to 6.1GHz (relative value of 17.9%) and phase noise of lower than -110.8dBc/Hz at 1MHz offset over the full tuning range. Figure-of-merit-with-tuning-range (FOMT) of the proposed VCO is -182dBc/Hz.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zaupa, M., E-mail: matteo.zaupa@igi.cnr.it; Consorzio RFX, Corso Stati Uniti 4, Padova 35127; Sartori, E.

Megavolt ITER Injector Concept Advancement is the full scale prototype of the heating and current drive neutral beam injectors for ITER, to be built at Consorzio RFX (Padova). The engineering design of its components is challenging: the total heat loads they will be subjected to (expected between 2 and 19 MW), the high heat fluxes (up to 20 MW/m{sup 2}), and the beam pulse duration up to 1 h, set demanding requirements for reliable active cooling circuits. In support of the design, the thermo-hydraulic behavior of each cooling circuit under steady state condition has been investigated by using one-dimensional models.more » The final results, obtained considering a number of optimizations for the cooling circuits, show that all the requirements in terms of flow rate, temperature, and pressure drop are properly fulfilled.« less

Equivalent circuit modeling of a piezo-patch energy harvester on a thin plate with AC-DC conversion

NASA Astrophysics Data System (ADS)

Bayik, B.; Aghakhani, A.; Basdogan, I.; Erturk, A.

2016-05-01

As an alternative to beam-like structures, piezoelectric patch-based energy harvesters attached to thin plates can be readily integrated to plate-like structures in automotive, marine, and aerospace applications, in order to directly exploit structural vibration modes of the host system without mass loading and volumetric occupancy of cantilever attachments. In this paper, a multi-mode equivalent circuit model of a piezo-patch energy harvester integrated to a thin plate is developed and coupled with a standard AC-DC conversion circuit. Equivalent circuit parameters are obtained in two different ways: (1) from the modal analysis solution of a distributed-parameter analytical model and (2) from the finite-element numerical model of the harvester by accounting for two-way coupling. After the analytical modeling effort, multi-mode equivalent circuit representation of the harvester is obtained via electronic circuit simulation software SPICE. Using the SPICE software, electromechanical response of the piezoelectric energy harvester connected to linear and nonlinear circuit elements are computed. Simulation results are validated for the standard AC-AC and AC-DC configurations. For the AC input-AC output problem, voltage frequency response functions are calculated for various resistive loads, and they show excellent agreement with modal analysis-based analytical closed-form solution and with the finite-element model. For the standard ideal AC input-DC output case, a full-wave rectifier and a smoothing capacitor are added to the harvester circuit for conversion of the AC voltage to a stable DC voltage, which is also validated against an existing solution by treating the single-mode plate dynamics as a single-degree-of-freedom system.

Short-circuit current and ionic fluxes in the isolated colonic mucosa of Bufo arenarum.

PubMed

Lew, V L

1970-03-01

1. The unidirectional fluxes of (22)Na, (36)Cl and [(14)C]bicarbonate ions were measured in paired portions of the isolated and short-circuited colonic mucosa of Bufo arenarum, separated from its muscular layer. Pharmacological effects as well as effects of changes in the composition of the nutrient solutions on the electrical parameters of membrane activity (potential difference, short-circuit current and total membrane resistance) are described.2. The net fluxes of both Cl and bicarbonate ions were not significantly different from zero in the absence of electrochemical gradients across the membrane.3. The net Na flux from mucosa to serosa represented a variable proportion of the short-circuit current ranging from 62 to 100%.4. The proportion of membranes with high discrepancies between net Na flux and short-circuit current decreased with the duration of captivity of the toads.5. When Na was entirely replaced by choline in the mucosal bathing solution, the short-circuit current dropped by a variable amount within the range of 64 to 98% of its control values in different membranes. This effect was completely reversible. Similar changes in the serosal solution had no effect.6. The short-circuit current and potential difference were very sensitive to the serosal concentration of bicarbonate ions. In different membranes, 60-100% of the short-circuit current was reversibly abolished by bathing the serosal surface with a bicarbonate-free solution. The mucosal bicarbonate level had no effect on either the potential difference or the short-circuit current. 5 mM bicarbonate in the serosal solution restored at least 50% of the short-circuit control value and full recovery was attained by concentrations near 30 mM bicarbonate.7. Anoxia brought the potential difference and short-circuit current reversibly down to zero in about 50 min.8. Ouabain reduced the short-circuit current up to 80% in about 40 min when present in the serosal solution at a concentration of 10(-4)M. At this or lower concentrations the ouabain effect was reversible. Above this level ouabain produced 100% inhibition in 3-4 hr, but this was no longer reversible. Ouabain had no effect on the short-circuit current either when applied to the mucosal surface or in the absence of Na from the mucosal solution.9. Diamox produced a variable inhibition of the short-circuit current of up to 30% only at concentrations above 10 mM.10. Possible mechanisms are discussed for the appearance of the non-Na component of the short-circuit current. A theory concerning its nature is proposed.

Commercial absorption chiller models for evaluation of control strategies

DOE Office of Scientific and Technical Information (OSTI.GOV)

Koeppel, E.A.; Klein, S.A.; Mitchell, J.W.

1995-08-01

A steady-state computer simulation model of a direct fired double-effect water-lithium bromide absorption chiller in the parallel-flow configuration was developed from first principles. Unknown model parameters such as heat transfer coefficients were determined by matching the model`s calculated state points and coefficient of performance (COP) against nominal full-load operating data and COPs obtained from a manufacturer`s catalog. The model compares favorably with the manufacturer`s performance ratings for varying water circuit (chilled and cooling) temperatures at full load conditions and for chiller part-load performance. The model was used (1) to investigate the effect of varying the water circuit flow rates withmore » the chiller load and (2) to optimize chiller part-load performance with respect to the distribution and flow of the weak solution.« less

42 CFR 84.93 - Gas flow test; open-circuit apparatus.

Code of Federal Regulations, 2014 CFR

2014-10-01

...) water-column height when full container pressure is applied. (c) Where pressure demand apparatus are tested, the flow will be measured at zero gage pressure in the facepiece. (d) Where apparatus with...

42 CFR 84.93 - Gas flow test; open-circuit apparatus.

Code of Federal Regulations, 2013 CFR

2013-10-01

...) water-column height when full container pressure is applied. (c) Where pressure demand apparatus are tested, the flow will be measured at zero gage pressure in the facepiece. (d) Where apparatus with...

42 CFR 84.93 - Gas flow test; open-circuit apparatus.

Code of Federal Regulations, 2012 CFR

2012-10-01

...) water-column height when full container pressure is applied. (c) Where pressure demand apparatus are tested, the flow will be measured at zero gage pressure in the facepiece. (d) Where apparatus with...

The 30/20 GHz mixed user architecture development study: Executive summary

NASA Technical Reports Server (NTRS)

1979-01-01

The baseline 30/30 GHz satellite communication system, designed for cost-effective communications in the years 1990 to 2000, incorporates on-board satellite demodulation and routing of individual 64 kbps digital voice-grade circuits. This level of routing flexibility is necessary to provide efficient communications to the large number of direct-to-user terminals (DTU) projected. The circuit interfacing hardware is distributed among all the DTU and master control stations. The switching circuitry which provides full interconnectivity between 30 to 45 thousand circuits is in the satellite. The DTU terminal cost, perhaps the largest element in the system cost, represents the largest economic value element of the system because it avoids using terrestrial signal distribution and routing and the charges associated with these functions. Satellite baseline design and power requirements for the system are examined.

Stability analysis of an autocatalytic protein model

NASA Astrophysics Data System (ADS)

Lee, Julian

2016-05-01

A self-regulatory genetic circuit, where a protein acts as a positive regulator of its own production, is known to be the simplest biological network with a positive feedback loop. Although at least three components—DNA, RNA, and the protein—are required to form such a circuit, stability analysis of the fixed points of this self-regulatory circuit has been performed only after reducing the system to a two-component system, either by assuming a fast equilibration of the DNA component or by removing the RNA component. Here, stability of the fixed points of the three-component positive feedback loop is analyzed by obtaining eigenvalues of the full three-dimensional Hessian matrix. In addition to rigorously identifying the stable fixed points and saddle points, detailed information about the system can be obtained, such as the existence of complex eigenvalues near a fixed point.

Solid State Technology Branch of NASA Lewis Research Center Second Annual Digest, June 1989 - June 1990

NASA Technical Reports Server (NTRS)

1990-01-01

A collection of papers and presentations authored by the branch between June 1989 and June 1990 is presented. The papers are organized into four sections. Section 1 deals with research in microwave circuits and includes full integrated circuits, the demonstration of optical/RF interfaces, and the evaluation of some hybrid circuitry. Section 2 indicates developments in coplanar waveguides and their use in breadboard circuits. Section 3 addresses high temperature superconductivity and includes: thin film deposition, transport measurement of film characteristics, RF surface resistant measurements, substrate permittivity measurements, measurements of microstrip line characteristics at cryogenic temperatures, patterning of superconducting films, and evaluation of simple passive microstrip circuitry based on YBaCuO films. Section 4 deals with carbon films, silicon carbide, GaAs/AlGaAs, HgCdTe, and other materials.

Implementation of a pulse coupled neural network in FPGA.

PubMed

Waldemark, J; Millberg, M; Lindblad, T; Waldemark, K; Becanovic, V

2000-06-01

The Pulse Coupled neural network, PCNN, is a biologically inspired neural net and it can be used in various image analysis applications, e.g. time-critical applications in the field of image pre-processing like segmentation, filtering, etc. a VHDL implementation of the PCNN targeting FPGA was undertaken and the results presented here. The implementation contains many interesting features. By pipelining the PCNN structure a very high throughput of 55 million neuron iterations per second could be achieved. By making the coefficients re-configurable during operation, a complete recognition system could be implemented on one, or maybe two, chip(s). Reconsidering the ranges and resolutions of the constants may save a lot of hardware, since the higher resolution requires larger multipliers, adders, memories etc.

Virtual gap dielectric wall accelerator

DOEpatents

Caporaso, George James; Chen, Yu-Jiuan; Nelson, Scott; Sullivan, Jim; Hawkins, Steven A

2013-11-05

A virtual, moving accelerating gap is formed along an insulating tube in a dielectric wall accelerator (DWA) by locally controlling the conductivity of the tube. Localized voltage concentration is thus achieved by sequential activation of a variable resistive tube or stalk down the axis of an inductive voltage adder, producing a "virtual" traveling wave along the tube. The tube conductivity can be controlled at a desired location, which can be moved at a desired rate, by light illumination, or by photoconductive switches, or by other means. As a result, an impressed voltage along the tube appears predominantly over a local region, the virtual gap. By making the length of the tube large in comparison to the virtual gap length, the effective gain of the accelerator can be made very large.

Multi-input and binary reproducible, high bandwidth floating point adder in a collective network

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Dong; Eisley, Noel A; Heidelberger, Philip

To add floating point numbers in a parallel computing system, a collective logic device receives the floating point numbers from computing nodes. The collective logic devices converts the floating point numbers to integer numbers. The collective logic device adds the integer numbers and generating a summation of the integer numbers. The collective logic device converts the summation to a floating point number. The collective logic device performs the receiving, the converting the floating point numbers, the adding, the generating and the converting the summation in one pass. One pass indicates that the computing nodes send inputs only once to themore » collective logic device and receive outputs only once from the collective logic device.« less

Preliminary results of Linear Induction Accelerator LIA-200

NASA Astrophysics Data System (ADS)

Sharma, Archana; Senthil, K.; Praveen Kumar, D. D.; Mitra, S.; Sharma, V.; Patel, A.; Sharma, D. K.; Rehim, R.; Kolge, T. S.; Saroj, P. C.; Acharya, S.; Amitava, Roy; Rakhee, M.; Nagesh, K. V.; Chakravarthy, D. P.

2010-05-01

Repetitive Pulsed Power Technology is being developed keeping in mind the potential applications of this technology in material modifications, disinfections of water, timber, and food pasteurization etc. BARC has indigenously developed a Linear Induction Accelerator (LIA-200) rated for 200 kV, 4 kA, 100 ns, 10 Hz. The satisfactory performance of all the sub-systems including solid state power modulator, amorphous core based pulsed transformers, magnetic switches, water capacitors, water pulse- forming line, induction adder and field-emission diode have been demonstrated. This paper presents some design details and operational results of this pulsed power system. It also highlights the need for further research and development to build reliable and economic high-average power systems for industrial applications.

Pneumatic oscillator circuits for timing and control of integrated microfluidics.

PubMed

Duncan, Philip N; Nguyen, Transon V; Hui, Elliot E

2013-11-05

Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices.

Integrated Cryogenic Electronics Testbed (ICE-T) for Evaluation of Superconductor and Cryo-Semiconductor Integrated Circuits

NASA Astrophysics Data System (ADS)

Dotsenko, V. V.; Sahu, A.; Chonigman, B.; Tang, J.; Lehmann, A. E.; Gupta, V.; Talalevskii, A.; Ruotolo, S.; Sarwana, S.; Webber, R. J.; Gupta, D.

2017-02-01

Research and development of cryogenic application-specific integrated circuits (ASICs), such as high-frequency (tens of GHz) semiconductor and superconductor mixed-signal circuits and large-scale (>10,000 Josephson Junctions) superconductor digital circuits, have long been hindered by the absence of specialized cryogenic test apparatus. During their iterative development phase, most ASICs require many additional input-output lines for applying independent bias controls, injecting test signals, and monitoring outputs of different sub-circuits. We are developing a full suite of modular test apparatus based on cryocoolers that do not consume liquid helium, and support extensive electrical interfaces to standard and custom test equipment. Our design separates the cryogenics from electrical connections, allowing even inexperienced users to conduct testing by simply mounting their ASIC on a removable electrical insert. Thermal connections between the cold stages and the inserts are made with robust thermal links. ICE-T accommodates two independent electrical inserts at the same time. We have designed various inserts, such as universal ones with all 40 or 80 coaxial cables and those with customized wiring and temperature-controlled stages. ICE-T features fast thermal cycling for rapid testing, enables detailed testing over long periods (days to months, if necessary), and even supports automated testing of digital ICs with modular additions.

Reversing-counterpulse repetitive-pulse inductive storage circuit

DOEpatents

Honig, Emanuel M.

1987-01-01

A high-power reversing-counterpulse repetitive-pulse inductive storage and transfer circuit includes an opening switch, a main energy storage coil, a counterpulse capacitor and a small inductor. After counterpulsing the opening switch off, the counterpulse capacitor is recharged by the main energy storage coil before the load pulse is initiated. This gives the counterpulse capacitor sufficient energy for the next counterpulse operation, although the polarity of the capacitor's voltage must be reversed before that can occur. By using a current-zero switch as the counterpulse start switch, the capacitor is disconnected from the circuit (with a full charge) when the load pulse is initiated, preventing the capacitor from depleting its energy store by discharging through the load. After the load pulse is terminated by reclosing the main opening switch, the polarity of the counterpulse capacitor voltage is reversed by discharging the capacitor through a small inductor and interrupting the discharge current oscillation at zero current and peak reversed voltage. The circuit enables high-power, high-repetition-rate operation with reusable switches and features total control (pulse-to-pulse) over output pulse initiation, duration, repetition rate, and, to some extent, risetime.

Reversing-counterpulse repetitive-pulse inductive storage circuit

DOEpatents

Honig, E.M.

1984-06-05

A high power reversing-counterpulse repetitive-pulse inductive storage and transfer circuit includes an opening switch, a main energy storage coil, a counterpulse capacitor and a small inductor. After counterpulsing the opening switch off, the counterpulse capacitor is recharged by the main energy storage coil before the load pulse is initiated. This gives the counterpulse capacitor sufficient energy for the next counterpulse operation, although the polarity of the capacitor's voltage must be reversed before that can occur. By using a current-zero switch as the counterpulse start switch, the capacitor is disconnected from the circuit (with a full charge) when the load pulse is initiated, preventing the capacitor from depleting its energy store by discharging through the load. After the load pulse is terminated by reclosing the main opening switch, the polarity of the counterpulse capacitor voltage is reversed by discharging the capacitor through a small inductor and interrupting the discharge current oscillation at zero current and peak reversed voltage. The circuit enables high-power, high-repetition-rate operation with reusable switches and features total control (pulse-to-pulse) over output pulse initiation, duration, repetition rate, and, to some extent, risetime.

Imperceptible and Ultraflexible p-Type Transistors and Macroelectronics Based on Carbon Nanotubes.

PubMed

Cao, Xuan; Cao, Yu; Zhou, Chongwu

2016-01-26

Flexible thin-film transistors based on semiconducting single-wall carbon nanotubes are promising for flexible digital circuits, artificial skins, radio frequency devices, active-matrix-based displays, and sensors due to the outstanding electrical properties and intrinsic mechanical strength of carbon nanotubes. Nevertheless, previous research effort only led to nanotube thin-film transistors with the smallest bending radius down to 1 mm. In this paper, we have realized the full potential of carbon nanotubes by making ultraflexible and imperceptible p-type transistors and circuits with a bending radius down to 40 μm. In addition, the resulted transistors show mobility up to 12.04 cm(2) V(-1) S(-1), high on-off ratio (∼10(6)), ultralight weight (<3 g/m(2)), and good mechanical robustness (accommodating severe crumpling and 67% compressive strain). Furthermore, the nanotube circuits can operate properly with 33% compressive strain. On the basis of the aforementioned features, our ultraflexible p-type nanotube transistors and circuits have great potential to work as indispensable components for ultraflexible complementary electronics.

Full control of far-field radiation via photonic integrated circuits decorated with plasmonic nanoantennas.

PubMed

Sun, Yi-Zhi; Feng, Li-Shuang; Bachelot, Renaud; Blaize, Sylvain; Ding, Wei

2017-07-24

We theoretically develop a hybrid architecture consisting of photonic integrated circuit and plasmonic nanoantennas to fully control optical far-field radiation with unprecedented flexibility. By exploiting asymmetric and lateral excitation from silicon waveguides, single gold nanorod and cascaded nanorod pair can function as component radiation pixels, featured by full 2π phase coverage and nanoscale footprint. These radiation pixels allow us to design scalable on-chip devices in a wavefront engineering fashion. We numerically demonstrate beam collimation with 30° out of the incident plane and nearly diffraction limited divergence angle. We also present high-numerical-aperture (NA) beam focusing with NA ≈0.65 and vector beam generation (the radially-polarized mode) with the mode similarity greater than 44%. This concept and approach constitutes a designable optical platform, which might be a future bridge between integrated photonics and metasurface functionalities.

Solid state pulsed power generator

DOEpatents

Tao, Fengfeng; Saddoughi, Seyed Gholamali; Herbon, John Thomas

2014-02-11

A power generator includes one or more full bridge inverter modules coupled to a semiconductor opening switch (SOS) through an inductive resonant branch. Each module includes a plurality of switches that are switched in a fashion causing the one or more full bridge inverter modules to drive the semiconductor opening switch SOS through the resonant circuit to generate pulses to a load connected in parallel with the SOS.

ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

NASA Technical Reports Server (NTRS)

Vasile, Stefan; Lipson, Jerold

2012-01-01

The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

Low-voltage harmonic multiplying gyrotron traveling-wave amplifier in G band

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yeh, Y. S.; Guo, Y. W.; Kao, B. H.

Harmonic multiplying operation in a gyrotron traveling-wave amplifier (gyro-TWA) permits for magnetic field reduction and frequency multiplication. Lowering a beam voltage is an important step toward miniaturization of a harmonic multiplying gyro-TWA. However, the additional degree of freedom that is provided by the multitude cyclotron harmonics in a low-voltage harmonic multiplying gyro-TWA still easily generates various competing modes. An improved mode-selective circuit, using circular waveguides with various radii, can provide the rejection points within the frequency range to suppress competing modes. Simulated results reveal that the mode-selective circuit can provide an attenuation of more than 14 dB to suppress the competingmore » modes. Furthermore, the performance of the gyro-TWA is analyzed for studying the sensitivity of the saturated output power and full width at half maximum bandwidth of the gyro-TWA to the beam voltage and the magnetic field. A stable low-voltage harmonic multiplying gyro-TWA with the mode-selective circuit is predicted to yield a peak output power of 24 kW at 200.4 GHz, corresponding to a saturated gain of 56 dB at an interaction efficiency of 20%. The full width at half maximum bandwidth is 3.0 GHz.« less

Short-circuit current and ionic fluxes in the isolated colonic mucosa of Bufo arenarum

PubMed Central

Lew, V. L.

1970-01-01

1. The unidirectional fluxes of 22Na, 36Cl and [14C]bicarbonate ions were measured in paired portions of the isolated and short-circuited colonic mucosa of Bufo arenarum, separated from its muscular layer. Pharmacological effects as well as effects of changes in the composition of the nutrient solutions on the electrical parameters of membrane activity (potential difference, short-circuit current and total membrane resistance) are described. 2. The net fluxes of both Cl and bicarbonate ions were not significantly different from zero in the absence of electrochemical gradients across the membrane. 3. The net Na flux from mucosa to serosa represented a variable proportion of the short-circuit current ranging from 62 to 100%. 4. The proportion of membranes with high discrepancies between net Na flux and short-circuit current decreased with the duration of captivity of the toads. 5. When Na was entirely replaced by choline in the mucosal bathing solution, the short-circuit current dropped by a variable amount within the range of 64 to 98% of its control values in different membranes. This effect was completely reversible. Similar changes in the serosal solution had no effect. 6. The short-circuit current and potential difference were very sensitive to the serosal concentration of bicarbonate ions. In different membranes, 60-100% of the short-circuit current was reversibly abolished by bathing the serosal surface with a bicarbonate-free solution. The mucosal bicarbonate level had no effect on either the potential difference or the short-circuit current. 5 mM bicarbonate in the serosal solution restored at least 50% of the short-circuit control value and full recovery was attained by concentrations near 30 mM bicarbonate. 7. Anoxia brought the potential difference and short-circuit current reversibly down to zero in about 50 min. 8. Ouabain reduced the short-circuit current up to 80% in about 40 min when present in the serosal solution at a concentration of 10-4 M. At this or lower concentrations the ouabain effect was reversible. Above this level ouabain produced 100% inhibition in 3-4 hr, but this was no longer reversible. Ouabain had no effect on the short-circuit current either when applied to the mucosal surface or in the absence of Na from the mucosal solution. 9. Diamox produced a variable inhibition of the short-circuit current of up to 30% only at concentrations above 10 mM. 10. Possible mechanisms are discussed for the appearance of the non-Na component of the short-circuit current. A theory concerning its nature is proposed. PMID:5498503

A study on stimulation of DC high voltage power of LCC series parallel resonant in projectile velocity measurement system

NASA Astrophysics Data System (ADS)

Lu, Dong-dong; Gu, Jin-liang; Luo, Hong-e.; Xia, Yan

2017-10-01

According to specific requirements of the X-ray machine system for measuring velocity of outfield projectile, a DC high voltage power supply system is designed for the high voltage or the smaller current. The system comprises: a series resonant circuit is selected as a full-bridge inverter circuit; a high-frequency zero-current soft switching of a high-voltage power supply is realized by PWM output by STM32; a nanocrystalline alloy transformer is chosen as a high-frequency booster transformer; and the related parameters of an LCC series-parallel resonant are determined according to the preset parameters of the transformer. The concrete method includes: a LCC series parallel resonant circuit and a voltage doubling circuit are stimulated by using MULTISM and MATLAB; selecting an optimal solution and an optimal parameter of all parts after stimulation analysis; and finally verifying the correctness of the parameter by stimulation of the whole system. Through stimulation analysis, the output voltage of the series-parallel resonant circuit gets to 10KV in 28s: then passing through the voltage doubling circuit, the output voltage gets to 120KV in one hour. According to the system, the wave range of the output voltage is so small as to provide the stable X-ray supply for the X-ray machine for measuring velocity of outfield projectile. It is fast in charging and high in efficiency.

A test technique for measuring lightning-induced voltages on aircraft electrical circuits

NASA Technical Reports Server (NTRS)

Walko, L. C.

1974-01-01

The development of a test technique used for the measurement of lightning-induced voltages in the electrical circuits of a complete aircraft is described. The resultant technique utilizes a portable device known as a transient analyzer capable of generating unidirectional current impulses similar to lightning current surges, but at a lower current level. A linear relationship between the magnitude of lightning current and the magnitude of induced voltage permitted the scaling up of measured induced values to full threat levels. The test technique was found to be practical when used on a complete aircraft.

Heuristics for the Hodgkin-Huxley system.

PubMed

Hoppensteadt, Frank

2013-09-01

Hodgkin and Huxley (HH) discovered that voltages control ionic currents in nerve membranes. This led them to describe electrical activity in a neuronal membrane patch in terms of an electronic circuit whose characteristics were determined using empirical data. Due to the complexity of this model, a variety of heuristics, including relaxation oscillator circuits and integrate-and-fire models, have been used to investigate activity in neurons, and these simpler models have been successful in suggesting experiments and explaining observations. Connections between most of the simpler models had not been made clear until recently. Shown here are connections between these heuristics and the full HH model. In particular, we study a new model (Type III circuit): It includes the van der Pol-based models; it can be approximated by a simple integrate-and-fire model; and it creates voltages and currents that correspond, respectively, to the h and V components of the HH system. Copyright © 2012 Elsevier Inc. All rights reserved.

A precision analogue integrator system for heavy current measurement in MFDC resistance spot welding

NASA Astrophysics Data System (ADS)

Xia, Yu-Jun; Zhang, Zhong-Dian; Xia, Zhen-Xin; Zhu, Shi-Liang; Zhang, Rui

2016-02-01

In order to control and monitor the quality of middle frequency direct current (MFDC) resistance spot welding (RSW), precision measurement of the welding current up to 100 kA is required, for which Rogowski coils are the only viable current transducers at present. Thus, a highly accurate analogue integrator is the key to restoring the converted signals collected from the Rogowski coils. Previous studies emphasised that the integration drift is a major factor that influences the performance of analogue integrators, but capacitive leakage error also has a significant impact on the result, especially in long-time pulse integration. In this article, new methods of measuring and compensating capacitive leakage error are proposed to fabricate a precision analogue integrator system for MFDC RSW. A voltage holding test is carried out to measure the integration error caused by capacitive leakage, and an original integrator with a feedback adder is designed to compensate capacitive leakage error in real time. The experimental results and statistical analysis show that the new analogue integrator system could constrain both drift and capacitive leakage error, of which the effect is robust to different voltage levels of output signals. The total integration error is limited within  ±0.09 mV s-1 0.005% s-1 or full scale at a 95% confidence level, which makes it possible to achieve the precision measurement of the welding current of MFDC RSW with Rogowski coils of 0.1% accuracy class.

An Efficient Implementation For Real Time Applications Of The Wigner-Ville Distribution

NASA Astrophysics Data System (ADS)

Boashash, Boualem; Black, Peter; Whitehouse, Harper J.

1986-03-01

The Wigner-Ville Distribution (WVD) is a valuable tool for time-frequency signal analysis. In order to implement the WVD in real time an efficient algorithm and architecture have been developed which may be implemented with commercial components. This algorithm successively computes the analytic signal corresponding to the input signal, forms a weighted kernel function and analyses the kernel via a Discrete Fourier Transform (DFT). To evaluate the analytic signal required by the algorithm it is shown that the time domain definition implemented as a finite impulse response (FIR) filter is practical and more efficient than the frequency domain definition of the analytic signal. The windowed resolution of the WVD in the frequency domain is shown to be similar to the resolution of a windowed Fourier Transform. A real time signal processsor has been designed for evaluation of the WVD analysis system. The system is easily paralleled and can be configured to meet a variety of frequency and time resolutions. The arithmetic unit is based on a pair of high speed VLSI floating-point multiplier and adder chips. Dual operand buses and an independent result bus maximize data transfer rates. The system is horizontally microprogrammed and utilizes a full instruction pipeline. Each microinstruction specifies two operand addresses, a result location, the type of arithmetic and the memory configuration. input and output is via shared memory blocks with front-end processors to handle data transfers during the non access periods of the analyzer.

One-fiftieth scale model studies of 40-by 80-foot and 80-by 120-foot wind tunnel complex at NASA Ames Research Center

NASA Technical Reports Server (NTRS)

Schmidt, Gene I.; Rossow, Vernon J.; Vanaken, Johannes M.; Parrish, Cynthia L.

1987-01-01

The features of a 1/50-scale model of the National Full-Scale Aerodynamics Complex are first described. An overview is then given of some results from the various tests conducted with the model to aid in the design of the full-scale facility. It was found that the model tunnel simulated accurately many of the operational characteristics of the full-scale circuits. Some characteristics predicted by the model were, however, noted to differ from previous full-scale results by about 10%.

SiNOI and AlGaAs-on-SOI nonlinear circuits for continuum generation in Si photonics

NASA Astrophysics Data System (ADS)

El Dirani, Houssein; Monat, Christelle; Brision, Stéphane; Olivier, Nicolas; Jany, Christophe; Letartre, Xavier; Pu, Minhao; Girouard, Peter D.; Hagedorn Frandsen, Lars; Semenova, Elizaveta; Katsuo Oxenløwe, Leif; Yvind, Kresten; Sciancalepore, Corrado

2018-02-01

In this communication, we report on the design, fabrication, and testing of Silicon Nitride on Insulator (SiNOI) and Aluminum-Gallium-Arsenide (AlGaAs) on silicon-on-insulator (SOI) nonlinear photonic circuits for continuum generation in Silicon (Si) photonics. As recently demonstrated, the generation of frequency continua and supercontinua can be used to overcome the intrinsic limitations of nowadays silicon photonics notably concerning the heterogeneous integration of III-V on SOI lasers for datacom and telecom applications. By using the Kerr nonlinearity of monolithic silicon nitride and heterointegrated GaAs-based alloys on SOI, the generation of tens or even hundreds of new optical frequencies can be obtained in dispersion tailored waveguides, thus providing an all-optical alternative to the heterointegration of hundreds of standalone III-V on Si lasers. In our work, we present paths to energy-efficient continua generation on silicon photonics circuits. Notably, we demonstrate spectral broadening covering the full C-band via Kerrbased self-phase modulation in SiNOI nanowires featuring full process compatibility with Si photonic devices. Moreover, AlGaAs waveguides are heterointegrated on SOI in order to dramatically reduce (x1/10) thresholds in optical parametric oscillation and in the power required for supercontinuum generation under pulsed pumping. The manufacturing techniques allowing the monolithic co-integration of nonlinear functionalities on existing CMOS-compatible Si photonics for both active and passive components will be shown. Experimental evidence based on self-phase modulation show SiNOI and AlGaAs nanowires capable of generating wide-spanning frequency continua in the C-Band. This will pave the way for low-threshold power-efficient Kerr-based comb- and continuum- sources featuring compatibility with Si photonic integrated circuits (Si-PICs).

A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses.

PubMed

Qiao, Ning; Mostafa, Hesham; Corradi, Federico; Osswald, Marc; Stefanini, Fabio; Sumislawska, Dora; Indiveri, Giacomo

2015-01-01

Implementing compact, low-power artificial neural processing systems with real-time on-line learning abilities is still an open challenge. In this paper we present a full-custom mixed-signal VLSI device with neuromorphic learning circuits that emulate the biophysics of real spiking neurons and dynamic synapses for exploring the properties of computational neuroscience models and for building brain-inspired computing systems. The proposed architecture allows the on-chip configuration of a wide range of network connectivities, including recurrent and deep networks, with short-term and long-term plasticity. The device comprises 128 K analog synapse and 256 neuron circuits with biologically plausible dynamics and bi-stable spike-based plasticity mechanisms that endow it with on-line learning abilities. In addition to the analog circuits, the device comprises also asynchronous digital logic circuits for setting different synapse and neuron properties as well as different network configurations. This prototype device, fabricated using a 180 nm 1P6M CMOS process, occupies an area of 51.4 mm(2), and consumes approximately 4 mW for typical experiments, for example involving attractor networks. Here we describe the details of the overall architecture and of the individual circuits and present experimental results that showcase its potential. By supporting a wide range of cortical-like computational modules comprising plasticity mechanisms, this device will enable the realization of intelligent autonomous systems with on-line learning capabilities.

Physical picture of immersed diode experiments on HERMES III and SABRE

DOE Office of Scientific and Technical Information (OSTI.GOV)

Olson, C.L.; Mazarakis, M.G.; Menge, P.R.

A needle-like, high-current, electron beam has been produced on the Hermes III and SABRE accelerators at SNL using inductive voltage adder (IVA) technology, and a diode consisting of a needle cathode and a planar anode/bremmstrahlung converter which are both fully immersed in a strong solenoidal magnetic field (12--50 T). Desired nominal parameters are 10 MV, 40 kA, 0.5 mm radius cathode, and 5--35 cm anode-cathode gaps. High dose and small x-ray spot size are required for radiography applications. Results are presented of initial experiments on Hermes III and SABRE, which have produced doses up to 1 kRad {at} 1 meter,more » and at lower doses, spot sizes as small as 1.7 mm diameter.« less

Concurrent error detecting codes for arithmetic processors

NASA Technical Reports Server (NTRS)

Lim, R. S.

1979-01-01

A method of concurrent error detection for arithmetic processors is described. Low-cost residue codes with check-length l and checkbase m = 2 to the l power - 1 are described for checking arithmetic operations of addition, subtraction, multiplication, division complement, shift, and rotate. Of the three number representations, the signed-magnitude representation is preferred for residue checking. Two methods of residue generation are described: the standard method of using modulo m adders and the method of using a self-testing residue tree. A simple single-bit parity-check code is described for checking the logical operations of XOR, OR, and AND, and also the arithmetic operations of complement, shift, and rotate. For checking complement, shift, and rotate, the single-bit parity-check code is simpler to implement than the residue codes.

Techniques for computing the discrete Fourier transform using the quadratic residue Fermat number systems

NASA Technical Reports Server (NTRS)

Truong, T. K.; Chang, J. J.; Hsu, I. S.; Pei, D. Y.; Reed, I. S.

1986-01-01

The complex integer multiplier and adder over the direct sum of two copies of finite field developed by Cozzens and Finkelstein (1985) is specialized to the direct sum of the rings of integers modulo Fermat numbers. Such multiplication over the rings of integers modulo Fermat numbers can be performed by means of two integer multiplications, whereas the complex integer multiplication requires three integer multiplications. Such multiplications and additions can be used in the implementation of a discrete Fourier transform (DFT) of a sequence of complex numbers. The advantage of the present approach is that the number of multiplications needed to compute a systolic array of the DFT can be reduced substantially. The architectural designs using this approach are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

QCE: A Simulator for Quantum Computer Hardware

NASA Astrophysics Data System (ADS)

Michielsen, Kristel; de Raedt, Hans

2003-09-01

The Quantum Computer Emulator (QCE) described in this paper consists of a simulator of a generic, general purpose quantum computer and a graphical user interface. The latter is used to control the simulator, to define the hardware of the quantum computer and to debug and execute quantum algorithms. QCE runs in a Windows 98/NT/2000/ME/XP environment. It can be used to validate designs of physically realizable quantum processors and as an interactive educational tool to learn about quantum computers and quantum algorithms. A detailed exposition is given of the implementation of the CNOT and the Toffoli gate, the quantum Fourier transform, Grover's database search algorithm, an order finding algorithm, Shor's algorithm, a three-input adder and a number partitioning algorithm. We also review the results of simulations of an NMR-like quantum computer.

A spin transfer torque magnetoresistance random access memory-based high-density and ultralow-power associative memory for fully data-adaptive nearest neighbor search with current-mode similarity evaluation and time-domain minimum searching

NASA Astrophysics Data System (ADS)

Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2017-04-01

A high-density nonvolatile associative memory (NV-AM) based on spin transfer torque magnetoresistive random access memory (STT-MRAM), which achieves highly concurrent and ultralow-power nearest neighbor search with full adaptivity of the template data format, has been proposed and fabricated using the 90 nm CMOS/70 nm perpendicular-magnetic-tunnel-junction hybrid process. A truly compact current-mode circuitry is developed to realize flexibly controllable and high-parallel similarity evaluation, which makes the NV-AM adaptable to any dimensionality and component-bit of template data. A compact dual-stage time-domain minimum searching circuit is also developed, which can freely extend the system for more template data by connecting multiple NM-AM cores without additional circuits for integrated processing. Both the embedded STT-MRAM module and the computing circuit modules in this NV-AM chip are synchronously power-gated to completely eliminate standby power and maximally reduce operation power by only activating the currently accessed circuit blocks. The operations of a prototype chip at 40 MHz are demonstrated by measurement. The average operation power is only 130 µW, and the circuit density is less than 11 µm2/bit. Compared with the latest conventional works in both volatile and nonvolatile approaches, more than 31.3% circuit area reductions and 99.2% power improvements are achieved, respectively. Further power performance analyses are discussed, which verify the special superiority of the proposed NV-AM in low-power and large-memory-based VLSIs.

Heart-rate pulse-shift detector

NASA Technical Reports Server (NTRS)

Anderson, M.

1974-01-01

Detector circuit accurately separates and counts phase-shift pulses over wide range of basic pulse-rate frequency, and also provides reasonable representation of full repetitive EKG waveform. Single telemeter implanted in small animal monitors not only body temperature but also animal movement and heart rate.

Extremely high frequency RF effects on electronics.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Loubriel, Guillermo Manuel; Vigliano, David; Coleman, Phillip Dale

The objective of this work was to understand the fundamental physics of extremely high frequency RF effects on electronics. To accomplish this objective, we produced models, conducted simulations, and performed measurements to identify the mechanisms of effects as frequency increases into the millimeter-wave regime. Our purpose was to answer the questions, 'What are the tradeoffs between coupling, transmission losses, and device responses as frequency increases?', and, 'How high in frequency do effects on electronic systems continue to occur?' Using full wave electromagnetics codes and a transmission-line/circuit code, we investigated how extremely high-frequency RF propagates on wires and printed circuit boardmore » traces. We investigated both field-to-wire coupling and direct illumination of printed circuit boards to determine the significant mechanisms for inducing currents at device terminals. We measured coupling to wires and attenuation along wires for comparison to the simulations, looking at plane-wave coupling as it launches modes onto single and multiconductor structures. We simulated the response of discrete and integrated circuit semiconductor devices to those high-frequency currents and voltages, using SGFramework, the open-source General-purpose Semiconductor Simulator (gss), and Sandia's Charon semiconductor device physics codes. This report documents our findings.« less

Three-dimensional crossbar arrays of self-rectifying Si/SiO 2/Si memristors

DOE PAGES

Li, Can; Han, Lili; Jiang, Hao; ...

2017-06-05

Memristors are promising building blocks for the next generation memory, unconventional computing systems and beyond. Currently common materials used to build memristors are not necessarily compatible with the silicon dominant complementary metal-oxide-semiconductor (CMOS) technology. Furthermore, external selector devices or circuits are usually required in order for large memristor arrays to function properly, resulting in increased circuit complexity. Here we demonstrate fully CMOS-compatible, all-silicon based and self-rectifying memristors that negate the need for external selectors in large arrays. It consists of p- and n-type doped single crystalline silicon electrodes and a thin chemically produced silicon oxide switching layer. The device exhibitsmore » repeatable resistance switching behavior with high rectifying ratio (10 5), high ON/OFF conductance ratio (10 4) and attractive retention at 300 °C. We further build a 5-layer 3-dimensional (3D) crossbar array of 100 nm memristors by stacking fluid supported silicon membranes. The CMOS compatibility and self-rectifying behavior open up opportunities for mass production of memristor arrays and 3D hybrid circuits on full-wafer scale silicon and flexible substrates without increasing circuit complexity.« less

Ambient temperature cadmium zinc telluride radiation detector and amplifier circuit

DOEpatents

McQuaid, James H.; Lavietes, Anthony D.

1998-05-29

A low noise, low power consumption, compact, ambient temperature signal amplifier for a Cadmium Zinc Telluride (CZT) radiation detector. The amplifier can be used within a larger system (e.g., including a multi-channel analyzer) to allow isotopic analysis of radionuclides in the field. In one embodiment, the circuit stages of the low power, low noise amplifier are constructed using integrated circuit (IC) amplifiers , rather than discrete components, and include a very low noise, high gain, high bandwidth dual part preamplification stage, an amplification stage, and an filter stage. The low noise, low power consumption, compact, ambient temperature amplifier enables the CZT detector to achieve both the efficiency required to determine the presence of radio nuclides and the resolution necessary to perform isotopic analysis to perform nuclear material identification. The present low noise, low power, compact, ambient temperature amplifier enables a CZT detector to achieve resolution of less than 3% full width at half maximum at 122 keV for a Cobalt-57 isotope source. By using IC circuits and using only a single 12 volt supply and ground, the novel amplifier provides significant power savings and is well suited for prolonged portable in-field use and does not require heavy, bulky power supply components.

Reversing-counterpulse repetitive-pulse inductive storage circuit

DOEpatents

Honig, E.M.

1987-02-10

A high-power reversing-counterpulse repetitive-pulse inductive storage and transfer circuit includes an opening switch, a main energy storage coil, a counterpulse capacitor and a small inductor. After counterpulsing the opening switch off, the counterpulse capacitor is recharged by the main energy storage coil before the load pulse is initiated. This gives the counterpulse capacitor sufficient energy for the next counterpulse operation, although the polarity of the capacitor's voltage must be reversed before that can occur. By using a current-zero switch as the counterpulse start switch, the capacitor is disconnected from the circuit (with a full charge) when the load pulse is initiated, preventing the capacitor from depleting its energy store by discharging through the load. After the load pulse is terminated by reclosing the main opening switch, the polarity of the counterpulse capacitor voltage is reversed by discharging the capacitor through a small inductor and interrupting the discharge current oscillation at zero current and peak reversed voltage. The circuit enables high-power, high-repetition-rate operation with reusable switches and features total control (pulse-to-pulse) over output pulse initiation, duration, repetition rate, and, to some extent, risetime. 10 figs.

Analysis of SEL on Commercial SRAM Memories and Mixed-Field Characterization of a Latchup Detection Circuit for LEO Space Applications

NASA Astrophysics Data System (ADS)

Secondo, R.; Alía, R. Garcia; Peronnard, P.; Brugger, M.; Masi, A.; Danzeca, S.; Merlenghi, A.; Vaillé, J.-R.; Dusseau, L.

2017-08-01

A single event latchup (SEL) experiment based on commercial static random access memory (SRAM) memories has recently been proposed in the framework of the European Organization for Nuclear Research (CERN) Latchup Experiment and Student Satellite nanosatellite low Earth orbit (LEO) space mission. SEL characterization of three commercial SRAM memories has been carried out at the Paul Scherrer Institut (PSI) facility, using monoenergetic focused proton beams and different acquisition setups. The best target candidate was selected and a circuit for SEL detection has been proposed and tested at CERN, in the CERN High Energy AcceleRator Mixed-field facility (CHARM). Experimental results were carried out at test locations representative of the LEO environment, thus providing a full characterization of the SRAM cross sections, together with the analysis of the single-event effect and total ionizing dose of the latchup detection circuit in relation to the particle spectra expected during mission. The setups used for SEL monitoring are described, and details of the proposed circuit components and topology are presented. Experimental results obtained both at PSI and at CHARM facilities are discussed.

Flip-flop logic circuit based on fully solution-processed organic thin film transistor devices with reduced variations in electrical performance

NASA Astrophysics Data System (ADS)

Takeda, Yasunori; Yoshimura, Yudai; Adib, Faiz Adi Ezarudin Bin; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2015-04-01

Organic reset-set (RS) flip-flop logic circuits based on pseudo-CMOS inverters have been fabricated using full solution processing at a relatively low process temperatures of 150 °C or less. The work function for printed silver electrodes was increased from 4.7 to 5.4 eV through surface modification with a self-assembled monolayer (SAM) material. A bottom-gate, bottom-contact organic thin-film transistor (OTFT) device using a solution-processable small-molecular semiconductor material exhibited field-effect mobility of 0.40 cm2 V-1 s-1 in the saturation region and a threshold voltage (VTH) of -2.4 V in ambient air operation conditions. In order to reduce the variations in mobility and VTH, we designed a circuit with six transistors arranged in parallel, in order to average out their electrical characteristics. As a result, we have succeeded in reducing these variations without changing the absolute values of the mobility and VTH. The fabricated RS flip-flop circuits were functioned well and exhibited short delay times of 3.5 ms at a supply voltage of 20 V.

Driver for solar cell I-V characteristic plots

NASA Technical Reports Server (NTRS)

Turner, G. B. (Inventor)

1980-01-01

A bipolar voltage ramp generator which applies a linear voltage through a resistor to a solar cell for plotting its current versus voltage (I-V) characteristic between short circuit and open circuit conditions is disclosed. The generator has automatic stops at the end points. The resistor serves the multiple purpose of providing a current sensing resistor, setting the full-scale current value, and providing a load line with a slope approximately equal to one, such that it will pass through the origin and the approximate center of the I-V curve with about equal distance from that center to each of the end points.

Concentric transmon qubit featuring fast tunability and site-selective Z coupling

NASA Astrophysics Data System (ADS)

Weides, Martin; Braumueller, Jochen; Sandberg, Martin; Vissers, Michael; Schneider, Andre; Schloer, Steffen; Gruenhaupt, Lukas; Rotzinger, Hannes; Marthaler, Michael; Lukashenko, Alexander; Dieter, Amadeus; Ustinov, Alexey; Pappas, David

We present a planar qubit design based on a superconducting circuit that we call concentric transmon. While employing a simple fabrication process using Al evaporation and lift-off lithography, we observe qubit lifetimes and coherence times in the order of 10 μs. We systematically characterize loss channels such as incoherent dielectric loss, Purcell decay and radiative losses. The implementation of a gradiometric SQUID loop allows for a fast tuning of the qubit transition frequency and therefore for full tomographic control of the quantum circuit. The presented qubit design features a passive direct Z coupling between neighboring qubits, being a pending quest in the field of quantum simulation.

Waferscale nanophotonic circuits made from diamond-on-insulator substrates.

PubMed

Rath, P; Gruhler, N; Khasminskaya, S; Nebel, C; Wild, C; Pernice, W H P

2013-05-06

Wide bandgap dielectrics are attractive materials for the fabrication of photonic devices because they allow broadband optical operation and do not suffer from free-carrier absorption. Here we show that polycrystalline diamond thin films deposited by chemical vapor deposition provide a promising platform for the realization of large scale integrated photonic circuits. We present a full suite of photonic components required for the investigation of on-chip devices, including input grating couplers, millimeter long nanophotonic waveguides and microcavities. In microring resonators we measure loaded optical quality factors up to 11,000. Corresponding propagation loss of 5 dB/mm is also confirmed by measuring transmission through long waveguides.

Magnetically coupled resonance wireless charging technology principles and transfer mechanisms

NASA Astrophysics Data System (ADS)

Zhou, Jiehua; Wan, Jian; Ma, Yinping

2017-05-01

With the tenure of Electric-Vehicle rising around the world, the charging methods have been paid more and more attention, the current charging mode mainly has the charging posts and battery swapping station. The construction of the charging pile or battery swapping station not only require lots of manpower, material costs but the bare conductor is also easy to generate electric spark hidden safety problems, still occupies large space. Compared with the wired charging, wireless charging mode is flexible, unlimited space and location factors and charging for vehicle safety and quickly. It complements the traditional charging methods in adaptability and the independent charge deficiencies. So the researching the wireless charging system have an important practical significance and application value. In this paper, wireless charging system designed is divided into three parts: the primary side, secondary side and resonant coupling. The main function of the primary side is to generate high-frequency alternating current, so selecting CLASS-E amplifier inverter structure through the research on full bridge, half-bridge and power amplification circuit. Addition, the wireless charging system is susceptible to outside interference, frequency drift phenomenon. Combined with the wireless energy transmission characteristics, resonant parts adopt resonant coupling energy transmission scheme and the Series-Series coupling compensation structure. For the electric vehicle charging power and voltage requirements, the main circuit is a full bridge inverter and Boost circuit used as the secondary side.

Laser Direct Routing for High Density Interconnects

NASA Astrophysics Data System (ADS)

Moreno, Wilfrido Alejandro

The laser restructuring of electronic circuits fabricated using standard Very Large Scale Integration (VLSI) process techniques, is an excellent alternative that allows low-cost quick turnaround production with full circuit similarity between the Laser Restructured prototype and the customized product for mass production. Laser Restructurable VLSI (LRVLSI) would allow design engineers the capability to interconnect cells that implement generic logic functions and signal processing schemes to achieve a higher level of design complexity. LRVLSI of a particular circuit at the wafer or packaged chip level is accomplished using an integrated computer controlled laser system to create low electrical resistance links between conductors and to cut conductor lines. An infrastructure for rapid prototyping and quick turnaround using Laser Restructuring of VLSI circuits was developed to meet three main parallel objectives: to pursue research on novel interconnect technologies using LRVLSI, to develop the capability of operating in a quick turnaround mode, and to maintain standardization and compatibility with commercially available equipment for feasible technology transfer. The system is to possess a high degree of flexibility, high data quality, total controllability, full documentation, short downtime, a user-friendly operator interface, automation, historical record keeping, and error indication and logging. A specially designed chip "SLINKY" was used as the test vehicle for the complete characterization of the Laser Restructuring system. With the use of Design of Experiment techniques the Lateral Diffused Link (LDL), developed originally at MIT Lincoln Laboratories, was completely characterized and for the first time a set of optimum process parameters was obtained. With the designed infrastructure fully operational, the priority objective was the search for a substitute for the high resistance, high current leakage to substrate, and relatively low density Lateral Diffused Link. A high density Laser Vertical Link with resistance values below 10 ohms was developed, studied and tested using design of experiment methodologies. The vertical link offers excellent advantages in the area of quick prototyping of electronic circuits, but even more important, due to having similar characteristics to a foundry produced via, it gives quick transfer from the prototype system verification stage to the mass production stage.

Fast and Scalable Computation of the Forward and Inverse Discrete Periodic Radon Transform.

PubMed

Carranza, Cesar; Llamocca, Daniel; Pattichis, Marios

2016-01-01

The discrete periodic radon transform (DPRT) has extensively been used in applications that involve image reconstructions from projections. Beyond classic applications, the DPRT can also be used to compute fast convolutions that avoids the use of floating-point arithmetic associated with the use of the fast Fourier transform. Unfortunately, the use of the DPRT has been limited by the need to compute a large number of additions and the need for a large number of memory accesses. This paper introduces a fast and scalable approach for computing the forward and inverse DPRT that is based on the use of: a parallel array of fixed-point adder trees; circular shift registers to remove the need for accessing external memory components when selecting the input data for the adder trees; an image block-based approach to DPRT computation that can fit the proposed architecture to available resources; and fast transpositions that are computed in one or a few clock cycles that do not depend on the size of the input image. As a result, for an N × N image (N prime), the proposed approach can compute up to N(2) additions per clock cycle. Compared with the previous approaches, the scalable approach provides the fastest known implementations for different amounts of computational resources. For example, for a 251×251 image, for approximately 25% fewer flip-flops than required for a systolic implementation, we have that the scalable DPRT is computed 36 times faster. For the fastest case, we introduce optimized just 2N + ⌈log(2) N⌉ + 1 and 2N + 3 ⌈log(2) N⌉ + B + 2 cycles, architectures that can compute the DPRT and its inverse in respectively, where B is the number of bits used to represent each input pixel. On the other hand, the scalable DPRT approach requires more 1-b additions than for the systolic implementation and provides a tradeoff between speed and additional 1-b additions. All of the proposed DPRT architectures were implemented in VHSIC Hardware Description Language (VHDL) and validated using an Field-Programmable Gate Array (FPGA) implementation.

From Spontaneous Motor Activity to Coordinated Behaviour: A Developmental Model

PubMed Central

Marques, Hugo Gravato; Bharadwaj, Arjun; Iida, Fumiya

2014-01-01

In mammals, the developmental path that links the primary behaviours observed during foetal stages to the full fledged behaviours observed in adults is still beyond our understanding. Often theories of motor control try to deal with the process of incremental learning in an abstract and modular way without establishing any correspondence with the mammalian developmental stages. In this paper, we propose a computational model that links three distinct behaviours which appear at three different stages of development. In order of appearance, these behaviours are: spontaneous motor activity (SMA), reflexes, and coordinated behaviours, such as locomotion. The goal of our model is to address in silico four hypotheses that are currently hard to verify in vivo: First, the hypothesis that spinal reflex circuits can be self-organized from the sensor and motor activity induced by SMA. Second, the hypothesis that supraspinal systems can modulate reflex circuits to achieve coordinated behaviour. Third, the hypothesis that, since SMA is observed in an organism throughout its entire lifetime, it provides a mechanism suitable to maintain the reflex circuits aligned with the musculoskeletal system, and thus adapt to changes in body morphology. And fourth, the hypothesis that by changing the modulation of the reflex circuits over time, one can switch between different coordinated behaviours. Our model is tested in a simulated musculoskeletal leg actuated by six muscles arranged in a number of different ways. Hopping is used as a case study of coordinated behaviour. Our results show that reflex circuits can be self-organized from SMA, and that, once these circuits are in place, they can be modulated to achieve coordinated behaviour. In addition, our results show that our model can naturally adapt to different morphological changes and perform behavioural transitions. PMID:25057775

Smart Power: New power integrated circuit technologies and their applications

NASA Astrophysics Data System (ADS)

Kuivalainen, Pekka; Pohjonen, Helena; Yli-Pietilae, Timo; Lenkkeri, Jaakko

1992-05-01

Power Integrated Circuits (PIC) is one of the most rapidly growing branches of the semiconductor technology. The PIC markets has been forecast to grow from 660 million dollars in 1990 to 1658 million dollars in 1994. It has even been forecast that at the end of the 1990's the PIC markets would correspond to the value of the whole semiconductor production in 1990. Automotive electronics will play the leading role in the development of the standard PIC's. Integrated motor drivers (36 V/4 A), smart integrated switches (60 V/30 A), solenoid drivers, integrated switch-mode power supplies and regulators are the latest standard devices of the PIC manufactures. ASIC (Application Specific Integrated Circuits) PIC solutions are needed for the same reasons as other ASIC devices: there are no proper standard devices, a company has a lot of application knowhow, which should be kept inside the company, the size of the product must be reduced, and assembly costs are wished to be reduced by decreasing the number of discrete devices. During the next few years the most probable ASIC PIC applications in Finland will be integrated solenoid and motor drivers, an integrated electronic lamp ballast circuit and various sensor interface circuits. Application of the PIC technologies to machines and actuators will strongly be increased all over the world. This means that various PIC's, either standard PIC's or full custom ASIC circuits, will appear in many products which compete with the corresponding Finnish products. Therefore the development of the PIC technologies must be followed carefully in order to immediately be able to apply the latest development in the smart power technologies and their design methods.

Biasing of Capacitive Micromachined Ultrasonic Transducers.

PubMed

Caliano, Giosue; Matrone, Giulia; Savoia, Alessandro Stuart

2017-02-01

Capacitive micromachined ultrasonic transducers (CMUTs) represent an effective alternative to piezoelectric transducers for medical ultrasound imaging applications. They are microelectromechanical devices fabricated using silicon micromachining techniques, developed in the last two decades in many laboratories. The interest for this novel transducer technology relies on its full compatibility with standard integrated circuit technology that makes it possible to integrate on the same chip the transducers and the electronics, thus enabling the realization of extremely low-cost and high-performance devices, including both 1-D or 2-D arrays. Being capacitive transducers, CMUTs require a high bias voltage to be properly operated in pulse-echo imaging applications. The typical bias supply residual ripple of high-quality high-voltage (HV) generators is in the millivolt range, which is comparable with the amplitude of the received echo signals, and it is particularly difficult to minimize. The aim of this paper is to analyze the classical CMUT biasing circuits, highlighting the features of each one, and to propose two novel HV generator architectures optimized for CMUT biasing applications. The first circuit proposed is an ultralow-residual ripple (<5 [Formula: see text]) HV generator that uses an extremely stable sinusoidal power oscillator topology. The second circuit employs a commercially available integrated step-up converter characterized by a particularly efficient switching topology. The circuit is used to bias the CMUT by charging a buffer capacitor synchronously with the pulsing sequence, thus reducing the impact of the switching noise on the received echo signals. The small area of the circuit (about 1.5 cm 2 ) makes it possible to generate the bias voltage inside the probe, very close to the CMUT, making the proposed solution attractive for portable applications. Measurements and experiments are shown to demonstrate the effectiveness of the new approaches presented.

30 CFR 75.805 - Couplers.

Code of Federal Regulations, 2010 CFR

2010-07-01

... ground check continuity conductor shall be broken first and the ground conductors shall be broken last.... [Statutory Provisions] Couplers that are used with medium-voltage or high-voltage power circuits shall be of the three-phase type with a full metallic shell, except that the Secretary may permit, under such...

Analysis of Lightning-induced Impulse Magnetic Fields in the Building with an Insulated Down Conductor

NASA Astrophysics Data System (ADS)

Du, Patrick Y.; Zhou, Qi-Bin

This paper presents an analysis of lightning-induced magnetic fields in a building. The building of concern is protected by the lightning protection system with an insulated down conductor. In this paper a system model for metallic structure of the building is constructed first using the circuit approach. The circuit model of the insulated down conductor is discussed extensively, and explicit expressions of the circuit parameters are presented. The system model was verified experimentally in the laboratory. The modeling approach is applied to analyze the impulse magnetic fields in a full-scale building during a direct lightning strike. It is found that the impulse magnetic field is significantly high near the down conductor. The field is attenuated if the down conductor is moved to a column in the building. The field can be reduced further if the down conductor is housed in an earthed metal pipe. Recommendations for protecting critical equipment against lightning-induced magnetic fields are also provided in the paper.

Tracing Activity Across the Whole Brain Neural Network with Optogenetic Functional Magnetic Resonance Imaging

PubMed Central

Lee, Jin Hyung

2011-01-01

Despite the overwhelming need, there has been a relatively large gap in our ability to trace network level activity across the brain. The complex dense wiring of the brain makes it extremely challenging to understand cell-type specific activity and their communication beyond a few synapses. Recent development of the optogenetic functional magnetic resonance imaging (ofMRI) provides a new impetus for the study of brain circuits by enabling causal tracing of activities arising from defined cell types and firing patterns across the whole brain. Brain circuit elements can be selectively triggered based on their genetic identity, cell body location, and/or their axonal projection target with temporal precision while the resulting network response is monitored non-invasively with unprecedented spatial and temporal accuracy. With further studies including technological innovations to bring ofMRI to its full potential, ofMRI is expected to play an important role in our system-level understanding of the brain circuit mechanism. PMID:22046160

High efficiency silicon solar cell based on asymmetric nanowire.

PubMed

Ko, Myung-Dong; Rim, Taiuk; Kim, Kihyun; Meyyappan, M; Baek, Chang-Ki

2015-07-08

Improving the efficiency of solar cells through novel materials and devices is critical to realize the full potential of solar energy to meet the growing worldwide energy demands. We present here a highly efficient radial p-n junction silicon solar cell using an asymmetric nanowire structure with a shorter bottom core diameter than at the top. A maximum short circuit current density of 27.5 mA/cm(2) and an efficiency of 7.53% were realized without anti-reflection coating. Changing the silicon nanowire (SiNW) structure from conventional symmetric to asymmetric nature improves the efficiency due to increased short circuit current density. From numerical simulation and measurement of the optical characteristics, the total reflection on the sidewalls is seen to increase the light trapping path and charge carrier generation in the radial junction of the asymmetric SiNW, yielding high external quantum efficiency and short circuit current density. The proposed asymmetric structure has great potential to effectively improve the efficiency of the SiNW solar cells.

A study of short test and charge retention test methods for nickel-cadmium spacecraft cells

NASA Technical Reports Server (NTRS)

Scott, W. R.

1975-01-01

Methods for testing nickel-cadmium cells for internal shorts and charge retention were studied. Included were (a) open circuit voltage decay after a brief charge, (b) open circuit voltage recovery after shorting, and (c) open circuit voltage decay and capacity loss after a full charge. The investigation included consideration of the effects of prior history, of conditioning cells prior to testing, and of various test method variables on the results of the tests. Sensitivity of the tests was calibrated in terms of equivalent external resistance. The results were correlated. It was shown that a large number of variables may affect the results of these tests. It is concluded that the voltage decay after a brief charge and the voltage recovery methods are more sensitive than the charged stand method, and can detect an internal short equivalent to a resistance of about (10,000/C)ohms where "C' is the numerical value of the capacity of the cell in ampere hours.

Measurement of electron density using reactance cutoff probe

DOE Office of Scientific and Technical Information (OSTI.GOV)

You, K. H.; Seo, B. H.; Kim, J. H.

2016-05-15

This paper proposes a new measurement method of electron density using the reactance spectrum of the plasma in the cutoff probe system instead of the transmission spectrum. The highly accurate reactance spectrum of the plasma-cutoff probe system, as expected from previous circuit simulations [Kim et al., Appl. Phys. Lett. 99, 131502 (2011)], was measured using the full two-port error correction and automatic port extension methods of the network analyzer. The electron density can be obtained from the analysis of the measured reactance spectrum, based on circuit modeling. According to the circuit simulation results, the reactance cutoff probe can measure themore » electron density more precisely than the previous cutoff probe at low densities or at higher pressure. The obtained results for the electron density are presented and discussed for a wide range of experimental conditions, and this method is compared with previous methods (a cutoff probe using the transmission spectrum and a single Langmuir probe).« less

Intrasystem Analysis Program (IAP) code summaries

NASA Astrophysics Data System (ADS)

Dobmeier, J. J.; Drozd, A. L. S.; Surace, J. A.

1983-05-01

This report contains detailed descriptions and capabilities of the codes that comprise the Intrasystem Analysis Program. The four codes are: Intrasystem Electromagnetic Compatibility Analysis Program (IEMCAP), General Electromagnetic Model for the Analysis of Complex Systems (GEMACS), Nonlinear Circuit Analysis Program (NCAP), and Wire Coupling Prediction Models (WIRE). IEMCAP is used for computer-aided evaluation of electromagnetic compatibility (ECM) at all stages of an Air Force system's life cycle, applicable to aircraft, space/missile, and ground-based systems. GEMACS utilizes a Method of Moments (MOM) formalism with the Electric Field Integral Equation (EFIE) for the solution of electromagnetic radiation and scattering problems. The code employs both full matrix decomposition and Banded Matrix Iteration solution techniques and is expressly designed for large problems. NCAP is a circuit analysis code which uses the Volterra approach to solve for the transfer functions and node voltage of weakly nonlinear circuits. The Wire Programs deal with the Application of Multiconductor Transmission Line Theory to the Prediction of Cable Coupling for specific classes of problems.

TOFPET 2: A high-performance circuit for PET time-of-flight

NASA Astrophysics Data System (ADS)

Di Francesco, Agostino; Bugalho, Ricardo; Oliveira, Luis; Rivetti, Angelo; Rolo, Manuel; Silva, Jose C.; Varela, Joao

2016-07-01

We present a readout and digitization ASIC featuring low-noise and low-power for time-of flight (TOF) applications using SiPMs. The circuit is designed in standard CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in Positron Emission Tomography (TOF-PET). The input amplifier is a low impedance current conveyor based on a regulated common-gate topology. Each channel has quad-buffered analogue interpolation TDCs (time binning 20 ps) and charge integration ADCs with linear response at full scale (1500 pC). The signal amplitude can also be derived from the measurement of time-over-threshold (ToT). Simulation results show that for a single photo-electron signal with charge 200 (550) fC generated by a SiPM with (320 pF) capacitance the circuit has 24 (30) dB SNR, 75 (39) ps r.m.s. resolution, and 4 (8) mW power consumption. The event rate is 600 kHz per channel, with up to 2 MHz dark counts rejection.

Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate

NASA Astrophysics Data System (ADS)

Kumar, Manoj; Arya, Sandeep K.; Pandey, Sujata

2012-03-01

Digital controlled oscillators (DCOs) are the core of all digital phase locked loop (ADPLL) circuits. Here, DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology. Three, four and five bit controlled DCO with NMOS, PMOS and NMOS & PMOS transistor switching networks are presented. A three-transistor XNOR gate has been used as the inverter which is used as the delay cell. Delay has been controlled digitally with a switch network of NMOS and PMOS transistors. The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591 μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740 μW. A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998 μW. Output frequency and power consumption results for 4 & 6 bit DCO circuits with one PMOS and NMOS & PMOS switching network have also been presented. The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits. Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.

New Magneto-Inductive DC Magnetometer for Space Missions

NASA Astrophysics Data System (ADS)

Moldwin, M.; Bronner, B.; Regoli, L.; Thoma, J.; Shen, A.; Jenkins, G.; Cutler, J.

2017-12-01

A new magneto-inductive DC magnetometer is being developed at the University of Michigan that provides fluxgate quality measurements in a low mass, volume, power and cost package. The magnetometer enables constellation-class missions not only due to its low-resource requirements, but also its potential for commercial integrated circuit fabrication. The magneto-inductive operating principle is based on a simple resistance-inductor (RL) circuit and involves measurement of the time it takes to charge and discharge the inductor between an upper and lower threshold by means of a Schmitt trigger oscillator. This time is proportional to the inductance that in turn is proportional to the field strength. We have modeled the operating principle in the circuit simulator SPICE and have built a proto-type using modified commercial sensors. The performance specifications include a dynamic range over the full-Earth's field, sampling rates up to 80 Hz, sensor and electronics mass of about 30 g, circuit board and sensor housing volume of < 100 cm3, and power consumption of about 5 mW. This system's noise levels are predicted to be about 100 pT /√Hz @ 1 Hz with a precision of about 100 pT. Due to the simple circuit design, lack of an analog-to-digital converter, and choice of oscillator, we anticipate that it will be extremely temperature stable and radiation tolerant. This presentation will describe the constellation mission enabling design, the development status and the testing results of this new magnetometer.

A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses

PubMed Central

Qiao, Ning; Mostafa, Hesham; Corradi, Federico; Osswald, Marc; Stefanini, Fabio; Sumislawska, Dora; Indiveri, Giacomo

2015-01-01

Implementing compact, low-power artificial neural processing systems with real-time on-line learning abilities is still an open challenge. In this paper we present a full-custom mixed-signal VLSI device with neuromorphic learning circuits that emulate the biophysics of real spiking neurons and dynamic synapses for exploring the properties of computational neuroscience models and for building brain-inspired computing systems. The proposed architecture allows the on-chip configuration of a wide range of network connectivities, including recurrent and deep networks, with short-term and long-term plasticity. The device comprises 128 K analog synapse and 256 neuron circuits with biologically plausible dynamics and bi-stable spike-based plasticity mechanisms that endow it with on-line learning abilities. In addition to the analog circuits, the device comprises also asynchronous digital logic circuits for setting different synapse and neuron properties as well as different network configurations. This prototype device, fabricated using a 180 nm 1P6M CMOS process, occupies an area of 51.4 mm2, and consumes approximately 4 mW for typical experiments, for example involving attractor networks. Here we describe the details of the overall architecture and of the individual circuits and present experimental results that showcase its potential. By supporting a wide range of cortical-like computational modules comprising plasticity mechanisms, this device will enable the realization of intelligent autonomous systems with on-line learning capabilities. PMID:25972778

Architecture of enteric neural circuits involved in intestinal motility.

PubMed

Costa, M; Brookes, S H

2008-08-01

This short review describes the conceptual development in the search for the enteric neural circuits with the initial identifications of the classes of enteric neurons on the bases of their morphology, neurochemistry, biophysical properties, projections and connectivity. The discovery of the presence of multiple neurochemicals in the same nerve cells in specific combinations led to the concept of "chemical coding" and of "plurichemical transmission". The proposal that enteric reflexes are largely responsible for the propulsion of contents led to investigations of polarised reflex pathways and how these may be activated to generate the coordinated propulsive behaviour of the intestine. The research over the past decades attempted to integrate information of chemical neuroanatomy with functional studies, with the development of methods combining anatomical, functional and pharmacological techniques. This multidisciplinary strategy led to a full accounting of all functional classes of enteric neurons in the guinea-pig, and advanced wiring diagrams of the enteric neural circuits have been proposed. In parallel, investigations of the actual behaviour of the intestine during physiological motor activity have advanced with the development of spatio-temporal analysis from video recordings. The relation between neural pathways, their activities and the generation of patterns of motor activity remain largely unexplained. The enteric neural circuits appear not set in rigid programs but respond to different physico-chemical contents in an adaptable way (neuromechanical hypothesis). The generation of the complex repertoire of motor patterns results from the interplay of myogenic and neuromechanical mechanisms with spontaneous generation of migratory motor activity by enteric circuits.

G-band harmonic multiplying gyrotron traveling-wave amplifier with a mode-selective circuit

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yeh, Y. S.; Chen, Chang-Hong; Wang, Z. W.

Harmonic multiplying gyrotron traveling-wave amplifiers (gyro-TWAs) permit for magnetic field reduction and frequency multiplication. A high-order-mode harmonic multiplying gyro-TWA with large circuit dimensions and low ohmic loss can achieve a high average power. By amplifying a fundamental harmonic TE{sub 01} drive wave, the second harmonic component of the beam current initiates a TE{sub 02} wave to be amplified. Wall losses can suppress some competing modes because they act as an effective sink of the energy of the modes. However, such wall losses do not suppress all competing modes as the fields are contracted in the copper section in the gyro-TWA.more » An improved mode-selective circuit, using circular waveguides with the specified radii, can provide the rejection points within the frequency range to suppress the competing modes. The simulated results reveal that the mode-selective circuit can provide an attenuation of more than 10 dB to suppress the competing modes (TE{sub 21}, TE{sub 51}, TE{sub 22}, and TE{sub 03}). A G-band second harmonic multiplying gyro-TWA with the mode-selective circuit is predicted to yield a peak output power of 50 kW at 198.8 GHz, corresponding to a saturated gain of 55 dB at an interaction efficiency of 10%. The full width at half maximum bandwidth is 5 GHz.« less

Full-Circle Resolver-to-Linear-Analog Converter

NASA Technical Reports Server (NTRS)

Alhorn, Dean C.; Smith, Dennis A.; Howard, David E.

2005-01-01

A circuit generates sinusoidal excitation signals for a shaft-angle resolver and, like the arctangent circuit described in the preceding article, generates an analog voltage proportional to the shaft angle. The disadvantages of the circuit described in the preceding article arise from the fact that it must be made from precise analog subcircuits, including a functional block capable of implementing some trigonometric identities; this circuitry tends to be expensive, sensitive to noise, and susceptible to errors caused by temperature-induced drifts and imprecise matching of gains and phases. These disadvantages are overcome by the design of the present circuit. The present circuit (see figure) includes an excitation circuit, which generates signals Ksin(Omega(t)) and Kcos(Omega(t)) [where K is an amplitude, Omega denotes 2(pi)x a carrier frequency (the design value of which is 10 kHz), and t denotes time]. These signals are applied to the excitation terminals of a shaft-angle resolver, causing the resolver to put out signals C sin(Omega(t)-Theta) and C cos(Omega(t)-Theta). The cosine excitation signal and the cosine resolver output signal are processed through inverting comparator circuits, which are configured to function as inverting squarers, to obtain logic-level or square-wave signals .-LL[cos(Omega(t)] and -LL[cos(Omega(t)-Theta)], respectively. These signals are fed as inputs to a block containing digital logic circuits that effectively measure the phase difference (which equals Theta between the two logic-level signals). The output of this block is a pulse-width-modulated signal, PWM(Theta), the time-averaged value of which ranges from 0 to 5 VDC as Theta ranges from .180 to +180deg. PWM(Theta) is fed to a block of amplifying and level-shifting circuitry, which converts the input PWM waveform to an output waveform that switches between precise reference voltage levels of +10 and -10 V. This waveform is processed by a two-pole, low-pass filter, which removes the carrier-frequency component. The final output signal is a DC potential, proportional to Theta that ranges continuously from -10 V at Theta = -180deg to +10 V at Theta = +180deg..

Superradiance of cold atoms coupled to a superconducting circuit

NASA Astrophysics Data System (ADS)

Braun, Daniel; Hoffman, Jonathan; Tiesinga, Eite

2011-06-01

We investigate superradiance of an ensemble of atoms coupled to an integrated superconducting LC circuit. Particular attention is paid to the effect of inhomogeneous coupling constants. Combining perturbation theory in the inhomogeneity and numerical simulations, we show that inhomogeneous coupling constants can significantly affect the superradiant relaxation process. Incomplete relaxation terminating in “dark states” can occur, from which the only escape is through individual spontaneous emission on a much longer time scale. The relaxation dynamics can be significantly accelerated or retarded, depending on the distribution of the coupling constants. On the technical side, we also generalize the previously known propagator of superradiance for identical couplings in the completely symmetric sector to the full exponentially large Hilbert space.

High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

PubMed

Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

2015-08-12

Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

Molecular evidence for the first records of facultative parthenogenesis in elapid snakes

PubMed Central

Sanders, K. L.

2018-01-01

Parthenogenesis is a form of asexual reproduction by which embryos develop from unfertilized eggs. Parthenogenesis occurs in reptiles; however, it is not yet known to occur in the widespread elapid snakes (Elapidae), which include well-known taxa such as cobras, mambas, taipans and sea snakes. Here, we describe the production of viable parthenogens in two species of Australo-Papuan elapids with divergent reproductive modes: the oviparous coastal/Papuan taipan (Oxyuranus scutellatus) and the viviparous southern death adder (Acanthophis antarcticus). Analyses of nuclear SNP data excluded paternity for putative fathers and convincingly demonstrated asexual reproduction, thus representing the first evidence of facultative parthenogenesis in Elapidae. Our finding has broad implications for understanding the evolution of reproductive diversity in snakes, as well as managing the conservation of genetic diversity in wild and captive populations. PMID:29515892

Molecular evidence for the first records of facultative parthenogenesis in elapid snakes.

PubMed

Allen, L; Sanders, K L; Thomson, V A

2018-02-01

Parthenogenesis is a form of asexual reproduction by which embryos develop from unfertilized eggs. Parthenogenesis occurs in reptiles; however, it is not yet known to occur in the widespread elapid snakes (Elapidae), which include well-known taxa such as cobras, mambas, taipans and sea snakes. Here, we describe the production of viable parthenogens in two species of Australo-Papuan elapids with divergent reproductive modes: the oviparous coastal/Papuan taipan ( Oxyuranus scutellatus ) and the viviparous southern death adder ( Acanthophis antarcticus ). Analyses of nuclear SNP data excluded paternity for putative fathers and convincingly demonstrated asexual reproduction, thus representing the first evidence of facultative parthenogenesis in Elapidae. Our finding has broad implications for understanding the evolution of reproductive diversity in snakes, as well as managing the conservation of genetic diversity in wild and captive populations.

Validation of an Accurate Three-Dimensional Helical Slow-Wave Circuit Model

NASA Technical Reports Server (NTRS)

Kory, Carol L.

1997-01-01

The helical slow-wave circuit embodies a helical coil of rectangular tape supported in a metal barrel by dielectric support rods. Although the helix slow-wave circuit remains the mainstay of the traveling-wave tube (TWT) industry because of its exceptionally wide bandwidth, a full helical circuit, without significant dimensional approximations, has not been successfully modeled until now. Numerous attempts have been made to analyze the helical slow-wave circuit so that the performance could be accurately predicted without actually building it, but because of its complex geometry, many geometrical approximations became necessary rendering the previous models inaccurate. In the course of this research it has been demonstrated that using the simulation code, MAFIA, the helical structure can be modeled with actual tape width and thickness, dielectric support rod geometry and materials. To demonstrate the accuracy of the MAFIA model, the cold-test parameters including dispersion, on-axis interaction impedance and attenuation have been calculated for several helical TWT slow-wave circuits with a variety of support rod geometries including rectangular and T-shaped rods, as well as various support rod materials including isotropic, anisotropic and partially metal coated dielectrics. Compared with experimentally measured results, the agreement is excellent. With the accuracy of the MAFIA helical model validated, the code was used to investigate several conventional geometric approximations in an attempt to obtain the most computationally efficient model. Several simplifications were made to a standard model including replacing the helical tape with filaments, and replacing rectangular support rods with shapes conforming to the cylindrical coordinate system with effective permittivity. The approximate models are compared with the standard model in terms of cold-test characteristics and computational time. The model was also used to determine the sensitivity of various circuit parameters including typical manufacturing dimensional tolerances and support rod permittivity. By varying the circuit parameters of an accurate model using MAFIA, these sensitivities can be computed for manufacturing concerns, and design optimization previous to fabrication, thus eliminating the need for costly experimental iterations. Several variations were made to a standard helical circuit using MAFIA to investigate the effect that variations on helical tape and support rod width, metallized loading height and support rod permittivity, have on TWT cold-test characteristics.

An Interdisciplinary Microprocessor Project.

ERIC Educational Resources Information Center

Wilcox, Alan D.; And Others

1985-01-01

Describes an unusual project in which third-year computer science students designed and built a four-bit multiplier circuit and then combines it with software to complete a full 16-bit multiplication. The multiplier was built using TTL components, interfaced with a Z-80 microprocessor system, and programed in assembly language. (JN)

Integrated biocircuits: engineering functional multicellular circuits and devices.

PubMed

Prox, Jordan; Smith, Tory; Holl, Chad; Chehade, Nick; Guo, Liang

2018-04-01

Implantable neurotechnologies have revolutionized neuromodulatory medicine for treating the dysfunction of diseased neural circuitry. However, challenges with biocompatibility and lack of full control over neural network communication and function limits the potential to create more stable and robust neuromodulation devices. Thus, we propose a platform technology of implantable and programmable cellular systems, namely Integrated Biocircuits, which use only cells as the functional components of the device. We envision the foundational principles for this concept begins with novel in vitro platforms used for the study and reconstruction of cellular circuitry. Additionally, recent advancements in organoid and 3D culture systems account for microenvironment factors of cytoarchitecture to construct multicellular circuits as they are normally formed in the brain. We explore the current state of the art of these platforms to provide knowledge of their advancements in circuit fabrication and identify the current biological principles that could be applied in designing integrated biocircuit devices. We have highlighted the exemplary methodologies and techniques of in vitro circuit fabrication and propose the integration of selected controllable parameters, which would be required in creating suitable biodevices. We provide our perspective and propose new insights into the future of neuromodulaion devices within the scope of living cellular systems that can be applied in designing more reliable and biocompatible stimulation-based neuroprosthetics.

Integrated biocircuits: engineering functional multicellular circuits and devices

NASA Astrophysics Data System (ADS)

Prox, Jordan; Smith, Tory; Holl, Chad; Chehade, Nick; Guo, Liang

2018-04-01

Objective. Implantable neurotechnologies have revolutionized neuromodulatory medicine for treating the dysfunction of diseased neural circuitry. However, challenges with biocompatibility and lack of full control over neural network communication and function limits the potential to create more stable and robust neuromodulation devices. Thus, we propose a platform technology of implantable and programmable cellular systems, namely Integrated Biocircuits, which use only cells as the functional components of the device. Approach. We envision the foundational principles for this concept begins with novel in vitro platforms used for the study and reconstruction of cellular circuitry. Additionally, recent advancements in organoid and 3D culture systems account for microenvironment factors of cytoarchitecture to construct multicellular circuits as they are normally formed in the brain. We explore the current state of the art of these platforms to provide knowledge of their advancements in circuit fabrication and identify the current biological principles that could be applied in designing integrated biocircuit devices. Main results. We have highlighted the exemplary methodologies and techniques of in vitro circuit fabrication and propose the integration of selected controllable parameters, which would be required in creating suitable biodevices. Significance. We provide our perspective and propose new insights into the future of neuromodulaion devices within the scope of living cellular systems that can be applied in designing more reliable and biocompatible stimulation-based neuroprosthetics.

Laser system for testing radiation imaging detector circuits

NASA Astrophysics Data System (ADS)

Zubrzycka, Weronika; Kasinski, Krzysztof

2015-09-01

Performance and functionality of radiation imaging detector circuits in charge and position measurement systems need to meet tight requirements. It is therefore necessary to thoroughly test sensors as well as read-out electronics. The major disadvantages of using radioactive sources or particle beams for testing are high financial expenses and limited accessibility. As an alternative short pulses of well-focused laser beam are often used for preliminary tests. There are number of laser-based devices available on the market, but very often their applicability in this field is limited. This paper describes concept, design and validation of laser system for testing silicon sensor based radiation imaging detector circuits. The emphasis is put on keeping overall costs low while achieving all required goals: mobility, flexible parameters, remote control and possibility of carrying out automated tests. The main part of the developed device is an optical pick-up unit (OPU) used in optical disc drives. The hardware includes FPGA-controlled circuits for laser positioning in 2 dimensions (horizontal and vertical), precision timing (frequency and number) and amplitude (diode current) of short ns-scale (3.2 ns) light pulses. The system is controlled via USB interface by a dedicated LabVIEW-based application enabling full manual or semi-automated test procedures.

Ambient temperature cadmium zinc telluride radiation detector and amplifier circuit

DOEpatents

McQuaid, J.H.; Lavietes, A.D.

1998-05-26

A low noise, low power consumption, compact, ambient temperature signal amplifier for a Cadmium Zinc Telluride (CZT) radiation detector is disclosed. The amplifier can be used within a larger system (e.g., including a multi-channel analyzer) to allow isotopic analysis of radionuclides in the field. In one embodiment, the circuit stages of the low power, low noise amplifier are constructed using integrated circuit (IC) amplifiers , rather than discrete components, and include a very low noise, high gain, high bandwidth dual part preamplification stage, an amplification stage, and an filter stage. The low noise, low power consumption, compact, ambient temperature amplifier enables the CZT detector to achieve both the efficiency required to determine the presence of radionuclides and the resolution necessary to perform isotopic analysis to perform nuclear material identification. The present low noise, low power, compact, ambient temperature amplifier enables a CZT detector to achieve resolution of less than 3% full width at half maximum at 122 keV for a Cobalt-57 isotope source. By using IC circuits and using only a single 12 volt supply and ground, the novel amplifier provides significant power savings and is well suited for prolonged portable in-field use and does not require heavy, bulky power supply components. 9 figs.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Alderfer, R.R.; Futa, P.W.

This patent describes a fuel system for an engine having a filter through which fuel from a pump passes to a regulator in response to an operator input. The regulator controls the flow of fuel presented to a combustion chamber in the engine, the regulator having a feedback apparatus to provide an operator with a signal indicative of the fuel supplied to the combustion chamber. It comprises: bypass means having a housing with a chamber therein, the chamber having an entrance port connected to the pump and an exit port connected to the regulator; piston means located in the chambermore » for separating the entrance port from the exit port, the piston having a face with a projection extending therefrom; stop means located in the chamber; resilient means located is the chamber for urging the piston means toward the stop means to prevent the flow of fuel from the pump through the housing to the regulator; and indicator means having a body retained in the housing with a first end which extends through the housing into the from a full-open position at which the closed circuit is fully opened to a full-closed position at which the closed circuit is fully blocked; ratio detecting means which detects the speed reduction ratio to find if the speed reduction ratio becomes substantially 1; and valve position detecting means which detects position of the direct clutch valve to find if the direct clutch valve is moved to a slight-open position at which the closed circuit is slightly opened.« less

Method and apparatus for enhancing microchannel plate data

DOEpatents

Thoe, R.S.

1983-10-24

A method and apparatus for determining centroid channel locations are disclosed for use in a system activated by one or more multichannel plates and including a linear diode array providing channels of information 1, 2, ...,n, ..., N containing signal amplitudes A/sub n/. A source of analog A/sub n/ signals, and a source of digital clock signals n, are provided. Non-zero A/sub n/ values are detected in a discriminator. A digital signal representing p, the value of n immediately preceding that whereat A/sub n/ takes its first non-zero value, is generated in a scaler. The analog A/sub n/ signals are converted to digital in an analog to digital converter. The digital A/sub n/ signals are added to produce a digital ..sigma..A/sub n/ signal in a full adder. Digital 1, 2, ..., m signals representing the number of non-zero A/sub n/ are produced by a discriminator pulse counter. Digital signals representing 1 A/sub p+1/, 2 A/sub p+2/, ..., m A/sub p+m/ are produced by pairwise multiplication in multiplier. These signal are added in multiplier summer to produce a digital ..sigma..nA/sub n/ - p..sigma..A/sub n/ signal. This signal is divided by the digital ..sigma..A/sub n/ signal in divider to provide a digital (..sigma..nA/sub n//..sigma..A/sub n/) -p signal. Finally, this last signal is added to the digital p signal in an offset summer to provide ..sigma..nA/sub n//..sigma..A/sub n/, the centroid channel locations.

Low-temperature crack-free Si3N4 nonlinear photonic circuits for CMOS-compatible optoelectronic co-integration

NASA Astrophysics Data System (ADS)

Casale, Marco; Kerdiles, Sebastien; Brianceau, Pierre; Hugues, Vincent; El Dirani, Houssein; Sciancalepore, Corrado

2017-02-01

In this communication, authors report for the first time on the fabrication and testing of Si3N4 non-linear photonic circuits for CMOS-compatible monolithic co-integration with silicon-based optoelectronics. In particular, a novel process has been developed to fabricate low-loss crack-free Si3N4 750-nm-thick films for Kerr-based nonlinear functions featuring full thermal budget compatibility with existing Silicon photonics and front-end Si optoelectronics. Briefly, differently from previous and state-of-the-art works, our nonlinear nitride-based platform has been realized without resorting to commonly-used high-temperature annealing ( 1200°C) of the film and its silica upper-cladding used to break N-H bonds otherwise causing absorption in the C-band and destroying its nonlinear functionality. Furthermore, no complex and fabrication-intolerant Damascene process - as recently reported earlier this year - aimed at controlling cracks generated in thick tensile-strained Si3N4 films has been used as well. Instead, a tailored Si3N4 multiple-step film deposition in 200-mm LPCVD-based reactor and subsequent low-temperature (400°C) PECVD oxide encapsulation have been used to fabricate the nonlinear micro-resonant circuits aiming at generating optical frequency combs via optical parametric oscillators (OPOs), thus allowing the monolithic co-integration of such nonlinear functions on existing CMOS-compatible optoelectronics, for both active and passive components such as, for instance, silicon modulators and wavelength (de-)multiplexers. Experimental evidence based on wafer-level statistics show nitride-based 112-μm-radius ring resonators using such low-temperature crack-free nitride film exhibiting quality factors exceeding Q >3 x 105, thus paving the way to low-threshold power-efficient Kerr-based comb sources and dissipative temporal solitons in the C-band featuring full thermal processing compatibility with Si photonic integrated circuits (Si-PICs).

Design of the small pixel pitch ROIC

NASA Astrophysics Data System (ADS)

Liang, Qinghua; Jiang, Dazhao; Chen, Honglei; Zhai, Yongcheng; Gao, Lei; Ding, Ruijun

2014-11-01

Since the technology trend of the third generation IRFPA towards resolution enhancing has steadily progressed,the pixel pitch of IRFPA has been greatly reduced.A 640×512 readout integrated circuit(ROIC) of IRFPA with 15μm pixel pitch is presented in this paper.The 15μm pixel pitch ROIC design will face many challenges.As we all known,the integrating capacitor is a key performance parameter when considering pixel area,charge capacity and dynamic range,so we adopt the effective method of 2 by 2 pixels sharing an integrating capacitor to solve this problem.The input unit cell architecture will contain two paralleled sample and hold parts,which not only allow the FPA to be operated in full frame snapshot mode but also save relatively unit circuit area.Different applications need more matching input unit circuits. Because the dimension of 2×2 pixels is 30μm×30μm, an input stage based on direct injection (DI) which has medium injection ratio and small layout area is proved to be suitable for middle wave (MW) while BDI with three-transistor cascode amplifier for long wave(LW). By adopting the 0.35μm 2P4M mixed signal process, the circuit architecture can make the effective charge capacity of 7.8Me- per pixel with 2.2V output range for MW and 7.3 Me- per pixel with 2.6V output range for LW. According to the simulation results, this circuit works well under 5V power supply and achieves less than 0.1% nonlinearity.

Understanding in an instant: neurophysiological evidence for mechanistic language circuits in the brain.

PubMed

Pulvermüller, Friedemann; Shtyrov, Yury; Hauk, Olaf

2009-08-01

How long does it take the human mind to grasp the idea when hearing or reading a sentence? Neurophysiological methods looking directly at the time course of brain activity indexes of comprehension are critical for finding the answer to this question. As the dominant cognitive approaches, models of serial/cascaded and parallel processing, make conflicting predictions on the time course of psycholinguistic information access, they can be tested using neurophysiological brain activation recorded in MEG and EEG experiments. Seriality and cascading of lexical, semantic and syntactic processes receives support from late (latency approximately 1/2s) sequential neurophysiological responses, especially N400 and P600. However, parallelism is substantiated by early near-simultaneous brain indexes of a range of psycholinguistic processes, up to the level of semantic access and context integration, emerging already 100-250ms after critical stimulus information is present. Crucially, however, there are reliable latency differences of 20-50ms between early cortical area activations reflecting lexical, semantic and syntactic processes, which are left unexplained by current serial and parallel brain models of language. We here offer a mechanistic model grounded in cortical nerve cell circuits that builds upon neuroanatomical and neurophysiological knowledge and explains both near-simultaneous activations and fine-grained delays. A key concept is that of discrete distributed cortical circuits with specific inter-area topographies. The full activation, or ignition, of specifically distributed binding circuits explains the near-simultaneity of early neurophysiological indexes of lexical, syntactic and semantic processing. Activity spreading within circuits determined by between-area conduction delays accounts for comprehension-related regional activation differences in the millisecond range.

Neural mechanism of optimal limb coordination in crustacean swimming

PubMed Central

Zhang, Calvin; Guy, Robert D.; Mulloney, Brian; Zhang, Qinghai; Lewis, Timothy J.

2014-01-01

A fundamental challenge in neuroscience is to understand how biologically salient motor behaviors emerge from properties of the underlying neural circuits. Crayfish, krill, prawns, lobsters, and other long-tailed crustaceans swim by rhythmically moving limbs called swimmerets. Over the entire biological range of animal size and paddling frequency, movements of adjacent swimmerets maintain an approximate quarter-period phase difference with the more posterior limbs leading the cycle. We use a computational fluid dynamics model to show that this frequency-invariant stroke pattern is the most effective and mechanically efficient paddling rhythm across the full range of biologically relevant Reynolds numbers in crustacean swimming. We then show that the organization of the neural circuit underlying swimmeret coordination provides a robust mechanism for generating this stroke pattern. Specifically, the wave-like limb coordination emerges robustly from a combination of the half-center structure of the local central pattern generating circuits (CPGs) that drive the movements of each limb, the asymmetric network topology of the connections between local CPGs, and the phase response properties of the local CPGs, which we measure experimentally. Thus, the crustacean swimmeret system serves as a concrete example in which the architecture of a neural circuit leads to optimal behavior in a robust manner. Furthermore, we consider all possible connection topologies between local CPGs and show that the natural connectivity pattern generates the biomechanically optimal stroke pattern most robustly. Given the high metabolic cost of crustacean swimming, our results suggest that natural selection has pushed the swimmeret neural circuit toward a connection topology that produces optimal behavior. PMID:25201976

COMMUNICATION IN THE SPACE AGE, THE USE OF SATELLITES BY THE MASS MEDIA.

ERIC Educational Resources Information Center

United Nations Educational, Scientific, and Cultural Organization, Paris (France).

THE FULL IMPACT OF SATELLITE COMMUNICATION WILL BE REALIZED ONLY WHEN IT BECOMES FEASIBLE TO SPACECAST DIRECTLY INTO HOMES, FACILITATING INEXPENSIVE LONG-DISTANCE CALLS AND ENABLING CONFERENCES TO BE HELD VIA TELEPHONE AND CLOSED-CIRCUIT TELEVISION. BUSINESS TRAVEL WILL DIMINISH. SPACE COMMUNICATION, BY INCREASING THE FLOW OF INFORMATION AND ITS…

40 CFR 1037.525 - Special procedures for testing hybrid vehicles with power take-off.

Code of Federal Regulations, 2014 CFR

2014-07-01

... of this section to allow testing hybrid vehicles other than electric-battery hybrids, consistent with... model, use good engineering judgment to select the vehicle type with the maximum number of PTO circuits... as needed to stabilize the battery at a full state of charge. For electric hybrid vehicles, we...

Power Conditioning for MEMS-Based Waste Vibrational Energy Harvester

DTIC Science & Technology

2015-06-01

circuits ...........................................................................................18 Figure 18. Full-wave passive MOSFET rectifier...ABBREVIATIONS AC Alternative Current AlN Aluminum Nitride DC Direct Current LIA Lock-In Amplifier MEMS Microelectromechanical Systems MOSFET ...efficiency is achieved when input voltage is over 2–3 V [14]. Using metal-oxide-semiconductor field-effect transistors ( MOSFETs ) in a rectifier instead of

Architectures and Design for Next-Generation Hybrid Circuit/Packet Networks

NASA Astrophysics Data System (ADS)

Vadrevu, Sree Krishna Chaitanya

Internet traffic is increasing rapidly at an annual growth rate of 35% with aggregate traffic exceeding several Exabyte's per month. The traffic is also becoming heterogeneous in bandwidth and quality-of-service (QoS) requirements with growing popularity of cloud computing, video-on-demand (VoD), e-science, etc. Hybrid circuit/packet networks which can jointly support circuit and packet services along with the adoption of high-bit-rate transmission systems form an attractive solution to address the traffic growth. 10 Gbps and 40 Gbps transmission systems are widely deployed in telecom backbone networks such as Comcast, AT&T, etc., and network operators are considering migration to 100 Gbps and beyond. This dissertation proposes robust architectures, capacity migration strategies, and novel service frameworks for next-generation hybrid circuit/packet architectures. In this dissertation, we study two types of hybrid circuit/packet networks: a) IP-over-WDM networks, in which the packet (IP) network is overlaid on top of the circuit (optical WDM) network and b) Hybrid networks in which the circuit and packet networks are deployed side by side such as US DoE's ESnet. We investigate techniques to dynamically migrate capacity between the circuit and packet sections by exploiting traffic variations over a day, and our methods show that significant bandwidth savings can be obtained with improved reliability of services. Specifically, we investigate how idle backup circuit capacity can be used to support packet services in IP-over-WDM networks, and similarly, excess capacity in packet network to support circuit services in ESnet. Control schemes that enable our mechanisms are also discussed. In IP-over-WDM networks, with upcoming 100 Gbps and beyond, dedicated protection will induce significant under-utilization of backup resources. We investigate design strategies to loan idle circuit backup capacity to support IP/packet services. However, failure of backup circuits will preempt IP services routed over them, and thus it is important to ensure IP topology survivability to successfully re-route preempted IP services. Integer-linear-program (ILP) and heuristic solutions have been developed and network cost reduction up to 60% has been observed. In ESnet, we study loaning packet links to support circuit services. Mixed-line-rate (MLR) networks supporting 10/40/100 Gbps on the same fiber are becoming increasingly popular. Services that accept degradation in bandwidth, latency, jitter, etc. under failure scenarios for lower cost are known as degraded services. We study degradation in bandwidth for lower cost under failure scenarios, a concept called partial protection, in the context of MLR networks. We notice partial protection enables significant cost savings compared to full protection. To cope with traffic growth, network operators need to deploy equipment at periodic time intervals, and this is known as the multi-period planning and upgrade problem. We study three important multi-period planning approaches, namely incremental planning, all-period planning, and two-period planning with mixed line rates. Our approaches predict the network equipment that needs to be deployed optimally at which nodes and at which time periods in the network to meet QoS requirements.

Stretched Lens Array Squarerigger (SLASR) Technology Maturation

NASA Technical Reports Server (NTRS)

O'Neill, Mark; McDanal, A.J.; Howell, Joe; Lollar, Louis; Carrington, Connie; Hoppe, David; Piszczor, Michael; Suszuki, Nantel; Eskenazi, Michael; Aiken, Dan;

Monolithic integration of GMR sensors for standard CMOS-IC current sensing

NASA Astrophysics Data System (ADS)

De Marcellis, A.; Reig, C.; Cubells-Beltrán, M.-D.; Madrenas, J.; Santos, J. D.; Cardoso, S.; Freitas, P. P.

2017-09-01

In this work we report on the development of Giant Magnetoresistive (GMR) sensors for off-line current measurements in standard integrated circuits. An ASIC has been specifically designed and fabricated in the well-known AMS-0.35 μm CMOS technology, including the electronic circuitry for sensor interfacing. It implements an oscillating circuit performing a voltage-to-frequency conversion. Subsequently, a fully CMOS-compatible low temperature post-process has been applied for depositing the GMR sensing devices in a full-bridge configuration onto the buried current straps. Sensitivity and resolution of these sensors have been investigated achieving experimental results that show a detection sensitivity of about 100 Hz/mA, with a resolution of about 5 μA.

A simple sub-nanosecond ultraviolet light pulse generator with high repetition rate and peak power.

PubMed

Binh, P H; Trong, V D; Renucci, P; Marie, X

2013-08-01

We present a simple ultraviolet sub-nanosecond pulse generator using commercial ultraviolet light-emitting diodes with peak emission wavelengths of 290 nm, 318 nm, 338 nm, and 405 nm. The generator is based on step recovery diode, short-circuited transmission line, and current-shaping circuit. The narrowest pulses achieved have 630 ps full width at half maximum at repetition rate of 80 MHz. Optical pulse power in the range of several hundreds of microwatts depends on the applied bias voltage. The bias voltage dependences of the output optical pulse width and peak power are analysed and discussed. Compared to commercial UV sub-nanosecond generators, the proposed generator can produce much higher pulse repetition rate and peak power.

Flexible Microstrip Circuits for Superconducting Electronics

NASA Technical Reports Server (NTRS)

Chervenak, James; Mateo, Jennette

2013-01-01

Flexible circuits with superconducting wiring atop polyimide thin films are being studied to connect large numbers of wires between stages in cryogenic apparatus with low heat load. The feasibility of a full microstrip process, consisting of two layers of superconducting material separated by a thin dielectric layer on 5 mil (approximately 0.13 mm) Kapton sheets, where manageable residual stress remains in the polyimide film after processing, has been demonstrated. The goal is a 2-mil (approximately 0.051-mm) process using spin-on polyimide to take advantage of the smoother polyimide surface for achieving highquality metal films. Integration of microstrip wiring with this polyimide film may require high-temperature bakes to relax the stress in the polyimide film between metallization steps.

A simultaneous all-optical half/full-subtraction strategy using cascaded highly nonlinear fibers

NASA Astrophysics Data System (ADS)

Singh, Karamdeep; Kaur, Gurmeet; Singh, Maninder Lal

2018-02-01

Using non-linear effects such as cross-gain modulation (XGM) and cross-phase modulation (XPM) inside two highly non-linear fibres (HNLF) arranged in cascaded configuration, a simultaneous half/full-subtracter is proposed. The proposed simultaneous half/full-subtracter design is attractive due to several features such as input data pattern independence and usage of minimal number of non-linear elements i.e. HNLFs. Proof of concept simulations have been conducted at 100 Gbps rate, indicating fine performance, as extinction ratio (dB) > 6.28 dB and eye opening factors (EO) > 77.1072% are recorded for each implemented output. The proposed simultaneous half/full-subtracter can be used as a key component in all-optical information processing circuits.

Microcomputer control of infrared detector arrays used in direct imaging and in Fabry-Perot spectroscopy

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rossano, G.S.

1989-02-01

A microcomputer based data acquisition system has been developed for astronomical observing with two-dimensional infrared detector arrays operating at high pixel rates. The system is based on a 16-bit 8086/8087 microcomputer operating at 10 MHz. Data rates of up to 560,000 pixels/sec from arrays of up to 4096 elements are supported using the microcomputer system alone. A hardware co-adder the authors are developing permits data accumulation at rates of up to 1.67 million pixels/sec in both staring and chopped data acquisition modes. The system has been used for direct imaging and for data acquisition in a Fabry-Perot Spectrometer developed bymore » NRL. The hardware is operated using interactive software which supports the several available modes of data acquisition, and permits data display and reduction during observing sessions.« less

Power optimization in logic isomers

NASA Technical Reports Server (NTRS)

Panwar, Ramesh; Rennels, David; Alkalaj, Leon

1993-01-01

Logic isomers are labeled, 2-isomorphic graphs that implement the same logic function. Logic isomers may have significantly different power requirements even though they have the same number of transistors in the implementation. The power requirements of the isomers depend on the transition activity of the input signals. The power requirements of isomorphic graph isomers of n-input NAND and NOR gates are shown. Choosing the less power-consuming isomer instead of the others can yield significant power savings. Experimental results on a ripple-carry adder are presented to show that the implementation using the least power-consuming isomers requires approximately 10 percent less power than the implementation using the most power-consuming isomers. Simulations of other random logic designs also confirm that designs using less power-consuming isomers can reduce the logic power demand by approximately 10 percent as compared to designs using more power-consuming isomers.

SABRE, a 10-MV linear induction accelerator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Corely, J.P.; Alexander, J.A.; Pankuch, P.J.

SABRE (Sandia Accelerator and Beam Research Experiment) is a 10-MV, 250-kA, 40-ns linear induction accelerator. It was designed to be used in positive polarity output. Positive polarity accelerators are important for application to Sandia's ICF (Inertial Confinement Fusion) and LMF (Laboratory Microfusion Facility) program efforts. SABRE was built to allow a more detailed study of pulsed power issues associated with positive polarity output machines. MITL (Magnetically Insulated Transmission Line) voltage adder efficiency, extraction ion diode development, and ion beam transport and focusing. The SABRE design allows the system to operate in either positive polarity output for ion extraction applications ormore » negative polarity output for more conventional electron beam loads. Details of the design of SABRE and the results of initial machine performance in negative polarity operation are presented in this paper. 13 refs., 12 figs., 1 tab.« less

Designs of Optoelectronic Trinary Signed-Digit Multiplication by use of Joint Spatial Encodings and Optical Correlation

NASA Astrophysics Data System (ADS)

Cherri, Abdallah K.

1999-02-01

Trinary signed-digit (TSD) symbolic-substitution-based (SS-based) optical adders, which were recently proposed, are used as the basic modules for designing highly parallel optical multiplications by use of cascaded optical correlators. The proposed multiplications perform carry-free generation of the multiplication partial products of two words in constant time. Also, three different multiplication designs are presented, and new joint spatial encodings for the TSD numbers are introduced. The proposed joint spatial encodings allow one to reduce the SS computation rules involved in optical multiplication. In addition, the proposed joint spatial encodings increase the space bandwidth product of the spatial light modulators of the optical system. This increase is achieved by reduction of the numbers of pixels in the joint spatial encodings for the input TSD operands as well as reduction of the number of pixels used in the proposed matched spatial filters for the optical multipliers.

Designs of optoelectronic trinary signed-digit multiplication by use of joint spatial encodings and optical correlation.

PubMed

Cherri, A K

1999-02-10

Trinary signed-digit (TSD) symbolic-substitution-based (SS-based) optical adders, which were recently proposed, are used as the basic modules for designing highly parallel optical multiplications by use of cascaded optical correlators. The proposed multiplications perform carry-free generation of the multiplication partial products of two words in constant time. Also, three different multiplication designs are presented, and new joint spatial encodings for the TSD numbers are introduced. The proposed joint spatial encodings allow one to reduce the SS computation rules involved in optical multiplication. In addition, the proposed joint spatial encodings increase the space-bandwidth product of the spatial light modulators of the optical system. This increase is achieved by reduction of the numbers of pixels in the joint spatial encodings for the input TSD operands as well as reduction of the number of pixels used in the proposed matched spatial filters for the optical multipliers.

Repetitively Pulsed High Power RF Solid-State System

NASA Astrophysics Data System (ADS)

Bowman, Chris; Ziemba, Timothy; Miller, Kenneth E.; Prager, James; Quinley, Morgan

2017-10-01

Eagle Harbor Technologies, Inc. (EHT) is developing a low-cost, fully solid-state architecture for the generation of the RF frequencies and power levels necessary for plasma heating and diagnostic systems at validation platform experiments within the fusion science community. In Year 1 of this program, EHT has developed a solid-state RF system that combines an inductive adder, nonlinear transmission line (NLTL), and antenna into a single system that can be deployed at fusion science experiments. EHT has designed and optimized a lumped-element NLTL that will be suitable RF generation near the lower-hybrid frequency at the High Beta Tokamak (HBT) located at Columbia University. In Year 2, EHT will test this system at the Helicity Injected Torus at the University of Washington and HBT at Columbia. EHT will present results from Year 1 testing and optimization of the NLTL-based RF system. With support of DOE SBIR.

Vertical blind phase search for low-complexity carrier phase recovery of offset-QAM Nyquist WDM transmission

NASA Astrophysics Data System (ADS)

Lu, Jianing; Fu, Songnian; Tang, Haoyuan; Xiang, Meng; Tang, Ming; Liu, Deming

2017-01-01

Low complexity carrier phase recovery (CPR) scheme based on vertical blind phase search (V-BPS) for M-ary offset quadrature amplitude modulation (OQAM) is proposed and numerically verified. After investigating the constellations of both even and odd samples with respect to the phase noise, we identify that the CPR can be realized by measuring the verticality of constellation with respect to different test phase angles. Then measurement without multiplication in the complex plane is found with low complexity. Furthermore, a two-stage configuration is put forward to further reduce the computational complexity (CC). Compared with our recently proposed modified blind phase search (M-BPS) algorithm, the proposed algorithm shows comparable tolerance of phase noise, but reduces the CC by a factor of 3.81 (or 3.05) in the form of multipliers (or adders), taking the CPR of 16-OQAM into account.

Quantum memristor in a superconducting circuit

NASA Astrophysics Data System (ADS)

Salmilehto, Juha; Sanz, Mikel; di Ventra, Massimiliano; Solano, Enrique

Memristors, resistive elements that retain information of their past, have garnered interest due to their paradigm-changing potential in information processing and electronics. The emergent hysteretic behaviour allows for novel architectural applications and has recently been classically demonstrated in a simplified superconducting setup using the phase-dependent conductance in the tunnel-junction-microscopic model. In this contribution, we present a truly quantum model for a memristor constructed using established elements and techniques in superconducting nanoelectronics, and explore the parameters for feasible operation as well as refine the methods for quantifying the memory retention. In particular, the memristive behaviour is shown to arise from quasiparticle-induced tunneling in the full dissipative model and can be observed in the phase-driven tunneling current. The relevant hysteretic behaviour should be observable using current state-of-the-art measurements for detecting quasiparticle excitations. Our theoretical findings constitute the first quantum memristor in a superconducting circuit and act as the starting point for designing further circuit elements that have non-Markovian characteristics The authors acknowledge support from the CCQED EU project and the Finnish Cultural Foundation.

Carbon Nanotube Self-Gating Diode and Application in Integrated Circuits.

PubMed

Si, Jia; Liu, Lijun; Wang, Fanglin; Zhang, Zhiyong; Peng, Lian-Mao

2016-07-26

A nano self-gating diode (SGD) based on nanoscale semiconducting material is proposed, simulated, and realized on semiconducting carbon nanotubes (CNTs) through a doping-free fabrication process. The relationships between the performance and material/structural parameters of the SGD are explored through numerical simulation and verified by experiment results. Based on these results, performance optimization strategy is outlined, and high performance CNT SGDs are fabricated and demonstrated to surpass other published CNT diodes. In particular the CNT SGD exhibits high rectifier factor of up to 1.4 × 10(6) while retains large on-state current. Benefiting from high yield and stability, CNT SGDs are used for constructing logic and analog integrated circuits. Two kinds of basic digital gates (AND and OR) have been realized on chip through using CNT SGDs and on-chip Ti wire resistances, and a full wave rectifier circuit has been demonstrated through using two CNT SGDs. Although demonstrated here using CNT SGDs, this device structure may in principle be implemented using other semiconducting nanomaterials, to provide ideas and building blocks for electronic applications based on nanoscale materials.

Heat Coulomb blockade of one ballistic channel

NASA Astrophysics Data System (ADS)

Sivre, E.; Anthore, A.; Parmentier, F. D.; Cavanna, A.; Gennser, U.; Ouerghi, A.; Jin, Y.; Pierre, F.

2018-02-01

Quantum mechanics and Coulomb interaction dictate the behaviour of small circuits. The thermal implications cover fundamental topics from quantum control of heat to quantum thermodynamics, with prospects of novel thermal machines and an ineluctably growing influence on nanocircuit engineering. Experimentally, the rare observations thus far include the universal thermal conductance quantum and heat interferometry. However, evidence for many-body thermal effects paving the way to markedly different heat and electrical behaviours in quantum circuits remains wanting. Here we report on the observation of the Coulomb blockade of electronic heat flow from a small metallic circuit node, beyond the widespread Wiedemann-Franz law paradigm. We demonstrate this thermal many-body phenomenon for perfect (ballistic) conduction channels to the node, where it amounts to the universal suppression of precisely one quantum of conductance for the transport of heat, but none for electricity. The inter-channel correlations that give rise to such selective heat current reduction emerge from local charge conservation, in the floating node over the full thermal frequency range (<~temperature × kB/h). This observation establishes the different nature of the quantum laws for thermal transport in nanocircuits.

Board Saver for Use with Developmental FPGAs

NASA Technical Reports Server (NTRS)

Berkun, Andrew

2009-01-01

A device denoted a board saver has been developed as a means of reducing wear and tear of a printed-circuit board onto which an antifuse field programmable gate array (FPGA) is to be eventually soldered permanently after a number of design iterations. The need for the board saver or a similar device arises because (1) antifuse-FPGA design iterations are common and (2) repeated soldering and unsoldering of FPGAs on the printed-circuit board to accommodate design iterations can wear out the printed-circuit board. The board saver is basically a solderable/unsolderable FPGA receptacle that is installed temporarily on the printed-circuit board. The board saver is, more specifically, a smaller, square-ring-shaped, printed-circuit board (see figure) that contains half via holes one for each contact pad along its periphery. As initially fabricated, the board saver is a wider ring containing full via holes, but then it is milled along its outer edges, cutting the via holes in half and laterally exposing their interiors. The board saver is positioned in registration with the designated FPGA footprint and each via hole is soldered to the outer portion of the corresponding FPGA contact pad on the first-mentioned printed-circuit board. The via-hole/contact joints can be inspected visually and can be easily unsoldered later. The square hole in the middle of the board saver is sized to accommodate the FPGA, and the thickness of the board saver is the same as that of the FPGA. Hence, when a non-final FPGA is placed in the square hole, the combination of the non-final FPGA and the board saver occupy no more area and thickness than would a final FPGA soldered directly into its designated position on the first-mentioned circuit board. The contact leads of a non-final FPGA are not bent and are soldered, at the top of the board saver, to the corresponding via holes. A non-final FPGA can readily be unsoldered from the board saver and replaced by another one. Once the final FPGA design has been determined, the board saver can be unsoldered from the contact pads on the first-mentioned printed-circuit board and replaced by the final FPGA.

Characterization and modelling of a microstrip line loaded with complementary split-ring resonators (CSRRs) and its application to highpass filters

NASA Astrophysics Data System (ADS)

Li, C.; Li, Fang

2007-06-01

A method to characterize and model a microstrip line coupled with complementary split-ring resonators (CSRRs) is investigated. The detailed parameter extraction approach based on three characteristic frequencies is presented. Good agreement between the results of the equivalent circuit model and the full wave simulations supports the effectiveness of the proposed modelling methodology. In particular, it is found that the shunt capacitance in the equivalent circuit has a negative value which appears to contradict the general physical perception. The physical rationality of the problem is discussed and justified. It is found that the negative capacitance is a natural part required to approximate more closely the distributed nature of the CSRR-loaded microstrip line and the whole equivalent circuit still satisfies Foster's reactance theorem. To extract the effective permittivity of the CSRR-loaded microstrip, the dielectric window concept and the effective medium theory are both applied. Both their results show the negative permittivity at the vicinity of the resonance. Finally, the application of the CSRRs in microstip highpass filters is presented to highlight the unique features of the CSRRs and the validity of their equivalent circuit descriptions. Compared with conventional structures, the proposed highpass filters not only have via free structure but also exhibit extremely steep out-of-band rejection. This may lead to useful applications.

Plasticity of Intact Rubral Projections Mediates Spontaneous Recovery of Function after Corticospinal Tract Injury

PubMed Central

Siegel, Chad S.; Fink, Kathren L.; Strittmatter, Stephen M.

2015-01-01

Axons in the adult CNS fail to regenerate after injury, and therefore recovery from spinal cord injury (SCI) is limited. Although full recovery is rare, a modest degree of spontaneous recovery is observed consistently in a broad range of clinical and nonclinical situations. To define the mechanisms mediating spontaneous recovery of function after incomplete SCI, we created bilaterally complete medullary corticospinal tract lesions in adult mice, eliminating a crucial pathway for voluntary skilled movement. Anatomic and pharmacogenetic tools were used to identify the pathways driving spontaneous functional recovery in wild-type and plasticity-sensitized mice lacking Nogo receptor 1. We found that plasticity-sensitized mice recovered 50% of normal skilled locomotor function within 5 weeks of lesion. This significant, yet incomplete, spontaneous recovery was accompanied by extensive sprouting of intact rubrofugal and rubrospinal projections with the emergence of a de novo circuit between the red nucleus and the nucleus raphe magnus. Transient silencing of this rubro–raphe circuit in vivo via activation of the inhibitory DREADD (designer receptor exclusively activated by designer drugs) receptor hM4di abrogated spontaneous functional recovery. These data highlight the pivotal role of uninjured motor circuit plasticity in supporting functional recovery after trauma, and support a focus of experimental strategies on enhancing intact circuit rearrangement to promote functional recovery after SCI. PMID:25632122

Performance of in-pixel circuits for photon counting arrays (PCAs) based on polycrystalline silicon TFTs.

PubMed

Liang, Albert K; Koniczek, Martin; Antonuk, Larry E; El-Mohri, Youcef; Zhao, Qihua; Street, Robert A; Lu, Jeng Ping

2016-03-07

Photon counting arrays (PCAs), defined as pixelated imagers which measure the absorbed energy of x-ray photons individually and record this information digitally, are of increasing clinical interest. A number of PCA prototypes with a 1 mm pixel-to-pixel pitch have recently been fabricated with polycrystalline silicon (poly-Si)-a thin-film technology capable of creating monolithic imagers of a size commensurate with human anatomy. In this study, analog and digital simulation frameworks were developed to provide insight into the influence of individual poly-Si transistors on pixel circuit performance-information that is not readily available through empirical means. The simulation frameworks were used to characterize the circuit designs employed in the prototypes. The analog framework, which determines the noise produced by individual transistors, was used to estimate energy resolution, as well as to identify which transistors contribute the most noise. The digital framework, which analyzes how well circuits function in the presence of significant variations in transistor properties, was used to estimate how fast a circuit can produce an output (referred to as output count rate). In addition, an algorithm was developed and used to estimate the minimum pixel pitch that could be achieved for the pixel circuits of the current prototypes. The simulation frameworks predict that the analog component of the PCA prototypes could have energy resolution as low as 8.9% full width at half maximum (FWHM) at 70 keV; and the digital components should work well even in the presence of significant thin-film transistor (TFT) variations, with the fastest component having output count rates as high as 3 MHz. Finally, based on conceivable improvements in the underlying fabrication process, the algorithm predicts that the 1 mm pitch of the current PCA prototypes could be reduced significantly, potentially to between ~240 and 290 μm.

A self-powered piezoelectric energy harvesting interface circuit with efficiency-enhanced P-SSHI rectifier

NASA Astrophysics Data System (ADS)

Liu, Lianxi; Pang, Yanbo; Yuan, Wenzhi; Zhu, Zhangming; Yang, Yintang

2018-04-01

The key to self-powered technique is initiative to harvest energy from the surrounding environment. Harvesting energy from an ambient vibration source utilizing piezoelectrics emerged as a popular method. Efficient interface circuits become the main limitations of existing energy harvesting techniques. In this paper, an interface circuit for piezoelectric energy harvesting is presented. An active full bridge rectifier is adopted to improve the power efficiency by reducing the conduction loss on the rectifying path. A parallel synchronized switch harvesting on inductor (P-SSHI) technique is used to improve the power extraction capability from piezoelectric harvester, thereby trying to reach the theoretical maximum output power. An intermittent power management unit (IPMU) and an output capacitor-less low drop regulator (LDO) are also introduced. Active diodes (AD) instead of traditional passive ones are used to reduce the voltage loss over the rectifier, which results in a good power efficiency. The IPMU with hysteresis comparator ensures the interface circuit has a large transient output power by limiting the output voltage ranges from 2.2 to 2 V. The design is fabricated in a SMIC 0.18 μm CMOS technology. Simulation results show that the flipping efficiency of the P-SSHI circuit is over 80% with an off-chip inductor value of 820 μH. The output power the proposed rectifier can obtain is 44.4 μW, which is 6.7× improvement compared to the maximum output power of a traditional rectifier. Both the active diodes and the P-SSHI help to improve the output power of the proposed rectifier. LDO outputs a voltage of 1.8 V with the maximum 90% power efficiency. The proposed P-SSHI rectifier interface circuit can be self-powered without the need for additional power supply. Project supported by the National Natural Science Foundation of China (Nos. 61574103, U1709218) and the Key Research and Development Program of Shaanxi Province (No. 2017ZDXM-GY-006).

Transient Negative Optical Nonlinearity of Indium Oxide Nanorod Arrays in the Full-Visible Range

DOE PAGES

Guo, Peijun; Chang, Robert P. H.; Schaller, Richard D.

2017-06-09

Dynamic control of the optical response of materials at visible wavelengths is key to future metamaterials and photonic integrated circuits. Here we demonstrate large amplitude, negative optical nonlinearity (Δ n from -0.05 to -0.09) of indium oxide nanorod arrays in the full-visible range. We experimentally quantify and theoretically calculate the optical nonlinearity, which arises from the modifications of interband optical transitions. Furthermore, the approach towards negative optical nonlinearity can be generalized to other transparent semiconductors and opens door to reconfigurable, sub-wavelength optical components.

IP Network Design and Implementation for the Caltech-USGS Element of TriNet

NASA Astrophysics Data System (ADS)

Johnson, M. L.; Busby, R.; Watkins, M.; Schwarz, S.; Hauksson, E.

2001-12-01

The new seismic network IP numbering scheme for the Caltech-USGS element of TriNet is designed to provide emergency response plans for computer outages and/or telemetry circuit failures so that data acquisition may continue with minimal interruption. IP numbers from the seismic stations through the Caltech acquisition machines are numbered using private, non-routable IP addresses, which allows the network administrator to create redundancy in the network design, more freedom in choosing IP numbers, and uniformity in the LAN and WAN network addressing. The network scheme used by the Caltech-USGS element of TriNet is designed to create redundancy and load sharing over three or more T1 circuits. A T1 circuit can support 80 dataloggers sending data at a design rate of 19.2 kbps or 120 dataloggers transmitting at a nominal rate of 12.8 kbps. During a circuit detour, the 80 dataloggers on the failed T1 are equally divided between the remaining two circuits. This increases the loads on the remaining two circuits to 120 dataloggers, which is the maximum load each T1 can handle at the nominal rate. Each T1 circuit has a router interface onto a LAN at Caltech with an independent subnet address. Some devices, such as Solaris computers, allow a single interface to be numbered with several IP addresses, a so called "multinetted" interface. This allows the central acquisition computers to appear with distinct addresses that are routable via different T1 circuits, but simplifies the physical cables between devices. We identify these T1 circuits as T1-1, T1-2, and T1-3. At the remote end, each Frame Relay Access Device (FRAD) and connected datalogger(s) is a subnetted LAN. The numbering is arranged so the second octet in the LAN IP address of the FRAD and datalogger identify the datalogger's primary and alternate T1 circuits. For example; a LAN with an IP address of 10.12.0.0/24 has T1-1 as its primary T1, and T1-2 as its alternate circuit. Stations with this number scheme are sometimes referred to as group "12". LANs with IP addresses of 10.23.0.0/24 have T1-2 as the primary circuit, and T1-3 as the alternate circuit. Static routes on the acquisition system are used to direct traffic through the primary T1. The network can operate in one of three modes. The most common and desirable mode is "normal", where all three T1's are operational and Caltech has both a primary and secondary central acquisition system running. The second mode is a "failover", where the primary acquisition system is down (due to maintenance or failure) and the secondary acquisition system assumes the primary role. This includes sending acknowledgments to dataloggers and multicasts to the rest of the network. The third mode is a circuit detour. The port numbers on the central acquisition system for the dataloggers on the failed T1 are changed to match the auxiliary ports on the dataloggers. This allows for the auxiliary ports on the dataloggers to receive acknowledgements from the acquiring system through the detoured circuit. The static routes on the system are changed to go through the detoured circuit as specified by the group's IP numbers. At this point the two working T1's will be running at full capacity but the data acquisition will continue with minimal interruption while the third T1 is being restored. The primary acquisition computer continues to listen for data on the failed T1 should things improve spontaneously.

Restructurable VLSI Program

DTIC Science & Technology

1981-03-31

logic testing element and a concomitant testability criterion ideally suited to dynamic circuit applications and appro- priate for automatic computer...making connections automatically . PF is an experimental feature which provides users with only four different chip sizes (full, half, quarter, and eighth...initial solution is found constructively which is improved by pair-wise swapping. Results show, however, that the constructive initial sorter , which

Harvesting the Full Potential of Photons with Organic Solar Cells.

PubMed

Ran, Niva A; Love, John A; Takacs, Christopher J; Sadhanala, Aditya; Beavers, Justin K; Collins, Samuel D; Huang, Ye; Wang, Ming; Friend, Richard H; Bazan, Guillermo C; Nguyen, Thuc-Quyen

2016-02-17

A low-bandgap polymer:fullerene blend that has significantly reduced energetic losses from photon absorption to VOC is described. The charge-transfer state and polymer singlet are of nearly equal energy, yet the short-circuit current still reaches 14 mA cm(-2). © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

24 CFR 3280.804 - Disconnecting means and branch-circuit protective equipment.

Code of Federal Regulations, 2013 CFR

2013-04-01

... the blank space. (k) When a home is provided with installed service equipment, a single disconnecting... closet entry if the location is such that a clear space of 6 inches to easily ignitable materials is... its full open position (at least 90 degrees). A clear working space at least 30 inches wide and 30...

24 CFR 3280.804 - Disconnecting means and branch-circuit protective equipment.

Code of Federal Regulations, 2012 CFR

2012-04-01

... the blank space. (k) When a home is provided with installed service equipment, a single disconnecting... closet entry if the location is such that a clear space of 6 inches to easily ignitable materials is... its full open position (at least 90 degrees). A clear working space at least 30 inches wide and 30...

Telemetry advances in data compression and channel coding

NASA Technical Reports Server (NTRS)

Miller, Warner H.; Morakis, James C.; Yeh, Pen-Shu

1990-01-01

Addressed in this paper is the dependence of telecommunication channel, forward error correcting coding and source data compression coding on integrated circuit technology. Emphasis is placed on real time high speed Reed Solomon (RS) decoding using full custom VLSI technology. Performance curves of NASA's standard channel coder and a proposed standard lossless data compression coder are presented.

Block QCA Fault-Tolerant Logic Gates

NASA Technical Reports Server (NTRS)

Firjany, Amir; Toomarian, Nikzad; Modarres, Katayoon

2003-01-01

Suitably patterned arrays (blocks) of quantum-dot cellular automata (QCA) have been proposed as fault-tolerant universal logic gates. These block QCA gates could be used to realize the potential of QCA for further miniaturization, reduction of power consumption, increase in switching speed, and increased degree of integration of very-large-scale integrated (VLSI) electronic circuits. The limitations of conventional VLSI circuitry, the basic principle of operation of QCA, and the potential advantages of QCA-based VLSI circuitry were described in several NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35; and Hybrid VLSI/QCA Architecture for Computing FFTs (NPO-20923), which follows this article. To recapitulate the principle of operation (greatly oversimplified because of the limitation on space available for this article): A quantum-dot cellular automata contains four quantum dots positioned at or between the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the quantummechanical sense) between neighboring dots within the cell. The Coulomb repulsion between the two electrons tends to make them occupy antipodal dots in the cell. For an isolated cell, there are two energetically equivalent arrangements (denoted polarization states) of the extra electrons. The cell polarization is used to encode binary information. Because the polarization of a nonisolated cell depends on Coulomb-repulsion interactions with neighboring cells, universal logic gates and binary wires could be constructed, in principle, by arraying QCA of suitable design in suitable patterns. Heretofore, researchers have recognized two major obstacles to realization of QCA-based logic gates: One is the need for (and the difficulty of attaining) operation of QCA circuitry at room temperature or, for that matter, at any temperature above a few Kelvins. It has been theorized that room-temperature operation could be made possible by constructing QCA as molecular-scale devices. However, in approaching the lower limit of miniaturization at the molecular level, it becomes increasingly imperative to overcome the second major obstacle, which is the need for (and the difficulty of attaining) high precision in the alignments of adjacent QCA in order to ensure the correct interactions among the quantum dots.

Symmetry boost of the fidelity of Shor factoring

NASA Astrophysics Data System (ADS)

Nam, Y. S.; Blümel, R.

2018-05-01

In Shor's algorithm quantum subroutines occur with the structure F U F-1 , where F is a unitary transform and U is performing a quantum computation. Examples are quantum adders and subunits of quantum modulo adders. In this paper we show, both analytically and numerically, that if, in analogy to spin echoes, F and F-1 can be implemented symmetrically when executing Shor's algorithm on actual, imperfect quantum hardware, such that F and F-1 have the same hardware errors, a symmetry boost in the fidelity of the combined F U F-1 quantum operation results when compared to the case in which the errors in F and F-1 are independently random. Running the complete gate-by-gate implemented Shor algorithm, we show that the symmetry-induced fidelity boost can be as large as a factor 4. While most of our analytical and numerical results concern the case of over- and under-rotation of controlled rotation gates, in the numerically accessible case of Shor's algorithm with a small number of qubits, we show explicitly that the symmetry boost is robust with respect to more general types of errors. While, expectedly, additional error types reduce the symmetry boost, we show explicitly, by implementing general off-diagonal SU (N ) errors (N =2 ,4 ,8 ), that the boost factor scales like a Lorentzian in δ /σ , where σ and δ are the error strengths of the diagonal over- and underrotation errors and the off-diagonal SU (N ) errors, respectively. The Lorentzian shape also shows that, while the boost factor may become small with increasing δ , it declines slowly (essentially like a power law) and is never completely erased. We also investigate the effect of diagonal nonunitary errors, which, in analogy to unitary errors, reduce but never erase the symmetry boost. Going beyond the case of small quantum processors, we present analytical scaling results that show that the symmetry boost persists in the practically interesting case of a large number of qubits. We illustrate this result explicitly for the case of Shor factoring of the semiprime RSA-1024, where, analytically, focusing on over- and underrotation errors, we obtain a boost factor of about 10. In addition, we provide a proof of the fidelity product formula, including its range of applicability.

Practical proof of CP element based design for 14nm node and beyond

NASA Astrophysics Data System (ADS)

Maruyama, Takashi; Takita, Hiroshi; Ikeno, Rimon; Osawa, Morimi; Kojima, Yoshinori; Sugatani, Shinji; Hoshino, Hiromi; Hino, Toshio; Ito, Masaru; Iizuka, Tetsuya; Komatsu, Satoshi; Ikeda, Makoto; Asada, Kunihiro

2013-03-01

To realize HVM (High Volume Manufacturing) with CP (Character Projection) based EBDW, the shot count reduction is the essential key. All device circuits should be composed with predefined character parts and we call this methodology "CP element based design". In our previous work, we presented following three concepts [2]. 1) Memory: We reported the prospects of affordability for the CP-stencil resource. 2) Logic cell: We adopted a multi-cell clustering approach in the physical synthesis. 3) Random interconnect: We proposed an ultra-regular layout scheme using fixed size wiring tiles containing repeated tracks and cutting points at the tile edges. In this paper, we will report the experimental proofs in these methodologies. In full chip layout, CP stencil resource management is critical key. From the MCC-POC (Proof of Concept) result [1], we assumed total available CP stencil resource as 9000um2. We should manage to layout all circuit macros within this restriction. Especially the issues in assignment of CP-stencil resource for the memory macros are the most important as they consume considerable degree of resource because of the various line-ups such as 1RW-, 2RW-SRAMs, Resister Files and ROM which require several varieties of large size peripheral circuits. Furthermore the memory macros typically take large area of more than 40% of die area in the forefront logic LSI products so that the shot count increase impact is serious. To realize CP-stencil resource saving we had constructed automatic CP analyzing system. We developed two types of extraction mode of simple division by block and layout repeatability recognition. By properly controlling these models based upon each peripheral circuit characteristics, we could minimize the consumption of CP stencil resources. The estimation for 14nm technology node had been performed based on the analysis of practical memory compiler. The required resource for memory macro is proved to be affordable value which is 60% of full CP stencil resource and wafer level converted shot count is proved to be the level which meets 100WPH throughput. In logic cell design, circuit performance verification result after the cell clustering has been estimated. The cell clustering by the acknowledgment of physical distance proved to owe large penalty mainly in the wiring length. To reduce this design penalty, we proposed CP cell clustering by the acknowledgment of logical distance. For shot-count reduction of random interconnect area design, we proposed a more structural routing architecture which consists of the track exchange and the via position arrangement. Putting these design approaches together, we can design CP stencils to hit the target throughput within the area constraint. From the analysis for other macros such as analog, I/O, and DUMMY, it has proved that we don't need special CP design approach than legacy pattern matching CP extraction. From all these experimental results we get good prospects to the reality of full CP element based layout.

Microfabricated ion trap array

DOEpatents

Blain, Matthew G [Albuquerque, NM; Fleming, James G [Albuquerque, NM

2006-12-26

A microfabricated ion trap array, comprising a plurality of ion traps having an inner radius of order one micron, can be fabricated using surface micromachining techniques and materials known to the integrated circuits manufacturing and microelectromechanical systems industries. Micromachining methods enable batch fabrication, reduced manufacturing costs, dimensional and positional precision, and monolithic integration of massive arrays of ion traps with microscale ion generation and detection devices. Massive arraying enables the microscale ion traps to retain the resolution, sensitivity, and mass range advantages necessary for high chemical selectivity. The reduced electrode voltage enables integration of the microfabricated ion trap array with on-chip circuit-based rf operation and detection electronics (i.e., cell phone electronics). Therefore, the full performance advantages of the microfabricated ion trap array can be realized in truly field portable, handheld microanalysis systems.

Sensitivity Challenge of Steep Transistors

NASA Astrophysics Data System (ADS)

Ilatikhameneh, Hesameddin; Ameen, Tarek A.; Chen, ChinYi; Klimeck, Gerhard; Rahman, Rajib

2018-04-01

Steep transistors are crucial in lowering power consumption of the integrated circuits. However, the difficulties in achieving steepness beyond the Boltzmann limit experimentally have hindered the fundamental challenges in application of these devices in integrated circuits. From a sensitivity perspective, an ideal switch should have a high sensitivity to the gate voltage and lower sensitivity to the device design parameters like oxide and body thicknesses. In this work, conventional tunnel-FET (TFET) and negative capacitance FET are shown to suffer from high sensitivity to device design parameters using full-band atomistic quantum transport simulations and analytical analysis. Although Dielectric Engineered (DE-) TFETs based on 2D materials show smaller sensitivity compared with the conventional TFETs, they have leakage issue. To mitigate this challenge, a novel DE-TFET design has been proposed and studied.

Method and apparatus for enhancing microchannel plate data

DOEpatents

Thoe, Robert S.

1987-01-01

A method and apparatus for determining centroid channel locations is disclosed for use in a system activated by one or more multichannel plates (16,18) and including a linear diode array (24) providing channels of information 1, 2, . . . , n, . . . , N containing signal amplitudes A.sub.n. A source of analog A.sub.n signals (40), and a source of digital clock signals n (48), are provided. Non-zero A.sub.n values are detected in a discriminator (42). A digital signal representing p, the value of n immediately preceding that whereat A.sub.n takes its first non-zero value, is generated in a scaler (50). The analog A.sub.n signals are converted to digital in an analog to digital converter (44). The digital A.sub.n signals are added to produce a digital .SIGMA.A.sub.n signal in a full adder (46). Digital 1, 2, . . . , m signals representing the number of non-zero A.sub.n are produced by a discriminator pulse counter (52). Digital signals representing 1 A.sub.p+ 1, 2 A.sub.p+2, . . . , m A.sub.p+m are produced by pairwise multiplication in multiplier (54). These signals are added in multiplier summer (56) to produce a digital .SIGMA.nA.sub.n -p.SIGMA.A.sub.n signal. This signal is divided by the digital .SIGMA.A.sub.n signal in divider (58) to provide a digital (.SIGMA.nA.sub.n /.SIGMA.A.sub.n) -p signal. Finally, this last signal is added to the digital p signal in an offset summer (60) to provide .SIGMA.nA.sub.n /.SIGMA.A.sub.n, the centroid channel locations.

The "E" Word

ERIC Educational Resources Information Center

Romano, Carlin

2006-01-01

This article presents the case of of Martin Zelnik v. Fashion Institute of Technology (FIT) et al. and the ruling of the U.S. Court of Appeals for the Second Circuit on the case. Zelnik served on the faculty of FIT from 1969 to 1999, retiring as a full professor of interior design. Zelnik applied for an emeritus status but was denied by FIT. The…

Speech Cases Turned Aside by High Court

ERIC Educational Resources Information Center

Walsh, Mark

2012-01-01

The U.S. Supreme Court declined without comment to take up two major appeals involving student free-speech rights on the Internet. One appeal encompassed two cases decided in favor of students last June by the full U.S. Court of Appeals for the 3rd Circuit, in Philadelphia. The other appeal stemmed from a decision by the U.S. Court of Appeals for…

24 CFR 3280.804 - Disconnecting means and branch-circuit protective equipment.

Code of Federal Regulations, 2014 CFR

2014-04-01

... ampere rating shall be marked on the blank space. (k) When a home is provided with installed service... permitted just inside a closet entry if the location is such that a clear space of 6 inches to easily... door can be extended to its full open position (at least 90 degrees). A clear working space at least 30...

Effect of Current and SOC on Round-Trip Energy Efficiency of a Lithium-Iron Phosphate (LiFePO4) Battery Pack (SAE Paper 2015-01-1186)

EPA Science Inventory

While equivalent circuit modeling is an effective way to model the performance and energy efficiency of automotive Li-ion batteries, in some applications it is more convenient to refer directly to round-trip energy efficiency. Energy efficiency of either cells or full packs is se...

Helping the Visually Impaired Student with Electronic Video Visual Aids.

ERIC Educational Resources Information Center

Visualtek, Inc., Santa Monica, CA.

THE FOLLOWING IS THE FULL TEXT OF THIS DOCUMENT: Video visual aids are Closed Circuit TV systems (CCTV's) which magnify print and enlarge it electronically upon a screen so partially sighted persons with some residual vision can read and write normal size print. These devices are in use around the world in homes, schools, industries and libraries,…

Modified timing module for Loran-C receiver

NASA Technical Reports Server (NTRS)

Lilley, R. W.

1983-01-01

Full hardware documentation is provided for the circuit card implementing the Loran-C timing loop, and the receiver event-mark and re-track functions. This documentation is to be combined with overall receiver drawings to form the as-built record for this device. Computer software to support this module is integrated with the remainder of the receiver software, in the LORPROM program.

Entanglement distribution schemes employing coherent photon-to-spin conversion in semiconductor quantum dot circuits

NASA Astrophysics Data System (ADS)

Gaudreau, Louis; Bogan, Alex; Korkusinski, Marek; Studenikin, Sergei; Austing, D. Guy; Sachrajda, Andrew S.

2017-09-01

Long distance entanglement distribution is an important problem for quantum information technologies to solve. Current optical schemes are known to have fundamental limitations. A coherent photon-to-spin interface built with quantum dots (QDs) in a direct bandgap semiconductor can provide a solution for efficient entanglement distribution. QD circuits offer integrated spin processing for full Bell state measurement (BSM) analysis and spin quantum memory. Crucially the photo-generated spins can be heralded by non-destructive charge detection techniques. We review current schemes to transfer a polarization-encoded state or a time-bin-encoded state of a photon to the state of a spin in a QD. The spin may be that of an electron or that of a hole. We describe adaptations of the original schemes to employ heavy holes which have a number of attractive properties including a g-factor that is tunable to zero for QDs in an appropriately oriented external magnetic field. We also introduce simple throughput scaling models to demonstrate the potential performance advantage of full BSM capability in a QD scheme, even when the quantum memory is imperfect, over optical schemes relying on linear optical elements and ensemble quantum memories.

Design of the control system for full-color LED display based on MSP430 MCU

NASA Astrophysics Data System (ADS)

Li, Xue; Xu, Hui-juan; Qin, Ling-ling; Zheng, Long-jiang

2013-08-01

The LED display incorporate the micro electronic technique, computer technology and information processing as a whole, it becomes the most preponderant of a new generation of display media with the advantages of bright in color, high dynamic range, high brightness and long operating life, etc. The LED display has been widely used in the bank, securities trading, highway signs, airport and advertising, etc. According to the display color, the LED display screen is divided into monochrome screen, double color display and full color display. With the diversification of the LED display's color and the ceaseless rise of the display demands, the LED display's drive circuit and control technology also get the corresponding progress and development. The earliest monochrome screen just displaying Chinese characters, simple character or digital, so the requirements of the controller are relatively low. With the widely used of the double color LED display, the performance of its controller will also increase. In recent years, the full color LED display with three primary colors of red, green, blue and grayscale display effect has been highly attention with its rich and colorful display effect. Every true color pixel includes three son pixels of red, green, blue, using the space colour mixture to realize the multicolor. The dynamic scanning control system of LED full-color display is designed based on MSP430 microcontroller technology of the low power consumption. The gray control technology of this system used the new method of pulse width modulation (PWM) and 19 games show principle are combining. This method in meet 256 level grayscale display conditions, improves the efficiency of the LED light device, and enhances the administrative levels feels of the image. Drive circuit used 1/8 scanning constant current drive mode, and make full use of the single chip microcomputer I/O mouth resources to complete the control. The system supports text, pictures display of 256 grayscale full-color LED screen.

Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

NASA Astrophysics Data System (ADS)

Geier, Michael

Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and symmetric threshold voltages. Additionally, a novel n-type doping procedure for SWCNT TFTs was also developed utilizing a solution-processed organometallic small molecule to demonstrate the first network top-gated n-type SWCNT TFTs. Lastly, new doping and encapsulation layers were incorporated to stabilize both p-type and n-type SWCNT TFT electronic properties, which enabled the fabrication of large-scale memory circuits. Employing these materials and processing advances has addressed many application specific barriers to commercialization. For instance, the first thin-film SWCNT complementary metal-oxide-semi-conductor (CMOS) logic devices are demonstrated with sub-nanowatt static power consumption and full rail-to-rail voltage transfer characteristics. With the introduction of a new n-type Rh-based molecular dopant, the first SWCNT TFTs are fabricated in top-gate geometries over large areas with high yield. Then by utilizing robust encapsulation methods, stable and uniform electronic performance of both p-type and n-type SWCNT TFTs has been achieved. Based on these complementary SWCNT TFTs, it is possible to simulate, design, and fabricate arrays of low-power static random access memory (SRAM) circuits, achieving large-scale integration for the first time based on solution-processed semiconductors. Together, this work provides a direct pathway for solution processable, large scale, power-efficient advanced integrated logic circuits and systems.

Superconducting quantum circuits at the surface code threshold for fault tolerance.

PubMed

Barends, R; Kelly, J; Megrant, A; Veitia, A; Sank, D; Jeffrey, E; White, T C; Mutus, J; Fowler, A G; Campbell, B; Chen, Y; Chen, Z; Chiaro, B; Dunsworth, A; Neill, C; O'Malley, P; Roushan, P; Vainsencher, A; Wenner, J; Korotkov, A N; Cleland, A N; Martinis, John M

2014-04-24

A quantum computer can solve hard problems, such as prime factoring, database searching and quantum simulation, at the cost of needing to protect fragile quantum states from error. Quantum error correction provides this protection by distributing a logical state among many physical quantum bits (qubits) by means of quantum entanglement. Superconductivity is a useful phenomenon in this regard, because it allows the construction of large quantum circuits and is compatible with microfabrication. For superconducting qubits, the surface code approach to quantum computing is a natural choice for error correction, because it uses only nearest-neighbour coupling and rapidly cycled entangling gates. The gate fidelity requirements are modest: the per-step fidelity threshold is only about 99 per cent. Here we demonstrate a universal set of logic gates in a superconducting multi-qubit processor, achieving an average single-qubit gate fidelity of 99.92 per cent and a two-qubit gate fidelity of up to 99.4 per cent. This places Josephson quantum computing at the fault-tolerance threshold for surface code error correction. Our quantum processor is a first step towards the surface code, using five qubits arranged in a linear array with nearest-neighbour coupling. As a further demonstration, we construct a five-qubit Greenberger-Horne-Zeilinger state using the complete circuit and full set of gates. The results demonstrate that Josephson quantum computing is a high-fidelity technology, with a clear path to scaling up to large-scale, fault-tolerant quantum circuits.

Thread-Like CMOS Logic Circuits Enabled by Reel-Processed Single-Walled Carbon Nanotube Transistors via Selective Doping.

PubMed

Heo, Jae Sang; Kim, Taehoon; Ban, Seok-Gyu; Kim, Daesik; Lee, Jun Ho; Jur, Jesse S; Kim, Myung-Gil; Kim, Yong-Hoon; Hong, Yongtaek; Park, Sung Kyu

2017-08-01

The realization of large-area electronics with full integration of 1D thread-like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread-like fiber electronic devices can be achieved using a simple reel-to-reel process, which is strongly required for low-cost and scalable manufacturing technology. Here, high-performance reel-processed complementary metal-oxide-semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical-doped single-walled carbon nanotube (SWCNT) transistors. With the introduction of selective n-type doping and a nonrelief photochemical patterning process, p- and n-type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high-performance and reliable thread-like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel-coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well-aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p- and n-type SWCNT transistors exhibit field-effect mobility of 4.03 and 2.15 cm 2 V -1 s -1 , respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High-voltage integrated active quenching circuit for single photon count rate up to 80 Mcounts/s.

PubMed

Acconcia, Giulia; Rech, Ivan; Gulinatti, Angelo; Ghioni, Massimo

2016-08-08

Single photon avalanche diodes (SPADs) have been subject to a fast improvement in recent years. In particular, custom technologies specifically developed to fabricate SPAD devices give the designer the freedom to pursue the best detector performance required by applications. A significant breakthrough in this field is represented by the recent introduction of a red enhanced SPAD (RE-SPAD) technology, capable of attaining a good photon detection efficiency in the near infrared range (e.g. 40% at a wavelength of 800 nm) while maintaining a remarkable timing resolution of about 100ps full width at half maximum. Being planar, the RE-SPAD custom technology opened the way to the development of SPAD arrays particularly suited for demanding applications in the field of life sciences. However, to achieve such excellent performance custom SPAD detectors must be operated with an external active quenching circuit (AQC) designed on purpose. Next steps toward the development of compact and practical multichannel systems will require a new generation of monolithically integrated AQC arrays. In this paper we present a new, fully integrated AQC fabricated in a high-voltage 0.18 µm CMOS technology able to provide quenching pulses up to 50 Volts with fast leading and trailing edges. Although specifically designed for optimal operation of RE-SPAD devices, the new AQC is quite versatile: it can be used with any SPAD detector, regardless its fabrication technology, reaching remarkable count rates up to 80 Mcounts/s and generating a photon detection pulse with a timing jitter as low as 119 ps full width at half maximum. The compact design of our circuit has been specifically laid out to make this IC a suitable building block for monolithically integrated AQC arrays.

Pulse excitation method for measurement of high frequency magnetic properties of large cores (abstract)

NASA Astrophysics Data System (ADS)

Hikosaka, Tomoyuki; Miyamoto, Masahiro; Yamada, Mamoru; Morita, Tadashi

1993-05-01

It is very important to obtain saturated magnetic properties from reverse saturation (full B-H curve) of ferromagnetic cores to design magnetic switches which are used in high power pulse generators. The magnetic switch is excited in the high frequency range (˜MHz). But, it is extremely difficult to measure full B-H curve of large toroidal cores of which diameter is some hundreds of mm, using the conventional ac excitation method at high frequency. The main reason is poor output ability of power source for core excitation. Therefore we have developed pulse excitation method to get high frequency magnetic properties. The measurement circuit has two sections. One is excitation part composed by charge transfer circuit. The others is reset part for adjustment initial point on direct B-H curve. The sample core is excited by sinusoidal voltage pulse expressed as 1-cos(2π ft). Excitation frequency f is decided by the constants of the elements of the charge transfer circuit. The change of magnetic flux density ΔB and magnetic field H are calculated, respectively, by measuring the induced voltage of search coil and magnetizing current. ΔB-H characteristics from reverse saturation of four different kinds of large cores were measured in frequency range from 50 kHz to 1 MHz. Core loss increases in proportion to Nth powers of the frequency, where the index N depends on each of cores. N is about 0.5 in case of winding ribbon cores, such as Fe-based amorphous, Co-based amorphous, and Finemet, but N is about 0.2 in case of the Ni-Zn ferrite.

Front-end Design and Characterization for the ν-Angra Nuclear Reactor Monitoring Detector

NASA Astrophysics Data System (ADS)

Dornelas, T. I.; Araújo, F. T. H.; Cerqueira, A. S.; Costa, J. A.; Nóbrega, R. A.

2016-07-01

The Neutrinos Angra (ν-Angra) Experiment aims to construct an antineutrinos detection device capable of monitoring the Angra dos Reis nuclear reactor activity. Nuclear reactors are intense sources of antineutrinos, and the thermal power released in the fission process is directly related to the flow rate of these particles. The antineutrinos energy spectrum also provides valuable information on the nuclear source isotopic composition. The proposed detector will be equipped with photomultipliers tubes (PMT) which will be readout by a custom Amplifier-Shaper-Discriminator circuit designed to condition its output signals to the acquisition modules to be digitized and processed by an FPGA. The readout circuit should be sensitive to single photoelectron signals, process fast signals, with a full-width-half-amplitude of about 5 ns, have a narrow enough output pulse width to detect both particles coming out from the inverse beta decay (bar nue+p → n + e+), and its output amplitude should be linear to the number of photoelectrons generated inside the PMT, used for energy estimation. In this work, some of the main PMT characteristics are measured and a new readout circuit is proposed, described and characterized.

High Performance Complementary Circuits Based on p-SnO and n-IGZO Thin-Film Transistors.

PubMed

Zhang, Jiawei; Yang, Jia; Li, Yunpeng; Wilson, Joshua; Ma, Xiaochen; Xin, Qian; Song, Aimin

2017-03-21

Oxide semiconductors are regarded as promising materials for large-area and/or flexible electronics. In this work, a ring oscillator based on n-type indium-gallium-zinc-oxide (IGZO) and p-type tin monoxide (SnO) is presented. The IGZO thin-film transistor (TFT) shows a linear mobility of 11.9 cm²/(V∙s) and a threshold voltage of 12.2 V. The SnO TFT exhibits a mobility of 0.51 cm²/(V∙s) and a threshold voltage of 20.1 V which is suitable for use with IGZO TFTs to form complementary circuits. At a supply voltage of 40 V, the complementary inverter shows a full output voltage swing and a gain of 24 with both TFTs having the same channel length/channel width ratio. The three-stage ring oscillator based on IGZO and SnO is able to operate at 2.63 kHz and the peak-to-peak oscillation amplitude reaches 36.1 V at a supply voltage of 40 V. The oxide-based complementary circuits, after further optimization of the operation voltage, may have wide applications in practical large-area flexible electronics.

High Performance Complementary Circuits Based on p-SnO and n-IGZO Thin-Film Transistors

PubMed Central

Zhang, Jiawei; Yang, Jia; Li, Yunpeng; Wilson, Joshua; Ma, Xiaochen; Xin, Qian; Song, Aimin

2017-01-01

Oxide semiconductors are regarded as promising materials for large-area and/or flexible electronics. In this work, a ring oscillator based on n-type indium-gallium-zinc-oxide (IGZO) and p-type tin monoxide (SnO) is presented. The IGZO thin-film transistor (TFT) shows a linear mobility of 11.9 cm2/(V∙s) and a threshold voltage of 12.2 V. The SnO TFT exhibits a mobility of 0.51 cm2/(V∙s) and a threshold voltage of 20.1 V which is suitable for use with IGZO TFTs to form complementary circuits. At a supply voltage of 40 V, the complementary inverter shows a full output voltage swing and a gain of 24 with both TFTs having the same channel length/channel width ratio. The three-stage ring oscillator based on IGZO and SnO is able to operate at 2.63 kHz and the peak-to-peak oscillation amplitude reaches 36.1 V at a supply voltage of 40 V. The oxide-based complementary circuits, after further optimization of the operation voltage, may have wide applications in practical large-area flexible electronics. PMID:28772679

NASA's Evolutionary Xenon Thruster (NEXT) Power Processing Unit (PPU) Capacitor Failure Root Cause Analysis

NASA Technical Reports Server (NTRS)

Soeder, James F.; Pinero, Luis; Schneidegger, Robert; Dunning, John; Birchenough, Art

2012-01-01

The NASA's Evolutionary Xenon Thruster (NEXT) project is developing an advanced ion propulsion system for future NASA missions for solar system exploration. A critical element of the propulsion system is the Power Processing Unit (PPU) which supplies regulated power to the key components of the thruster. The PPU contains six different power supplies including the beam, discharge, discharge heater, neutralizer, neutralizer heater, and accelerator supplies. The beam supply is the largest and processes up to 93+% of the power. The NEXT PPU had been operated for approximately 200+ hours and has experienced a series of three capacitor failures in the beam supply. The capacitors are in the same, nominally non-critical location the input filter capacitor to a full wave switching inverter. The three failures occurred after about 20, 30, and 135 hours of operation. This paper provides background on the NEXT PPU and the capacitor failures. It discusses the failure investigation approach, the beam supply power switching topology and its operating modes, capacitor characteristics and circuit testing. Finally, it identifies root cause of the failures to be the unusual confluence of circuit switching frequency, the physical layout of the power circuits, and the characteristics of the capacitor.

NASA's Evolutionary Xenon Thruster (NEXT) Power Processing Unit (PPU) Capacitor Failure Root Cause Analysis

NASA Technical Reports Server (NTRS)

Soeder, James F.; Scheidegger, Robert J.; Pinero, Luis R.; Birchenough, Arthur J.; Dunning, John W.

2012-01-01

The NASA s Evolutionary Xenon Thruster (NEXT) project is developing an advanced ion propulsion system for future NASA missions for solar system exploration. A critical element of the propulsion system is the Power Processing Unit (PPU) which supplies regulated power to the key components of the thruster. The PPU contains six different power supplies including the beam, discharge, discharge heater, neutralizer, neutralizer heater, and accelerator supplies. The beam supply is the largest and processes up to 93+% of the power. The NEXT PPU had been operated for approximately 200+ hr and has experienced a series of three capacitor failures in the beam supply. The capacitors are in the same, nominally non-critical location-the input filter capacitor to a full wave switching inverter. The three failures occurred after about 20, 30, and 135 hr of operation. This paper provides background on the NEXT PPU and the capacitor failures. It discusses the failure investigation approach, the beam supply power switching topology and its operating modes, capacitor characteristics and circuit testing. Finally, it identifies root cause of the failures to be the unusual confluence of circuit switching frequency, the physical layout of the power circuits, and the characteristics of the capacitor.

Molecular-Scale Electronics: From Concept to Function.

PubMed

Xiang, Dong; Wang, Xiaolong; Jia, Chuancheng; Lee, Takhee; Guo, Xuefeng

2016-04-13

Creating functional electrical circuits using individual or ensemble molecules, often termed as "molecular-scale electronics", not only meets the increasing technical demands of the miniaturization of traditional Si-based electronic devices, but also provides an ideal window of exploring the intrinsic properties of materials at the molecular level. This Review covers the major advances with the most general applicability and emphasizes new insights into the development of efficient platform methodologies for building reliable molecular electronic devices with desired functionalities through the combination of programmed bottom-up self-assembly and sophisticated top-down device fabrication. First, we summarize a number of different approaches of forming molecular-scale junctions and discuss various experimental techniques for examining these nanoscale circuits in details. We then give a full introduction of characterization techniques and theoretical simulations for molecular electronics. Third, we highlight the major contributions and new concepts of integrating molecular functionalities into electrical circuits. Finally, we provide a critical discussion of limitations and main challenges that still exist for the development of molecular electronics. These analyses should be valuable for deeply understanding charge transport through molecular junctions, the device fabrication process, and the roadmap for future practical molecular electronics.

Simplifications in modelling of dynamical response of coupled electro-mechanical system

NASA Astrophysics Data System (ADS)

Darula, Radoslav; Sorokin, Sergey

2016-12-01

The choice of a most suitable model of an electro-mechanical system depends on many variables, such as a scale of the system, type and frequency range of its operation, or power requirements. The article focuses on the model of the electromagnetic element used in passive regime (no feedback loops are assumed) and a general lumped parameter model (a conventional mass-spring-damper system coupled to an electric circuit consisting of a resistance, an inductance and a capacitance) is compared with its simplified version, where the full RLC circuit is replaced with its RL simplification, i.e. the capacitance of the electric system is neglected and just its inductance and the resistance are considered. From the comparison of dynamical responses of these systems, the range of applicability of a simplified model is assessed for free as well as forced vibration.

Programmable high-output-impedance, large-voltage compliance, microstimulator for low-voltage biomedical applications.

PubMed

Farahmand, Sina; Maghami, Mohammad Hossein; Sodagar, Amir M

2012-01-01

This paper reports on the design of a programmable, high output impedance, large voltage compliance microstimulator for low-voltage biomedical applications. A 6-bit binary-weighted digital to analog converter (DAC) is used to generate biphasic stimulus current pulses. A compact current mirror with large output voltage compliance and high output resistance conveys the current pulses to the target tissue. Designed and simulated in a standard 0.18µm CMOS process, the microstimulator circuit is capable of delivering a maximum stimulation current of 160µA to a 10-kΩ resistive load. Operated at a 1.8-V supply voltage, the output stage exhibits a voltage compliance of 1.69V and output resistance of 160MΩ at full scale stimulus current. Layout of the core microelectrode circuit measures 25.5µm×31.5µm.

Concentric transmon qubit featuring fast tunability and an anisotropic magnetic dipole moment

NASA Astrophysics Data System (ADS)

Braumüller, Jochen; Sandberg, Martin; Vissers, Michael R.; Schneider, Andre; Schlör, Steffen; Grünhaupt, Lukas; Rotzinger, Hannes; Marthaler, Michael; Lukashenko, Alexander; Dieter, Amadeus; Ustinov, Alexey V.; Weides, Martin; Pappas, David P.

2016-01-01

We present a planar qubit design based on a superconducting circuit that we call concentric transmon. While employing a straightforward fabrication process using Al evaporation and lift-off lithography, we observe qubit lifetimes and coherence times in the order of 10 μ s . We systematically characterize loss channels such as incoherent dielectric loss, Purcell decay and radiative losses. The implementation of a gradiometric SQUID loop allows for a fast tuning of the qubit transition frequency and therefore for full tomographic control of the quantum circuit. Due to the large loop size, the presented qubit architecture features a strongly increased magnetic dipole moment as compared to conventional transmon designs. This renders the concentric transmon a promising candidate to establish a site-selective passive direct Z ̂ coupling between neighboring qubits, being a pending quest in the field of quantum simulation.

Microbatteries for Combinatorial Studies of Conventional Lithium-Ion Batteries

NASA Technical Reports Server (NTRS)

West, William; Whitacre, Jay; Bugga, Ratnakumar

2003-01-01

Integrated arrays of microscopic solid-state batteries have been demonstrated in a continuing effort to develop microscopic sources of power and of voltage reference circuits to be incorporated into low-power integrated circuits. Perhaps even more importantly, arrays of microscopic batteries can be fabricated and tested in combinatorial experiments directed toward optimization and discovery of battery materials. The value of the combinatorial approach to optimization and discovery has been proven in the optoelectronic, pharmaceutical, and bioengineering industries. Depending on the specific application, the combinatorial approach can involve the investigation of hundreds or even thousands of different combinations; hence, it is time-consuming and expensive to attempt to implement the combinatorial approach by building and testing full-size, discrete cells and batteries. The conception of microbattery arrays makes it practical to bring the advantages of the combinatorial approach to the development of batteries.

DOE Office of Scientific and Technical Information (OSTI.GOV)

De Geronimo, Gianluigi

Embodiments of comparator circuits are disclosed. A comparator circuit may include a differential input circuit, an output circuit, a positive feedback circuit operably coupled between the differential input circuit and the output circuit, and a hysteresis control circuit operably coupled with the positive feedback circuit. The hysteresis control circuit includes a switching device and a transistor. The comparator circuit provides sub-hysteresis discrimination and high speed discrimination.

A Framework for Robust Multivariable Optimization of Integrated Circuits in Space Applications

NASA Technical Reports Server (NTRS)

DuMonthier, Jeffrey; Suarez, George

2013-01-01

Application Specific Integrated Circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way which facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as framework of software modules, templates and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation. Templates provide a starting point for both while toolbox functions minimize the code required. Once a test bench has been coded to optimize a particular circuit, it is also used to verify the final design. The combination of test bench and cost function can then serve as a template for similar circuits or be re-used to migrate the design to different processes by re-running it with the new process specific device models. The system has been used in the design of time to digital converters for laser ranging and time-of-flight mass spectrometry to optimize analog, mixed signal and digital circuits such as charge sensitive amplifiers, comparators, delay elements, radiation tolerant dual interlocked (DICE) flip-flops and two of three voter gates.

33 CFR 117.997 - Atlantic Intracoastal Waterway, South Branch of the Elizabeth River to the Albermarle and...

Code of Federal Regulations, 2010 CFR

2010-07-01

... bridge and directly beneath the bridge with closed circuit cameras mounted on top of the bridge and with... movement, a warning alarm will sound until the bridge is seated and locked down or in the full open... bridge is seated and locked down. When the bridge is seated and locked down to vessels, the channel...

A process modification for CMOS monolithic active pixel sensors for enhanced depletion, timing performance and radiation tolerance

NASA Astrophysics Data System (ADS)

Snoeys, W.; Aglieri Rinella, G.; Hillemanns, H.; Kugathasan, T.; Mager, M.; Musa, L.; Riedler, P.; Reidt, F.; Van Hoorne, J.; Fenigstein, A.; Leitner, T.

2017-11-01

For the upgrade of its Inner Tracking System, the ALICE experiment plans to install a new tracker fully constructed with monolithic active pixel sensors implemented in a standard 180 nm CMOS imaging sensor process, with a deep pwell allowing full CMOS within the pixel. Reverse substrate bias increases the tolerance to non-ionizing energy loss (NIEL) well beyond 1013 1 MeVneq /cm2, but does not allow full depletion of the sensitive layer and hence full charge collection by drift, mandatory for more extreme radiation tolerance. This paper describes a process modification to fully deplete the epitaxial layer even with a small charge collection electrode. It uses a low dose blanket deep high energy n-type implant in the pixel array and does not require significant circuit or layout changes so that the same design can be fabricated both in the standard and modified process. When exposed to a 55 Fe source at a reverse substrate bias of -6 V, pixels implemented in the standard and the modified process in a low and high dose variant for the deep n-type implant respectively yield a signal of about 115 mV, 110 mV and 90 mV at the output of a follower circuit. Signal rise times heavily affected by the speed of this circuit are 27 . 8 + / - 5 ns, 23 . 2 + / - 4 . 2 ns, and 22 . 2 + / - 3 . 7 ns rms, respectively. In a different setup, the single pixel signal from a 90 Sr source only degrades by less than 20% for the modified process after a 1015 1 MeVneq /cm2 irradiation, while the signal rise time only degrades by about 16 + / - 2 ns to 19 + / - 2 . 8 ns rms. From sensors implemented in the standard process no useful signal could be extracted after the same exposure. These first results indicate the process modification maintains low sensor capacitance, improves timing performance and increases NIEL tolerance by at least an order of magnitude.

ALPIDE, the Monolithic Active Pixel Sensor for the ALICE ITS upgrade

NASA Astrophysics Data System (ADS)

Mager, M.; ALICE Collaboration

2016-07-01

A new 10 m2 inner tracking system based on seven concentric layers of Monolithic Active Pixel Sensors will be installed in the ALICE experiment during the second long shutdown of LHC in 2019-2020. The monolithic pixel sensors will be fabricated in the 180 nm CMOS Imaging Sensor process of TowerJazz. The ALPIDE design takes full advantage of a particular process feature, the deep p-well, which allows for full CMOS circuitry within the pixel matrix, while at the same time retaining the full charge collection efficiency. Together with the small feature size and the availability of six metal layers, this allowed a continuously active low-power front-end to be placed into each pixel and an in-matrix sparsification circuit to be used that sends only the addresses of hit pixels to the periphery. This approach led to a power consumption of less than 40 mWcm-2, a spatial resolution of around 5 μm, a peaking time of around 2 μs, while being radiation hard to some 1013 1 MeVneq /cm2, fulfilling or exceeding the ALICE requirements. Over the last years of R & D, several prototype circuits have been used to verify radiation hardness, and to optimize pixel geometry and in-pixel front-end circuitry. The positive results led to a submission of full-scale (3 cm×1.5 cm) sensor prototypes in 2014. They are being characterized in a comprehensive campaign that also involves several irradiation and beam tests. A summary of the results obtained and prospects towards the final sensor to instrument the ALICE Inner Tracking System are given.

Modeling and control of fuel cell based distributed generation systems

NASA Astrophysics Data System (ADS)

Jung, Jin Woo

This dissertation presents circuit models and control algorithms of fuel cell based distributed generation systems (DGS) for two DGS topologies. In the first topology, each DGS unit utilizes a battery in parallel to the fuel cell in a standalone AC power plant and a grid-interconnection. In the second topology, a Z-source converter, which employs both the L and C passive components and shoot-through zero vectors instead of the conventional DC/DC boost power converter in order to step up the DC-link voltage, is adopted for a standalone AC power supply. In Topology 1, two applications are studied: a standalone power generation (Single DGS Unit and Two DGS Units) and a grid-interconnection. First, dynamic model of the fuel cell is given based on electrochemical process. Second, two full-bridge DC to DC converters are adopted and their controllers are designed: an unidirectional full-bridge DC to DC boost converter for the fuel cell and a bidirectional full-bridge DC to DC buck/boost converter for the battery. Third, for a three-phase DC to AC inverter without or with a Delta/Y transformer, a discrete-time state space circuit model is given and two discrete-time feedback controllers are designed: voltage controller in the outer loop and current controller in the inner loop. And last, for load sharing of two DGS units and power flow control of two DGS units or the DGS connected to the grid, real and reactive power controllers are proposed. Particularly, for the grid-connected DGS application, a synchronization issue between an islanding mode and a paralleling mode to the grid is investigated, and two case studies are performed. To demonstrate the proposed circuit models and control strategies, simulation test-beds using Matlab/Simulink are constructed for each configuration of the fuel cell based DGS with a three-phase AC 120 V (L-N)/60 Hz/50 kVA and various simulation results are presented. In Topology 2, this dissertation presents system modeling, modified space vector PWM implementation (MSVPWM) and design of a closed-loop controller of the Z-source converter which utilizes L and C components and shoot-through zero vectors for the standalone AC power generation. The fuel cell system is modeled by an electrical R-C circuit in order to include slow dynamics of the fuel cells and a voltage-current characteristic of a cell is also considered. A discrete-time state space model is derived to implement digital control and a space vector pulse-width modulation (SVPWM) technique is modified to realize the shoot-through zero vectors that boost the DC-link voltage. Also, three discrete-time feedback controllers are designed: a discrete-time optimal voltage controller, a discrete-time sliding mode current controller, and a discrete-time PI DC-link voltage controller. Furthermore, an asymptotic observer is used to reduce the number of sensors and enhance the reliability of the system. To demonstrate the analyzed circuit model and proposed control strategy, various simulation results using Matlab/Simulink are presented under both light/heavy loads and linear/nonlinear loads for a three-phase AC 208 V (L-L)/60 Hz/10 kVA.

Boolean gates on actin filaments

NASA Astrophysics Data System (ADS)

Siccardi, Stefano; Tuszynski, Jack A.; Adamatzky, Andrew

2016-01-01

Actin is a globular protein which forms long polar filaments in the eukaryotic cytoskeleton. Actin networks play a key role in cell mechanics and cell motility. They have also been implicated in information transmission and processing, memory and learning in neuronal cells. The actin filaments have been shown to support propagation of voltage pulses. Here we apply a coupled nonlinear transmission line model of actin filaments to study interactions between voltage pulses. To represent digital information we assign a logical TRUTH value to the presence of a voltage pulse in a given location of the actin filament, and FALSE to the pulse's absence, so that information flows along the filament with pulse transmission. When two pulses, representing Boolean values of input variables, interact, then they can facilitate or inhibit further propagation of each other. We explore this phenomenon to construct Boolean logical gates and a one-bit half-adder with interacting voltage pulses. We discuss implications of these findings on cellular process and technological applications.

Active Detection of Shielded Special Nuclear Material in the Presence of Variable High Backgrounds Using a Mixed Photon-Neutron Source

NASA Astrophysics Data System (ADS)

Martin, Philip N.; Clemett, Ceri D.; Hill, Cassie; O'Malley, John; Campbell, Ben

This paper describes and compares two approaches to the analysis of active interrogation data containing high photon backgrounds associated with mixed photon-neutron source flash active interrogation. Results from liquid scintillation detectors (EJ301/EJ309) fielded at the Naval Research Laboratory (NRL), in collaboration with the Atomic Weapons Establishment (AWE), using the NRL Mercury Inductive Voltage Adder (IVA) operating in both a photon and mixed photon-neutron mode at a Depleted Uranium (DU) target are presented. The standard approach applying a Figure of Merit (FOM) consisting of background sigma above background is compared with an approach looking to fit only the time-decaying photon signal with standard delayed photon emission from ∼10-MeV end-point-energy Bremsstrahlung photofission of DU. Examples where each approach does well and less well are presented together with a discussion of the relative limitations of both approaches to the type of mixed photon-neutron flash active interrogation being considered.

Development of EUV mask handling technology at MIRAI-Selete

NASA Astrophysics Data System (ADS)

Ota, Kazuya; Amemiya, Mitsuaki; Taguchi, Takao; Kamono, Takashi; Kubo, Hiroyoshi; Takikawa, Tadahiko; Usui, Yoichi; Suga, Osamu

2007-03-01

We, MIRAI-Selete, started a new EUV mask program in April, 2006. Development of EUV mask handling technology is one of the key areas of the program. We plan to develop mask handling technology and to evaluate EUV mask carriers using Lasertec M3350, a particle inspection tool with the defect sensitivity less than 50nm PSL, and Mask Protection Engineering Tool (named "MPE Tool"). M3350 is a newly developed tool based on a conventional M1350 for EUV blanks inspection. Since our M3350 has a blank flipping mechanism in it, we can inspect the front and the back surface of the blank automatically. We plan to use the M3350 for evaluating particle adders during mask shipping, storage and handling. MPE Tool is a special tool exclusively developed for demonstration of pellicleless mask handling. It can handle a mask within a protective enclosure, which Canon and Nikon have been jointly proposing1, and also, can be modified to handle other type of carrier as the need arises.

Design and implementation in VHDL code of the two-dimensional fast Fourier transform for frequency filtering, convolution and correlation operations

NASA Astrophysics Data System (ADS)

Vilardy, Juan M.; Giacometto, F.; Torres, C. O.; Mattos, L.

2011-01-01

The two-dimensional Fast Fourier Transform (FFT 2D) is an essential tool in the two-dimensional discrete signals analysis and processing, which allows developing a large number of applications. This article shows the description and synthesis in VHDL code of the FFT 2D with fixed point binary representation using the programming tool Simulink HDL Coder of Matlab; showing a quick and easy way to handle overflow, underflow and the creation registers, adders and multipliers of complex data in VHDL and as well as the generation of test bench for verification of the codes generated in the ModelSim tool. The main objective of development of the hardware architecture of the FFT 2D focuses on the subsequent completion of the following operations applied to images: frequency filtering, convolution and correlation. The description and synthesis of the hardware architecture uses the XC3S1200E family Spartan 3E FPGA from Xilinx Manufacturer.