Design, development, fabrication and delivery of register and multiplexer units. [CMOS monolithic chip development

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardi, T.

1978-01-01

Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated. The CMOS standard cell array technique was selected and implemented. Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation. One of the chip types, multiplexer register type 1, is fabricated on a 0.143 x 0.123 inch chip. It uses nine standard cell types for a total of 54 standard cells. This involves more than 350 transistors and has the functional equivalent of 111 gates. The second chip, multiplexer register type 2, is housed on a 0.12 x 0.12 inch die. It uses 13 standard cell types, for a total of 42 standard cells. It contains more than 300 transistors, the functional equivalent of 112 gates. All of the hermetically sealed units were initially screened for proper functional operation. The static leakage and the dynamic leakage were measured. Dynamic measurements were made and recorded. At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1. At 5 V these units shifted data at a 6.6 MHz rate. The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C.

A 65k pixel, 150k frames-per-second camera with global gating and micro-lenses suitable for fluorescence lifetime imaging

NASA Astrophysics Data System (ADS)

Burri, Samuel; Powolny, François; Bruschini, Claudio E.; Michalet, Xavier; Regazzoni, Francesco; Charbon, Edoardo

2014-05-01

This paper presents our work on a 65k pixel single-photon avalanche diode (SPAD) based imaging sensor realized in a 0.35μm standard CMOS process. At a resolution of 512 by 128 pixels the sensor is read out in 6.4μs to deliver over 150k monochrome frames per second. The individual pixel has a size of 24μm2 and contains the SPAD with a 12T quenching and gating circuitry along with a memory element. The gating signals are distributed across the chip through a balanced tree to minimize the signal skew between the pixels. The array of pixels is row-addressable and data is sent out of the chip on 128 lines in parallel at a frequency of 80MHz. The system is controlled by an FPGA which generates the gating and readout signals and can be used for arbitrary real-time computation on the frames from the sensor. The communication protocol between the camera and a conventional PC is USB2. The active area of the chip is 5% and can be significantly improved with the application of a micro-lens array. A micro-lens array, for use with collimated light, has been designed and its performance is reviewed in the paper. Among other high-speed phenomena the gating circuitry capable of generating illumination periods shorter than 5ns can be used for Fluorescence Lifetime Imaging (FLIM). In order to measure the lifetime of fluorophores excited by a picosecond laser, the sensor's illumination period is synchronized with the excitation laser pulses. A histogram of the photon arrival times relative to the excitation is then constructed by counting the photons arriving during the sensitive time for several positions of the illumination window. The histogram for each pixel is transferred afterwards to a computer where software routines extract the lifetime at each location with an accuracy better than 100ps. We show results for fluorescence lifetime measurements using different fluorophores with lifetimes ranging from 150ps to 5ns.

A Robust Strategy for Total Ionizing Dose Testing of Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Wilcox, Edward; Berg, Melanie; Friendlich, Mark; Lakeman, Joseph; KIm, Hak; Pellish, Jonathan; LaBel, Kenneth

2012-01-01

We present a novel method of FPGA TID testing that measures propagation delay between flip-flops operating at maximum speed. Measurement is performed on-chip at-speed and provides a key design metric when building system-critical synchronous designs.

All optical programmable logic array (PLA)

NASA Astrophysics Data System (ADS)

Hiluf, Dawit

2018-03-01

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

Optimized FPGA Implementation of the Thyroid Hormone Secretion Mechanism Using CAD Tools.

PubMed

Alghazo, Jaafar M

2017-02-01

The goal of this paper is to implement the secretion mechanism of the Thyroid Hormone (TH) based on bio-mathematical differential eqs. (DE) on an FPGA chip. Hardware Descriptive Language (HDL) is used to develop a behavioral model of the mechanism derived from the DE. The Thyroid Hormone secretion mechanism is simulated with the interaction of the related stimulating and inhibiting hormones. Synthesis of the simulation is done with the aid of CAD tools and downloaded on a Field Programmable Gate Arrays (FPGAs) Chip. The chip output shows identical behavior to that of the designed algorithm through simulation. It is concluded that the chip mimics the Thyroid Hormone secretion mechanism. The chip, operating in real-time, is computer-independent stand-alone system.

Sequence information signal processor for local and global string comparisons

DOEpatents

Peterson, John C.; Chow, Edward T.; Waterman, Michael S.; Hunkapillar, Timothy J.

1997-01-01

A sequence information signal processing integrated circuit chip designed to perform high speed calculation of a dynamic programming algorithm based upon the algorithm defined by Waterman and Smith. The signal processing chip of the present invention is designed to be a building block of a linear systolic array, the performance of which can be increased by connecting additional sequence information signal processing chips to the array. The chip provides a high speed, low cost linear array processor that can locate highly similar global sequences or segments thereof such as contiguous subsequences from two different DNA or protein sequences. The chip is implemented in a preferred embodiment using CMOS VLSI technology to provide the equivalent of about 400,000 transistors or 100,000 gates. Each chip provides 16 processing elements, and is designed to provide 16 bit, two's compliment operation for maximum score precision of between -32,768 and +32,767. It is designed to provide a comparison between sequences as long as 4,194,304 elements without external software and between sequences of unlimited numbers of elements with the aid of external software. Each sequence can be assigned different deletion and insertion weight functions. Each processor is provided with a similarity measure device which is independently variable. Thus, each processor can contribute to maximum value score calculation using a different similarity measure.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging.

PubMed

Wygant, Ira O; Jamal, Nafis S; Lee, Hyunjoo J; Nikoozadeh, Amin; Oralkan, Omer; Karaman, Mustafa; Khuri-Yakub, Butrus T

2009-10-01

State-of-the-art 3-D medical ultrasound imaging requires transmitting and receiving ultrasound using a 2-D array of ultrasound transducers with hundreds or thousands of elements. A tight combination of the transducer array with integrated circuitry eliminates bulky cables connecting the elements of the transducer array to a separate system of electronics. Furthermore, preamplifiers located close to the array can lead to improved receive sensitivity. A combined IC and transducer array can lead to a portable, high-performance, and inexpensive 3-D ultrasound imaging system. This paper presents an IC flip-chip bonded to a 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array for 3-D ultrasound imaging. The IC includes a transmit beamformer that generates 25-V unipolar pulses with programmable focusing delays to 224 of the 256 transducer elements. One-shot circuits allow adjustment of the pulse widths for different ultrasound transducer center frequencies. For receiving reflected ultrasound signals, the IC uses the 32-elements along the array diagonals. The IC provides each receiving element with a low-noise 25-MHz-bandwidth transimpedance amplifier. Using a field-programmable gate array (FPGA) clocked at 100 MHz to operate the IC, the IC generated properly timed transmit pulses with 5-ns accuracy. With the IC flip-chip bonded to a CMUT array, we show that the IC can produce steered and focused ultrasound beams. We present 2-D and 3-D images of a wire phantom and 2-D orthogonal cross-sectional images (Bscans) of a latex heart phantom.

Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

PubMed Central

Ou, Chien-Min; Li, Hui-Ya; Hwang, Wen-Jyi

2012-01-01

A novel k-winners-take-all (k-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing k-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for realtime on-chip learning. Experimental results show that the SOPC has significantly lower training time than that of other k-WTA CL counterparts operating with or without hardware support.

PROGRAPE-1: A Programmable, Multi-Purpose Computer for Many-Body Simulations

NASA Astrophysics Data System (ADS)

Hamada, Tsuyoshi; Fukushige, Toshiyuki; Kawai, Atsushi; Makino, Junichiro

2000-10-01

We have developed PROGRAPE-1 (PROgrammable GRAPE-1), a programmable multi-purpose computer for many-body simulations. The main difference between PROGRAPE-1 and ``traditional'' GRAPE systems is that the former uses FPGA (Field Programmable Gate Array) chips as the processing elements, while the latter relies on a hardwired pipeline processor specialized to gravitational interactions. Since the logic implemented in FPGA chips can be reconfigured, we can use PROGRAPE-1 to calculate not only gravitational interactions, but also other forms of interactions, such as the van der Waals force, hydro\\-dynamical interactions in the SPHr calculation, and so on. PROGRAPE-1 comprises two Altera EPF10K100 FPGA chips, each of which contains nominally 100000 gates. To evaluate the programmability and performance of PROGRAPE-1, we implemented a pipeline for gravitational interactions similar to that of GRAPE-3. One pipeline is fitted into a single FPGA chip, operated at 16 MHz clock. Thus, for gravitational interactions, PROGRAPE-1 provided a speed of 0.96 Gflops-equivalent. PROGRAPE will prove to be useful for a wide-range of particle-based simulations in which the calculation cost of interactions other than gravity is high, such as the evaluation of SPH interactions.

Direct protein detection with a nano-interdigitated array gate MOSFET.

PubMed

Tang, Xiaohui; Jonas, Alain M; Nysten, Bernard; Demoustier-Champagne, Sophie; Blondeau, Franoise; Prévot, Pierre-Paul; Pampin, Rémi; Godfroid, Edmond; Iñiguez, Benjamin; Colinge, Jean-Pierre; Raskin, Jean-Pierre; Flandre, Denis; Bayot, Vincent

2009-08-15

A new protein sensor is demonstrated by replacing the gate of a metal oxide semiconductor field effect transistor (MOSFET) with a nano-interdigitated array (nIDA). The sensor is able to detect the binding reaction of a typical antibody Ixodes ricinus immunosuppressor (anti-Iris) protein at a concentration lower than 1 ng/ml. The sensor exhibits a high selectivity and reproducible specific detection. We provide a simple model that describes the behavior of the sensor and explains the origin of its high sensitivity. The simulated and experimental results indicate that the drain current of nIDA-gate MOSFET sensor is significantly increased with the successive binding of the thiol layer, Iris and anti-Iris protein layers. It is found that the sensor detection limit can be improved by well optimizing the geometrical parameters of nIDA-gate MOSFET. This nanobiosensor, with real-time and label-free capabilities, can easily be used for the detection of other proteins, DNA, virus and cancer markers. Moreover, an on-chip associated electronics nearby the sensor can be integrated since its fabrication is compatible with complementary metal oxide semiconductor (CMOS) technology.

Space Qualified High Speed Reed Solomon Encoder

NASA Technical Reports Server (NTRS)

Gambles, Jody W.; Winkert, Tom

1993-01-01

This paper reports a Class S CCSDS recommendation Reed Solomon encoder circuit baselined for several NASA programs. The chip is fabricated using United Technologies Microelectronics Center's UTE-R radiation-hardened gate array family, contains 64,000 p-n transistor pairs, and operates at a sustained output data rate of 200 MBits/s. The chip features a pin selectable message interleave depth of from 1 to 8 and supports output block lengths of 33 to 255 bytes. The UTE-R process is reported to produce parts that are radiation hardened to 16 Rads (Si) total dose and 1.0(exp -10) errors/bit-day.

Fabrication of resistively-coupled single-electron device using an array of gold nanoparticles

NASA Astrophysics Data System (ADS)

Huong, Tran Thi Thu; Matsumoto, Kazuhiko; Moriya, Masataka; Shimada, Hiroshi; Kimura, Yasuo; Hirano-Iwata, Ayumi; Mizugaki, Yoshinao

2017-08-01

We demonstrated one type of single-electron device that exhibited electrical characteristics similar to those of resistively-coupled SE transistor (R-SET) at 77 K and room temperature (287 K). Three Au electrodes on an oxidized Si chip served as drain, source, and gate electrodes were formed using electron-beam lithography and evaporation techniques. A narrow (70-nm-wide) gate electrode was patterned using thermal evaporation, whereas wide (800-nm-wide) drain and source electrodes were made using shadow evaporation. Subsequently, aqueous solution of citric acid and 15-nm-diameter gold nanoparticles (Au NPs) and toluene solution of 3-nm-diameter Au NPs chemisorbed via decanethiol were dropped on the chip to make the connections between the electrodes. Current-voltage characteristics between the drain and source electrodes exhibited Coulomb blockade (CB) at both 77 and 287 K. Dependence of the CB region on the gate voltage was similar to that of an R-SET. Simulation results of the model based on the scanning electron microscopy image of the device could reproduce the characteristics like the R-SET.

CMOS minimal array

NASA Astrophysics Data System (ADS)

Janesick, James; Cheng, John; Bishop, Jeanne; Andrews, James T.; Tower, John; Walker, Jeff; Grygon, Mark; Elliot, Tom

2006-08-01

A high performance prototype CMOS imager is introduced. Test data is reviewed for different array formats that utilize 3T photo diode, 5T pinned photo diode and 6T photo gate CMOS pixel architectures. The imager allows several readout modes including progressive scan, snap and windowed operation. The new imager is built on different silicon substrates including very high resistivity epitaxial wafers for deep depletion operation. Data products contained in this paper focus on sensor's read noise, charge capacity, charge transfer efficiency, thermal dark current, RTS dark spikes, QE, pixel cross- talk and on-chip analog circuitry performance.

InGaAs/InP SPAD photon-counting module with auto-calibrated gate-width generation and remote control

NASA Astrophysics Data System (ADS)

Tosi, Alberto; Ruggeri, Alessandro; Bahgat Shehata, Andrea; Della Frera, Adriano; Scarcella, Carmelo; Tisa, Simone; Giudice, Andrea

2013-01-01

We present a photon-counting module based on InGaAs/InP SPAD (Single-Photon Avalanche Diode) for detecting single photons up to 1.7 μm. The module exploits a novel architecture for generating and calibrating the gate width, along with other functions (such as module supervision, counting and processing of detected photons, etc.). The gate width, i.e. the time interval when the SPAD is ON, is user-programmable in the range from 500 ps to 1.5 μs, by means of two different delay generation methods implemented with an FPGA (Field-Programmable Gate Array). In order to compensate chip-to-chip delay variation, an auto-calibration circuit picks out a combination of delays in order to match at best the selected gate width. The InGaAs/InP module accepts asynchronous and aperiodic signals and introduces very low timing jitter. Moreover the photon counting module provides other new features like a microprocessor for system supervision, a touch-screen for local user interface, and an Ethernet link for smart remote control. Thanks to the fullyprogrammable and configurable architecture, the overall instrument provides high system flexibility and can easily match all requirements set by many different applications requiring single photon-level sensitivity in the near infrared with very low photon timing jitter.

Low-Noise Free-Running High-Rate Photon-Counting for Space Communication and Ranging

NASA Technical Reports Server (NTRS)

Lu, Wei; Krainak, Michael A.; Yang, Guangning; Sun, Xiaoli; Merritt, Scott

2016-01-01

We present performance data for low-noise free-running high-rate photon counting method for space optical communication and ranging. NASA GSFC is testing the performance of two types of novel photon-counting detectors 1) a 2x8 mercury cadmium telluride (HgCdTe) avalanche array made by DRS Inc., and a 2) a commercial 2880-element silicon avalanche photodiode (APD) array. We successfully measured real-time communication performance using both the 2 detected-photon threshold and logic AND-gate coincidence methods. Use of these methods allows mitigation of dark count, after-pulsing and background noise effects without using other method of Time Gating The HgCdTe APD array routinely demonstrated very high photon detection efficiencies ((is) greater than 50%) at near infrared wavelength. The commercial silicon APD array exhibited a fast output with rise times of 300 ps and pulse widths of 600 ps. On-chip individually filtered signals from the entire array were multiplexed onto a single fast output. NASA GSFC has tested both detectors for their potential application for space communications and ranging. We developed and compare their performances using both the 2 detected photon threshold and coincidence methods.

Low-Noise Free-Running High-Rate Photon-Counting for Space Communication and Ranging

NASA Technical Reports Server (NTRS)

Lu, Wei; Krainak, Michael A.; Yang, Guan; Sun, Xiaoli; Merritt, Scott

2016-01-01

We present performance data for low-noise free-running high-rate photon counting method for space optical communication and ranging. NASA GSFC is testing the performance of two types of novel photon-counting detectors 1) a 2x8 mercury cadmium telluride (HgCdTe) avalanche array made by DRS Inc., and a 2) a commercial 2880-element silicon avalanche photodiode (APD) array. We successfully measured real-time communication performance using both the 2 detected-photon threshold and logic AND-gate coincidence methods. Use of these methods allows mitigation of dark count, after-pulsing and background noise effects without using other method of Time Gating The HgCdTe APD array routinely demonstrated very high photon detection efficiencies (50) at near infrared wavelength. The commercial silicon APD array exhibited a fast output with rise times of 300 ps and pulse widths of 600 ps. On-chip individually filtered signals from the entire array were multiplexed onto a single fast output. NASA GSFC has tested both detectors for their potential application for space communications and ranging. We developed and compare their performances using both the 2 detected photon threshold and coincidence methods.

FPGA implementation of ICA algorithm for blind signal separation and adaptive noise canceling.

PubMed

Kim, Chang-Min; Park, Hyung-Min; Kim, Taesu; Choi, Yoon-Kyung; Lee, Soo-Young

2003-01-01

An field programmable gate array (FPGA) implementation of independent component analysis (ICA) algorithm is reported for blind signal separation (BSS) and adaptive noise canceling (ANC) in real time. In order to provide enormous computing power for ICA-based algorithms with multipath reverberation, a special digital processor is designed and implemented in FPGA. The chip design fully utilizes modular concept and several chips may be put together for complex applications with a large number of noise sources. Experimental results with a fabricated test board are reported for ANC only, BSS only, and simultaneous ANC/BSS, which demonstrates successful speech enhancement in real environments in real time.

A wideband software reconfigurable modem

NASA Astrophysics Data System (ADS)

Turner, J. H., Jr.; Vickers, H.

A wideband modem is described which provides signal processing capability for four Lx-band signals employing QPSK, MSK and PPM waveforms and employs a software reconfigurable architecture for maximum system flexibility and graceful degradation. The current processor uses a 2901 and two 8086 microprocessors per channel and performs acquisition, tracking, and data demodulation for JITDS, GPS, IFF and TACAN systems. The next generation processor will be implemented using a VHSIC chip set employing a programmable complex array vector processor module, a GP computer module, customized gate array modules, and a digital array correlator. This integrated processor has application to a wide number of diverse system waveforms, and will bring the benefits of VHSIC technology insertion into avionic antijam communications systems.

A digital optical phase-locked loop for diode lasers based on field programmable gate array.

PubMed

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382∕MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad(2) and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

NASA Astrophysics Data System (ADS)

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad2 and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device

NASA Astrophysics Data System (ADS)

Szplet, R.; Kalisz, J.; Jachna, Z.

2009-02-01

We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizer's transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second.

Analyzing System on A Chip Single Event Upset Responses using Single Event Upset Data, Classical Reliability Models, and Space Environment Data

NASA Technical Reports Server (NTRS)

Berg, Melanie; LaBel, Kenneth; Campola, Michael; Xapsos, Michael

2017-01-01

We are investigating the application of classical reliability performance metrics combined with standard single event upset (SEU) analysis data. We expect to relate SEU behavior to system performance requirements. Our proposed methodology will provide better prediction of SEU responses in harsh radiation environments with confidence metrics. single event upset (SEU), single event effect (SEE), field programmable gate array devises (FPGAs)

T-gate aligned nanotube radio frequency transistors and circuits with superior performance.

PubMed

Che, Yuchi; Lin, Yung-Chen; Kim, Pyojae; Zhou, Chongwu

2013-05-28

In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics.

A compressive-sensing Fourier-transform on-chip Raman spectrometer

NASA Astrophysics Data System (ADS)

Podmore, Hugh; Scott, Alan; Lee, Regina

2018-02-01

We demonstrate a novel compressive sensing Fourier-transform spectrometer (FTS) for snapshot Raman spectroscopy in a compact format. The on-chip FTS consists of a set of planar-waveguide Mach-Zehnder interferometers (MZIs) arrayed on a photonic chip, effecting a discrete Fourier-transform of the input spectrum. Incoherence between the sampling domain (time), and the spectral domain (frequency) permits compressive sensing retrieval using undersampled interferograms for sparse spectra such as Raman emission. In our fabricated device we retain our chosen bandwidth and resolution while reducing the number of MZIs, e.g. the size of the interferogram, to 1/4th critical sampling. This architecture simultaneously reduces chip footprint and concentrates the interferogram in fewer pixels to improve the signal to noise ratio. Our device collects interferogram samples simultaneously, therefore a time-gated detector may be used to separate Raman peaks from sample fluorescence. A challenge for FTS waveguide spectrometers is to achieve multi-aperture high throughput broadband coupling to a large number of single-mode waveguides. A multi-aperture design allows one to increase the bandwidth and spectral resolution without sacrificing optical throughput. In this device, multi-aperture coupling is achieved using an array of microlenses bonded to the surface of the chip, and aligned with a grid of vertically illuminated waveguide apertures. The microlens array accepts a collimated beam with near 100% fill-factor, and the resulting spherical wavefronts are coupled into the single-mode waveguides using 45& mirrors etched into the waveguide layer via focused ion-beam (FIB). The interferogram from the waveguide outputs is imaged using a CCD, and inverted via l1-norm minimization to correctly retrieve a sparse input spectrum.

Multi-element germanium detectors for synchrotron applications

NASA Astrophysics Data System (ADS)

Rumaiz, A. K.; Kuczewski, A. J.; Mead, J.; Vernon, E.; Pinelli, D.; Dooryhee, E.; Ghose, S.; Caswell, T.; Siddons, D. P.; Miceli, A.; Baldwin, J.; Almer, J.; Okasinski, J.; Quaranta, O.; Woods, R.; Krings, T.; Stock, S.

2018-04-01

We have developed a series of monolithic multi-element germanium detectors, based on sensor arrays produced by the Forschungzentrum Julich, and on Application-specific integrated circuits (ASICs) developed at Brookhaven. Devices have been made with element counts ranging from 64 to 384. These detectors are being used at NSLS-II and APS for a range of diffraction experiments, both monochromatic and energy-dispersive. Compact and powerful readout systems have been developed, based on the new generation of FPGA system-on-chip devices, which provide closely coupled multi-core processors embedded in large gate arrays. We will discuss the technical details of the systems, and present some of the results from them.

Design of an MR image processing module on an FPGA chip

NASA Astrophysics Data System (ADS)

Li, Limin; Wyrwicz, Alice M.

2015-06-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128 × 128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments.

Design of an MR image processing module on an FPGA chip

PubMed Central

Li, Limin; Wyrwicz, Alice M.

2015-01-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128 × 128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments. PMID:25909646

Advanced modulation technology development for earth station demodulator applications. Coded modulation system development

NASA Technical Reports Server (NTRS)

Miller, Susan P.; Kappes, J. Mark; Layer, David H.; Johnson, Peter N.

1990-01-01

A jointly optimized coded modulation system is described which was designed, built, and tested by COMSAT Laboratories for NASA LeRC which provides a bandwidth efficiency of 2 bits/s/Hz at an information rate of 160 Mbit/s. A high speed rate 8/9 encoder with a Viterbi decoder and an Octal PSK modem are used to achieve this. The BER performance is approximately 1 dB from the theoretically calculated value for this system at a BER of 5 E-7 under nominal conditions. The system operates in burst mode for downlink applications and tests have demonstrated very little degradation in performance with frequency and level offset. Unique word miss rate measurements were conducted which demonstrate reliable acquisition at low values of Eb/No. Codec self tests have verified the performance of this subsystem in a stand alone mode. The codec is capable of operation at a 200 Mbit/s information rate as demonstrated using a codec test set which introduces noise digitally. The measured performance is within 0.2 dB of the computer simulated predictions. A gate array implementation of the most time critical element of the high speed Viterbi decoder was completed. This gate array add-compare-select chip significantly reduces the power consumption and improves the manufacturability of the decoder. This chip has general application in the implementation of high speed Viterbi decoders.

Multiport backside-illuminated CCD imagers for high-frame-rate camera applications

NASA Astrophysics Data System (ADS)

Levine, Peter A.; Sauer, Donald J.; Hseuh, Fu-Lung; Shallcross, Frank V.; Taylor, Gordon C.; Meray, Grazyna M.; Tower, John R.; Harrison, Lorna J.; Lawler, William B.

1994-05-01

Two multiport, second-generation CCD imager designs have been fabricated and successfully tested. They are a 16-port 512 X 512 array and a 32-port 1024 X 1024 array. Both designs are back illuminated, have on-chip CDS, lateral blooming control, and use a split vertical frame transfer architecture with full frame storage. The 512 X 512 device has been operated at rates over 800 frames per second. The 1024 X 1024 device has been operated at rates over 300 frames per second. The major changes incorporated in the second-generation design are, reduction in gate length in the output area to give improved high-clock-rate performance, modified on-chip CDS circuitry for reduced noise, and optimized implants to improve performance of blooming control at lower clock amplitude. This paper discusses the imager design improvements and presents measured performance results at high and moderate frame rates. The design and performance of three moderate frame rate cameras are discussed.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xu Zhouxiang; Zhang Xian; Huang Kaikai

2012-09-15

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat notemore » line width below 1 Hz, residual mean-square phase error of 0.14 rad{sup 2} and transition time of 100 {mu}s under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.« less

Developments of FPGA-based digital back-ends for low frequency antenna arrays at Medicina radio telescopes

NASA Astrophysics Data System (ADS)

Naldi, G.; Bartolini, M.; Mattana, A.; Pupillo, G.; Hickish, J.; Foster, G.; Bianchi, G.; Lingua, A.; Monari, J.; Montebugnoli, S.; Perini, F.; Rusticelli, S.; Schiaffino, M.; Virone, G.; Zarb Adami, K.

In radio astronomy Field Programmable Gate Array (FPGA) technology is largely used for the implementation of digital signal processing techniques applied to antenna arrays. This is mainly due to the good trade-off among computing resources, power consumption and cost offered by FPGA chip compared to other technologies like ASIC, GPU and CPU. In the last years several digital backend systems based on such devices have been developed at the Medicina radio astronomical station (INAF-IRA, Bologna, Italy). Instruments like FX correlator, direct imager, beamformer, multi-beam system have been successfully designed and realized on CASPER (Collaboration for Astronomy Signal Processing and Electronics Research, https://casper.berkeley.edu) processing boards. In this paper we present the gained experience in this kind of applications.

United States Air Force Summer Faculty Research Program. Program Technical Report. 1990. Volume 3

DTIC Science & Technology

1991-06-05

flowchart of the progran "NCHIPSIM" is shown o. the following two pages. 95-7 SSTAR ’ ’.Choose-Chip type; Microprocessor or Gate,-Array Choose...oeet ~alulaew ntegrionRsut YEYES FLOW CHART FOR NCHIPSIM" 95-9 IV. THE PROGRAM "NCHIPSIM": Using the flowchart and the steps outlined in the above...would make the technique more versatile in flaw detection in metallic materials. 113-16 REFERENCES 1. RUDLIN, J.R., "A Beginners Guide to-Eddy Current

A Single-Photon Avalanche Diode Array for Fluorescence Lifetime Imaging Microscopy.

PubMed

Schwartz, David Eric; Charbon, Edoardo; Shepard, Kenneth L

2008-11-21

We describe the design, characterization, and demonstration of a fully integrated single-photon avalanche diode (SPAD) imager for use in time-resolved fluorescence imaging. The imager consists of a 64-by-64 array of active SPAD pixels and an on-chip time-to-digital converter (TDC) based on a delay-locked loop (DLL) and calibrated interpolators. The imager can perform both standard time-correlated single-photon counting (TCSPC) and an alternative gated-window detection useful for avoiding pulse pile-up when measuring bright signal levels. To illustrate the use of the imager, we present measurements of the decay lifetimes of fluorescent dyes of several types with a timing resolution of 350 ps.

A Single-Photon Avalanche Diode Array for Fluorescence Lifetime Imaging Microscopy

PubMed Central

Schwartz, David Eric; Charbon, Edoardo; Shepard, Kenneth L.

2013-01-01

We describe the design, characterization, and demonstration of a fully integrated single-photon avalanche diode (SPAD) imager for use in time-resolved fluorescence imaging. The imager consists of a 64-by-64 array of active SPAD pixels and an on-chip time-to-digital converter (TDC) based on a delay-locked loop (DLL) and calibrated interpolators. The imager can perform both standard time-correlated single-photon counting (TCSPC) and an alternative gated-window detection useful for avoiding pulse pile-up when measuring bright signal levels. To illustrate the use of the imager, we present measurements of the decay lifetimes of fluorescent dyes of several types with a timing resolution of 350 ps. PMID:23976789

Fabrication and characteristics of MOSFET protein chip for detection of ribosomal protein.

PubMed

Park, Keun-Yong; Kim, Min-Suk; Choi, Sie-Young

2005-04-15

A metal oxide silicon field effect transistor (MOSFET) protein chip for the easy detection of protein was fabricated and its characteristics were investigated. Generally, the drain current of the MOSFET is varied by the gate potential. It is expected that the formation of an antibody-antigen complex on the gate of MOSFET would lead to a detectable change in the charge distribution and thus, directly modulate the drain current of MOSFET. As such, the drain current of the MOSFET protein chip can be varied by ribosomal proteins absorbed by the self-assembled monolayer (SAM) immobilized on the gate (Au) surface, as ribosomal protein has positive charge, and these current variations then used as the response of the protein chip. The gate of MOSFET protein chip is not directly biased by an external voltage source, so called open gate or floating gate MOSFET, but rather chemically modified by immobilized molecular receptors called self-assembled monolayer (SAM). In our experiments, the current variation in the proposed protein chip was about 8% with a protein concentration of 0.7 mM. As the protein concentration increased, the drain current also gradually increased. In addition, there were some drift of the drain current in the device. It is considered that these drift might be caused by the drift from the MOSFET itself or protein absorption procedures that are relied on the facile attachment of thiol (-S) ligands to the gate (Au) surface. We verified the formation of SAM on the gold surface and the absorption of protein through the surface plasmon resonance (SPR) measurement.

Tunable metamaterial-induced transparency with gate-controlled on-chip graphene metasurface.

PubMed

Chen, Zan Hui; Tao, Jin; Gu, Jia Hua; Li, Jian; Hu, Di; Tan, Qi Long; Zhang, Fengchun; Huang, Xu Guang

2016-12-12

We propose and numerically investigate a gate-controlled on-chip graphene metasurface consisting of a monolayer graphene sheet and silicon photonic crystal-like substrate, to achieve an electrically-tunable induced transparency. The operation mechanism of the induced transparency of the on-chip graphene metasurface is analyzed. The tunable optical properties with different gate-voltages and polarizations have been discussed. Additionally, the spectral feature of the on-chip graphene metasurface as a function of the refractive index of the local environment is also investigated. The result shows that the on-chip graphene metasurface as a refractive index sensor can achieve an overall figure of merit of 8.89 in infrared wavelength range. Our study suggests that the proposed structure is potentially attractive as optoelectronic modulators and refractive index sensors.

Microsensor research

NASA Astrophysics Data System (ADS)

Hughes, R. C.; Drebing, C. G.

1990-04-01

The technology that led to very large scale integrated circuits on silicon chips also provides a basis for new microsensors that are small, inexpensive, low power, rugged, and reliable. Two examples of microsensors Sandia is developing that take advantage of this technology are the microelectronic chemical sensor array and the radiation sensing field effect transistor (RADFET). Increasingly, the technology of chemical sensing needs new microsensor concepts. Applications in this area include environmental monitoring, criminal investigations, and state-of-health monitoring, both for equipment and living things. Chemical microsensors can satisfy sensing needs in the industrial, consumer, aerospace, and defense sectors. The microelectronic chemical-sensor array may address some of these applications. We have fabricated six separate chemical gas sensing areas on the microelectronic chemical sensor array. By using different catalytic metals on the gate areas of the diodes, we can selectively sense several gases.

Testing interconnected VLSI circuits in the Big Viterbi Decoder

NASA Technical Reports Server (NTRS)

Onyszchuk, I. M.

1991-01-01

The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

Design of an MR image processing module on an FPGA chip.

PubMed

Li, Limin; Wyrwicz, Alice M

2015-06-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128×128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments. Copyright © 2015 Elsevier Inc. All rights reserved.

Real-time system for measuring three-dimensional shape of solder bump array by focus using varifocal mirror

NASA Astrophysics Data System (ADS)

Ishii, Akira; Tai, Haruka; Mitsudo, Jun

2007-10-01

This paper describes a real-time system for measuring the three-dimensional shape of solder bumps arrayed on an LSI chip-size-package (CSP) board presented for inspection based on the shape-from-focus technique. It uses a copper-alloy mirror deformed by a piezoelectric actuator as a varifocal mirror enabling a simple, fast, precise focusing mechanism without moving parts to be built. A practical measuring speed of 1.69 s/package for a small CSP board (4 x 4 mm2) was achieved by incorporating an exclusive field programmable gate array processor to calculate focus measure and by constructing a domed array of LEDs as a high-intensity, uniform illumination system so that a fast (150 fps) and high-resolution (1024 x 1024 pixels/frame) CMOS image sensor could be used. Accurate measurements of bump height were also achieved with errors of 10 μm (2σ) meeting the requirements for testing the coplanarity of a bump array.

Dual-Gated Active Metasurface at 1550 nm with Wide (>300°) Phase Tunability.

PubMed

Kafaie Shirmanesh, Ghazaleh; Sokhoyan, Ruzan; Pala, Ragip A; Atwater, Harry A

2018-05-09

Active metasurfaces composed of electrically reconfigurable nanoscale subwavelength antenna arrays can enable real-time control of scattered light amplitude and phase. Achievement of widely tunable phase and amplitude in chip-based active metasurfaces operating at or near 1550 nm wavelength has considerable potential for active beam steering, dynamic hologram rendition, and realization of flat optics with reconfigurable focal lengths. Previously, electrically tunable conducting oxide-based reflectarray metasurfaces have demonstrated dynamic phase control of reflected light with a maximum phase shift of 184° ( Nano Lett. 2016 , 16 , 5319 ). Here, we introduce a dual-gated reflectarray metasurface architecture that enables much wider (>300°) phase tunability. We explore light-matter interactions with dual-gated metasurface elements that incorporate two independent voltage-controlled MOS field effect channels connected in series to form a single metasurface element that enables wider phase tunability. Using indium tin oxide (ITO) as the active metasurface material and a composite hafnia/alumina gate dielectric, we demonstrate a prototype dual-gated metasurface with a continuous phase shift from 0 to 303° and a relative reflectance modulation of 89% under applied voltage bias of 6.5 V.

Multi-element germanium detectors for synchrotron applications

DOE PAGES

Rumaiz, A. K.; Kuczewski, A. J.; Mead, J.; ...

2018-04-27

In this paper, we have developed a series of monolithic multi-element germanium detectors, based on sensor arrays produced by the Forschungzentrum Julich, and on Application-specific integrated circuits (ASICs) developed at Brookhaven. Devices have been made with element counts ranging from 64 to 384. These detectors are being used at NSLS-II and APS for a range of diffraction experiments, both monochromatic and energy-dispersive. Compact and powerful readout systems have been developed, based on the new generation of FPGA system-on-chip devices, which provide closely coupled multi-core processors embedded in large gate arrays. Finally, we will discuss the technical details of the systems,more » and present some of the results from them.« less

Multi-element germanium detectors for synchrotron applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rumaiz, A. K.; Kuczewski, A. J.; Mead, J.

In this paper, we have developed a series of monolithic multi-element germanium detectors, based on sensor arrays produced by the Forschungzentrum Julich, and on Application-specific integrated circuits (ASICs) developed at Brookhaven. Devices have been made with element counts ranging from 64 to 384. These detectors are being used at NSLS-II and APS for a range of diffraction experiments, both monochromatic and energy-dispersive. Compact and powerful readout systems have been developed, based on the new generation of FPGA system-on-chip devices, which provide closely coupled multi-core processors embedded in large gate arrays. Finally, we will discuss the technical details of the systems,more » and present some of the results from them.« less

Design of transient light signal simulator based on FPGA

NASA Astrophysics Data System (ADS)

Kang, Jing; Chen, Rong-li; Wang, Hong

2014-11-01

A design scheme of transient light signal simulator based on Field Programmable gate Array (FPGA) was proposed in this paper. Based on the characteristics of transient light signals and measured feature points of optical intensity signals, a fitted curve was created in MATLAB. And then the wave data was stored in a programmed memory chip AT29C1024 by using SUPERPRO programmer. The control logic was realized inside one EP3C16 FPGA chip. Data readout, data stream cache and a constant current buck regulator for powering high-brightness LEDs were all controlled by FPGA. A 12-Bit multiplying CMOS digital-to-analog converter (DAC) DAC7545 and an amplifier OPA277 were used to convert digital signals to voltage signals. A voltage-controlled current source constituted by a NPN transistor and an operational amplifier controlled LED array diming to achieve simulation of transient light signal. LM3405A, 1A Constant Current Buck Regulator for Powering LEDs, was used to simulate strong background signal in space. Experimental results showed that the scheme as a transient light signal simulator can satisfy the requests of the design stably.

A Reconfigurable Communications System for Small Spacecraft

NASA Technical Reports Server (NTRS)

Chu, Pong P.; Kifle, Muli

2004-01-01

Two trends of NASA missions are the use of multiple small spacecraft and the development of an integrated space network. To achieve these goals, a robust and agile communications system is needed. Advancements in field programmable gate array (FPGA) technology have made it possible to incorporate major communication and network functionalities in FPGA chips; thus this technology has great potential as the basis for a reconfigurable communications system. This report discusses the requirements of future space communications, reviews relevant issues, and proposes a methodology to design and construct a reconfigurable communications system for small scientific spacecraft.

VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.

PubMed

Feng, Lichen; Li, Zunchao; Wang, Yuanfa

2018-02-01

Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three-level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time-frequency domain features reflecting the nonstationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.

A self-timed multipurpose delay sensor for Field Programmable Gate Arrays (FPGAs).

PubMed

Osuna, Carlos Gómez; Ituero, Pablo; López-Vallejo, Marisa

2013-12-20

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor's measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of  ±0.67 °C, over the range of 20-100 °C, employing 20 logic elements with a 2-point calibration.

A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs)

PubMed Central

Osuna, Carlos Gómez; Ituero, Pablo; López-Vallejo, Marisa

2014-01-01

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor's measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of ±0.67 °C, over the range of 20–100 °C, employing 20 logic elements with a 2-point calibration. PMID:24361927

CMOS image sensor with lateral electric field modulation pixels for fluorescence lifetime imaging with sub-nanosecond time response

NASA Astrophysics Data System (ADS)

Li, Zhuo; Seo, Min-Woong; Kagawa, Keiichiro; Yasutomi, Keita; Kawahito, Shoji

2016-04-01

This paper presents the design and implementation of a time-resolved CMOS image sensor with a high-speed lateral electric field modulation (LEFM) gating structure for time domain fluorescence lifetime measurement. Time-windowed signal charge can be transferred from a pinned photodiode (PPD) to a pinned storage diode (PSD) by turning on a pair of transfer gates, which are situated beside the channel. Unwanted signal charge can be drained from the PPD to the drain by turning on another pair of gates. The pixel array contains 512 (V) × 310 (H) pixels with 5.6 × 5.6 µm2 pixel size. The imager chip was fabricated using 0.11 µm CMOS image sensor process technology. The prototype sensor has a time response of 150 ps at 374 nm. The fill factor of the pixels is 5.6%. The usefulness of the prototype sensor is demonstrated for fluorescence lifetime imaging through simulation and measurement results.

ASIC implementation of recursive scaled discrete cosine transform algorithm

NASA Astrophysics Data System (ADS)

On, Bill N.; Narasimhan, Sam; Huang, Victor K.

1994-05-01

A program to implement the Recursive Scaled Discrete Cosine Transform (DCT) algorithm as proposed by H. S. Hou has been undertaken at the Institute of Microelectronics. Implementation of the design was done using top-down design methodology with VHDL (VHSIC Hardware Description Language) for chip modeling. When the VHDL simulation has been satisfactorily completed, the design is synthesized into gates using a synthesis tool. The architecture of the design consists of two processing units together with a memory module for data storage and transpose. Each processing unit is composed of four pipelined stages which allow the internal clock to run at one-eighth (1/8) the speed of the pixel clock. Each stage operates on eight pixels in parallel. As the data flows through each stage, there are various adders and multipliers to transform them into the desired coefficients. The Scaled IDCT was implemented in a similar fashion with the adders and multipliers rearranged to perform the inverse DCT algorithm. The chip has been verified using Field Programmable Gate Array devices. The design is operational. The combination of fewer multiplications required and pipelined architecture give Hou's Recursive Scaled DCT good potential of achieving high performance at a low cost in using Very Large Scale Integration implementation.

Submillimeter-Wave Amplifier Module with Integrated Waveguide Transitions

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Chattopadhyay, Goutam; Pukala, David; Gaier, Todd; Soria, Mary; ManFung, King; Deal, William; Mei, Gerry; Radisic, Vesna; Lai, Richard

2009-01-01

To increase the usefulness of monolithic millimeter-wave integrated circuit (MMIC) components at submillimeter-wave frequencies, a chip has been designed that incorporates two integrated, radial E-plane probes with an MMIC amplifier in between, thus creating a fully integrated waveguide module. The integrated amplifier chip has been fabricated in 35-nm gate length InP high-electron-mobility-transistor (HEMT) technology. The radial probes were mated to grounded coplanar waveguide input and output lines in the internal amplifier. The total length of the internal HEMT amplifier is 550 m, while the total integrated chip length is 1,085 m. The chip thickness is 50 m with the chip width being 320 m. The internal MMIC amplifier is biased through wire-bond connections to the gates and drains of the chip. The chip has 3 stages, employing 35-nm gate length transistors in each stage. Wire bonds from the DC drain and gate pads are connected to off-chip shunt 51-pF capacitors, and additional off-chip capacitors and resistors are added to the gate and drain bias lines for low-frequency stability of the amplifier. Additionally, bond wires to the grounded coplanar waveguide pads at the RF input and output of the internal amplifier are added to ensure good ground connections to the waveguide package. The S-parameters of the module, not corrected for input or output waveguide loss, are measured at the waveguide flange edges. The amplifier module has over 10 dB of gain from 290 to 330 GHz, with a peak gain of over 14 dB at 307 GHz. The WR2.2 waveguide cutoff is again observed at 268 GHz. The module is biased at a drain current of 27 mA, a drain voltage of 1.24 V, and a gate voltage of +0.21 V. Return loss of the module is very good between 5 to 25 dB. This result illustrates the usefulness of the integrated radial probe transition, and the wide (over 10-percent) bandwidth that one can expect for amplifier modules with integrated radial probes in the submillimeter-regime (>300 GHz).

Miniature MMIC Low Mass/Power Radiometer Modules for the 180 GHz GeoSTAR Array

NASA Technical Reports Server (NTRS)

Kangaslahti, Pekka; Tanner, Alan; Pukala, David; Lambrigtsen, Bjorn; Lim, Boon; Mei, Xiaobing; Lai, Richard

2010-01-01

We have developed and demonstrated miniature 180 GHz Monolithic Microwave Integrated Circuit (MMIC) radiometer modules that have low noise temperature, low mass and low power consumption. These modules will enable the Geostationary Synthetic Thinned Aperture Radiometer (GeoSTAR) of the Precipitation and All-weather Temperature and Humidity (PATH) Mission for atmospheric temperature and humidity profiling. The GeoSTAR instrument has an array of hundreds of receivers. Technology that was developed included Indium Phosphide (InP) MMIC Low Noise Amplifiers (LNAs) and second harmonic MMIC mixers and I-Q mixers, surface mount Multi-Chip Module (MCM) packages at 180 GHz, and interferometric array at 180 GHz. A complete MMIC chip set for the 180 GHz receiver modules (LNAs and I-Q Second harmonic mixer) was developed. The MMIC LNAs had more than 50% lower noise temperature (NT=300K) than previous state-of-art and MMIC I-Q mixers demonstrated low LO power (3 dBm). Two lots of MMIC wafers were processed with very high DC transconductance of up to 2800 mS/mm for the 35 nm gate length devices. Based on these MMICs a 180 GHz Multichip Module was developed that had a factor of 100 lower mass/volume (16x18x4.5 mm3, 3g) than previous generation 180 GHz receivers.

Detector and energy analyzer for energetic-hydrogen in beams and plasmas

DOEpatents

Bastasz, Robert J.; Hughes, Robert C.; Wampler, William R.

1988-01-01

A detector for detecting energetic hydrogen ions and atoms ranging in energy from about 1 eV up to 1 keV in an evacuated environment includes a Schottky diode with a palladium or palladium-alloy gate metal applied to a silicondioxide layer on an n-silicon substrate. An array of the energetic-hydrogen detectors having a range of energy sensitivities form a plasma energy analyzer having a rapid response time and a sensitivity for measuring fluxes of energetic hydrogen. The detector is sensitive to hydrogen and its isotopes but is insensitive to non-hydrogenic particles. The array of energetic-hydrogen detectors can be formed on a single silicon chip, with thin-film layers of gold metal applied in various thicknesses to successive detectors in the array. The gold layers serve as particle energy-filters so that each detector is sensitive to a different range of hydrogen energies.

Detector and energy analyzer for energetic-hydrogen in beams and plasmas

DOEpatents

Bastasz, R.J.; Hughes, R.C.; Wampler, W.R.

1988-11-01

A detector for detecting energetic hydrogen ions and atoms ranging in energy from about 1 eV up to 1 keV in an evacuated environment includes a Schottky diode with a palladium or palladium-alloy gate metal applied to a silicon-dioxide layer on an n-silicon substrate. An array of the energetic-hydrogen detectors having a range of energy sensitivities form a plasma energy analyzer having a rapid response time and a sensitivity for measuring fluxes of energetic hydrogen. The detector is sensitive to hydrogen and its isotopes but is insensitive to non-hydrogenic particles. The array of energetic-hydrogen detectors can be formed on a single silicon chip, with thin-film layers of gold metal applied in various thicknesses to successive detectors in the array. The gold layers serve as particle energy-filters so that each detector is sensitive to a different range of hydrogen energies. 4 figs.

Blanket Gate Would Address Blocks Of Memory

NASA Technical Reports Server (NTRS)

Lambe, John; Moopenn, Alexander; Thakoor, Anilkumar P.

1988-01-01

Circuit-chip area used more efficiently. Proposed gate structure selectively allows and restricts access to blocks of memory in electronic neural-type network. By breaking memory into independent blocks, gate greatly simplifies problem of reading from and writing to memory. Since blocks not used simultaneously, share operational amplifiers that prompt and read information stored in memory cells. Fewer operational amplifiers needed, and chip area occupied reduced correspondingly. Cost per bit drops as result.

Characterization and recovery of Deep Sub Micron (DSM) technologies behavior under radiation

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Wang, Xiao

2005-01-01

This paper serves a twofold purpose: characterize the behavior of a reconfigurable chip exposed to radiation; and demonstrate a method for functionality recovery due to Total Ionizing Dose (TID) effects. The experiments are performed using a PL developed reconfigurable device, a Field Programmable Transistor Array (FPTA). The paper initially describes experiments on the characterization of the NMOS transistor behavior for TID values up to 300krad. The behavior of analog and digital circuits downloaded onto the FPTA chip is also assessed for TID effects. This paper also presents a novel approach for circuit functionality recovery due to radiation effects based on Evolvable Hardware. The key idea is to reconfigure a programmable device, in-situ, to compensate, or bypass its degraded or damaged components. Experiments with total radiation dose up to 300kRad show that while the functionality of a variety of circuits, including digital gates, a rectifier and a Digital to Analog Converter implemented on a FPTA-2 chip is degraded/lost at levels before 200kRad, the correct functionality can be recovered through the proposed evolutionary approach and the chips are able to survive higher radiation, for several functions in excess of total radiation dose of 250kRad.

Creating an Assured Joint DOD and Interagency Interoperable Net-Centric Enterprise. Report of the Defense Science Board Task Force on Achieving Interoperability in a Net-Centric Environment

DTIC Science & Technology

2009-03-01

policy, elliptic curve public key cryptography using the 256 -bit prime modulus elliptic curve as specified in FIPS-186-2 and SHA - 256 are appropriate for...publications/fips/fips186-2/fips186-2-change1.pdf 76 I P ART I . CH A PT E R 5 Hashing via the Secure Hash Algorithm (using SHA - 256 and...lithography and processing techniques. Field programmable gate arrays ( FPGAs ) are a chip design of interest. These devices are extensively used in

Digital Filter ASIC for NASA Deep Space Radio Science

NASA Technical Reports Server (NTRS)

Kowalski, James E.

1995-01-01

This paper is about the implementation of an 80 MHz, 16-bit, multi-stage digital filter to decimate by 1600, providing a 50 kHz output with bandpass ripple of less than +/-0.1 dB. The chip uses two decimation by five units and six decimations by two executed by a single decimation by two units. The six decimations by two consist of six halfband filters, five having 30-taps and one having 51-taps. Use of a 16x16 register file for the digital delay lines enables implementation in the Vitesse 350K gate array.

Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays.

PubMed

Sánchez-Azqueta, Carlos; Goll, Bernhard; Celma, Santiago; Zimmermann, Horst

2016-05-25

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of -26.0 dBm and -25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10(-9) ) with an energy efficiency of 2 pJ/bit.

Special purpose computer system with highly parallel pipelines for flow visualization using holography technology

NASA Astrophysics Data System (ADS)

Masuda, Nobuyuki; Sugie, Takashige; Ito, Tomoyoshi; Tanaka, Shinjiro; Hamada, Yu; Satake, Shin-ichi; Kunugi, Tomoaki; Sato, Kazuho

2010-12-01

We have designed a PC cluster system with special purpose computer boards for visualization of fluid flow using digital holographic particle tracking velocimetry (DHPTV). In this board, there is a Field Programmable Gate Array (FPGA) chip in which is installed a pipeline for calculating the intensity of an object from a hologram by fast Fourier transform (FFT). This cluster system can create 1024 reconstructed images from a 1024×1024-grid hologram in 0.77 s. It is expected that this system will contribute to the analysis of fluid flow using DHPTV.

A Hardware Platform for Tuning of MEMS Devices Using Closed-Loop Frequency Response

NASA Technical Reports Server (NTRS)

Ferguson, Michael I.; MacDonald, Eric; Foor, David

2005-01-01

We report on the development of a hardware platform for integrated tuning and closed-loop operation of MEMS gyroscopes. The platform was developed and tested for the second generation JPL/Boeing Post-Resonator MEMS gyroscope. The control of this device is implemented through a digital design on a Field Programmable Gate Array (FPGA). A software interface allows the user to configure, calibrate, and tune the bias voltages on the micro-gyro. The interface easily transitions to an embedded solution that allows for the miniaturization of the system to a single chip.

Electron Beam/Optical Hybrid Lithography For The Production Of Gallium Arsenide Monolithic Microwave Integrated Circuits (Mimics)

NASA Astrophysics Data System (ADS)

Nagarajan, Rao M.; Rask, Steven D.

1988-06-01

A hybrid lithography technique is described in which selected levels are fabricated by high resolution direct write electron beam lithography and all other levels are fabricated optically. This technique permits subhalf micron geometries and the site-by-site alignment for each field written by electron beam lithography while still maintaining the high throughput possible with optical lithography. The goal is to improve throughput and reduce overall cost of fabricating MIMIC GaAS chips without compromising device performance. The lithography equipment used for these experiments is the Cambridge Electron beam vector scan system EBMF 6.4 capable of achieving ultra high current densities with a beam of circular cross section and a gaussian intensity profile operated at 20 kev. The optical aligner is a Karl Suss Contact aligner. The flexibility of the Cambridge electron beam system is matched to the less flexible Karl Suss contact aligner. The lithography related factors, such as image placement, exposure and process related analyses, which influence overlay, pattern quality and performance, are discussed. A process chip containing 3.2768mm fields in an eleven by eleven array was used for alignment evaluation on a 3" semi-insulating GaAS wafer. Each test chip contained five optical verniers and four Prometrix registration marks per field along with metal bumps for alignment marks. The process parameters for these chips are identical to those of HEMT/epi-MESFET ohmic contact and gate layer processes. These layers were used to evaluate the overlay accuracy because of their critical alignment and dimensional control requirements. Two cases were examined: (1) Electron beam written gate layers aligned to optically imaged ohmic contact layers and (2) Electron beam written gate layers aligned to electron beam written ohmic contact layers. The effect of substrate charging by the electron beam is also investigated. The resulting peak overlay error accuracies are: (1) Electron beam to optical with t 0.2μm (2 sigma) and (2) Electron beam to electron beam with f 0.lμm (2 sigma). These results suggest that the electron beam/optical hybrid lithography techniques could be used for MIMIC volume production as alignment tolerances required by GaAS chips are met in both cases. These results are discussed in detail.

Slow Controls Using the Axiom M5235BCC

NASA Astrophysics Data System (ADS)

Hague, Tyler

2008-10-01

The Forward Vertex Detector group at PHENIX plans to adopt the Axiom M5235 Business Card Controller for use as slow controls. It is also being evaluated for slow controls on FermiLab e906. This controller features the Freescale MCF5235 microprocessor. It also has three parallel buses, these being the MCU port, BUS port, and enhanced Time Processing Unit (eTPU) port. The BUS port uses a chip select module with three external chip selects to communicate with peripherals. This will be used to communicate with and configure Field Programmable Gate Arrays (FPGAs). The controller also has an Ethernet port which can use several different protocols such as TCP and UDP. This will be used to transfer files with computers on a network. The M5235 Business Card Controller will be placed in a VME crate along with VME card and a Spartan-3 FPGA.

Solid state lighting component

DOEpatents

Yuan, Thomas; Keller, Bernd; Tarsa, Eric; Ibbetson, James; Morgan, Frederick; Dowling, Kevin; Lys, Ihor

2017-10-17

An LED component according to the present invention comprising an array of LED chips mounted on a submount with the LED chips capable of emitting light in response to an electrical signal. The array can comprise LED chips emitting at two colors of light wherein the LED component emits light comprising the combination of the two colors of light. A single lens is included over the array of LED chips. The LED chip array can emit light of greater than 800 lumens with a drive current of less than 150 milli-Amps. The LED chip component can also operate at temperatures less than 3000 degrees K. In one embodiment, the LED array is in a substantially circular pattern on the submount.

Assurance of Complex Electronics. What Path Do We Take?

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled in software, such as communication protocols. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of "software-like" bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and "bugs" can be detected earlier in the development cycle, thus creating a development process for CE that will be easily maintained and configurable based on the device used.

Trapping and Collection of Lymphocytes Using Microspot Array Chip and Magnetic Beads

NASA Astrophysics Data System (ADS)

Hashioka, Shingi; Obata, Tsutomu; Tokimitsu, Yoshiharu; Fujiki, Satoshi; Nakazato, Hiroyoshi; Muraguchi, Atsushi; Kishi, Hiroyuki; Tanino, Katsumi

2006-04-01

A microspot array chip, which has microspots of a magnetic thin film patterned on a glass substrate, was fabricated for trapping individual cells and for measuring their cellular response. The chip was easily fabricated by conventional semiconductor fabrication techniques on a mass production level as a disposable medical device. When a solution of lymphocyte-bound-magnetic beads was poured into the magnetized chip, each lymphocyte was trapped on each microspot of the magnetic thin film. The trapped cells were easily recovered from the chip using a micromanipulator. The micro-spot array chip can be utilized for arraying live cells and for measuring the response of each cell. The chip will be useful for preparing on array of different kinds of cells and for analyzing cellular response at the single cell level. The chip will be particularly useful for detecting antigen-specific B-lymphocytes and antigen-specific antibody complementary deoxyribonucleic acid (cDNA).

Using Spare Logic Resources To Create Dynamic Test Points

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor

2011-01-01

A technique has been devised to enable creation of a dynamic set of test points in an embedded digital electronic system. As a result, electronics contained in an application specific circuit [e.g., gate array, field programmable gate array (FPGA)] can be internally probed, even when contained in a closed housing during all phases of test. In the present technique, the test points are not fixed and limited to a small number; the number of test points can vastly exceed the number of buffers or pins, resulting in a compact footprint. Test points are selected by means of spare logic resources within the ASIC(s) and/or FPGA(s). A register is programmed with a command, which is used to select the signals that are sent off-chip and out of the housing for monitoring by test engineers and external test equipment. The register can be commanded by any suitable means: for example, it could be commanded through a command port that would normally be used in the operation of the system. In the original application of the technique, commanding of the register is performed via a MIL-STD-1553B communication subsystem.

Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

NASA Astrophysics Data System (ADS)

Yussup, N.; Ibrahim, M. M.; Lombigit, L.; Rahman, N. A. A.; Zin, M. R. M.

2014-02-01

Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of data acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed.

Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yussup, N.; Ibrahim, M. M.; Lombigit, L.

Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of datamore » acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed.« less

Silicon ball grid array chip carrier

DOEpatents

Palmer, David W.; Gassman, Richard A.; Chu, Dahwey

2000-01-01

A ball-grid-array integrated circuit (IC) chip carrier formed from a silicon substrate is disclosed. The silicon ball-grid-array chip carrier is of particular use with ICs having peripheral bond pads which can be reconfigured to a ball-grid-array. The use of a semiconductor substrate such as silicon for forming the ball-grid-array chip carrier allows the chip carrier to be fabricated on an IC process line with, at least in part, standard IC processes. Additionally, the silicon chip carrier can include components such as transistors, resistors, capacitors, inductors and sensors to form a "smart" chip carrier which can provide added functionality and testability to one or more ICs mounted on the chip carrier. Types of functionality that can be provided on the "smart" chip carrier include boundary-scan cells, built-in test structures, signal conditioning circuitry, power conditioning circuitry, and a reconfiguration capability. The "smart" chip carrier can also be used to form specialized or application-specific ICs (ASICs) from conventional ICs. Types of sensors that can be included on the silicon ball-grid-array chip carrier include temperature sensors, pressure sensors, stress sensors, inertia or acceleration sensors, and/or chemical sensors. These sensors can be fabricated by IC processes and can include microelectromechanical (MEM) devices.

Autonomous Magnetic Microrobots by Navigating Gates for Multiple Biomolecules Delivery.

PubMed

Hu, Xinghao; Lim, Byeonghwa; Torati, Sri Ramulu; Ding, Junjia; Novosad, Valentine; Im, Mi-Young; Reddy, Venu; Kim, Kunwoo; Jung, Eunjoo; Shawl, Asif Iqbal; Kim, Eunjoo; Kim, CheolGi

2018-05-08

The precise delivery of biofunctionalized matters is of great interest from the fundamental and applied viewpoints. In spite of significant progress achieved during the last decade, a parallel and automated isolation and manipulation of rare analyte, and their simultaneous on-chip separation and trapping, still remain challenging. Here, a universal micromagnet junction for self-navigating gates of microrobotic particles to deliver the biomolecules to specific sites using a remote magnetic field is described. In the proposed concept, the nonmagnetic gap between the lithographically defined donor and acceptor micromagnets creates a crucial energy barrier to restrict particle gating. It is shown that by carefully designing the geometry of the junctions, it becomes possible to deliver multiple protein-functionalized carriers in high resolution, as well as MCF-7 and THP-1 cells from the mixture, with high fidelity and trap them in individual apartments. Integration of such junctions with magnetophoretic circuitry elements could lead to novel platforms without retrieving for the synchronous digital manipulation of particles/biomolecules in microfluidic multiplex arrays for next-generation biochips. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Automating analog design: Taming the shrew

NASA Technical Reports Server (NTRS)

Barlow, A.

1990-01-01

The pace of progress in the design of integrated circuits continues to amaze observers inside and outside of the industry. Three decades ago, a 50 transistor chip was a technological wonder. Fifteen year later, a 5000 transistor device would 'wow' the crowds. Today, 50,000 transistor chips will earn a 'not too bad' assessment, but it takes 500,000 to really leave an impression. In 1975 a typical ASIC device had 1000 transistors, took one year to first samples (and two years to production) and sold for about 5 cents per transistor. Today's 50,000 transistor gate array takes about 4 months from spec to silicon, works the first time, and sells for about 0.02 cents per transistor. Fifteen years ago, the single most laborious and error prone step in IC design was the physical layout. Today, most IC's never see the hand of a layout designer: and automatic place and route tool converts the engineer's computer captured schematic to a complete physical design using a gate array or a library of standard cells also created by software rather than by designers. CAD has also been a generous benefactor to the digital design process. The architect of today's digital systems creates the design using an RTL or other high level simulator. Then the designer pushes a button to invoke the logic synthesizer-optimizer tool. A fault analyzer checks the result for testability and suggests where scan based cells will improve test coverage. One obstinate holdout amidst this parade of progress is the automation of analog design and its reduction to semi-custom techniques. This paper investigates the application of CAD techniques to analog design.

Aeroflex Technology as Class-Y Demonstrator

NASA Technical Reports Server (NTRS)

Suh, Jong-ook; Agarwal, Shri; Popelar, Scott

2014-01-01

Modern space field programmable gate array (FPGA) devices with increased functional density and operational frequency, such as Xilinx Virtex 4 (V4) and S (V5), are packaged in non-hermetic ceramic flip chip forms. These next generation space parts were not qualified to the MIL-PRF-38535 Qualified Manufacturer Listing (QML) class-V when they were released because class-V was only intended for hermetic parts. In order to bring Xilinx V5 type packages into the QML system, it was suggested that class-Y be set up as a new category. From 2010 through 2014, a JEDEC G12 task group developed screening and qualification requirements for Class-Y products. The Document Standardization Division of the Defense Logistics Agency (DLA) has completed an engineering practice study. In parallel with the class-Y efforts, the NASA Electronic Parts and Packaging (NEPP) program has funded JPL to study potential reliability issues of the class-Y products. The major hurdle of this task was the absence of adequate research samples. Figure 1-1 shows schematic diagrams of typical structures of class-Y type products. Typically, class-Y products are either in ceramic flip chip column grid array (CGA) or land grid array (LGA) form. In class-Y packages, underfill and heat spread adhesive materials are directly exposed to the spacecraft environment due to their non-hermeticity. One of the concerns originally raised was that the underfill material could degrade due to the spacecraft environment and negatively impact the reliability of the package. In order to study such issues, it was necessary to use ceramic daisy chain flip chip package samples so that continuity of flip chip solder bumps could be monitored during the reliability tests. However, none of the commercially available class-Y daisy chain parts had electrical connections through flip chip solder bumps; only solder columns were daisy chained, which made it impossible to test continuity of flip chip solder bumps without using extremely costly functional parts. Among space parts manufacturers who were interested in producing class-Y products, Aeroflex Microelectronic Solutions-HiRel had been developing assembly processes using their internal R&D classy type samples. In early 2012, JPL and Aeroflex initiated a collaboration to study reliability of the Aeroflex technology as a class-Y demonstrator.

Radiation-hardened optically reconfigurable gate array exploiting holographic memory characteristics

NASA Astrophysics Data System (ADS)

Seto, Daisaku; Watanabe, Minoru

2015-09-01

In this paper, we present a proposal for a radiation-hardened optically reconfigurable gate array (ORGA). The ORGA is a type of field programmable gate array (FPGA). The ORGA configuration can be executed by the exploitation of holographic memory characteristics even if 20% of the configuration data are damaged. Moreover, the optoelectronic technology enables the high-speed reconfiguration of the programmable gate array. Such a high-speed reconfiguration can increase the radiation tolerance of its programmable gate array to 9.3 × 104 times higher than that of current FPGAs. Through experimentation, this study clarified the configuration dependability using the impulse-noise emulation and high-speed configuration capabilities of the ORGA with corrupt configuration contexts. Moreover, the radiation tolerance of the programmable gate array was confirmed theoretically through probabilistic calculation.

Radar wideband digital beamforming based on time delay and phase compensation

NASA Astrophysics Data System (ADS)

Fu, Wei; Jiang, Defu

2018-07-01

In conventional phased array radars, analogue time delay devices and phase shifters have been used for wideband beamforming. These methods suffer from insertion losses, gain mismatches and delay variations, and they occupy a large chip area. To solve these problems, a compact architecture of digital array antennas based on subarrays was considered. In this study, the receiving beam patterns of wideband linear frequency modulation (LFM) signals were constructed by applying analogue stretch processing via mixing with delayed reference signals at the subarray level. Subsequently, narrowband digital time delaying and phase compensation of the tone signals were implemented with reduced arithmetic complexity. Due to the differences in amplitudes, phases and time delays between channels, severe performance degradation of the beam patterns occurred without corrections. To achieve good beamforming performance, array calibration was performed in each channel to adjust the amplitude, frequency and phase of the tone signal. Using a field-programmable gate array, wideband LFM signals and finite impulse response filters with continuously adjustable time delays were implemented in a polyphase structure. Simulations and experiments verified the feasibility and effectiveness of the proposed digital beamformer.

Fabrication of five-level ultraplanar micromirror arrays by flip-chip assembly

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper reports a detailed study of the fabrication of various piston, torsion, and cantilever style micromirror arrays using a novel, simple, and inexpensive flip-chip assembly technique. Several rectangular and polar arrays were commercially prefabricated in the MUMPs process and then flip-chip bonded to form advanced micromirror arrays where adverse effects typically associated with surface micromachining were removed. These arrays were bonded by directly fusing the MUMPs gold layers with no complex preprocessing. The modules were assembled using a computer-controlled, custom-built flip-chip bonding machine. Topographically opposed bond pads were designed to correct for slight misalignment errors during bonding and typically result in less than 2 micrometers of lateral alignment error. Although flip-chip micromirror performance is briefly discussed, the means used to create these arrays is the focus of the paper. A detailed study of flip-chip process yield is presented which describes the primary failure mechanisms for flip-chip bonding. Studies of alignment tolerance, bonding force, stress concentration, module planarity, bonding machine calibration techniques, prefabrication errors, and release procedures are presented in relation to specific observations in process yield. Ultimately, the standard thermo-compression flip-chip assembly process remains a viable technique to develop highly complex prototypes of advanced micromirror arrays.

The initial characterization of a revised 10-Gsps analog-to-digital converter board for radio telescopes

NASA Astrophysics Data System (ADS)

Jiango, Homin; Liuo, Howard; Guzzino, Kim

2016-07-01

In this study, the design of a 4 bit, 10-gigasamples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was revised, manufactured, and tested. It is used for digitizing radio telescopes. An Adsantec ANST7120-KMA flash ADC chip was used, as in the original design. Associated with the field-programmable gate array platform developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the developed PCBA provides data acquisition systems with a wider bandwidth and simplifies the intermediate frequency section. The current version of the PCBA exhibits an analog bandwidth of up to 10 GHz (3 dB loss), and the chip exhibits an analog bandwidth of up to 18 GHz. This facilitates second and third Nyquist sampling. The following worstcase performance parameters were obtained from the revised PCBA at over 5 GHz: spurious-free dynamic range of 12 dB, signal-to-noise and distortion ratio of 2 dB, and effective number of bits of 0.7. The design bugs in the ADC chip caused the poor performance. The vendor created a new batch run and confirmed that the ADC chips of the new batch will meet the specifications addressed in its data sheet.

Data Acquisition System for Silicon Ultra Fast Cameras for Electron and Gamma Sources in Medical Applications (sucima Imager)

NASA Astrophysics Data System (ADS)

Czermak, A.; Zalewska, A.; Dulny, B.; Sowicki, B.; Jastrząb, M.; Nowak, L.

2004-07-01

The needs for real time monitoring of the hadrontherapy beam intensity and profile as well as requirements for the fast dosimetry using Monolithic Active Pixel Sensors (MAPS) forced the SUCIMA collaboration to the design of the unique Data Acquisition System (DAQ SUCIMA Imager). The DAQ system has been developed on one of the most advanced XILINX Field Programmable Gate Array chip - VERTEX II. The dedicated multifunctional electronic board for the detector's analogue signals capture, their parallel digital processing and final data compression as well as transmission through the high speed USB 2.0 port has been prototyped and tested.

Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays

PubMed Central

Sánchez-Azqueta, Carlos; Goll, Bernhard; Celma, Santiago; Zimmermann, Horst

2016-01-01

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of −26.0 dBm and −25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10−9 ) with an energy efficiency of 2 pJ/bit. PMID:27231915

Noise-margin limitations on gallium-arsenide VLSI

NASA Technical Reports Server (NTRS)

Long, Stephen I.; Sundaram, Mani

1988-01-01

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

Another expert system rule inference based on DNA molecule logic gates

NASA Astrophysics Data System (ADS)

WÄ siewicz, Piotr

2013-10-01

With the help of silicon industry microfluidic processors were invented utilizing nano membrane valves, pumps and microreactors. These so called lab-on-a-chips combined together with molecular computing create molecular-systems-ona- chips. This work presents a new approach to implementation of molecular inference systems. It requires the unique representation of signals by DNA molecules. The main part of this work includes the concept of logic gates based on typical genetic engineering reactions. The presented method allows for constructing logic gates with many inputs and for executing them at the same quantity of elementary operations, regardless of a number of input signals. Every microreactor of the lab-on-a-chip performs one unique operation on input molecules and can be connected by dataflow output-input connections to other ones.

Three Realizations and Comparison of Hardware for Piezoresistive Tactile Sensors

PubMed Central

Vidal-Verdú, Fernando; Oballe-Peinado, Óscar; Sánchez-Durán, José A.; Castellanos-Ramos, Julián; Navas-González, Rafael

2011-01-01

Tactile sensors are basically arrays of force sensors that are intended to emulate the skin in applications such as assistive robotics. Local electronics are usually implemented to reduce errors and interference caused by long wires. Realizations based on standard microcontrollers, Programmable Systems on Chip (PSoCs) and Field Programmable Gate Arrays (FPGAs) have been proposed by the authors for the case of piezoresistive tactile sensors. The solution employing FPGAs is especially relevant since their performance is closer to that of Application Specific Integrated Circuits (ASICs) than that of the other devices. This paper presents an implementation of such an idea for a specific sensor. For the purpose of comparison, the circuitry based on the other devices is also made for the same sensor. This paper discusses the implementation issues, provides details regarding the design of the hardware based on the three devices and compares them. PMID:22163797

Dedicated hardware processor and corresponding system-on-chip design for real-time laser speckle imaging.

PubMed

Jiang, Chao; Zhang, Hongyan; Wang, Jia; Wang, Yaru; He, Heng; Liu, Rui; Zhou, Fangyuan; Deng, Jialiang; Li, Pengcheng; Luo, Qingming

2011-11-01

Laser speckle imaging (LSI) is a noninvasive and full-field optical imaging technique which produces two-dimensional blood flow maps of tissues from the raw laser speckle images captured by a CCD camera without scanning. We present a hardware-friendly algorithm for the real-time processing of laser speckle imaging. The algorithm is developed and optimized specifically for LSI processing in the field programmable gate array (FPGA). Based on this algorithm, we designed a dedicated hardware processor for real-time LSI in FPGA. The pipeline processing scheme and parallel computing architecture are introduced into the design of this LSI hardware processor. When the LSI hardware processor is implemented in the FPGA running at the maximum frequency of 130 MHz, up to 85 raw images with the resolution of 640×480 pixels can be processed per second. Meanwhile, we also present a system on chip (SOC) solution for LSI processing by integrating the CCD controller, memory controller, LSI hardware processor, and LCD display controller into a single FPGA chip. This SOC solution also can be used to produce an application specific integrated circuit for LSI processing.

Fully chip-embedded automation of a multi-step lab-on-a-chip process using a modularized timer circuit.

PubMed

Kang, Junsu; Lee, Donghyeon; Heo, Young Jin; Chung, Wan Kyun

2017-11-07

For highly-integrated microfluidic systems, an actuation system is necessary to control the flow; however, the bulk of actuation devices including pumps or valves has impeded the broad application of integrated microfluidic systems. Here, we suggest a microfluidic process control method based on built-in microfluidic circuits. The circuit is composed of a fluidic timer circuit and a pneumatic logic circuit. The fluidic timer circuit is a serial connection of modularized timer units, which sequentially pass high pressure to the pneumatic logic circuit. The pneumatic logic circuit is a NOR gate array designed to control the liquid-controlling process. By using the timer circuit as a built-in signal generator, multi-step processes could be done totally inside the microchip without any external controller. The timer circuit uses only two valves per unit, and the number of process steps can be extended without limitation by adding timer units. As a demonstration, an automation chip has been designed for a six-step droplet treatment, which entails 1) loading, 2) separation, 3) reagent injection, 4) incubation, 5) clearing and 6) unloading. Each process was successfully performed for a pre-defined step-time without any external control device.

A 256-channel, high throughput and precision time-to-digital converter with a decomposition encoding scheme in a Kintex-7 FPGA

NASA Astrophysics Data System (ADS)

Song, Z.; Wang, Y.; Kuang, J.

2018-05-01

Field Programmable Gate Arrays (FPGAs) made with 28 nm and more advanced process technology have great potentials for implementation of high precision time-to-digital convertors (TDC), because the delay cells in the tapped delay line (TDL) used for time interpolation are getting smaller and smaller. However, the bubble problems in the TDL status are becoming more complicated, which make it difficult to achieve TDCs on these chips with a high time precision. In this paper, we are proposing a novel decomposition encoding scheme, which not only can solve the bubble problem easily, but also has a high encoding efficiency. The potential of these chips to realize TDC can be fully released with the scheme. In a Xilinx Kintex-7 FPGA chip, we implemented a TDC system with 256 TDC channels, which doubles the number of TDC channels that our previous technique could achieve. Performances of all these TDC channels are evaluated. The average RMS time precision among them is 10.23 ps in the time-interval measurement range of (0–10 ns), and their measurement throughput reaches 277 M measures per second.

Meeting critical gate linewidth control needs at the 65 nm node

NASA Astrophysics Data System (ADS)

Mahorowala, Arpan; Halle, Scott; Gabor, Allen; Chu, William; Barberet, Alexandra; Samuels, Donald; Abdo, Amr; Tsou, Len; Yan, Wendy; Iseda, Seiji; Patel, Kaushal; Dirahoui, Bachir; Nomura, Asuka; Ahsan, Ishtiaq; Azam, Faisal; Berg, Gary; Brendler, Andrew; Zimmerman, Jeffrey; Faure, Tom

2006-03-01

With the nominal gate length at the 65 nm node being only 35 nm, controlling the critical dimension (CD) in polysilicon to within a few nanometers is essential to achieve a competitive power-to-performance ratio. Gate linewidths must be controlled, not only at the chip level so that the chip performs as the circuit designers and device engineers had intended, but also at the wafer level so that more chips with the optimum power-to-performance ratio are manufactured. Achieving tight across-chip linewidth variation (ACLV) and chip mean variation (CMV) is possible only if the mask-making, lithography, and etching processes are all controlled to very tight specifications. This paper identifies the various ACLV and CMV components, describes their root causes, and discusses a methodology to quantify them. For example, the site-to-site ACLV component is divided into systematic and random sub-components. The systematic component of the variation is attributed in part to pattern density variation across the field, and variation in exposure dose across the slit. The paper demonstrates our team's success in achieving the tight gate CD tolerances required for 65 nm technology. Certain key challenges faced, and methods employed to overcome them are described. For instance, the use of dose-compensation strategies to correct the small but systematic CD variations measured across the wafer, is described. Finally, the impact of immersion lithography on both ACLV and CMV is briefly discussed.

Photosensitive biosensor array system using optical addressing without an addressing circuit on array biochips

NASA Astrophysics Data System (ADS)

Ahn, Chang-Geun; Ah, Chil Seong; Kim, Tae-Youb; Park, Chan Woo; Yang, Jong-Heon; Kim, Ansoon; Sung, Gun Yong

2010-09-01

This paper introduces a photosensitive biosensor array system with a simple photodiode array that detects photocurrent changes caused by reactions between probe and target molecules. Using optical addressing, the addressing circuit on the array chip is removed for low-cost application, and real cell addressing is achieved using an externally located computer-controllable light-emitting diode array module. The fabricated biosensor array chip shows a good dynamic range of 1-100 ng/mL under prostate-specific antigen detection, with an on-chip resolution of roughly 1 ng/mL.

Carbon nanotube-based three-dimensional monolithic optoelectronic integrated system

NASA Astrophysics Data System (ADS)

Liu, Yang; Wang, Sheng; Liu, Huaping; Peng, Lian-Mao

2017-06-01

Single material-based monolithic optoelectronic integration with complementary metal oxide semiconductor-compatible signal processing circuits is one of the most pursued approaches in the post-Moore era to realize rapid data communication and functional diversification in a limited three-dimensional space. Here, we report an electrically driven carbon nanotube-based on-chip three-dimensional optoelectronic integrated circuit. We demonstrate that photovoltaic receivers, electrically driven transmitters and on-chip electronic circuits can all be fabricated using carbon nanotubes via a complementary metal oxide semiconductor-compatible low-temperature process, providing a seamless integration platform for realizing monolithic three-dimensional optoelectronic integrated circuits with diversified functionality such as the heterogeneous AND gates. These circuits can be vertically scaled down to sub-30 nm and operates in photovoltaic mode at room temperature. Parallel optical communication between functional layers, for example, bottom-layer digital circuits and top-layer memory, has been demonstrated by mapping data using a 2 × 2 transmitter/receiver array, which could be extended as the next generation energy-efficient signal processing paradigm.

System Design of One-chip Wave Particle Interaction Analyzer for SCOPE mission.

NASA Astrophysics Data System (ADS)

Fukuhara, Hajime; Ueda, Yoshikatsu; Kojima, Hiro; Yamakawa, Hiroshi

In past science spacecrafts such like GEOTAIL, we usually capture electric and magnetic field waveforms and observe energetic eletron and ion particles as velocity distributions by each sensor. We analyze plasma wave-particle interactions by these respective data and the discussions are sometimes restricted by the difference of time resolution and by the data loss in desired regions. One-chip Wave Particle Interaction Analyzer (OWPIA) conducts direct quantitative observations of wave-particle interaction by direct 'E dot v' calculation on-board. This new instruments have a capability to use all plasma waveform data and electron particle informations. In the OWPIA system, we have to calibrate the digital observation data and transform the same coordinate system. All necessary calculations are processed in Field Programmable Gate Array(FPGA). In our study, we introduce a basic concept of the OWPIA system and a optimization method for each calculation functions installed in FPGA. And we also discuss the process speed, the FPGA utilization efficiency, the total power consumption.

Universal microfluidic automaton for autonomous sample processing: application to the Mars Organic Analyzer.

PubMed

Kim, Jungkyu; Jensen, Erik C; Stockton, Amanda M; Mathies, Richard A

2013-08-20

A fully integrated multilayer microfluidic chemical analyzer for automated sample processing and labeling, as well as analysis using capillary zone electrophoresis is developed and characterized. Using lifting gate microfluidic control valve technology, a microfluidic automaton consisting of a two-dimensional microvalve cellular array is fabricated with soft lithography in a format that enables facile integration with a microfluidic capillary electrophoresis device. The programmable sample processor performs precise mixing, metering, and routing operations that can be combined to achieve automation of complex and diverse assay protocols. Sample labeling protocols for amino acid, aldehyde/ketone and carboxylic acid analysis are performed automatically followed by automated transfer and analysis by the integrated microfluidic capillary electrophoresis chip. Equivalent performance to off-chip sample processing is demonstrated for each compound class; the automated analysis resulted in a limit of detection of ~16 nM for amino acids. Our microfluidic automaton provides a fully automated, portable microfluidic analysis system capable of autonomous analysis of diverse compound classes in challenging environments.

Transparently wrap-gated semiconductor nanowire arrays for studies of gate-controlled photoluminescence

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nylund, Gustav; Storm, Kristian; Torstensson, Henrik

2013-12-04

We present a technique to measure gate-controlled photoluminescence (PL) on arrays of semiconductor nanowire (NW) capacitors using a transparent film of Indium-Tin-Oxide (ITO) wrapping around the nanowires as the gate electrode. By tuning the wrap-gate voltage, it is possible to increase the PL peak intensity of an array of undoped InP NWs by more than an order of magnitude. The fine structure of the PL spectrum reveals three subpeaks whose relative peak intensities change with gate voltage. We interpret this as gate-controlled state-filling of luminescing quantum dot segments formed by zincblende stacking faults in the mainly wurtzite NW crystal structure.

Filling the Assurance Gap on Complex Electronics

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled by software, such as communication protocols. For example, the James Webb Space Telescope will use Field Programmable Gate Arrays (FPGAs), which can have over a million logic gates, to send telemetry. System-on-chip (SoC) devices, another type of complex electronics, can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, mature software methodologies have been proposed, with slight modifications, to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and bugs can be detected earlier in the development cycle, thus creating a development process for CE that can be easily maintained and configurable based on the device used.

Software Process Assurance for Complex Electronics

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Complex Electronics (CE) now perform tasks that were previously handled in software, such as communication protocols. Many methods used to develop software bare a close resemblance to CE development. Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. With CE devices obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that used standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques were used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that was more easily maintained, consistent and configurable based on the device used.

Microcircuit Device Reliability Digital Detailed Data

DTIC Science & Technology

1976-01-01

TYPE s No. FUNCTION A LASS PINS TEMP. TYPE CLASS LEVEL I eFAILED 8 NO. CHIP TEST APPL. TEST PAR1 t T AGATES PROTECT. DATE E:V. D TYPE HOURST :708 FLIP...LEVEL # EFAILED s a NO. t CHIP i TEST 3 APPL. a TEST I PAR! 3 a GATES s PROTECT. a DATE 3 ENV. t TYPE I 3 -OUHb s 354H0( 3 GATE C-I CDIP 14 150C :11.A

A miniature electronic nose system based on an MWNT-polymer microsensor array and a low-power signal-processing chip.

PubMed

Chiu, Shih-Wen; Wu, Hsiang-Chiu; Chou, Ting-I; Chen, Hsin; Tang, Kea-Tiong

2014-06-01

This article introduces a power-efficient, miniature electronic nose (e-nose) system. The e-nose system primarily comprises two self-developed chips, a multiple-walled carbon nanotube (MWNT)-polymer based microsensor array, and a low-power signal-processing chip. The microsensor array was fabricated on a silicon wafer by using standard photolithography technology. The microsensor array comprised eight interdigitated electrodes surrounded by SU-8 "walls," which restrained the material-solvent liquid in a defined area of 650 × 760 μm(2). To achieve a reliable sensor-manufacturing process, we used a two-layer deposition method, coating the MWNTs and polymer film as the first and second layers, respectively. The low-power signal-processing chip included array data acquisition circuits and a signal-processing core. The MWNT-polymer microsensor array can directly connect with array data acquisition circuits, which comprise sensor interface circuitry and an analog-to-digital converter; the signal-processing core consists of memory and a microprocessor. The core executes the program, classifying the odor data received from the array data acquisition circuits. The low-power signal-processing chip was designed and fabricated using the Taiwan Semiconductor Manufacturing Company 0.18-μm 1P6M standard complementary metal oxide semiconductor process. The chip consumes only 1.05 mW of power at supply voltages of 1 and 1.8 V for the array data acquisition circuits and the signal-processing core, respectively. The miniature e-nose system, which used a microsensor array, a low-power signal-processing chip, and an embedded k-nearest-neighbor-based pattern recognition algorithm, was developed as a prototype that successfully recognized the complex odors of tincture, sorghum wine, sake, whisky, and vodka.

37 CFR 211.4 - Registration of claims of protection in mask works.

Code of Federal Regulations, 2010 CFR

2010-07-01

... adding metal-connection layers to unpersonalized gate arrays may separately register the entire unpersonalized gate array and the custom metallization layers. Applicants seeking to register separately entire unpersonalized gate arrays or custom metallization layers should make the nature of their claim clear at Space 8...

Flexible High Speed Codec (FHSC)

NASA Technical Reports Server (NTRS)

Segallis, G. P.; Wernlund, J. V.

1991-01-01

The ongoing NASA/Harris Flexible High Speed Codec (FHSC) program is described. The program objectives are to design and build an encoder decoder that allows operation in either burst or continuous modes at data rates of up to 300 megabits per second. The decoder handles both hard and soft decision decoding and can switch between modes on a burst by burst basis. Bandspreading is low since the code rate is greater than or equal to 7/8. The encoder and a hard decision decoder fit on a single application specific integrated circuit (ASIC) chip. A soft decision applique is implemented using 300 K emitter coupled logic (ECL) which can be easily translated to an ECL gate array.

Physics of Failure Analysis of Xilinx Flip Chip CCGA Packages: Effects of Mission Environments on Properties of LP2 Underfill and ATI Lid Adhesive Materials

NASA Technical Reports Server (NTRS)

Suh, Jong-ook

2013-01-01

The Xilinx Virtex 4QV and 5QV (V4 and V5) are next-generation field-programmable gate arrays (FPGAs) for space applications. However, there have been concerns within the space community regarding the non-hermeticity of V4/V5 packages; polymeric materials such as the underfill and lid adhesive will be directly exposed to the space environment. In this study, reliability concerns associated with the non-hermeticity of V4/V5 packages were investigated by studying properties and behavior of the underfill and the lid adhesvie materials used in V4/V5 packages.

Implementation of image transmission server system using embedded Linux

NASA Astrophysics Data System (ADS)

Park, Jong-Hyun; Jung, Yeon Sung; Nam, Boo Hee

2005-12-01

In this paper, we performed the implementation of image transmission server system using embedded system that is for the specified object and easy to install and move. Since the embedded system has lower capability than the PC, we have to reduce the quantity of calculation of the baseline JPEG image compression and transmission. We used the Redhat Linux 9.0 OS at the host PC and the target board based on embedded Linux. The image sequences are obtained from the camera attached to the FPGA (Field Programmable Gate Array) board with ALTERA cooperation chip. For effectiveness and avoiding some constraints from the vendor's own, we made the device driver using kernel module.

A design method for high performance seismic data acquisition based on oversampling delta-sigma modulation

NASA Astrophysics Data System (ADS)

Gao, Shanghua; Xue, Bing

2017-04-01

The dynamic range of the currently most widely used 24-bit seismic data acquisition devices is 10-20 dB lower than that of broadband seismometers, and this can affect the completeness of seismic waveform recordings under certain conditions. However, this problem is not easy to solve because of the lack of analog to digital converter (ADC) chips with more than 24 bits in the market. So the key difficulties for higher-resolution data acquisition devices lie in achieving more than 24-bit ADC circuit. In the paper, we propose a method in which an adder, an integrator, a digital to analog converter chip, a field-programmable gate array, and an existing low-resolution ADC chip are used to build a third-order 16-bit oversampling delta-sigma modulator. This modulator is equipped with a digital decimation filter, thus forming a complete analog to digital converting circuit. Experimental results show that, within the 0.1-40 Hz frequency range, the circuit board's dynamic range reaches 158.2 dB, its resolution reaches 25.99 dB, and its linearity error is below 2.5 ppm, which is better than what is achieved by the commercial 24-bit ADC chips ADS1281 and CS5371. This demonstrates that the proposed method may alleviate or even solve the amplitude-limitation problem that broadband observation systems so commonly have to face during strong earthquakes.

Sparsely-Bonded CMOS Hybrid Imager

NASA Technical Reports Server (NTRS)

Sun, Chao (Inventor); Jones, Todd J. (Inventor); Nikzad, Shouleh (Inventor); Newton, Kenneth W. (Inventor); Cunningham, Thomas J. (Inventor); Hancock, Bruce R. (Inventor); Dickie, Matthew R. (Inventor); Hoenk, Michael E. (Inventor); Wrigley, Christopher J. (Inventor); Pain, Bedabrata (Inventor)

2015-01-01

A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.

Control and gating of kinesin-microtubule motility on electrically heated thermo-chips.

PubMed

Ramsey, Laurence; Schroeder, Viktor; van Zalinge, Harm; Berndt, Michael; Korten, Till; Diez, Stefan; Nicolau, Dan V

2014-06-01

First lab-on-chip devices based on active transport by biomolecular motors have been demonstrated for basic detection and sorting applications. However, to fully employ the advantages of such hybrid nanotechnology, versatile spatial and temporal control mechanisms are required. Using a thermo-responsive polymer, we demonstrated a temperature controlled gate that either allows or disallows the passing of microtubules through a topographically defined channel. The gate is addressed by a narrow gold wire, which acts as a local heating element. It is shown that the electrical current flowing through a narrow gold channel can control the local temperature and as a result the conformation of the polymer. This is the first demonstration of a spatially addressable gate for microtubule motility which is a key element of nanodevices based on biomolecular motors.

Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

NASA Astrophysics Data System (ADS)

Ashenafi, Emeshaw

Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse-with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on-ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.

Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)

DOEpatents

Asaad, Sameh W; Bellofatto, Ralph E; Brezzo, Bernard; Haymes, Charles L; Kapur, Mohit; Parker, Benjamin D; Roewer, Thomas; Tierno, Jose A

2014-01-28

A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.

Partition resampling and extrapolation averaging: approximation methods for quantifying gene expression in large numbers of short oligonucleotide arrays.

PubMed

Goldstein, Darlene R

2006-10-01

Studies of gene expression using high-density short oligonucleotide arrays have become a standard in a variety of biological contexts. Of the expression measures that have been proposed to quantify expression in these arrays, multi-chip-based measures have been shown to perform well. As gene expression studies increase in size, however, utilizing multi-chip expression measures is more challenging in terms of computing memory requirements and time. A strategic alternative to exact multi-chip quantification on a full large chip set is to approximate expression values based on subsets of chips. This paper introduces an extrapolation method, Extrapolation Averaging (EA), and a resampling method, Partition Resampling (PR), to approximate expression in large studies. An examination of properties indicates that subset-based methods can perform well compared with exact expression quantification. The focus is on short oligonucleotide chips, but the same ideas apply equally well to any array type for which expression is quantified using an entire set of arrays, rather than for only a single array at a time. Software implementing Partition Resampling and Extrapolation Averaging is under development as an R package for the BioConductor project.

Novel Photon-Counting Detectors for Free-Space Communication

NASA Technical Reports Server (NTRS)

Krainak, M. A.; Yang, G.; Sun, X.; Lu, W.; Merritt, S.; Beck, J.

2016-01-01

We present performance data for novel photon-counting detectors for free space optical communication. NASA GSFC is testing the performance of two types of novel photon-counting detectors 1) a 2x8 mercury cadmium telluride (HgCdTe) avalanche array made by DRS Inc., and a 2) a commercial 2880-element silicon avalanche photodiode (APD) array. We present and compare dark count, photon-detection efficiency, wavelength response and communication performance data for these detectors. We successfully measured real-time communication performance using both the 2 detected-photon threshold and AND-gate coincidence methods. Use of these methods allows mitigation of dark count, after-pulsing and background noise effects. The HgCdTe APD array routinely demonstrated photon detection efficiencies of greater than 50% across 5 arrays, with one array reaching a maximum PDE of 70%. We performed high-resolution pixel-surface spot scans and measured the junction diameters of its diodes. We found that decreasing the junction diameter from 31 micrometers to 25 micrometers doubled the e- APD gain from 470 for an array produced in the year 2010 to a gain of 1100 on an array delivered to NASA GSFC recently. The mean single-photon SNR was over 12 and the excess noise factors measurements were 1.2-1.3. The commercial silicon APD array exhibited a fast output with rise times of 300 ps and pulse widths of 600 ps. On-chip individually filtered signals from the entire array were multiplexed onto a single fast output.

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

NASA Astrophysics Data System (ADS)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Detection of pathogenic copy number variants in children with idiopathic intellectual disability using 500 K SNP array genomic hybridization

PubMed Central

2009-01-01

Background Array genomic hybridization is being used clinically to detect pathogenic copy number variants in children with intellectual disability and other birth defects. However, there is no agreement regarding the kind of array, the distribution of probes across the genome, or the resolution that is most appropriate for clinical use. Results We performed 500 K Affymetrix GeneChip® array genomic hybridization in 100 idiopathic intellectual disability trios, each comprised of a child with intellectual disability of unknown cause and both unaffected parents. We found pathogenic genomic imbalance in 16 of these 100 individuals with idiopathic intellectual disability. In comparison, we had found pathogenic genomic imbalance in 11 of 100 children with idiopathic intellectual disability in a previous cohort who had been studied by 100 K GeneChip® array genomic hybridization. Among 54 intellectual disability trios selected from the previous cohort who were re-tested with 500 K GeneChip® array genomic hybridization, we identified all 10 previously-detected pathogenic genomic alterations and at least one additional pathogenic copy number variant that had not been detected with 100 K GeneChip® array genomic hybridization. Many benign copy number variants, including one that was de novo, were also detected with 500 K array genomic hybridization, but it was possible to distinguish the benign and pathogenic copy number variants with confidence in all but 3 (1.9%) of the 154 intellectual disability trios studied. Conclusion Affymetrix GeneChip® 500 K array genomic hybridization detected pathogenic genomic imbalance in 10 of 10 patients with idiopathic developmental disability in whom 100 K GeneChip® array genomic hybridization had found genomic imbalance, 1 of 44 patients in whom 100 K GeneChip® array genomic hybridization had found no abnormality, and 16 of 100 patients who had not previously been tested. Effective clinical interpretation of these studies requires considerable skill and experience. PMID:19917086

Matching OPC and masks on 300-mm lithography tools utilizing variable illumination settings

NASA Astrophysics Data System (ADS)

Palitzsch, Katrin; Kubis, Michael; Schroeder, Uwe P.; Schumacher, Karl; Frangen, Andreas

2004-05-01

CD control is crucial to maximize product yields on 300mm wafers. This is particularly true for DRAM frontend lithography layers, like gate level, and deep trench (capacitor) level. In the DRAM process, large areas of the chip are taken up by array structures, which are difficult to structure due to aggressive pitch requirements. Consequently, the lithography process is centered such that the array structures are printed on target. Optical proximity correction is applied to print gate level structures in the periphery circuitry on target. Only slight differences of the different Zernike terms can cause rather large variations of the proximity curves, resulting in a difference of isolated and semi-isolated lines printed on different tools. If the deviations are too large, tool specific OPC is needed. The same is true for deep trench level, where the length to width ratio of elongated contact-like structures is an important parameter to adjust the electrical properties of the chip. Again, masks with specific biases for tools with different Zernikes are needed to optimize product yield. Additionally, mask making contributes to the CD variation of the process. Theoretically, the CD deviation caused by an off-centered mask process can easily eat up the majority of the CD budget of a lithography process. In practice, masks are very often distributed intelligently among production tools, such that lens and mask effects cancel each other. However, only dose adjusting and mask allocation may still result in a high CD variation with large systematical contributions. By adjusting the illumination settings, we have successfully implemented a method to reduce CD variation on our advanced processes. Especially inner and outer sigma for annular illumination, and the numerical aperture, can be optimized to match mask and stepper properties. This process will be shown to overcome slight lens and mask differences effectively. The effects on lithography process windows have to be considered, nonetheless.

A convenient method of manufacturing liquid-gated MoS2 field effect transistors

NASA Astrophysics Data System (ADS)

Lin, Kabin; Yuan, Zhishan; Yu, Yu; Li, Kun; Li, Zhongwu; Sha, Jingjie; Li, Tie; Chen, Yunfei

2017-10-01

In this paper, we present a simple and convenient method of manufacturing liquid-gated MoS2 field effect transistors (FETs). A Si3N4 chip is firstly fabricated by the semiconductor manufacturing process, then the mechanical exfoliation MoS2 is transferred onto the Si3N4 chip and is connected with the gold electrodes by depositing platinum to construct the MoS2 FETs. The liquid-gated is formed by injecting 0.1 M NaCl solution into reservoir to contact the back side of the Si3N4. Our measured results show that the contact properties between MoS2 and electrodes are in well condition and the liquid-gated MoS2 FETs have a high mobility that can reach up to 109 cm2 V-1 s-1.

Detection of Her2-overexpressing cancer cells using keyhole shaped chamber array employing a magnetic droplet-handling system.

PubMed

Okochi, Mina; Koike, Shinji; Tanaka, Masayoshi; Honda, Hiroyuki

2017-07-15

An on-chip gene expression analysis compartmentalized in droplets was developed for detection of cancer cells at a single-cell level. The chip consists of a keyhole-shaped reaction chamber with hydrophobic modification employing a magnetic bead-droplet-handling system with a gate for bead separation. Using three kinds of water-based droplets in oil, a droplet with sample cells, a lysis buffer with magnetic beads, and RT-PCR buffer, parallel magnetic manipulation and fusion of droplets were performed using a magnet-handling device containing small external magnet patterns in an array. The actuation with the magnet offers a simple system for droplet manipulation that allows separation and fusion of droplets containing magnetic beads. After reverse transcription and amplification by thermal cycling, fluorescence was obtained for detection of overexpressing genes. For clinical detection of gastric cancer cells in peritoneal washing, the Her2-overexpressing gastric cancer cells spiked within normal cells was detected by gene expression analysis of droplets containing an average of 2.5 cells. Our developed droplet-based cancer detection system manipulated by external magnetic force without pumps or valves offers a simple and flexible set-up for transcriptional detection of cancer cells, and will be greatly advantageous for less-invasive clinical diagnosis and prognostic prediction. Copyright © 2016 Elsevier B.V. All rights reserved.

ADMET biosensors: up-to-date issues and strategies.

PubMed

Fang, Yan; Offenhaeusser, Andrease

2004-12-01

This insight review introduces the new concepts, theories, technology, instruments, frontier issues, and key strategies of ADMET (absorption, distribution, metabolism, elimination, and toxicity) biosensors, from the fermi to the quantum levels. Information about ADMET, originating from one author's invention, a patented pharmacotherapy for rescuing cardio-cerebral vascular stunning and regulating vascular endothelial growth-factor signaling at the post-genomic level, can be detected by a new generation of ADMET biosensor. This is a single-cell/single-molecule field-effect transistor (FET) hybrid system, where single molecules or single cells are assembled at the FET surface in a high density array manner via complementary metal-oxide-semiconductor (CMOS)-compatible technologies. Within a given nanometer distance, ADMET-mediated oxidation-reduction (redox) potentials, electrochemistry responses, and electron transfer processes can be simultaneously and directly probed by the gates of field-effect transistor arrays. The nanometer details of the functional coupling principles and characterization technologies of DNA single-molecule/single-cell FETs, as well as the design of lab-on-a-chip instruments, are indicated. Four frontier issues and key strategies are elucidated in detail. This can lead to innovative technology for high-throughout screening of labs-on-chips to resolve the pharmaceutical industry's current bottleneck via novel, FET-based drug discovery and single-molecule/single-cell screening methods, which can bring about a pharmaceutical industry revolution in the 21st century.

Mapping of transcription factor binding regions in mammalian cells by ChIP: Comparison of array- and sequencing-based technologies

PubMed Central

Euskirchen, Ghia M.; Rozowsky, Joel S.; Wei, Chia-Lin; Lee, Wah Heng; Zhang, Zhengdong D.; Hartman, Stephen; Emanuelsson, Olof; Stolc, Viktor; Weissman, Sherman; Gerstein, Mark B.; Ruan, Yijun; Snyder, Michael

2007-01-01

Recent progress in mapping transcription factor (TF) binding regions can largely be credited to chromatin immunoprecipitation (ChIP) technologies. We compared strategies for mapping TF binding regions in mammalian cells using two different ChIP schemes: ChIP with DNA microarray analysis (ChIP-chip) and ChIP with DNA sequencing (ChIP-PET). We first investigated parameters central to obtaining robust ChIP-chip data sets by analyzing STAT1 targets in the ENCODE regions of the human genome, and then compared ChIP-chip to ChIP-PET. We devised methods for scoring and comparing results among various tiling arrays and examined parameters such as DNA microarray format, oligonucleotide length, hybridization conditions, and the use of competitor Cot-1 DNA. The best performance was achieved with high-density oligonucleotide arrays, oligonucleotides ≥50 bases (b), the presence of competitor Cot-1 DNA and hybridizations conducted in microfluidics stations. When target identification was evaluated as a function of array number, 80%–86% of targets were identified with three or more arrays. Comparison of ChIP-chip with ChIP-PET revealed strong agreement for the highest ranked targets with less overlap for the low ranked targets. With advantages and disadvantages unique to each approach, we found that ChIP-chip and ChIP-PET are frequently complementary in their relative abilities to detect STAT1 targets for the lower ranked targets; each method detected validated targets that were missed by the other method. The most comprehensive list of STAT1 binding regions is obtained by merging results from ChIP-chip and ChIP-sequencing. Overall, this study provides information for robust identification, scoring, and validation of TF targets using ChIP-based technologies. PMID:17568005

ChIP-chip.

PubMed

Kim, Tae Hoon; Dekker, Job

2018-05-01

ChIP-chip can be used to analyze protein-DNA interactions in a region-wide and genome-wide manner. DNA microarrays contain PCR products or oligonucleotide probes that are designed to represent genomic sequences. Identification of genomic sites that interact with a specific protein is based on competitive hybridization of the ChIP-enriched DNA and the input DNA to DNA microarrays. The ChIP-chip protocol can be divided into two main sections: Amplification of ChIP DNA and hybridization of ChIP DNA to arrays. A large amount of DNA is required to hybridize to DNA arrays, and hybridization to a set of multiple commercial arrays that represent the entire human genome requires two rounds of PCR amplifications. The relative hybridization intensity of ChIP DNA and that of the input DNA is used to determine whether the probe sequence is a potential site of protein-DNA interaction. Resolution of actual genomic sites bound by the protein is dependent on the size of the chromatin and on the genomic distance between the probes on the array. As with expression profiling using gene chips, ChIP-chip experiments require multiple replicates for reliable statistical measure of protein-DNA interactions. © 2018 Cold Spring Harbor Laboratory Press.

Field Programmable Gate Array Control of Power Systems in Graduate Student Laboratories

DTIC Science & Technology

2008-03-01

NAVAL POSTGRADUATE SCHOOL MONTEREY, CALIFORNIA THESIS Approved for public release; distribution is unlimited FIELD PROGRAMMABLE...REPORT TYPE AND DATES COVERED Master’s Thesis 4. TITLE AND SUBTITLE Field Programmable Gate Array Control of Power Systems in Graduate Student...Electronics curriculum track is the development of a design center that explores Field Programmable Gate Array (FPGA) control of power electronics

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

1989-01-01

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Design of a Ferroelectric Programmable Logic Gate Array

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

2003-01-01

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

NASA Astrophysics Data System (ADS)

Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

2003-06-01

We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

In situ synthesis of protein arrays.

PubMed

He, Mingyue; Stoevesandt, Oda; Taussig, Michael J

2008-02-01

In situ or on-chip protein array methods use cell free expression systems to produce proteins directly onto an immobilising surface from co-distributed or pre-arrayed DNA or RNA, enabling protein arrays to be created on demand. These methods address three issues in protein array technology: (i) efficient protein expression and availability, (ii) functional protein immobilisation and purification in a single step and (iii) protein on-chip stability over time. By simultaneously expressing and immobilising many proteins in parallel on the chip surface, the laborious and often costly processes of DNA cloning, expression and separate protein purification are avoided. Recently employed methods reviewed are PISA (protein in situ array) and NAPPA (nucleic acid programmable protein array) from DNA and puromycin-mediated immobilisation from mRNA.

Neuron array with plastic synapses and programmable dendrites.

PubMed

Ramakrishnan, Shubha; Wunderlich, Richard; Hasler, Jennifer; George, Suma

2013-10-01

We describe a novel neuromorphic chip architecture that models neurons for efficient computation. Traditional architectures of neuron array chips consist of large scale systems that are interfaced with AER for implementing intra- or inter-chip connectivity. We present a chip that uses AER for inter-chip communication but uses fast, reconfigurable FPGA-style routing with local memory for intra-chip connectivity. We model neurons with biologically realistic channel models, synapses and dendrites. This chip is suitable for small-scale network simulations and can also be used for sequence detection, utilizing directional selectivity properties of dendrites, ultimately for use in word recognition.

Integrated circuit package with lead structure and method of preparing the same

NASA Technical Reports Server (NTRS)

Kennedy, B. W. (Inventor)

1973-01-01

A beam-lead integrated circuit package assembly including a beam-lead integrated circuit chip, a lead frame array bonded to projecting fingers of the chip, a rubber potting compound disposed around the chip, and an encapsulating molded plastic is described. The lead frame array is prepared by photographically printing a lead pattern on a base metal sheet, selectively etching to remove metal between leads, and plating with gold. Joining of the chip to the lead frame array is carried out by thermocompression bonding of mating goldplated surfaces. A small amount of silicone rubber is then applied to cover the chip and bonded joints, and the package is encapsulated with epoxy resin, applied by molding.

A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro

PubMed Central

Tateno, Takashi; Nishikawa, Jun

2014-01-01

In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording) electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μ V root mean square (10 Hz to 100 kHz), which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μ Vpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution) spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system. PMID:25346683

A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro.

PubMed

Tateno, Takashi; Nishikawa, Jun

2014-01-01

In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording) electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μ V root mean square (10 Hz to 100 kHz), which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μ Vpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution) spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system.

X-band T/R switch with body-floating multi-gate PDSOI NMOS transistors

NASA Astrophysics Data System (ADS)

Park, Mingyo; Min, Byung-Wook

2018-03-01

This paper presents an X-band transmit/receive switch using multi-gate NMOS transistors in a silicon-on-insulator CMOS process. For low loss and high power handling capability, floating body multi-gate NMOS transistors are adopted instead of conventional stacked NMOS transistors, resulting in 53% reduction of transistor area. Comparing to the stacked NMOS transistors, the multi gate transistor shares the source and drain region between stacked transistors, resulting in reduced chip area and parasitics. The impedance between bodies of gates in multi-gate NMOS transistors is assumed to be very large during design and confirmed after measurement. The measured input 1 dB compression point is 34 dBm. The measured insertion losses of TX and RX modes are respectively 1.7 dB and 2.0 dB at 11 GHz, and the measured isolations of TX and RX modes are >27 dB and >20 dB in X-band, respectively. The chip size is 0.086 mm2 without pads, which is 25% smaller than the T/R switch with stacked transistors.

Thermoacoustic chips with carbon nanotube thin yarn arrays.

PubMed

Wei, Yang; Lin, Xiaoyang; Jiang, Kaili; Liu, Peng; Li, Qunqing; Fan, Shoushan

2013-10-09

Aligned carbon nanotube (CNT) films drawn from CNT arrays have shown the potential as thermoacoustic loudspeakers. CNT thermoacoustic chips with robust structures are proposed to promote the applications. The silicon-based chips can play sound and fascinating rhythms by feeding alternating currents and audio signal to the suspending CNT thin yarn arrays across grooves in them. In additional to the thin yarns, experiments further revealed more essential elements of the chips, the groove depth and the interdigital electrodes. The sound pressure depends on the depth of the grooves, and the thermal wavelength can be introduced to define the influence-free depth. The interdigital fingers can effectively reduce the driving voltage, making the chips safe and easy to use. The chips were successfully assembled into earphones and have been working stably for about one year. The thermoacoustic chips can find many applications in consumer electronics and possibly improve the audiovisual experience.

Electrostatically focused addressable field emission array chips (AFEA's) for high-speed massively parallel maskless digital E-beam direct write lithography and scanning electron microscopy

DOEpatents

Thomas, Clarence E.; Baylor, Larry R.; Voelkl, Edgar; Simpson, Michael L.; Paulus, Michael J.; Lowndes, Douglas H.; Whealton, John H.; Whitson, John C.; Wilgen, John B.

2002-12-24

Systems and methods are described for addressable field emission array (AFEA) chips. A method of operating an addressable field-emission array, includes: generating a plurality of electron beams from a pluralitly of emitters that compose the addressable field-emission array; and focusing at least one of the plurality of electron beams with an on-chip electrostatic focusing stack. The systems and methods provide advantages including the avoidance of space-charge blow-up.

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

NASA Astrophysics Data System (ADS)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

Image processing applications: From particle physics to society

NASA Astrophysics Data System (ADS)

Sotiropoulou, C.-L.; Luciano, P.; Gkaitatzis, S.; Citraro, S.; Giannetti, P.; Dell'Orso, M.

2017-01-01

We present an embedded system for extremely efficient real-time pattern recognition execution, enabling technological advancements with both scientific and social impact. It is a compact, fast, low consumption processing unit (PU) based on a combination of Field Programmable Gate Arrays (FPGAs) and the full custom associative memory chip. The PU has been developed for real time tracking in particle physics experiments, but delivers flexible features for potential application in a wide range of fields. It has been proposed to be used in accelerated pattern matching execution for Magnetic Resonance Fingerprinting (biomedical applications), in real time detection of space debris trails in astronomical images (space applications) and in brain emulation for image processing (cognitive image processing). We illustrate the potentiality of the PU for the new applications.

Hardware platforms for MEMS gyroscope tuning based on evolutionary computation using open-loop and closed -loop frequency response

NASA Technical Reports Server (NTRS)

Keymeulen, Didier; Ferguson, Michael I.; Fink, Wolfgang; Oks, Boris; Peay, Chris; Terrile, Richard; Cheng, Yen; Kim, Dennis; MacDonald, Eric; Foor, David

2005-01-01

We propose a tuning method for MEMS gyroscopes based on evolutionary computation to efficiently increase the sensitivity of MEMS gyroscopes through tuning. The tuning method was tested for the second generation JPL/Boeing Post-resonator MEMS gyroscope using the measurement of the frequency response of the MEMS device in open-loop operation. We also report on the development of a hardware platform for integrated tuning and closed loop operation of MEMS gyroscopes. The control of this device is implemented through a digital design on a Field Programmable Gate Array (FPGA). The hardware platform easily transitions to an embedded solution that allows for the miniaturization of the system to a single chip.

Design and implementation of GaAs HBT circuits with ACME

NASA Technical Reports Server (NTRS)

Hutchings, Brad L.; Carter, Tony M.

1993-01-01

GaAs HBT circuits offer high performance (5-20 GHz) and radiation hardness (500 Mrad) that is attractive for space applications. ACME is a CAD tool specifically developed for HBT circuits. ACME implements a novel physical schematic-capture design technique where designers simultaneously view the structure and physical organization of a circuit. ACME's design interface is similar to schematic capture; however, unlike conventional schematic capture, designers can directly control the physical placement of both function and interconnect at the schematic level. In addition, ACME provides design-time parasitic extraction, complex wire models, and extensions to Multi-Chip Modules (MCM's). A GaAs HBT gate-array and semi-custom circuits have been developed with ACME; several circuits have been fabricated and found to be fully functional .

3D printed high density, reversible, chip-to-chip microfluidic interconnects.

PubMed

Gong, Hua; Woolley, Adam T; Nordin, Gregory P

2018-02-13

Our latest developments in miniaturizing 3D printed microfluidics [Gong et al., Lab Chip, 2016, 16, 2450; Gong et al., Lab Chip, 2017, 17, 2899] offer the opportunity to fabricate highly integrated chips that measure only a few mm on a side. For such small chips, an interconnection method is needed to provide the necessary world-to-chip reagent and pneumatic connections. In this paper, we introduce simple integrated microgaskets (SIMs) and controlled-compression integrated microgaskets (CCIMs) to connect a small device chip to a larger interface chip that implements world-to-chip connections. SIMs or CCIMs are directly 3D printed as part of the device chip, and therefore no additional materials or components are required to make the connection to the larger 3D printed interface chip. We demonstrate 121 chip-to-chip interconnections in an 11 × 11 array for both SIMs and CCIMs with an areal density of 53 interconnections per mm 2 and show that they withstand fluid pressures of 50 psi. We further demonstrate their reusability by testing the devices 100 times without seal failure. Scaling experiments show that 20 × 20 interconnection arrays are feasible and that the CCIM areal density can be increased to 88 interconnections per mm 2 . We then show the utility of spatially distributed discrete CCIMs by using an interconnection chip with 28 chip-to-world interconnects to test 45 3D printed valves in a 9 × 5 array. Each valve is only 300 μm in diameter (the smallest yet reported for 3D printed valves). Every row of 5 valves is tested to at least 10 000 actuations, with one row tested to 1 000 000 actuations. In all cases, there is no sign of valve failure, and the CCIM interconnections prove an effective means of using a single interface chip to test a series of valve array chips.

A fully on-chip fast-transient NMOS low dropout voltage regulator with quasi floating gate pass element

NASA Astrophysics Data System (ADS)

Wang, Han; Gou, Chao; Luo, Kai

2017-04-01

This paper presents a fully on-chip NMOS low-dropout regulator (LDO) for portable applications with quasi floating gate pass element and fast transient response. The quasi floating gate structure makes the gate of the NMOS transistor only periodically charged or refreshed by the charge pump, which allows the charge pump to be a small economical circuit with small silicon area. In addition, a variable reference circuit is introduced enlarging the dynamic range of error amplifier during load transient. The proposed LDO has been implemented in a 0.35 μm BCD process. From experimental results, the regulator can operate with a minimum dropout voltage of 250 mV at a maximum 1 A load and {I}{{Q}} of 395 μA. Under full-range load current step, the voltage undershoot and overshoot of the proposed LDO are reduced to 50 and 26 mV, respectively.

Flip-chip fabrication of integrated micromirror arrays using a novel latching off-chip hinge mechanism

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper presents the design, fabrication, modeling, and testing of various arrays of cantilever micromirror devices integrated atop CMOS control electronics. The upper layers of the arrays are prefabricated in the MUMPs process and then flip-chip transferred to CMOS receiving modules using a novel latching off-chip hinge mechanism. This mechanism allows the micromirror arrays to be released, rotated off the edge of the host module and then bonded to the receiving module using a standard probe station. The hinge mechanism supports the arrays by tethers that are severed to free the arrays once bonded. The resulting devices are inherently planarized since the bottom of the first releasable MUMPs layer becomes the surface of the integrated mirror. The working devices are formed by mirror surfaces bonded to address electrodes fabricated above static memory cells on the CMOS module. These arrays demonstrate highly desirable features such as compatible address potentials, less than 2 nm of RMS roughness, approximately 1 micrometers of lateral position accuracy and the unique ability to metallize reflective surfaces without masking. Ultimately, the off-chip hinge mechanism enables very low-cost, simple, reliable, repeatable and accurate assembly of advanced MEMS and integrated microsystems without specialized equipment or complex procedures.

All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

PubMed

Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

2016-01-30

This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement

PubMed Central

Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

2016-01-01

This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of −20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system. PMID:26840316

Field ion source development for neutron generators

NASA Astrophysics Data System (ADS)

Bargsten Johnson, B.; Schwoebel, P. R.; Holland, C. E.; Resnick, P. J.; Hertz, K. L.; Chichester, D. L.

2012-01-01

An ion source based on the principles of electrostatic field desorption is being developed to improve the performance of existing compact neutron generators. The ion source is an array of gated metal tips derived from field electron emitter array microfabrication technology. A comprehensive summary of development and experimental activities is presented. Many structural modifications to the arrays have been incorporated to achieve higher tip operating fields, while lowering fields at the gate electrode to prevent gate field electron emission which initiates electrical breakdown in the array. The latest focus of fabrication activities has been on rounding the gate electrode edge and surrounding the gate electrode with dielectric material. Array testing results have indicated a steady progression of increased array tip operating fields with each new design tested. The latest arrays have consistently achieved fields beyond those required for the onset of deuterium desorption (˜20 V/nm), and have demonstrated the desorption of deuterium at fields up to 36 V/nm. The number of ions desorbed from an array has been quantified, and field desorption of metal tip substrate material from array tips has been observed for the first time. Gas-phase field ionization studies with ˜10,000 tip arrays have achieved deuterium ion currents of ˜50 nA. Neutron production by field ionization has yielded ˜10 2 n/s from ˜1 mm 2 of array area using the deuterium-deuterium fusion reaction at 90 kV.

Design of barrier bucket kicker control system

NASA Astrophysics Data System (ADS)

Ni, Fa-Fu; Wang, Yan-Yu; Yin, Jun; Zhou, De-Tai; Shen, Guo-Dong; Zheng, Yang-De.; Zhang, Jian-Chuan; Yin, Jia; Bai, Xiao; Ma, Xiao-Li

2018-05-01

The Heavy-Ion Research Facility in Lanzhou (HIRFL) contains two synchrotrons: the main cooler storage ring (CSRm) and the experimental cooler storage ring (CSRe). Beams are extracted from CSRm, and injected into CSRe. To apply the Barrier Bucket (BB) method on the CSRe beam accumulation, a new BB technology based kicker control system was designed and implemented. The controller of the system is implemented using an Advanced Reduced Instruction Set Computer (RISC) Machine (ARM) chip and a field-programmable gate array (FPGA) chip. Within the architecture, ARM is responsible for data presetting and floating number arithmetic processing. The FPGA computes the RF phase point of the two rings and offers more accurate control of the time delay. An online preliminary experiment on HIRFL was also designed to verify the functionalities of the control system. The result shows that the reference trigger point of two different sinusoidal RF signals for an arbitrary phase point was acquired with a matched phase error below 1° (approximately 2.1 ns), and the step delay time better than 2 ns were realized.

Systems-on-chip approach for real-time simulation of wheel-rail contact laws

NASA Astrophysics Data System (ADS)

Mei, T. X.; Zhou, Y. J.

2013-04-01

This paper presents the development of a systems-on-chip approach to speed up the simulation of wheel-rail contact laws, which can be used to reduce the requirement for high-performance computers and enable simulation in real time for the use of hardware-in-loop for experimental studies of the latest vehicle dynamic and control technologies. The wheel-rail contact laws are implemented using a field programmable gate array (FPGA) device with a design that substantially outperforms modern general-purpose PC platforms or fixed architecture digital signal processor devices in terms of processing time, configuration flexibility and cost. In order to utilise the FPGA's parallel-processing capability, the operations in the contact laws algorithms are arranged in a parallel manner and multi-contact patches are tackled simultaneously in the design. The interface between the FPGA device and the host PC is achieved by using a high-throughput and low-latency Ethernet link. The development is based on FASTSIM algorithms, although the design can be adapted and expanded for even more computationally demanding tasks.

A Low-cost 4 Bit, 10 Giga-samples-per-second Analog-to-digital Converter Printed Circuit Board Assembly for FPGA-based Backends

NASA Astrophysics Data System (ADS)

Jiang, Homin; Yu, Chen-Yu; Kubo, Derek; Chen, Ming-Tang; Guzzino, Kim

2016-11-01

In this study, a 4 bit, 10 giga-samples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was designed, manufactured, and characterized for digitizing radio telescopes. For this purpose, an Adsantec ANST7120A-KMA flash ADC chip was used. Together with the field-programmable gate array platform, developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the PCBA enables data acquisition with a wide bandwidth and simplifies the intermediate frequency section. In the current version, the PCBA and the chip exhibit an analog bandwidth of 10 GHz (3 dB loss) and 20 GHz, respectively, which facilitates second, third, and even fourth Nyquist sampling. The following average performance parameters were obtained from the first and second Nyquist zones of the three boards: a spurious-free dynamic range of 31.35/30.45 dB, a signal-to-noise and distortion ratio of 22.95/21.83 dB, and an effective number of bits of 3.65/3.43, respectively.

Software Process Assurance for Complex Electronics (SPACE)

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Complex Electronics (CE) are now programmed to perform tasks that were previously handled in software, such as communication protocols. Many of the methods used to develop software bare a close resemblance to CE development. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that looks at using standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques can be used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that will be more easily maintained, consistent and configurable based on the device used.

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity

PubMed Central

Zhang, Fan; Niu, Hanben

2016-01-01

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 107 when illuminated by a 405-nm diode laser and 1/1.4 × 104 when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e− rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena. PMID:27367699

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity.

PubMed

Zhang, Fan; Niu, Hanben

2016-06-29

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 10⁷ when illuminated by a 405-nm diode laser and 1/1.4 × 10⁴ when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e(-) rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena.

GaAs circuits for monolithic optical controller

NASA Technical Reports Server (NTRS)

Gustafson, G.; Bendett, M.; Carney, J.; Mactaggart, R.; Palmquist, S.

1988-01-01

GaAs circuits for use in a fully monolithic 1 Gb/s optical controller have been developed and tested. The circuits include photodetectors, transimpedance amplifiers and 1:16 demultiplexers that can directly control the phase of MMIC phase shifters. The entire chip contains approximately 300 self-aligned gate E/D-mode MESFETs. The MESFETs have one micron-wide gate and the E-mode FETs typically have transconductance of 200 ms/mm. Results of simulations and tests are reported. Also, the design and layout of the fully monolithic chip is discussed.

Optical computing research

NASA Astrophysics Data System (ADS)

Goodman, Joseph W.

1987-10-01

Work Accomplished: OPTICAL INTERCONNECTIONS - the powerful interconnect abilities of optical beams have led much optimism about the possible roles for optics in solving interconnect problems at various levels of computer architecture. Examined were the powerful requirements of optical interconnects at the gate-to-gate and chip-to-chip levels. OPTICAL NEUTRAL NETWORKS - basic studies of the convergence properties on the Holfield model, based on mathematical approach - graph theory. OPTICS AND ARTIFICIAL INTELLIGENCE - review the field of optical processing and artificial intelligence, with the aim of finding areas that might be particularly attractive for future investigation(s).

Development of advanced micromirror arrays by flip-chip assembly

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper presents the design, commercial prefabrication, modeling and testing of advanced micromirror arrays fabricated using a novel, simple and inexpensive flip-chip assembly technique. Several polar piston arrays and rectangular cantilever arrays were fabricated using flip-chip assembly by which the upper layers of the array are fabricated on a separate chip and then transferred to a receiving module containing the lower layers. Typical polar piston arrays boast 98.3% active surface area, highly planarized surfaces, low address potentials compatible with CMOS electronics, highly standardized actuation between devices, and complex segmentation of mirror surfaces which allows for custom aberration configurations. Typical cantilever arrays boast large angles of rotation as well as an average surface planarity of only 1.779 nm of RMS roughness across 100 +m mirrors. Continuous torsion devices offer stable operation through as much as six degrees of rotation while binary operation devices offer stable activated positions with as much as 20 degrees of rotation. All arrays have desirable features of costly fabrication services like five structural layers and planarized mirror surfaces, but are prefabricated in the less costly MUMPs process. Models are developed for all devices and used to compare empirical data.

GeneChip{sup {trademark}} screening assay for cystic fibrosis mutations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cronn, M.T.; Miyada, C.G.; Fucini, R.V.

1994-09-01

GeneChip{sup {trademark}} assays are based on high density, carefully designed arrays of short oligonucleotide probes (13-16 bases) built directly on derivatized silica substrates. DNA target sequence analysis is achieved by hybridizing fluorescently labeled amplification products to these arrays. Fluorescent hybridization signals located within the probe array are translated into target sequence information using the known probe sequence at each array feature. The mutation screening assay for cystic fibrosis includes sets of oligonucleotide probes designed to detect numerous different mutations that have been described in 14 exons and one intron of the CFTR gene. Each mutation site is addressed by amore » sub-array of at least 40 probe sequences, half designed to detect the wild type gene sequence and half designed to detect the reported mutant sequence. Hybridization with homozygous mutant, homozygous wild type or heterozygous targets results in distinctive hybridization patterns within a sub-array, permitting specific discrimination of each mutation. The GeneChip probe arrays are very small (approximately 1 cm{sup 2}). There miniature size coupled with their high information content make GeneChip probe arrays a useful and practical means for providing CF mutation analysis in a clinical setting.« less

Arbitrary photonic wave plate operations on chip: Realizing Hadamard, Pauli-X, and rotation gates for polarisation qubits

PubMed Central

Heilmann, René; Gräfe, Markus; Nolte, Stefan; Szameit, Alexander

2014-01-01

Chip-based photonic quantum computing is an emerging technology that promises much speedup over conventional computers at small integration volumes. Particular interest is thereby given to polarisation-encoded photonic qubits, and many protocols have been developed for this encoding. However, arbitrary wave plate operation on chip are not available so far, preventing from the implementation of integrated universal quantum computing algorithms. In our work we close this gap and present Hadamard, Pauli-X, and rotation gates of high fidelity for photonic polarisation qubits on chip by employing a reorientation of the optical axis of birefringent waveguides. The optical axis of the birefringent waveguide is rotated due to the impact of an artificial stress field created by an additional modification close to the waveguide. By adjusting this length of the defect along the waveguide, the retardation between ordinary and extraordinary field components is precisely tunable including half-wave plate and quarter-wave plate operations. Our approach demonstrates the full range control of orientation and strength of the induced birefringence and thus allows arbitrary wave plate operations without affecting the degree of polarisation or introducing additional losses to the waveguides. The implemented gates are tested with classical and quantum light. PMID:24534893

Defense Industrial Base Assessment: U.S. Integrated Circuit Design and Fabrication Capability

DTIC Science & Technology

2009-05-01

in the U.S for the period 2003-2006, with projections to 2011.6 The resulting draft OTE survey was field tested for accuracy and usability with a...custom application specific integrated circuits (ASICs) to field programmable gate arrays (FPGAs). Companies of all sizes can manufacture these IC...able to design one-time Electronically Programmable Gate Arrays (EPGAs) while nine are able to design Field Programmable Gate Arrays (FPGAs). Eight

Integrated field emission array for ion desorption

DOEpatents

Resnick, Paul J; Hertz, Kristin L.; Holland, Christopher; Chichester, David

2016-08-23

An integrated field emission array for ion desorption includes an electrically conductive substrate; a dielectric layer lying over the electrically conductive substrate comprising a plurality of laterally separated cavities extending through the dielectric layer; a like plurality of conically-shaped emitter tips on posts, each emitter tip/post disposed concentrically within a laterally separated cavity and electrically contacting the substrate; and a gate electrode structure lying over the dielectric layer, including a like plurality of circular gate apertures, each gate aperture disposed concentrically above an emitter tip/post to provide a like plurality of annular gate electrodes and wherein the lower edge of each annular gate electrode proximate the like emitter tip/post is rounded. Also disclosed herein are methods for fabricating an integrated field emission array.

Integrated field emission array for ion desorption

DOEpatents

Resnick, Paul J; Hertz, Kristin L; Holland, Christopher; Chichester, David; Schwoebel, Paul

2013-09-17

An integrated field emission array for ion desorption includes an electrically conductive substrate; a dielectric layer lying over the electrically conductive substrate comprising a plurality of laterally separated cavities extending through the dielectric layer; a like plurality of conically-shaped emitter tips on posts, each emitter tip/post disposed concentrically within a laterally separated cavity and electrically contacting the substrate; and a gate electrode structure lying over the dielectric layer, including a like plurality of circular gate apertures, each gate aperture disposed concentrically above an emitter tip/post to provide a like plurality of annular gate electrodes and wherein the lower edge of each annular gate electrode proximate the like emitter tip/post is rounded. Also disclosed herein are methods for fabricating an integrated field emission array.

A novel lab-on-chip platform with integrated solid phase PCR and Supercritical Angle Fluorescence (SAF) microlens array for highly sensitive and multiplexed pathogen detection.

PubMed

Hung, Tran Quang; Chin, Wai Hoe; Sun, Yi; Wolff, Anders; Bang, Dang Duong

2017-04-15

Solid-phase PCR (SP-PCR) has become increasingly popular for molecular diagnosis and there have been a few attempts to incorporate SP-PCR into lab-on-a-chip (LOC) devices. However, their applicability for on-line diagnosis is hindered by the lack of sensitive and portable on-chip optical detection technology. In this paper, we addressed this challenge by combining the SP-PCR with super critical angle fluorescence (SAF) microlens array embedded in a microchip. We fabricated miniaturized SAF microlens array as part of a microfluidic chamber in thermoplastic material and performed multiplexed SP-PCR directly on top of the SAF microlens array. Attribute to the high fluorescence collection efficiency of the SAF microlens array, the SP-PCR assay on the LOC platform demonstrated a high sensitivity of 1.6 copies/µL, comparable to off-chip detection using conventional laser scanner. The combination of SP-PCR and SAF microlens array allows for on-chip highly sensitive and multiplexed pathogen detection with low-cost and compact optical components. The LOC platform would be widely used as a high-throughput biosensor to analyze food, clinical and environmental samples. Copyright © 2016 Elsevier B.V. All rights reserved.

Neuromorphic VLSI vision system for real-time texture segregation.

PubMed

Shimonomura, Kazuhiro; Yagi, Tetsuya

2008-10-01

The visual system of the brain can perceive an external scene in real-time with extremely low power dissipation, although the response speed of an individual neuron is considerably lower than that of semiconductor devices. The neurons in the visual pathway generate their receptive fields using a parallel and hierarchical architecture. This architecture of the visual cortex is interesting and important for designing a novel perception system from an engineering perspective. The aim of this study is to develop a vision system hardware, which is designed inspired by a hierarchical visual processing in V1, for real time texture segregation. The system consists of a silicon retina, orientation chip, and field programmable gate array (FPGA) circuit. The silicon retina emulates the neural circuits of the vertebrate retina and exhibits a Laplacian-Gaussian-like receptive field. The orientation chip selectively aggregates multiple pixels of the silicon retina in order to produce Gabor-like receptive fields that are tuned to various orientations by mimicking the feed-forward model proposed by Hubel and Wiesel. The FPGA circuit receives the output of the orientation chip and computes the responses of the complex cells. Using this system, the neural images of simple cells were computed in real-time for various orientations and spatial frequencies. Using the orientation-selective outputs obtained from the multi-chip system, a real-time texture segregation was conducted based on a computational model inspired by psychophysics and neurophysiology. The texture image was filtered by the two orthogonally oriented receptive fields of the multi-chip system and the filtered images were combined to segregate the area of different texture orientation with the aid of FPGA. The present system is also useful for the investigation of the functions of the higher-order cells that can be obtained by combining the simple and complex cells.

The research of data acquisition system for Raman spectrometer

NASA Astrophysics Data System (ADS)

Cui, Xiao; Guo, Pan; Zhang, Yinchao; Chen, Siying; Chen, He; Chen, Wenbo

2011-11-01

Raman spectrometer has been widely used as an identification tool for analyzing material structure and composition in many fields. However, Raman scattering echo signal is very weak, about dozens of photons at most in one laser plus signal. Therefore, it is a great challenge to design a Raman spectrum data acquisition system which could accurately receive the weak echo signal. The system designed in this paper receives optical signals with the principle of photon counter and could detect single photon. The whole system consists of a photoelectric conversion module H7421-40 and a photo counting card including a field programmable gate array (FPGA) chip and a PCI9054 chip. The module H7421-40 including a PMT, an amplifier and a discriminator has high sensitivity on wavelength from 300nm to 720nm. The Center Wavelength is 580nm which is close to the excitation wavelength (532nm), QE 40% at peak wavelength, Count Sensitivity is 7.8*105(S-1PW-1) and Count Linearity is 1.5MHZ. In FPGA chip, the functions are divided into three parts: parameter setting module, controlling module, data collection and storage module. All the commands, parameters and data are transmitted between FPGA and computer by PCI9054 chip through the PCI interface. The result of experiment shows that the Raman spectrum data acquisition system is reasonable and efficient. There are three primary advantages of the data acquisition system: the first one is the high sensitivity with single photon detection capability; the second one is the high integrated level which means all the operation could be done by the photo counting card; and the last one is the high expansion ability because of the smart reconfigurability of FPGA chip.

GaAs VLSI for aerospace electronics

NASA Technical Reports Server (NTRS)

Larue, G.; Chan, P.

1990-01-01

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

GateKeeper: a new hardware architecture for accelerating pre-alignment in DNA short read mapping.

PubMed

Alser, Mohammed; Hassan, Hasan; Xin, Hongyi; Ergin, Oguz; Mutlu, Onur; Alkan, Can

2017-11-01

High throughput DNA sequencing (HTS) technologies generate an excessive number of small DNA segments -called short reads- that cause significant computational burden. To analyze the entire genome, each of the billions of short reads must be mapped to a reference genome based on the similarity between a read and 'candidate' locations in that reference genome. The similarity measurement, called alignment, formulated as an approximate string matching problem, is the computational bottleneck because: (i) it is implemented using quadratic-time dynamic programming algorithms and (ii) the majority of candidate locations in the reference genome do not align with a given read due to high dissimilarity. Calculating the alignment of such incorrect candidate locations consumes an overwhelming majority of a modern read mapper's execution time. Therefore, it is crucial to develop a fast and effective filter that can detect incorrect candidate locations and eliminate them before invoking computationally costly alignment algorithms. We propose GateKeeper, a new hardware accelerator that functions as a pre-alignment step that quickly filters out most incorrect candidate locations. GateKeeper is the first design to accelerate pre-alignment using Field-Programmable Gate Arrays (FPGAs), which can perform pre-alignment much faster than software. When implemented on a single FPGA chip, GateKeeper maintains high accuracy (on average >96%) while providing, on average, 90-fold and 130-fold speedup over the state-of-the-art software pre-alignment techniques, Adjacency Filter and Shifted Hamming Distance (SHD), respectively. The addition of GateKeeper as a pre-alignment step can reduce the verification time of the mrFAST mapper by a factor of 10. https://github.com/BilkentCompGen/GateKeeper. mohammedalser@bilkent.edu.tr or onur.mutlu@inf.ethz.ch or calkan@cs.bilkent.edu.tr. Supplementary data are available at Bioinformatics online. © The Author (2017). Published by Oxford University Press. All rights reserved. For Permissions, please email: journals.permissions@oup.com

Theory of the synchronous motion of an array of floating flap gates oscillating wave surge converter

NASA Astrophysics Data System (ADS)

Michele, Simone; Sammarco, Paolo; d'Errico, Michele

2016-08-01

We consider a finite array of floating flap gates oscillating wave surge converter (OWSC) in water of constant depth. The diffraction and radiation potentials are solved in terms of elliptical coordinates and Mathieu functions. Generated power and capture width ratio of a single gate excited by incoming waves are given in terms of the radiated wave amplitude in the far field. Similar to the case of axially symmetric absorbers, the maximum power extracted is shown to be directly proportional to the incident wave characteristics: energy flux, angle of incidence and wavelength. Accordingly, the capture width ratio is directly proportional to the wavelength, thus giving a design estimate of the maximum efficiency of the system. We then compare the array and the single gate in terms of energy production. For regular waves, we show that excitation of the out-of-phase natural modes of the array increases the power output, while in the case of random seas we show that the array and the single gate achieve the same efficiency.

Field programmable gate arrays-based number plate binarization and adjustment for automatic number plate recognition systems

NASA Astrophysics Data System (ADS)

Zhai, Xiaojun; Bensaali, Faycal; Sotudeh, Reza

2013-01-01

Number plate (NP) binarization and adjustment are important preprocessing stages in automatic number plate recognition (ANPR) systems and are used to link the number plate localization (NPL) and character segmentation stages. Successfully linking these two stages will improve the performance of the entire ANPR system. We present two optimized low-complexity NP binarization and adjustment algorithms. Efficient area/speed architectures based on the proposed algorithms are also presented and have been successfully implemented and tested using the Mentor Graphics RC240 FPGA development board, which together require only 9% of the available on-chip resources of a Virtex-4 FPGA, run with a maximum frequency of 95.8 MHz and are capable of processing one image in 0.07 to 0.17 ms.

A reconfigurable continuous-flow fluidic routing fabric using a modular, scalable primitive.

PubMed

Silva, Ryan; Bhatia, Swapnil; Densmore, Douglas

2016-07-05

Microfluidic devices, by definition, are required to move liquids from one physical location to another. Given a finite and frequently fixed set of physical channels to route fluids, a primitive design element that allows reconfigurable routing of that fluid from any of n input ports to any n output ports will dramatically change the paradigms by which these chips are designed and applied. Furthermore, if these elements are "regular" regarding their design, the programming and fabrication of these elements becomes scalable. This paper presents such a design element called a transposer. We illustrate the design, fabrication and operation of a single transposer. We then scale this design to create a programmable fabric towards a general-purpose, reconfigurable microfluidic platform analogous to the Field Programmable Gate Array (FPGA) found in digital electronics.

A generic FPGA-based detector readout and real-time image processing board

NASA Astrophysics Data System (ADS)

Sarpotdar, Mayuresh; Mathew, Joice; Safonova, Margarita; Murthy, Jayant

2016-07-01

For space-based astronomical observations, it is important to have a mechanism to capture the digital output from the standard detector for further on-board analysis and storage. We have developed a generic (application- wise) field-programmable gate array (FPGA) board to interface with an image sensor, a method to generate the clocks required to read the image data from the sensor, and a real-time image processor system (on-chip) which can be used for various image processing tasks. The FPGA board is applied as the image processor board in the Lunar Ultraviolet Cosmic Imager (LUCI) and a star sensor (StarSense) - instruments developed by our group. In this paper, we discuss the various design considerations for this board and its applications in the future balloon and possible space flights.

FPGA Implementation of Generalized Hebbian Algorithm for Texture Classification

PubMed Central

Lin, Shiow-Jyu; Hwang, Wen-Jyi; Lee, Wei-Hao

2012-01-01

This paper presents a novel hardware architecture for principal component analysis. The architecture is based on the Generalized Hebbian Algorithm (GHA) because of its simplicity and effectiveness. The architecture is separated into three portions: the weight vector updating unit, the principal computation unit and the memory unit. In the weight vector updating unit, the computation of different synaptic weight vectors shares the same circuit for reducing the area costs. To show the effectiveness of the circuit, a texture classification system based on the proposed architecture is physically implemented by Field Programmable Gate Array (FPGA). It is embedded in a System-On-Programmable-Chip (SOPC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient design for attaining both high speed performance and low area costs. PMID:22778640

Deterministic Integration of Quantum Dots into on-Chip Multimode Interference Beamsplitters Using in Situ Electron Beam Lithography.

PubMed

Schnauber, Peter; Schall, Johannes; Bounouar, Samir; Höhne, Theresa; Park, Suk-In; Ryu, Geun-Hwan; Heindel, Tobias; Burger, Sven; Song, Jin-Dong; Rodt, Sven; Reitzenstein, Stephan

2018-04-11

The development of multinode quantum optical circuits has attracted great attention in recent years. In particular, interfacing quantum-light sources, gates, and detectors on a single chip is highly desirable for the realization of large networks. In this context, fabrication techniques that enable the deterministic integration of preselected quantum-light emitters into nanophotonic elements play a key role when moving forward to circuits containing multiple emitters. Here, we present the deterministic integration of an InAs quantum dot into a 50/50 multimode interference beamsplitter via in situ electron beam lithography. We demonstrate the combined emitter-gate interface functionality by measuring triggered single-photon emission on-chip with g (2) (0) = 0.13 ± 0.02. Due to its high patterning resolution as well as spectral and spatial control, in situ electron beam lithography allows for integration of preselected quantum emitters into complex photonic systems. Being a scalable single-step approach, it paves the way toward multinode, fully integrated quantum photonic chips.

Transcript Profiling of Common Bean (Phaseolus vulgaris L.) Using the GeneChip(R) Soybean Genome Array: Optimizing Analysis by Masking Biased Probes

USDA-ARS?s Scientific Manuscript database

Common bean (Phaseolus vulgaris) and soybean (Glycine max) both belong to the Phaseoleae tribe and share significant coding sequence homology. This suggests that the GeneChip(R) Soybean Genome Array (soybean GeneChip) may be used for gene expression studies using common bean. To evaluate the utility...

A Front-End Electronics Prototype Based on Gigabit Ethernet for the ATLAS Small-Strip Thin Gap Chamber

NASA Astrophysics Data System (ADS)

Hu, Kun; Lu, Houbing; Wang, Xu; Li, Feng; Wang, Xinxin; Geng, Tianru; Yang, Hang; Liu, Shengquan; Han, Liang; Jin, Ge

2017-06-01

A front-end electronics prototype for the ATLAS small-strip Thin Gap Chamber (sTGC) based on gigabit Ethernet has been developed. The prototype is designed to read out signals of pads, wires, and strips of the sTGC detector. The prototype includes two VMM2 chips developed to read out the signals of the sTGC, a Xilinx Kintex-7 field-programmable gate array (FPGA) used for the VMM2 configuration and the events storage, and a gigabit Ethernet transceiver PHY chip for interfacing with a computer. The VMM2 chip is designed for the readout of the Micromegas detector and sTGC detector, which is composed of 64 linear front-end channels. Each channel integrates a charge-sensitive amplifier, a shaper, several analog-to-digital converters, and other digital functions. For a bunch-crossing interval of 25 ns, events are continuously read out by the FPGA and forwarded to the computer. The interface between the computer and the prototype has been measured to reach an error-free rate of 900 Mb/s, therefore making a very effective use of the available bandwidth. Additionally, the computer can control several prototypes of this kind simultaneously via the Ethernet interface. At present, the prototype will be used for the sTGC performance test. The features of the prototype are described in detail.

Low-power grating detection system chip for high-speed low-cost length and angle precision measurement

NASA Astrophysics Data System (ADS)

Hou, Ligang; Luo, Rengui; Wu, Wuchen

2006-11-01

This paper forwards a low power grating detection chip (EYAS) on length and angle precision measurement. Traditional grating detection method, such as resister chain divide or phase locked divide circuit are difficult to design and tune. The need of an additional CPU for control and display makes these methods' implementation more complex and costly. Traditional methods also suffer low sampling speed for the complex divide circuit scheme and CPU software compensation. EYAS is an application specific integrated circuit (ASIC). It integrates micro controller unit (MCU), power management unit (PMU), LCD controller, Keyboard interface, grating detection unit and other peripherals. Working at 10MHz, EYAS can afford 5MHz internal sampling rate and can handle 1.25MHz orthogonal signal from grating sensor. With a simple control interface by keyboard, sensor parameter, data processing and system working mode can be configured. Two LCD controllers can adapt to dot array LCD or segment bit LCD, which comprised output interface. PMU alters system between working and standby mode by clock gating technique to save power. EYAS in test mode (system action are more frequently than real world use) consumes 0.9mw, while 0.2mw in real world use. EYAS achieved the whole grating detection system function, high-speed orthogonal signal handling in a single chip with very low power consumption.

Morphologies and optical and electrical properties of InGaN/GaN micro-square array light-emitting diode chips.

PubMed

Han, Dan; Ma, Shufang; Jia, Zhigang; Liu, Peizhi; Jia, Wei; Shang, Lin; Zhai, Guangmei; Xu, Bingshe

2018-04-10

InGaN/GaN micro-square array light-emitting diode (LED) chips (micro-chips) have been prepared via the focused ion beam (FIB) etching technique, which can not only reduce ohmic contact degradation but also control the aspect ratio precisely in three-dimensional (3D) structure LED (3D-LED) device fabrication. The effects of FIB beam current and micro-square array depth on morphologies and optical and electrical properties of the micro-chips have been studied. Our results show that sidewall surface morphology and optical and electrical properties of the micro-chips degrade with increased beam current. After potassium hydroxide etching with different times, an optimal current-voltage and luminescence performance can be obtained. Combining the results of cathodoluminescence mappings and light output-current characteristics, the light extraction efficiency of the micro-chips is reduced as FIB etch depth increases. The mechanisms of micro-square depth on light extraction have been revealed by 3D finite difference time domain.

Arrays of nucleic acid probes on biological chips

DOEpatents

Chee, Mark; Cronin, Maureen T.; Fodor, Stephen P. A.; Huang, Xiaohua X.; Hubbell, Earl A.; Lipshutz, Robert J.; Lobban, Peter E.; Morris, MacDonald S.; Sheldon, Edward L.

1998-11-17

DNA chips containing arrays of oligonucleotide probes can be used to determine whether a target nucleic acid has a nucleotide sequence identical to or different from a specific reference sequence. The array of probes comprises probes exactly complementary to the reference sequence, as well as probes that differ by one or more bases from the exactly complementary probes.

The role of simulation in the design of a neural network chip

NASA Technical Reports Server (NTRS)

Desai, Utpal; Roppel, Thaddeus A.; Padgett, Mary L.

1993-01-01

An iterative, simulation-based design procedure for a neural network chip is introduced. For this design procedure, the goal is to produce a chip layout for a neural network in which the weights are determined by transistor gate width-to-length ratios. In a given iteration, the current layout is simulated using the circuit simulator SPICE, and layout adjustments are made based on conventional gradient-decent methods. After the iteration converges, the chip is fabricated. Monte Carlo analysis is used to predict the effect of statistical fabrication process variations on the overall performance of the neural network chip.

Towards on-chip time-resolved thermal mapping with micro-/nanosensor arrays

PubMed Central

2012-01-01

In recent years, thin-film thermocouple (TFTC) array emerged as a versatile candidate in micro-/nanoscale local temperature sensing for its high resolution, passive working mode, and easy fabrication. However, some key issues need to be taken into consideration before real instrumentation and industrial applications of TFTC array. In this work, we will demonstrate that TFTC array can be highly scalable from micrometers to nanometers and that there are potential applications of TFTC array in integrated circuits, including time-resolvable two-dimensional thermal mapping and tracing the heat source of a device. Some potential problems and relevant solutions from a view of industrial applications will be discussed in terms of material selection, multiplexer reading, pattern designing, and cold-junction compensation. We show that the TFTC array is a powerful tool for research fields such as chip thermal management, lab-on-a-chip, and other novel electrical, optical, or thermal devices. PMID:22931306

Hybridization of Environmental Microbial Community Nucleic Acids by GeoChip.

PubMed

Van Nostrand, Joy D; Yin, Huaqin; Wu, Liyou; Yuan, Tong; Zhou, Jizhong

2016-01-01

Functional gene arrays, like the GeoChip, allow for the study of tens of thousands of genes in a single assay. The GeoChip array (5.0) contains probes for genes involved in geochemical cycling (N, C, S, and P), metal homeostasis, stress response, organic contaminant degradation, antibiotic resistance, secondary metabolism, and virulence factors as well as genes specific for fungi, protists, and viruses. Here, we briefly describe GeoChip design strategies (gene selection and probe design) and discuss minimum quantity and quality requirements for nucleic acids. We then provide detailed protocols for amplification, labeling, and hybridization of samples to the GeoChip.

Design, processing and testing of LSI arrays, hybrid microelectronics task

NASA Technical Reports Server (NTRS)

Himmel, R. P.; Stuhlbarg, S. M.; Ravetti, R. G.; Zulueta, P. J.; Rothrock, C. W.

1979-01-01

Mathematical cost models previously developed for hybrid microelectronic subsystems were refined and expanded. Rework terms related to substrate fabrication, nonrecurring developmental and manufacturing operations, and prototype production are included. Sample computer programs were written to demonstrate hybrid microelectric applications of these cost models. Computer programs were generated to calculate and analyze values for the total microelectronics costs. Large scale integrated (LST) chips utilizing tape chip carrier technology were studied. The feasibility of interconnecting arrays of LSU chips utilizing tape chip carrier and semiautomatic wire bonding technology was demonstrated.

Wire like link for cycle reproducible and cycle accurate hardware accelerator

DOEpatents

Asaad, Sameh; Kapur, Mohit; Parker, Benjamin D

2015-04-07

First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.

Leadless Chip Carrier Packaging and CAD/CAM-Supported Wire Wrap Interconnect Technology for Subnanosecond ECL.

DTIC Science & Technology

1981-11-01

Showing Wire . 99 Impregnanted Silicone Rubber Contacts, Chip Carrier, ard Lid 35. Technit Connector For 68-Pad JEDEC Type A Leadless . . 100 Chip Carrier...Points of Various . . . . 124 Solders 4. Composition of Alloys Employed in Dual-In-Line . . . . 128 Package Pins and Plating by Mass Spectrographic...swings, and subnanosecond gate delays and risetimes. Presently, emitter coupled logic (ECL) and current mode logic (CML), both fabricated with silicon tech

A 2x2 W-Band Reference Time-Shifted Phase-Locked Transmitter Array in 65nm CMOS Technology

NASA Technical Reports Server (NTRS)

Tang, Adrian; Virbila, Gabriel; Hsiao, Frank; Wu, Hao; Murphy, David; Mehdi, Imran; Siegel, P. H.; Chang, M-C. Frank

2013-01-01

This paper presents a complete 2x2 phased array transmitter system operating at W-band (90-95 GHz) which employs a PLL reference time-shifting approach instead of using traditional mm-wave phase shifters. PLL reference shifting enables a phased array to be distributed over multiple chips without the need for coherent mm-wave signal distribution between chips. The proposed phased array transmitter system consumes 248 mW per array element when implemented in a 65 nm CMOS technology.

High-power, format-flexible, 885-nm vertical-cavity surface-emitting laser arrays

NASA Astrophysics Data System (ADS)

Wang, Chad; Talantov, Fedor; Garrett, Henry; Berdin, Glen; Cardellino, Terri; Millenheft, David; Geske, Jonathan

2013-03-01

High-power, format flexible, 885 nm vertical-cavity surface-emitting laser (VCSEL) arrays have been developed for solid-state pumping and illumination applications. In this approach, a common VCSEL size format was designed to enable tiling into flexible formats and operating configurations. The fabrication of a common chip size on ceramic submount enables low-cost volume manufacturing of high-power VCSEL arrays. This base VCSEL chip was designed to be 5x3.33 mm2, and produced up to 50 Watts of peak continuous wave (CW) power. To scale to higher powers, multiple chips can be tiled into a combination of series or parallel configurations tailored to the application driver conditions. In actively cooled CW operation, the VCSEL array chips were packaged onto a single water channel cooler, and we have demonstrated 0.5x1, 1x1, and 1x3 cm2 formats, producing 150, 250, and 500 Watts of peak power, respectively, in under 130 A operating current. In QCW operation, the 1x3 cm2 VCSEL module, which contains 18 VCSEL array chips packaged on a single water cooler, produced over 1.3 kW of peak power. In passively cooled packages, multiple chip configurations have been developed for illumination applications, producing over 300 Watts of peak power in QCW operating conditions. These VCSEL chips use a substrate-removed structure to allow for efficient thermal heatsinking to enable high-power operation. This scalable, format flexible VCSEL architecture can be applied to wavelengths ranging from 800 to 1100 nm, and can be used to tailor emission spectral widths and build high-power hyperspectral sources.

Microfluidic multiplexed partitioning enables flexible and effective utilization of magnetic sensor arrays.

PubMed

Bechstein, Daniel J B; Ng, Elaine; Lee, Jung-Rok; Cone, Stephanie G; Gaster, Richard S; Osterfeld, Sebastian J; Hall, Drew A; Weaver, James A; Wilson, Robert J; Wang, Shan X

2015-11-21

We demonstrate microfluidic partitioning of a giant magnetoresistive sensor array into individually addressable compartments that enhances its effective use. Using different samples and reagents in each compartment enables measuring of cross-reactive species and wide dynamic ranges on a single chip. This compartmentalization technique motivates the employment of high density sensor arrays for highly parallelized measurements in lab-on-a-chip devices.

Mechanical flip-chip for ultra-high electron mobility devices

DOE PAGES

Bennaceur, Keyan; Schmidt, Benjamin A.; Gaucher, Samuel; ...

2015-09-22

In this study, electrostatic gates are of paramount importance for the physics of devices based on high-mobility two-dimensional electron gas (2DEG) since they allow depletion of electrons in selected areas. This field-effect gating enables the fabrication of a wide range of devices such as, for example, quantum point contacts (QPC), electron interferometers and quantum dots. To fabricate these gates, processing is usually performed on the 2DEG material, which is in many cases detrimental to its electron mobility. Here we propose an alternative process which does not require any processing of the 2DEG material other than for the ohmic contacts. Thismore » approach relies on processing a separate wafer that is then mechanically mounted on the 2DEG material in a flip-chip fashion. This technique proved successful to fabricate quantum point contacts on both GaAs/AlGaAs materials with both moderate and ultra-high electron mobility.« less

Optical interconnection for a polymeric PLC device using simple positional alignment.

PubMed

Ryu, Jin Hwa; Kim, Po Jin; Cho, Cheon Soo; Lee, El-Hang; Kim, Chang-Seok; Jeong, Myung Yung

2011-04-25

This study proposes a simple cost-effective method of optical interconnection between a planar lightwave circuit (PLC) device chip and an optical fiber. It was conducted to minimize and overcome the coupling loss caused by lateral offset which is due to the process tolerance and the dimensional limitation existing between PLC device chips and fiber array blocks with groove structures. A PLC device chip and a fiber array block were simultaneously fabricated in a series of polymer replication processes using the original master. The dimensions (i.e., width and thickness) of the under-clad of the PLC device chip were identical to those of the fiber array block. The PLC device chip and optical fiber were aligned by simple positional control for the vertical direction of the PLC device chip under a particular condition. The insertion loss of the proposed 1 x 2 multimode optical splitter device interconnection was 4.0 dB at 850 nm and the coupling loss was below 0.1 dB compared with single-fiber based active alignment.

Nanohole Array-directed Trapping of Mammalian Mitochondria Enabling Single Organelle Analysis

PubMed Central

Kumar, Shailabh; Wolken, Gregory G.; Wittenberg, Nathan J.; Arriaga, Edgar A.; Oh, Sang-Hyun

2016-01-01

We present periodic nanohole arrays fabricated in free-standing metal-coated nitride films as a platform for trapping and analyzing single organelles. When a microliter-scale droplet containing mitochondria is dispensed above the nanohole array, the combination of evaporation and capillary flow directs individual mitochondria to the nanoholes. Mammalian mitochondria arrays were rapidly formed on chip using this technique without any surface modification steps, microfluidic interconnects or external power sources. The trapped mitochondria were depolarized on chip using an ionophore with results showing that the organelle viability and behavior were preserved during the on-chip assembly process. Fluorescence signal related to mitochondrial membrane potential was obtained from single mitochondria trapped in individual nanoholes revealing statistical differences between the behavior of polarized vs. depolarized mammalian mitochondria. This technique provides a fast and stable route for droplet-based directed localization of organelles-on-a-chip with minimal limitations and complexity, as well as promotes integration with other optical or electrochemical detection techniques. PMID:26593329

On-chip visual perception of motion: a bio-inspired connectionist model on FPGA.

PubMed

Torres-Huitzil, César; Girau, Bernard; Castellanos-Sánchez, Claudio

2005-01-01

Visual motion provides useful information to understand the dynamics of a scene to allow intelligent systems interact with their environment. Motion computation is usually restricted by real time requirements that need the design and implementation of specific hardware architectures. In this paper, the design of hardware architecture for a bio-inspired neural model for motion estimation is presented. The motion estimation is based on a strongly localized bio-inspired connectionist model with a particular adaptation of spatio-temporal Gabor-like filtering. The architecture is constituted by three main modules that perform spatial, temporal, and excitatory-inhibitory connectionist processing. The biomimetic architecture is modeled, simulated and validated in VHDL. The synthesis results on a Field Programmable Gate Array (FPGA) device show the potential achievement of real-time performance at an affordable silicon area.

Embedded System Implementation on FPGA System With μCLinux OS

NASA Astrophysics Data System (ADS)

Fairuz Muhd Amin, Ahmad; Aris, Ishak; Syamsul Azmir Raja Abdullah, Raja; Kalos Zakiah Sahbudin, Ratna

2011-02-01

Embedded systems are taking on more complicated tasks as the processors involved become more powerful. The embedded systems have been widely used in many areas such as in industries, automotives, medical imaging, communications, speech recognition and computer vision. The complexity requirements in hardware and software nowadays need a flexibility system for further enhancement in any design without adding new hardware. Therefore, any changes in the design system will affect the processor that need to be changed. To overcome this problem, a System On Programmable Chip (SOPC) has been designed and developed using Field Programmable Gate Array (FPGA). A softcore processor, NIOS II 32-bit RISC, which is the microprocessor core was utilized in FPGA system together with the embedded operating system(OS), μClinux. In this paper, an example of web server is explained and demonstrated

Comparison of laser Doppler and laser speckle contrast imaging using a concurrent processing system

NASA Astrophysics Data System (ADS)

Sun, Shen; Hayes-Gill, Barrie R.; He, Diwei; Zhu, Yiqun; Huynh, Nam T.; Morgan, Stephen P.

2016-08-01

Full field laser Doppler imaging (LDI) and single exposure laser speckle contrast imaging (LSCI) are directly compared using a novel instrument which can concurrently image blood flow using both LDI and LSCI signal processing. Incorporating a commercial CMOS camera chip and a field programmable gate array (FPGA) the flow images of LDI and the contrast maps of LSCI are simultaneously processed by utilizing the same detected optical signals. The comparison was carried out by imaging a rotating diffuser. LDI has a linear response to the velocity. In contrast, LSCI is exposure time dependent and does not provide a linear response in the presence of static speckle. It is also demonstrated that the relationship between LDI and LSCI can be related through a power law which depends on the exposure time of LSCI.

Neural dynamics in reconfigurable silicon.

PubMed

Basu, A; Ramakrishnan, S; Petre, C; Koziol, S; Brink, S; Hasler, P E

2010-10-01

A neuromorphic analog chip is presented that is capable of implementing massively parallel neural computations while retaining the programmability of digital systems. We show measurements from neurons with Hopf bifurcations and integrate and fire neurons, excitatory and inhibitory synapses, passive dendrite cables, coupled spiking neurons, and central pattern generators implemented on the chip. This chip provides a platform for not only simulating detailed neuron dynamics but also uses the same to interface with actual cells in applications such as a dynamic clamp. There are 28 computational analog blocks (CAB), each consisting of ion channels with tunable parameters, synapses, winner-take-all elements, current sources, transconductance amplifiers, and capacitors. There are four other CABs which have programmable bias generators. The programmability is achieved using floating gate transistors with on-chip programming control. The switch matrix for interconnecting the components in CABs also consists of floating-gate transistors. Emphasis is placed on replicating the detailed dynamics of computational neural models. Massive computational area efficiency is obtained by using the reconfigurable interconnect as synaptic weights, resulting in more than 50 000 possible 9-b accurate synapses in 9 mm(2).

Deterministic Integration of Quantum Dots into on-Chip Multimode Interference Beamsplitters Using in Situ Electron Beam Lithography

NASA Astrophysics Data System (ADS)

Schnauber, Peter; Schall, Johannes; Bounouar, Samir; Höhne, Theresa; Park, Suk-In; Ryu, Geun-Hwan; Heindel, Tobias; Burger, Sven; Song, Jin-Dong; Rodt, Sven; Reitzenstein, Stephan

2018-04-01

The development of multi-node quantum optical circuits has attracted great attention in recent years. In particular, interfacing quantum-light sources, gates and detectors on a single chip is highly desirable for the realization of large networks. In this context, fabrication techniques that enable the deterministic integration of pre-selected quantum-light emitters into nanophotonic elements play a key role when moving forward to circuits containing multiple emitters. Here, we present the deterministic integration of an InAs quantum dot into a 50/50 multi-mode interference beamsplitter via in-situ electron beam lithography. We demonstrate the combined emitter-gate interface functionality by measuring triggered single-photon emission on-chip with $g^{(2)}(0) = 0.13\\pm 0.02$. Due to its high patterning resolution as well as spectral and spatial control, in-situ electron beam lithography allows for integration of pre-selected quantum emitters into complex photonic systems. Being a scalable single-step approach, it paves the way towards multi-node, fully integrated quantum photonic chips.

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Li, K.; Shih, Y. C.

1992-01-01

Packaging schemes were developed that provide low-loss, hermetic enclosure for advanced monolithic microwave and millimeter-wave integrated circuits (MMICs). The package designs are based on a fused quartz substrate material that offers improved radio frequency (RF) performance through 44 gigahertz (GHz). The small size and weight of the packages make them appropriate for a variety of applications, including phased array antenna systems. Packages were designed in two forms; one for housing a single MMIC chip, the second in the form of a multi-chip phased array module. The single chip array module was developed in three separate sizes, for chips of different geometry and frequency requirements. The phased array module was developed to address packaging directly for antenna applications, and includes transmission line and interconnect structures to support multi-element operation. All packages are fabricated using fused quartz substrate materials. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices. The package and test fixture designs were both developed in a generic sense, optimizing performance for a wide range of possible applications and devices.

Quantum confinement effects in lithographic sub-5 nm Silicon nanowire fets and integration of si nanograting fet biosensors

NASA Astrophysics Data System (ADS)

Trivedi, Krutarth B.

In recent years, widespread accessibility to reliable nanofabrication techniques such as high resolution electron beam lithography as well as development of innovative techniques such as nanoimprint lithography and chemically grown nano-materials like carbon nanotubes and graphene have spurred a boom in many fields of research involving nanoscale features and devices. The breadth of fields in which nanoscale features represent a new paradigm is staggering. Scaling down device dimensions to nanoscale enables non-classical quantum behavior and allows for interaction with similarly sized natural materials, like proteins and DNA, as never before, affording an unprecedented level of performance and control and fostering a seemingly boundless array of unique applications. Much of the research effort has been directed toward understanding such interactions to leverage the potential of nanoscale devices to enhance electronic and medical technology. In keeping with the spirit of application based research, my graduate research career has spanned the development of nanoimprint techniques and devices for novel applications, demonstration and study of sub-5 nm Si nanowire FETs exhibiting tangible performance enhancement over conventional MOSFETs, and development of an integrated Si nanograting FET based biosensor and related framework. The following dissertation details my work in fabrication of sub-5 nm Si nanowire FETs and characterization of quantum confinement effects in charge transport of FETs with 2D and 1D channel geometry, fabrication and characterization of schottky contact Si nanograting FET sensors, integration of miniaturized Si nanograting FET biosensors into Chip-in-Strip(c) packaging, development of an automated microfluidic sensing system, and investigation of electrochemical considerations in the Si nanograting FET biosensor gate stack followed by development of a novel patent-pending strategy for a lithographically patterned on-chip gate electrode.

A robotics platform for automated batch fabrication of high density, microfluidics-based DNA microarrays, with applications to single cell, multiplex assays of secreted proteins

NASA Astrophysics Data System (ADS)

Ahmad, Habib; Sutherland, Alex; Shin, Young Shik; Hwang, Kiwook; Qin, Lidong; Krom, Russell-John; Heath, James R.

2011-09-01

Microfluidics flow-patterning has been utilized for the construction of chip-scale miniaturized DNA and protein barcode arrays. Such arrays have been used for specific clinical and fundamental investigations in which many proteins are assayed from single cells or other small sample sizes. However, flow-patterned arrays are hand-prepared, and so are impractical for broad applications. We describe an integrated robotics/microfluidics platform for the automated preparation of such arrays, and we apply it to the batch fabrication of up to eighteen chips of flow-patterned DNA barcodes. The resulting substrates are comparable in quality with hand-made arrays and exhibit excellent substrate-to-substrate consistency. We demonstrate the utility and reproducibility of robotics-patterned barcodes by utilizing two flow-patterned chips for highly parallel assays of a panel of secreted proteins from single macrophage cells.

A robotics platform for automated batch fabrication of high density, microfluidics-based DNA microarrays, with applications to single cell, multiplex assays of secreted proteins

PubMed Central

Ahmad, Habib; Sutherland, Alex; Shin, Young Shik; Hwang, Kiwook; Qin, Lidong; Krom, Russell-John; Heath, James R.

2011-01-01

Microfluidics flow-patterning has been utilized for the construction of chip-scale miniaturized DNA and protein barcode arrays. Such arrays have been used for specific clinical and fundamental investigations in which many proteins are assayed from single cells or other small sample sizes. However, flow-patterned arrays are hand-prepared, and so are impractical for broad applications. We describe an integrated robotics/microfluidics platform for the automated preparation of such arrays, and we apply it to the batch fabrication of up to eighteen chips of flow-patterned DNA barcodes. The resulting substrates are comparable in quality with hand-made arrays and exhibit excellent substrate-to-substrate consistency. We demonstrate the utility and reproducibility of robotics-patterned barcodes by utilizing two flow-patterned chips for highly parallel assays of a panel of secreted proteins from single macrophage cells. PMID:21974603

A robotics platform for automated batch fabrication of high density, microfluidics-based DNA microarrays, with applications to single cell, multiplex assays of secreted proteins.

PubMed

Ahmad, Habib; Sutherland, Alex; Shin, Young Shik; Hwang, Kiwook; Qin, Lidong; Krom, Russell-John; Heath, James R

2011-09-01

Microfluidics flow-patterning has been utilized for the construction of chip-scale miniaturized DNA and protein barcode arrays. Such arrays have been used for specific clinical and fundamental investigations in which many proteins are assayed from single cells or other small sample sizes. However, flow-patterned arrays are hand-prepared, and so are impractical for broad applications. We describe an integrated robotics/microfluidics platform for the automated preparation of such arrays, and we apply it to the batch fabrication of up to eighteen chips of flow-patterned DNA barcodes. The resulting substrates are comparable in quality with hand-made arrays and exhibit excellent substrate-to-substrate consistency. We demonstrate the utility and reproducibility of robotics-patterned barcodes by utilizing two flow-patterned chips for highly parallel assays of a panel of secreted proteins from single macrophage cells. © 2011 American Institute of Physics

Field-Programmable Gate Array Computer in Structural Analysis: An Initial Exploration

NASA Technical Reports Server (NTRS)

Singleterry, Robert C., Jr.; Sobieszczanski-Sobieski, Jaroslaw; Brown, Samuel

2002-01-01

This paper reports on an initial assessment of using a Field-Programmable Gate Array (FPGA) computational device as a new tool for solving structural mechanics problems. A FPGA is an assemblage of binary gates arranged in logical blocks that are interconnected via software in a manner dependent on the algorithm being implemented and can be reprogrammed thousands of times per second. In effect, this creates a computer specialized for the problem that automatically exploits all the potential for parallel computing intrinsic in an algorithm. This inherent parallelism is the most important feature of the FPGA computational environment. It is therefore important that if a problem offers a choice of different solution algorithms, an algorithm of a higher degree of inherent parallelism should be selected. It is found that in structural analysis, an 'analog computer' style of programming, which solves problems by direct simulation of the terms in the governing differential equations, yields a more favorable solution algorithm than current solution methods. This style of programming is facilitated by a 'drag-and-drop' graphic programming language that is supplied with the particular type of FPGA computer reported in this paper. Simple examples in structural dynamics and statics illustrate the solution approach used. The FPGA system also allows linear scalability in computing capability. As the problem grows, the number of FPGA chips can be increased with no loss of computing efficiency due to data flow or algorithmic latency that occurs when a single problem is distributed among many conventional processors that operate in parallel. This initial assessment finds the FPGA hardware and software to be in their infancy in regard to the user conveniences; however, they have enormous potential for shrinking the elapsed time of structural analysis solutions if programmed with algorithms that exhibit inherent parallelism and linear scalability. This potential warrants further development of FPGA-tailored algorithms for structural analysis.

Gene chips and arrays revealed: a primer on their power and their uses.

PubMed

Watson, S J; Akil, H

1999-03-01

This article provides an overview and general explanation of the rapidly developing area of gene chips and expression array technology. These are methods targeted at allowing the simultaneous study of thousands of genes or messenger RNAs under various physiological and pathological states. Their technical basis grows from the Human Genome Project. Both methods place DNA strands on glass computer chips (or microscope slides). Expression arrays start with complementary DNA (cDNA) clones derived from the EST data base, whereas Gene Chips synthesize oligonucleotides directly on the chip itself. Both are analyzed using image analysis systems, are capable of reading values from two different individuals at any one site, and can yield quantitative data for thousands of genes or mRNAs per slide. These methods promise to revolutionize molecular biology, cell biology, neuroscience and psychiatry. It is likely that this technology will radically open up our ability to study the actions and structure of the multiple genes involved in the complex genetics of brain disorders.

Construction of a versatile SNP array for pyramiding useful genes of rice.

PubMed

Kurokawa, Yusuke; Noda, Tomonori; Yamagata, Yoshiyuki; Angeles-Shim, Rosalyn; Sunohara, Hidehiko; Uehara, Kanako; Furuta, Tomoyuki; Nagai, Keisuke; Jena, Kshirod Kumar; Yasui, Hideshi; Yoshimura, Atsushi; Ashikari, Motoyuki; Doi, Kazuyuki

2016-01-01

DNA marker-assisted selection (MAS) has become an indispensable component of breeding. Single nucleotide polymorphisms (SNP) are the most frequent polymorphism in the rice genome. However, SNP markers are not readily employed in MAS because of limitations in genotyping platforms. Here the authors report a Golden Gate SNP array that targets specific genes controlling yield-related traits and biotic stress resistance in rice. As a first step, the SNP genotypes were surveyed in 31 parental varieties using the Affymetrix Rice 44K SNP microarray. The haplotype information for 16 target genes was then converted to the Golden Gate platform with 143-plex markers. Haplotypes for the 14 useful allele are unique and can discriminate among all other varieties. The genotyping consistency between the Affymetrix microarray and the Golden Gate array was 92.8%, and the accuracy of the Golden Gate array was confirmed in 3 F2 segregating populations. The concept of the haplotype-based selection by using the constructed SNP array was proofed. Copyright © 2015 The Authors. Published by Elsevier Ireland Ltd.. All rights reserved.

Automatic Digital Hardware Synthesis

DTIC Science & Technology

1990-09-01

VHDL to PALASM, a hardware synthesis language. The PALASM description is then directly implemented into a field programmable gate array (FPGAI using...process of translating VHDL to PALASM, a hardware synthesis language. The PALASM description is then directly implemented into a field programmable gate...allows the engineer to use VHDL to create and validate a design, and then to implement it in a gate array. The development of software o translate VHDL

32 x 16 CMOS smart pixel array for optical interconnects

NASA Astrophysics Data System (ADS)

Kim, Jongwoo; Guilfoyle, Peter S.; Stone, Richard V.; Hessenbruch, John M.; Choquette, Kent D.; Kiamilev, Fouad E.

2000-05-01

Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32 X 16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 micrometers technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 micrometers technology.

Printing Peptide arrays with a complementary metal oxide semiconductor chip.

PubMed

Loeffler, Felix F; Cheng, Yun-Chien; Muenster, Bastian; Striffler, Jakob; Liu, Fanny C; Ralf Bischoff, F; Doersam, Edgar; Breitling, Frank; Nesterov-Mueller, Alexander

2013-01-01

: In this chapter, we discuss the state-of-the-art peptide array technologies, comparing the spot technique, lithographical methods, and microelectronic chip-based approaches. Based on this analysis, we describe a novel peptide array synthesis method with a microelectronic chip printer. By means of a complementary metal oxide semiconductor chip, charged bioparticles can be patterned on its surface. The bioparticles serve as vehicles to transfer molecule monomers to specific synthesis spots. Our chip offers 16,384 pixel electrodes on its surface with a spot-to-spot pitch of 100 μm. By switching the voltage of each pixel between 0 and 100 V separately, it is possible to generate arbitrary particle patterns for combinatorial molecule synthesis. Afterwards, the patterned chip surface serves as a printing head to transfer the particle pattern from its surface to a synthesis substrate. We conducted a series of proof-of-principle experiments to synthesize high-density peptide arrays. Our solid phase synthesis approach is based on the 9-fluorenylmethoxycarbonyl protection group strategy. After melting the particles, embedded monomers diffuse to the surface and participate in the coupling reaction to the surface. The method demonstrated herein can be easily extended to the synthesis of more complicated artificial molecules by using bioparticles with artificial molecular building blocks. The possibility of synthesizing artificial peptides was also shown in an experiment in which we patterned biotin particles in a high-density array format. These results open the road to the development of peptide-based functional modules for diverse applications in biotechnology.

CMOS chip planarization by chemical mechanical polishing for a vertically stacked metal MEMS integration

NASA Astrophysics Data System (ADS)

Lee, Hocheol; Miller, Michele H.; Bifano, Thomas G.

2004-01-01

In this paper we present the planarization process of a CMOS chip for the integration of a microelectromechanical systems (MEMS) metal mirror array. The CMOS chip, which comes from a commercial foundry, has a bumpy passivation layer due to an underlying aluminum interconnect pattern (1.8 µm high), which is used for addressing individual micromirror array elements. To overcome the tendency for tilt error in the CMOS chip planarization, the approach is to sputter a thick layer of silicon nitride at low temperature and to surround the CMOS chip with dummy silicon pieces that define a polishing plane. The dummy pieces are first lapped down to the height of the CMOS chip, and then all pieces are polished. This process produced a chip surface with a root-mean-square flatness error of less than 100 nm, including tilt and curvature errors.

Bubble pump: scalable strategy for in-plane liquid routing.

PubMed

Oskooei, Ali; Günther, Axel

2015-07-07

We present an on-chip liquid routing technique intended for application in well-based microfluidic systems that require long-term active pumping at low to medium flowrates. Our technique requires only one fluidic feature layer, one pneumatic control line and does not rely on flexible membranes and mechanical or moving parts. The presented bubble pump is therefore compatible with both elastomeric and rigid substrate materials and the associated scalable manufacturing processes. Directed liquid flow was achieved in a microchannel by an in-series configuration of two previously described "bubble gates", i.e., by gas-bubble enabled miniature gate valves. Only one time-dependent pressure signal is required and initiates at the upstream (active) bubble gate a reciprocating bubble motion. Applied at the downstream (passive) gate a time-constant gas pressure level is applied. In its rest state, the passive gate remains closed and only temporarily opens while the liquid pressure rises due to the active gate's reciprocating bubble motion. We have designed, fabricated and consistently operated our bubble pump with a variety of working liquids for >72 hours. Flow rates of 0-5.5 μl min(-1), were obtained and depended on the selected geometric dimensions, working fluids and actuation frequencies. The maximum operational pressure was 2.9 kPa-9.1 kPa and depended on the interfacial tension of the working fluids. Attainable flow rates compared favorably with those of available micropumps. We achieved flow rate enhancements of 30-100% by operating two bubble pumps in tandem and demonstrated scalability of the concept in a multi-well format with 12 individually and uniformly perfused microchannels (variation in flow rate <7%). We envision the demonstrated concept to allow for the consistent on-chip delivery of a wide range of different liquids that may even include highly reactive or moisture sensitive solutions. The presented bubble pump may provide active flow control for analytical and point-of-care diagnostic devices, as well as for microfluidic cells culture and organ-on-chip platforms.

RAM Technology Study.

DTIC Science & Technology

1980-01-03

characteristics. 4 2 Example of MOS scaling. 18 3 RAM chip area comparison. 31 4 Summary of RAM switching response. 34 5 Summary of RAM power dissipation...array to retain the data after power is removed (volatility). The level of chip complexity is that of the most complex arrays in current production and is...4) ..4 L) . C U ~~~~ -- -- t 0 -, 4 4 . . Data in the Read-Only-Memory is defined by the metallization pattern during chip fabrication. The stored

Tag Array gene chip rapid diagnosis anti-tuberculosis drug resistance in pulmonary tuberculosis -a feasibility study.

PubMed

Wu, Wenjie; Cheng, Peng; Lyu, Jingtong; Zhang, Zehua; Xu, Jianzhong

2018-05-01

We developed a Tag Array chip for detecting first- and second-line anti tuberculosis drug resistance in pulmonary tuberculosis and compared the analytical performance of the gene chip to that of phenotypic drug susceptibility testing (DST). From November 2011 to April 2016.234 consecutive culture-confirmed, clinically and imaging diagnosed patients with pulmonary tuberculosis from Southwest Hospital, Chongqing were enrolled into the study. Specimens collected during sputum or bronchoalveolar lavage fluid from the pulmonary tuberculosis patients were subjected to M. tuberculosis species identification and drug-resistance detection by the Tag Array gene chip, and evaluate the sensitivity and specificity of chip. A total of 186 patients was diagnosed drug-resistant tuberculosis. The detection of rifampicin (RFP), isoniazid (INH), fluoroquinolones (FQS), streptomycin (SM) resistance genes was highly sensitive and specific: however, for detection of amikacin (AMK), capreomycin (CPM), Kanamycin (KM), specificity was higher, but sensitivity was lower. Sensitivity for the detection of a mutation in the eis promoter region could be improved. The detection sensitivity of the EMB resistance gene was low, therefore it is easy to miss a diagnosis of EMB drug resistance, but its specificity was high. Tag Array chip can achieve rapid, accurate and high-throughput detection of tuberculosis resistance in pulmonary tuberculosis, which has important clinical significance and feasibility. Copyright © 2018. Published by Elsevier Ltd.

Use of Field Programmable Gate Array Technology in Future Space Avionics

NASA Technical Reports Server (NTRS)

Ferguson, Roscoe C.; Tate, Robert

2005-01-01

Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.

Ultrasound phase rotation beamforming on multi-core DSP.

PubMed

Ma, Jieming; Karadayi, Kerem; Ali, Murtaza; Kim, Yongmin

2014-01-01

Phase rotation beamforming (PRBF) is a commonly-used digital receive beamforming technique. However, due to its high computational requirement, it has traditionally been supported by hardwired architectures, e.g., application-specific integrated circuits (ASICs) or more recently field-programmable gate arrays (FPGAs). In this study, we investigated the feasibility of supporting software-based PRBF on a multi-core DSP. To alleviate the high computing requirement, the analog front-end (AFE) chips integrating quadrature demodulation in addition to analog-to-digital conversion were defined and used. With these new AFE chips, only delay alignment and phase rotation need to be performed by DSP, substantially reducing the computational load. We implemented the delay alignment and phase rotation modules on a Texas Instruments C6678 DSP with 8 cores. We found it takes 200 μs to beamform 2048 samples from 64 channels using 2 cores. With 4 cores, 20 million samples can be beamformed in one second. Therefore, ADC frequencies up to 40 MHz with 2:1 decimation in AFE chips or up to 20 MHz with no decimation can be supported as long as the ADC-to-DSP I/O requirement can be met. The remaining 4 cores can work on back-end processing tasks and applications, e.g., color Doppler or ultrasound elastography. One DSP being able to handle both beamforming and back-end processing could lead to low-power and low-cost ultrasound machines, benefiting ultrasound imaging in general, particularly portable ultrasound machines. Copyright © 2013 Elsevier B.V. All rights reserved.

Metabolic enzyme microarray coupled with miniaturized cell-culture array technology for high-throughput toxicity screening.

PubMed

Lee, Moo-Yeal; Dordick, Jonathan S; Clark, Douglas S

2010-01-01

Due to poor drug candidate safety profiles that are often identified late in the drug development process, the clinical progression of new chemical entities to pharmaceuticals remains hindered, thus resulting in the high cost of drug discovery. To accelerate the identification of safer drug candidates and improve the clinical progression of drug candidates to pharmaceuticals, it is important to develop high-throughput tools that can provide early-stage predictive toxicology data. In particular, in vitro cell-based systems that can accurately mimic the human in vivo response and predict the impact of drug candidates on human toxicology are needed to accelerate the assessment of drug candidate toxicity and human metabolism earlier in the drug development process. The in vitro techniques that provide a high degree of human toxicity prediction will be perhaps more important in cosmetic and chemical industries in Europe, as animal toxicity testing is being phased out entirely in the immediate future.We have developed a metabolic enzyme microarray (the Metabolizing Enzyme Toxicology Assay Chip, or MetaChip) and a miniaturized three-dimensional (3D) cell-culture array (the Data Analysis Toxicology Assay Chip, or DataChip) for high-throughput toxicity screening of target compounds and their metabolic enzyme-generated products. The human or rat MetaChip contains an array of encapsulated metabolic enzymes that is designed to emulate the metabolic reactions in the human or rat liver. The human or rat DataChip contains an array of 3D human or rat cells encapsulated in alginate gels for cell-based toxicity screening. By combining the DataChip with the complementary MetaChip, in vitro toxicity results are obtained that correlate well with in vivo rat data.

Chip-based microtrap arrays for cold polar molecules

NASA Astrophysics Data System (ADS)

Hou, Shunyong; Wei, Bin; Deng, Lianzhong; Yin, Jianping

2017-12-01

Compared to the atomic chip, which has been a powerful platform to perform an astonishing range of applications from rapid Bose-Einstein condensate (BEC) production to the atomic clock, the molecular chip is only in its infant stages. Recently a one-dimensional electric lattice was demonstrated to trap polar molecules on a chip. This excellent work opens up the way to building a molecular chip laboratory. Here we propose a two-dimensional (2D) electric lattice on a chip with concise and robust structure, which is formed by arrays of squared gold wires. Arrays of microtraps that originate in the microsize electrodes offer a steep gradient and thus allow for confining both light and heavy polar molecules. Theoretical analysis and numerical calculations are performed using two types of sample molecules, N D3 and SrF, to justify the possibility of our proposal. The height of the minima of the potential wells is about 10 μm above the surface of the chip and can be easily adjusted in a wide range by changing the voltages applied on the electrodes. These microtraps offer intriguing perspectives for investigating cold molecules in periodic potentials, such as quantum computing science, low-dimensional physics, and some other possible applications amenable to magnetic or optical lattice. The 2D adjustable electric lattice is expected to act as a building block for a future gas-phase molecular chip laboratory.

Gate protective device for SOS array

NASA Technical Reports Server (NTRS)

Meyer, J. E., Jr.; Scott, J. H.

1972-01-01

Protective gate device consisting of alternating heavily doped n(+) and p(+) diffusions eliminates breakdown voltages in silicon oxide on sapphire arrays caused by electrostatic discharge from person or equipment. Diffusions are easily produced during normal double epitaxial processing. Devices with nine layers had 27-volt breakdown.

High-performance genetic analysis on microfabricated capillary array electrophoresis plastic chips fabricated by injection molding.

PubMed

Dang, Fuquan; Tabata, Osamu; Kurokawa, Masaya; Ewis, Ashraf A; Zhang, Lihua; Yamaoka, Yoshihisa; Shinohara, Shouji; Shinohara, Yasuo; Ishikawa, Mitsuru; Baba, Yoshinobu

2005-04-01

We have developed a novel technique for mass production of microfabricated capillary array electrophoresis (mu-CAE) plastic chips for high-speed, high-throughput genetic analysis. The mu-CAE chips, containing 10 individual separation channels of 50-microm width, 50-microm depth, and a 100-microm lane-to-lane spacing at the detection region and a sacrificial channel network, were fabricated on a poly(methyl methacrylate) substrate by injection molding and then bonded manually using a pressure-sensitive sealing tape within several seconds at room temperature. The conditions for injection molding and bonding were carefully characterized to yield mu-CAE chips with well-defined channel and injection structures. A CCD camera equipped with an image intensifier was used to monitor simultaneously the separation in a 10-channel array with laser-induced fluorescence detection. High-performance electrophoretic separations of phiX174 HaeIII DNA restriction fragments and PCR products related to the human beta-globin gene and SP-B gene (the surfactant protein B) have been demonstrated on mu-CAE plastic chips using a methylcellulose sieving matrix in individual channels. The current work demonstrated greatly simplified the fabrication process as well as a detection scheme for mu-CAE chips and will bring the low-cost mass production and application of mu-CAE plastic chips for genetic analysis.

Read-In Integrated Circuits for Large-Format Multi-Chip Emitter Arrays

DTIC Science & Technology

2015-03-31

chip has been designed and fabricated using ONSEMI C5N process to verify our approach. Keywords: Large scale arrays; Tiling; Mosaic; Abutment ...required. X and y addressing is not a sustainable and easily expanded addressing architecture nor will it work well with abutted RIICs. Abutment Method... Abutting RIICs into an array is challenging because of the precise positioning required to achieve a uniform image. This problem is a new design

Electromechanical Displacement Detection With an On-Chip High Electron Mobility Transistor Amplifier

NASA Astrophysics Data System (ADS)

Oda, Yasuhiko; Onomitsu, Koji; Kometani, Reo; Warisawa, Shin-ichi; Ishihara, Sunao; Yamaguchi, Hiroshi

2011-06-01

We developed a highly sensitive displacement detection scheme for a GaAs-based electromechanical resonator using an integrated high electron mobility transistor (HEMT). Piezoelectric voltage generated by the vibration of the resonator is applied to the gate of the HEMT, resulting in the on-chip amplification of the signal voltage. This detection scheme achieves a displacement sensitivity of ˜9 pm·Hz-1/2, which is one of the highest among on-chip purely electrical displacement detection schemes at room temperature.

Oxide-confined 2D VCSEL arrays for high-density inter/intra-chip interconnects

NASA Astrophysics Data System (ADS)

King, Roger; Michalzik, Rainer; Jung, Christian; Grabherr, Martin; Eberhard, Franz; Jaeger, Roland; Schnitzer, Peter; Ebeling, Karl J.

1998-04-01

We have designed and fabricated 4 X 8 vertical-cavity surface-emitting laser (VCSEL) arrays intended to be used as transmitters in short-distance parallel optical interconnects. In order to meet the requirements of 2D, high-speed optical links, each of the 32 laser diodes is supplied with two individual top contacts. The metallization scheme allows flip-chip mounting of the array modules junction-side down on silicon complementary metal oxide semiconductor (CMOS) chips. The optical and electrical characteristics across the arrays with device pitch of 250 micrometers are quite homogeneous. Arrays with 3 micrometers , 6 micrometers and 10 micrometers active diameter lasers have been investigated. The small devices show threshold currents of 600 (mu) A, single-mode output powers as high as 3 mW and maximum wavelength deviations of only 3 nm. The driving characteristics of all arrays are fully compatible to advanced 3.3 V CMOS technology. Using these arrays, we have measured small-signal modulation bandwidths exceeding 10 GHz and transmitted pseudo random data at 8 Gbit/s channel over 500 m graded index multimode fiber. This corresponds to a data transmission rate of 256 Gbit/s per array of 1 X 2 mm2 footprint area.

Design considerations for FET-gated power transistors

NASA Technical Reports Server (NTRS)

Chen, D. Y.; Chin, S. A.

1983-01-01

An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.

High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip.

PubMed

Issadore, David; Franke, Thomas; Brown, Keith A; Hunt, Thomas P; Westervelt, Robert M

2009-12-01

A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm(2) in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip's surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications.

Estimation and partitioning of (co)heritability of inflammatory bowel disease from GWAS and immunochip data.

PubMed

Chen, Guo-Bo; Lee, Sang Hong; Brion, Marie-Jo A; Montgomery, Grant W; Wray, Naomi R; Radford-Smith, Graham L; Visscher, Peter M

2014-09-01

As custom arrays are cheaper than generic GWAS arrays, larger sample size is achievable for gene discovery. Custom arrays can tag more variants through denser genotyping of SNPs at associated loci, but at the cost of losing genome-wide coverage. Balancing this trade-off is important for maximizing experimental designs. We quantified both the gain in captured SNP-heritability at known candidate regions and the loss due to imperfect genome-wide coverage for inflammatory bowel disease using immunochip (iChip) and imputed GWAS data on 61,251 and 38.550 samples, respectively. For Crohn's disease (CD), the iChip and GWAS data explained 19 and 26% of variation in liability, respectively, and SNPs in the densely genotyped iChip regions explained 13% of the SNP-heritability for both the iChip and GWAS data. For ulcerative colitis (UC), the iChip and GWAS data explained 15 and 19% of variation in liability, respectively, and the dense iChip regions explained 10 and 9% of the SNP-heritability in the iChip and the GWAS data. From bivariate analyses, estimates of the genetic correlation in risk between CD and UC were 0.75 (SE 0.017) and 0.62 (SE 0.042) for the iChip and GWAS data, respectively. We also quantified the SNP-heritability of genomic regions that did or did not contain the previous 163 GWAS hits for CD and UC, and SNP-heritability of the overlapping loci between the densely genotyped iChip regions and the 163 GWAS hits. For both diseases, over different genomic partitioning, the densely genotyped regions on the iChip tagged at least as much variation in liability as in the corresponding regions in the GWAS data, however a certain amount of tagged SNP-heritability in the GWAS data was lost using the iChip due to the low coverage at unselected regions. These results imply that custom arrays with a GWAS backbone will facilitate more gene discovery, both at associated and novel loci. © The Author 2014. Published by Oxford University Press. All rights reserved. For Permissions, please email: journals.permissions@oup.com.

Electrochemical microfluidic chip based on molecular imprinting technique applied for therapeutic drug monitoring.

PubMed

Liu, Jiang; Zhang, Yu; Jiang, Min; Tian, Liping; Sun, Shiguo; Zhao, Na; Zhao, Feilang; Li, Yingchun

2017-05-15

In this work, a novel electrochemical detection platform was established by integrating molecularly imprinting technique with microfluidic chip and applied for trace measurement of three therapeutic drugs. The chip foundation is acrylic panel with designed grooves. In the detection cell of the chip, a Pt wire is used as the counter electrode and reference electrode, and a Au-Ag alloy microwire (NPAMW) with 3D nanoporous surface modified with electro-polymerized molecularly imprinted polymer (MIP) film as the working electrode. Detailed characterization of the chip and the working electrode was performed, and the properties were explored by cyclic voltammetry and electrochemical impedance spectroscopy. Two methods, respectively based on electrochemical catalysis and MIP/gate effect were employed for detecting warfarin sodium by using the prepared chip. The linearity of electrochemical catalysis method was in the range of 5×10 -6 -4×10 -4 M, which fails to meet clinical testing demand. By contrast, the linearity of gate effect was 2×10 -11 -4×10 -9 M with remarkably low detection limit of 8×10 -12 M (S/N=3), which is able to satisfy clinical assay. Then the system was applied for 24-h monitoring of drug concentration in plasma after administration of warfarin sodium in rabbit, and the corresponding pharmacokinetic parameters were obtained. In addition, the microfluidic chip was successfully adopted to analyze cyclophosphamide and carbamazepine, implying its good versatile ability. It is expected that this novel electrochemical microfluidic chip can act as a promising format for point-of-care testing via monitoring different analytes sensitively and conveniently. Copyright © 2017 Elsevier B.V. All rights reserved.

The GenoChip: A New Tool for Genetic Anthropology

PubMed Central

Elhaik, Eran; Greenspan, Elliott; Staats, Sean; Krahn, Thomas; Tyler-Smith, Chris; Xue, Yali; Tofanelli, Sergio; Francalacci, Paolo; Cucca, Francesco; Pagani, Luca; Jin, Li; Li, Hui; Schurr, Theodore G.; Greenspan, Bennett; Spencer Wells, R.

2013-01-01

The Genographic Project is an international effort aimed at charting human migratory history. The project is nonprofit and nonmedical, and, through its Legacy Fund, supports locally led efforts to preserve indigenous and traditional cultures. Although the first phase of the project was focused on uniparentally inherited markers on the Y-chromosome and mitochondrial DNA (mtDNA), the current phase focuses on markers from across the entire genome to obtain a more complete understanding of human genetic variation. Although many commercial arrays exist for genome-wide single-nucleotide polymorphism (SNP) genotyping, they were designed for medical genetic studies and contain medically related markers that are inappropriate for global population genetic studies. GenoChip, the Genographic Project’s new genotyping array, was designed to resolve these issues and enable higher resolution research into outstanding questions in genetic anthropology. The GenoChip includes ancestry informative markers obtained for over 450 human populations, an ancient human (Saqqaq), and two archaic hominins (Neanderthal and Denisovan) and was designed to identify all known Y-chromosome and mtDNA haplogroups. The chip was carefully vetted to avoid inclusion of medically relevant markers. To demonstrate its capabilities, we compared the FST distributions of GenoChip SNPs to those of two commercial arrays. Although all arrays yielded similarly shaped (inverse J) FST distributions, the GenoChip autosomal and X-chromosomal distributions had the highest mean FST, attesting to its ability to discern subpopulations. The chip performances are illustrated in a principal component analysis for 14 worldwide populations. In summary, the GenoChip is a dedicated genotyping platform for genetic anthropology. With an unprecedented number of approximately 12,000 Y-chromosomal and approximately 3,300 mtDNA SNPs and over 130,000 autosomal and X-chromosomal SNPs without any known health, medical, or phenotypic relevance, the GenoChip is a useful tool for genetic anthropology and population genetics. PMID:23666864

The GenoChip: a new tool for genetic anthropology.

PubMed

Elhaik, Eran; Greenspan, Elliott; Staats, Sean; Krahn, Thomas; Tyler-Smith, Chris; Xue, Yali; Tofanelli, Sergio; Francalacci, Paolo; Cucca, Francesco; Pagani, Luca; Jin, Li; Li, Hui; Schurr, Theodore G; Greenspan, Bennett; Spencer Wells, R

2013-01-01

The Genographic Project is an international effort aimed at charting human migratory history. The project is nonprofit and nonmedical, and, through its Legacy Fund, supports locally led efforts to preserve indigenous and traditional cultures. Although the first phase of the project was focused on uniparentally inherited markers on the Y-chromosome and mitochondrial DNA (mtDNA), the current phase focuses on markers from across the entire genome to obtain a more complete understanding of human genetic variation. Although many commercial arrays exist for genome-wide single-nucleotide polymorphism (SNP) genotyping, they were designed for medical genetic studies and contain medically related markers that are inappropriate for global population genetic studies. GenoChip, the Genographic Project's new genotyping array, was designed to resolve these issues and enable higher resolution research into outstanding questions in genetic anthropology. The GenoChip includes ancestry informative markers obtained for over 450 human populations, an ancient human (Saqqaq), and two archaic hominins (Neanderthal and Denisovan) and was designed to identify all known Y-chromosome and mtDNA haplogroups. The chip was carefully vetted to avoid inclusion of medically relevant markers. To demonstrate its capabilities, we compared the FST distributions of GenoChip SNPs to those of two commercial arrays. Although all arrays yielded similarly shaped (inverse J) FST distributions, the GenoChip autosomal and X-chromosomal distributions had the highest mean FST, attesting to its ability to discern subpopulations. The chip performances are illustrated in a principal component analysis for 14 worldwide populations. In summary, the GenoChip is a dedicated genotyping platform for genetic anthropology. With an unprecedented number of approximately 12,000 Y-chromosomal and approximately 3,300 mtDNA SNPs and over 130,000 autosomal and X-chromosomal SNPs without any known health, medical, or phenotypic relevance, the GenoChip is a useful tool for genetic anthropology and population genetics.

MethLAB

PubMed Central

Kilaru, Varun; Barfield, Richard T; Schroeder, James W; Smith, Alicia K

2012-01-01

Recent evidence suggests that DNA methylation changes may underlie numerous complex traits and diseases. The advent of commercial, array-based methods to interrogate DNA methylation has led to a profusion of epigenetic studies in the literature. Array-based methods, such as the popular Illumina GoldenGate and Infinium platforms, estimate the proportion of DNA methylated at single-base resolution for thousands of CpG sites across the genome. These arrays generate enormous amounts of data, but few software resources exist for efficient and flexible analysis of these data. We developed a software package called MethLAB (http://genetics.emory.edu/conneely/MethLAB) using R, an open source statistical language that can be edited to suit the needs of the user. MethLAB features a graphical user interface (GUI) with a menu-driven format designed to efficiently read in and manipulate array-based methylation data in a user-friendly manner. MethLAB tests for association between methylation and relevant phenotypes by fitting a separate linear model for each CpG site. These models can incorporate both continuous and categorical phenotypes and covariates, as well as fixed or random batch or chip effects. MethLAB accounts for multiple testing by controlling the false discovery rate (FDR) at a user-specified level. Standard output includes a spreadsheet-ready text file and an array of publication-quality figures. Considering the growing interest in and availability of DNA methylation data, there is a great need for user-friendly open source analytical tools. With MethLAB, we present a timely resource that will allow users with no programming experience to implement flexible and powerful analyses of DNA methylation data. PMID:22430798

Disposable MoS2-Arrayed MALDI MS Chip for High-Throughput and Rapid Quantification of Sulfonamides in Multiple Real Samples.

PubMed

Zhao, Yaju; Tang, Minmin; Liao, Qiaobo; Li, Zhoumin; Li, Hui; Xi, Kai; Tan, Li; Zhang, Mei; Xu, Danke; Chen, Hong-Yuan

2018-04-27

In this work, we demonstrate, for the first time, the development of a disposable MoS 2 -arrayed matrix-assisted laser desorption/ionization mass spectrometry (MALDI MS) chip combined with an immunoaffinity enrichment method for high-throughput, rapid, and simultaneous quantitation of multiple sulfonamides (SAs). The disposable MALDI MS chip was designed and fabricated by MoS 2 array formation on a commercial indium tin oxide (ITO) glass slide. A series of SAs were analyzed, and clear deprotonated signals were obtained in negative-ion mode. Compared with MoS 2 -arrayed commercial steel plate, the prepared MALDI MS chip exhibited comparable LDI efficiency, providing a good alternative and disposable substrate for MALDI MS analysis. Furthermore, internal standard (IS) was previously deposited onto the MoS 2 array to simplify the experimental process for MALDI MS quantitation. 96 sample spots could be analyzed within 10 min in one single chip to perform quantitative analysis, recovery studies, and real foodstuff detection. Upon targeted extraction and enrichment by antibody conjugated magnetic beads, five SAs were quantitatively determined by the IS-first method with the linear range of 0.5-10 ng/mL ( R 2 > 0.990). Good recoveries and repeatability were obtained for spiked pork, egg, and milk samples. SAs in several real foodstuffs were successfully identified and quantified. The developed method may provide a promising tool for the routine analysis of antibiotic residues in real samples.

CHIP, CHIP, ARRAY! THREE CHIPS FOR POST-GENOMIC RESEARCH

EPA Science Inventory

Cambridge Healthtech Institute recently held the 4th installment of their popular "Lab-on-a-Chip" series in Zurich, Switzerland. As usual, it was enthusiastically received and over 225 people attended the 2-1/2 day meeting to see and hear about some of the latest developments an...

Fabrication and characterization of microfabricated on-chip microelectrochemical cell for biosensing applications

NASA Astrophysics Data System (ADS)

Said, N. A. Mohd; Twomey, K.; Herzog, G.; Ogurtsov, V. I.

2017-03-01

The fabrication of on-chip microelectrochemical cell on Si wafer by means of photolithography is described here. The single on-chip microelectrochemical cell device has dimensions of 100 × 380 mm with integrated Pt counter electrode (CE), Ag/AgCl reference electrode (RE) and gold microelectrode array of 500 nm recess depth as the working electrode (WE). Two geometries of electrode array were implemented, band and disc, with fixed diameter/width of 10 µm; and varied centre-to-centre spacing (d) and number of electrodes (N) in the array. The on-chip microelectrochemical cell structure has been designed to facilitate further WE biomodifications. Firstly, the developed microelectrochemical cell does not require packaging hence reducing the production cost and time. Secondly, the working electrode (WE) on the microelectrochemical cell is positioned towards the end of the chip enabling modification of the working electrode surface to be carried out for surface bio-functionalisation without affecting both the RE and CE surface conditions. The developed on-chip microelectrochemical cell was examined with scanning electron microscopy (SEM) and characterised by two electrochemical techniques. Both cyclic voltammetry (CV) and electrochemical impedance spectroscopy (EIS) were performed in 1 mM ferrocenecarboxylic acid (FCA) in 0.01 M phosphate buffered saline (PBS) solution at pH7.4. Electrochemical experiments showed that in the case of halving the interspacing distance of the microdisc WE array (50 nm instead of 100 nm), the voltammogram shifted from a steady-state CV (feature of hemispherical diffusion) to an inclined peak-shaped CV (feature of linear diffusion) albeit the arrays had the same surface area. In terms of EIS it was also found that linear diffusion dominates the surface instead of hemispherical diffusion once the interspacing distance was reduced, supporting the fact that closely packed arrays may behave like a macroelectrode

Electronic Switch Arrays for Managing Microbattery Arrays

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Alahmad, Mahmoud; Sukumar, Vinesh; Zghoul, Fadi; Buck, Kevin; Hess, Herbert; Li, Harry; Cox, David

2008-01-01

Integrated circuits have been invented for managing the charging and discharging of such advanced miniature energy-storage devices as planar arrays of microscopic energy-storage elements [typically, microscopic electrochemical cells (microbatteries) or microcapacitors]. The architecture of these circuits enables implementation of the following energy-management options: dynamic configuration of the elements of an array into a series or parallel combination of banks (subarrarys), each array comprising a series of parallel combination of elements; direct addressing of individual banks for charging/or discharging; and, disconnection of defective elements and corresponding reconfiguration of the rest of the array to utilize the remaining functional elements to obtain the desited voltage and current performance. An integrated circuit according to the invention consists partly of a planar array of field-effect transistors that function as switches for routing electric power among the energy-storage elements, the power source, and the load. To connect the energy-storage elements to the power source for charging, a specific subset of switches is closed; to connect the energy-storage elements to the load for discharging, a different specific set of switches is closed. Also included in the integrated circuit is circuitry for monitoring and controlling charging and discharging. The control and monitoring circuitry, the switching transistors, and interconnecting metal lines are laid out on the integrated-circuit chip in a pattern that registers with the array of energy-storage elements. There is a design option to either (1) fabricate the energy-storage elements in the corresponding locations on, and as an integral part of, this integrated circuit; or (2) following a flip-chip approach, fabricate the array of energy-storage elements on a separate integrated-circuit chip and then align and bond the two chips together.

Broadband Light Collection Efficiency Enhancement of Carbon Nanotube Excitons Coupled to Metallo-Dielectric Antenna Arrays

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shayan, Kamran; Rabut, Claire; Kong, Xiaoqing

The realization of on-chip quantum networks ideally requires lossless interfaces between photons and solid-state quantum emitters. We propose and demonstrate on-chip arrays of metallo-dielectric antennas (MDA) that are tailored toward efficient and broadband light collection from individual embedded carbon nanotube quantum emitters by trapping air gaps on chip that form cavity modes. Scalable implementation is realized by employing polymer layer dry-transfer techniques that avoid solvent incompatibility issues, as well as a planar design that avoids solid-immersion lenses. Cryogenic measurements demonstrate 7-fold enhanced exciton intensity when compared to emitters located on bare wafers, corresponding to a light collection efficiency (LCE) upmore » to 92% in the best case (average LCE of 69%) into a narrow output cone of +/-15 degrees that enables a priori fiber-to-chip butt coupling. The demonstrated MDA arrays are directly compatible with other quantum systems, particularly 2D materials, toward enabling efficient on-chip quantum light sources or spin-photon interfaces requiring unity light collection, both at cryogenic or room temperature.« less

Low-frequency interferometry: Design, calibration, and analysis towards detecting the epoch of reionization

NASA Astrophysics Data System (ADS)

Parsons, Aaron Robert

Low-frequency interferometry provides us with the possibility of directly observing, via red-shifted 21cm emission, the ionization of the primordial intergalactic medium by radiation from the first stars and black holes. Building such interferometers presents daunting technical challenges related to the cross-correlation, calibration, and analysis of data from large antenna arrays with wide fields-of-view in an observing band below 200 MHz. Addressing cross-correlation data processing, I present a general-purpose correlator architecture that uses standard 10-Gbit Ethernet switches to pass data between flexible hardware modules containing Field Programmable Gate Array chips. These chips are programmed using open-source signal processing libraries developed to be flexible, scalable, and chip-independent. This work reduces the time and cost of implementing a wide range of signal processing systems, and facilitates upgrading to new generations of processing technology. This correlator architecture is supporting the incremental build-out of the Precision Array for Probing the Epoch of Reionization. Targeting calibration concerns, I present a filtering technique that can be applied to individual baselines of wide-bandwidth, wide-field interferometric data to geometrically select regions on the celestial sphere that contain primary calibration sources. The technique relies on the Fourier transformation of wide-band frequency spectra from a given baseline to obtain one-dimensional "delay images", and then the transformation of a time-series of delay images to obtain two-dimensional "delay/delayrate images." These filters are augmented by a one-dimensional, complex CLEAN algorithm has been developed to compensate for data-excision effects related to the removal of radio frequency interference. This approach allows CLEANed, source-isolated data to be used to isolate bandpass and primary beam gain functions. These techniques are applied to PAPER data as a demonstration of their value in calibrating a new generation of low-frequency radio interferometers with wide relative bandwidths and large fields-of-view. Finally, I describe PAPER's overall architecture and summarize two PAPER deployments: a 4-antenna array in of Western Australia and an 8-antenna array in Green Bank, WV. After reporting on system characterization and data analysis techniques, I present an all-sky map synthesized between 139 MHz and 174 MHz using data from both arrays that reaches down to 80 mJy (4.9 K, for a beam size of 2.15e-5 steradians at 154 MHz), with a 10 mJy (620 mK) thermal noise level that indicates what would be achievable with better foreground subtraction. I calculate angular power spectra (Cℓ) in a cold patch and determine them to be dominated by point sources. Although the sample variance of foregrounds dominates errors in these power spectra, I measure a thermal noise level of 310 mK at ℓ = 100 for a 1.46-MHz band centered at 164.5 MHz. This sensitivity level is approximately three orders of magnitude in temperature above the expected level of 21cm fluctuations associated with reionization.

An IO block array in a radiation-hardened SOI SRAM-based FPGA

NASA Astrophysics Data System (ADS)

Yan, Zhao; Lihua, Wu; Xiaowei, Han; Yan, Li; Qianli, Zhang; Liang, Chen; Guoquan, Zhang; Jianzhong, Li; Bo, Yang; Jiantou, Gao; Jian, Wang; Ming, Li; Guizhai, Liu; Feng, Zhang; Xufeng, Guo; Kai, Zhao; Chen, Stanley L.; Fang, Yu; Zhongli, Liu

2012-01-01

We present an input/output block (IOB) array used in the radiation-hardened SRAM-based field-programmable gate array (FPGA) VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the programmable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different capacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad(Si), a dose survivability rate of 1.5 × 1011 rad(Si)/s, and a neutron fluence immunity of 1 × 1014 n/cm2.

Design and performance of single photon APD focal plane arrays for 3-D LADAR imaging

NASA Astrophysics Data System (ADS)

Itzler, Mark A.; Entwistle, Mark; Owens, Mark; Patel, Ketan; Jiang, Xudong; Slomkowski, Krystyna; Rangwala, Sabbir; Zalud, Peter F.; Senko, Tom; Tower, John; Ferraro, Joseph

2010-08-01

×We describe the design, fabrication, and performance of focal plane arrays (FPAs) for use in 3-D LADAR imaging applications requiring single photon sensitivity. These 32 × 32 FPAs provide high-efficiency single photon sensitivity for three-dimensional LADAR imaging applications at 1064 nm. Our GmAPD arrays are designed using a planarpassivated avalanche photodiode device platform with buried p-n junctions that has demonstrated excellent performance uniformity, operational stability, and long-term reliability. The core of the FPA is a chip stack formed by hybridizing the GmAPD photodiode array to a custom CMOS read-out integrated circuit (ROIC) and attaching a precision-aligned GaP microlens array (MLA) to the back-illuminated detector array. Each ROIC pixel includes an active quenching circuit governing Geiger-mode operation of the corresponding avalanche photodiode pixel as well as a pseudo-random counter to capture per-pixel time-of-flight timestamps in each frame. The FPA has been designed to operate at frame rates as high as 186 kHz for 2 μs range gates. Effective single photon detection efficiencies as high as 40% (including all optical transmission and MLA losses) are achieved for dark count rates below 20 kHz. For these planar-geometry diffused-junction GmAPDs, isolation trenches are used to reduce crosstalk due to hot carrier luminescence effects during avalanche events, and we present details of the crosstalk performance for different operating conditions. Direct measurement of temporal probability distribution functions due to cumulative timing uncertainties of the GmAPDs and ROIC circuitry has demonstrated a FWHM timing jitter as low as 265 ps (standard deviation is ~100 ps).

MethLAB: a graphical user interface package for the analysis of array-based DNA methylation data.

PubMed

Kilaru, Varun; Barfield, Richard T; Schroeder, James W; Smith, Alicia K; Conneely, Karen N

2012-03-01

Recent evidence suggests that DNA methylation changes may underlie numerous complex traits and diseases. The advent of commercial, array-based methods to interrogate DNA methylation has led to a profusion of epigenetic studies in the literature. Array-based methods, such as the popular Illumina GoldenGate and Infinium platforms, estimate the proportion of DNA methylated at single-base resolution for thousands of CpG sites across the genome. These arrays generate enormous amounts of data, but few software resources exist for efficient and flexible analysis of these data. We developed a software package called MethLAB (http://genetics.emory.edu/conneely/MethLAB) using R, an open source statistical language that can be edited to suit the needs of the user. MethLAB features a graphical user interface (GUI) with a menu-driven format designed to efficiently read in and manipulate array-based methylation data in a user-friendly manner. MethLAB tests for association between methylation and relevant phenotypes by fitting a separate linear model for each CpG site. These models can incorporate both continuous and categorical phenotypes and covariates, as well as fixed or random batch or chip effects. MethLAB accounts for multiple testing by controlling the false discovery rate (FDR) at a user-specified level. Standard output includes a spreadsheet-ready text file and an array of publication-quality figures. Considering the growing interest in and availability of DNA methylation data, there is a great need for user-friendly open source analytical tools. With MethLAB, we present a timely resource that will allow users with no programming experience to implement flexible and powerful analyses of DNA methylation data.

Dependence of the 0.7 anomaly on the curvature of the potential barrier in quantum wires

NASA Astrophysics Data System (ADS)

Smith, L. W.; Al-Taie, H.; Lesage, A. A. J.; Sfigakis, F.; See, P.; Griffiths, J. P.; Beere, H. E.; Jones, G. A. C.; Ritchie, D. A.; Hamilton, A. R.; Kelly, M. J.; Smith, C. G.

2015-06-01

Ninety-eight one-dimensional channels defined using split gates fabricated on a GaAs/AlGaAs heterostructure are measured during one cooldown at 1.4 K. The devices are arranged in an array on a single chip and are individually addressed using a multiplexing technique. The anomalous conductance feature known as the "0.7 structure" is studied using statistical techniques. The ensemble of data shows that the 0.7 anomaly becomes more pronounced and occurs at lower values as the curvature of the potential barrier in the transport direction decreases. This corresponds to an increase in the effective length of the device. The 0.7 anomaly is not strongly influenced by other properties of the conductance related to density. The curvature of the potential barrier appears to be the primary factor governing the shape of the 0.7 structure at a given T and B .

A digitalized silicon microgyroscope based on embedded FPGA.

PubMed

Xia, Dunzhu; Yu, Cheng; Wang, Yuliang

2012-09-27

This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high-speed 18-bit analog to digital convertor, a high-performance core Field Programmable Gate Array (FPGA) chip and other peripherals such as high-speed serial ports for transmitting data. In drive mode, the closed-loop drive circuit are implemented by automatic gain control (AGC) loop and software phase-locked loop (SPLL) based on the Coordinated Rotation Digital Computer (CORDIC) algorithm. Meanwhile, the sense demodulation module based on varying step least mean square demodulation (LMSD) are addressed in detail. All kinds of algorithms are simulated by Simulink and DSPbuilder tools, which is in good agreement with the theoretical design. The experimental results have fully demonstrated the stability and flexibility of the system.

A Digitalized Silicon Microgyroscope Based on Embedded FPGA

PubMed Central

Xia, Dunzhu; Yu, Cheng; Wang, Yuliang

2012-01-01

This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high-speed 18-bit analog to digital convertor, a high-performance core Field Programmable Gate Array (FPGA) chip and other peripherals such as high-speed serial ports for transmitting data. In drive mode, the closed-loop drive circuit are implemented by automatic gain control (AGC) loop and software phase-locked loop (SPLL) based on the Coordinated Rotation Digital Computer (CORDIC) algorithm. Meanwhile, the sense demodulation module based on varying step least mean square demodulation (LMSD) are addressed in detail. All kinds of algorithms are simulated by Simulink and DSPbuilder tools, which is in good agreement with the theoretical design. The experimental results have fully demonstrated the stability and flexibility of the system. PMID:23201990

DOE Office of Scientific and Technical Information (OSTI.GOV)

Harvey-Collard, Patrick; Jacobson, N. Tobias; Rudolph, Martin

Individual donors in silicon chips are used as quantum bits with extremely low error rates. However, physical realizations have been limited to one donor because their atomic size causes fabrication challenges. Quantum dot qubits, in contrast, are highly adjustable using electrical gate voltages. This adjustability could be leveraged to deterministically couple donors to quantum dots in arrays of qubits. In this work, we demonstrate the coherent interaction of a 31P donor electron with the electron of a metal-oxide-semiconductor quantum dot. We form a logical qubit encoded in the spin singlet and triplet states of the two-electron system. We show thatmore » the donor nuclear spin drives coherent rotations between the electronic qubit states through the contact hyperfine interaction. This provides every key element for compact two-electron spin qubits requiring only a single dot and no additional magnetic field gradients, as well as a means to interact with the nuclear spin qubit.« less

Performance evaluation of heart sound cancellation in FPGA hardware implementation for electronic stethoscope.

PubMed

Chao, Chun-Tang; Maneetien, Nopadon; Wang, Chi-Jo; Chiou, Juing-Shian

2014-01-01

This paper presents the design and evaluation of the hardware circuit for electronic stethoscopes with heart sound cancellation capabilities using field programmable gate arrays (FPGAs). The adaptive line enhancer (ALE) was adopted as the filtering methodology to reduce heart sound attributes from the breath sounds obtained via the electronic stethoscope pickup. FPGAs were utilized to implement the ALE functions in hardware to achieve near real-time breath sound processing. We believe that such an implementation is unprecedented and crucial toward a truly useful, standalone medical device in outpatient clinic settings. The implementation evaluation with one Altera cyclone II-EP2C70F89 shows that the proposed ALE used 45% resources of the chip. Experiments with the proposed prototype were made using DE2-70 emulation board with recorded body signals obtained from online medical archives. Clear suppressions were observed in our experiments from both the frequency domain and time domain perspectives.

A digital receiver module with direct data acquisition for magnetic resonance imaging systems.

PubMed

Tang, Weinan; Sun, Hongyu; Wang, Weimin

2012-10-01

A digital receiver module for magnetic resonance imaging (MRI) with detailed hardware implementations is presented. The module is based on a direct sampling scheme using the latest mixed-signal circuit design techniques. A single field-programmable gate array chip is employed to perform software-based digital down conversion for radio frequency signals. The modular architecture of the receiver allows multiple acquisition channels to be implemented on a highly integrated printed circuit board. To maintain the phase coherence of the receiver and the exciter in the context of direct sampling, an effective phase synchronization method was proposed to achieve a phase deviation as small as 0.09°. The performance of the described receiver module was verified in the experiments for both low- and high-field (0.5 T and 1.5 T) MRI scanners and was compared to a modern commercial MRI receiver system.

Heavy-Ion Microbeam Fault Injection into SRAM-Based FPGA Implementations of Cryptographic Circuits

NASA Astrophysics Data System (ADS)

Li, Huiyun; Du, Guanghua; Shao, Cuiping; Dai, Liang; Xu, Guoqing; Guo, Jinlong

2015-06-01

Transistors hit by heavy ions may conduct transiently, thereby introducing transient logic errors. Attackers can exploit these abnormal behaviors and extract sensitive information from the electronic devices. This paper demonstrates an ion irradiation fault injection attack experiment into a cryptographic field-programmable gate-array (FPGA) circuit. The experiment proved that the commercial FPGA chip is vulnerable to low-linear energy transfer carbon irradiation, and the attack can cause the leakage of secret key bits. A statistical model is established to estimate the possibility of an effective fault injection attack on cryptographic integrated circuits. The model incorporates the effects from temporal, spatial, and logical probability of an effective attack on the cryptographic circuits. The rate of successful attack calculated from the model conforms well to the experimental results. This quantitative success rate model can help evaluate security risk for designers as well as for the third-party assessment organizations.

Upgrading the Digital Electronics of the PEP-II Bunch Current Monitors at the Stanford Linear Accelerator Center

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kline, Josh; /SLAC

2006-08-28

The testing of the upgrade prototype for the bunch current monitors (BCMs) in the PEP-II storage rings at the Stanford Linear Accelerator Center (SLAC) is the topic of this paper. Bunch current monitors are used to measure the charge in the electron/positron bunches traveling in particle storage rings. The BCMs in the PEP-II storage rings need to be upgraded because components of the current system have failed and are known to be failure prone with age, and several of the integrated chips are no longer produced making repairs difficult if not impossible. The main upgrade is replacing twelve old (1995)more » field programmable gate arrays (FPGAs) with a single Virtex II FPGA. The prototype was tested using computer synthesis tools, a commercial signal generator, and a fast pulse generator.« less

Coherent all-optical control of ultracold atoms arrays in permanent magnetic traps.

PubMed

Abdelrahman, Ahmed; Mukai, Tetsuya; Häffner, Hartmut; Byrnes, Tim

2014-02-10

We propose a hybrid architecture for quantum information processing based on magnetically trapped ultracold atoms coupled via optical fields. The ultracold atoms, which can be either Bose-Einstein condensates or ensembles, are trapped in permanent magnetic traps and are placed in microcavities, connected by silica based waveguides on an atom chip structure. At each trapping center, the ultracold atoms form spin coherent states, serving as a quantum memory. An all-optical scheme is used to initialize, measure and perform a universal set of quantum gates on the single and two spin-coherent states where entanglement can be generated addressably between spatially separated trapped ultracold atoms. This allows for universal quantum operations on the spin coherent state quantum memories. We give detailed derivations of the composite cavity system mediated by a silica waveguide as well as the control scheme. Estimates for the necessary experimental conditions for a working hybrid device are given.

Measurement of charge transfer potential barrier in pinned photodiode CMOS image sensors

NASA Astrophysics Data System (ADS)

Chen, Cao; Bing, Zhang; Junfeng, Wang; Longsheng, Wu

2016-05-01

The charge transfer potential barrier (CTPB) formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode (PPD) CMOS image sensors (CIS), and is difficult to measure straightforwardly since it is embedded inside the device. From an understanding of the CTPB formation mechanism, we report on an alternative method to feasibly measure the CTPB height by performing a linear extrapolation coupled with a horizontal left-shift on the sensor photoresponse curve under the steady-state illumination. The theoretical study was performed in detail on the principle of the proposed method. Application of the measurements on a prototype PPD-CIS chip with an array of 160 × 160 pixels is demonstrated. Such a method intends to shine new light on the guidance for the lag-free and high-speed sensors optimization based on PPD devices. Project supported by the National Defense Pre-Research Foundation of China (No. 51311050301095).

Single-cell recording and stimulation with a 16k micro-nail electrode array integrated on a 0.18 μm CMOS chip.

PubMed

Huys, Roeland; Braeken, Dries; Jans, Danny; Stassen, Andim; Collaert, Nadine; Wouters, Jan; Loo, Josine; Severi, Simone; Vleugels, Frank; Callewaert, Geert; Verstreken, Kris; Bartic, Carmen; Eberle, Wolfgang

2012-04-07

To cope with the growing needs in research towards the understanding of cellular function and network dynamics, advanced micro-electrode arrays (MEAs) based on integrated complementary metal oxide semiconductor (CMOS) circuits have been increasingly reported. Although such arrays contain a large number of sensors for recording and/or stimulation, the size of the electrodes on these chips are often larger than a typical mammalian cell. Therefore, true single-cell recording and stimulation remains challenging. Single-cell resolution can be obtained by decreasing the size of the electrodes, which inherently increases the characteristic impedance and noise. Here, we present an array of 16,384 active sensors monolithically integrated on chip, realized in 0.18 μm CMOS technology for recording and stimulation of individual cells. Successful recording of electrical activity of cardiac cells with the chip, validated with intracellular whole-cell patch clamp recordings are presented, illustrating single-cell readout capability. Further, by applying a single-electrode stimulation protocol, we could pace individual cardiac cells, demonstrating single-cell addressability. This novel electrode array could help pave the way towards solving complex interactions of mammalian cellular networks. This journal is © The Royal Society of Chemistry 2012

GaAs VLSI technology and circuit elements for DSP

NASA Astrophysics Data System (ADS)

Mikkelson, James M.

1990-10-01

Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

64 x 64 thresholding photodetector array for optical pattern recognition

NASA Astrophysics Data System (ADS)

Langenbacher, Harry; Chao, Tien-Hsin; Shaw, Timothy; Yu, Jeffrey W.

1993-10-01

A high performance 32 X 32 peak detector array is introduced. This detector consists of a 32 X 32 array of thresholding photo-transistor cells, manufactured with a standard MOSIS digital 2-micron CMOS process. A built-in thresholding function that is able to perform 1024 thresholding operations in parallel strongly distinguishes this chip from available CCD detectors. This high speed detector offers responses from one to 10 milliseconds that is much higher than the commercially available CCD detectors operating at a TV frame rate. The parallel multiple peaks thresholding detection capability makes it particularly suitable for optical correlator and optoelectronically implemented neural networks. The principle of operation, circuit design and the performance characteristics are described. Experimental demonstration of correlation peak detection is also provided. Recently, we have also designed and built an advanced version of a 64 X 64 thresholding photodetector array chip. Experimental investigation of using this chip for pattern recognition is ongoing.

Electrolyte-gated transistors based on conducting polymer nanowire junction arrays.

PubMed

Alam, Maksudul M; Wang, Jun; Guo, Yaoyao; Lee, Stephanie P; Tseng, Hsian-Rong

2005-07-07

In this study, we describe the electrolyte gating and doping effects of transistors based on conducting polymer nanowire electrode junction arrays in buffered aqueous media. Conducting polymer nanowires including polyaniline, polypyrrole, and poly(ethylenedioxythiophene) were investigated. In the presence of a positive gate bias, the device exhibits a large on/off current ratio of 978 for polyaniline nanowire-based transistors; these values vary according to the acidity of the gate medium. We attribute these efficient electrolyte gating and doping effects to the electrochemically fabricated nanostructures of conducting polymer nanowires. This study demonstrates that two-terminal devices can be easily converted into three-terminal transistors by simply immersing the device into an electrolyte solution along with a gate electrode. Here, the field-induced modulation can be applied for signal amplification to enhance the device performance.

Development and fabrication of low ON resistance high current vertical VMOS power FETs

NASA Technical Reports Server (NTRS)

Kay, S.

1979-01-01

The design of a VMOS Power FET exhibiting low ON resistance, high current as well as high breakdown voltage and fast switching speeds is described. The design which is based on a 1st-order device model, features a novel polysilicon-gate structure and fieldplated groove termination to achieve high packing density and high breakdown voltage, respectively. One test chip, named VNTKI, can block 180 V at an ON resistence of 2.5 ohm. A 150 mil x 200 mil (.19 sq cm) experimental chip has demonstrated a breakdown voltage of 200v, an ON resistance of 0.12 ohm, a switching time of less than 100 ns, and a pulse drain - current of 50 A with 10 V gate drive.

Micro-array isolation of circulating tumor cells (CTCs): the droplet biopsy chip

NASA Astrophysics Data System (ADS)

Panchapakesan, B.

2017-08-01

We present a new method for circulating tumor cell capture based on micro-array isolation from droplets. Called droplet biopsy, our technique uses a 76-element array of carbon nanotube devices functionalized with anti-EpCAM and antiHer2 antibodies for immunocapture of spiked breast cancer cells in the blood. This droplet biopsy chip can enable capture of CTCs based on both positive and negative selection strategy. Negative selection is achieved through depletion of contaminating leukocytes through the differential settling of blood into layers. We report 55%-100% cancer cell capture yield in this first droplet biopsy chip study. The droplet biopsy is an enabling idea where one can capture CTCs based on multiple biomarkers in a single blood sample.

Fine-grained parallel RNAalifold algorithm for RNA secondary structure prediction on FPGA

PubMed Central

Xia, Fei; Dou, Yong; Zhou, Xingming; Yang, Xuejun; Xu, Jiaqing; Zhang, Yang

2009-01-01

Background In the field of RNA secondary structure prediction, the RNAalifold algorithm is one of the most popular methods using free energy minimization. However, general-purpose computers including parallel computers or multi-core computers exhibit parallel efficiency of no more than 50%. Field Programmable Gate-Array (FPGA) chips provide a new approach to accelerate RNAalifold by exploiting fine-grained custom design. Results RNAalifold shows complicated data dependences, in which the dependence distance is variable, and the dependence direction is also across two dimensions. We propose a systolic array structure including one master Processing Element (PE) and multiple slave PEs for fine grain hardware implementation on FPGA. We exploit data reuse schemes to reduce the need to load energy matrices from external memory. We also propose several methods to reduce energy table parameter size by 80%. Conclusion To our knowledge, our implementation with 16 PEs is the only FPGA accelerator implementing the complete RNAalifold algorithm. The experimental results show a factor of 12.2 speedup over the RNAalifold (ViennaPackage – 1.6.5) software for a group of aligned RNA sequences with 2981-residue running on a Personal Computer (PC) platform with Pentium 4 2.6 GHz CPU. PMID:19208138

Design and implementation of a programming circuit in radiation-hardened FPGA

NASA Astrophysics Data System (ADS)

Lihua, Wu; Xiaowei, Han; Yan, Zhao; Zhongli, Liu; Fang, Yu; Chen, Stanley L.

2011-08-01

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

A simple laser locking system based on a field-programmable gate array.

PubMed

Jørgensen, N B; Birkmose, D; Trelborg, K; Wacker, L; Winter, N; Hilliard, A J; Bason, M G; Arlt, J J

2016-07-01

Frequency stabilization of laser light is crucial in both scientific and industrial applications. Technological developments now allow analog laser stabilization systems to be replaced with digital electronics such as field-programmable gate arrays, which have recently been utilized to develop such locking systems. We have developed a frequency stabilization system based on a field-programmable gate array, with emphasis on hardware simplicity, which offers a user-friendly alternative to commercial and previous home-built solutions. Frequency modulation, lock-in detection, and a proportional-integral-derivative controller are programmed on the field-programmable gate array and only minimal additional components are required to frequency stabilize a laser. The locking system is administered from a host-computer which provides comprehensive, long-distance control through a versatile interface. Various measurements were performed to characterize the system. The linewidth of the locked laser was measured to be 0.7 ± 0.1 MHz with a settling time of 10 ms. The system can thus fully match laser systems currently in use for atom trapping and cooling applications.

A simple laser locking system based on a field-programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jørgensen, N. B.; Birkmose, D.; Trelborg, K.

Frequency stabilization of laser light is crucial in both scientific and industrial applications. Technological developments now allow analog laser stabilization systems to be replaced with digital electronics such as field-programmable gate arrays, which have recently been utilized to develop such locking systems. We have developed a frequency stabilization system based on a field-programmable gate array, with emphasis on hardware simplicity, which offers a user-friendly alternative to commercial and previous home-built solutions. Frequency modulation, lock-in detection, and a proportional-integral-derivative controller are programmed on the field-programmable gate array and only minimal additional components are required to frequency stabilize a laser. The lockingmore » system is administered from a host-computer which provides comprehensive, long-distance control through a versatile interface. Various measurements were performed to characterize the system. The linewidth of the locked laser was measured to be 0.7 ± 0.1 MHz with a settling time of 10 ms. The system can thus fully match laser systems currently in use for atom trapping and cooling applications.« less

Configurable hardware integrate and fire neurons for sparse approximation.

PubMed

Shapero, Samuel; Rozell, Christopher; Hasler, Paul

2013-09-01

Sparse approximation is an important optimization problem in signal and image processing applications. A Hopfield-Network-like system of integrate and fire (IF) neurons is proposed as a solution, using the Locally Competitive Algorithm (LCA) to solve an overcomplete L1 sparse approximation problem. A scalable system architecture is described, including IF neurons with a nonlinear firing function, and current-based synapses to provide linear computation. A network of 18 neurons with 12 inputs is implemented on the RASP 2.9v chip, a Field Programmable Analog Array (FPAA) with directly programmable floating gate elements. Said system uses over 1400 floating gates, the largest system programmed on a FPAA to date. The circuit successfully reproduced the outputs of a digital optimization program, converging to within 4.8% RMS, and an objective cost only 1.7% higher on average. The active circuit consumed 559 μA of current at 2.4 V and converges on solutions in 25 μs, with measurement of the converged spike rate taking an additional 1 ms. Extrapolating the scaling trends to a N=1000 node system, the spiking LCA compares favorably with state-of-the-art digital solutions, and analog solutions using a non-spiking approach. Copyright © 2013 Elsevier Ltd. All rights reserved.

Coverage and efficiency in current SNP chips

PubMed Central

Ha, Ngoc-Thuy; Freytag, Saskia; Bickeboeller, Heike

2014-01-01

To answer the question as to which commercial high-density SNP chip covers most of the human genome given a fixed budget, we compared the performance of 12 chips of different sizes released by Affymetrix and Illumina for the European, Asian, and African populations. These include Affymetrix' relatively new population-optimized arrays, whose SNP sets are each tailored toward a specific ethnicity. Our evaluation of the chips included the use of two measures, efficiency and cost–benefit ratio, which we developed as supplements to genetic coverage. Unlike coverage, these measures factor in the price of a chip or its substitute size (number of SNPs on chip), allowing comparisons to be drawn between differently priced chips. In this fashion, we identified the Affymetrix population-optimized arrays as offering the most cost-effective coverage for the Asian and African population. For the European population, we established the Illumina Human Omni 2.5-8 as the preferred choice. Interestingly, the Affymetrix chip tailored toward an Eastern Asian subpopulation performed well for all three populations investigated. However, our coverage estimates calculated for all chips proved much lower than those advertised by the producers. All our analyses were based on the 1000 Genome Project as reference population. PMID:24448550

Spatial mapping and statistical reproducibility of an array of 256 one-dimensional quantum wires

NASA Astrophysics Data System (ADS)

Al-Taie, H.; Smith, L. W.; Lesage, A. A. J.; See, P.; Griffiths, J. P.; Beere, H. E.; Jones, G. A. C.; Ritchie, D. A.; Kelly, M. J.; Smith, C. G.

2015-08-01

We utilize a multiplexing architecture to measure the conductance properties of an array of 256 split gates. We investigate the reproducibility of the pinch off and one-dimensional definition voltage as a function of spatial location on two different cooldowns, and after illuminating the device. The reproducibility of both these properties on the two cooldowns is high, the result of the density of the two-dimensional electron gas returning to a similar state after thermal cycling. The spatial variation of the pinch-off voltage reduces after illumination; however, the variation of the one-dimensional definition voltage increases due to an anomalous feature in the center of the array. A technique which quantifies the homogeneity of split-gate properties across the array is developed which captures the experimentally observed trends. In addition, the one-dimensional definition voltage is used to probe the density of the wafer at each split gate in the array on a micron scale using a capacitive model.

Integrated-optics heralded controlled-NOT gate for polarization-encoded qubits

NASA Astrophysics Data System (ADS)

Zeuner, Jonas; Sharma, Aditya N.; Tillmann, Max; Heilmann, René; Gräfe, Markus; Moqanaki, Amir; Szameit, Alexander; Walther, Philip

2018-03-01

Recent progress in integrated-optics technology has made photonics a promising platform for quantum networks and quantum computation protocols. Integrated optical circuits are characterized by small device footprints and unrivalled intrinsic interferometric stability. Here, we take advantage of femtosecond-laser-written waveguides' ability to process polarization-encoded qubits and present an implementation of a heralded controlled-NOT gate on chip. We evaluate the gate performance in the computational basis and a superposition basis, showing that the gate can create polarization entanglement between two photons. Transmission through the integrated device is optimized using thermally expanded core fibers and adiabatically reduced mode-field diameters at the waveguide facets. This demonstration underlines the feasibility of integrated quantum gates for all-optical quantum networks and quantum repeaters.

A nanoporous alumina microelectrode array for functional cell-chip coupling.

PubMed

Wesche, Manuel; Hüske, Martin; Yakushenko, Alexey; Brüggemann, Dorothea; Mayer, Dirk; Offenhäusser, Andreas; Wolfrum, Bernhard

2012-12-14

The design of electrode interfaces has a strong impact on cell-based bioelectronic applications. We present a new type of microelectrode array chip featuring a nanoporous alumina interface. The chip is fabricated in a combination of top-down and bottom-up processes using state-of-the-art clean room technology and self-assembled generation of nanopores by aluminum anodization. The electrode characteristics are investigated in phosphate buffered saline as well as under cell culture conditions. We show that the modified microelectrodes exhibit decreased impedance compared to planar microelectrodes, which is caused by a nanostructuring effect of the underlying gold during anodization. The stability and biocompatibility of the device are demonstrated by measuring action potentials from cardiomyocyte-like cells growing on top of the chip. Cross sections of the cell-surface interface reveal that the cell membrane seals the nanoporous alumina layer without bending into the sub-50 nm apertures. The nanoporous microelectrode array device may be used as a platform for combining extracellular recording of cell activity with stimulating topographical cues.

Performance characteristics of a nanoscale double-gate reconfigurable array

NASA Astrophysics Data System (ADS)

Beckett, Paul

2008-12-01

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

Field-Programmable Gate Array-based fluxgate magnetometer with digital integration

NASA Astrophysics Data System (ADS)

Butta, Mattia; Janosek, Michal; Ripka, Pavel

2010-05-01

In this paper, a digital magnetometer based on printed circuit board fluxgate is presented. The fluxgate is pulse excited and the signal is extracted by gate integration. We investigate the possibility to perform integration on very narrow gates (typically 500 ns) by using digital techniques. The magnetometer is based on field-programmable gate array (FPGA) card: we will show all the advantages and disadvantages, given by digitalization of fluxgate output voltage by means of analog-to-digital converter on FPGA card, as well as digitalization performed by external digitizer. Due to very narrow gate, it is shown that a magnetometer entirely based on a FPGA card is preferable, because it avoids noise due to trigger instability. Both open loop and feedback operative mode are described and achieved results are presented.

Multichip imager with improved optical performance near the butt region

NASA Technical Reports Server (NTRS)

Kinnard, Kenneth P. (Inventor); Strong, Jr., Richard T. (Inventor); Goldfarb, Samuel (Inventor); Tower, John R. (Inventor)

1991-01-01

A compound imager consists of two or more individual chips, each with at least one line array of sensors thereupon. Each chip has a glass support plate attached to the side from which light reaches the line arrays. The chips are butted together end-to-end to make large line arrays of sensors. Because of imperfections in cutting, the butted surfaces define a gap. Light entering in the region of the gap is either lost or falls on an individual imager other than the one for which it is intended. This results in vignetting and/or crosstalk near the butted region. The gap is filled with an epoxy resin or other similar material which, when hardened, has an index of referaction near that of the glass support plate.

CMOS imager for pointing and tracking applications

NASA Technical Reports Server (NTRS)

Sun, Chao (Inventor); Pain, Bedabrata (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

2006-01-01

Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

RHrFPGA Radiation-Hardened Re-programmable Field-Programmable Gate Array

NASA Technical Reports Server (NTRS)

Sanders, A. B.; LaBel, K. A.; McCabe, J. F.; Gardner, G. A.; Lintz, J.; Ross, C.; Golke, K.; Burns, B.; Carts, M. A.; Kim, H. S.

2004-01-01

Viewgraphs on the development of the Radiation-Hardened Re-programmable Field-Programmable Gate Array (RHrFPGA) are presented. The topics include: 1) Radiation Test Suite; 2) Testing Interface; 3) Test Configuration; 4) Facilities; 5) Test Programs; 6) Test Procedure; and 7) Test Results. A summary of heavy ion and proton testing is also included.

An Undergraduate Course and Laboratory in Digital Signal Processing with Field Programmable Gate Arrays

ERIC Educational Resources Information Center

Meyer-Base, U.; Vera, A.; Meyer-Base, A.; Pattichis, M. S.; Perry, R. J.

2010-01-01

In this paper, an innovative educational approach to introducing undergraduates to both digital signal processing (DSP) and field programmable gate array (FPGA)-based design in a one-semester course and laboratory is described. While both DSP and FPGA-based courses are currently present in different curricula, this integrated approach reduces the…

Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit.

PubMed

Nakazato, Kazuo

2014-03-28

By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10 MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor.

High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip

PubMed Central

Issadore, David; Franke, Thomas; Brown, Keith A.; Hunt, Thomas P.; Westervelt, Robert M.

2010-01-01

A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm2 in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip’s surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications. PMID:20625468

Continuous adjustment of threshold voltage in carbon nanotube field-effect transistors through gate engineering

NASA Astrophysics Data System (ADS)

Zhong, Donglai; Zhao, Chenyi; Liu, Lijun; Zhang, Zhiyong; Peng, Lian-Mao

2018-04-01

In this letter, we report a gate engineering method to adjust threshold voltage of carbon nanotube (CNT) based field-effect transistors (FETs) continuously in a wide range, which makes the application of CNT FETs especially in digital integrated circuits (ICs) easier. Top-gated FETs are fabricated using solution-processed CNT network films with stacking Pd and Sc films as gate electrodes. By decreasing the thickness of the lower layer metal (Pd) from 20 nm to zero, the effective work function of the gate decreases, thus tuning the threshold voltage (Vt) of CNT FETs from -1.0 V to 0.2 V. The continuous adjustment of threshold voltage through gate engineering lays a solid foundation for multi-threshold technology in CNT based ICs, which then can simultaneously provide high performance and low power circuit modules on one chip.

Simultaneous electrical recording of cardiac electrophysiology and contraction on chip

DOE PAGES

Qian, Fang; Huang, Chao; Lin, Yi-Dong; ...

2017-04-18

Prevailing commercialized cardiac platforms for in vitro drug development utilize planar microelectrode arrays to map action potentials, or impedance sensing to record contraction in real time, but cannot record both functions on the same chip with high spatial resolution. We report a novel cardiac platform that can record cardiac tissue adhesion, electrophysiology, and contractility on the same chip. The platform integrates two independent yet interpenetrating sensor arrays: a microelectrode array for field potential readouts and an interdigitated electrode array for impedance readouts. Together, these arrays provide real-time, non-invasive data acquisition of both cardiac electrophysiology and contractility under physiological conditions andmore » under drug stimuli. Furthermore, we cultured human induced pluripotent stem cell-derived cardiomyocytes as a model system, and used to validate the platform with an excitation–contraction decoupling chemical. Preliminary data using the platform to investigate the effect of the drug norepinephrine are combined with computational efforts. Finally, this platform provides a quantitative and predictive assay system that can potentially be used for comprehensive assessment of cardiac toxicity earlier in the drug discovery process.« less

Simultaneous electrical recording of cardiac electrophysiology and contraction on chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Qian, Fang; Huang, Chao; Lin, Yi-Dong

Prevailing commercialized cardiac platforms for in vitro drug development utilize planar microelectrode arrays to map action potentials, or impedance sensing to record contraction in real time, but cannot record both functions on the same chip with high spatial resolution. We report a novel cardiac platform that can record cardiac tissue adhesion, electrophysiology, and contractility on the same chip. The platform integrates two independent yet interpenetrating sensor arrays: a microelectrode array for field potential readouts and an interdigitated electrode array for impedance readouts. Together, these arrays provide real-time, non-invasive data acquisition of both cardiac electrophysiology and contractility under physiological conditions andmore » under drug stimuli. Furthermore, we cultured human induced pluripotent stem cell-derived cardiomyocytes as a model system, and used to validate the platform with an excitation–contraction decoupling chemical. Preliminary data using the platform to investigate the effect of the drug norepinephrine are combined with computational efforts. Finally, this platform provides a quantitative and predictive assay system that can potentially be used for comprehensive assessment of cardiac toxicity earlier in the drug discovery process.« less

Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation

NASA Astrophysics Data System (ADS)

Koike, Hiroki; Ohsawa, Takashi; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2015-04-01

A spintronic-based power-gated micro-processing unit (MPU) is proposed. It includes a power control circuit activated by the newly supported power-off instruction for the deep-sleep mode. These means enable the power-off procedure for the MPU to be executed appropriately. A test chip was designed and fabricated using 90 nm CMOS and an additional 100 nm MTJ process; it was successfully operated. The guideline of the energy reduction effects for this MPU was presented, using the estimation based on the measurement results of the test chip. The result shows that a large operation energy reduction of 1/28 can be achieved when the operation duty is 10%, under the condition of a sufficient number of idle clock cycles.

Hybrid III/V silicon photonic source with integrated 1D free-space beam steering.

PubMed

Doylend, J K; Heck, M J R; Bovington, J T; Peters, J D; Davenport, M L; Coldren, L A; Bowers, J E

2012-10-15

A chip-scale optical source with integrated beam steering is demonstrated. The chip was fabricated using the hybrid silicon platform and incorporates an on-chip laser, waveguide splitter, amplifiers, phase modulators, and surface gratings to comprise an optical phased array with beam steering across a 12° field of view in one axis. Tuning of the phased array is used to achieve 1.8°(steered axis)×0.6°(nonsteered axis) beam width with 7 dB background suppression for arbitrary beam direction within the field of view.

Evaluation of Bovine High-Density SNP Genotyping Array in Indigenous Dairy Cattle Breeds.

PubMed

Dash, S; Singh, A; Bhatia, A K; Jayakumar, S; Sharma, A; Singh, S; Ganguly, I; Dixit, S P

2018-04-03

In total 52 samples of Sahiwal ( 19 ), Tharparkar ( 17 ), and Gir ( 16 ) were genotyped by using BovineHD SNP chip to analyze minor allele frequency (MAF), genetic diversity, and linkage disequilibrium among these cattle. The common SNPs of BovineHD and 54K SNP Chips were also extracted and evaluated for their performance. Only 40%-50% SNPs of these arrays was found informative for genetic analysis in these cattle breeds. The overall mean of MAF for SNPs of BovineHD SNPChip was 0.248 ± 0.006, 0.241 ± 0.007, and 0.242 ± 0.009 in Sahiwal, Tharparkar and Gir, respectively, while that for 54K SNPs was on lower side. The average Reynold's genetic distance between breeds ranged from 0.042 to 0.055 based on BovineHD Beadchip, and from 0.052 to 0.084 based on 54K SNP Chip. The estimates of genetic diversity based on HD and 54K chips were almost same and, hence, low density chip seems to be good enough to decipher genetic diversity of these cattle breeds. The linkage disequilibrium started decaying (r 2  < 0.2) at 140 kb inter-marker distance and, hence, a 20K low density customized SNP array from HD chip could be designed for genomic selection in these cattle else the 54K Bead Chip as such will be useful.

The 30-GHz monolithic receive module

NASA Technical Reports Server (NTRS)

Bauhahn, P.; Geddes, J.; Sokolov, V.; Contolatis, T.

1988-01-01

The fourth year progress is described on a program to develop a 27.5 to 30 GHz GaAs monolithic receive module for spaceborne-communication antenna feed array applications, and to deliver submodules for experimental evaluation. Program goals include an overall receive module noise figure of 5 dB, a 30 dB RF to IF gain with six levels of intermediate gain control, a five bit phase shifter, and a maximum power consumption of 250 mW. Submicron gate length single and dual gate FETs are described and applied in the development of monolithic gain control amplifiers and low noise amplifiers. A two-stage monolithic gain control amplifier based on ion implanted dual gate MESFETs was designed and fabricated. The gain control amplifier has a gain of 12 dB at 29 GHz with a gain control range of over 13 dB. A two-stage monolithic low noise amplifier based on ion implanted MESFETs which provides 7 dB gain with 6.2 dB noise figure at 29 GHz was also developed. An interconnected receive module containing LNA, gain control, and phase shifter submodules was built using the LNA and gain control ICs as well as a monolithic phase shifter developed previously under this program. The design, fabrication, and evaluation of this interconnected receiver is presented. Progress in the development of an RF/IF submodule containing a unique ion implanted diode mixer diode and a broadband balanced mixer monolithic IC with on-chip IF amplifier and the initial design of circuits for the RF portion of a two submodule receiver are also discussed.

PbS-PbSe IR detector arrays

NASA Technical Reports Server (NTRS)

Barrett, John R. (Inventor)

1986-01-01

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chipping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

Microfluidic LC Device with Orthogonal Sample Extraction for On-Chip MALDI-MS Detection

PubMed Central

Lazar, Iulia M.; Kabulski, Jarod L.

2013-01-01

A microfluidic device that enables on-chip matrix assisted laser desorption ionization-mass spectrometry (MALDI-MS) detection for liquid chromatography (LC) separations is described. The device comprises an array of functional elements to carry out LC separations, integrates a novel microchip-MS interface to facilitate the orthogonal transposition of the microfluidic LC channel into an array of reservoirs, and enables sensitive MALDI-MS detection directly from the chip. Essentially, the device provides a snapshot MALDI-MS map of the content of the separation channel present on the chip. The detection of proteins with biomarker potential from MCF10A breast epithelial cell extracts, and detection limits in the low fmol range, are demonstrated. In addition, the design of the novel LC-MALDI-MS chip entices the promotion of a new concept for performing sample separations within the limited time-frame that accompanies the dead-volume of a separation channel. PMID:23592150

Multipass comminution process to produce precision wood particles of uniform size and shape with disrupted grain structure from wood chips

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dooley, James H; Lanning, David N

A process of comminution of wood chips (C) having a grain direction to produce a mixture of wood particles (P), wherein the wood chips are characterized by an average length dimension (L.sub.C) as measured substantially parallel to the grain, an average width dimension (W.sub.C) as measured normal to L.sub.C and aligned cross grain, and an average height dimension (H.sub.C) as measured normal to W.sub.C and L.sub.C, and wherein the comminution process comprises the step of feeding the wood chips in a direction of travel substantially randomly to the grain direction one or more times through a counter rotating pair ofmore » intermeshing arrays of cutting discs (D) arrayed axially perpendicular to the direction of wood chip travel.« less

CMOS-array design-automation techniques

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardt, T.

1979-01-01

Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

European Seminar on Neural Computing

DTIC Science & Technology

1988-08-31

elements can be fabricated on a single chip . Two specific oriented language (for example, SMALLTALK or cellular arrays, namely, the programmable systolic... chip POOL) the basic concepts are: objects are viewed as (Fisher, 1983) and the connection machine (Treleaven, active, they may contain state, and...flow computer the availability of 1. Programmable Systolic Chip . Programmable Sys- input operands triggers the execution of the instruction tolic Chips

Miniaturized high throughput detection system for capillary array electrophoresis on chip with integrated light emitting diode array as addressed ring-shaped light source.

PubMed

Ren, Kangning; Liang, Qionglin; Mu, Xuan; Luo, Guoan; Wang, Yiming

2009-03-07

A novel miniaturized, portable fluorescence detection system for capillary array electrophoresis (CAE) on a microfluidic chip was developed, consisting of a scanning light-emitting diode (LED) light source and a single point photoelectric sensor. Without charge coupled detector (CCD), lens, fibers and moving parts, the system was extremely simplified. Pulsed driving of the LED significantly increased the sensitivity, and greatly reduced the power consumption and photobleaching effect. The highly integrated system was robust and easy to use. All the advantages realized the concept of a portable micro-total analysis system (micro-TAS), which could work on a single universal serial bus (USB) port. Compared with traditional CAE detecting systems, the current system could scan the radial capillary array with high scanning rate. An 8-channel CAE of fluorescein isothiocyanate (FITC) labeled arginine (Arg) on chip was demonstrated with this system, resulting in a limit of detection (LOD) of 640 amol.

Packaging and testing of multi-wavelength DFB laser array using REC technology

NASA Astrophysics Data System (ADS)

Ni, Yi; Kong, Xuan; Gu, Xiaofeng; Chen, Xiangfei; Zheng, Guanghui; Luan, Jia

2014-02-01

Packaging of distributed feedback (DFB) laser array based on reconstruction-equivalent-chirp (REC) technology is a bridge from chip to system, and influences the practical process of REC chip. In this paper, DFB laser arrays of 4-channel @1310 nm and 8-channel @1550 nm are packaged. Our experimental results show that both these laser arrays have uniform wavelength spacing and larger than 35 dB average Side Mode Suppression Ratio (SMSR). When I=35 mA, we obtain the total output power of 1 mW for 4-channel @1310 nm, and 227 μw for 8-channel @1550 nm respectively. The high frequency characteristics of the packaged chips are also obtained, and the requirements for 4×10 G or even 8×10 G systems can be reached. Our results demonstrate the practical and low cost performance of REC technology and indicate its potential in the future fiber-to-the-home (FTTH) application.

Systems and methods for detecting a failure event in a field programmable gate array

NASA Technical Reports Server (NTRS)

Ng, Tak-Kwong (Inventor); Herath, Jeffrey A. (Inventor)

2009-01-01

An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.

Push-broom imaging spectrometer based on planar lightwave circuit MZI array

NASA Astrophysics Data System (ADS)

Yang, Minyue; Li, Mingyu; He, Jian-Jun

2017-05-01

We propose a large aperture static imaging spectrometer (LASIS) based on planar lightwave circuit (PLC) MZI array. The imaging spectrometer works in the push-broom mode with the spectrum performed by interferometry. While the satellite/aircraft is orbiting, the same source, seen from the satellite/aircraft, moves across the aperture and enters different MZIs, while adjacent sources enter adjacent MZIs at the same time. The on-chip spectrometer consists of 256 input mode converters, followed by 256 MZIs with linearly increasing optical path delays and a detector array. Multiple chips are stick together to form the 2D image surface and receive light from the imaging lens. Two MZI arrays are proposed, one works in wavelength ranging from 500nm to 900nm with SiON(refractive index 1.6) waveguides and another ranging from 1100nm to 1700nm with SOI platform. To meet the requirements of imaging spectrometer applications, we choose large cross-section ridge waveguide to achieve polarization insensitive, maintain single mode propagation in broad spectrum and increase production tolerance. The SiON on-chip spectrometer has a spectral resolution of 80cm-1 with a footprint of 17×15mm2 and the SOI based on-chip spectrometer has a resolution of 38cm-1 with a size of 22×19mm2. The spectral and space resolution of the imaging spectrometer can be further improved by simply adding more MZIs. The on-chip waveguide MZI array based Fourier transform imaging spectrometer can provide a highly compact solution for remote sensing on unmanned aerial vehicles or satellites with advantages of small size, light weight, no moving parts and large input aperture.

[Theoretical foundations of protein chips and their possible use in medical research and diagnostics].

PubMed

Spisák, Sándor; Molnár, Béla; Galamb, Orsolya; Sipos, Ferenc; Tulassay, Zsolt

2007-08-12

The confirmation of mRNA expression studies by protein chips is of high recent interest due to the widespread application of expression arrays. In this review the advantages, technical limitations, application fields and the first results of the protein arrays is described. The bottlenecks of the increasing protein array applications are the fast decomposition of proteins, the problem with aspecific binding and the lack of amplification techniques. Today glass slide based printed, SELDI (MS) based, electrophoresis based and tissue microarray based technologies are available. The advantage of the glass slide based chips are the simplicity of their application, and relatively low cost. The SELDI based protein chip technique is applicable to minute amounts of starting material (<1 microg) but it is the most expensive one. The electrophoresis based techniques are still under intensive development. The tissue microarrays can be used for the parallel testing of the sensitivity and specificity of single antibodies on a broad range of histological specimens on a single slide. Protein chips were successfully used for serum tumor marker detection, cancer research, cell physiology studies and for the verification of mRNA expression studies. Protein chips are envisioned to be available for routine diagnostic applications if the ongoing technology development will be successful in increase in sensitivity, specificity, costs reduction and for the reduction of the necessary sample volume.

N-Channel field-effect transistors with floating gates for extracellular recordings.

PubMed

Meyburg, Sven; Goryll, Michael; Moers, Jürgen; Ingebrandt, Sven; Böcker-Meffert, Simone; Lüth, Hans; Offenhäusser, Andreas

2006-01-15

A field-effect transistor (FET) for recording extracellular signals from electrogenic cells is presented. The so-called floating gate architecture combines a complementary metal oxide semiconductor (CMOS)-type n-channel transistor with an independent sensing area. This concept allows the transistor and sensing area to be optimised separately. The devices are robust and can be reused several times. The noise level of the devices was smaller than of comparable non-metallised gate FETs. In addition to the usual drift of FET devices, we observed a long-term drift that has to be controlled for future long-term measurements. The device performance for extracellular signal recording was tested using embryonic rat cardiac myocytes cultured on fibronectin-coated chips. The extracellular cell signals were recorded before and after the addition of the cardioactive isoproterenol. The signal shapes of the measured action potentials were comparable to the non-metallised gate FETs previously used in similar experiments. The fabrication of the devices involved the process steps of standard CMOS that were necessary to create n-channel transistors. The implementation of a complete CMOS process would facilitate the integration of the logical circuits necessary for signal pre-processing on a chip, which is a prerequisite for a greater number of sensor spots in future layouts.

Two-Dimensional Planar Lightwave Circuit Integrated Spatial Filter Array and Method of Use Thereof

NASA Technical Reports Server (NTRS)

Dimov, Fedor (Inventor); Ai, Jun (Inventor)

2015-01-01

A large coherent two-dimensional (2D) spatial filter array (SFA), 30 by 30 or larger, is produced by coupling a 2D planar lightwave circuit (PLC) array with a pair of lenslet arrays at the input and output side. The 2D PLC array is produced by stacking a plurality of chips, each chip with a plural number of straight PLC waveguides. A pupil array is coated onto the focal plane of the lenslet array. The PLC waveguides are produced by deposition of a plural number of silica layers on the silicon wafer, followed by photolithography and reactive ion etching (RIE) processes. A plural number of mode filters are included in the silica-on-silicon waveguide such that the PLC waveguide is transparent to the fundamental mode but higher order modes are attenuated by 40 dB or more.

Electroosmotic flow in microchannels with nanostructures.

PubMed

Yasui, Takao; Kaji, Noritada; Mohamadi, Mohamad Reza; Okamoto, Yukihiro; Tokeshi, Manabu; Horiike, Yasuhiro; Baba, Yoshinobu

2011-10-25

Here we report that nanopillar array structures have an intrinsic ability to suppress electroosmotic flow (EOF). Currently using glass chips for electrophoresis requires laborious surface coating to control EOF, which works as a counterflow to the electrophoresis mobility of negatively charged samples such as DNA and sodium dodecyl sulfate (SDS) denatured proteins. Due to the intrinsic ability of the nanopillar array to suppress the EOF, we carried out electrophoresis of SDS-protein complexes in nanopillar chips without adding any reagent to suppress protein adsorption and the EOF. We also show that the EOF profile inside a nanopillar region was deformed to an inverse parabolic flow. We used a combination of EOF measurements and fluorescence observations to compare EOF in microchannel, nanochannel, and nanopillar array chips. Our results of EOF measurements in micro- and nanochannel chips were in complete agreement with the conventional equation of the EOF mobility (μ(EOF-channel) = αC(i)(-0.5), where C(i) is the bulk concentration of the i-ions and α differs in micro- and nanochannels), whereas EOF in the nanopillar chips did not follow this equation. Therefore we developed a new modified form of the conventional EOF equation, μ(EOF-nanopillar) ≈ β[C(i) - (C(i)(2)/N(i))], where N(i) is the number of sites available to i-ions and β differs for each nanopillar chip because of different spacings or patterns, etc. The modified equation of the EOF mobility that we proposed here was in good agreement with our experimental results. In this equation, we showed that the charge density of the nanopillar region, that is, the total number of nanopillars inside the microchannel, affected the suppression of EOF, and the arrangement of nanopillars into a tilted or square array had no effect on it.

A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System.

PubMed

Current, K W; Yuk, K; McConaghy, C; Gascoyne, P R C; Schwartz, J A; Vykoukal, J V; Andrews, C

2007-06-01

A high-voltage (HV) integrated circuit has been demonstrated to transport fluidic droplet samples on programmable paths across the array of driving electrodes on its hydrophobically coated surface. This exciter chip is the engine for dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip systems, creating field excitations that inject and move fluidic droplets onto and about the manipulation surface. The architecture of this chip is expandable to arrays of N X N identical HV electrode driver circuits and electrodes. The exciter chip is programmable in several senses. The routes of multiple droplets may be set arbitrarily within the bounds of the electrode array. The electrode excitation waveform voltage amplitude, phase, and frequency may be adjusted based on the system configuration and the signal required to manipulate a particular fluid droplet composition. The voltage amplitude of the electrode excitation waveform can be set from the minimum logic level up to the maximum limit of the breakdown voltage of the fabrication technology. The frequency of the electrode excitation waveform can also be set independently of its voltage, up to a maximum depending upon the type of droplets that must be driven. The exciter chip can be coated and its oxide surface used as the droplet manipulation surface or it can be used with a top-mounted, enclosed fluidic chamber consisting of a variety of materials. The HV capability of the exciter chip allows the generated DEP forces to penetrate into the enclosed chamber region and an adjustable voltage amplitude can accommodate a variety of chamber floor thicknesses. This demonstration exciter chip has a 32 x 32 array of nominally 100 V electrode drivers that are individually programmable at each time point in the procedure to either of two phases: 0deg and 180deg with respect to the reference clock. For this demonstration chip, while operating the electrodes with a 100-V peak-to-peak periodic waveform, the maximum HV electrode waveform frequency is about 200 Hz; and standard 5-V CMOS logic data communication rate is variable up to 250 kHz. This HV demonstration chip is fabricated in a 130-V 1.0-mum SOI CMOS fabrication technology, dissipates a maximum of 1.87 W, and is about 10.4 mm x 8.2 mm.

Planar waveguide integrated spatial filter array

NASA Astrophysics Data System (ADS)

Ai, Jun; Dimov, Fedor; Lyon, Richard; Rakuljic, Neven; Griffo, Chris; Xia, Xiaowei; Arik, Engin

2013-09-01

An innovative integrated spatial filter array (iSFA) was developed for the nulling interferometer for the detection of earth-like planets and life beyond our solar system. The coherent iSFA comprised a 2D planar lightwave circuit (PLC) array coupled with a pair of 2D lenslet arrays in a hexagonal grid to achieve the optimum fill factor and throughput. The silica-on-silicon waveguide mode field diameter and numerical aperture (NA) were designed to match with the Airy disc and NA of the microlens for optimum coupling. The lenslet array was coated with a chromium pinhole array at the focal plane to pass the single-mode waveguide but attenuate the higher modes. We assembled a 32 by 30 array by stacking 32 chips that were produced by photolithography from a 6-in. silicon wafer. Each chip has 30 planar waveguides. The PLC array is inherently polarization-maintaining (PM) and requires much less alignment in contrast to a fiber array, where each PM fiber must be placed individually and oriented correctly. The PLC array offers better scalability than the fiber bundle array for large arrays of over 1,000 waveguides.

Monolithic acoustic graphene transistors based on lithium niobate thin film

NASA Astrophysics Data System (ADS)

Liang, J.; Liu, B.-H.; Zhang, H.-X.; Zhang, H.; Zhang, M.-L.; Zhang, D.-H.; Pang, W.

2018-05-01

This paper introduces an on-chip acoustic graphene transistor based on lithium niobate thin film. The graphene transistor is embedded in a microelectromechanical systems (MEMS) acoustic wave device, and surface acoustic waves generated by the resonator induce a macroscopic current in the graphene due to the acousto-electric (AE) effect. The acoustic resonator and the graphene share the lithium niobate film, and a gate voltage is applied through the back side of the silicon substrate. The AE current induced by the Rayleigh and Sezawa modes was investigated, and the transistor outputs a larger current in the Rayleigh mode because of a larger coupling to velocity ratio. The output current increases linearly with the input radiofrequency power and can be effectively modulated by the gate voltage. The acoustic graphene transistor realized a five-fold enhancement in the output current at an optimum gate voltage, outperforming its counterpart with a DC input. The acoustic graphene transistor demonstrates a paradigm for more-than-Moore technology. By combining the benefits of MEMS and graphene circuits, it opens an avenue for various system-on-chip applications.

Carbon Nanotube Self-Gating Diode and Application in Integrated Circuits.

PubMed

Si, Jia; Liu, Lijun; Wang, Fanglin; Zhang, Zhiyong; Peng, Lian-Mao

2016-07-26

A nano self-gating diode (SGD) based on nanoscale semiconducting material is proposed, simulated, and realized on semiconducting carbon nanotubes (CNTs) through a doping-free fabrication process. The relationships between the performance and material/structural parameters of the SGD are explored through numerical simulation and verified by experiment results. Based on these results, performance optimization strategy is outlined, and high performance CNT SGDs are fabricated and demonstrated to surpass other published CNT diodes. In particular the CNT SGD exhibits high rectifier factor of up to 1.4 × 10(6) while retains large on-state current. Benefiting from high yield and stability, CNT SGDs are used for constructing logic and analog integrated circuits. Two kinds of basic digital gates (AND and OR) have been realized on chip through using CNT SGDs and on-chip Ti wire resistances, and a full wave rectifier circuit has been demonstrated through using two CNT SGDs. Although demonstrated here using CNT SGDs, this device structure may in principle be implemented using other semiconducting nanomaterials, to provide ideas and building blocks for electronic applications based on nanoscale materials.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1980-01-01

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Multienzyme-nanoparticles amplification for sensitive virus genotyping in microfluidic microbeads array using Au nanoparticle probes and quantum dots as labels.

PubMed

Zhang, He; Liu, Lian; Li, Cheuk-Wing; Fu, Huayang; Chen, Yao; Yang, Mengsu

2011-11-15

A novel microfluidic device with microbeads array was developed and sensitive genotyping of human papillomavirus was demonstrated using a multiple-enzyme labeled oligonucleotide-Au nanoparticle bioconjugate as the detection tool. This method utilizes microbeads as sensing platform that was functionalized with the capture probes and modified electron rich proteins, and uses the horseradish peroxidase (HRP)-functionalized gold nanoparticles as label with a secondary DNA probe. The functionalized microbeads were independently introduced into the arrayed chambers using the loading chip slab. A single channel was used to generate weir structures to confine the microbeads and make the beads array accessible by microfluidics. Through "sandwich" hybridization, the enzyme-functionalized Au nanoparticles labels were brought close to the surface of microbeads. The oxidation of biotin-tyramine by hydrogen peroxide resulted in the deposition of multiple biotin moieties onto the surface of beads. This deposition is markedly increased in the presence of immobilized electron rich proteins. Streptavidin-labeled quantum dots were then allowed to bind to the deposited biotin moieties and displayed the signal. Enhanced detection sensitivity was achieved where the large surface area of Au nanoparticle carriers increased the amount HRP bound per sandwiched hybridization. The on-chip genotyping method could discriminate as low as 1fmol/L (10zmol/chip, SNR>3) synthesized HPV oligonucleotides DNA. The chip-based signal enhancement of the amplified assay resulted in 1000 times higher sensitivity than that of off-chip test. In addition, this on-chip format could discriminate and genotype 10copies/μL HPV genomic DNA using the PCR products. These results demonstrated that this on-chip approach can achieve highly sensitive detection and genotyping of target DNA and can be further developed for detection of disease-related biomolecules at the lowest level at their earliest incidence. Copyright © 2011 Elsevier B.V. All rights reserved.

Solid state lighting component

DOEpatents

Yuan, Thomas; Keller, Bernd; Ibbetson, James; Tarsa, Eric; Negley, Gerald

2010-10-26

An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in a series circuit. A lens is included over the LED chips. Other embodiments can comprise thermal spreading structures included integral to the submount and arranged to dissipate heat from the LED chips.

Solid state lighting component

DOEpatents

Yuan, Thomas; Keller, Bernd; Ibbetson, James; Tarsa, Eric; Negley, Gerald

2015-07-07

An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in a series circuit. A lens is included over the LED chips. Other embodiments can comprise thermal spreading structures included integral to the submount and arranged to dissipate heat from the LED chips.

Solid state lighting component

DOEpatents

Keller, Bernd; Ibbetson, James; Tarsa, Eric; Negley, Gerald; Yuan, Thomas

2012-07-10

An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in a series circuit. A lens is included over the LED chips. Other embodiments can comprise thermal spreading structures included integral to the submount and arranged to dissipate heat from the LED chips.

Active C4 Electrodes for Local Field Potential Recording Applications

PubMed Central

Wang, Lu; Freedman, David; Sahin, Mesut; Ünlü, M. Selim; Knepper, Ronald

2016-01-01

Extracellular neural recording, with multi-electrode arrays (MEAs), is a powerful method used to study neural function at the network level. However, in a high density array, it can be costly and time consuming to integrate the active circuit with the expensive electrodes. In this paper, we present a 4 mm × 4 mm neural recording integrated circuit (IC) chip, utilizing IBM C4 bumps as recording electrodes, which enable a seamless active chip and electrode integration. The IC chip was designed and fabricated in a 0.13 μm BiCMOS process for both in vitro and in vivo applications. It has an input-referred noise of 4.6 μVrms for the bandwidth of 10 Hz to 10 kHz and a power dissipation of 11.25 mW at 2.5 V, or 43.9 μW per input channel. This prototype is scalable for implementing larger number and higher density electrode arrays. To validate the functionality of the chip, electrical testing results and acute in vivo recordings from a rat barrel cortex are presented. PMID:26861324

VLSI design of an RSA encryption/decryption chip using systolic array based architecture

NASA Astrophysics Data System (ADS)

Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

2016-09-01

This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations

NASA Astrophysics Data System (ADS)

Li, Xiaoyun; Chen, Houpeng; Li, Xi; Wang, Qian; Fan, Xi; Hu, Jiajun; Lei, Yu; Zhang, Qi; Tian, Zhen; Song, Zhitang

2016-10-01

The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.

Single Event Analysis and Fault Injection Techniques Targeting Complex Designs Implemented in Xilinx-Virtex Family Field Programmable Gate Array (FPGA) Devices

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; LaBel, Kenneth; Kim, Hak

2014-01-01

An informative session regarding SRAM FPGA basics. Presenting a framework for fault injection techniques applied to Xilinx Field Programmable Gate Arrays (FPGAs). Introduce an overlooked time component that illustrates fault injection is impractical for most real designs as a stand-alone characterization tool. Demonstrate procedures that benefit from fault injection error analysis.

Systolic array IC for genetic computation

NASA Technical Reports Server (NTRS)

Anderson, D.

1991-01-01

Measuring similarities between large sequences of genetic information is a formidable task requiring enormous amounts of computer time. Geneticists claim that nearly two months of CRAY-2 time are required to run a single comparison of the known database against the new bases that will be found this year, and more than a CRAY-2 year for next year's genetic discoveries, and so on. The DNA IC, designed at HP-ICBD in cooperation with the California Institute of Technology and the Jet Propulsion Laboratory, is being implemented in order to move the task of genetic comparison onto workstations and personal computers, while vastly improving performance. The chip is a systolic (pumped) array comprised of 16 processors, control logic, and global RAM, totaling 400,000 FETS. At 12 MHz, each chip performs 2.7 billion 16 bit operations per second. Using 35 of these chips in series on one PC board (performing nearly 100 billion operations per second), a sequence of 560 bases can be compared against the eventual total genome of 3 billion bases, in minutes--on a personal computer. While the designed purpose of the DNA chip is for genetic research, other disciplines requiring similarity measurements between strings of 7 bit encoded data could make use of this chip as well. Cryptography and speech recognition are two examples. A mix of full custom design and standard cells, in CMOS34, were used to achieve these goals. Innovative test methods were developed to enhance controllability and observability in the array. This paper describes these techniques as well as the chip's functionality. This chip was designed in the 1989-90 timeframe.

Insertion of GaAs MMICs into EW systems

NASA Astrophysics Data System (ADS)

Schineller, E. R.; Pospishil, A.; Grzyb, J.

1989-09-01

Development activities on a microwave/mm-wave monolithic IC (MIMIC) program are described, as well as the methodology for inserting these GaAs IC chips into several EW systems. The generic EW chip set developed on the MIMIC program consists of 23 broadband chip types, including amplifiers, oscillators, mixers, switches, variable attenuators, power dividers, and power combiners. These chips are being designed for fabrication using the multifunction self-aligned gate process. The benefits from GaAs IC insertion are quantified by a comparison of hardware units fabricated with existing MIC and digital ECL technology and the same units manufactured with monolithic technology. It is found that major improvements in cost, reliability, size, weight, and performance can be realized. Examples illustrating the methodology for technology insertion are presented.

Scaling Trapped Ion Quantum Computers Using Fast Gates and Microtraps

NASA Astrophysics Data System (ADS)

Ratcliffe, Alexander K.; Taylor, Richard L.; Hope, Joseph J.; Carvalho, André R. R.

2018-06-01

Most attempts to produce a scalable quantum information processing platform based on ion traps have focused on the shuttling of ions in segmented traps. We show that an architecture based on an array of microtraps with fast gates will outperform architectures based on ion shuttling. This system requires higher power lasers but does not require the manipulation of potentials or shuttling of ions. This improves optical access, reduces the complexity of the trap, and reduces the number of conductive surfaces close to the ions. The use of fast gates also removes limitations on the gate time. Error rates of 10-5 are shown to be possible with 250 mW laser power and a trap separation of 100 μ m . The performance of the gates is shown to be robust to the limitations in the laser repetition rate and the presence of many ions in the trap array.

Time delay and integration array (TDI) using charge transfer device technology. Phase 2, volume 1: Technical

NASA Technical Reports Server (NTRS)

1977-01-01

The 20x9 TDI array was developed to meet the LANDSAT Thematic Mapper Requirements. This array is based upon a self-aligned, transparent gate, buried channel process. The process features: (1) buried channel, four phase, overlapping gate CCD's for high transfer efficiency without fat zero; (2) self-aligned transistors to minimize clock feedthrough and parasitic capacitance; and (3) transparent tin oxide electrode for high quantum efficiency with front surface irradiation. The requirements placed on the array and the performance achieved are summarized. This data is the result of flat field measurements only, no imaging or dynamic target measurements were made during this program. Measurements were performed with two different test stands. The bench test equipment fabricated for this program operated at the 8 micro sec line time and employed simple sampling of the gated MOSFET output video signal. The second stand employed Correlated Doubled Sampling (CDS) and operated at 79.2 micro sec line time.

Field ionization characteristics of an ion source array for neutron generators

NASA Astrophysics Data System (ADS)

Bargsten Johnson, B.; Schwoebel, P. R.; Resnick, P. J.; Holland, C. E.; Hertz, K. L.; Chichester, D. L.

2013-11-01

A new deuterium ion source is being developed to improve the performance of existing compact neutron generators. The ion source is a microfabricated array of metal tips with an integrated gate (i.e., grid) and produces deuterium ions by field ionizing (or field desorbing) a supply of deuterium gas. Deuterium field ion currents from arrays at source temperatures of 77 K and 293 K are studied. Ion currents from single etched-wire tips operating under the same conditions are used to help understand array results. I-F characteristics of the arrays were found to follow trends similar to those of the better understood single etched-wire tip results; however, the fields achieved by the arrays are limited by electrical breakdown of the structure. Neutron production by field ionization at 293 K was demonstrated for the first time from microfabricated array structures with integrated gates.

A Conductometric Indium Oxide Semiconducting Nanoparticle Enzymatic Biosensor Array

PubMed Central

Lee, Dongjin; Ondrake, Janet; Cui, Tianhong

2011-01-01

We report a conductometric nanoparticle biosensor array to address the significant variation of electrical property in nanomaterial biosensors due to the random network nature of nanoparticle thin-film. Indium oxide and silica nanoparticles (SNP) are assembled selectively on the multi-site channel area of the resistors using layer-by-layer self-assembly. To demonstrate enzymatic biosensing capability, glucose oxidase is immobilized on the SNP layer for glucose detection. The packaged sensor chip onto a ceramic pin grid array is tested using syringe pump driven feed and multi-channel I–V measurement system. It is successfully demonstrated that glucose is detected in many different sensing sites within a chip, leading to concentration dependent currents. The sensitivity has been found to be dependent on the channel length of the resistor, 4–12 nA/mM for channel lengths of 5–20 μm, while the apparent Michaelis-Menten constant is 20 mM. By using sensor array, analytical data could be obtained with a single step of sample solution feeding. This work sheds light on the applicability of the developed nanoparticle microsensor array to multi-analyte sensors, novel bioassay platforms, and sensing components in a lab-on-a-chip. PMID:22163696

Monolithic optical phased-array transceiver in a standard SOI CMOS process.

PubMed

Abediasl, Hooman; Hashemi, Hossein

2015-03-09

Monolithic microwave phased arrays are turning mainstream in automotive radars and high-speed wireless communications fulfilling Gordon Moores 1965 prophecy to this effect. Optical phased arrays enable imaging, lidar, display, sensing, and holography. Advancements in fabrication technology has led to monolithic nanophotonic phased arrays, albeit without independent phase and amplitude control ability, integration with electronic circuitry, or including receive and transmit functions. We report the first monolithic optical phased array transceiver with independent control of amplitude and phase for each element using electronic circuitry that is tightly integrated with the nanophotonic components on one substrate using a commercial foundry CMOS SOI process. The 8 × 8 phased array chip includes thermo-optical tunable phase shifters and attenuators, nano-photonic antennas, and dedicated control electronics realized using CMOS transistors. The complex chip includes over 300 distinct optical components and over 74,000 distinct electrical components achieving the highest level of integration for any electronic-photonic system.

Integrated optical phased arrays for quasi-Bessel-beam generation.

PubMed

Notaros, Jelena; Poulton, Christopher V; Byrd, Matthew J; Raval, Manan; Watts, Michael R

2017-09-01

Integrated optical phased arrays for generating quasi-Bessel beams are proposed and experimentally demonstrated in a CMOS-compatible platform. Owing to their elongated central beams, Bessel beams have applications in a range of fields, including multiparticle trapping and laser lithography. In this Letter, continuous Bessel theory is manipulated to formulate the phase and amplitude conditions necessary for generating free-space-propagating Bessel-Gauss beams using on-chip optical phased arrays. Discussion of the effects of select phased array parameters on the generated beam's figures of merit is included. A one-dimensional splitter-tree-based phased array architecture is modified to enable arbitrary passive control of the array's element phase and amplitude distributions. This architecture is used to experimentally demonstrate on-chip quasi-Bessel-beam generation with a ∼14  mm Bessel length and ∼30  μm power full width at half maximum.

Characterization of electrokinetic gating valve in microfluidic channels.

PubMed

Zhang, Guiseng; Du, Wei; Liu, Bi-Feng; Hisamoto, Hideaki; Terabe, Shigeru

2007-02-12

Electrokinetic gating, functioning as a micro-valve, has been widely employed in microfluidic chips for sample injection and flow switch. Investigating its valving performance is fundamentally vital for microfluidics and microfluidics-based chemical analysis. In this paper, electrokinetic gating valve in microchannels was evaluated using optical imaging technique. Microflow profiles at channels junction were examined, revealing that molecular diffusion played a significant role in the valving disable; which could cause analyte leakage in sample injection. Due to diffusion, the analyte crossed the interface of the analyte flow and gating flow, and then formed a cometic tail-like diffusion area at channels junction. From theoretical calculation and some experimental evidences, the size of the area was related to the diffusion coefficient and the velocity of analytes. Additionally, molecular diffusion was also believed to be another reason of sampling bias in gated injection.

Source-drain burnout mechanism of GaAs power MESFETS: Three terminal effects

NASA Astrophysics Data System (ADS)

Takamiya, Saburo; Sonoda, Takuji; Yamanouchi, Masahide; Fujioka, Takashi; Kohno, Masaki

1997-03-01

Theoretical expressions for thermal and electrical feedback effects are derived. These limit the power capability of a power FET and lead a device to catastrophic breakdown (source-drain burnout) when the loop gain of the former reaches unity. Field emission of thermally excited electrons at the Schottky gate plays the key role in thermal feedback, while holes being impact ionized by the drain current play a similar role in the electrical feedback. Thermal feedback is dominant in a high temperature and low drain voltage area. Electrical feedback is dominant in a high drain voltage and low temperature area. In the first area, a high junction temperature is the main factor causing the thermal runaway of the device. In the second area, the electrcal feedback increases the drain current and the temperature and gives a trigger to the thermal feedback so that it reaches unity more easily. Both effects become significant in proportion to transconductance and gate bias resistance, and cause simultaneous runaway of the gate and drain currents. The expressions of the loop gains clearly indicate the safe operating conditions for a power FET. C-band 4 W (1 chip) and 16 W (4 chip) GaAs MESFETs were used as the experimental samples. With these devices the simultaneous runaway of the gate and the drain currents, apparent dependence of the three teminal breakdown voltage on the gate bias resistance in the region dominated by electrical feedback, the rapid increase of the field emitted current at the critical temperature and clear coincidence between the measured and calculated three terminal gate currents both in the thermal feedback dominant region, etc. are demonstrated. The theory explains the experimental results well.

A VLSI decomposition of the deBruijn graph

NASA Technical Reports Server (NTRS)

Collins, O.; Dolinar, S.; Mceliece, R.; Pollara, F.

1990-01-01

A new Viterbi decoder for convolutional codes with constraint lengths up to 15, called the Big Viterbi Decoder, is under development for the Deep Space Network. It will be demonstrated by decoding data from the Galileo spacecraft, which has a rate 1/4, constraint-length 15 convolutional encoder on board. Here, the mathematical theory underlying the design of the very-large-scale-integrated (VLSI) chips that are being used to build this decoder is explained. The deBruijn graph B sub n describes the topology of a fully parallel, rate 1/v, constraint length n+2 Viterbi decoder, and it is shown that B sub n can be built by appropriately wiring together (i.e., connecting together with extra edges) many isomorphic copies of a fixed graph called a B sub n building block. The efficiency of such a building block is defined as the fraction of the edges in B sub n that are present in the copies of the building block. It is shown, among other things, that for any alpha less than 1, there exists a graph G which is a B sub n building block of efficiency greater than alpha for all sufficiently large n. These results are illustrated by describing a special hierarchical family of deBruijn building blocks, which has led to the design of the gate-array chips being used in the Big Viterbi Decoder.

Fabrication and demonstration of 1 × 8 silicon-silica multi-chip switch based on optical phased array

NASA Astrophysics Data System (ADS)

Katayose, Satomi; Hashizume, Yasuaki; Itoh, Mikitaka

2016-08-01

We experimentally demonstrated a 1 × 8 silicon-silica hybrid thermo-optic switch based on an optical phased array using a multi-chip integration technique. The switch consists of a silicon chip with optical phase shifters and two silica-based planar lightwave circuit (PLC) chips composed of optical couplers and fiber connections. We adopted a rib waveguide as the silicon waveguide to reduce the coupling loss and increase the alignment tolerance for coupling between silicon and silica waveguides. As a result, we achieved a fast switching response of 81 µs, a high extinction ratio of over 18 dB and a low insertion loss of 4.9-8.1 dB including a silicon-silica coupling loss of 0.5 ± 0.3 dB at a wavelength of 1.55 µm.

VIZARD: analysis of Affymetrix Arabidopsis GeneChip data

NASA Technical Reports Server (NTRS)

Moseyko, Nick; Feldman, Lewis J.

2002-01-01

SUMMARY: The Affymetrix GeneChip Arabidopsis genome array has proved to be a very powerful tool for the analysis of gene expression in Arabidopsis thaliana, the most commonly studied plant model organism. VIZARD is a Java program created at the University of California, Berkeley, to facilitate analysis of Arabidopsis GeneChip data. It includes several integrated tools for filtering, sorting, clustering and visualization of gene expression data as well as tools for the discovery of regulatory motifs in upstream sequences. VIZARD also includes annotation and upstream sequence databases for the majority of genes represented on the Affymetrix Arabidopsis GeneChip array. AVAILABILITY: VIZARD is available free of charge for educational, research, and not-for-profit purposes, and can be downloaded at http://www.anm.f2s.com/research/vizard/ CONTACT: moseyko@uclink4.berkeley.edu.

High-speed line-scan camera with digital time delay integration

NASA Astrophysics Data System (ADS)

Bodenstorfer, Ernst; Fürtler, Johannes; Brodersen, Jörg; Mayer, Konrad J.; Eckel, Christian; Gravogl, Klaus; Nachtnebel, Herbert

2007-02-01

Dealing with high-speed image acquisition and processing systems, the speed of operation is often limited by the amount of available light, due to short exposure times. Therefore, high-speed applications often use line-scan cameras, based on charge-coupled device (CCD) sensors with time delayed integration (TDI). Synchronous shift and accumulation of photoelectric charges on the CCD chip - according to the objects' movement - result in a longer effective exposure time without introducing additional motion blur. This paper presents a high-speed color line-scan camera based on a commercial complementary metal oxide semiconductor (CMOS) area image sensor with a Bayer filter matrix and a field programmable gate array (FPGA). The camera implements a digital equivalent to the TDI effect exploited with CCD cameras. The proposed design benefits from the high frame rates of CMOS sensors and from the possibility of arbitrarily addressing the rows of the sensor's pixel array. For the digital TDI just a small number of rows are read out from the area sensor which are then shifted and accumulated according to the movement of the inspected objects. This paper gives a detailed description of the digital TDI algorithm implemented on the FPGA. Relevant aspects for the practical application are discussed and key features of the camera are listed.

Roll Angle Estimation Using Thermopiles for a Flight Controlled Mortar

DTIC Science & Technology

2012-06-01

Using Xilinx’s System generator, the entire design was implemented at a relatively high level within Malab’s Simulink. This allowed VHDL code to...thermopile data with a Recursive Least Squares (RLS) filter implemented on a field programmable gate array (FPGA). These results demonstrate the...accurately estimated by processing the thermopile data with a Recursive Least Squares (RLS) filter implemented on a field programmable gate array (FPGA

TRIGA: Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Arrays

NASA Technical Reports Server (NTRS)

Pang, Jackson; Pingree, Paula J.; Torgerson, J. Leigh

2006-01-01

We present the Telecommunications protocol processing subsystem using Reconfigurable Interoperable Gate Arrays (TRIGA), a novel approach that unifies fault tolerance, error correction coding and interplanetary communication protocol off-loading to implement CCSDS File Delivery Protocol and Datalink layers. The new reconfigurable architecture offers more than one order of magnitude throughput increase while reducing footprint requirements in memory, command and data handling processor utilization, communication system interconnects and power consumption.

Monolithic Integration of a Silicon Nanowire Field-Effect Transistors Array on a Complementary Metal-Oxide Semiconductor Chip for Biochemical Sensor Applications

PubMed Central

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2017-01-01

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I−V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs. PMID:26348408

Comminution process to produce precision wood particles of uniform size and shape with disrupted grain structure from wood chips

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dooley, James H; Lanning, David N

A process of comminution of wood chips (C) having a grain direction to produce a mixture of wood particles (P), wherein the wood chips are characterized by an average length dimension (L.sub.C) as measured substantially parallel to the grain, an average width dimension (W.sub.C) as measured normal to L.sub.C and aligned cross grain, and an average height dimension (H.sub.C) as measured normal to W.sub.C and L.sub.C, and wherein the comminution process comprises the step of feeding the wood chips in a direction of travel substantially randomly to the grain direction through a counter rotating pair of intermeshing arrays of cuttingmore » discs (D) arrayed axially perpendicular to the direction of wood chip travel, wherein the cutting discs have a uniform thickness (T.sub.D), and wherein at least one of L.sub.C, W.sub.C, and H.sub.C is greater than T.sub.D.« less

Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

PubMed

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2015-10-06

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

Binary CMOS image sensor with a gate/body-tied MOSFET-type photodetector for high-speed operation

NASA Astrophysics Data System (ADS)

Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Kim, Sang-Hwan; Shin, Jang-Kyoo

2016-05-01

In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.

Electrofluidics in Micro/Nanofluidic Systems

NASA Astrophysics Data System (ADS)

Guan, Weihua

This work presents the efforts to study the electrofluidics, with a focus on the electric field - matter interactions in microfluidic and nanofluidic systems for lab-on-a-chip applications. The field of electrofluidics integrates the multidisciplinary knowledge in silicon technology, solid and soft condensed matter physics, fluidics, electrochemistry, and electronics. The fundamental understanding of electrofluidics in engineered micro and nano structures opens up wide opportunities for biomedical sensing and actuation devices integrated on a single chip. Using spatial and temporal properties of electric fields in top-down engineered micro/nana structures, we successfully demonstrated the precise control over a single macro-ion and a collective group of ions in aqueous solutions. In the manipulation of a single macro-ion, we revisited the long-time overlooked AC electrophoretic (ACEP) phenomena. We proved that the widely held notion of vanishing electrophoretic (EP) effects in AC fields does not apply to spatially non-uniform electric fields. In contrast to dielectrophoretic (DEP) traps, ACEP traps favor the downscaling of the particle size if it is sufficiently charged. We experimentally demonstrated the predicted ACEP trap by recognizing that the ACEP dynamics is equivalent to that of Paul traps working in an aqueous solution. Since all Paul traps realized so far have only been operated in vacuum or gaseous phase, our experimental effort represents the world's first aqueous Paul trap device. In the manipulation of a collective group of ions, we demonstrated that the ion transport in nanochannels can be directly gated by DC electric fields, an impossible property in microscale geometries. Successful fabrication techniques were developed to create the nanochannel structures with gating ability. Using the gated nanochannel structures, we demonstrated a field effect reconfigurable nanofluidic diode, whose forward/reverse direction as well as the rectification degree can be significantly modulated. We also demonstrated a solid-state protocell, whose ion selectivity and membrane potential can be modulated by external electric field. Moreover, by recognizing the key role played by the surface charge density in electrofluidic gating of nanochannels, a low-cost, off-chip extended gate field effect transistor (FET) structure to measure the surface charges at the dielectric-electrolyte interface is demonstrated. This technique simplifies and accelerates the process of dielectric selection for effective electrofluidic gating.

Semiconductor ring lasers subject to both on-chip filtered optical feedback and external conventional optical feedback

NASA Astrophysics Data System (ADS)

Khoder, Mulham; Van der Sande, Guy; Danckaert, Jan; Verschaffelt, Guy

2016-05-01

It is well known that the performance of semiconductor lasers is very sensitive to external optical feedback. This feedback can lead to changes in lasing characteristics and a variety of dynamical effects including chaos and coherence collapse. One way to avoid this external feedback is by using optical isolation, but these isolators and their packaging will increase the cost of the total system. Semiconductor ring lasers nowadays are promising sources in photonic integrated circuits because they do not require cleaved facets or mirrors to form a laser cavity. Recently, some of us proposed to combine semiconductor ring lasers with on chip filtered optical feedback to achieve tunable lasers. The feedback is realized by employing two arrayed waveguide gratings to split/recombine light into different wavelength channels. Semiconductor optical amplifier gates are used to control the feedback strength. In this work, we investigate how such lasers with filtered feedback are influenced by an external conventional optical feedback. The experimental results show intensity fluctuations in the time traces in both the clockwise and counterclockwise directions due to the conventional feedback. We quantify the strength of the conventional feedback induced dynamics be extracting the standard deviation of the intensity fluctuations in the time traces. By using filtered feedback, we can shift the onset of the conventional feedback induced dynamics to larger values of the feedback rate [ Khoder et al, IEEE Photon. Technol. Lett. DOI: 10.1109/LPT.2016.2522184]. The on-chip filtered optical feedback thus makes the semiconductor ring laser less senstive to the effect of (long) conventional optical feedback. We think these conclusions can be extended to other types of lasers.

Multipurpose silicon photonics signal processor core.

PubMed

Pérez, Daniel; Gasulla, Ivana; Crudgington, Lee; Thomson, David J; Khokhar, Ali Z; Li, Ke; Cao, Wei; Mashanovich, Goran Z; Capmany, José

2017-09-21

Integrated photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint, and cost. Application-specific photonic integrated circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long development times. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable photonic processor, where a common hardware implemented by a two-dimensional photonic waveguide mesh realizes different functionalities through programming. Here, we report the demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate over 20 different functionalities with a simple seven hexagonal cell structure, which can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks, and quantum information systems. Our work is an important step toward this paradigm.Integrated optical circuits today are typically designed for a few special functionalities and require complex design and development procedures. Here, the authors demonstrate a reconfigurable but simple silicon waveguide mesh with different functionalities.

A Real-Time Marker-Based Visual Sensor Based on a FPGA and a Soft Core Processor

PubMed Central

Tayara, Hilal; Ham, Woonchul; Chong, Kil To

2016-01-01

This paper introduces a real-time marker-based visual sensor architecture for mobile robot localization and navigation. A hardware acceleration architecture for post video processing system was implemented on a field-programmable gate array (FPGA). The pose calculation algorithm was implemented in a System on Chip (SoC) with an Altera Nios II soft-core processor. For every frame, single pass image segmentation and Feature Accelerated Segment Test (FAST) corner detection were used for extracting the predefined markers with known geometries in FPGA. Coplanar PosIT algorithm was implemented on the Nios II soft-core processor supplied with floating point hardware for accelerating floating point operations. Trigonometric functions have been approximated using Taylor series and cubic approximation using Lagrange polynomials. Inverse square root method has been implemented for approximating square root computations. Real time results have been achieved and pixel streams have been processed on the fly without any need to buffer the input frame for further implementation. PMID:27983714

A single FPGA-based portable ultrasound imaging system for point-of-care applications.

PubMed

Kim, Gi-Duck; Yoon, Changhan; Kye, Sang-Bum; Lee, Youngbae; Kang, Jeeun; Yoo, Yangmo; Song, Tai-kyong

2012-07-01

We present a cost-effective portable ultrasound system based on a single field-programmable gate array (FPGA) for point-of-care applications. In the portable ultrasound system developed, all the ultrasound signal and image processing modules, including an effective 32-channel receive beamformer with pseudo-dynamic focusing, are embedded in an FPGA chip. For overall system control, a mobile processor running Linux at 667 MHz is used. The scan-converted ultrasound image data from the FPGA are directly transferred to the system controller via external direct memory access without a video processing unit. The potable ultrasound system developed can provide real-time B-mode imaging with a maximum frame rate of 30, and it has a battery life of approximately 1.5 h. These results indicate that the single FPGA-based portable ultrasound system developed is able to meet the processing requirements in medical ultrasound imaging while providing improved flexibility for adapting to emerging POC applications.

Compact, Low-Overhead, MIL-STD-1553B Controller

NASA Technical Reports Server (NTRS)

Katz, Richard; Barto, Rod

2009-01-01

A compact and flexible controller has been developed to provide MIL-STD- 1553B Remote Terminal (RT) communications and supporting and related functions with minimal demand on the resources of the system in which the controller is to be installed. (MIL-STD-1553B is a military standard that encompasses a method of communication and electrical-interface requirements for digital electronic subsystems connected to a data bus. MIL-STD-1553B is commonly used in defense and space applications.) Many other MIL-STD-1553B RT controllers are complicated, and to enable them to function, it is necessary to provide software and to use such ancillary separate hardware devices as microprocessors and dual-port memories. The present controller functions without need for software and any ancillary hardware. In addition, it contains a flexible system interface and extensive support hardware while including on-chip error-checking and diagnostic support circuitry. This controller is implemented within part of a modern field-programmable gate array.

An Analysis of Offset, Gain, and Phase Corrections in Analog to Digital Converters

NASA Astrophysics Data System (ADS)

Cody, Devin; Ford, John

2015-01-01

Many high-speed analog to digital converters (ADCs) use interwoven ADCs to greatly boost their sample rate. This interwoven architecture can introduce problems if the low speed ADCs do not have identical outputs. These errors are manifested as phantom frequencies that appear in the digitized signal although they never existed in the analog domain. Through the application of offset, gain, and phase (OGP) corrections to the ADC, this problem can be reduced. Here we report on an implementation of such a correction in a high speed ADC chip used for radio astronomy. While the corrections could not be implemented in the ADCs themselves, a partial solution was devised and implemented digitally inside of a signal processing field programmable gate array (FPGA). Positive results to contrived situations are shown, and null results are presented for implementation in an ADC083000 card with minimal error. Lastly, we discuss the implications of this method as well as its mathematical basis.

Diagnostic layer integration in FPGA-based pipeline measurement systems for HEP experiments

NASA Astrophysics Data System (ADS)

Pozniak, Krzysztof T.

2007-08-01

Integrated triggering and data acquisition systems for high energy physics experiments may be considered as fast, multichannel, synchronous, distributed, pipeline measurement systems. A considerable extension of functional, technological and monitoring demands, which has recently been imposed on them, forced a common usage of large field-programmable gate array (FPGA), digital signal processing-enhanced matrices and fast optical transmission for their realization. This paper discusses modelling, design, realization and testing of pipeline measurement systems. A distribution of synchronous data stream flows is considered in the network. A general functional structure of a single network node is presented. A suggested, novel block structure of the node model facilitates full implementation in the FPGA chip, circuit standardization and parametrization, as well as integration of functional and diagnostic layers. A general method for pipeline system design was derived. This method is based on a unified model of the synchronous data network node. A few examples of practically realized, FPGA-based, pipeline measurement systems were presented. The described systems were applied in ZEUS and CMS.

Coherent coupling between a quantum dot and a donor in silicon

DOE PAGES

Harvey-Collard, Patrick; Jacobson, N. Tobias; Rudolph, Martin; ...

2017-10-18

Individual donors in silicon chips are used as quantum bits with extremely low error rates. However, physical realizations have been limited to one donor because their atomic size causes fabrication challenges. Quantum dot qubits, in contrast, are highly adjustable using electrical gate voltages. This adjustability could be leveraged to deterministically couple donors to quantum dots in arrays of qubits. In this work, we demonstrate the coherent interaction of a 31P donor electron with the electron of a metal-oxide-semiconductor quantum dot. We form a logical qubit encoded in the spin singlet and triplet states of the two-electron system. We show thatmore » the donor nuclear spin drives coherent rotations between the electronic qubit states through the contact hyperfine interaction. This provides every key element for compact two-electron spin qubits requiring only a single dot and no additional magnetic field gradients, as well as a means to interact with the nuclear spin qubit.« less

Performance Evaluation of Heart Sound Cancellation in FPGA Hardware Implementation for Electronic Stethoscope

PubMed Central

Chao, Chun-Tang

2014-01-01

This paper presents the design and evaluation of the hardware circuit for electronic stethoscopes with heart sound cancellation capabilities using field programmable gate arrays (FPGAs). The adaptive line enhancer (ALE) was adopted as the filtering methodology to reduce heart sound attributes from the breath sounds obtained via the electronic stethoscope pickup. FPGAs were utilized to implement the ALE functions in hardware to achieve near real-time breath sound processing. We believe that such an implementation is unprecedented and crucial toward a truly useful, standalone medical device in outpatient clinic settings. The implementation evaluation with one Altera cyclone II–EP2C70F89 shows that the proposed ALE used 45% resources of the chip. Experiments with the proposed prototype were made using DE2-70 emulation board with recorded body signals obtained from online medical archives. Clear suppressions were observed in our experiments from both the frequency domain and time domain perspectives. PMID:24790573

A Real-Time Marker-Based Visual Sensor Based on a FPGA and a Soft Core Processor.

PubMed

Tayara, Hilal; Ham, Woonchul; Chong, Kil To

2016-12-15

This paper introduces a real-time marker-based visual sensor architecture for mobile robot localization and navigation. A hardware acceleration architecture for post video processing system was implemented on a field-programmable gate array (FPGA). The pose calculation algorithm was implemented in a System on Chip (SoC) with an Altera Nios II soft-core processor. For every frame, single pass image segmentation and Feature Accelerated Segment Test (FAST) corner detection were used for extracting the predefined markers with known geometries in FPGA. Coplanar PosIT algorithm was implemented on the Nios II soft-core processor supplied with floating point hardware for accelerating floating point operations. Trigonometric functions have been approximated using Taylor series and cubic approximation using Lagrange polynomials. Inverse square root method has been implemented for approximating square root computations. Real time results have been achieved and pixel streams have been processed on the fly without any need to buffer the input frame for further implementation.

Colt: an experiment in wormhole run-time reconfiguration

NASA Astrophysics Data System (ADS)

Bittner, Ray; Athanas, Peter M.; Musgrove, Mark

1996-10-01

Wormhole run-time reconfiguration (RTR) is an attempt to create a refined computing paradigm for high performance computational tasks. By combining concepts from field programmable gate array (FPGA) technologies with data flow computing, the Colt/Stallion architecture achieves high utilization of hardware resources, and facilitates rapid run-time reconfiguration. Targeted mainly at DSP-type operations, the Colt integrated circuit -- a prototype wormhole RTR device -- compares favorably to contemporary DSP alternatives in terms of silicon area consumed per unit computation and in computing performance. Although emphasis has been placed on signal processing applications, general purpose computation has not been overlooked. Colt is a prototype that defines an architecture not only at the chip level but also in terms of an overall system design. As this system is realized, the concept of wormhole RTR will be applied to numerical computation and DSP applications including those common to image processing, communications systems, digital filters, acoustic processing, real-time control systems and simulation acceleration.

On the implementation of IP protection using biometrics based information hiding and firewall

NASA Astrophysics Data System (ADS)

Basu, Abhishek; Nandy, Kingshuk; Banerjee, Avishek; Giri, Supratick; Sarkar, Souvik; Sarkar, Subir Kumar

2016-02-01

System-on-chip-based design style creates a revolution in very large scale integration industry with design efficiency, operating speed and development time. To support this process, reuse and exchange of components are essential in electronic form called intellectual property (IP). This, however, increases the possibility of encroachment of IP of the design. So copyright protection of IP against piracy is the most important concern for IP vendors. The existing solutions for IP protection are still not secure enough with flexibility, cost, etc. This paper proposes an information-hiding-based solution for IP protection by embedding a biometric copyright information and firewall inside an IP in the form of a finite state machine with unique configuration. The scheme first introduces biometric signature-based copyright as ownership proof. Second, firewall interrupts the normal functionality of IP at the end of the user time period. The experimental outcomes of field-programmable-gate-array implementation illustrate the efficiency of the proposed method.

Dosimetric verification of gated delivery of electron beams using a 2D ion chamber array

PubMed Central

Yoganathan, S. A.; Das, K. J. Maria; Raj, D. Gowtham; Kumar, Shaleen

2015-01-01

The purpose of this study was to compare the dosimetric characteristics; such as beam output, symmetry and flatness between gated and non-gated electron beams. Dosimetric verification of gated delivery was carried for all electron beams available on Varian CL 2100CD medical linear accelerator. Measurements were conducted for three dose rates (100 MU/min, 300 MU/min and 600 MU/min) and two respiratory motions (breathing period of 4s and 8s). Real-time position management (RPM) system was used for the gated deliveries. Flatness and symmetry values were measured using Imatrixx 2D ion chamber array device and the beam output was measured using plane parallel ion chamber. These detector systems were placed over QUASAR motion platform which was programmed to simulate the respiratory motion of target. The dosimetric characteristics of gated deliveries were compared with non-gated deliveries. The flatness and symmetry of all the evaluated electron energies did not differ by more than 0.7 % with respect to corresponding non-gated deliveries. The beam output variation of gated electron beam was less than 0.6 % for all electron energies except for 16 MeV (1.4 %). Based on the results of this study, it can be concluded that Varian CL2100 CD is well suitable for gated delivery of non-dynamic electron beams. PMID:26170552

Novel conformal organic antireflective coatings for advanced I-line lithography

NASA Astrophysics Data System (ADS)

Deshpande, Shreeram V.; Nowak, Kelly A.; Fowler, Shelly; Williams, Paul; Arjona, Mikko

2001-08-01

Flash memory chips are playing a critical role in semiconductor devices due to increased popularity of hand held electronic communication devices such as cell phones and PDAs (personal Digital Assistants). Flash memory offers two primary advantages in semiconductor devices. First, it offers flexibility of in-circuit programming capability to reduce the loss from programming errors and to significantly reduce commercialization time to market for new devices. Second, flash memory has a double density memory capability through stacked gate structures which increases the memory capability and thus saves significantly on chip real estate. However, due to stacked gate structures the requirements for manufacturing of flash memory devices are significantly different from traditional memory devices. Stacked gate structures also offer unique challenges to lithographic patterning materials such as Bottom Anti-Reflective Coating (BARC) compositions used to achieve CD control and to minimize standing wave effect in photolithography. To be applicable in flash memory manufacturing a BARC should form a conformal coating on high topography of stacked gate features as well as provide the normal anti-reflection properties for CD control. In this paper we report on a new highly conformal advanced i-line BARC for use in design and manufacture of flash memory devices. Conformal BARCs being significantly thinner in trenches than the planarizing BARCs offer the advantage of reducing BARC overetch and thus minimizing resist thickness loss.

Super-Lattice Light Emitting Diodes (SLEDS) on GaAs

DTIC Science & Technology

2016-03-31

Super-Lattice Light Emitting Diodes (SLEDS) on GaAs Kassem Nabha1, Russel Ricker2, Rodney McGee1, Nick Waite1, John Prineas2, Sydney Provence2...infrared light emitting diodes (LEDs). Typically, the LED arrays are mated with CMOS read-in integrated circuit (RIIC) chips using flip-chip bonding. In...circuit (RIIC) chips using flip-chip bonding. This established technology is called Hybrid-super-lattice light emitting diodes (Hybrid- SLEDS). In

High-Performance, Radiation-Hardened Electronics for Space Environments

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Watson, Michael D.; Frazier, Donald O.; Adams, James H.; Johnson, Michael A.; Kolawa, Elizabeth A.

2007-01-01

The Radiation Hardened Electronics for Space Environments (RHESE) project endeavors to advance the current state-of-the-art in high-performance, radiation-hardened electronics and processors, ensuring successful performance of space systems required to operate within extreme radiation and temperature environments. Because RHESE is a project within the Exploration Technology Development Program (ETDP), RHESE's primary customers will be the human and robotic missions being developed by NASA's Exploration Systems Mission Directorate (ESMD) in partial fulfillment of the Vision for Space Exploration. Benefits are also anticipated for NASA's science missions to planetary and deep-space destinations. As a technology development effort, RHESE provides a broad-scoped, full spectrum of approaches to environmentally harden space electronics, including new materials, advanced design processes, reconfigurable hardware techniques, and software modeling of the radiation environment. The RHESE sub-project tasks are: SelfReconfigurable Electronics for Extreme Environments, Radiation Effects Predictive Modeling, Radiation Hardened Memory, Single Event Effects (SEE) Immune Reconfigurable Field Programmable Gate Array (FPGA) (SIRF), Radiation Hardening by Software, Radiation Hardened High Performance Processors (HPP), Reconfigurable Computing, Low Temperature Tolerant MEMS by Design, and Silicon-Germanium (SiGe) Integrated Electronics for Extreme Environments. These nine sub-project tasks are managed by technical leads as located across five different NASA field centers, including Ames Research Center, Goddard Space Flight Center, the Jet Propulsion Laboratory, Langley Research Center, and Marshall Space Flight Center. The overall RHESE integrated project management responsibility resides with NASA's Marshall Space Flight Center (MSFC). Initial technology development emphasis within RHESE focuses on the hardening of Field Programmable Gate Arrays (FPGA)s and Field Programmable Analog Arrays (FPAA)s for use in reconfigurable architectures. As these component/chip level technologies mature, the RHESE project emphasis shifts to focus on efforts encompassing total processor hardening techniques and board-level electronic reconfiguration techniques featuring spare and interface modularity. This phased approach to distributing emphasis between technology developments provides hardened FPGA/FPAAs for early mission infusion, then migrates to hardened, board-level, high speed processors with associated memory elements and high density storage for the longer duration missions encountered for Lunar Outpost and Mars Exploration occurring later in the Constellation schedule.

Real-time, multiplexed electrochemical DNA detection using an active complementary metal-oxide-semiconductor biosensor array with integrated sensor electronics.

PubMed

Levine, Peter M; Gong, Ping; Levicky, Rastislav; Shepard, Kenneth L

2009-03-15

Optical biosensing based on fluorescence detection has arguably become the standard technique for quantifying extents of hybridization between surface-immobilized probes and fluorophore-labeled analyte targets in DNA microarrays. However, electrochemical detection techniques are emerging which could eliminate the need for physically bulky optical instrumentation, enabling the design of portable devices for point-of-care applications. Unlike fluorescence detection, which can function well using a passive substrate (one without integrated electronics), multiplexed electrochemical detection requires an electronically active substrate to analyze each array site and benefits from the addition of integrated electronic instrumentation to further reduce platform size and eliminate the electromagnetic interference that can result from bringing non-amplified signals off chip. We report on an active electrochemical biosensor array, constructed with a standard complementary metal-oxide-semiconductor (CMOS) technology, to perform quantitative DNA hybridization detection on chip using targets conjugated with ferrocene redox labels. A 4 x 4 array of gold working electrodes and integrated potentiostat electronics, consisting of control amplifiers and current-input analog-to-digital converters, on a custom-designed 5 mm x 3 mm CMOS chip drive redox reactions using cyclic voltammetry, sense DNA binding, and transmit digital data off chip for analysis. We demonstrate multiplexed and specific detection of DNA targets as well as real-time monitoring of hybridization, a task that is difficult, if not impossible, with traditional fluorescence-based microarrays.

Telecom meets terahertz

NASA Astrophysics Data System (ADS)

Nikitin, Alexey Y.

2018-01-01

Excitation and gate tuning of terahertz plasmons in dual-layer graphene integrated into on-chip telecom photonic waveguides using infrared lasers has now been demonstrated. This may open the door to atomically thick optoelectronic devices for security, tomography or data processing.

Topological Properties of Some Integrated Circuits for Very Large Scale Integration Chip Designs

NASA Astrophysics Data System (ADS)

Swanson, S.; Lanzerotti, M.; Vernizzi, G.; Kujawski, J.; Weatherwax, A.

2015-03-01

This talk presents topological properties of integrated circuits for Very Large Scale Integration chip designs. These circuits can be implemented in very large scale integrated circuits, such as those in high performance microprocessors. Prior work considered basic combinational logic functions and produced a mathematical framework based on algebraic topology for integrated circuits composed of logic gates. Prior work also produced an historically-equivalent interpretation of Mr. E. F. Rent's work for today's complex circuitry in modern high performance microprocessors, where a heuristic linear relationship was observed between the number of connections and number of logic gates. This talk will examine topological properties and connectivity of more complex functionally-equivalent integrated circuits. The views expressed in this article are those of the author and do not reflect the official policy or position of the United States Air Force, Department of Defense or the U.S. Government.

Real-Time Label-Free Detection of Suspicious Powders Using Noncontact Optical Methods

DTIC Science & Technology

2013-11-05

energy in a small, 1 pound, low power consumption package; and 2) new technology resistive gate linear CCD array detectors developed by Hamamatsu Corp...as a wide range of possible interferent or confusant organic materials such as powdered sugar, granulate sugar, fruit pectin, flower, corn starch ...resolution, room temperature, resistive gate linear CCD array, the BRANE sensor SWAP decreases along with a decrease in sensitivity, but the information

NEPP Update of Independent Single Event Upset Field Programmable Gate Array Testing

NASA Technical Reports Server (NTRS)

Berg, Melanie; Label, Kenneth; Campola, Michael; Pellish, Jonathan

2017-01-01

This presentation provides a NASA Electronic Parts and Packaging (NEPP) Program update of independent Single Event Upset (SEU) Field Programmable Gate Array (FPGA) testing including FPGA test guidelines, Microsemi RTG4 heavy-ion results, Xilinx Kintex-UltraScale heavy-ion results, Xilinx UltraScale+ single event effect (SEE) test plans, development of a new methodology for characterizing SEU system response, and NEPP involvement with FPGA security and trust.

Initial Single Event Effects Testing of the Xilinx Virtex-4 Field Programmable Gate Array

NASA Technical Reports Server (NTRS)

Allen, Gregory R.; Swift, Gary M.; Carmichael, C.; Tseng, C.

2007-01-01

We present initial results for the thin epitaxial Xilinx Virtex-4 Fie ld Programmable Gate Array (FPGA), and compare to previous results ob tained for the Virtex-II and Virtex-II Pro. The data presented was a cquired through a consortium based effort with the common goal of pr oviding the space community with data and mitigation methods for the use of Xilinx FPGAs in space.

Analog storage integrated circuit

DOEpatents

Walker, J. T.; Larsen, R. S.; Shapiro, S. L.

1989-01-01

A high speed data storage array is defined utilizing a unique cell design for high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates between the signal input and a storage capacitor. The gates are controlled by a high speed row clock and low speed column clock so that the instantaneous analog value of the signal is only sampled and stored by each cell on coincidence of the two clocks.

Analog storage integrated circuit

DOEpatents

Walker, J.T.; Larsen, R.S.; Shapiro, S.L.

1989-03-07

A high speed data storage array is defined utilizing a unique cell design for high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates between the signal input and a storage capacitor. The gates are controlled by a high speed row clock and low speed column clock so that the instantaneous analog value of the signal is only sampled and stored by each cell on coincidence of the two clocks. 6 figs.

Gas Sensors Characterization and Multilayer Perceptron (MLP) Hardware Implementation for Gas Identification Using a Field Programmable Gate Array (FPGA)

PubMed Central

Benrekia, Fayçal; Attari, Mokhtar; Bouhedda, Mounir

2013-01-01

This paper develops a primitive gas recognition system for discriminating between industrial gas species. The system under investigation consists of an array of eight micro-hotplate-based SnO2 thin film gas sensors with different selectivity patterns. The output signals are processed through a signal conditioning and analyzing system. These signals feed a decision-making classifier, which is obtained via a Field Programmable Gate Array (FPGA) with Very High-Speed Integrated Circuit Hardware Description Language. The classifier relies on a multilayer neural network based on a back propagation algorithm with one hidden layer of four neurons and eight neurons at the input and five neurons at the output. The neural network designed after implementation consists of twenty thousand gates. The achieved experimental results seem to show the effectiveness of the proposed classifier, which can discriminate between five industrial gases. PMID:23529119

Single array of magnetic vortex disks uses in-plane anisotropy to create different logic gates

NASA Astrophysics Data System (ADS)

Vigo-Cotrina, H.; Guimarães, A. P.

2017-11-01

Using micromagnetic simulation, we show that in-plane uniaxial magnetic anisotropy (IPUA) can be used to obtain FAN-OUT, AND and OR gates in an array of coupled disks with magnetic vortex configuration. First, we studied the influence of the direction of application of the IPUA on the energy transfer time (τ) between two identical coupled nanodisks. We found that when the direction of the IPUA is along the x axis the magnetic interaction increases, allowing shorter values of τ , while the IPUA along the y direction has the opposite effect. The magnetic interactions between the nanodisks along x and y directions (the coupling integrals) as a function of the uniaxial anisotropy constant (Kσ) were obtained using a simple dipolar model. Next, we demonstrated that choosing a suitable direction of application of the IPUA, it is possible to create several different logic gates with a single array of coupled nanodisks.

Design of an Elliptic Curve Cryptography processor for RFID tag chips.

PubMed

Liu, Zilong; Liu, Dongsheng; Zou, Xuecheng; Lin, Hui; Cheng, Jian

2014-09-26

Radio Frequency Identification (RFID) is an important technique for wireless sensor networks and the Internet of Things. Recently, considerable research has been performed in the combination of public key cryptography and RFID. In this paper, an efficient architecture of Elliptic Curve Cryptography (ECC) Processor for RFID tag chip is presented. We adopt a new inversion algorithm which requires fewer registers to store variables than the traditional schemes. A new method for coordinate swapping is proposed, which can reduce the complexity of the controller and shorten the time of iterative calculation effectively. A modified circular shift register architecture is presented in this paper, which is an effective way to reduce the area of register files. Clock gating and asynchronous counter are exploited to reduce the power consumption. The simulation and synthesis results show that the time needed for one elliptic curve scalar point multiplication over GF(2163) is 176.7 K clock cycles and the gate area is 13.8 K with UMC 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) technology. Moreover, the low power and low cost consumption make the Elliptic Curve Cryptography Processor (ECP) a prospective candidate for application in the RFID tag chip.

Design of an Elliptic Curve Cryptography Processor for RFID Tag Chips

PubMed Central

Liu, Zilong; Liu, Dongsheng; Zou, Xuecheng; Lin, Hui; Cheng, Jian

2014-01-01

Radio Frequency Identification (RFID) is an important technique for wireless sensor networks and the Internet of Things. Recently, considerable research has been performed in the combination of public key cryptography and RFID. In this paper, an efficient architecture of Elliptic Curve Cryptography (ECC) Processor for RFID tag chip is presented. We adopt a new inversion algorithm which requires fewer registers to store variables than the traditional schemes. A new method for coordinate swapping is proposed, which can reduce the complexity of the controller and shorten the time of iterative calculation effectively. A modified circular shift register architecture is presented in this paper, which is an effective way to reduce the area of register files. Clock gating and asynchronous counter are exploited to reduce the power consumption. The simulation and synthesis results show that the time needed for one elliptic curve scalar point multiplication over GF(2163) is 176.7 K clock cycles and the gate area is 13.8 K with UMC 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) technology. Moreover, the low power and low cost consumption make the Elliptic Curve Cryptography Processor (ECP) a prospective candidate for application in the RFID tag chip. PMID:25264952

Promotion of osteoblast differentiation in 3D biomaterial micro-chip arrays comprising fibronectin-coated poly(methyl methacrylate) polycarbonate.

PubMed

Altmann, Brigitte; Steinberg, Thorsten; Giselbrecht, Stefan; Gottwald, Eric; Tomakidi, Pascal; Bächle-Haas, Maria; Kohal, Ralf-Joachim

2011-12-01

Due to the architecture of solid body tissues including bone, three-dimensional (3D) in vitro microenvironments appear favorable, since herein cell growth proceeds under more physiological conditions compared to conventional 2D systems. In the present study we show that a 3D microenvironment comprising a fibronectin-coated PMMA/PC-based micro-chip promotes differentiation of primary human osteoblasts as reflected by the densely-packed 3D bone cell aggregates and expression of biomarkers indicating osteoblast differentiation. Morphogenesis and fluorescence dye-based live/dead staining revealed homogenous cell coverage of the microcavities of the chip array, whereat cells showed high viability up to 14 days. Moreover, Azur II staining proved formation of uniform sized multilayered aggregates, exhibiting progressive intracellular deposition of extracellular bone matrix constituents comprising fibronectin, osteocalcin and osteonectin from day 7 on. Compared to 2D monolayers, osteoblasts grown in the 3D chip environment displayed differential mostly higher gene expression for osteocalcin, osteonectin, and alkaline phosphatase, while collagen type I remained fairly constant in both culture environments. Our results indicate that the 3D microenvironment, based on the PMMA biomaterial chip array promotes osteoblast differentiation, and hereby renders a promising tool for tissue-specific in vitro preconditioning of osteoblasts designated for clinically-oriented bone augmentation or regeneration. Copyright © 2011 Elsevier Ltd. All rights reserved.

Integrated photonic quantum gates for polarization qubits.

PubMed

Crespi, Andrea; Ramponi, Roberta; Osellame, Roberto; Sansoni, Linda; Bongioanni, Irene; Sciarrino, Fabio; Vallone, Giuseppe; Mataloni, Paolo

2011-11-29

The ability to manipulate quantum states of light by integrated devices may open new perspectives both for fundamental tests of quantum mechanics and for novel technological applications. However, the technology for handling polarization-encoded qubits, the most commonly adopted approach, is still missing in quantum optical circuits. Here we demonstrate the first integrated photonic controlled-NOT (CNOT) gate for polarization-encoded qubits. This result has been enabled by the integration, based on femtosecond laser waveguide writing, of partially polarizing beam splitters on a glass chip. We characterize the logical truth table of the quantum gate demonstrating its high fidelity to the expected one. In addition, we show the ability of this gate to transform separable states into entangled ones and vice versa. Finally, the full accessibility of our device is exploited to carry out a complete characterization of the CNOT gate through a quantum process tomography.

Silicon chip with capacitors and transistors for interfacing organotypic brain slice of rat hippocampus.

PubMed

Hutzler, Michael; Fromherz, Peter

2004-04-01

Probing projections between brain areas and their modulation by synaptic potentiation requires dense arrays of contacts for noninvasive electrical stimulation and recording. Semiconductor technology is able to provide planar arrays with high spatial resolution to be used with planar neuronal structures such as organotypic brain slices. To address basic methodical issues we developed a silicon chip with simple arrays of insulated capacitors and field-effect transistors for stimulation of neuronal activity and recording of evoked field potentials. Brain slices from rat hippocampus were cultured on that substrate. We achieved local stimulation of the CA3 region by applying defined voltage pulses to the chip capacitors. Recording of resulting local field potentials in the CA1 region was accomplished with transistors. The relationship between stimulation and recording was rationalized by a sheet conductor model. By combining a row of capacitors with a row of transistors we determined a simple stimulus-response matrix from CA3 to CA1. Possible contributions of inhomogeneities of synaptic projection, of tissue structure and of neuroelectronic interfacing were considered. The study provides the basis for a development of semiconductor chips with high spatial resolution that are required for long-term studies of topographic mapping.

Chip-based molecularly imprinted monolithic capillary array columns coated GO/SiO2 for selective extraction and sensitive determination of rhodamine B in chili powder.

PubMed

Zhai, Haiyun; Huang, Lu; Chen, Zuanguang; Su, Zihao; Yuan, Kaisong; Liang, Guohuan; Pan, Yufang

2017-01-01

A novel solid-phase extraction chip embedded with array columns of molecularly imprinted polymer-coated silanized graphene oxide (GO/SiO2-MISPE) was established to detect trace rhodamine B (RB) in chili powder. GO/SiO2-MISPE monolithic columns for RB detection were prepared by optimizing the supporting substrate, template, and polymerizing monomer under mild water bath conditions. Adsorption capacity and specificity, which are critical properties for the application of the GO/SiO2-MISPE monolithic column, were investigated. GO/SiO2-MIP was examined by scanning electron microscopy (SEM) and Fourier transform-infrared spectroscopy. The recovery and the intraday and interday relative standard deviations for RB ranged from 83.7% to 88.4% and 2.5% to 4.0% and the enrichment factors were higher than 110-fold. The chip-based array columns effectively eliminated impurities in chili powder, indicating that the chip-based GO/SiO2-MISPE method was reliable for RB detection in food samples using high-performance liquid chromatography. Accordingly, this method has direct applications for monitoring potentially harmful dyes in processed food. Copyright © 2016 Elsevier Ltd. All rights reserved.

Linear and passive silicon diodes, isolators, and logic gates

NASA Astrophysics Data System (ADS)

Li, Zhi-Yuan

2013-12-01

Silicon photonic integrated devices and circuits have offered a promising means to revolutionalize information processing and computing technologies. One important reason is that these devices are compatible with conventional complementary metal oxide semiconductor (CMOS) processing technology that overwhelms current microelectronics industry. Yet, the dream to build optical computers has yet to come without the breakthrough of several key elements including optical diodes, isolators, and logic gates with low power, high signal contrast, and large bandwidth. Photonic crystal has a great power to mold the flow of light in micrometer/nanometer scale and is a promising platform for optical integration. In this paper we present our recent efforts of design, fabrication, and characterization of ultracompact, linear, passive on-chip optical diodes, isolators and logic gates based on silicon two-dimensional photonic crystal slabs. Both simulation and experiment results show high performance of these novel designed devices. These linear and passive silicon devices have the unique properties of small fingerprint, low power request, large bandwidth, fast response speed, easy for fabrication, and being compatible with COMS technology. Further improving their performance would open up a road towards photonic logics and optical computing and help to construct nanophotonic on-chip processor architectures for future optical computers.

Single-Chip CMUT-on-CMOS Front-End System for Real-Time Volumetric IVUS and ICE Imaging

PubMed Central

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F. Levent

2014-01-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of CMUT arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-µm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-µm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single-chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex-vivo chicken heart sample. The measured axial and lateral point resolutions are 92 µm and 251 µm, respectively. We successfully acquired volumetric imaging data from the ex-vivo chicken heart with 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce real-time volumetric images with image quality and speed suitable for catheter based clinical applications. PMID:24474131

Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

PubMed

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

2014-02-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

Multiplexed protein detection using antibody-conjugated microbead arrays in a microfabricated electrophoretic device

PubMed Central

Barbee, Kristopher D.; Hsiao, Alexander P.; Roller, Eric E.; Huang, Xiaohua

2011-01-01

We report the development of a microfabricated electrophoretic device for assembling high-density arrays of antibody-conjugated microbeads for chip-based protein detection. The device consists of a flow cell formed between a gold-coated silicon chip with an array of microwells etched in a silicon dioxide film and a glass coverslip with a series of thin gold counter electrode lines. We have demonstrated that 0.4 and 1 μm beads conjugated with antibodies can be rapidly assembled into the microwells by applying a pulsed electric field across the chamber. By assembling step-wise a mixture of fluorescently labeled antibody-conjugated microbeads, we incorporated both spatial and fluorescence encoding strategies to demonstrate significant multiplexing capabilities. We have shown that these antibody-conjugated microbead arrays can be used to perform on-chip sandwich immunoassays to detect test antigens at concentrations as low as 40 pM (6 ng/mL). A finite element model was also developed to examine the electric field distribution within the device for different counter electrode configurations over a range of line pitches and chamber heights. This device will be useful for assembling high-density, encoded antibody arrays for multiplexed detection of proteins and other types of protein-conjugated microbeads for applications such as the analysis of protein-protein interactions. PMID:20820631

Direct detector for terahertz radiation

DOEpatents

Wanke, Michael C [Albuquerque, NM; Lee, Mark [Albuquerque, NM; Shaner, Eric A [Albuquerque, NM; Allen, S James [Santa Barbara, CA

2008-09-02

A direct detector for terahertz radiation comprises a grating-gated field-effect transistor with one or more quantum wells that provide a two-dimensional electron gas in the channel region. The grating gate can be a split-grating gate having at least one finger that can be individually biased. Biasing an individual finger of the split-grating gate to near pinch-off greatly increases the detector's resonant response magnitude over prior QW FET detectors while maintaining frequency selectivity. The split-grating-gated QW FET shows a tunable resonant plasmon response to FIR radiation that makes possible an electrically sweepable spectrometer-on-a-chip with no moving mechanical optical parts. Further, the narrow spectral response and signal-to-noise are adequate for use of the split-grating-gated QW FET in a passive, multispectral terahertz imaging system. The detector can be operated in a photoconductive or a photovoltaic mode. Other embodiments include uniform front and back gates to independently vary the carrier densities in the channel region, a thinned substrate to increase bolometric responsivity, and a resistive shunt to connect the fingers of the grating gate in parallel and provide a uniform gate-channel voltage along the length of the channel to increase the responsivity and improve the spectral resolution.

High-density CMOS Microelectrode Array System for Impedance Spectroscopy and Imaging of Biological Cells.

PubMed

Vijay, Viswam; Raziyeh, Bounik; Amir, Shadmani; Jelena, Dragas; Alicia, Boos Julia; Axel, Birchler; Jan, Müller; Yihui, Chen; Andreas, Hierlemann

2017-01-26

A monolithic measurement platform was implemented to enable label-free in-vitro electrical impedance spectroscopy measurements of cells on multi-functional CMOS microelectrode array. The array includes 59,760 platinum microelectrodes, densely packed within a 4.5 mm × 2.5 mm sensing region at a pitch of 13.5 μm. The 32 on-chip lock-in amplifiers can be used to measure the impedance of any arbitrarily chosen electrodes on the array by applying a sinusoidal voltage, generated by an on-chip waveform generator with a frequency range from 1 Hz to 1 MHz, and measuring the respective current. Proof-of-concept measurements of impedance sensing and imaging are shown in this paper. Correlations between cell detection through optical microscopy and electrochemical impedance scanning were established.

Ice-assisted transfer of carbon nanotube arrays.

PubMed

Wei, Haoming; Wei, Yang; Lin, Xiaoyang; Liu, Peng; Fan, Shoushan; Jiang, Kaili

2015-03-11

Decoupling the growth and the application of nanomaterials by transfer is an important issue in nanotechnology. Here, we developed an efficient transfer technique for carbon nanotube (CNT) arrays by using ice as a binder to temporarily bond the CNT array and the target substrate. Ice makes it an ultraclean transfer because the evaporation of ice ensures that no contaminants are introduced. The transferred superaligned carbon nanotube (SACNT) arrays not only keep their original appearance and initial alignment but also inherit their spinnability, which is the most desirable feature. The transfer-then-spin strategy can be employed to fabricate patterned CNT arrays, which can act as 3-dimensional electrodes in CNT thermoacoustic chips. Besides, the flip-chipped CNTs are promising field electron emitters. Furthermore, the ice-assisted transfer technique provides a cost-effective solution for mass production of SACNTs, giving CNT technologies a competitive edge, and this method may inspire new ways to transfer other nanomaterials.

X-ray metrology of an array of active edge pixel sensors for use at synchrotron light sources

NASA Astrophysics Data System (ADS)

Plackett, R.; Arndt, K.; Bortoletto, D.; Horswell, I.; Lockwood, G.; Shipsey, I.; Tartoni, N.; Williams, S.

2018-01-01

We report on the production and testing of an array of active edge silicon sensors as a prototype of a large array. Four Medipix3RX.1 chips were bump bonded to four single chip sized Advacam active edge n-on-n sensors. These detectors were then mounted into a 2 by 2 array and tested on B16 at Diamond Light Source with an x-ray beam spot of 2um. The results from these tests, compared with optical metrology demonstrate that this type of sensor is sensitive to the physical edge of the silicon, with only a modest loss of efficiency in the final two rows of pixels. We present the efficiency maps recorded with the microfocus beam and a sample powder diffraction measurement. These results give confidence that this sensor technology can be used effectively in larger arrays of detectors at synchrotron light sources.

Fabrication of arrayed Si nanowire-based nano-floating gate memory devices on flexible plastics.

PubMed

Yoon, Changjoon; Jeon, Youngin; Yun, Junggwon; Kim, Sangsig

2012-01-01

Arrayed Si nanowire (NW)-based nano-floating gate memory (NFGM) devices with Pt nanoparticles (NPs) embedded in Al2O3 gate layers are successfully constructed on flexible plastics by top-down approaches. Ten arrayed Si NW-based NFGM devices are positioned on the first level. Cross-linked poly-4-vinylphenol (PVP) layers are spin-coated on them as isolation layers between the first and second level, and another ten devices are stacked on the cross-linked PVP isolation layers. The electrical characteristics of the representative Si NW-based NFGM devices on the first and second levels exhibit threshold voltage shifts, indicating the trapping and detrapping of electrons in their NPs nodes. They have an average threshold voltage shift of 2.5 V with good retention times of more than 5 x 10(4) s. Moreover, most of the devices successfully retain their electrical characteristics after about one thousand bending cycles. These well-arrayed and stacked Si NW-based NFGM devices demonstrate the potential of nanowire-based devices for large-scale integration.

Evaluation of the thermal conductance of flip-chip bonding structure utilizing the measurement based on Fourier's law of heat conduction at steady-state

NASA Astrophysics Data System (ADS)

Wu, Chia-Yu; Huang, Yin-Hsien; Wu, Hsin-Han; Hsieh, Tsung-Eong

2018-06-01

Fourier's law of heat conduction at steady-state was adopted to establish a measurement method utilizing platinum (Pt) thin-film electrodes as the heater and the temperature sensor. The thermal conductivities (κ's) of Pyrex glass, an epoxy resin and a commercial underfill for flip-chip devices were measured and a good agreement with previously reported values was obtained. The thermal boundary resistances (RTBR's) of Pt/sample interfaces were also extracted for discussing their influence on the thermal conduction of samples. Afterward, the flip-chip samples with 2×2 solder joint array utilizing Si wafers as the die and the substrate, without and with the underfills, were prepared and their thermal conductance were measured. For the sample without underfill, the air presenting in the gap of die and the substrate led to the poor thermal conductance of sample. With the insertion of underfills, the thermal conductance of flip-chip samples improved. The resistance to heat transfer across Si/underfill interfaces was also suppressed and to promote the thermal conductance of samples. The thermal properties of underfill and RTBR at Si/underfill interface were further implanted in the calculation of thermal conductance of flip-chip samples containing various solder joint arrays. The increasing number of solder joints diminished the influence of thermal conduction of underfill and RTBR of Si/underfill interface on the thermal conductance of samples. The insertion of underfill with high-κ value might promote the heat conductance of samples containing low-density solder joint arrays; however, it became insignificant in improving the heat conductance of samples containing high-density solder joint arrays.

Single-bead arrays for fluorescence-based immunoassays on capillary-driven microfluidic chips

NASA Astrophysics Data System (ADS)

Temiz, Yuksel; Lim, Michel; Delamarche, Emmanuel

2016-03-01

We report a concept for the simple fabrication of easy-to-use chips for immunoassays in the context of point-of-care diagnostics. The chip concept comprises mainly three features: (1) the efficient integration of reagents using beads functionalized with receptors, (2) the generation of capillary-driven liquid flows without using external pumps, and (3) a high-sensitivity detection of analytes using fluorescence microscopy. We fabricated prototype chips using dry etching of Si wafers. 4.5-μm-diameter beads were integrated into hexagonal arrays by sedimentation and removing the excess using a stream of water. We studied the effect of different parameters and showed that array occupancies from 30% to 50% can be achieved by pipetting a 250 nL droplet of 1% bead solution and allowing the beads sediment for 3 min. Chips with integrated beads were sealed using a 50-μm-thick dry-film resist laminated at 45 °C. Liquids pipetted to loading pads were autonomously pulled by capillary pumps at a rate of 0.35 nL s-1 for about 30 min. We studied ligand-receptor interactions and binding kinetics using time-lapse fluorescence microscopy and demonstrated a 5 pM limit of detection (LOD) for an anti-biotin immunoassay. As a clinically-relevant example, we implemented an immunoassay to detect prostate specific antigen (PSA) and showed an LOD of 108 fM (i.e. 3.6 pg mL-1). While a specific implementation is provided here for the detection of PSA, we believe that combining capillary-driven microfluidics with arrays of single beads and fluorescence readout to be very flexible and sufficiently sensitive for the detection of other clinically-relevant analytes.

[Detection of transgenic crop with gene chip].

PubMed

Huang, Ying-Chun; Sun, Chun-Yun; Feng, Hong; Hu, Xiao-Dong; Yin, Hai-Bin

2003-05-01

Some selected available sequences of reporter genes,resistant genes, promoters and terminators are amplified by PCR for the probes of transgenic crop detection gene chip. These probes are arrayed at definite density and printed on the surface of amino-slides by bioRobot MicroGrid II. Results showed that gene chip worked quickly and correctly, when transgenic rice, pawpaw,maize and soybean were applied.

Invited Article: Terahertz microfluidic chips sensitivity-enhanced with a few arrays of meta-atoms

NASA Astrophysics Data System (ADS)

Serita, Kazunori; Matsuda, Eiki; Okada, Kosuke; Murakami, Hironaru; Kawayama, Iwao; Tonouchi, Masayoshi

2018-05-01

We present a nonlinear optical crystal (NLOC)-based terahertz (THz) microfluidic chip with a few arrays of split ring resonators (SRRs) for ultra-trace and quantitative measurements of liquid solutions. The proposed chip operates on the basis of near-field coupling between the SRRs and a local emission of point like THz source that is generated in the process of optical rectification in NLOCs on a sub-wavelength scale. The liquid solutions flowing inside the microchannel modify the resonance frequency and peak attenuation in the THz transmission spectra. In contrast to conventional bio-sensing with far/near-field THz waves, our technique can be expected to compactify the chip design as well as realize high sensitive near-field measurement of liquid solutions without any high-power optical/THz source, near-field probes, and prisms. Using this chip, we have succeeded in observing the 31.8 fmol of ion concentration in actual amount of 318 pl water solutions from the shift of the resonance frequency. The technique opens the door to microanalysis of biological samples with THz waves and accelerates development of THz lab-on-chip devices.

Two-qubit gates and coupling with low-impedance flux qubits

NASA Astrophysics Data System (ADS)

Chow, Jerry; Corcoles, Antonio; Rigetti, Chad; Rozen, Jim; Keefe, George; Rothwell, Mary-Beth; Rohrs, John; Borstelmann, Mark; Divincenzo, David; Ketchen, Mark; Steffen, Matthias

2011-03-01

We experimentally demonstrate the coupling of two low-impedance flux qubits mediated via a transmission line resonator. We explore the viability of experimental coupling protocols which involve selective microwave driving on the qubits independently as well as fast frequency tuning through on-chip flux-bias. Pulse-shaping techniques for single-qubit and two-qubit gates are employed for reducing unwanted leakage and phase errors. A joint readout through the transmission line resonator is used for characterizing single-qubit and two-qubit states.

Preparation of a Superhydrophobic and Peroxidase-like Activity Array Chip for H2O2 Sensing by Surface-Enhanced Raman Scattering.

PubMed

Yu, Zhi; Park, Yeonju; Chen, Lei; Zhao, Bing; Jung, Young Mee; Cong, Qian

2015-10-28

In this paper, we propose a novel and simple method for preparing a dual-biomimetic functional array possessing both superhydrophobic and peroxidase-like activity that can be used for hydrogen peroxide (H2O2) sensing. The proposed method is an integration innovation that combines the above two properties and surface-enhanced Raman scattering (SERS). We integrated a series of well-ordered arrays of Au points (d = 1 mm) onto a superhydrophobic copper (Cu)/silver (Ag) surface by replicating an arrayed molybdenum template. Instead of using photoresists and the traditional lithography method, we utilized a chemical etching method (a substitution reaction between Cu and HAuCl4) with a Cu/Ag superhydrophobic surface as the barrier layer, which has the benefit of water repellency. The as-prepared Au points were observed to possess peroxidase-like activity, allowing for catalytic oxidation of the chromogenic molecule o-phenylenediamine dihydrochloride (OPD). Oxidation was evidenced by a color change in the presence of H2O2, which allows the array chip to act as an H2O2 sensor. In this study, the water repellency of the superhydrophobic surface was used to fabricate the array chip and increase the local reactant concentration during the catalytic reaction. As a result, the catalytic reaction occurred when only 2 μL of an aqueous sample (OPD/H2O2) was placed onto the Au point, and the enzymatic product, 2,3-diaminophenazine, showed a SERS signal distinguishable from that of OPD after mixing with 2 μL of colloidal Au. Using the dual-biomimetic functional array chip, quantitative analysis of H2O2 was performed by observing the change in the SERS spectra, which showed a concentration-dependent behavior for H2O2. This method allows for the detection of H2O2 at concentrations as low as 3 pmol per 2 μL of sample, which is a considerable advantage in H2O2 analysis. The as-prepared substrate was convenient for H2O2 detection because only a small amount of sample was required in each analysis. Highly sensitive detection was realized using SERS. Therefore, this chip was shown to exhibit significant potential for applications in bioanalysis.

Semantically Aware Foundation Environment (SAFE) for Clean-Slate Design of Resilient, Adaptive Secure Hosts (CRASH)

DTIC Science & Technology

2016-02-01

system consists of a high-fidelity hardware simulation using field programmable gate arrays (FPGAs), with a set of runtime services (ConcreteWare...perimeter protection, patch, and pray” is not aligned with the threat. Programmers will not bail us out of this situation (by writing defect free code...hosted on a Field Programmable Gate Array (FPGA), with a set of runtime services (concreteware) running on the hardware. Secure applications can be

Single-Event Effect (SEE) Survey of Advanced Reconfigurable Field Programmable Gate Arrays: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

NASA Technical Reports Server (NTRS)

Allen, Gregory

2011-01-01

The NEPP Reconfigurable Field-Programmable Gate Array (FPGA) task has been charged to evaluate reconfigurable FPGA technologies for use in space. Under this task, the Xilinx single-event-immune, reconfigurable FPGA (SIRF) XQR5VFX130 device was evaluated for SEE. Additionally, the Altera Stratix-IV and SiliconBlue iCE65 were screened for single-event latchup (SEL).

Implementing a Microcontroller Watchdog with a Field-Programmable Gate Array (FPGA)

NASA Technical Reports Server (NTRS)

Straka, Bartholomew

2013-01-01

Reliability is crucial to safety. Redundancy of important system components greatly enhances reliability and hence safety. Field-Programmable Gate Arrays (FPGAs) are useful for monitoring systems and handling the logic necessary to keep them running with minimal interruption when individual components fail. A complete microcontroller watchdog with logic for failure handling can be implemented in a hardware description language (HDL.). HDL-based designs are vendor-independent and can be used on many FPGAs with low overhead.

Plastic fiber scintillator response to fast neutrons

NASA Astrophysics Data System (ADS)

Danly, C. R.; Sjue, S.; Wilde, C. H.; Merrill, F. E.; Haight, R. C.

2014-11-01

The Neutron Imaging System at NIF uses an array of plastic scintillator fibers in conjunction with a time-gated imaging system to form an image of the neutron emission from the imploded capsule. By gating on neutrons that have scattered from the 14.1 MeV DT energy to lower energy ranges, an image of the dense, cold fuel around the hotspot is also obtained. An unmoderated spallation neutron beamline at the Weapons Neutron Research facility at Los Alamos was used in conjunction with a time-gated imaging system to measure the yield of a scintillating fiber array over several energy bands ranging from 1 to 15 MeV. The results and comparison to simulation are presented.

Plastic fiber scintillator response to fast neutrons.

PubMed

Danly, C R; Sjue, S; Wilde, C H; Merrill, F E; Haight, R C

2014-11-01

The Neutron Imaging System at NIF uses an array of plastic scintillator fibers in conjunction with a time-gated imaging system to form an image of the neutron emission from the imploded capsule. By gating on neutrons that have scattered from the 14.1 MeV DT energy to lower energy ranges, an image of the dense, cold fuel around the hotspot is also obtained. An unmoderated spallation neutron beamline at the Weapons Neutron Research facility at Los Alamos was used in conjunction with a time-gated imaging system to measure the yield of a scintillating fiber array over several energy bands ranging from 1 to 15 MeV. The results and comparison to simulation are presented.

Field programmable gate arrays: Evaluation report for space-flight application

NASA Technical Reports Server (NTRS)

Sandoe, Mike; Davarpanah, Mike; Soliman, Kamal; Suszko, Steven; Mackey, Susan

1992-01-01

Field Programmable Gate Arrays commonly called FPGA's are the newer generation of field programmable devices and offer more flexibility in the logic modules they incorporate and in how they are interconnected. The flexibility, the number of logic building blocks available, and the high gate densities achievable are why users find FPGA's attractive. These attributes are important in reducing product development costs and shortening the development cycle. The aerospace community is interested in incorporating this new generation of field programmable technology in space applications. To this end, a consortium was formed to evaluate the quality, reliability, and radiation performance of FPGA's. This report presents the test results on FPGA parts provided by ACTEL Corporation.

Toward Evolvable Hardware Chips: Experiments with a Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Stoica, Adrian

1998-01-01

Evolvable Hardware is reconfigurable hardware that self-configures under the control of an evolutionary algorithm. We search for a hardware configuration can be performed using software models or, faster and more accurate, directly in reconfigurable hardware. Several experiments have demonstrated the possibility to automatically synthesize both digital and analog circuits. The paper introduces an approach to automated synthesis of CMOS circuits, based on evolution on a Programmable Transistor Array (PTA). The approach is illustrated with a software experiment showing evolutionary synthesis of a circuit with a desired DC characteristic. A hardware implementation of a test PTA chip is then described, and the same evolutionary experiment is performed on the chip demonstrating circuit synthesis/self-configuration directly in hardware.

Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

NASA Astrophysics Data System (ADS)

Marmon, Jason; Rai, Satish; Wang, Kai; Zhou, Weilie; Zhang, Yong

2016-03-01

Modern electronics are developing electronic-optical integrated circuits, while their electronic backbone, e.g. field-effect transistors (FETs), remains the same. However, further FET down scaling is facing physical and technical challenges. A light-effect transistor (LET) offers electronic-optical hybridization at the component level, which can continue Moore’s law to quantum region without requiring a FET’s fabrication complexity, e.g. physical gate and doping, by employing optical gating and photoconductivity. Multiple independent gates are therefore readily realized to achieve unique functionalities without increasing chip space. Here we report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs show output and transfer characteristics resembling advanced FETs, e.g. on/off ratios up to ~1.0x106 with a source-drain voltage of ~1.43 V, gate-power of ~260 nW, and subthreshold swing of ~0.3 nW/decade (excluding losses). Our work offers new electronic-optical integration strategies and electronic and optical computing approaches.

Rapidly reconfigurable all-optical universal logic gate

DOEpatents

Goddard, Lynford L.; Bond, Tiziana C.; Kallman, Jeffrey S.

2010-09-07

A new reconfigurable cascadable all-optical on-chip device is presented. The gate operates by combining the Vernier effect with a novel effect, the gain-index lever, to help shift the dominant lasing mode from a mode where the laser light is output at one facet to a mode where it is output at the other facet. Since the laser remains above threshold, the speed of the gate for logic operations as well as for reprogramming the function of the gate is primarily limited to the small signal optical modulation speed of the laser, which can be on the order of up to about tens of GHz. The gate can be rapidly and repeatedly reprogrammed to perform any of the basic digital logic operations by using an appropriate analog optical or electrical signal at the gate selection port. Other all-optical functionality includes wavelength conversion, signal duplication, threshold switching, analog to digital conversion, digital to analog conversion, signal routing, and environment sensing. Since each gate can perform different operations, the functionality of such a cascaded circuit grows exponentially.

Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip

NASA Astrophysics Data System (ADS)

Jara Casas, L. M.; Ceresa, D.; Kulis, S.; Miryala, S.; Christiansen, J.; Francisco, R.; Gnani, D.

2017-02-01

A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (<1 Grad) and Single Event Upset (SEU) on digital logic gates in a 65 nm CMOS technology. Nine different versions of standard cell libraries are studied in this chip, basically differing in the device dimensions, Vt flavor and layout of the device. Each library has eighteen test structures specifically designed to characterize delay degradation and power consumption of the standard cells. For SEU study, a dedicated test structure based on a shift register is designed for each library. TID results up to 500 Mrad are reported.

Scalable, efficient ASICS for the square kilometre array: From A/D conversion to central correlation

NASA Astrophysics Data System (ADS)

Schmatz, M. L.; Jongerius, R.; Dittmann, G.; Anghel, A.; Engbersen, T.; van Lunteren, J.; Buchmann, P.

2014-05-01

The Square Kilometre Array (SKA) is a future radio telescope, currently being designed by the worldwide radio-astronomy community. During the first of two construction phases, more than 250,000 antennas will be deployed, clustered in aperture-array stations. The antennas will generate 2.5 Pb/s of data, which needs to be processed in real time. For the processing stages from A/D conversion to central correlation, we propose an ASIC solution using only three chip architectures. The architecture is scalable - additional chips support additional antennas or beams - and versatile - it can relocate its receiver band within a range of a few MHz up to 4GHz. This flexibility makes it applicable to both SKA phases 1 and 2. The proposed chips implement an antenna and station processor for 289 antennas with a power consumption on the order of 600W and a correlator, including corner turn, for 911 stations on the order of 90 kW.

Demonstration of Compact and Low-Loss Athermal Arrayed-Waveguide Grating Module Based on 2.5%-Δ Silica-Based Waveguides

NASA Astrophysics Data System (ADS)

Maru, Koichi; Abe, Yukio; Uetsuka, Hisato

2008-10-01

We demonstrated a compact and low-loss athermal arrayed-waveguide grating (AWG) module utilizing silica-based planar lightwave circuit (PLC) technology. Spot-size converters based on a vertical ridge-waveguide taper were integrated with a 2.5%-Δ athermal AWG to reduce the loss at chip-to-fiber interface. Spot-size converters based on a segmented core were formed around resin-filled trenches for athermalization formed in the slab to reduce the diffraction loss at the trenches. A 16-channel athermal AWG module with 100-GHz channel spacing was fabricated. The use of a 2.5%-Δ athermal chip with a single-side fiber array enabled a compact package of the size of 41.6×16.6×4.5 mm3. Athermal characteristics and a small insertion loss of 3.5-3.8 dB were obtained by virtue of low fiber-to-chip coupling loss and athermalization with low excess loss.

Holographic pixel super-resolution in portable lensless on-chip microscopy using a fiber-optic array.

PubMed

Bishara, Waheb; Sikora, Uzair; Mudanyali, Onur; Su, Ting-Wei; Yaglidere, Oguzhan; Luckhart, Shirley; Ozcan, Aydogan

2011-04-07

We report a portable lensless on-chip microscope that can achieve <1 µm resolution over a wide field-of-view of ∼ 24 mm(2) without the use of any mechanical scanning. This compact on-chip microscope weighs ∼ 95 g and is based on partially coherent digital in-line holography. Multiple fiber-optic waveguides are butt-coupled to light emitting diodes, which are controlled by a low-cost micro-controller to sequentially illuminate the sample. The resulting lensfree holograms are then captured by a digital sensor-array and are rapidly processed using a pixel super-resolution algorithm to generate much higher resolution holographic images (both phase and amplitude) of the objects. This wide-field and high-resolution on-chip microscope, being compact and light-weight, would be important for global health problems such as diagnosis of infectious diseases in remote locations. Toward this end, we validate the performance of this field-portable microscope by imaging human malaria parasites (Plasmodium falciparum) in thin blood smears. Our results constitute the first-time that a lensfree on-chip microscope has successfully imaged malaria parasites.

Fundamental Problems of Hybrid CMOS/Nanodevice Circuits

DTIC Science & Technology

2010-12-14

Development of an area-distributed CMOS/nanodevice interface We have carried out the first design of CMOS chips for the CMOS/nanodevice integration, and...got them fabricated in IBM’ 180-nm 7RF process (via MOSIS, Inc. silicon foundry). Each 44 mm2 chip assembly of the design consists of 4 component... chips , merged together for processing convenience. Each 22 mm2 component chip features two interface arrays, with 1010 vias each, with chip’s MOSFETs

Nitride micro-LEDs and beyond--a decade progress review.

PubMed

Jiang, H X; Lin, J Y

2013-05-06

Since their inception, micro-size light emitting diode (µLED) arrays based on III-nitride semiconductors have emerged as a promising technology for a range of applications. This paper provides an overview on a decade progresses on realizing III-nitride µLED based high voltage single-chip AC/DC-LEDs without power converters to address the key compatibility issue between LEDs and AC power grid infrastructure; and high-resolution solid-state self-emissive microdisplays operating in an active driving scheme to address the need of high brightness, efficiency and robustness of microdisplays. These devices utilize the photonic integration approach by integrating µLED arrays on-chip. Other applications of nitride µLED arrays are also discussed.

Titanium dioxide nanowire sensor array integration on CMOS platform using deterministic assembly.

PubMed

Gall, Oren Z; Zhong, Xiahua; Schulman, Daniel S; Kang, Myungkoo; Razavieh, Ali; Mayer, Theresa S

2017-06-30

Nanosensor arrays have recently received significant attention due to their utility in a wide range of applications, including gas sensing, fuel cells, internet of things, and portable health monitoring systems. Less attention has been given to the production of sensor platforms in the μW range for ultra-low power applications. Here, we discuss how to scale the nanosensor energy demand by developing a process for integration of nanowire sensing arrays on a monolithic CMOS chip. This work demonstrates an off-chip nanowire fabrication method; subsequently nanowires link to a fused SiO 2 substrate using electric-field assisted directed assembly. The nanowire resistances shown in this work have the highest resistance uniformity reported to date of 18%, which enables a practical roadmap towards the coupling of nanosensors to CMOS circuits and signal processing systems. The article also presents the utility of optimizing annealing conditions of the off-chip metal-oxides prior to CMOS integration to avoid limitations of thermal budget and process incompatibility. In the context of the platform demonstrated here, directed assembly is a powerful tool that can realize highly uniform, cross-reactive arrays of different types of metal-oxide nanosensors suited for gas discrimination and signal processing systems.

Titanium dioxide nanowire sensor array integration on CMOS platform using deterministic assembly

NASA Astrophysics Data System (ADS)

Gall, Oren Z.; Zhong, Xiahua; Schulman, Daniel S.; Kang, Myungkoo; Razavieh, Ali; Mayer, Theresa S.

2017-06-01

Nanosensor arrays have recently received significant attention due to their utility in a wide range of applications, including gas sensing, fuel cells, internet of things, and portable health monitoring systems. Less attention has been given to the production of sensor platforms in the μW range for ultra-low power applications. Here, we discuss how to scale the nanosensor energy demand by developing a process for integration of nanowire sensing arrays on a monolithic CMOS chip. This work demonstrates an off-chip nanowire fabrication method; subsequently nanowires link to a fused SiO2 substrate using electric-field assisted directed assembly. The nanowire resistances shown in this work have the highest resistance uniformity reported to date of 18%, which enables a practical roadmap towards the coupling of nanosensors to CMOS circuits and signal processing systems. The article also presents the utility of optimizing annealing conditions of the off-chip metal-oxides prior to CMOS integration to avoid limitations of thermal budget and process incompatibility. In the context of the platform demonstrated here, directed assembly is a powerful tool that can realize highly uniform, cross-reactive arrays of different types of metal-oxide nanosensors suited for gas discrimination and signal processing systems.

Gold patterned biochips for on-chip immuno-MALDI-TOF MS: SPR imaging coupled multi-protein MS analysis.

PubMed

Kim, Young Eun; Yi, So Yeon; Lee, Chang-Soo; Jung, Yongwon; Chung, Bong Hyun

2012-01-21

Matrix-assisted laser desorption/ionization time-of-flight mass spectrometry (MALDI-TOF-MS) analysis of immuno-captured target protein efficiently complements conventional immunoassays by offering rich molecular information such as protein isoforms or modifications. Direct immobilization of antibodies on MALDI solid support enables both target enrichment and MS analysis on the same plate, allowing simplified and potentially multiplexing protein MS analysis. Reliable on-chip immuno-MALDI-TOF MS for multiple biomarkers requires successful adaptation of antibody array biochips, which also must accommodate consistent reaction conditions on antibody arrays during immuno-capture and MS analysis. Here we developed a facile fabrication process of versatile antibody array biochips for reliable on-chip MALDI-TOF-MS analysis of multiple immuno-captured proteins. Hydrophilic gold arrays surrounded by super-hydrophobic surfaces were formed on a gold patterned biochip via spontaneous chemical or protein layer deposition. From antibody immobilization to MALDI matrix treatment, this hydrophilic/phobic pattern allowed highly consistent surface reactions on each gold spot. Various antibodies were immobilized on these gold spots both by covalent coupling or protein G binding. Four different protein markers were successfully analyzed on the present immuno-MALDI biochip from complex protein mixtures including serum samples. Tryptic digests of captured PSA protein were also effectively detected by on-chip MALDI-TOF-MS. Moreover, the present MALDI biochip can be directly applied to the SPR imaging system, by which antibody and subsequent antigen immobilization were successfully monitored.

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2011-01-01

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

Vertical integration of array-type miniature interferometers at wafer level by using multistack anodic bonding

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Wiemer, Maik; Froemel, Joerg; Enderlein, Tom; Gessner, Thomas; Lullin, Justine; Bargiel, Sylwester; Passilly, Nicolas; Albero, Jorge; Gorecki, Christophe

2016-04-01

In this work, vertical integration of miniaturized array-type Mirau interferometers at wafer level by using multi-stack anodic bonding is presented. Mirau interferometer is suitable for MEMS metrology and for medical imaging according to its vertical-, lateral- resolutions and working distances. Miniaturized Mirau interferometer can be a promising candidate as a key component of an optical coherence tomography (OCT) system. The miniaturized array-type interferometer consists of a microlens doublet, a Si-based MEMS Z scanner, a spacer for focus-adjustment and a beam splitter. Therefore, bonding technologies which are suitable for heterogeneous substrates are of high interest and necessary for the integration of MEMS/MOEMS devices. Multi-stack anodic bonding, which meets the optical and mechanical requirements of the MOEMS device, is adopted to integrate the array-type interferometers. First, the spacer and the beam splitter are bonded, followed by bonding of the MEMS Z scanner. In the meanwhile, two microlenses, which are composed of Si and glass wafers, are anodically bonded to form a microlens doublet. Then, the microlens doublet is aligned and bonded with the scanner/spacer/beam splitter stack. The bonded array-type interferometer is a 7- wafer stack and the thickness is approximately 5mm. To separate such a thick wafer stack with various substrates, 2-step laser cutting is used to dice the bonded stack into Mirau chips. To simplify fabrication process of each component, electrical connections are created at the last step by mounting a Mirau chip onto a flip chip PCB instead of through wafer vias. Stability of Au/Ti films on the MEMS Z scanner after anodic bonding, laser cutting and flip chip bonding are discussed as well.

Parallel Transport Quantum Logic Gates with Trapped Ions.

PubMed

de Clercq, Ludwig E; Lo, Hsiang-Yu; Marinelli, Matteo; Nadlinger, David; Oswald, Robin; Negnevitsky, Vlad; Kienzler, Daniel; Keitch, Ben; Home, Jonathan P

2016-02-26

We demonstrate single-qubit operations by transporting a beryllium ion with a controlled velocity through a stationary laser beam. We use these to perform coherent sequences of quantum operations, and to perform parallel quantum logic gates on two ions in different processing zones of a multiplexed ion trap chip using a single recycled laser beam. For the latter, we demonstrate individually addressed single-qubit gates by local control of the speed of each ion. The fidelities we observe are consistent with operations performed using standard methods involving static ions and pulsed laser fields. This work therefore provides a path to scalable ion trap quantum computing with reduced requirements on the optical control complexity.

Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

NASA Astrophysics Data System (ADS)

Park, Hyeonwoo; Teramoto, Akinobu; Kuroda, Rihito; Suwa, Tomoyuki; Sugawa, Shigetoshi

2018-04-01

Localized stress-induced leakage current (SILC) has become a major problem in the reliability of flash memories. To reduce it, clarifying the SILC mechanism is important, and statistical measurement and analysis have to be carried out. In this study, we applied an array test circuit that can measure the SILC distribution of more than 80,000 nMOSFETs with various gate areas at a high speed (within 80 s) and a high accuracy (on the 10-17 A current order). The results clarified that the distributions of localized SILC in different gate areas follow a universal distribution assuming the same SILC defect density distribution per unit area, and the current of localized SILC defects does not scale down with the gate area. Moreover, the distribution of SILC defect density and its dependence on the oxide field for measurement (E OX-Measure) were experimentally determined for fabricated devices.

A 400 KHz line rate 2048-pixel stitched SWIR linear array

NASA Astrophysics Data System (ADS)

Anchlia, Ankur; Vinella, Rosa M.; Gielen, Daphne; Wouters, Kristof; Vervenne, Vincent; Hooylaerts, Peter; Deroo, Pieter; Ruythooren, Wouter; De Gaspari, Danny; Das, Jo; Merken, Patrick

2016-05-01

Xenics has developed a family of stitched SWIR long linear arrays that operate up to 400 KHz of line rate. These arrays serve medical and industrial applications that require high line rates as well as space applications that require long linear arrays. The arrays are based on a modular ROIC design concept: modules of 512 pixels are stitched during fabrication to achieve 512, 1024 and 2048 pixel arrays. Each 512-pixel module has its own on-chip digital sequencer, analog readout chain and 4 output buffers. This modular concept enables a long array to run at a high line rates irrespective of the array length, which limits the line rate in a traditional linear array. The ROIC is flip-chipped with InGaAs detector arrays. The FPA has a pixel pitch of 12.5μm and has two pixel flavors: square (12.5μm) and rectangular (250μm). The frontend circuit is based on Capacitive Trans-impedance Amplifier (CTIA) to attain stable detector bias, and good linearity and signal integrity, especially at high speeds. The CTIA has an input auto-zero mechanism that allows to have low detector bias (<20mV). An on-chip Correlated Double Sample (CDS) facilitates removal of CTIA KTC and 1/f noise, and other offsets, achieving low noise performance. There are five gain modes in the FPA giving the full well range from 85Ke- to 40Me-. The measured input referred noise is 35e-rms in the highest gain mode. The FPA operates in Integrate While Read mode and, at a master clock rate of 60MHz and a minimum integration time of 1.4μs, achieves the highest line rate of 400 KHz. In this paper, design details and measurements results are presented in order to demonstrate the array performance.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baart, T. A.; Vandersypen, L. M. K.; Kavli Institute of Nanoscience, Delft University of Technology, P.O. Box 5046, 2600 GA Delft

We report the computer-automated tuning of gate-defined semiconductor double quantum dots in GaAs heterostructures. We benchmark the algorithm by creating three double quantum dots inside a linear array of four quantum dots. The algorithm sets the correct gate voltages for all the gates to tune the double quantum dots into the single-electron regime. The algorithm only requires (1) prior knowledge of the gate design and (2) the pinch-off value of the single gate T that is shared by all the quantum dots. This work significantly alleviates the user effort required to tune multiple quantum dot devices.

One GigaSample Per Second Data Acquisition using Available Gate Array Technology

NASA Technical Reports Server (NTRS)

Wagner, K.W.

1999-01-01

A new National Aeronautics and Space Administration instrument forced demanding requirements upon its altimeter digitizer system. Eight-bit data would be generated at a rate of one billion samples per second. NASA had never before attempted to capture such high-speed data in the radiation, low-power, no-convective-cooling, limited-board-area environment of space. This presentation describes how the gate array technology available at the time of the design was used to implement this one gigasample per second data acquisition system

Single Event Test Methodologies and System Error Rate Analysis for Triple Modular Redundant Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Allen, Gregory; Edmonds, Larry D.; Swift, Gary; Carmichael, Carl; Tseng, Chen Wei; Heldt, Kevin; Anderson, Scott Arlo; Coe, Michael

2010-01-01

We present a test methodology for estimating system error rates of Field Programmable Gate Arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilins Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.

Detection of Bioaerosols Using Single Particle Thermal Emission Spectroscopy (First-year Report)

DTIC Science & Technology

2012-02-01

cooled MCT detector with a noise equivalent power (NEP) of 7x10(–13) W/Hz, yields a detection S/N > 13 (assuming a sufficiently cooled background). We...dispersively resolved using 190-mm Horiba spectrometer that houses a time-gated 32-element mercury cadmium telluride ( MCT ) linear array. In this report...to 10.0 ms. Minimum integration (and readout) periods for the time-gated 32-element mercury cadmium telluride ( MCT ) linear array are 10 µs. Based

A novel high electrode count spike recording array using an 81,920 pixel transimpedance amplifier-based imaging chip.

PubMed

Johnson, Lee J; Cohen, Ethan; Ilg, Doug; Klein, Richard; Skeath, Perry; Scribner, Dean A

2012-04-15

Microelectrode recording arrays of 60-100 electrodes are commonly used to record neuronal biopotentials, and these have aided our understanding of brain function, development and pathology. However, higher density microelectrode recording arrays of larger area are needed to study neuronal function over broader brain regions such as in cerebral cortex or hippocampal slices. Here, we present a novel design of a high electrode count picocurrent imaging array (PIA), based on an 81,920 pixel Indigo ISC9809 readout integrated circuit camera chip. While originally developed for interfacing to infrared photodetector arrays, we have adapted the chip for neuron recording by bonding it to microwire glass resulting in an array with an inter-electrode pixel spacing of 30 μm. In a high density electrode array, the ability to selectively record neural regions at high speed and with good signal to noise ratio are both functionally important. A critical feature of our PIA is that each pixel contains a dedicated low noise transimpedance amplifier (∼0.32 pA rms) which allows recording high signal to noise ratio biocurrents comparable to single electrode voltage amplifier recordings. Using selective sampling of 256 pixel subarray regions, we recorded the extracellular biocurrents of rabbit retinal ganglion cell spikes at sampling rates up to 7.2 kHz. Full array local electroretinogram currents could also be recorded at frame rates up to 100 Hz. A PIA with a full complement of 4 readout circuits would span 1cm and could acquire simultaneous data from selected regions of 1024 electrodes at sampling rates up to 9.3 kHz. Published by Elsevier B.V.

A customized metal oxide semiconductor-based gas sensor array for onion quality evaluation: system development and characterization.

PubMed

Konduru, Tharun; Rains, Glen C; Li, Changying

2015-01-12

A gas sensor array, consisting of seven Metal Oxide Semiconductor (MOS) sensors that are sensitive to a wide range of organic volatile compounds was developed to detect rotten onions during storage. These MOS sensors were enclosed in a specially designed Teflon chamber equipped with a gas delivery system to pump volatiles from the onion samples into the chamber. The electronic circuit mainly comprised a microcontroller, non-volatile memory chip, and trickle-charge real time clock chip, serial communication chip, and parallel LCD panel. User preferences are communicated with the on-board microcontroller through a graphical user interface developed using LabVIEW. The developed gas sensor array was characterized and the discrimination potential was tested by exposing it to three different concentrations of acetone (ketone), acetonitrile (nitrile), ethyl acetate (ester), and ethanol (alcohol). The gas sensor array could differentiate the four chemicals of same concentrations and different concentrations within the chemical with significant difference. Experiment results also showed that the system was able to discriminate two concentrations (196 and 1964 ppm) of methlypropyl sulfide and two concentrations (145 and 1452 ppm) of 2-nonanone, two key volatile compounds emitted by rotten onions. As a proof of concept, the gas sensor array was able to achieve 89% correct classification of sour skin infected onions. The customized low-cost gas sensor array could be a useful tool to detect onion postharvest diseases in storage.

A Customized Metal Oxide Semiconductor-Based Gas Sensor Array for Onion Quality Evaluation: System Development and Characterization

PubMed Central

Konduru, Tharun; Rains, Glen C.; Li, Changying

2015-01-01

A gas sensor array, consisting of seven Metal Oxide Semiconductor (MOS) sensors that are sensitive to a wide range of organic volatile compounds was developed to detect rotten onions during storage. These MOS sensors were enclosed in a specially designed Teflon chamber equipped with a gas delivery system to pump volatiles from the onion samples into the chamber. The electronic circuit mainly comprised a microcontroller, non-volatile memory chip, and trickle-charge real time clock chip, serial communication chip, and parallel LCD panel. User preferences are communicated with the on-board microcontroller through a graphical user interface developed using LabVIEW. The developed gas sensor array was characterized and the discrimination potential was tested by exposing it to three different concentrations of acetone (ketone), acetonitrile (nitrile), ethyl acetate (ester), and ethanol (alcohol). The gas sensor array could differentiate the four chemicals of same concentrations and different concentrations within the chemical with significant difference. Experiment results also showed that the system was able to discriminate two concentrations (196 and 1964 ppm) of methlypropyl sulfide and two concentrations (145 and 1452 ppm) of 2-nonanone, two key volatile compounds emitted by rotten onions. As a proof of concept, the gas sensor array was able to achieve 89% correct classification of sour skin infected onions. The customized low-cost gas sensor array could be a useful tool to detect onion postharvest diseases in storage. PMID:25587975

Design and implementation of digital controllers for smart structures using field-programmable gate arrays

NASA Astrophysics Data System (ADS)

Kelly, Jamie S.; Bowman, Hiroshi C.; Rao, Vittal S.; Pottinger, Hardy J.

1997-06-01

Implementation issues represent an unfamiliar challenge to most control engineers, and many techniques for controller design ignore these issues outright. Consequently, the design of controllers for smart structural systems usually proceeds without regard for their eventual implementation, thus resulting either in serious performance degradation or in hardware requirements that squander power, complicate integration, and drive up cost. The level of integration assumed by the Smart Patch further exacerbates these difficulties, and any design inefficiency may render the realization of a single-package sensor-controller-actuator system infeasible. The goal of this research is to automate the controller implementation process and to relieve the design engineer of implementation concerns like quantization, computational efficiency, and device selection. We specifically target Field Programmable Gate Arrays (FPGAs) as our hardware platform because these devices are highly flexible, power efficient, and reprogrammable. The current study develops an automated implementation sequence that minimizes hardware requirements while maintaining controller performance. Beginning with a state space representation of the controller, the sequence automatically generates a configuration bitstream for a suitable FPGA implementation. MATLAB functions optimize and simulate the control algorithm before translating it into the VHSIC hardware description language. These functions improve power efficiency and simplify integration in the final implementation by performing a linear transformation that renders the controller computationally friendly. The transformation favors sparse matrices in order to reduce multiply operations and the hardware necessary to support them; simultaneously, the remaining matrix elements take on values that minimize limit cycles and parameter sensitivity. The proposed controller design methodology is implemented on a simple cantilever beam test structure using FPGA hardware. The experimental closed loop response is compared with that of an automated FPGA controller implementation. Finally, we explore the integration of FPGA based controllers into a multi-chip module, which we believe represents the next step towards the realization of the Smart Patch.

Process development of beam-lead silicon-gate COS/MOS integrated circuits

NASA Technical Reports Server (NTRS)

Baptiste, B.; Boesenberg, W.

1974-01-01

Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.

Gallium arsenide processing for gate array logic

NASA Technical Reports Server (NTRS)

Cole, Eric D.

1989-01-01

The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

Real-time label-free biosensing with integrated planar waveguide ring resonators

NASA Astrophysics Data System (ADS)

Sohlström, Hans; Gylfason, Kristinn B.; Hill, Daniel

2010-05-01

We review the use of planar integrated optical waveguide ring resonators for label free bio-sensing and present recent results from two European biosensor collaborations: SABIO and InTopSens. Planar waveguide ring resonators are attractive for label-free biosensing due to their small footprint, high Q-factors, and compatibility with on-chip optics and microfluidics. This enables integrated sensor arrays for compact labs-on-chip. One application of label-free sensor arrays is for point-of-care medical diagnostics. Bringing such powerful tools to the single medical practitioner is an important step towards personalized medicine, but requires addressing a number of issues: improving limit of detection, managing the influence of temperature, parallelization of the measurement for higher throughput and on-chip referencing, efficient light-coupling strategies to simplify alignment, and packaging of the optical chip and integration with microfluidics. From the SABIO project we report refractive index measurement and label-free biosensing in an 8-channel slotwaveguide ring resonator sensor array, within a compact cartridge with integrated microfluidics. The sensors show a volume sensing detection limit of 5 x 10-6 RIU and a surface sensing detection limit of 0.9 pg/mm2. From the InTopSens project we report early results on silicon-on-insulator racetrack resonators.

SU-E-T-350: Verification of Gating Performance of a New Elekta Gating Solution: Response Kit and Catalyst System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xie, X; Cao, D; Housley, D

2014-06-01

Purpose: In this work, we have tested the performance of new respiratory gating solutions for Elekta linacs. These solutions include the Response gating and the C-RAD Catalyst surface mapping system.Verification measurements have been performed for a series of clinical cases. We also examined the beam on latency of the system and its impact on delivery efficiency. Methods: To verify the benefits of tighter gating windows, a Quasar Respiratory Motion Platform was used. Its vertical-motion plate acted as a respiration surrogate and was tracked by the Catalyst system to generate gating signals. A MatriXX ion-chamber array was mounted on its longitudinal-movingmore » platform. Clinical plans are delivered to a stationary and moving Matrix array at 100%, 50% and 30% gating windows and gamma scores were calculated comparing moving delivery results to the stationary result. It is important to note that as one moves to tighter gating windows, the delivery efficiency will be impacted by the linac's beam-on latency. Using a specialized software package, we generated beam-on signals of lengths of 1000ms, 600ms, 450ms, 400ms, 350ms and 300ms. As the gating windows get tighter, one can expect to reach a point where the dose rate will fall to nearly zero, indicating that the gating window is close to beam-on latency. A clinically useful gating window needs to be significantly longer than the latency for the linac. Results: As expected, the use of tighter gating windows improved delivery accuracy. However, a lower limit of the gating window, largely defined by linac beam-on latency, exists at around 300ms. Conclusion: The Response gating kit, combined with the C-RAD Catalyst, provides an effective solution for respiratorygated treatment delivery. Careful patient selection, gating window design, even visual/audio coaching may be necessary to ensure both delivery quality and efficiency. This research project is funded by Elekta.« less

Chip level modeling of LSI devices

NASA Technical Reports Server (NTRS)

Armstrong, J. R.

1984-01-01

The advent of Very Large Scale Integration (VLSI) technology has rendered the gate level model impractical for many simulation activities critical to the design automation process. As an alternative, an approach to the modeling of VLSI devices at the chip level is described, including the specification of modeling language constructs important to the modeling process. A model structure is presented in which models of the LSI devices are constructed as single entities. The modeling structure is two layered. The functional layer in this structure is used to model the input/output response of the LSI chip. A second layer, the fault mapping layer, is added, if fault simulations are required, in order to map the effects of hardware faults onto the functional layer. Modeling examples for each layer are presented. Fault modeling at the chip level is described. Approaches to realistic functional fault selection and defining fault coverage for functional faults are given. Application of the modeling techniques to single chip and bit slice microprocessors is discussed.

Electron lithography STAR design guidelines. Part 2: The design of a STAR for space applications

NASA Technical Reports Server (NTRS)

Trotter, J. D.; Newman, W.

1982-01-01

The STAR design system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computr programs to place, route, and display designs implemented with cells from the library. Also described is the development of a radiation-hard array designed for the STAR system. The design is based on the CMOS silicon gate technology developed by SANDIA National Laboratories. The design rules used are given as well as the model parameters developed for the basic array element. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Microwell Arrays for Studying Many Individual Cells

NASA Technical Reports Server (NTRS)

Folch, Albert; Kosar, Turgut Fettah

2009-01-01

"Laboratory-on-a-chip" devices that enable the simultaneous culturing and interrogation of many individual living cells have been invented. Each such device includes a silicon nitride-coated silicon chip containing an array of micromachined wells sized so that each well can contain one cell in contact or proximity with a patch clamp or other suitable single-cell-interrogating device. At the bottom of each well is a hole, typically 0.5 m wide, that connects the well with one of many channels in a microfluidic network formed in a layer of poly(dimethylsiloxane) on the underside of the chip. The microfluidic network makes it possible to address wells (and, thus, cells) individually to supply them with selected biochemicals. The microfluidic channels also provide electrical contact to the bottoms of the wells.

L-connect routing of die surface pads to the die edge for stacking in a 3D array

DOEpatents

Petersen, Robert W.

2000-01-01

Integrated circuit chips and method of routing the interface pads from the face of the chip or die to one or more sidewall surfaces of the die. The interconnection is routed from the face of the die to one or more edges of the die, then routed over the edge of the die and onto the side surface. A new pad is then formed on the sidewall surface, which allows multiple die or chips to be stacked in a three-dimensional array, while enabling follow-on signal routing from the sidewall pads. The routing of the interconnects and formation of the sidewall pads can be carried out in an L-connect or L-shaped routing configuration, using a metalization process such as laser pantography.

Nanophotonic Trapping for Precise Manipulation of Biomolecular Arrays

PubMed Central

Soltani, Mohammad; Lin, Jun; Forties, Robert A.; Inman, James T.; Saraf, Summer N.; Fulbright, Robert M.; Lipson, Michal; Wang, Michelle D.

2014-01-01

Optical trapping is a powerful manipulation and measurement technique widely employed in the biological and materials sciences1–8. Miniaturizing optical trap instruments onto optofluidic platforms holds promise for high throughput lab-on-chip applications9–16. However, a persistent challenge with existing optofluidic devices has been controlled and precise manipulation of trapped particles. Here we report a new class of on-chip optical trapping devices. Using photonic interference functionalities, an array of stable, three-dimensional on-chip optical traps is formed at the antinodes of a standing-wave evanescent field on a nanophotonic waveguide. By employing the thermo-optic effect via integrated electric microheaters, the traps can be repositioned at high speed (~ 30 kHz) with nanometer precision. We demonstrate sorting and manipulation of individual DNA molecules. In conjunction with laminar flows and fluorescence, we also show precise control of the chemical environment of a sample with simultaneous monitoring. Such a controllable trapping device has the potential for high-throughput precision measurements on chip. PMID:24776649

Nanophotonic trapping for precise manipulation of biomolecular arrays.

PubMed

Soltani, Mohammad; Lin, Jun; Forties, Robert A; Inman, James T; Saraf, Summer N; Fulbright, Robert M; Lipson, Michal; Wang, Michelle D

2014-06-01

Optical trapping is a powerful manipulation and measurement technique widely used in the biological and materials sciences. Miniaturizing optical trap instruments onto optofluidic platforms holds promise for high-throughput lab-on-a-chip applications. However, a persistent challenge with existing optofluidic devices has been achieving controlled and precise manipulation of trapped particles. Here, we report a new class of on-chip optical trapping devices. Using photonic interference functionalities, an array of stable, three-dimensional on-chip optical traps is formed at the antinodes of a standing-wave evanescent field on a nanophotonic waveguide. By employing the thermo-optic effect via integrated electric microheaters, the traps can be repositioned at high speed (∼30 kHz) with nanometre precision. We demonstrate sorting and manipulation of individual DNA molecules. In conjunction with laminar flows and fluorescence, we also show precise control of the chemical environment of a sample with simultaneous monitoring. Such a controllable trapping device has the potential to achieve high-throughput precision measurements on chip.

Quantum Logic with Cavity Photons From Single Atoms.

PubMed

Holleczek, Annemarie; Barter, Oliver; Rubenok, Allison; Dilley, Jerome; Nisbet-Jones, Peter B R; Langfahl-Klabes, Gunnar; Marshall, Graham D; Sparrow, Chris; O'Brien, Jeremy L; Poulios, Konstantinos; Kuhn, Axel; Matthews, Jonathan C F

2016-07-08

We demonstrate quantum logic using narrow linewidth photons that are produced with an a priori nonprobabilistic scheme from a single ^{87}Rb atom strongly coupled to a high-finesse cavity. We use a controlled-not gate integrated into a photonic chip to entangle these photons, and we observe nonclassical correlations between photon detection events separated by periods exceeding the travel time across the chip by 3 orders of magnitude. This enables quantum technology that will use the properties of both narrow-band single photon sources and integrated quantum photonics.

Statistical evaluation of metal fill widths for emulated metal fill in parasitic extraction methodology

NASA Astrophysics Data System (ADS)

J-Me, Teh; Noh, Norlaili Mohd.; Aziz, Zalina Abdul

2015-05-01

In the chip industry today, the key goal of a chip development organization is to develop and market chips within a short time frame to gain foothold on market share. This paper proposes a design flow around the area of parasitic extraction to improve the design cycle time. The proposed design flow utilizes the usage of metal fill emulation as opposed to the current flow which performs metal fill insertion directly. By replacing metal fill structures with an emulation methodology in earlier iterations of the design flow, this is targeted to help reduce runtime in fill insertion stage. Statistical design of experiments methodology utilizing the randomized complete block design was used to select an appropriate emulated metal fill width to improve emulation accuracy. The experiment was conducted on test cases of different sizes, ranging from 1000 gates to 21000 gates. The metal width was varied from 1 x minimum metal width to 6 x minimum metal width. Two-way analysis of variance and Fisher's least significant difference test were used to analyze the interconnect net capacitance values of the different test cases. This paper presents the results of the statistical analysis for the 45 nm process technology. The recommended emulated metal fill width was found to be 4 x the minimum metal width.

Multisensory architectures for action-oriented perception

NASA Astrophysics Data System (ADS)

Alba, L.; Arena, P.; De Fiore, S.; Listán, J.; Patané, L.; Salem, A.; Scordino, G.; Webb, B.

2007-05-01

In order to solve the navigation problem of a mobile robot in an unstructured environment a versatile sensory system and efficient locomotion control algorithms are necessary. In this paper an innovative sensory system for action-oriented perception applied to a legged robot is presented. An important problem we address is how to utilize a large variety and number of sensors, while having systems that can operate in real time. Our solution is to use sensory systems that incorporate analog and parallel processing, inspired by biological systems, to reduce the required data exchange with the motor control layer. In particular, as concerns the visual system, we use the Eye-RIS v1.1 board made by Anafocus, which is based on a fully parallel mixed-signal array sensor-processor chip. The hearing sensor is inspired by the cricket hearing system and allows efficient localization of a specific sound source with a very simple analog circuit. Our robot utilizes additional sensors for touch, posture, load, distance, and heading, and thus requires customized and parallel processing for concurrent acquisition. Therefore a Field Programmable Gate Array (FPGA) based hardware was used to manage the multi-sensory acquisition and processing. This choice was made because FPGAs permit the implementation of customized digital logic blocks that can operate in parallel allowing the sensors to be driven simultaneously. With this approach the multi-sensory architecture proposed can achieve real time capabilities.

Integrated Electrode Arrays for Neuro-Prosthetic Implants

NASA Technical Reports Server (NTRS)

Brandon, Erik; Mojarradi, Mohammede

2003-01-01

Arrays of electrodes integrated with chip-scale packages and silicon-based integrated circuits have been proposed for use as medical electronic implants, including neuro-prosthetic devices that might be implanted in brains of patients who suffer from strokes, spinal-cord injuries, or amyotrophic lateral sclerosis. The electrodes of such a device would pick up signals from neurons in the cerebral cortex, and the integrated circuit would perform acquisition and preprocessing of signal data. The output of the integrated circuit could be used to generate, for example, commands for a robotic arm. Electrode arrays capable of acquiring electrical signals from neurons already exist, but heretofore, there has been no convenient means to integrate these arrays with integrated-circuit chips. Such integration is needed in order to eliminate the need for the extensive cabling now used to pass neural signals to data-acquisition and -processing equipment outside the body. The proposed integration would enable progress toward neuro-prostheses that would be less restrictive of patients mobility. An array of electrodes would comprise a set of thin wires of suitable length and composition protruding from and supported by a fine-pitch micro-ball grid array or chip-scale package (see figure). The associated integrated circuit would be mounted on the package face opposite the probe face, using the solder bumps (the balls of the ball grid array) to make the electrical connections between the probes and the input terminals of the integrated circuit. The key innovation is the insertion of probe wires of the appropriate length and material into the solder bumps through a reflow process, thereby fixing the probes in place and electrically connecting them with the integrated circuit. The probes could be tailored to any distribution of lengths and made of any suitable metal that could be drawn into fine wires. Furthermore, the wires could be coated with an insulating layer using anodization or other processes, to achieve the correct electrical impedance. The probe wires and the packaging materials must be biocompatible using such materials as lead-free solders. For protection, the chip and package can be coated with parylene.

AlGaN/GaN-on-Si monolithic power-switching device with integrated gate current booster

NASA Astrophysics Data System (ADS)

Han, Sang-Woo; Jo, Min-Gi; Kim, Hyungtak; Cho, Chun-Hyung; Cha, Ho-Young

2017-08-01

This study investigates the effects of a monolithic gate current booster integrated with an AlGaN/GaN-on-Si power-switching device. The integrated gate current booster was implemented by a single-stage inverter topology consisting of a recessed normally-off AlGaN/GaN MOS-HFET and a mesa resistor. The monolithically integrated gate current booster in a switching FET eliminated the parasitic elements caused by external interconnection and enabled fast switching operation. The gate charging and discharging currents were boosted by the integrated inverter, which significantly reduced both rise and fall times: the rise time was reduced from 626 to 41.26 ns, while the fall time was reduced from 554 to 42.19 ns by the single-stage inverter. When the packaged monolithic power chip was tested under 1 MHz hard-switching operation with VDD = 200 V, the switching loss was found to have been drastically reduced, from 5.27 to 0.55 W.

On-Chip Sorting of Long Semiconducting Carbon Nanotubes for Multiple Transistors along an Identical Array.

PubMed

Otsuka, Keigo; Inoue, Taiki; Maeda, Etsuo; Kometani, Reo; Chiashi, Shohei; Maruyama, Shigeo

2017-11-28

Ballistic transport and sub-10 nm channel lengths have been achieved in transistors containing one single-walled carbon nanotube (SWNT). To fill the gap between single-tube transistors and high-performance logic circuits for the replacement of silicon, large-area, high-density, and purely semiconducting (s-) SWNT arrays are highly desired. Here we demonstrate the fabrication of multiple transistors along a purely semiconducting SWNT array via an on-chip purification method. Water- and polymer-assisted burning from site-controlled nanogaps is developed for the reliable full-length removal of metallic SWNTs with the damage to s-SWNTs minimized even in high-density arrays. All the transistors with various channel lengths show large on-state current and excellent switching behavior in the off-state. Since our method potentially provides pure s-SWNT arrays over a large area with negligible damage, numerous transistors with arbitrary dimensions could be fabricated using a conventional semiconductor process, leading to SWNT-based logic, high-speed communication, and other next-generation electronic devices.

Programmable synaptic chip for electronic neural networks

NASA Technical Reports Server (NTRS)

Moopenn, A.; Langenbacher, H.; Thakoor, A. P.; Khanna, S. K.

1988-01-01

A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.

A Compression Algorithm for Field Programmable Gate Arrays in the Space Environment

DTIC Science & Technology

2011-12-01

Bit 1 ,Bit 0P  . (V.3) Equation (V.3) is implemented with a string of XOR gates and Bit Basher blocks, as shown in Figure 31. As discussed in...5], the string of Bit Basher blocks are used to separate each 35-bit value into 35 one-bit values, and the string of XOR gates is used to

UW VLSI chip tester

NASA Astrophysics Data System (ADS)

McKenzie, Neil

1989-12-01

We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

Survey Of High Speed Test Techniques

NASA Astrophysics Data System (ADS)

Gheewala, Tushar

1988-02-01

The emerging technologies for the characterization and production testing of high-speed devices and integrated circuits are reviewed. The continuing progress in the field of semiconductor technologies will, in the near future, demand test techniques to test 10ps to lOOps gate delays, 10 GHz to 100 GHz analog functions and 10,000 to 100,000 gates on a single chip. Clearly, no single test technique would provide a cost-effective answer to all the above demands. A divide-and-conquer approach based on a judicial selection of parametric, functional and high-speed tests will be required. In addition, design-for-test methods need to be pursued which will include on-chip test electronics as well as circuit techniques that minimize the circuit performance sensitivity to allowable process variations. The electron and laser beam based test technologies look very promising and may provide the much needed solutions to not only the high-speed test problem but also to the need for high levels of fault coverage during functional testing.

Design and Fabrication of an Implantable Cortical Semiconductor Integrated Circuit Electrode Array

DTIC Science & Technology

1990-12-01

25 Array Pads....................25 Polyimide ....................26 III. METHODOLOGY.........................27 Brain Chip Electronics...38 Ionic Permeation. .................. 38 Polyimide . ................... 38 Implantation. .................... 39 Wire Bonding...53 Pad Sensitivity ................. 53 Ionic Permeat:.on. .................. 54 Polyimide . ................... 54 Implantation

Advanced InSb monolithic Charge Coupled Infrared Imaging Devices (CCIRID)

NASA Technical Reports Server (NTRS)

Koch, T. L.; Thom, R. D.; Parrish, W. D.

1981-01-01

The continued development of monolithic InSb charge coupled infrared imaging devices (CCIRIDs) is discussed. The processing sequence and structural design of 20-element linear arrays are discussed. Also, results obtained from radiometric testing of the 20-element arrays using a clamped sample-and-hold output circuit are reported. The design and layout of a next-generation CCIRID chip are discussed. The major devices on this chip are a 20 by 16 time-delay-and-integration (TDI) area array and a 100-element linear imaging array. The development of a process for incorporating an ion implanted S(+) planar channel stop into the CCIRID structure and the development of a thin film transparent photogate are also addressed. The transparent photogates will increase quantum efficiency to greater than 70% across the 2.5 to 5.4 micrometer spectral region in future front-side illuminated CCIRIDs.

Monolithic short wave infrared (SWIR) detector array

NASA Technical Reports Server (NTRS)

1983-01-01

A monolithic self-scanned linear detector array was developed for remote sensing in the 1.1- 2.4-micron spectral region. A high-density IRCCD test chip was fabricated to verify new design approaches required for the detector array. The driving factors in the Schottky barrier IRCCD (Pdsub2Si) process development are the attainment of detector yield, uniformity, adequate quantum efficiency, and lowest possible dark current consistent with radiometric accuracy. A dual-band module was designed that consists of two linear detector arrays. The sensor architecture places the floating diffusion output structure in the middle of the chip, away from the butt edges. A focal plane package was conceptualized and includes a polycrystalline silicon substrate carrying a two-layer, thick-film interconnecting conductor pattern and five epoxy-mounted modules. A polycrystalline silicon cover encloses the modules and bond wires, and serves as a radiation and EMI shield, thermal conductor, and contamination seal.

Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays.

PubMed

Ciçek, Ihsan; Bozkurt, Ayhan; Karaman, Mustafa

2005-12-01

Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMUT element, we developed an electrical CMUT model with parameters derived through finite element analysis, and performed both the pre- and postlayout verification. An experimental chip consisting of 4 X 4 array of the designed circuit cells, each cell occupying a 200 X 200 microm2 area, was formed for the initial test studies and scheduled for fabrication in 0.8 microm, 50 V CMOS technology. The designed circuit is suitable for integration with CMUT arrays through flip-chip bonding and the CMUT-on-CMOS process.

Actuation and transduction of resonant vibrations in GaAs/AlGaAs-based nanoelectromechanical systems containing two-dimensional electron gas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shevyrin, A. A., E-mail: shevandrey@isp.nsc.ru; Pogosov, A. G.; Bakarov, A. K.

2015-05-04

Driven vibrations of a nanoelectromechanical system based on GaAs/AlGaAs heterostructure containing two-dimensional electron gas are experimentally investigated. The system represents a conductive cantilever with the free end surrounded by a side gate. We show that out-of-plane flexural vibrations of the cantilever are driven when alternating signal biased by a dc voltage is applied to the in-plane side gate. We demonstrate that these vibrations can be on-chip linearly transduced into a low-frequency electrical signal using the heterodyne down-mixing method. The obtained data indicate that the dominant physical mechanism of the vibrations actuation is capacitive interaction between the cantilever and the gate.

Combining axial and radial nanowire heterostructures: radial Esaki diodes and tunnel field-effect transistors.

PubMed

Dey, Anil W; Svensson, Johannes; Ek, Martin; Lind, Erik; Thelander, Claes; Wernersson, Lars-Erik

2013-01-01

The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit (Radosavljevic et al., IEEE Int. Devices Meeting 2009, 1-4 and Cho et al., IEEE Int. Devices Meeting 2011, 15.1.1-15.1.4). The continued scaling of the supply voltage of field-effect transistors, such as tunnel field-effect transistors (TFETs), requires the implementation of advanced transistor architectures including FinFETs and nanowire devices. Moreover, integration of novel materials with high electron mobilities, such as III-V semiconductors and graphene, are also being considered to further enhance the device properties (del Alamo, Nature 2011, 479, 317-323, and Liao et al., Nature 2010, 467, 305-308). In nanowire devices, boosting the drive current at a fixed supply voltage or maintaining a constant drive current at a reduced supply voltage may be achieved by increasing the cross-sectional area of a device, however at the cost of deteriorated electrostatics. A gate-all-around nanowire device architecture is the most favorable electrostatic configuration to suppress short channel effects; however, the arrangement of arrays of parallel vertical nanowires to address the drive current predicament will require additional chip area. The use of a core-shell nanowire with a radial heterojunction in a transistor architecture provides an attractive means to address the drive current issue without compromising neither chip area nor device electrostatics. In addition to design advantages of a radial transistor architecture, we in this work illustrate the benefit in terms of drive current per unit chip area and compare the experimental data for axial GaSb/InAs Esaki diodes and TFETs to their radial counterparts and normalize the electrical data to the largest cross-sectional area of the nanowire, i.e. the occupied chip area, assuming a vertical device geometry. Our data on lateral devices show that radial Esaki diodes deliver almost 7 times higher peak current, Jpeak = 2310 kA/cm(2), than the maximum peak current of axial GaSb/InAs(Sb) Esaki diodes per unit chip area. The radial TFETs also deliver high peak current densities Jpeak = 1210 kA/cm(2), while their axial counterparts at most carry Jpeak = 77 kA/cm(2), normalized to the largest cross-sectional area of the nanowire.

A microfluidic platform with integrated arrays for immunologic assays for biological pathogen detection

NASA Astrophysics Data System (ADS)

Klemm, Richard; Becker, Holger; Hlawatsch, Nadine; Julich, Sandra; Miethe, Peter; Moche, Christian; Schattschneider, Sebastian; Tomaso, Herbert; Gärtner, Claudia

2014-05-01

The ability to integrate complete assays on a microfluidic chip helps to greatly simplify instrument requirements and allows the use of lab-on-a-chip technology in the field. A core application for such field-portable systems is the detection of pathogens in a CBRN scenario such as permanent monitoring of airborne pathogens, e.g. in subway stations or hospitals etc. An immunological assay was chosen as method for the pathogen identification. The conceptual approach was its realization as a lab-on-a-chip system, enabling an easy handling of the sample in an automated manner. The immunological detection takes place on an antibody array directly implemented in the microfluidic network. Different immobilization strategies will be presented showing the performance of the system. Central elements of the disposable microfluidic device like fluidic interface, turning valves, liquid introduction and waste storage, as well as the architecture of measurement and control fluidic network, will be introduced. Overall process times of about 30 minutes were achieved and assays for the detection of Francisella tularensis and Yersinia pestis are presented. An important feature of the integrated lab-on-a-chip approach is that all waste liquids remain on-chip and contamination risks can be avoided.

Bimodal imprint chips for peptide screening: integration of high-throughput sequencing by MS and affinity analyses by surface plasmon resonance imaging.

PubMed

Wang, Weizhi; Li, Menglin; Wei, Zewen; Wang, Zihua; Bu, Xiangli; Lai, Wenjia; Yang, Shu; Gong, He; Zheng, Hui; Wang, Yuqiao; Liu, Ying; Li, Qin; Fang, Qiaojun; Hu, Zhiyuan

2014-04-15

Peptide probes and drugs have widespread applications in disease diagnostics and therapy. The demand for peptides ligands with high affinity and high specificity toward various targets has surged in the biomedical field in recent years. The traditional peptide screening procedure involves selection, sequencing, and characterization steps, and each step is manual and tedious. Herein, we developed a bimodal imprint microarray system to embrace the whole peptide screening process. Silver-sputtered silicon chip fabricated with microwell array can trap and pattern the candidate peptide beads in a one-well-one-bead manner. Peptides on beads were photocleaved in situ. A portion of the peptide in each well was transferred to a gold-coated chip to print the peptide array for high-throughput affinity analyses by surface plasmon resonance imaging (SPRi), and the peptide left in the silver-sputtered chip was ready for in situ single bead sequencing by matrix-assisted laser desorption ionization time-of-flight mass spectrometry (MALDI-TOF-MS). Using the bimodal imprint chip system, affinity peptides toward AHA were efficiently screened out from the 7 × 10(4) peptide library. The method provides a solution for high efficiency peptide screening.

Nonvolatile Array Of Synapses For Neural Network

NASA Technical Reports Server (NTRS)

Tawel, Raoul

1993-01-01

Elements of array programmed with help of ultraviolet light. A 32 x 32 very-large-scale integrated-circuit array of electronic synapses serves as building-block chip for analog neural-network computer. Synaptic weights stored in nonvolatile manner. Makes information content of array invulnerable to loss of power, and, by eliminating need for circuitry to refresh volatile synaptic memory, makes architecture simpler and more compact.

Image Decoding of Photonic Crystal Beads Array in the Microfluidic Chip for Multiplex Assays

PubMed Central

Yuan, Junjie; Zhao, Xiangwei; Wang, Xiaoxia; Gu, Zhongze

2014-01-01

Along with the miniaturization and intellectualization of biomedical instruments, the increasing demand of health monitoring at anywhere and anytime elevates the need for the development of point of care testing (POCT). Photonic crystal beads (PCBs) as one kind of good encoded microcarriers can be integrated with microfluidic chips in order to realize cost-effective and high sensitive multiplex bioassays. However, there are difficulties in analyzing them towards automated analysis due to the characters of the PCBs and the unique detection manner. In this paper, we propose a strategy to take advantage of automated image processing for the color decoding of the PCBs array in the microfluidic chip for multiplex assays. By processing and alignment of two modal images of epi-fluorescence and epi-white light, every intact bead in the image is accurately extracted and decoded by PC colors, which stand for the target species. This method, which shows high robustness and accuracy under various configurations, eliminates the high hardware requirement of spectroscopy analysis and user-interaction software, and provides adequate supports for the general automated analysis of POCT based on PCBs array. PMID:25341876

Ultra-High-Speed DNA Fragment Separations Using Microfabricated Capillary Array Electrophoresis Chips

NASA Astrophysics Data System (ADS)

Woolley, Adam T.; Mathies, Richard A.

1994-11-01

Capillary electrophoresis arrays have been fabricated on planar glass substrates by photolithographic masking and chemical etching techniques. The photolithographically defined channel patterns were etched in a glass substrate, and then capillaries were formed by thermally bonding the etched substrate to a second glass slide. High-resolution electrophoretic separations of φX174 Hae III DNA restriction fragments have been performed with these chips using a hydroxyethyl cellulose sieving matrix in the channels. DNA fragments were fluorescently labeled with dye in the running buffer and detected with a laser-excited, confocal fluorescence system. The effects of variations in the electric field, procedures for injection, and sizes of separation and injection channels (ranging from 30 to 120 μm) have been explored. By use of channels with an effective length of only 3.5 cm, separations of φX174 Hae III DNA fragments from ≈70 to 1000 bp are complete in only 120 sec. We have also demonstrated high-speed sizing of PCR-amplified HLA-DQα alleles. This work establishes methods for high-speed, high-throughput DNA separations on capillary array electrophoresis chips.

A novel miniaturized PCR multi-reactor array fabricated using flip-chip bonding techniques

NASA Astrophysics Data System (ADS)

Zou, Zhi-Qing; Chen, Xiang; Jin, Qing-Hui; Yang, Meng-Su; Zhao, Jian-Long

2005-08-01

This paper describes a novel miniaturized multi-chamber array capable of high throughput polymerase chain reaction (PCR). The structure of the proposed device is verified by using finite element analysis (FEA) to optimize the thermal performance, and then implemented on a glass-silicon substrate using a standard MEMS process and post-processing. Thermal analysis simulation and verification of each reactor cell is equipped with integrated Pt temperature sensors and heaters at the bottom of the reaction chamber for real-time accurate temperature sensing and control. The micro-chambers are thermally separated from each other, and can be controlled independently. The multi-chip array was packaged on a printed circuit board (PCB) substrate using a conductive polymer flip-chip bonding technique, which enables effective heat dissipation and suppresses thermal crosstalk between the chambers. The designed system has successfully demonstrated a temperature fluctuation of ±0.5 °C during thermal multiplexing of up to 2 × 2 chambers, a full speed of 30 min for 30 cycle PCR, as well as the capability of controlling each chamber digitally and independently.

An ultra-compact and low loss passive beam-forming network integrated on chip with off chip linear array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lepkowski, Stefan Mark

2015-05-01

The work here presents a review of beam forming architectures. As an example, the author presents an 8x8 Butler Matrix passive beam forming network including the schematic, design/modeling, operation, and simulated results. The limiting factor in traditional beam formers has been the large size dictated by transmission line based couplers. By replacing these couplers with transformer-based couplers, the matrix size is reduced substantially allowing for on chip compact integration. In the example presented, the core area, including the antenna crossover, measures 0.82mm×0.39mm (0.48% the size of a branch line coupler at the same frequency). The simulated beam forming achieves amore » peak PNR of 17.1 dB and 15dB from 57 to 63GHz. At the 60GHz center frequency the average insertion loss is simulated to be 3.26dB. The 8x8 Butler Matrix feeds into an 8-element antenna array to show the array patterns with single beam and adjacent beam isolation.« less

Ultrafast optical control of individual quantum dot spin qubits.

PubMed

De Greve, Kristiaan; Press, David; McMahon, Peter L; Yamamoto, Yoshihisa

2013-09-01

Single spins in semiconductor quantum dots form a promising platform for solid-state quantum information processing. The spin-up and spin-down states of a single electron or hole, trapped inside a quantum dot, can represent a single qubit with a reasonably long decoherence time. The spin qubit can be optically coupled to excited (charged exciton) states that are also trapped in the quantum dot, which provides a mechanism to quickly initialize, manipulate and measure the spin state with optical pulses, and to interface between a stationary matter qubit and a 'flying' photonic qubit for quantum communication and distributed quantum information processing. The interaction of the spin qubit with light may be enhanced by placing the quantum dot inside a monolithic microcavity. An entire system, consisting of a two-dimensional array of quantum dots and a planar microcavity, may plausibly be constructed by modern semiconductor nano-fabrication technology and could offer a path toward chip-sized scalable quantum repeaters and quantum computers. This article reviews the recent experimental developments in optical control of single quantum dot spins for quantum information processing. We highlight demonstrations of a complete set of all-optical single-qubit operations on a single quantum dot spin: initialization, an arbitrary SU(2) gate, and measurement. We review the decoherence and dephasing mechanisms due to hyperfine interaction with the nuclear-spin bath, and show how the single-qubit operations can be combined to perform spin echo sequences that extend the qubit decoherence from a few nanoseconds to several microseconds, more than 5 orders of magnitude longer than the single-qubit gate time. Two-qubit coupling is discussed, both within a single chip by means of exchange coupling of nearby spins and optically induced geometric phases, as well as over longer-distances. Long-distance spin-spin entanglement can be generated if each spin can emit a photon that is entangled with the spin, and these photons are then interfered. We review recent work demonstrating entanglement between a stationary spin qubit and a flying photonic qubit. These experiments utilize the polarization- and frequency-dependent spontaneous emission from the lowest charged exciton state to single spin Zeeman sublevels.

Flight Qualified Micro Sun Sensor

NASA Technical Reports Server (NTRS)

Liebe, Carl Christian; Mobasser, Sohrab; Wrigley, Chris; Schroeder, Jeffrey; Bae, Youngsam; Naegle, James; Katanyoutanant, Sunant; Jerebets, Sergei; Schatzel, Donald; Lee, Choonsup

2007-01-01

A prototype small, lightweight micro Sun sensor (MSS) has been flight qualified as part of the attitude-determination system of a spacecraft or for Mars surface operations. The MSS has previously been reported at a very early stage of development in NASA Tech Briefs, Vol. 28, No. 1 (January 2004). An MSS is essentially a miniature multiple-pinhole electronic camera combined with digital processing electronics that functions analogously to a sundial. A micromachined mask containing a number of microscopic pinholes is mounted in front of an active-pixel sensor (APS). Electronic circuits for controlling the operation of the APS, readout from the pixel photodetectors, and analog-to-digital conversion are all integrated onto the same chip along with the APS. The digital processing includes computation of the centroids of the pinhole Sun images on the APS. The spacecraft computer has the task of converting the Sun centroids into Sun angles utilizing a calibration polynomial. The micromachined mask comprises a 500-micron-thick silicon wafer, onto which is deposited a 57-nm-thick chromium adhesion- promotion layer followed by a 200-nm-thick gold light-absorption layer. The pinholes, 50 microns in diameter, are formed in the gold layer by photolithography. The chromium layer is thin enough to be penetrable by an amount of Sunlight adequate to form measurable pinhole images. A spacer frame between the mask and the APS maintains a gap of .1 mm between the pinhole plane and the photodetector plane of the APS. To minimize data volume, mass, and power consumption, the digital processing of the APS readouts takes place in a single field-programmable gate array (FPGA). The particular FPGA is a radiation- tolerant unit that contains .32,000 gates. No external memory is used so the FPGA calculates the centroids in real time as pixels are read off the APS with minimal internal memory. To enable the MSS to fit into a small package, the APS, the FPGA, and other components are mounted on a single two-sided board following chip-on-board design practices

Large-Scale Precise Printing of Ultrathin Sol-Gel Oxide Dielectrics for Directly Patterned Solution-Processed Metal Oxide Transistor Arrays.

PubMed

Lee, Won-June; Park, Won-Tae; Park, Sungjun; Sung, Sujin; Noh, Yong-Young; Yoon, Myung-Han

2015-09-09

Ultrathin and dense metal oxide gate di-electric layers are reported by a simple printing of AlOx and HfOx sol-gel precursors. Large-area printed indium gallium zinc oxide (IGZO) thin-film transistor arrays, which exhibit mobilities >5 cm(2) V(-1) s(-1) and gate leakage current of 10(-9) A cm(-2) at a very low operation voltage of 2 V, are demonstrated by continuous simple bar-coated processes. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Qualification Strategies of Field Programmable Gate Arrays (FPGAs) for Space Application

NASA Technical Reports Server (NTRS)

Sheldon, Douglas; Schone, Harald

2005-01-01

This viewgraph document reviews the issue of using Field Programmable Gate Arrays (FPGAs) in Space Application, and the some of the strategies for qualifying the FPGA. Qualification and risk management of such complex systems requires new approaches. The paper presents a matrix approach to qualification has been presented that: - Complements historical specifications - Highlights the importance of device physics as a cornerstone to qualification. - Provides levels of risk management that expressly document trade offs. - Stresses the role of the FPGA vendor as team member in the development of modern spacecraft.

A software framework for pipelined arithmetic algorithms in field programmable gate arrays

NASA Astrophysics Data System (ADS)

Kim, J. B.; Won, E.

2018-03-01

Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++, ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.

Development of a photodiode array biochip using a bipolar semiconductor and its application to detection of human papilloma virus.

PubMed

Baek, Taek Jin; Park, Pan Yun; Han, Kwi Nam; Kwon, Ho Taik; Seong, Gi Hun

2008-03-01

We describe a DNA microarray system using a bipolar integrated circuit photodiode array (PDA) chip as a new platform for DNA analysis. The PDA chip comprises an 8 x 6 array of photodiodes each with a diameter of 600 microm. Each photodiode element acts both as a support for an immobilizing probe DNA and as a two-dimensional photodetector. The usefulness of the PDA microarray platform is demonstrated by the detection of high-risk subtypes of human papilloma virus (HPV). The polymerase chain reaction (PCR)-amplified biotinylated HPV target DNA was hybridized with the immobilized probe DNA on the photodiode surface, and the chip was incubated in an anti-biotin antibody-conjugated gold nanoparticle solution. The silver enhancement by the gold nanoparticles bound to the biotin of the HPV target DNA precipitates silver metal particles at the chip surfaces, which block light irradiated from above. The resulting drop in output voltage depends on the amount of target DNA present in the sample solution, which allows the specific detection and the quantitative analysis of the complementary target DNA. The PDA chip showed high relative signal ratios of HPV probe DNA hybridized with complementary target DNA, indicating an excellent capability in discriminating HPV subtypes. The detection limit for the HPV target DNA analysis improved from 1.2 nM to 30 pM by changing the silver development time from 5 to 10 min. Moreover, the enhanced silver development promoted by the gold nanoparticles could be applied to a broader range of target DNA concentration by controlling the silver development time.

Expression Profiling Smackdown: Human Transcriptome Array HTA 2.0 vs. RNA-Seq

PubMed Central

Palermo, Meghann; Driscoll, Heather; Tighe, Scott; Dragon, Julie; Bond, Jeff; Shukla, Arti; Vangala, Mahesh; Vincent, James; Hunter, Tim

2014-01-01

The advent of both microarray and massively parallel sequencing have revolutionized high-throughput analysis of the human transcriptome. Due to limitations in microarray technology, detecting and quantifying coding transcript isoforms, in addition to non-coding transcripts, has been challenging. As a result, RNA-Seq has been the preferred method for characterizing the full human transcriptome, until now. A new high-resolution array from Affymetrix, GeneChip Human Transcriptome Array 2.0 (HTA 2.0), has been designed to interrogate all transcript isoforms in the human transcriptome with >6 million probes targeting coding transcripts, exon-exon splice junctions, and non-coding transcripts. Here we compare expression results from GeneChip HTA 2.0 and RNA-Seq data using identical RNA extractions from three samples each of healthy human mesothelial cells in culture, LP9-C1, and healthy mesothelial cells treated with asbestos, LP9-A1. For GeneChip HTA 2.0 sample preparation, we chose to compare two target preparation methods, NuGEN Ovation Pico WTA V2 with the Encore Biotin Module versus Affymetrix's GeneChip WT PLUS with the WT Terminal Labeling Kit, on identical RNA extractions from both untreated and treated samples. These same RNA extractions were used for the RNA-Seq library preparation. All analyses were performed in Partek Genomics Suite 6.6. Expression profiles for control and asbestos-treated mesothelial cells prepared with NuGEN versus Affymetrix target preparation methods (GeneChip HTA 2.0) are compared to each other as well as to RNA-Seq results.

Enhancement mode GaN-based multiple-submicron channel array gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Wang, Chun-Chi

2018-04-01

To study the function of channel width in multiple-submicron channel array, we fabricated the enhancement mode GaN-based gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with a channel width of 450 nm and 195 nm, respectively. In view of the enhanced gate controllability in a narrower fin-channel structure, the transconductance was improved from 115 mS/mm to 151 mS/mm, the unit gain cutoff frequency was improved from 6.2 GHz to 6.8 GHz, and the maximum oscillation frequency was improved from 12.1 GHz to 13.1 GHz of the devices with a channel width of 195 nm, compared with the devices with a channel width of 450 nm.

The effect of split gate dimensions on the electrostatic potential and 0.7 anomaly within one-dimensional quantum wires on a modulation doped GaAs/AlGaAs heterostructure

NASA Astrophysics Data System (ADS)

Smith, L. W.; Al-Taie, H.; Lesage, A. A. J.; Thomas, K. J.; Sfigakis, F.; See, P.; Griffiths, J. P.; Farrer, I.; Jones, G. A. C.; Ritchie, D. A.; Kelly, M. J.; Smith, C. G.

We use a multiplexing scheme to measure the conductance properties of 95 split gates of 7 different gate dimensions fabricated on a GaAs/AlGaAs chip, in a single cool down. The number of devices for which conductance is accurately quantized reduces as the gate length increases. However, even the devices for which conductance is accurately quantized in units of 2e2 / h show no correlation between the length of electrostatic potential barrier in the channel and the gate length, using a saddle point model to estimate the barrier length. Further, the strength of coupling between the gates and the 1D channel does not increase with gate length beyond 0.7 μm. The background electrostatic profile appears as significant as the gate dimension in determining device behavior. We find a clear correlation between the curvature of the electrostatic barrier along the channel and the strength of the ``0.7 anomaly'' which identifies the electrostatic length of the channel as the principal factor governing the conductance of the 0.7 anomaly. Present address: Wisconsin Institute for Quantum Information, University of Wisconsin-Madison, Madison, WI.

Terahertz modulation based on surface plasmon resonance by self-gated graphene

NASA Astrophysics Data System (ADS)

Qian, Zhenhai; Yang, Dongxiao; Wang, Wei

2018-05-01

We theoretically and numerically investigate the extraordinary optical transmission through a terahertz metamaterial composed of metallic ring aperture arrays. The physical mechanism of different transmission peaks is elucidated to be magnetic polaritons or propagation surface plasmons with the help of surface current and electromagnetic field distributions at respective resonance frequencies. Then, we propose a high performance terahertz modulator based on the unique PSP resonance and combined with the metallic ring aperture arrays and a self-gated parallel-plate graphene capacitor. Because, to date, few researches have exhibited gate-controlled graphene modulation in terahertz region with low insertion losses, high modulation depth and low control voltage at room temperature. Here, we propose a 96% amplitude modulation with 0.7 dB insertion losses and ∼5.5 V gate voltage. Besides, we further study the absorption spectra of the modulator. When the transmission of modulator is very low, a 91% absorption can be achieved for avoiding damaging the source devices.

A hybrid analog-digital phase-locked loop for frequency mode non-contact scanning probe microscopy.

PubMed

Mehta, M M; Chandrasekhar, V

2014-01-01

Non-contact scanning probe microscopy (SPM) has developed into a powerful technique to image many different properties of samples. The conventional method involves monitoring the amplitude, phase, or frequency of a cantilever oscillating at or near its resonant frequency as it is scanned across the surface of a sample. For high Q factor cantilevers, monitoring the resonant frequency is the preferred method in order to obtain reasonable scan times. This can be done by using a phase-locked-loop (PLL). PLLs can be obtained as commercial integrated circuits, but these do not have the frequency resolution required for SPM. To increase the resolution, all-digital PLLs requiring sophisticated digital signal processors or field programmable gate arrays have also been implemented. We describe here a hybrid analog/digital PLL where most of the components are implemented using discrete analog integrated circuits, but the frequency resolution is provided by a direct digital synthesis chip controlled by a simple peripheral interface controller (PIC) microcontroller. The PLL has excellent frequency resolution and noise, and can be controlled and read by a computer via a universal serial bus connection.

A hybrid analog-digital phase-locked loop for frequency mode non-contact scanning probe microscopy

NASA Astrophysics Data System (ADS)

Mehta, M. M.; Chandrasekhar, V.

2014-01-01

Non-contact scanning probe microscopy (SPM) has developed into a powerful technique to image many different properties of samples. The conventional method involves monitoring the amplitude, phase, or frequency of a cantilever oscillating at or near its resonant frequency as it is scanned across the surface of a sample. For high Q factor cantilevers, monitoring the resonant frequency is the preferred method in order to obtain reasonable scan times. This can be done by using a phase-locked-loop (PLL). PLLs can be obtained as commercial integrated circuits, but these do not have the frequency resolution required for SPM. To increase the resolution, all-digital PLLs requiring sophisticated digital signal processors or field programmable gate arrays have also been implemented. We describe here a hybrid analog/digital PLL where most of the components are implemented using discrete analog integrated circuits, but the frequency resolution is provided by a direct digital synthesis chip controlled by a simple peripheral interface controller (PIC) microcontroller. The PLL has excellent frequency resolution and noise, and can be controlled and read by a computer via a universal serial bus connection.

Fast, multi-channel real-time processing of signals with microsecond latency using graphics processing units.

PubMed

Rath, N; Kato, S; Levesque, J P; Mauel, M E; Navratil, G A; Peng, Q

2014-04-01

Fast, digital signal processing (DSP) has many applications. Typical hardware options for performing DSP are field-programmable gate arrays (FPGAs), application-specific integrated DSP chips, or general purpose personal computer systems. This paper presents a novel DSP platform that has been developed for feedback control on the HBT-EP tokamak device. The system runs all signal processing exclusively on a Graphics Processing Unit (GPU) to achieve real-time performance with latencies below 8 μs. Signals are transferred into and out of the GPU using PCI Express peer-to-peer direct-memory-access transfers without involvement of the central processing unit or host memory. Tests were performed on the feedback control system of the HBT-EP tokamak using forty 16-bit floating point inputs and outputs each and a sampling rate of up to 250 kHz. Signals were digitized by a D-TACQ ACQ196 module, processing done on an NVIDIA GTX 580 GPU programmed in CUDA, and analog output was generated by D-TACQ AO32CPCI modules.

A Survey on FPGA-Based Sensor Systems: Towards Intelligent and Reconfigurable Low-Power Sensors for Computer Vision, Control and Signal Processing

PubMed Central

García, Gabriel J.; Jara, Carlos A.; Pomares, Jorge; Alabdo, Aiman; Poggi, Lucas M.; Torres, Fernando

2014-01-01

The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc.), reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field. PMID:24691100

A high-resolution programmable Vernier delay generator based on carry chains in FPGA

NASA Astrophysics Data System (ADS)

Cui, Ke; Li, Xiangyu; Zhu, Rihong

2017-06-01

This paper presents an architecture of a high-resolution delay generator implemented in a single field programmable gate array chip by exploiting the method of utilizing dedicated carry chains. It serves as the core component in various physical instruments. The proposed delay generator contains the coarse delay step and the fine delay step to guarantee both large dynamic range and high resolution. The carry chains are organized in the Vernier delay loop style to fulfill the fine delay step with high precision and high linearity. The delay generator was implemented in the EP3SE110F1152I3 Stratix III device from Altera on a self-designed test board. Test results show that the obtained resolution is 38.6 ps, and the differential nonlinearity/integral nonlinearity is in the range of [-0.18 least significant bit (LSB), 0.24 LSB]/(-0.02 LSB, 0.01 LSB) under the nominal supply voltage of 1100 mV and environmental temperature of 2 0°C. The delay generator is rather efficient concerning resource cost, which uses only 668 look-up tables and 146 registers in total.

Implementation of an RBF neural network on embedded systems: real-time face tracking and identity verification.

PubMed

Yang, Fan; Paindavoine, M

2003-01-01

This paper describes a real time vision system that allows us to localize faces in video sequences and verify their identity. These processes are image processing techniques based on the radial basis function (RBF) neural network approach. The robustness of this system has been evaluated quantitatively on eight video sequences. We have adapted our model for an application of face recognition using the Olivetti Research Laboratory (ORL), Cambridge, UK, database so as to compare the performance against other systems. We also describe three hardware implementations of our model on embedded systems based on the field programmable gate array (FPGA), zero instruction set computer (ZISC) chips, and digital signal processor (DSP) TMS320C62, respectively. We analyze the algorithm complexity and present results of hardware implementations in terms of the resources used and processing speed. The success rates of face tracking and identity verification are 92% (FPGA), 85% (ZISC), and 98.2% (DSP), respectively. For the three embedded systems, the processing speeds for images size of 288 /spl times/ 352 are 14 images/s, 25 images/s, and 4.8 images/s, respectively.

SNAVA-A real-time multi-FPGA multi-model spiking neural network simulation architecture.

PubMed

Sripad, Athul; Sanchez, Giovanny; Zapata, Mireya; Pirrone, Vito; Dorta, Taho; Cambria, Salvatore; Marti, Albert; Krishnamourthy, Karthikeyan; Madrenas, Jordi

2018-01-01

Spiking Neural Networks (SNN) for Versatile Applications (SNAVA) simulation platform is a scalable and programmable parallel architecture that supports real-time, large-scale, multi-model SNN computation. This parallel architecture is implemented in modern Field-Programmable Gate Arrays (FPGAs) devices to provide high performance execution and flexibility to support large-scale SNN models. Flexibility is defined in terms of programmability, which allows easy synapse and neuron implementation. This has been achieved by using a special-purpose Processing Elements (PEs) for computing SNNs, and analyzing and customizing the instruction set according to the processing needs to achieve maximum performance with minimum resources. The parallel architecture is interfaced with customized Graphical User Interfaces (GUIs) to configure the SNN's connectivity, to compile the neuron-synapse model and to monitor SNN's activity. Our contribution intends to provide a tool that allows to prototype SNNs faster than on CPU/GPU architectures but significantly cheaper than fabricating a customized neuromorphic chip. This could be potentially valuable to the computational neuroscience and neuromorphic engineering communities. Copyright © 2017 Elsevier Ltd. All rights reserved.

A survey on FPGA-based sensor systems: towards intelligent and reconfigurable low-power sensors for computer vision, control and signal processing.

PubMed

García, Gabriel J; Jara, Carlos A; Pomares, Jorge; Alabdo, Aiman; Poggi, Lucas M; Torres, Fernando

2014-03-31

The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc.), reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field.

Room temperature 1040fps, 1 megapixel photon-counting image sensor with 1.1um pixel pitch

NASA Astrophysics Data System (ADS)

Masoodian, S.; Ma, J.; Starkey, D.; Wang, T. J.; Yamashita, Y.; Fossum, E. R.

2017-05-01

A 1Mjot single-bit quanta image sensor (QIS) implemented in a stacked backside-illuminated (BSI) process is presented. This is the first work to report a megapixel photon-counting CMOS-type image sensor to the best of our knowledge. A QIS with 1.1μm pitch tapered-pump-gate jots is implemented with cluster-parallel readout, where each cluster of jots is associated with its own dedicated readout electronics stacked under the cluster. Power dissipation is reduced with this cluster readout because of the reduced column bus parasitic capacitance, which is important for the development of 1Gjot arrays. The QIS functions at 1040fps with binary readout and dissipates only 17.6mW, including I/O pads. The readout signal chain uses a fully differential charge-transfer amplifier (CTA) gain stage before a 1b-ADC to achieve an energy/bit FOM of 16.1pJ/b and 6.9pJ/b for the whole sensor and gain stage+ADC, respectively. Analog outputs with on-chip gain are implemented for pixel characterization purposes.

Development of an embedded atmospheric turbulence mitigation engine

NASA Astrophysics Data System (ADS)

Paolini, Aaron; Bonnett, James; Kozacik, Stephen; Kelmelis, Eric

2017-05-01

Methods to reconstruct pictures from imagery degraded by atmospheric turbulence have been under development for decades. The techniques were initially developed for observing astronomical phenomena from the Earth's surface, but have more recently been modified for ground and air surveillance scenarios. Such applications can impose significant constraints on deployment options because they both increase the computational complexity of the algorithms themselves and often dictate a requirement for low size, weight, and power (SWaP) form factors. Consequently, embedded implementations must be developed that can perform the necessary computations on low-SWaP platforms. Fortunately, there is an emerging class of embedded processors driven by the mobile and ubiquitous computing industries. We have leveraged these processors to develop embedded versions of the core atmospheric correction engine found in our ATCOM software. In this paper, we will present our experience adapting our algorithms for embedded systems on a chip (SoCs), namely the NVIDIA Tegra that couples general-purpose ARM cores with their graphics processing unit (GPU) technology and the Xilinx Zynq which pairs similar ARM cores with their field-programmable gate array (FPGA) fabric.

Two stage dual gate MESFET monolithic gain control amplifier for Ka-band

NASA Technical Reports Server (NTRS)

Sokolov, V.; Geddes, J.; Contolatis, A.

1987-01-01

A monolithic two stage gain control amplifier has been developed using submicron gate length dual gate MESFETs fabricated on ion implanted material. The amplifier has a gain of 12 dB at 30 GHz with a gain control range of over 30 dB. This ion implanted monolithic IC is readily integrable with other phased array receiver functions such as low noise amplifiers and phase shifters.

Chip-scale integrated optical interconnects: a key enabler for future high-performance computing

NASA Astrophysics Data System (ADS)

Haney, Michael; Nair, Rohit; Gu, Tian

2012-01-01

High Performance Computing (HPC) systems are putting ever-increasing demands on the throughput efficiency of their interconnection fabrics. In this paper, the limits of conventional metal trace-based inter-chip interconnect fabrics are examined in the context of state-of-the-art HPC systems, which currently operate near the 1 GFLOPS/W level. The analysis suggests that conventional metal trace interconnects will limit performance to approximately 6 GFLOPS/W in larger HPC systems that require many computer chips to be interconnected in parallel processing architectures. As the HPC communications bottlenecks push closer to the processing chips, integrated Optical Interconnect (OI) technology may provide the ultra-high bandwidths needed at the inter- and intra-chip levels. With inter-chip photonic link energies projected to be less than 1 pJ/bit, integrated OI is projected to enable HPC architecture scaling to the 50 GFLOPS/W level and beyond - providing a path to Peta-FLOPS-level HPC within a single rack, and potentially even Exa-FLOPSlevel HPC for large systems. A new hybrid integrated chip-scale OI approach is described and evaluated. The concept integrates a high-density polymer waveguide fabric directly on top of a multiple quantum well (MQW) modulator array that is area-bonded to the Silicon computing chip. Grayscale lithography is used to fabricate 5 μm x 5 μm polymer waveguides and associated novel small-footprint total internal reflection-based vertical input/output couplers directly onto a layer containing an array of GaAs MQW devices configured to be either absorption modulators or photodetectors. An external continuous wave optical "power supply" is coupled into the waveguide links. Contrast ratios were measured using a test rider chip in place of a Silicon processing chip. The results suggest that sub-pJ/b chip-scale communication is achievable with this concept. When integrated into high-density integrated optical interconnect fabrics, it could provide a seamless interconnect fabric spanning the intra-

Actuation of digital micro drops by electrowetting on open microfluidic chips fabricated in photolithography.

PubMed

Ko, Hyojin; Lee, Jeong Soo; Jung, Chan-Hee; Choi, Jae-Hak; Kwon, Oh-Sun; Shin, Kwanwoo

2014-08-01

Basic manipulations of discrete liquid drops on opened microfluidic chips based on electrowetting on dielectrics were described. While most developed microfluidic chips are closed systems equipped with a top plate to cover mechanically and to contact electrically to drop samples, our chips are opened systems with a single plate without any electric contact to drops directly. The chips consist of a linear array of patterned electrodes at 1.8 mm pitch was fabricated on a glass plate coated with thin hydrophobic and dielectric layers by using various methods including photolithography, spin coating and ion sputtering. Several actuations such as lateral oscillation, colliding mergence and translational motion for 3-10 μL water drops have been demonstrated satisfactory. All these kinetic performances of opened chips were similar to those of closed chip systems, indicating superiority of a none-contact method for the transport of drops on opened microfluidic chips actuated by using electrowetting technique.

The charge pump PLL clock generator designed for the 1.56 ns bin size time-to-digital converter pixel array of the Timepix3 readout ASIC

NASA Astrophysics Data System (ADS)

Fu, Y.; Brezina, C.; Desch, K.; Poikela, T.; Llopart, X.; Campbell, M.; Massimiliano, D.; Gromov, V.; Kluit, R.; van Beauzekom, M.; Zappon, F.; Zivkovic, V.

2014-01-01

Timepix3 is a newly developed pixel readout chip which is expected to be operated in a wide range of gaseous and silicon detectors. It is made of 256 × 256 pixels organized in a square pixel-array with 55 μm pitch. Oscillators running at 640 MHz are distributed across the pixel-array and allow for a highly accurate measurement of the arrival time of a hit. This paper concentrates on a low-jitter phase locked loop (PLL) that is located in the chip periphery. This PLL provides a control voltage which regulates the actual frequency of the individual oscillators, allowing for compensation of process, voltage, and temperature variations.

3D Nanochannel Array Platform for High-throughput Cell Manipulation and Nano-electroporation

NASA Astrophysics Data System (ADS)

Chang, Lingqian

Electroporation is one of the most common non-viral methods for gene delivery. Recent progress in gene therapy has offered special opportunities to electroporation for in vitro and in vivo applications. However, conventional bulk electroporation (BEP) inevitably causes serious cell damage and stochastic transfection between cells. Microfluidic electroporation (MEP) has been claimed to provide benign single cell transfection for the last decade. Nevertheless, the intracellular transport in both MEP and BEP systems is highly diffusion-dominant, which prevents precise dose control and high uniformity. In this Ph.D. research, we developed a 3D nanochannel-electroporation (3D NEP) platform for mass cell transfection. A silicon-based nanochannel array (3D NEP) chip was designed and fabricated for cell manipulation and electroporation. The chip, designed as Z-directional microchannel - nanochannel array, was fabricated by clean room techniques including projection photolithography and deep reactive-ion etching (DRIE). The fabricated 3D NEP chip is capable of handling 40,000 cells per 1 cm2, up to 1 million per wafer (100 mm diameter). High-throughput cell manipulation technologies were investigated for precise alignment of individual cells to the nanochannel array, a key step for NEP to achieve dose control. We developed three techniques for cell trapping in this work. (1) Magnetic tweezers (MTs) were integrated on the chip to remotely control cells under a programmed magnetic field. (2) A positive dielectrophoresis (pDEP) power system was built as an alternative to trap cells onto the nanochannel array using DEP force. (3) A novel yet simple 'dipping-trap' method was used to rapidly trap cells onto a nanochannel array, aligned by a micro-cap array pattern on the 3D NEP chip, which eventually offered 70 - 90 % trapping efficiency and 90 % specificity. 3D NEP platforms were assembled for cell transfection based on the Si-based nanochannel array chip and cell manipulation techniques. Cells were patterned on the nanochannel array and collectively were electroporated in parallel, injected with cargo in Z-direction. Controlling the dose was demonstrated with the external pulse durations at high-throughput. The 'electrophoretic'- expedited delivery of large molecular weight plasmids were demonstrated with large numbers of primary cells simultaneously, which cannot be achieved in BEP and MEP. Two clinically valuable case studies were performed with our 3D NEP for living cell sensing / interrogation. (1) In the case of in vitro transfection of primary cardiomyocytes, we studied the dose-effects of miR-29 on mitochondrial changes and the suppression of the Mcl-1 gene in adult mouse cardiomyocytes by precisely controlling the miR-29 dose injected. (2) Glioma stem cells (GSCs), a type of cell hypothesized to be highly aggressive and to lead to the relapses of gliobastoma in human brain, was studied at single cell resolution on 3D NEP platform. The developed 3D NEP system moves towards clinically oriented and user-friendly tools for life science applications. The batch-treated cells with controlled dosage delivery provide a useful tool for single cell analysis. The pioneering experiments in this work have demonstrated the 3D NEP for the applications of cell reprogramming, adoptive immunotherapy, in vitro cardiomyocytes transfection and glioma stem cells study.

Golden Gate Assembly of CRISPR gRNA expression array for simultaneously targeting multiple genes.

PubMed

Vad-Nielsen, Johan; Lin, Lin; Bolund, Lars; Nielsen, Anders Lade; Luo, Yonglun

2016-11-01

The engineered CRISPR/Cas9 technology has developed as the most efficient and broadly used genome editing tool. However, simultaneously targeting multiple genes (or genomic loci) in the same individual cells using CRISPR/Cas9 remain one technical challenge. In this article, we have developed a Golden Gate Assembly method for the generation of CRISPR gRNA expression arrays, thus enabling simultaneous gene targeting. Using this method, the generation of CRISPR gRNA expression array can be accomplished in 2 weeks, and contains up to 30 gRNA expression cassettes. We demonstrated in the study that simultaneously targeting 10 genomic loci or simultaneously inhibition of multiple endogenous genes could be achieved using the multiplexed gRNA expression array vector in human cells. The complete set of plasmids is available through the non-profit plasmid repository Addgene.

Fully parallel write/read in resistive synaptic array for accelerating on-chip learning

NASA Astrophysics Data System (ADS)

Gao, Ligang; Wang, I.-Ting; Chen, Pai-Yu; Vrudhula, Sarma; Seo, Jae-sun; Cao, Yu; Hou, Tuo-Hung; Yu, Shimeng

2015-11-01

A neuro-inspired computing paradigm beyond the von Neumann architecture is emerging and it generally takes advantage of massive parallelism and is aimed at complex tasks that involve intelligence and learning. The cross-point array architecture with synaptic devices has been proposed for on-chip implementation of the weighted sum and weight update in the learning algorithms. In this work, forming-free, silicon-process-compatible Ta/TaO x /TiO2/Ti synaptic devices are fabricated, in which >200 levels of conductance states could be continuously tuned by identical programming pulses. In order to demonstrate the advantages of parallelism of the cross-point array architecture, a novel fully parallel write scheme is designed and experimentally demonstrated in a small-scale crossbar array to accelerate the weight update in the training process, at a speed that is independent of the array size. Compared to the conventional row-by-row write scheme, it achieves >30× speed-up and >30× improvement in energy efficiency as projected in a large-scale array. If realistic synaptic device characteristics such as device variations are taken into an array-level simulation, the proposed array architecture is able to achieve ∼95% recognition accuracy of MNIST handwritten digits, which is close to the accuracy achieved by software using the ideal sparse coding algorithm.

On-chip concentration of bacteria using a 3D dielectrophoretic chip and subsequent laser-based DNA extraction in the same chip

NASA Astrophysics Data System (ADS)

Cho, Yoon-Kyoung; Kim, Tae-hyeong; Lee, Jeong-Gun

2010-06-01

We report the on-chip concentration of bacteria using a dielectrophoretic (DEP) chip with 3D electrodes and subsequent laser-based DNA extraction in the same chip. The DEP chip has a set of interdigitated Au post electrodes with 50 µm height to generate a network of non-uniform electric fields for the efficient trapping by DEP. The metal post array was fabricated by photolithography and subsequent Ni and Au electroplating. Three model bacteria samples (Escherichia coli, Staphylococcus epidermidis, Streptococcus mutans) were tested and over 80-fold concentrations were achieved within 2 min. Subsequently, on-chip DNA extraction from the concentrated bacteria in the 3D DEP chip was performed by laser irradiation using the laser-irradiated magnetic bead system (LIMBS) in the same chip. The extracted DNA was analyzed with silicon chip-based real-time polymerase chain reaction (PCR). The total process of on-chip bacteria concentration and the subsequent DNA extraction can be completed within 10 min including the manual operation time.

Flip Chip on Organic Substrates: A Feasibility Study for Space Applications

DTIC Science & Technology

2017-03-01

scheme, a 1752 I/O land grid array (LGA) package with decoupling capacitors, heat sink and optional column attach [1] as shown in Figure 1...investigated the effect of moisture and current loading on the Class Y flip chip on ceramic reliability [ 2 ]. The UT1752FC Class Y technology has...chip assembly to ceramic test substrates, the FA10 die are assembled to build-up organic test substrates as shown in Figure 2 . These assemblies

Micromagnet arrays for on-chip focusing, switching, and separation of superparamagnetic beads and single cells.

PubMed

Rampini, S; Kilinc, D; Li, P; Monteil, C; Gandhi, D; Lee, G U

2015-08-21

Nonlinear magnetophoresis (NLM) is a novel approach for on-chip transport and separation of superparamagnetic (SPM) beads, based on a travelling magnetic field wave generated by the combination of a micromagnet array (MMA) and an applied rotating magnetic field. Here, we present two novel MMA designs that allow SPM beads to be focused, sorted, and separated on-chip. Converging MMAs were used to rapidly collect the SPM beads from a large region of the chip and focus them into synchronised lines. We characterise the collection efficiency of the devices and demonstrate that they can facilitate on-chip analysis of populations of SPM beads using a single-point optical detector. The diverging MMAs were used to control the transport of the beads and to separate them based on their size. The separation efficiency of these devices was determined by the orientation of the magnetisation of the micromagnets relative to the external magnetic field and the size of the beads and relative to that of micromagnets. By controlling these parameters and the rotation of the external magnetic field we demonstrated the controlled transport of SPM bead-labelled single MDA-MB-231 cells. The use of these novel MMAs promises to allow magnetically-labelled cells to be efficiently isolated and then manipulated on-chip for analysis with high-resolution chemical and physical techniques.

High-resolution depth profiling using a range-gated CMOS SPAD quanta image sensor.

PubMed

Ren, Ximing; Connolly, Peter W R; Halimi, Abderrahim; Altmann, Yoann; McLaughlin, Stephen; Gyongy, Istvan; Henderson, Robert K; Buller, Gerald S

2018-03-05

A CMOS single-photon avalanche diode (SPAD) quanta image sensor is used to reconstruct depth and intensity profiles when operating in a range-gated mode used in conjunction with pulsed laser illumination. By designing the CMOS SPAD array to acquire photons within a pre-determined temporal gate, the need for timing circuitry was avoided and it was therefore possible to have an enhanced fill factor (61% in this case) and a frame rate (100,000 frames per second) that is more difficult to achieve in a SPAD array which uses time-correlated single-photon counting. When coupled with appropriate image reconstruction algorithms, millimeter resolution depth profiles were achieved by iterating through a sequence of temporal delay steps in synchronization with laser illumination pulses. For photon data with high signal-to-noise ratios, depth images with millimeter scale depth uncertainty can be estimated using a standard cross-correlation approach. To enhance the estimation of depth and intensity images in the sparse photon regime, we used a bespoke clustering-based image restoration strategy, taking into account the binomial statistics of the photon data and non-local spatial correlations within the scene. For sparse photon data with total exposure times of 75 ms or less, the bespoke algorithm can reconstruct depth images with millimeter scale depth uncertainty at a stand-off distance of approximately 2 meters. We demonstrate a new approach to single-photon depth and intensity profiling using different target scenes, taking full advantage of the high fill-factor, high frame rate and large array format of this range-gated CMOS SPAD array.

3-D readout-electronics packaging for high-bandwidth massively paralleled imager

DOEpatents

Kwiatkowski, Kris; Lyke, James

2007-12-18

Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a "mirror cube"). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a 45.degree. angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.

TU-E-BRB-08: Dual Gated Volumetric Modulated Arc Therapy.

PubMed

Wu, J; Fahimian, B; Wu, H; Xing, L

2012-06-01

Gated Volumetric Modulated Arc Therapy (VMAT) is an emerging treatment modality for Stereotactic Body Radiotherapy (SBRT). However, gating significantly prolongs treatment time. In order to enhance treatment efficiency, a novel dual gated VMAT, in which dynamic arc deliveries are executed sequentially in alternating exhale and inhale phases, is proposed and evaluated experimentally. The essence of dual gated VMAT is to take advantage of the natural pauses that occur at inspiration and exhalation by alternatively delivering the dose at the two phases, instead of the exhale window only. The arc deliveries at the two phases are realized by rotating gantry forward at the exhale window and backward at the inhale in an alternative fashion. Custom XML scripts were developed in Varian's TrueBeam STx Developer Mode to enable dual gated VMAT delivery. RapidArc plans for a lung case were generated for both inhale and exhale phases. The two plans were then combined into a dual gated arc by interleaving the arc treatment nodes of the two RapidArc plans. The dual gated plan was delivered in the development mode of TrueBeam LINAC onto a motion phantom and the delivery was measured by using pinpoint chamber/film/diode array (delta 4). The measured dose distribution was compared with that computed using Eclipse AAA algorithm. The treatment delivery time was recorded and compared with the corresponding single gated plans. Relative to the corresponding single gated delivery, it was found that treatment time efficiency was improved by 95.5% for the case studied here. Pinpoint chamber absolute dose measurement agreed the calculation to within 0.7%. Diode chamber array measurements revealed that 97.5% of measurement points of dual gated RapidArc delivery passed the 3% and 3mm gamma-test criterion. A dual gated VMAT treatment has been developed and implemented successfully with nearly doubled treatment delivery efficiency. © 2012 American Association of Physicists in Medicine.

Development of chip passivated monolithic complementary MISFET circuits with beam leads

NASA Technical Reports Server (NTRS)

Ragonese, L. J.; Kim, M. J.; Corrie, B. L.; Brouillette, J. W.; Warr, R. E.

1972-01-01

The results are presented of a program to demonstrate the processes for fabricating complementary MISFET beam-leaded circuits, which, potentially, are comparable in quality to available bipolar beam-lead chips that use silicon nitride passivation in conjunction with a platinum-titanium-gold metal system. Materials and techniques, different from the bipolar case, were used in order to be more compatible with the special requirements of fully passivated complementary MISFET devices. Two types of circuits were designed and fabricated, a D-flip-flop and a three-input NOR/NAND gate. Fifty beam-leaded chips of each type were constructed. A quality and reliability assurance program was performed to identify failure mechanisms. Sample tests and inspections (including destructive) were developed to measure the physical characteristics of the circuits.

Resonant tunneling of 1-dimensional electrons across an array of 3-dimensionally confined potential wells

NASA Astrophysics Data System (ADS)

Allee, D. R.; Chou, S. Y.; Harris, J. S.; Pease, R. F. W.

A lateral resonant tunneling field effect transistor has been fabricated with a gate electrode in the form of a railway such that the two rails form a lateral double barrier potential at the GaAs/AlGaAs interface. The ties confine the electrons in the third dimension forming an array of potential boxes or three dimensionally confined potential wells. The width of the ties and rails is 50nm; the spacings between the ties and between the two rails are 230nm and 150nm respectively. The ties are 750nm long and extend beyond the the two rails forming one dimensional wires on either side. Conductance oscillations are observed in the drain current at 4.2K as the gate voltage is scanned. Comparison with devices with a solid gate, and with a monorail gate with ties fabricated on the same wafer suggest that these conductance oscillations are electron resonant tunneling from one dimensional wires through the quasi-bound states of the three dimensionally confined potential wells. Comparison with a device with a two rail gate without ties (previously published) indicates that additional confinement due to the ties enhances the strength of the conductance oscillations.

Comparison between genotyping by sequencing and SNP-chip genotyping in QTL mapping in wheat

USDA-ARS?s Scientific Manuscript database

Array- or chip-based single nucleotide polymorphism (SNP) markers are widely used in genomic studies because of their abundance in a genome and cost less per data point compared to older marker technologies. Genotyping by sequencing (GBS), a relatively newer approach of genotyping, suggests equal or...

Yield and Production Properties of Wood chips and Particles Torrefied in a Crucible Furnace Retort

Treesearch

Thomas L. Eberhardt; Chi-Leung So; Karen G. Reed

2016-01-01

Biomass preprocessing by torrefaction improves feedstock consistency and thereby improves the efficiency of biofuels operations, including pyrolysis, gasification, and combustion. A crucible furnace retort was fabricated of sufficient size to handle a commercially available wood chip feedstock. Varying the torrefaction times and temperatures provided an array of...

Microarrays (DNA Chips) for the Classroom Laboratory

ERIC Educational Resources Information Center

Barnard, Betsy; Sussman, Michael; BonDurant, Sandra Splinter; Nienhuis, James; Krysan, Patrick

2006-01-01

We have developed and optimized the necessary laboratory materials to make DNA microarray technology accessible to all high school students at a fraction of both cost and data size. The primary component is a DNA chip/array that students "print" by hand and then analyze using research tools that have been adapted for classroom use. The…

A Microwell-Printing Fabrication Strategy for the On-Chip Templated Biosynthesis of Protein Microarrays for Surface Plasmon Resonance Imaging

PubMed Central

Manuel, Gerald; Lupták, Andrej; Corn, Robert M.

2017-01-01

A two-step templated, ribosomal biosynthesis/printing method for the fabrication of protein microarrays for surface plasmon resonance imaging (SPRI) measurements is demonstrated. In the first step, a sixteen component microarray of proteins is created in microwells by cell free on chip protein synthesis; each microwell contains both an in vitro transcription and translation (IVTT) solution and 350 femtomoles of a specific DNA template sequence that together are used to create approximately 40 picomoles of a specific hexahistidine-tagged protein. In the second step, the protein microwell array is used to contact print one or more protein microarrays onto nitrilotriacetic acid (NTA)-functionalized gold thin film SPRI chips for real-time SPRI surface bioaffinity adsorption measurements. Even though each microwell array element only contains approximately 40 picomoles of protein, the concentration is sufficiently high for the efficient bioaffinity adsorption and capture of the approximately 100 femtomoles of hexahistidine-tagged protein required to create each SPRI microarray element. As a first example, the protein biosynthesis process is verified with fluorescence imaging measurements of a microwell array containing His-tagged green fluorescent protein (GFP), yellow fluorescent protein (YFP) and mCherry (RFP), and then the fidelity of SPRI chips printed from this protein microwell array is ascertained by measuring the real-time adsorption of various antibodies specific to these three structurally related proteins. This greatly simplified two-step synthesis/printing fabrication methodology eliminates most of the handling, purification and processing steps normally required in the synthesis of multiple protein probes, and enables the rapid fabrication of SPRI protein microarrays from DNA templates for the study of protein-protein bioaffinity interactions. PMID:28706572

Ion channels in artificial bolaamphiphile membranes deposited on sensor chips: optical detection in an ion-channel-based biosensor

NASA Astrophysics Data System (ADS)

Schalkhammer, Thomas G. M.; Weiss-Wichert, Christof; Smetazko, Michaela M.; Valina-Saba, Miriam

1997-06-01

Signal amplification using labels should be replaced by a technique monitoring the biochemical binding event directly. The use of a ligand coupled to an artificial gated membrane ion channel is a new promising strategy. Binding of protein- or DNA/RNA-analytes at ligand modified peptide channels results in an on/off-response of the channel current due to channel closure or distortion. The sensor consists of stable transmembrane channels with a ligand bound covalently at the peptide channel entrance, a sensor chip with a photostructurized hydrophobic polymer frame, a hydrophilic ion conducting membrane support, a lipid membrane incorporating the engineered ion channels, and a current amplifier or a sensitive fluorescence monitor. Detection of channel opening or closure can ether be obtained by directly monitoring membrane conductivity or a transient change of pH or ion concentration within the membrane compartment. This change can be induced by electrochemical or optical means and its decay is directly correlated to the permeability of the membrane. The ion concentration in the sub membrane compartment was monitored by incorporation of fluorescent indicator dyes. To obtain the stable sensor membrane the lipid layer had to be attached on a support and the floating of the second lipid membrane on top of the first one had to be prevented. Both problems do not occur using our new circular C44-C76 bolaamphiphilic lipids consisting of a long hydrophobic core region and two hydrophilic heads. Use of maleic ester-head groups enabled us to easily modify the lipids with amines, thioles, alcohols, phosphates, boronic acid as well as fluorescent dyes. The properties of these membranes were studied using LB and fluorescence techniques. Based on this detection principle miniaturized sensor chips with significantly enhanced sensitivity and large multi analyte arrays are under construction.

A dry-cooled AC quantum voltmeter

NASA Astrophysics Data System (ADS)

Schubert, M.; Starkloff, M.; Peiselt, K.; Anders, S.; Knipper, R.; Lee, J.; Behr, R.; Palafox, L.; Böck, A. C.; Schaidhammer, L.; Fleischmann, P. M.; Meyer, H.-G.

2016-10-01

The paper describes a dry-cooled AC quantum voltmeter system operated up to kilohertz frequencies and 7 V rms. A 10 V programmable Josephson voltage standard (PJVS) array was installed on a pulse tube cooler (PTC) driven with a 4 kW air-cooled compressor. The operating margins at 70 GHz frequencies were investigated in detail and found to exceed 1 mA Shapiro step width. A key factor for the successful chip operation was the low on-chip power consumption of 65 mW in total. A thermal interface between PJVS chip and PTC cold stage was used to avoid a significant chip overheating. By installing the cryocooled PJVS array into an AC quantum voltmeter setup, several calibration measurements of dc standards and calibrator ac voltages up to 2 kHz frequencies were carried out to demonstrate the full functionality. The results are discussed and compared to systems with standard liquid helium cooling. For dc voltages, a direct comparison measurement between the dry-cooled AC quantum voltmeter and a liquid-helium based 10 V PJVS shows an agreement better than 1 part in 1010.

Two-Volt Josephson Arbitrary Waveform Synthesizer Using Wilkinson Dividers.

PubMed

Flowers-Jacobs, Nathan E; Fox, Anna E; Dresselhaus, Paul D; Schwall, Robert E; Benz, Samuel P

2016-09-01

The root-mean-square (rms) output voltage of the NIST Josephson arbitrary waveform synthesizer (JAWS) has been doubled from 1 V to a record 2 V by combining two new 1 V chips on a cryocooler. This higher voltage will improve calibrations of ac thermal voltage converters and precision voltage measurements that require state-of-the-art quantum accuracy, stability, and signal-to-noise ratio. We achieved this increase in output voltage by using four on-chip Wilkinson dividers and eight inner-outer dc blocks, which enable biasing of eight Josephson junction (JJ) arrays with high-speed inputs from only four high-speed pulse generator channels. This approach halves the number of pulse generator channels required in future JAWS systems. We also implemented on-chip superconducting interconnects between JJ arrays, which reduces systematic errors and enables a new modular chip package. Finally, we demonstrate a new technique for measuring and visualizing the operating current range that reduces the measurement time by almost two orders of magnitude and reveals the relationship between distortion in the output spectrum and output pulse sequence errors.

Read disturb errors in a CMOS static RAM chip. [radiation hardened for spacedraft

NASA Technical Reports Server (NTRS)

Wood, Steven H.; Marr, James C., IV; Nguyen, Tien T.; Padgett, Dwayne J.; Tran, Joe C.; Griswold, Thomas W.; Lebowitz, Daniel C.

1989-01-01

Results are reported from an extensive investigation into pattern-sensitive soft errors (read disturb errors) in the TCC244 CMOS static RAM chip. The TCC244, also known as the SA2838, is a radiation-hard single-event-upset-resistant 4 x 256 memory chip. This device is being used by the Jet Propulsion Laboratory in the Galileo and Magellan spacecraft, which will have encounters with Jupiter and Venus, respectively. Two aspects of the part's design are shown to result in the occurrence of read disturb errors: the transparence of the signal path from the address pins to the array of cells, and the large resistance in the Vdd and Vss lines of the cells in the center of the array. Probe measurements taken during a read disturb failure illustrate how address skews and the data pattern in the chip combine to produce a bit flip. A capacitive charge pump formed by the individual cell capacitances and the resistance in the supply lines pumps down both the internal cell voltage and the local supply voltage until a bit flip occurs.

Increasing Electrochemiluminescence Intensity of a Wireless Electrode Array Chip by Thousands of Times Using a Diode for Sensitive Visual Detection by a Digital Camera.

PubMed

Qi, Liming; Xia, Yong; Qi, Wenjing; Gao, Wenyue; Wu, Fengxia; Xu, Guobao

2016-01-19

Both a wireless electrochemiluminescence (ECL) electrode microarray chip and the dramatic increase in ECL by embedding a diode in an electromagnetic receiver coil have been first reported. The newly designed device consists of a chip and a transmitter. The chip has an electromagnetic receiver coil, a mini-diode, and a gold electrode array. The mini-diode can rectify alternating current into direct current and thus enhance ECL intensities by 18 thousand times, enabling a sensitive visual detection using common cameras or smart phones as low cost detectors. The detection limit of hydrogen peroxide using a digital camera is comparable to that using photomultiplier tube (PMT)-based detectors. Coupled with a PMT-based detector, the device can detect luminol with higher sensitivity with linear ranges from 10 nM to 1 mM. Because of the advantages including high sensitivity, high throughput, low cost, high portability, and simplicity, it is promising in point of care testing, drug screening, and high throughput analysis.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Becker, Julian; Tate, Mark W.; Shanks, Katherine S.

Pixel Array Detectors (PADs) consist of an x-ray sensor layer bonded pixel-by-pixel to an underlying readout chip. This approach allows both the sensor and the custom pixel electronics to be tailored independently to best match the x-ray imaging requirements. Here we describe the hybridization of CdTe sensors to two different charge-integrating readout chips, the Keck PAD and the Mixed-Mode PAD (MM-PAD), both developed previously in our laboratory. The charge-integrating architecture of each of these PADs extends the instantaneous counting rate by many orders of magnitude beyond that obtainable with photon counting architectures. The Keck PAD chip consists of rapid, 8-frame,more » in-pixel storage elements with framing periods <150 ns. The second detector, the MM-PAD, has an extended dynamic range by utilizing an in-pixel overflow counter coupled with charge removal circuitry activated at each overflow. This allows the recording of signals from the single-photon level to tens of millions of x-rays/pixel/frame while framing at 1 kHz. Both detector chips consist of a 128×128 pixel array with (150 µm){sup 2} pixels.« less

Laser micromachining of biofactory-on-a-chip devices

NASA Astrophysics Data System (ADS)

Burt, Julian P.; Goater, Andrew D.; Hayden, Christopher J.; Tame, John A.

2002-06-01

Excimer laser micromachining provides a flexible means for the manufacture and rapid prototyping of miniaturized systems such as Biofactory-on-a-Chip devices. Biofactories are miniaturized diagnostic devices capable of characterizing, manipulating, separating and sorting suspension of particles such as biological cells. Such systems operate by exploiting the electrical properties of microparticles and controlling particle movement in AC non- uniform stationary and moving electric fields. Applications of Biofactory devices are diverse and include, among others, the healthcare, pharmaceutical, chemical processing, environmental monitoring and food diagnostic markets. To achieve such characterization and separation, Biofactory devices employ laboratory-on-a-chip type components such as complex multilayer microelectrode arrays, microfluidic channels, manifold systems and on-chip detection systems. Here we discuss the manufacturing requirements of Biofactory devices and describe the use of different excimer laser micromachined methods both in stand-alone processes and also in conjunction with conventional fabrication processes such as photolithography and thermal molding. Particular attention is given to the production of large area multilayer microelectrode arrays and the manufacture of complex cross-section microfluidic channel systems for use in simple distribution and device interfacing.

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

NASA Astrophysics Data System (ADS)

Liu, Lintao; Gao, Yuhan; Deng, Jun

2017-11-01

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication. Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

Novel all-optical logic gate using an add/drop filter and intensity switch.

PubMed

Threepak, T; Mitatha, S; Yupapin, P P

2011-12-01

A novel design of all-optical logic device is proposed. An all-optical logic device system composes of an optical intensity switch and add/drop filter. The intensity switch is formed to switch signal by using the relationship between refraction angle and signal intensity. In operation, two input signals are coupled into one with some coupling loss and attenuation, in which the combination of add/drop with intensity switch produces the optical logic gate. The advantage is that the proposed device can operate the high speed logic function. Moreover, it uses low power consumption. Furthermore, by using the extremely small component, this design can be put into a single chip. Finally, we have successfully produced the all-optical logic gate that can generate the accurate AND and NOT operation results.

Face classification using electronic synapses

NASA Astrophysics Data System (ADS)

Yao, Peng; Wu, Huaqiang; Gao, Bin; Eryilmaz, Sukru Burc; Huang, Xueyao; Zhang, Wenqiang; Zhang, Qingtian; Deng, Ning; Shi, Luping; Wong, H.-S. Philip; Qian, He

2017-05-01

Conventional hardware platforms consume huge amount of energy for cognitive learning due to the data movement between the processor and the off-chip memory. Brain-inspired device technologies using analogue weight storage allow to complete cognitive tasks more efficiently. Here we present an analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials. The device shows bidirectional continuous weight modulation behaviour. Grey-scale face classification is experimentally demonstrated using an integrated 1024-cell array with parallel online training. The energy consumption within the analogue synapses for each iteration is 1,000 × (20 ×) lower compared to an implementation using Intel Xeon Phi processor with off-chip memory (with hypothetical on-chip digital resistive random access memory). The accuracy on test sets is close to the result using a central processing unit. These experimental results consolidate the feasibility of analogue synaptic array and pave the way toward building an energy efficient and large-scale neuromorphic system.

On-chip supercapacitors with ultrahigh volumetric performance based on electrochemically co-deposited CuO/polypyrrole nanosheet arrays

NASA Astrophysics Data System (ADS)

Qian, Tao; Zhou, Jinqiu; Xu, Na; Yang, Tingzhou; Shen, Xiaowei; Liu, Xuejun; Wu, Shishan; Yan, Chenglin

2015-10-01

We introduce a new method for fabricating unique on-chip supercapacitors based on CuO/polypyrrole core/shell nanosheet arrays by means of direct electrochemical co-deposition on interdigital-like electrodes. The prepared all-solid-state device demonstrates exceptionally high specific capacitance of 1275.5 F cm-3 (˜40 times larger than that of CuO-only supercapacitors) and high-energy-density of 28.35 mWh cm-3, which are both significantly greater than other solid-state supercapacitors. More importantly, the device maintains approximately 100% capacity retention at 2.5 A cm-3 after 3000 cycles. The in situ co-deposition of CuO/polypyrrole nanosheets on interdigital substrate enables effective charge transport, electrode fabrication integrity, and device integration. Because of their high energy, power density, and stable cycling stability, these newly developed on-chip supercapacitors permit fast, reliable applications in portable and miniaturized electronic devices.

Low-cost and easy-to-use "on-chip ELISA" for developing health-promoting foods.

PubMed

Hoshino, Fumihiko; Watanabe, Osamu; Wu, Xiaohong; Takimoto, Yosuke; Osawa, Toshihiko

2014-01-01

We have determined that a biological molecule can be physically immobilized on a polymer containing an azobenzene (azopolymer) using irradiating light. We immobilized antibodies and antigens on the surface of an azopolymer coated glass slide (antibody array) to establish "on-chip ELISAs". The assays used the flat-surface of a glass slide and could be applied to both sandwich and competitive ELISAs. The sensitivity and accuracy of the on-chip ELISA were similar to a conventional ELISA using a polystyrene plate. Using the assay system, we proved that representative oxidative-biomarkers could be simultaneously measured from uL of urine. That should realize low-cost study on animal or human, and accelerate development of health-promoting foods. So, this new concept antibody array has promising applications in proteomic studies, and could be used to examine biomarkers to investigate health-promoting food.

Multigigabit optical transceivers for high-data rate military applications

NASA Astrophysics Data System (ADS)

Catanzaro, Brian E.; Kuznia, Charlie

2012-01-01

Avionics has experienced an ever increasing demand for processing power and communication bandwidth. Currently deployed avionics systems require gigabit communication using opto-electronic transceivers connected with parallel optical fiber. Ultra Communications has developed a series of transceiver solutions combining ASIC technology with flip-chip bonding and advanced opto-mechanical molded optics. Ultra Communications custom high speed ASIC chips are developed using an SoS (silicon on sapphire) process. These circuits are flip chip bonded with sources (VCSEL arrays) and detectors (PIN diodes) to create an Opto-Electronic Integrated Circuit (OEIC). These have been combined with micro-optics assemblies to create transceivers with interfaces to standard fiber array (MT) cabling technology. We present an overview of the demands for transceivers in military applications and how new generation transceivers leverage both previous generation military optical transceivers as well as commercial high performance computing optical transceivers.

Face classification using electronic synapses.

PubMed

Yao, Peng; Wu, Huaqiang; Gao, Bin; Eryilmaz, Sukru Burc; Huang, Xueyao; Zhang, Wenqiang; Zhang, Qingtian; Deng, Ning; Shi, Luping; Wong, H-S Philip; Qian, He

2017-05-12

Conventional hardware platforms consume huge amount of energy for cognitive learning due to the data movement between the processor and the off-chip memory. Brain-inspired device technologies using analogue weight storage allow to complete cognitive tasks more efficiently. Here we present an analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials. The device shows bidirectional continuous weight modulation behaviour. Grey-scale face classification is experimentally demonstrated using an integrated 1024-cell array with parallel online training. The energy consumption within the analogue synapses for each iteration is 1,000 × (20 ×) lower compared to an implementation using Intel Xeon Phi processor with off-chip memory (with hypothetical on-chip digital resistive random access memory). The accuracy on test sets is close to the result using a central processing unit. These experimental results consolidate the feasibility of analogue synaptic array and pave the way toward building an energy efficient and large-scale neuromorphic system.

On-chip supercapacitors with ultrahigh volumetric performance based on electrochemically co-deposited CuO/polypyrrole nanosheet arrays.

PubMed

Qian, Tao; Zhou, Jinqiu; Xu, Na; Yang, Tingzhou; Shen, Xiaowei; Liu, Xuejun; Wu, Shishan; Yan, Chenglin

2015-10-23

We introduce a new method for fabricating unique on-chip supercapacitors based on CuO/polypyrrole core/shell nanosheet arrays by means of direct electrochemical co-deposition on interdigital-like electrodes. The prepared all-solid-state device demonstrates exceptionally high specific capacitance of 1275.5 F cm(-3) (∼40 times larger than that of CuO-only supercapacitors) and high-energy-density of 28.35 mWh cm(-3), which are both significantly greater than other solid-state supercapacitors. More importantly, the device maintains approximately 100% capacity retention at 2.5 A cm(-3) after 3000 cycles. The in situ co-deposition of CuO/polypyrrole nanosheets on interdigital substrate enables effective charge transport, electrode fabrication integrity, and device integration. Because of their high energy, power density, and stable cycling stability, these newly developed on-chip supercapacitors permit fast, reliable applications in portable and miniaturized electronic devices.

TID Effects of High-Z Material Spot Shields on FPGA Using MPTB Data

NASA Technical Reports Server (NTRS)

Hardage, Donna (Technical Monitor); Crain, S. H.; Mazur, J. E.; Looper, M. D.

2003-01-01

An experiment on the Microelectronics and Photonics Test Bed (MPTB) was testing lield programmable gate arrays using spot shields to extend the life of some of the devices being tested. It was expected that the unshielded parts would fail from a total ionizing dose (TID) and yet the opposite occurred. The data show that the devices failing from the TID effects are those with the spot shields attached. This effort is to determine the mechanism by which the environment is interacting with the high-Z material to enhance the TID in these field programmable gate arrays.

Note: The design of thin gap chamber simulation signal source based on field programmable gate array.

PubMed

Hu, Kun; Lu, Houbing; Wang, Xu; Li, Feng; Liang, Futian; Jin, Ge

2015-01-01

The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability.

Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong (Inventor); Herath, Jeffrey A. (Inventor)

2010-01-01

An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.

Note: The design of thin gap chamber simulation signal source based on field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hu, Kun; Wang, Xu; Li, Feng

The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability.