Direct protein detection with a nano-interdigitated array gate MOSFET.

PubMed

Tang, Xiaohui; Jonas, Alain M; Nysten, Bernard; Demoustier-Champagne, Sophie; Blondeau, Franoise; Prévot, Pierre-Paul; Pampin, Rémi; Godfroid, Edmond; Iñiguez, Benjamin; Colinge, Jean-Pierre; Raskin, Jean-Pierre; Flandre, Denis; Bayot, Vincent

2009-08-15

A new protein sensor is demonstrated by replacing the gate of a metal oxide semiconductor field effect transistor (MOSFET) with a nano-interdigitated array (nIDA). The sensor is able to detect the binding reaction of a typical antibody Ixodes ricinus immunosuppressor (anti-Iris) protein at a concentration lower than 1 ng/ml. The sensor exhibits a high selectivity and reproducible specific detection. We provide a simple model that describes the behavior of the sensor and explains the origin of its high sensitivity. The simulated and experimental results indicate that the drain current of nIDA-gate MOSFET sensor is significantly increased with the successive binding of the thiol layer, Iris and anti-Iris protein layers. It is found that the sensor detection limit can be improved by well optimizing the geometrical parameters of nIDA-gate MOSFET. This nanobiosensor, with real-time and label-free capabilities, can easily be used for the detection of other proteins, DNA, virus and cancer markers. Moreover, an on-chip associated electronics nearby the sensor can be integrated since its fabrication is compatible with complementary metal oxide semiconductor (CMOS) technology.

Transparently wrap-gated semiconductor nanowire arrays for studies of gate-controlled photoluminescence

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nylund, Gustav; Storm, Kristian; Torstensson, Henrik

2013-12-04

We present a technique to measure gate-controlled photoluminescence (PL) on arrays of semiconductor nanowire (NW) capacitors using a transparent film of Indium-Tin-Oxide (ITO) wrapping around the nanowires as the gate electrode. By tuning the wrap-gate voltage, it is possible to increase the PL peak intensity of an array of undoped InP NWs by more than an order of magnitude. The fine structure of the PL spectrum reveals three subpeaks whose relative peak intensities change with gate voltage. We interpret this as gate-controlled state-filling of luminescing quantum dot segments formed by zincblende stacking faults in the mainly wurtzite NW crystal structure.

A Field Programmable Gate Array-Based Reconfigurable Smart-Sensor Network for Wireless Monitoring of New Generation Computer Numerically Controlled Machines

PubMed Central

Moreno-Tapia, Sandra Veronica; Vera-Salas, Luis Alberto; Osornio-Rios, Roque Alfredo; Dominguez-Gonzalez, Aurelio; Stiharu, Ion; de Jesus Romero-Troncoso, Rene

2010-01-01

Computer numerically controlled (CNC) machines have evolved to adapt to increasing technological and industrial requirements. To cover these needs, new generation machines have to perform monitoring strategies by incorporating multiple sensors. Since in most of applications the online Processing of the variables is essential, the use of smart sensors is necessary. The contribution of this work is the development of a wireless network platform of reconfigurable smart sensors for CNC machine applications complying with the measurement requirements of new generation CNC machines. Four different smart sensors are put under test in the network and their corresponding signal processing techniques are implemented in a Field Programmable Gate Array (FPGA)-based sensor node. PMID:22163602

A field programmable gate array-based reconfigurable smart-sensor network for wireless monitoring of new generation computer numerically controlled machines.

PubMed

Moreno-Tapia, Sandra Veronica; Vera-Salas, Luis Alberto; Osornio-Rios, Roque Alfredo; Dominguez-Gonzalez, Aurelio; Stiharu, Ion; Romero-Troncoso, Rene de Jesus

2010-01-01

Computer numerically controlled (CNC) machines have evolved to adapt to increasing technological and industrial requirements. To cover these needs, new generation machines have to perform monitoring strategies by incorporating multiple sensors. Since in most of applications the online Processing of the variables is essential, the use of smart sensors is necessary. The contribution of this work is the development of a wireless network platform of reconfigurable smart sensors for CNC machine applications complying with the measurement requirements of new generation CNC machines. Four different smart sensors are put under test in the network and their corresponding signal processing techniques are implemented in a Field Programmable Gate Array (FPGA)-based sensor node.

37 CFR 211.4 - Registration of claims of protection in mask works.

Code of Federal Regulations, 2010 CFR

2010-07-01

... adding metal-connection layers to unpersonalized gate arrays may separately register the entire unpersonalized gate array and the custom metallization layers. Applicants seeking to register separately entire unpersonalized gate arrays or custom metallization layers should make the nature of their claim clear at Space 8...

Technology, design, simulation, and evaluation for SEP-hardened circuits

NASA Technical Reports Server (NTRS)

Adams, J. R.; Allred, D.; Barry, M.; Rudeck, P.; Woodruff, R.; Hoekstra, J.; Gardner, H.

1991-01-01

This paper describes the technology, design, simulation, and evaluation for improvement of the Single Event Phenomena (SEP) hardness of gate-array and SRAM cells. Through the use of design and processing techniques, it is possible to achieve an SEP error rate less than 1.0 x 10(exp -10) errors/bit-day for a 9O percent worst-case geosynchronous orbit environment.

A novel biomimetic sonarhead using beamforming technology to mimic bat echolocation.

PubMed

Steckel, Jan; Peremans, Herbert

2012-07-01

A novel biomimetic sonarhead has been developed to allow researchers of bat echolocation behavior and biomimetic sonar to perform experiments with a system similar to the bat¿s sensory system. The bat's echolocation-related transfer function (ERTF) is implemented using an array of receivers to implement the head-related transfer function (HRTF), and an array of emitters mounted on a cylindrical manifold to implement the emission pattern of the bat. The complete system is controlled by a field-programmable gate array (FPGA) based embedded system connected through a USB interface.

Radiation Hardened Electronics for Extreme Environments

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Watson, Michael D.

2007-01-01

The Radiation Hardened Electronics for Space Environments (RHESE) project consists of a series of tasks designed to develop and mature a broad spectrum of radiation hardened and low temperature electronics technologies. Three approaches are being taken to address radiation hardening: improved material hardness, design techniques to improve radiation tolerance, and software methods to improve radiation tolerance. Within these approaches various technology products are being addressed including Field Programmable Gate Arrays (FPGA), Field Programmable Analog Arrays (FPAA), MEMS Serial Processors, Reconfigurable Processors, and Parallel Processors. In addition to radiation hardening, low temperature extremes are addressed with a focus on material and design approaches.

Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)

DOEpatents

Asaad, Sameh W; Bellofatto, Ralph E; Brezzo, Bernard; Haymes, Charles L; Kapur, Mohit; Parker, Benjamin D; Roewer, Thomas; Tierno, Jose A

2014-01-28

A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.

Microsensor research

NASA Astrophysics Data System (ADS)

Hughes, R. C.; Drebing, C. G.

1990-04-01

The technology that led to very large scale integrated circuits on silicon chips also provides a basis for new microsensors that are small, inexpensive, low power, rugged, and reliable. Two examples of microsensors Sandia is developing that take advantage of this technology are the microelectronic chemical sensor array and the radiation sensing field effect transistor (RADFET). Increasingly, the technology of chemical sensing needs new microsensor concepts. Applications in this area include environmental monitoring, criminal investigations, and state-of-health monitoring, both for equipment and living things. Chemical microsensors can satisfy sensing needs in the industrial, consumer, aerospace, and defense sectors. The microelectronic chemical-sensor array may address some of these applications. We have fabricated six separate chemical gas sensing areas on the microelectronic chemical sensor array. By using different catalytic metals on the gate areas of the diodes, we can selectively sense several gases.

Population patch clamp electrophysiology: a breakthrough technology for ion channel screening.

PubMed

Dale, Tim J; Townsend, Claire; Hollands, Emma C; Trezise, Derek J

2007-10-01

Population patch clamp (PPC) is a novel high throughput planar array electrophysiology technique that allows ionic currents to be recorded from populations of cells under voltage clamp. For the drug discovery pharmacologist, PPC promises greater speed and precision than existing methods for screening compounds at voltage-gated ion channel targets. Moreover, certain constitutively active or slow-ligand gated channels that have hitherto proved challenging to screen with planar array electrophysiology (e.g. SK/IK channels) are now more accessible. In this article we review early findings using PPC and provide a perspective on its likely impact on ion channel drug discovery. To support this, we include some new data on ion channel assay duplexing and on modulator assays, approaches that have thus far not been described.

Image intensification; Proceedings of the Meeting, Los Angeles, CA, Jan. 17, 18, 1989

NASA Astrophysics Data System (ADS)

Csorba, Illes P.

Various papers on image intensification are presented. Individual topics discussed include: status of high-speed optical detector technologies, super second generation imge intensifier, gated image intensifiers and applications, resistive-anode position-sensing photomultiplier tube operational modeling, undersea imaging and target detection with gated image intensifier tubes, image intensifier modules for use with commercially available solid state cameras, specifying the components of an intensified solid state television camera, superconducting IR focal plane arrays, one-inch TV camera tube with very high resolution capacity, CCD-Digicon detector system performance parameters, high-resolution X-ray imaging device, high-output technology microchannel plate, preconditioning of microchannel plate stacks, recent advances in small-pore microchannel plate technology, performance of long-life curved channel microchannel plates, low-noise microchannel plates, development of a quartz envelope heater.

FPGA-based gating and logic for multichannel single photon counting

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pooser, Raphael C; Earl, Dennis Duncan; Evans, Philip G

2012-01-01

We present results characterizing multichannel InGaAs single photon detectors utilizing gated passive quenching circuits (GPQC), self-differencing techniques, and field programmable gate array (FPGA)-based logic for both diode gating and coincidence counting. Utilizing FPGAs for the diode gating frontend and the logic counting backend has the advantage of low cost compared to custom built logic circuits and current off-the-shelf detector technology. Further, FPGA logic counters have been shown to work well in quantum key distribution (QKD) test beds. Our setup combines multiple independent detector channels in a reconfigurable manner via an FPGA backend and post processing in order to perform coincidencemore » measurements between any two or more detector channels simultaneously. Using this method, states from a multi-photon polarization entangled source are detected and characterized via coincidence counting on the FPGA. Photons detection events are also processed by the quantum information toolkit for application testing (QITKAT)« less

Field Programmable Gate Array Control of Power Systems in Graduate Student Laboratories

DTIC Science & Technology

2008-03-01

NAVAL POSTGRADUATE SCHOOL MONTEREY, CALIFORNIA THESIS Approved for public release; distribution is unlimited FIELD PROGRAMMABLE...REPORT TYPE AND DATES COVERED Master’s Thesis 4. TITLE AND SUBTITLE Field Programmable Gate Array Control of Power Systems in Graduate Student...Electronics curriculum track is the development of a design center that explores Field Programmable Gate Array (FPGA) control of power electronics

Design of a Ferroelectric Programmable Logic Gate Array

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

2003-01-01

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

Orientation selectivity in a multi-gated organic electrochemical transistor

NASA Astrophysics Data System (ADS)

Gkoupidenis, Paschalis; Koutsouras, Dimitrios A.; Lonjaret, Thomas; Fairfield, Jessamyn A.; Malliaras, George G.

2016-06-01

Neuromorphic devices offer promising computational paradigms that transcend the limitations of conventional technologies. A prominent example, inspired by the workings of the brain, is spatiotemporal information processing. Here we demonstrate orientation selectivity, a spatiotemporal processing function of the visual cortex, using a poly(3,4ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) organic electrochemical transistor with multiple gates. Spatially distributed inputs on a gate electrode array are found to correlate with the output of the transistor, leading to the ability to discriminate between different stimuli orientations. The demonstration of spatiotemporal processing in an organic electronic device paves the way for neuromorphic devices with new form factors and a facile interface with biology.

Field application of smart SHM using field programmable gate array technology to monitor an RC bridge in New Mexico

NASA Astrophysics Data System (ADS)

Azarbayejani, M.; Jalalpour, M.; El-Osery, A. I.; Reda Taha, M. M.

2011-08-01

In this paper, an innovative field application of a structural health monitoring (SHM) system using field programmable gate array (FPGA) technology and wireless communication is presented. The new SHM system was installed to monitor a reinforced concrete (RC) bridge on Interstate 40 (I-40) in Tucumcari, New Mexico. This newly installed system allows continuous remote monitoring of this bridge using solar power. Details of the SHM component design and installation are discussed. The integration of FPGA and solar power technologies make it possible to remotely monitor infrastructure with limited access to power. Furthermore, the use of FPGA technology enables smart monitoring where data communication takes place on-need (when damage warning signs are met) and on-demand for periodic monitoring of the bridge. Such a system enables a significant cut in communication cost and power demands which are two challenges during SHM operation. Finally, a three-dimensional finite element (FE) model of the bridge was developed and calibrated using a static loading field test. This model is then used for simulating damage occurrence on the bridge. Using the proposed automation process for SHM will reduce human intervention significantly and can save millions of dollars currently spent on prescheduled inspection of critical infrastructure worldwide.

A CMOS Time-Resolved Fluorescence Lifetime Analysis Micro-System

PubMed Central

Rae, Bruce R.; Muir, Keith R.; Gong, Zheng; McKendry, Jonathan; Girkin, John M.; Gu, Erdan; Renshaw, David; Dawson, Martin D.; Henderson, Robert K.

2009-01-01

We describe a CMOS-based micro-system for time-resolved fluorescence lifetime analysis. It comprises a 16 × 4 array of single-photon avalanche diodes (SPADs) fabricated in 0.35 μm high-voltage CMOS technology with in-pixel time-gated photon counting circuitry and a second device incorporating an 8 × 8 AlInGaN blue micro-pixellated light-emitting diode (micro-LED) array bump-bonded to an equivalent array of LED drivers realized in a standard low-voltage 0.35 μm CMOS technology, capable of producing excitation pulses with a width of 777 ps (FWHM). This system replaces instrumentation based on lasers, photomultiplier tubes, bulk optics and discrete electronics with a PC-based micro-system. Demonstrator lifetime measurements of colloidal quantum dot and Rhodamine samples are presented. PMID:22291564

Developments of FPGA-based digital back-ends for low frequency antenna arrays at Medicina radio telescopes

NASA Astrophysics Data System (ADS)

Naldi, G.; Bartolini, M.; Mattana, A.; Pupillo, G.; Hickish, J.; Foster, G.; Bianchi, G.; Lingua, A.; Monari, J.; Montebugnoli, S.; Perini, F.; Rusticelli, S.; Schiaffino, M.; Virone, G.; Zarb Adami, K.

In radio astronomy Field Programmable Gate Array (FPGA) technology is largely used for the implementation of digital signal processing techniques applied to antenna arrays. This is mainly due to the good trade-off among computing resources, power consumption and cost offered by FPGA chip compared to other technologies like ASIC, GPU and CPU. In the last years several digital backend systems based on such devices have been developed at the Medicina radio astronomical station (INAF-IRA, Bologna, Italy). Instruments like FX correlator, direct imager, beamformer, multi-beam system have been successfully designed and realized on CASPER (Collaboration for Astronomy Signal Processing and Electronics Research, https://casper.berkeley.edu) processing boards. In this paper we present the gained experience in this kind of applications.

Topological horseshoe analysis and field-programmable gate array implementation of a fractional-order four-wing chaotic attractor

NASA Astrophysics Data System (ADS)

Dong, En-Zeng; Wang, Zhen; Yu, Xiao; Chen, Zeng-Qiang; Wang, Zeng-Hui

2018-01-01

Not Available Project supported by the National Natural Science Foundation of China (Grant Nos. 61502340 and 61374169), the Application Base and Frontier Technology Research Project of Tianjin, China (Grant No. 15JCYBJC51800), and the South African National Research Foundation Incentive Grants (Grant No. 81705).

Defense Industrial Base Assessment: U.S. Integrated Circuit Design and Fabrication Capability

DTIC Science & Technology

2009-05-01

in the U.S for the period 2003-2006, with projections to 2011.6 The resulting draft OTE survey was field tested for accuracy and usability with a...custom application specific integrated circuits (ASICs) to field programmable gate arrays (FPGAs). Companies of all sizes can manufacture these IC...able to design one-time Electronically Programmable Gate Arrays (EPGAs) while nine are able to design Field Programmable Gate Arrays (FPGAs). Eight

Integrated field emission array for ion desorption

DOEpatents

Resnick, Paul J; Hertz, Kristin L.; Holland, Christopher; Chichester, David

2016-08-23

An integrated field emission array for ion desorption includes an electrically conductive substrate; a dielectric layer lying over the electrically conductive substrate comprising a plurality of laterally separated cavities extending through the dielectric layer; a like plurality of conically-shaped emitter tips on posts, each emitter tip/post disposed concentrically within a laterally separated cavity and electrically contacting the substrate; and a gate electrode structure lying over the dielectric layer, including a like plurality of circular gate apertures, each gate aperture disposed concentrically above an emitter tip/post to provide a like plurality of annular gate electrodes and wherein the lower edge of each annular gate electrode proximate the like emitter tip/post is rounded. Also disclosed herein are methods for fabricating an integrated field emission array.

Integrated field emission array for ion desorption

DOEpatents

Resnick, Paul J; Hertz, Kristin L; Holland, Christopher; Chichester, David; Schwoebel, Paul

2013-09-17

An integrated field emission array for ion desorption includes an electrically conductive substrate; a dielectric layer lying over the electrically conductive substrate comprising a plurality of laterally separated cavities extending through the dielectric layer; a like plurality of conically-shaped emitter tips on posts, each emitter tip/post disposed concentrically within a laterally separated cavity and electrically contacting the substrate; and a gate electrode structure lying over the dielectric layer, including a like plurality of circular gate apertures, each gate aperture disposed concentrically above an emitter tip/post to provide a like plurality of annular gate electrodes and wherein the lower edge of each annular gate electrode proximate the like emitter tip/post is rounded. Also disclosed herein are methods for fabricating an integrated field emission array.

ECL gate array with integrated PLL-based clock recovery and synthesis for high-speed data and telecom applications

NASA Astrophysics Data System (ADS)

Rosky, David S.; Coy, Bruce H.; Friedmann, Marc D.

1992-03-01

A 2500 gate mixed signal gate array has been developed that integrates custom PLL-based clock recovery and clock synthesis functions with 2500 gates of configurable logic cells to provide a single chip solution for 200 - 1244 MHz fiber based digital interface applications. By customizing the digital logic cells, any of the popular telecom and datacom standards may be implemented.

Theory of the synchronous motion of an array of floating flap gates oscillating wave surge converter

NASA Astrophysics Data System (ADS)

Michele, Simone; Sammarco, Paolo; d'Errico, Michele

2016-08-01

We consider a finite array of floating flap gates oscillating wave surge converter (OWSC) in water of constant depth. The diffraction and radiation potentials are solved in terms of elliptical coordinates and Mathieu functions. Generated power and capture width ratio of a single gate excited by incoming waves are given in terms of the radiated wave amplitude in the far field. Similar to the case of axially symmetric absorbers, the maximum power extracted is shown to be directly proportional to the incident wave characteristics: energy flux, angle of incidence and wavelength. Accordingly, the capture width ratio is directly proportional to the wavelength, thus giving a design estimate of the maximum efficiency of the system. We then compare the array and the single gate in terms of energy production. For regular waves, we show that excitation of the out-of-phase natural modes of the array increases the power output, while in the case of random seas we show that the array and the single gate achieve the same efficiency.

Developing a gate-array capability at a research and development laboratory

NASA Astrophysics Data System (ADS)

Balch, J. W.; Current, K. W.; Magnuson, W. G., Jr.; Pocha, M. D.

1983-03-01

Experiences in developing a gate array capability for low volume applications in a research and development (R and D) laboratory are described. By purchasing unfinished wafers and doing the customization steps in-house. Turnaround time was shortened to as little as one week and the direct costs reduced to as low as $5K per design. Designs generally require fast turnaround (a few weeks to a few months) and very low volumes (1 to 25). Design costs must be kept at a minimum. After reviewing available commercial gate array design and fabrication services, it was determined that objectives would best be met by using existing internal integrated circuit fabrication facilities, the COMPUTERVISION interactive graphics layout system, and extensive computational capabilities. The reasons and the approach taken for; selection for a particular gate array wafer, adapting a particular logic simulation program, and how layout aids were enhanced are discussed. Testing of the customized chips is described. The content, schedule, and results of the internal gate array course recently completed are discussed. Finally, problem areas and near term plans are presented.

A digital optical phase-locked loop for diode lasers based on field programmable gate array.

PubMed

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382∕MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad(2) and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

NASA Astrophysics Data System (ADS)

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad2 and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

Field-programmable gate array implementation of an all-digital IEEE 802.15.4-compliant transceiver

NASA Astrophysics Data System (ADS)

Cornetta, Gianluca; Touhafi, Abdellah; Santos, David J.; Vázquez, José M.

2010-12-01

An architecture for a low-cost, low-complexity digital transceiver is presented in this article. The proposed architecture targets the IEEE 802.15.4 standard for short-range wireless personal area networks and has been implemented as a synthesisable VHDL register transfer level description. The system has been evaluated and tested using a Xilinx 90 nm Virtex-4 field-programmable gate array as the target technology. Bit error rate (BER) and error vector magnitude (EVM) have been used as the figures of merit for modem performance. Simulations show that the recommended minimum BER is achieved at E b/N 0 = 8.7 dB, whereas the EVM is 19.5%. The implemented device occupies 10% of the target FPGA and has a normalised maximum power consumption of 44 mW in transmit mode and 53 mW in receiver mode.

[Hardware Implementation of Numerical Simulation Function of Hodgkin-Huxley Model Neurons Action Potential Based on Field Programmable Gate Array].

PubMed

Wang, Jinlong; Lu, Mai; Hu, Yanwen; Chen, Xiaoqiang; Pan, Qiangqiang

2015-12-01

Neuron is the basic unit of the biological neural system. The Hodgkin-Huxley (HH) model is one of the most realistic neuron models on the electrophysiological characteristic description of neuron. Hardware implementation of neuron could provide new research ideas to clinical treatment of spinal cord injury, bionics and artificial intelligence. Based on the HH model neuron and the DSP Builder technology, in the present study, a single HH model neuron hardware implementation was completed in Field Programmable Gate Array (FPGA). The neuron implemented in FPGA was stimulated by different types of current, the action potential response characteristics were analyzed, and the correlation coefficient between numerical simulation result and hardware implementation result were calculated. The results showed that neuronal action potential response of FPGA was highly consistent with numerical simulation result. This work lays the foundation for hardware implementation of neural network.

Multiplexed charge-locking device for large arrays of quantum devices

NASA Astrophysics Data System (ADS)

Puddy, R. K.; Smith, L. W.; Al-Taie, H.; Chong, C. H.; Farrer, I.; Griffiths, J. P.; Ritchie, D. A.; Kelly, M. J.; Pepper, M.; Smith, C. G.

2015-10-01

We present a method of forming and controlling large arrays of gate-defined quantum devices. The method uses an on-chip, multiplexed charge-locking system and helps to overcome the restraints imposed by the number of wires available in cryostat measurement systems. The device architecture that we describe here utilises a multiplexer-type scheme to lock charge onto gate electrodes. The design allows access to and control of gates whose total number exceeds that of the available electrical contacts and enables the formation, modulation and measurement of large arrays of quantum devices. We fabricate such devices on n-type GaAs/AlGaAs substrates and investigate the stability of the charge locked on to the gates. Proof-of-concept is shown by measurement of the Coulomb blockade peaks of a single quantum dot formed by a floating gate in the device. The floating gate is seen to drift by approximately one Coulomb oscillation per hour.

Compiling for Application Specific Computational Acceleration in Reconfigurable Architectures Final Report CRADA No. TSB-2033-01

DOE Office of Scientific and Technical Information (OSTI.GOV)

De Supinski, B.; Caliga, D.

2017-09-28

The primary objective of this project was to develop memory optimization technology to efficiently deliver data to, and distribute data within, the SRC-6's Field Programmable Gate Array- ("FPGA") based Multi-Adaptive Processors (MAPs). The hardware/software approach was to explore efficient MAP configurations and generate the compiler technology to exploit those configurations. This memory accessing technology represents an important step towards making reconfigurable symmetric multi-processor (SMP) architectures that will be a costeffective solution for large-scale scientific computing.

Measurement of transverse emittance and coherence of double-gate field emitter array cathodes

PubMed Central

Tsujino, Soichiro; Das Kanungo, Prat; Monshipouri, Mahta; Lee, Chiwon; Miller, R.J. Dwayne

2016-01-01

Achieving small transverse beam emittance is important for high brightness cathodes for free electron lasers and electron diffraction and imaging experiments. Double-gate field emitter arrays with on-chip focussing electrode, operating with electrical switching or near infrared laser excitation, have been studied as cathodes that are competitive with photocathodes excited by ultraviolet lasers, but the experimental demonstration of the low emittance has been elusive. Here we demonstrate this for a field emitter array with an optimized double-gate structure by directly measuring the beam characteristics. Further we show the successful application of the double-gate field emitter array to observe the low-energy electron beam diffraction from suspended graphene in minimal setup. The observed low emittance and long coherence length are in good agreement with theory. These results demonstrate that our all-metal double-gate field emitters are highly promising for applications that demand extremely low-electron bunch-phase space volume and large transverse coherence. PMID:28008918

Measurement of transverse emittance and coherence of double-gate field emitter array cathodes

NASA Astrophysics Data System (ADS)

Tsujino, Soichiro; Das Kanungo, Prat; Monshipouri, Mahta; Lee, Chiwon; Miller, R. J. Dwayne

2016-12-01

Achieving small transverse beam emittance is important for high brightness cathodes for free electron lasers and electron diffraction and imaging experiments. Double-gate field emitter arrays with on-chip focussing electrode, operating with electrical switching or near infrared laser excitation, have been studied as cathodes that are competitive with photocathodes excited by ultraviolet lasers, but the experimental demonstration of the low emittance has been elusive. Here we demonstrate this for a field emitter array with an optimized double-gate structure by directly measuring the beam characteristics. Further we show the successful application of the double-gate field emitter array to observe the low-energy electron beam diffraction from suspended graphene in minimal setup. The observed low emittance and long coherence length are in good agreement with theory. These results demonstrate that our all-metal double-gate field emitters are highly promising for applications that demand extremely low-electron bunch-phase space volume and large transverse coherence.

An Improved Scheduling Algorithm for Data Transmission in Ultrasonic Phased Arrays with Multi-Group Ultrasonic Sensors

PubMed Central

Tang, Wenming; Liu, Guixiong; Li, Yuzhong; Tan, Daji

2017-01-01

High data transmission efficiency is a key requirement for an ultrasonic phased array with multi-group ultrasonic sensors. Here, a novel FIFOs scheduling algorithm was proposed and the data transmission efficiency with hardware technology was improved. This algorithm includes FIFOs as caches for the ultrasonic scanning data obtained from the sensors with the output data in a bandwidth-sharing way, on the basis of which an optimal length ratio of all the FIFOs is achieved, allowing the reading operations to be switched among all the FIFOs without time slot waiting. Therefore, this algorithm enhances the utilization ratio of the reading bandwidth resources so as to obtain higher efficiency than the traditional scheduling algorithms. The reliability and validity of the algorithm are substantiated after its implementation in the field programmable gate array (FPGA) technology, and the bandwidth utilization ratio and the real-time performance of the ultrasonic phased array are enhanced. PMID:29035345

A wideband software reconfigurable modem

NASA Astrophysics Data System (ADS)

Turner, J. H., Jr.; Vickers, H.

A wideband modem is described which provides signal processing capability for four Lx-band signals employing QPSK, MSK and PPM waveforms and employs a software reconfigurable architecture for maximum system flexibility and graceful degradation. The current processor uses a 2901 and two 8086 microprocessors per channel and performs acquisition, tracking, and data demodulation for JITDS, GPS, IFF and TACAN systems. The next generation processor will be implemented using a VHSIC chip set employing a programmable complex array vector processor module, a GP computer module, customized gate array modules, and a digital array correlator. This integrated processor has application to a wide number of diverse system waveforms, and will bring the benefits of VHSIC technology insertion into avionic antijam communications systems.

Rad-Hard Structured ASIC Body of Knowledge

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2013-01-01

Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

Wire like link for cycle reproducible and cycle accurate hardware accelerator

DOEpatents

Asaad, Sameh; Kapur, Mohit; Parker, Benjamin D

2015-04-07

First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.

The Advanced Gamma-ray Imaging System (AGIS): Real Time Stereoscopic Array Trigger

NASA Astrophysics Data System (ADS)

Byrum, K.; Anderson, J.; Buckley, J.; Cundiff, T.; Dawson, J.; Drake, G.; Duke, C.; Haberichter, B.; Krawzcynski, H.; Krennrich, F.; Madhavan, A.; Schroedter, M.; Smith, A.

2009-05-01

Future large arrays of Imaging Atmospheric Cherenkov telescopes (IACTs) such as AGIS and CTA are conceived to comprise of 50 - 100 individual telescopes each having a camera with 10**3 to 10**4 pixels. To maximize the capabilities of such IACT arrays with a low energy threshold, a wide field of view and a low background rate, a sophisticated array trigger is required. We describe the design of a stereoscopic array trigger that calculates image parameters and then correlates them across a subset of telescopes. Fast Field Programmable Gate Array technology allows to use lookup tables at the array trigger level to form a real-time pattern recognition trigger tht capitalizes on the multiple view points of the shower at different shower core distances. A proof of principle system is currently under construction. It is based on 400 MHz FPGAs and the goal is for camera trigger rates of up to 10 MHz and a tunable cosmic-ray background suppression at the array level.

Limits in point to point resolution of MOS based pixels detector arrays

NASA Astrophysics Data System (ADS)

Fourches, N.; Desforge, D.; Kebbiri, M.; Kumar, V.; Serruys, Y.; Gutierrez, G.; Leprêtre, F.; Jomard, F.

2018-01-01

In high energy physics point-to-point resolution is a key prerequisite for particle detector pixel arrays. Current and future experiments require the development of inner-detectors able to resolve the tracks of particles down to the micron range. Present-day technologies, although not fully implemented in actual detectors, can reach a 5-μm limit, this limit being based on statistical measurements, with a pixel-pitch in the 10 μm range. This paper is devoted to the evaluation of the building blocks for use in pixel arrays enabling accurate tracking of charged particles. Basing us on simulations we will make here a quantitative evaluation of the physical and technological limits in pixel size. Attempts to design small pixels based on SOI technology will be briefly recalled here. A design based on CMOS compatible technologies that allow a reduction of the pixel size below the micrometer is introduced here. Its physical principle relies on a buried carrier-localizing collecting gate. The fabrication process needed by this pixel design can be based on existing process steps used in silicon microelectronics. The pixel characteristics will be discussed as well as the design of pixel arrays. The existing bottlenecks and how to overcome them will be discussed in the light of recent ion implantation and material characterization experiments.

Construction of a versatile SNP array for pyramiding useful genes of rice.

PubMed

Kurokawa, Yusuke; Noda, Tomonori; Yamagata, Yoshiyuki; Angeles-Shim, Rosalyn; Sunohara, Hidehiko; Uehara, Kanako; Furuta, Tomoyuki; Nagai, Keisuke; Jena, Kshirod Kumar; Yasui, Hideshi; Yoshimura, Atsushi; Ashikari, Motoyuki; Doi, Kazuyuki

2016-01-01

DNA marker-assisted selection (MAS) has become an indispensable component of breeding. Single nucleotide polymorphisms (SNP) are the most frequent polymorphism in the rice genome. However, SNP markers are not readily employed in MAS because of limitations in genotyping platforms. Here the authors report a Golden Gate SNP array that targets specific genes controlling yield-related traits and biotic stress resistance in rice. As a first step, the SNP genotypes were surveyed in 31 parental varieties using the Affymetrix Rice 44K SNP microarray. The haplotype information for 16 target genes was then converted to the Golden Gate platform with 143-plex markers. Haplotypes for the 14 useful allele are unique and can discriminate among all other varieties. The genotyping consistency between the Affymetrix microarray and the Golden Gate array was 92.8%, and the accuracy of the Golden Gate array was confirmed in 3 F2 segregating populations. The concept of the haplotype-based selection by using the constructed SNP array was proofed. Copyright © 2015 The Authors. Published by Elsevier Ireland Ltd.. All rights reserved.

Highly sensitive and area-efficient CMOS image sensor using a PMOSFET-type photodetector with a built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Kim, Kyoung-Do; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2007-02-01

In this paper, a new CMOS image sensor is presented, which uses a PMOSFET-type photodetector with a transfer gate that has a high and variable sensitivity. The proposed CMOS image sensor has been fabricated using a 0.35 μm 2-poly 4- metal standard CMOS technology and is composed of a 256 × 256 array of 7.05 × 7.10 μm pixels. The unit pixel has a configuration of a pseudo 3-transistor active pixel sensor (APS) with the PMOSFET-type photodetector with a transfer gate, which has a function of conventional 4-transistor APS. The generated photocurrent is controlled by the transfer gate of the PMOSFET-type photodetector. The maximum responsivity of the photodetector is larger than 1.0 × 10 3 A/W without any optical lens. Fabricated 256 × 256 CMOS image sensor exhibits a good response to low-level illumination as low as 5 lux.

Automatic Digital Hardware Synthesis

DTIC Science & Technology

1990-09-01

VHDL to PALASM, a hardware synthesis language. The PALASM description is then directly implemented into a field programmable gate array (FPGAI using...process of translating VHDL to PALASM, a hardware synthesis language. The PALASM description is then directly implemented into a field programmable gate...allows the engineer to use VHDL to create and validate a design, and then to implement it in a gate array. The development of software o translate VHDL

Use of Field Programmable Gate Array Technology in Future Space Avionics

NASA Technical Reports Server (NTRS)

Ferguson, Roscoe C.; Tate, Robert

2005-01-01

Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.

Realization of the manipulation of ultracold atoms with a reconfigurable nanomagnetic system of domain walls.

PubMed

West, Adam D; Weatherill, Kevin J; Hayward, Thomas J; Fry, Paul W; Schrefl, Thomas; Gibbs, Mike R J; Adams, Charles S; Allwood, Dan A; Hughes, Ifan G

2012-08-08

Planar magnetic nanowires have been vital to the development of spintronic technology. They provide an unparalleled combination of magnetic reconfigurability, controllability, and scalability, which has helped to realize such applications as racetrack memory and novel logic gates. Microfabricated atom optics benefit from all of these properties, and we present the first demonstration of the amalgamation of spintronic technology with ultracold atoms. A magnetic interaction is exhibited through the reflection of a cloud of (87)Rb atoms at a temperature of 10 μK, from a 2 mm × 2 mm array of nanomagnetic domain walls. In turn, the incident atoms approach the array at heights of the order of 100 nm and are thus used to probe magnetic fields at this distance.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xu Zhouxiang; Zhang Xian; Huang Kaikai

2012-09-15

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat notemore » line width below 1 Hz, residual mean-square phase error of 0.14 rad{sup 2} and transition time of 100 {mu}s under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.« less

Gate protective device for SOS array

NASA Technical Reports Server (NTRS)

Meyer, J. E., Jr.; Scott, J. H.

1972-01-01

Protective gate device consisting of alternating heavily doped n(+) and p(+) diffusions eliminates breakdown voltages in silicon oxide on sapphire arrays caused by electrostatic discharge from person or equipment. Diffusions are easily produced during normal double epitaxial processing. Devices with nine layers had 27-volt breakdown.

A Reconfigurable Communications System for Small Spacecraft

NASA Technical Reports Server (NTRS)

Chu, Pong P.; Kifle, Muli

2004-01-01

Two trends of NASA missions are the use of multiple small spacecraft and the development of an integrated space network. To achieve these goals, a robust and agile communications system is needed. Advancements in field programmable gate array (FPGA) technology have made it possible to incorporate major communication and network functionalities in FPGA chips; thus this technology has great potential as the basis for a reconfigurable communications system. This report discusses the requirements of future space communications, reviews relevant issues, and proposes a methodology to design and construct a reconfigurable communications system for small scientific spacecraft.

Analog Module Architecture for Space-Qualified Field-Programmable Mixed-Signal Arrays

NASA Technical Reports Server (NTRS)

Edwards, R. Timothy; Strohbehn, Kim; Jaskulek, Steven E.; Katz, Richard

1999-01-01

Spacecraft require all manner of both digital and analog circuits. Onboard digital systems are constructed almost exclusively from field-programmable gate array (FPGA) circuits providing numerous advantages over discrete design including high integration density, high reliability, fast turn-around design cycle time, lower mass, volume, and power consumption, and lower parts acquisition and flight qualification costs. Analog and mixed-signal circuits perform tasks ranging from housekeeping to signal conditioning and processing. These circuits are painstakingly designed and built using discrete components due to a lack of options for field-programmability. FPAA (Field-Programmable Analog Array) and FPMA (Field-Programmable Mixed-signal Array) parts exist but not in radiation-tolerant technology and not necessarily in an architecture optimal for the design of analog circuits for spaceflight applications. This paper outlines an architecture proposed for an FPAA fabricated in an existing commercial digital CMOS process used to make radiation-tolerant antifuse-based FPGA devices. The primary concerns are the impact of the technology and the overall array architecture on the flexibility of programming, the bandwidth available for high-speed analog circuits, and the accuracy of the components for high-performance applications.

Environmental Effects on Data Retention in Flash Cells

NASA Technical Reports Server (NTRS)

Katz, Rich; Flowers, David; Bergevin, Keith

2017-01-01

Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Antifuse technology, prevalent in non-volatile field programmable gate arrays (FPGAs), will eventually be phased out as new devices have not been developed for approximately a decade. The reliance on flash technology presents a long-term reliability issue for both DoD and NASA safety- and mission-critical applications. A thorough understanding of the data retention failure modes and statistics associated with Flash data retention is of vital concern to the fuze safety community. A key retention parameter for a flash cell is the threshold voltage (VTH), which is an indirect indicator of the amount of charge stored on the cells floating gate. This paper will present the results of our on-going tests: long-term storage at 150 C for a small population of devices, neutron radiation exposure, electrostatic discharge (ESD) testing, and the trends of large populations (over 300 devices for each condition) exposed to three difference temperatures: 25 C, 125 C, and 150 C.

Development of InSb charge-coupled infrared imaging devices: Linear imager

NASA Technical Reports Server (NTRS)

Phillips, J. D.

1976-01-01

The following results were accomplished in the development of charge coupled infrared imaging devices: (1) a four-phase overlapping gate with 9 transfers (2-bits) and 1.0-mil gate lengths was successfully operated, (2) the measured transfer efficiency of 0.975 for this device is in excellent agreement with predictions for the reduced gate length device, (3) mask revisions of the channel stop metal on the 8582 mask have been carried out with the result being a large increase in the dc yield of the tested devices, (4) partial optical sensitivity to chopped blackbody radiation was observed for an 8582 9-bit imager, (5) analytical consideration of the modulation transfer function degradation caused by transfer inefficiency in the CCD registers was presented, and (6) for larger array lengths or for the insertion of isolated bits between sensors, improvements in InSb fabrication technology with corresponding decrease in the interface state density are required.

Remediation of transuranic-contaminated coral soil at Johnston Atoll using the segmented gate system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bramlitt, E.; Johnson, N.

1994-12-31

Thermo Analytical, Inc. (TMA) has developed a system to remove clean soil from contaminated soil. The system consists of a soil conveyor, an array of radiation detectors toward the conveyor feed end, a gate assembly at the conveyor discharge end, and two additional conveyors which move discharged soil to one or another paths. The gate assembly is as wide as the ``sorter conveyor,`` and it has eight individual gates or segments. The segments automatically open or close depending on the amount of radioactivity present. In one position they pass soil to a clean soil conveyor, and in the other positionmore » they let soil fall to a hot soil conveyor. The soil sorting process recovers clean soil for beneficial use and it substantially reduces the quantity of soil which must be decontaminated or prepared for waste disposal. The Segmented Gate System (SGS) was developed for the cleanup of soil contaminated with some transuranium elements at Johnston Atoll. It has proven to be an effective means for recovering clean soil and verifying that soil is clean, minimizing the quantity of truly contaminated soil, and providing measures of contamination for waste transport and disposal. TMA is constructing a small, transportable soil cleanup as it is confident the SGS technology can be adapted to soils and contaminants other than those at Johnston Atoll. It will use this transportable plant to demonstrate the technology and to develop site specific parameters for use in designing plants to meet cleanup needs.« less

3.4-Inch Quarter High Definition Flexible Active Matrix Organic Light Emitting Display with Oxide Thin Film Transistor

NASA Astrophysics Data System (ADS)

Hatano, Kaoru; Chida, Akihiro; Okano, Tatsuya; Sugisawa, Nozomu; Inoue, Tatsunori; Seo, Satoshi; Suzuki, Kunihiko; Oikawa, Yoshiaki; Miyake, Hiroyuki; Koyama, Jun; Yamazaki, Shunpei; Eguchi, Shingo; Katayama, Masahiro; Sakakura, Masayuki

2011-03-01

In this paper, we report a 3.4-in. flexible active matrix organic light emitting display (AMOLED) display with remarkably high definition (quarter high definition: QHD) in which oxide thin film transistors (TFTs) are used. We have developed a transfer technology in which a TFT array formed on a glass substrate is separated from the substrate by physical force and then attached to a flexible plastic substrate. Unlike a normal process in which a TFT array is directly fabricated on a thin plastic substrate, our transfer technology permits a high integration of high performance TFTs, such as low-temperature polycrystalline silicon TFTs (LTPS TFTs) and oxide TFTs, on a plastic substrate, because a flat, rigid, and thermally-stable glass substrate can be used in the TFT fabrication process in our transfer technology. As a result, this technology realized an oxide TFT array for an AMOLED on a plastic substrate. Furthermore, in order to achieve a high-definition AMOLED, color filters were incorporated in the TFT array and a white organic light-emitting diode (OLED) was combined. One of the features of this device is that the whole body of the device can be bent freely because a source driver and a gate driver can be integrated on the substrate due to the high mobility of an oxide TFT. This feature means “true” flexibility.

Electrolyte-gated transistors based on conducting polymer nanowire junction arrays.

PubMed

Alam, Maksudul M; Wang, Jun; Guo, Yaoyao; Lee, Stephanie P; Tseng, Hsian-Rong

2005-07-07

In this study, we describe the electrolyte gating and doping effects of transistors based on conducting polymer nanowire electrode junction arrays in buffered aqueous media. Conducting polymer nanowires including polyaniline, polypyrrole, and poly(ethylenedioxythiophene) were investigated. In the presence of a positive gate bias, the device exhibits a large on/off current ratio of 978 for polyaniline nanowire-based transistors; these values vary according to the acidity of the gate medium. We attribute these efficient electrolyte gating and doping effects to the electrochemically fabricated nanostructures of conducting polymer nanowires. This study demonstrates that two-terminal devices can be easily converted into three-terminal transistors by simply immersing the device into an electrolyte solution along with a gate electrode. Here, the field-induced modulation can be applied for signal amplification to enhance the device performance.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Technical Reports Server (NTRS)

Sewell, James S.; Bozada, Christopher A.

1994-01-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Astrophysics Data System (ADS)

Sewell, James S.; Bozada, Christopher A.

1994-02-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

IOTA: the array controller for a gigapixel OTCCD camera for Pan-STARRS

NASA Astrophysics Data System (ADS)

Onaka, Peter; Tonry, John; Luppino, Gerard; Lockhart, Charles; Lee, Aaron; Ching, Gregory; Isani, Sidik; Uyeshiro, Robin

2004-09-01

The PanSTARRS project has undertaken an ambitious effort to develop a completely new array controller architecture that is fundamentally driven by the large 1gigapixel, low noise, high speed OTCCD mosaic requirements as well as the size, power and weight restrictions of the PanSTARRS telescope. The result is a very small form factor next generation controller scalar building block with 1 Gigabit Ethernet interfaces that will be assembled into a system that will readout 512 outputs at ~1 Megapixel sample rates on each output. The paper will also discuss critical technology and fabrication techniques such as greater than 1MHz analog to digital converters (ADCs), multiple fast sampling and digital calculation of multiple correlated samples (DMCS), ball grid array (BGA) packaged circuits, LINUX running on embedded field programmable gate arrays (FPGAs) with hard core microprocessors for the prototype currently being developed.

Scan direction induced charging dynamics and the application for detection of gate to S/D shorts in logic devices

NASA Astrophysics Data System (ADS)

Lei, Ming; Tian, Qing; Wu, Kevin; Zhao, Yan

2016-03-01

Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

Spatial mapping and statistical reproducibility of an array of 256 one-dimensional quantum wires

NASA Astrophysics Data System (ADS)

Al-Taie, H.; Smith, L. W.; Lesage, A. A. J.; See, P.; Griffiths, J. P.; Beere, H. E.; Jones, G. A. C.; Ritchie, D. A.; Kelly, M. J.; Smith, C. G.

2015-08-01

We utilize a multiplexing architecture to measure the conductance properties of an array of 256 split gates. We investigate the reproducibility of the pinch off and one-dimensional definition voltage as a function of spatial location on two different cooldowns, and after illuminating the device. The reproducibility of both these properties on the two cooldowns is high, the result of the density of the two-dimensional electron gas returning to a similar state after thermal cycling. The spatial variation of the pinch-off voltage reduces after illumination; however, the variation of the one-dimensional definition voltage increases due to an anomalous feature in the center of the array. A technique which quantifies the homogeneity of split-gate properties across the array is developed which captures the experimentally observed trends. In addition, the one-dimensional definition voltage is used to probe the density of the wafer at each split gate in the array on a micron scale using a capacitive model.

The Advanced Gamma-ray Imaging System (AGIS): Topological Array Trigger

NASA Astrophysics Data System (ADS)

Smith, Andrew W.

2010-03-01

AGIS is a concept for the next-generation ground-based gamma-ray observatory. It will be an array of 36 imaging atmospheric Cherenkov telescopes (IACTs) sensitive in the energy range from 50 GeV to 200 TeV. The required improvements in sensitivity, angular resolution, and reliability of operation relative to the present generation instruments imposes demanding technological and cost requirements on the design of the telescopes and on the triggering and readout systems for AGIS. To maximize the capabilities of large arrays of IACTs with a low energy threshold, a wide field of view and a low background rate, a sophisticated array trigger is required. We outline the status of the development of a stereoscopic array trigger that calculates image parameters and correlates them across a subset of telescopes. Field Programmable Gate Arrays (FPGAs) implement the real-time pattern recognition to suppress cosmic rays and night-sky background events. A proof of principle system is being developed to run at camera trigger rates up to 10MHz and array-level rates up to 10kHz.

High- k Gate Dielectrics for Emerging Flexible and Stretchable Electronics.

PubMed

Wang, Binghao; Huang, Wei; Chi, Lifeng; Al-Hashimi, Mohammed; Marks, Tobin J; Facchetti, Antonio

2018-05-22

Recent advances in flexible and stretchable electronics (FSE), a technology diverging from the conventional rigid silicon technology, have stimulated fundamental scientific and technological research efforts. FSE aims at enabling disruptive applications such as flexible displays, wearable sensors, printed RFID tags on packaging, electronics on skin/organs, and Internet-of-things as well as possibly reducing the cost of electronic device fabrication. Thus, the key materials components of electronics, the semiconductor, the dielectric, and the conductor as well as the passive (substrate, planarization, passivation, and encapsulation layers) must exhibit electrical performance and mechanical properties compatible with FSE components and products. In this review, we summarize and analyze recent advances in materials concepts as well as in thin-film fabrication techniques for high- k (or high-capacitance) gate dielectrics when integrated with FSE-compatible semiconductors such as organics, metal oxides, quantum dot arrays, carbon nanotubes, graphene, and other 2D semiconductors. Since thin-film transistors (TFTs) are the key enablers of FSE devices, we discuss TFT structures and operation mechanisms after a discussion on the needs and general requirements of gate dielectrics. Also, the advantages of high- k dielectrics over low- k ones in TFT applications were elaborated. Next, after presenting the design and properties of high- k polymers and inorganic, electrolyte, and hybrid dielectric families, we focus on the most important fabrication methodologies for their deposition as TFT gate dielectric thin films. Furthermore, we provide a detailed summary of recent progress in performance of FSE TFTs based on these high- k dielectrics, focusing primarily on emerging semiconductor types. Finally, we conclude with an outlook and challenges section.

Performance characteristics of a nanoscale double-gate reconfigurable array

NASA Astrophysics Data System (ADS)

Beckett, Paul

2008-12-01

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

Field-Programmable Gate Array-based fluxgate magnetometer with digital integration

NASA Astrophysics Data System (ADS)

Butta, Mattia; Janosek, Michal; Ripka, Pavel

2010-05-01

In this paper, a digital magnetometer based on printed circuit board fluxgate is presented. The fluxgate is pulse excited and the signal is extracted by gate integration. We investigate the possibility to perform integration on very narrow gates (typically 500 ns) by using digital techniques. The magnetometer is based on field-programmable gate array (FPGA) card: we will show all the advantages and disadvantages, given by digitalization of fluxgate output voltage by means of analog-to-digital converter on FPGA card, as well as digitalization performed by external digitizer. Due to very narrow gate, it is shown that a magnetometer entirely based on a FPGA card is preferable, because it avoids noise due to trigger instability. Both open loop and feedback operative mode are described and achieved results are presented.

RHrFPGA Radiation-Hardened Re-programmable Field-Programmable Gate Array

NASA Technical Reports Server (NTRS)

Sanders, A. B.; LaBel, K. A.; McCabe, J. F.; Gardner, G. A.; Lintz, J.; Ross, C.; Golke, K.; Burns, B.; Carts, M. A.; Kim, H. S.

2004-01-01

Viewgraphs on the development of the Radiation-Hardened Re-programmable Field-Programmable Gate Array (RHrFPGA) are presented. The topics include: 1) Radiation Test Suite; 2) Testing Interface; 3) Test Configuration; 4) Facilities; 5) Test Programs; 6) Test Procedure; and 7) Test Results. A summary of heavy ion and proton testing is also included.

An Undergraduate Course and Laboratory in Digital Signal Processing with Field Programmable Gate Arrays

ERIC Educational Resources Information Center

Meyer-Base, U.; Vera, A.; Meyer-Base, A.; Pattichis, M. S.; Perry, R. J.

2010-01-01

In this paper, an innovative educational approach to introducing undergraduates to both digital signal processing (DSP) and field programmable gate array (FPGA)-based design in a one-semester course and laboratory is described. While both DSP and FPGA-based courses are currently present in different curricula, this integrated approach reduces the…

In-situ Testing of the EHT High Gain and Frequency Ultra-Stable Integrators

NASA Astrophysics Data System (ADS)

Miller, Kenneth; Ziemba, Timothy; Prager, James; Slobodov, Ilia; Lotz, Dan

2014-10-01

Eagle Harbor Technologies (EHT) has developed a long-pulse integrator that exceeds the ITER specification for integration error and pulse duration. During the Phase I program, EHT improved the RPPL short-pulse integrators, added a fast digital reset, and demonstrated that the new integrators exceed the ITER integration error and pulse duration requirements. In Phase II, EHT developed Field Programmable Gate Array (FPGA) software that allows for integrator control and real-time signal digitization and processing. In the second year of Phase II, the EHT integrator will be tested at a validation platform experiment (HIT-SI) and tokamak (DIII-D). In the Phase IIB program, EHT will continue development of the EHT integrator to reduce overall cost per channel. EHT will test lower cost components, move to surface mount components, and add an onboard Field Programmable Gate Array and data acquisition to produce a stand-alone system with lower cost per channel and increased the channel density. EHT will test the Phase IIB integrator at a validation platform experiment (HIT-SI) and tokamak (DIII-D). Work supported by the DOE under Contract Number (DE-SC0006281).

Modular design and implementation of field-programmable-gate-array-based Gaussian noise generator

NASA Astrophysics Data System (ADS)

Li, Yuan-Ping; Lee, Ta-Sung; Hwang, Jeng-Kuang

2016-05-01

The modular design of a Gaussian noise generator (GNG) based on field-programmable gate array (FPGA) technology was studied. A new range reduction architecture was included in a series of elementary function evaluation modules and was integrated into the GNG system. The approximation and quantisation errors for the square root module with a first polynomial approximation were high; therefore, we used the central limit theorem (CLT) to improve the noise quality. This resulted in an output rate of one sample per clock cycle. We subsequently applied Newton's method for the square root module, thus eliminating the need for the use of the CLT because applying the CLT resulted in an output rate of two samples per clock cycle (>200 million samples per second). Two statistical tests confirmed that our GNG is of high quality. Furthermore, the range reduction, which is used to solve a limited interval of the function approximation algorithms of the System Generator platform using Xilinx FPGAs, appeared to have a higher numerical accuracy, was operated at >350 MHz, and can be suitably applied for any function evaluation.

A new 9T global shutter pixel with CDS technique

NASA Astrophysics Data System (ADS)

Liu, Yang; Ma, Cheng; Zhou, Quan; Wang, Xinyang

2015-04-01

Benefiting from motion blur free, Global shutter pixel is very widely used in the design of CMOS image sensors for high speed applications such as motion vision, scientifically inspection, etc. In global shutter sensors, all pixel signal information needs to be stored in the pixel first and then waiting for readout. For higher frame rate, we need very fast operation of the pixel array. There are basically two ways for the in pixel signal storage, one is in charge domain, such as the one shown in [1], this needs complicated process during the pixel fabrication. The other one is in voltage domain, one example is the one in [2], this pixel is based on the 4T PPD technology and normally the driving of the high capacitive transfer gate limits the speed of the array operation. In this paper we report a new 9T global shutter pixel based on 3-T partially pinned photodiode (PPPD) technology. It incorporates three in-pixel storage capacitors allowing for correlated double sampling (CDS) and pipeline operation of the array (pixel exposure during the readout of the array). Only two control pulses are needed for all the pixels at the end of exposure which allows high speed exposure control.

High-Performance, Radiation-Hardened Electronics for Space Environments

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Watson, Michael D.; Frazier, Donald O.; Adams, James H.; Johnson, Michael A.; Kolawa, Elizabeth A.

2007-01-01

The Radiation Hardened Electronics for Space Environments (RHESE) project endeavors to advance the current state-of-the-art in high-performance, radiation-hardened electronics and processors, ensuring successful performance of space systems required to operate within extreme radiation and temperature environments. Because RHESE is a project within the Exploration Technology Development Program (ETDP), RHESE's primary customers will be the human and robotic missions being developed by NASA's Exploration Systems Mission Directorate (ESMD) in partial fulfillment of the Vision for Space Exploration. Benefits are also anticipated for NASA's science missions to planetary and deep-space destinations. As a technology development effort, RHESE provides a broad-scoped, full spectrum of approaches to environmentally harden space electronics, including new materials, advanced design processes, reconfigurable hardware techniques, and software modeling of the radiation environment. The RHESE sub-project tasks are: SelfReconfigurable Electronics for Extreme Environments, Radiation Effects Predictive Modeling, Radiation Hardened Memory, Single Event Effects (SEE) Immune Reconfigurable Field Programmable Gate Array (FPGA) (SIRF), Radiation Hardening by Software, Radiation Hardened High Performance Processors (HPP), Reconfigurable Computing, Low Temperature Tolerant MEMS by Design, and Silicon-Germanium (SiGe) Integrated Electronics for Extreme Environments. These nine sub-project tasks are managed by technical leads as located across five different NASA field centers, including Ames Research Center, Goddard Space Flight Center, the Jet Propulsion Laboratory, Langley Research Center, and Marshall Space Flight Center. The overall RHESE integrated project management responsibility resides with NASA's Marshall Space Flight Center (MSFC). Initial technology development emphasis within RHESE focuses on the hardening of Field Programmable Gate Arrays (FPGA)s and Field Programmable Analog Arrays (FPAA)s for use in reconfigurable architectures. As these component/chip level technologies mature, the RHESE project emphasis shifts to focus on efforts encompassing total processor hardening techniques and board-level electronic reconfiguration techniques featuring spare and interface modularity. This phased approach to distributing emphasis between technology developments provides hardened FPGA/FPAAs for early mission infusion, then migrates to hardened, board-level, high speed processors with associated memory elements and high density storage for the longer duration missions encountered for Lunar Outpost and Mars Exploration occurring later in the Constellation schedule.

Field emitter arrays and displays produced by ion tracking lithography

NASA Astrophysics Data System (ADS)

Felter, T. E.; Musket, R. G.; Bernhardt, A. F.

2005-12-01

When ions of sufficient electronic energy loss traverse a dielectric film or foil, they alter the chemical bonding along their nominally straight path within the material. A suitable etchant can quickly dissolve these so-called latent tracks leaving holes of small diameter (∼10 nm) but long length - several microns. Continuing the etching process gradually increases the diameter reproducibly and uniformly. The trackable medium can be applied as a uniform film onto large substrates. The small, monodisperse holes produced by this track etching can be used in conjunction with additional thin film processing to create functional structures attached to the substrate. For example, Lawrence Livermore National Laboratory and Candescent Technologies Corporation (CTC) co-developed a process to make arrays of gated field emitters (∼100 nm diameter electron guns) for CTC's Thin CRTTM displays, which have been fabricated to diagonal dimensions >13 in. Additional technological applications of ion tracking lithography will be briefly covered.

Mapping brain activity with flexible graphene micro-transistors

NASA Astrophysics Data System (ADS)

Blaschke, Benno M.; Tort-Colet, Núria; Guimerà-Brunet, Anton; Weinert, Julia; Rousseau, Lionel; Heimann, Axel; Drieschner, Simon; Kempski, Oliver; Villa, Rosa; Sanchez-Vives, Maria V.; Garrido, Jose A.

2017-06-01

Establishing a reliable communication interface between the brain and electronic devices is of paramount importance for exploiting the full potential of neural prostheses. Current microelectrode technologies for recording electrical activity, however, evidence important shortcomings, e.g. challenging high density integration. Solution-gated field-effect transistors (SGFETs), on the other hand, could overcome these shortcomings if a suitable transistor material were available. Graphene is particularly attractive due to its biocompatibility, chemical stability, flexibility, low intrinsic electronic noise and high charge carrier mobilities. Here, we report on the use of an array of flexible graphene SGFETs for recording spontaneous slow waves, as well as visually evoked and also pre-epileptic activity in vivo in rats. The flexible array of graphene SGFETs allows mapping brain electrical activity with excellent signal-to-noise ratio (SNR), suggesting that this technology could lay the foundation for a future generation of in vivo recording implants.

Systems and methods for detecting a failure event in a field programmable gate array

NASA Technical Reports Server (NTRS)

Ng, Tak-Kwong (Inventor); Herath, Jeffrey A. (Inventor)

2009-01-01

An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.

CMOS image sensor with lateral electric field modulation pixels for fluorescence lifetime imaging with sub-nanosecond time response

NASA Astrophysics Data System (ADS)

Li, Zhuo; Seo, Min-Woong; Kagawa, Keiichiro; Yasutomi, Keita; Kawahito, Shoji

2016-04-01

This paper presents the design and implementation of a time-resolved CMOS image sensor with a high-speed lateral electric field modulation (LEFM) gating structure for time domain fluorescence lifetime measurement. Time-windowed signal charge can be transferred from a pinned photodiode (PPD) to a pinned storage diode (PSD) by turning on a pair of transfer gates, which are situated beside the channel. Unwanted signal charge can be drained from the PPD to the drain by turning on another pair of gates. The pixel array contains 512 (V) × 310 (H) pixels with 5.6 × 5.6 µm2 pixel size. The imager chip was fabricated using 0.11 µm CMOS image sensor process technology. The prototype sensor has a time response of 150 ps at 374 nm. The fill factor of the pixels is 5.6%. The usefulness of the prototype sensor is demonstrated for fluorescence lifetime imaging through simulation and measurement results.

Single Event Analysis and Fault Injection Techniques Targeting Complex Designs Implemented in Xilinx-Virtex Family Field Programmable Gate Array (FPGA) Devices

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; LaBel, Kenneth; Kim, Hak

2014-01-01

An informative session regarding SRAM FPGA basics. Presenting a framework for fault injection techniques applied to Xilinx Field Programmable Gate Arrays (FPGAs). Introduce an overlooked time component that illustrates fault injection is impractical for most real designs as a stand-alone characterization tool. Demonstrate procedures that benefit from fault injection error analysis.

Scaling Trapped Ion Quantum Computers Using Fast Gates and Microtraps

NASA Astrophysics Data System (ADS)

Ratcliffe, Alexander K.; Taylor, Richard L.; Hope, Joseph J.; Carvalho, André R. R.

2018-06-01

Most attempts to produce a scalable quantum information processing platform based on ion traps have focused on the shuttling of ions in segmented traps. We show that an architecture based on an array of microtraps with fast gates will outperform architectures based on ion shuttling. This system requires higher power lasers but does not require the manipulation of potentials or shuttling of ions. This improves optical access, reduces the complexity of the trap, and reduces the number of conductive surfaces close to the ions. The use of fast gates also removes limitations on the gate time. Error rates of 10-5 are shown to be possible with 250 mW laser power and a trap separation of 100 μ m . The performance of the gates is shown to be robust to the limitations in the laser repetition rate and the presence of many ions in the trap array.

Field ionization characteristics of an ion source array for neutron generators

NASA Astrophysics Data System (ADS)

Bargsten Johnson, B.; Schwoebel, P. R.; Resnick, P. J.; Holland, C. E.; Hertz, K. L.; Chichester, D. L.

2013-11-01

A new deuterium ion source is being developed to improve the performance of existing compact neutron generators. The ion source is a microfabricated array of metal tips with an integrated gate (i.e., grid) and produces deuterium ions by field ionizing (or field desorbing) a supply of deuterium gas. Deuterium field ion currents from arrays at source temperatures of 77 K and 293 K are studied. Ion currents from single etched-wire tips operating under the same conditions are used to help understand array results. I-F characteristics of the arrays were found to follow trends similar to those of the better understood single etched-wire tip results; however, the fields achieved by the arrays are limited by electrical breakdown of the structure. Neutron production by field ionization at 293 K was demonstrated for the first time from microfabricated array structures with integrated gates.

Wafer-scale, massively parallel carbon nanotube arrays for realizing field effect transistors with current density exceeding silicon and gallium arsenide

NASA Astrophysics Data System (ADS)

Arnold, Michael

Calculations have indicated that aligned arrays of semiconducting carbon nanotubes (CNTs) promise to outperform conventional semiconducting materials in short-channel, aggressively scaled field effect transistors (FETs) like those used in semiconductor logic and high frequency amplifier technologies. These calculations have been based on extrapolation of measurements of FETs based on one CNT, in which ballistic transport approaching the quantum conductance limit of 2Go = 4e2/h has been achieved. However, constraints in CNT sorting, processing, alignment, and contacts give rise to non-idealities when CNTs are implemented in densely-packed parallel arrays, which has resulted in a conductance per CNT far from 2Go. The consequence has been that it has been very difficult to create high performance CNT array FETs, and CNT array FETs have not outperformed but rather underperformed channel materials such as Si by 6 x or more. Here, we report nearly ballistic CNT array FETs at a density of 50 CNTs um-1, created via CNT sorting, wafer-scale alignment and assembly, and treatment. The on-state conductance in the arrays is as high as 0.46 Go per CNT, and the conductance of the arrays reaches 1.7 mS um-1, which is 7 x higher than previous state-of-the-art CNT array FETs made by other methods. The saturated on-state current density reaches 900 uA um-1 and is similar to or exceeds that of Si FETs when compared at equivalent gate oxide thickness, off-state current density, and channel length. The on-state current density exceeds that of GaAs FETs, as well. This leap in CNT FET array performance is a significant advance towards the exploitation of CNTs in high-performance semiconductor electronics technologies.

Parallel algorithm for computation of second-order sequential best rotations

NASA Astrophysics Data System (ADS)

Redif, Soydan; Kasap, Server

2013-12-01

Algorithms for computing an approximate polynomial matrix eigenvalue decomposition of para-Hermitian systems have emerged as a powerful, generic signal processing tool. A technique that has shown much success in this regard is the sequential best rotation (SBR2) algorithm. Proposed is a scheme for parallelising SBR2 with a view to exploiting the modern architectural features and inherent parallelism of field-programmable gate array (FPGA) technology. Experiments show that the proposed scheme can achieve low execution times while requiring minimal FPGA resources.

Asymmetric Core Computing for U.S. Army High-Performance Computing Applications

DTIC Science & Technology

2009-04-01

Playstation 4 (should one be announced). 8 4.2 FPGAs Reconfigurable computing refers to performing computations using Field Programmable Gate Arrays...2008 4 . TITLE AND SUBTITLE Asymmetric Core Computing for U.S. Army High-Performance Computing Applications 5a. CONTRACT NUMBER 5b. GRANT NUMBER...Acknowledgments vi  1.  Introduction 1  2.  Relevant Technologies 2  3.  Technical Approach 5  4 .  Research and Development Highlights 7  4.1  Cell

Radiation Tolerant, FPGA-Based SmallSat Computer System

NASA Technical Reports Server (NTRS)

LaMeres, Brock J.; Crum, Gary A.; Martinez, Andres; Petro, Andrew

2015-01-01

The Radiation Tolerant, FPGA-based SmallSat Computer System (RadSat) computing platform exploits a commercial off-the-shelf (COTS) Field Programmable Gate Array (FPGA) with real-time partial reconfiguration to provide increased performance, power efficiency and radiation tolerance at a fraction of the cost of existing radiation hardened computing solutions. This technology is ideal for small spacecraft that require state-of-the-art on-board processing in harsh radiation environments but where using radiation hardened processors is cost prohibitive.

Two CMOS gate arrays for the EPACT experiment

DOE Office of Scientific and Technical Information (OSTI.GOV)

Winkert, G.

1992-08-01

Two semicustom CMOS digital gate arrays are described in this paper which have been developed for the Energetic Particles: Acceleration, Composition, and Transport (EPACT) experiment. The first device, the 'Event Counters: 16 by 24-bit' (EC1624), implements sixteen 24-bit ripple counters and has flexible counting and readout options. The second device, the 'Serial Transmitter/Receiver' (SXR), is a multi-personality chip that can be used at either end of a serial, synchronous communications data link. It can be configured as a master in a central control unit, or as one of many slaves within remote assemblies. Together a network of SXRs allows formore » commanding and verification of distributed control signals. Both gate arrays are radiation hardened and qualified for space flight use. The architecture of each chip is presented and the benefits to the experiment summarized.« less

Development of a stationary chest tomosynthesis system using carbon nanotube x-ray source array

NASA Astrophysics Data System (ADS)

Shan, Jing

X-ray imaging system has shown its usefulness for providing quick and easy access of imaging in both clinic settings and emergency situations. It greatly improves the workflow in hospitals. However, the conventional radiography systems, lacks 3D information in the images. The tissue overlapping issue in the 2D projection image result in low sensitivity and specificity. Both computed tomography and digital tomosynthesis, the two conventional 3D imaging modalities, requires a complex gantry to mechanically translate the x-ray source to various positions. Over the past decade, our research group has developed a carbon nanotube (CNT) based x-ray source technology. The CNT x-ray sources allows compacting multiple x-ray sources into a single x-ray tube. Each individual x-ray source in the source array can be electronically switched. This technology allows development of stationary tomographic imaging modalities without any complex mechanical gantries. The goal of this work is to develop a stationary digital chest tomosynthesis (s-DCT) system, and implement it for a clinical trial. The feasibility of s-DCT was investigated. It is found that the CNT source array can provide sufficient x-ray output for chest imaging. Phantom images have shown comparable image qualities as conventional DCT. The s-DBT system was then used to study the effects of source array configurations and tomosynthesis image quality, and the feasibility of a physiological gated s-DCT. Using physical measures for spatial resolution, the 2D source configuration was shown to have improved depth resolution and comparable in-plane resolution. The prospective gated tomosynthesis images have shown substantially reduction of image blur associated with lung motions. The system was also used to investigate the feasibility of using s-DCT as a diagnosis and monitoring tools for cystic fibrosis patients. A new scatter reduction methods for s-DCT was also studied. Finally, a s-DCT system was constructed by retrofitting the source array to a Carestream digital radiography system. The system passed the electrical and radiation safety tests, and was installed in Marsico Hall. The patient trial started in March of 2015, and the first patient was successfully imaged.

Quantum cellular automata

NASA Astrophysics Data System (ADS)

Porod, Wolfgang; Lent, Craig S.; Bernstein, Gary H.

1994-06-01

The Notre Dame group has developed a new paradigm for ultra-dense and ultra-fast information processing in nanoelectronic systems. These Quantum Cellular Automata (QCA's) are the first concrete proposal for a technology based on arrays of coupled quantum dots. The basic building block of these cellular arrays is the Notre Dame Logic Cell, as it has been called in the literature. The phenomenon of Coulomb exclusion, which is a synergistic interplay of quantum confinement and Coulomb interaction, leads to a bistable behavior of each cell which makes possible their use in large-scale cellular arrays. The physical interaction between neighboring cells has been exploited to implement logic functions. New functionality may be achieved in this fashion, and the Notre Dame group invented a versatile majority logic gate. In a series of papers, the feasibility of QCA wires, wire crossing, inverters, and Boolean logic gates was demonstrated. A major finding is that all logic functions may be integrated in a hierarchial fashion which allows the design of complicated QCA structures. The most complicated system which was simulated to date is a one-bit full adder consisting of some 200 cells. In addition to exploring these new concepts, efforts are under way to physically realize such structures both in semiconductor and metal systems. Extensive modeling work of semiconductor quantum dot structures has helped identify optimum design parameters for QCA experimental implementations.

Roll Angle Estimation Using Thermopiles for a Flight Controlled Mortar

DTIC Science & Technology

2012-06-01

Using Xilinx’s System generator, the entire design was implemented at a relatively high level within Malab’s Simulink. This allowed VHDL code to...thermopile data with a Recursive Least Squares (RLS) filter implemented on a field programmable gate array (FPGA). These results demonstrate the...accurately estimated by processing the thermopile data with a Recursive Least Squares (RLS) filter implemented on a field programmable gate array (FPGA

TRIGA: Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Arrays

NASA Technical Reports Server (NTRS)

Pang, Jackson; Pingree, Paula J.; Torgerson, J. Leigh

2006-01-01

We present the Telecommunications protocol processing subsystem using Reconfigurable Interoperable Gate Arrays (TRIGA), a novel approach that unifies fault tolerance, error correction coding and interplanetary communication protocol off-loading to implement CCSDS File Delivery Protocol and Datalink layers. The new reconfigurable architecture offers more than one order of magnitude throughput increase while reducing footprint requirements in memory, command and data handling processor utilization, communication system interconnects and power consumption.

Dosimetric verification of gated delivery of electron beams using a 2D ion chamber array

PubMed Central

Yoganathan, S. A.; Das, K. J. Maria; Raj, D. Gowtham; Kumar, Shaleen

2015-01-01

The purpose of this study was to compare the dosimetric characteristics; such as beam output, symmetry and flatness between gated and non-gated electron beams. Dosimetric verification of gated delivery was carried for all electron beams available on Varian CL 2100CD medical linear accelerator. Measurements were conducted for three dose rates (100 MU/min, 300 MU/min and 600 MU/min) and two respiratory motions (breathing period of 4s and 8s). Real-time position management (RPM) system was used for the gated deliveries. Flatness and symmetry values were measured using Imatrixx 2D ion chamber array device and the beam output was measured using plane parallel ion chamber. These detector systems were placed over QUASAR motion platform which was programmed to simulate the respiratory motion of target. The dosimetric characteristics of gated deliveries were compared with non-gated deliveries. The flatness and symmetry of all the evaluated electron energies did not differ by more than 0.7 % with respect to corresponding non-gated deliveries. The beam output variation of gated electron beam was less than 0.6 % for all electron energies except for 16 MeV (1.4 %). Based on the results of this study, it can be concluded that Varian CL2100 CD is well suitable for gated delivery of non-dynamic electron beams. PMID:26170552

Radiation Effects on Current Field Programmable Technologies

NASA Technical Reports Server (NTRS)

Katz, R.; LaBel, K.; Wang, J. J.; Cronquist, B.; Koga, R.; Penzin, S.; Swift, G.

1997-01-01

Manufacturers of field programmable gate arrays (FPGAS) take different technological and architectural approaches that directly affect radiation performance. Similar y technological and architectural features are used in related technologies such as programmable substrates and quick-turn application specific integrated circuits (ASICs). After analyzing current technologies and architectures and their radiation-effects implications, this paper includes extensive test data quantifying various devices total dose and single event susceptibilities, including performance degradation effects and temporary or permanent re-configuration faults. Test results will concentrate on recent technologies being used in space flight electronic systems and those being developed for use in the near term. This paper will provide the first extensive study of various configuration memories used in programmable devices. Radiation performance limits and their impacts will be discussed for each design. In addition, the interplay between device scaling, process, bias voltage, design, and architecture will be explored. Lastly, areas of ongoing research will be discussed.

NEPP Update of Independent Single Event Upset Field Programmable Gate Array Testing

NASA Technical Reports Server (NTRS)

Berg, Melanie; Label, Kenneth; Campola, Michael; Pellish, Jonathan

2017-01-01

This presentation provides a NASA Electronic Parts and Packaging (NEPP) Program update of independent Single Event Upset (SEU) Field Programmable Gate Array (FPGA) testing including FPGA test guidelines, Microsemi RTG4 heavy-ion results, Xilinx Kintex-UltraScale heavy-ion results, Xilinx UltraScale+ single event effect (SEE) test plans, development of a new methodology for characterizing SEU system response, and NEPP involvement with FPGA security and trust.

Initial Single Event Effects Testing of the Xilinx Virtex-4 Field Programmable Gate Array

NASA Technical Reports Server (NTRS)

Allen, Gregory R.; Swift, Gary M.; Carmichael, C.; Tseng, C.

2007-01-01

We present initial results for the thin epitaxial Xilinx Virtex-4 Fie ld Programmable Gate Array (FPGA), and compare to previous results ob tained for the Virtex-II and Virtex-II Pro. The data presented was a cquired through a consortium based effort with the common goal of pr oviding the space community with data and mitigation methods for the use of Xilinx FPGAs in space.

Analog storage integrated circuit

DOEpatents

Walker, J. T.; Larsen, R. S.; Shapiro, S. L.

1989-01-01

A high speed data storage array is defined utilizing a unique cell design for high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates between the signal input and a storage capacitor. The gates are controlled by a high speed row clock and low speed column clock so that the instantaneous analog value of the signal is only sampled and stored by each cell on coincidence of the two clocks.

Analog storage integrated circuit

DOEpatents

Walker, J.T.; Larsen, R.S.; Shapiro, S.L.

1989-03-07

A high speed data storage array is defined utilizing a unique cell design for high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates between the signal input and a storage capacitor. The gates are controlled by a high speed row clock and low speed column clock so that the instantaneous analog value of the signal is only sampled and stored by each cell on coincidence of the two clocks. 6 figs.

Gas Sensors Characterization and Multilayer Perceptron (MLP) Hardware Implementation for Gas Identification Using a Field Programmable Gate Array (FPGA)

PubMed Central

Benrekia, Fayçal; Attari, Mokhtar; Bouhedda, Mounir

2013-01-01

This paper develops a primitive gas recognition system for discriminating between industrial gas species. The system under investigation consists of an array of eight micro-hotplate-based SnO2 thin film gas sensors with different selectivity patterns. The output signals are processed through a signal conditioning and analyzing system. These signals feed a decision-making classifier, which is obtained via a Field Programmable Gate Array (FPGA) with Very High-Speed Integrated Circuit Hardware Description Language. The classifier relies on a multilayer neural network based on a back propagation algorithm with one hidden layer of four neurons and eight neurons at the input and five neurons at the output. The neural network designed after implementation consists of twenty thousand gates. The achieved experimental results seem to show the effectiveness of the proposed classifier, which can discriminate between five industrial gases. PMID:23529119

Single array of magnetic vortex disks uses in-plane anisotropy to create different logic gates

NASA Astrophysics Data System (ADS)

Vigo-Cotrina, H.; Guimarães, A. P.

2017-11-01

Using micromagnetic simulation, we show that in-plane uniaxial magnetic anisotropy (IPUA) can be used to obtain FAN-OUT, AND and OR gates in an array of coupled disks with magnetic vortex configuration. First, we studied the influence of the direction of application of the IPUA on the energy transfer time (τ) between two identical coupled nanodisks. We found that when the direction of the IPUA is along the x axis the magnetic interaction increases, allowing shorter values of τ , while the IPUA along the y direction has the opposite effect. The magnetic interactions between the nanodisks along x and y directions (the coupling integrals) as a function of the uniaxial anisotropy constant (Kσ) were obtained using a simple dipolar model. Next, we demonstrated that choosing a suitable direction of application of the IPUA, it is possible to create several different logic gates with a single array of coupled nanodisks.

Superconducting quantum circuits at the surface code threshold for fault tolerance.

PubMed

Barends, R; Kelly, J; Megrant, A; Veitia, A; Sank, D; Jeffrey, E; White, T C; Mutus, J; Fowler, A G; Campbell, B; Chen, Y; Chen, Z; Chiaro, B; Dunsworth, A; Neill, C; O'Malley, P; Roushan, P; Vainsencher, A; Wenner, J; Korotkov, A N; Cleland, A N; Martinis, John M

2014-04-24

A quantum computer can solve hard problems, such as prime factoring, database searching and quantum simulation, at the cost of needing to protect fragile quantum states from error. Quantum error correction provides this protection by distributing a logical state among many physical quantum bits (qubits) by means of quantum entanglement. Superconductivity is a useful phenomenon in this regard, because it allows the construction of large quantum circuits and is compatible with microfabrication. For superconducting qubits, the surface code approach to quantum computing is a natural choice for error correction, because it uses only nearest-neighbour coupling and rapidly cycled entangling gates. The gate fidelity requirements are modest: the per-step fidelity threshold is only about 99 per cent. Here we demonstrate a universal set of logic gates in a superconducting multi-qubit processor, achieving an average single-qubit gate fidelity of 99.92 per cent and a two-qubit gate fidelity of up to 99.4 per cent. This places Josephson quantum computing at the fault-tolerance threshold for surface code error correction. Our quantum processor is a first step towards the surface code, using five qubits arranged in a linear array with nearest-neighbour coupling. As a further demonstration, we construct a five-qubit Greenberger-Horne-Zeilinger state using the complete circuit and full set of gates. The results demonstrate that Josephson quantum computing is a high-fidelity technology, with a clear path to scaling up to large-scale, fault-tolerant quantum circuits.

An Anti-Electromagnetic Attack PUF Based on a Configurable Ring Oscillator for Wireless Sensor Networks

PubMed Central

Lu, Zhaojun; Li, Dongfang; Liu, Hailong; Gong, Mingyang; Liu, Zhenglin

2017-01-01

Wireless sensor networks (WSNs) are an emerging technology employed in some crucial applications. However, limited resources and physical exposure to attackers make security a challenging issue for a WSN. Ring oscillator-based physical unclonable function (RO PUF) is a potential option to protect the security of sensor nodes because it is able to generate random responses efficiently for a key extraction mechanism, which prevents the non-volatile memory from storing secret keys. In order to deploy RO PUF in a WSN, hardware efficiency, randomness, uniqueness, and reliability should be taken into account. Besides, the resistance to electromagnetic (EM) analysis attack is important to guarantee the security of RO PUF itself. In this paper, we propose a novel architecture of configurable RO PUF based on exclusive-or (XOR) gates. First, it dramatically increases the hardware efficiency compared with other types of RO PUFs. Second, it mitigates the vulnerability to EM analysis attack by placing the adjacent RO arrays in accordance with the cosine wave and sine wave so that the frequency of each RO cannot be detected. We implement our proposal in XINLINX A-7 field programmable gate arrays (FPGAs) and conduct a set of experiments to evaluate the quality of the responses. The results show that responses pass the National Institute of Standards and Technology (NIST) statistical test and have good uniqueness and reliability under different environments. Therefore, the proposed configurable RO PUF is suitable to establish a key extraction mechanism in a WSN. PMID:28914756

An Anti-Electromagnetic Attack PUF Based on a Configurable Ring Oscillator for Wireless Sensor Networks.

PubMed

Lu, Zhaojun; Li, Dongfang; Liu, Hailong; Gong, Mingyang; Liu, Zhenglin

2017-09-15

Wireless sensor networks (WSNs) are an emerging technology employed in some crucial applications. However, limited resources and physical exposure to attackers make security a challenging issue for a WSN. Ring oscillator-based physical unclonable function (RO PUF) is a potential option to protect the security of sensor nodes because it is able to generate random responses efficiently for a key extraction mechanism, which prevents the non-volatile memory from storing secret keys. In order to deploy RO PUF in a WSN, hardware efficiency, randomness, uniqueness, and reliability should be taken into account. Besides, the resistance to electromagnetic (EM) analysis attack is important to guarantee the security of RO PUF itself. In this paper, we propose a novel architecture of configurable RO PUF based on exclusive-or (XOR) gates. First, it dramatically increases the hardware efficiency compared with other types of RO PUFs. Second, it mitigates the vulnerability to EM analysis attack by placing the adjacent RO arrays in accordance with the cosine wave and sine wave so that the frequency of each RO cannot be detected. We implement our proposal in XINLINX A-7 field programmable gate arrays (FPGAs) and conduct a set of experiments to evaluate the quality of the responses. The results show that responses pass the National Institute of Standards and Technology (NIST) statistical test and have good uniqueness and reliability under different environments. Therefore, the proposed configurable RO PUF is suitable to establish a key extraction mechanism in a WSN.

Fabrication of arrayed Si nanowire-based nano-floating gate memory devices on flexible plastics.

PubMed

Yoon, Changjoon; Jeon, Youngin; Yun, Junggwon; Kim, Sangsig

2012-01-01

Arrayed Si nanowire (NW)-based nano-floating gate memory (NFGM) devices with Pt nanoparticles (NPs) embedded in Al2O3 gate layers are successfully constructed on flexible plastics by top-down approaches. Ten arrayed Si NW-based NFGM devices are positioned on the first level. Cross-linked poly-4-vinylphenol (PVP) layers are spin-coated on them as isolation layers between the first and second level, and another ten devices are stacked on the cross-linked PVP isolation layers. The electrical characteristics of the representative Si NW-based NFGM devices on the first and second levels exhibit threshold voltage shifts, indicating the trapping and detrapping of electrons in their NPs nodes. They have an average threshold voltage shift of 2.5 V with good retention times of more than 5 x 10(4) s. Moreover, most of the devices successfully retain their electrical characteristics after about one thousand bending cycles. These well-arrayed and stacked Si NW-based NFGM devices demonstrate the potential of nanowire-based devices for large-scale integration.

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

PubMed

Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-06-24

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

Semantically Aware Foundation Environment (SAFE) for Clean-Slate Design of Resilient, Adaptive Secure Hosts (CRASH)

DTIC Science & Technology

2016-02-01

system consists of a high-fidelity hardware simulation using field programmable gate arrays (FPGAs), with a set of runtime services (ConcreteWare...perimeter protection, patch, and pray” is not aligned with the threat. Programmers will not bail us out of this situation (by writing defect free code...hosted on a Field Programmable Gate Array (FPGA), with a set of runtime services (concreteware) running on the hardware. Secure applications can be

Implementing a Microcontroller Watchdog with a Field-Programmable Gate Array (FPGA)

NASA Technical Reports Server (NTRS)

Straka, Bartholomew

2013-01-01

Reliability is crucial to safety. Redundancy of important system components greatly enhances reliability and hence safety. Field-Programmable Gate Arrays (FPGAs) are useful for monitoring systems and handling the logic necessary to keep them running with minimal interruption when individual components fail. A complete microcontroller watchdog with logic for failure handling can be implemented in a hardware description language (HDL.). HDL-based designs are vendor-independent and can be used on many FPGAs with low overhead.

Plastic fiber scintillator response to fast neutrons

NASA Astrophysics Data System (ADS)

Danly, C. R.; Sjue, S.; Wilde, C. H.; Merrill, F. E.; Haight, R. C.

2014-11-01

The Neutron Imaging System at NIF uses an array of plastic scintillator fibers in conjunction with a time-gated imaging system to form an image of the neutron emission from the imploded capsule. By gating on neutrons that have scattered from the 14.1 MeV DT energy to lower energy ranges, an image of the dense, cold fuel around the hotspot is also obtained. An unmoderated spallation neutron beamline at the Weapons Neutron Research facility at Los Alamos was used in conjunction with a time-gated imaging system to measure the yield of a scintillating fiber array over several energy bands ranging from 1 to 15 MeV. The results and comparison to simulation are presented.

Plastic fiber scintillator response to fast neutrons.

PubMed

Danly, C R; Sjue, S; Wilde, C H; Merrill, F E; Haight, R C

2014-11-01

The Neutron Imaging System at NIF uses an array of plastic scintillator fibers in conjunction with a time-gated imaging system to form an image of the neutron emission from the imploded capsule. By gating on neutrons that have scattered from the 14.1 MeV DT energy to lower energy ranges, an image of the dense, cold fuel around the hotspot is also obtained. An unmoderated spallation neutron beamline at the Weapons Neutron Research facility at Los Alamos was used in conjunction with a time-gated imaging system to measure the yield of a scintillating fiber array over several energy bands ranging from 1 to 15 MeV. The results and comparison to simulation are presented.

Digital MOS integrated circuits

NASA Astrophysics Data System (ADS)

Elmasry, M. I.

MOS in digital circuit design is considered along with aspects of digital VLSI, taking into account a comparison of MOSFET logic circuits, 1-micrometer MOSFET VLSI technology, a generalized guide for MOSFET miniaturization, processing technologies, novel circuit structures for VLSI, and questions of circuit and system design for VLSI. MOS memory cells and circuits are discussed, giving attention to a survey of high-density dynamic RAM cell concepts, one-device cells for dynamic random-access memories, variable resistance polysilicon for high density CMOS Ram, high performance MOS EPROMs using a stacked-gate cell, and the optimization of the latching pulse for dynamic flip-flop sensors. Programmable logic arrays are considered along with digital signal processors, microprocessors, static RAMs, and dynamic RAMs.

Characteristics of a semi-custom library development system

NASA Technical Reports Server (NTRS)

Yancey, M.; Cannon, R.

1990-01-01

Standard cell and gate array macro libraries are in common use with workstation computer aided design (CAD) tools for application specific integrated circuit (ASIC) semi-custom application and have resulted in significant improvements in the overall design efficiencies as contrasted with custom design methodologies. Similar design methodology enhancements in providing for the efficient development of the library cells is an important factor in responding to the need for continuous technology improvement. The characteristics of a library development system that provides design flexibility and productivity enhancements for the library development engineer as he provides libraries in the state-of-the-art process technologies are presented. An overview of Gould's library development system ('Accolade') is also presented.

QPatch: the missing link between HTS and ion channel drug discovery.

PubMed

Mathes, Chris; Friis, Søren; Finley, Michael; Liu, Yi

2009-01-01

The conventional patch clamp has long been considered the best approach for studying ion channel function and pharmacology. However, its low throughput has been a major hurdle to overcome for ion channel drug discovery. The recent emergence of higher throughput, automated patch clamp technology begins to break this bottleneck by providing medicinal chemists with high-quality, information-rich data in a more timely fashion. As such, these technologies have the potential to bridge a critical missing link between high-throughput primary screening and meaningful ion channel drug discovery programs. One of these technologies, the QPatch automated patch clamp system developed by Sophion Bioscience, records whole-cell ion channel currents from 16 or 48 individual cells in a parallel fashion. Here, we review the general applicability of the QPatch to studying a wide variety of ion channel types (voltage-/ligand-gated cationic/anionic channels) in various expression systems. The success rate of gigaseals, formation of the whole-cell configuration and usable cells ranged from 40-80%, depending on a number of factors including the cell line used, ion channel expressed, assay development or optimization time and expression level in these studies. We present detailed analyses of the QPatch features and results in case studies in which secondary screening assays were successfully developed for a voltage-gated calcium channel and a ligand-gated TRP channel. The increase in throughput compared to conventional patch clamp with the same cells was approximately 10-fold. We conclude that the QPatch, combining high data quality and speed with user friendliness and suitability for a wide array of ion channels, resides on the cutting edge of automated patch clamp technology and plays a pivotal role in expediting ion channel drug discovery.

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2011-01-01

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

NASA Astrophysics Data System (ADS)

Park, Hyeonwoo; Teramoto, Akinobu; Kuroda, Rihito; Suwa, Tomoyuki; Sugawa, Shigetoshi

2018-04-01

Localized stress-induced leakage current (SILC) has become a major problem in the reliability of flash memories. To reduce it, clarifying the SILC mechanism is important, and statistical measurement and analysis have to be carried out. In this study, we applied an array test circuit that can measure the SILC distribution of more than 80,000 nMOSFETs with various gate areas at a high speed (within 80 s) and a high accuracy (on the 10-17 A current order). The results clarified that the distributions of localized SILC in different gate areas follow a universal distribution assuming the same SILC defect density distribution per unit area, and the current of localized SILC defects does not scale down with the gate area. Moreover, the distribution of SILC defect density and its dependence on the oxide field for measurement (E OX-Measure) were experimentally determined for fabricated devices.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baart, T. A.; Vandersypen, L. M. K.; Kavli Institute of Nanoscience, Delft University of Technology, P.O. Box 5046, 2600 GA Delft

We report the computer-automated tuning of gate-defined semiconductor double quantum dots in GaAs heterostructures. We benchmark the algorithm by creating three double quantum dots inside a linear array of four quantum dots. The algorithm sets the correct gate voltages for all the gates to tune the double quantum dots into the single-electron regime. The algorithm only requires (1) prior knowledge of the gate design and (2) the pinch-off value of the single gate T that is shared by all the quantum dots. This work significantly alleviates the user effort required to tune multiple quantum dot devices.

Single Event Test Methodologies and System Error Rate Analysis for Triple Modular Redundant Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Allen, Gregory; Edmonds, Larry D.; Swift, Gary; Carmichael, Carl; Tseng, Chen Wei; Heldt, Kevin; Anderson, Scott Arlo; Coe, Michael

2010-01-01

We present a test methodology for estimating system error rates of Field Programmable Gate Arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilins Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.

Detection of Bioaerosols Using Single Particle Thermal Emission Spectroscopy (First-year Report)

DTIC Science & Technology

2012-02-01

cooled MCT detector with a noise equivalent power (NEP) of 7x10(–13) W/Hz, yields a detection S/N > 13 (assuming a sufficiently cooled background). We...dispersively resolved using 190-mm Horiba spectrometer that houses a time-gated 32-element mercury cadmium telluride ( MCT ) linear array. In this report...to 10.0 ms. Minimum integration (and readout) periods for the time-gated 32-element mercury cadmium telluride ( MCT ) linear array are 10 µs. Based

DIFMOS - A floating-gate electrically erasable nonvolatile semiconductor memory technology. [Dual Injector Floating-gate MOS

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1977-01-01

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.

Current Status of The Low Frequency All Sky Monitor

NASA Astrophysics Data System (ADS)

Dartez, Louis; Creighton, Teviet; Jenet, Fredrick; Dolch, Timothy; Boehler, Keith; Bres, Luis; Cole, Brent; Luo, Jing; Miller, Rossina; Murray, James; Reyes, Alex; Rivera, Jesse

2018-01-01

The Low Frequency All Sky Monitor (LoFASM) is a distributed array of cross-dipole antennas that are sensitive to radio frequencies from 10 to 88 MHz. LoFASM consists of antennas and front end electronics that were originally developed for the Long Wavelength Array by the U.S. Naval Research Lab, the University of New Mexico, Virginia Tech, and the Jet Propulsion Laboratory. LoFASM, funded by the U.S. Department of Defense, will initially consist of 4 stations, each consisting of 12 dual- polarization dipole antenna stands. The primary science goals of LoFASM will be the detection and study of low-frequency radio transients, a high priority science goal as deemed by the National Research Council’s ASTRO2010 decadal survey. The data acquisition system for the LoFASM antenna array uses Field Programmable Gate Array (FPGA) technology to implement a real time full Stokes spectrometer and data recorder. This poster presents an overview of the LoFASM Radio Telescope as well as the status of data analysis of initial commissioning observations.

Johnston Atoll Plutonium Cleanup Project. Contract bridge report. Technical report, 1 June-5 August 1993

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hellier, C.L.; Doane, R.W.

1995-04-01

This report continues the documentation of the operation of TMA/Eberline`s Segmented Gate System technology for removing mixed plutonium and americium contamination at DNA`s Johnston Atoll site. Contaminated feed is conveyed under arrays of radiation detectors coupled with sophisticated computer software developed by Eberline Instrument Corporation. Segmented gates (chutes) on pneumatically-driven pistons move forward when contamination is detected to remove only the contaminated portion from the main flow of feed material. Only about one pint of contaminant is removed during each diversion event. At the JA site, a 98% volume reduction has been achieved, with the remediated soil cleaned to DNA`smore » criteria for release for unrestricted use of 500 Bq/kg total transuranic alpha contamination and no hot particles of greater than 5000 Becquerrels. The low level waste concentrate is expected to be packaged for shipment to an approved defense waste disposal site.« less

Gallium arsenide processing for gate array logic

NASA Technical Reports Server (NTRS)

Cole, Eric D.

1989-01-01

The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

SU-E-T-350: Verification of Gating Performance of a New Elekta Gating Solution: Response Kit and Catalyst System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xie, X; Cao, D; Housley, D

2014-06-01

Purpose: In this work, we have tested the performance of new respiratory gating solutions for Elekta linacs. These solutions include the Response gating and the C-RAD Catalyst surface mapping system.Verification measurements have been performed for a series of clinical cases. We also examined the beam on latency of the system and its impact on delivery efficiency. Methods: To verify the benefits of tighter gating windows, a Quasar Respiratory Motion Platform was used. Its vertical-motion plate acted as a respiration surrogate and was tracked by the Catalyst system to generate gating signals. A MatriXX ion-chamber array was mounted on its longitudinal-movingmore » platform. Clinical plans are delivered to a stationary and moving Matrix array at 100%, 50% and 30% gating windows and gamma scores were calculated comparing moving delivery results to the stationary result. It is important to note that as one moves to tighter gating windows, the delivery efficiency will be impacted by the linac's beam-on latency. Using a specialized software package, we generated beam-on signals of lengths of 1000ms, 600ms, 450ms, 400ms, 350ms and 300ms. As the gating windows get tighter, one can expect to reach a point where the dose rate will fall to nearly zero, indicating that the gating window is close to beam-on latency. A clinically useful gating window needs to be significantly longer than the latency for the linac. Results: As expected, the use of tighter gating windows improved delivery accuracy. However, a lower limit of the gating window, largely defined by linac beam-on latency, exists at around 300ms. Conclusion: The Response gating kit, combined with the C-RAD Catalyst, provides an effective solution for respiratorygated treatment delivery. Careful patient selection, gating window design, even visual/audio coaching may be necessary to ensure both delivery quality and efficiency. This research project is funded by Elekta.« less

Downsampling Photodetector Array with Windowing

NASA Technical Reports Server (NTRS)

Patawaran, Ferze D.; Farr, William H.; Nguyen, Danh H.; Quirk, Kevin J.; Sahasrabudhe, Adit

2012-01-01

In a photon counting detector array, each pixel in the array produces an electrical pulse when an incident photon on that pixel is detected. Detection and demodulation of an optical communication signal that modulated the intensity of the optical signal requires counting the number of photon arrivals over a given interval. As the size of photon counting photodetector arrays increases, parallel processing of all the pixels exceeds the resources available in current application-specific integrated circuit (ASIC) and gate array (GA) technology; the desire for a high fill factor in avalanche photodiode (APD) detector arrays also precludes this. Through the use of downsampling and windowing portions of the detector array, the processing is distributed between the ASIC and GA. This allows demodulation of the optical communication signal incident on a large photon counting detector array, as well as providing architecture amenable to algorithmic changes. The detector array readout ASIC functions as a parallel-to-serial converter, serializing the photodetector array output for subsequent processing. Additional downsampling functionality for each pixel is added to this ASIC. Due to the large number of pixels in the array, the readout time of the entire photodetector is greater than the time between photon arrivals; therefore, a downsampling pre-processing step is done in order to increase the time allowed for the readout to occur. Each pixel drives a small counter that is incremented at every detected photon arrival or, equivalently, the charge in a storage capacitor is incremented. At the end of a user-configurable counting period (calculated independently from the ASIC), the counters are sampled and cleared. This downsampled photon count information is then sent one counter word at a time to the GA. For a large array, processing even the downsampled pixel counts exceeds the capabilities of the GA. Windowing of the array, whereby several subsets of pixels are designated for processing, is used to further reduce the computational requirements. The grouping of the designated pixel frame as the photon count information is sent one word at a time to the GA, the aggregation of the pixels in a window can be achieved by selecting only the designated pixel counts from the serial stream of photon counts, thereby obviating the need to store the entire frame of pixel count in the gate array. The pixel count se quence from each window can then be processed, forming lower-rate pixel statistics for each window. By having this processing occur in the GA rather than in the ASIC, future changes to the processing algorithm can be readily implemented. The high-bandwidth requirements of a photon counting array combined with the properties of the optical modulation being detected by the array present a unique problem that has not been addressed by current CCD or CMOS sensor array solutions.

Whispering galleries and the control of artificial atoms.

PubMed

Forrester, Derek Michael; Kusmartsev, Feodor V

2016-04-28

Quantum computation using artificial-atoms, such as novel superconducting circuits, can be sensitively controlled by external electromagnetic fields. These fields and the self-fields attributable to the coupled artificial-atoms influence the amount of quantum correlation in the system. However, control elements that can operate without complete destruction of the entanglement of the quantum-bits are difficult to engineer. Here we investigate the possibility of using closely-spaced-linear arrays of metallic-elliptical discs as whispering gallery waveguides to control artificial-atoms. The discs confine and guide radiation through the array with small notches etched into their sides that act as scatterers. We focus on π-ring artificial-atoms, which can generate their own spontaneous fluxes. We find that the micro-discs of the waveguides can be excited by terahertz frequency fields to exhibit whispering-modes and that a quantum-phase-gate composed of π-rings can be operated under their influence. Furthermore, we gauge the level of entanglement through the concurrence measure and show that under certain magnetic conditions a series of entanglement sudden-deaths and revivals occur between the two qubits. This is important for understanding the stability and life-time of qubit operations using, for example, a phase gate in a hybrid of quantum technologies composed of control elements and artificial-atoms.

Microdot - A Four-Bit Microcontroller Designed for Distributed Low-End Computing in Satellites

NASA Astrophysics Data System (ADS)

2002-03-01

Many satellites are an integrated collection of sensors and actuators that require dedicated real-time control. For single processor systems, additional sensors require an increase in computing power and speed to provide the multi-tasking capability needed to service each sensor. Faster processors cost more and consume more power, which taxes a satellite's power resources and may lead to shorter satellite lifetimes. An alternative design approach is a distributed network of small and low power microcontrollers designed for space that handle the computing requirements of each individual sensor and actuator. The design of microdot, a four-bit microcontroller for distributed low-end computing, is presented. The design is based on previous research completed at the Space Electronics Branch, Air Force Research Laboratory (AFRL/VSSE) at Kirtland AFB, NM, and the Air Force Institute of Technology at Wright-Patterson AFB, OH. The Microdot has 29 instructions and a 1K x 4 instruction memory. The distributed computing architecture is based on the Philips Semiconductor I2C Serial Bus Protocol. A prototype was implemented and tested using an Altera Field Programmable Gate Array (FPGA). The prototype was operable to 9.1 MHz. The design was targeted for fabrication in a radiation-hardened-by-design gate-array cell library for the TSMC 0.35 micrometer CMOS process.

A Compression Algorithm for Field Programmable Gate Arrays in the Space Environment

DTIC Science & Technology

2011-12-01

Bit 1 ,Bit 0P  . (V.3) Equation (V.3) is implemented with a string of XOR gates and Bit Basher blocks, as shown in Figure 31. As discussed in...5], the string of Bit Basher blocks are used to separate each 35-bit value into 35 one-bit values, and the string of XOR gates is used to

Large-Scale Precise Printing of Ultrathin Sol-Gel Oxide Dielectrics for Directly Patterned Solution-Processed Metal Oxide Transistor Arrays.

PubMed

Lee, Won-June; Park, Won-Tae; Park, Sungjun; Sung, Sujin; Noh, Yong-Young; Yoon, Myung-Han

2015-09-09

Ultrathin and dense metal oxide gate di-electric layers are reported by a simple printing of AlOx and HfOx sol-gel precursors. Large-area printed indium gallium zinc oxide (IGZO) thin-film transistor arrays, which exhibit mobilities >5 cm(2) V(-1) s(-1) and gate leakage current of 10(-9) A cm(-2) at a very low operation voltage of 2 V, are demonstrated by continuous simple bar-coated processes. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Qualification Strategies of Field Programmable Gate Arrays (FPGAs) for Space Application

NASA Technical Reports Server (NTRS)

Sheldon, Douglas; Schone, Harald

2005-01-01

This viewgraph document reviews the issue of using Field Programmable Gate Arrays (FPGAs) in Space Application, and the some of the strategies for qualifying the FPGA. Qualification and risk management of such complex systems requires new approaches. The paper presents a matrix approach to qualification has been presented that: - Complements historical specifications - Highlights the importance of device physics as a cornerstone to qualification. - Provides levels of risk management that expressly document trade offs. - Stresses the role of the FPGA vendor as team member in the development of modern spacecraft.

A software framework for pipelined arithmetic algorithms in field programmable gate arrays

NASA Astrophysics Data System (ADS)

Kim, J. B.; Won, E.

2018-03-01

Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++, ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.

Large-N correlator systems for low frequency radio astronomy

NASA Astrophysics Data System (ADS)

Foster, Griffin

Low frequency radio astronomy has entered a second golden age driven by the development of a new class of large-N interferometric arrays. The low frequency array (LOFAR) and a number of redshifted HI Epoch of Reionization (EoR) arrays are currently undergoing commission and regularly observing. Future arrays of unprecedented sensitivity and resolutions at low frequencies, such as the square kilometer array (SKA) and the hydrogen epoch of reionization array (HERA), are in development. The combination of advancements in specialized field programmable gate array (FPGA) hardware for signal processing, computing and graphics processing unit (GPU) resources, and new imaging and calibration algorithms has opened up the oft underused radio band below 300 MHz. These interferometric arrays require efficient implementation of digital signal processing (DSP) hardware to compute the baseline correlations. FPGA technology provides an optimal platform to develop new correlators. The significant growth in data rates from these systems requires automated software to reduce the correlations in real time before storing the data products to disk. Low frequency, widefield observations introduce a number of unique calibration and imaging challenges. The efficient implementation of FX correlators using FPGA hardware is presented. Two correlators have been developed, one for the 32 element BEST-2 array at Medicina Observatory and the other for the 96 element LOFAR station at Chilbolton Observatory. In addition, calibration and imaging software has been developed for each system which makes use of the radio interferometry measurement equation (RIME) to derive calibrations. A process for generating sky maps from widefield LOFAR station observations is presented. Shapelets, a method of modelling extended structures such as resolved sources and beam patterns has been adapted for radio astronomy use to further improve system calibration. Scaling of computing technology allows for the development of larger correlator systems, which in turn allows for improvements in sensitivity and resolution. This requires new calibration techniques which account for a broad range of systematic effects.

Enhancement mode GaN-based multiple-submicron channel array gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Wang, Chun-Chi

2018-04-01

To study the function of channel width in multiple-submicron channel array, we fabricated the enhancement mode GaN-based gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with a channel width of 450 nm and 195 nm, respectively. In view of the enhanced gate controllability in a narrower fin-channel structure, the transconductance was improved from 115 mS/mm to 151 mS/mm, the unit gain cutoff frequency was improved from 6.2 GHz to 6.8 GHz, and the maximum oscillation frequency was improved from 12.1 GHz to 13.1 GHz of the devices with a channel width of 195 nm, compared with the devices with a channel width of 450 nm.

Modular Adder Designs Using Optimal Reversible and Fault Tolerant Gates in Field-Coupled QCA Nanocomputing

NASA Astrophysics Data System (ADS)

Bilal, Bisma; Ahmed, Suhaib; Kakkar, Vipan

2018-02-01

The challenges which the CMOS technology is facing toward the end of the technology roadmap calls for an investigation of various logical and technological solutions to CMOS at the nano scale. Two such paradigms which are considered in this paper are the reversible logic and the quantum-dot cellular automata (QCA) nanotechnology. Firstly, a new 3 × 3 reversible and universal gate, RG-QCA, is proposed and implemented in QCA technology using conventional 3-input majority voter based logic. Further the gate is optimized by using explicit interaction of cells and this optimized gate is then used to design an optimized modular full adder in QCA. Another configuration of RG-QCA gate, CRG-QCA, is then proposed which is a 4 × 4 gate and includes the fault tolerant characteristics and parity preserving nature. The proposed CRG-QCA gate is then tested to design a fault tolerant full adder circuit. Extensive comparisons of gate and adder circuits are drawn with the existing literature and it is envisaged that our proposed designs perform better and are cost efficient in QCA technology.

Terahertz modulation based on surface plasmon resonance by self-gated graphene

NASA Astrophysics Data System (ADS)

Qian, Zhenhai; Yang, Dongxiao; Wang, Wei

2018-05-01

We theoretically and numerically investigate the extraordinary optical transmission through a terahertz metamaterial composed of metallic ring aperture arrays. The physical mechanism of different transmission peaks is elucidated to be magnetic polaritons or propagation surface plasmons with the help of surface current and electromagnetic field distributions at respective resonance frequencies. Then, we propose a high performance terahertz modulator based on the unique PSP resonance and combined with the metallic ring aperture arrays and a self-gated parallel-plate graphene capacitor. Because, to date, few researches have exhibited gate-controlled graphene modulation in terahertz region with low insertion losses, high modulation depth and low control voltage at room temperature. Here, we propose a 96% amplitude modulation with 0.7 dB insertion losses and ∼5.5 V gate voltage. Besides, we further study the absorption spectra of the modulator. When the transmission of modulator is very low, a 91% absorption can be achieved for avoiding damaging the source devices.

A Programmable and Configurable Mixed-Mode FPAA SoC

DTIC Science & Technology

2016-03-17

A Programmable and Configurable Mixed-Mode FPAA SoC Sahil Shah, Sihwan Kim, Farhan Adil, Jennifer Hasler, Suma George, Michelle Collins, Richard...Abstract: The authors present a Floating-Gate based, System-On-Chip large-scale Field- Programmable Analog Array IC that integrates divergent concepts...Floating-Gate, SoC, Command Word Classification This paper presents a Floating-Gate (FG) based, System- On-Chip (SoC) large-scale Field- Programmable

Two stage dual gate MESFET monolithic gain control amplifier for Ka-band

NASA Technical Reports Server (NTRS)

Sokolov, V.; Geddes, J.; Contolatis, A.

1987-01-01

A monolithic two stage gain control amplifier has been developed using submicron gate length dual gate MESFETs fabricated on ion implanted material. The amplifier has a gain of 12 dB at 30 GHz with a gain control range of over 30 dB. This ion implanted monolithic IC is readily integrable with other phased array receiver functions such as low noise amplifiers and phase shifters.

Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs

PubMed Central

Brady, Gerald J.; Way, Austin J.; Safron, Nathaniel S.; Evensen, Harold T.; Gopalan, Padma; Arnold, Michael S.

2016-01-01

Carbon nanotubes (CNTs) are tantalizing candidates for semiconductor electronics because of their exceptional charge transport properties and one-dimensional electrostatics. Ballistic transport approaching the quantum conductance limit of 2G0 = 4e2/h has been achieved in field-effect transistors (FETs) containing one CNT. However, constraints in CNT sorting, processing, alignment, and contacts give rise to nonidealities when CNTs are implemented in densely packed parallel arrays such as those needed for technology, resulting in a conductance per CNT far from 2G0. The consequence has been that, whereas CNTs are ultimately expected to yield FETs that are more conductive than conventional semiconductors, CNTs, instead, have underperformed channel materials, such as Si, by sixfold or more. We report quasi-ballistic CNT array FETs at a density of 47 CNTs μm−1, fabricated through a combination of CNT purification, solution-based assembly, and CNT treatment. The conductance is as high as 0.46 G0 per CNT. In parallel, the conductance of the arrays reaches 1.7 mS μm−1, which is seven times higher than the previous state-of-the-art CNT array FETs made by other methods. The saturated on-state current density is as high as 900 μA μm−1 and is similar to or exceeds that of Si FETs when compared at and equivalent gate oxide thickness and at the same off-state current density. The on-state current density exceeds that of GaAs FETs as well. This breakthrough in CNT array performance is a critical advance toward the exploitation of CNTs in logic, high-speed communications, and other semiconductor electronics technologies. PMID:27617293

Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs.

PubMed

Brady, Gerald J; Way, Austin J; Safron, Nathaniel S; Evensen, Harold T; Gopalan, Padma; Arnold, Michael S

2016-09-01

Carbon nanotubes (CNTs) are tantalizing candidates for semiconductor electronics because of their exceptional charge transport properties and one-dimensional electrostatics. Ballistic transport approaching the quantum conductance limit of 2G 0 = 4e (2)/h has been achieved in field-effect transistors (FETs) containing one CNT. However, constraints in CNT sorting, processing, alignment, and contacts give rise to nonidealities when CNTs are implemented in densely packed parallel arrays such as those needed for technology, resulting in a conductance per CNT far from 2G 0. The consequence has been that, whereas CNTs are ultimately expected to yield FETs that are more conductive than conventional semiconductors, CNTs, instead, have underperformed channel materials, such as Si, by sixfold or more. We report quasi-ballistic CNT array FETs at a density of 47 CNTs μm(-1), fabricated through a combination of CNT purification, solution-based assembly, and CNT treatment. The conductance is as high as 0.46 G 0 per CNT. In parallel, the conductance of the arrays reaches 1.7 mS μm(-1), which is seven times higher than the previous state-of-the-art CNT array FETs made by other methods. The saturated on-state current density is as high as 900 μA μm(-1) and is similar to or exceeds that of Si FETs when compared at and equivalent gate oxide thickness and at the same off-state current density. The on-state current density exceeds that of GaAs FETs as well. This breakthrough in CNT array performance is a critical advance toward the exploitation of CNTs in logic, high-speed communications, and other semiconductor electronics technologies.

High-Precision Pulse Generator

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor

2011-01-01

A document discusses a pulse generator with subnanosecond resolution implemented with a low-cost field-programmable gate array (FPGA) at low power levels. The method used exploits the fast carry chains of certain FPGAs. Prototypes have been built and tested in both Actel AX and Xilinx Virtex 4 technologies. In-flight calibration or control can be performed by using a similar and related technique as a time interval measurement circuit by measuring a period of the stable oscillator, as the delays through the fast carry chains will vary as a result of manufacturing variances as well as the result of environmental conditions (voltage, aging, temperature, and radiation).

Special purpose computer system with highly parallel pipelines for flow visualization using holography technology

NASA Astrophysics Data System (ADS)

Masuda, Nobuyuki; Sugie, Takashige; Ito, Tomoyoshi; Tanaka, Shinjiro; Hamada, Yu; Satake, Shin-ichi; Kunugi, Tomoaki; Sato, Kazuho

2010-12-01

We have designed a PC cluster system with special purpose computer boards for visualization of fluid flow using digital holographic particle tracking velocimetry (DHPTV). In this board, there is a Field Programmable Gate Array (FPGA) chip in which is installed a pipeline for calculating the intensity of an object from a hologram by fast Fourier transform (FFT). This cluster system can create 1024 reconstructed images from a 1024×1024-grid hologram in 0.77 s. It is expected that this system will contribute to the analysis of fluid flow using DHPTV.

Space Qualified High Speed Reed Solomon Encoder

NASA Technical Reports Server (NTRS)

Gambles, Jody W.; Winkert, Tom

1993-01-01

This paper reports a Class S CCSDS recommendation Reed Solomon encoder circuit baselined for several NASA programs. The chip is fabricated using United Technologies Microelectronics Center's UTE-R radiation-hardened gate array family, contains 64,000 p-n transistor pairs, and operates at a sustained output data rate of 200 MBits/s. The chip features a pin selectable message interleave depth of from 1 to 8 and supports output block lengths of 33 to 255 bytes. The UTE-R process is reported to produce parts that are radiation hardened to 16 Rads (Si) total dose and 1.0(exp -10) errors/bit-day.

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

NASA Astrophysics Data System (ADS)

Maheran, A. H. Afifah; Menon, P. S.; Ahmad, I.; Shaari, S.; Faizah, Z. A. Noor

2015-04-01

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (ILEAK) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO2) and tungsten silicide (WSix). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum ILEAK where the maximum predicted ILEAK value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/µm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device's leakage current. The absolute process parameters combination results in ILEAK mean value of 3.96821 nA/µm where is far lower than the predicted value.

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maheran, A. H. Afifah; Menon, P. S.; Shaari, S.

2015-04-24

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (I{sub LEAK}) onmore » PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO{sub 2}) and tungsten silicide (WSi{sub x}). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum I{sub LEAK} where the maximum predicted I{sub LEAK} value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/µm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device’s leakage current. The absolute process parameters combination results in I{sub LEAK} mean value of 3.96821 nA/µm where is far lower than the predicted value.« less

High-resolution depth profiling using a range-gated CMOS SPAD quanta image sensor.

PubMed

Ren, Ximing; Connolly, Peter W R; Halimi, Abderrahim; Altmann, Yoann; McLaughlin, Stephen; Gyongy, Istvan; Henderson, Robert K; Buller, Gerald S

2018-03-05

A CMOS single-photon avalanche diode (SPAD) quanta image sensor is used to reconstruct depth and intensity profiles when operating in a range-gated mode used in conjunction with pulsed laser illumination. By designing the CMOS SPAD array to acquire photons within a pre-determined temporal gate, the need for timing circuitry was avoided and it was therefore possible to have an enhanced fill factor (61% in this case) and a frame rate (100,000 frames per second) that is more difficult to achieve in a SPAD array which uses time-correlated single-photon counting. When coupled with appropriate image reconstruction algorithms, millimeter resolution depth profiles were achieved by iterating through a sequence of temporal delay steps in synchronization with laser illumination pulses. For photon data with high signal-to-noise ratios, depth images with millimeter scale depth uncertainty can be estimated using a standard cross-correlation approach. To enhance the estimation of depth and intensity images in the sparse photon regime, we used a bespoke clustering-based image restoration strategy, taking into account the binomial statistics of the photon data and non-local spatial correlations within the scene. For sparse photon data with total exposure times of 75 ms or less, the bespoke algorithm can reconstruct depth images with millimeter scale depth uncertainty at a stand-off distance of approximately 2 meters. We demonstrate a new approach to single-photon depth and intensity profiling using different target scenes, taking full advantage of the high fill-factor, high frame rate and large array format of this range-gated CMOS SPAD array.

TU-E-BRB-08: Dual Gated Volumetric Modulated Arc Therapy.

PubMed

Wu, J; Fahimian, B; Wu, H; Xing, L

2012-06-01

Gated Volumetric Modulated Arc Therapy (VMAT) is an emerging treatment modality for Stereotactic Body Radiotherapy (SBRT). However, gating significantly prolongs treatment time. In order to enhance treatment efficiency, a novel dual gated VMAT, in which dynamic arc deliveries are executed sequentially in alternating exhale and inhale phases, is proposed and evaluated experimentally. The essence of dual gated VMAT is to take advantage of the natural pauses that occur at inspiration and exhalation by alternatively delivering the dose at the two phases, instead of the exhale window only. The arc deliveries at the two phases are realized by rotating gantry forward at the exhale window and backward at the inhale in an alternative fashion. Custom XML scripts were developed in Varian's TrueBeam STx Developer Mode to enable dual gated VMAT delivery. RapidArc plans for a lung case were generated for both inhale and exhale phases. The two plans were then combined into a dual gated arc by interleaving the arc treatment nodes of the two RapidArc plans. The dual gated plan was delivered in the development mode of TrueBeam LINAC onto a motion phantom and the delivery was measured by using pinpoint chamber/film/diode array (delta 4). The measured dose distribution was compared with that computed using Eclipse AAA algorithm. The treatment delivery time was recorded and compared with the corresponding single gated plans. Relative to the corresponding single gated delivery, it was found that treatment time efficiency was improved by 95.5% for the case studied here. Pinpoint chamber absolute dose measurement agreed the calculation to within 0.7%. Diode chamber array measurements revealed that 97.5% of measurement points of dual gated RapidArc delivery passed the 3% and 3mm gamma-test criterion. A dual gated VMAT treatment has been developed and implemented successfully with nearly doubled treatment delivery efficiency. © 2012 American Association of Physicists in Medicine.

Pixel parallel localized driver design for a 128 x 256 pixel array 3D 1Gfps image sensor

NASA Astrophysics Data System (ADS)

Zhang, C.; Dao, V. T. S.; Etoh, T. G.; Charbon, E.

2017-02-01

In this paper, a 3D 1Gfps BSI image sensor is proposed, where 128 × 256 pixels are located in the top-tier chip and a 32 × 32 localized driver array in the bottom-tier chip. Pixels are designed with Multiple Collection Gates (MCG), which collects photons selectively with different collection gates being active at intervals of 1ns to achieve 1Gfps. For the drivers, a global PLL is designed, which consists of a ring oscillator with 6-stage current starved differential inverters, achieving a wide frequency tuning range from 40MHz to 360MHz (20ps rms jitter). The drivers are the replicas of the ring oscillator that operates within a PLL. Together with level shifters and XNOR gates, continuous 3.3V pulses are generated with desired pulse width, which is 1/12 of the PLL clock period. The driver array is activated by a START signal, which propagates through a highly balanced clock tree, to activate all the pixels at the same time with virtually negligible skew.

Resonant tunneling of 1-dimensional electrons across an array of 3-dimensionally confined potential wells

NASA Astrophysics Data System (ADS)

Allee, D. R.; Chou, S. Y.; Harris, J. S.; Pease, R. F. W.

A lateral resonant tunneling field effect transistor has been fabricated with a gate electrode in the form of a railway such that the two rails form a lateral double barrier potential at the GaAs/AlGaAs interface. The ties confine the electrons in the third dimension forming an array of potential boxes or three dimensionally confined potential wells. The width of the ties and rails is 50nm; the spacings between the ties and between the two rails are 230nm and 150nm respectively. The ties are 750nm long and extend beyond the the two rails forming one dimensional wires on either side. Conductance oscillations are observed in the drain current at 4.2K as the gate voltage is scanned. Comparison with devices with a solid gate, and with a monorail gate with ties fabricated on the same wafer suggest that these conductance oscillations are electron resonant tunneling from one dimensional wires through the quasi-bound states of the three dimensionally confined potential wells. Comparison with a device with a two rail gate without ties (previously published) indicates that additional confinement due to the ties enhances the strength of the conductance oscillations.

GATE Center of Excellence at UAB in Lightweight Materials for Automotive Applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

None

2011-07-31

This report summarizes the accomplishments of the UAB GATE Center of Excellence in Lightweight Materials for Automotive Applications. The first Phase of the UAB DOE GATE center spanned the period 2005-2011. The UAB GATE goals coordinated with the overall goals of DOE's FreedomCAR and Vehicles Technologies initiative and DOE GATE program. The FCVT goals are: (1) Development and validation of advanced materials and manufacturing technologies to significantly reduce automotive vehicle body and chassis weight without compromising other attributes such as safety, performance, recyclability, and cost; (2) To provide a new generation of engineers and scientists with knowledge and skills inmore » advanced automotive technologies. The UAB GATE focused on both the FCVT and GATE goals in the following manner: (1) Train and produce graduates in lightweight automotive materials technologies; (2) Structure the engineering curricula to produce specialists in the automotive area; (3) Leverage automotive related industry in the State of Alabama; (4) Expose minority students to advanced technologies early in their career; (5) Develop innovative virtual classroom capabilities tied to real manufacturing operations; and (6) Integrate synergistic, multi-departmental activities to produce new product and manufacturing technologies for more damage tolerant, cost-effective, and lighter automotive structures.« less

TID Effects of High-Z Material Spot Shields on FPGA Using MPTB Data

NASA Technical Reports Server (NTRS)

Hardage, Donna (Technical Monitor); Crain, S. H.; Mazur, J. E.; Looper, M. D.

2003-01-01

An experiment on the Microelectronics and Photonics Test Bed (MPTB) was testing lield programmable gate arrays using spot shields to extend the life of some of the devices being tested. It was expected that the unshielded parts would fail from a total ionizing dose (TID) and yet the opposite occurred. The data show that the devices failing from the TID effects are those with the spot shields attached. This effort is to determine the mechanism by which the environment is interacting with the high-Z material to enhance the TID in these field programmable gate arrays.

Note: The design of thin gap chamber simulation signal source based on field programmable gate array.

PubMed

Hu, Kun; Lu, Houbing; Wang, Xu; Li, Feng; Liang, Futian; Jin, Ge

2015-01-01

The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability.

Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong (Inventor); Herath, Jeffrey A. (Inventor)

2010-01-01

An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.

Note: The design of thin gap chamber simulation signal source based on field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hu, Kun; Wang, Xu; Li, Feng

The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability.

A control system based on field programmable gate array for papermaking sewage treatment

NASA Astrophysics Data System (ADS)

Zhang, Zi Sheng; Xie, Chang; Qing Xiong, Yan; Liu, Zhi Qiang; Li, Qing

2013-03-01

A sewage treatment control system is designed to improve the efficiency of papermaking wastewater treatment system. The automation control system is based on Field Programmable Gate Array (FPGA), coded with Very-High-Speed Integrate Circuit Hardware Description Language (VHDL), compiled and simulated with Quartus. In order to ensure the stability of the data used in FPGA, the data is collected through temperature sensors, water level sensor and online PH measurement system. The automatic control system is more sensitive, and both the treatment efficiency and processing power are increased. This work provides a new method for sewage treatment control.

Evaluation of the Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Array

NASA Technical Reports Server (NTRS)

Pang, Jackson; Liddicoat, Albert; Ralston, Jesse; Pingree, Paula

2006-01-01

The current implementation of the Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Arrays (TRIGA) is equipped with CFDP protocol and CCSDS Telemetry and Telecommand framing schemes to replace the CPU intensive software counterpart implementation for reliable deep space communication. We present the hardware/software co-design methodology used to accomplish high data rate throughput. The hardware CFDP protocol stack implementation is then compared against the two recent flight implementations. The results from our experiments show that TRIGA offers more than 3 orders of magnitude throughput improvement with less than one-tenth of the power consumption.

All optical programmable logic array (PLA)

NASA Astrophysics Data System (ADS)

Hiluf, Dawit

2018-03-01

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

Floating gate memory with charge storage dots array formed by Dps protein modified with site-specific binding peptides

NASA Astrophysics Data System (ADS)

Kamitake, Hiroki; Uenuma, Mutsunori; Okamoto, Naofumi; Horita, Masahiro; Ishikawa, Yasuaki; Yamashita, Ichro; Uraoka, Yukiharu

2015-05-01

We report a nanodot (ND) floating gate memory (NFGM) with a high-density ND array formed by a biological nano process. We utilized two kinds of cage-shaped proteins displaying SiO2 binding peptide (minTBP-1) on their outer surfaces: ferritin and Dps, which accommodate cobalt oxide NDs in their cavities. The diameters of the cobalt NDs were regulated by the cavity sizes of the proteins. Because minTBP-1 is strongly adsorbed on the SiO2 surface, high-density cobalt oxide ND arrays were obtained by a simple spin coating process. The densities of cobalt oxide ND arrays based on ferritin and Dps were 6.8 × 1011 dots cm-2 and 1.2 × 1012 dots cm-2, respectively. After selective protein elimination and embedding in a metal-oxide-semiconductor (MOS) capacitor, the charge capacities of both ND arrays were evaluated by measuring their C-V characteristics. The MOS capacitor embedded with the Dps ND array showed a wider memory window than the device embedded with the ferritin ND array. Finally, we fabricated an NFGM with a high-density ND array based on Dps, and confirmed its competent writing/erasing characteristics and long retention time.

Power-Combined GaN Amplifier with 2.28-W Output Power at 87 GHz

NASA Technical Reports Server (NTRS)

Fung, King Man; Ward, John; Chattopadhyay, Goutam; Lin, Robert H.; Samoska, Lorene A.; Kangaslahti, Pekka P.; Mehdi, Imran; Lambrigtsen, Bjorn H.; Goldsmith, Paul F.; Soria, Mary M.;

PCI-based WILDFIRE reconfigurable computing engines

NASA Astrophysics Data System (ADS)

Fross, Bradley K.; Donaldson, Robert L.; Palmer, Douglas J.

1996-10-01

WILDFORCE is the first PCI-based custom reconfigurable computer that is based on the Splash 2 technology transferred from the National Security Agency and the Institute for Defense Analyses, Supercomputing Research Center (SRC). The WILDFORCE architecture has many of the features of the WILDFIRE computer, such as field- programmable gate array (FPGA) based processing elements, linear array and crossbar interconnection, and high- performance memory and I/O subsystems. New features introduced in the PCI-based WILDFIRE systems include memory/processor options that can be added to any processing element. These options include static and dynamic memory, digital signal processors (DSPs), FPGAs, and microprocessors. In addition to memory/processor options, many different application specific connectors can be used to extend the I/O capabilities of the system, including systolic I/O, camera input and video display output. This paper also discusses how this new PCI-based reconfigurable computing engine is used for rapid-prototyping, real-time video processing and other DSP applications.

A time-resolved image sensor for tubeless streak cameras

NASA Astrophysics Data System (ADS)

Yasutomi, Keita; Han, SangMan; Seo, Min-Woong; Takasawa, Taishi; Kagawa, Keiichiro; Kawahito, Shoji

2014-03-01

This paper presents a time-resolved CMOS image sensor with draining-only modulation (DOM) pixels for tube-less streak cameras. Although the conventional streak camera has high time resolution, the device requires high voltage and bulky system due to the structure with a vacuum tube. The proposed time-resolved imager with a simple optics realize a streak camera without any vacuum tubes. The proposed image sensor has DOM pixels, a delay-based pulse generator, and a readout circuitry. The delay-based pulse generator in combination with an in-pixel logic allows us to create and to provide a short gating clock to the pixel array. A prototype time-resolved CMOS image sensor with the proposed pixel is designed and implemented using 0.11um CMOS image sensor technology. The image array has 30(Vertical) x 128(Memory length) pixels with the pixel pitch of 22.4um. .

A CCD experimental platform for large telescope in Antarctica based on FPGA

NASA Astrophysics Data System (ADS)

Zhu, Yuhua; Qi, Yongjun

2014-07-01

The CCD , as a detector , is one of the important components of astronomical telescopes. For a large telescope in Antarctica, a set of CCD detector system with large size, high sensitivity and low noise is indispensable. Because of the extremely low temperatures and unattended, system maintenance and software and hardware upgrade become hard problems. This paper introduces a general CCD controller experiment platform, using Field programmable gate array FPGA, which is, in fact, a large-scale field reconfigurable array. Taking the advantage of convenience to modify the system, construction of driving circuit, digital signal processing module, network communication interface, control algorithm validation, and remote reconfigurable module may realize. With the concept of integrated hardware and software, the paper discusses the key technology of building scientific CCD system suitable for the special work environment in Antarctica, focusing on the method of remote reconfiguration for controller via network and then offering a feasible hardware and software solution.

The Use of Field Programmable Gate Arrays (FPGA) in Small Satellite Communication Systems

NASA Technical Reports Server (NTRS)

Varnavas, Kosta; Sims, William Herbert; Casas, Joseph

2015-01-01

This paper will describe the use of digital Field Programmable Gate Arrays (FPGA) to contribute to advancing the state-of-the-art in software defined radio (SDR) transponder design for the emerging SmallSat and CubeSat industry and to provide advances for NASA as described in the TAO5 Communication and Navigation Roadmap (Ref 4). The use of software defined radios (SDR) has been around for a long time. A typical implementation of the SDR is to use a processor and write software to implement all the functions of filtering, carrier recovery, error correction, framing etc. Even with modern high speed and low power digital signal processors, high speed memories, and efficient coding, the compute intensive nature of digital filters, error correcting and other algorithms is too much for modern processors to get efficient use of the available bandwidth to the ground. By using FPGAs, these compute intensive tasks can be done in parallel, pipelined fashion and more efficiently use every clock cycle to significantly increase throughput while maintaining low power. These methods will implement digital radios with significant data rates in the X and Ka bands. Using these state-of-the-art technologies, unprecedented uplink and downlink capabilities can be achieved in a 1/2 U sized telemetry system. Additionally, modern FPGAs have embedded processing systems, such as ARM cores, integrated inside the FPGA allowing mundane tasks such as parameter commanding to occur easily and flexibly. Potential partners include other NASA centers, industry and the DOD. These assets are associated with small satellite demonstration flights, LEO and deep space applications. MSFC currently has an SDR transponder test-bed using Hardware-in-the-Loop techniques to evaluate and improve SDR technologies.

Reconfigurable, Cognitive Software-Defined Radio

NASA Technical Reports Server (NTRS)

Bhat, Arvind

2015-01-01

Software-defined radio (SDR) technology allows radios to be reconfigured to perform different communication functions without using multiple radios to accomplish each task. Intelligent Automation, Inc., has developed SDR platforms that switch adaptively between different operation modes. The innovation works by modifying both transmit waveforms and receiver signal processing tasks. In Phase I of the project, the company developed SDR cognitive capabilities, including adaptive modulation and coding (AMC), automatic modulation recognition (AMR), and spectrum sensing. In Phase II, these capabilities were integrated into SDR platforms. The reconfigurable transceiver design employs high-speed field-programmable gate arrays, enabling multimode operation and scalable architecture. Designs are based on commercial off-the-shelf (COTS) components and are modular in nature, making it easier to upgrade individual components rather than redesigning the entire SDR platform as technology advances.

A novel nanoscaled Schottky barrier based transmission gate and its digital circuit applications

NASA Astrophysics Data System (ADS)

Kumar, Sunil; Loan, Sajad A.; Alamoud, Abdulrahman M.

2017-04-01

In this work we propose and simulate a compact nanoscaled transmission gate (TG) employing a single Schottky barrier based transistor in the transmission path and a single transistor based Sajad-Sunil-Schottky (SSS) device as an inverter. Therefore, just two transistors are employed to realize a complete transmission gate which normally consumes four transistors in the conventional technology. The transistors used to realize the transmission path and the SSS inverter in the proposed TG are the double gate Schottky barrier devices, employing stacks of two metal silicides, platinum silicide (PtSi) and erbium silicide (ErSi). It has been observed that the realization of the TG gate by the proposed technology has resulted into a compact structure, with reduced component count, junctions, interconnections and regions in comparison to the conventional technology. The further focus of this work is on the application part of the proposed technology. So for the first time, the proposed technology has been used to realize various combinational circuits, like a two input AND gate, a 2:1 multiplexer and a two input XOR circuits. It has been observed that the transistor count has got reduced by half in a TG, two input AND gate, 2:1 multiplexer and in a two input XOR gate. Therefore, a significant reduction in transistor count and area requirement can be achieved by using the proposed technology. The proposed technology can be also used to perform the compact realization of other combinational and sequential circuitry in future.

Compact SPAD-Based Pixel Architectures for Time-Resolved Image Sensors

PubMed Central

Perenzoni, Matteo; Pancheri, Lucio; Stoppa, David

2016-01-01

This paper reviews the state of the art of single-photon avalanche diode (SPAD) image sensors for time-resolved imaging. The focus of the paper is on pixel architectures featuring small pixel size (<25 μm) and high fill factor (>20%) as a key enabling technology for the successful implementation of high spatial resolution SPAD-based image sensors. A summary of the main CMOS SPAD implementations, their characteristics and integration challenges, is provided from the perspective of targeting large pixel arrays, where one of the key drivers is the spatial uniformity. The main analog techniques aimed at time-gated photon counting and photon timestamping suitable for compact and low-power pixels are critically discussed. The main features of these solutions are the adoption of analog counting techniques and time-to-analog conversion, in NMOS-only pixels. Reliable quantum-limited single-photon counting, self-referenced analog-to-digital conversion, time gating down to 0.75 ns and timestamping with 368 ps jitter are achieved. PMID:27223284

Johnston Atoll Plutonium Cleanup Project, plant modification and operation. Volume 1. Annual report option year 2. Technical report, 1 October 1992-24 May 1993

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moroney, K.S.; Moroney, J.D.; Johnson, N.R.

1995-04-01

This report continues the documentation of the operation of TMA/Eberline`s Segmented Gate System technology for removing mixed plutonium and americium contamination at DNA`s Johnston Atoll site. Contaminated feed is conveyed under arrays of radiation detectors coupled with sophisticated computer software developed by Eberline Instrument Corporation. Segmented gates (chutes) on pneumatically-driven pistons move forward when contamination is detected to remove only the contaminated portion from the main flow of feed material. Only about one pint of contaminant is removed during each diversion event. At the JA site, a 98% volume reduction has been achieved, with the remediated soil cleaned to DNA`smore » criteria for release for unrestricted use of 500 Bq/kg total tnansuranic alpha contamination and no hot particles of greater than 5000 Becquerrels. The low level waste concentrate is expected to be packaged for shipment to an approved defense waste disposal site.« less

Johnston Atoll Plutonium Cleanup Project. Plant modification and operation. Volume 2. Annual report option year 2. Appendix A. Technical report, 1 October 1992-24 May 1993

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moroney, K.S.; Moroney, J.D.; Johnson, N.R.

1995-04-01

This report continues the documentation of the operation of TMA/Eberline`s Segmented Gate System technology for removing mixed plutonium and americium contamination at DNA`s Johnston Atoll site. Contaminated feed is conveyed under arrays of radiation detectors coupled with sophisticated computer software developed by Eberline Instrument Corporation. Segmented gates (chutes) on pneumatically-driven pistons move forward when contamination is detected to remove only the contaminated portion from the main flow of feed material. Only about one pint of contaminant is removed during each diversion event. At the JA site, a 98% volume reduction has been achieved, with the remediated soil cleaned to DNA`smore » criteria for release for unrestricted use of 500 Bq/kg total transuranic alpha contamination and no hot particles of greater than 5000 Becquerrels. The low level waste concentrate is expected to be packaged for shipment to an approved defense waste disposal site.« less

Johnston Atoll Plutonium Cleanup Project, plant modification and operation. Volume 3. Annual report option year 2. Appendices b through h. Technical report, 1 October 1992-24 May 1993

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moroney, K.S.; Moroney, J.D.; Johnson, N.R.

1995-04-01

This report continues the documentation of the operation of TMA/Eberline`s Segmented Gate System technology for removing mixed plutonium and americium contamination at DNA`s Johnston Atoll site. Contaminated feed is conveyed under arrays of radiation detectors coupled with sophisticated computer software developed by Eberline Instrument Corporation. Segmented gates (chutes) on pneumatically-driven pistons move forward when contamination is detected to remove only the contaminated portion from the main flow of feed material. Only about one pint of contaminant is removed during each diversion event. At the JA site, a 98% volume reduction has been achieved, with the remediated soil cleaned to DNA`smore » criteria for release for unrestricted use of 500 Bq/kg total transuranic alpha contamination and no hot particles of greater than 5000 Becquerrels. The low level waste concentrate is expected to be packaged for shipment to an approved defense waste disposal site.« less

A nanocryotron comparator can connect single-flux-quantum circuits to conventional electronics

NASA Astrophysics Data System (ADS)

Zhao, Qing-Yuan; McCaughan, Adam N.; Dane, Andrew E.; Berggren, Karl K.; Ortlepp, Thomas

2017-04-01

Integration with conventional electronics offers a straightforward and economical approach to upgrading existing superconducting technologies, such as scaling up superconducting detectors into large arrays and combining single flux quantum (SFQ) digital circuits with semiconductor logic gates and memories. However, direct output signals from superconducting devices (e.g., Josephson junctions) are usually not compatible with the input requirements of conventional devices (e.g., transistors). Here, we demonstrate the use of a single three-terminal superconducting-nanowire device, called the nanocryotron (nTron), as a digital comparator to combine SFQ circuits with mature semiconductor circuits such as complementary metal oxide semiconductor (CMOS) circuits. Since SFQ circuits can digitize output signals from general superconducting devices and CMOS circuits can interface existing CMOS-compatible electronics, our results demonstrate the feasibility of a general architecture that uses an nTron as an interface to realize a ‘super-hybrid’ system consisting of superconducting detectors, superconducting quantum electronics, CMOS logic gates and memories, and other conventional electronics.

Advanced modulation technology development for earth station demodulator applications. Coded modulation system development

NASA Technical Reports Server (NTRS)

Miller, Susan P.; Kappes, J. Mark; Layer, David H.; Johnson, Peter N.

1990-01-01

A jointly optimized coded modulation system is described which was designed, built, and tested by COMSAT Laboratories for NASA LeRC which provides a bandwidth efficiency of 2 bits/s/Hz at an information rate of 160 Mbit/s. A high speed rate 8/9 encoder with a Viterbi decoder and an Octal PSK modem are used to achieve this. The BER performance is approximately 1 dB from the theoretically calculated value for this system at a BER of 5 E-7 under nominal conditions. The system operates in burst mode for downlink applications and tests have demonstrated very little degradation in performance with frequency and level offset. Unique word miss rate measurements were conducted which demonstrate reliable acquisition at low values of Eb/No. Codec self tests have verified the performance of this subsystem in a stand alone mode. The codec is capable of operation at a 200 Mbit/s information rate as demonstrated using a codec test set which introduces noise digitally. The measured performance is within 0.2 dB of the computer simulated predictions. A gate array implementation of the most time critical element of the high speed Viterbi decoder was completed. This gate array add-compare-select chip significantly reduces the power consumption and improves the manufacturability of the decoder. This chip has general application in the implementation of high speed Viterbi decoders.

Design, development, fabrication and delivery of register and multiplexer units. [CMOS monolithic chip development

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardi, T.

1978-01-01

Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated. The CMOS standard cell array technique was selected and implemented. Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation. One of the chip types, multiplexer register type 1, is fabricated on a 0.143 x 0.123 inch chip. It uses nine standard cell types for a total of 54 standard cells. This involves more than 350 transistors and has the functional equivalent of 111 gates. The second chip, multiplexer register type 2, is housed on a 0.12 x 0.12 inch die. It uses 13 standard cell types, for a total of 42 standard cells. It contains more than 300 transistors, the functional equivalent of 112 gates. All of the hermetically sealed units were initially screened for proper functional operation. The static leakage and the dynamic leakage were measured. Dynamic measurements were made and recorded. At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1. At 5 V these units shifted data at a 6.6 MHz rate. The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C.

ADMET biosensors: up-to-date issues and strategies.

PubMed

Fang, Yan; Offenhaeusser, Andrease

2004-12-01

This insight review introduces the new concepts, theories, technology, instruments, frontier issues, and key strategies of ADMET (absorption, distribution, metabolism, elimination, and toxicity) biosensors, from the fermi to the quantum levels. Information about ADMET, originating from one author's invention, a patented pharmacotherapy for rescuing cardio-cerebral vascular stunning and regulating vascular endothelial growth-factor signaling at the post-genomic level, can be detected by a new generation of ADMET biosensor. This is a single-cell/single-molecule field-effect transistor (FET) hybrid system, where single molecules or single cells are assembled at the FET surface in a high density array manner via complementary metal-oxide-semiconductor (CMOS)-compatible technologies. Within a given nanometer distance, ADMET-mediated oxidation-reduction (redox) potentials, electrochemistry responses, and electron transfer processes can be simultaneously and directly probed by the gates of field-effect transistor arrays. The nanometer details of the functional coupling principles and characterization technologies of DNA single-molecule/single-cell FETs, as well as the design of lab-on-a-chip instruments, are indicated. Four frontier issues and key strategies are elucidated in detail. This can lead to innovative technology for high-throughout screening of labs-on-chips to resolve the pharmaceutical industry's current bottleneck via novel, FET-based drug discovery and single-molecule/single-cell screening methods, which can bring about a pharmaceutical industry revolution in the 21st century.

An Undergraduate Survey Course on Asynchronous Sequential Logic, Ladder Logic, and Fuzzy Logic

ERIC Educational Resources Information Center

Foster, D. L.

2012-01-01

For a basic foundation in computer engineering, universities traditionally teach synchronous sequential circuit design, using discrete gates or field programmable gate arrays, and a microcomputers course that includes basic I/O processing. These courses, though critical, expose students to only a small subset of tools. At co-op schools like…

GateKeeper: a new hardware architecture for accelerating pre-alignment in DNA short read mapping.

PubMed

Alser, Mohammed; Hassan, Hasan; Xin, Hongyi; Ergin, Oguz; Mutlu, Onur; Alkan, Can

2017-11-01

High throughput DNA sequencing (HTS) technologies generate an excessive number of small DNA segments -called short reads- that cause significant computational burden. To analyze the entire genome, each of the billions of short reads must be mapped to a reference genome based on the similarity between a read and 'candidate' locations in that reference genome. The similarity measurement, called alignment, formulated as an approximate string matching problem, is the computational bottleneck because: (i) it is implemented using quadratic-time dynamic programming algorithms and (ii) the majority of candidate locations in the reference genome do not align with a given read due to high dissimilarity. Calculating the alignment of such incorrect candidate locations consumes an overwhelming majority of a modern read mapper's execution time. Therefore, it is crucial to develop a fast and effective filter that can detect incorrect candidate locations and eliminate them before invoking computationally costly alignment algorithms. We propose GateKeeper, a new hardware accelerator that functions as a pre-alignment step that quickly filters out most incorrect candidate locations. GateKeeper is the first design to accelerate pre-alignment using Field-Programmable Gate Arrays (FPGAs), which can perform pre-alignment much faster than software. When implemented on a single FPGA chip, GateKeeper maintains high accuracy (on average >96%) while providing, on average, 90-fold and 130-fold speedup over the state-of-the-art software pre-alignment techniques, Adjacency Filter and Shifted Hamming Distance (SHD), respectively. The addition of GateKeeper as a pre-alignment step can reduce the verification time of the mrFAST mapper by a factor of 10. https://github.com/BilkentCompGen/GateKeeper. mohammedalser@bilkent.edu.tr or onur.mutlu@inf.ethz.ch or calkan@cs.bilkent.edu.tr. Supplementary data are available at Bioinformatics online. © The Author (2017). Published by Oxford University Press. All rights reserved. For Permissions, please email: journals.permissions@oup.com

An optimized nanoparticle separator enabled by electron beam induced deposition

NASA Astrophysics Data System (ADS)

Fowlkes, J. D.; Doktycz, M. J.; Rack, P. D.

2010-04-01

Size-based separations technologies will inevitably benefit from advances in nanotechnology. Direct-write nanofabrication provides a useful mechanism for depositing/etching nanoscale elements in environments otherwise inaccessible to conventional nanofabrication techniques. Here, electron beam induced deposition was used to deposit an array of nanoscale features in a 3D environment with minimal material proximity effects outside the beam-interaction region. Specifically, the membrane component of a nanoparticle separator was fabricated by depositing a linear array of sharply tipped nanopillars, with a singular pitch, designed for sub-50 nm nanoparticle permeability. The nanopillar membrane was used in a dual capacity to control the flow of nanoparticles in the transaxial direction of the array while facilitating the sealing of the cellular-sized compartment in the paraxial direction. An optimized growth recipe resulted which (1) maximized the growth efficiency of the membrane (which minimizes proximity effects) and (2) preserved the fidelity of the spacing between nanopillars (which maximizes the size-based gating quality of the membrane) while (3) maintaining sharp nanopillar apexes for impaling an optically transparent polymeric lid critical for device sealing.

Cryogenic on-chip multiplexer for the study of quantum transport in 256 split-gate devices

NASA Astrophysics Data System (ADS)

Al-Taie, H.; Smith, L. W.; Xu, B.; See, P.; Griffiths, J. P.; Beere, H. E.; Jones, G. A. C.; Ritchie, D. A.; Kelly, M. J.; Smith, C. G.

2013-06-01

We present a multiplexing scheme for the measurement of large numbers of mesoscopic devices in cryogenic systems. The multiplexer is used to contact an array of 256 split gates on a GaAs/AlGaAs heterostructure, in which each split gate can be measured individually. The low-temperature conductance of split-gate devices is governed by quantum mechanics, leading to the appearance of conductance plateaux at intervals of 2e2/h. A fabrication-limited yield of 94% is achieved for the array, and a "quantum yield" is also defined, to account for disorder affecting the quantum behaviour of the devices. The quantum yield rose from 55% to 86% after illuminating the sample, explained by the corresponding increase in carrier density and mobility of the two-dimensional electron gas. The multiplexer is a scalable architecture, and can be extended to other forms of mesoscopic devices. It overcomes previous limits on the number of devices that can be fabricated on a single chip due to the number of electrical contacts available, without the need to alter existing experimental set ups.

The quantal nature of Ca2+ sparks and in situ operation of the ryanodine receptor array in cardiac cells.

PubMed

Wang, Shi Qiang; Stern, Michael D; Ríos, Eduardo; Cheng, Heping

2004-03-16

Intracellular Ca(2+) release in many types of cells is mediated by ryanodine receptor Ca(2+) release channels (RyRCs) that are assembled into two-dimensional paracrystalline arrays in the endoplasmic/sarcoplasmic reticulum. However, the in situ operating mechanism of the RyRC array is unknown. Here, we found that the elementary Ca(2+) release events, Ca(2+) sparks from individual RyRC arrays in rat ventricular myocytes, exhibit quantized Ca(2+) release flux. Analysis of the quantal property of Ca(2+) sparks provided a view of unitary Ca(2+) current and gating kinetics of the RyRC in intact cells and revealed that spark activation involves dynamic recruitment of small, variable cohorts of RyRCs. Intriguingly, interplay of RyRCs in multichannel sparks renders an unusual, thermodynamically irreversible mode of channel gating that is unshared by an RyRC acting solo, nor by RyRCs in vitro. Furthermore, an array-based inhibitory feedback, overriding the regenerative Ca(2+)-induced Ca(2+) release of RyRCs, provides a supramolecular mechanism for the microscopic stability of intracellular Ca(2+) signaling.

Time-Reversal MUSIC Imaging with Time-Domain Gating Technique

NASA Astrophysics Data System (ADS)

Choi, Heedong; Ogawa, Yasutaka; Nishimura, Toshihiko; Ohgane, Takeo

A time-reversal (TR) approach with multiple signal classification (MUSIC) provides super-resolution for detection and localization using multistatic data collected from an array antenna system. The theory of TR-MUSIC assumes that the number of antenna elements is greater than that of scatterers (targets). Furthermore, it requires many sets of frequency-domain data (snapshots) in seriously noisy environments. Unfortunately, these conditions are not practical for real environments due to the restriction of a reasonable antenna structure as well as limited measurement time. We propose an approach that treats both noise reduction and relaxation of the transceiver restriction by using a time-domain gating technique accompanied with the Fourier transform before applying the TR-MUSIC imaging algorithm. Instead of utilizing the conventional multistatic data matrix (MDM), we employ a modified MDM obtained from the gating technique. The resulting imaging functions yield more reliable images with only a few snapshots regardless of the limitation of the antenna arrays.

Power reduction by power gating in differential pair type spin-transfer-torque magnetic random access memories for low-power nonvolatile cache memories

NASA Astrophysics Data System (ADS)

Ohsawa, Takashi; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2014-01-01

Array operation currents in spin-transfer-torque magnetic random access memories (STT-MRAMs) that use four differential pair type magnetic tunnel junction (MTJ)-based memory cells (4T2MTJ, two 6T2MTJs and 8T2MTJ) are simulated and compared with that in SRAM. With L3 cache applications in mind, it is assumed that the memories are composed of 32 Mbyte capacity to be accessed in 64 byte in parallel. All the STT-MRAMs except for the 8T2MTJ one are designed with 32 bit fine-grained power gating scheme applied to eliminate static currents in the memory cells that are not accessed. The 8T2MTJ STT-MRAM, the cell’s design concept being not suitable for the fine-grained power gating, loads and saves 32 Mbyte data in 64 Mbyte unit per 1 Mbit sub-array in 2 × 103 cycles. It is shown that the array operation current of the 4T2MTJ STT-MRAM is 70 mA averaged in 15 ns write cycles at Vdd = 0.9 V. This is the smallest among the STT-MRAMs, about the half of the low standby power (LSTP) SRAM whose array operation current is totally dominated by the cells’ subthreshold leakage.

Neural control of cursor trajectory and click by a human with tetraplegia 1000 days after implant of an intracortical microelectrode array

NASA Astrophysics Data System (ADS)

Simeral, J. D.; Kim, S.-P.; Black, M. J.; Donoghue, J. P.; Hochberg, L. R.

2011-04-01

The ongoing pilot clinical trial of the BrainGate neural interface system aims in part to assess the feasibility of using neural activity obtained from a small-scale, chronically implanted, intracortical microelectrode array to provide control signals for a neural prosthesis system. Critical questions include how long implanted microelectrodes will record useful neural signals, how reliably those signals can be acquired and decoded, and how effectively they can be used to control various assistive technologies such as computers and robotic assistive devices, or to enable functional electrical stimulation of paralyzed muscles. Here we examined these questions by assessing neural cursor control and BrainGate system characteristics on five consecutive days 1000 days after implant of a 4 × 4 mm array of 100 microelectrodes in the motor cortex of a human with longstanding tetraplegia subsequent to a brainstem stroke. On each of five prospectively-selected days we performed time-amplitude sorting of neuronal spiking activity, trained a population-based Kalman velocity decoding filter combined with a linear discriminant click state classifier, and then assessed closed-loop point-and-click cursor control. The participant performed both an eight-target center-out task and a random target Fitts metric task which was adapted from a human-computer interaction ISO standard used to quantify performance of computer input devices. The neural interface system was further characterized by daily measurement of electrode impedances, unit waveforms and local field potentials. Across the five days, spiking signals were obtained from 41 of 96 electrodes and were successfully decoded to provide neural cursor point-and-click control with a mean task performance of 91.3% ± 0.1% (mean ± s.d.) correct target acquisition. Results across five consecutive days demonstrate that a neural interface system based on an intracortical microelectrode array can provide repeatable, accurate point-and-click control of a computer interface to an individual with tetraplegia 1000 days after implantation of this sensor.

Neural control of cursor trajectory and click by a human with tetraplegia 1000 days after implant of an intracortical microelectrode array

PubMed Central

Simeral, J D; Kim, S-P; Black, M J; Donoghue, J P; Hochberg, L R

2013-01-01

The ongoing pilot clinical trial of the BrainGate neural interface system aims in part to assess the feasibility of using neural activity obtained from a small-scale, chronically implanted, intracortical microelectrode array to provide control signals for a neural prosthesis system. Critical questions include how long implanted microelectrodes will record useful neural signals, how reliably those signals can be acquired and decoded, and how effectively they can be used to control various assistive technologies such as computers and robotic assistive devices, or to enable functional electrical stimulation of paralyzed muscles. Here we examined these questions by assessing neural cursor control and BrainGate system characteristics on five consecutive days 1000 days after implant of a 4 × 4 mm array of 100 microelectrodes in the motor cortex of a human with longstanding tetraplegia subsequent to a brainstem stroke. On each of five prospectively-selected days we performed time-amplitude sorting of neuronal spiking activity, trained a population-based Kalman velocity decoding filter combined with a linear discriminant click state classifier, and then assessed closed-loop point-and-click cursor control. The participant performed both an eight-target center-out task and a random target Fitts metric task which was adapted from a human-computer interaction ISO standard used to quantify performance of computer input devices. The neural interface system was further characterized by daily measurement of electrode impedances, unit waveforms and local field potentials. Across the five days, spiking signals were obtained from 41 of 96 electrodes and were successfully decoded to provide neural cursor point-and-click control with a mean task performance of 91.3% ± 0.1% (mean ± s.d.) correct target acquisition. Results across five consecutive days demonstrate that a neural interface system based on an intracortical microelectrode array can provide repeatable, accurate point-and-click control of a computer interface to an individual with tetraplegia 1000 days after implantation of this sensor. PMID:21436513

Towards a DNA Nanoprocessor: Reusable Tile-Integrated DNA Circuits.

PubMed

Gerasimova, Yulia V; Kolpashchikov, Dmitry M

2016-08-22

Modern electronic microprocessors use semiconductor logic gates organized on a silicon chip to enable efficient inter-gate communication. Here, arrays of communicating DNA logic gates integrated on a single DNA tile were designed and used to process nucleic acid inputs in a reusable format. Our results lay the foundation for the development of a DNA nanoprocessor, a small and biocompatible device capable of performing complex analyses of DNA and RNA inputs. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Remotely Powered Reconfigurable Receiver for Extreme Environment Sensing Platforms

NASA Technical Reports Server (NTRS)

Sheldon, Douglas J.

2012-01-01

Wireless sensors connected in a local network offer revolutionary exploration capabilities, but the current solutions do not work in extreme environments of low temperatures (200K) and low to moderate radiation levels (<50 krad). These sensors (temperature, radiation, infrared, etc.) would need to operate outside the spacecraft/ lander and be totally independent of power from the spacecraft/lander. Flash memory field-programmable gate arrays (FPGAs) are being used as the main signal processing and protocol generation platform in a new receiver. Flash-based FPGAs have been shown to have at least 100 reduced standby power and 10 reduction operating power when compared to normal SRAM-based FPGA technology.

Radiation-Tolerant Intelligent Memory Stack - RTIMS

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong; Herath, Jeffrey A.

2011-01-01

This innovation provides reconfigurable circuitry and 2-Gb of error-corrected or 1-Gb of triple-redundant digital memory in a small package. RTIMS uses circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field-programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuits are stacked into a module of 42.7 42.7 13 mm. Triple module redundancy, current limiting, configuration scrubbing, and single- event function interrupt detection are employed to mitigate radiation effects. The novel self-scrubbing and single event functional interrupt (SEFI) detection allows a relatively soft FPGA to become radiation tolerant without external scrubbing and monitoring hardware

FPGA-based real time processing of the Plenoptic Wavefront Sensor

NASA Astrophysics Data System (ADS)

Rodríguez-Ramos, L. F.; Marín, Y.; Díaz, J. J.; Piqueras, J.; García-Jiménez, J.; Rodríguez-Ramos, J. M.

The plenoptic wavefront sensor combines measurements at pupil and image planes in order to obtain simultaneously wavefront information from different points of view, being capable to sample the volume above the telescope to extract the tomographic information of the atmospheric turbulence. The advantages of this sensor are presented elsewhere at this conference (José M. Rodríguez-Ramos et al). This paper will concentrate in the processing required for pupil plane phase recovery, and its computation in real time using FPGAs (Field Programmable Gate Arrays). This technology eases the implementation of massive parallel processing and allows tailoring the system to the requirements, maintaining flexibility, speed and cost figures.

Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms.

PubMed

Pruttivarasin, Thaned; Katori, Hidetoshi

2015-11-01

We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 transistor-transistor logic (TTL) channels with a timing resolution of 40 ns and contains a built-in 100 MHz frequency counter for counting electrical pulses from a photo-multiplier tube. There are 16 independent direct-digital-synthesizers RF sources with fast (rise-time of ∼60 ns) amplitude switching and sub-mHz frequency tuning from 0 to 800 MHz.

Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pruttivarasin, Thaned, E-mail: thaned.pruttivarasin@riken.jp; Katori, Hidetoshi; Innovative Space-Time Project, ERATO, JST, Bunkyo-ku, Tokyo 113-8656

We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 transistor-transistor logic (TTL) channels with a timing resolution of 40 ns and contains a built-in 100 MHz frequency counter for counting electrical pulses from a photo-multiplier tube. There are 16 independent direct-digital-synthesizers RF sources with fast (rise-time of ∼60 ns) amplitude switching and sub-mHz frequency tuning from 0 to 800 MHz.

CMOS Active-Pixel Image Sensor With Simple Floating Gates

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Assessing the potential of surface-immobilized molecular logic machines for integration with solid state technology.

PubMed

Dunn, Katherine E; Trefzer, Martin A; Johnson, Steven; Tyrrell, Andy M

2016-08-01

Molecular computation with DNA has great potential for low power, highly parallel information processing in a biological or biochemical context. However, significant challenges remain for the field of DNA computation. New technology is needed to allow multiplexed label-free readout and to enable regulation of molecular state without addition of new DNA strands. These capabilities could be provided by hybrid bioelectronic systems in which biomolecular computing is integrated with conventional electronics through immobilization of DNA machines on the surface of electronic circuitry. Here we present a quantitative experimental analysis of a surface-immobilized OR gate made from DNA and driven by strand displacement. The purpose of our work is to examine the performance of a simple representative surface-immobilized DNA logic machine, to provide valuable information for future work on hybrid bioelectronic systems involving DNA devices. We used a quartz crystal microbalance to examine a DNA monolayer containing approximately 5×10(11)gatescm(-2), with an inter-gate separation of approximately 14nm, and we found that the ensemble of gates took approximately 6min to switch. The gates could be switched repeatedly, but the switching efficiency was significantly degraded on the second and subsequent cycles when the binding site for the input was near to the surface. Otherwise, the switching efficiency could be 80% or better, and the power dissipated by the ensemble of gates during switching was approximately 0.1nWcm(-2), which is orders of magnitude less than the power dissipated during switching of an equivalent array of transistors. We propose an architecture for hybrid DNA-electronic systems in which information can be stored and processed, either in series or in parallel, by a combination of molecular machines and conventional electronics. In this architecture, information can flow freely and in both directions between the solution-phase and the underlying electronics via surface-immobilized DNA machines that provide the interface between the molecular and electronic domains. Copyright © 2016 Elsevier Ireland Ltd. All rights reserved.

Update and Expansion of the Center of Automotive Technology Excellence Under the Graduate Automotive Technology Education (GATE) Program at the University of Tennessee, Knoxville

DOE Office of Scientific and Technical Information (OSTI.GOV)

Irick, David

2012-08-30

The Graduate Automotive Technology Education (GATE) Center at the University of Tennessee, Knoxville has completed its seventh year of operation under this agreement, its thirteenth year in total. During this period the Center has involved eleven GATE Fellows and three GATE Research Assistants in preparing them to contribute to advanced automotive technologies in the center’s focus area: Advanced Hybrid Propulsion and Control Systems. In addition to the impact that the Center has had on the students and faculty involved, the presence of the center has led to the acquisition of resources that probably would not have been obtained if themore » GATE Center had not existed. Significant industry interaction such as equipment donations, and support for GATE students has been realized. The value of the total resources brought to the university (including related research contracts) exceeds $2,000,000.« less

Dual-gate photo thin-film transistor: a “smart” pixel for high- resolution and low-dose X-ray imaging

NASA Astrophysics Data System (ADS)

Wang, Kai; Ou, Hai; Chen, Jun

2015-06-01

Since its emergence a decade ago, amorphous silicon flat panel X-ray detector has established itself as a ubiquitous platform for an array of digital radiography modalities. The fundamental building block of a flat panel detector is called a pixel. In all current pixel architectures, sensing, storage, and readout are unanimously kept separate, inevitably compromising resolution by increasing pixel size. To address this issue, we hereby propose a “smart” pixel architecture where the aforementioned three components are combined in a single dual-gate photo thin-film transistor (TFT). In other words, the dual-gate photo TFT itself functions as a sensor, a storage capacitor, and a switch concurrently. Additionally, by harnessing the amplification effect of such a thin-film transistor, we for the first time created a single-transistor active pixel sensor. The proof-of-concept device had a W/L ratio of 250μm/20μm and was fabricated using a simple five-mask photolithography process, where a 130nm transparent ITO was used as the top photo gate, and a 200nm amorphous silicon as the absorbing channel layer. The preliminary results demonstrated that the photocurrent had been increased by four orders of magnitude due to light-induced threshold voltage shift in the sub-threshold region. The device sensitivity could be simply tuned by photo gate bias to specifically target low-level light detection. The dependence of threshold voltage on light illumination indicated that a dynamic range of at least 80dB could be achieved. The "smart" pixel technology holds tremendous promise for developing high-resolution and low-dose X-ray imaging and may potentially lower the cancer risk imposed by radiation, especially among paediatric patients.

Collision management utilizing CCD and remote sensing technology

NASA Technical Reports Server (NTRS)

Mcdaniel, Harvey E., Jr.

1995-01-01

With the threat of damage to aerospace systems (space station, shuttle, hypersonic a/c, solar power satellites, loss of life, etc.) from collision with debris (manmade/artificial), there exists an opportunity for the design of a novel system (collision avoidance) to be incorporated into the overall design. While incorporating techniques from ccd and remote sensing technologies, an integrated system utilized in the infrared/visible spectrum for detection, tracking, localization, and maneuvering from doppler shift measurements is achievable. Other analysis such as impact assessment, station keeping, chemical, and optical tracking/fire control solutions are possible through this system. Utilizing modified field programmable gated arrays (software reconfiguring the hardware) the mission and mission effectiveness can be varied. This paper outlines the theoretical operation of a prototype system as it applies to collision avoidance (to be followed up by research).

GATE: software for the analysis and visualization of high-dimensional time series expression data.

PubMed

MacArthur, Ben D; Lachmann, Alexander; Lemischka, Ihor R; Ma'ayan, Avi

2010-01-01

We present Grid Analysis of Time series Expression (GATE), an integrated computational software platform for the analysis and visualization of high-dimensional biomolecular time series. GATE uses a correlation-based clustering algorithm to arrange molecular time series on a two-dimensional hexagonal array and dynamically colors individual hexagons according to the expression level of the molecular component to which they are assigned, to create animated movies of systems-level molecular regulatory dynamics. In order to infer potential regulatory control mechanisms from patterns of correlation, GATE also allows interactive interroga-tion of movies against a wide variety of prior knowledge datasets. GATE movies can be paused and are interactive, allowing users to reconstruct networks and perform functional enrichment analyses. Movies created with GATE can be saved in Flash format and can be inserted directly into PDF manuscript files as interactive figures. GATE is available for download and is free for academic use from http://amp.pharm.mssm.edu/maayan-lab/gate.htm

Investigation of field induced trapping on floating gates

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1975-01-01

The development of a technology for building electrically alterable read only memories (EAROMs) or reprogrammable read only memories (RPROMs) using a single level metal gate p channel MOS process with all conventional processing steps is outlined. Nonvolatile storage of data is achieved by the use of charged floating gate electrodes. The floating gates are charged by avalanche injection of hot electrodes through gate oxide, and discharged by avalanche injection of hot holes through gate oxide. Three extra diffusion and patterning steps are all that is required to convert a standard p channel MOS process into a nonvolatile memory process. For identification, this nonvolatile memory technology was given the descriptive acronym DIFMOS which stands for Dual Injector, Floating gate MOS.

Optically Programmable Field Programmable Gate Arrays (FPGA) Systems

DTIC Science & Technology

2004-01-01

VCSEL requires placing the array far enough as to overlap the entire footprint of the signal beam in order to record the hologram. Therefore, these...hologram that self-focuses, due to phase -conjugation, on the array of detectors in the chip. VC A 10 m m 10 mm 18mm 16mm SEL RRAY OPTICAL MEMORY LOGIC...the VCSEL array , the chip and the optical material, and the requirements they have to meet for their use in the OPGA system. Section

Auto and hetero-associative memory using a 2-D optical logic gate

NASA Technical Reports Server (NTRS)

Chao, Tien-Hsin (Inventor)

1992-01-01

An optical system for auto-associative and hetero-associative recall utilizing Hamming distance as the similarity measure between a binary input image vector V(sup k) and a binary image vector V(sup m) in a first memory array using an optical Exclusive-OR gate for multiplication of each of a plurality of different binary image vectors in memory by the input image vector. After integrating the light of each product V(sup k) x V(sup m), a shortest Hamming distance detection electronics module determines which product has the lowest light intensity and emits a signal that activates a light emitting diode to illuminate a corresponding image vector in a second memory array for display. That corresponding image vector is identical to the memory image vector V(sup m) in the first memory array for auto-associative recall or related to it, such as by name, for hetero-associative recall.

Self-Adaptive System based on Field Programmable Gate Array for Extreme Temperature Electronics

NASA Technical Reports Server (NTRS)

Keymeulen, Didier; Zebulum, Ricardo; Rajeshuni, Ramesham; Stoica, Adrian; Katkoori, Srinivas; Graves, Sharon; Novak, Frank; Antill, Charles

2006-01-01

In this work, we report the implementation of a self-adaptive system using a field programmable gate array (FPGA) and data converters. The self-adaptive system can autonomously recover the lost functionality of a reconfigurable analog array (RAA) integrated circuit (IC) [3]. Both the RAA IC and the self-adaptive system are operating in extreme temperatures (from 120 C down to -180 C). The RAA IC consists of reconfigurable analog blocks interconnected by several switches and programmable by bias voltages. It implements filters/amplifiers with bandwidth up to 20 MHz. The self-adaptive system controls the RAA IC and is realized on Commercial-Off-The-Shelf (COTS) parts. It implements a basic compensation algorithm that corrects a RAA IC in less than a few milliseconds. Experimental results for the cold temperature environment (down to -180 C) demonstrate the feasibility of this approach.

A Flexible Annular-Array Imaging Platform for Micro-Ultrasound

PubMed Central

Qiu, Weibao; Yu, Yanyan; Chabok, Hamid Reza; Liu, Cheng; Tsang, Fu Keung; Zhou, Qifa; Shung, K. Kirk; Zheng, Hairong; Sun, Lei

2013-01-01

Micro-ultrasound is an invaluable imaging tool for many clinical and preclinical applications requiring high resolution (approximately several tens of micrometers). Imaging systems for micro-ultrasound, including single-element imaging systems and linear-array imaging systems, have been developed extensively in recent years. Single-element systems are cheaper, but linear-array systems give much better image quality at a higher expense. Annular-array-based systems provide a third alternative, striking a balance between image quality and expense. This paper presents the development of a novel programmable and real-time annular-array imaging platform for micro-ultrasound. It supports multi-channel dynamic beamforming techniques for large-depth-of-field imaging. The major image processing algorithms were achieved by a novel field-programmable gate array technology for high speed and flexibility. Real-time imaging was achieved by fast processing algorithms and high-speed data transfer interface. The platform utilizes a printed circuit board scheme incorporating state-of-the-art electronics for compactness and cost effectiveness. Extensive tests including hardware, algorithms, wire phantom, and tissue mimicking phantom measurements were conducted to demonstrate good performance of the platform. The calculated contrast-to-noise ratio (CNR) of the tissue phantom measurements were higher than 1.2 in the range of 3.8 to 8.7 mm imaging depth. The platform supported more than 25 images per second for real-time image acquisition. The depth-of-field had about 2.5-fold improvement compared to single-element transducer imaging. PMID:23287923

Within compound, from Gate House, looking northwest, Power Plant (Building ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

Within compound, from Gate House, looking northwest, Power Plant (Building 5761) to left, Electrical Substation (Building 5770) and Supply Warehouse (Building 5768) center, Satellite Communications Terminal (Building 5771) to far left - Beale Air Force Base, Perimeter Acquisition Vehicle Entry Phased-Array Warning System, End of Spencer Paul Road, north of Warren Shingle Road (14th Street), Marysville, Yuba County, CA

Graduate Automotive Technology Education (GATE) Center

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jeffrey Hodgson; David Irick

2005-09-30

The Graduate Automotive Technology Education (GATE) Center at the University of Tennessee, Knoxville has completed its sixth year of operation. During this period the Center has involved thirteen GATE Fellows and ten GATE Research Assistants in preparing them to contribute to advanced automotive technologies in the center's focus area: hybrid drive trains and control systems. Eighteen GATE students have graduated, and three have completed their course work requirements. Nine faculty members from three departments in the College of Engineering have been involved in the GATE Center. In addition to the impact that the Center has had on the students andmore » faculty involved, the presence of the center has led to the acquisition of resources that probably would not have been obtained if the GATE Center had not existed. Significant industry interaction such as internships, equipment donations, and support for GATE students has been realized. The value of the total resources brought to the university (including related research contracts) exceeds $4,000,000. Problem areas are discussed in the hope that future activities may benefit from the operation of the current program.« less

Low-Noise Free-Running High-Rate Photon-Counting for Space Communication and Ranging

NASA Technical Reports Server (NTRS)

Lu, Wei; Krainak, Michael A.; Yang, Guangning; Sun, Xiaoli; Merritt, Scott

2016-01-01

We present performance data for low-noise free-running high-rate photon counting method for space optical communication and ranging. NASA GSFC is testing the performance of two types of novel photon-counting detectors 1) a 2x8 mercury cadmium telluride (HgCdTe) avalanche array made by DRS Inc., and a 2) a commercial 2880-element silicon avalanche photodiode (APD) array. We successfully measured real-time communication performance using both the 2 detected-photon threshold and logic AND-gate coincidence methods. Use of these methods allows mitigation of dark count, after-pulsing and background noise effects without using other method of Time Gating The HgCdTe APD array routinely demonstrated very high photon detection efficiencies ((is) greater than 50%) at near infrared wavelength. The commercial silicon APD array exhibited a fast output with rise times of 300 ps and pulse widths of 600 ps. On-chip individually filtered signals from the entire array were multiplexed onto a single fast output. NASA GSFC has tested both detectors for their potential application for space communications and ranging. We developed and compare their performances using both the 2 detected photon threshold and coincidence methods.

Low-Noise Free-Running High-Rate Photon-Counting for Space Communication and Ranging

NASA Technical Reports Server (NTRS)

Lu, Wei; Krainak, Michael A.; Yang, Guan; Sun, Xiaoli; Merritt, Scott

2016-01-01

We present performance data for low-noise free-running high-rate photon counting method for space optical communication and ranging. NASA GSFC is testing the performance of two types of novel photon-counting detectors 1) a 2x8 mercury cadmium telluride (HgCdTe) avalanche array made by DRS Inc., and a 2) a commercial 2880-element silicon avalanche photodiode (APD) array. We successfully measured real-time communication performance using both the 2 detected-photon threshold and logic AND-gate coincidence methods. Use of these methods allows mitigation of dark count, after-pulsing and background noise effects without using other method of Time Gating The HgCdTe APD array routinely demonstrated very high photon detection efficiencies (50) at near infrared wavelength. The commercial silicon APD array exhibited a fast output with rise times of 300 ps and pulse widths of 600 ps. On-chip individually filtered signals from the entire array were multiplexed onto a single fast output. NASA GSFC has tested both detectors for their potential application for space communications and ranging. We developed and compare their performances using both the 2 detected photon threshold and coincidence methods.

Formation of holographic memory for optically reconfigurable gate array by angle-multiplexing recording of multi-circuit information in liquid crystal composites

NASA Astrophysics Data System (ADS)

Ogiwara, Akifumi; Maekawa, Hikaru; Watanabe, Minoru; Moriwaki, Retsu

2014-02-01

A holographic polymer-dispersed liquid crystal (HPDLC) memory to record multi-context information for an optically reconfigurable gate array is formed by the angle-multiplexing recording using a successive laser exposure in liquid crystal (LC) composites. The laser illumination system is constructed using the half mirror and photomask written by the different configuration contexts placed on the motorized stages under the control of a personal computer. The fabricated holographic memory implements a precise reconstruction of configuration contexts corresponding to the various logical circuits such as OR circuit and NOR circuit by the laser illumination at different incident angle in the HPDLC memory.

A new 4D chaotic system with hidden attractor and its engineering applications: Analog circuit design and field programmable gate array implementation

NASA Astrophysics Data System (ADS)

Abdolmohammadi, Hamid Reza; Khalaf, Abdul Jalil M.; Panahi, Shirin; Rajagopal, Karthikeyan; Pham, Viet-Thanh; Jafari, Sajad

2018-06-01

Nowadays, designing chaotic systems with hidden attractor is one of the most interesting topics in nonlinear dynamics and chaos. In this paper, a new 4D chaotic system is proposed. This new chaotic system has no equilibria, and so it belongs to the category of systems with hidden attractors. Dynamical features of this system are investigated with the help of its state-space portraits, bifurcation diagram, Lyapunov exponents diagram, and basin of attraction. Also a hardware realisation of this system is proposed by using field programmable gate arrays (FPGA). In addition, an electronic circuit design for the chaotic system is introduced.

Two-dimensional radiant energy array computers and computing devices

NASA Technical Reports Server (NTRS)

Schaefer, D. H.; Strong, J. P., III (Inventor)

1976-01-01

Two dimensional digital computers and computer devices operate in parallel on rectangular arrays of digital radiant energy optical signal elements which are arranged in ordered rows and columns. Logic gate devices receive two input arrays and provide an output array having digital states dependent only on the digital states of the signal elements of the two input arrays at corresponding row and column positions. The logic devices include an array of photoconductors responsive to at least one of the input arrays for either selectively accelerating electrons to a phosphor output surface, applying potentials to an electroluminescent output layer, exciting an array of discrete radiant energy sources, or exciting a liquid crystal to influence crystal transparency or reflectivity.

Gate-Sensing the Potential Landscape of a GaAs Two-Dimensional Electron Gas

NASA Astrophysics Data System (ADS)

Croot, Xanthe; Mahoney, Alice; Pauka, Sebastian; Colless, James; Reilly, David; Watson, John; Fallahi, Saeed; Gardner, Geoff; Manfra, Michael; Lu, Hong; Gossard, Arthur

In situ dispersive gate sensors hold potential as a means of enabling the scalable readout of quantum dot arrays. Sensitive to quantum capacitance, dispersive sensors have been used to detect inter- and intra-dot transitions in GaAs double quantum dots, and can distinguish the spin states of singlet triplet qubits. In addition, the gate-sensing technique is likely of value in probing the physics of Majorana zero modes in nanowire devices. Beyond the readout signatures associated with charge and spin configurations of qubits, gate-sensing is sensitive to trapped charge in the potential landscape. Here, we report gate-sensing signals arising from tunnelling of electrons between puddles of trapped charge in a GaAs 2DEG. We examine these signals in a family of different devices with varying mobilities, and as a function of temperature and bias. Implications for qubit readout using the gate-sensing technique are discussed.

Design considerations and emerging challenges for nanotube-, nanowire-, and negative capacitor-field effect transistors

NASA Astrophysics Data System (ADS)

Wahab, Md. Abdul

As the era of classical planar metal-oxide-semiconductor field-effect transistors (MOSFETs) comes to an end, the semiconductor industry is beginning to adopt 3D device architectures, such as FinFETs, starting at the 22 nm technology node. Since physical limits such as short channel effect (SCE) and self-heating may dominate, it may be difficult to scale Si FinFET below 10 nm. In this regard, transistors with different materials, geometries, or operating principles may help. For example, gate has excellent electrostatic control over 2D thin film channel with planar geometry, and 1D nanowire (NW) channel with gate-all-around (GAA) geometry to reduce SCE. High carrier mobility of single wall carbon nanotube (SWNT) or III-V channels may reduce VDD to reduce power consumption. Therefore, as channel of transistor, 2D thin film of array SWNTs and 1D III-V multi NWs are promising for sub 10 nm technology nodes. In this thesis, we analyze the potential of these transistors from process, performance, and reliability perspectives. For SWNT FETs, we discuss a set of challenges (such as how to (i) characterize diameter distribution, (ii) remove metallic (m)-SWNTs, and (iii) avoid electrostatic cross-talk among the neighboring SWNTs), and demonstrate solution strategies both theoretically and experimentally. Regarding self-heating in these new class of devices (SWNT FET and GAA NW FET including state-of-the-art FinFET), higher thermal resistance from poor thermal conducting oxides results significant temperature rise, and reduces the IC life-time. For GAA NW FETs, we discuss accurate self-heating evaluation with good spatial, temporal, and thermal resolutions. The introduction of negative capacitor (NC), as gate dielectric stack of transistor, allows sub 60 mV/dec operation to reduce power consumption significantly. Taken together, our work provides a comprehensive perspective regarding the challenges and opportunities of sub 10 nm technology nodes.

Development of a Low-Cost and High-speed Single Event Effects Testers based on Reconfigurable Field Programmable Gate Arrays (FPGA)

NASA Technical Reports Server (NTRS)

Howard, J. W.; Kim, H.; Berg, M.; LaBel, K. A.; Stansberry, S.; Friendlich, M.; Irwin, T.

2006-01-01

A viewgraph presentation on the development of a low cost, high speed tester reconfigurable Field Programmable Gata Array (FPGA) is shown. The topics include: 1) Introduction; 2) Objectives; 3) Tester Descriptions; 4) Tester Validations and Demonstrations; 5) Future Work; and 6) Summary.

Space charge effects on the current-voltage characteristics of gated field emitter arrays

NASA Astrophysics Data System (ADS)

Jensen, K. L.; Kodis, M. A.; Murphy, R. A.; Zaidman, E. G.

1997-07-01

Microfabricated field emitter arrays (FEAs) can provide the very high electron current densities required for rf amplifier applications, typically on the order of 100 A/cm2. Determining the dependence of emission current on gate voltage is important for the prediction of emitter performance for device applications. Field emitters use high applied fields to extract current, and therefore, unlike thermionic emitters, the current densities can exceed 103A/cm2 when averaged over an array. At such high current densities, space charge effects (i.e., the influence of charge between cathode and collector on emission) affect the emission process or initiate conditions which can lead to failure mechanisms for field emitters. A simple model of a field emitter will be used to calculate the one-dimensional space charge effects on the emission characteristics by examining two components: charge between the gate and anode, which leads to Child's law, and charge within the FEA unit cell, which gives rise to a field suppression effect which can exist for a single field emitter. The predictions of the analytical model are compared with recent experimental measurements designed to assess space charge effects and predict the onset of gate current. It is shown that negative convexity on a Fowler-Nordheim plot of Ianode(Vgate) data can be explained in terms of field depression at the emitter tip in addition to reflection of electrons by a virtual cathode created when the anode field is insufficient to extract all of the current; in particular, the effects present within the unit cell constitute a newly described effect.

Real-time implementation of a multispectral mine target detection algorithm

NASA Astrophysics Data System (ADS)

Samson, Joseph W.; Witter, Lester J.; Kenton, Arthur C.; Holloway, John H., Jr.

2003-09-01

Spatial-spectral anomaly detection (the "RX Algorithm") has been exploited on the USMC's Coastal Battlefield Reconnaissance and Analysis (COBRA) Advanced Technology Demonstration (ATD) and several associated technology base studies, and has been found to be a useful method for the automated detection of surface-emplaced antitank land mines in airborne multispectral imagery. RX is a complex image processing algorithm that involves the direct spatial convolution of a target/background mask template over each multispectral image, coupled with a spatially variant background spectral covariance matrix estimation and inversion. The RX throughput on the ATD was about 38X real time using a single Sun UltraSparc system. A goal to demonstrate RX in real-time was begun in FY01. We now report the development and demonstration of a Field Programmable Gate Array (FPGA) solution that achieves a real-time implementation of the RX algorithm at video rates using COBRA ATD data. The approach uses an Annapolis Microsystems Firebird PMC card containing a Xilinx XCV2000E FPGA with over 2,500,000 logic gates and 18MBytes of memory. A prototype system was configured using a Tek Microsystems VME board with dual-PowerPC G4 processors and two PMC slots. The RX algorithm was translated from its C programming implementation into the VHDL language and synthesized into gates that were loaded into the FPGA. The VHDL/synthesizer approach allows key RX parameters to be quickly changed and a new implementation automatically generated. Reprogramming the FPGA is done rapidly and in-circuit. Implementation of the RX algorithm in a single FPGA is a major first step toward achieving real-time land mine detection.

Radiation tolerant 1 micron CMOS technology

NASA Astrophysics Data System (ADS)

Crevel, P.; Rodde, K.

1991-03-01

Starting from a standard one micron Complementary Metal Oxide Semiconductor (CMOS) for high density, low power memory applications, the degree of radiation tolerance of the baseline process is evaluated. Implemented process modifications to improve latchup sensitivity under heavy ion irradiation as well as total dose effects without changing layout rules are described. By changing doping profiles in Metal Nitride Oxide Semiconductors (MNOS) and P-channel MOS (PMOS) device regions, it is possible to guarantee data sheet specification of a 64 K low power static RAM for total gamma dose up to 35 krad (Si) (and even higher values for the gate array family) without latch up for Linear Energy Transfer LET up to 115 MeV/(mg/cm squared).

Design of an Oximeter Based on LED-LED Configuration and FPGA Technology

PubMed Central

Stojanovic, Radovan; Karadaglic, Dejan

2013-01-01

A fully digital photoplethysmographic (PPG) sensor and actuator has been developed. The sensing circuit uses one Light Emitting Diode (LED) for emitting light into human tissue and one LED for detecting the reflectance light from human tissue. A Field Programmable Gate Array (FPGA) is used to control the LEDs and determine the PPG and Blood Oxygen Saturation (SpO2). The configurations with two LEDs and four LEDs are developed for measuring PPG signal and Blood Oxygen Saturation (SpO2). N-LEDs configuration is proposed for multichannel SpO2 measurements. The approach resulted in better spectral sensitivity, increased and adjustable resolution, reduced noise, small size, low cost and low power consumption. PMID:23291575

Mutation Testing for Effective Verification of Digital Components of Physical Systems

NASA Astrophysics Data System (ADS)

Kushik, N. G.; Evtushenko, N. V.; Torgaev, S. N.

2015-12-01

Digital components of modern physical systems are often designed applying circuitry solutions based on the field programmable gate array technology (FPGA). Such (embedded) digital components should be carefully tested. In this paper, an approach for the verification of digital physical system components based on mutation testing is proposed. The reference description of the behavior of a digital component in the hardware description language (HDL) is mutated by introducing into it the most probable errors and, unlike mutants in high-level programming languages, the corresponding test case is effectively derived based on a comparison of special scalable representations of the specification and the constructed mutant using various logic synthesis and verification systems.

Using benchmarks for radiation testing of microprocessors and FPGAs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather; Robinson, William H.; Rech, Paolo

Performance benchmarks have been used over the years to compare different systems. These benchmarks can be useful for researchers trying to determine how changes to the technology, architecture, or compiler affect the system's performance. No such standard exists for systems deployed into high radiation environments, making it difficult to assess whether changes in the fabrication process, circuitry, architecture, or software affect reliability or radiation sensitivity. In this paper, we propose a benchmark suite for high-reliability systems that is designed for field-programmable gate arrays and microprocessors. As a result, we describe the development process and report neutron test data for themore » hardware and software benchmarks.« less

A Low Cost Matching Motion Estimation Sensor Based on the NIOS II Microprocessor

PubMed Central

González, Diego; Botella, Guillermo; Meyer-Baese, Uwe; García, Carlos; Sanz, Concepción; Prieto-Matías, Manuel; Tirado, Francisco

2012-01-01

This work presents the implementation of a matching-based motion estimation sensor on a Field Programmable Gate Array (FPGA) and NIOS II microprocessor applying a C to Hardware (C2H) acceleration paradigm. The design, which involves several matching algorithms, is mapped using Very Large Scale Integration (VLSI) technology. These algorithms, as well as the hardware implementation, are presented here together with an extensive analysis of the resources needed and the throughput obtained. The developed low-cost system is practical for real-time throughput and reduced power consumption and is useful in robotic applications, such as tracking, navigation using an unmanned vehicle, or as part of a more complex system. PMID:23201989

Using benchmarks for radiation testing of microprocessors and FPGAs

DOE PAGES

Quinn, Heather; Robinson, William H.; Rech, Paolo; ...

2015-12-17

Performance benchmarks have been used over the years to compare different systems. These benchmarks can be useful for researchers trying to determine how changes to the technology, architecture, or compiler affect the system's performance. No such standard exists for systems deployed into high radiation environments, making it difficult to assess whether changes in the fabrication process, circuitry, architecture, or software affect reliability or radiation sensitivity. In this paper, we propose a benchmark suite for high-reliability systems that is designed for field-programmable gate arrays and microprocessors. As a result, we describe the development process and report neutron test data for themore » hardware and software benchmarks.« less

Digital quantum simulators in a scalable architecture of hybrid spin-photon qubits

PubMed Central

Chiesa, Alessandro; Santini, Paolo; Gerace, Dario; Raftery, James; Houck, Andrew A.; Carretta, Stefano

2015-01-01

Resolving quantum many-body problems represents one of the greatest challenges in physics and physical chemistry, due to the prohibitively large computational resources that would be required by using classical computers. A solution has been foreseen by directly simulating the time evolution through sequences of quantum gates applied to arrays of qubits, i.e. by implementing a digital quantum simulator. Superconducting circuits and resonators are emerging as an extremely promising platform for quantum computation architectures, but a digital quantum simulator proposal that is straightforwardly scalable, universal, and realizable with state-of-the-art technology is presently lacking. Here we propose a viable scheme to implement a universal quantum simulator with hybrid spin-photon qubits in an array of superconducting resonators, which is intrinsically scalable and allows for local control. As representative examples we consider the transverse-field Ising model, a spin-1 Hamiltonian, and the two-dimensional Hubbard model and we numerically simulate the scheme by including the main sources of decoherence. PMID:26563516

Fabrication of Amorphous Indium Gallium Zinc Oxide Thin Film Transistor by using Focused Ion Beam

NASA Astrophysics Data System (ADS)

Zhu, Wencong

Compared with other transparent semiconductors, amorphous indium gallium zinc oxide (a-IGZO) has both good uniformity and high electron mobility, which make it as a good candidate for displays or large-scale transparent circuit. The goal of this research is to fabricate alpha-IGZO thin film transistor (TFT) with channel milled by focused ion beam (FIB). TFTs with different channel geometries can be achieved by applying different milling strategies, which facilitate modifying complex circuit. Technology Computer-Aided Design (TCAD) was also introduced to understand the effect of trapped charges on the device performance. The investigation of the trapped charge at IGZO/SiO2 interface was performed on the IGZO TFT on p-Silicon substrate with thermally grown SiO2 as dielectric. The subgap density-of-state model was used for the simulation, which includes conduction band-tail trap states and donor-like state in the subgap. The result shows that the de-trapping and donor-state ionization determine the interface trapped charge density at various gate biases. Simulation of IGZO TFT with FIB defined channel on the same substrate was also applied. The drain and source were connected intentionally during metal deposition and separated by FIB milling. Based on the simulation, the Ga ions in SiO2 introduced by the ion beam was drifted by gate bias and affects the saturation drain current. Both side channel and direct channel transparent IGZO TFTs were fabricated on the glass substrate with coated ITO. Higher ion energy (30 keV) was used to etch through the substrate between drain and source and form side channels at the corner of milled trench. Lower ion energy (16 keV) was applied to stop the milling inside IGZO thin film and direct channel between drain and source was created. Annealing after FIB milling removed the residual Ga ions and the devices show switch feature. Direct channel shows higher saturation drain current (~10-6 A) compared with side channel (~10-7 A) because of its shorter channel length and wider width, however, it also exhibit higher gate leakage current (>10-7 A) than side channel (<10-7 A) due to larger Ga ion implantation and diffusion region in SiO2 after annealing. Hysteresis window increase and positive VON shift were also observed due to the interface trap density increase and carrier density suppression both by Ga ions. Laser interference lithography was applied to define the IGZO active region, which gives more flexibility on TFT channel dimension and circuit modification. He-Cd laser with 325 nm wavelength was used to define 2D array of IGZO islands with period of 2.5 im. Logic gate array was designed and fabricated by combining this 2D array of IGZO islands and FIB direct channel milling. After annealing, device shows on-off feature, but high temperature (400 °C) release more free carrier and results in negative shift of VON. The row selection voltage was also introduced in the design of logic gate array to act as switch of input signals to each row separately. However, due to the long input signal sweeping time, the leakage current cannot be overlooked. The idea can be verified by AC or short pulse input signal.

Fully digital routing logic for single-photon avalanche diode arrays in highly efficient time-resolved imaging

NASA Astrophysics Data System (ADS)

Cominelli, Alessandro; Acconcia, Giulia; Ghioni, Massimo; Rech, Ivan

2018-03-01

Time-correlated single-photon counting (TCSPC) is a powerful optical technique, which permits recording fast luminous signals with picosecond precision. Unfortunately, given its repetitive nature, TCSPC is recognized as a relatively slow technique, especially when a large time-resolved image has to be recorded. In recent years, there has been a fast trend toward the development of TCPSC imagers. Unfortunately, present systems still suffer from a trade-off between number of channels and performance. Even worse, the overall measurement speed is still limited well below the saturation of the transfer bandwidth toward the external processor. We present a routing algorithm that enables a smart connection between a 32×32 detector array and five shared high-performance converters able to provide an overall conversion rate up to 10 Gbit/s. The proposed solution exploits a fully digital logic circuit distributed in a tree structure to limit the number and length of interconnections, which is a major issue in densely integrated circuits. The behavior of the logic has been validated by means of a field-programmable gate array, while a fully integrated prototype has been designed in 180-nm technology and analyzed by means of postlayout simulations.

20-GFLOPS QR processor on a Xilinx Virtex-E FPGA

NASA Astrophysics Data System (ADS)

Walke, Richard L.; Smith, Robert W. M.; Lightbody, Gaye

2000-11-01

Adaptive beamforming can play an important role in sensor array systems in countering directional interference. In high-sample rate systems, such as radar and comms, the calculation of adaptive weights is a very computational task that requires highly parallel solutions. For systems where low power consumption and volume are important the only viable implementation is as an Application Specific Integrated Circuit (ASIC). However, the rapid advancement of Field Programmable Gate Array (FPGA) technology is enabling highly credible re-programmable solutions. In this paper we present the implementation of a scalable linear array processor for weight calculation using QR decomposition. We employ floating-point arithmetic with mantissa size optimized to the target application to minimize component size, and implement them as relationally placed macros (RPMs) on Xilinx Virtex FPGAs to achieve predictable dense layout and high-speed operation. We present results that show that 20GFLOPS of sustained computation on a single XCV3200E-8 Virtex-E FPGA is possible. We also describe the parameterized implementation of the floating-point operators and QR-processor, and the design methodology that enables us to rapidly generate complex FPGA implementations using the industry standard hardware description language VHDL.

Molecular computational elements encode large populations of small objects

NASA Astrophysics Data System (ADS)

Prasanna de Silva, A.; James, Mark R.; McKinney, Bernadine O. F.; Pears, David A.; Weir, Sheenagh M.

2006-10-01

Since the introduction of molecular computation, experimental molecular computational elements have grown to encompass small-scale integration, arithmetic and games, among others. However, the need for a practical application has been pressing. Here we present molecular computational identification (MCID), a demonstration that molecular logic and computation can be applied to a widely relevant issue. Examples of populations that need encoding in the microscopic world are cells in diagnostics or beads in combinatorial chemistry (tags). Taking advantage of the small size (about 1nm) and large `on/off' output ratios of molecular logic gates and using the great variety of logic types, input chemical combinations, switching thresholds and even gate arrays in addition to colours, we produce unique identifiers for members of populations of small polymer beads (about 100μm) used for synthesis of combinatorial libraries. Many millions of distinguishable tags become available. This method should be extensible to far smaller objects, with the only requirement being a `wash and watch' protocol. Our focus on converting molecular science into technology concerning analog sensors, turns to digital logic devices in the present work.

Molecular computational elements encode large populations of small objects.

PubMed

de Silva, A Prasanna; James, Mark R; McKinney, Bernadine O F; Pears, David A; Weir, Sheenagh M

2006-10-01

Since the introduction of molecular computation, experimental molecular computational elements have grown to encompass small-scale integration, arithmetic and games, among others. However, the need for a practical application has been pressing. Here we present molecular computational identification (MCID), a demonstration that molecular logic and computation can be applied to a widely relevant issue. Examples of populations that need encoding in the microscopic world are cells in diagnostics or beads in combinatorial chemistry (tags). Taking advantage of the small size (about 1 nm) and large 'on/off' output ratios of molecular logic gates and using the great variety of logic types, input chemical combinations, switching thresholds and even gate arrays in addition to colours, we produce unique identifiers for members of populations of small polymer beads (about 100 microm) used for synthesis of combinatorial libraries. Many millions of distinguishable tags become available. This method should be extensible to far smaller objects, with the only requirement being a 'wash and watch' protocol. Our focus on converting molecular science into technology concerning analog sensors, turns to digital logic devices in the present work.

Design of video processing and testing system based on DSP and FPGA

NASA Astrophysics Data System (ADS)

Xu, Hong; Lv, Jun; Chen, Xi'ai; Gong, Xuexia; Yang, Chen'na

2007-12-01

Based on high speed Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA), a video capture, processing and display system is presented, which is of miniaturization and low power. In this system, a triple buffering scheme was used for the capture and display, so that the application can always get a new buffer without waiting; The Digital Signal Processor has an image process ability and it can be used to test the boundary of workpiece's image. A video graduation technology is used to aim at the position which is about to be tested, also, it can enhance the system's flexibility. The character superposition technology realized by DSP is used to display the test result on the screen in character format. This system can process image information in real time, ensure test precision, and help to enhance product quality and quality management.

High-Speed Scanning Interferometer Using CMOS Image Sensor and FPGA Based on Multifrequency Phase-Tracking Detection

NASA Technical Reports Server (NTRS)

Ohara, Tetsuo

2012-01-01

A sub-aperture stitching optical interferometer can provide a cost-effective solution for an in situ metrology tool for large optics; however, the currently available technologies are not suitable for high-speed and real-time continuous scan. NanoWave s SPPE (Scanning Probe Position Encoder) has been proven to exhibit excellent stability and sub-nanometer precision with a large dynamic range. This same technology can transform many optical interferometers into real-time subnanometer precision tools with only minor modification. The proposed field-programmable gate array (FPGA) signal processing concept, coupled with a new-generation, high-speed, mega-pixel CMOS (complementary metal-oxide semiconductor) image sensor, enables high speed (>1 m/s) and real-time continuous surface profiling that is insensitive to variation of pixel sensitivity and/or optical transmission/reflection. This is especially useful for large optics surface profiling.

Design Tools for Reconfigurable Hardware in Orbit (RHinO)

NASA Technical Reports Server (NTRS)

French, Mathew; Graham, Paul; Wirthlin, Michael; Larchev, Gregory; Bellows, Peter; Schott, Brian

2004-01-01

The Reconfigurable Hardware in Orbit (RHinO) project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. These tools leverage an established FPGA design environment and focus primarily on space effects mitigation and power optimization. The project is creating software to automatically test and evaluate the single-event-upsets (SEUs) sensitivities of an FPGA design and insert mitigation techniques. Extensions into the tool suite will also allow evolvable algorithm techniques to reconfigure around single-event-latchup (SEL) events. In the power domain, tools are being created for dynamic power visualiization and optimization. Thus, this technology seeks to enable the use of Reconfigurable Hardware in Orbit, via an integrated design tool-suite aiming to reduce risk, cost, and design time of multimission reconfigurable space processors using SRAM-based FPGAs.

Intellectual Disability and Assistive Technology: Opening the GATE Wider.

PubMed

Boot, Fleur Heleen; Dinsmore, John; Khasnabis, Chapal; MacLachlan, Malcolm

2017-01-01

The World Health Organization has launched a program to promote Global Cooperation on Assistive Technology (GATE). The objective of the GATE program is to improve access to high quality, affordable assistive technology for people with varying disabilities, diseases, and age-related conditions. As a first step, GATE has developed the assistive products list, a list of priority assistive products based on addressing the greatest need at population level. A specific group of people who can benefit from user appropriate assistive technology are people with intellectual disabilities. However, the use of assistive products by people with intellectual disabilities is a neglected area of research and practice, and offers considerable opportunities for the advancement of population health and the realization of basic human rights. It is unknown how many people with intellectual disabilities globally have access to appropriate assistive products and which factors influence their access. We call for a much greater focus on people with intellectual disabilities within the GATE program. We present a framework for understanding the complex interaction between intellectual disability, health and wellbeing, and assistive technology.

High-performance reconfigurable coincidence counting unit based on a field programmable gate array.

PubMed

Park, Byung Kwon; Kim, Yong-Su; Kwon, Osung; Han, Sang-Wook; Moon, Sung

2015-05-20

We present a high-performance reconfigurable coincidence counting unit (CCU) using a low-end field programmable gate array (FPGA) and peripheral circuits. Because of the flexibility guaranteed by the FPGA program, we can easily change system parameters, such as internal input delays, coincidence configurations, and the coincidence time window. In spite of a low-cost implementation, the proposed CCU architecture outperforms previous ones in many aspects: it has 8 logic inputs and 4 coincidence outputs that can measure up to eight-fold coincidences. The minimum coincidence time window and the maximum input frequency are 0.47 ns and 163 MHz, respectively. The CCU will be useful in various experimental research areas, including the field of quantum optics and quantum information.

Nine-channel mid-power bipolar pulse generator based on a field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Haylock, Ben, E-mail: benjamin.haylock2@griffithuni.edu.au; Lenzini, Francesco; Kasture, Sachin

Many channel arbitrary pulse sequence generation is required for the electro-optic reconfiguration of optical waveguide networks in Lithium Niobate. Here we describe a scalable solution to the requirement for mid-power bipolar parallel outputs, based on pulse patterns generated by an externally clocked field programmable gate array. Positive and negative pulses can be generated at repetition rates up to 80 MHz with pulse width adjustable in increments of 1.6 ns across nine independent outputs. Each channel can provide 1.5 W of RF power and can be synchronised with the operation of other components in an optical network such as light sourcesmore » and detectors through an external clock with adjustable delay.« less

Fault-Tolerant Software-Defined Radio on Manycore

NASA Technical Reports Server (NTRS)

Ricketts, Scott

2015-01-01

Software-defined radio (SDR) platforms generally rely on field-programmable gate arrays (FPGAs) and digital signal processors (DSPs), but such architectures require significant software development. In addition, application demands for radiation mitigation and fault tolerance exacerbate programming challenges. MaXentric Technologies, LLC, has developed a manycore-based SDR technology that provides 100 times the throughput of conventional radiationhardened general purpose processors. Manycore systems (30-100 cores and beyond) have the potential to provide high processing performance at error rates that are equivalent to current space-deployed uniprocessor systems. MaXentric's innovation is a highly flexible radio, providing over-the-air reconfiguration; adaptability; and uninterrupted, real-time, multimode operation. The technology is also compliant with NASA's Space Telecommunications Radio System (STRS) architecture. In addition to its many uses within NASA communications, the SDR can also serve as a highly programmable research-stage prototyping device for new waveforms and other communications technologies. It can also support noncommunication codes on its multicore processor, collocated with the communications workload-reducing the size, weight, and power of the overall system by aggregating processing jobs to a single board computer.

Power efficient, clock gated multiplexer based full adder cell using 28 nm technology

NASA Astrophysics Data System (ADS)

Gupta, Ashutosh; Murgai, Shruti; Gulati, Anmol; Kumar, Pradeep

2016-03-01

Clock gating is a leading technique used for power saving. Full adders is one of the basic circuit that can be found in maximum VLSI circuits. In this paper clock gated multiplexer based full adder cell is implemented on 28 nm technology. We have designed a full adder cell using a multiplexer with a gated clock without degrading its performance of the cell. We have negative latch circuit for generating gated clock. This gated clock is used to control the multiplexer based full adder cell. The circuit has been synthesized on kintex FPGA through Xilinx ISE Design Suite 14.7 using 28 nm technology in Verilog HDL. The circuit has been simulated on Modelsim 10.3c. The design is verified using System Verilog on QuestaSim in UVM environment. The total power of the circuit has been reduced by 7.41% without degrading the performance of original circuit. The power has been calculated using XPower Analyzer tool of XILINX ISE DESIGN SUITE 14.3.

ManPortable and UGV LIVAR: advances in sensor suite integration bring improvements to target observation and identification for the electronic battlefield

NASA Astrophysics Data System (ADS)

Lynam, Jeff R.

2001-09-01

A more highly integrated, electro-optical sensor suite using Laser Illuminated Viewing and Ranging (LIVAR) techniques is being developed under the Army Advanced Concept Technology- II (ACT-II) program for enhanced manportable target surveillance and identification. The ManPortable LIVAR system currently in development employs a wide-array of sensor technologies that provides the foot-bound soldier and UGV significant advantages and capabilities in lightweight, fieldable, target location, ranging and imaging systems. The unit incorporates a wide field-of-view, 5DEG x 3DEG, uncooled LWIR passive sensor for primary target location. Laser range finding and active illumination is done with a triggered, flash-lamp pumped, eyesafe micro-laser operating in the 1.5 micron region, and is used in conjunction with a range-gated, electron-bombarded CCD digital camera to then image the target objective in a more- narrow, 0.3$DEG, field-of-view. Target range determination is acquired using the integrated LRF and a target position is calculated using data from other onboard devices providing GPS coordinates, tilt, bank and corrected magnetic azimuth. Range gate timing and coordinated receiver optics focus control allow for target imaging operations to be optimized. The onboard control electronics provide power efficient, system operations for extended field use periods from the internal, rechargeable battery packs. Image data storage, transmission, and processing performance capabilities are also being incorporated to provide the best all-around support, for the electronic battlefield, in this type of system. The paper will describe flash laser illumination technology, EBCCD camera technology with flash laser detection system, and image resolution improvement through frame averaging.

Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System

PubMed Central

Yang, Jong-Ryul; Lee, Woo-Jae; Han, Seong-Tae

2016-01-01

A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS) detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC) offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s. PMID:26950128

Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System.

PubMed

Yang, Jong-Ryul; Lee, Woo-Jae; Han, Seong-Tae

2016-03-02

A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS) detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC) offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s.

Field-programmable gate array-controlled sweep velocity-locked laser pulse generator

NASA Astrophysics Data System (ADS)

Chen, Zhen; Hefferman, Gerald; Wei, Tao

2017-05-01

A field-programmable gate array (FPGA)-controlled sweep velocity-locked laser pulse generator (SV-LLPG) design based on an all-digital phase-locked loop (ADPLL) is proposed. A distributed feedback laser with modulated injection current was used as a swept-frequency laser source. An open-loop predistortion modulation waveform was calibrated using a feedback iteration method to initially improve frequency sweep linearity. An ADPLL control system was then implemented using an FPGA to lock the output of a Mach-Zehnder interferometer that was directly proportional to laser sweep velocity to an on-board system clock. Using this system, linearly chirped laser pulses with a sweep bandwidth of 111.16 GHz were demonstrated. Further testing evaluating the sensing utility of the system was conducted. In this test, the SV-LLPG served as the swept laser source of an optical frequency-domain reflectometry system used to interrogate a subterahertz range fiber structure (sub-THz-FS) array. A static strain test was then conducted and linear sensor results were observed.

Multiple Quantum Phase Transitions in a two-dimensional superconductor

NASA Astrophysics Data System (ADS)

Bergeal, Nicolas; Biscaras, J.; Hurand, S.; Feuillet-Palma, C.; Lesueur, J.; Budhani, R. C.; Rastogi, A.; Caprara, S.; Grilli, M.

2013-03-01

We studied the magnetic field driven Quantum Phase Transition (QPT) in electrostatically gated superconducting LaTiO3/SrTiO3 interfaces. Through finite size scaling analysis, we showed that it belongs to the (2 +1)D XY model universality class. The system can be described as a disordered array of superconducting islands coupled by a two dimensional electron gas (2DEG). Depending on the 2DEG conductance tuned by the gate voltage, the QPT is single (corresponding to the long range phase coherence in the whole array) or double (one related to local phase coherence, the other one to the array). By retrieving the coherence length critical exponent ν, we showed that the QPT can be ``clean'' or ``dirty'' according to the Harris criteria, depending on whether the phase coherence length is smaller or larger than the island size. The overall behaviour is well described by a model of coupled superconducting puddles in the framework of the fermionic scenario of 2D superconducting QPT.

Mechanical design of SST-GATE, a dual-mirror telescope for the Cherenkov Telescope Array

NASA Astrophysics Data System (ADS)

Dournaux, Jean-Laurent; Huet, Jean-Michel; Amans, Jean-Philippe; Dumas, Delphine; Laporte, Philippe; Sol, Hélène; Blake, Simon

2014-07-01

The Cherenkov Telescope Array (CTA) project aims to create the next generation Very High Energy (VHE) gamma-ray telescope array. It will be devoted to the observation of gamma rays over a wide band of energy, from a few tens of GeV to more than 100 TeV. Two sites are foreseen to view the whole sky where about 100 telescopes, composed of three different classes, related to the specific energy region to be investigated, will be installed. Among these, the Small Size class of Telescopes, SSTs, are devoted to the highest energy region, to beyond 100 TeV. Due to the large number of SSTs, their unit cost is an important parameter. At the Observatoire de Paris, we have designed a prototype of a Small Size Telescope named SST-GATE, based on the dual-mirror Schwarzschild-Couder optical formula, which has never before been implemented in the design of a telescope. Over the last two years, we developed a mechanical design for SST-GATE from the optical and preliminary mechanical designs made by the University of Durham. The integration of this telescope is currently in progress. Since the early stages of mechanical design of SST-GATE, finite element method has been used employing shape and topology optimization techniques to help design several elements of the telescope. This allowed optimization of the mechanical stiffness/mass ratio, leading to a lightweight and less expensive mechanical structure. These techniques and the resulting mechanical design are detailed in this paper. We will also describe the finite element analyses carried out to calculate the mechanical deformations and the stresses in the structure under observing and survival conditions.

UC Davis Fuel Cell, Hydrogen, and Hybrid Vehicle (FCH2V) GATE Center of Excellence

DOE Office of Scientific and Technical Information (OSTI.GOV)

Erickson, Paul

This is the final report of the UC Davis Fuel Cell, Hydrogen, and Hybrid Vehicle (FCH2V) GATE Center of Excellence which spanned from 2005-2012. The U.S. Department of Energy (DOE) established the Graduate Automotive Technology Education (GATE) Program, to provide a new generation of engineers and scientists with knowledge and skills to create advanced automotive technologies. The UC Davis Fuel Cell, Hydrogen, and Hybrid Vehicle (FCH2V) GATE Center of Excellence established in 2005 is focused on research, education, industrial collaboration and outreach within automotive technology. UC Davis has had two independent GATE centers with separate well-defined objectives and research programsmore » from 1998. The Fuel Cell Center, administered by ITS-Davis, has focused on fuel cell technology. The Hybrid-Electric Vehicle Design Center (HEV Center), administered by the Department of Mechanical and Aeronautical Engineering, has focused on the development of plug-in hybrid technology using internal combustion engines. The merger of these two centers in 2005 has broadened the scope of research and lead to higher visibility of the activity. UC Davis's existing GATE centers have become the campus's research focal points on fuel cells and hybrid-electric vehicles, and the home for graduate students who are studying advanced automotive technologies. The centers have been highly successful in attracting, training, and placing top-notch students into fuel cell and hybrid programs in both industry and government.« less

Demonstration of universal parametric entangling gates on a multi-qubit lattice

PubMed Central

Reagor, Matthew; Osborn, Christopher B.; Tezak, Nikolas; Staley, Alexa; Prawiroatmodjo, Guenevere; Scheer, Michael; Alidoust, Nasser; Sete, Eyob A.; Didier, Nicolas; da Silva, Marcus P.; Acala, Ezer; Angeles, Joel; Bestwick, Andrew; Block, Maxwell; Bloom, Benjamin; Bradley, Adam; Bui, Catvu; Caldwell, Shane; Capelluto, Lauren; Chilcott, Rick; Cordova, Jeff; Crossman, Genya; Curtis, Michael; Deshpande, Saniya; El Bouayadi, Tristan; Girshovich, Daniel; Hong, Sabrina; Hudson, Alex; Karalekas, Peter; Kuang, Kat; Lenihan, Michael; Manenti, Riccardo; Manning, Thomas; Marshall, Jayss; Mohan, Yuvraj; O’Brien, William; Otterbach, Johannes; Papageorge, Alexander; Paquette, Jean-Philip; Pelstring, Michael; Polloreno, Anthony; Rawat, Vijay; Ryan, Colm A.; Renzas, Russ; Rubin, Nick; Russel, Damon; Rust, Michael; Scarabelli, Diego; Selvanayagam, Michael; Sinclair, Rodney; Smith, Robert; Suska, Mark; To, Ting-Wai; Vahidpour, Mehrnoosh; Vodrahalli, Nagesh; Whyland, Tyler; Yadav, Kamal; Zeng, William; Rigetti, Chad T.

2018-01-01

We show that parametric coupling techniques can be used to generate selective entangling interactions for multi-qubit processors. By inducing coherent population exchange between adjacent qubits under frequency modulation, we implement a universal gate set for a linear array of four superconducting qubits. An average process fidelity of ℱ = 93% is estimated for three two-qubit gates via quantum process tomography. We establish the suitability of these techniques for computation by preparing a four-qubit maximally entangled state and comparing the estimated state fidelity with the expected performance of the individual entangling gates. In addition, we prepare an eight-qubit register in all possible bitstring permutations and monitor the fidelity of a two-qubit gate across one pair of these qubits. Across all these permutations, an average fidelity of ℱ = 91.6 ± 2.6% is observed. These results thus offer a path to a scalable architecture with high selectivity and low cross-talk. PMID:29423443

Disturb-Free Three-Dimensional Vertical Floating Gate NAND with Separated-Sidewall Control Gate

NASA Astrophysics Data System (ADS)

Seo, Moon-Sik; Endoh, Tetsuo

2012-02-01

Recently, the three-dimensional (3D) vertical floating gate (FG) type NAND cell arrays with the sidewall control gate (SCG) structure are receiving attention to overcome the reliability issues of charge trap (CT) type 3D NAND. In order to achieve the multilevel cell (MLC) operation for lower bit cost in 3D NAND, it is important to eliminate reliability issues, such as the Vth distribution with interference and disturbance problems and Vth shift with retention issues. In this paper, we intensively investigated the disturbance problems of the 3D vertical FG type NAND cell with separated-sidewall control gate (S-SCG) structure for the reliable MLC operation. Above all, we successfully demonstrate the fully suppressed disturbance problems, such as indirect programming of the unselected cells, hot electron injection of the edge cells and direct influence to the neighboring passing cells, by using the S-SCG with 30 nm pillar size.

Quantum Algorithms to Simulate Many-Body Physics of Correlated Fermions

NASA Astrophysics Data System (ADS)

Jiang, Zhang; Sung, Kevin J.; Kechedzhi, Kostyantyn; Smelyanskiy, Vadim N.; Boixo, Sergio

2018-04-01

Simulating strongly correlated fermionic systems is notoriously hard on classical computers. An alternative approach, as proposed by Feynman, is to use a quantum computer. We discuss simulating strongly correlated fermionic systems using near-term quantum devices. We focus specifically on two-dimensional (2D) or linear geometry with nearest-neighbor qubit-qubit couplings, typical for superconducting transmon qubit arrays. We improve an existing algorithm to prepare an arbitrary Slater determinant by exploiting a unitary symmetry. We also present a quantum algorithm to prepare an arbitrary fermionic Gaussian state with O (N2) gates and O (N ) circuit depth. Both algorithms are optimal in the sense that the numbers of parameters in the quantum circuits are equal to those describing the quantum states. Furthermore, we propose an algorithm to implement the 2D fermionic Fourier transformation on a 2D qubit array with only O (N1.5) gates and O (√{N }) circuit depth, which is the minimum depth required for quantum information to travel across the qubit array. We also present methods to simulate each time step in the evolution of the 2D Fermi-Hubbard model—again on a 2D qubit array—with O (N ) gates and O (√{N }) circuit depth. Finally, we discuss how these algorithms can be used to determine the ground-state properties and phase diagrams of strongly correlated quantum systems using the Hubbard model as an example.

NOTE: Pre-clinical evaluation of respiratory-gated delivery of volumetric modulated arc therapy with RapidArc

NASA Astrophysics Data System (ADS)

Nicolini, Giorgia; Vanetti, Eugenio; Clivio, Alessandro; Fogliata, Antonella; Cozzi, Luca

2010-06-01

A study was carried out to evaluate the possibility of delivering volumetric modulated arc therapy with the RapidArc technology under respiratory-gated conditions. The experiments were performed in the framework of a non-clinically released environment. Plans of six patients, all realized for a single arc, were used for the experiments. The Real-time Position Management™ (RPM) respiratory gating system from Varian was used to generate gate-open signals of different durations. Arcs were delivered applying the different gates creating sequences of beam-hold/beam-on during the dose delivery: the average number of interruptions for a single arc ranged from 0 to 45. Dose prescription was set to 2 Gy and different gate-open periods of 30, 15 and 5 s to keep gantry speed constant at maximum. 5 Gy and 15 Gy doses were then applied to gate-open signals of 5 and 8 s, respectively, to mimic the most challenging conditions of slow gantry rotation and high-frequency interruptions. The 5 and 15 Gy experiments represent dose conditions of clinical interest for stereotactic treatments. For each patient and gating condition, pre-treatment 2D verification measurements were performed using the PTW-729 array in conjunction with the Octavius phantom (PTW, Freiburg); measurements were performed on different days (one per patient, with the complete setup of phantom and detectors every time), while each gating experiment was repeated seven consecutive times for reproducibility (without a new setup of the measurement equipment). Measurements were compared with dose calculations in the treatment planning system (performed without any gating) to appraise the dosimetric impact of the presence of gating and the eventual dependence from the number of interruptions during a single arc. Analysis of machine-registered log files in terms of average deviations between actual and expected positions (from automatic measurements every 50 ms) resulted in mean ΔMU (monitor units) <0.02% for all gating conditions. Δ(Gantry angle) = 0.38 ± 0.01° for 2 Gy (all gate periods), 0.24 ± 0.01° for 5 Gy, and 0.10 ± 0.01° for 15 Gy deliveries. Average deviations for multileaf collimator (MLC) positions (root mean square over all 120 leaves) were 0.45 ± 0.01 mm for 2 Gy (all gate periods), 0.32 ± 0.01 mm for 5 Gy and 0.14 ± 0.01 mm for 15 Gy. Results in terms of dose measurements confirmed that the application of gating to RapidArc delivery does not affect the quality of the dose delivery. With criteria of ΔD = 3%, DTA = 3 mm, the gamma test was passing in a range of 99 to 100% of the measured points for most of the cases (with maximum number of interruptions of about 20 per arc) and from 97 to 98% for the extreme case of 15 Gy and 8 s gate-open signal (corresponding to almost 50 interruptions per arc). In conclusion, RapidArc delivery proved, in a pre-clinical phase and non-clinically released framework, to be reliable and dosimetrically accurate also when applied in conjunction with gating procedures.

Development of a Crosstalk Suppression Algorithm for KID Readout

NASA Astrophysics Data System (ADS)

Lee, Kyungmin; Ishitsuka, H.; Oguri, S.; Suzuki, J.; Tajima, O.; Tomita, N.; Won, Eunil; Yoshida, M.

2018-06-01

The GroundBIRD telescope aims to detect B-mode polarization of the cosmic microwave background radiation using the kinetic inductance detector array as a polarimeter. For the readout of the signal from detector array, we have developed a frequency division multiplexing readout system based on a digital down converter method. These techniques in general have the leakage problems caused by the crosstalks. The window function was applied in the field programmable gate arrays to mitigate the effect of these problems and tested it in algorithm level.

Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography.

PubMed

Lim, Cheol-Min; Lee, In-Kyu; Lee, Ki Joong; Oh, Young Kyoung; Shin, Yong-Beom; Cho, Won-Ju

2017-01-01

This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.

Microfluidic valve array control system integrating a fluid demultiplexer circuit

NASA Astrophysics Data System (ADS)

Kawai, Kentaro; Arima, Kenta; Morita, Mizuho; Shoji, Shuichi

2015-06-01

This paper proposes an efficient control method for the large-scale integration of microvalves in microfluidic systems. The proposed method can control 2n individual microvalves with 2n + 2 control lines (where n is an integer). The on-chip valves are closed by applying pressure to a control line, similar to conventional pneumatic microvalves. Another control line closes gate valves between the control line to the on-chip valves and the on-chip valves themselves, to preserve the state of the on-chip valves. The remaining control lines select an activated gate valve. While the addressed gate valve is selected by the other control lines, the corresponding on-chip valve is actuated by applying input pressure to the control line to the on-chip valves. Using this method would substantially reduce the number of world-to-chip connectors and off-chip valve controllers. Experiments conducted using a fabricated 28 microvalve array device, comprising 256 individual on-chip valves controlled with 18 (2   ×   8 + 2) control lines, yielded switching speeds for the selected on-chip valve under 90 ms.

Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography

NASA Astrophysics Data System (ADS)

Lim, Cheol-Min; Lee, In-Kyu; Lee, Ki Joong; Oh, Young Kyoung; Shin, Yong-Beom; Cho, Won-Ju

2017-12-01

This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.

Two-Dimensional Arrays of Neutral Atom Quantum Gates

DTIC Science & Technology

2012-10-20

Box 12211 Research Triangle Park, NC 27709-2211 15. SUBJECT TERMS quantum computing , Rydberg atoms, entanglement Mark Saffman University of...Nature Physics, (01 2009): 0. doi: 10.1038/nphys1178 10/19/2012 9.00 K. Mølmer, M. Saffman. Scaling the neutral-atom Rydberg gate quantum computer by...Saffman, E. Brion, K. Mølmer. Error Correction in Ensemble Registers for Quantum Repeaters and Quantum Computers , Physical Review Letters, (3 2008): 0

Design, processing, and testing of LSI arrays for space station

NASA Technical Reports Server (NTRS)

Schneider, W. C.

1974-01-01

At wafer probe, units of the TA6567 circuit, a beam leaded COS/MOS/SOS 256-bit RAM, were demonstrated to be functionally perfect. An aluminum gate current-sense version and a silicon-gate voltage-sense version of this memory were developed. Initial base line data for the beam lead SOS process using the TA5388 circuit show the stability of the dc device characteristics through the beam lead processing.

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Britton, Paul; Hatfield, Glen Spencer; Novack, Steven D.

2017-01-01

Today's launch vehicles complex electronic and avionics systems heavily utilize Field Programmable Gate Array (FPGA) integrated circuits (IC) for their superb speed and reconfiguration capabilities. Consequently, FPGAs are prevalent ICs in communication protocols such as MILSTD- 1553B and in control signal commands such as in solenoid valve actuations. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Evolutionary Based Techniques for Fault Tolerant Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Larchev, Gregory V.; Lohn, Jason D.

2006-01-01

The use of SRAM-based Field Programmable Gate Arrays (FPGAs) is becoming more and more prevalent in space applications. Commercial-grade FPGAs are potentially susceptible to permanently debilitating Single-Event Latchups (SELs). Repair methods based on Evolutionary Algorithms may be applied to FPGA circuits to enable successful fault recovery. This paper presents the experimental results of applying such methods to repair four commonly used circuits (quadrature decoder, 3-by-3-bit multiplier, 3-by-3-bit adder, 440-7 decoder) into which a number of simulated faults have been introduced. The results suggest that evolutionary repair techniques can improve the process of fault recovery when used instead of or as a supplement to Triple Modular Redundancy (TMR), which is currently the predominant method for mitigating FPGA faults.

Real-time field programmable gate array architecture for computer vision

NASA Astrophysics Data System (ADS)

Arias-Estrada, Miguel; Torres-Huitzil, Cesar

2001-01-01

This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low-level image processing. The field programmable gate array (FPGA)-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and it is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on dedicated very- large-scale-integrated devices to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real-time performance are discussed. Some results are presented and discussed.

Field programmable gate array processing of eye-safe all-fiber coherent wind Doppler lidar return signals

NASA Astrophysics Data System (ADS)

Abdelazim, S.; Santoro, D.; Arend, M.; Moshary, F.; Ahmed, S.

2011-11-01

A field deployable all-fiber eye-safe Coherent Doppler LIDAR is being developed at the Optical Remote Sensing Lab at the City College of New York (CCNY) and is designed to monitor wind fields autonomously and continuously in urban settings. Data acquisition is accomplished by sampling lidar return signals at 400 MHz and performing onboard processing using field programmable gate arrays (FPGAs). The FPGA is programmed to accumulate signal information that is used to calculate the power spectrum of the atmospherically back scattered signal. The advantage of using FPGA is that signal processing will be performed at the hardware level, reducing the load on the host computer and allowing for 100% return signal processing. An experimental setup measured wind speeds at ranges of up to 3 km.

A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization.

PubMed

Berger, Andrew J; Page, Michael R; Jacob, Jan; Young, Justin R; Lewis, Jim; Wenzel, Lothar; Bhallamudi, Vidya P; Johnston-Halperin, Ezekiel; Pelekhov, Denis V; Hammel, P Chris

2014-12-01

Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.

A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berger, Andrew J., E-mail: berger.156@osu.edu; Page, Michael R.; Young, Justin R.

Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform themore » various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.« less

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

NASA Astrophysics Data System (ADS)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

Image processing applications: From particle physics to society

NASA Astrophysics Data System (ADS)

Sotiropoulou, C.-L.; Luciano, P.; Gkaitatzis, S.; Citraro, S.; Giannetti, P.; Dell'Orso, M.

2017-01-01

We present an embedded system for extremely efficient real-time pattern recognition execution, enabling technological advancements with both scientific and social impact. It is a compact, fast, low consumption processing unit (PU) based on a combination of Field Programmable Gate Arrays (FPGAs) and the full custom associative memory chip. The PU has been developed for real time tracking in particle physics experiments, but delivers flexible features for potential application in a wide range of fields. It has been proposed to be used in accelerated pattern matching execution for Magnetic Resonance Fingerprinting (biomedical applications), in real time detection of space debris trails in astronomical images (space applications) and in brain emulation for image processing (cognitive image processing). We illustrate the potentiality of the PU for the new applications.

Graphene based terahertz phase modulators

NASA Astrophysics Data System (ADS)

Kakenov, N.; Ergoktas, M. S.; Balci, O.; Kocabas, C.

2018-07-01

Electrical control of amplitude and phase of terahertz radiation (THz) is the key technological challenge for high resolution and noninvasive THz imaging. The lack of active materials and devices hinders the realization of these imaging systems. Here, we demonstrate an efficient terahertz phase and amplitude modulation using electrically tunable graphene devices. Our device structure consists of electrolyte-gated graphene placed at quarter wavelength distance from a reflecting metallic surface. In this geometry, graphene operates as a tunable impedance surface which yields electrically controlled reflection phase. Terahertz time domain reflection spectroscopy reveals the voltage controlled phase modulation of π and the reflection modulation of 50 dB. To show the promises of our approach, we demonstrate a multipixel phase modulator array which operates as a gradient impedance surface.

Iris unwrapping using the Bresenham circle algorithm for real-time iris recognition

NASA Astrophysics Data System (ADS)

Carothers, Matthew T.; Ngo, Hau T.; Rakvic, Ryan N.; Broussard, Randy P.

2015-02-01

An efficient parallel architecture design for the iris unwrapping process in a real-time iris recognition system using the Bresenham Circle Algorithm is presented in this paper. Based on the characteristics of the model parameters this algorithm was chosen over the widely used polar conversion technique as the iris unwrapping model. The architecture design is parallelized to increase the throughput of the system and is suitable for processing an inputted image size of 320 × 240 pixels in real-time using Field Programmable Gate Array (FPGA) technology. Quartus software is used to implement, verify, and analyze the design's performance using the VHSIC Hardware Description Language. The system's predicted processing time is faster than the modern iris unwrapping technique used today∗.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Citterio, M.; Camplani, A.; Cannon, M.

SRAM based Field Programmable Gate Arrays (FPGAs) have been rarely used in High Energy Physics (HEP) due to their sensitivity to radiation. The last generation of commercial FPGAs based on 28 nm feature size and on Silicon On Insulator (SOI) technologies are more tolerant to radiation to the level that their use in front-end electronics is now feasible. FPGAs provide re-programmability, high-speed computation and fast data transmission through the embedded serial transceivers. They could replace custom application specific integrated circuits in front end electronics in locations with moderate radiation field. Finally, the use of a FPGA in HEP experiments ismore » only limited by our ability to mitigate single event effects induced by the high energy hadrons present in the radiation field.« less

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

An innovative telescope control system architecture for SST-GATE telescopes at the CTA Observatory

NASA Astrophysics Data System (ADS)

Fasola, Gilles; Mignot, Shan; Laporte, Philippe; Abchiche, Abdel; Buchholtz, Gilles; Jégouzo, Isabelle

2014-07-01

SST-GATE (Small Size Telescope - GAmma-ray Telescope Elements) is a 4-metre telescope designed as a prototype for the Small Size Telescopes (SST) of the Cherenkov Telescope Array (CTA), a major facility for the very high energy gamma-ray astronomy of the next three decades. In this 100-telescope array there will be 70 SSTs, involving a design with an industrial view aiming at long-term service, low maintenance effort and reduced costs. More than a prototype, SST-GATE is also a fully functional telescope that shall be usable by scientists and students at the Observatoire de Meudon for 30 years. The Telescope Control System (TCS) is designed to work either as an element of a large array driven by an array controller or in a stand-alone mode with a remote workstation. Hence it is built to be autonomous with versatile interfacing; as an example, pointing and tracking —the main functions of the telescope— are managed onboard, including astronomical transformations, geometrical transformations (e.g. telescope bending model) and drive control. The core hardware is a CompactRIO (cRIO) featuring a real-time operating system and an FPGA. In this paper, we present an overview of the current status of the TCS. We especially focus on three items: the pointing computation implemented in the FPGA of the cRIO —using CORDIC algorithms— since it enables an optimisation of the hardware resources; data flow management based on OPCUA with its specific implementation on the cRIO; and the use of an EtherCAT field-bus for its ability to provide real-time data exchanges with the sensors and actuators distributed throughout the telescope.

Flexible amorphous silicon PIN diode x-ray detectors

NASA Astrophysics Data System (ADS)

Marrs, Michael; Bawolek, Edward; Smith, Joseph T.; Raupp, Gregory B.; Morton, David

2013-05-01

A low temperature amorphous silicon (a-Si) thin film transistor (TFT) and amorphous silicon PIN photodiode technology for flexible passive pixel detector arrays has been developed using active matrix display technology. The flexible detector arrays can be conformed to non-planar surfaces with the potential to detect x-rays or other radiation with an appropriate conversion layer. The thin, lightweight, and robust backplanes may enable the use of highly portable x-ray detectors for use in the battlefield or in remote locations. We have fabricated detector arrays up to 200 millimeters along the diagonal on a Gen II (370 mm x 470 mm rectangular substrate) using plasma enhanced chemical vapor deposition (PECVD) a-Si as the active layer and PECVD silicon nitride (SiN) as the gate dielectric and passivation. The a-Si based TFTs exhibited an effective saturation mobility of 0.7 cm2/V-s, which is adequate for most sensing applications. The PIN diode material was fabricated using a low stress amorphous silicon (a-Si) PECVD process. The PIN diode dark current was 1.7 pA/mm2, the diode ideality factor was 1.36, and the diode fill factor was 0.73. We report on the critical steps in the evolution of the backplane process from qualification of the low temperature (180°C) TFT and PIN diode process on the 150 mm pilot line, the transfer of the process to flexible plastic substrates, and finally a discussion and demonstration of the scale-up to the Gen II (370 x 470 mm) panel scale pilot line.

Introduction to FPGA Devices and The Challenges for Critical Application - A User's Perspective

NASA Technical Reports Server (NTRS)

Berg, Melanie; LaBel, Kenneth

2015-01-01

This presentation is an introduction to Field Programmable Gate Array (FPGA) devices and the challenges of critical application including: safety, reliability, availability, recoverability, and security.

Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Arrays

NASA Technical Reports Server (NTRS)

Pang, Jackson; Pingree, Paula; Torgerson, J. Leigh

2006-01-01

Deep Space Telecommunications Requirements: 1) Automated file transfer across inter-planetary distances; 2) Limited communication periods; 3) Reliable transport; 4) Delay and Disruption Tolerant; and 5) Asymmetric Data Channels.

A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm

PubMed Central

Guo, Xinyu; Wang, Hong; Devabhaktuni, Vijay

2012-01-01

A design of systolic array-based Field Programmable Gate Array (FPGA) parallel architecture for Basic Local Alignment Search Tool (BLAST) Algorithm is proposed. BLAST is a heuristic biological sequence alignment algorithm which has been used by bioinformatics experts. In contrast to other designs that detect at most one hit in one-clock-cycle, our design applies a Multiple Hits Detection Module which is a pipelining systolic array to search multiple hits in a single-clock-cycle. Further, we designed a Hits Combination Block which combines overlapping hits from systolic array into one hit. These implementations completed the first and second step of BLAST architecture and achieved significant speedup comparing with previously published architectures. PMID:25969747

Reconfigurable ultra-thin film GDNMOS device for ESD protection in 28 nm FD-SOI technology

NASA Astrophysics Data System (ADS)

Athanasiou, Sotirios; Legrand, Charles-Alexandre; Cristoloveanu, Sorin; Galy, Philippe

2017-02-01

We propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fabricated with 28 nm UTBB FD-SOI high-k metal gate technology. By modifying the combination of the diode and transistor gate stacks, the robustness of the device is optimized, achieving a maximum breakdown voltage (VBR) of 4.9 V. In addition, modifications of the gate length modulate the trigger voltage (Vt1) with a minimum value of 3.5 V. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation. A lower doping of the base enhances the bipolar gain, leading to thyristor behavior. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior.

The effect of plasma density and emitter geometry on space charge limits for field emitter array electron charge emission into a space plasma

NASA Astrophysics Data System (ADS)

Morris, Dave; Gilchrist, Brian; Gallimore, Alec

2001-02-01

Field Emitter Array Cathodes (FEACs) are a new technology being developed for several potential spacecraft electron emission and charge control applications. Instead of a single hot (i.e., high powered) emitter, or a gas dependant plasma contactor, FEAC systems consist of many (hundreds or thousands) of small (micron level) cathode/gate pairs printed on a semiconductor wafer that effect cold field emission at relatively low voltages. Each individual cathode emits only micro-amp level currents, but a functional array is capable of amp/cm2 current densities. It is hoped that thus FEAC offers the possibility of a relatively low-power, simple to integrate, and inexpensive technique for the high level of current emissions that are required for an electrodynamic tether (EDT) propulsion mission. Space charge limits are a significant concern for the EDT application. Vacuum chamber tests and PIC simulations are being performed at the University of Michigan Plasmadynamics and Electric Propulsion Laboratory and Space Physics Research Laboratory to determine the effect of plasma density and emitter geometry on space charge limitations. The results of this work and conclusions to date of how to best mitigate space charge limits will be presented. .

A Digital Backend for the Low Frequency All Sky Monitor

NASA Astrophysics Data System (ADS)

Dartez, L. P.

2014-04-01

The Low Frequency All Sky Monitor (LoFASM) is a distributed array of dipole antennas that are sensitive to radio frequencies from 10 to 88 MHz. The primary science goals of LoFASM are the detection and study of low-frequency radio transients, a high priority science goal as deemed by the National Research Council's decadal survey. LoFASM consists of antennas and front-end electronics that were originally developed for the Long Wavelength Array (LWA) by the U.S. Naval Research Lab, the University of New Mexico, Virginia Tech, and the Jet Propulsion Laboratory. LoFASM, funded by the U.S. Department of Defense, will initially consist of four stations, each consisting of 12 dual-polarization dipole antennas. In a single station, RF signals from each of the individual LoFASM dipoles are combined in phase in order to synthesize LoFASM's beam. The LoFASM RF signals are phased up so that the resulting beam is sensitive to radio emission that originates from the zenith and RF signals approaching from the horizon are attenuated. Digitally, this is achieved using a full Stokes 100MHz correlating spectrometer constructed using field programmable gate array (FPGA) technology. In this thesis I will describe the design and usage of the LoFASM Correlator.

Miniature MMIC Low Mass/Power Radiometer Modules for the 180 GHz GeoSTAR Array

NASA Technical Reports Server (NTRS)

Kangaslahti, Pekka; Tanner, Alan; Pukala, David; Lambrigtsen, Bjorn; Lim, Boon; Mei, Xiaobing; Lai, Richard

2010-01-01

We have developed and demonstrated miniature 180 GHz Monolithic Microwave Integrated Circuit (MMIC) radiometer modules that have low noise temperature, low mass and low power consumption. These modules will enable the Geostationary Synthetic Thinned Aperture Radiometer (GeoSTAR) of the Precipitation and All-weather Temperature and Humidity (PATH) Mission for atmospheric temperature and humidity profiling. The GeoSTAR instrument has an array of hundreds of receivers. Technology that was developed included Indium Phosphide (InP) MMIC Low Noise Amplifiers (LNAs) and second harmonic MMIC mixers and I-Q mixers, surface mount Multi-Chip Module (MCM) packages at 180 GHz, and interferometric array at 180 GHz. A complete MMIC chip set for the 180 GHz receiver modules (LNAs and I-Q Second harmonic mixer) was developed. The MMIC LNAs had more than 50% lower noise temperature (NT=300K) than previous state-of-art and MMIC I-Q mixers demonstrated low LO power (3 dBm). Two lots of MMIC wafers were processed with very high DC transconductance of up to 2800 mS/mm for the 35 nm gate length devices. Based on these MMICs a 180 GHz Multichip Module was developed that had a factor of 100 lower mass/volume (16x18x4.5 mm3, 3g) than previous generation 180 GHz receivers.

Dielectrophoresis-Assisted Integration of 1024 Carbon Nanotube Sensors into a CMOS Microsystem.

PubMed

Seichepine, Florent; Rothe, Jörg; Dudina, Alexandra; Hierlemann, Andreas; Frey, Urs

2017-05-01

Carbon-nanotube (CNT)-based sensors offer the potential to detect single-molecule events and picomolar analyte concentrations. An important step toward applications of such nanosensors is their integration in large arrays. The availability of large arrays would enable multiplexed and parallel sensing, and the simultaneously obtained sensor signals would facilitate statistical analysis. A reliable method to fabricate an array of 1024 CNT-based sensors on a fully processed complementary-metal-oxide-semiconductor microsystem is presented. A high-yield process for the deposition of CNTs from a suspension by means of liquid-coupled floating-electrode dielectrophoresis (DEP), which yielded 80% of the sensor devices featuring between one and five CNTs, is developed. The mechanism of floating-electrode DEP on full arrays and individual devices to understand its self-limiting behavior is studied. The resistance distributions across the array of CNT devices with respect to different DEP parameters are characterized. The CNT devices are then operated as liquid-gated CNT field-effect-transistors (LG-CNTFET) in liquid environment. Current dependency to the gate voltage of up to two orders of magnitude is recorded. Finally, the sensors are validated by studying the pH dependency of the LG-CNTFET conductance and it is demonstrated that 73% of the CNT sensors of a given microsystem show a resistance decrease upon increasing the pH value. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

GaAs VLSI technology and circuit elements for DSP

NASA Astrophysics Data System (ADS)

Mikkelson, James M.

1990-10-01

Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

NASA Astrophysics Data System (ADS)

Marmon, Jason; Rai, Satish; Wang, Kai; Zhou, Weilie; Zhang, Yong

The pathway for CMOS technology beyond the 5-nm technology node remains unclear for both physical and technological reasons. A new transistor paradigm is required. A LET (Marmon et. al., Front. Phys. 2016, 4, No. 8) offers electronic-optical hybridization at the component level, and is capable of continuing Moore's law to the quantum scale. A LET overcomes a FET's fabrication complexity, e.g., physical gate and doping, by employing optical gating and photoconductivity, while multiple independent, optical gates readily realize unique functionalities. We report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs, incorporating an M-S-M structure, show output and transfer characteristics resembling advanced FETs, e.g., on/off ratios up to 106 with a source-drain voltage of 1.43V, gate-power of 260nW, and a subthreshold swing of 0.3nW/decade (excluding losses). A LET has potential for high-switching (THz) speeds and extremely low-switching energies (aJ) in the ballistic transport region. Our work offers new electronic-optical integration strategies for high speed and low energy computing approaches, which could potentially be extended to other materials and devices.

A 65k pixel, 150k frames-per-second camera with global gating and micro-lenses suitable for fluorescence lifetime imaging

NASA Astrophysics Data System (ADS)

Burri, Samuel; Powolny, François; Bruschini, Claudio E.; Michalet, Xavier; Regazzoni, Francesco; Charbon, Edoardo

2014-05-01

This paper presents our work on a 65k pixel single-photon avalanche diode (SPAD) based imaging sensor realized in a 0.35μm standard CMOS process. At a resolution of 512 by 128 pixels the sensor is read out in 6.4μs to deliver over 150k monochrome frames per second. The individual pixel has a size of 24μm2 and contains the SPAD with a 12T quenching and gating circuitry along with a memory element. The gating signals are distributed across the chip through a balanced tree to minimize the signal skew between the pixels. The array of pixels is row-addressable and data is sent out of the chip on 128 lines in parallel at a frequency of 80MHz. The system is controlled by an FPGA which generates the gating and readout signals and can be used for arbitrary real-time computation on the frames from the sensor. The communication protocol between the camera and a conventional PC is USB2. The active area of the chip is 5% and can be significantly improved with the application of a micro-lens array. A micro-lens array, for use with collimated light, has been designed and its performance is reviewed in the paper. Among other high-speed phenomena the gating circuitry capable of generating illumination periods shorter than 5ns can be used for Fluorescence Lifetime Imaging (FLIM). In order to measure the lifetime of fluorophores excited by a picosecond laser, the sensor's illumination period is synchronized with the excitation laser pulses. A histogram of the photon arrival times relative to the excitation is then constructed by counting the photons arriving during the sensitive time for several positions of the illumination window. The histogram for each pixel is transferred afterwards to a computer where software routines extract the lifetime at each location with an accuracy better than 100ps. We show results for fluorescence lifetime measurements using different fluorophores with lifetimes ranging from 150ps to 5ns.

Bidirectional quantum teleportation of unknown photons using path-polarization intra-particle hybrid entanglement and controlled-unitary gates via cross-Kerr nonlinearity

NASA Astrophysics Data System (ADS)

Heo, Jino; Hong, Chang-Ho; Lim, Jong-In; Yang, Hyung-Jin

2015-05-01

We propose an arbitrary controlled-unitary (CU) gate and a bidirectional quantum teleportation (BQTP) scheme. The proposed CU gate utilizes photonic qubits (photons) with cross-Kerr nonlinearities (XKNLs), X-homodyne detectors, and linear optical elements, and consists of the consecutive operation of a controlled-path (C-path) gate and a gathering-path (G-path) gate. It is almost deterministic and feasible with current technology when a strong coherent state and weak XKNLs are employed. Based on the CU gate, we present a BQTP scheme that simultaneously teleports two unknown photons between distant users by transmitting only one photon in a path-polarization intra-particle hybrid entangled state. Consequently, it is possible to experimentally implement BQTP with a certain success probability using the proposed CU gate. Project supported by the Ministry of Science, ICT&Future Planning, Korea, under the C-ITRC (Convergence Information Technology Research Center) Support program (NIPA-2013-H0301-13-3007) supervised by the National IT Industry Promotion Agency.

High-performance enhancement-mode Al2O3/InAlGaN/GaN MOS high-electron mobility transistors with a self-aligned gate recessing technology

NASA Astrophysics Data System (ADS)

Zhang, Kai; Kong, Cen; Zhou, Jianjun; Kong, Yuechan; Chen, Tangsheng

2017-02-01

The paper reports high-performance enhancement-mode MOS high-electron mobility transistors (MOS-HEMTs) based on a quaternary InAlGaN barrier. Self-aligned gate technology is used for gate recessing, dielectric deposition, and gate electrode formation. An improved digital recessing process is developed, and an Al2O3 gate dielectric grown with O2 plasma is used. Compared to results with AlGaN barrier, the fabricated E-mode MOS-HEMT with InAlGaN barrier delivers a record output current density of 1.7 A/mm with a threshold voltage (V TH) of 1.5 V, and a small on-resistance (R on) of 2.0 Ω·mm. Excellent V TH hysteresis and greatly improved gate leakage characteristics are also demonstrated.

A SEU-Hard Flip-Flop for Antifuse FPGAs

NASA Technical Reports Server (NTRS)

Katz, R.; Wang, J. J.; McCollum, J.; Cronquist, B.; Chan, R.; Yu, D.; Kleyner, I.; Day, John H. (Technical Monitor)

2001-01-01

A single event upset (SEU)-hardened flip-flop has been designed and developed for antifuse Field Programmable Gate Array (FPGA) application. Design and application issues, testability, test methods, simulation, and results are discussed.

Nanosecond-timescale spin transfer using individual electrons in a quadruple-quantum-dot device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baart, T. A.; Jovanovic, N.; Vandersypen, L. M. K.

2016-07-25

The ability to coherently transport electron-spin states between different sites of gate-defined semiconductor quantum dots is an essential ingredient for a quantum-dot-based quantum computer. Previous shuttles using electrostatic gating were too slow to move an electron within the spin dephasing time across an array. Here, we report a nanosecond-timescale spin transfer of individual electrons across a quadruple-quantum-dot device. Utilizing enhanced relaxation rates at a so-called hot spot, we can upper bound the shuttle time to at most 150 ns. While actual shuttle times are likely shorter, 150 ns is already fast enough to preserve spin coherence in, e.g., silicon based quantum dots.more » This work therefore realizes an important prerequisite for coherent spin transfer in quantum dot arrays.« less

Field Programmable Gate Array Reliability Analysis Guidelines for Launch Vehicle Reliability Block Diagrams

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Britton, Paul; Hatfield, Glen Spencer; Novack, Steven D.

2017-01-01

Field Programmable Gate Arrays (FPGAs) integrated circuits (IC) are one of the key electronic components in today's sophisticated launch and space vehicle complex avionic systems, largely due to their superb reprogrammable and reconfigurable capabilities combined with relatively low non-recurring engineering costs (NRE) and short design cycle. Consequently, FPGAs are prevalent ICs in communication protocols and control signal commands. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Novack, Steven D.; Hatfield, Glen S.; Britton, Paul

2017-01-01

Today's launch vehicles complex electronic and avionic systems heavily utilize the Field Programmable Gate Array (FPGA) integrated circuit (IC). FPGAs are prevalent ICs in communication protocols such as MIL-STD-1553B, and in control signal commands such as in solenoid/servo valves actuations. This paper will demonstrate guidelines to estimate FPGA failure rates for a launch vehicle, the guidelines will account for hardware, firmware, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC, FPGA memory and clock. The firmware portion will provide guidelines on the high level FPGA programming language and ways to account for software/code reliability growth. The radiation portion will provide guidelines on environment susceptibility as well as guidelines on tailoring other launch vehicle programs historical data to a specific launch vehicle.

Mesoscopic Field-Effect-Induced Devices in Depleted Two-Dimensional Electron Systems

NASA Astrophysics Data System (ADS)

Bachsoliani, N.; Platonov, S.; Wieck, A. D.; Ludwig, S.

2017-12-01

Nanoelectronic devices embedded in the two-dimensional electron system (2DES) of a GaAs /(Al ,Ga )As heterostructure enable a large variety of applications ranging from fundamental research to high-speed transistors. Electrical circuits are thereby commonly defined by creating barriers for carriers by the selective depletion of a preexisting 2DES. We explore an alternative approach: we deplete the 2DES globally by applying a negative voltage to a global top gate and screen the electric field of the top gate only locally using nanoscale gates placed on the wafer surface between the plane of the 2DES and the top gate. Free carriers are located beneath the screen gates, and their properties can be controlled by means of geometry and applied voltages. This method promises considerable advantages for the definition of complex circuits by the electric-field effect, as it allows us to reduce the number of gates and simplify gate geometries. Examples are carrier systems with ring topology or large arrays of quantum dots. We present a first exploration of this method pursuing field effect, Hall effect, and Aharonov-Bohm measurements to study electrostatic, dynamic, and coherent properties.

Independent component analysis algorithm FPGA design to perform real-time blind source separation

NASA Astrophysics Data System (ADS)

Meyer-Baese, Uwe; Odom, Crispin; Botella, Guillermo; Meyer-Baese, Anke

2015-05-01

The conditions that arise in the Cocktail Party Problem prevail across many fields creating a need for of Blind Source Separation. The need for BSS has become prevalent in several fields of work. These fields include array processing, communications, medical signal processing, and speech processing, wireless communication, audio, acoustics and biomedical engineering. The concept of the cocktail party problem and BSS led to the development of Independent Component Analysis (ICA) algorithms. ICA proves useful for applications needing real time signal processing. The goal of this research was to perform an extensive study on ability and efficiency of Independent Component Analysis algorithms to perform blind source separation on mixed signals in software and implementation in hardware with a Field Programmable Gate Array (FPGA). The Algebraic ICA (A-ICA), Fast ICA, and Equivariant Adaptive Separation via Independence (EASI) ICA were examined and compared. The best algorithm required the least complexity and fewest resources while effectively separating mixed sources. The best algorithm was the EASI algorithm. The EASI ICA was implemented on hardware with Field Programmable Gate Arrays (FPGA) to perform and analyze its performance in real time.

Fabrication of Gate-Electrode Integrated Carbon-Nanotube Bundle Field Emitters

NASA Technical Reports Server (NTRS)

Toda, Risaku; Bronikowski, Michael; Luong, Edward; Manohara, Harish

2008-01-01

A continuing effort to develop carbon-nanotube-based field emitters (cold cathodes) as high-current-density electron sources has yielded an optimized device design and a fabrication scheme to implement the design. One major element of the device design is to use a planar array of bundles of carbon nanotubes as the field-emission tips and to optimize the critical dimensions of the array (principally, heights of bundles and distances between them) to obtain high area-averaged current density and high reliability over a long operational lifetime a concept that was discussed in more detail in Arrays of Bundles of Carbon Nanotubes as Field Emitters (NPO-40817), NASA Tech Briefs, Vol. 31, No. 2 (February 2007), page 58. Another major element of the design is to configure the gate electrodes (anodes used to extract, accelerate, and/or focus electrons) as a ring that overhangs a recess wherein the bundles of nanotubes are located, such that by virtue of the proximity between the ring and the bundles, a relatively low applied potential suffices to generate the large electric field needed for emission of electrons.

Design, optimization and evaluation of a "smart" pixel sensor array for low-dose digital radiography

NASA Astrophysics Data System (ADS)

Wang, Kai; Liu, Xinghui; Ou, Hai; Chen, Jun

2016-04-01

Amorphous silicon (a-Si:H) thin-film transistors (TFTs) have been widely used to build flat-panel X-ray detectors for digital radiography (DR). As the demand for low-dose X-ray imaging grows, a detector with high signal-to-noise-ratio (SNR) pixel architecture emerges. "Smart" pixel is intended to use a dual-gate photosensitive TFT for sensing, storage, and switch. It differs from a conventional passive pixel sensor (PPS) and active pixel sensor (APS) in that all these three functions are combined into one device instead of three separate units in a pixel. Thus, it is expected to have high fill factor and high spatial resolution. In addition, it utilizes the amplification effect of the dual-gate photosensitive TFT to form a one-transistor APS that leads to a potentially high SNR. This paper addresses the design, optimization and evaluation of the smart pixel sensor and array for low-dose DR. We will design and optimize the smart pixel from the scintillator to TFT levels and validate it through optical and electrical simulation and experiments of a 4x4 sensor array.

Defectivity control of aluminum chemical mechanical planarization in replacement metal gate process of MOSFET

NASA Astrophysics Data System (ADS)

Jin, Zhang; Yuling, Liu; Chenqi, Yan; Yangang, He; Baohong, Gao

2016-04-01

The replacement metal gate (RMG) defectivity performance control is very challenging in high-k metal gate (HKMG) chemical mechanical polishing (CMP). In this study, three major defect types, including fall-on particles, micro-scratch and corrosion have been investigated. The research studied the effects of polishing pad, pressure, rotating speed, flow rate and post-CMP cleaning on the three kinds of defect, which finally eliminated the defects and achieved good surface morphology. This study will provide an important reference value for the future research of aluminum metal gate CMP. Project supported by the Major National Science and Technology Special Projects (No. 2009ZX02308), the Natural Science Foundation for the Youth of Hebei Province (Nos. F2012202094, F2015202267), and the Outstanding Youth Science and Technology Innovation Fund of Hebei University of Technology (No. 2013010).

Convolutional Neural Network on Embedded Linux(trademark) System-on-Chip: A Methodology and Performance Benchmark

DTIC Science & Technology

2016-05-01

A9 CPU and 15 W for the i7 CPU. A method of accelerating this computation is by using a customized hardware unit called a field- programmable gate...implementation of custom logic to accelerate com- putational workloads. This FPGA fabric, in addition to the standard programmable logic, contains 220...chip; field- programmable gate array Daniel Gebhardt U U U U 18 (619) 553-2786 INITIAL DISTRIBUTION 84300 Library (2) 85300 Archive/Stock (1

Convolutional Neural Network on Embedded Linux System-on-Chip: A Methodology and Performance Benchmark

DTIC Science & Technology

2016-05-01

A9 CPU and 15 W for the i7 CPU. A method of accelerating this computation is by using a customized hardware unit called a field- programmable gate...implementation of custom logic to accelerate com- putational workloads. This FPGA fabric, in addition to the standard programmable logic, contains 220...chip; field- programmable gate array Daniel Gebhardt U U U U 18 (619) 553-2786 INITIAL DISTRIBUTION 84300 Library (2) 85300 Archive/Stock (1

Three-dimensional cross point readout detector design for including depth information

NASA Astrophysics Data System (ADS)

Lee, Seung-Jae; Baek, Cheol-Ha

2018-04-01

We designed a depth-encoding positron emission tomography (PET) detector using a cross point readout method with wavelength-shifting (WLS) fibers. To evaluate the characteristics of the novel detector module and the PET system, we used the DETECT2000 to perform optical photon transport in the crystal array. The GATE was also used. The detector module is made up of four layers of scintillator arrays, the five layers of WLS fiber arrays, and two sensor arrays. The WLS fiber arrays in each layer cross each other to transport light to each sensor array. The two sensor arrays are coupled to the forward and left sides of the WLS fiber array, respectively. The identification of three-dimensional pixels was determined using a digital positioning algorithm. All pixels were well decoded, with the system resolution ranging from 2.11 mm to 2.29 mm at full width at half maximum (FWHM).

Portable Multispectral Colorimeter for Metallic Ion Detection and Classification

PubMed Central

Jaimes, Ruth F. V. V.; Borysow, Walter; Gomes, Osmar F.; Salcedo, Walter J.

2017-01-01

This work deals with a portable device system applied to detect and classify different metallic ions as proposed and developed, aiming its application for hydrological monitoring systems such as rivers, lakes and groundwater. Considering the system features, a portable colorimetric system was developed by using a multispectral optoelectronic sensor. All the technology of quantification and classification of metallic ions using optoelectronic multispectral sensors was fully integrated in the embedded hardware FPGA ( Field Programmable Gate Array) technology and software based on virtual instrumentation (NI LabView®). The system draws on an indicative colorimeter by using the chromogen reagent of 1-(2-pyridylazo)-2-naphthol (PAN). The results obtained with the signal processing and pattern analysis using the method of the linear discriminant analysis, allows excellent results during detection and classification of Pb(II), Cd(II), Zn(II), Cu(II), Fe(III) and Ni(II) ions, with almost the same level of performance as for those obtained from the Ultravioled and visible (UV-VIS) spectrophotometers of high spectral resolution. PMID:28788082

Coherent ultra dense wavelength division multiplexing passive optical networks

NASA Astrophysics Data System (ADS)

Shahpari, Ali; Ferreira, Ricardo; Ribeiro, Vitor; Sousa, Artur; Ziaie, Somayeh; Tavares, Ana; Vujicic, Zoran; Guiomar, Fernando P.; Reis, Jacklyn D.; Pinto, Armando N.; Teixeira, António

2015-12-01

In this paper, we firstly review the progress in ultra-dense wavelength division multiplexing passive optical network (UDWDM-PON), by making use of the key attributes of this technology in the context of optical access and metro networks. Besides the inherit properties of coherent technology, we explore different modulation formats and pulse shaping. The performance is experimentally demonstrated through a 12 × 10 Gb/s bidirectional UDWDM-PON over hybrid 80 km standard single mode fiber (SSMF) and optical wireless link. High density, 6.25 GHz grid, Nyquist shaped 16-ary quadrature amplitude modulation (16QAM) and digital frequency shifting are some of the properties exploited together in the tests. Also, bidirectional transmission in fiber, relevant in the context, is analyzed in terms of nonlinear and back-reflection effects on receiver sensitivity. In addition, as a basis for the discussion on market readiness, we experimentally demonstrate real-time detection of a Nyquist-shaped quaternary phase-shift keying (QPSK) signal using simple 8-bit digital signal processing (DSP) on a field-programmable gate array (FPGA).

Cortical control of intraspinal microstimulation: Toward a new approach for restoration of function after spinal cord injury.

PubMed

Shahdoost, Shahab; Frost, Shawn; Dunham, Caleb; DeJong, Stacey; Barbay, Scott; Nudo, Randolph; Mohseni, Pedram

2015-08-01

Approximately 6 million people in the United States are currently living with paralysis in which 23% of the cases are related to spinal cord injury (SCI). Miniaturized closed-loop neural interfaces have the potential for restoring function and mobility lost to debilitating neural injuries such as SCI by leveraging recent advancements in bioelectronics and a better understanding of the processes that underlie functional and anatomical reorganization in an injured nervous system. This paper describes our current progress toward developing a miniaturized brain-machine-spinal cord interface (BMSI) that converts in real time the neural command signals recorded from the cortical motor regions to electrical stimuli delivered to the spinal cord below the injury level. Using a combination of custom integrated circuit (IC) technology for corticospinal interfacing and field-programmable gate array (FPGA)-based technology for embedded signal processing, we demonstrate proof-of-concept of distinct muscle pattern activation via intraspinal microstimulation (ISMS) controlled in real time by intracortical neural spikes in an anesthetized laboratory rat.

Generic FPGA-Based Platform for Distributed IO in Proton Therapy Patient Safety Interlock System

NASA Astrophysics Data System (ADS)

Eichin, Michael; Carmona, Pablo Fernandez; Johansen, Ernst; Grossmann, Martin; Mayor, Alexandre; Erhardt, Daniel; Gomperts, Alexander; Regele, Harald; Bula, Christian; Sidler, Christof

2017-06-01

At the Paul Scherrer Institute (PSI) in Switzerland, cancer patients are treated with protons. Proton therapy at PSI has a long history and started in the 1980s. More than 30 years later, a new gantry has recently been installed in the existing facility. This new machine has been delivered by an industry partner. A big challenge is the integration of the vendor's safety system into the existing PSI environment. Different interface standards and the complexity of the system made it necessary to find a technical solution connecting an industry system to the existing PSI infrastructure. A novel very flexible distributed IO system based on field-programmable gate array (FPGA) technology was developed, supporting many different IO interface standards and high-speed communication links connecting the device to a PSI standard versa module eurocard-bus input output controller. This paper summarizes the features of the hardware technology, the FPGA framework with its high-speed communication link protocol, and presents our first measurement results.

Single Event Effects Test Results for the Actel ProASIC Plus and Altera Stratix-II Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Allen, Gregory R.; Swift, Gary M.

2006-01-01

This work describes radiation testing of Actel's ProASIC Plus and Altera's Stratix-II FPGAs. The Actel Device Under Test (DUT) was a ProASIC Plus APA300-PQ208 nonvolatile, field reprogrammable device which is based on a 0.22micron flash-based LVCMOS technology. Limited investigation has taken place into flash based FPGA technologies, therefore this test served as a preliminary reference point for various SEE behaviors. The Altera DUT was a Stratix-II EP2S60F1020C4. Single Event Upset (SEU) and Single Event Latchup (SEL) were the focus of these studies. For the Actel, a latchup test was done at an effective LET of 75.0 MeV-sq cm/mg at room temperature, and no latchup was detected when irradiated to a total fluence of 1 x 10(exp 7) particles/sq cm. The Altera part was shown to latchup at room temperature.

Portable Multispectral Colorimeter for Metallic Ion Detection and Classification.

PubMed

Braga, Mauro S; Jaimes, Ruth F V V; Borysow, Walter; Gomes, Osmar F; Salcedo, Walter J

2017-07-28

This work deals with a portable device system applied to detect and classify different metallic ions as proposed and developed, aiming its application for hydrological monitoring systems such as rivers, lakes and groundwater. Considering the system features, a portable colorimetric system was developed by using a multispectral optoelectronic sensor. All the technology of quantification and classification of metallic ions using optoelectronic multispectral sensors was fully integrated in the embedded hardware FPGA ( Field Programmable Gate Array) technology and software based on virtual instrumentation (NI LabView ® ). The system draws on an indicative colorimeter by using the chromogen reagent of 1-(2-pyridylazo)-2-naphthol (PAN). The results obtained with the signal processing and pattern analysis using the method of the linear discriminant analysis, allows excellent results during detection and classification of Pb(II), Cd(II), Zn(II), Cu(II), Fe(III) and Ni(II) ions, with almost the same level of performance as for those obtained from the Ultravioled and visible (UV-VIS) spectrophotometers of high spectral resolution.

The design of RFID convey or belt gate systems using an antenna control unit.

PubMed

Park, Chong Ryol; Lee, Seung Joon; Eom, Ki Hwan

2011-01-01

This paper proposes an efficient management system utilizing a Radio Frequency Identification (RFID) antenna control unit which is moving along with the path of boxes of materials on the conveyor belt by manipulating a motor. The proposed antenna control unit, which is driven by a motor and is located on top of the gate, has an array structure of two antennas with parallel connection. The array structure helps improve the directivity of antenna beam pattern and the readable RFID distance due to its configuration. In the experiments, as the control unit follows moving materials, the reading time has been improved by almost three-fold compared to an RFID system employing conventional fixed antennas. The proposed system also has a recognition rate of over 99% without additional antennas for detecting the sides of a box of materials. The recognition rate meets the conditions recommended by the Electronic Product Code glbal network (EPC)global for commercializing the system, with three antennas at a 20 dBm power of reader and a conveyor belt speed of 3.17 m/s. This will enable a host of new RFID conveyor belt gate systems with increased performance.

The Design of RFID Convey or Belt Gate Systems Using an Antenna Control Unit

PubMed Central

Park, Chong Ryol; Lee, Seung Joon; Eom, Ki Hwan

2011-01-01

This paper proposes an efficient management system utilizing a Radio Frequency Identification (RFID) antenna control unit which is moving along with the path of boxes of materials on the conveyor belt by manipulating a motor. The proposed antenna control unit, which is driven by a motor and is located on top of the gate, has an array structure of two antennas with parallel connection. The array structure helps improve the directivity of antenna beam pattern and the readable RFID distance due to its configuration. In the experiments, as the control unit follows moving materials, the reading time has been improved by almost three-fold compared to an RFID system employing conventional fixed antennas. The proposed system also has a recognition rate of over 99% without additional antennas for detecting the sides of a box of materials. The recognition rate meets the conditions recommended by the Electronic Product Code glbal network (EPC)global for commercializing the system, with three antennas at a 20 dBm power of reader and a conveyor belt speed of 3.17 m/s. This will enable a host of new RFID conveyor belt gate systems with increased performance. PMID:22164119

A High-Throughput Processor for Flight Control Research Using Small UAVs

NASA Technical Reports Server (NTRS)

Klenke, Robert H.; Sleeman, W. C., IV; Motter, Mark A.

2006-01-01

There are numerous autopilot systems that are commercially available for small (<100 lbs) UAVs. However, they all share several key disadvantages for conducting aerodynamic research, chief amongst which is the fact that most utilize older, slower, 8- or 16-bit microcontroller technologies. This paper describes the development and testing of a flight control system (FCS) for small UAV s based on a modern, high throughput, embedded processor. In addition, this FCS platform contains user-configurable hardware resources in the form of a Field Programmable Gate Array (FPGA) that can be used to implement custom, application-specific hardware. This hardware can be used to off-load routine tasks such as sensor data collection, from the FCS processor thereby further increasing the computational throughput of the system.

Radiation testing campaign results for understanding the suitability of FPGAs in detector electronics

DOE PAGES

Citterio, M.; Camplani, A.; Cannon, M.; ...

2015-11-19

SRAM based Field Programmable Gate Arrays (FPGAs) have been rarely used in High Energy Physics (HEP) due to their sensitivity to radiation. The last generation of commercial FPGAs based on 28 nm feature size and on Silicon On Insulator (SOI) technologies are more tolerant to radiation to the level that their use in front-end electronics is now feasible. FPGAs provide re-programmability, high-speed computation and fast data transmission through the embedded serial transceivers. They could replace custom application specific integrated circuits in front end electronics in locations with moderate radiation field. Finally, the use of a FPGA in HEP experiments ismore » only limited by our ability to mitigate single event effects induced by the high energy hadrons present in the radiation field.« less

A CDMA system implementation with dimming control for visible light communication

NASA Astrophysics Data System (ADS)

Chen, Danyang; Wang, Jianping; Jin, Jianli; Lu, Huimin; Feng, Lifang

2018-04-01

Visible light communication (VLC), using solid-state lightings to transmit information, has become a complement technology to wireless radio communication. As a realistic multiple access scheme for VLC system, code division multiple access (CDMA) has attracted more and more attentions in recent years. In this paper, we address and implement an improved CDMA scheme for VLC system. The simulation results reveal that the improved CDMA scheme not only supports multi-users' transmission but also maintains dimming value at about 50% and enhances the system efficiency. It can also realize the flexible dimming control by adjusting some parameters of system structure, which rarely affects the system BER performance. A real-time experimental VLC system with improved CDMA scheme is performed based on field programmable gate array (FPGA), reaching a good BER performance.

Next generation agricultural system data, models and knowledge products: Introduction.

PubMed

Antle, John M; Jones, James W; Rosenzweig, Cynthia E

2017-07-01

Agricultural system models have become important tools to provide predictive and assessment capability to a growing array of decision-makers in the private and public sectors. Despite ongoing research and model improvements, many of the agricultural models today are direct descendants of research investments initially made 30-40 years ago, and many of the major advances in data, information and communication technology (ICT) of the past decade have not been fully exploited. The purpose of this Special Issue of Agricultural Systems is to lay the foundation for the next generation of agricultural systems data, models and knowledge products. The Special Issue is based on a "NextGen" study led by the Agricultural Model Intercomparison and Improvement Project (AgMIP) with support from the Bill and Melinda Gates Foundation.

Spacesuit Data Display and Management System

NASA Technical Reports Server (NTRS)

Hall, David G.; Sells, Aaron; Shah, Hemal

2009-01-01

A prototype embedded avionics system has been designed for the next generation of NASA extra-vehicular-activity (EVA) spacesuits. The system performs biomedical and other sensor monitoring, image capture, data display, and data transmission. An existing NASA Phase I and II award winning design for an embedded computing system (ZIN vMetrics - BioWATCH) has been modified. The unit has a reliable, compact form factor with flexible packaging options. These innovations are significant, because current state-of-the-art EVA spacesuits do not provide capability for data displays or embedded data acquisition and management. The Phase 1 effort achieved Technology Readiness Level 4 (high fidelity breadboard demonstration). The breadboard uses a commercial-grade field-programmable gate array (FPGA) with embedded processor core that can be upgraded to a space-rated device for future revisions.

Information storage and retrieval in a single levitating colloidal particle

NASA Astrophysics Data System (ADS)

Myers, Christopher J.; Celebrano, Michele; Krishnan, Madhavi

2015-10-01

The binary switch is a basic component of digital information. From phase-change alloys to nanomechanical beams, molecules and atoms, new strategies for controlled bistability hold great interest for emerging technologies. We present a generic methodology for precise and parallel spatiotemporal control of nanometre-scale matter in a fluid, and demonstrate the ability to attain digital functionalities such as switching, gating and data storage in a single colloid, with further implications for signal amplification and logic operations. This fluid-phase bit can be arrayed at high densities, manipulated by either electrical or optical fields, supports low-energy, high-speed operation and marks a first step toward ‘colloidal information’. The principle generalizes to any system where spatial perturbation of a particle elicits a differential response amenable to readout.

Information storage and retrieval in a single levitating colloidal particle.

PubMed

Myers, Christopher J; Celebrano, Michele; Krishnan, Madhavi

2015-10-01

The binary switch is a basic component of digital information. From phase-change alloys to nanomechanical beams, molecules and atoms, new strategies for controlled bistability hold great interest for emerging technologies. We present a generic methodology for precise and parallel spatiotemporal control of nanometre-scale matter in a fluid, and demonstrate the ability to attain digital functionalities such as switching, gating and data storage in a single colloid, with further implications for signal amplification and logic operations. This fluid-phase bit can be arrayed at high densities, manipulated by either electrical or optical fields, supports low-energy, high-speed operation and marks a first step toward 'colloidal information'. The principle generalizes to any system where spatial perturbation of a particle elicits a differential response amenable to readout.

Data transmission optical link for RF-GUN project

NASA Astrophysics Data System (ADS)

Olowski, Krzysztof; Zielinski, Jerzy; Jalmuzna, Wojciech; Pozniak, Krzysztof; Romaniuk, Ryszard

2005-09-01

Today, the fast optical data transmission is one of the fundamentals of modern distributed control systems. The fibers are widely use as multi-gigabit data stream medium. For a short range transmission, the multimode fibers are in common use. The data rate for this kind of transmission exceeds 10 Gbps for 10 Gigabit Ethernet and 10G Fibre Channel protocols. The Field Programmable Gate Arrays are one of the opportunities of managing the optical transmission. This article is concerning a synchronous optical transmission system via a multimode fiber. The transmission is controlled by the FPGA of two manufacturers: Xilinx and Altera. This paper contains the newest technology overview and market device parameters. It also describes a board for the optical transmission, technical details of the transmission and optical transmission results.

Next Generation Agricultural System Data, Models and Knowledge Products: Introduction

NASA Technical Reports Server (NTRS)

Antle, John M.; Jones, James W.; Rosenzweig, Cynthia E.

2016-01-01

Agricultural system models have become important tools to provide predictive and assessment capability to a growing array of decision-makers in the private and public sectors. Despite ongoing research and model improvements, many of the agricultural models today are direct descendants of research investments initially made 30-40 years ago, and many of the major advances in data, information and communication technology (ICT) of the past decade have not been fully exploited. The purpose of this Special Issue of Agricultural Systems is to lay the foundation for the next generation of agricultural systems data, models and knowledge products. The Special Issue is based on a 'NextGen' study led by the Agricultural Model Intercomparison and Improvement Project (AgMIP) with support from the Bill and Melinda Gates Foundation.

Research on range-gated laser active imaging seeker

NASA Astrophysics Data System (ADS)

You, Mu; Wang, PengHui; Tan, DongJie

2013-09-01

Compared with other imaging methods such as millimeter wave imaging, infrared imaging and visible light imaging, laser imaging provides both a 2-D array of reflected intensity data as well as 2-D array of range data, which is the most important data for use in autonomous target acquisition .In terms of application, it can be widely used in military fields such as radar, guidance and fuse. In this paper, we present a laser active imaging seeker system based on range-gated laser transmitter and sensor technology .The seeker system presented here consist of two important part, one is laser image system, which uses a negative lens to diverge the light from a pulse laser to flood illuminate a target, return light is collected by a camera lens, each laser pulse triggers the camera delay and shutter. The other is stabilization gimbals, which is designed to be a rotatable structure both in azimuth and elevation angles. The laser image system consists of transmitter and receiver. The transmitter is based on diode pumped solid-state lasers that are passively Q-switched at 532nm wavelength. A visible wavelength was chosen because the receiver uses a Gen III image intensifier tube with a spectral sensitivity limited to wavelengths less than 900nm.The receiver is image intensifier tube's micro channel plate coupled into high sensitivity charge coupled device camera. The image has been taken at range over one kilometer and can be taken at much longer range in better weather. Image frame frequency can be changed according to requirement of guidance with modifiable range gate, The instantaneous field of views of the system was found to be 2×2 deg. Since completion of system integration, the seeker system has gone through a series of tests both in the lab and in the outdoor field. Two different kinds of buildings have been chosen as target, which is located at range from 200m up to 1000m.To simulate dynamic process of range change between missile and target, the seeker system has been placed on the truck vehicle running along the road in an expected speed. The test result shows qualified image and good performance of the seeker system.

SEMICONDUCTOR TECHNOLOGY: TaN wet etch for application in dual-metal-gate integration technology

NASA Astrophysics Data System (ADS)

Yongliang, Li; Qiuxia, Xu

2009-12-01

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and Jg-Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.

Automating analog design: Taming the shrew

NASA Technical Reports Server (NTRS)

Barlow, A.

1990-01-01

The pace of progress in the design of integrated circuits continues to amaze observers inside and outside of the industry. Three decades ago, a 50 transistor chip was a technological wonder. Fifteen year later, a 5000 transistor device would 'wow' the crowds. Today, 50,000 transistor chips will earn a 'not too bad' assessment, but it takes 500,000 to really leave an impression. In 1975 a typical ASIC device had 1000 transistors, took one year to first samples (and two years to production) and sold for about 5 cents per transistor. Today's 50,000 transistor gate array takes about 4 months from spec to silicon, works the first time, and sells for about 0.02 cents per transistor. Fifteen years ago, the single most laborious and error prone step in IC design was the physical layout. Today, most IC's never see the hand of a layout designer: and automatic place and route tool converts the engineer's computer captured schematic to a complete physical design using a gate array or a library of standard cells also created by software rather than by designers. CAD has also been a generous benefactor to the digital design process. The architect of today's digital systems creates the design using an RTL or other high level simulator. Then the designer pushes a button to invoke the logic synthesizer-optimizer tool. A fault analyzer checks the result for testability and suggests where scan based cells will improve test coverage. One obstinate holdout amidst this parade of progress is the automation of analog design and its reduction to semi-custom techniques. This paper investigates the application of CAD techniques to analog design.

Engineering integrated photonics for heralded quantum gates

NASA Astrophysics Data System (ADS)

Meany, Thomas; Biggerstaff, Devon N.; Broome, Matthew A.; Fedrizzi, Alessandro; Delanty, Michael; Steel, M. J.; Gilchrist, Alexei; Marshall, Graham D.; White, Andrew G.; Withford, Michael J.

2016-06-01

Scaling up linear-optics quantum computing will require multi-photon gates which are compact, phase-stable, exhibit excellent quantum interference, and have success heralded by the detection of ancillary photons. We investigate the design, fabrication and characterisation of the optimal known gate scheme which meets these requirements: the Knill controlled-Z gate, implemented in integrated laser-written waveguide arrays. We show device performance to be less sensitive to phase variations in the circuit than to small deviations in the coupler reflectivity, which are expected given the tolerance values of the fabrication method. The mode fidelity is also shown to be less sensitive to reflectivity and phase errors than the process fidelity. Our best device achieves a fidelity of 0.931 ± 0.001 with the ideal 4 × 4 unitary circuit and a process fidelity of 0.680 ± 0.005 with the ideal computational-basis process.

Engineering integrated photonics for heralded quantum gates

PubMed Central

Meany, Thomas; Biggerstaff, Devon N.; Broome, Matthew A.; Fedrizzi, Alessandro; Delanty, Michael; Steel, M. J.; Gilchrist, Alexei; Marshall, Graham D.; White, Andrew G.; Withford, Michael J.

2016-01-01

Scaling up linear-optics quantum computing will require multi-photon gates which are compact, phase-stable, exhibit excellent quantum interference, and have success heralded by the detection of ancillary photons. We investigate the design, fabrication and characterisation of the optimal known gate scheme which meets these requirements: the Knill controlled-Z gate, implemented in integrated laser-written waveguide arrays. We show device performance to be less sensitive to phase variations in the circuit than to small deviations in the coupler reflectivity, which are expected given the tolerance values of the fabrication method. The mode fidelity is also shown to be less sensitive to reflectivity and phase errors than the process fidelity. Our best device achieves a fidelity of 0.931 ± 0.001 with the ideal 4 × 4 unitary circuit and a process fidelity of 0.680 ± 0.005 with the ideal computational-basis process. PMID:27282928

Engineering integrated photonics for heralded quantum gates.

PubMed

Meany, Thomas; Biggerstaff, Devon N; Broome, Matthew A; Fedrizzi, Alessandro; Delanty, Michael; Steel, M J; Gilchrist, Alexei; Marshall, Graham D; White, Andrew G; Withford, Michael J

2016-06-10

Scaling up linear-optics quantum computing will require multi-photon gates which are compact, phase-stable, exhibit excellent quantum interference, and have success heralded by the detection of ancillary photons. We investigate the design, fabrication and characterisation of the optimal known gate scheme which meets these requirements: the Knill controlled-Z gate, implemented in integrated laser-written waveguide arrays. We show device performance to be less sensitive to phase variations in the circuit than to small deviations in the coupler reflectivity, which are expected given the tolerance values of the fabrication method. The mode fidelity is also shown to be less sensitive to reflectivity and phase errors than the process fidelity. Our best device achieves a fidelity of 0.931 ± 0.001 with the ideal 4 × 4 unitary circuit and a process fidelity of 0.680 ± 0.005 with the ideal computational-basis process.

High-frequency self-aligned graphene transistors with transferred gate stacks.

PubMed

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-07-17

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra-high-frequency circuits.

Structure-based membrane dome mechanism for Piezo mechanosensitivity

PubMed Central

Guo, Yusong R

2017-01-01

Mechanosensitive ion channels convert external mechanical stimuli into electrochemical signals for critical processes including touch sensation, balance, and cardiovascular regulation. The best understood mechanosensitive channel, MscL, opens a wide pore, which accounts for mechanosensitive gating due to in-plane area expansion. Eukaryotic Piezo channels have a narrow pore and therefore must capture mechanical forces to control gating in another way. We present a cryo-EM structure of mouse Piezo1 in a closed conformation at 3.7Å-resolution. The channel is a triskelion with arms consisting of repeated arrays of 4-TM structural units surrounding a pore. Its shape deforms the membrane locally into a dome. We present a hypothesis in which the membrane deformation changes upon channel opening. Quantitatively, membrane tension will alter gating energetics in proportion to the change in projected area under the dome. This mechanism can account for highly sensitive mechanical gating in the setting of a narrow, cation-selective pore. PMID:29231809

Nearly deterministic quantum Fredkin gate based on weak cross-Kerr nonlinearity

NASA Astrophysics Data System (ADS)

Wu, Yun-xiang; Zhu, Chang-hua; Pei, Chang-xing

2016-09-01

A scheme of an optical quantum Fredkin gate is presented based on weak cross-Kerr nonlinearity. By an auxiliary coherent state with the cross-Kerr nonlinearity effect, photons can interact with each other indirectly, and a non-demolition measurement for photons can be implemented. Combined with the homodyne detection, classical feedforward, polarization beam splitters and Pauli-X operations, a controlled-path gate is constructed. Furthermore, a quantum Fredkin gate is built based on the controlled-path gate. The proposed Fredkin gate is simple in structure and feasible by current experimental technology.

Risk Reduction for Use of Complex Devices in Space Projects

NASA Technical Reports Server (NTRS)

Berg, Melanie; Poivey, Christian; Friendlich, Mark; Petrick, Dave; LaBel, Kenneth; Stansberry, Scott

2007-01-01

We present guidel!nes to reduce risk to an acceptable level when using complex devices in space applications. Application to Virtex 4 Field Programmable Gate Array (FPGA) on Express Logistic Carrier (ELC) project is presented.

Integrated all-optical programmable logic array based on semiconductor optical amplifiers.

PubMed

Dong, Wenchan; Huang, Zhuyang; Hou, Jie; Santos, Rui; Zhang, Xinliang

2018-05-01

The all-optical programmable logic array (PLA) is one of the most important optical complex logic devices that can implement combinational logic functions. In this Letter, we propose and experimentally demonstrate an integrated all-optical PLA at the operation speed of 40 Gb/s. The PLA mainly consists of a delay interferometer (DI) and semiconductor optical amplifiers (SOAs) of different lengths. The DI is used to pre-code the input signals and improve the reconfigurability of the scheme. The longer SOAs are nonlinear media for generating canonical logic units (CLUs) using four-wave mixing. The shorter SOAs are used to select the appropriate CLUs by changing the working states; then reconfigurable logic functions can be output directly. The results show that all the CLUs are realized successfully, and the optical signal-to-noise ratios are above 22 dB. The exclusive NOR gate and exclusive OR gate are experimentally demonstrated based on output CLUs.

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement

PubMed Central

Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

2016-01-01

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates. PMID:26763827

A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device

NASA Astrophysics Data System (ADS)

Szplet, R.; Kalisz, J.; Jachna, Z.

2009-02-01

We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizer's transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second.

A field programmable gate array unit for the diagnosis and control of neoclassical tearing modes on MAST

DOE Office of Scientific and Technical Information (OSTI.GOV)

O'Gorman, T.; Gibson, K. J.; Snape, J. A.

2012-10-15

A real-time system has been developed to trigger both the MAST Thomson scattering (TS) system and the plasma control system on the phase and amplitude of neoclassical tearing modes (NTMs), extending the capabilities of the original system. This triggering system determines the phase and amplitude of a given NTM using magnetic coils at different toroidal locations. Real-time processing of the raw magnetic data occurs on a low cost field programmable gate array (FPGA) based unit which permits triggering of the TS lasers on specific amplitudes and phases of NTM evolution. The MAST plasma control system can receive a separate triggermore » from the FPGA unit that initiates a vertical shift of the MAST magnetic axis. Such shifts have fully removed m/n= 2/1 NTMs instabilities on a number of MAST discharges.« less

Magnetic gates and guides for superconducting vortices

DOE PAGES

Vlasko-Vlasov, V. K.; Colauto, F.; Buzdin, A. I.; ...

2017-04-04

Here, we image the motion of superconducting vortices in niobium film covered with a regular array of thin permalloy stripes. By altering the magnetization orientation in the stripes using a small in-plane magnetic field, we can tune the strength of interactions between vortices and the stripe edges, enabling acceleration or retardation of the superconducting vortices in the sample and consequently introducing strong tunable anisotropy into the vortex dynamics. We discuss our observations in terms of the attraction/repulsion between point magnetic charges carried by vortices and lines of magnetic charges at the stripe edges, and derive analytical formulas for the vortex-magneticmore » stripes coupling. Our approach demonstrates the analogy between the vortex motion regulated by the magnetic stripe array and electric carrier flow in gated semiconducting devices. Scaling down the geometrical features of the proposed design may enable controlled manipulation of single vortices, paving the way for Abrikosov vortex microcircuits and memories.« less

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement.

PubMed

Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

2016-01-01

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates.

Single and pair-wise manipulation of atoms in a 3D optical lattice

NASA Astrophysics Data System (ADS)

Corcovilos, Theodore; Wang, Yang; Weiss, David

2013-05-01

We describe the hardware used in a quantum computing experiment using individual Cs atoms in a 5 μm -spaced 3D optical lattice as qubits. Far-off-resonance addressing beams can be steered to any site in the array using MEMS mirrors within 10 μs , allowing the translation of individual atoms between lattice sites, for example to remove vacancies in the atom array, and the manipulation of single atoms for single qubit gates in < 100 μs . Two-qubit gates on adjacent atoms can be performed via the Rydberg blockade mechanism using a second MEMS system and high-NA imaging objective. The lasers for the Rydberg excitation are built using a new extended cavity diode laser design utilizing an interference filter as the frequency selecting element following Baillard, et al. (Opt. Comm. 266: 609 (2009)), but using commercially available components. We gratefully acknowledge funding from ARO and DARPA.

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

NASA Astrophysics Data System (ADS)

Wang, Yonggang; Kuang, Jie; Liu, Chong; Cao, Qiang; Li, Deng

2017-03-01

A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9 ps time-interval RMS precision, 16 TDC channels with 6.9 ps RMS precision, or 8 TDC channels with 5.8 ps RMS precision. All TDCs have a 380 M Samples/second measurement throughput and a 2.63 ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28 nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

Magnetic gates and guides for superconducting vortices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vlasko-Vlasov, V. K.; Colauto, F.; Buzdin, A. I.

Here, we image the motion of superconducting vortices in niobium film covered with a regular array of thin permalloy stripes. By altering the magnetization orientation in the stripes using a small in-plane magnetic field, we can tune the strength of interactions between vortices and the stripe edges, enabling acceleration or retardation of the superconducting vortices in the sample and consequently introducing strong tunable anisotropy into the vortex dynamics. We discuss our observations in terms of the attraction/repulsion between point magnetic charges carried by vortices and lines of magnetic charges at the stripe edges, and derive analytical formulas for the vortex-magneticmore » stripes coupling. Our approach demonstrates the analogy between the vortex motion regulated by the magnetic stripe array and electric carrier flow in gated semiconducting devices. Scaling down the geometrical features of the proposed design may enable controlled manipulation of single vortices, paving the way for Abrikosov vortex microcircuits and memories.« less

Field Programmable Gate Array for Implementation of Redundant Advanced Digital Feedback Control

NASA Technical Reports Server (NTRS)

King, K. D.

2003-01-01

The goal of this effort was to develop a digital motor controller using field programmable gate arrays (FPGAs). This is a more rugged approach than a conventional microprocessor digital controller. FPGAs typically have higher radiation (rad) tolerance than both the microprocessor and memory required for a conventional digital controller. Furthermore, FPGAs can typically operate at higher speeds. (While speed is usually not an issue for motor controllers, it can be for other system controllers.) Other than motor power, only a 3.3-V digital power supply was used in the controller; no analog bias supplies were used. Since most of the circuit was implemented in the FPGA, no additional parts were needed other than the power transistors to drive the motor. The benefits that FPGAs provide over conventional designs-lower power and fewer parts-allow for smaller packaging and reduced weight and cost.

An acceleration framework for synthetic aperture radar algorithms

NASA Astrophysics Data System (ADS)

Kim, Youngsoo; Gloster, Clay S.; Alexander, Winser E.

2017-04-01

Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, Field Programmable Gate Arrays (FPGAs) can be used to accelerate these kernels using hardware-based custom logic implementations. In this paper, we demonstrate a framework for algorithm acceleration. We used SAR as a case study to illustrate the potential for algorithm acceleration offered by FPGAs. Initially, we profiled the SAR algorithm and implemented a homomorphic filter using a hardware implementation of the natural logarithm. Experimental results show a linear speedup by adding reasonably small processing elements in Field Programmable Gate Array (FPGA) as opposed to using a software implementation running on a typical general purpose processor.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jermoumi, M; Cao, D; Housley, D

Purpose: In this study, we evaluated the performance of an Elekta linac in the delivery of gated radiotherapy. We examined whether the use of either a short gating window or a long beam hold impacts the accuracy of the delivery Methods: The performance of an Elekta linac in the delivery of gated radiotherapy was assessed using a 20cmX 20cm open field with the radiation delivered using a range of beam-on and beam-off time periods. Two SBRT plans were used to examine the accuracy of gated beam delivery for clinical treatment plans. For the SBRT cases, tests were performed for bothmore » free-breathing based gating and for gated delivery with a simulated breath-hold. A MatriXX 2D ion chamber array was used for data collection, and the gating accuracy was evaluated using gamma score. Results: For the 20cmX20cm open field, the gated beam delivery agreed closely with the non-gated delivery results. Discrepancies in the agreement, however, began to appear with a 5-to-1 ratio of the beam-off to beam-on. For these tight gating windows, each beam-on segment delivered a small number of monitor units. This finding was confirmed with dose distribution analysis from the delivery of the two VMAT plans where the gamma score(±1%,2%/1mm) showed passing rates in the range of 95% to 100% for gating windows of 25%, 38%, 50%, 63%, 75%, and 83%. Using a simulated sinusoidal breathing signal with a 4 second period, the gamma score of freebreathing gating and breath-hold gating deliveries were measured in the range of 95.7% to 100%. Conclusion: The results demonstrate that Elekta linacs can be used to accurately deliver respiratory gated treatments for both free-breathing and breath-hold patients. The accuracy of beams delivered in a gated delivery mode at low small MU proved higher than similar deliveries performed in a non-gated (manually interrupted) fashion.« less

Controller for the Electronically Scanned Thinned Array Radiometer (ESTAR) instrument

NASA Technical Reports Server (NTRS)

Zomberg, Brian G.; Chren, William A., Jr.

1994-01-01

A prototype controller for the ESTAR (electronically scanned thinned array radiometer) instrument has been designed and tested. It manages the operation of the digital data subsystem (DDS) and its communication with the Small Explorer data system (SEDS). Among the data processing tasks that it coordinates are FEM data acquisition, noise removal, phase alignment and correlation. Its control functions include instrument calibration and testing of two critical subsystems, the output data formatter and Walsh function generator. It is implemented in a Xilinx XC3064PC84-100 field programmable gate array (FPGA) and has a maximum clocking frequency of 10 MHz.

Simple method for assembly of CRISPR synergistic activation mediator gRNA expression array.

PubMed

Vad-Nielsen, Johan; Nielsen, Anders Lade; Luo, Yonglun

2018-05-20

When studying complex interconnected regulatory networks, effective methods for simultaneously manipulating multiple genes expression are paramount. Previously, we have developed a simple method for generation of an all-in-one CRISPR gRNA expression array. We here present a Golden Gate Assembly-based system of synergistic activation mediator (SAM) compatible CRISPR/dCas9 gRNA expression array for the simultaneous activation of multiple genes. Using this system, we demonstrated the simultaneous activation of the transcription factors, TWIST, SNAIL, SLUG, and ZEB1 a human breast cancer cell line. Copyright © 2018 Elsevier B.V. All rights reserved.

Many-body strategies for multiqubit gates: Quantum control through Krawtchouk-chain dynamics

NASA Astrophysics Data System (ADS)

Groenland, Koen; Schoutens, Kareljan

2018-04-01

We propose a strategy for engineering multiqubit quantum gates. As a first step, it employs an eigengate to map states in the computational basis to eigenstates of a suitable many-body Hamiltonian. The second step employs resonant driving to enforce a transition between a single pair of eigenstates, leaving all others unchanged. The procedure is completed by mapping back to the computational basis. We demonstrate the strategy for the case of a linear array with an even number N of qubits, with specific X X +Y Y couplings between nearest neighbors. For this so-called Krawtchouk chain, a two-body driving term leads to the iSWAPN gate, which we numerically test for N =4 and 6.

Technical Note: Evaluation of the latency and the beam characteristics of a respiratory gating system using an Elekta linear accelerator and a respiratory indicator device, Abches.

PubMed

Saito, Masahide; Sano, Naoki; Ueda, Koji; Shibata, Yuki; Kuriyama, Kengo; Komiyama, Takafumi; Marino, Kan; Aoki, Shinichi; Onishi, Hiroshi

2018-01-01

To evaluate the basic performance of a respiratory gating system using an Elekta linac and an Abches respiratory-monitoring device. The gating system was comprised of an Elekta Synergy linac equipped with a Response TM gating interface module and an Abches respiratory-monitoring device. The latencies from a reference respiratory signal to the resulting Abches gating output signal and the resulting monitor-ion-chamber output signal were measured. Then, the flatness and symmetry of the gated beams were measured using a two-dimensional ionization chamber array for fixed and arc beams, respectively. Furthermore, the beam quality, TPR 20,10 , and the output of the fixed gated beams were also measured using a Farmer chamber. Each of the beam characteristics was compared with each of those for nongated irradiation. The full latencies at beam-on and beam-off for 6-MV gated beams were 336.4 ± 23.4 ms and 87.6 ± 7.1 ms, respectively. The differences in flatness between the gated and nongated beams were within 0.91% and 0.87% for the gun-target and left-right directions, respectively. In the same manner, the beam symmetries were within 0.68% and 0.82%, respectively. The percentage differences in beam quality and beam output were below 1% for a beam-on time range of 1.1-7 s. The latency of the Elekta gating system combined with Abches was found to be acceptable using our measurement method. Furthermore, we demonstrated that the beam characteristics of the gating system using our respiratory indicator were comparable with the nongated beams for a single-arc gated beam delivery. © 2017 American Association of Physicists in Medicine.

Repeatable, accurate, and high speed multi-level programming of memristor 1T1R arrays for power efficient analog computing applications.

PubMed

Merced-Grafals, Emmanuelle J; Dávila, Noraica; Ge, Ning; Williams, R Stanley; Strachan, John Paul

2016-09-09

Beyond use as high density non-volatile memories, memristors have potential as synaptic components of neuromorphic systems. We investigated the suitability of tantalum oxide (TaOx) transistor-memristor (1T1R) arrays for such applications, particularly the ability to accurately, repeatedly, and rapidly reach arbitrary conductance states. Programming is performed by applying an adaptive pulsed algorithm that utilizes the transistor gate voltage to control the SET switching operation and increase programming speed of the 1T1R cells. We show the capability of programming 64 conductance levels with <0.5% average accuracy using 100 ns pulses and studied the trade-offs between programming speed and programming error. The algorithm is also utilized to program 16 conductance levels on a population of cells in the 1T1R array showing robustness to cell-to-cell variability. In general, the proposed algorithm results in approximately 10× improvement in programming speed over standard algorithms that do not use the transistor gate to control memristor switching. In addition, after only two programming pulses (an initialization pulse followed by a programming pulse), the resulting conductance values are within 12% of the target values in all cases. Finally, endurance of more than 10(6) cycles is shown through open-loop (single pulses) programming across multiple conductance levels using the optimized gate voltage of the transistor. These results are relevant for applications that require high speed, accurate, and repeatable programming of the cells such as in neural networks and analog data processing.

Graduate Automotive Technology Education (GATE) Program: Center of Automotive Technology Excellence in Advanced Hybrid Vehicle Technology at West Virginia University

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nigle N. Clark

2006-12-31

This report summarizes the technical and educational achievements of the Graduate Automotive Technology Education (GATE) Center at West Virginia University (WVU), which was created to emphasize Advanced Hybrid Vehicle Technology. The Center has supported the graduate studies of 17 students in the Department of Mechanical and Aerospace Engineering and the Lane Department of Computer Science and Electrical Engineering. These students have addressed topics such as hybrid modeling, construction of a hybrid sport utility vehicle (in conjunction with the FutureTruck program), a MEMS-based sensor, on-board data acquisition for hybrid design optimization, linear engine design and engine emissions. Courses have been developedmore » in Hybrid Vehicle Design, Mobile Source Powerplants, Advanced Vehicle Propulsion, Power Electronics for Automotive Applications and Sensors for Automotive Applications, and have been responsible for 396 hours of graduate student coursework. The GATE program also enhanced the WVU participation in the U.S. Department of Energy Student Design Competitions, in particular FutureTruck and Challenge X. The GATE support for hybrid vehicle technology enhanced understanding of hybrid vehicle design and testing at WVU and encouraged the development of a research agenda in heavy-duty hybrid vehicles. As a result, WVU has now completed three programs in hybrid transit bus emissions characterization, and WVU faculty are leading the Transportation Research Board effort to define life cycle costs for hybrid transit buses. Research and enrollment records show that approximately 100 graduate students have benefited substantially from the hybrid vehicle GATE program at WVU.« less

High-κ/Metal Gate Science and Technology

NASA Astrophysics Data System (ADS)

Guha, Supratik; Narayanan, Vijay

2009-08-01

High-κ/metal gate technology is on the verge of replacing conventional oxynitride dielectrics in state-of-the-art transistors for both high-performance and low-power applications. In this review we discuss some of the key materials issues that complicated the introduction of high-κ dielectrics, including reduced electron mobility, oxygen-based thermal instabilities, and the absence of thermally stable dual-metal electrodes. We show that through a combination of materials innovations and engineering ingenuity these issues were successfully overcome, thereby paving the way for high-κ/metal gate implementation.

Dynamically Reconfigurable Systolic Array Accelerator

NASA Technical Reports Server (NTRS)

Dasu, Aravind; Barnes, Robert

2012-01-01

A polymorphic systolic array framework has been developed that works in conjunction with an embedded microprocessor on a field-programmable gate array (FPGA), which allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and a hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms, and is extendable to more complex applications in the area of aerospace embedded systems. FPGA chips can be responsive to realtime demands for changing applications needs, but only if the electronic fabric can respond fast enough. This systolic array framework allows for rapid partial and dynamic reconfiguration of the chip in response to the real-time needs of scalability, and adaptability of executables.

Radiation and Scattering Compact Antenna Laboratory (RASCAL) Capabilities Brochure

DTIC Science & Technology

2016-09-06

Array Measurements Integrated Measurement of Subsystems with Digital Backends RADIATION AND SCATTERING COMPACT ANTENNA LABORATORY...hardware gating to eliminate sources of error within the range itself. Processing is also available for multi-arm spiral antennas for the generation

A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications

NASA Astrophysics Data System (ADS)

Liu, Chunsen; Yan, Xiao; Song, Xiongfei; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2018-05-01

As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 106 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

Integrated photonic quantum gates for polarization qubits.

PubMed

Crespi, Andrea; Ramponi, Roberta; Osellame, Roberto; Sansoni, Linda; Bongioanni, Irene; Sciarrino, Fabio; Vallone, Giuseppe; Mataloni, Paolo

2011-11-29

The ability to manipulate quantum states of light by integrated devices may open new perspectives both for fundamental tests of quantum mechanics and for novel technological applications. However, the technology for handling polarization-encoded qubits, the most commonly adopted approach, is still missing in quantum optical circuits. Here we demonstrate the first integrated photonic controlled-NOT (CNOT) gate for polarization-encoded qubits. This result has been enabled by the integration, based on femtosecond laser waveguide writing, of partially polarizing beam splitters on a glass chip. We characterize the logical truth table of the quantum gate demonstrating its high fidelity to the expected one. In addition, we show the ability of this gate to transform separable states into entangled ones and vice versa. Finally, the full accessibility of our device is exploited to carry out a complete characterization of the CNOT gate through a quantum process tomography.

Sequence information signal processor for local and global string comparisons

DOEpatents

Peterson, John C.; Chow, Edward T.; Waterman, Michael S.; Hunkapillar, Timothy J.

1997-01-01

A sequence information signal processing integrated circuit chip designed to perform high speed calculation of a dynamic programming algorithm based upon the algorithm defined by Waterman and Smith. The signal processing chip of the present invention is designed to be a building block of a linear systolic array, the performance of which can be increased by connecting additional sequence information signal processing chips to the array. The chip provides a high speed, low cost linear array processor that can locate highly similar global sequences or segments thereof such as contiguous subsequences from two different DNA or protein sequences. The chip is implemented in a preferred embodiment using CMOS VLSI technology to provide the equivalent of about 400,000 transistors or 100,000 gates. Each chip provides 16 processing elements, and is designed to provide 16 bit, two's compliment operation for maximum score precision of between -32,768 and +32,767. It is designed to provide a comparison between sequences as long as 4,194,304 elements without external software and between sequences of unlimited numbers of elements with the aid of external software. Each sequence can be assigned different deletion and insertion weight functions. Each processor is provided with a similarity measure device which is independently variable. Thus, each processor can contribute to maximum value score calculation using a different similarity measure.

Space-charge-limited solid-state triode

NASA Technical Reports Server (NTRS)

Shumka, A. (Inventor)

1975-01-01

A solid-state triode is provided from a wafer of nearinstrinsic semiconductor material sliced into filaments of rectangular cross section. Before slicing, emitter and collector regions are formed on the narrow sides of the filaments, and after slicing gate regions are formed in arrow strips extending longitudinally along the midsections of the wide sides of the filaments. Contacts are then formed on the emitter, collector and gate regions of each filament individually for a single filament device, or in parallel for an array of filament devices to increase load current.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1977-01-01

Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.

A high performance cost-effective digital complex correlator for an X-band polarimetry survey.

PubMed

Bergano, Miguel; Rocha, Armando; Cupido, Luís; Barbosa, Domingos; Villela, Thyrso; Boas, José Vilas; Rocha, Graça; Smoot, George F

2016-01-01

The detailed knowledge of the Milky Way radio emission is important to characterize galactic foregrounds masking extragalactic and cosmological signals. The update of the global sky models describing radio emissions over a very large spectral band requires high sensitivity experiments capable of observing large sky areas with long integration times. Here, we present the design of a new 10 GHz (X-band) polarimeter digital back-end to map the polarization components of the galactic synchrotron radiation field of the Northern Hemisphere sky. The design follows the digital processing trends in radio astronomy and implements a large bandwidth (1 GHz) digital complex cross-correlator to extract the Stokes parameters of the incoming synchrotron radiation field. The hardware constraints cover the implemented VLSI hardware description language code and the preliminary results. The implementation is based on the simultaneous digitized acquisition of the Cartesian components of the two linear receiver polarization channels. The design strategy involves a double data rate acquisition of the ADC interleaved parallel bus, and field programmable gate array device programming at the register transfer mode. The digital core of the back-end is capable of processing 32 Gbps and is built around an Altera field programmable gate array clocked at 250 MHz, 1 GSps analog to digital converters and a clock generator. The control of the field programmable gate array internal signal delays and a convenient use of its phase locked loops provide the timing requirements to achieve the target bandwidths and sensitivity. This solution is convenient for radio astronomy experiments requiring large bandwidth, high functionality, high volume availability and low cost. Of particular interest, this correlator was developed for the Galactic Emission Mapping project and is suitable for large sky area polarization continuum surveys. The solutions may also be adapted to be used at signal processing subsystem levels for large projects like the square kilometer array testbeds.

Penn State DOE GATE Program

DOE Office of Scientific and Technical Information (OSTI.GOV)

Anstrom, Joel

2012-08-31

The Graduate Automotive Technology Education (GATE) Program at The Pennsylvania State University (Penn State) was established in October 1998 pursuant to an award from the U.S. Department of Energy (U.S. DOE). The focus area of the Penn State GATE Program is advanced energy storage systems for electric and hybrid vehicles.

Toward Scalable Ion Traps for Quantum Information Processing

DTIC Science & Technology

2010-01-01

3/033031 Abstract. In this paper, we report the design, fabrication and preliminary testing of a 150 zone ion trap array built in a ‘ surface ...gates [4–6]. We report here on the design, fabrication and preliminary testing of a large array built in a ‘ surface -electrode’ geometry [7, 8] and...report the first transport of atomic ions through a surface -electrode trap junction. Transport of ions through a junction has been demonstrated previously

Channel Temperature Determination for AlGaN/GaN HEMTs on SiC and Sapphire

NASA Technical Reports Server (NTRS)

Freeman, Jon C.; Mueller, Wolfgang

2008-01-01

Numerical simulation results (with emphasis on channel temperature) for a single gate AlGaN/GaN High Electron Mobility Transistor (HEMT) with either a sapphire or SiC substrate are presented. The static I-V characteristics, with concomitant channel temperatures (T(sub ch)) are calculated using the software package ATLAS, from Silvaco, Inc. An in-depth study of analytical (and previous numerical) methods for the determination of T(sub ch) in both single and multiple gate devices is also included. We develop a method for calculating T(sub ch) for the single gate device with the temperature dependence of the thermal conductivity of all material layers included. We also present a new method for determining the temperature on each gate in a multi-gate array. These models are compared with experimental results, and show good agreement. We demonstrate that one may obtain the channel temperature within an accuracy of +/-10 C in some cases. Comparisons between different approaches are given to show the limits, sensitivities, and needed approximations, for reasonable agreement with measurements.

Development of optics with micro-LED arrays for improved opto-electronic neural stimulation

NASA Astrophysics Data System (ADS)

Chaudet, Lionel; Neil, Mark; Degenaar, Patrick; Mehran, Kamyar; Berlinguer-Palmini, Rolando; Corbet, Brian; Maaskant, Pleun; Rogerson, David; Lanigan, Peter; Bamberg, Ernst; Roska, Botond

2013-03-01

The breakthrough discovery of a nanoscale optically gated ion channel protein, Channelrhodopsin 2 (ChR2), and its combination with a genetically expressed ion pump, Halorhodopsin, allowed the direct stimulation and inhibition of individual action potentials with light alone. This work reports developments of ultra-bright elec­ tronically controlled optical array sources with enhanced light gated ion channels and pumps for use in systems to further our understanding of both brain and visual function. This work is undertaken as part of the European project, OptoNeuro. Micro-LED arrays permit spatio-temporal control of neuron stimulation on sub-millisecond timescales. However they are disadvantaged by their broad spatial light emission distribution and low fill factor. We present the design and implementation of a projection and micro-optics system for use with a micro-LED array consisting of a 16x16 matrix of 25 μm diameter micro-LEDs with 150 μm centre-to-centre spacing and an emission spectrum centred at 470 nm overlapping the peak sensitivity of ChR2 and its testing on biological samples. The projection system images the micro-LED array onto micro-optics to improve the fill-factor from ~2% to more than 78% by capturing a larger fraction of the LED emission and directing it correctly to the sample plane. This approach allows low fill factor arrays to be used effectively, which in turn has benefits in terms of thermal management and electrical drive from CMOS backplane electronics. The entire projection system is integrated into a microscope prototype to provide stimulation spots at the same size as the neuron cell body (μ10 pm).

Size dependence in tunneling spectra of PbSe quantum-dot arrays.

PubMed

Ou, Y C; Cheng, S F; Jian, W B

2009-07-15

Interdot Coulomb interactions and collective Coulomb blockade were theoretically argued to be a newly important topic, and experimentally identified in semiconductor quantum dots, formed in the gate confined two-dimensional electron gas system. Developments of cluster science and colloidal synthesis accelerated the studies of electron transport in colloidal nanocrystal or quantum-dot solids. To study the interdot coupling, various sizes of two-dimensional arrays of colloidal PbSe quantum dots are self-assembled on flat gold surfaces for scanning tunneling microscopy and scanning tunneling spectroscopy measurements at both room and liquid-nitrogen temperatures. The tip-to-array, array-to-substrate, and interdot capacitances are evaluated and the tunneling spectra of quantum-dot arrays are analyzed by the theory of collective Coulomb blockade. The current-voltage of PbSe quantum-dot arrays conforms properly to a scaling power law function. In this study, the dependence of tunneling spectra on the sizes (numbers of quantum dots) of arrays is reported and the capacitive coupling between quantum dots in the arrays is explored.

New Developments in Error Detection and Correction Strategies for Critical Applications

NASA Technical Reports Server (NTRS)

Berg, Melanie; Label, Ken

2017-01-01

The presentation will cover a variety of mitigation strategies that were developed for critical applications. An emphasis is placed on strengths and weaknesses per mitigation technique as it pertains to different Field programmable gate array (FPGA) device types.

Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure

PubMed Central

Khan, Z. N.; Ahmed, S.; Ali, M.

2016-01-01

Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application. PMID:27571412

Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

PubMed Central

Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M.; Avila-García, Alejandro; Vazquez-Acosta, E. N.; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

2010-01-01

Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

A multimode electromechanical parametric resonator array

PubMed Central

Mahboob, I.; Mounaix, M.; Nishiguchi, K.; Fujiwara, A.; Yamaguchi, H.

2014-01-01

Electromechanical resonators have emerged as a versatile platform in which detectors with unprecedented sensitivities and quantum mechanics in a macroscopic context can be developed. These schemes invariably utilise a single resonator but increasingly the concept of an array of electromechanical resonators is promising a wealth of new possibilities. In spite of this, experimental realisations of such arrays have remained scarce due to the formidable challenges involved in their fabrication. In a variation to this approach, we identify 75 harmonic vibration modes in a single electromechanical resonator of which 7 can also be parametrically excited. The parametrically resonating modes exhibit vibrations with only 2 oscillation phases which are used to build a binary information array. We exploit this array to execute a mechanical byte memory, a shift-register and a controlled-NOT gate thus vividly illustrating the availability and functionality of an electromechanical resonator array by simply utilising higher order vibration modes. PMID:24658349

An Ultrasonic Multiple-Access Ranging Core Based on Frequency Shift Keying Towards Indoor Localization

PubMed Central

Segers, Laurent; Van Bavegem, David; De Winne, Sam; Braeken, An; Touhafi, Abdellah; Steenhaut, Kris

2015-01-01

This paper describes a new approach and implementation methodology for indoor ranging based on the time difference of arrival using code division multiple access with ultrasound signals. A novel implementation based on a field programmable gate array using finite impulse response filters and an optimized correlation demodulator implementation for ultrasound orthogonal signals is developed. Orthogonal codes are modulated onto ultrasound signals using frequency shift keying with carrier frequencies of 24.5 kHz and 26 kHz. This implementation enhances the possibilities for real-time, embedded and low-power tracking of several simultaneous transmitters. Due to the high degree of parallelism offered by field programmable gate arrays, up to four transmitters can be tracked simultaneously. The implementation requires at most 30% of the available logic gates of a Spartan-6 XC6SLX45 device and is evaluated on accuracy and precision through several ranging topologies. In the first topology, the distance between one transmitter and one receiver is evaluated. Afterwards, ranging analyses are applied between two simultaneous transmitters and one receiver. Ultimately, the position of the receiver against four transmitters using trilateration is also demonstrated. Results show enhanced distance measurements with distances ranging from a few centimeters up to 17 m, while keeping a centimeter-level accuracy. PMID:26263986

Room-temperature InP/InAsP Quantum Discs-in-Nanowire Infrared Photodetectors.

PubMed

Karimi, Mohammad; Jain, Vishal; Heurlin, Magnus; Nowzari, Ali; Hussain, Laiq; Lindgren, David; Stehr, Jan Eric; Buyanova, Irina A; Gustafsson, Anders; Samuelson, Lars; Borgström, Magnus T; Pettersson, Håkan

2017-06-14

The possibility to engineer nanowire heterostructures with large bandgap variations is particularly interesting for technologically important broadband photodetector applications. Here we report on a combined study of design, fabrication, and optoelectronic properties of infrared photodetectors comprising four million n + -i-n + InP nanowires periodically ordered in arrays. The nanowires were grown by metal-organic vapor phase epitaxy on InP substrates, with either a single or 20 InAsP quantum discs embedded in the i-segment. By Zn compensation of the residual n-dopants in the i-segment, the room-temperature dark current is strongly suppressed to a level of pA/NW at 1 V bias. The low dark current is manifested in the spectrally resolved photocurrent measurements, which reveal strong photocurrent contributions from the InAsP quantum discs at room temperature with a threshold wavelength of about 2.0 μm and a bias-tunable responsivity reaching 7 A/W@1.38 μm at 2 V bias. Two different processing schemes were implemented to study the effects of radial self-gating in the nanowires induced by the nanowire/SiO x /ITO wrap-gate geometry. Summarized, our results show that properly designed axial InP/InAsP nanowire heterostructures are promising candidates for broadband photodetectors.

The future of automation for high-volume wafer fabrication and ASIC manufacturing

NASA Astrophysics Data System (ADS)

Hughes, Randall A.; Shott, John D.

1986-12-01

A framework is given to analyze the future trends in semiconductor manufacturing automation systems, focusing specifically on the needs of ASIC (application-specific integrated circuit) or custom integrated circuit manufacturing. Advances in technologies such as gate arrays and standard cells now make it significantly easier to obtain system cost and performance advantages by integrating nonstandard functions on silicon. ASICs are attractive to U.S. manufacturers because they place a premium on sophisticated design tools, familiarity with customer needs and applications, and fast turn-around fabrication. These are areas where U.S. manufacturers believe they have an advantage and, consequently, will not suffer from the severe price/manufacturing competition encountered in conventional high-volume semiconductor products. Previously, automation was often considered viable only for high-volume manufacturing, but automation becomes a necessity in the new ASIC environment.

Compute Element and Interface Box for the Hazard Detection System

NASA Technical Reports Server (NTRS)

Villalpando, Carlos Y.; Khanoyan, Garen; Stern, Ryan A.; Some, Raphael R.; Bailey, Erik S.; Carson, John M.; Vaughan, Geoffrey M.; Werner, Robert A.; Salomon, Phil M.; Martin, Keith E.;

Pre-Hardware Optimization of Spacecraft Image Processing Algorithms and Hardware Implementation

NASA Technical Reports Server (NTRS)

Kizhner, Semion; Petrick, David J.; Flatley, Thomas P.; Hestnes, Phyllis; Jentoft-Nilsen, Marit; Day, John H. (Technical Monitor)

2002-01-01

Spacecraft telemetry rates and telemetry product complexity have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image data processing and color picture generation application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The proposed solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms, and reconfigurable computing hardware (RC) technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processors (DSP). It has been shown that this approach can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft.

Radiation Mitigation and Power Optimization Design Tools for Reconfigurable Hardware in Orbit

NASA Technical Reports Server (NTRS)

French, Matthew; Graham, Paul; Wirthlin, Michael; Wang, Li; Larchev, Gregory

2005-01-01

The Reconfigurable Hardware in Orbit (RHinO)project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. In the second year of the project, design tools that leverage an established FPGA design environment have been created to visualize and analyze an FPGA circuit for radiation weaknesses and power inefficiencies. For radiation, a single event Upset (SEU) emulator, persistence analysis tool, and a half-latch removal tool for Xilinx/Virtex-II devices have been created. Research is underway on a persistence mitigation tool and multiple bit upsets (MBU) studies. For power, synthesis level dynamic power visualization and analysis tools have been completed. Power optimization tools are under development and preliminary test results are positive.

Auto-converging stereo cameras for 3D robotic tele-operation

NASA Astrophysics Data System (ADS)

Edmondson, Richard; Aycock, Todd; Chenault, David

2012-06-01

Polaris Sensor Technologies has developed a Stereovision Upgrade Kit for TALON robot to provide enhanced depth perception to the operator. This kit previously required the TALON Operator Control Unit to be equipped with the optional touchscreen interface to allow for operator control of the camera convergence angle adjustment. This adjustment allowed for optimal camera convergence independent of the distance from the camera to the object being viewed. Polaris has recently improved the performance of the stereo camera by implementing an Automatic Convergence algorithm in a field programmable gate array in the camera assembly. This algorithm uses scene content to automatically adjust the camera convergence angle, freeing the operator to focus on the task rather than adjustment of the vision system. The autoconvergence capability has been demonstrated on both visible zoom cameras and longwave infrared microbolometer stereo pairs.

Maturing CCD Photon-Counting Technology for Space Flight

NASA Technical Reports Server (NTRS)

Mallik, Udayan; Lyon, Richard; Petrone, Peter; McElwain, Michael; Benford, Dominic; Clampin, Mark; Hicks, Brian

2015-01-01

This paper discusses charge blooming and starlight saturation - two potential technical problems - when using an Electron Multiplying Charge Coupled Device (EMCCD) type detector in a high-contrast instrument for imaging exoplanets. These problems especially affect an interferometric type coronagraph - coronagraphs that do not use a mask to physically block starlight in the science channel of the instrument. These problems are presented using images taken with a commercial Princeton Instrument EMCCD camera in the Goddard Space Flight Center's (GSFC), Interferometric Coronagraph facility. In addition, this paper discusses techniques to overcome such problems. This paper also discusses the development and architecture of a Field Programmable Gate Array and Digital-to-Analog Converter based shaped clock controller for a photon-counting EMCCD camera. The discussion contained here will inform high-contrast imaging groups in their work with EMCCD detectors.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Jiyin; Huang, Shaoyun, E-mail: hqxu@pku.edu.cn, E-mail: syhuang@pku.edu.cn; Lei, Zijin

We demonstrate direct measurements of the spin-orbit interaction and Landé g factors in a semiconductor nanowire double quantum dot. The device is made from a single-crystal pure-phase InAs nanowire on top of an array of finger gates on a Si/SiO{sub 2} substrate and the measurements are performed in the Pauli spin-blockade regime. It is found that the double quantum dot exhibits a large singlet-triplet energy splitting of Δ{sub ST} ∼ 2.3 meV, a strong spin-orbit interaction of Δ{sub SO} ∼ 140 μeV, and a large and strongly level-dependent Landé g factor of ∼12.5. These results imply that single-crystal pure-phase InAs nanowires are desired semiconductormore » nanostructures for applications in quantum information technologies.« less

Nanoscale thermocapillarity enabled purification for horizontally aligned arrays of single walled carbon nanotubes

NASA Astrophysics Data System (ADS)

Jin, Sung Hun; Dunham, Simon; Xie, Xu; Rogers, John A.

2015-09-01

Among the remarkable variety of semiconducting nanomaterials that have been discovered over the past two decades, single-walled carbon nanotubes remain uniquely well suited for applications in high-performance electronics, sensors and other technologies. The most advanced opportunities demand the ability to form perfectly aligned, horizontal arrays of purely semiconducting, chemically pristine carbon nanotubes. Here, we present strategies that offer this capability. Nanoscale thermos-capillary flows in thin-film organic coatings followed by reactive ion etching serve as highly efficient means for selectively removing metallic carbon nanotubes from electronically heterogeneous aligned arrays grown on quartz substrates. The low temperatures and unusual physics associated with this process enable robust, scalable operation, with clear potential for practical use. Especially for the purpose of selective joule heating over only metallic nanotubes, two representative platforms are proposed and confirmed. One is achieved by selective joule heating associated with thin film transistors with partial gate structure. The other is based on a simple, scalable, large-area scheme through microwave irradiation by using micro-strip dipole antennas of low work-function metals. In this study, based on purified semiconducting SWNTs, we demonstrated field effect transistors with mobility (> 1,000 cm2/Vsec) and on/off switching ratio (~10,000) with current outputs in the milliamp range. Furthermore, as one demonstration of the effectiveness over large area-scalability and simplicity, implementing the micro-wave based purification, on large arrays consisting of ~20,000 SWNTs completely removes all of the m-SWNTs (~7,000) to yield a purity of s-SWNTs that corresponds, quantitatively, to at least to 99.9925% and likely significantly higher.

Charge reconfiguration in arrays of quantum dots

NASA Astrophysics Data System (ADS)

Bayer, Johannes C.; Wagner, Timo; Rugeramigabo, Eddy P.; Haug, Rolf J.

2017-12-01

Semiconductor quantum dots are potential building blocks for scalable qubit architectures. Efficient control over the exchange interaction and the possibility of coherently manipulating electron states are essential ingredients towards this goal. We studied experimentally the shuttling of electrons trapped in serial quantum dot arrays isolated from the reservoirs. The isolation hereby enables a high degree of control over the tunnel couplings between the quantum dots, while electrons can be transferred through the array by gate voltage variations. Model calculations are compared with our experimental results for double, triple, and quadruple quantum dot arrays. We are able to identify all transitions observed in our experiments, including cotunneling transitions between distant quantum dots. The shuttling of individual electrons between quantum dots along chosen paths is demonstrated.

Fully transparent conformal organic thin-film transistor array and its application as LED front driving.

PubMed

Cui, Nan; Ren, Hang; Tang, Qingxin; Zhao, Xiaoli; Tong, Yanhong; Hu, Wenping; Liu, Yichun

2018-02-22

A fully transparent conformal organic thin-film field-effect transistor array is demonstrated based on a photolithography-compatible ultrathin metallic grid gate electrode and a solution-processed C 8 -BTBT film. The resulting organic field-effect transistor array exhibits a high optical transparency of >80% over the visible spectrum, mobility up to 2 cm 2 V -1 s -1 , on/off ratio of 10 5 -10 6 , switching current of >0.1 mA, and excellent light stability. The transparent conformal transistor array is demonstrated to adhere well to flat and curved LEDs as front driving. These results present promising applications of the solution-processed wide-bandgap organic semiconductor thin films in future large-scale transparent conformal active-matrix displays.

Modulation transfer function of partial gating detector by liquid crystal auto-controlling light intensity

NASA Astrophysics Data System (ADS)

Yang, Xusan; Tang, Yuanhe; Liu, Kai; Liu, Hanchen; Gao, Haiyang; Li, Qing; Zhang, Ruixia; Ye, Na; Liang, Yuan; Zhao, Gaoxiang

2008-12-01

Based on the electro-optical properties of liquid crystal, we have designed a novel partial gating detector. Liquid crystal can be taken to change its own transmission according to the light intensity outside. Every single pixel of the image is real-time modulated by liquid crystal, thus the strong light is weakened and low light goes through the detector normally .The purpose of partial-gating strong light (>105lx) can be achieved by this detector. The modulation transfer function (MTF) equations of the main optical sub-systems are calculated in this paper, they are liquid crystal panels, linear fiber panel and CCD array detector. According to the relevant size, the MTF value of this system is fitted out. The result is MTF= 0.518 at Nyquist frequency.

4D micro-CT using fast prospective gating

NASA Astrophysics Data System (ADS)

Guo, Xiaolian; Johnston, Samuel M.; Qi, Yi; Johnson, G. Allan; Badea, Cristian T.

2012-01-01

Micro-CT is currently used in preclinical studies to provide anatomical information. But, there is also significant interest in using this technology to obtain functional information. We report here a new sampling strategy for 4D micro-CT for functional cardiac and pulmonary imaging. Rapid scanning of free-breathing mice is achieved with fast prospective gating (FPG) implemented on a field programmable gate array. The method entails on-the-fly computation of delays from the R peaks of the ECG signals or the peaks of the respiratory signals for the triggering pulses. Projection images are acquired for all cardiac or respiratory phases at each angle before rotating to the next angle. FPG can deliver the faster scan time of retrospective gating (RG) with the regular angular distribution of conventional prospective gating for cardiac or respiratory gating. Simultaneous cardio-respiratory gating is also possible with FPG in a hybrid retrospective/prospective approach. We have performed phantom experiments to validate the new sampling protocol and compared the results from FPG and RG in cardiac imaging of a mouse. Additionally, we have evaluated the utility of incorporating respiratory information in 4D cardiac micro-CT studies with FPG. A dual-source micro-CT system was used for image acquisition with pulsed x-ray exposures (80 kVp, 100 mA, 10 ms). The cardiac micro-CT protocol involves the use of a liposomal blood pool contrast agent containing 123 mg I ml-1 delivered via a tail vein catheter in a dose of 0.01 ml g-1 body weight. The phantom experiment demonstrates that FPG can distinguish the successive phases of phantom motion with minimal motion blur, and the animal study demonstrates that respiratory FPG can distinguish inspiration and expiration. 4D cardiac micro-CT imaging with FPG provides image quality superior to RG at an isotropic voxel size of 88 µm and 10 ms temporal resolution. The acquisition time for either sampling approach is less than 5 min. The radiation dose associated with the proposed method is in the range of a typical micro-CT dose (256 mGy for the cardiac study). Ignoring respiration does not significantly affect anatomic information in cardiac studies. FPG can deliver short scan times with low-dose 4D micro-CT imaging without sacrificing image quality. FPG can be applied in high-throughput longitudinal studies in a wide range of applications, including drug safety and cardiopulmonary phenotyping.

Extraction of the gate capacitance coupling coefficient in floating gate non-volatile memories: Statistical study of the effect of mismatching between floating gate memory and reference transistor in dummy cell extraction methods

NASA Astrophysics Data System (ADS)

Rafhay, Quentin; Beug, M. Florian; Duane, Russell

2007-04-01

This paper presents an experimental comparison of dummy cell extraction methods of the gate capacitance coupling coefficient for floating gate non-volatile memory structures from different geometries and technologies. These results show the significant influence of mismatching floating gate devices and reference transistors on the extraction of the gate capacitance coupling coefficient. In addition, it demonstrates the accuracy of the new bulk bias dummy cell extraction method and the importance of the β function, introduced recently in [Duane R, Beug F, Mathewson A. Novel capacitance coupling coefficient measurement methodology for floating gate non-volatile memory devices. IEEE Electr Dev Lett 2005;26(7):507-9], to determine matching pairs of floating gate memory and reference transistor.

Mitigating Upsets in SRAM Based FPGAs from the Xilinix Virtex 2 Family

NASA Technical Reports Server (NTRS)

Swift, Gary M.; Yui, Candice C.; Carmichael, Carl; Koga, Rocky; George, Jeffrey S.

2003-01-01

This slide presentation reviews the single event upset static testing of the Virtex II field programmable gate arrays (FPGA) that were tested in protons and heavy-ions. The test designs and static and dynamic test results are reviewed.

Nanofabrication of Arrays of Silicon Field Emitters with Vertical Silicon Nanowire Current Limiters and Self-Aligned Gates

DTIC Science & Technology

2016-08-19

in a dielectric matrix. This paper explores the electronic device applications of dense arrays of silicon nanowires that are embedded in Nanotechnology ... Nanotechnology 27 (2016) 295302 (11pp) doi:10.1088/0957-4484/27/29/295302 Original content from this work may be used under the terms of the Creative...compared 2 Nanotechnology 27 (2016) 295302 S A Guerrera and A I Akinwande to the device reported by Velasquez-Garcia et al, but it also reduces the

Optimization of a Fast Neutron Scintillator for Real-Time Pulse Shape Discrimination in the Transient Reactor Test Facility (TREAT) Hodoscope

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnson, James T.; Thompson, Scott J.; Watson, Scott M.

We present a multi-channel, fast neutron/gamma ray detector array system that utilizes ZnS(Ag) scintillator detectors. The system employs field programmable gate arrays (FPGAs) to do real-time all digital neutron/gamma ray discrimination with pulse height and time histograms to allow count rates in excess of 1,000,000 pulses per second per channel. The system detector number is scalable in blocks of 16 channels.

The IMPACT Common Module - A Low Cost, Reconfigurable Building Block for Next Generation Phased Arrays

DTIC Science & Technology

2016-03-31

The SiGe receiver has two stages of programmable RF filtering and one stage of IF filtering. Each filter can be tuned in center frequency and...distribution unlimited. transmit, with an IF to RF upconversion chain that is split to programmable phase shifters and VGAs at each output port. Figure 2...These are optimized to run on medium grade Field Programmable Gate Arrays (FPGAs), such as the Altera Arria 10, and represent a few of the many

Biologically Assembled Quantum Electronic Arrays

DTIC Science & Technology

2013-06-07

characterizing the NP arrays. Theory of gate-tunable exchange coupling in the case of cobalt NP on graphene . Used Spin-density-functional theory and...polarization. We can estimate this field using the material parameters for Cobalt , which gives B neEo:N~ M;r; "󈧶 T zrv M M "’ m s s Here N1 is the...minority spin density of states at the Fermi surface for Cobalt , M5 is its saturation magnetization, while M:x is the x-component of the magnetization

Hybrid ECG-gated versus non-gated 512-slice CT angiography of the aorta and coronary artery: image quality and effect of a motion correction algorithm.

PubMed

Lee, Ji Won; Kim, Chang Won; Lee, Geewon; Lee, Han Cheol; Kim, Sang-Pil; Choi, Bum Sung; Jeong, Yeon Joo

2018-02-01

Background Using the hybrid electrocardiogram (ECG)-gated computed tomography (CT) technique, assessment of entire aorta, coronary arteries, and aortic valve can be possible using single-bolus contrast administration within a single acquisition. Purpose To compare the image quality of hybrid ECG-gated and non-gated CT angiography of the aorta and evaluate the effect of a motion correction algorithm (MCA) on coronary artery image quality in a hybrid ECG-gated aorta CT group. Material and Methods In total, 104 patients (76 men; mean age = 65.8 years) prospectively randomized into two groups (Group 1 = hybrid ECG-gated CT; Group 2 = non-gated CT) underwent wide-detector array aorta CT. Image quality, assessed using a four-point scale, was compared between the groups. Coronary artery image quality was compared between the conventional reconstruction and motion correction reconstruction subgroups in Group 1. Results Group 1 showed significant advantages over Group 2 in aortic wall, cardiac chamber, aortic valve, coronary ostia, and main coronary arteries image quality (all P < 0.001). All Group 1 patients had diagnostic image quality of the aortic wall and left ostium. The MCA significantly improved the image quality of the three main coronary arteries ( P < 0.05). Moreover, per-vessel interpretability improved from 92.3% to 97.1% with the MCA ( P = 0.013). Conclusion Hybrid ECG-gated CT significantly improved the heart and aortic wall image quality and the MCA can further improve the image quality and interpretability of coronary arteries.

Getting to the Bottom of the $10,000 Bachelor's Degree

ERIC Educational Resources Information Center

Kelderman, Eric

2013-01-01

In August 2010, Bill Gates, founder of Microsoft, speaking informally at a technology conference, said technological innovations should be able to lower the cost of college to $2,000 a year. Mr. Gates's comments reportedly caught the attention of Gov. Rick Perry, a Republican of Texas, who came up with his own back-of-the-envelope estimate of how…

Structure-based membrane dome mechanism for Piezo mechanosensitivity.

PubMed

Guo, Yusong R; MacKinnon, Roderick

2017-12-12

Mechanosensitive ion channels convert external mechanical stimuli into electrochemical signals for critical processes including touch sensation, balance, and cardiovascular regulation. The best understood mechanosensitive channel, MscL, opens a wide pore, which accounts for mechanosensitive gating due to in-plane area expansion. Eukaryotic Piezo channels have a narrow pore and therefore must capture mechanical forces to control gating in another way. We present a cryo-EM structure of mouse Piezo1 in a closed conformation at 3.7Å-resolution. The channel is a triskelion with arms consisting of repeated arrays of 4-TM structural units surrounding a pore. Its shape deforms the membrane locally into a dome. We present a hypothesis in which the membrane deformation changes upon channel opening. Quantitatively, membrane tension will alter gating energetics in proportion to the change in projected area under the dome. This mechanism can account for highly sensitive mechanical gating in the setting of a narrow, cation-selective pore. © 2017, Guo et al.

Apparatus for sensing patterns of electrical field variations across a surface

DOE Office of Scientific and Technical Information (OSTI.GOV)

Warren, William L.; Devine, Roderick A. B.

An array of nonvolatile field effect transistors used to sense electric potential variations. The transistors owe their nonvolatility to the movement of protons within the oxide layer that occurs only in response to an externally applied electric potential between the gate on one side of the oxide and the source/drain on the other side. The position of the protons within the oxide layer either creates or destroys a conducting channel in the adjacent source/channel/drain layer below it, the current in the channel being measured as the state of the nonvolatile memory. The protons can also be moved by potentials createdmore » by other instrumentalities, such as charges on fingerprints or styluses above the gates, pressure on a piezoelectric layer above the gates, light shining upon a photoconductive layer above the gates. The invention allows sensing of fingerprints, handwriting, and optical images, which are converted into digitized images thereof in a nonvolatile format.« less

High-frequency self-aligned graphene transistors with transferred gate stacks

PubMed Central

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-01-01

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra–high-frequency circuits. PMID:22753503

Performance characteristics of nanocrystalline diamond vacuum field emission transistor array

NASA Astrophysics Data System (ADS)

Hsu, S. H.; Kang, W. P.; Davidson, J. L.; Huang, J. H.; Kerns, D. V.

2012-06-01

Nitrogen-incorporated nanocrystalline diamond (ND) vacuum field emission transistor (VFET) with self-aligned gate is fabricated by mold transfer microfabrication technique in conjunction with chemical vapor deposition (CVD) of nanocrystalline diamond on emitter cavity patterned on silicon-on-insulator (SOI) substrate. The fabricated ND-VFET demonstrates gate-controlled emission current with good signal amplification characteristics. The dc characteristics of the ND-VFET show well-defined cutoff, linear, and saturation regions with low gate turn-on voltage, high anode current, negligible gate intercepted current, and large dc voltage gain. The ac performance of the ND-VFET is measured, and the experimental data are analyzed using a modified small signal circuit model. The experimental results obtained for the ac voltage gain are found to agree with the theoretical model. A higher ac voltage gain is attainable by using a better test setup to eliminate the associated parasitic capacitances. The paper reveals the amplifier characteristics of the ND-VFET for potential applications in vacuum microelectronics.

Performance characteristics of nanocrystalline diamond vacuum field emission transistor array

NASA Astrophysics Data System (ADS)

Hsu, S. H.; Kang, W. P.; Davidson, J. L.; Huang, J. H.; Kerns, D. V.

2012-05-01

Nitrogen-incorporated nanocrystalline diamond (ND) vacuum field emission transistor (VFET) with self-aligned gate is fabricated by mold transfer microfabrication technique in conjunction with chemical vapor deposition (CVD) of nanocrystalline diamond on emitter cavity patterned on silicon-on-insulator (SOI) substrate. The fabricated ND-VFET demonstrates gate-controlled emission current with good signal amplification characteristics. The dc characteristics of the ND-VFET show well-defined cutoff, linear, and saturation regions with low gate turn-on voltage, high anode current, negligible gate intercepted current, and large dc voltage gain. The ac performance of the ND-VFET is measured, and the experimental data are analyzed using a modified small signal circuit model. The experimental results obtained for the ac voltage gain are found to agree with the theoretical model. A higher ac voltage gain is attainable by using a better test setup to eliminate the associated parasitic capacitances. The paper reveals the amplifier characteristics of the ND-VFET for potential applications in vacuum microelectronics.

Water gate array for current flow or tidal movement pneumatic harnessing system

DOEpatents

Gorlov, Alexander M.

1991-01-01

The invention, which provides a system for harnessing power from current flow or tidal movement in a body of water, comprises first and second hydro-pneumatic chambers each having ingress and egress below the water surface near the river or ocean floor and water gates operative to open or seal the ports to the passage of water. In an exemplary embodiment, the gates are sychronized by shafts so that the ingress ports of each chamber are connected to the egress ports of each other chamber. Thus, one set of gates is closed, while the other is open, thereby allowing water to flow into one chamber and build air pressure therein and allowing water to flow out of the other chamber and create a partial vacuum therein. A pipe connects the chambers, and an air turbine harnesses the air movement within the pipe. When water levels are equilibrated, the open set of gates is closed by a counterweight, and the other set is allowed to open by natural force of the water differential. The water gates may be comprised of a plurality of louvers which are ganged for simultaneous opening and closing. The system is designed to operate with air turbines or other pneumatic devices. Its design minimizes construction cost and environmental impact, yet provides a clean renewable energy source.

Effects of an Environmentally-relevant Mixture of Pyrethroid Insecticides on Spontaneous Activity in Primary Cortical Networks on Microelectrode Arrays

EPA Science Inventory

Pyrethroid insecticides exert their insecticidal and toxicological effects primarily by disrupting voltage-gated sodium channel (VGSC) function, resulting in altered neuronal excitability. Numerous studies of individual pyrethroids have characterized effects on mammalian VGSC fun...

A Robust Strategy for Total Ionizing Dose Testing of Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Wilcox, Edward; Berg, Melanie; Friendlich, Mark; Lakeman, Joseph; KIm, Hak; Pellish, Jonathan; LaBel, Kenneth

2012-01-01

We present a novel method of FPGA TID testing that measures propagation delay between flip-flops operating at maximum speed. Measurement is performed on-chip at-speed and provides a key design metric when building system-critical synchronous designs.

Micromachined mold-type double-gated metal field emitters

NASA Astrophysics Data System (ADS)

Lee, Yongjae; Kang, Seokho; Chun, Kukjin

1997-12-01

Electron field emitters with double gates were fabricated using micromachining technology and the effect of the electric potential of the focusing gate (or second gate) was experimentally evaluated. The molybdenum field emission tip was made by filling a cusplike mold formed when a conformal film was deposited on the hole-trench that had been patterned on stacked metals and dielectric layers. The hole-trench was patterned by electron beam lithography and reactive ion etching. Each field emitter has a 0960-1317/7/4/009/img1 diameter extraction gate (or first gate) and a 0960-1317/7/4/009/img2 diameter focusing gate (or second gate). To make a path for the emitted electrons, silicon bulk was etched anisotropically in KOH and EDP (ethylene-diamine pyrocatechol) solution successively. The I - V characteristics and anode current change due to the focusing gate potential were measured.

Mosad and Stream Vision For A Telerobotic, Flying Camera System

NASA Technical Reports Server (NTRS)

Mandl, William

2002-01-01

Two full custom camera systems using the Multiplexed OverSample Analog to Digital (MOSAD) conversion technology for visible light sensing were built and demonstrated. They include a photo gate sensor and a photo diode sensor. The system includes the camera assembly, driver interface assembly, a frame stabler board with integrated decimeter and Windows 2000 compatible software for real time image display. An array size of 320X240 with 16 micron pixel pitch was developed for compatibility with 0.3 inch CCTV optics. With 1.2 micron technology, a 73% fill factor was achieved. Noise measurements indicated 9 to 11 bits operating with 13.7 bits best case. Power measured under 10 milliwatts at 400 samples per second. Nonuniformity variation was below noise floor. Pictures were taken with different cameras during the characterization study to demonstrate the operable range. The successful conclusion of this program demonstrates the utility of the MOSAD for NASA missions, providing superior performance over CMOS and lower cost and power consumption over CCD. The MOSAD approach also provides a path to radiation hardening for space based applications.

The New Meteor Radar at Penn State: Design and First Observations

NASA Technical Reports Server (NTRS)

Urbina, J.; Seal, R.; Dyrud, L.

2011-01-01

In an effort to provide new and improved meteor radar sensing capabilities, Penn State has been developing advanced instruments and technologies for future meteor radars, with primary objectives of making such instruments more capable and more cost effective in order to study the basic properties of the global meteor flux, such as average mass, velocity, and chemical composition. Using low-cost field programmable gate arrays (FPGAs), combined with open source software tools, we describe a design methodology enabling one to develop state-of-the art radar instrumentation, by developing a generalized instrumentation core that can be customized using specialized output stage hardware. Furthermore, using object-oriented programming (OOP) techniques and open-source tools, we illustrate a technique to provide a cost-effective, generalized software framework to uniquely define an instrument s functionality through a customizable interface, implemented by the designer. The new instrument is intended to provide instantaneous profiles of atmospheric parameters and climatology on a daily basis throughout the year. An overview of the instrument design concepts and some of the emerging technologies developed for this meteor radar are presented.

A Survey on FPGA-Based Sensor Systems: Towards Intelligent and Reconfigurable Low-Power Sensors for Computer Vision, Control and Signal Processing

PubMed Central

García, Gabriel J.; Jara, Carlos A.; Pomares, Jorge; Alabdo, Aiman; Poggi, Lucas M.; Torres, Fernando

2014-01-01

The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc.), reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field. PMID:24691100

A survey on FPGA-based sensor systems: towards intelligent and reconfigurable low-power sensors for computer vision, control and signal processing.

PubMed

García, Gabriel J; Jara, Carlos A; Pomares, Jorge; Alabdo, Aiman; Poggi, Lucas M; Torres, Fernando

2014-03-31

The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc.), reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field.

Flexible graphene transistors for recording cell action potentials

NASA Astrophysics Data System (ADS)

Blaschke, Benno M.; Lottner, Martin; Drieschner, Simon; Bonaccini Calia, Andrea; Stoiber, Karolina; Rousseau, Lionel; Lissourges, Gaëlle; Garrido, Jose A.

2016-06-01

Graphene solution-gated field-effect transistors (SGFETs) are a promising platform for the recording of cell action potentials due to the intrinsic high signal amplification of graphene transistors. In addition, graphene technology fulfills important key requirements for in-vivo applications, such as biocompability, mechanical flexibility, as well as ease of high density integration. In this paper we demonstrate the fabrication of flexible arrays of graphene SGFETs on polyimide, a biocompatible polymeric substrate. We investigate the transistor’s transconductance and intrinsic electronic noise which are key parameters for the device sensitivity, confirming that the obtained values are comparable to those of rigid graphene SGFETs. Furthermore, we show that the devices do not degrade during repeated bending and the transconductance, governed by the electronic properties of graphene, is unaffected by bending. After cell culture, we demonstrate the recording of cell action potentials from cardiomyocyte-like cells with a high signal-to-noise ratio that is higher or comparable to competing state of the art technologies. Our results highlight the great capabilities of flexible graphene SGFETs in bioelectronics, providing a solid foundation for in-vivo experiments and, eventually, for graphene-based neuroprosthetics.

Note: a 4 ns hardware photon correlator based on a general-purpose field-programmable gate array development board implemented in a compact setup for fluorescence correlation spectroscopy.

PubMed

Kalinin, Stanislav; Kühnemuth, Ralf; Vardanyan, Hayk; Seidel, Claus A M

2012-09-01

We present a fast hardware photon correlator implemented in a field-programmable gate array (FPGA) combined with a compact confocal fluorescence setup. The correlator has two independent units with a time resolution of 4 ns while utilizing less than 15% of a low-end FPGA. The device directly accepts transistor-transistor logic (TTL) signals from two photon counting detectors and calculates two auto- or cross-correlation curves in real time. Test measurements demonstrate that the performance of our correlator is comparable with the current generation of commercial devices. The sensitivity of the optical setup is identical or even superior to current commercial devices. The FPGA design and the optical setup both allow for a straightforward extension to multi-color applications. This inexpensive and compact solution with a very good performance can serve as a versatile platform for uses in education, applied sciences, and basic research.

Coherent beam combining in atmospheric channels using gated backscatter.

PubMed

Naeh, Itay; Katzir, Abraham

2016-02-01

This paper introduces the concept of atmospheric channels and describes a possible approach for the coherent beam combining of lasers of an optical phased array (OPA) in a turbulent atmosphere. By using the recently introduced sparse spectrum harmonic augmentation method, a comprehensive simulative investigation was performed and the exceptional properties of the atmospheric channels were numerically demonstrated. Among the interesting properties are the ability to guide light in a confined manner in a refractive channel, the ability to gather different sources to the same channel, and the ability to maintain a constant relative phase within the channel between several sources. The newly introduced guiding properties combined with a suggested method for channel probing and phase measurement by aerosol backscattered radiation allows coherence improvement of the phased array's elements and energy refocusing at the location of the channel in order to increase power in the bucket without feedback from the target. The method relies on the electronic focusing, electronic scanning, and time gating of the OPA, combined with elements of the relative phase measurements.

Fast contactless vibrating structure characterization using real time field programmable gate array-based digital signal processing: demonstrations with a passive wireless acoustic delay line probe and vision.

PubMed

Goavec-Mérou, G; Chrétien, N; Friedt, J-M; Sandoz, P; Martin, G; Lenczner, M; Ballandras, S

2014-01-01

Vibrating mechanical structure characterization is demonstrated using contactless techniques best suited for mobile and rotating equipments. Fast measurement rates are achieved using Field Programmable Gate Array (FPGA) devices as real-time digital signal processors. Two kinds of algorithms are implemented on FPGA and experimentally validated in the case of the vibrating tuning fork. A first application concerns in-plane displacement detection by vision with sampling rates above 10 kHz, thus reaching frequency ranges above the audio range. A second demonstration concerns pulsed-RADAR cooperative target phase detection and is applied to radiofrequency acoustic transducers used as passive wireless strain gauges. In this case, the 250 ksamples/s refresh rate achieved is only limited by the acoustic sensor design but not by the detection bandwidth. These realizations illustrate the efficiency, interest, and potentialities of FPGA-based real-time digital signal processing for the contactless interrogation of passive embedded probes with high refresh rates.

Sn nanothreads in GaAs: experiment and simulation

NASA Astrophysics Data System (ADS)

Semenikhin, I.; Vyurkov, V.; Bugaev, A.; Khabibullin, R.; Ponomarev, D.; Yachmenev, A.; Maltsev, P.; Ryzhii, M.; Otsuji, T.; Ryzhii, V.

2016-12-01

The gated GaAs structures like the field-effect transistor with the array of the Sn nanothreads was fabricated via delta-doping of vicinal GaAs surface by Sn atoms with a subsequent regrowth. That results in the formation of the chains of Sn atoms at the terrace edges. Two device models were developed. The quantum model accounts for the quantization of the electron energy spectrum in the self-consistent two-dimensional electric potential, herewith the electron density distribution in nanothread arrays for different gate voltages is calculated. The classical model ignores the quantization and electrons are distributed in space according to 3D density of states and Fermi-Dirac statistics. It turned out that qualitatively both models demonstrate similar behavior, nevertheless, the classical one is in better quantitative agreement with experimental data. Plausibly, the quantization could be ignored because Sn atoms are randomly placed along the thread axis. The terahertz hot-electron bolometers (HEBs) could be based on the structure under consideration.

Note: A 4 ns hardware photon correlator based on a general-purpose field-programmable gate array development board implemented in a compact setup for fluorescence correlation spectroscopy

NASA Astrophysics Data System (ADS)

Kalinin, Stanislav; Kühnemuth, Ralf; Vardanyan, Hayk; Seidel, Claus A. M.

2012-09-01

We present a fast hardware photon correlator implemented in a field-programmable gate array (FPGA) combined with a compact confocal fluorescence setup. The correlator has two independent units with a time resolution of 4 ns while utilizing less than 15% of a low-end FPGA. The device directly accepts transistor-transistor logic (TTL) signals from two photon counting detectors and calculates two auto- or cross-correlation curves in real time. Test measurements demonstrate that the performance of our correlator is comparable with the current generation of commercial devices. The sensitivity of the optical setup is identical or even superior to current commercial devices. The FPGA design and the optical setup both allow for a straightforward extension to multi-color applications. This inexpensive and compact solution with a very good performance can serve as a versatile platform for uses in education, applied sciences, and basic research.

Making MUSIC: A multiple sampling ionization chamber

NASA Astrophysics Data System (ADS)

Shumard, B.; Henderson, D. J.; Rehm, K. E.; Tang, X. D.

2007-08-01

A multiple sampling ionization chamber (MUSIC) was developed for use in conjunction with the Atlas scattering chamber (ATSCAT). This chamber was developed to study the (α, p) reaction in stable and radioactive beams. The gas filled ionization chamber is used as a target and detector for both particles in the outgoing channel (p + beam particles for elastic scattering or p + residual nucleus for (α, p) reactions). The MUSIC detector is followed by a Si array to provide a trigger for anode events. The anode events are gated by a gating grid so that only (α, p) reactions where the proton reaches the Si detector result in an anode event. The MUSIC detector is a segmented ionization chamber. The active length of the chamber is 11.95 in. and is divided into 16 equal anode segments (3.5 in. × 0.70 in. with 0.3 in. spacing between pads). The dead area of the chamber was reduced by the addition of a Delrin snout that extends 0.875 in. into the chamber from the front face, to which a mylar window is affixed. 0.5 in. above the anode is a Frisch grid that is held at ground potential. 0.5 in. above the Frisch grid is a gating grid. The gating grid functions as a drift electron barrier, effectively halting the gathering of signals. Setting two sets of alternating wires at differing potentials creates a lateral electric field which traps the drift electrons, stopping the collection of anode signals. The chamber also has a reinforced mylar exit window separating the Si array from the target gas. This allows protons from the (α, p) reaction to be detected. The detection of these protons opens the gating grid to allow the drift electrons released from the ionizing gas during the (α, p) reaction to reach the anode segment below the reaction.

Implementation of a Virtual Microphone Array to Obtain High Resolution Acoustic Images

PubMed Central

Izquierdo, Alberto; Suárez, Luis; Suárez, David

2017-01-01

Using arrays with digital MEMS (Micro-Electro-Mechanical System) microphones and FPGA-based (Field Programmable Gate Array) acquisition/processing systems allows building systems with hundreds of sensors at a reduced cost. The problem arises when systems with thousands of sensors are needed. This work analyzes the implementation and performance of a virtual array with 6400 (80 × 80) MEMS microphones. This virtual array is implemented by changing the position of a physical array of 64 (8 × 8) microphones in a grid with 10 × 10 positions, using a 2D positioning system. This virtual array obtains an array spatial aperture of 1 × 1 m2. Based on the SODAR (SOund Detection And Ranging) principle, the measured beampattern and the focusing capacity of the virtual array have been analyzed, since beamforming algorithms assume to be working with spherical waves, due to the large dimensions of the array in comparison with the distance between the target (a mannequin) and the array. Finally, the acoustic images of the mannequin, obtained for different frequency and range values, have been obtained, showing high angular resolutions and the possibility to identify different parts of the body of the mannequin. PMID:29295485

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-02-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

Compact quantum gates on electron-spin qubits assisted by diamond nitrogen-vacancy centers inside cavities

NASA Astrophysics Data System (ADS)

Wei, Hai-Rui; Deng, Fu-Guo

2013-10-01

Constructing compact quantum circuits for universal quantum gates on solid-state systems is crucial for quantum computing. We present some compact quantum circuits for a deterministic solid-state quantum computing, including the cnot, Toffoli, and Fredkin gates on the diamond NV centers confined inside cavities, achieved by some input-output processes of a single photon. Our quantum circuits for these universal quantum gates are simple and economic. Moreover, additional electron qubits are not employed, but only a single-photon medium. These gates have a long coherent time. We discuss the feasibility of these universal solid-state quantum gates, concluding that they are feasible with current technology.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-05-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

Decision Gate Process for Assessment of a NASA Technology Development Portfolio

NASA Technical Reports Server (NTRS)

Kohli, Rajiv; Fishman, Julianna L.; Hyatt, Mark J.

2012-01-01

The NASA Dust Management Project (DMP) was established to provide technologies (to Technology Readiness Level (TRL) 6) required to address adverse effects of lunar dust to humans and to exploration systems and equipment, to reduce life cycle cost and risk, and to increase the probability of sustainable and successful lunar missions. The technology portfolio of DMP consisted of different categories of technologies whose final product was either a technology solution in itself, or one that contributes toward a dust mitigation strategy for a particular application. A Decision Gate Process (DGP) was developed to assess and validate the achievement and priority of the dust mitigation technologies as the technologies progress through the development cycle. The DGP was part of continuous technology assessment and was a critical element of DMP risk management. At the core of the process were technology-specific criteria developed to measure the success of each DMP technology in attaining the technology readiness levels assigned to each decision gate. The DGP accounts for both categories of technologies and qualifies the technology progression from technology development tasks to application areas. The process provided opportunities to validate performance, as well as to identify non-performance in time to adjust resources and direction. This paper describes the overall philosophy of the DGP and the methodology for implementation for DMP, and describes the method for defining the technology evaluation criteria. The process is illustrated by example of an application to a specific DMP technology.

Single-electron thermal devices coupled to a mesoscopic gate

NASA Astrophysics Data System (ADS)

Sánchez, Rafael; Thierschmann, Holger; Molenkamp, Laurens W.

2017-11-01

We theoretically investigate the propagation of heat currents in a three-terminal quantum dot engine. Electron-electron interactions introduce state-dependent processes which can be resolved by energy-dependent tunneling rates. We identify the relevant transitions which define the operation of the system as a thermal transistor or a thermal diode. In the former case, thermal-induced charge fluctuations in the gate dot modify the thermal currents in the conductor with suppressed heat injection, resulting in huge amplification factors and the possible gating with arbitrarily low energy cost. In the latter case, enhanced correlations of the state-selective tunneling transitions redistribute heat flows giving high rectification coefficients and the unexpected cooling of one conductor terminal by heating the other one. We propose quantum dot arrays as a possible way to achieve the extreme tunneling asymmetries required for the different operations.

T-gate aligned nanotube radio frequency transistors and circuits with superior performance.

PubMed

Che, Yuchi; Lin, Yung-Chen; Kim, Pyojae; Zhou, Chongwu

2013-05-28

In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics.

Short-Wave Infrared HgCdTe Electron Avalanche Photodiodes for Gated Viewing

NASA Astrophysics Data System (ADS)

Sieck, A.; Benecke, M.; Eich, D.; Oelmaier, R.; Wendler, J.; Figgemeier, H.

2018-06-01

Short-wave infrared (SWIR) HgCdTe electron avalanche photodiodes (eAPDs) with different doping profiles have been characterized for use in SWIR gated viewing systems. Gated viewing offers enhanced image contrast in scenes with clutter from the foreground or background. HgCdTe-based eAPDs show exponential gain-voltage characteristics and low excess noise and are, therefore, well suited for active imaging applications. The gain achievable at a fixed reverse voltage varies with the bandgap of the Hg1-xCdxTe detector material. We analyze current-voltage and gain-voltage plots measured on SWIR Hg1-xCdxTe eAPDs with x = 0.45, corresponding to a cutoff wavelength of 2.55 μm at 150 K. The cutoff has been chosen as a trade-off between achievable APD gain and operating temperature for SWIR gated-viewing systems with target distances of about 1000 m. Focal plane arrays with a readout-integrated circuit featuring a fast internal clock have been built and their performance with respect to gated viewing applications has been evaluated on a laboratory demonstrator for short distances. Future plans for a field demonstrator for distances up to 1000 m are described briefly at the end.

Dual-Gated Active Metasurface at 1550 nm with Wide (>300°) Phase Tunability.

PubMed

Kafaie Shirmanesh, Ghazaleh; Sokhoyan, Ruzan; Pala, Ragip A; Atwater, Harry A

2018-05-09

Active metasurfaces composed of electrically reconfigurable nanoscale subwavelength antenna arrays can enable real-time control of scattered light amplitude and phase. Achievement of widely tunable phase and amplitude in chip-based active metasurfaces operating at or near 1550 nm wavelength has considerable potential for active beam steering, dynamic hologram rendition, and realization of flat optics with reconfigurable focal lengths. Previously, electrically tunable conducting oxide-based reflectarray metasurfaces have demonstrated dynamic phase control of reflected light with a maximum phase shift of 184° ( Nano Lett. 2016 , 16 , 5319 ). Here, we introduce a dual-gated reflectarray metasurface architecture that enables much wider (>300°) phase tunability. We explore light-matter interactions with dual-gated metasurface elements that incorporate two independent voltage-controlled MOS field effect channels connected in series to form a single metasurface element that enables wider phase tunability. Using indium tin oxide (ITO) as the active metasurface material and a composite hafnia/alumina gate dielectric, we demonstrate a prototype dual-gated metasurface with a continuous phase shift from 0 to 303° and a relative reflectance modulation of 89% under applied voltage bias of 6.5 V.

Braiding by Majorana tracking and long-range CNOT gates with color codes

NASA Astrophysics Data System (ADS)

Litinski, Daniel; von Oppen, Felix

2017-11-01

Color-code quantum computation seamlessly combines Majorana-based hardware with topological error correction. Specifically, as Clifford gates are transversal in two-dimensional color codes, they enable the use of the Majoranas' non-Abelian statistics for gate operations at the code level. Here, we discuss the implementation of color codes in arrays of Majorana nanowires that avoid branched networks such as T junctions, thereby simplifying their realization. We show that, in such implementations, non-Abelian statistics can be exploited without ever performing physical braiding operations. Physical braiding operations are replaced by Majorana tracking, an entirely software-based protocol which appropriately updates the Majoranas involved in the color-code stabilizer measurements. This approach minimizes the required hardware operations for single-qubit Clifford gates. For Clifford completeness, we combine color codes with surface codes, and use color-to-surface-code lattice surgery for long-range multitarget CNOT gates which have a time overhead that grows only logarithmically with the physical distance separating control and target qubits. With the addition of magic state distillation, our architecture describes a fault-tolerant universal quantum computer in systems such as networks of tetrons, hexons, or Majorana box qubits, but can also be applied to nontopological qubit platforms.

Enhanced transconductance in a double-gate graphene field-effect transistor

NASA Astrophysics Data System (ADS)

Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

2018-03-01

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

Prospects for quantum computing with an array of ultracold polar paramagnetic molecules.

PubMed

Karra, Mallikarjun; Sharma, Ketan; Friedrich, Bretislav; Kais, Sabre; Herschbach, Dudley

2016-03-07

Arrays of trapped ultracold molecules represent a promising platform for implementing a universal quantum computer. DeMille [Phys. Rev. Lett. 88, 067901 (2002)] has detailed a prototype design based on Stark states of polar (1)Σ molecules as qubits. Herein, we consider an array of polar (2)Σ molecules which are, in addition, inherently paramagnetic and whose Hund's case (b) free-rotor pair-eigenstates are Bell states. We show that by subjecting the array to combinations of concurrent homogeneous and inhomogeneous electric and magnetic fields, the entanglement of the array's Stark and Zeeman states can be tuned and the qubit sites addressed. Two schemes for implementing an optically controlled CNOT gate are proposed and their feasibility discussed in the face of the broadening of spectral lines due to dipole-dipole coupling and the inhomogeneity of the electric and magnetic fields.

A special purpose silicon compiler for designing supercomputing VLSI systems

NASA Technical Reports Server (NTRS)

Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.

1991-01-01

Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

Decision Gate Process for Assessment of a Technology Development Portfolio

NASA Technical Reports Server (NTRS)

Kohli, Rajiv; Fishman, Julianna; Hyatt, Mark

2012-01-01

The NASA Dust Management Project (DMP) was established to provide technologies (to TRL 6 development level) required to address adverse effects of lunar dust to humans and to exploration systems and equipment, which will reduce life cycle cost and risk, and will increase the probability of sustainable and successful lunar missions. The technology portfolio of DMP consisted of different categories of technologies whose final product is either a technology solution in itself, or one that contributes toward a dust mitigation strategy for a particular application. A Decision Gate Process (DGP) was developed to assess and validate the achievement and priority of the dust mitigation technologies as the technologies progress through the development cycle. The DGP was part of continuous technology assessment and was a critical element of DMP risk management. At the core of the process were technology-specific criteria developed to measure the success of each DMP technology in attaining the technology readiness levels assigned to each decision gate. The DGP accounts for both categories of technologies and qualifies the technology progression from technology development tasks to application areas. The process provided opportunities to validate performance, as well as to identify non-performance in time to adjust resources and direction. This paper describes the overall philosophy of the DGP and the methodology for implementation for DMP, and describes the method for defining the technology evaluation criteria. The process is illustrated by example of an application to a specific DMP technology.

Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Takano, H.; Hosogi, K.; Kato, T.

1995-05-01

A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier withmore » an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs.« less

High-speed sorting of grains by color and surface texture

USDA-ARS?s Scientific Manuscript database

A high-speed, low-cost, image-based sorting device was developed to detect and separate grains with different colors/textures. The device directly combines a complementary metal–oxide–semiconductor (CMOS) color image sensor with a field-programmable gate array (FPGA) that was programmed to execute ...

Technical Note: Validation and implementation of a wireless transponder tracking system for gated stereotactic ablative radiotherapy of the liver

DOE Office of Scientific and Technical Information (OSTI.GOV)

James, Joshua, E-mail: joshua.james@louisville.edu; Dunlap, Neal E.; Nguyen, Vi Nhan

Purpose: Tracking soft-tissue targets has recently been cleared as a new application of Calypso, an electromagnetic wireless transponder tracking system, allowing for gated treatment of the liver based on the motion of the target volume itself. The purpose of this study is to describe the details of validating the Calypso system for wireless transponder tracking of the liver and to present the clinical workflow for using it to deliver gated stereotactic ablative radiotherapy (SABR). Methods: A commercial 3D diode array motion system was used to evaluate the dynamic tracking accuracy of Calypso when tracking continuous large amplitude motion. It wasmore » then used to perform end-to-end tests to evaluate the dosimetric accuracy of gated beam delivery for liver SABR. In addition, gating limits were investigated to determine how large the gating window can be while still maintaining dosimetric accuracy. The gating latency of the Calypso system was also measured using a customized motion phantom. Results: The average absolute difference between the measured and expected positional offset was 0.3 mm. The 2%/2 mm gamma pass rates for the gated treatment delivery were greater than 97%. When increasing the gating limits beyond the known extent of planned motion, the gamma pass rates decreased as expected. The 2%/2 mm gamma pass rate for a 1, 2, and 3 mm increase in gating limits was measured to be 97.8%, 82.9%, and 61.4%, respectively. The average gating latency was measured to be 63.8 ms for beam-hold and 195.8 ms for beam-on. Four liver patients with 17 total fractions have been successfully treated at our institution. Conclusions: Wireless transponder tracking was validated as a dosimetrically accurate way to provide gated SABR of the liver. The dynamic tracking accuracy of the Calypso system met manufacturer’s specification, even for continuous large amplitude motion that can be encountered when tracking liver tumors close to the diaphragm. The measured beam-hold gating latency was appropriate for targets that will traverse the gating limit each respiratory cycle causing the beam to be interrupted constantly throughout treatment delivery.« less

X-ray characterization of a multichannel smart-pixel array detector.

PubMed

Ross, Steve; Haji-Sheikh, Michael; Huntington, Andrew; Kline, David; Lee, Adam; Li, Yuelin; Rhee, Jehyuk; Tarpley, Mary; Walko, Donald A; Westberg, Gregg; Williams, George; Zou, Haifeng; Landahl, Eric

2016-01-01

The Voxtel VX-798 is a prototype X-ray pixel array detector (PAD) featuring a silicon sensor photodiode array of 48 × 48 pixels, each 130 µm × 130 µm × 520 µm thick, coupled to a CMOS readout application specific integrated circuit (ASIC). The first synchrotron X-ray characterization of this detector is presented, and its ability to selectively count individual X-rays within two independent arrival time windows, a programmable energy range, and localized to a single pixel is demonstrated. During our first trial run at Argonne National Laboratory's Advance Photon Source, the detector achieved a 60 ns gating time and 700 eV full width at half-maximum energy resolution in agreement with design parameters. Each pixel of the PAD holds two independent digital counters, and the discriminator for X-ray energy features both an upper and lower threshold to window the energy of interest discarding unwanted background. This smart-pixel technology allows energy and time resolution to be set and optimized in software. It is found that the detector linearity follows an isolated dead-time model, implying that megahertz count rates should be possible in each pixel. Measurement of the line and point spread functions showed negligible spatial blurring. When combined with the timing structure of the synchrotron storage ring, it is demonstrated that the area detector can perform both picosecond time-resolved X-ray diffraction and fluorescence spectroscopy measurements.

Magnetophoretic circuits for digital control of single particles and cells

NASA Astrophysics Data System (ADS)

Lim, Byeonghwa; Reddy, Venu; Hu, Xinghao; Kim, Kunwoo; Jadhav, Mital; Abedini-Nassab, Roozbeh; Noh, Young-Woock; Lim, Yong Taik; Yellen, Benjamin B.; Kim, Cheolgi

2014-05-01

The ability to manipulate small fluid droplets, colloidal particles and single cells with the precision and parallelization of modern-day computer hardware has profound applications for biochemical detection, gene sequencing, chemical synthesis and highly parallel analysis of single cells. Drawing inspiration from general circuit theory and magnetic bubble technology, here we demonstrate a class of integrated circuits for executing sequential and parallel, timed operations on an ensemble of single particles and cells. The integrated circuits are constructed from lithographically defined, overlaid patterns of magnetic film and current lines. The magnetic patterns passively control particles similar to electrical conductors, diodes and capacitors. The current lines actively switch particles between different tracks similar to gated electrical transistors. When combined into arrays and driven by a rotating magnetic field clock, these integrated circuits have general multiplexing properties and enable the precise control of magnetizable objects.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Averyanov, A. V.; Bajajin, A. G.; Chepurnov, V. F.

The time-projection chamber (TPC) is the main tracking detector in the MPD/NICA. The information on charge-particle tracks in the TPC is registered by the MWPG with cathode pad readout. The frontend electronics (FEE) are developed with use of modern technologies such as application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), and data transfer to a concentrator via a fast optical interface. The main parameters of the FEE are as follows: total number of channels, ∼95 000; data stream from the whole TPC, 5 GB/s; low power consumption, less than 100 mW/ch; signal to noise ratio (S/N), 30; equivalent noisemore » charge (ENC), <1000e{sup –} (C{sub in} = 10–20 pF); and zero suppression (pad signal rejection ∼90%). The article presents the status of the readout chamber construction and the data acquisition system. The results of testing FEE prototypes are presented.« less

Simulation analysis of rectifying microfluidic mixing with field-effect-tunable electrothermal induced flow.

PubMed

Liu, Weiyu; Ren, Yukun; Tao, Ye; Yao, Bobin; Li, You

2018-03-01

We report herein field-effect control on in-phase electrothermal streaming from a theoretical point of view, a phenomenon termed "alternating-current electrothermal-flow field effect transistor" (ACET-FFET), in the context of a new technology for handing analytes in microfluidics. Field-effect control through a gate terminal endows ACET-FFET the ability to generate arbitrary symmetry breaking in the transverse vortex flow pattern, which makes it attractive for mixing microfluidic samples. A computational model is developed to study the feasibility of this new microfluidic device design for micromixing. The influence of various parameters on developing an efficient mixer is investigated, and an integrated layout of discrete electrode array is suggested for achieving high-throughput mixing. Our physical demonstration with field-effect electrothermal flow control using a simple electrode structure proves invaluable for designing active micromixers for modern micro total analytical system. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Common source cascode amplifiers for integrating IR-FPA applications

NASA Technical Reports Server (NTRS)

Woolaway, James T.; Young, Erick T.

1989-01-01

Space based astronomical infrared measurements present stringent performance requirements on the infrared detector arrays and their associated readout circuitry. To evaluate the usefulness of commercial CMOS technology for astronomical readout applications a theoretical and experimental evaluation was performed on source follower and common-source cascode integrating amplifiers. Theoretical analysis indicates that for conditions where the input amplifier integration capacitance is limited by the detectors capacitance the input referred rms noise electrons of each amplifier should be equivalent. For conditions of input gate limited capacitance the source follower should provide lower noise. Measurements of test circuits containing both source follower and common source cascode circuits showed substantially lower input referred noise for the common-source cascode input circuits. Noise measurements yielded 4.8 input referred rms noise electrons for an 8.5 minute integration. The signal and noise gain of the common-source cascode amplifier appears to offer substantial advantages in acheiving predicted noise levels.

First imagery generated by near-field real-time aperture synthesis passive millimetre wave imagers at 94 GHz and 183 GHz

NASA Astrophysics Data System (ADS)

Salmon, Neil A.; Mason, Ian; Wilkinson, Peter; Taylor, Chris; Scicluna, Peter

2010-10-01

The first passive millimetre wave (PMMW) imagery is presented from two proof-of-concept aperture synthesis demonstrators, developed to investigate the use of aperture synthesis for personnel security screening and all weather flying at 94 GHz, and satellite based earth observation at 183 GHz [1]. Emission from point noise sources and discharge tubes are used to examine the coherence on system baselines and to measure the point spread functions, making comparisons with theory. Image quality is examined using near field aperture synthesis and G-matrix calibration imaging algorithms. The radiometric sensitivity is measured using the emission from absorbers at elevated temperatures acting as extended sources and compared with theory. Capabilities of the latest Field Programmable Gate Arrays (FPGA) technologies for aperture synthesis PMMW imaging in all-weather and security screening applications are examined.

Hardware Architecture Study for NASA's Space Software Defined Radios

NASA Technical Reports Server (NTRS)

Reinhart, Richard C.; Scardelletti, Maximilian C.; Mortensen, Dale J.; Kacpura, Thomas J.; Andro, Monty; Smith, Carl; Liebetreu, John

2008-01-01

This study defines a hardware architecture approach for software defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general purpose processors, digital signal processors, field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) in addition to flexible and tunable radio frequency (RF) front-ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and and interfaces. The modules are a logical division of common radio functions that comprise a typical communication radio. This paper describes the architecture details, module definitions, and the typical functions on each module as well as the module interfaces. Trade-offs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify the internal physical implementation within each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

Ultra-narrow pulse generator with precision-adjustable pulse width

NASA Astrophysics Data System (ADS)

Fu, Zaiming; Liu, Hanglin

2018-05-01

In this paper, a novel ultra-narrow pulse generation approach is proposed. It is based on the decomposition and synthesis of pulse edges. Through controlling their relative delay, an ultra-narrow pulse could be generated. By employing field programmable gate array digital synthesis technology, the implemented pulse generator is with programmable ability. The amplitude of pulse signals is controlled by the radio frequency amplifiers and bias tees, and high precision can be achieved. More importantly, the proposed approach can break through the limitation of device's propagation delay and optimize the resolution and the accuracy of the pulse width significantly. The implemented pulse generator has two channels, whose minimum pulse width, frequency range, and amplitude range are 100 ps, 15 MHz-1.5 GHz, and 0.1 Vpp-1.8 Vpp, respectively. Both resolution of pulse width and channel delay are 1 ps, and amplitude resolution is 10 mVpp.

Hardware for dynamic quantum computing.

PubMed

Ryan, Colm A; Johnson, Blake R; Ristè, Diego; Donovan, Brian; Ohki, Thomas A

2017-10-01

We describe the hardware, gateware, and software developed at Raytheon BBN Technologies for dynamic quantum information processing experiments on superconducting qubits. In dynamic experiments, real-time qubit state information is fed back or fed forward within a fraction of the qubits' coherence time to dynamically change the implemented sequence. The hardware presented here covers both control and readout of superconducting qubits. For readout, we created a custom signal processing gateware and software stack on commercial hardware to convert pulses in a heterodyne receiver into qubit state assignments with minimal latency, alongside data taking capability. For control, we developed custom hardware with gateware and software for pulse sequencing and steering information distribution that is capable of arbitrary control flow in a fraction of superconducting qubit coherence times. Both readout and control platforms make extensive use of field programmable gate arrays to enable tailored qubit control systems in a reconfigurable fabric suitable for iterative development.

Space Telecommunications Radio Systems (STRS) Hardware Architecture Standard: Release 1.0 Hardware Section

NASA Technical Reports Server (NTRS)

Reinhart, Richard C.; Kacpura, Thomas J.; Smith, Carl R.; Liebetreu, John; Hill, Gary; Mortensen, Dale J.; Andro, Monty; Scardelletti, Maximilian C.; Farrington, Allen

2008-01-01

This report defines a hardware architecture approach for software-defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general-purpose processors, digital signal processors, field programmable gate arrays, and application-specific integrated circuits (ASICs) in addition to flexible and tunable radiofrequency front ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and interfaces. The modules are a logical division of common radio functions that compose a typical communication radio. This report describes the architecture details, the module definitions, the typical functions on each module, and the module interfaces. Tradeoffs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify a physical implementation internally on each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

Fast noninvasive eye-tracking and eye-gaze determination for biomedical and remote monitoring applications

NASA Astrophysics Data System (ADS)

Talukder, Ashit; Morookian, John M.; Monacos, Steve P.; Lam, Raymond K.; Lebaw, C.; Bond, A.

2004-04-01

Eyetracking is one of the latest technologies that has shown potential in several areas including human-computer interaction for people with and without disabilities, and for noninvasive monitoring, detection, and even diagnosis of physiological and neurological problems in individuals. Current non-invasive eyetracking methods achieve a 30 Hz rate with possibly low accuracy in gaze estimation, that is insufficient for many applications. We propose a new non-invasive visual eyetracking system that is capable of operating at speeds as high as 6-12 KHz. A new CCD video camera and hardware architecture is used, and a novel fast image processing algorithm leverages specific features of the input CCD camera to yield a real-time eyetracking system. A field programmable gate array (FPGA) is used to control the CCD camera and execute the image processing operations. Initial results show the excellent performance of our system under severe head motion and low contrast conditions.

Implementation of a Multichannel Serial Data Streaming Algorithm using the Xilinx Serial RapidIO Solution

NASA Technical Reports Server (NTRS)

Doxley, Charles A.

2016-01-01

In the current world of applications that use reconfigurable technology implemented on field programmable gate arrays (FPGAs), there is a need for flexible architectures that can grow as the systems evolve. A project has limited resources and a fixed set of requirements that development efforts are tasked to meet. Designers must develop robust solutions that practically meet the current customer demands and also have the ability to grow for future performance. This paper describes the development of a high speed serial data streaming algorithm that allows for transmission of multiple data channels over a single serial link. The technique has the ability to change to meet new applications developed for future design considerations. This approach uses the Xilinx Serial RapidIO LOGICORE Solution to implement a flexible infrastructure to meet the current project requirements with the ability to adapt future system designs.

Radiation Tolerant Intelligent Memory Stack (RTIMS)

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong; Herath, Jeffrey A.

2006-01-01

The Radiation Tolerant Intelligent Memory Stack (RTIMS), suitable for both geostationary and low earth orbit missions, has been developed. The memory module is fully functional and undergoing environmental and radiation characterization. A self-contained flight-like module is expected to be completed in 2006. RTIMS provides reconfigurable circuitry and 2 gigabits of error corrected or 1 gigabit of triple redundant digital memory in a small package. RTIMS utilizes circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuitries are stacked into a module of 42.7mm x 42.7mm x 13.00mm. Triple module redundancy, current limiting, configuration scrubbing, and single event function interrupt detection are employed to mitigate radiation effects. The mitigation techniques significantly simplify system design. RTIMS is well suited for deployment in real-time data processing, reconfigurable computing, and memory intensive applications.

Local Control Models of Cardiac Excitation–Contraction Coupling

PubMed Central

Stern, Michael D.; Song, Long-Sheng; Cheng, Heping; Sham, James S.K.; Yang, Huang Tian; Boheler, Kenneth R.; Ríos, Eduardo

1999-01-01

In cardiac muscle, release of activator calcium from the sarcoplasmic reticulum occurs by calcium- induced calcium release through ryanodine receptors (RyRs), which are clustered in a dense, regular, two-dimensional lattice array at the diad junction. We simulated numerically the stochastic dynamics of RyRs and L-type sarcolemmal calcium channels interacting via calcium nano-domains in the junctional cleft. Four putative RyR gating schemes based on single-channel measurements in lipid bilayers all failed to give stable excitation–contraction coupling, due either to insufficiently strong inactivation to terminate locally regenerative calcium-induced calcium release or insufficient cooperativity to discriminate against RyR activation by background calcium. If the ryanodine receptor was represented, instead, by a phenomenological four-state gating scheme, with channel opening resulting from simultaneous binding of two Ca2+ ions, and either calcium-dependent or activation-linked inactivation, the simulations gave a good semiquantitative accounting for the macroscopic features of excitation–contraction coupling. It was possible to restore stability to a model based on a bilayer-derived gating scheme, by introducing allosteric interactions between nearest-neighbor RyRs so as to stabilize the inactivated state and produce cooperativity among calcium binding sites on different RyRs. Such allosteric coupling between RyRs may be a function of the foot process and lattice array, explaining their conservation during evolution. PMID:10051521

Quantum gate-set tomography

NASA Astrophysics Data System (ADS)

Blume-Kohout, Robin

2014-03-01

Quantum information technology is built on (1) physical qubits and (2) precise, accurate quantum logic gates that transform their states. Developing quantum logic gates requires good characterization - both in the development phase, where we need to identify a device's flaws so as to fix them, and in the production phase, where we need to make sure that the device works within specs and predict residual error rates and types. This task falls to quantum state and process tomography. But until recently, protocols for tomography relied on a pre-existing and perfectly calibrated reference frame comprising the measurements (and, for process tomography, input states) used to characterize the device. In practice, these measurements are neither independent nor perfectly known - they are usually implemented via exactly the same gates that we are trying to characterize! In the past year, several partial solutions to this self-consistency problem have been proposed. I will present a framework (gate set tomography, or GST) that addresses and resolves this problem, by self-consistently characterizing an entire set of quantum logic gates on a black-box quantum device. In particular, it contains an explicit closed-form protocol for linear-inversion gate set tomography (LGST), which is immune to both calibration error and technical pathologies like local maxima of the likelihood (which plagued earlier methods). GST also demonstrates significant (multiple orders of magnitude) improvements in efficiency over standard tomography by using data derived from long sequences of gates (much like randomized benchmarking). GST has now been applied to qubit devices in multiple technologies. I will present and discuss results of GST experiments in technologies including a single trapped-ion qubit and a silicon quantum dot qubit. Sandia National Laboratories is a multiprogram laboratory operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL850.

Time-gated luminescence microscopy allowing direct visual inspection of lanthanide-stained microorganisms in background-free condition.

PubMed

Jin, Dayong; Piper, James A

2011-03-15

Application of standard immuno-fluorescence microscopy techniques for detection of rare-event microorganisms in dirty samples is severely limited by autofluorescence of nontarget organisms or other debris. Time-gated detection using gateable array detectors in combination with microsecond-lifetime luminescent bioprobes (usually lanthanide-based) is highly effective in suppression of (nanosecond-lifetime) autofluorescence background; however, the complexity and cost of the instrumentation is a major barrier to application of these techniques to routine diagnostics. We report a practical, low-cost implementation of time-gated luminescence detection in a standard epifluorescence microscope which has been modified to include a high-power pulsed UV light-emitting diode (LED) illumination source and a standard fast chopper inserted in the focal plane behind a microscope eyepiece. Synchronization of the pulsed illumination/gated detection cycle is driven from the clock signal from the chopper. To achieve time-gated luminescence intensities sufficient for direct visual observation, we use high cycle rates, up to 2.5 kHz, taking advantage of the fast switching capabilities of the LED source. We have demonstrated real-time direct-visual inspection of europium-labeled Giardia lamblia cysts in dirty samples and Cryptosporidium parvum oocysts in fruit juice concentrate. The signal-to-background ratio has been enhanced by a factor of 18 in time-gated mode. The availability of low-cost, robust time-gated microscopes will aid development of long-lifetime luminescence bioprobes and accelerate their application in routine laboratory diagnostics.

ICE: A Scalable, Low-Cost FPGA-Based Telescope Signal Processing and Networking System

NASA Astrophysics Data System (ADS)

Bandura, K.; Bender, A. N.; Cliche, J. F.; de Haan, T.; Dobbs, M. A.; Gilbert, A. J.; Griffin, S.; Hsyu, G.; Ittah, D.; Parra, J. Mena; Montgomery, J.; Pinsonneault-Marotte, T.; Siegel, S.; Smecher, G.; Tang, Q. Y.; Vanderlinde, K.; Whitehorn, N.

2016-03-01

We present an overview of the ‘ICE’ hardware and software framework that implements large arrays of interconnected field-programmable gate array (FPGA)-based data acquisition, signal processing and networking nodes economically. The system was conceived for application to radio, millimeter and sub-millimeter telescope readout systems that have requirements beyond typical off-the-shelf processing systems, such as careful control of interference signals produced by the digital electronics, and clocking of all elements in the system from a single precise observatory-derived oscillator. A new generation of telescopes operating at these frequency bands and designed with a vastly increased emphasis on digital signal processing to support their detector multiplexing technology or high-bandwidth correlators — data rates exceeding a terabyte per second — are becoming common. The ICE system is built around a custom FPGA motherboard that makes use of an Xilinx Kintex-7 FPGA and ARM-based co-processor. The system is specialized for specific applications through software, firmware and custom mezzanine daughter boards that interface to the FPGA through the industry-standard FPGA mezzanine card (FMC) specifications. For high density applications, the motherboards are packaged in 16-slot crates with ICE backplanes that implement a low-cost passive full-mesh network between the motherboards in a crate, allow high bandwidth interconnection between crates and enable data offload to a computer cluster. A Python-based control software library automatically detects and operates the hardware in the array. Examples of specific telescope applications of the ICE framework are presented, namely the frequency-multiplexed bolometer readout systems used for the South Pole Telescope (SPT) and Simons Array and the digitizer, F-engine, and networking engine for the Canadian Hydrogen Intensity Mapping Experiment (CHIME) and Hydrogen Intensity and Real-time Analysis eXperiment (HIRAX) radio interferometers.

KSC-00padig055

NASA Image and Video Library

2000-10-31

KENNEDY SPACE CENTER, Fla. -- Perched atop the Mobile Launcher Platform, Space Shuttle Endeavour approaches the gate to Launch Pad 39B. To the right of the pad is a 290-foot tall water tower. Endeavour is scheduled to be launched Nov. 30 at 10:01 p.m. EST on mission STS-97, the sixth construction flight to the International Space Station. Its payload includes the P6 Integrated Truss Structure and a photovoltaic (PV) module, with giant solar arrays that will provide power to the Station. The mission includes two spacewalks to complete the solar array connections

KSC00padig055

NASA Image and Video Library

2000-10-31

KENNEDY SPACE CENTER, Fla. -- Perched atop the Mobile Launcher Platform, Space Shuttle Endeavour approaches the gate to Launch Pad 39B. To the right of the pad is a 290-foot tall water tower. Endeavour is scheduled to be launched Nov. 30 at 10:01 p.m. EST on mission STS-97, the sixth construction flight to the International Space Station. Its payload includes the P6 Integrated Truss Structure and a photovoltaic (PV) module, with giant solar arrays that will provide power to the Station. The mission includes two spacewalks to complete the solar array connections

CMOS minimal array

NASA Astrophysics Data System (ADS)

Janesick, James; Cheng, John; Bishop, Jeanne; Andrews, James T.; Tower, John; Walker, Jeff; Grygon, Mark; Elliot, Tom

2006-08-01

A high performance prototype CMOS imager is introduced. Test data is reviewed for different array formats that utilize 3T photo diode, 5T pinned photo diode and 6T photo gate CMOS pixel architectures. The imager allows several readout modes including progressive scan, snap and windowed operation. The new imager is built on different silicon substrates including very high resistivity epitaxial wafers for deep depletion operation. Data products contained in this paper focus on sensor's read noise, charge capacity, charge transfer efficiency, thermal dark current, RTS dark spikes, QE, pixel cross- talk and on-chip analog circuitry performance.

3D gate-all-around bandgap-engineered SONOS flash memory in vertical silicon pillar with metal gate

NASA Astrophysics Data System (ADS)

Oh, Jae-Sub; Yang, Seong-Dong; Lee, Sang-Youl; Kim, Young-Su; Kang, Min-Ho; Lim, Sung-Kyu; Lee, Hi-Deok; Lee, Ga-Won

2013-08-01

In this paper, a gate-all-around bandgap-engineered silicon-oxide-nitride-oxide-silicon device with a vertical silicon pillar structure and a Ti metal gate are demonstrated for a potential solution to overcome the scaling-down of flash memory device. The devices were fabricated using CMOS-compatible technology and exhibited well-behaved memory characteristics in terms of the program/erase window, retention, and endurance properties. Moreover, the integration of the Ti metal gate demonstrated a significant improvement in the erase characteristics due to the efficient suppression of the electron back tunneling through the blocking oxide.

CIDR

Science.gov Websites

NIH CIDR Program Studies For whole exome sequencing projects, we pretest all samples using a high -density SNP array (>200,000 markers). For custom targeted sequencing, we pretest all samples using a 96 pretest samples using a 96 SNP GoldenGate assay. This extensive pretesting allows us to unambiguously tie

Low-Latency Embedded Vision Processor (LLEVS)

DTIC Science & Technology

2016-03-01

26 3.2.3 Task 3 Projected Performance Analysis of FPGA- based Vision Processor ........... 31 3.2.3.1 Algorithms Latency Analysis ...Programmable Gate Array Custom Hardware for Real- Time Multiresolution Analysis . ............................................... 35...conduct data analysis for performance projections. The data acquired through measurements , simulation and estimation provide the requisite platform for

Achieving High Performance with FPGA-Based Computing

PubMed Central

Herbordt, Martin C.; VanCourt, Tom; Gu, Yongfeng; Sukhwani, Bharat; Conti, Al; Model, Josh; DiSabello, Doug

2011-01-01

Numerous application areas, including bioinformatics and computational biology, demand increasing amounts of processing capability. In many cases, the computation cores and data types are suited to field-programmable gate arrays. The challenge is identifying the design techniques that can extract high performance potential from the FPGA fabric. PMID:21603088

Hardware-based image processing for high-speed inspection of grains

USDA-ARS?s Scientific Manuscript database

A high-speed, low-cost, image-based sorting device was developed to detect and separate grains with slight color differences and small defects on grains The device directly combines a complementary metal–oxide–semiconductor (CMOS) color image sensor with a field-programmable gate array (FPGA) which...

Analysis of Voltage and Current Signal Processing in a Li-ion Battery Management System

DTIC Science & Technology

2010-09-01

SUBJECT TERMS Pulsed Power, Charger, Buck Converter, Field Programmable Gate Array (FPGA), Lithium - ion Batteries 16. PRICE CODE 17. SECURITY...Congressional Research Service. July 31, 2000. [3] F. E. Filler, “A Pulsed Power System Design Using Lithium - ion Batteries and One Charger per Battery

ESD protection design for advanced CMOS

NASA Astrophysics Data System (ADS)

Huang, Jin B.; Wang, Gewen

2001-10-01

ESD effects in integrated circuits have become a major concern as today's technologies shrink to sub-micron/deep- sub-micron dimensions. The thinner gate oxide and shallower junction depth used in the advanced technologies make them very vulnerable to ESD damages. The advanced techniques like silicidation and STI (shallow trench insulation) used for improving other device performances make ESD design even more challenging. For non-silicided technologies, a certain DCGS (drain contact to gate edge spacing) is needed to achieve ESD hardness for nMOS output drivers and nMOS protection transistors. The typical DCGS values are 4-5um and 2-3um for 0.5um and 0.25um CMOS, respectively. The silicidation reduces the ballast resistance provided by DCGS with at least a factor of 10. As a result, scaling of the ESD performance with device width is lost and even zero ESD performance is reported for standard silicided devices. The device level ESD design is focused in this paper, which includes GGNMOS (gate grounded NMOS) and GCNMOS (gate coupled NMOS). The device level ESD testing including TLP (transmission line pulse) is given. Several ESD issues caused by advanced technologies have been pointed out. The possible solutions have been developed and summarized including silicide blocking, process optimization, back-end ballasting, and new protection scheme, dummy gate/n-well resistor ballsting, etc. Some of them require process cost increase, and others provide novel, compact, and simple design but involving royalty/IP (intellectual property) issue. Circuit level ESD design and layout design considerations are covered. The top-level ESD protection strategies are also given.

Bill Gates eyes healthcare market.

PubMed

Dunbar, C

1995-02-01

The entrepreneurial spirit is still top in Bill Gates' mind as he look toward healthcare and other growth industries. Microsoft's CEO has not intention of going the way of other large technology companies that became obsolete before they could compete today.

An addressable quantum dot qubit with fault-tolerant control-fidelity.

PubMed

Veldhorst, M; Hwang, J C C; Yang, C H; Leenstra, A W; de Ronde, B; Dehollain, J P; Muhonen, J T; Hudson, F E; Itoh, K M; Morello, A; Dzurak, A S

2014-12-01

Exciting progress towards spin-based quantum computing has recently been made with qubits realized using nitrogen-vacancy centres in diamond and phosphorus atoms in silicon. For example, long coherence times were made possible by the presence of spin-free isotopes of carbon and silicon. However, despite promising single-atom nanotechnologies, there remain substantial challenges in coupling such qubits and addressing them individually. Conversely, lithographically defined quantum dots have an exchange coupling that can be precisely engineered, but strong coupling to noise has severely limited their dephasing times and control fidelities. Here, we combine the best aspects of both spin qubit schemes and demonstrate a gate-addressable quantum dot qubit in isotopically engineered silicon with a control fidelity of 99.6%, obtained via Clifford-based randomized benchmarking and consistent with that required for fault-tolerant quantum computing. This qubit has dephasing time T2* = 120 μs and coherence time T2 = 28 ms, both orders of magnitude larger than in other types of semiconductor qubit. By gate-voltage-tuning the electron g*-factor we can Stark shift the electron spin resonance frequency by more than 3,000 times the 2.4 kHz electron spin resonance linewidth, providing a direct route to large-scale arrays of addressable high-fidelity qubits that are compatible with existing manufacturing technologies.

Rapid wide-field Mueller matrix polarimetry imaging based on four photoelastic modulators with no moving parts.

PubMed

Alali, Sanaz; Gribble, Adam; Vitkin, I Alex

2016-03-01

A new polarimetry method is demonstrated to image the entire Mueller matrix of a turbid sample using four photoelastic modulators (PEMs) and a charge coupled device (CCD) camera, with no moving parts. Accurate wide-field imaging is enabled with a field-programmable gate array (FPGA) optical gating technique and an evolutionary algorithm (EA) that optimizes imaging times. This technique accurately and rapidly measured the Mueller matrices of air, polarization elements, and turbid phantoms. The system should prove advantageous for Mueller matrix analysis of turbid samples (e.g., biological tissues) over large fields of view, in less than a second.

Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA

PubMed Central

de Souza, Alisson C. D.; Fernandes, Marcelo A. C.

2014-01-01

This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained online with a least mean square (LMS) algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate and interpolation using the sine function were also analyzed in a hardware implementation. The entire project was developed using the System Generator platform (Xilinx), with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA. PMID:25268918

Nano Peltier cooling device from geometric effects using a single graphene nanoribbon

NASA Astrophysics Data System (ADS)

Li, Wan-Ju; Yao, Dao-Xin; Carlson, Erica

2012-02-01

Based on the phenomenon of curvature-induced doping in graphene we propose a class of Peltier cooling devices, produced by geometrical effects, without gating. We show how a graphene nanoribbon laid on an array of curved nano cylinders can be used to create a targeted cooling device. Using theoretical calculations and experimental inputs, we predict that the cooling power of such a device can approach 1kW/cm^2, on par with the best known techniques using standard lithography methods. The structure proposed here helps pave the way toward designing graphene electronics which use geometry rather than gating to control devices.

Addressable Inverter Matrix Tests Integrated-Circuit Wafer

NASA Technical Reports Server (NTRS)

Buehler, Martin G.

1988-01-01

Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

Electrostatic modulation of periodic potentials in a two-dimensional electron gas: From antidot lattice to quantum dot lattice

DOE Office of Scientific and Technical Information (OSTI.GOV)

Goswami, Srijit; Aamir, Mohammed Ali; Shamim, Saquib

2013-12-04

We use a dual gated device structure to introduce a gate-tuneable periodic potential in a GaAs/AlGaAs two dimensional electron gas (2DEG). Using only a suitable choice of gate voltages we can controllably alter the potential landscape of the bare 2DEG, inducing either a periodic array of antidots or quantum dots. Antidots are artificial scattering centers, and therefore allow for a study of electron dynamics. In particular, we show that the thermovoltage of an antidot lattice is particularly sensitive to the relative positions of the Fermi level and the antidot potential. A quantum dot lattice, on the other hand, provides themore » opportunity to study correlated electron physics. We find that its current-voltage characteristics display a voltage threshold, as well as a power law scaling, indicative of collective Coulomb blockade in a disordered background.« less

Architecture and applications of a high resolution gated SPAD image sensor

PubMed Central

Burri, Samuel; Maruyama, Yuki; Michalet, Xavier; Regazzoni, Francesco; Bruschini, Claudio; Charbon, Edoardo

2014-01-01

We present the architecture and three applications of the largest resolution image sensor based on single-photon avalanche diodes (SPADs) published to date. The sensor, fabricated in a high-voltage CMOS process, has a resolution of 512 × 128 pixels and a pitch of 24 μm. The fill-factor of 5% can be increased to 30% with the use of microlenses. For precise control of the exposure and for time-resolved imaging, we use fast global gating signals to define exposure windows as small as 4 ns. The uniformity of the gate edges location is ∼140 ps (FWHM) over the whole array, while in-pixel digital counting enables frame rates as high as 156 kfps. Currently, our camera is used as a highly sensitive sensor with high temporal resolution, for applications ranging from fluorescence lifetime measurements to fluorescence correlation spectroscopy and generation of true random numbers. PMID:25090572

Investigation of ablation of thin foil aluminum ribbon array at 1.5 MA

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ye, Fan, E-mail: yefan1931@126.com; Li, Zhenghong; Chen, Faxin

We present experimental studies of initiation and ablation of a thin foil aluminum ribbon array at the 1.5 MA current level. In contrast to the previous work, we employ ribbon arrays with different ribbon gap parameters to investigate how this affects plasma initiation and foil ablation. Gated narrowband ultraviolet imaging indicated that the current was disorderly distributed at early period of discharge. But later on, it became axially stable and azimuthally symmetrical even for load with a gap as small as 0.1 mm. Using magnetic field probes installed inside and outside the array, we also observed that precursor current at positionsmore » with a distance of less than 2.7 mm to the central axis for 4-mm-radius arrays decreased when ribbon gap became small. Results of 0.2 mm gap ribbon array showed an evidence that ribbons can be merged. These observations imply that thin foil ribbon arrays may have potential applications in z-pinch experiments on large scale pulsed power facilities.« less

Assisted extraction of the energy level spacings and lever arms in direct current bias measurements of one-dimensional quantum wires, using an image recognition routine

NASA Astrophysics Data System (ADS)

Lesage, A. A. J.; Smith, L. W.; Al-Taie, H.; See, P.; Griffiths, J. P.; Farrer, I.; Jones, G. A. C.; Ritchie, D. A.; Kelly, M. J.; Smith, C. G.

2015-01-01

A multiplexer technique is used to individually measure an array of 256 split gates on a single GaAs/AlGaAs heterostructure. This results in the generation of large volumes of data, which requires the development of automated data analysis routines. An algorithm is developed to find the spacing between discrete energy levels, which form due to transverse confinement from the split gate. The lever arm, which relates split gate voltage to energy, is also found from the measured data. This reduces the time spent on the analysis. Comparison with estimates obtained visually shows that the algorithm returns reliable results for subband spacing of split gates measured at 1.4 K. The routine is also used to assess direct current bias spectroscopy measurements at lower temperatures (50 mK). This technique is versatile and can be extended to other types of measurements. For example, it is used to extract the magnetic field at which Zeeman-split 1D subbands cross one another.

Solar array technology evaluation program for SEPS (Solar Electrical Propulsion Stage)

NASA Technical Reports Server (NTRS)

1974-01-01

An evaluation of the technology and the development of a preliminary design for a 25 kilowatt solar array system for solar electric propulsion are discussed. The solar array has a power to weight ratio of 65 watts per kilogram. The solar array system is composed of two wings. Each wing consists of a solar array blanket, a blanket launch storage container, an extension/retraction mast assembly, a blanket tensioning system, an array electrical harness, and hardware for supporting the system for launch and in the operating position. The technology evaluation was performed to assess the applicable solar array state-of-the-art and to define supporting research necessary to achieve technology readiness for meeting the solar electric propulsion system solar array design requirements.

Development and implementation of a highly-multiplexed SNP array for genetic mapping in maritime pine and comparative mapping with loblolly pine

PubMed Central

2011-01-01

Background Single nucleotide polymorphisms (SNPs) are the most abundant source of genetic variation among individuals of a species. New genotyping technologies allow examining hundreds to thousands of SNPs in a single reaction for a wide range of applications such as genetic diversity analysis, linkage mapping, fine QTL mapping, association studies, marker-assisted or genome-wide selection. In this paper, we evaluated the potential of highly-multiplexed SNP genotyping for genetic mapping in maritime pine (Pinus pinaster Ait.), the main conifer used for commercial plantation in southwestern Europe. Results We designed a custom GoldenGate assay for 1,536 SNPs detected through the resequencing of gene fragments (707 in vitro SNPs/Indels) and from Sanger-derived Expressed Sequenced Tags assembled into a unigene set (829 in silico SNPs/Indels). Offspring from three-generation outbred (G2) and inbred (F2) pedigrees were genotyped. The success rate of the assay was 63.6% and 74.8% for in silico and in vitro SNPs, respectively. A genotyping error rate of 0.4% was further estimated from segregating data of SNPs belonging to the same gene. Overall, 394 SNPs were available for mapping. A total of 287 SNPs were integrated with previously mapped markers in the G2 parental maps, while 179 SNPs were localized on the map generated from the analysis of the F2 progeny. Based on 98 markers segregating in both pedigrees, we were able to generate a consensus map comprising 357 SNPs from 292 different loci. Finally, the analysis of sequence homology between mapped markers and their orthologs in a Pinus taeda linkage map, made it possible to align the 12 linkage groups of both species. Conclusions Our results show that the GoldenGate assay can be used successfully for high-throughput SNP genotyping in maritime pine, a conifer species that has a genome seven times the size of the human genome. This SNP-array will be extended thanks to recent sequencing effort using new generation sequencing technologies and will include SNPs from comparative orthologous sequences that were identified in the present study, providing a wider collection of anchor points for comparative genomics among the conifers. PMID:21767361

Integration of digital signal processing technologies with pulsed electron paramagnetic resonance imaging

PubMed Central

Pursley, Randall H.; Salem, Ghadi; Devasahayam, Nallathamby; Subramanian, Sankaran; Koscielniak, Janusz; Krishna, Murali C.; Pohida, Thomas J.

2006-01-01

The integration of modern data acquisition and digital signal processing (DSP) technologies with Fourier transform electron paramagnetic resonance (FT-EPR) imaging at radiofrequencies (RF) is described. The FT-EPR system operates at a Larmor frequency (Lf) of 300 MHz to facilitate in vivo studies. This relatively low frequency Lf, in conjunction with our ~10 MHz signal bandwidth, enables the use of direct free induction decay time-locked subsampling (TLSS). This particular technique provides advantages by eliminating the traditional analog intermediate frequency downconversion stage along with the corresponding noise sources. TLSS also results in manageable sample rates that facilitate the design of DSP-based data acquisition and image processing platforms. More specifically, we utilize a high-speed field programmable gate array (FPGA) and a DSP processor to perform advanced real-time signal and image processing. The migration to a DSP-based configuration offers the benefits of improved EPR system performance, as well as increased adaptability to various EPR system configurations (i.e., software configurable systems instead of hardware reconfigurations). The required modifications to the FT-EPR system design are described, with focus on the addition of DSP technologies including the application-specific hardware, software, and firmware developed for the FPGA and DSP processor. The first results of using real-time DSP technologies in conjunction with direct detection bandpass sampling to implement EPR imaging at RF frequencies are presented. PMID:16243552

Optical Multi-Gas Monitor Technology Demonstration on the International Space Station

NASA Technical Reports Server (NTRS)

Pilgrim, Jeffrey S.; Wood, William R.; Casias, Miguel E.; Vakhtin, Andrei B.; Johnson, Michael D.; Mudgett, Paul D.

2014-01-01

The International Space Station (ISS) employs a suite of portable and permanently located gas monitors to insure crew health and safety. These sensors are tasked with functions ranging from fixed mass spectrometer based major constituents analysis to portable electrochemical sensor based combustion product monitoring. An all optical multigas sensor is being developed that can provide the specificity of a mass spectrometer with the portability of an electrochemical cell. The technology, developed under the Small Business Innovation Research program, allows for an architecture that is rugged, compact and low power. A four gas version called the Multi-Gas Monitor was launched to ISS in November 2013 aboard Soyuz and activated in February 2014. The portable instrument is comprised of a major constituents analyzer (water vapor, carbon dioxide, oxygen) and high dynamic range real-time ammonia sensor. All species are sensed inside the same enhanced path length optical cell with a separate vertical cavity surface emitting laser (VCSEL) targeted at each species. The prototype is controlled digitally with a field-programmable gate array/microcontroller architecture. The optical and electronic approaches are designed for scalability and future versions could add three important acid gases and carbon monoxide combustion product gases to the four species already sensed. Results obtained to date from the technology demonstration on ISS are presented and discussed.

Moving belt metal detector

NASA Astrophysics Data System (ADS)

Nelson, Carl V.; Mendat, Deborah P.; Huynh, Toan B.

2006-05-01

The Johns Hopkins University Applied Physics Laboratory (APL) has developed a prototype metal detection survey system that will increase the search speed of conventional technology while maintaining high sensitivity. Higher search speeds will reduce the time to clear roads of landmines and improvised explosive devices (IED) and to locate unexploded ordnance (UXO) at Base Realignment and Closure (BRAC) sites, thus reducing remediation costs. The new survey sensor system is called the moving belt metal detector (MBMD) and operates by both increasing sensor speed over the ground while maintaining adequate sensor dwell time over the target for good signal-to-noise ratio (SNR) and reducing motion-induced sensor noise. The MBMD uses an array of metal detection sensors mounted on a flexible belt similar to a tank track. The belt motion is synchronized with the forward survey speed so individual sensor elements remain stationary relative to the ground. A single pulsed transmitter coil is configured to provide a uniform magnetic field along the length of the receivers in ground contact. Individual time-domain electromagnetic induction (EMI) receivers are designed to sense a single time-gate measurement of the total metal content. Each sensor module consists of a receiver coil, amplifier, digitizing electronics and a low power UHF wireless transmitter. This paper presents the survey system design concepts and metal detection data from various targets at several survey speeds. Although the laboratory prototype is designed to demonstrate metal detection survey speeds up to 10 m/s, higher speeds are achievable with a larger sensor array. In addition, the concept can be adapted to work with other sensor technologies not previously considered for moving platforms.

The Implementation of Advanced Solar Array Technology in Future NASA Missions

NASA Technical Reports Server (NTRS)

Piszczor, Michael F.; Kerslake, Thomas W.; Hoffman, David J.; White, Steve; Douglas, Mark; Spence, Brian; Jones, P. Alan

2003-01-01

Advanced solar array technology is expected to be critical in achieving the mission goals on many future NASA space flight programs. Current PV cell development programs offer significant potential and performance improvements. However, in order to achieve the performance improvements promised by these devices, new solar array structures must be designed and developed to accommodate these new PV cell technologies. This paper will address the use of advanced solar array technology in future NASA space missions and specifically look at how newer solar cell technologies impact solar array designs and overall power system performance.

Fabrication of FORTIS

NASA Astrophysics Data System (ADS)

McCandliss, Stephan R.; Fleming, Brian; Kaiser, Mary Elizabeth; Kruk, Jeffrey; Feldman, Paul D.; Kutyrev, Alexander S.; Li, Mary J.; Goodwin, Phillip A.; Rapchun, David; Lyness, Eric; Brown, Ari D.; Moseley, Harvey; Siegmund, Oswald; Vallerga, John

2010-07-01

The Johns Hopkins University sounding rocket group is building the Far-ultraviolet Off Rowland-circle Telescope for Imaging and Spectroscopy (FORTIS), which is a Gregorian telescope with rulings on the secondary mirror. FORTIS will be launched on a sounding rocket from White Sand Missile Range to study the relationship between Lyman alpha escape and the local gas-to-dust ratio in star forming galaxies with non-zero redshifts. It is designed to acquire images of a 30' x 30' field and provide fully redundant "on-the-fly" spectral acquisition of 43 separate targets in the field with a bandpass of 900 - 1800 Angstroms. FORTIS is an enabling scientific and technical activity for future cutting edge far- and near-uv survey missions seeking to: search for Lyman continuum radiation leaking from star forming galaxies, determine the epoch of He II reionization and characterize baryon acoustic oscillations using the Lyman forest. In addition to the high efficiency "two bounce" dual-order spectro-telescope design, FORTIS incorporates a number of innovative technologies including: an image dissecting microshutter array developed by GSFC; a large area (~ 45 mm x 170 mm) microchannel plate detector with central imaging and "outrigger" spectral channels provided by Sensor Sciences; and an autonomous targeting microprocessor incorporating commercially available field programable gate arrays. We discuss progress to date in developing our pathfinder instrument.

Planarized thick copper gate polycrystalline silicon thin film transistors for ultra-large AMOLED displays

NASA Astrophysics Data System (ADS)

Yun, Seung Jae; Lee, Yong Woo; Son, Se Wan; Byun, Chang Woo; Reddy, A. Mallikarjuna; Joo, Seung Ki

2012-08-01

A planarized thick copper (Cu) gate low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) is fabricated for ultra-large active-matrix organic light-emitting diode (AMOLED) displays. We introduce a damascene and chemical mechanical polishing process to embed a planarized Cu gate of 500 nm thickness into a trench and Si3N4/SiO2 multilayer gate insulator, to prevent the Cu gate from diffusing into the silicon (Si) layer at 550°C, and metal-induced lateral crystallization (MILC) technology to crystallize the amorphous Si layer. A poly-Si TFT with planarized thick Cu gate exhibits a field effect mobility of 5 cm2/Vs and a threshold voltage of -9 V, and a subthreshold swing (S) of 1.4 V/dec.

Single attosecond pulse generation by using plasmon-driven double optical gating technology in crossed metal nanostructures

NASA Astrophysics Data System (ADS)

Feng, Liqiang; Liu, Katheryn

2018-05-01

An effective method to obtain the single attosecond pulses (SAPs) by using the multi-cycle plasmon-driven double optical gating (DOG) technology in the specifically designed metal nanostructures has been proposed and investigated. It is found that with the introduction of the crossed metal nanostructures along the driven and the gating polarization directions, not only the harmonic cutoff can be extended, but also the efficient high-order harmonic generation (HHG) at the very highest orders occurs only at one side of the region inside the nanostructure. As a result, a 93 eV supercontinuum with the near stable phase can be found. Further, by properly introducing an ultraviolet (UV) pulse into the driven laser polarization direction (which is defined as the DOG), the harmonic yield can be enhanced by two orders of magnitude in comparison with the singe polarization gating (PG) technology. However, as the polarized angle or the ellipticity of the UV pulse increase, the enhancement of the harmonic yield is slightly reduced. Finally, by superposing the selected harmonics from the DOG scheme, a 30 as SAP with intensity enhancement of two orders of magnitude can be obtained.

Ryanodine receptor gating controls generation of diastolic calcium waves in cardiac myocytes

PubMed Central

Petrovič, Pavol; Valent, Ivan; Cocherová, Elena; Pavelková, Jana

2015-01-01

The role of cardiac ryanodine receptor (RyR) gating in the initiation and propagation of calcium waves was investigated using a mathematical model comprising a stochastic description of RyR gating and a deterministic description of calcium diffusion and sequestration. We used a one-dimensional array of equidistantly spaced RyR clusters, representing the confocal scanning line, to simulate the formation of calcium sparks. Our model provided an excellent description of the calcium dependence of the frequency of diastolic calcium sparks and of the increased tendency for the production of calcium waves after a decrease in cytosolic calcium buffering. We developed a hypothesis relating changes in the propensity to form calcium waves to changes of RyR gating and tested it by simulation. With a realistic RyR gating model, increased ability of RyR to be activated by Ca2+ strongly increased the propensity for generation of calcium waves at low (0.05–0.1-µM) calcium concentrations but only slightly at high (0.2–0.4-µM) calcium concentrations. Changes in RyR gating altered calcium wave formation by changing the calcium sensitivity of spontaneous calcium spark activation and/or the average number of open RyRs in spontaneous calcium sparks. Gating changes that did not affect RyR activation by Ca2+ had only a weak effect on the propensity to form calcium waves, even if they strongly increased calcium spark frequency. Calcium waves induced by modulating the properties of the RyR activation site could be suppressed by inhibiting the spontaneous opening of the RyR. These data can explain the increased tendency for production of calcium waves under conditions when RyR gating is altered in cardiac diseases. PMID:26009544

Controllable Hysteresis and Threshold Voltage of Single-Walled Carbon Nano-tube Transistors with Ferroelectric Polymer Top-Gate Insulators

PubMed Central

Sun, Yi-Lin; Xie, Dan; Xu, Jian-Long; Zhang, Cheng; Dai, Rui-Xuan; Li, Xian; Meng, Xiang-Jian; Zhu, Hong-Wei

2016-01-01

Double-gated field effect transistors have been fabricated using the SWCNT networks as channel layer and the organic ferroelectric P(VDF-TrFE) film spin-coated as top gate insulators. Standard photolithography process has been adopted to achieve the patterning of organic P(VDF-TrFE) films and top-gate electrodes, which is compatible with conventional CMOS process technology. An effective way for modulating the threshold voltage in the channel of P(VDF-TrFE) top-gate transistors under polarization has been reported. The introduction of functional P(VDF-TrFE) gate dielectric also provides us an alternative method to suppress the initial hysteresis of SWCNT networks and obtain a controllable ferroelectric hysteresis behavior. Applied bottom gate voltage has been found to be another effective way to highly control the threshold voltage of the networked SWCNTs based FETs by electrostatic doping effect. PMID:26980284

Photonic ququart logic assisted by the cavity-QED system.

PubMed

Luo, Ming-Xing; Deng, Yun; Li, Hui-Ran; Ma, Song-Ya

2015-08-14

Universal quantum logic gates are important elements for a quantum computer. In contrast to previous constructions of qubit systems, we investigate the possibility of ququart systems (four-dimensional states) dependent on two DOFs of photon systems. We propose some useful one-parameter four-dimensional quantum transformations for the construction of universal ququart logic gates. The interface between the spin of a photon and an electron spin confined in a quantum dot embedded in a microcavity is applied to build universal ququart logic gates on the photon system with two freedoms. Our elementary controlled-ququart gates cost no more than 8 CNOT gates in a qubit system, which is far less than the 104 CNOT gates required for a general four-qubit logic gate. The ququart logic is also used to generate useful hyperentanglements and hyperentanglement-assisted quantum error-correcting code, which may be available in modern physical technology.

Photonic ququart logic assisted by the cavity-QED system

PubMed Central

Luo, Ming-Xing; Deng, Yun; Li, Hui-Ran; Ma, Song-Ya

2015-01-01

Universal quantum logic gates are important elements for a quantum computer. In contrast to previous constructions of qubit systems, we investigate the possibility of ququart systems (four-dimensional states) dependent on two DOFs of photon systems. We propose some useful one-parameter four-dimensional quantum transformations for the construction of universal ququart logic gates. The interface between the spin of a photon and an electron spin confined in a quantum dot embedded in a microcavity is applied to build universal ququart logic gates on the photon system with two freedoms. Our elementary controlled-ququart gates cost no more than 8 CNOT gates in a qubit system, which is far less than the 104 CNOT gates required for a general four-qubit logic gate. The ququart logic is also used to generate useful hyperentanglements and hyperentanglement-assisted quantum error-correcting code, which may be available in modern physical technology. PMID:26272869

Solution for the nonuniformity correction of infrared focal plane arrays.

PubMed

Zhou, Huixin; Liu, Shangqian; Lai, Rui; Wang, Dabao; Cheng, Yubao

2005-05-20

Based on the S-curve model of the detector response of infrared focal plan arrays (IRFPAs), an improved two-point correction algorithm is presented. The algorithm first transforms the nonlinear image data into linear data and then uses the normal two-point algorithm to correct the linear data. The algorithm can effectively overcome the influence of nonlinearity of the detector's response, and it enlarges the correction precision and the dynamic range of the response. A real-time imaging-signal-processing system for IRFPAs that is based on a digital signal processor and field-programmable gate arrays is also presented. The nonuniformity correction capability of the presented solution is validated by experimental imaging procedures of a 128 x 128 pixel IRFPA camera prototype.

A wideband analog correlator system for AMiBA

NASA Astrophysics Data System (ADS)

Li, Chao-Te; Kubo, Derek; Han, Chih-Chiang; Chen, Chung-Cheng; Chen, Ming-Tang; Lien, Chun-Hsien; Wang, Huei; Wei, Ray-Ming; Yang, Chia-Hsiang; Chiueh, Tzi-Dar; Peterson, Jeffrey; Kesteven, Michael; Wilson, Warwick

2004-10-01

A wideband correlator system with a bandwidth of 16 GHz or more is required for Array for Microwave Background Anisotropy (AMiBA) to achieve the sensitivity of 10μK in one hour of observation. Double-balanced diode mixers were used as multipliers in 4-lag correlator modules. Several wideband modules were developed for IF signal distribution between receivers and correlators. Correlator outputs were amplified, and digitized by voltage-to-frequency converters. Data acquisition circuits were designed using field programmable gate arrays (FPGA). Subsequent data transfer and control software were based on the configuration for Australia Telescope Compact Array. Transform matrix method will be adopted during calibration to take into account the phase and amplitude variations of analog devices across the passband.

SU-F-T-518: Development and Characterization of a Gated Treatment System Implemented with An In-House Optical Tracking System and the Elekta Response Interface

DOE Office of Scientific and Technical Information (OSTI.GOV)

Barraclough, B; Park, J; Li, F

2016-06-15

Purpose: To report the development and characterization of the first in-house gating system implemented with an optical tracking system (OTS) and the Elekta Response™ interface. Methods: The Response™ connects a patient tracking system with a linac, enabling the tracking system to control radiation delivery. The developed system uses an in-house OTS to monitor patient breathing. The OTS consists of two infrared-based cameras, tracking markers affixed on patient. It achieves gated or breath-held (BH) treatment by calling beam ON/OFF functions in the Response™ dynamic-link library (DLL). A 4D motion phantom was used to evaluate its dosimetric and time delay characteristics. Twomore » FF- and two FFF-IMRT beams were delivered in non-gated, BH and gated mode. The sinusoidal gating signal had a 6 sec period and 15 mm amplitude. The duty cycle included 10%, 20%, 30% and 50%. The BH signal was adapted from the sinusoidal wave by inserting 15 sec BHs. Each delivery was measured with a 2D diode array (MapCHECK™) and compared with the non-gated delivery using gamma analysis (3%). The beam ON/OFF time was captured using the service graphing utility of the linac. Results: The gated treatments were successfully delivered except the 10% duty cycle. The BH delivery had perfect agreement (100%) with non-gated delivery; the agreement of gated delivery decreased from 99% to 88% as duty cycle reduced from 50% to 20%. The beam on/off delay was on average 0.25/0.06 sec. The delivery time for the 50%, 30% and 20% duty cycle increased by 29%, 71% and 139%, respectively. No dosimetric or time delay difference was noticed between FF- and FFF-IMRT beams. Conclusion: The in-house gating system was successfully developed with dosimetric and time delay characteristics in line with published results for commercial systems. It will be an important platform for further research and clinical development of gated treatment.« less

Dose verification for respiratory-gated volumetric modulated arc therapy (VMAT)

PubMed Central

Qian, Jianguo; Xing, Lei; Liu, Wu; Luxton, Gary

2011-01-01

A novel commercial medical linac system (TrueBeam™, Varian Medical Systems, Palo Alto, CA) allows respiratory-gated volumetric modulated arc therapy (VMAT), a new modality for treating moving tumors with high precision and improved accuracy by allowing for regular motion associated with a patient's breathing during VMAT delivery. The purpose of this work is to adapt a previously-developed dose reconstruction technique to evaluate the fidelity of VMAT treatment during gated delivery under clinic-relevant periodic motion related to patient breathing. A Varian TrueBeam system was used in this study. VMAT plans were created for three patients with lung or pancreas tumors. Conventional 6 MV and 15 MV beams with flattening filter and high dose-rate 10 MV beams with no flattening filter were used in these plans. Each patient plan was delivered to a phantom first without gating and then with gating for three simulated respiratory periods (3, 4.5 and 6 seconds). Using the adapted log file-based dose reconstruction procedure supplemented with ion chamber array (Seven29™, PTW, Freiburg, Germany) measurements, the delivered dose was used to evaluate the fidelity of gated VMAT delivery. Comparison of Seven29 measurements with and without gating showed good agreement with gamma-index passing rates above 99% for 1%/1mm dose accuracy/distance-to-agreement criteria. With original plans as reference, gamma-index passing rates were 100% for the reconstituted plans (1%/1 mm criteria) and 93.5–100% for gated Seven29 measurements (3%/3 mm criteria). In the presence of leaf error deliberately introduced into the gated delivery of a pancreas patient plan, both dose reconstruction and Seven29 measurement consistently indicated substantial dosimetric differences from the original plan. In summary, a dose reconstruction procedure was demonstrated for evaluating the accuracy of respiratory-gated VMAT delivery. This technique showed that under clinical operation, the TrueBeam system faithfully realized treatment plans with gated delivery. This methodology affords a useful tool for machine and patient-specific quality assurance of the newly available respiratory-gated VMAT. PMID:21753232

Reversibility and energy dissipation in adiabatic superconductor logic.

PubMed

Takeuchi, Naoki; Yamanashi, Yuki; Yoshikawa, Nobuyuki

2017-03-06

Reversible computing is considered to be a key technology to achieve an extremely high energy efficiency in future computers. In this study, we investigated the relationship between reversibility and energy dissipation in adiabatic superconductor logic. We analyzed the evolution of phase differences of Josephson junctions in the reversible quantum-flux-parametron (RQFP) gate and confirmed that the phase differences can change time reversibly, which indicates that the RQFP gate is physically, as well as logically, reversible. We calculated energy dissipation required for the RQFP gate to perform a logic operation and numerically demonstrated that the energy dissipation can fall below the thermal limit, or the Landauer bound, by lowering operation frequencies. We also investigated the 1-bit-erasure gate as a logically irreversible gate and the quasi-RQFP gate as a physically irreversible gate. We calculated the energy dissipation of these irreversible gates and showed that the energy dissipation of these gate is dominated by non-adiabatic state changes, which are induced by unwanted interactions between gates due to logical or physical irreversibility. Our results show that, in reversible computing using adiabatic superconductor logic, logical and physical reversibility are required to achieve energy dissipation smaller than the Landauer bound without non-adiabatic processes caused by gate interactions.

An Ultra Low Cost Wireless Communications Laboratory for Education and Research

ERIC Educational Resources Information Center

Linn, Y.

2012-01-01

This paper presents an ultra-low-cost wireless communications laboratory that is based on a commercial off-the-shelf field programmable gate array (FPGA) development board that is both inexpensive and available worldwide. The total cost of the laboratory is under USD $200, but it includes complete transmission, channel emulation, reception…

Commercial Parts Radiation Testing

DTIC Science & Technology

2015-01-13

New Mexico’s COSMIAC Center performed radiation testing on a series of operational amplifiers, microcontrollers and microprocessor. The...commercial microcontroller and microprocessor equipment. The team would develop a list of the most promising commercial parts that might be utilized to...parts will include microprocessors, microcontrollers and memory modules. In addition, Field Programmable Gate Arrays (FPGAs) will also be chosen

Digital Fingerprinting of Field Programmable Gate Arrays

DTIC Science & Technology

2008-03-01

48 vii Page Appendix B . Tranistional Sampling Outputs . . . . . . . . . . . . . . 49 Appendix C. VHDL Entities...cumulative sampling outputs by pin . . . . . . . . . . . 48 B .1. FPGA outputs for Sample 0, Clk 18 . . . . . . . . . . . . . . . 49 B .2. FPGA outputs for...Sample 0, Clk 19 . . . . . . . . . . . . . . . 49 B .3. FPGA outputs for Sample 0, Clk 21 . . . . . . . . . . . . . . . 50 B .4. FPGA outputs for Sample

High altitude subsonic parachute field programmable gate array

NASA Technical Reports Server (NTRS)

Kowalski, James E.; Gromov, Konstantin; Konefat, Edward H.

2005-01-01

This paper describes a rapid, top down requirements-driven design of an FPGA used in an Earth qualification test program for a new Mars subsonic parachute. The FPGA is used to process and control storage of telemetry data from multiple sensors throughout; launch, ascent, deployment and descent phases of the subsonic parachute test.

Design for Review - Applying Lessons Learned to Improve the FPGA Review Process

NASA Technical Reports Server (NTRS)

Figueiredo, Marco A.; Li, Kenneth E.

2014-01-01

Flight Field Programmable Gate Array (FPGA) designs are required to be independently reviewed. This paper provides recommendations to Flight FPGA designers to properly prepare their designs for review in order to facilitate the review process, and reduce the impact of the review time in the overall project schedule.

Evaluating the Instructional Sensitivity of Four States' Student Achievement Tests

ERIC Educational Resources Information Center

Polikoff, Morgan S.

2016-01-01

As state tests of student achievement are used for an increasingly wide array of high- and low-stakes purposes, evaluating their instructional sensitivity is essential. This article uses data from the Bill and Melinda Gates Foundation's Measures of Effective Project to examine the instructional sensitivity of 4 states' mathematics and English…

An Analysis of Heavy-Ion Single Event Effects for a Variety of Finite State-Machine Mitigation Strategies

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; Label, Kenneth A.; Kim, Hak; Phan, Anthony; Seidleck, Christina

2014-01-01

Finite state-machines (FSMs) are used to control operational flow in application specific integrated circuits (ASICs) and field programmable gate array (FPGA) devices. Because of their ease of interpretation, FSMs simplify the design and verification process and consequently are significant components in a synchronous design.

A self-timed multipurpose delay sensor for Field Programmable Gate Arrays (FPGAs).

PubMed

Osuna, Carlos Gómez; Ituero, Pablo; López-Vallejo, Marisa

2013-12-20

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor's measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of  ±0.67 °C, over the range of 20-100 °C, employing 20 logic elements with a 2-point calibration.

Synchronized operation by field programmable gate array based signal controller for the Thomson scattering diagnostic system in KSTAR.

PubMed

Lee, W R; Kim, H S; Park, M K; Lee, J H; Kim, K H

2012-09-01

The Thomson scattering diagnostic system is successfully installed in the Korea Superconducting Tokamak Advanced Research (KSTAR) facility. We got the electron temperature and electron density data for the first time in 2011, 4th campaign using a field programmable gate array (FPGA) based signal control board. It operates as a signal generator, a detector, a controller, and a time measuring device. This board produces two configurable trigger pulses to operate Nd:YAG laser system and receives a laser beam detection signal from a photodiode detector. It allows a trigger pulse to be delivered to a time delay module to make a scattered signal measurement, measuring an asynchronous time value between the KSTAR timing board and the laser system injection signal. All functions are controlled by the embedded processor running on operating system within a single FPGA. It provides Ethernet communication interface and is configured with standard middleware to integrate with KSTAR. This controller has operated for two experimental campaigns including commissioning and performed the reconfiguration of logic designs to accommodate varying experimental situation without hardware rebuilding.

Field programmable gate array based fuzzy neural signal processing system for differential diagnosis of QRS complex tachycardia and tachyarrhythmia in noisy ECG signals.

PubMed

Chowdhury, Shubhajit Roy

2012-04-01

The paper reports of a Field Programmable Gate Array (FPGA) based embedded system for detection of QRS complex in a noisy electrocardiogram (ECG) signal and thereafter differential diagnosis of tachycardia and tachyarrhythmia. The QRS complex has been detected after application of entropy measure of fuzziness to build a detection function of ECG signal, which has been previously filtered to remove power line interference and base line wander. Using the detected QRS complexes, differential diagnosis of tachycardia and tachyarrhythmia has been performed. The entire algorithm has been realized in hardware on an FPGA. Using the standard CSE ECG database, the algorithm performed highly effectively. The performance of the algorithm in respect of QRS detection with sensitivity (Se) of 99.74% and accuracy of 99.5% is achieved when tested using single channel ECG with entropy criteria. The performance of the QRS detection system has been compared and found to be better than most of the QRS detection systems available in literature. Using the system, 200 patients have been diagnosed with an accuracy of 98.5%.

A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs)

PubMed Central

Osuna, Carlos Gómez; Ituero, Pablo; López-Vallejo, Marisa

2014-01-01

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor's measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of ±0.67 °C, over the range of 20–100 °C, employing 20 logic elements with a 2-point calibration. PMID:24361927

An Intelligent Architecture Based on Field Programmable Gate Arrays Designed to Detect Moving Objects by Using Principal Component Analysis

PubMed Central

Bravo, Ignacio; Mazo, Manuel; Lázaro, José L.; Gardel, Alfredo; Jiménez, Pedro; Pizarro, Daniel

2010-01-01

This paper presents a complete implementation of the Principal Component Analysis (PCA) algorithm in Field Programmable Gate Array (FPGA) devices applied to high rate background segmentation of images. The classical sequential execution of different parts of the PCA algorithm has been parallelized. This parallelization has led to the specific development and implementation in hardware of the different stages of PCA, such as computation of the correlation matrix, matrix diagonalization using the Jacobi method and subspace projections of images. On the application side, the paper presents a motion detection algorithm, also entirely implemented on the FPGA, and based on the developed PCA core. This consists of dynamically thresholding the differences between the input image and the one obtained by expressing the input image using the PCA linear subspace previously obtained as a background model. The proposal achieves a high ratio of processed images (up to 120 frames per second) and high quality segmentation results, with a completely embedded and reliable hardware architecture based on commercial CMOS sensors and FPGA devices. PMID:22163406

An intelligent architecture based on Field Programmable Gate Arrays designed to detect moving objects by using Principal Component Analysis.

PubMed

Bravo, Ignacio; Mazo, Manuel; Lázaro, José L; Gardel, Alfredo; Jiménez, Pedro; Pizarro, Daniel

2010-01-01

This paper presents a complete implementation of the Principal Component Analysis (PCA) algorithm in Field Programmable Gate Array (FPGA) devices applied to high rate background segmentation of images. The classical sequential execution of different parts of the PCA algorithm has been parallelized. This parallelization has led to the specific development and implementation in hardware of the different stages of PCA, such as computation of the correlation matrix, matrix diagonalization using the Jacobi method and subspace projections of images. On the application side, the paper presents a motion detection algorithm, also entirely implemented on the FPGA, and based on the developed PCA core. This consists of dynamically thresholding the differences between the input image and the one obtained by expressing the input image using the PCA linear subspace previously obtained as a background model. The proposal achieves a high ratio of processed images (up to 120 frames per second) and high quality segmentation results, with a completely embedded and reliable hardware architecture based on commercial CMOS sensors and FPGA devices.

The discrete Fourier transform algorithm for determining decay constants—Implementation using a field programmable gate array

NASA Astrophysics Data System (ADS)

Bostrom, G.; Atkinson, D.; Rice, A.

2015-04-01

Cavity ringdown spectroscopy (CRDS) uses the exponential decay constant of light exiting a high-finesse resonance cavity to determine analyte concentration, typically via absorption. We present a high-throughput data acquisition system that determines the decay constant in near real time using the discrete Fourier transform algorithm on a field programmable gate array (FPGA). A commercially available, high-speed, high-resolution, analog-to-digital converter evaluation board system is used as the platform for the system, after minor hardware and software modifications. The system outputs decay constants at maximum rate of 4.4 kHz using an 8192-point fast Fourier transform by processing the intensity decay signal between ringdown events. We present the details of the system, including the modifications required to adapt the evaluation board to accurately process the exponential waveform. We also demonstrate the performance of the system, both stand-alone and incorporated into our existing CRDS system. Details of FPGA, microcontroller, and circuitry modifications are provided in the Appendix and computer code is available upon request from the authors.

Single Event Effects Test Results for Advanced Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Allen, Gregory R.; Swift, Gary M.

2006-01-01

Reconfigurable Field Programmable Gate Arrays (FPGAs) from Altera and Actel and an FPGA-based quick-turnApplication Specific Integrated Circuit (ASIC) from Altera were subjected to single-event testing using heavy ions. Both Altera devices (Stratix II and HardCopy II) exhibited a low latchup threshold (below an LET of 3 MeV-cm2/mg) and thus are not recommended for applications in the space radiation environment. The flash-based Actel ProASIC Plus device did not exhibit latchup to an effective LET of 75 MeV-cm2/mg at room temperature. In addition, these tests did not show flash cell charge loss (upset) or retention damage. Upset characterization of the design-level flip-flops yielded an LET threshold below 10 MeV-cm2/mg and a high LET cross section of about lxlO-6 cm2/bit for storing ones and about lxl0-7 cm2/bit for storing zeros . Thus, the ProASIC device may be suitable for critical flight applications with appropriate triple modular redundancy mitigation techniques.

High-performance computing for airborne applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather M; Manuzzato, Andrea; Fairbanks, Tom

2010-06-28

Recently, there has been attempts to move common satellite tasks to unmanned aerial vehicles (UAVs). UAVs are significantly cheaper to buy than satellites and easier to deploy on an as-needed basis. The more benign radiation environment also allows for an aggressive adoption of state-of-the-art commercial computational devices, which increases the amount of data that can be collected. There are a number of commercial computing devices currently available that are well-suited to high-performance computing. These devices range from specialized computational devices, such as field-programmable gate arrays (FPGAs) and digital signal processors (DSPs), to traditional computing platforms, such as microprocessors. Even thoughmore » the radiation environment is relatively benign, these devices could be susceptible to single-event effects. In this paper, we will present radiation data for high-performance computing devices in a accelerated neutron environment. These devices include a multi-core digital signal processor, two field-programmable gate arrays, and a microprocessor. From these results, we found that all of these devices are suitable for many airplane environments without reliability problems.« less

A counting-weighted calibration method for a field-programmable-gate-array-based time-to-digital converter

NASA Astrophysics Data System (ADS)

Chen, Yuan-Ho

2017-05-01

In this work, we propose a counting-weighted calibration method for field-programmable-gate-array (FPGA)-based time-to-digital converter (TDC) to provide non-linearity calibration for use in positron emission tomography (PET) scanners. To deal with the non-linearity in FPGA, we developed a counting-weighted delay line (CWD) to count the delay time of the delay cells in the TDC in order to reduce the differential non-linearity (DNL) values based on code density counts. The performance of the proposed CWD-TDC with regard to linearity far exceeds that of TDC with a traditional tapped delay line (TDL) architecture, without the need for nonlinearity calibration. When implemented in a Xilinx Vertix-5 FPGA device, the proposed CWD-TDC achieved time resolution of 60 ps with integral non-linearity (INL) and DNL of [-0.54, 0.24] and [-0.66, 0.65] least-significant-bit (LSB), respectively. This is a clear indication of the suitability of the proposed FPGA-based CWD-TDC for use in PET scanners.

Case for a field-programmable gate array multicore hybrid machine for an image-processing application

NASA Astrophysics Data System (ADS)

Rakvic, Ryan N.; Ives, Robert W.; Lira, Javier; Molina, Carlos

2011-01-01

General purpose computer designers have recently begun adding cores to their processors in order to increase performance. For example, Intel has adopted a homogeneous quad-core processor as a base for general purpose computing. PlayStation3 (PS3) game consoles contain a multicore heterogeneous processor known as the Cell, which is designed to perform complex image processing algorithms at a high level. Can modern image-processing algorithms utilize these additional cores? On the other hand, modern advancements in configurable hardware, most notably field-programmable gate arrays (FPGAs) have created an interesting question for general purpose computer designers. Is there a reason to combine FPGAs with multicore processors to create an FPGA multicore hybrid general purpose computer? Iris matching, a repeatedly executed portion of a modern iris-recognition algorithm, is parallelized on an Intel-based homogeneous multicore Xeon system, a heterogeneous multicore Cell system, and an FPGA multicore hybrid system. Surprisingly, the cheaper PS3 slightly outperforms the Intel-based multicore on a core-for-core basis. However, both multicore systems are beaten by the FPGA multicore hybrid system by >50%.

Single event upset susceptibilities of latchup immune CMOS process programmable gate arrays

NASA Astrophysics Data System (ADS)

Koga, R.; Crain, W. R.; Crawford, K. B.; Hansel, S. J.; Lau, D. D.; Tsubota, T. K.

Single event upsets (SEU) and latchup susceptibilities of complementary metal oxide semiconductor programmable gate arrays (CMOS PPGA's) were measured at the Lawrence Berkeley Laboratory 88-in. cyclotron facility with Xe (603 MeV), Cu (290 MeV), and Ar (180 MeV) ion beams. The PPGA devices tested were those which may be used in space. Most of the SEU measurements were taken with a newly constructed tester called the Bus Access Storage and Comparison System (BASACS) operating via a Macintosh II computer. When BASACS finds that an output does not match a prerecorded pattern, the state of all outputs, position in the test cycle, and other necessary information is transmitted and stored in the Macintosh. The upset rate was kept between 1 and 3 per second. After a sufficient number of errors are stored, the test is stopped and the total fluence of particles and total errors are recorded. The device power supply current was closely monitored to check for occurrence of latchup. Results of the tests are presented, indicating that some of the PPGA's are good candidates for selected space applications.

The Role of Water Vapor and Dissociative Recombination Processes in Solar Array Arc Initiation

NASA Technical Reports Server (NTRS)

Galofar, J.; Vayner, B.; Degroot, W.; Ferguson, D.

2002-01-01

Experimental plasma arc investigations involving the onset of arc initiation for a negatively biased solar array immersed in low-density plasma have been performed. Previous studies into the arc initiation process have shown that the most probable arcing sites tend to occur at the triple junction involving the conductor, dielectric and plasma. More recently our own experiments have led us to believe that water vapor is the main causal factor behind the arc initiation process. Assuming the main component of the expelled plasma cloud by weight is water, the fastest process available is dissociative recombination (H2O(+) + e(-) (goes to) H* + OH*). A model that agrees with the observed dependency of arc current pulse width on the square root of capacitance is presented. A 400 MHz digital storage scope and current probe was used to detect arcs at the triple junction of a solar array. Simultaneous measurements of the arc trigger pulse, the gate pulse, the arc current and the arc voltage were then obtained. Finally, a large number of measurements of individual arc spectra were obtained in very short time intervals, ranging from 10 to 30 microseconds, using a 1/4 a spectrometer coupled with a gated intensified CCD. The spectrometer was systematically tuned to obtain optical arc spectra over the entire wavelength range of 260 to 680 nanometers. All relevant atomic lines and molecular bands were then identified.

Multicolor, time-gated, soft x-ray pinhole imaging of wire array and gas puff Z pinches on the Z and Saturn pulsed power generators.

PubMed

Jones, B; Coverdale, C A; Nielsen, D S; Jones, M C; Deeney, C; Serrano, J D; Nielsen-Weber, L B; Meyer, C J; Apruzese, J P; Clark, R W; Coleman, P L

2008-10-01

A multicolor, time-gated, soft x-ray pinhole imaging instrument is fielded as part of the core diagnostic set on the 25 MA Z machine [M. E. Savage et al., in Proceedings of the Pulsed Power Plasma Sciences Conference (IEEE, New York, 2007), p. 979] for studying intense wire array and gas puff Z-pinch soft x-ray sources. Pinhole images are reflected from a planar multilayer mirror, passing 277 eV photons with <10 eV bandwidth. An adjacent pinhole camera uses filtration alone to view 1-10 keV photons simultaneously. Overlaying these data provides composite images that contain both spectral as well as spatial information, allowing for the study of radiation production in dense Z-pinch plasmas. Cu wire arrays at 20 MA on Z show the implosion of a colder cloud of material onto a hot dense core where K-shell photons are excited. A 528 eV imaging configuration has been developed on the 8 MA Saturn generator [R. B. Spielman et al., and A. I. P. Conf, Proc. 195, 3 (1989)] for imaging a bright Li-like Ar L-shell line. Ar gas puff Z pinches show an intense K-shell emission from a zippering stagnation front with L-shell emission dominating as the plasma cools.

Fabrication and characterization of controllable grain boundary arrays in solution-processed small molecule organic semiconductor films

NASA Astrophysics Data System (ADS)

Wo, Songtao; Headrick, Randall L.; Anthony, John E.

2012-04-01

We have produced solution-processed thin films of 6,13-bis(tri-isopropyl-silylethynyl) pentacene with grain sizes from a few micrometers up to millimeter scale by lateral crystallization from a rectangular stylus. Grains are oriented along the crystallization direction, and the grain size transverse to the crystallization direction depends inversely on the writing speed, hence forming a regular array of oriented grain boundaries with controllable spacing. We utilize these controllable arrays to systematically study the role of large-angle grain boundaries in carrier transport and charge trapping in thin film transistors. The effective mobility scales with the grain size, leading to an estimate of the potential drop at individual large-angle grain boundaries of more than 1 volt. This result indicates that the structure of grain boundaries is not molecularly abrupt, which may be a general feature of solution-processed small molecule organic semiconductor thin films, where relatively high energy grain boundaries are typically formed. Transient measurements after switching from positive to negative gate bias or between large and small negative gate bias reveal reversible charge trapping, with time constants on the order of 10 s and trap densities that are correlated with grain boundary density. We suggest that charge diffusion along grain boundaries and other defects is the rate-determining mechanism of the reversible trapping.

Phased-array-fed antenna configuration study. Volume 1: Technology assessment

NASA Technical Reports Server (NTRS)

Sorbello, R. M.; Zaghloul, A. I.; Lee, B. S.; Siddiqi, S.; Geller, B. D.; Gerson, H. I.; Srinivas, D. N.

1983-01-01

The status of the technologies for phased-array-fed dual reflector systems is reviewed. The different aspects of these technologies, including optical performances, phased array systems, problems encountered in phased array design, beamforming networks, MMIC design and its incorporation into waveguide systems, reflector antenna structures, and reflector deployment mechanisms are addressed.

Real-time system for measuring three-dimensional shape of solder bump array by focus using varifocal mirror

NASA Astrophysics Data System (ADS)

Ishii, Akira; Tai, Haruka; Mitsudo, Jun

2007-10-01

This paper describes a real-time system for measuring the three-dimensional shape of solder bumps arrayed on an LSI chip-size-package (CSP) board presented for inspection based on the shape-from-focus technique. It uses a copper-alloy mirror deformed by a piezoelectric actuator as a varifocal mirror enabling a simple, fast, precise focusing mechanism without moving parts to be built. A practical measuring speed of 1.69 s/package for a small CSP board (4 x 4 mm2) was achieved by incorporating an exclusive field programmable gate array processor to calculate focus measure and by constructing a domed array of LEDs as a high-intensity, uniform illumination system so that a fast (150 fps) and high-resolution (1024 x 1024 pixels/frame) CMOS image sensor could be used. Accurate measurements of bump height were also achieved with errors of 10 μm (2σ) meeting the requirements for testing the coplanarity of a bump array.

III-V/Ge MOS device technologies for low power integrated systems

NASA Astrophysics Data System (ADS)

Takagi, S.; Noguchi, M.; Kim, M.; Kim, S.-H.; Chang, C.-Y.; Yokoyama, M.; Nishi, K.; Zhang, R.; Ke, M.; Takenaka, M.

2016-11-01

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. The plasma post oxidation to form GeOx interfacial layers is a key gate stack technology for Ge CMOS. Also, direct wafer bonding of ultrathin body quantum well III-V-OI channels, combined with Tri-gate structures, realizes high performance III-V n-MOSFETs on Si. We also demonstrate planar-type InGaAs and Ge/strained SOI TFETs. The defect-less p+-n source junction formation with steep impurity profiles is a key for high performance TFET operation.

Downscaling ferroelectric field effect transistors by using ferroelectric Si-doped HfO2

NASA Astrophysics Data System (ADS)

Martin, Dominik; Yurchuk, Ekaterina; Müller, Stefan; Müller, Johannes; Paul, Jan; Sundquist, Jonas; Slesazeck, Stefan; Schlösser, Till; van Bentum, Ralf; Trentzsch, Martin; Schröder, Uwe; Mikolajick, Thomas

2013-10-01

Throughout the 22 nm technology node HfO2 is established as a reliable gate dielectric in contemporary complementary metal oxide semiconductor (CMOS) technology. The working principle of ferroelectric field effect transistors FeFET has also been demonstrated for some time for dielectric materials like Pb[ZrxTi1-x]O3 and SrBi2Ta2O9. However, integrating these into contemporary downscaled CMOS technology nodes is not trivial due to the necessity of an extremely thick gate stack. Recent developments have shown HfO2 to have ferroelectric properties, given the proper doping. Moreover, these doped HfO2 thin films only require layer thicknesses similar to the ones already in use in CMOS technology. This work will show how the incorporation of Si induces ferroelectricity in HfO2 based capacitor structures and finally demonstrate non-volatile storage in nFeFETs down to a gate length of 100 nm. A memory window of 0.41 V can be retained after 20,000 switching cycles. Retention can be extrapolated to 10 years.