Titanium-tungsten nanocrystals embedded in a SiO(2)/Al(2)O(3) gate dielectric stack for low-voltage operation in non-volatile memory.

PubMed

Yang, Shiqian; Wang, Qin; Zhang, Manhong; Long, Shibing; Liu, Jing; Liu, Ming

2010-06-18

Titanium-tungsten nanocrystals (NCs) were fabricated by a self-assembly rapid thermal annealing (RTA) process. Well isolated Ti(0.46)W(0.54) NCs were embedded in the gate dielectric stack of SiO(2)/Al(2)O(3). A metal-oxide-semiconductor (MOS) capacitor was fabricated to investigate its application in a non-volatile memory (NVM) device. It demonstrated a large memory window of 6.2 V in terms of flat-band voltage (V(FB)) shift under a dual-directional sweeping gate voltage of - 10 to 10 V. A 1.1 V V(FB) shift under a low dual-directional sweeping gate voltage of - 4 to 4 V was also observed. The retention characteristic of this MOS capacitor was demonstrated by a 0.5 V memory window after 10(4) s of elapsed time at room temperature. The endurance characteristic was demonstrated by a program/erase cycling test.

Control of Ga-oxide interlayer growth and Ga diffusion in SiO2/GaN stacks for high-quality GaN-based metal-oxide-semiconductor devices with improved gate dielectric reliability

NASA Astrophysics Data System (ADS)

Yamada, Takahiro; Watanabe, Kenta; Nozaki, Mikito; Yamada, Hisashi; Takahashi, Tokio; Shimizu, Mitsuaki; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-01-01

A simple and feasible method for fabricating high-quality and highly reliable GaN-based metal-oxide-semiconductor (MOS) devices was developed. The direct chemical vapor deposition of SiO2 films on GaN substrates forming Ga-oxide interlayers was carried out to fabricate SiO2/GaO x /GaN stacked structures. Although well-behaved hysteresis-free GaN-MOS capacitors with extremely low interface state densities below 1010 cm-2 eV-1 were obtained by postdeposition annealing, Ga diffusion into overlying SiO2 layers severely degraded the dielectric breakdown characteristics. However, this problem was found to be solved by rapid thermal processing, leading to the superior performance of the GaN-MOS devices in terms of interface quality, insulating property, and gate dielectric reliability.

Characterization and metrology implications of the 1997 NTRS

NASA Astrophysics Data System (ADS)

Class, W.; Wortman, J. J.

1998-11-01

In the Front-end (transistor forming) area of silicon CMOS device processing, several NTRS difficult challenges have been identified including; scaled and alternate gate dielectric materials, new DRAM dielectric materials, alternate gate materials, elevated contact structures, engineered channels, and large-area cost-effective silicon substrates. This paper deals with some of the characterization and metrology challenges facing the industry if it is to meet the projected needs identified in the NTRS. In the areas of gate and DRAM dielectric, scaling requires that existing material layers be thinned to maximize capacitance. For the current gate dielectric, SiO2 and its nitrided derivatives, direct tunneling will limit scaling to approximately 1.5nm for logic applications before power losses become unacceptable. Low power logic and memory applications may limit scaling to the 2.0-2.2nm range. Beyond these limits, dielectric materials having higher dielectric constant, will permit continued capacitance increases while allowing for the use of thicker dielectric layers, where tunneling may be minimized. In the near term silicon nitride is a promising SiO2 substitute material while in the longer term "high-k" materials such as tantalum pentoxide and barium strontium titanate (BST) will be required. For these latter materials, it is likely that a multilayer dielectric stack will be needed, consisting of an ultra-thin (1-2 atom layer) interfacial SiO2 layer and a high-k overlayer. Silicon wafer surface preparation control, as well as the control of composition, crystal structure, and thickness for such stacks pose significant characterization and metrology challenges. In addition to the need for new gate dielectric materials, new gate materials will be required to overcome the limitations of the current doped polysilicon gate materials. Such a change has broad ramifications on device electrical performance and manufacturing process robustness which again implies a broad range of new characterization and metrology requirements. Finally, the doped structure of the MOS transistor must scale to very small lateral and depth dimensions, and thermal budgets must be reduced to permit the retention of very abrupt highly doped drain and channel engineered structures. Eventually, the NTRS forecasts the need for an elevated contact structure. Here, there are significant challenges associated with three-dimensional dopant profiling, measurement of dopant activity in ultra-shallow device regions, as well as point defect metrology and characterization.

Gate bias stress stability under light irradiation for indium zinc oxide thin-film transistors based on anodic aluminium oxide gate dielectrics

NASA Astrophysics Data System (ADS)

Li, Min; Lan, Linfeng; Xu, Miao; Wang, Lei; Xu, Hua; Luo, Dongxiang; Zou, Jianhua; Tao, Hong; Yao, Rihui; Peng, Junbiao

2011-11-01

Thin-film transistors (TFTs) using indium zinc oxide as the active layer and anodic aluminium oxide (Al2O3) as the gate dielectric layer were fabricated. The device showed an electron mobility of as high as 10.1 cm2 V-1 s-1, an on/off current ratio of as high as ~108, and a turn-on voltage (Von) of only -0.5 V. Furthermore, this kind of TFTs was very stable under positive bias illumination stress. However, when the device experienced negative bias illumination stress, the threshold voltage shifted to the positive direction. It was found that the instability under negative bias illumination stress (NBIS) was due to the electrons from the Al gate trapping into the Al2O3 dielectric when exposed to the illuminated light. Using a stacked structure of Al2O3/SiO2 dielectrics, the device became more stable under NBIS.

Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure

PubMed Central

Khan, Z. N.; Ahmed, S.; Ali, M.

2016-01-01

Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application. PMID:27571412

Combining a multi deposition multi annealing technique with a scavenging (Ti) to improve the high-k/metal gate stack performance for a gate-last process

NASA Astrophysics Data System (ADS)

ShuXiang, Zhang; Hong, Yang; Bo, Tang; Zhaoyun, Tang; Yefeng, Xu; Jing, Xu; Jiang, Yan

2014-10-01

ALD HfO2 films fabricated by a novel multi deposition multi annealing (MDMA) technique are investigated, we have included samples both with and without a Ti scavenging layer. As compared to the reference gate stack treated by conventional one-time deposition and annealing (D&A), devices receiving MDMA show a significant reduction in leakage current. Meanwhile, EOT growth is effectively controlled by the Ti scavenging layer. This improvement strongly correlates with the cycle number of D&A (while keeping the total annealing time and total dielectrics thickness the same). Transmission electron microscope and energy-dispersive X-ray spectroscopy analysis suggests that oxygen incorporation into both the high-k film and the interfacial layer is likely to be responsible for the improvement of the device. This novel MDMA is promising for the development of gate stack technology in a gate last integration scheme.

Effect of Al-diffusion-induced positive flatband voltage shift on the electrical characteristics of Al-incorporated high-k metal-oxide-semiconductor field-effective transistor

NASA Astrophysics Data System (ADS)

Wang, Wenwu; Akiyama, Koji; Mizubayashi, Wataru; Nabatame, Toshihide; Ota, Hiroyuki; Toriumi, Akira

2009-03-01

We systematically studied what effect Al diffusion from high-k dielectrics had on the flatband voltage (Vfb) of Al-incorporated high-k gate stacks. An anomalous positive shift fin Vfb with the decreasing equivalent oxide thickness (EOT) of high-k gate stacks is reported. As the SiO2 interfacial layer is aggressively thinned in Al-incorporated HfxAl1-xOy gate stacks with a metal-gate electrode, the Vfb first lies on the well known linear Vfb-EOT plot and deviates toward the positive-voltage direction (Vfb roll-up), followed by shifting toward negative voltage (Vfb roll-off). We demonstrated that the Vfb roll-up behavior remarkably decreases the threshold voltage (Vth) of p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs), and does not cause severe degradation in the characteristics of hole mobility. The Vfb roll-up behavior, which is independent of gate materials but strongly dependent on high-k dielectrics, was ascribed to variations in fixed charges near the SiO2/Si interface, which are caused by Al diffusion from HfxAl1-xOy through SiO2 to the SiO2/Si interface. These results indicate that anomalous positive shift in Vfb, i.e., Vfb roll-up, should be taken into consideration in quantitatively adjusting Vfb in thin EOT regions and that it could be used to further tune Vth in p-MOSFETs.

Enhancement of thermal stability and water resistance in yttrium-doped GeO{sub 2}/Ge gate stack

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Cimang, E-mail: cimang@adam.t.u-tokyo.ac.jp; Hyun Lee, Choong; Zhang, Wenfeng

2014-03-03

We have systematically investigated the material and electrical properties of yttrium-doped GeO{sub 2} (Y-GeO{sub 2}) on Germanium (Ge). A significant improvement of both thermal stability and water resistance were demonstrated by Y-GeO{sub 2}/Ge stack, compared to that of pure GeO{sub 2}/Ge stack. The excellent electrical properties of Y-GeO{sub 2}/Ge stacks with low D{sub it} were presented as well as enhancement of dielectric constant in Y-GeO{sub 2} layer, which is beneficial for further equivalent oxide thickness scaling of Ge gate stack. The improvement of thermal stability and water resistance are discussed both in terms of the Gibbs free energy lowering andmore » network modification of Y-GeO{sub 2}.« less

Thin film transistors for flexible electronics: contacts, dielectrics and semiconductors.

PubMed

Quevedo-Lopez, M A; Wondmagegn, W T; Alshareef, H N; Ramirez-Bon, R; Gnade, B E

2011-06-01

The development of low temperature, thin film transistor processes that have enabled flexible displays also present opportunities for flexible electronics and flexible integrated systems. Of particular interest are possible applications in flexible sensor systems for unattended ground sensors, smart medical bandages, electronic ID tags for geo-location, conformal antennas, radiation detectors, etc. In this paper, we review the impact of gate dielectrics, contacts and semiconductor materials on thin film transistors for flexible electronics applications. We present our recent results to fully integrate hybrid complementary metal oxide semiconductors comprising inorganic and organic-based materials. In particular, we demonstrate novel gate dielectric stacks and semiconducting materials. The impact of source and drain contacts on device performance is also discussed.

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

PubMed

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J

2016-06-09

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

Evaluation of border traps and interface traps in HfO2/MoS2 gate stacks by capacitance–voltage analysis

NASA Astrophysics Data System (ADS)

Zhao, Peng; Khosravi, Ava; Azcatl, Angelica; Bolshakov, Pavel; Mirabelli, Gioele; Caruso, Enrico; Hinkle, Christopher L.; Hurley, Paul K.; Wallace, Robert M.; Young, Chadwin D.

2018-07-01

Border traps and interface traps in HfO2/few-layer MoS2 top-gate stacks are investigated by C–V characterization. Frequency dependent C–V data shows dispersion in both the depletion and accumulation regions for the MoS2 devices. The border trap density is extracted with a distributed model, and interface traps are analyzed using the high-low frequency and multi-frequency methods. The physical origins of interface traps appear to be caused by impurities/defects in the MoS2 layers, performing as band tail states, while the border traps are associated with the dielectric, likely a consequence of the low-temperature deposition. This work provides a method of using multiple C–V measurements and analysis techniques to analyze the behavior of high-k/TMD gate stacks and deconvolute border traps from interface traps.

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer

PubMed Central

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J.

2016-01-01

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack. PMID:27279454

Investigation on interfacial and electrical properties of Ge MOS capacitor with different NH3-plasma treatment procedure

NASA Astrophysics Data System (ADS)

Liu, Xiaoyu; Xu, Jingping; Liu, Lu; Cheng, Zhixiang; Huang, Yong; Gong, Jingkang

2017-08-01

The effects of different NH3-plasma treatment procedures on interfacial and electrical properties of Ge MOS capacitors with stacked gate dielectric of HfTiON/TaON were investigated. The NH3-plasma treatment was performed at different steps during fabrication of the stacked gate dielectric, i.e. before or after interlayer (TaON) deposition, or after deposition of high-k dielectric (HfTiON). It was found that the excellent interface quality with an interface-state density of 4.79 × 1011 eV-1 cm-2 and low gate leakage current (3.43 × 10-5 A/cm2 at {V}{{g}}=1 {{V}}) could be achieved for the sample with NH3-plasma treatment directly on the Ge surface before TaON deposition. The involved mechanisms are attributed to the fact that the NH3-plasma can directly react with the Ge surface to form more Ge-N bonds, i.e. more GeO x Ny, which effectively blocks the inter-diffusion of elements and suppresses the formation of unstable GeO x interfacial layer, and also passivates oxygen vacancies and dangling bonds near/at the interface due to more N incorporation and decomposed H atoms from the NH3-plasma. Project supported by the National Natural Science Foundation of China (Nos. 61176100, 61274112).

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

NASA Astrophysics Data System (ADS)

Hu, Ai-Bin; Xu, Qiu-Xia

2010-05-01

Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO2 (1 < x < 2). Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V · s) and 81.0 cm2/(V · s), respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.

Improved interfacial and electrical properties of GaAs metal-oxide-semiconductor capacitors with HfTiON as gate dielectric and TaON as passivation interlayer

NASA Astrophysics Data System (ADS)

Wang, L. S.; Xu, J. P.; Zhu, S. Y.; Huang, Y.; Lai, P. T.

2013-08-01

The interfacial and electrical properties of sputtered HfTiON on sulfur-passivated GaAs with or without TaON as interfacial passivation layer (IPL) are investigated. Experimental results show that the GaAs metal-oxide-semiconductor capacitor with HfTiON/TaON stacked gate dielectric annealed at 600 °C exhibits low interface-state density (1.0 × 1012 cm-2 eV-1), small gate leakage current (7.3 × 10-5 A cm-2 at Vg = Vfb + 1 V), small capacitance equivalent thickness (1.65 nm), and large equivalent dielectric constant (26.2). The involved mechanisms lie in the fact that the TaON IPL can effectively block the diffusions of Hf, Ti, and O towards GaAs surface and suppress the formation of interfacial As-As bonds, Ga-/As-oxides, thus unpinning the Femi level at the TaON/GaAs interface and improving the interface quality and electrical properties of the device.

First-principles study on leakage current caused by oxygen vacancies at HfO2/SiO2/Si interface

NASA Astrophysics Data System (ADS)

Takagi, Kensuke; Ono, Tomoya

2018-06-01

The relationship between the position of oxygen vacancies in HfO2/SiO2/Si gate stacks and the leakage current is studied by first-principles electronic-structure and electron-conduction calculations. We find that the increase in the leakage current due to the creation of oxygen vacancies in the HfO2 layer is much larger than that in the SiO2 interlayer. According to previous first-principles total energy calculations, the formation energy of oxygen vacancies is smaller in the SiO2 interlayer than that in the HfO2 layer under the same conditions. Therefore, oxygen vacancies will be attracted from the SiO2 interlayer to minimize the energy, thermodynamically justifying the scavenging technique. Thus, the scavenging process efficiently improves the dielectric constant of HfO2-based gate stacks without increasing the number of oxygen vacancies, which cause the dielectric breakdown.

Improvement in top-gate MoS2 transistor performance due to high quality backside Al2O3 layer

NASA Astrophysics Data System (ADS)

Bolshakov, Pavel; Zhao, Peng; Azcatl, Angelica; Hurley, Paul K.; Wallace, Robert M.; Young, Chadwin D.

2017-07-01

A high quality Al2O3 layer is developed to achieve high performance in top-gate MoS2 transistors. Compared with top-gate MoS2 field effect transistors on a SiO2 layer, the intrinsic mobility and subthreshold slope were greatly improved in high-k backside layer devices. A forming gas anneal is found to enhance device performance due to a reduction in the charge trap density of the backside dielectric. The major improvements in device performance are ascribed to the forming gas anneal and the high-k dielectric screening effect of the backside Al2O3 layer. Top-gate devices built upon these stacks exhibit a near-ideal subthreshold slope of ˜69 mV/dec and a high Y-Function extracted intrinsic carrier mobility (μo) of 145 cm2/V.s, indicating a positive influence on top-gate device performance even without any backside bias.

Surface and Interface Chemistry for Gate Stacks on Silicon

NASA Astrophysics Data System (ADS)

Frank, M. M.; Chabal, Y. J.

This chapter addresses the fundamental silicon surface science associated with the continued progress of nanoelectronics along the path prescribed by Moore's law. Focus is on hydrogen passivation layers and on ultrathin oxide films encountered during silicon cleaning and gate stack formation in the fabrication of metal-oxide-semiconductor field-effect transistors (MOSFETs). Three main topics are addressed. (i) First, the current practices and understanding of silicon cleaning in aqueous solutions are reviewed, including oxidizing chemistries and cleans leading to a hydrogen passivation layer. The dependence of the final surface termination and morphology/roughness on reactant choice and pH and the influence of impurities such as dissolved oxygen or metal ions are discussed. (ii) Next, the stability of hydrogen-terminated silicon in oxidizing liquid and gas phase environments is considered. In particular, the remarkable stability of hydrogen-terminated silicon surface in pure water vapor is discussed in the context of atomic layer deposition (ALD) of high-permittivity (high-k) gate dielectrics where water is often used as an oxygen precursor. Evidence is also provided for co-operative action between oxygen and water vapor that accelerates surface oxidation in humid air. (iii) Finally, the fabrication of hafnium-, zirconium- and aluminum-based high-k gate stacks is described, focusing on the continued importance of the silicon/silicon oxide interface. This includes a review of silicon surface preparation by wet or gas phase processing and its impact on high-k nucleation during ALD growth, and the consideration of gate stack capacitance and carrier mobility. In conclusion, two issues are highlighted: the impact of oxygen vacancies on the electrical characteristics of high-k MOS devices, and the way alloyed metal ions (such as Al in Hf-based gate stacks) in contact with the interfacial silicon oxide layer can be used to control flatband and threshold voltages.

Multifunctional Hybrid Multilayer Gate Dielectrics with Tunable Surface Energy for Ultralow-Power Organic and Amorphous Oxide Thin-Film Transistors.

PubMed

Byun, Hye-Ran; You, Eun-Ah; Ha, Young-Geun

2017-03-01

For large-area, printable, and flexible electronic applications using advanced semiconductors, novel dielectric materials with excellent capacitance, insulating property, thermal stability, and mechanical flexibility need to be developed to achieve high-performance, ultralow-voltage operation of thin-film transistors (TFTs). In this work, we first report on the facile fabrication of multifunctional hybrid multilayer gate dielectrics with tunable surface energy via a low-temperature solution-process to produce ultralow-voltage organic and amorphous oxide TFTs. The hybrid multilayer dielectric materials are constructed by iteratively stacking bifunctional phosphonic acid-based self-assembled monolayers combined with ultrathin high-k oxide layers. The nanoscopic thickness-controllable hybrid dielectrics exhibit the superior capacitance (up to 970 nF/cm 2 ), insulating property (leakage current densities <10 -7 A/cm 2 ), and thermal stability (up to 300 °C) as well as smooth surfaces (root-mean-square roughness <0.35 nm). In addition, the surface energy of the hybrid multilayer dielectrics are easily changed by switching between mono- and bifunctional phosphonic acid-based self-assembled monolayers for compatible fabrication with both organic and amorphous oxide semiconductors. Consequently, the hybrid multilayer dielectrics integrated into TFTs reveal their excellent dielectric functions to achieve high-performance, ultralow-voltage operation (< ± 2 V) for both organic and amorphous oxide TFTs. Because of the easily tunable surface energy, the multifunctional hybrid multilayer dielectrics can also be adapted for various organic and inorganic semiconductors, and metal gates in other device configurations, thus allowing diverse advanced electronic applications including ultralow-power and large-area electronic devices.

Experimental evidence for the correlation between the weak inversion hump and near midgap states in dielectric/InGaAs interfaces

NASA Astrophysics Data System (ADS)

Krylov, Igor; Kornblum, Lior; Gavrilov, Arkady; Ritter, Dan; Eizenberg, Moshe

2012-04-01

Temperature dependent capacitance-voltage (C-V) and conductance-voltage (G-V) measurements were performed to obtain activation energies (EA) for weak inversion C-V humps and parallel conductance peaks in Al2O3/InGaAs and Si3N4/InGaAs gate stacks. Values of 0.48 eV (slightly more than half of the band gap of the studied In0.53Ga0.47As) were obtained for EA of both phenomena for both gate dielectrics studied. This indicates an universal InGaAs behavior and shows that both phenomena are due to generation-recombination of minority carriers through near midgap located interface states. The C-V hump correlates with the interface states density (Dit) and can be used as a characterization tool for dielectric/InGaAs systems.

van der Waals Heterostructures with High Accuracy Rotational Alignment.

PubMed

Kim, Kyounghwan; Yankowitz, Matthew; Fallahazad, Babak; Kang, Sangwoo; Movva, Hema C P; Huang, Shengqiang; Larentis, Stefano; Corbet, Chris M; Taniguchi, Takashi; Watanabe, Kenji; Banerjee, Sanjay K; LeRoy, Brian J; Tutuc, Emanuel

2016-03-09

We describe the realization of van der Waals (vdW) heterostructures with accurate rotational alignment of individual layer crystal axes. We illustrate the approach by demonstrating a Bernal-stacked bilayer graphene formed using successive transfers of monolayer graphene flakes. The Raman spectra of this artificial bilayer graphene possess a wide 2D band, which is best fit by four Lorentzians, consistent with Bernal stacking. Scanning tunneling microscopy reveals no moiré pattern on the artificial bilayer graphene, and tunneling spectroscopy as a function of gate voltage reveals a constant density of states, also in agreement with Bernal stacking. In addition, electron transport probed in dual-gated samples reveals a band gap opening as a function of transverse electric field. To illustrate the applicability of this technique to realize vdW heterostructuctures in which the functionality is critically dependent on rotational alignment, we demonstrate resonant tunneling double bilayer graphene heterostructures separated by hexagonal boron-nitride dielectric.

Crystalline ZrTiO{sub 4} gated p-metal–oxide–semiconductor field effect transistors with sub-nm equivalent oxide thickness featuring good electrical characteristics and reliability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Chao-Yi; Hsieh, Ching-Heng; Lee, Ching-Wei

2015-02-02

ZrTiO{sub 4} crystallized in orthorhombic (o-) phase was stacked with an amorphous Yb{sub 2}O{sub 3} interfacial layer as the gate dielectric for Si-based p-MOSFETs. With thermal annealing after gate electrode, the gate stack with equivalent oxide thickness (EOT) of 0.82 nm achieves high dielectric quality by showing a low interface trap density (D{sub it}) of 2.75 × 10{sup 11 }cm{sup −2}eV{sup −1} near the midgap and low oxide traps. Crystallization of ZrTiO{sub 4} and post metal annealing are also proven to introduce very limited amount of metal induced gap states or interfacial dipole. The p-MOSFETs exhibit good sub-threshold swing of 75 mV/dec which is ascribedmore » to the low D{sub it} value and small EOT. Owing to the Y{sub 2}O{sub 3} interfacial layer and smooth interface with Si substrate that, respectively, suppress phonon and surface roughness scattering, the p-MOSFETs also display high hole mobility of 49 cm{sup 2}/V-s at 1 MV/cm. In addition, I{sub on}/I{sub off} ratio larger than 10{sup 6} is also observed. From the reliability evaluation by negative bias temperature instability test, after stressing with an electric field of −10 MV/cm at 85 °C for 1000 s, satisfactory threshold voltage shift of 12 mV and sub-threshold swing degradation of 3% were obtained. With these promising characteristics, the Yb{sub 2}O{sub 3}/o-ZrTiO{sub 4} gate stack holds the great potential for next-generation electronics.« less

Micromachined mold-type double-gated metal field emitters

NASA Astrophysics Data System (ADS)

Lee, Yongjae; Kang, Seokho; Chun, Kukjin

1997-12-01

Electron field emitters with double gates were fabricated using micromachining technology and the effect of the electric potential of the focusing gate (or second gate) was experimentally evaluated. The molybdenum field emission tip was made by filling a cusplike mold formed when a conformal film was deposited on the hole-trench that had been patterned on stacked metals and dielectric layers. The hole-trench was patterned by electron beam lithography and reactive ion etching. Each field emitter has a 0960-1317/7/4/009/img1 diameter extraction gate (or first gate) and a 0960-1317/7/4/009/img2 diameter focusing gate (or second gate). To make a path for the emitted electrons, silicon bulk was etched anisotropically in KOH and EDP (ethylene-diamine pyrocatechol) solution successively. The I - V characteristics and anode current change due to the focusing gate potential were measured.

Synergistic High Charge-Storage Capacity for Multi-level Flexible Organic Flash Memory

NASA Astrophysics Data System (ADS)

Kang, Minji; Khim, Dongyoon; Park, Won-Tae; Kim, Jihong; Kim, Juhwan; Noh, Yong-Young; Baeg, Kang-Jun; Kim, Dong-Yu

2015-07-01

Electret and organic floating-gate memories are next-generation flash storage mediums for printed organic complementary circuits. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.

Synergistic High Charge-Storage Capacity for Multi-level Flexible Organic Flash Memory.

PubMed

Kang, Minji; Khim, Dongyoon; Park, Won-Tae; Kim, Jihong; Kim, Juhwan; Noh, Yong-Young; Baeg, Kang-Jun; Kim, Dong-Yu

2015-07-23

Electret and organic floating-gate memories are next-generation flash storage mediums for printed organic complementary circuits. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.

Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

PubMed Central

Long, Rathnait D.; McIntyre, Paul C.

2012-01-01

The literature on polar Gallium Nitride (GaN) surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS) devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

The Performance Improvement of N2 Plasma Treatment on ZrO2 Gate Dielectric Thin-Film Transistors with Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition IGZO Channel.

PubMed

Wu, Chien-Hung; Huang, Bo-Wen; Chang, Kow-Ming; Wang, Shui-Jinn; Lin, Jian-Hong; Hsu, Jui-Mei

2016-06-01

The aim of this paper is to illustrate the N2 plasma treatment for high-κ ZrO2 gate dielectric stack (30 nm) with indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs). Experimental results reveal that a suitable incorporation of nitrogen atoms could enhance the device performance by eliminating the oxygen vacancies and provide an amorphous surface with better surface roughness. With N2 plasma treated ZrO2 gate, IGZO channel is fabricated by atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) technique. The best performance of the AP-PECVD IGZO TFTs are obtained with 20 W-90 sec N2 plasma treatment with field-effect mobility (μ(FET)) of 22.5 cm2/V-s, subthreshold swing (SS) of 155 mV/dec, and on/off current ratio (I(on)/I(off)) of 1.49 x 10(7).

Enhancement of field effect mobility of poly(3-hexylthiophene) thin film transistors by soft-lithographical nanopatterning on the gate-dielectric surface

NASA Astrophysics Data System (ADS)

Park, Jeong-Ho; Kang, Seok-Ju; Park, Jeong-Woo; Lim, Bogyu; Kim, Dong-Yu

2007-11-01

The submicroscaled octadecyltrichlorosilane (OTS) line patterns on gate-dielectric surfaces were introduced into the fabrication of organic field effect transistors (OFETs). These spin-cast regioregular poly(3-hexylthiophene) films on soft-lithographically patterned SiO2 surfaces yielded a higher hole mobility (˜0.072cm2/Vs ) than those of unpatterned (˜0.015cm2/Vs) and untreated (˜5×10-3cm2/Vs) OFETs. The effect of mobility enhancement as a function of the patterned line pitch was investigated in structural and geometric characteristics. The resulting improved mobility is likely attributed to the formation of efficient π-π stacking as a result of guide-assisted, local self-organization-involved molecular interactions between the poly(3-hexylthiophene) polymer and the geometrical OTS patterns.

Schottky barrier SOI-MOSFETs with high-k La2O3/ZrO2 gate dielectrics

PubMed Central

Henkel, C.; Abermann, S.; Bethge, O.; Pozzovivo, G.; Klang, P.; Stöger-Pollach, M.; Bertagnolli, E.

2011-01-01

Schottky barrier SOI-MOSFETs incorporating a La2O3/ZrO2 high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N′-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500 °C. Excellent drive current properties, low interface trap densities of 1.9 × 1011 eV−1 cm−2, a low subthreshold slope of 70-80 mV/decade, and an ION/IOFF current ratio greater than 2 × 106 are obtained. PMID:21461054

Sub-60 mV/decade switching in 2D negative capacitance field-effect transistors with integrated ferroelectric polymer

NASA Astrophysics Data System (ADS)

McGuire, Felicia A.; Cheng, Zhihui; Price, Katherine; Franklin, Aaron D.

2016-08-01

There is a rising interest in employing the negative capacitance (NC) effect to achieve sub-60 mV/decade (below the thermal limit) switching in field-effect transistors (FETs). The NC effect, which is an effectual amplification of the applied gate potential, is realized by incorporating a ferroelectric material in series with a dielectric in the gate stack of a FET. One of the leading challenges to such NC-FETs is the variable substrate capacitance exhibited in 3D semiconductor channels (bulk, Fin, or nanowire) that minimizes the extent of sub-60 mV/decade switching. In this work, we demonstrate 2D NC-FETs that combine the NC effect with 2D MoS2 channels to extend the steep switching behavior. Using the ferroelectric polymer, poly(vinylidene difluoride-trifluoroethylene) (P(VDF-TrFE)), these 2D NC-FETs are fabricated by modification of top-gated 2D FETs through the integrated addition of P(VDF-TrFE) into the gate stack. The impact of including an interfacial metal between the ferroelectric and dielectric is studied and shown to be critical. These 2D NC-FETs exhibit a decrease in subthreshold swing from 113 mV/decade down to 11.7 mV/decade at room temperature with sub-60 mV/decade switching occurring over more than 4 decades of current. The P(VDF-TrFE) proves to be an unstable option for a device technology, yet the superb switching behavior observed herein opens the way for further exploration of nanomaterials for extremely low-voltage NC-FETs.

Phosphorus oxide gate dielectric for black phosphorus field effect transistors

NASA Astrophysics Data System (ADS)

Dickerson, W.; Tayari, V.; Fakih, I.; Korinek, A.; Caporali, M.; Serrano-Ruiz, M.; Peruzzini, M.; Heun, S.; Botton, G. A.; Szkopek, T.

2018-04-01

The environmental stability of the layered semiconductor black phosphorus (bP) remains a challenge. Passivation of the bP surface with phosphorus oxide, POx, grown by a reactive ion etch with oxygen plasma is known to improve photoluminescence efficiency of exfoliated bP flakes. We apply phosphorus oxide passivation in the fabrication of bP field effect transistors using a gate stack consisting of a POx layer grown by reactive ion etching followed by atomic layer deposition of Al2O3. We observe room temperature top-gate mobilities of 115 cm2 V-1 s-1 in ambient conditions, which we attribute to the low defect density of the bP/POx interface.

Role of oxygen vacancies in HfO2-based gate stack breakdown

NASA Astrophysics Data System (ADS)

Wu, X.; Migas, D. B.; Li, X.; Bosman, M.; Raghavan, N.; Borisenko, V. E.; Pey, K. L.

2010-04-01

We study the influence of multiple oxygen vacancy traps in the percolated dielectric on the postbreakdown random telegraph noise (RTN) digital fluctuations in HfO2-based metal-oxide-semiconductor transistors. Our electrical characterization results indicate that these digital fluctuations are triggered only beyond a certain gate stress voltage. First-principles calculations suggest the oxygen vacancies to be responsible for the formation of a subband in the forbidden band gap region, which affects the triggering voltage (VTRIG) for the RTN fluctuations and leads to a shrinkage of the HfO2 band gap.

Interfacial, Electrical, and Band Alignment Characteristics of HfO2/Ge Stacks with In Situ-Formed SiO2 Interlayer by Plasma-Enhanced Atomic Layer Deposition

NASA Astrophysics Data System (ADS)

Cao, Yan-Qiang; Wu, Bing; Wu, Di; Li, Ai-Dong

2017-05-01

In situ-formed SiO2 was introduced into HfO2 gate dielectrics on Ge substrate as interlayer by plasma-enhanced atomic layer deposition (PEALD). The interfacial, electrical, and band alignment characteristics of the HfO2/SiO2 high-k gate dielectric stacks on Ge have been well investigated. It has been demonstrated that Si-O-Ge interlayer is formed on Ge surface during the in situ PEALD SiO2 deposition process. This interlayer shows fantastic thermal stability during annealing without obvious Hf-silicates formation. In addition, it can also suppress the GeO2 degradation. The electrical measurements show that capacitance equivalent thickness of 1.53 nm and a leakage current density of 2.1 × 10-3 A/cm2 at gate bias of Vfb + 1 V was obtained for the annealed sample. The conduction (valence) band offsets at the HfO2/SiO2/Ge interface with and without PDA are found to be 2.24 (2.69) and 2.48 (2.45) eV, respectively. These results indicate that in situ PEALD SiO2 may be a promising interfacial control layer for the realization of high-quality Ge-based transistor devices. Moreover, it can be demonstrated that PEALD is a much more powerful technology for ultrathin interfacial control layer deposition than MOCVD.

Interfacial, Electrical, and Band Alignment Characteristics of HfO2/Ge Stacks with In Situ-Formed SiO2 Interlayer by Plasma-Enhanced Atomic Layer Deposition.

PubMed

Cao, Yan-Qiang; Wu, Bing; Wu, Di; Li, Ai-Dong

2017-12-01

In situ-formed SiO 2 was introduced into HfO 2 gate dielectrics on Ge substrate as interlayer by plasma-enhanced atomic layer deposition (PEALD). The interfacial, electrical, and band alignment characteristics of the HfO 2 /SiO 2 high-k gate dielectric stacks on Ge have been well investigated. It has been demonstrated that Si-O-Ge interlayer is formed on Ge surface during the in situ PEALD SiO 2 deposition process. This interlayer shows fantastic thermal stability during annealing without obvious Hf-silicates formation. In addition, it can also suppress the GeO 2 degradation. The electrical measurements show that capacitance equivalent thickness of 1.53 nm and a leakage current density of 2.1 × 10 -3 A/cm 2 at gate bias of V fb  + 1 V was obtained for the annealed sample. The conduction (valence) band offsets at the HfO 2 /SiO 2 /Ge interface with and without PDA are found to be 2.24 (2.69) and 2.48 (2.45) eV, respectively. These results indicate that in situ PEALD SiO 2 may be a promising interfacial control layer for the realization of high-quality Ge-based transistor devices. Moreover, it can be demonstrated that PEALD is a much more powerful technology for ultrathin interfacial control layer deposition than MOCVD.

Hafnium silicate and hafnium silicon oxynitride gate dielectrics for strained Si_xGe_1-x: Interface stability

NASA Astrophysics Data System (ADS)

Addepalli, Swarna; Sivasubramani, Prasanna; El-Bouanani, Mohamed; Kim, Moon; Gnade, Bruce; Wallace, Robert

2003-03-01

Strained Si_xGe_1-x layers have gained considerable attention due to hole mobility enhancement, and ease of integration with Si-based CMOS technology. The deposition of stable high-κ dielectrics [1] such as hafnium silicate and hafnium silicon oxynitride in direct contact with SiGe would simultaneously improve the capacitance of the gate stack and lower the leakage current for high performance SiGe devices. However, the oxidation of the Si_xGe_1-x substrate either during dielectric deposition or post-deposition processing would degrade device performance due to the thermodynamic instability of germanium oxide [2,3]. Results from XPS, HR-TEM, and C-V, and I-V analyses after various annealing treatments will be presented for hafnium silicate and hafnium silicon oxynitride films deposited on strained Si_xGe_1-x(100), and correlated with dielectric-Si_xGe_1-x(100) interface stability. Implications to the introduction of these oxides as viable gate dielectric candidates for SiGe-based CMOS technology will be discussed. This work is supported by DARPA through SPAWAR Grant No. N66001-00-1-8928, and the Texas Advanced Technology Program. References: [1] G. D. Wilk, R. M. Wallace and J. M. Anthony, Journal of Applied Physics, 89, 5243 (2001) [2] W. S. Liu, J .S. Chen, M.-A. Nicolet, V. Arbet-Engels, K. L. Wang, Journal of Applied Physics, 72, 4444 (1992), and, Applied Physics Letters, 62, 3321 (1993) [3] W. S. Liu, M. -A. Nicolet, H. -H. Park, B. -H. Koak, J. -W. Lee, Journal of Applied Physics, 78, 2631 (1995)

Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II-VI Tunnel Insulators

NASA Astrophysics Data System (ADS)

Suarez, E.; Gogna, M.; Al-Amoody, F.; Karmakar, S.; Ayers, J.; Heller, E.; Jain, F.

2010-07-01

This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn0.95Mg0.05S/ZnS tunnel insulators. The GeO x -cladded Ge and SiO x -cladded Si quantum dots (QDs) are self-assembled site-specifically on the II-VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudomorphic II-VI stack serves both as a tunnel insulator and a high- κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si3N4 and SiO2 layers grown by plasma- enhanced chemical vapor deposition.

Downscaling ferroelectric field effect transistors by using ferroelectric Si-doped HfO2

NASA Astrophysics Data System (ADS)

Martin, Dominik; Yurchuk, Ekaterina; Müller, Stefan; Müller, Johannes; Paul, Jan; Sundquist, Jonas; Slesazeck, Stefan; Schlösser, Till; van Bentum, Ralf; Trentzsch, Martin; Schröder, Uwe; Mikolajick, Thomas

2013-10-01

Throughout the 22 nm technology node HfO2 is established as a reliable gate dielectric in contemporary complementary metal oxide semiconductor (CMOS) technology. The working principle of ferroelectric field effect transistors FeFET has also been demonstrated for some time for dielectric materials like Pb[ZrxTi1-x]O3 and SrBi2Ta2O9. However, integrating these into contemporary downscaled CMOS technology nodes is not trivial due to the necessity of an extremely thick gate stack. Recent developments have shown HfO2 to have ferroelectric properties, given the proper doping. Moreover, these doped HfO2 thin films only require layer thicknesses similar to the ones already in use in CMOS technology. This work will show how the incorporation of Si induces ferroelectricity in HfO2 based capacitor structures and finally demonstrate non-volatile storage in nFeFETs down to a gate length of 100 nm. A memory window of 0.41 V can be retained after 20,000 switching cycles. Retention can be extrapolated to 10 years.

Steep-slope hysteresis-free negative capacitance MoS2 transistors

NASA Astrophysics Data System (ADS)

Si, Mengwei; Su, Chun-Jung; Jiang, Chunsheng; Conrad, Nathan J.; Zhou, Hong; Maize, Kerry D.; Qiu, Gang; Wu, Chien-Ting; Shakouri, Ali; Alam, Muhammad A.; Ye, Peide D.

2018-01-01

The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV dec-1 at room temperature and therefore precludes lowering of the supply voltage and overall power consumption1,2. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier3. Meanwhile, two-dimensional semiconductors such as atomically thin transition-metal dichalcogenides, due to their low dielectric constant and ease of integration into a junctionless transistor topology, offer enhanced electrostatic control of the channel4-12. Here, we combine these two advantages and demonstrate a molybdenum disulfide (MoS2) two-dimensional steep-slope transistor with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack. This device exhibits excellent performance in both on and off states, with a maximum drain current of 510 μA μm-1 and a sub-thermionic subthreshold slope, and is essentially hysteresis-free. Negative differential resistance was observed at room temperature in the MoS2 negative-capacitance FETs as the result of negative capacitance due to the negative drain-induced barrier lowering. A high on-current-induced self-heating effect was also observed and studied.

Physical understanding of trends in current collapse with atomic layer deposited dielectrics in AlGaN/GaN MOS heterojunction FETs

NASA Astrophysics Data System (ADS)

Ramanan, Narayanan; Lee, Bongmook; Misra, Veena

2016-03-01

Many passivation dielectrics are pursued for suppressing current collapse due to trapping/detrapping of access-region surface traps in AlGaN/GaN based metal oxide semiconductor heterojuction field effect transistors (MOS-HFETs). The suppression of current collapse can potentially be achieved either by reducing the interaction of surface traps with the gate via surface leakage current reduction, or by eliminating surface traps that can interact with the gate. But, the latter is undesirable since a high density of surface donor traps is required to sustain a high 2D electron gas density at the AlGaN/GaN heterointerface and provide a low ON-resistance. This presents a practical trade-off wherein a passivation dielectric with the optimal surface trap characteristics and minimal surface leakage is to be chosen. In this work, we compare MOS-HFETs fabricated with popular ALD gate/passivation dielectrics like SiO2, Al2O3, HfO2 and HfAlO along with an additional thick plasma-enhanced chemical vapor deposition SiO2 passivation. It is found that after annealing in N2 at 700 °C, the stack containing ALD HfAlO provides a combination of low surface leakage and a high density of shallow donor traps. Physics-based TCAD simulations confirm that this combination of properties helps quick de-trapping and minimal current collapse along with a low ON resistance.

Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs

NASA Astrophysics Data System (ADS)

Dentoni Litta, E.; Hellström, P.-E.; Östling, M.

2015-06-01

High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.

Frequency-Stable Ionic-Type Hybrid Gate Dielectrics for High Mobility Solution-Processed Metal-Oxide Thin-Film Transistors

PubMed Central

Heo, Jae Sang; Choi, Seungbeom; Jo, Jeong-Wan; Kang, Jingu; Park, Ho-Hyun; Kim, Yong-Hoon; Park, Sung Kyu

2017-01-01

In this paper, we demonstrate high mobility solution-processed metal-oxide thin-film transistors (TFTs) by using a high-frequency-stable ionic-type hybrid gate dielectric (HGD). The HGD gate dielectric, a blend of sol-gel aluminum oxide (AlOx) and poly(4-vinylphenol) (PVP), exhibited high dielectric constant (ε~8.15) and high-frequency-stable characteristics (1 MHz). Using the ionic-type HGD as a gate dielectric layer, an minimal electron-double-layer (EDL) can be formed at the gate dielectric/InOx interface, enhancing the field-effect mobility of the TFTs. Particularly, using the ionic-type HGD gate dielectrics annealed at 350 °C, InOx TFTs having an average field-effect mobility of 16.1 cm2/Vs were achieved (maximum mobility of 24 cm2/Vs). Furthermore, the ionic-type HGD gate dielectrics can be processed at a low temperature of 150 °C, which may enable their applications in low-thermal-budget plastic and elastomeric substrates. In addition, we systematically studied the operational stability of the InOx TFTs using the HGD gate dielectric, and it was observed that the HGD gate dielectric effectively suppressed the negative threshold voltage shift during the negative-illumination-bias stress possibly owing to the recombination of hole carriers injected in the gate dielectric with the negatively charged ionic species in the HGD gate dielectric. PMID:28772972

Poly(methyl methacrylate) as a self-assembled gate dielectric for graphene field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sanne, A.; Movva, H. C. P.; Kang, S.

We investigate poly(methyl methacrylate) (PMMA) as a low thermal budget organic gate dielectric for graphene field effect-transistors (GFETs) based on a simple process flow. We show that high temperature baking steps above the glass transition temperature (∼130 °C) can leave a self-assembled, thin PMMA film on graphene, where we get a gate dielectric almost for “free” without additional atomic layer deposition type steps. Electrical characterization of GFETs with PMMA as a gate dielectric yields a dielectric constant of k = 3.0. GFETs with thinner PMMA dielectrics have a lower dielectric constant due to decreased polarization arising from neutralization of dipoles and charged carriersmore » as baking temperatures increase. The leakage through PMMA gate dielectric increases with decreasing dielectric thickness and increasing electric field. Unlike conventional high-k gate dielectrics, such low-k organic gate dielectrics are potentially attractive for devices such as the proposed Bilayer pseudoSpin Field-Effect Transistor or flexible high speed graphene electronics.« less

Al{sub 2}O{sub 3}/GeO{sub x} gate stack on germanium substrate fabricated by in situ cycling ozone oxidation method

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Xu; Zeng, Zhen-Hua; Microwave Device and IC Department, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029

2014-09-01

Al{sub 2}O{sub 3}/GeO{sub x}/Ge gate stack fabricated by an in situ cycling ozone oxidation (COO) method in the atomic layer deposition (ALD) system at low temperature is systematically investigated. Excellent electrical characteristics such as minimum interface trap density as low as 1.9 × 10{sup 11 }cm{sup −2 }eV{sup −1} have been obtained by COO treatment. The impact of COO treatment against the band alignment of Al{sub 2}O{sub 3} with respect to Ge is studied by x-ray photoelectron spectroscopy (XPS) and spectroscopic ellipsometry (SE). Based on both XPS and SE studies, the origin of gate leakage in the ALD-Al{sub 2}O{sub 3} is attributed to themore » sub-gap states, which may be correlated to the OH-related groups in Al{sub 2}O{sub 3} network. It is demonstrated that the COO method is effective in repairing the OH-related defects in high-k dielectrics as well as forming superior high-k/Ge interface for high performance Ge MOS devices.« less

Lanthanide-based oxides and silicates for high-kappa gate dielectric applications

NASA Astrophysics Data System (ADS)

Jur, Jesse Stephen

The ability to improve performance of the high-end metal oxide semiconductor field effect transistor (MOSFET) is highly reliant on the dimensional scaling of such a device. In scaling, a decrease in dielectric thickness results in high current leakage between the electrode and the substrate by way of direct tunneling through the gate dielectric. Observation of a high leakage current when the standard gate dielectric, SiO2, is decreased below a thickness of 1.5 nm requires engineering of a replacement dielectric that is much more scalable. This high-kappa dielectric allows for a physically thicker oxide, reducing leakage current. Integration of select lanthanide-based oxides and silicates, in particular lanthanum oxide and silicate, into MOS gate stack devices is examined. The quality of the high-kappa dielectrics is monitored electrically to determine properties such as equivalent oxide thickness, leakage current density and defect densities. In addition, analytical characterization of the dielectric and the gate stack is provided to examine the materialistic significance to the change of the electrical properties of the devices. In this work, lanthanum oxide films have been deposited by thermal evaporation on to a pre-grown chemical oxide layer on silicon. It is observed that the SiO2 interfacial layer can be consumed by a low-temperature reaction with lanthanum oxide to produce a high-quality silicate. This is opposed to depositing lanthanum oxide directly on silicon, which can possibly favor silicide formation. The importance of oxygen regulation in the surrounding environment of the La2O3-SiO2 reaction-anneal is observed. By controlling the oxygen available during the reaction, SiO2 growth can be limited to achieve high stoichiometric ratios of La2O 3 to SiO2. As a result, MOS devices with an equivalent oxide thickness (EOT) of 5 A and a leakage current density of 5.0 A/cm 2 are attained. This data equals the best value achieved in this field and is a substantial improvement over SiO(N) dielectrics, allowing for increased device scaling. High-temperature processing, consistent with the source/drain activation anneal in MOSFET processing, is performed on lanthanum-silicate based MOS devices with Ta or TaN gate electrodes and a W metal capping layer. The thermal limit of Ta is observed to be less than 800°C, resulting in a phase transformation that can result in uncontrolled shifting of the MOS device flat-band voltage. TaN is observed to be more thermally stable (up to 1000°C) and results in an increase in the capacitance density suggesting that it impedes oxygen reaction with silicon to produce SiO2. It is later observed that a W metal capping layer can serve as a high-oxygen source, which results in an increased interfacial SiO2 formation. By limiting the oxygen content in the W capping layer and by utilizing a thermally stable TaN gate electrode, control over the electrical properties of the MOS device is acquired. To determine the stability of amorphous lanthanum-silicate in contact with investigated by means of back-side secondary ion mass spectroscopy profiling. The results are the first reported data showing that the lanthanum incorporated in the silica matrix doe not diffuse into the silicon substrate after high temperature processing. The decrease in the device effective work function (φM,eff ) observed in these samples is examined in detail. First, as a La 2O3 capping layer on HfSiO(N), the shift yields ideal-φ M,eff values for nMOSFET deices (4.0 eV) that were previously inaccessible. Other lanthanide oxides (Dy, Ho and Yb) used as capping layers show similar effects. It is also shown that tuning of φM,eff can be realized by controlling the extent of lanthanide-silicate formation. This research, conducted in conjunction with SEMATECH and the SRC, represents a significant technological advancement in realizing 45 and sub-45 nm MOSFET device nodes.

Nano-scale zirconia and hafnia dielectrics grown by atomic layer deposition: Crystallinity, interface structures and electrical properties

NASA Astrophysics Data System (ADS)

Kim, Hyoungsub

With the continued scaling of transistors, leakage current densities across the SiO2 gate dielectric have increased enormously through direct tunneling. Presently, metal oxides having higher dielectric constants than SiO2 are being investigated to reduce the leakage current by increasing the physical thickness of the dielectric. Many possible techniques exist for depositing high-kappa gate dielectrics. Atomic layer deposition (ALD) has drawn attention as a method for preparing ultrathin metal oxide layers with excellent electrical characteristics and near-perfect film conformality due to the layer-by-layer nature of the deposition mechanism. For this research, an ALD system using ZrCl4/HfCl4 and H2O was built and optimized. The microstructural and electrical properties of ALD-ZrO2 and HfO2 grown on SiO2/Si substrates were investigated and compared using various characterization tools. In particular, the crystallization kinetics of amorphous ALD-HfO2 films were studied using in-situ annealing experiments in a TEM. The effect of crystallization on the electrical properties of ALD-HfO 2 was also investigated using various in-situ and ex-situ post-deposition anneals. Our results revealed that crystallization had little effect on the magnitude of the gate leakage current or on the conduction mechanisms. Building upon the results for each metal oxide separately, more advanced investigations were made. Several nanolaminate structures using ZrO2 and HfO2 with different sequences and layer thicknesses were characterized. The effects of the starting microstructure on the microstructural evolution of nanolaminate stacks were studied. Additionally, a promising new approach for engineering the thickness of the SiO2-based interface layer between the metal oxide and silicon substrate after deposition of the metal oxide layer was suggested. Through experimental measurements and thermodynamic analysis, it is shown that a Ti overlayer, which exhibits a high oxygen solubility, can effectively getter oxygen from the interface layer, thus decomposing SiO2 and reducing the interface layer thickness in a controllable fashion. As one of several possible applications, ALD-ZrO2 and HfO 2 gate dielectric films were deposited on Ge (001) substrates with different surface passivations. After extensive characterization using various microstructural, electrical, and chemical analyses, excellent MOS electrical properties of high-kappa gate dielectrics on Ge were successfully demonstrated with optimized surface nitridation of the Ge substrates.

Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

NASA Astrophysics Data System (ADS)

Jayanti, Srikant

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG in the form of PVD TaN was investigated along with high-k blocking dielectric. The material properties of TaN metal and high-k / low-k dielectric engineering were systematically studied. And the resulting memory structures exhibit excellent memory characteristics and scalability of the metal FG down to ˜1nm, which is promising in order to reduce the unwanted FG-FG interferences. In the later part of the study, the thermal stability of the combined stack was examined and various approaches to improve the stability and understand the cause of instability were explored. The performance of the high-k IPD metal FG memory structure was observed to degrade with higher annealing conditions and the deteriorated behavior was attributed to the leakage instability of the high-k /TaN capacitor. While the degradation is pronounced in both MIM and MIS capacitors, a higher leakage increment was seen in MIM, which was attributed to the higher degree of dielectric crystallization. In an attempt to improve the thermal stability, the trade-off in using amorphous interlayers to reduce the enhanced dielectric crystallization on metal was highlighted. Also, the effect of oxygen vacancies and grain growth on the dielectric leakage was studied through a multi-deposition-multi-anneal technique. Multi step deposition and annealing in a more electronegative ambient was observed to have a positive impact on the dielectric performance.

Improvement of Ion/Ioff for h-BN encapsulated bilayer graphene by graphite local back gate electrode

NASA Astrophysics Data System (ADS)

Uwanno, Teerayut; Taniguchi, Takashi; Watanabe, Kenji; Nagashio, Kosuke

The critical issue for bilayer graphene (BLG) devices is low Ion/Ioff even at the band gap of 0.3eV. Band gap in BLG can be formed by creating potential difference between the two layers of BLG. This can be done by applying external electric field perpendicularly to BLG to induce different carrier densities in the two layers. Due to such origin, the spatial uniformity of band gap in the channel is quite sensitive to charge inhomogeneity in BLG. In order to apply electric field of 3V/nm to open the maximum band gap of 0.3eV, high- k gate stack has been utilized so far. However, oxide dielectrics usually have large charge inhomogeneity causing in-plane potential fluctuation in BLG channel. Due to surface flatness and small charge inhomogeneity, h-BN has been used as dielectrics to achieve high quality graphene devices, however, Ion/Iofffor BLG/ h-BN heterostuctures has not been reported yet. In this study, we used graphite as local back gate electrode to BLG encapsulated with h-BN. This resulted in much higher Ion/Ioff, indicating the importance of screening of charge inhomogeneity from SiO2 substrate surface by local graphite back gate electrode. This research was partly supported by JSPS Core-to-Core Program, A. Advanced Research Networks.

The effect of Al segregation on Schottky barrier height and effective work function in TiAl/TiN/HfO2 gate stacks

NASA Astrophysics Data System (ADS)

Kim, Geun-Myeong; Oh, Young Jun; Chang, K. J.

2016-07-01

We perform first-principles density functional calculations to investigate the effects of Al incorporation on the p-type Schottky barrier height ≤ft({φ\\text{p}}\\right) and the effective work function for various high-k/metal gate stacks, such as TiN/HfO2 with interface Al impurities, Ti1-x Al x N/HfO2, and TiAl/TiN/HfO2. When Al atoms substitute for the interface Ti atoms at TiN/HfO2 interface, interface dipole fields become stronger, leading to the increase of {φ\\text{p}} and thereby the n-type shift of effective work function. In Ti1-x Al x N/HfO2 interface, {φ\\text{p}} linearly increases with the Al content, attributed to the presence of interface Al atoms. On the other hand, in TiAl/TiN/HfO2 interface, where Al is assumed not to segregate from TiAl to TiN, {φ\\text{p}} is nearly independent of the thickness of TiAl. Our results indicate that Al impurities at the metal/dielectric interface play an important role in controlling the effective work function, and provide a clue to understanding the n-type shift of the effective work function observed in TiAl/TiN/HfO2 gate stacks fabricated by using thegate-last process.

Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics on Flexible Substrates

PubMed Central

Tetzner, Kornelius; Bose, Indranil R.; Bock, Karlheinz

2014-01-01

In this work, the insulating properties of poly(4-vinylphenol) (PVP) and SU-8 (MicroChem, Westborough, MA, USA) dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP) using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor. PMID:28788243

Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics onFlexible Substrates.

PubMed

Tetzner, Kornelius; Bose, Indranil R; Bock, Karlheinz

2014-10-29

In this work, the insulating properties of poly(4-vinylphenol) (PVP) and SU-8 (MicroChem, Westborough, MA, USA) dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP) using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor.

Bragg reflector based gate stack architecture for process integration of excimer laser annealing

NASA Astrophysics Data System (ADS)

Fortunato, G.; Mariucci, L.; Cuscunà, M.; Privitera, V.; La Magna, A.; Spinella, C.; Magrı, A.; Camalleri, M.; Salinas, D.; Simon, F.; Svensson, B.; Monakhov, E.

2006-12-01

An advanced gate stack structure, which incorporates a Bragg reflector, has been developed for the integration of excimer laser annealing into the power metal-oxide semiconductor (MOS) transistor fabrication process. This advanced gate structure effectively protects the gate stack from melting, thus solving the problem related to protrusion formation. By using this gate stack configuration, power MOS transistors were fabricated with improved electrical characteristics. The Bragg reflector based gate stack architecture can be applied to other device structures, such as scaled MOS transistors, thus extending the possibilities of process integration of excimer laser annealing.

Characterizing Radio Emission From Extensive Air Showers with the SLAC-T510 Experiment, with Applications to ANITA

NASA Astrophysics Data System (ADS)

McGuire, Felicia Ann

Essential to metal-oxide-semiconductor field-effect transistor (MOSFET) scaling is the reduction of the supply voltage to mitigate the power consumption and corresponding heat dissipation. Conventional dielectric materials are subject to the thermal limit imposed by the Boltzmann factor in the subthreshold swing, which places an absolute minimum on the supply voltage required to modulate the current. Furthermore, as technology approaches the 5 nm node, electrostatic control of a silicon channel becomes exceedingly difficult, regardless of the gating technique. This notion of "the end of silicon scaling" has rapidly increased research into more scalable channel materials as well as new methods of transistor operation. Among the many promising options are two-dimensional (2D) FETs and negative capacitance (NC) FETs. 2D-FETs make use of atomically thin semiconducting channels that have enabled demonstrated scalability beyond what silicon can offer. NC-FETs demonstrate an effective negative capacitance arising from the integration of a ferroelectric into the transistor gate stack, allowing sub-60 mV/dec switching. While both of these devices provide significant advantages, neither can accomplish the ultimate goal of a FET that is both low-voltage and scalable. However, an appropriate fusion of the 2D-FET and NC-FET into a 2D NC-FET has the potential of enabling a steep-switching device that is dimensionally scalable beyond the 5 nm technology node. In this work, the motivation for and operation of 2D NC-FETs is presented. Experimental realization of 2D NC-FETs using 2D transition metal dichalcogenide molybdenum disulfide (MoS2) as the channel is shown with two different ferroelectric materials: 1) a solution-processed, polymeric poly(vinylidene difluoride trifluoroethylene) ferroelectric and 2) an atomic layer deposition (ALD) grown hafnium zirconium oxide (HfZrO2) ferroelectric. Each ferroelectric was integrated into the gate stack of a 2D-FET having either a top-gate (polymeric ferroelectric) or bottom-gate (HfZrO2 ferroelectric) configuration. HfZrO 2 devices with metallic interfacial layers (between ferroelectric and dielectric) and thinner ferroelectric layers were found to reduce both the hysteresis and the threshold voltage. Detailed characterization of the devices was performed and, most significantly, the 2D NC-FETs with HfZrO2 reproducibly yielded subthreshold swings well below the thermal limit with over more than four orders of magnitude in drain current modulation. HfZrO 2 devices without metallic interfacial layers were utilized to explore the impact of ferroelectric thickness, dielectric thickness, and dielectric composition on device performance. The impact of an interfacial metallic layer on the device operation was investigated in devices with HfZrO2 and shown to be crucial at enabling sub-60 mV/dec switching and large internal voltage gains. The significance of dielectric material choice on device performance was explored and found to be a critical factor in 2D NC-FET transistor operation. These successful results pave the way for future integration of this new device structure into existing technology markets.

Use of a hard mask for formation of gate and dielectric via nanofilament field emission devices

DOEpatents

Morse, Jeffrey D.; Contolini, Robert J.

2001-01-01

A process for fabricating a nanofilament field emission device in which a via in a dielectric layer is self-aligned to gate metal via structure located on top of the dielectric layer. By the use of a hard mask layer located on top of the gate metal layer, inert to the etch chemistry for the gate metal layer, and in which a via is formed by the pattern from etched nuclear tracks in a trackable material, a via is formed by the hard mask will eliminate any erosion of the gate metal layer during the dielectric via etch. Also, the hard mask layer will protect the gate metal layer while the gate structure is etched back from the edge of the dielectric via, if such is desired. This method provides more tolerance for the electroplating of a nanofilament in the dielectric via and sharpening of the nanofilament.

Impact of post metal annealing on gate work function engineering for advanced MOS applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, S. Sachin, E-mail: ssachikl995@yahoo.in; Prasad, Amitesh; Sinha, Amrita

2016-05-06

Ultra thin HfO{sub 2} high-k gate dielectric has been deposited directly on strained Si{sub 0.81}Ge{sub 0.19} by Atomic Layer Deposition (ALD) technique. The influence of different types of metal gate electrodes (Al, Au, Pt) on electrical characteristics of Metal-Oxide-Semiconductor capacitors has been studied. Our results show that the electrical characteristics of MOS device are highly dependent on the gate electrodes used. The dependency of electrical characteristics on post metal annealing was studied in detail. The measured flat band (V{sub fb}) and hysteresis (ΔV{sub fb}) from high frequency C-V characteristics were used to study the pre-existing traps in the dielectric. Impactmore » of PMA on interface state density (D{sub it}), border trap density (N{sub bt}) and oxide trap density (Q{sub f/q}) of high-k gate stack were also examined for all the devices. The N{sub bt} and frequency dispersion significantly reduces to ~2.77x1010 cm{sup −2} and ~11.34 % respectively in case of Al electrode with a Dit value of ~4x10{sup 12} eV{sup −1}cm{sup −2} after PMA (350°C) in N{sub 2}, suggesting an improvement in device performance while Pt electrode shows a much less value of ΔVfb (~0.02 V) and Dit (~3.44x10{sup 12} eV{sup −1}cm{sup −2}) after PMA.« less

Giant optical field enhancement in multi-dielectric stacks by photon scanning tunneling microscopy

NASA Astrophysics Data System (ADS)

Ndiaye, C.; Zerrad, M.; Lereu, A. L.; Roche, R.; Dumas, Ph.; Lemarchand, F.; Amra, C.

2013-09-01

Dielectric optical thin films, as opposed to metallic, have been very sparsely explored as good candidates for absorption-based optical field enhancement. In such materials, the low imaginary part of the refractive index implies that absorption processes are usually not predominant. This leads to dielectric-based optical resonances mainly via waveguiding modes. We show here that when properly designed, a multi-layered dielectric thin films stack can give rise to optical resonances linked to total absorption. We report here, on such dielectric stack designed to possess a theoretical optical field enhancement above 1000. Using photon scanning tunneling microscopy, we experimentally evaluate the resulting field enhancement of the stack as well as the associated penetration depth. We thus demonstrate the capability of multi-dielectric stacks in generating giant optical field with tunable penetration depth (down to few dozens of nm).

Adhesion promoters for large scale fabrication of dielectric elastomer stack transducers (DESTs) made of pre-fabricated dielectric films

NASA Astrophysics Data System (ADS)

Grotepaß, T.; Förster-Zügel, F.; Mößinger, H.; Schlaak, H. F.

2015-04-01

Multilayer dielectric elastomer stack transducers (DESTs) are a promising new transducer technology with many applications in different industry sectors, like medical devices, human-machine-interaction, etc. Stacked dielectric elastomer transducers show larger thickness contraction driven by lower voltages than transducers made from a single dielectric layer. Traditionally multilayered DESTs are produced by repeatedly cross-linking a liquid elastomeric pre-polymer into the required shape. Our recent research focusses on a novel fabrication method for large scale stack transducers with a surface area over 200 x 300 mm by processing pre-fabricated elastomeric thin films of less than 50 μm thicknesses. The thin films are provided as two- or three-layer composites, where the elastomer is sandwiched between one or two sacrificial liners. Separating the elastomeric film from the residual layers and assembling them into dielectric elastomer stack transducers poses many challenges concerning adhesion, since the dielectric film merely separates from the liner if the adhesive forces between them are overcome. Conversely, during the assembly of a dielectric elastomer stack transducer, adhesive forces have to be established between two elastomeric layers or between the dielectric and the electrode layer. The very low Young's modulus of at least one adhesion partner requires suitable means of increasing the adhesive forces between the different adhesive layers of a dielectric elastomer stack transducer to prevent a delamination of the transducer during its lifetime. This work evaluates different surface activation treatments - corona, low-pressure plasma and UV-light - and their applicability in the production of large scale DESTs made from pre-fabricated elastomeric films.

TEM studies of III-V MOSFETs for ultimate CMOS

NASA Astrophysics Data System (ADS)

Longo, Paolo

Over the past half-century electronic industry has enormously grown changing the way people live their lives. Such growth has been driven by the miniaturisation and development of the transistors which are the main components in an integrated circuit (IC) commonly referred as a chip. Until today electronic industry has been based on the use of Si and its native oxide SiO2 in transistors. However, the performance limit of conventional Si based transistors is rapidly being approached and alternatives will soon be required. One of the proposed alternatives is GaAs. n-type GaAs has a mobility 5 times higher than Si. This makes it a suitable candidate for MOSFETs devices. So far, GaAs has not been used for practical MOSFETs because of the difficulties of making a good dielectric oxide layer in terms of leakage current and unpinned Fermi Level. Using processes pioneered by Passlack et al, dielectric gate stacks consisting of a template layer of amorphous Ga2O3 followed by amorphous GdGaO have been grown on GaAs substrates. Careful deposition of Ga2O3 can leave the Fermi Level unpinned. The introduction of Gd is important in order to decrease the leakage of current. The electrical properties of the Ga2O3/Gd[x]Ga[0.4-x]O[0.6] dielectric stack are related to the Gd concentration and the quality of the GaAs/Ga2O3 interface. Over the past years in a unique partnership several research groups from the Physics and the Electronic and Electrical engineering Department have collaboratively worked for the realisation and development of such new generation of GaAs based transistors using the technology described above. The properties of such devices depend on structures at the nanoscale which is only few atoms across. Thus the characterization using the transmission electron microscope (TEM) becomes essential. In this project TEM has been used to study several MBE grown III-V semiconductor nanostructures. In particular most of the thesis is focussed on the chemical characterisation of the GaAs/Ga2O3/GGO dielectric gate stack, mainly using electron energy loss spectroscopy (EELS) and high-resolution scanning Transmission electron microscopy (STEM) imaging. As said above the quality of such interfaces affects the properties of the whole device. Hence the results presented herein represent an important feedback for the realisation of world performance GaAs devices.

Atomic layer deposition of sub-10 nm high-K gate dielectrics on top-gated MoS2 transistors without surface functionalization

NASA Astrophysics Data System (ADS)

Lin, Yu-Shu; Cheng, Po-Hsien; Huang, Kuei-Wen; Lin, Hsin-Chih; Chen, Miin-Jang

2018-06-01

Sub-10 nm high-K gate dielectrics are of critical importance in two-dimensional transition metal dichalcogenides (TMDs) transistors. However, the chemical inertness of TMDs gives rise to a lot of pinholes in gate dielectrics, resulting in large gate leakage current. In this study, sub-10 nm, uniform and pinhole-free Al2O3 high-K gate dielectrics on MoS2 were achieved by atomic layer deposition without surface functionalization, in which an ultrathin Al2O3 layer prepared with a short purge time at a low temperature of 80 °C offers the nucleation cites for the deposition of the overlaying oxide at a higher temperature. Conductive atomic force microscopy reveals the significant suppression of gate leakage current in the sub-10 nm Al2O3 gate dielectrics with the low-temperature nucleation layer. Raman and X-ray photoelectron spectroscopies indicate that no oxidation occurred during the deposition of the low-temperature Al2O3 nucleation layer on MoS2. With the high-quality sub-10 nm Al2O3 high-K gate dielectrics, low hysteresis and subthreshold swing were demonstrated on the normally-off top-gated MoS2 transistors.

A study of nitrogen behavior in the formation of Ta/TaN and Ti/TaN alloyed metal electrodes on SiO2 and HfO2 dielectrics

NASA Astrophysics Data System (ADS)

Gassilloud, R.; Maunoury, C.; Leroux, C.; Piallat, F.; Saidi, B.; Martin, F.; Maitrejean, S.

2014-04-01

We studied Ta, TaN, and sub-stoichiometric TaNx electrodes (obtained by nitrogen redistribution in Ta/TaN or Ti/TaN bilayers) deposited on thermal SiO2 and HfO2/IL (0.8 nm SiO2 IL, i.e., interlayer) stacks. Effective work-functions (WF) were extracted on MOS capacitor structures on SiO2 bevelled insulator of 4.2 eV for pure Ta, 4.6 eV for TaN, and 4.3 eV for sub-stoichiometric TaNx. This intermediate WF value is explained by TaN nitrogen redistribution with reactive Ta or Ti elements shifting the gate work-function toward the Si conduction band. The same electrodes deposited on an HfO2/IL dielectric showed different behavior: First, the Ta/HfO2/IL stack shows a +200 meV WF increase (towards the Si valence band) compared to the SiO2 dielectric stack. This increase is explained by the well-known HfO2/IL dipole formation. Second, in contrast to electrodes deposited on SiO2, sub-stoichiometric TaNx/HfO2 is found to have a lower WF (4.3 eV), than pure Ta on HfO2 (4.4 eV). This inversion in work-function behavior measured on SiO2 vs. HfO2 is explained by the nitrogen redistribution in Ta/TaN bilayer together with diffusion of nitrogen through the HfO2 layer, leading to Si-N formation which prevents dipole formation at the HfO2/IL interface.

Hot-Carrier Immunity of Polycrystalline Silicon Thin Film Transistors Using Silicon Oxynitride Gate Dielectric Formed with Plasma-Enhanced Chemical Vapor Deposition

NASA Astrophysics Data System (ADS)

Kunii, Masafumi

2009-11-01

An analysis is presented of the hot-carrier degradation in a polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon oxynitride gate dielectric formed with plasma-enhanced chemical vapor deposition. An introduction of silicon oxynitride into a gate dielectric significantly improves hot-carrier immunity even under the severe stressing mode of drain avalanche hot carriers. To compensate the initial negative shift of threshold voltage for TFTs with a silicon oxynitride gate dielectric, high-pressure water vapor annealing (HWA) is applied. A comparison of TFTs with and without HWA reveals that the improvement in hot-carrier immunity is mainly attributed to the introduction of Si≡N bonds into a gate dielectric.

Stacking stability of MoS2 bilayer: An ab initio study

NASA Astrophysics Data System (ADS)

Tao, Peng; Guo, Huai-Hong; Yang, Teng; Zhang, Zhi-Dong

2014-10-01

The study of the stacking stability of bilayer MoS2 is essential since a bilayer has exhibited advantages over single layer MoS2 in many aspects for nanoelectronic applications. We explored the relative stability, optimal sliding path between different stacking orders of bilayer MoS2, and (especially) the effect of inter-layer stress, by combining first-principles density functional total energy calculations and the climbing-image nudge-elastic-band (CI-NEB) method. Among five typical stacking orders, which can be categorized into two kinds (I: AA, AB and II: AA', AB', A'B), we found that stacking orders with Mo and S superposing from both layers, such as AA' and AB, is more stable than the others. With smaller computational efforts than potential energy profile searching, we can study the effect of inter-layer stress on the stacking stability. Under isobaric condition, the sliding barrier increases by a few eV/(ucGPa) from AA' to AB', compared to 0.1 eV/(ucGPa) from AB to [AB]. Moreover, we found that interlayer compressive stress can help enhance the transport properties of AA'. This study can help understand why inter-layer stress by dielectric gating materials can be an effective means to improving MoS2 on nanoelectronic applications.

On gate stack scalability of double-gate negative-capacitance FET with ferroelectric HfO2 for energy efficient sub-0.2 V operation

NASA Astrophysics Data System (ADS)

Jang, Kyungmin; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2018-02-01

We have investigated the gate stack scalability and energy efficiency of double-gate negative-capacitance FET (DGNCFET) with a CMOS-compatible ferroelectric HfO2 (FE:HfO2). Analytic model-based simulation is conducted to investigate the impacts of ferroelectric characteristic of FE:HfO2 and gate stack thickness on the I on/I off ratio of DGNCFET. DGNCFET has wider design window for the gate stack where higher I on/I off ratio can be achieved than DG classical MOSFET. Under a process-induced constraint with sub-10 nm gate length (L g), FE:HfO2-based DGNCFET still has a design point for high I on/I off ratio. With an optimized gate stack thickness for sub-10 nm L g, FE:HfO2-based DGNCFET has 2.5× higher energy efficiency than DG classical MOSFET even at ultralow operation voltage of sub-0.2 V.

Reduced electron back-injection in Al2O3/AlOx/Al2O3/graphene charge-trap memory devices

NASA Astrophysics Data System (ADS)

Lee, Sejoon; Song, Emil B.; Min Kim, Sung; Lee, Youngmin; Seo, David H.; Seo, Sunae; Wang, Kang L.

2012-12-01

A graphene charge-trap memory is devised using a single-layer graphene channel with an Al2O3/AlOx/Al2O3 oxide stack, where the ion-bombarded AlOx layer is intentionally added to create an abundance of charge-trap sites. The low dielectric constant of AlOx compared to Al2O3 reduces the potential drop in the control oxide Al2O3 and suppresses the electron back-injection from the gate to the charge-storage layer, allowing the memory window of the device to be further extended. This shows that the usage of a lower dielectric constant in the charge-storage layer compared to that of the control oxide layer improves the memory performance for graphene charge-trap memories.

Metallorganic chemical vapor deposition and atomic layer deposition approaches for the growth of hafnium-based thin films from dialkylamide precursors for advanced CMOS gate stack applications

NASA Astrophysics Data System (ADS)

Consiglio, Steven P.

To continue the rapid progress of the semiconductor industry as described by Moore's Law, the feasibility of new material systems for front end of the line (FEOL) process technologies needs to be investigated, since the currently employed polysilicon/SiO2-based transistor system is reaching its fundamental scaling limits. Revolutionary breakthroughs in complementary-metal-oxide-semiconductor (CMOS) technology were recently announced by Intel Corporation and International Business Machines Corporation (IBM), with both organizations revealing significant progress in the implementation of hafnium-based high-k dielectrics along with metal gates. This announcement was heralded by Gordon Moore as "...the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s." Accordingly, the study described herein focuses on the growth of Hf-based dielectrics and Hf-based metal gates using chemical vapor-based deposition methods, specifically metallorganic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). A family of Hf source complexes that has received much attention recently due to their desirable properties for implementation in wafer scale manufacturing is the Hf dialkylamide precursors. These precursors are room temperature liquids and possess sufficient volatility and desirable decomposition characteristics for both MOCVD and ALD processing. Another benefit of using these sources is the existence of chemically compatible Si dialkylamide sources as co-precursors for use in Hf silicate growth. The first part of this study investigates properties of MOCVD-deposited HfO2 and HfSixOy using dimethylamido Hf and Si precursor sources using a customized MOCVD reactor. The second part of this study involves a study of wet and dry surface pre-treatments for ALD growth of HfO2 using tetrakis(ethylmethylamido)hafnium in a wafer scale manufacturing environment. The third part of this study is an investigation of the properties of conductive HfN grown via plasma-assisted atomic layer deposition (PA-ALD) using tetrakis(ethylmethylamido)hafnium on a modified commercially available wafer processing tool. Key properties of these materials for use as gate stack replacement materials are addressed and future directions for further characterization and novel material investigations are proposed.

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

NASA Astrophysics Data System (ADS)

Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

2018-06-01

The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

The Study of Electrical Properties for Multilayer La2O3/Al2O3 Dielectric Stacks and LaAlO3 Dielectric Film Deposited by ALD.

PubMed

Feng, Xing-Yao; Liu, Hong-Xia; Wang, Xing; Zhao, Lu; Fei, Chen-Xi; Liu, He-Lei

2017-12-01

The capacitance and leakage current properties of multilayer La 2 O 3 /Al 2 O 3 dielectric stacks and LaAlO 3 dielectric film are investigated in this paper. A clear promotion of capacitance properties is observed for multilayer La 2 O 3 /Al 2 O 3 stacks after post-deposition annealing (PDA) at 800 °C compared with PDA at 600 °C, which indicated the recombination of defects and dangling bonds performs better at the high-k/Si substrate interface for a higher annealing temperature. For LaAlO 3 dielectric film, compared with multilayer La 2 O 3 /Al 2 O 3 dielectric stacks, a clear promotion of trapped charges density (N ot ) and a degradation of interface trap density (D it ) can be obtained simultaneously. In addition, a significant improvement about leakage current property is observed for LaAlO 3 dielectric film compared with multilayer La 2 O 3 /Al 2 O 3 stacks at the same annealing condition. We also noticed that a better breakdown behavior for multilayer La 2 O 3 /Al 2 O 3 stack is achieved after annealing at a higher temperature for its less defects.

Solubility- and temperature-driven thin film structures of polymeric thiophene derivatives for high performance OFET applications

NASA Astrophysics Data System (ADS)

LeFevre, Scott W.; Bao, Zhenan; Ryu, Chang Y.; Siegel, Richard W.; Yang, Hoichang

2007-09-01

It has been shown that high charge mobility in solution-processible organic semiconductor-based field effect transistors is due in part to a highly parallel π-π stacking plane orientation of the semiconductors with respect to gate-dielectric. Fast solvent evaporation methods, generally, exacerbate kinetically random crystal orientations in the films deposited, specifically, from good solvents. We have investigated solubility-driven thin film structures of thiophene derivative polymers via spin- and drop-casting with volatile solvents of a low boiling point. Among volatile solvents examined, marginal solvents, which have temperature-dependent solubility for the semiconductors (e.g. methylene chloride for regioregular poly(3-alkylthiophene)s), can be used to direct the favorable crystal orientation regardless of solvent drying time, when the temperature of gate-dielectrics is held to relatively cooler than the warm solution. Grazing-incidence X-ray diffraction and atomic force microscopy strongly support that significant control of crystal orientation and mesoscale morphology using a "cold" substrate holds true for both drop and spin casting. The effects of physiochemical post-modificaiton on film crystal structures and morphologies of poly(9,9-dioctylfluorene-co-bithiophene) have also been investigated.

Remote interfacial dipole scattering and electron mobility degradation in Ge field-effect transistors with GeO x /Al2O3 gate dielectrics

NASA Astrophysics Data System (ADS)

Wang, Xiaolei; Xiang, Jinjuan; Wang, Shengkai; Wang, Wenwu; Zhao, Chao; Ye, Tianchun; Xiong, Yuhua; Zhang, Jing

2016-06-01

Remote Coulomb scattering (RCS) on electron mobility degradation is investigated experimentally in Ge-based metal-oxide-semiconductor field-effect-transistors (MOSFETs) with GeO x /Al2O3 gate stacks. It is found that the mobility increases with greater GeO x thickness (7.8-20.8 Å). The physical origin of this mobility dependence on GeO x thickness is explored. The following factors are excluded: Coulomb scattering due to interfacial traps at GeO x /Ge, phonon scattering, and surface roughness scattering. Therefore, the RCS from charges in gate stacks is studied. The charge distributions in GeO x /Al2O3 gate stacks are evaluated experimentally. The bulk charges in Al2O3 and GeO x are found to be negligible. The density of the interfacial charge is  +3.2  ×  1012 cm-2 at the GeO x /Ge interface and  -2.3  ×  1012 cm-2 at the Al2O3/GeO x interface. The electric dipole at the Al2O3/GeO x interface is found to be  +0.15 V, which corresponds to an areal charge density of 1.9  ×  1013 cm-2. The origin of this mobility dependence on GeO x thickness is attributed to the RCS due to the electric dipole at the Al2O3/GeO x interface. This remote dipole scattering is found to play a significant role in mobility degradation. The discovery of this new scattering mechanism indicates that the engineering of the Al2O3/GeO x interface is key for mobility enhancement and device performance improvement. These results are helpful for understanding and engineering Ge mobility enhancement.

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

NASA Astrophysics Data System (ADS)

Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

2013-06-01

In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fakhri, M.; Theisen, M.; Behrendt, A.

Top gated metal-oxide thin-film transistors (TFTs) provide two benefits compared to their conventional bottom-gate counterparts: (i) The gate dielectric may concomitantly serve as encapsulation layer for the TFT channel. (ii) Damage of the dielectric due to high-energetic particles during channel deposition can be avoided. In our work, the top-gate dielectric is prepared by ozone based atomic layer deposition at low temperatures. For ultra-low gas permeation rates, we introduce nano-laminates of Al{sub 2}O{sub 3}/ZrO{sub 2} as dielectrics. The resulting TFTs show a superior environmental stability even at elevated temperatures. Their outstanding stability vs. bias stress is benchmarked against bottom-gate devices withmore » encapsulation.« less

High-performance SEGISFET pH Sensor using the structure of double-gate a-IGZO TFTs with engineered gate oxides

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2017-03-01

In this paper, we propose a high-performance separative extended gate ion-sensitive field-effect transistor (SEGISFET) that consists of a tin dioxide (SnO2) SEG sensing part and a double-gate structure amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with tantalum pentoxide/silicon dioxide (Ta2O5/SiO2)-engineered top-gate oxide. To increase sensitivity, we maximized the capacitive coupling ratio by applying high-k dielectric at the top-gate oxide layer. As an engineered top-gate oxide, a stack of 25 nm-thick Ta2O5 and 10 nm-thick SiO2 layers was found to simultaneously satisfy a small equivalent oxide thickness (˜17.14 nm), a low leakage current, and a stable interfacial property. The threshold-voltage instability, which is a fundamental issue in a-IGZO TFTs, was improved by low-temperature post-deposition annealing (˜87 °C) using microwave irradiation. The double-gate structure a-IGZO TFTs with engineered top-gate oxide exhibited high mobility, small subthreshold swing, high drive current, and larger on/off current ratio. The a-IGZO SEGISFETs with a dual-gate sensing mode showed a pH sensitivity of 649.04 mV pH-1, which is far beyond the Nernst limit. The non-ideal behavior of ISFETs, hysteresis, and drift effect also improved. These results show that the double-gate structure a-IGZO TFTs with engineered top-gate oxide can be a good candidate for cheap and disposable SEGISFET sensors.

Comparative study of CAVET with dielectric and p-GaN gate and Mg ion-implanted current blocking layer

NASA Astrophysics Data System (ADS)

Mandal, Saptarshi; Agarwal, Anchal; Ahmadi, Elaheh; Mahadeva Bhat, K.; Laurent, Matthew A.; Keller, Stacia; Chowdhury, Srabanti

2017-08-01

In this work, a study of two different types of current aperture vertical electron transistor (CAVET) with ion-implanted blocking layer are presented. The device fabrication and performance limitation of a CAVET with a dielectric gate is discussed, and the breakdown limiting structure is evaluated using on-wafer test structures. The gate dielectric limited the device breakdown to 50V, while the blocking layer was able to withstand over 400V. To improve the device performance, an alternative CAVET structure with a p-GaN gate instead of dielectric is designed and realized. The pGaN gated CAVET structure increased the breakdown voltage to over 400V. Measurement of test structures on the wafer showed the breakdown was limited by the blocking layer instead of the gate p-n junction.

A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

NASA Astrophysics Data System (ADS)

Wallace, Robert M.

2001-03-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Metal-Halide Perovskites for Gate Dielectrics in Field-Effect Transistors and Photodetectors Enabled by PMMA Lift-Off Process.

PubMed

Daus, Alwin; Roldán-Carmona, Cristina; Domanski, Konrad; Knobelspies, Stefan; Cantarella, Giuseppe; Vogt, Christian; Grätzel, Michael; Nazeeruddin, Mohammad Khaja; Tröster, Gerhard

2018-06-01

Metal-halide perovskites have emerged as promising materials for optoelectronics applications, such as photovoltaics, light-emitting diodes, and photodetectors due to their excellent photoconversion efficiencies. However, their instability in aqueous solutions and most organic solvents has complicated their micropatterning procedures, which are needed for dense device integration, for example, in displays or cameras. In this work, a lift-off process based on poly(methyl methacrylate) and deep ultraviolet lithography on flexible plastic foils is presented. This technique comprises simultaneous patterning of the metal-halide perovskite with a top electrode, which results in microscale vertical device architectures with high spatial resolution and alignment properties. Hence, thin-film transistors (TFTs) with methyl-ammonium lead iodide (MAPbI 3 ) gate dielectrics are demonstrated for the first time. The giant dielectric constant of MAPbI 3 (>1000) leads to excellent low-voltage TFT switching capabilities with subthreshold swings ≈80 mV decade -1 over ≈5 orders of drain current magnitude. Furthermore, vertically stacked low-power Au-MAPbI 3 -Au photodetectors with close-to-ideal linear response (R 2 = 0.9997) are created. The mechanical stability down to a tensile radius of 6 mm is demonstrated for the TFTs and photodetectors, simultaneously realized on the same flexible plastic substrate. These results open the way for flexible low-power integrated (opto-)electronic systems based on metal-halide perovskites. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Paramagnetic defects and charge trapping behavior of ZrO2 films deposited on germanium by plasma-enhanced CVD

NASA Astrophysics Data System (ADS)

Mahata, C.; Bera, M. K.; Bose, P. K.; Maiti, C. K.

2009-02-01

Internal photoemission and magnetic resonance studies have been performed to investigate the charge trapping behavior and chemical nature of defects in ultrathin (~14 nm) high-k ZrO2 dielectric films deposited on p-Ge (1 0 0) substrates at low temperature (<200 °C) by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma at a pressure of ~65 Pa. Both the band and defect-related electron states have been characterized using electron paramagnetic resonance, internal photoemission, capacitance-voltage and current-voltage measurements under UV illumination. Capacitance-voltage and photocurrent-voltage measurements were used to determine the centroid of oxide charge within the high-k gate stack. The observed shifts in photocurrent response of the Al/ZrO2/GeO2/p-Ge metal-insulator-semiconductor (MIS) capacitors indicate the location of the centroids to be within the ZrO2 dielectric near to the gate electrode. Moreover, the measured flat band voltage and photocurrent shifts also indicate a large density of traps in the dielectric. The impact of plasma nitridation on the interfacial quality of the oxides has been investigated. Different N sources, such as NO and NH3, have been used for nitrogen engineering. Oxynitride samples show a lower defect density and trapping over the non-nitrided samples. The charge trapping and detrapping properties of MIS capacitors under stressing in constant current and voltage modes have been investigated in detail.

Implementation of atomic layer deposition-based AlON gate dielectrics in AlGaN/GaN MOS structure and its physical and electrical properties

NASA Astrophysics Data System (ADS)

Nozaki, Mikito; Watanabe, Kenta; Yamada, Takahiro; Shih, Hong-An; Nakazawa, Satoshi; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

Alumina incorporating nitrogen (aluminum oxynitride; AlON) for immunity against charge injection was grown on a AlGaN/GaN substrate through the repeated atomic layer deposition (ALD) of AlN layers and in situ oxidation in ozone (O3) ambient under optimized conditions. The nitrogen distribution was uniform in the depth direction, the composition was controllable over a wide range (0.5–32%), and the thickness could be precisely controlled. Physical analysis based on synchrotron radiation X-ray photoelectron spectroscopy (SR-XPS) revealed that harmful intermixing at the insulator/AlGaN interface causing Ga out-diffusion in the gate stack was effectively suppressed by this method. AlON/AlGaN/GaN MOS capacitors were fabricated, and they had excellent electrical properties and immunity against electrical stressing as a result of the improved interface stability.

Tunneling-injection in vertical quasi-2D heterojunctions enabled efficient and adjustable optoelectronic conversion

PubMed Central

Tan, Wei-Chun; Chiang, Chia-Wei; Hofmann, Mario; Chen, Yang-Fang

2016-01-01

The advent of 2D materials integration has enabled novel heterojunctions where carrier transport proceeds thrsough different ultrathin layers. We here demonstrate the potential of such heterojunctions on a graphene/dielectric/semiconductor vertical stack that combines several enabling features for optoelectronic devices. Efficient and stable light emission was achieved through carrier tunneling from the graphene injector into prominent states of a luminescent material. Graphene’s unique properties enable fine control of the band alignment in the heterojunction. This advantage was used to produce vertical tunneling-injection light-emitting transistors (VtiLET) where gating allows adjustment of the light emission intensity independent of applied bias. This device was shown to simultaneously act as a light detecting transistor with a linear and gate tunable sensitivity. The presented development of an electronically controllable multifunctional light emitter, light detector and transistor open up a new route for future optoelectronics. PMID:27507171

Tunneling-injection in vertical quasi-2D heterojunctions enabled efficient and adjustable optoelectronic conversion

NASA Astrophysics Data System (ADS)

Tan, Wei-Chun; Chiang, Chia-Wei; Hofmann, Mario; Chen, Yang-Fang

2016-08-01

The advent of 2D materials integration has enabled novel heterojunctions where carrier transport proceeds thrsough different ultrathin layers. We here demonstrate the potential of such heterojunctions on a graphene/dielectric/semiconductor vertical stack that combines several enabling features for optoelectronic devices. Efficient and stable light emission was achieved through carrier tunneling from the graphene injector into prominent states of a luminescent material. Graphene’s unique properties enable fine control of the band alignment in the heterojunction. This advantage was used to produce vertical tunneling-injection light-emitting transistors (VtiLET) where gating allows adjustment of the light emission intensity independent of applied bias. This device was shown to simultaneously act as a light detecting transistor with a linear and gate tunable sensitivity. The presented development of an electronically controllable multifunctional light emitter, light detector and transistor open up a new route for future optoelectronics.

The origin of excellent gate-bias stress stability in organic field-effect transistors employing fluorinated-polymer gate dielectrics.

PubMed

Kim, Jiye; Jang, Jaeyoung; Kim, Kyunghun; Kim, Haekyoung; Kim, Se Hyun; Park, Chan Eon

2014-11-12

Tuning of the energetic barriers to charge transfer at the semiconductor/dielectric interface in organic field-effect transistors (OFETs) is achieved by varying the dielectric functionality. Based on this, the correlation between the magnitude of the energy barrier and the gate-bias stress stability of the OFETs is demonstrated, and the origin of the excellent device stability of OFETs employing fluorinated dielectrics is revealed. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

PubMed

Kwon, Jimin; Takeda, Yasunori; Fukuda, Kenjiro; Cho, Kilwon; Tokito, Shizuo; Jung, Sungjune

2016-11-22

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Nanocomposites of polyimide and mixed oxide nanoparticles for high performance nanohybrid gate dielectrics in flexible thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Ju Hyun; Hwang, Byeong-Ung; Kim, Do-Il; Kim, Jin Soo; Seol, Young Gug; Kim, Tae Woong; Lee, Nae-Eung

2017-05-01

Organic gate dielectrics in thin film transistors (TFTs) for flexible display have advantages of high flexibility yet have the disadvantage of low dielectric constant (low- k). To supplement low- k characteristics of organic gate dielectrics, an organic/inorganic nanocomposite insulator loaded with high- k inorganic oxide nanoparticles (NPs) has been investigated but high loading of high- k NPs in polymer matrix is essential. Herein, compositing of over-coated polyimide (PI) on self-assembled (SA) layer of mixed HfO2 and ZrO2 NPs as inorganic fillers was used to make dielectric constant higher and leakage characteristics lower. A flexible TFT with lower the threshold voltage and high current on/off ratio could be fabricated by using the hybrid gate dielectric structure of the nanocomposite with SA layer of mixed NPs on ultrathin atomic-layer deposited Al2O3. [Figure not available: see fulltext.

Light-erasable embedded charge-trapping memory based on MoS2 for system-on-panel applications

NASA Astrophysics Data System (ADS)

He, Long-Fei; Zhu, Hao; Xu, Jing; Liu, Hao; Nie, Xin-Ran; Chen, Lin; Sun, Qing-Qing; Xia, Yang; Wei Zhang, David

2017-11-01

The continuous scaling and challenges in device integrations in modern portable electronic products have aroused many scientific interests, and a great deal of effort has been made in seeking solutions towards a more microminiaturized package assembled with smaller and more powerful components. In this study, an embedded light-erasable charge-trapping memory with a high-k dielectric stack (Al2O3/HfO2/Al2O3) and an atomically thin MoS2 channel has been fabricated and fully characterized. The memory exhibits a sufficient memory window, fast programming and erasing (P/E) speed, and high On/Off current ratio up to 107. Less than 25% memory window degradation is observed after projected 10-year retention, and the device functions perfectly after 8000 P/E operation cycles. Furthermore, the programmed device can be fully erased by incident light without electrical assistance. Such excellent memory performance originates from the intrinsic properties of two-dimensional (2D) MoS2 and the engineered back-gate dielectric stack. Our integration of 2D semiconductors in the infrastructure of light-erasable charge-trapping memory is very promising for future system-on-panel applications like storage of metadata and flexible imaging arrays.

Utilizing self-assembled-monolayer-based gate dielectrics to fabricate molybdenum disulfide field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kawanago, Takamasa, E-mail: kawanago.t.ab@m.titech.ac.jp; Oda, Shunri

In this study, we apply self-assembled-monolayer (SAM)-based gate dielectrics to the fabrication of molybdenum disulfide (MoS{sub 2}) field-effect transistors. A simple fabrication process involving the selective formation of a SAM on metal oxides in conjunction with the dry transfer of MoS{sub 2} flakes was established. A subthreshold slope (SS) of 69 mV/dec and no hysteresis were demonstrated with the ultrathin SAM-based gate dielectrics accompanied by a low gate leakage current. The small SS and no hysteresis indicate the superior interfacial properties of the MoS{sub 2}/SAM structure. Cross-sectional transmission electron microscopy revealed a sharp and abrupt interface of the MoS{sub 2}/SAM structure.more » The SAM-based gate dielectrics are found to be applicable to the fabrication of low-voltage MoS{sub 2} field-effect transistors and can also be extended to various layered semiconductor materials. This study opens up intriguing possibilities of SAM-based gate dielectrics in functional electronic devices.« less

Electrical characterization of 4H-SiC metal-oxide-semiconductor structure with Al2O3 stacking layers as dielectric

NASA Astrophysics Data System (ADS)

Chang, P. K.; Hwu, J. G.

2018-02-01

Interface defects and oxide bulk traps conventionally play important roles in the electrical performance of SiC MOS device. Introducing the Al2O3 stack grown by repeated anodization of Al films can notably lower the leakage current in comparison to the SiO2 structure, and enhance the minority carrier response at low frequency when the number of Al2O3 layers increase. In addition, the interface quality is not deteriorated by the stacking of Al2O3 layers because the stacked Al2O3 structure grown by anodization possesses good uniformity. In this work, the capacitance equivalent thickness (CET) of stacking Al2O3 will be up to 19.5 nm and the oxidation process can be carried out at room temperature. For the Al2O3 gate stack with CET 19.5 nm on n-SiC substrate, the leakage current at 2 V is 2.76 × 10-10 A/cm2, the interface trap density at the flatband voltage is 3.01 × 1011 eV-1 cm-2, and the effective breakdown field is 11.8 MV/cm. Frequency dispersion and breakdown characteristics may thus be improved as a result of the reduction in trap density. The Al2O3 stacking layers are capable of maintaining the leakage current as low as possible even after constant voltage stress test, which will further ameliorate reliability characteristics.

Dual-Gated MoTe2/MoS2 van der Waals Heterojunction p-n Diode

NASA Astrophysics Data System (ADS)

Rai, Amritesh; Movva, Hema C. P.; Kang, Sangwoo; Larentis, Stefano; Roy, Anupam; Tutuc, Emanuel; Banerjee, Sanjay K.

2D materials are promising for future electronic and optoelectronic applications. In this regard, it is important to realize p-n diodes, the most fundamental building block of all modern semiconductor devices, based on these 2D materials. While it is challenging to achieve homojunction diodes in 2D semiconductors due to lack of reliable selective doping techniques, it is relatively easier to achieve diode-like behavior in van der Waals (vdW) heterostructures comprising different 2D semiconductors. Here, we demonstrate dual-gated vdW heterojunction p-n diodes based on p-type MoTe2 and n-type MoS2, with hBN as the top and bottom gate dielectric. The heterostructure stack is assembled using a polymer-based `dry-transfer' technique. Pt contact is used for hole injection in MoTe2, whereas Ag is used for electron injection in MoS2. The dual-gates allow for independent electrostatic tuning of the carriers in MoTe2 and MoS2. Room temperature interlayer current-voltage characteristics reveal a strong gate-tunable rectification behavior. At low temperatures, the diode turn-on voltage increases, whereas the reverse saturation current decreases, in accordance with conventional p-n diode behavior. Dual-Gated MoTe2/MoS2 van der Waals Heterojunction p-n Diode.

High-k dielectric Al2O3 nanowire and nanoplate field effect sensors for improved pH sensing

PubMed Central

Reddy, Bobby; Dorvel, Brian R.; Go, Jonghyun; Nair, Pradeep R.; Elibol, Oguz H.; Credo, Grace M.; Daniels, Jonathan S.; Chow, Edmond K. C.; Su, Xing; Varma, Madoo; Alam, Muhammad A.

2011-01-01

Over the last decade, field-effect transistors (FETs) with nanoscale dimensions have emerged as possible label-free biological and chemical sensors capable of highly sensitive detection of various entities and processes. While significant progress has been made towards improving their sensitivity, much is yet to be explored in the study of various critical parameters, such as the choice of a sensing dielectric, the choice of applied front and back gate biases, the design of the device dimensions, and many others. In this work, we present a process to fabricate nanowire and nanoplate FETs with Al2O3 gate dielectrics and we compare these devices with FETs with SiO2 gate dielectrics. The use of a high-k dielectric such as Al2O3 allows for the physical thickness of the gate dielectric to be thicker without losing sensitivity to charge, which then reduces leakage currents and results in devices that are highly robust in fluid. This optimized process results in devices stable for up to 8 h in fluidic environments. Using pH sensing as a benchmark, we show the importance of optimizing the device bias, particularly the back gate bias which modulates the effective channel thickness. We also demonstrate that devices with Al2O3 gate dielectrics exhibit superior sensitivity to pH when compared to devices with SiO2 gate dielectrics. Finally, we show that when the effective electrical silicon channel thickness is on the order of the Debye length, device response to pH is virtually independent of device width. These silicon FET sensors could become integral components of future silicon based Lab on Chip systems. PMID:21203849

Time-dependent dielectric breakdown in pure and lightly Al-doped Ta2O5 stacks

NASA Astrophysics Data System (ADS)

Atanassova, E.; Stojadinović, N.; Spassov, D.; Manić, I.; Paskaleva, A.

2013-05-01

The time-dependent dielectric breakdown (TDDB) characteristics of 7 nm pure and lightly Al-doped Ta2O5 (equivalent oxide thickness of 2.2 and 1.5 nm, respectively) with W gate electrodes in MOS capacitor configuration are studied using gate injection and constant voltage stress. The effect of both the process-induced defects and the dopant on the breakdown distribution, and on the extracted Weibull slope values, are discussed. The pre-existing traps which provoke weak spots dictate early breakdowns. Their effect is compounded of both the stress-induced new traps generation (percolation model is valid) and the inevitable lower-k interface layer in the region with long time-to-breakdown. The domination of one of these competitive effects defines the mechanism of degradation: the trapping at pre-existing traps appears to dominate in Ta2O5; Al doping reduces defects in Ta2O5, the generation of new traps prevails over the charge trapping in the doped samples, and the mechanism of breakdown is more adequate to the percolation concept. The doping of high-k Ta2O5 even with small amount (5 at.%) may serve as an engineering solution for improving its TDDB characteristics and reliability.

Electrical Properties of Ultrathin Hf-Ti-O Higher k Gate Dielectric Films and Their Application in ETSOI MOSFET.

PubMed

Xiong, Yuhua; Chen, Xiaoqiang; Wei, Feng; Du, Jun; Zhao, Hongbin; Tang, Zhaoyun; Tang, Bo; Wang, Wenwu; Yan, Jiang

2016-12-01

Ultrathin Hf-Ti-O higher k gate dielectric films (~2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) ~9.4%, low equivalent gate oxide thickness (EOT) of ~0.69 nm and acceptable gate leakage current density of 0.61 A/cm 2 @ (V fb  - 1)V could be obtained. The conduction mechanism through the gate dielectric is dominated by the F-N tunneling in the gate voltage range of -0.5 to -2 V. Under the same physical thickness and process flow, lower EOT and higher I on /I off ratio could be obtained while using Hf-Ti-O as gate dielectric compared with HfO 2 . With Hf-Ti-O as gate dielectric, two ETSOI PMOSFETs with gate width/gate length (W/L) of 0.5 μm/25 nm and 3 μm/40 nm show good performances such as high I on , I on /I off ratio in the magnitude of 10 5 , and peak transconductance, as well as suitable threshold voltage (-0.3~-0.2 V). Particularly, ETSOI PMOSFETs show superior short-channel control capacity with DIBL <82 mV/V and subthreshold swing <70 mV/decade.

Low-voltage organic strain sensor on plastic using polymer/high- K inorganic hybrid gate dielectrics

NASA Astrophysics Data System (ADS)

Jung, Soyoun; Ji, Taeksoo; Varadan, Vijay K.

2007-12-01

In this paper, gate-induced pentacene semiconductor strain sensors based on hybrid-gate dielectrics using poly-vinylphenol (PVP) and high-K inorganic, Ta IIO 5 are fabricated on flexible substrates, polyethylene naphthalate (PEN). The Ta IIO 5 gate dielectric layer is combined with a thin PVP layer to obtain very smooth and hydrophobic surfaces which improve the molecular structures of pentacene films. The PVP-Ta IIO 5 hybrid-gate dielectric films exhibit a high dielectric capacitance and low leakage current. The sensors adopting thin film transistor (TFT)-like structures show a significantly reduced operating voltage (~6V), and good device characteristics with a field-effect mobility of 1.89 cm2/V•s, a threshold voltage of -0.5 V, and an on/off ratio of 10 3. The strain sensor, one of the practical applications in large-area organic electronics, was characterized with different bending radii of 50, 40, 30, and 20 mm. The sensor output signals were significantly improved with low-operating voltages.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Duan, Guo Xing; Hatchtel, Jordan; Shen, Xiao

Here, we investigate negative-bias temperature instabilities in SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics. The activation energies we measured for interface-trap charge buildup during negative-bias temperature stress were lower for SiGe channel pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si capping layers than for conventional Si channel pMOSFETs with SiO 2 gate dielectrics. Electron energy loss spectroscopy and scanning transmission electron microscopy images demonstrate that Ge atoms can diffuse from the SiGe layer into the Si capping layer, which is adjacent to the SiO 2/HfO 2 gate dielectric. Density functional calculations show that these Ge atoms reduce themore » strength of nearby Si-H bonds and that Ge-H bond energies are still lower, thereby reducing the activation energy for interface-trap generation for the SiGe devices. Moreover, activation energies for oxide-trap charge buildup during negative-bias temperature stress are similarly small for SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si pMOSFETs with SiO 2 gate dielectrics, suggesting that, in both cases, the oxide-trap charge buildup likely is rate-limited by hole tunneling into the near-interfacial SiO 2.« less

Designing hybrid gate dielectric for fully printing high-performance carbon nanotube thin film transistors

NASA Astrophysics Data System (ADS)

Li, Qian; Li, Shilong; Yang, Dehua; Su, Wei; Wang, Yanchun; Zhou, Weiya; Liu, Huaping; Xie, Sishen

2017-10-01

The electrical characteristics of carbon nanotube (CNT) thin-film transistors (TFTs) strongly depend on the properties of the gate dielectric that is in direct contact with the semiconducting CNT channel materials. Here, we systematically investigated the dielectric effects on the electrical characteristics of fully printed semiconducting CNT-TFTs by introducing the organic dielectrics of poly(methyl methacrylate) (PMMA) and octadecyltrichlorosilane (OTS) to modify SiO2 dielectric. The results showed that the organic-modified SiO2 dielectric formed a favorable interface for the efficient charge transport in s-SWCNT-TFTs. Compared to single-layer SiO2 dielectric, the use of organic-inorganic hybrid bilayer dielectrics dramatically improved the performances of SWCNT-TFTs such as mobility, threshold voltage, hysteresis and on/off ratio due to the suppress of charge scattering, gate leakage current and charge trapping. The transport mechanism is related that the dielectric with few charge trapping provided efficient percolation pathways for charge carriers, while reduced the charge scattering. High density of charge traps which could directly act as physical transport barriers and significantly restrict the charge carrier transport and, thus, result in decreased mobile carriers and low device performance. Moreover, the gate leakage phenomenon is caused by conduction through charge traps. So, as a component of TFTs, the gate dielectric is of crucial importance to the manufacture of high quality TFTs from the aspects of affecting the gate leakage current and device operation voltage, as well as the charge carrier transport. Interestingly, the OTS-modified SiO2 allows to directly print horizontally aligned CNT film, and the corresponding devices exhibited a higher mobility than that of the devices with the hybrid PMMA/SiO2 dielectric although the thickness of OTS layer is only ˜2.5 nm. Our present result may provide key guidance for the further development of printed nanomaterial electronics.

Performance comparison of single and dual metal dielectrically modulated TFETs for the application of label free biosensor

NASA Astrophysics Data System (ADS)

Verma, Madhulika; Sharma, Dheeraj; Pandey, Sunil; Nigam, Kaushal; Kondekar, P. N.

2017-01-01

In this work, we perform a comparative analysis between single and dual metal dielectrically modulated tunnel field-effect transistors (DMTFETs) for the application of label free biosensor. For this purpose, two different gate material with work-function as ϕM 1 and ϕM 2 are used in short-gate DMTFET, where ϕM 1 represents the work-function of gate M1 near to the drain end, while ϕM 2 denotes the work-function of gate M2 near to the source end. A nanogap cavity in the gate dielectric is formed by removing the selected portion of gate oxide for sensing the biomolecules. To investigate the sensitivity of these biosensors, dielectric constant and charge density within the cavity region are considered as governing parameters. The work-function of gate M2 is optimized and considered less than M1 to achieve abruptness at the source/channel junction, which results in better tunneling and improved ON-state current. The ATLAS device simulations show that dual metal SG-DMTFETs attains higher ON-state current and drain current sensitivity as compared to its counterpart device. Finally, a dual metal short-gate (DSG) biosensor is compared with the single metal short-gate (SG), single metal full-gate (FG), and dual metal full-gate (DFG) biosensors to analyse structurally enhanced conjugation effect on gate-channel coupling.

Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11,000 cm(2)/V·s.

PubMed

Smith, Casey; Qaisi, Ramy; Liu, Zhihong; Yu, Qingkai; Hussain, Muhammad Mustafa

2013-07-23

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11,000 cm(2)/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low tox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance.

Periodic dielectric structure for production of photonic band gap and method for fabricating the same

DOEpatents

Ozbay, Ekmel; Tuttle, Gary; Michel, Erick; Ho, Kai-Ming; Biswas, Rana; Chan, Che-Ting; Soukoulis, Costas

1995-01-01

A method for fabricating a periodic dielectric structure which exhibits a photonic band gap. Alignment holes are formed in a wafer of dielectric material having a given crystal orientation. A planar layer of elongate rods is then formed in a section of the wafer. The formation of the rods includes the step of selectively removing the dielectric material of the wafer between the rods. The formation of alignment holes and layers of elongate rods and wafers is then repeated to form a plurality of patterned wafers. A stack of patterned wafers is then formed by rotating each successive wafer with respect to the next-previous wafer, and then placing the successive wafer on the stack. This stacking results in a stack of patterned wafers having a four-layer periodicity exhibiting a photonic band gap.

High-κ gate dielectrics: Current status and materials properties considerations

NASA Astrophysics Data System (ADS)

Wilk, G. D.; Wallace, R. M.; Anthony, J. M.

2001-05-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward successful integration into the expected processing conditions for future CMOS technologies, especially due to their tendency to form at interfaces with Si (e.g. silicates). These pseudobinary systems also thereby enable the use of other high-κ materials by serving as an interfacial high-κ layer. While work is ongoing, much research is still required, as it is clear that any material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Threshold-Voltage Shifts in Organic Transistors Due to Self-Assembled Monolayers at the Dielectric: Evidence for Electronic Coupling and Dipolar Effects.

PubMed

Aghamohammadi, Mahdieh; Rödel, Reinhold; Zschieschang, Ute; Ocal, Carmen; Boschker, Hans; Weitz, R Thomas; Barrena, Esther; Klauk, Hagen

2015-10-21

The mechanisms behind the threshold-voltage shift in organic transistors due to functionalizing of the gate dielectric with self-assembled monolayers (SAMs) are still under debate. We address the mechanisms by which SAMs determine the threshold voltage, by analyzing whether the threshold voltage depends on the gate-dielectric capacitance. We have investigated transistors based on five oxide thicknesses and two SAMs with rather diverse chemical properties, using the benchmark organic semiconductor dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene. Unlike several previous studies, we have found that the dependence of the threshold voltage on the gate-dielectric capacitance is completely different for the two SAMs. In transistors with an alkyl SAM, the threshold voltage does not depend on the gate-dielectric capacitance and is determined mainly by the dipolar character of the SAM, whereas in transistors with a fluoroalkyl SAM the threshold voltages exhibit a linear dependence on the inverse of the gate-dielectric capacitance. Kelvin probe force microscopy measurements indicate this behavior is attributed to an electronic coupling between the fluoroalkyl SAM and the organic semiconductor.

Development of III-V p-MOSFETs with high-kappa gate stack for future CMOS applications

NASA Astrophysics Data System (ADS)

Nagaiah, Padmaja

As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, non-silicon materials and new device architectures are gradually being introduced to improve Si integrated circuit performance and continue transistor scaling. Recently, the replacement of SiO2 with a high-k material (HfO2) as gate dielectric has essentially removed one of the biggest advantages of Si as channel material. As a result, alternate high mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. III-V materials in particular have become of great interest as channel materials, owing to their superior electron transport properties. However, there are several critical challenges that need to be addressed before III-V based CMOS can replace Si CMOS technology. Some of these challenges include development of a high quality, thermally stable gate dielectric/III-V interface, and improvement in III-V p-channel hole mobility to complement the n-channel mobility, low source/drain resistance and integration onto Si substrate. In this thesis, we would be addressing the first two issues i.e. the development high performance III-V p-channels and obtaining high quality III-V/high-k interface. We start with using the device architecture of the already established InGaAs n-channels as a baseline to understand the effect of remote scattering from the high-k oxide and oxide/semiconductor interface on channel transport properties such as electron mobility and channel electron concentration. Temperature dependent Hall electron mobility measurements were performed to separate various scattering induced mobility limiting factors. Dependence of channel mobility on proximity of the channel to the oxide interface, oxide thickness, annealing conditions are discussed. The results from this work will be used in the design of the p-channel MOSFETs. Following this, InxGa1-xAs (x>0.53) is chosen as channel material for developing p-channel MOSFETs. Band engineering, strain induced valence band splitting and quantum confinement is used to improve channel hole mobility. Experimental results on the Hall hole mobility is presented for InxGa1-xAs channels with varying In content, thickness of the quantum well and temperature. Then, high mobility InxGa 1-xAs heterostructure thus obtained are integrated with in-situ deposited high-k gate oxide required for high performance p-MOSFET and discuss the challenges associated with the gated structure and draw conclusions on this material system. Antimonide based channel materials such as GaSb and InxGa 1-xSb are explored for III-V based p-MOSFETs in last two chapters. Options for Sb based strained QW channels to obtain maximum hole mobility by varying the strain, channel and barrier material, thickness of the layers etc. is discussed followed by the growth of these Sb channels on GaAs and InP substrates using molecular beam epitaxy. The physical properties of the structures such as the heterostructure quality, alloy content and surface roughness are examined via TEM, XRD and AFM. Following this, electrical measurement results on Hall hole mobility is presented. The effect of strain, alloy content, temperature and thickness on channel mobility and concentration is reported. Development of GaSb n- and p-MOS capacitor structures with in-situ deposited HfO2 gate oxide dielectric using in-situ deposited amorphous Si (a-Si) interface passivation layer (IPL) to improve the interface quality of high-k oxide and (In)GaSb surface is presented. In-situ deposited gate oxides such as Al2O3 and combination oxide of Al 2O3 and HfO2 with and without the a-Si IPL are also explored as alternate gate dielectrics. Subsequently, MOS capacitor structures using buried InGaSb QWs are demonstrated. Development of an inversion type bulk GaSb with implanted source-drain contacts and in-situ deposited gate oxide HfO2 gate oxide is discussed. The merits of biaxial compressive strain is demonstrated on strained surface and buried channel In0.36 Ga0.64Sb QW MOSFETs with thin top barrier and in-situ deposited a-Si IPL and high-k HfO2 as well as combination Al 2O3+HfO2 gate stacks and ex-situ atomic layer deposited (ALD) combination gate oxide and with thin 2 nm InAs surface passivation layer is presented. Finally, summary of the salient results from the different chapters is provided with recommendations for future research.

Formation of nanofilament field emission devices

DOEpatents

Morse, Jeffrey D.; Contolini, Robert J.; Musket, Ronald G.; Bernhardt, Anthony F.

2000-01-01

A process for fabricating a nanofilament field emission device. The process enables the formation of high aspect ratio, electroplated nanofilament structure devices for field emission displays wherein a via is formed in a dielectric layer and is self-aligned to a via in the gate metal structure on top of the dielectric layer. The desired diameter of the via in the dielectric layer is on the order of 50-200 nm, with an aspect ratio of 5-10. In one embodiment, after forming the via in the dielectric layer, the gate metal is passivated, after which a plating enhancement layer is deposited in the bottom of the via, where necessary. The nanofilament is then electroplated in the via, followed by removal of the gate passification layer, etch back of the dielectric, and sharpening of the nanofilament. A hard mask layer may be deposited on top of the gate metal and removed following electroplating of the nanofilament.

Impact of device engineering on analog/RF performances of tunnel field effect transistors

NASA Astrophysics Data System (ADS)

Vijayvargiya, V.; Reniwal, B. S.; Singh, P.; Vishvakarma, S. K.

2017-06-01

The tunnel field effect transistor (TFET) and its analog/RF performance is being aggressively studied at device architecture level for low power SoC design. Therefore, in this paper we have investigated the influence of the gate-drain underlap (UL) and different dielectric materials for the spacer and gate oxide on DG-TFET (double gate TFET) and its analog/RF performance for low power applications. Here, it is found that the drive current behavior in DG-TFET with a UL feature while implementing dielectric material for the spacer is different in comparison to that of DG-FET. Further, hetero gate dielectric-based DG-TFET (HGDG-TFET) is more resistive against drain-induced barrier lowering (DIBL) as compared to DG-TFET with high-k (HK) gate dielectric. Along with that, as compared to DG-FET, this paper also analyses the attributes of UL and dielectric material on analog/RF performance of DG-TFET in terms of transconductance (gm ), transconductance generation factor (TGF), capacitance, intrinsic resistance (Rdcr), cut-off frequency (F T), and maximum oscillation frequency (F max). The LK spacer-based HGDG-TFET with a gate-drain UL has the potential to improve the RF performance of device.

Improved linearity in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with nonlinear polarization dielectric

NASA Astrophysics Data System (ADS)

Gao, Tao; Xu, Ruimin; Kong, Yuechan; Zhou, Jianjun; Kong, Cen; Dong, Xun; Chen, Tangsheng

2015-06-01

We demonstrate highly improved linearity in a nonlinear ferroelectric of Pb(Zr0.52Ti0.48)-gated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). Distinct double-hump feature in the transconductance-gate voltage (gm-Vg) curve is observed, yielding remarkable enhancement in gate voltage swing as compared to MIS-HEMT with conventional linear gate dielectric. By incorporating the ferroelectric polarization into a self-consistent calculation, it is disclosed that in addition to the common hump corresponding to the onset of electron accumulation, the second hump at high current level is originated from the nonlinear polar nature of ferroelectric, which enhances the gate capacitance by increasing equivalent dielectric constant nonlinearly. This work paves a way for design of high linearity GaN MIS-HEMT by exploiting the nonlinear properties of dielectric.

Gate bias stress in pentacene field-effect-transistors: Charge trapping in the dielectric or semiconductor

NASA Astrophysics Data System (ADS)

Häusermann, R.; Batlogg, B.

2011-08-01

Gate bias stress instability in organic field-effect transistors (OFETs) is a major conceptual and device issue. This effect manifests itself by an undesirable shift of the transfer characteristics and is associated with long term charge trapping. We study the role of the dielectric and the semiconductor separately by producing OFETs with the same semiconductor (pentacene) combined with different dielectrics (SiO2 and Cytop). We show that it is possible to fabricate devices which are immune to gate bias stress. For other material combinations, charge trapping occurs in the semiconductor alone or in the dielectric.

Automated manufacturing process for DEAP stack-actuators

NASA Astrophysics Data System (ADS)

Tepel, Dominik; Hoffstadt, Thorben; Maas, Jürgen

2014-03-01

Dielectric elastomers (DE) are thin polymer films belonging to the class of electroactive polymers (EAP), which are coated with compliant and conductive electrodes on each side. Due to the influence of an electrical field, dielectric elastomers perform a large amount of deformation. In this contribution a manufacturing process of automated fabricated stack-actuators based on dielectric electroactive polymers (DEAP) are presented. First of all the specific design of the considered stack-actuator is explained and afterwards the development, construction and realization of an automated manufacturing process is presented in detail. By applying this automated process, stack-actuators with reproducible and homogeneous properties can be manufactured. Finally, first DEAP actuator modules fabricated by the mentioned process are validated experimentally.

A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered Zr x Si1- x O2 Gate dielectric and improved electrical and hysteresis performance

NASA Astrophysics Data System (ADS)

Hung, Chien-Hsiung; Wang, Shui-Jinn; Liu, Pang-Yi; Wu, Chien-Hung; Wu, Nai-Sheng; Yan, Hao-Ping; Lin, Tseng-Hsing

2017-04-01

The use of co-sputtered zirconium silicon oxide (Zr x Si1- x O2) gate dielectrics to improve the gate controllability of amorphous indium gallium zinc oxide (α-IGZO) thin-film transistors (TFTs) through a room-temperature fabrication process is proposed and demonstrated. With the sputtering power of the SiO2 target in the range of 0-150 W and with that of the ZrO2 target kept at 100 W, a dielectric constant ranging from approximately 28.1 to 7.8 is obtained. The poly-structure formation immunity of the Zr x Si1- x O2 dielectrics, reduction of the interface trap density suppression, and gate leakage current are examined. Our experimental results reveal that the Zr0.85Si0.15O2 gate dielectric can lead to significantly improved TFT subthreshold swing performance (103 mV/dec) and field effect mobility (33.76 cm2 V-1 s-1).

LaAlO{sub 3}/Si capacitors: Comparison of different molecular beam deposition conditions and their impact on electrical properties

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pelloquin, Sylvain; Baboux, Nicolas; Albertini, David

2013-01-21

A study of the structural and electrical properties of amorphous LaAlO{sub 3} (LAO)/Si thin films fabricated by molecular beam deposition (MBD) is presented. Two substrate preparation procedures have been explored namely a high temperature substrate preparation technique-leading to a step and terraces surface morphology-and a chemical HF-based surface cleaning. The LAO deposition conditions were improved by introducing atomic plasma-prepared oxygen instead of classical molecular O{sub 2} in the chamber. An Au/Ni stack was used as the top electrode for its electrical characteristics. The physico-chemical properties (surface topography, thickness homogeneity, LAO/Si interface quality) and electrical performance (capacitance and current versus voltagemore » and TunA current topography) of the samples were systematically evaluated. Deposition conditions (substrate temperature of 550 Degree-Sign C, oxygen partial pressure settled at 10{sup -6} Torr, and 550 W of power applied to the O{sub 2} plasma) and post-depositions treatments were investigated to optimize the dielectric constant ({kappa}) and leakage currents density (J{sub Gate} at Double-Vertical-Line V{sub Gate} Double-Vertical-Line = Double-Vertical-Line V{sub FB}- 1 Double-Vertical-Line ). In the best reproducible conditions, we obtained a LAO/Si layer with a dielectric constant of 16, an equivalent oxide thickness of 8.7 A, and J{sub Gate} Almost-Equal-To 10{sup -2}A/cm{sup 2}. This confirms the importance of LaAlO{sub 3} as an alternative high-{kappa} for ITRS sub-22 nm technology node.« less

Periodic dielectric structure for production of photonic band gap and method for fabricating the same

DOEpatents

Ozbay, E.; Tuttle, G.; Michel, E.; Ho, K.M.; Biswas, R.; Chan, C.T.; Soukoulis, C.

1995-04-11

A method is disclosed for fabricating a periodic dielectric structure which exhibits a photonic band gap. Alignment holes are formed in a wafer of dielectric material having a given crystal orientation. A planar layer of elongate rods is then formed in a section of the wafer. The formation of the rods includes the step of selectively removing the dielectric material of the wafer between the rods. The formation of alignment holes and layers of elongate rods and wafers is then repeated to form a plurality of patterned wafers. A stack of patterned wafers is then formed by rotating each successive wafer with respect to the next-previous wafer, and then placing the successive wafer on the stack. This stacking results in a stack of patterned wafers having a four-layer periodicity exhibiting a photonic band gap. 42 figures.

High-Mobility 6,13-Bis(triisopropylsilylethynyl) Pentacene Transistors Using Solution-Processed Polysilsesquioxane Gate Dielectric Layers.

PubMed

Matsuda, Yu; Nakahara, Yoshio; Michiura, Daisuke; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) is a low-temperature curable polymer that is compatible with low-cost plastic substrates. We cured PSQ gate dielectric layers by irradiation with ultraviolet light at ~60 °C, and used them for 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) thin film transistors (TFTs). The fabricated TFTs have shown the maximum and average hole mobility of 1.3 and 0.78 ± 0.3 cm2V-1s-1, which are comparable to those of the previously reported transistors using single-crystalline TIPS-pentacene micro-ribbons for their active layers and thermally oxidized SiO2 for their gate dielectric layers. Itis therefore demonstrated that PSQ is a promising polymer gate dielectric material for low-cost organic TFTs.

Dependence of Pentacene Crystal Growth on Dielectric Roughness for Fabrication of Flexible Field-Effect Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, H.; Yang, C; Kim, S

2010-01-01

The dependence of pentacene nanostructures on gate dielectric surfaces were investigated for flexible organic field-effect transistor (OFET) applications. Two bilayer types of polymer/aluminum oxide (Al{sub 2}O{sub 3}) gate dielectrics were fabricated on commercial Al foils laminated onto a polymer back plate. Some Al foils were directly used as gate electrodes, and others were smoothly polished by an electrolytic etching. These Al surfaces were then anodized and coated with poly({alpha}-methyl styrene) (PAMS). For PAMS/Al{sub 2}O{sub 3} dielectrics onto etched Al foils, surface roughness up to 1 nm could be reached, although isolated dimples with a lateral diameter of several micrometers weremore » still present. On PAMS/Al{sub 2}O{sub 3} dielectrics (surface roughness >40 nm) containing mechanical grooves of Al foil, average hole mobility ({mu}FET) of 50 nm thick pentacene-FETs under the low operating voltages (|V| < 6 V) was {approx}0.15 cm{sup 2} V{sup -1} s{sup -1}. In contrast, pentacene-FETs employing the etched Al gates exhibited {mu}FET of 0.39 cm{sup 2} V{sup -1} s{sup -1}, which was comparable to that of reference samples with PAMS/Al{sub 2}O{sub 3} dielectrics onto flat sputtered Al gates. Conducting-probe atomic force microscopy and two-dimensional X-ray diffraction of pentacene films with various thicknesses revealed different out-of-plane and in-plane crystal orderings of pentacene, depending on the surface roughness of the gate dielectrics.« less

Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

PubMed

Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

2015-03-04

Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

MOCVD of HfO2 and ZrO2 high-k gate dielectrics for InAlN/AlN/GaN MOS-HEMTs

NASA Astrophysics Data System (ADS)

Abermann, S.; Pozzovivo, G.; Kuzmik, J.; Strasser, G.; Pogany, D.; Carlin, J.-F.; Grandjean, N.; Bertagnolli, E.

2007-12-01

We apply metal organic chemical vapour deposition (MOCVD) of HfO2 and of ZrO2 from β-diketonate precursors to grow high-k gate dielectrics for InAlN/AlN/GaN metal oxide semiconductor (MOS)-high electron mobility transistors (HEMTs). High-k oxides of about 12 nm-14 nm are deposited for the MOS-HEMTs incorporating Ni/Au gates, whereas as a reference, Ni-contact-based 'conventional' Schottky-barrier (SB)-HEMTs are processed. The processed dielectrics decrease the gate current leakage of the HEMTs by about four orders of magnitude if compared with the SB-gated HEMTs and show superior device characteristics in terms of IDS and breakdown.

Integrated field emission array for ion desorption

DOEpatents

Resnick, Paul J; Hertz, Kristin L.; Holland, Christopher; Chichester, David

2016-08-23

An integrated field emission array for ion desorption includes an electrically conductive substrate; a dielectric layer lying over the electrically conductive substrate comprising a plurality of laterally separated cavities extending through the dielectric layer; a like plurality of conically-shaped emitter tips on posts, each emitter tip/post disposed concentrically within a laterally separated cavity and electrically contacting the substrate; and a gate electrode structure lying over the dielectric layer, including a like plurality of circular gate apertures, each gate aperture disposed concentrically above an emitter tip/post to provide a like plurality of annular gate electrodes and wherein the lower edge of each annular gate electrode proximate the like emitter tip/post is rounded. Also disclosed herein are methods for fabricating an integrated field emission array.

Integrated field emission array for ion desorption

DOEpatents

Resnick, Paul J; Hertz, Kristin L; Holland, Christopher; Chichester, David; Schwoebel, Paul

2013-09-17

An integrated field emission array for ion desorption includes an electrically conductive substrate; a dielectric layer lying over the electrically conductive substrate comprising a plurality of laterally separated cavities extending through the dielectric layer; a like plurality of conically-shaped emitter tips on posts, each emitter tip/post disposed concentrically within a laterally separated cavity and electrically contacting the substrate; and a gate electrode structure lying over the dielectric layer, including a like plurality of circular gate apertures, each gate aperture disposed concentrically above an emitter tip/post to provide a like plurality of annular gate electrodes and wherein the lower edge of each annular gate electrode proximate the like emitter tip/post is rounded. Also disclosed herein are methods for fabricating an integrated field emission array.

Electrolyte creepage barrier for liquid electrolyte fuel cells

DOEpatents

Li, Jian [Alberta, CA; Farooque, Mohammad [Danbury, CT; Yuh, Chao-Yi [New Milford, CT

2008-01-22

A dielectric assembly for electrically insulating a manifold or other component from a liquid electrolyte fuel cell stack wherein the dielectric assembly includes a substantially impermeable dielectric member over which electrolyte is able to flow and a barrier adjacent the dielectric member and having a porosity of less than 50% and greater than 10% so that the barrier is able to measurably absorb and chemically react with the liquid electrolyte flowing on the dielectric member to form solid products which are stable in the liquid electrolyte. In this way, the barrier inhibits flow or creepage of electrolyte from the dielectric member to the manifold or component to be electrically insulated from the fuel cell stack by the dielectric assembly.

Technology and characterization of Thin-Film Transistors (TFTs) with a-IGZO semiconductor and high-k dielectric layer

NASA Astrophysics Data System (ADS)

Mroczyński, R.; Wachnicki, Ł.; Gierałtowska, S.

2016-12-01

In this work, we present the design of the technology and fabrication of TFTs with amorphous IGZO semiconductor and high-k gate dielectric layer in the form of hafnium oxide (HfOx). In the course of this work, the IGZO fabrication was optimized by means of Taguchi orthogonal tables approach in order to obtain an active semiconductor with reasonable high concentration of charge carriers, low roughness and relatively high mobility. The obtained Thin-Film Transistors can be characterized by very good electrical parameters, i.e., the effective mobility (μeff ≍ 12.8 cm2V-1s-1) significantly higher than that for a-Si TFTs (μeff ≍ 1 cm2V-1s-1). However, the value of sub-threshold swing (i.e., 640 mV/dec) points that the interfacial properties of IGZO/HfOx stack is characterized by high value of interface states density (Dit) which, in turn, demands further optimization for future applications of the demonstrated TFT structures.

Interface engineering and reliability characteristics of hafnium dioxide with poly silicon gate and dual metal (ruthenium-tantalum alloy, ruthenium) gate electrode for beyond 65 nm technology

NASA Astrophysics Data System (ADS)

Kim, Young-Hee

Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is still necessary to understand what is intrinsic we can not change, or what is extrinsic one we can improve.

Effect of dual-dielectric hydrogen-diffusion barrier layers on the performance of low-temperature processed transparent InGaZnO thin-film transistors

NASA Astrophysics Data System (ADS)

Tari, Alireza; Wong, William S.

2018-02-01

Dual-dielectric SiOx/SiNx thin-film layers were used as back-channel and gate-dielectric barrier layers for bottom-gate InGaZnO (IGZO) thin-film transistors (TFTs). The concentration profiles of hydrogen, indium, gallium, and zinc oxide were analyzed using secondary-ion mass spectroscopy characterization. By implementing an effective H-diffusion barrier, the hydrogen concentration and the creation of H-induced oxygen deficiency (H-Vo complex) defects during the processing of passivated flexible IGZO TFTs were minimized. A bilayer back-channel passivation layer, consisting of electron-beam deposited SiOx on plasma-enhanced chemical vapor-deposition (PECVD) SiNx films, effectively protected the TFT active region from plasma damage and minimized changes in the chemical composition of the semiconductor layer. A dual-dielectric PECVD SiOx/PECVD SiNx gate-dielectric, using SiOx as a barrier layer, also effectively prevented out-diffusion of hydrogen atoms from the PECVD SiNx-gate dielectric to the IGZO channel layer during the device fabrication.

Ultrahigh near infrared photoresponsive organic field-effect transistors with lead phthalocyanine/C60 heterojunction on poly(vinyl alcohol) gate dielectric.

PubMed

Sun, Lei; Zhang, Jianping; Zhao, Feiyu; Luo, Xiao; Lv, Wenli; li, Yao; Ren, Qiang; Wen, Zhanwei; Peng, Yingquan; Liu, Xingyuan

2015-05-08

Performances of photoresponsive organic field-effect transistors (photOFETs) operating in the near infrared (NIR) region utilizing SiO2 as the gate dielectric is generally low due to low carrier mobility of the channel. We report on NIR photOFETs based on lead phthalocyanine (PbPc)/C60 heterojunction with ultrahigh photoresponsivity by utilizing poly(vinyl alcohol) (PVA) as the gate dielectric. For 808 nm NIR illumination of 1.69 mW cm(-2), an ultrahigh photoresponsivity of 21 A W(-1), and an external quantum efficiency of 3230% were obtained at a gate voltage of 30 V and a drain voltage of 80 V, which are 124 times and 126 times as large as the reference device with SiO2 as the gate dielectric, respectively. The ultrahigh enhancement of photoresponsivity is resulted from the huge increase of electron mobility of C60 film grown on PVA dielectric. AFM investigations revealed that the C60 film grown on PVA is much smooth and uniform and the grain size is much larger than that grown on SiO2 dielectric, which together results in four orders of magnitude increase of the field-effect electron mobility of C60 film.

A novel method of fabricating laminated silicone stack actuators with pre-strained dielectric layers

NASA Astrophysics Data System (ADS)

Hinitt, Andrew D.; Conn, Andrew T.

2014-03-01

In recent studies, stack based Dielectric Elastomer Actuators (DEAs) have been successfully used in haptic feedback and sensing applications. However, limitations in the fabrication method, and materials used to con- struct stack actuators constrain their force and displacement output per unit volume. This paper focuses on a fabrication process enabling a stacked elastomer actuator to withstand the high tensile forces needed for high power applications, such as mimetics for mammalian muscle contraction (i.e prostheses), whilst requiring low voltage for thickness-mode contractile actuation. Spun elastomer layers are bonded together in a pre-strained state using a conductive adhesive filler, forming a Laminated Inter-Penetrating Network (L-IPN) with repeatable and uniform electrode thickness. The resulting structure utilises the stored strain energy of the dielectric elas- tomer to compress the cured electrode composite material. The method is used to fabricate an L-IPN example, which demonstrated that the bonded L-IPN has high tensile strength normal to the lamination. Additionally, the uniformity and retained dielectric layer pre-strain of the L-IPN are confirmed. The described method is envisaged to be used in a semi-automated assembly of large-scale multi-layer stacks of pre-strained dielectric layers possessing a tensile strength in the range generated by mammalian muscle.

Analytical Modeling of Triple-Metal Hetero-Dielectric DG SON TFET

NASA Astrophysics Data System (ADS)

Mahajan, Aman; Dash, Dinesh Kumar; Banerjee, Pritha; Sarkar, Subir Kumar

2018-02-01

In this paper, a 2-D analytical model of triple-metal hetero-dielectric DG TFET is presented by combining the concepts of triple material gate engineering and hetero-dielectric engineering. Three metals with different work functions are used as both front- and back gate electrodes to modulate the barrier at source/channel and channel/drain interface. In addition to this, front gate dielectric consists of high-K HfO2 at source end and low-K SiO2 at drain side, whereas back gate dielectric is replaced by air to further improve the ON current of the device. Surface potential and electric field of the proposed device are formulated solving 2-D Poisson's equation and Young's approximation. Based on this electric field expression, tunneling current is obtained by using Kane's model. Several device parameters are varied to examine the behavior of the proposed device. The analytical model is validated with TCAD simulation results for proving the accuracy of our proposed model.

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors

PubMed Central

2013-01-01

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric. PMID:23294730

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors.

PubMed

Chen, Fa-Hsyang; Her, Jim-Long; Shao, Yu-Hsuan; Matsuda, Yasuhiro H; Pan, Tung-Ming

2013-01-08

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric.

HIGH-k GATE DIELECTRIC: AMORPHOUS Ta/La2O3 FILMS GROWN ON Si AT LOW PRESSURE

NASA Astrophysics Data System (ADS)

Bahari, Ali; Khorshidi, Zahra

2014-09-01

In the present study, Ta/La2O3 films (La2O3 doped with Ta2O5) as a gate dielectric were prepared using a sol-gel method at low pressure. Ta/La2O3 film has some hopeful properties as a gate dielectric of logic device. The structure and morphology of Ta/La2O3 films were studied using X-ray diffraction (XRD), atomic force microscopy (AFM) and scanning electron microscopy (SEM). Electrical properties of films were performed using capacitance-voltage (C-V) and current density-voltage (J-V) measurements. The optical bandgap of samples was studied by UV-visible optical absorbance measurement. The optical bandgap, Eopt, is determined from the absorbance spectra. The obtained results show that Ta/La2O3 film as a good gate dielectric has amorphous structure, good thermal stability, high dielectric constant (≈ 25), low leakage current and wide bandgap (≈ 4.7 eV).

A low-frequency noise model with carrier generation-recombination process for pentacene organic thin-film transistor

NASA Astrophysics Data System (ADS)

Han, C. Y.; Qian, L. X.; Leung, C. H.; Che, C. M.; Lai, P. T.

2013-07-01

By including the generation-recombination process of charge carriers in conduction channel, a model for low-frequency noise in pentacene organic thin-film transistors (OTFTs) is proposed. In this model, the slope and magnitude of power spectral density for low-frequency noise are related to the traps in the gate dielectric and accumulation layer of the OTFT for the first time. The model can well fit the measured low-frequency noise data of pentacene OTFTs with HfO2 or HfLaO gate dielectric, which validates this model, thus providing an estimate on the densities of traps in the gate dielectric and accumulation layer. It is revealed that the traps in the accumulation layer are much more than those in the gate dielectric, and so dominate the low-frequency noise of pentacene OTFTs.

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors.

PubMed

Chaure, Nandu B; Cammidge, Andrew N; Chambrier, Isabelle; Cook, Michael J; Cain, Markys G; Murphy, Craig E; Pal, Chandana; Ray, Asim K

2011-04-01

Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl) copper phthalocyanine (CuPc 6 ) were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs) in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO 2 ) as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS) resulted in values of 4×10 -2 cm 2 V -1 s -1 and 10 6 for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones.

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors

PubMed Central

Chaure, Nandu B; Cammidge, Andrew N; Chambrier, Isabelle; Cook, Michael J; Cain, Markys G; Murphy, Craig E; Pal, Chandana; Ray, Asim K

2011-01-01

Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl) copper phthalocyanine (CuPc6) were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs) in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO2) as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS) resulted in values of 4×10−2 cm2 V−1 s−1 and 106 for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones. PMID:27877383

X-band T/R switch with body-floating multi-gate PDSOI NMOS transistors

NASA Astrophysics Data System (ADS)

Park, Mingyo; Min, Byung-Wook

2018-03-01

This paper presents an X-band transmit/receive switch using multi-gate NMOS transistors in a silicon-on-insulator CMOS process. For low loss and high power handling capability, floating body multi-gate NMOS transistors are adopted instead of conventional stacked NMOS transistors, resulting in 53% reduction of transistor area. Comparing to the stacked NMOS transistors, the multi gate transistor shares the source and drain region between stacked transistors, resulting in reduced chip area and parasitics. The impedance between bodies of gates in multi-gate NMOS transistors is assumed to be very large during design and confirmed after measurement. The measured input 1 dB compression point is 34 dBm. The measured insertion losses of TX and RX modes are respectively 1.7 dB and 2.0 dB at 11 GHz, and the measured isolations of TX and RX modes are >27 dB and >20 dB in X-band, respectively. The chip size is 0.086 mm2 without pads, which is 25% smaller than the T/R switch with stacked transistors.

Oxygen vacancy defect engineering using atomic layer deposited HfAlOx in multi-layered gate stack

NASA Astrophysics Data System (ADS)

Bhuyian, M. N.; Sengupta, R.; Vurikiti, P.; Misra, D.

2016-05-01

This work evaluates the defects in high quality atomic layer deposited (ALD) HfAlOx with extremely low Al (<3% Al/(Al + Hf)) incorporation in the Hf based high-k dielectrics. The defect activation energy estimated by the high temperature current voltage measurement shows that the charged oxygen vacancies, V+/V2+, are the primary source of defects in these dielectrics. When Al is added in HfO2, the V+ type defects with a defect activation energy of Ea ˜ 0.2 eV modify to V2+ type to Ea ˜ 0.1 eV with reference to the Si conduction band. When devices were stressed in the gate injection mode for 1000 s, more V+ type defects are generated and Ea reverts back to ˜0.2 eV. Since Al has a less number of valence electrons than do Hf, the change in the co-ordination number due to Al incorporation seems to contribute to the defect level modifications. Additionally, the stress induced leakage current behavior observed at 20 °C and at 125 °C demonstrates that the addition of Al in HfO2 contributed to suppressed trap generation process. This further supports the defect engineering model as reduced flat-band voltage shifts were observed at 20 °C and at 125 °C.

Memristive behavior in a junctionless flash memory cell

DOE Office of Scientific and Technical Information (OSTI.GOV)

Orak, Ikram; Department of Physics, Faculty of Science and Art, Bingöl University, 12000 Bingöl; Ürel, Mustafa

2015-06-08

We report charge storage based memristive operation of a junctionless thin film flash memory cell when it is operated as a two terminal device by grounding the gate. Unlike memristors based on nanoionics, the presented device mode, which we refer to as the flashristor mode, potentially allows greater control over the memristive properties, allowing rational design. The mode is demonstrated using a depletion type n-channel ZnO transistor grown by atomic layer deposition (ALD), with HfO{sub 2} as the tunnel dielectric, Al{sub 2}O{sub 3} as the control dielectric, and non-stoichiometric silicon nitride as the charge storage layer. The device exhibits themore » pinched hysteresis of a memristor and in the unoptimized device, R{sub off}/R{sub on} ratios of about 3 are presented with low operating voltages below 5 V. A simplified model predicts R{sub off}/R{sub on} ratios can be improved significantly by adjusting the native threshold voltage of the devices. The repeatability of the resistive switching is excellent and devices exhibit 10{sup 6 }s retention time, which can, in principle, be improved by engineering the gate stack and storage layer properties. The flashristor mode can find use in analog information processing applications, such as neuromorphic computing, where well-behaving and highly repeatable memristive properties are desirable.« less

Effect of nanocomposite gate-dielectric properties on pentacene microstructure and field-effect transistor characteristics.

PubMed

Lee, Wen-Hsi; Wang, Chun-Chieh

2010-02-01

In this study, the effect of surface energy and roughness of the nanocomposite gate dielectric on pentacene morphology and electrical properties of pentacene OTFT are reported. Nanoparticles TiO2 were added in the polyimide matrix to form a nanocomposite which has a significantly different surface characteristic from polyimide, leading to a discrepancy in the structural properties of pentacene growth. A growth mode of pentacene deposited on the nanocomposite is proposed to explain successfully the effect of surface properties of nanocomposite gate dielectric such as surface energy and roughness on the pentacene morphology and electrical properties of OTFT. To obtain the lower surface energy and smoother surface of nanocomposite gate dielectric that is responsible for the desired crystalline, microstructure of pentacene and electrical properties of device, a bottom contact OTFT-pentacene deposited on the double-layer nanocomposite gate dielectric consisting of top smoothing layer of the neat polyimide and bottom layer of (PI+ nano-TiO2 particles) nanocomposite has been successfully demonstrated to exhibit very promising performance including high current on to off ratio of about 6 x 10(5), threshold voltage of -10 V and moderately high filed mobility of 0.15 cm2V(-1)s(-1).

Pentacene-based low voltage organic field-effect transistors with anodized Ta2O5 gate dielectric

NASA Astrophysics Data System (ADS)

Jeong, Yeon Taek; Dodabalapur, Ananth

2007-11-01

Pentacene-based low voltage organic field-effect transistors were realized using an anodized Ta2O5 gate dielectric. The Ta2O5 gate dielectric layer with a surface roughness of 1.3Å was obtained by anodizing an e-beam evaporated Ta film. The device exhibited values of saturation mobility, threshold voltage, and Ion/Ioff ratio of 0.45cm2/Vs, 0.56V, and 7.5×101, respectively. The gate leakage current was reduced by more than 70% with a hexamethyldisilazane (HMDS) treatment on the Ta2O5 layer. The HMDS treatment also resulted in enhanced mobility values and a larger pentacene grain size.

Nonlinear pulse propagation in one-dimensional metal-dielectric multilayer stacks: ultrawide bandwidth optical limiting.

PubMed

Scalora, Michael; Mattiucci, Nadia; D'Aguanno, Giuseppe; Larciprete, MariaCristina; Bloemer, Mark J

2006-01-01

We numerically study the nonlinear optical properties of metal-dielectric photonic band gap structures in the pulsed regime. We exploit the high chi3 of copper metal to induce nonlinear effects such as broadband optical limiting, self-phase modulation, and unusual spectral narrowing of high intensity pulses. We show that in a single pass through a typical, chirped multilayer stack nonlinear transmittance and peak powers can be reduced by nearly two orders of magnitude compared to low light intensity levels across the entire visible range. Chirping dielectric layer thickness dramatically improves the linear transmittance through the stack and achieves large fields inside the copper to access the large nonlinearity. At the same time, the linear properties of the stack block most of the remaining electromagnetic spectrum.

Radiation sensors based on the generation of mobile protons in organic dielectrics.

PubMed

Kapetanakis, Eleftherios; Douvas, Antonios M; Argitis, Panagiotis; Normand, Pascal

2013-06-26

A sensing scheme based on mobile protons generated by radiation, including ionizing radiation (IonR), in organic gate dielectrics is investigated for the development of metal-insulator-semiconductor (MIS)-type dosimeters. Application of an electric field to the gate dielectric moves the protons and thereby alters the flat band voltage (VFB) of the MIS device. The shift in the VFB is proportional to the IonR-generated protons and, therefore, to the IonR total dose. Triphenylsulfonium nonaflate (TPSNF) photoacid generator (PAG)-containing poly(methyl methacrylate) (PMMA) polymeric films was selected as radiation-sensitive gate dielectrics. The effects of UV (249 nm) and gamma (Co-60) irradiations on the high-frequency capacitance versus the gate voltage (C-VG) curves of the MIS devices were investigated for different total dose values. Systematic improvements in sensitivity can be accomplished by increasing the concentration of the TPSNF molecules embedded in the polymeric matrix.

Energy-loss return gate via liquid dielectric polarization.

PubMed

Kim, Taehun; Yong, Hyungseok; Kim, Banseok; Kim, Dongseob; Choi, Dukhyun; Park, Yong Tae; Lee, Sangmin

2018-04-12

There has been much research on renewable energy-harvesting techniques. However, owing to increasing energy demands, significant energy-related issues remain to be solved. Efforts aimed at reducing the amount of energy loss in electric/electronic systems are essential for reducing energy consumption and protecting the environment. Here, we design an energy-loss return gate system that reduces energy loss from electric/electronic systems by utilizing the polarization of liquid dielectrics. The use of a liquid dielectric material in the energy-loss return gate generates electrostatic potential energy while reducing the dielectric loss of the electric/electronic system. Hence, an energy-loss return gate can make breakthrough impacts possible by amplifying energy-harvesting efficiency, lowering the power consumption of electronics, and storing the returned energy. Our study indicates the potential for enhancing energy-harvesting technologies for electric/electronics systems, while increasing the widespread development of these systems.

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

PubMed

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Atomic layer deposition of dielectrics on graphene using reversibly physisorbed ozone.

PubMed

Jandhyala, Srikar; Mordi, Greg; Lee, Bongki; Lee, Geunsik; Floresca, Carlo; Cha, Pil-Ryung; Ahn, Jinho; Wallace, Robert M; Chabal, Yves J; Kim, Moon J; Colombo, Luigi; Cho, Kyeongjae; Kim, Jiyoung

2012-03-27

Integration of graphene field-effect transistors (GFETs) requires the ability to grow or deposit high-quality, ultrathin dielectric insulators on graphene to modulate the channel potential. Here, we study a novel and facile approach based on atomic layer deposition through ozone functionalization to deposit high-κ dielectrics (such as Al(2)O(3)) without breaking vacuum. The underlying mechanisms of functionalization have been studied theoretically using ab initio calculations and experimentally using in situ monitoring of transport properties. It is found that ozone molecules are physisorbed on the surface of graphene, which act as nucleation sites for dielectric deposition. The physisorbed ozone molecules eventually react with the metal precursor, trimethylaluminum to form Al(2)O(3). Additionally, we successfully demonstrate the performance of dual-gated GFETs with Al(2)O(3) of sub-5 nm physical thickness as a gate dielectric. Back-gated GFETs with mobilities of ~19,000 cm(2)/(V·s) are also achieved after Al(2)O(3) deposition. These results indicate that ozone functionalization is a promising pathway to achieve scaled gate dielectrics on graphene without leaving a residual nucleation layer. © 2012 American Chemical Society

Ablation of film stacks in solar cell fabrication processes

DOEpatents

Harley, Gabriel; Kim, Taeseok; Cousins, Peter John

2013-04-02

A dielectric film stack of a solar cell is ablated using a laser. The dielectric film stack includes a layer that is absorptive in a wavelength of operation of the laser source. The laser source, which fires laser pulses at a pulse repetition rate, is configured to ablate the film stack to expose an underlying layer of material. The laser source may be configured to fire a burst of two laser pulses or a single temporally asymmetric laser pulse within a single pulse repetition to achieve complete ablation in a single step.

Interfacial fields in organic field-effect transistors and sensors

NASA Astrophysics Data System (ADS)

Dawidczyk, Thomas J.

Organic electronics are currently being commercialized and present a viable alternative to conventional electronics. These organic materials offer the ability to chemically manipulate the molecule, allowing for more facile mass processing techniques, which in turn reduces the cost. One application where organic semiconductors (OSCs) are being investigated is sensors. This work evaluates an assortment of n- and p-channel semiconductors as organic field-effect transistor (OFET) sensors. The sensor responses to dinitrotoluene (DNT) vapor and solid along with trinitrotoluene (TNT) solid were studied. Different semiconductor materials give different magnitude and direction of electrical current response upon exposure to DNT. Additional OFET parameters---mobility and threshold voltage---further refine the response to the DNT with each OFET sensor requiring a certain gate voltage for an optimized response to the vapor. The pattern of responses has sufficient diversity to distinguish DNT from other vapors. To effectively use these OFET sensors in a circuit, the threshold voltage needs to be tuned for each transistor to increase the efficiency of the circuit and maximize the sensor response. The threshold voltage can be altered by embedding charges into the dielectric layer of the OFET. To study the quantity and energy of charges needed to alter the threshold voltage, charge carriers were injected into polystyrene (PS) and investigated with scanning Kelvin probe microscopy (SKPM) and thermally stimulated discharge current (TSDC). Lateral heterojunctions of pentacene/PS were scanned using SKPM, effectively observing polarization along a side view of a lateral nonvolatile organic field-effect transistor dielectric interface. TSDC was used to observe charge migration out of PS films and to estimate the trap energy level inside the PS, using the initial rise method. The process was further refined to create lateral heterojunctions that were actual working OFETs, consisting of a PS or poly (3-trifluoro)styrene (F-PS) gate dielectric and a pentacene OSC. The charge storage inside the dielectric was visualized with SKPM, correlated to a threshold voltage shift in the transistor operation, and related to bias stress as well. The SKPM method allows the dielectric/OSC interface of the OFET to be visualized without any alteration of the OFET. Furthermore, this technique allows for the observation of charge distribution between the two dielectric interfaces, PS and F-PS. The SKPM is used to visualize the charge from conventional gate biasing and also as a result of embedding charges deliberately into the dielectric to shift the threshold voltage. Conventional gate biasing shows considerable residual charge in the PS dielectric, which results in gate bias stress. Gate bias stress is one of the major hurdles left in the commercialization of OFETs. To prevent this bias stress, additives of different energy levels were inserted into the dielectric to limit the gate bias stress. Additionally, the dielectrics were pre-charged to try and prevent further bias stress. Neither pre-charging the dielectric or the addition of additive has been used in gate bias prevention, but both methods offer improved resistance to gate bias stress, and help to further refine the dielectric design.

Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

NASA Astrophysics Data System (ADS)

Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

2018-01-01

Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

High-frequency self-aligned graphene transistors with transferred gate stacks.

PubMed

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-07-17

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra-high-frequency circuits.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium-gallium-zinc oxide gate stack.

PubMed

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-20

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium-gallium-zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>10 4 ). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium–gallium–zinc oxide gate stack

NASA Astrophysics Data System (ADS)

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-01

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium–gallium–zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>104). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement

NASA Astrophysics Data System (ADS)

Raad, Bhagwan Ram; Nigam, Kaushal; Sharma, Dheeraj; Kondekar, P. N.

2016-06-01

This script features a study of bandgap, gate material work function and gate dielectric engineering for enhancement of DC and Analog/RF performance, reduction in the hot carriers effect (HCEs) and drain induced barrier lowering (DIBL) for better device reliability. In this concern, the use of band gap and gate material work function engineering improves the device performance in terms of the ON-state current and suppressed ambipolar behaviour with maintaining the low OFF-state current. With these advantages, the use of gate material work function engineering imposes restriction on the high frequency performance due to increment in the parasitic capacitances and also introduces the hot carrier effects. Hence, the gate dielectric engineering with bandgap and gate material work function engineering are used in this paper to overcome the cons of the gate material work function engineering by obtaining a superior performance in terms of the current driving capability, ambipolar conduction, HCEs, DIBL and high frequency parameters of the device for ultra-low power applications. Finally, the optimization of length for different work function is performed to get the best out of this.

Role of the dielectric for the charging dynamics of the dielectric/barrier interface in AlGaN/GaN based metal-insulator-semiconductor structures under forward gate bias stress

NASA Astrophysics Data System (ADS)

Lagger, P.; Steinschifter, P.; Reiner, M.; Stadtmüller, M.; Denifl, G.; Naumann, A.; Müller, J.; Wilde, L.; Sundqvist, J.; Pogany, D.; Ostermaier, C.

2014-07-01

The high density of defect states at the dielectric/III-N interface in GaN based metal-insulator-semiconductor structures causes tremendous threshold voltage drifts, ΔVth, under forward gate bias conditions. A comprehensive study on different dielectric materials, as well as varying dielectric thickness tD and barrier thickness tB, is performed using capacitance-voltage analysis. It is revealed that the density of trapped electrons, ΔNit, scales with the dielectric capacitance under spill-over conditions, i.e., the accumulation of a second electron channel at the dielectric/AlGaN barrier interface. Hence, the density of trapped electrons is defined by the charging of the dielectric capacitance. The scaling behavior of ΔNit is explained universally by the density of accumulated electrons at the dielectric/III-N interface under spill-over conditions. We conclude that the overall density of interface defects is higher than what can be electrically measured, due to limits set by dielectric breakdown. These findings have a significant impact on the correct interpretation of threshold voltage drift data and are of relevance for the development of normally off and normally on III-N/GaN high electron mobility transistors with gate insulation.

Comparison of conductor and dielectric inks in printed organic complementary transistors

NASA Astrophysics Data System (ADS)

Ng, Tse Nga; Mei, Ping; Whiting, Gregory L.; Schwartz, David E.; Abraham, Biby; Wu, Yiliang; Veres, Janos

2014-10-01

Two types of printable conductor and a bilayer gate dielectric are evaluated for use in all-additive, inkjetprinted complementary OTFTs. The Ag nanoparticle ink based on nonpolar alkyl amine surfactant or stabilizer enables good charge injection into p-channel devices, but this ink also leaves residual stabilizer that modifies the transistor backchannel and shifts the turn-on voltage to negative values. The Ag ink based on polar solvent requires dopant modification to improve charge injection to p-channel devices, but this ink allows the OTFT turn-on voltage to be close to 0 V. The reverse trend is observed for n-channel OTFTs. For gate insulator, a bilayer dielectric is demonstrated that combines the advantages of two types of insulator materials, in which a fluoropolymer reduces dipolar disorder at the semiconductor-dielectric interface, while a high-k PVDF terpolymer dielectric facilitates high gate capacitance. The dielectric is incorporated into an inverter and a three-stage ring oscillator, and the resulting circuits were demonstrated to operate at a supply voltage as low as 2 V, with bias stress levels comparable to circuits with other types of dielectrics.

Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tari, Alireza, E-mail: atari@uwaterloo.ca; Lee, Czang-Ho; Wong, William S.

Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer intomore » the IGZO and resulted in higher resistivity films.« less

FAST TRACK COMMUNICATION High mobility and low operating voltage ZnGaO and ZnGaLiO transistors with spin-coated Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Xia, D. X.; Xu, J. B.

2010-11-01

Spin-coated alumina serving as a gate dielectric in thin film transistors shows interesting dielectric properties for low-voltage applications, despite a moderate capacitance. With Ga singly doped and Ga, Li co-doped ZnO as the active channel layers, typical mobilities of 4.7 cm2 V-1 s-1 and 2.1 cm2 V-1 s-1 are achieved, respectively. At a given gate bias, the operation current is much smaller than the previously reported values in low-voltage thin film transistors, primarily relying on the giant-capacitive dielectric. The reported devices combine advantages of high mobility, low power consumption, low cost and ease of fabrication. In addition to the transparent nature of both the dielectric and semiconducting active channels, the superior electrical properties of the devices may provide a new avenue for future transparent electronics.

Improvement in the breakdown endurance of high-κ dielectric by utilizing stacking technology and adding sufficient interfacial layer.

PubMed

Pang, Chin-Sheng; Hwu, Jenn-Gwo

2014-01-01

Improvement in the time-zero dielectric breakdown (TZDB) endurance of metal-oxide-semiconductor (MOS) capacitor with stacking structure of Al/HfO2/SiO2/Si is demonstrated in this work. The misalignment of the conduction paths between two stacking layers is believed to be effective to increase the breakdown field of the devices. Meanwhile, the resistance of the dielectric after breakdown for device with stacking structure would be less than that of without stacking structure due to a higher breakdown field and larger breakdown power. In addition, the role of interfacial layer (IL) in the control of the interface trap density (D it) and device reliability is also analyzed. Device with a thicker IL introduces a higher breakdown field and also a lower D it. High-resolution transmission electron microscopy (HRTEM) of the samples with different IL thicknesses is provided to confirm that IL is needed for good interfacial property.

All 2D, high mobility, flexible, transparent thin film transistor

DOEpatents

Das, Saptarshi; Sumant, Anirudha V.; Roelofs, Andreas

2017-01-17

A two-dimensional thin film transistor and a method for manufacturing a two-dimensional thin film transistor includes layering a semiconducting channel material on a substrate, providing a first electrode material on top of the semiconducting channel material, patterning a source metal electrode and a drain metal electrode at opposite ends of the semiconducting channel material from the first electrode material, opening a window between the source metal electrode and the drain metal electrode, removing the first electrode material from the window located above the semiconducting channel material providing a gate dielectric above the semiconducting channel material, and providing a top gate above the gate dielectric, the top gate formed from a second electrode material. The semiconducting channel material is made of tungsten diselenide, the first electrode material and the second electrode material are made of graphene, and the gate dielectric is made of hexagonal boron nitride.

Dual-band absorption of mid-infrared metamaterial absorber based on distinct dielectric spacing layers.

PubMed

Zhang, Nan; Zhou, Peiheng; Cheng, Dengmu; Weng, Xiaolong; Xie, Jianliang; Deng, Longjiang

2013-04-01

We present the simulation, fabrication, and characterization of a dual-band metamaterial absorber in the mid-infrared regime. Two pairs of circular-patterned metal-dielectric stacks are employed to excite the dual-band absorption peaks. Dielectric characteristics of the dielectric spacing layer determine energy dissipation in each resonant stack, i.e., dielectric or ohmic loss. By controlling material parameters, both two mechanisms are introduced into our structure. Up to 98% absorption is obtained at 9.03 and 13.32 μm in the simulation, which is in reasonable agreement with experimental results. The proposed structure holds promise for various applications, e.g., thermal radiation modulators and multicolor infrared focal plane arrays.

Role of deposition and annealing of the top gate dielectric in a-IGZO TFT-based dual-gate ion-sensitive field-effect transistors

NASA Astrophysics Data System (ADS)

Kumar, Narendra; Sutradhar, Moitri; Kumar, Jitendra; Panda, Siddhartha

2017-03-01

The deposition of the top gate dielectric in thin film transistor (TFT)-based dual-gate ion-sensitive field-effect transistors (DG ISFETs) is critical, and expected not to affect the bottom gate TFT characteristics, while providing a higher pH sensitive surface and efficient capacitive coupling between the gates. Amorphous Ta2O5, in addition to having good sensing properties, possesses a high dielectric constant of ˜25 making it well suited as the top gate dielectric in a DG ISFET by providing higher capacitive coupling (ratio of C top/C bottom) leading to higher amplification. To avoid damage of the a-IGZO channel reported to be caused by plasma exposure, deposition of Ta2O5 by e-beam evaporation followed by annealing was investigated in this work to obtain sensitivity over the Nernst limit. The deteriorated bottom gate TFT characteristics, indicated by an increase in the channel conductance, confirmed that plasma exposure is not the sole contributor to the changes. Oxygen vacancies at the Ta2O5/a-IGZO interface, which emerged during processing, increased the channel conductivity, became filled by optimum annealing in oxygen at 400 °C for 1 h, which was confirmed by an x-ray photoelectron spectroscopy depth profiling analysis. The obtained pH sensitivity of the TFT-based DG ISFET was 402 mV pH-1, which is about 6.8 times the Nernst limit (59 mV pH-1). The concept of capacitive coupling was also demonstrated by simulating an a-IGZO-based DG TFT structure. Here, the exposure of the top gate dielectric to the electrolyte without applying any top gate bias led to changes in the measured threshold voltage of the bottom gate TFT, and this obviated the requirement of a reference electrode needed in conventional ISFETs and other reported DG ISFETs. These devices, with high sensitivities and requiring low volumes (˜2 μl) of analyte solution, could be potential candidates for utilization as chemical sensors and biosensors.

Dielectric collapse at the LaAlO 3/SrTiO 3 (001) heterointerface under applied electric field

DOE Office of Scientific and Technical Information (OSTI.GOV)

Minohara, M.; Hikita, Y.; Bell, C.

The fascinating interfacial transport properties at the LaAlO 3/SrTiO 3 heterointerface have led to intense investigations of this oxide system. Exploiting the large dielectric constant of SrTiO 3 at low temperatures, tunability in the interfacial conductivity over a wide range has been demonstrated using a back-gate device geometry. In order to understand the effect of back-gating, it is crucial to assess the interface band structure and its evolution with external bias. In this study, we report measurements of the gate-bias dependent interface band alignment, especially the confining potential profile, at the conducting LaAlO 3/SrTiO 3 (001) heterointerface using soft andmore » hard x-ray photoemission spectroscopy in conjunction with detailed model simulations. Depth-profiling analysis incorporating the electric field dependent dielectric constant in SrTiO 3 reveals that a significant potential drop on the SrTiO 3 side of the interface occurs within ~2 nm of the interface under negative gate-bias. These results demonstrate gate control of the collapse of the dielectric permittivity at the interface, and explain the dramatic loss of electron mobility with back-gate depletion.« less

Dielectric collapse at the LaAlO 3/SrTiO 3 (001) heterointerface under applied electric field

DOE PAGES

Minohara, M.; Hikita, Y.; Bell, C.; ...

2017-08-25

The fascinating interfacial transport properties at the LaAlO 3/SrTiO 3 heterointerface have led to intense investigations of this oxide system. Exploiting the large dielectric constant of SrTiO 3 at low temperatures, tunability in the interfacial conductivity over a wide range has been demonstrated using a back-gate device geometry. In order to understand the effect of back-gating, it is crucial to assess the interface band structure and its evolution with external bias. In this study, we report measurements of the gate-bias dependent interface band alignment, especially the confining potential profile, at the conducting LaAlO 3/SrTiO 3 (001) heterointerface using soft andmore » hard x-ray photoemission spectroscopy in conjunction with detailed model simulations. Depth-profiling analysis incorporating the electric field dependent dielectric constant in SrTiO 3 reveals that a significant potential drop on the SrTiO 3 side of the interface occurs within ~2 nm of the interface under negative gate-bias. These results demonstrate gate control of the collapse of the dielectric permittivity at the interface, and explain the dramatic loss of electron mobility with back-gate depletion.« less

Performance of PZT stacks under high-field electric cycling at various temperatures in heavy-duty diesel engine fuel injectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Hong; Lin, Hua-Tay; Stafford, Mr Randy

2016-01-01

Testing and characterization of large prototype lead zirconate titanate (PZT) stacks present substantial technical challenges to electronic systems. The work in this study shows that an alternative approach can be pursued by using subunits extracted from prototype stacks. Piezoelectric and dielectric integrity was maintained even though the PZT plate specimens experienced an additional loading process involved with the extraction after factory poling. Extracted 10-layer plate specimens were studied by an electric cycle test under an electric field of 3.0/0.0 kV/mm, 100 Hz to 108 cycles, both at room temperature (22 C) and at 50 C. The elevated temperature had amore » defined impact on the fatigue of PZT stacks. About 48 and 28% reductions were observed in the piezoelectric and dielectric coefficients, respectively, after 108 cycles at 50 C, compared with reductions of 25 and 15% in the respective coefficients at 22 C. At the same time, the loss tangent varied to a limited extent. The evolution of PZT electrode interfacial layers or nearby dielectric layers should account for the difference in the fatigue rates of piezoelectric and dielectric coefficients. But the basic contribution to observed fatigue may result from the buildup of a bias field that finally suppressed the motion of the domain walls. Finally, monitoring of dielectric coefficients can be an effective tool for on-line lifetime prediction of PZT stacks in service if a failure criterion is defined properly.« less

Performance of PZT stacks under high-field electric cycling at various temperatures in heavy-duty diesel engine fuel injectors

NASA Astrophysics Data System (ADS)

Wang, Hong; Lee, Sung-Min; Lin, Hua-Tay; Stafford, Randy

2016-04-01

Testing and characterization of large prototype lead zirconate titanate (PZT) stacks present substantial technical challenges to electronic systems. The work in this study shows that an alternative approach can be pursued by using subunits extracted from prototype stacks. Piezoelectric and dielectric integrity was maintained even though the PZT plate specimens experienced an additional loading process involved with the extraction after factory poling. Extracted 10-layer plate specimens were studied by an electric cycle test under an electric field of 3.0/0.0 kV/mm, 100 Hz to 108 cycles, both at room temperature (22°C) and at 50°C. The elevated temperature had a defined impact on the fatigue of PZT stacks. About 48 and 28% reductions were observed in the piezoelectric and dielectric coefficients, respectively, after 108 cycles at 50°C, compared with reductions of 25 and 15% in the respective coefficients at 22°C. At the same time, the loss tangent varied to a limited extent. The evolution of PZT-electrode interfacial layers or nearby dielectric layers should account for the difference in the fatigue rates of piezoelectric and dielectric coefficients. But the basic contribution to observed fatigue may result from the buildup of a bias field that finally suppressed the motion of the domain walls. Finally, monitoring of dielectric coefficients can be an effective tool for on-line lifetime prediction of PZT stacks in service if a failure criterion is defined properly.

Morphology and electronic transport of polycrystalline pentacene thin-film transistors

NASA Astrophysics Data System (ADS)

Knipp, D.; Street, R. A.; Völkel, A. R.

2003-06-01

Temperature-dependent measurements of thin-film transistors were performed to gain insight in the electronic transport of polycrystalline pentacene. Devices were fabricated with plasma-enhanced chemical vapor deposited silicon nitride gate dielectrics. The influence of the dielectric roughness and the deposition temperature of the thermally evaporated pentacene films were studied. Although films on rougher gate dielectrics and films prepared at low deposition temperatures exhibit similar grain size, the electronic properties are different. Increasing the dielectric roughness reduces the free carrier mobility, while low substrate temperature leads to more and deeper hole traps.

High kappa Dielectrics on InGaAs and GaN - Growth, Interfacial Structural Studies, and Surface Fermi Level Unpinning

DTIC Science & Technology

2011-04-20

ALD-Al2O3 and in-situ MBE-Al2O3/ Ga2O3 (Gd2O3) [GGO] as the gate dielectrics. The advances of the InGaAs MOSFETs achieved will enable future CMOS...and GaN MOSFETs:  High-performance self-aligned inversion-channel In0.53Ga0.47As and In0.75Ga0.25As MOSFET’s with Al2O3/ Ga2O3 (Gd2O3) as gate... Ga2O3 (Gd2O3) as gate dielectrics Key accomplishments in devices of 1m gate length: High drain current of 1.23 mA/m High transcoductance of 714

Effects of negative gate-bias stress on the performance of solution-processed zinc-oxide transistors

NASA Astrophysics Data System (ADS)

Kim, Dongwook; Lee, Woo-Sub; Shin, Hyunji; Choi, Jong Sun; Zhang, Xue; Park, Jaehoon; Hwang, Jaeeun; Kim, Hongdoo; Bae, Jin-Hyuk

2014-08-01

We studied the effects of negative gate-bias stress on the electrical characteristics of top-contact zinc-oxide (ZnO) thin-film transistors (TFTs), which were fabricated by spin coating a ZnO solution onto a silicon-nitride gate dielectric layer. The negative gate-bias stress caused characteristic degradations in the on-state currents and the field-effect mobility of the fabricated ZnO TFTs. Additionally, a decrease in the off-state currents and a positive shift in the threshold voltage occurred with increasing stress time. These results indicate that the negative gate-bias stress caused an injection of electrons into the gate dielectric, thereby deteriorating the TFT's performance.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

NASA Astrophysics Data System (ADS)

Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

Method of doping organic semiconductors

DOEpatents

Kloc,; Christian Leo; Ramirez; Arthur Penn; So, Woo-Young

2010-10-26

An apparatus has a crystalline organic semiconducting region that includes polyaromatic molecules. A source electrode and a drain electrode of a field-effect transistor are both in contact with the crystalline organic semiconducting region. A gate electrode of the field-effect transistor is located to affect the conductivity of the crystalline organic semiconducting region between the source and drain electrodes. A dielectric layer of a first dielectric that is substantially impermeable to oxygen is in contact with the crystalline organic semiconducting region. The crystalline organic semiconducting region is located between the dielectric layer and a substrate. The gate electrode is located on the dielectric layer. A portion of the crystalline organic semiconducting region is in contact with a second dielectric via an opening in the dielectric layer. A physical interface is located between the second dielectric and the first dielectric.

High-frequency self-aligned graphene transistors with transferred gate stacks

PubMed Central

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-01-01

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra–high-frequency circuits. PMID:22753503

Bi-layer channel structure-based oxide thin-film transistors consisting of ZnO and Al-doped ZnO with different Al compositions and stacking sequences

NASA Astrophysics Data System (ADS)

Cho, Sung Woon; Yun, Myeong Gu; Ahn, Cheol Hyoun; Kim, So Hee; Cho, Hyung Koun

2015-03-01

Zinc oxide (ZnO)-based bi-layers, consisting of ZnO and Al-doped ZnO (AZO) layers grown by atomic layer deposition, were utilized as the channels of oxide thin-film transistors (TFTs). Thin AZO layers (5 nm) with different Al compositions (5 and 14 at. %) were deposited on top of and beneath the ZnO layers in a bi-layer channel structure. All of the bi-layer channel TFTs that included the AZO layers showed enhanced stability (Δ V Th ≤ 3.2 V) under a positive bias stress compared to the ZnO single-layer channel TFT (Δ V Th = 4.0 V). However, the AZO/ZnO bi-layer channel TFTs with an AZO interlayer between the gate dielectric and the ZnO showed a degraded field effect mobility (0.3 cm2/V·s for 5 at. % and 1.8 cm2/V·s for 14 at. %) compared to the ZnO single-layer channel TFT (5.5 cm2/V·s) due to increased scattering caused by Al-related impurities near the gate dielectric/channel interface. In contrast, the ZnO/AZO bi-layer channel TFTs with an AZO layer on top of the ZnO layer exhibited an improved field effect mobility (7.8 cm2/V·s for 14 at. %) and better stability. [Figure not available: see fulltext.

Device performance of in situ steam generated gate dielectric nitrided by remote plasma nitridation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Al-Shareef, H. N.; Karamcheti, A.; Luo, T. Y.

2001-06-11

In situ steam generated (ISSG) oxides have recently attracted interest for use as gate dielectrics because of their demonstrated reliability improvement over oxides formed by dry oxidation. [G. Minor, G. Xing, H. S. Joo, E. Sanchez, Y. Yokota, C. Chen, D. Lopes, and A. Balakrishna, Electrochem. Soc. Symp. Proc. 99-10, 3 (1999); T. Y. Luo, H. N. Al-Shareef, G. A. Brown, M. Laughery, V. Watt, A. Karamcheti, M. D. Jackson, and H. R. Huff, Proc. SPIE 4181, 220 (2000).] We show in this letter that nitridation of ISSG oxide using a remote plasma decreases the gate leakage current of ISSGmore » oxide by an order of magnitude without significantly degrading transistor performance. In particular, it is shown that the peak normalized transconductance of n-channel devices with an ISSG oxide gate dielectric decreases by only 4% and the normalized drive current by only 3% after remote plasma nitridation (RPN). In addition, it is shown that the reliability of the ISSG oxide exhibits only a small degradation after RPN. These observations suggest that the ISSG/RPN process holds promise for gate dielectric applications. {copyright} 2001 American Institute of Physics.« less

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO₂ Gate Dielectrics by CF₄ Plasma Treatment.

PubMed

Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

2018-05-17

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO₂ gate insulator and CF₄ plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO₂ gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm²/V∙s (without treatment) to 54.6 cm²/V∙s (with CF₄ plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO₂ gate dielectric has also been improved by the CF₄ plasma treatment. By applying the CF₄ plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device's immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF₄ plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO₂ gate dielectric, but also enhances the device's reliability.

Relationship between effective mobility and border traps associated with charge trapping in In0.7Ga0.3As MOSFETs with various high-κ stacks

NASA Astrophysics Data System (ADS)

Kwon, Hyuk-Min; Kim, Dae-Hyun; Kim, Tae-Woo

2018-03-01

The effective mobility and reliability characteristics of In0.7Ga0.3As quantum-well (QW) MOSFETs with various high-κ gate stacks and HEMTs with a Schottky gate under bias temperature instability (BTI) stress were investigated. The effective mobilities (μeff) of HEMTs, single-layer Al2O3, bilayer Al2O3 (0.6 nm)/HfO2 (2.0 nm), and Al2O3 (0.6 nm)/HfO2 (3.0 nm) were ˜9000, ˜6158, ˜4789, and ˜4447 cm2 V-1 s-1 at N inv = 1.5 × 1012/cm2, respectively. The maximum effective mobility of In0.7Ga0.3As channel MOSFETs was compared with that of In0.7Ga0.3As/In0.48Al0.52As HEMTs, which are interface and border trap-free FETs. The results showed that the effective channel mobility was sensitive to traps in high-κ dielectrics related to interface trap density and border traps in the oxide. The ΔV T degradation of the bilayer Al2O3/HfO2 under BTI stress was greater than that of a single Al2O3 layer because the HfO2 layer had a high density of oxygen vacancies which were related to border traps.

High- k Gate Dielectrics for Emerging Flexible and Stretchable Electronics.

PubMed

Wang, Binghao; Huang, Wei; Chi, Lifeng; Al-Hashimi, Mohammed; Marks, Tobin J; Facchetti, Antonio

2018-05-22

Recent advances in flexible and stretchable electronics (FSE), a technology diverging from the conventional rigid silicon technology, have stimulated fundamental scientific and technological research efforts. FSE aims at enabling disruptive applications such as flexible displays, wearable sensors, printed RFID tags on packaging, electronics on skin/organs, and Internet-of-things as well as possibly reducing the cost of electronic device fabrication. Thus, the key materials components of electronics, the semiconductor, the dielectric, and the conductor as well as the passive (substrate, planarization, passivation, and encapsulation layers) must exhibit electrical performance and mechanical properties compatible with FSE components and products. In this review, we summarize and analyze recent advances in materials concepts as well as in thin-film fabrication techniques for high- k (or high-capacitance) gate dielectrics when integrated with FSE-compatible semiconductors such as organics, metal oxides, quantum dot arrays, carbon nanotubes, graphene, and other 2D semiconductors. Since thin-film transistors (TFTs) are the key enablers of FSE devices, we discuss TFT structures and operation mechanisms after a discussion on the needs and general requirements of gate dielectrics. Also, the advantages of high- k dielectrics over low- k ones in TFT applications were elaborated. Next, after presenting the design and properties of high- k polymers and inorganic, electrolyte, and hybrid dielectric families, we focus on the most important fabrication methodologies for their deposition as TFT gate dielectric thin films. Furthermore, we provide a detailed summary of recent progress in performance of FSE TFTs based on these high- k dielectrics, focusing primarily on emerging semiconductor types. Finally, we conclude with an outlook and challenges section.

Modeling of mechanical properties of stack actuators based on electroactive polymers

NASA Astrophysics Data System (ADS)

Tepel, Dominik; Graf, Christian; Maas, Jürgen

2013-04-01

Dielectric elastomers are thin polymer films belonging to the class of electroactive polymers, which are coated with compliant and conductive electrodes on each side. Under the influence of an electrical field, dielectric elastomers perform a large amount of deformation. Depending on the mechanical setup, stack and roll actuators can be realized. In this contribution the mechanical properties of stack actuators are modeled by a holistic electromechanical approach of a single actuator film, by which the model of a stack actuator without constraints can be derived. Due to the mechanical connection between the stack actuator and the application, bulges occur at the free surfaces of the EAP material, which are calculated, experimentally validated and considered in the model of the stack actuator. Finally, the analytic actuator film model as well as the stack actuator model are validated by comparison to numerical FEM-models in ANSYS.

Phase Modulator with Terahertz Optical Bandwidth Formed by Multi-Layered Dielectric Stack

NASA Technical Reports Server (NTRS)

Keys, Andrew S. (Inventor); Fork, Richard L. (Inventor)

2005-01-01

An optical phase modulator includes a bandpass multilayer stack, formed by a plurality of dielectric layers, preferably of GaAs and AlAs, and having a transmission function related to the refractive index of the layers of the stack, for receiving an optical input signal to be phase modulated. A phase modulator device produces a nonmechanical change in the refractive index of each layer of the stack by, e.g., the injection of free carrier, to provide shifting of the transmission function so as to produce phase modulation of the optical input signal and to thereby produce a phase modulated output signal.

Fluorinated graphene as high performance dielectric materials and the applications for graphene nanoelectronics.

PubMed

Ho, Kuan-I; Huang, Chi-Hsien; Liao, Jia-Hong; Zhang, Wenjing; Li, Lain-Jong; Lai, Chao-Sung; Su, Ching-Yuan

2014-07-31

There is broad interest in surface functionalization of 2D materials and its related applications. In this work, we present a novel graphene layer transistor fabricated by introducing fluorinated graphene (fluorographene), one of the thinnest 2D insulator, as the gate dielectric material. For the first time, the dielectric properties of fluorographene, including its dielectric constant, frequency dispersion, breakdown electric field and thermal stability, were comprehensively investigated. We found that fluorographene with extremely thin thickness (5 nm) can sustain high resistance at temperature up to 400 °C. The measured breakdown electric field is higher than 10 MV cm(-1), which is the heightest value for dielectric materials in this thickness. Moreover, a proof-of-concept methodology, one-step fluorination of 10-layered graphene, is readily to obtain the fluorographene/graphene heterostructures, where the top-gated transistor based on this structure exhibits an average carrier mobility above 760 cm(2)/Vs, higher than that obtained when SiO₂ and GO were used as gate dielectric materials. The demonstrated fluorographene shows excellent dielectric properties with fast and scalable processing, providing a universal applications for the integration of versatile nano-electronic devices.

Fluorinated Graphene as High Performance Dielectric Materials and the Applications for Graphene Nanoelectronics

PubMed Central

Ho, Kuan-I; Huang, Chi-Hsien; Liao, Jia-Hong; Zhang, Wenjing; Li, Lain-Jong; Lai, Chao-Sung; Su, Ching-Yuan

2014-01-01

There is broad interest in surface functionalization of 2D materials and its related applications. In this work, we present a novel graphene layer transistor fabricated by introducing fluorinated graphene (fluorographene), one of the thinnest 2D insulator, as the gate dielectric material. For the first time, the dielectric properties of fluorographene, including its dielectric constant, frequency dispersion, breakdown electric field and thermal stability, were comprehensively investigated. We found that fluorographene with extremely thin thickness (5 nm) can sustain high resistance at temperature up to 400°C. The measured breakdown electric field is higher than 10 MV cm−1, which is the heightest value for dielectric materials in this thickness. Moreover, a proof-of-concept methodology, one-step fluorination of 10-layered graphene, is readily to obtain the fluorographene/graphene heterostructures, where the top-gated transistor based on this structure exhibits an average carrier mobility above 760 cm2/Vs, higher than that obtained when SiO2 and GO were used as gate dielectric materials. The demonstrated fluorographene shows excellent dielectric properties with fast and scalable processing, providing a universal applications for the integration of versatile nano-electronic devices. PMID:25081226

Effect of gate bias sweep rate on the threshold voltage of in-plane gate nanowire transistor

NASA Astrophysics Data System (ADS)

Liu, H. X.; Li, J.; Tan, R. R.

2018-01-01

In2O3 nanowire electric-double-layer (EDL) transistors with in-plane gate gated by SiO2 solid-electrolyte are fabricated on transparent glass substrates. The gate voltage sweep rates can effectively modulate the threshold voltage (Vth) of nanowire device. Both depletion mode and enhancement mode are realized, and the Vth shift of the nanowire transistors is estimated to be 0.73V (without light). This phenomenon is due to increased adsorption of oxygen on the nanowire surface by the slower gate voltage sweep rates. Adsorbed oxygens capture electrons and cause a surface of nanowire channel was depleted. The operation voltage of transistor was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance. These transparent in-plane gate nanowire transistors are promising for “see-through” nanoscale sensors.

Top-gate dielectric induced doping and scattering of charge carriers in epitaxial graphene

NASA Astrophysics Data System (ADS)

Puls, Conor P.; Staley, Neal E.; Moon, Jeong-Sun; Robinson, Joshua A.; Campbell, Paul M.; Tedesco, Joseph L.; Myers-Ward, Rachael L.; Eddy, Charles R.; Gaskill, D. Kurt; Liu, Ying

2011-07-01

We show that an e-gun deposited dielectric impose severe limits on epitaxial graphene-based device performance based on Raman spectroscopy and low-temperature transport measurements. Specifically, we show from studies of epitaxial graphene Hall bars covered by SiO2 that the measured carrier density is strongly inhomogenous and predominantly induced by charged impurities at the grapheme/dielectric interface that limit mobility via Coulomb interactions. Our work emphasizes that material integration of epitaxial graphene and a gate dielectric is the next major road block towards the realization of graphene-based electronics.

Improved memory characteristics by NH3-nitrided GdO as charge storage layer for nonvolatile memory applications

NASA Astrophysics Data System (ADS)

Liu, L.; Xu, J. P.; Ji, F.; Chen, J. X.; Lai, P. T.

2012-07-01

Charge-trapping memory capacitor with nitrided gadolinium oxide (GdO) as charge storage layer (CSL) is fabricated, and the influence of post-deposition annealing in NH3 on its memory characteristics is investigated. Transmission electron microscopy, x-ray photoelectron spectroscopy, and x-ray diffraction are used to analyze the cross-section and interface quality, composition, and crystallinity of the stack gate dielectric, respectively. It is found that nitrogen incorporation can improve the memory window and achieve a good trade-off among the memory properties due to NH3-annealing-induced reasonable distribution profile of a large quantity of deep-level bulk traps created in the nitrided GdO film and reduction of shallow traps near the CSL/SiO2 interface.

Improved linearity in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with nonlinear polarization dielectric

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, Tao; Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Devices Institute, Nanjing 210016; Xu, Ruimin

2015-06-15

We demonstrate highly improved linearity in a nonlinear ferroelectric of Pb(Zr{sub 0.52}Ti{sub 0.48})-gated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). Distinct double-hump feature in the transconductance-gate voltage (g{sub m}-V{sub g}) curve is observed, yielding remarkable enhancement in gate voltage swing as compared to MIS-HEMT with conventional linear gate dielectric. By incorporating the ferroelectric polarization into a self-consistent calculation, it is disclosed that in addition to the common hump corresponding to the onset of electron accumulation, the second hump at high current level is originated from the nonlinear polar nature of ferroelectric, which enhances the gate capacitance by increasing equivalent dielectricmore » constant nonlinearly. This work paves a way for design of high linearity GaN MIS-HEMT by exploiting the nonlinear properties of dielectric.« less

Anomalous bias-stress-induced unstable phenomena of InZnO thin-film transistors using Ta2O5 gate dielectric

NASA Astrophysics Data System (ADS)

Xu, Wangying; Dai, Mingzhi; Liang, Lingyan; Liu, Zhimin; Sun, Xilian; Wan, Qing; Cao, Hongtao

2012-05-01

InZnO thin-film transistors using high-κ Ta2O5 gate dielectric are presented and analysed. The large capacitance coupling effect of amorphous Ta2O5 results in fabricated devices with good electrical properties. However, an anomalous negative threshold voltage (Vth) shift under positive bias stress is observed. It is suggested that electron detrapping from the high-κ Ta2O5 dielectric to the gate electrode is responsible for this Vth shift, which is supported both by the logarithmical dependence of the Vth change on the duration of the bias stress and device simulation extracted trapped charges involved.

Threshold Voltage Instability in A-Si:H TFTS and the Implications for Flexible Displays and Circuits

DTIC Science & Technology

2008-12-01

and negative gate voltages with and without elevated drain voltages for FDC TFTs. Extending techniques used to localize hot electron degradation...in MOSFETs, experiments in our lab have localized the degradation of a-Si:H to the gate dielectric/a-Si:H channel interface [Shringarpure, et al...saturation, increased drain source current measured with the source and drain reversed indicates localization of ΔVth to the gate dielectric/amorphous

A two-dimensional analytical modeling for channel potential and threshold voltage of short channel triple material symmetrical gate Stack (TMGS) DG-MOSFET

NASA Astrophysics Data System (ADS)

Tripathi, Shweta

2016-10-01

In the present work, a two-dimensional (2D) analytical framework of triple material symmetrical gate stack (TMGS) DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS™ device simulator to affirm and formalize the proposed device structure.

Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jin, Jong Woo; Nathan, Arokia, E-mail: an299@cam.ac.uk; Barquinha, Pedro

2016-08-15

Oxide semiconductor thin-film transistors can show anomalous behavior under bias stress. Two types of anomalies are discussed in this paper. The first is the shift in threshold voltage (V{sub TH}) in a direction opposite to the applied bias stress, and highly dependent on gate dielectric material. We attribute this to charge trapping/detrapping and charge migration within the gate dielectric. We emphasize the fundamental difference between trapping/detrapping events occurring at the semiconductor/dielectric interface and those occurring at gate/dielectric interface, and show that charge migration is essential to explain the first anomaly. We model charge migration in terms of the non-instantaneous polarizationmore » density. The second type of anomaly is negative V{sub TH} shift under high positive bias stress, with logarithmic evolution in time. This can be argued as electron-donating reactions involving H{sub 2}O molecules or derived species, with a reaction rate exponentially accelerated by positive gate bias and exponentially decreased by the number of reactions already occurred.« less

Nanowire FET Based Neural Element for Robotic Tactile Sensing Skin

PubMed Central

Taube Navaraj, William; García Núñez, Carlos; Shakthivel, Dhayalan; Vinciguerra, Vincenzo; Labeau, Fabrice; Gregory, Duncan H.; Dahiya, Ravinder

2017-01-01

This paper presents novel Neural Nanowire Field Effect Transistors (υ-NWFETs) based hardware-implementable neural network (HNN) approach for tactile data processing in electronic skin (e-skin). The viability of Si nanowires (NWs) as the active material for υ-NWFETs in HNN is explored through modeling and demonstrated by fabricating the first device. Using υ-NWFETs to realize HNNs is an interesting approach as by printing NWs on large area flexible substrates it will be possible to develop a bendable tactile skin with distributed neural elements (for local data processing, as in biological skin) in the backplane. The modeling and simulation of υ-NWFET based devices show that the overlapping areas between individual gates and the floating gate determines the initial synaptic weights of the neural network - thus validating the working of υ-NWFETs as the building block for HNN. The simulation has been further extended to υ-NWFET based circuits and neuronal computation system and this has been validated by interfacing it with a transparent tactile skin prototype (comprising of 6 × 6 ITO based capacitive tactile sensors array) integrated on the palm of a 3D printed robotic hand. In this regard, a tactile data coding system is presented to detect touch gesture and the direction of touch. Following these simulation studies, a four-gated υ-NWFET is fabricated with Pt/Ti metal stack for gates, source and drain, Ni floating gate, and Al2O3 high-k dielectric layer. The current-voltage characteristics of fabricated υ-NWFET devices confirm the dependence of turn-off voltages on the (synaptic) weight of each gate. The presented υ-NWFET approach is promising for a neuro-robotic tactile sensory system with distributed computing as well as numerous futuristic applications such as prosthetics, and electroceuticals. PMID:28979183

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-01

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

PubMed

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-17

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Low leakage current gate dielectrics prepared by ion beam assisted deposition for organic thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Chang Su; Jo, Sung Jin; Kim, Jong Bok; Ryu, Seung Yoon; Noh, Joo Hyon; Baik, Hong Koo; Lee, Se Jong; Kim, Youn Sang

2007-12-01

This communication reports on the fabrication of low operating voltage pentacene thin-film transistors with high-k gate dielectrics by ion beam assisted deposition (IBAD). These densely packed dielectric layers by IBAD show a much lower level of leakage current than those created by e-beam evaporation. These results, from the fact that those thin films deposited with low adatom mobility, have an open structure, consisting of spherical grains with pores in between, that acts as a significant path for leakage current. By contrast, our results demonstrate the potential to limit this leakage. The field effect mobility, on/off current ratio, and subthreshold slope obtained from pentacene thin-film transistors (TFTs) were 1.14 cm2/V s, 105, and 0.41 V/dec, respectively. Thus, the high-k gate dielectrics obtained by IBAD show promise in realizing low leakage current, low voltage, and high mobility pentacene TFTs.

Broadening of Distribution of Trap States in PbS Quantum Dot Field-Effect Transistors with High-k Dielectrics

PubMed Central

2017-01-01

We perform a quantitative analysis of the trap density of states (trap DOS) in PbS quantum dot field-effect transistors (QD-FETs), which utilize several polymer gate insulators with a wide range of dielectric constants. With increasing gate dielectric constant, we observe increasing trap DOS close to the lowest unoccupied molecular orbital (LUMO) of the QDs. In addition, this increase is also consistently followed by broadening of the trap DOS. We rationalize that the increase and broadening of the spectral trap distribution originate from dipolar disorder as well as polaronic interactions, which are appearing at strong dielectric polarization. Interestingly, the increased polaron-induced traps do not show any negative effect on the charge carrier mobility in our QD devices at the highest applied gate voltage, giving the possibility to fabricate efficient low-voltage QD devices without suppressing carrier transport. PMID:28084725

Materials properties of hafnium and zirconium silicates: Metal interdiffusion and dopant penetration studies

NASA Astrophysics Data System (ADS)

Quevedo Lopez, Manuel Angel

Hafnium and Zirconium based gate dielectrics are considered potential candidates to replace SiO2 or SiON as the gate dielectric in CMOS processing. Furthermore, the addition of nitrogen into this pseudo-binary alloy has been shown to improve their thermal stability, electrical properties, and reduce dopant penetration. Because CMOS processing requires high temperature anneals (up to 1050°C), it is important to understand the diffusion properties of any metal associated with the gate dielectric in silicon at these temperatures. In addition, dopant penetration from the doped polysilicon gate into the Si channel at these temperatures must also be studied. Impurity outdiffusion (Hf, Zr) from the dielectric, or dopant (B, As, P) penetration through the dielectric into the channel region would likely result in deleterious effects upon the carrier mobility. In this dissertation extensive thermal stability studies of alternate gate dielectric candidates ZrSixOy and HfSixO y are presented. Dopant penetration studies from doped-polysilicon through HfSixOy and HfSixOyNz are also presented. Rutherford Backscattering Spectroscopy (RBS), Heavy Ion RBS (HI-RBS), X-ray Photoelectron Spectroscopy (XPS), High Resolution Transmission Electron Microscopy (HR-TEM), and Time of Flight and Dynamic Secondary Ion Mass Spectroscopy (ToF-SIMS, D-SIMS) methods were used to characterize these materials. The dopant diffusivity is calculated by modeling of the dopant profiles in the Si substrate. In this disseration is reported that Hf silicate films are more stable than Zr silicate films, from the metal interdiffusion point of view. On the other hand, dopant (B, As, and P) penetration is observed for HfSixO y films. However, the addition of nitrogen to the Hf - Si - O systems improves the dopant penetration properties of the resulting HfSi xOyNz films.

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO2 Gate Dielectrics by CF4 Plasma Treatment

PubMed Central

Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

2018-01-01

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO2 gate insulator and CF4 plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO2 gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm2/V∙s (without treatment) to 54.6 cm2/V∙s (with CF4 plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO2 gate dielectric has also been improved by the CF4 plasma treatment. By applying the CF4 plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device’s immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF4 plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO2 gate dielectric, but also enhances the device’s reliability. PMID:29772767

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gala, F.; Zollo, G.

2014-06-19

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

NASA Astrophysics Data System (ADS)

Gala, F.; Zollo, G.

2014-06-01

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Effect of incorporation of nitrogen atoms in Al2O3 gate dielectric of wide-bandgap-semiconductor MOSFET on gate leakage current and negative fixed charge

NASA Astrophysics Data System (ADS)

Kojima, Eiji; Chokawa, Kenta; Shirakawa, Hiroki; Araidai, Masaaki; Hosoi, Takuji; Watanabe, Heiji; Shiraishi, Kenji

2018-06-01

We performed first-principle calculations to investigate the effect of incorporation of N atoms into Al2O3 gate dielectrics. Our calculations show that the defect levels generated by VO in Al2O3 are the origin of the stress-induced gate leakage current and that VOVAl complexes in Al2O3 cause negative fixed charge. We revealed that the incorporation of N atoms into Al2O3 eliminates the VO defect levels, reducing the stress-induced gate leakage current. Moreover, this suppresses the formation of negatively charged VOVAl complexes. Therefore, AlON can reduce both stress-induced gate leakage current and negative fixed charge in wide-bandgap-semiconductor MOSFETs.

Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

NASA Astrophysics Data System (ADS)

Suarez, Ernesto; Chan, Pik-Yiu; Lingalugari, Murali; Ayers, John E.; Heller, Evan; Jain, Faquir

2013-11-01

This paper describes the use of II-VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeO x -cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn0.95Mg0.05S-ZnS tunneling layers. The II-VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrödinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.

Enhanced ZnO Thin-Film Transistor Performance Using Bilayer Gate Dielectrics.

PubMed

Alshammari, Fwzah H; Nayak, Pradipta K; Wang, Zhenwei; Alshareef, Husam N

2016-09-07

We report ZnO TFTs using Al2O3/Ta2O5 bilayer gate dielectrics grown by atomic layer deposition. The saturation mobility of single layer Ta2O5 dielectric TFT was 0.1 cm(2) V(-1) s(-1), but increased to 13.3 cm(2) V(-1) s(-1) using Al2O3/Ta2O5 bilayer dielectric with significantly lower leakage current and hysteresis. We show that point defects present in ZnO film, particularly VZn, are the main reason for the poor TFT performance with single layer dielectric, although interfacial roughness scattering effects cannot be ruled out. Our approach combines the high dielectric constant of Ta2O5 and the excellent Al2O3/ZnO interface quality, resulting in improved device performance.

Interface and gate bias dependence responses of sensing organic thin-film transistors.

PubMed

Tanese, Maria Cristina; Fine, Daniel; Dodabalapur, Ananth; Torsi, Luisa

2005-11-15

The effects of the exposure of organic thin-film transistors, comprising different organic semiconductors and gate dielectrics, to 1-pentanol are investigated. The transistor sensors exhibited an increase or a decrease of the transient source-drain current in the presence of the analyte, most likely as a result of a trapping or of a doping process of the organic active layer. The occurrence of these two effects, that can also coexist, depend on the gate-dielectric/organic semiconductor interface and on the applied gate field. Evidence of a systematic and sizable response enhancement for an OTFT sensor operated in the enhanced mode is also presented.

Comparative analysis of full-gate and short-gate dielectric modulated electrically doped Tunnel-FET based biosensors

NASA Astrophysics Data System (ADS)

Sharma, Dheeraj; Singh, Deepika; Pandey, Sunil; Yadav, Shivendra; Kondekar, P. N.

2017-11-01

In this work, we have done a comprehensive study between full-gate and short-gate dielectrically modulated (DM) electrically doped tunnel field-effect transistor (SGDM-EDTFET) based biosensors of equivalent dimensions. However, in both the structures, dielectric constant and charge density are considered as a sensing parameter for sensing the charged and non-charged biomolecules in the given solution. In SGDM-EDTFET architecture, the reduction in gate length results a significant improvement in the tunneling current due to occurrence of strong coupling between gate and channel region which ensures higher drain current sensitivity for detection of the biomolecules. Moreover, the sensitivity of dual metal SGDM-EDTFET is compared with the single metal SGDM-EDTFET to analyze the better sensing capability of both the devices for the biosensor application. Further, the effect of sensing parameter i.e., ON-current (ION), and ION/IOFF ratio is analysed for dual metal SGDM-EDTFET in comparison with dual metal SGDM-EDFET. From the comparison, it is found that dual metal SGDM-EDTFET based biosensor attains relatively better sensitivity and can be utilized as a suitable candidate for biosensing applications.

Manifold gasket accommodating differential movement of fuel cell stack

DOEpatents

Kelley, Dana A.; Farooque, Mohammad

2007-11-13

A gasket for use in a fuel cell system having at least one externally manifolded fuel cell stack, for sealing the manifold edge and the stack face. In accordance with the present invention, the gasket accommodates differential movement between the stack and manifold by promoting slippage at interfaces between the gasket and the dielectric and between the gasket and the stack face.

Fabrication of amorphous InGaZnO thin-film transistor with solution processed SrZrO3 gate insulator

NASA Astrophysics Data System (ADS)

Takahashi, Takanori; Oikawa, Kento; Hoga, Takeshi; Uraoka, Yukiharu; Uchiyama, Kiyoshi

2017-10-01

In this paper, we describe a method of fabrication of thin film transistors (TFTs) with high dielectric constant (high-k) gate insulator by a solution deposition. We chose a solution processed SrZrO3 as a gate insulator material, which possesses a high dielectric constant of 21 with smooth surface. The IGZO-TFT with solution processed SrZrO3 showed good switching property and enough saturation features, i.e. field effect mobility of 1.7cm2/Vs, threshold voltage of 4.8V, sub-threshold swing of 147mV/decade, and on/off ratio of 2.3×107. Comparing to the TFTs with conventional SiO2 gate insulator, the sub-threshold swing was improved by smooth surface and high field effect due to the high dielectric constant of SrZrO3. These results clearly showed that use of solution processed high-k SrZrO3 gate insulator could improve sub-threshold swing. In addition, the residual carbon originated from organic precursors makes TFT performances degraded.

Label Free Detection of Biomolecules Using Charge-Plasma-Based Gate Underlap Dielectric Modulated Junctionless TFET

NASA Astrophysics Data System (ADS)

Wadhwa, Girish; Raj, Balwinder

2018-05-01

Nanoscale devices are emerging as a platform for detecting biomolecules. Various issues were observed during the fabrication process such as random dopant fluctuation and thermal budget. To reduce these issues charge-plasma-based concept is introduced. This paper proposes the implementation of charge-plasma-based gate underlap dielectric modulated junctionless tunnel field effect transistor (DM-JLTFET) for the revelation of biomolecule immobilized in the open cavity gate channel region. In this p+ source and n+ drain regions are introduced by employing different work function over the intrinsic silicon. Also dual material gate architecture is implemented to reduce short channel effect without abandoning any other device characteristic. The sensitivity of biosensor is studied for both the neutral and charge-neutral biomolecules. The effect of device parameters such as channel thickness, cavity length and cavity thickness on drain current have been analyzed through simulations. This paper investigates the performance of charge-plasma-based gate underlap DM-JLTFET for biomolecule sensing applications while varying dielectric constant, charge density at different biasing conditions.

Oxygen vacancy defect engineering using atomic layer deposited HfAlO{sub x} in multi-layered gate stack

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bhuyian, M. N., E-mail: mnb3@njit.edu; Misra, D.; Sengupta, R.

2016-05-02

This work evaluates the defects in high quality atomic layer deposited (ALD) HfAlO{sub x} with extremely low Al (<3% Al/(Al + Hf)) incorporation in the Hf based high-k dielectrics. The defect activation energy estimated by the high temperature current voltage measurement shows that the charged oxygen vacancies, V{sup +}/V{sup 2+}, are the primary source of defects in these dielectrics. When Al is added in HfO{sub 2}, the V{sup +} type defects with a defect activation energy of E{sub a} ∼ 0.2 eV modify to V{sup 2+} type to E{sub a} ∼ 0.1 eV with reference to the Si conduction band. When devices were stressedmore » in the gate injection mode for 1000 s, more V{sup +} type defects are generated and E{sub a} reverts back to ∼0.2 eV. Since Al has a less number of valence electrons than do Hf, the change in the co-ordination number due to Al incorporation seems to contribute to the defect level modifications. Additionally, the stress induced leakage current behavior observed at 20 °C and at 125 °C demonstrates that the addition of Al in HfO{sub 2} contributed to suppressed trap generation process. This further supports the defect engineering model as reduced flat-band voltage shifts were observed at 20 °C and at 125 °C.« less

Effects of HfO2/Al2O3 gate stacks on electrical performance of planar In x Ga1- x As tunneling field-effect transistors

NASA Astrophysics Data System (ADS)

Ahn, Dae-Hwan; Yoon, Sang-Hee; Takenaka, Mitsuru; Takagi, Shinichi

2017-08-01

We study the impact of gate stacks on the electrical characteristics of Zn-diffused source In x Ga1- x As tunneling field-effect transistors (TFETs) with Al2O3 or HfO2/Al2O3 gate insulators. Ta and W gate electrodes are compared in terms of the interface trap density (D it) of InGaAs MOS interfaces. It is found that D it is lower at the W/HfO2/Al2O3 InGaAs MOS interface than at the Ta/HfO2/Al2O3 interface. The In0.53Ga0.47As TFET with a W/HfO2 (2.7 nm)/Al2O3 (0.3 nm) gate stack of 1.4-nm-thick capacitance equivalent thickness (CET) has a steep minimum subthreshold swing (SS) of 57 mV/dec, which is attributed to the thin CET and low D it. Also, the In0.53Ga0.47As (2.6 nm)/In0.67Ga0.33As (3.2 nm)/In0.53Ga0.47As (96.5 nm) quantum-well (QW) TFET supplemented with this 1.4-nm-thick CET gate stack exhibits a steeper minimum SS of 54 mV/dec and a higher on-current (I on) than those of the In0.53Ga0.47As TFET.

Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for AdvancedCMOS Devices

PubMed Central

Suzuki, Masamichi

2012-01-01

A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3) high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT) of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al) atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process. PMID:28817057

Modeling and estimation of process-induced stress in the nanowire field-effect-transistors (NW-FETs) on Insulator-on-Silicon substrates with high-k gate-dielectrics

NASA Astrophysics Data System (ADS)

Chatterjee, Sulagna; Chattopadhyay, Sanatan

2016-10-01

An analytical model including the simultaneous impact of lattice and thermo-elastic constant mismatch-induced stress in nanowires on Insulator-on-Silicon substrate is developed. It is used to calibrate the finite-element based software, ANSYS, which is subsequently employed to estimate process-induced stress in the sequential steps of NW-FET fabrication. The model considers crystal structures and orientations for both the nanowires and substrates. In-plane stress components along nanowire-axis are estimated for different radii and fractions of insertion. Nature of longitudinal stress is observed to change when inserted fraction of nanowires is changed. Effect of various high-k gate-dielectrics is also investigated. A longitudinal tensile stress of 2.4 GPa and compressive stress of 1.89 GPa have been obtained for NW-FETs with 1/4th and 3/4th insertions with La2O3 and TiO2 as the gate-dielectrics, respectively. Therefore, it is possible to achieve comparable values of electron and hole mobility in NW-FETs by judiciously choosing gate-dielectrics and fractional insertion of the nanowires.

Flexible, Low-Power Thin-Film Transistors Made of Vapor-Phase Synthesized High-k, Ultrathin Polymer Gate Dielectrics.

PubMed

Choi, Junhwan; Joo, Munkyu; Seong, Hyejeong; Pak, Kwanyong; Park, Hongkeun; Park, Chan Woo; Im, Sung Gap

2017-06-21

A series of high-k, ultrathin copolymer gate dielectrics were synthesized from 2-cyanoethyl acrylate (CEA) and di(ethylene glycol) divinyl ether (DEGDVE) monomers by a free radical polymerization via a one-step, vapor-phase, initiated chemical vapor deposition (iCVD) method. The chemical composition of the copolymers was systematically optimized by tuning the input ratio of the vaporized CEA and DEGDVE monomers to achieve a high dielectric constant (k) as well as excellent dielectric strength. Interestingly, DEGDVE was nonhomopolymerizable but it was able to form a copolymer with other kinds of monomers. Utilizing this interesting property of the DEGDVE cross-linker, the dielectric constant of the copolymer film could be maximized with minimum incorporation of the cross-linker moiety. To our knowledge, this is the first report on the synthesis of a cyanide-containing polymer in the vapor phase, where a high-purity polymer film with a maximized dielectric constant was achieved. The dielectric film with the optimized composition showed a dielectric constant greater than 6 and extremely low leakage current densities (<3 × 10 -8 A/cm 2 in the range of ±2 MV/cm), with a thickness of only 20 nm, which is an outstanding thickness for down-scalable cyanide polymer dielectrics. With this high-k dielectric layer, organic thin-film transistors (OTFTs) and oxide TFTs were fabricated, which showed hysteresis-free transfer characteristics with an operating voltage of less than 3 V. Furthermore, the flexible OTFTs retained their low gate leakage current and ideal TFT characteristics even under 2% applied tensile strain, which makes them some of the most flexible OTFTs reported to date. We believe that these ultrathin, high-k organic dielectric films with excellent mechanical flexibility will play a crucial role in future soft electronics.

Medium band gap polymer based solution-processed high-κ composite gate dielectrics for ambipolar OFET

NASA Astrophysics Data System (ADS)

Canımkurbey, Betül; Unay, Hande; Çakırlar, Çiğdem; Büyükköse, Serkan; Çırpan, Ali; Berber, Savas; Altürk Parlak, Elif

2018-03-01

The authors present a novel ambipolar organic filed-effect transistors (OFETs) composed of a hybrid dielectric thin film of Ta2O5:PMMA nanocomposite material, and solution processed poly(selenophene, benzotriazole and dialkoxy substituted [1,2-b:4, 5-b‧] dithiophene (P-SBTBDT)-based organic semiconducting material as the active layer of the device. We find that the Ta2O5:PMMA insulator shows n-type conduction character, and its combination with the p-type P-SBTBDT organic semiconductor leads to an ambipolar OFET device. Top-gated OFETs were fabricated on glass substrate consisting of interdigitated ITO electrodes. P-SBTBDT-based material was spin coated on the interdigitated ITO electrodes. Subsequently, a solution processed Ta2O5:PMMA nanocomposite material was spin coated, thereby creating the gate dielectric layer. Finally, as a gate metal, an aluminum layer was deposited by thermal evaporation. The fabricated OFETs exhibited an ambipolar performance with good air-stability, high field-induced current and relatively high electron and hole mobilities although Ta2O5:PMMA nanocomposite films have slightly higher leakage current compared to the pure Ta2O5 films. Dielectric properties of the devices with different ratios of Ta2O5:PMMA were also investigated. The dielectric constant varied between 3.6 and 5.3 at 100 Hz, depending on the Ta2O5:PMMA ratio.

High-κ/Metal Gate Science and Technology

NASA Astrophysics Data System (ADS)

Guha, Supratik; Narayanan, Vijay

2009-08-01

High-κ/metal gate technology is on the verge of replacing conventional oxynitride dielectrics in state-of-the-art transistors for both high-performance and low-power applications. In this review we discuss some of the key materials issues that complicated the introduction of high-κ dielectrics, including reduced electron mobility, oxygen-based thermal instabilities, and the absence of thermally stable dual-metal electrodes. We show that through a combination of materials innovations and engineering ingenuity these issues were successfully overcome, thereby paving the way for high-κ/metal gate implementation.

Fabrication and characterization of active nanostructures

NASA Astrophysics Data System (ADS)

Opondo, Noah F.

Three different nanostructure active devices have been designed, fabricated and characterized. Junctionless transistors based on highly-doped silicon nanowires fabricated using a bottom-up fabrication approach are first discussed. The fabrication avoids the ion implantation step since silicon nanowires are doped in-situ during growth. Germanium junctionless transistors fabricated with a top down approach starting from a germanium on insulator substrate and using a gate stack of high-k dielectrics and GeO2 are also presented. The levels and origin of low-frequency noise in junctionless transistor devices fabricated from silicon nanowires and also from GeOI devices are reported. Low-frequency noise is an indicator of the quality of the material, hence its characterization can reveal the quality and perhaps reliability of fabricated transistors. A novel method based on low-frequency noise measurement to envisage trap density in the semiconductor bandgap near the semiconductor/oxide interface of nanoscale silicon junctionless transistors (JLTs) is presented. Low-frequency noise characterization of JLTs biased in saturation is conducted at different gate biases. The noise spectrum indicates either a Lorentzian or 1/f. A simple analysis of the low-frequency noise data leads to the density of traps and their energy within the semiconductor bandgap. The level of noise in silicon JLT devices is lower than reported values on transistors fabricated using a top-down approach. This noise level can be significantly improved by improving the quality of dielectric and the channel interface. A micro-vacuum electron device based on silicon field emitters for cold cathode emission is also presented. The presented work utilizes vertical Si nanowires fabricated by means of self-assembly, standard lithography and etching techniques as field emitters in this dissertation. To obtain a high nanowire density, hence a high current density, a simple and inexpensive Langmuir Blodgett technique to deposit silica nanoparticles as a mask to etch Si is adopted. Fabrication and characterization of a metal-gated microtriode with a high current density and low operating voltage are presented.

Graphene/Pentacene Barristor with Ion-Gel Gate Dielectric: Flexible Ambipolar Transistor with High Mobility and On/Off Ratio.

PubMed

Oh, Gwangtaek; Kim, Jin-Soo; Jeon, Ji Hoon; Won, EunA; Son, Jong Wan; Lee, Duk Hyun; Kim, Cheol Kyeom; Jang, Jingon; Lee, Takhee; Park, Bae Ho

2015-07-28

High-quality channel layer is required for next-generation flexible electronic devices. Graphene is a good candidate due to its high carrier mobility and unique ambipolar transport characteristics but typically shows a low on/off ratio caused by gapless band structure. Popularly investigated organic semiconductors, such as pentacene, suffer from poor carrier mobility. Here, we propose a graphene/pentacene channel layer with high-k ion-gel gate dielectric. The graphene/pentacene device shows both high on/off ratio and carrier mobility as well as excellent mechanical flexibility. Most importantly, it reveals ambipolar behaviors and related negative differential resistance, which are controlled by external bias. Therefore, our graphene/pentacene barristor with ion-gel gate dielectric can offer various flexible device applications with high performances.

Study on the dielectric properties of Al2O3/TiO2 sub-nanometric laminates: effect of the bottom electrode and the total thickness

NASA Astrophysics Data System (ADS)

Ben Elbahri, M.; Kahouli, A.; Mercey, B.; Lebedev, O.; Donner, W.; Lüders, U.

2018-02-01

Dielectrics based on amorphous sub-nanometric laminates of TiO2 and Al2O3 are subject to elevated dielectric losses and leakage currents, in large parts due to the extremely thin individual layer thickness chosen for the creation of the Maxwell-Wagner relaxation and therefore the high apparent dielectric constants. The optimization of performances of the laminate itself being strongly limited by this contradiction concerning its internal structure, we will show in this study that modifications of the dielectric stack of capacitors based on these sub-nanometric laminates can positively influence the dielectric losses and the leakage, as for example the nature of the electrodes, the introduction of thick insulating layers at the laminate/electrode interfaces and the modification of the total laminate thickness. The optimization of the dielectric stack leads to the demonstration of a capacitor with an apparent dielectric constant of 90, combined with low dielectric loss (tan δ) of 7 · 10-2 and with leakage currents smaller than 1  ×  10-6 A cm-2 at 10 MV m-1.

Solution processed flexible organic thin film back-gated transistors based on polyimide dielectric films

NASA Astrophysics Data System (ADS)

Park, Janghoon; Min, Yoonki; Lee, Dongjin

2018-04-01

An organic thin film back-gated transistor (OBGT) was fabricated and characterized. The gate electrode was printed on the back side of substrate, and the dielectric layer was omitted by substituting the dielectric layer with the polyimide (PI) film substrate. Roll-to-roll (R2R) gravure printing, doctor blading, and drop casting methods were used to fabricate the OBGT. The printed OBGT device shows better performance compared with an OTFT device based on dielectric layer of BaTiO3. Additionally, a calendering process enhanced the performance by a factor of 3 to 7 (mobility: 0.016 cm2/V.s, on/off ratio: 9.17×103). A bending test was conducted to confirm the flexibility and durability of the OBGT device. The results show the fabricated device endures 20000-cyclic motions. The realized OBGT device was successfully fabricated and working, which is meaningful for production engineering from the viewpoint of process development.

High-performance pentacene OTFT by incorporating Ti in LaON gate dielectric

NASA Astrophysics Data System (ADS)

Ma, Y. X.; Han, C. Y.; Tang, W. M.; Lai, P. T.

2017-07-01

Pentacene organic thin-film transistors (OTFT) using high-k LaTiON gate dielectric with different Ti contents are investigated. The LaxTi(1-x)ON films (with x = 1, 0.87, 0.76, and 0.67) are deposited by reactive sputtering followed by an annealing in N2 at 200 °C. The OTFT with La0.87Ti0.13ON can achieve a high carrier mobility of 2.6 cm2/V.s, a small threshold voltage of -1.5 V, a small sub-threshold swing of 0.07 V/dec, and a small hysteresis of 0.17 V. AFM and X-ray photoelectron spectroscopy reveal that Ti can suppress the hygroscopicity of La oxide to achieve a smoother dielectric surface, which can result in larger pentacene grains and thus higher carrier mobility. All the devices show a clockwise hysteresis because both the LaOH formation and Ti incorporation can generate acceptor-like traps in the gate dielectric.

Fabrication of PVDF-TrFE based bilayered PbTiO3/PVDF-TrFE films capacitor

NASA Astrophysics Data System (ADS)

Nurbaya, Z.; Wahid, M. H.; Rozana, M. D.; Annuar, I.; Alrokayan, S. A. H.; Khan, H. A.; Rusop, M.

2016-07-01

Development of high performance capacitor is reaching towards new generation where the ferroelectric materials take places as the active dielectric layer. The motivation of this study is to produce high capacitance device with long life cycle. This was configured by preparing bilayered films where lead titanate as an active dielectric layer and stacked with the top dielectric layer, poly(vinyledenefluoride-trifluoroethylene). Both of them are being referred that have one in common which is ferroelectric behavior. Therefore the combination of ceramic and polymer ferroelectric material could perform optimum dielectric characteristic for capacitor applications. The fabrication was done by simple sol-gel spin coating method that being varied at spinning speed property for polymer layers, whereas maintaining the ceramic layer. The characterization of PVDF-TrFE/PbTiO3 was performed according to metal-insulator-metal stacked capacitor measurement which includes structural, dielectric, and ferroelectric measurement.

Fully inkjet-printed two-dimensional material field-effect heterojunctions for wearable and textile electronics.

PubMed

Carey, Tian; Cacovich, Stefania; Divitini, Giorgio; Ren, Jiesheng; Mansouri, Aida; Kim, Jong M; Wang, Chaoxia; Ducati, Caterina; Sordan, Roman; Torrisi, Felice

2017-10-31

Fully printed wearable electronics based on two-dimensional (2D) material heterojunction structures also known as heterostructures, such as field-effect transistors, require robust and reproducible printed multi-layer stacks consisting of active channel, dielectric and conductive contact layers. Solution processing of graphite and other layered materials provides low-cost inks enabling printed electronic devices, for example by inkjet printing. However, the limited quality of the 2D-material inks, the complexity of the layered arrangement, and the lack of a dielectric 2D-material ink able to operate at room temperature, under strain and after several washing cycles has impeded the fabrication of electronic devices on textile with fully printed 2D heterostructures. Here we demonstrate fully inkjet-printed 2D-material active heterostructures with graphene and hexagonal-boron nitride (h-BN) inks, and use them to fabricate all inkjet-printed flexible and washable field-effect transistors on textile, reaching a field-effect mobility of ~91 cm 2  V -1  s -1 , at low voltage (<5 V). This enables fully inkjet-printed electronic circuits, such as reprogrammable volatile memory cells, complementary inverters and OR logic gates.

Ferroelectric HfZrOx-based MoS2 negative capacitance transistor with ITO capping layers for steep-slope device application

NASA Astrophysics Data System (ADS)

Xu, Jing; Jiang, Shu-Ye; Zhang, Min; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

2018-03-01

A negative capacitance field-effect transistor (NCFET) built with hafnium-based oxide is one of the most promising candidates for low power-density devices due to the extremely steep subthreshold swing (SS) and high on-state current induced by incorporating the ferroelectric material in the gate stack. Here, we demonstrated a two-dimensional (2D) back-gate NCFET with the integration of ferroelectric HfZrOx in the gate stack and few-layer MoS2 as the channel. Instead of using the conventional TiN capping metal to form ferroelectricity in HfZrOx, the NCFET was fabricated on a thickness-optimized Al2O3/indium tin oxide (ITO)/HfZrOx/ITO/SiO2/Si stack, in which the two ITO layers sandwiching the HfZrOx film acted as the control back gate and ferroelectric gate, respectively. The thickness of each layer in the stack was engineered for distinguishable optical identification of the exfoliated 2D flakes on the surface. The NCFET exhibited small off-state current and steep switching behavior with minimum SS as low as 47 mV/dec. Such a steep-slope transistor is compatible with the standard CMOS fabrication process and is very attractive for 2D logic and sensor applications and future energy-efficient nanoelectronic devices with scaling power supply.

Investigating compositional effects of atomic layer deposition ternary dielectric Ti-Al-O on metal-insulator-semiconductor heterojunction capacitor structure for gate insulation of InAlN/GaN and AlGaN/GaN

DOE Office of Scientific and Technical Information (OSTI.GOV)

Colon, Albert; Stan, Liliana; Divan, Ralu

Gate insulation/surface passivation in AlGaN/GaN and InAlN/GaN heterojunction field-effect transistors is a major concern for passivation of surface traps and reduction of gate leakage current. However, finding the most appropriate gate dielectric materials is challenging and often involves a compromise of the required properties such as dielectric constant, conduction/valence band-offsets, or thermal stability. Creating a ternary compound such as Ti-Al-O and tailoring its composition may result in a reasonably good gate material in terms of the said properties. To date, there is limited knowledge of the performance of ternary dielectric compounds on AlGaN/GaN and even less on InAlN/GaN. To approachmore » this problem, the authors fabricated metal-insulator-semiconductor heterojunction (MISH) capacitors with ternary dielectrics Ti-Al-O of various compositions, deposited by atomic layer deposition (ALD). The film deposition was achieved by alternating cycles of TiO2 and Al2O3 using different ratios of ALD cycles. TiO2 was also deposited as a reference sample. The electrical characterization of the MISH capacitors shows an overall better performance of ternary compounds compared to the pure TiO2. The gate leakage current density decreases with increasing Al content, being similar to 2-3 orders of magnitude lower for a TiO2:Al2O3 cycle ratio of 2:1. Although the dielectric constant has the highest value of 79 for TiO2 and decreases with increasing the number of Al2O3 cycles, it is maintaining a relatively high value compared to an Al2O3 film. Capacitance voltage sweeps were also measured in order to characterize the interface trap density. A decreasing trend in the interface trap density was found while increasing Al content in the film. In conclusion, our study reveals that the desired high-kappa properties of TiO2 can be adequately maintained while improving other insulator performance factors. The ternary compounds may be an excellent choice as a gate material for both AlGaN/GaN and InAlN/GaN based devices.« less

High-performance enhancement-mode Al2O3/InAlGaN/GaN MOS high-electron mobility transistors with a self-aligned gate recessing technology

NASA Astrophysics Data System (ADS)

Zhang, Kai; Kong, Cen; Zhou, Jianjun; Kong, Yuechan; Chen, Tangsheng

2017-02-01

The paper reports high-performance enhancement-mode MOS high-electron mobility transistors (MOS-HEMTs) based on a quaternary InAlGaN barrier. Self-aligned gate technology is used for gate recessing, dielectric deposition, and gate electrode formation. An improved digital recessing process is developed, and an Al2O3 gate dielectric grown with O2 plasma is used. Compared to results with AlGaN barrier, the fabricated E-mode MOS-HEMT with InAlGaN barrier delivers a record output current density of 1.7 A/mm with a threshold voltage (V TH) of 1.5 V, and a small on-resistance (R on) of 2.0 Ω·mm. Excellent V TH hysteresis and greatly improved gate leakage characteristics are also demonstrated.

Chemical vapor deposited monolayer MoS2 top-gate MOSFET with atomic-layer-deposited ZrO2 as gate dielectric

NASA Astrophysics Data System (ADS)

Hu, Yaoqiao; Jiang, Huaxing; Lau, Kei May; Li, Qiang

2018-04-01

For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec-1, and a field-effect electron mobility of 12.1 cm2 V-1 s-1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm-1 at V DS = 5 V. The gate leakage current is below 10-2 A cm-2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm-1 is obtained. Gate hysteresis and frequency-dependent capacitance-voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ˜3 × 1012 cm-2 eV-1.

SEMICONDUCTOR TECHNOLOGY: TaN wet etch for application in dual-metal-gate integration technology

NASA Astrophysics Data System (ADS)

Yongliang, Li; Qiuxia, Xu

2009-12-01

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and Jg-Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.

Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance

NASA Astrophysics Data System (ADS)

Yadav, Dharmendra Singh; Verma, Abhishek; Sharma, Dheeraj; Tirkey, Sukeshni; Raad, Bhagwan Ram

2017-11-01

Tunnel-field-effect-transistor (TFET) has emerged as one of the most prominent devices to replace conventional MOSFET due to its ability to provide sub-threshold slope below 60 mV/decade (SS ≤ 60 mV/decade) and low leakage current. Despite this, TFETs suffer from ambipolar behavior, lower ON-state current, and poor RF performance. To address these issues, we have introduced drain and gate work function engineering with hetero gate dielectric for the first time in charge plasma based doping-less TFET (DL TFET). In this, the usage of dual work functionality over the drain region significantly reduces the ambipolar behavior of the device by varying the energy barrier at drain/channel interface. Whereas, the presence of dual work function at the gate terminal increases the ON-state current (ION). The combined effect of dual work function at the gate and drain electrode results in the increment of ON-state current (ION) and decrement of ambipolar conduction (Iambi) respectively. Furthermore, the incorporation of hetero gate dielectric along with dual work functionality at the drain and gate electrode provides an overall improvement in the performance of the device in terms of reduction in ambipolarity, threshold voltage and sub-threshold slope along with improved ON-state current and high frequency figures of merit.

Multibands tunneling in AAA-stacked trilayer graphene

NASA Astrophysics Data System (ADS)

Redouani, Ilham; Jellal, Ahmed; Bahaoui, Abdelhadi; Bahlouli, Hocine

2018-04-01

We study the electronic transport through np and npn junctions for AAA-stacked trilayer graphene. Two kinds of gates are considered where the first is a single gate and the second is a double gate. After obtaining the solutions for the energy spectrum, we use the transfer matrix method to determine the three transmission probabilities for each individual cone τ = 0 , ± 1 . We show that the quasiparticles in AAA-stacked trilayer graphene are not only chiral but also labeled by an additional cone index τ. The obtained bands are composed of three Dirac cones that depend on the chirality indexes. We show that there is perfect transmission for normal or near normal incidence, which is a manifestation of the Klein tunneling effect. We analyze also the corresponding total conductance, which is defined as the sum of the conductance channels in each individual cone. Our results are numerically discussed and compared with those obtained for ABA- and ABC-stacked trilayer graphene.

2-D modeling and analysis of short-channel behavior of a front high- K gate stack triple-material gate SB SON MOSFET

NASA Astrophysics Data System (ADS)

Banerjee, Pritha; Kumari, Tripty; Sarkar, Subir Kumar

2018-02-01

This paper presents the 2-D analytical modeling of a front high- K gate stack triple-material gate Schottky Barrier Silicon-On-Nothing MOSFET. Using the two-dimensional Poisson's equation and considering the popular parabolic potential approximation, expression for surface potential as well as the electric field has been considered. In addition, the response of the proposed device towards aggressive downscaling, that is, its extent of immunity towards the different short-channel effects, has also been considered in this work. The analytical results obtained have been validated using the simulated results obtained using ATLAS, a two-dimensional device simulator from SILVACO.

Low-voltage operation of Si-based ferroelectric field effect transistors using organic ferroelectrics, poly(vinylidene fluoride-trifluoroethylene), as a gate dielectric

NASA Astrophysics Data System (ADS)

Miyata, Yusuke; Yoshimura, Takeshi; Ashida, Atsushi; Fujimura, Norifumi

2016-04-01

Si-based metal-ferroelectric-semiconductor (MFS) capacitors have been fabricated using poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as a ferroelectric gate. The pinhole-free P(VDF-TrFE) thin films with high resistivity were able to be prepared by spin-coating directly onto hydrogen-terminated Si. The capacitance-voltage (C-V) characteristics of the ferroelectric gate field effect transistor (FeFET) using this MFS structure clearly show butterfly-shaped hysteresis originating from the ferroelectricity, indicating carrier modulation on the Si surface at gate voltages below 2 V. The drain current-gate voltage (I D-V G) characteristics also show counterclockwise hysteresis at gate voltages below 5 V. This is the first report on the low-voltage operation of a Si-based FeFET using P(VDF-TrFE) as a gate dielectric. This organic gate FeFET without any insulator layer at the ferroelectric/Si interface should be one of the promising devices for overcoming the critical issues of the FeFET, such as depolarization field and a decrease in the gate voltage.

An LOD with improved breakdown voltage in full-frame CCD devices

NASA Astrophysics Data System (ADS)

Banghart, Edmund K.; Stevens, Eric G.; Doan, Hung Q.; Shepherd, John P.; Meisenzahl, Eric J.

2005-02-01

In full-frame image sensors, lateral overflow drain (LOD) structures are typically formed along the vertical CCD shift registers to provide a means for preventing charge blooming in the imager pixels. In a conventional LOD structure, the n-type LOD implant is made through the thin gate dielectric stack in the device active area and adjacent to the thick field oxidation that isolates the vertical CCD columns of the imager. In this paper, a novel LOD structure is described in which the n-type LOD impurities are placed directly under the field oxidation and are, therefore, electrically isolated from the gate electrodes. By reducing the electrical fields that cause breakdown at the silicon surface, this new structure permits a larger amount of n-type impurities to be implanted for the purpose of increasing the LOD conductivity. As a consequence of the improved conductance, the LOD width can be significantly reduced, enabling the design of higher resolution imaging arrays without sacrificing charge capacity in the pixels. Numerical simulations with MEDICI of the LOD leakage current are presented that identify the breakdown mechanism, while three-dimensional solutions to Poisson's equation are used to determine the charge capacity as a function of pixel dimension.

In-line charge-trapping characterization of dielectrics for sub-0.5-um CMOS technologies

NASA Astrophysics Data System (ADS)

Roy, Pradip K.; Chacon, Carlos M.; Ma, Yi; Horner, Gregory

1997-09-01

The advent of ultra-large and giga-scale-integration (ULSI/GSI) has placed considerable emphasis on the development of new gate oxides and interlevel dielectrics capable of meeting strict performance and reliability requirements. The costs and demands associated with ULSI fabrication have in turn fueled the need for cost-effective, rapid and accurate in-line characterization techniques for evaluating dielectric quality. The use of non-contact surface photovoltage characterization techniques provides cost-effective rapid feedback on dielectric quality, reducing costs through the reutilization of control wafers and the elimination of processing time. This technology has been applied to characterize most of the relevant C-V parameters, including flatband voltage (Vfb), density of interface traps (Dit), mobile charge density (Qm), oxide thickness (Tox), oxide resistivity (pox) and total charge (Qtot) for gate and interlevel (ILO) oxides. A novel method of measuring tunneling voltage by this technique on various gate oxides is discussed. For ILO, PECVD and high density plasma dielectrics, surface voltage maps are also presented. Measurements of near-surface silicon quality are described, including minority carrier generation lifetime, and examples of their application in diagnosing manufacturing problems.

A SONOS device with a separated charge trapping layer for improvement of charge injection

NASA Astrophysics Data System (ADS)

Ahn, Jae-Hyuk; Moon, Dong-Il; Ko, Seung-Won; Kim, Chang-Hoon; Kim, Jee-Yeon; Kim, Moon-Seok; Seol, Myeong-Lok; Moon, Joon-Bae; Choi, Ji-Min; Oh, Jae-Sub; Choi, Sung-Jin; Choi, Yang-Kyu

2017-03-01

A charge trapping layer that is separated from the primary gate dielectric is implemented on a FinFET SONOS structure. By virtue of the reduced effective oxide thickness of the primary gate dielectric, a strong gate-to-channel coupling is obtained and thus short-channel effects in the proposed device are effectively suppressed. Moreover, a high program/erase speed and a large shift in the threshold voltage are achieved due to the improved charge injection by the reduced effective oxide thickness. The proposed structure has potential for use in high speed flash memory.

Low-temperature fabrication of sputtered high-k HfO2 gate dielectric for flexible a-IGZO thin film transistors

NASA Astrophysics Data System (ADS)

Yao, Rihui; Zheng, Zeke; Xiong, Mei; Zhang, Xiaochen; Li, Xiaoqing; Ning, Honglong; Fang, Zhiqiang; Xie, Weiguang; Lu, Xubing; Peng, Junbiao

2018-03-01

In this work, low temperature fabrication of a sputtered high-k HfO2 gate dielectric for flexible a-IGZO thin film transistors (TFTs) on polyimide substrates was investigated. The effects of Ar-pressure during the sputtering process and then especially the post-annealing treatments at low temperature (≤200 °C) for HfO2 on reducing the density of defects in the bulk and on the surface were systematically studied. X-ray reflectivity, UV-vis and X-ray photoelectron spectroscopy, and micro-wave photoconductivity decay measurements were carried out and indicated that the high quality of optimized HfO2 film and its high dielectric properties contributed to the low concentration of structural defects and shallow localized defects such as oxygen vacancies. As a result, the well-structured HfO2 gate dielectric exhibited a high density of 9.7 g/cm3, a high dielectric constant of 28.5, a wide optical bandgap of 4.75 eV, and relatively low leakage current. The corresponding flexible a-IGZO TFT on polyimide exhibited an optimal device performance with a saturation mobility of 10.3 cm2 V-1 s-1, an Ion/Ioff ratio of 4.3 × 107, a SS value of 0.28 V dec-1, and a threshold voltage (Vth) of 1.1 V, as well as favorable stability under NBS/PBS gate bias and bending stress.

Carbon nanotube network thin-film transistors on flexible/stretchable substrates

DOEpatents

Takei, Kuniharu; Takahashi, Toshitake; Javey, Ali

2016-03-29

This disclosure provides systems, methods, and apparatus for flexible thin-film transistors. In one aspect, a device includes a polymer substrate, a gate electrode disposed on the polymer substrate, a dielectric layer disposed on the gate electrode and on exposed portions of the polymer substrate, a carbon nanotube network disposed on the dielectric layer, and a source electrode and a drain electrode disposed on the carbon nanotube network.

Improved integration of ultra-thin high-k dielectrics in few-layer MoS2 FET by remote forming gas plasma pretreatment

NASA Astrophysics Data System (ADS)

Wang, Xiao; Zhang, Tian-Bao; Yang, Wen; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

2017-01-01

The effective and high-quality integration of high-k dielectrics on two-dimensional (2D) crystals is essential to the device structure engineering and performance improvement of field-effect transistor (FET) based on the 2D semiconductors. We report a 2D MoS2 transistor with ultra-thin Al2O3 top-gate dielectric (6.1 nm) and extremely low leakage current. Remote forming gas plasma pretreatment was carried out prior to the atomic layer deposition, providing nucleation sites with the physically adsorbed ions on the MoS2 surface. The top gate MoS2 FET exhibited excellent electrical performance, including high on/off current ratio over 109, subthreshold swing of 85 mV/decade and field-effect mobility of 45.03 cm2/V s. Top gate leakage current less than 0.08 pA/μm2 at 4 MV/cm has been obtained, which is the smallest compared with the reported top-gated MoS2 transistors. Such an optimized integration of high-k dielectric in 2D semiconductor FET with enhanced performance is very attractive, and it paves the way towards the realization of more advanced 2D nanoelectronic devices and integrated circuits.

Electrode influence on the number of oxygen vacancies at the gate/high-κ dielectric interface in nanoscale MIM capacitors

NASA Astrophysics Data System (ADS)

Stojanovska-Georgievska, Lihnida

2015-02-01

In this paper, a particular attention has been paid in determining the impact of the type of top electrode (the gate), on the overall characteristics of the examined metal-insulator-metal structures, that contain doped Ta2O5:Hf high-κ dielectric as an insulator. For that purpose MIM capacitors with different metal gates (conventional Al and also W, Au, Pt, Mo, TiN, Ta) were formed. The results obtained, consider both the influence of metal work function and oxygen affinity, as possible reasons for increasing of number of oxygen vacancies at the gate/dielectric interface. Here we use capacitance-voltage alteration (C-V measurements) under constant current stress (CCS) conditions as characterization technique. The measurements show grater creation of positive oxygen vacancies in the case of metal electrodes with high work function, like Au and Pt, for almost one order of magnitude. It is also indicative that these metals have also the lowest values of heat of oxygen formation, which also favors the creation of oxygen vacancies. All results are discussed taking into consideration the nanoscale thickness of the dielectric layer (of the order of 8 nm), implicating the stronger effect of interface properties on the overall behavior rather than the one originating from the bulk of material.

Ambipolar transport in CVD grown MoSe2 monolayer using an ionic liquid gel gate dielectric

NASA Astrophysics Data System (ADS)

Ortiz, Deliris N.; Ramos, Idalia; Pinto, Nicholas J.; Zhao, Meng-Qiang; Kumar, Vinayak; Johnson, A. T. Charlie

2018-03-01

CVD grown MoSe2 monolayers were electrically characterized at room temperature in a field effect transistor (FET) configuration using an ionic liquid (IL) as the gate dielectric. During the growth, instead of using MoO3 powder, ammonium heptamolybdate was used for better Mo control of the source and sodium cholate added for lager MoSe2 growth areas. In addition, a high specific capacitance (˜7 μF/cm2) IL was used as the gate dielectric to significantly reduce the operating voltage. The device exhibited ambipolar charge transport at low voltages with enhanced parameters during n- and p-FET operation. IL gating thins the Schottky barrier at the metal/semiconductor interface permitting efficient charge injection into the channel and reduces the effects of contact resistance on device performance. The large specific capacitance of the IL was also responsible for a much higher induced charge density compared to the standard SiO2 dielectric. The device was successfully tested as an inverter with a gain of ˜2. Using a common metal for contacts simplifies fabrication of this ambipolar device, and the possibility of radiative recombination of holes and electrons could further extend its use in low power optoelectronic applications.

Polycrystalline diamond RF MOSFET with MoO3 gate dielectric

NASA Astrophysics Data System (ADS)

Ren, Zeyang; Zhang, Jinfeng; Zhang, Jincheng; Zhang, Chunfu; Chen, Dazheng; Quan, Rudai; Yang, Jiayin; Lin, Zhiyu; Hao, Yue

2017-12-01

We report the radio frequency characteristics of the diamond metal-oxide-semiconductor field effect transistor with MoO3 gate dielectric for the first time. The device with 2-μm gate length was fabricated on high quality polycrystalline diamond. The maximum drain current of 150 mA/mm at VGS = -5 V and the maximum transconductance of 27 mS/mm were achieved. The extrinsic cutoff frequency of 1.2 GHz and the maximum oscillation frequency of 1.9 GHz have been measured. The moderate frequency characteristics are attributed to the moderate transconductance limited by the series resistance along the channel. We expect that the frequency characteristics of the device can be improved by increasing the magnitude of gm, or fundamentally decreasing the gate-controlled channel resistance and series resistance along the channel, and down-scaling the gate length.

Effects of HfO2 encapsulation on electrical performances of few-layered MoS2 transistor with ALD HfO2 as back-gate dielectric.

PubMed

Xu, Jingping; Wen, Ming; Zhao, Xinyuan; Liu, Lu; Song, Xingjuan; Lai, Pui-To; Tang, Wing-Man

2018-08-24

The carrier mobility of MoS 2 transistors can be greatly improved by the screening role of high-k gate dielectric. In this work, atomic-layer deposited (ALD) HfO 2 annealed in NH 3 is used to replace SiO 2 as the gate dielectric to fabricate back-gated few-layered MoS 2 transistors, and good electrical properties are achieved with field-effect mobility (μ) of 19.1 cm 2 V -1 s -1 , subthreshold swing (SS) of 123.6 mV dec -1 and on/off ratio of 3.76 × 10 5 . Furthermore, enhanced device performance is obtained when the surface of the MoS 2 channel is coated by an ALD HfO 2 layer with different thicknesses (10, 15 and 20 nm), where the transistor with a 15 nm HfO 2 encapsulation layer exhibits the best overall electrical properties: μ = 42.1 cm 2 V -1 s -1 , SS = 87.9 mV dec -1 and on/off ratio of 2.72 × 10 6 . These improvements should be associated with the enhanced screening effect on charged-impurity scattering and protection from absorption of environmental gas molecules by the high-k encapsulation. The capacitance equivalent thickness of the back-gate dielectric (HfO 2 ) is only 6.58 nm, which is conducive to scaling of the MoS 2 transistors.

Positive Bias Instability of Bottom-Gate Zinc Oxide Thin-Film Transistors with a SiOx/SiNx-Stacked Gate Insulator

NASA Astrophysics Data System (ADS)

Furuta, Mamoru; Kamada, Yudai; Hiramatsu, Takahiro; Li, Chaoyang; Kimura, Mutsumi; Fujita, Shizuo; Hirao, Takashi

2011-03-01

The positive bias instabilities of the zinc oxide thin-film transistors (ZnO TFTs) with a SiOx/SiNx-stacked gate insulator have been investigated. The film quality of a gate insulator of SiOx, which forms an interface with the ZnO channel, was varied by changing the gas mixture ratio of SiH4/N2O/N2 during plasma-enhanced chemical vapor deposition. The positive bias stress endurance of ZnO TFT strongly depended on the deposition condition of the SiOx gate insulator. From the relaxations of the transfer curve shift after imposition of positive bias stress, transfer curves could not be recovered completely without any thermal annealing. A charge trapping in a gate insulator rather than that in bulk ZnO and its interface with a gate insulator is a dominant instability mechanism of ZnO TFTs under positive bias stress.

A solid dielectric gated graphene nanosensor in electrolyte solutions.

PubMed

Zhu, Yibo; Wang, Cheng; Petrone, Nicholas; Yu, Jaeeun; Nuckolls, Colin; Hone, James; Lin, Qiao

2015-03-23

This letter presents a graphene field effect transistor (GFET) nanosensor that, with a solid gate provided by a high- κ dielectric, allows analyte detection in liquid media at low gate voltages. The gate is embedded within the sensor and thus is isolated from a sample solution, offering a high level of integration and miniaturization and eliminating errors caused by the liquid disturbance, desirable for both in vitro and in vivo applications. We demonstrate that the GFET nanosensor can be used to measure pH changes in a range of 5.3-9.3. Based on the experimental observations and quantitative analysis, the charging of an electrical double layer capacitor is found to be the major mechanism of pH sensing.

Electrical Characteristics of Organic Field Effect Transistor Formed by Gas Treatment of High-k Al2O3 at Low Temperature

NASA Astrophysics Data System (ADS)

Lee, Sunwoo; Yoon, Seungki; Park, In-Sung; Ahn, Jinho

2009-04-01

We studied the electrical characteristics of an organic field effect transistor (OFET) formed by the hydrogen (H2) and nitrogen (N2) mixed gas treatment of a gate dielectric layer. We also investigated how device mobility is related to the length and width variations of the channel. Aluminum oxide (Al2O3) was used as the gate dielectric layer. After the treatment, the mobility and subthreshold swing were observed to be significantly improved by the decreased hole carrier localization at the interfacial layer between the gate oxide and pentacene channel layers. H2 gas plays an important role in removing the defects of the gate oxide layer at temperatures below 100 °C.

High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

PubMed

Jaehnike, Felix; Pham, Duy Vu; Anselmann, Ralf; Bock, Claudia; Kunze, Ulrich

2015-07-01

A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications.

Comparing electrical characteristics of in situ and ex situ Al2O3/GaN interfaces formed by metalorganic chemical vapor deposition

NASA Astrophysics Data System (ADS)

Chan, Silvia H.; Bisi, Davide; Tahhan, Maher; Gupta, Chirag; DenBaars, Steven P.; Keller, Stacia; Zanoni, Enrico; Mishra, Umesh K.

2018-04-01

Al2O3/n-GaN MOS-capacitors grown by metalorganic chemical vapor deposition with in-situ- and ex-situ-formed Al2O3/GaN interfaces were characterized. Capacitors grown entirely in situ exhibited ˜4 × 1012 cm-2 fewer positive fixed charges and up to ˜1 × 1013 cm-2 eV-1 lower interface-state density near the band-edge than did capacitors with ex situ oxides. When in situ Al2O3/GaN interfaces were reformed via the insertion of a 10-nm-thick GaN layer, devices exhibited behavior between the in situ and ex situ limits. These results illustrate the extent to which an in-situ-formed dielectric/GaN gate stack improves the interface quality and breakdown performance.

The electrical performance and gate bias stability of an amorphous InGaZnO thin-film transistor with HfO2 high-k dielectrics

NASA Astrophysics Data System (ADS)

Wang, Ruo Zheng; Wu, Sheng Li; Li, Xin Yu; Zhang, Jin Tao

2017-07-01

In this study, we set out to fabricate an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with SiNx/HfO2/SiNx (SHS) sandwiched dielectrics. The J-V and C-V of this SHS film were extracted by the Au/p-Si/SHS/Ti structure. At room temperature the a-IGZO with SHS dielectrics showed the following electrical properties: a threshold voltage of 2.9 V, a subthreshold slope of 0.35 V/decade, an on/off current ratio of 3.5 × 107, and a mobility of 12.8 cm2 V-1 s-1. Finally, we tested the influence of gate bias stress on the TFT, and the result showed that the threshold voltage shifted to a positive voltage when applying a positive gate voltage to the TFT.

High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric

PubMed Central

Fujii, Mami N.; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

2015-01-01

The use of indium–gallium–zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic–inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic–inorganic hybrid devices. PMID:26677773

High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric.

PubMed

Fujii, Mami N; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

2015-12-18

The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices.

Vacancy-fluorine complexes and their impact on the properties of metal-oxide transistors with high-k gate dielectrics studied using monoenergetic positron beams

NASA Astrophysics Data System (ADS)

Uedono, A.; Inumiya, S.; Matsuki, T.; Aoyama, T.; Nara, Y.; Ishibashi, S.; Ohdaira, T.; Suzuki, R.; Miyazaki, S.; Yamada, K.

2007-09-01

Vacancy-fluorine complexes in metal-oxide semiconductors (MOS) with high-k gate dielectrics were studied using a positron annihilation technique. F+ ions were implanted into Si substrates before the deposition of gate dielectrics (HfSiON). The shift of threshold voltage (Vth) in MOS capacitors and an increase in Fermi level position below the HfSiON/Si interface were observed after F+ implantation. Doppler broadening spectra of the annihilation radiation and positron lifetimes were measured before and after HfSiON fabrication processes. From a comparison between Doppler broadening spectra and those obtained by first-principles calculation, the major defect species in Si substrates after annealing treatment (1050 °C, 5 s) was identified as vacancy-fluorine complexes (V3F2). The origin of the Vth shift in the MOS capacitors was attributed to V3F2 located in channel regions.

Influence of Gate Dielectrics, Electrodes and Channel Width on OFET Characteristics

NASA Astrophysics Data System (ADS)

Liyana, V. P.; Stephania, A. M.; Shiju, K.; Predeep, P.

2015-06-01

Organic Field Effect Transistors (OFET) possess wide applications in large area electronics owing to their attractive features like easy fabrication process, light weight, flexibility, cost effectiveness etc. But instability, high operational voltages and low carrier mobility act as inhibitors to commercialization of OFETs and various approaches were tried on a regular basis so as to make it viable. In this work, Poly 3-hexylthiophene-2,5diyl (P3HT) based OFETs with bottom-contact top-gate configuration using Poly vinyl alcohol (PVA) and Poly (methyl methacrylate) (PMMA) as gate dielectrics, aluminium and copper as source-drain electrodes are investigated. An effort is made to compare the effect of these dielectric materials and electrodes on the performance of OFET. Also, an attempt has been made to optimize the channel width of the device. These devices are characterised with mobility (μ), threshold voltage (VT), on-off ratio (Ion/Ioff) and their comparative analysis is reported.

Theory and practical considerations of multilayer dielectric thin-film stacks in Ag-coated hollow waveguides.

PubMed

Bledt, Carlos M; Melzer, Jeffrey E; Harrington, James A

2014-02-01

This analysis explores the theory and design of dielectric multilayer reflection-enhancing thin film stacks based on high and low refractive index alternating layers of cadmium sulfide (CdS) and lead sulfide (PbS) on silver (Ag)-coated hollow glass waveguides (HGWs) for low loss transmission at midinfrared wavelengths. The fundamentals for determining propagation losses in such multilayer thin-film-coated Ag hollow waveguides is thoroughly discussed, and forms the basis for further theoretical analysis presented in this study. The effects on propagation loss resulting from several key parameters of these multilayer thin film stacks is further explored in order to bridge the gap between results predicted through calculation under ideal conditions and deviations from such ideal models that often arise in practice. In particular, the effects on loss due to the number of dielectric thin film layers deposited, deviation from ideal individual layer thicknesses, and surface roughness related scattering losses are presented and thoroughly investigated. Through such extensive theoretical analysis the level of understanding of the underlying loss mechanisms of multilayer thin-film Ag-coated HGWs is greatly advanced, considerably increasing the potential practical development of next-generation ultralow-loss mid-IR Ag/multilayer dielectric-coated HGWs.

Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance

NASA Astrophysics Data System (ADS)

Tayal, Shubham; Nandi, Ashutosh

2018-06-01

This paper for the first time investigates the effect of temperature variation on analog/RF performance of SiO2 as well as high-K gate dielectric based junctionless silicon nanotube FET (JL-SiNTFET). It is observed that the change in temperature does not variate the analog/RF performance of junctionless silicon nanotube FET by substantial amount. By increasing the temperature from 77 K to 400 K, the deterioration in intrinsic dc gain (AV) is marginal that is only ∼3 dB. Furthermore, the variation in cut-off frequency (fT), maximum oscillation frequency (fMAX), and gain-frequency product (GFP) with temperature is also minimal in JLSiNT-FET. More so, the same trend is observed even at scaled gate length (Lg = 15 nm). Furthermore, we have observed that the use of high-K gate dielectric deteriorates the analog/RF performance of JLSiNT-FET. However, the use of high-K gate dielectric negligibly changes the effect of temperature variation on analog/RF performance of JLSINT-FET device.

Interfacial and electrical properties of InGaAs metal-oxide-semiconductor capacitor with TiON/TaON multilayer composite gate dielectric

NASA Astrophysics Data System (ADS)

Wang, L. S.; Xu, J. P.; Liu, L.; Lu, H. H.; Lai, P. T.; Tang, W. M.

2015-03-01

InGaAs metal-oxide-semiconductor (MOS) capacitors with composite gate dielectric consisting of Ti-based oxynitride (TiON)/Ta-based oxynitride (TaON) multilayer are fabricated by RF sputtering. The interfacial and electrical properties of the TiON/TaON/InGaAs and TaON/TiON/InGaAs MOS structures are investigated and compared. Experimental results show that the former exhibits lower interface-state density (1.0 × 1012 cm-2 eV-1 at midgap), smaller gate leakage current (9.5 × 10-5 A/cm2 at a gate voltage of 2 V), larger equivalent dielectric constant (19.8), and higher reliability under electrical stress than the latter. The involved mechanism lies in the fact that the ultrathin TaON interlayer deposited on the sulfur-passivated InGaAs surface can effectively reduce the defective states and thus unpin the Femi level at the TaON/InGaAs interface, improving the electrical properties of the device.

rf Quantum Capacitance of the Topological Insulator Bi2Se3 in the Bulk Depleted Regime for Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Inhofer, A.; Duffy, J.; Boukhicha, M.; Bocquillon, E.; Palomo, J.; Watanabe, K.; Taniguchi, T.; Estève, I.; Berroir, J. M.; Fève, G.; Plaçais, B.; Assaf, B. A.

2018-02-01

A metal-dielectric topological-insulator capacitor device based on hexagonal-boron-nitrate- (h -BN) encapsulated CVD-grown Bi2Se3 is realized and investigated in the radio-frequency regime. The rf quantum capacitance and device resistance are extracted for frequencies as high as 10 GHz and studied as a function of the applied gate voltage. The superior quality h -BN gate dielectric combined with the optimized transport characteristics of CVD-grown Bi2Se3 (n ˜1018 cm-3 in 8 nm) on h -BN allow us to attain a bulk depleted regime by dielectric gating. A quantum-capacitance minimum and a linear variation of the capacitance with the chemical potential are observed revealing a Dirac regime. The topological surface state in proximity to the gate is seen to reach charge neutrality, but the bottom surface state remains charged and capacitively coupled to the top via the insulating bulk. Our work paves the way toward implementation of topological materials in rf devices.

Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics

NASA Astrophysics Data System (ADS)

Sangwan, Vinod K.; Jariwala, Deep; Everaerts, Ken; McMorrow, Julian J.; He, Jianting; Grayson, Matthew; Lauhon, Lincoln J.; Marks, Tobin J.; Hersam, Mark C.

2014-02-01

Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2 V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure < 2 × 10-5 Torr), and overall improved performance compared to control devices on conventional SiO2 gate dielectrics. Statistical analysis of the field-effect mobility and residual carrier concentration demonstrate high spatial uniformity of the dielectric interfacial properties and graphene transistor characteristics over full 3 in. wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

Ester-free cross-linker molecules for ultraviolet-light-cured polysilsesquioxane gate dielectric layers of organic thin-film transistors

NASA Astrophysics Data System (ADS)

Okada, Shuichi; Nakahara, Yoshio; Uno, Kazuyuki; Tanaka, Ichiro

2018-04-01

Pentacene thin-film transistors (TFTs) were fabricated with ultraviolet-light (UV)-cured polysilsesquioxane (PSQ) gate dielectric layers using cross-linker molecules with or without ester groups. To polymerize PSQ without ester groups, thiol-ene reaction was adopted. The TFTs fabricated with PSQ layers comprising ester-free cross-linkers showed a higher carrier mobility than the TFTs with PSQ layers cross-linked with ester groups, which had large electric dipole moments that limited the carrier mobility. It was demonstrated that the thiol-ene reaction is more suitable than the conventional radical reaction for UV-cured PSQ with small dielectric constant.

Fabrication of PVDF-TrFE based bilayered PbTiO{sub 3}/PVDF-TrFE films capacitor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nurbaya, Z., E-mail: nurbayazainal@gmail.com; Razak School of Engineering and Advanced Technology, Universiti Teknologi Malaysia, 54100 Kuala Lumpur; Wahid, M. H.

2016-07-06

Development of high performance capacitor is reaching towards new generation where the ferroelectric materials take places as the active dielectric layer. The motivation of this study is to produce high capacitance device with long life cycle. This was configured by preparing bilayered films where lead titanate as an active dielectric layer and stacked with the top dielectric layer, poly(vinyledenefluoride-trifluoroethylene). Both of them are being referred that have one in common which is ferroelectric behavior. Therefore the combination of ceramic and polymer ferroelectric material could perform optimum dielectric characteristic for capacitor applications. The fabrication was done by simple sol-gel spin coatingmore » method that being varied at spinning speed property for polymer layers, whereas maintaining the ceramic layer. The characterization of PVDF-TrFE/PbTiO3 was performed according to metal-insulator-metal stacked capacitor measurement which includes structural, dielectric, and ferroelectric measurement.« less

Dependence of electrical and time stress in organic field effect transistor with low temperature forming gas treated Al2O3 gate dielectrics.

PubMed

Lee, Sunwoo; Chung, Keum Jee; Park, In-Sung; Ahn, Jinho

2009-12-01

We report the characteristics of the organic field effect transistor (OFET) after electrical and time stress. Aluminum oxide (Al2O3) was used as a gate dielectric layer. The surface of the gate oxide layer was treated with hydrogen (H2) and nitrogen (N2) mixed gas to minimize the dangling bond at the interface layer of gate oxide. According to the two stress parameters of electrical and time stress, threshold voltage shift was observed. In particular, the mobility and subthreshold swing of OFET were significantly decreased due to hole carrier localization and degradation of the channel layer between gate oxide and pentacene by electrical stress. Electrical stress is a more critical factor in the degradation of mobility than time stress caused by H2O and O2 in the air.

Thin Film Transistors On Plastic Substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

2004-01-20

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

Synthesis and electron storage characteristics of isolated silver nanodots on/embedded in Al 2O 3 gate dielectric

NASA Astrophysics Data System (ADS)

Wang, Q.; Song, Z. T.; Liu, W. L.; Lin, C. L.; Wang, T. H.

2004-05-01

Monolayer-isolated silver (Ag) nanodots with the average diameter down to 7 nm are synthesized on Al 2O 3/Si substrate by vacuum electron-beam evaporation followed by annealing at 400 °C in N 2 ambient. Metal-insulator-silicon (MIS) structures with Ag nanodots embedded in Al 2O 3 gate dielectric are fabricated. Clear electron storage effect with the flatband voltage shift of 1.3 eV is observed through capacitance-conductance and conductance-voltage measurements. Our results demonstrate the feasibility of applying Ag nanodots for nanocrystal floating-gate memory devices.

The electrical and interfacial properties of metal-high-k oxide-semiconductor field effect transistors with CeO2/HfO2 laminated gate dielectrics

NASA Astrophysics Data System (ADS)

Chang, Ingram Yin-ku; Chen, Chun-Heng; Chiu, Fu-Chien; Lee, Joseph Ya-min

2007-11-01

Metal-oxide-semiconductor field-effect transistors with CeO2/HfO2 laminated gate dielectrics were fabricated. The transistors have a subthreshold slope of 74.9mV/decade. The interfacial properties were measured using gated diodes. The surface state density Dit was 9.78×1011cm-2eV-1. The surface-recombination velocity (s0) and the minority carrier lifetime in the field-induced depletion region (τ0,FIJ) measured from the gated diode were about 6.11×103cm /s and 1.8×10-8s, respectively. The effective capture cross section of surface state (σs) extracted using the subthreshold-swing measurement and the gated diode was about 7.69×10-15cm2. The effective electron mobility of CeO2/HfO2 laminated gated transistors was determined to be 212cm2/Vs.

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

High efficient light absorption and nanostructure-dependent birefringence of a metal-dielectric symmetrical layered structure

NASA Astrophysics Data System (ADS)

Jen, Yi-Jun; Jhang, Yi-Ciang; Liu, Wei-Chih

2017-08-01

A multilayer that comprises ultra-thin metal and dielectric films has been investigated and applied as a layered metamaterial. By arranging metal and dielectric films alternatively and symmetrically, the equivalent admittance and refractive index can be tailored separately. The tailored admittance and refractive index enable us to design optical filters with more flexibility. The admittance matching is achieved via the admittance tracing in the normalized admittance diagram. In this work, an ultra-thin light absorber is designed as a multilayer composed of one or several cells. Each cell is a seven-layered film stack here. The design concept is to have the extinction as large as possible under the condition of admittance matching. For a seven-layered symmetrical film stack arranged as Ta2O5 (45 nm)/ a-Si (17 nm)/ Cr (30 nm)/ Al (30 nm)/ Cr (30 nm)/ a-Si (17 nm)/ Ta2O5 (45 nm), its mean equivalent admittance and extinction coefficient over the visible regime is 1.4+0.2i and 2.15, respectively. The unit cell on a transparent BK7 glass substrate absorbs 99% of normally incident light energy for the incident medium is glass. On the other hand, a transmission-induced metal-dielectric film stack is investigated by using the admittance matching method. The equivalent anisotropic property of the metal-dielectric multilayer varied with wavelength and nanostructure are investigated here.

Radiation Effects On Emerging Electronic Materials And Devices

DTIC Science & Technology

2010-01-17

RADIATION EFFECTS ON EMERGING ELECTRONIC MATERIALS AND DEVICES FINAL PERFORMANCE REPORT PREPARED FOR: Kitt Reinhardt AFOSR/NE 875 N...and the other with metal gates and a high-K gate dielectric. These devices were programmed using both back-gate pulse and gate induced drain leakage... metal gate process GIDL method Fig. 1. Sensing margin as a function of total ionizing dose for nMOS 1T-DRAM cells programmed by back-gate pulse and

Finite element analysis of multilayer DEAP stack-actuators

NASA Astrophysics Data System (ADS)

Kuhring, Stefan; Uhlenbusch, Dominik; Hoffstadt, Thorben; Maas, Jürgen

2015-04-01

Dielectric elastomers (DE) are thin polymer films belonging to the class of electroactive polymers (EAP). They are coated with compliant and conductive electrodes on each side, which make them performing a relative high amount of deformation with considerable force generation under the influence of an electric field. Because the realization of high electric fields with a limited voltage level requests single layer polymer films to be very thin, novel multilayer actuators are utilized to increase the absolute displacement and force. In case of a multilayer stack-actuator, many actuator films are mechanically stacked in series and electrically connected in parallel. Because there are different ways to design such a stack-actuator, this contribution considers an optimization of some design parameters using the finite element analysis (FEA), whereby the behavior and the actuation of a multilayer dielectric electroactive polymer (DEAP) stack-actuator can be improved. To describe the material behavior, first different material models are compared and necessary material parameters are identified by experiments. Furthermore, a FEA model of a DEAP film is presented, which is expanded to a multilayer DEAP stack-actuator model. Finally, the results of the FEA are discussed and conclusions for design rules of optimized stack-actuators are outlined.

Effect of dielectric layers on device stability of pentacene-based field-effect transistors.

PubMed

Di, Chong-an; Yu, Gui; Liu, Yunqi; Guo, Yunlong; Sun, Xiangnan; Zheng, Jian; Wen, Yugeng; Wang, Ying; Wu, Weiping; Zhu, Daoben

2009-09-07

We report stable organic field-effect transistors (OFETs) based on pentacene. It was found that device stability strongly depends on the dielectric layer. Pentacene thin-film transistors based on the bare or polystyrene-modified SiO(2) gate dielectrics exhibit excellent electrical stabilities. In contrast, the devices with the octadecyltrichlorosilane (OTS)-treated SiO(2) dielectric layer showed the worst stabilities. The effects of the different dielectrics on the device stabilities were investigated. We found that the surface energy of the gate dielectric plays a crucial role in determining the stability of the pentacene thin film, device performance and degradation of electrical properties. Pentacene aggregation, phase transfer and film morphology are also important factors that influence the device stability of pentacene devices. As a result of the surface energy mismatch between the dielectric layer and organic semiconductor, the electronic performance was degraded. Moreover, when pentacene was deposited on the OTS-treated SiO(2) dielectric layer with very low surface energy, pentacene aggregation occurred and resulted in a dramatic decrease of device performance. These results demonstrated that the stable OFETs could be obtained by using pentacene as a semiconductor layer.

A manufacturable process integration approach for graphene devices

NASA Astrophysics Data System (ADS)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Impact of metal gates on remote phonon scattering in titanium nitride/hafnium dioxide n-channel metal-oxide-semiconductor field effect transistors-low temperature electron mobility study

NASA Astrophysics Data System (ADS)

Maitra, Kingsuk; Frank, Martin M.; Narayanan, Vijay; Misra, Veena; Cartier, Eduard A.

2007-12-01

We report low temperature (40-300 K) electron mobility measurements on aggressively scaled [equivalent oxide thickness (EOT)=1 nm] n-channel metal-oxide-semiconductor field effect transistors (nMOSFETs) with HfO2 gate dielectrics and metal gate electrodes (TiN). A comparison is made with conventional nMOSFETs containing HfO2 with polycrystalline Si (poly-Si) gate electrodes. No substantial change in the temperature acceleration factor is observed when poly-Si is replaced with a metal gate, showing that soft optical phonons are not significantly screened by metal gates. A qualitative argument based on an analogy between remote phonon scattering and high-resolution electron energy-loss spectroscopy (HREELS) is provided to explain the underlying physics of the observed phenomenon. It is also shown that soft optical phonon scattering is strongly damped by thin SiO2 interface layers, such that room temperature electron mobility values at EOT=1 nm become competitive with values measured in nMOSFETs with SiON gate dielectrics used in current high performance processors.

Nanometer-scale oxide thin film transistor with potential for high-density image sensor applications.

PubMed

Jeon, Sanghun; Park, Sungho; Song, Ihun; Hur, Ji-Hyun; Park, Jaechul; Kim, Hojung; Kim, Sunil; Kim, Sangwook; Yin, Huaxiang; Chung, U-In; Lee, Eunha; Kim, Changjung

2011-01-01

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al₂O₃/SiO₂) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.

An “ohmic-first” self-terminating gate-recess technique for normally-off Al2O3/GaN MOSFET

NASA Astrophysics Data System (ADS)

Wang, Hongyue; Wang, Jinyan; Li, Mengjun; He, Yandong; Wang, Maojun; Yu, Min; Wu, Wengang; Zhou, Yang; Dai, Gang

2018-04-01

In this article, an ohmic-first AlGaN/GaN self-terminating gate-recess etching technique was demonstrated where ohmic contact formation is ahead of gate-recess-etching/gate-dielectric-deposition (GRE/GDD) process. The ohmic contact exhibits few degradations after the self-terminating gate-recess process. Besides, when comparing with that using the conventional fabrication process, the fabricated device using the ohmic-first fabrication process shows a better gate dielectric quality in terms of more than 3 orders lower forward gate leakage current, more than twice higher reverse breakdown voltage as well as better stability. Based on this proposed technique, the normally-off Al2O3/GaN MOSFET exhibits a threshold voltage (V th) of ˜1.8 V, a maximum drain current of ˜328 mA/mm, a forward gate leakage current of ˜10-6 A/mm and an off-state breakdown voltage of 218 V at room temperature. Meanwhile, high temperature characteristics of the device was also evaluated and small variations (˜7.6%) of the threshold voltage was confirmed up to 300 °C.

Novel conformal organic antireflective coatings for advanced I-line lithography

NASA Astrophysics Data System (ADS)

Deshpande, Shreeram V.; Nowak, Kelly A.; Fowler, Shelly; Williams, Paul; Arjona, Mikko

2001-08-01

Flash memory chips are playing a critical role in semiconductor devices due to increased popularity of hand held electronic communication devices such as cell phones and PDAs (personal Digital Assistants). Flash memory offers two primary advantages in semiconductor devices. First, it offers flexibility of in-circuit programming capability to reduce the loss from programming errors and to significantly reduce commercialization time to market for new devices. Second, flash memory has a double density memory capability through stacked gate structures which increases the memory capability and thus saves significantly on chip real estate. However, due to stacked gate structures the requirements for manufacturing of flash memory devices are significantly different from traditional memory devices. Stacked gate structures also offer unique challenges to lithographic patterning materials such as Bottom Anti-Reflective Coating (BARC) compositions used to achieve CD control and to minimize standing wave effect in photolithography. To be applicable in flash memory manufacturing a BARC should form a conformal coating on high topography of stacked gate features as well as provide the normal anti-reflection properties for CD control. In this paper we report on a new highly conformal advanced i-line BARC for use in design and manufacture of flash memory devices. Conformal BARCs being significantly thinner in trenches than the planarizing BARCs offer the advantage of reducing BARC overetch and thus minimizing resist thickness loss.

Solar cell contact formation using laser ablation

DOEpatents

Harley, Gabriel; Smith, David D.; Cousins, Peter John

2015-07-21

The formation of solar cell contacts using a laser is described. A method of fabricating a back-contact solar cell includes forming a poly-crystalline material layer above a single-crystalline substrate. The method also includes forming a dielectric material stack above the poly-crystalline material layer. The method also includes forming, by laser ablation, a plurality of contacts holes in the dielectric material stack, each of the contact holes exposing a portion of the poly-crystalline material layer; and forming conductive contacts in the plurality of contact holes.

Solar cell contact formation using laser ablation

DOEpatents

Harley, Gabriel; Smith, David; Cousins, Peter

2012-12-04

The formation of solar cell contacts using a laser is described. A method of fabricating a back-contact solar cell includes forming a poly-crystalline material layer above a single-crystalline substrate. The method also includes forming a dielectric material stack above the poly-crystalline material layer. The method also includes forming, by laser ablation, a plurality of contacts holes in the dielectric material stack, each of the contact holes exposing a portion of the poly-crystalline material layer; and forming conductive contacts in the plurality of contact holes.

Solar cell contact formation using laser ablation

DOEpatents

Harley, Gabriel; Smith, David D.; Cousins, Peter John

2014-07-22

The formation of solar cell contacts using a laser is described. A method of fabricating a back-contact solar cell includes forming a poly-crystalline material layer above a single-crystalline substrate. The method also includes forming a dielectric material stack above the poly-crystalline material layer. The method also includes forming, by laser ablation, a plurality of contacts holes in the dielectric material stack, each of the contact holes exposing a portion of the poly-crystalline materiat layer; and forming conductive contacts in the plurality of contact holes.

Structural Effects of Gating Poly(3-hexylthiophene) through an Ionic Liquid

DOE PAGES

Guardado, Jesus O.; Salleo, Alberto

2017-07-17

Ionic liquids are increasingly employed as dielectrics to generate high charge densities and enable low-voltage operation with organic semiconductors. But, effects on structure and morphology of the active material are not fully known, particularly for permeable semiconductors such as conjugated polymers, in which ions from the ionic liquid can enter and electrochemically dope the semicrystalline film. In order to understand when ions enter, where they go, and how they affect the film, thin films of the archetypal semiconducting polymer, poly(3-hexylthiophene), are electrochemically doped with 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide, the archetypal ionic liquid. High-resolution, ex situ X-ray diffraction measurements and complete pole figuresmore » reveal changes with applied voltage, cycling, and frequency in lattice spacing, crystallite orientation, and crystallinity in the bulk and at the buried interface. Dopant ions penetrate the film and enter the crystallites at sufficiently high voltages and low frequencies. Upon infiltrating crystallites, ions permanently expand lamellar stacking and contract pi-stacking. Cycling amplifies these effects, but higher frequencies mitigate the expansion of bulk crystallites as ions are hindered from entering crystallites. Furthermore, this mechanistic understanding of the structural effects of ion penetration will help develop models of the frequency and voltage impedance response of electrochemically doped conjugated polymers and advance electronic applications.« less

Structural Effects of Gating Poly(3-hexylthiophene) through an Ionic Liquid

DOE Office of Scientific and Technical Information (OSTI.GOV)

Guardado, Jesus O.; Salleo, Alberto

Ionic liquids are increasingly employed as dielectrics to generate high charge densities and enable low-voltage operation with organic semiconductors. But, effects on structure and morphology of the active material are not fully known, particularly for permeable semiconductors such as conjugated polymers, in which ions from the ionic liquid can enter and electrochemically dope the semicrystalline film. In order to understand when ions enter, where they go, and how they affect the film, thin films of the archetypal semiconducting polymer, poly(3-hexylthiophene), are electrochemically doped with 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide, the archetypal ionic liquid. High-resolution, ex situ X-ray diffraction measurements and complete pole figuresmore » reveal changes with applied voltage, cycling, and frequency in lattice spacing, crystallite orientation, and crystallinity in the bulk and at the buried interface. Dopant ions penetrate the film and enter the crystallites at sufficiently high voltages and low frequencies. Upon infiltrating crystallites, ions permanently expand lamellar stacking and contract pi-stacking. Cycling amplifies these effects, but higher frequencies mitigate the expansion of bulk crystallites as ions are hindered from entering crystallites. Furthermore, this mechanistic understanding of the structural effects of ion penetration will help develop models of the frequency and voltage impedance response of electrochemically doped conjugated polymers and advance electronic applications.« less

Stable indium oxide thin-film transistors with fast threshold voltage recovery

NASA Astrophysics Data System (ADS)

Vygranenko, Yuriy; Wang, Kai; Nathan, Arokia

2007-12-01

Stable thin-film transistors (TFTs) with semiconducting indium oxide channel and silicon dioxide gate dielectric were fabricated by reactive ion beam assisted evaporation and plasma-enhanced chemical vapor deposition. The field-effect mobility is 3.3cm2/Vs, along with an on/off current ratio of 106, and subthreshold slope of 0.5V/decade. When subject to long-term gate bias stress, the TFTs show fast recovery of the threshold voltage (VT) when relaxed without annealing, suggesting that charge trapping at the interface and/or in the bulk gate dielectric to be the dominant mechanism underlying VT instability. Device performance and stability make indium oxide TFTs promising for display applications.

A novel approach for the improvement of electrostatic behaviour of physically doped TFET using plasma formation and shortening of gate electrode with hetero-gate dielectric

NASA Astrophysics Data System (ADS)

Soni, Deepak; Sharma, Dheeraj; Aslam, Mohd.; Yadav, Shivendra

2018-04-01

This article presents a new device configuration to enhance current drivability and suppress negative conduction (ambipolar conduction) with improved RF characteristics of physically doped TFET. Here, we used a new approach to get excellent electrical characteristics of hetero-dielectric short gate source electrode TFET (HD-SG SE-TFET) by depositing a metal electrode of 5.93 eV work function over the heavily doped source (P+) region. Deposition of metal electrode induces the plasma (thin layer) of holes under the Si/HfO2 interface due to work function difference of metal and semiconductor. Plasma layer of holes is advantageous to increase abruptness as well as decrease the tunneling barrier at source/channel junction for attaining higher tunneling rate of charge carriers (i.e., electrons), which turns into 86.66 times higher ON-state current compared with the conventional physically doped TFET (C-TFET). Along with metal electrode deposition, gate electrode is under-lapped for inducing asymmetrical concentration of charge carriers in the channel region, which is helpful for widening the tunneling barrier width at the drain/channel interface. Consequently, HD-SG SE-TFET shows suppression of ambipolar behavior with reduction in gate-to-drain capacitance which is beneficial for improvement in RF performance. Furthermore, the effectiveness of hetero-gate dielectric concept has been used for improving the RF performance. Furthermore, reliability of C-TFET and proposed structures has been confirmed in term of linearity.

Electrical in-situ characterisation of interface stabilised organic thin-film transistors

PubMed Central

Striedinger, Bernd; Fian, Alexander; Petritz, Andreas; Lassnig, Roman; Winkler, Adolf; Stadlober, Barbara

2015-01-01

We report on the electrical in-situ characterisation of organic thin film transistors under high vacuum conditions. Model devices in a bottom-gate/bottom-contact (coplanar) configuration are electrically characterised in-situ, monolayer by monolayer (ML), while the organic semiconductor (OSC) is evaporated by organic molecular beam epitaxy (OMBE). Thermal SiO2 with an optional polymer interface stabilisation layer serves as the gate dielectric and pentacene is chosen as the organic semiconductor. The evolution of transistor parameters is studied on a bi-layer dielectric of a 150 nm of SiO2 and 20 nm of poly((±)endo,exo-bicyclo[2.2.1]hept-5-ene-2,3-dicarboxylic acid, diphenylester) (PNDPE) and compared to the behaviour on a pure SiO2 dielectric. The thin layer of PNDPE, which is an intrinsically photo-patternable organic dielectric, shows an excellent stabilisation performance, significantly reducing the calculated interface trap density at the OSC/dielectric interface up to two orders of magnitude, and thus remarkably improving the transistor performance. PMID:26457122

High-performance, low-operating voltage, and solution-processable organic field-effect transistor with silk fibroin as the gate dielectric

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shi, Leilei; Xu, Xinjun, E-mail: xuxj@mater.ustb.edu.cn, E-mail: lidong@mater.ustb.edu.cn; Ma, Mingchao

2014-01-13

We report the use of silk fibroin as the gate dielectric material in solution-processed organic field-effect transistors (OFETs) with poly(3-hexylthiophene) (P3HT) as the semiconducting layer. Such OFETs exhibit a low threshold of −0.77 V and a low-operating voltage (0 to −3 V) compatible with the voltage level commonly-used in current electronic industry. The carrier mobility of such OFETs is as high as 0.21 cm{sup 2} V{sup −1} s{sup −1} in the saturation regime, comparable to the best value of P3HT-based OFETs with dielectric layer that is not solution-processed. The high-performance of this kind of OFET is related with the high contentmore » of β strands in fibroin dielectric which leads to an array of fibers in a highly ordered structure, thus reducing the trapping sites at the semiconductor/dielectric interface.« less

Fabrication of dielectric elastomer stack transducers (DEST) by liquid deposition modeling

NASA Astrophysics Data System (ADS)

Klug, Florian; Solano-Arana, Susana; Mößinger, Holger; Förster-Zügel, Florentine; Schlaak, Helmut F.

2017-04-01

Established fabrication methods for dielectric elastomer stack transducers (DEST) are mostly based on twodimensional thin-film technology. Because of this, DEST are based on simple two-dimensionally structured shapes. For certain applications, like valves or Braille displays, these structures are suited well enough. However, a more flexible fabrication method allows for more complex actuator designs, which would otherwise require extra processing steps. Fabrication methods with the possibility of three-dimensional structuring allow e.g. the integration of electrical connections, cavities, channels, sensor and other structural elements during the fabrication. This opens up new applications, as well as the opportunity for faster prototype production of individually designed DEST for a given application. In this work, a manufacturing system allowing three dimensional structuring is described. It enables the production of multilayer and three-dimensional structured DEST by liquid deposition modelling. The system is based on a custom made dual extruder, connected to a commercial threeaxis positioning system. It allows a computer controlled liquid deposition of two materials. After tuning the manufacturing parameters the production of thin layers with at thickness of less than 50 μm, as well as stacking electrode and dielectric materials is feasible. With this setup a first DEST with dielectric layer thickness less than 50 μm is build successfully and its performance is evaluated.

Top-gated chemical vapor deposition grown graphene transistors with current saturation.

PubMed

Bai, Jingwei; Liao, Lei; Zhou, Hailong; Cheng, Rui; Liu, Lixin; Huang, Yu; Duan, Xiangfeng

2011-06-08

Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.

Fabrication of InGaZnO Nonvolatile Memory Devices at Low Temperature of 150 degrees C for Applications in Flexible Memory Displays and Transparency Coating on Plastic Substrates.

PubMed

Hanh, Nguyen Hong; Jang, Kyungsoo; Yi, Junsin

2016-05-01

We directly deposited amorphous InGaZnO (a-IGZO) nonvolatile memory (NVM) devices with oxynitride-oxide-dioxide (OOO) stack structures on plastic substrate by a DC pulsed magnetron sputtering and inductively coupled plasma chemical vapor deposition (ICPCVD) system, using a low-temperature of 150 degrees C. The fabricated bottom gate a-IGZO NVM devices have a wide memory window with a low operating voltage during programming and erasing, due to an effective control of the gate dielectrics. In addition, after ten years, the memory device retains a memory window of over 73%, with a programming duration of only 1 ms. Moreover, the a-IGZO films show high optical transmittance of over 85%, and good uniformity with a root mean square (RMS) roughness of 0.26 nm. This film is a promising candidate to achieve flexible displays and transparency on plastic substrates because of the possibility of low-temperature deposition, and the high transparent properties of a-IGZO films. These results demonstrate that the a-IGZO NVM devices obtained at low-temperature have a suitable programming and erasing efficiency for data storage under low-voltage conditions, in combination with excellent charge retention characteristics, and thus show great potential application in flexible memory displays.

Solution processed lanthanum aluminate gate dielectrics for use in metal oxide-based thin film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Esro, M.; Adamopoulos, G., E-mail: g.adamopoulos@lancaster.ac.uk; Mazzocco, R.

2015-05-18

We report on ZnO-based thin-film transistors (TFTs) employing lanthanum aluminate gate dielectrics (La{sub x}Al{sub 1−x}O{sub y}) grown by spray pyrolysis in ambient atmosphere at 440 °C. The structural, electronic, optical, morphological, and electrical properties of the La{sub x}Al{sub 1−x}O{sub y} films and devices as a function of the lanthanum to aluminium atomic ratio were investigated using a wide range of characterization techniques such as UV-visible absorption spectroscopy, impedance spectroscopy, spectroscopic ellipsometry, atomic force microscopy, x-ray diffraction, and field-effect measurements. As-deposited LaAlO{sub y} dielectrics exhibit a wide band gap (∼6.18 eV), high dielectric constant (k ∼ 16), low roughness (∼1.9 nm), and very low leakage currentsmore » (<3 nA/cm{sup 2}). TFTs employing solution processed LaAlO{sub y} gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with hysteresis-free operation, low operation voltages (∼10 V), high on/off current modulation ratio of >10{sup 6}, subthreshold swing of ∼650 mV dec{sup −1}, and electron mobility of ∼12 cm{sup 2} V{sup −1} s{sup −1}.« less

Electrical Characterization of Semiconductor and Dielectric Materials with a Non-Damaging FastGateTM Probe

NASA Astrophysics Data System (ADS)

Robert, Hillard; William, Howland; Bryan, Snyder

2002-03-01

Determination of the electrical properties of semiconductor materials and dielectrics is highly desirable since these correlate best to final device performance. The properties of SiO2 and high k dielectrics such as Equivalent Oxide Thickness(EOT), Interface Trap Density(Dit), Oxide Effective Charge(Neff), Flatband Voltage Hysteresis(Delta Vfb), Threshold Voltage(VT) and, bulk properties such as carrier density profile and channel dose are all important parameters that require monitoring during front end processing. Conventional methods for determining these parameters involve the manufacturing of polysilicon or metal gate MOS capacitors and subsequent measurements of capacitance-voltage(CV) and/or current-voltage(IV). These conventional techniques are time consuming and can introduce changes to the materials being monitored. Also, equivalent circuit effects resulting from excessive leakage current, series resistance and stray inductance can introduce large errors in the measured results. In this paper, a new method is discussed that provides rapid determination of these critical parameters and is robust against equivalent circuit errors. This technique uses a small diameter(30 micron), elastically deformed probe to form a gate for MOSCAP CV and IV and can be used to measure either monitor wafers or test areas within scribe lines on product wafers. It allows for measurements of dielectrics thinner than 10 Angstroms. A detailed description and applications such as high k dielectrics, will be presented.

Stable Low-Voltage Operation Top-Gate Organic Field-Effect Transistors on Cellulose Nanocrystal Substrates

Treesearch

Cheng-Yin Wang; Canek Fuentes-Hernandez; Jen-Chieh Liu; Amir Dindar; Sangmoo Choi; Jeffrey P. Youngblood; Robert J. Moon; Bernard Kippelen

2015-01-01

We report on the performance and the characterization of top-gate organic field-effect transistors (OFETs), comprising a bilayer gate dielectric of CYTOP/ Al2O3 and a solution-processed semiconductor layer made of a blend of TIPS-pentacene:PTAA, fabricated on recyclable cellulose nanocrystal−glycerol (CNC/glycerol...

Application of calendering for improving the electrical characteristics of a printed top-gate, bottom-contact organic thin film transistors

NASA Astrophysics Data System (ADS)

Lee, Sang Hoon; Lee, Dong Geun; Jung, Hoeryong; Lee, Sangyoon

2018-05-01

Interface between the channel and the gate dielectric of organic thin film transistors (OTFTs) needs to be smoothed in order to improve the electrical characteristics. In this study, an optimized calendering process was proposed to improve the surface roughness of the channel. Top-gate, bottom-contact structural p-type OTFT samples were fabricated using roll-to-roll gravure printing (source/drain, channel), spin coating (gate dielectric), and inkjet printing (gate electrode). The calendering process was optimized using the grey-based Taguchi method. The channel surface roughness and electrical characteristics of calendered and non-calendered samples were measured and compared. As a result, the average improvement in the surface roughness of the calendered samples was 26.61%. The average on–off ratio and field-effect mobility of the calendered samples were 3.574 × 104 and 0.1113 cm2 V‑1 s‑1, respectively, which correspond to the improvements of 16.72 and 10.20%, respectively.

Device optimization and scaling properties of a gate-on-germanium source tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Chattopadhyay, Avik; Mallik, Abhijit; Omura, Yasuhisa

2015-06-01

A gate-on-germanium source (GoGeS) tunnel field-effect transistor (TFET) shows great promise for low-power (sub-0.5 V) applications. A detailed investigation, with the help of a numerical device simulator, on the effects of variation in different structural parameters of a GoGeS TFET on its electrical performance is reported in this paper. Structural parameters such as κ-value of the gate dielectric, length and κ-value of the spacer, and doping concentrations of both the substrate and source are considered. A low-κ symmetric spacer and a high-κ gate dielectric are found to yield better device performance. The substrate doping influences only the p-i-n leakage floor. The source doping is found to significantly affect performance parameters such as OFF-state current, ON-state current and subthreshold swing, in addition to a threshold voltage shift. Results of the investigation on the gate length scaling of such devices are also reported in this paper.

Highly stable organic field-effect transistors with engineered gate dielectrics (Conference Presentation)

NASA Astrophysics Data System (ADS)

Kippelen, Bernard; Wang, Cheng-Yin; Fuentes-Hernandez, Canek; Yun, Minseong; Singh, Ankit K.; Dindar, Amir; Choi, Sangmoo; Graham, Samuel

2016-11-01

Organic field-effect transistors (OFETs) have the potential to lead to low-cost flexible displays, wearable electronics, and sensors. While recent efforts have focused greatly on improving the maximum charge mobility that can be achieved in such devices, studies about the stability and reliability of such high performance devices are relatively scarce. In this talk, we will discuss the results of recent studies aimed at improving the stability of OFETs under operation and their shelf lifetime. In particular, we will focus on device architectures where the gate dielectric is engineered to act simultaneously as an environmental barrier layer. In the past, our group had demonstrated solution-processed top-gate OFETs using TIPS-pentacene and PTAA blends as a semiconductor layer with a bilayer gate dielectric layer of CYTOP/Al2O3, where the oxide layer was fabricated by atomic layer deposition, ALD. Such devices displayed high operational stability with little degradation after 20,000 on/off scan cycles or continuous operation (24 h), and high environmental stability when kept in air for more than 2 years, with unchanged carrier mobility. Using this stable device geometry, simple circuits and sensors operating in aqueous conditions were demonstrated. However, the Al2O3 layer was found to degrade due to corrosion under prolonged exposure in aqueous solutions. In this talk, we will report on the use of a nanolaminate (NL) composed of Al2O3 and HfO2 by ALD to replace the Al2O3 single layer in the bilayer gate dielectric use in top-gate OFETs. Such OFETs were found to operate under harsh condition such as immersion in water at 95 °C. This work was funded by the Department of Energy (DOE) through the Bay Area Photovoltaics Consortium (BAPVC) under Award Number DE-EE0004946.

Band Offsets and Interfacial Properties of HfAlO Gate Dielectric Grown on InP by Atomic Layer Deposition.

PubMed

Yang, Lifeng; Wang, Tao; Zou, Ying; Lu, Hong-Liang

2017-12-01

X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy have been used to determine interfacial properties of HfO 2 and HfAlO gate dielectrics grown on InP by atomic layer deposition. An undesirable interfacial InP x O y layer is easily formed at the HfO 2 /InP interface, which can severely degrade the electrical performance. However, an abrupt interface can be achieved when the growth of the HfAlO dielectric on InP starts with an ultrathin Al 2 O 3 layer. The valence and conduction band offsets for HfAlO/InP heterojunctions have been determined to be 1.87 ± 0.1 and 2.83 ± 0.1 eV, respectively. These advantages make HfAlO a potential dielectric for InP MOSFETs.

Ferroelectric FET for nonvolatile memory application with two-dimensional MoSe2 channels

NASA Astrophysics Data System (ADS)

Wang, Xudong; Liu, Chunsen; Chen, Yan; Wu, Guangjian; Yan, Xiao; Huang, Hai; Wang, Peng; Tian, Bobo; Hong, Zhenchen; Wang, Yutao; Sun, Shuo; Shen, Hong; Lin, Tie; Hu, Weida; Tang, Minghua; Zhou, Peng; Wang, Jianlu; Sun, Jinglan; Meng, Xiangjian; Chu, Junhao; Li, Zheng

2017-06-01

Graphene and other two-dimensional materials have received considerable attention regarding their potential applications in nano-electronics. Here, we report top-gate nonvolatile memory field-effect transistors (FETs) with different layers of MoSe2 nanosheets channel gated by ferroelectric film. The conventional gate dielectric of FETs was replaced by a ferroelectric thin film that provides a ferroelectric polarization electric field, and therefore defined as an Fe-FET where the poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) was used as the gate dielectric. Among the devices with MoSe2 channels of different thicknesses, the device with a single layer of MoSe2 exhibited a large hysteresis of electronic transport with an over 105 write/erase ratio, and displayed excellent retention and endurance performance. The possible mechanism of the device’s good properties was qualitatively analyzed using band theory. Additionally, a comprehensive study comparing the memory properties of MoSe2 channels of different thicknesses is presented. Increasing the numbers of MoSe2 layers was found to cause a reduced memory window. However, MoSe2 thickness of 5 nm yielded a write/erase ratio of more than 103. The results indicate that, based on a Fe-FET structure, the combination of two-dimensional semiconductors and organic ferroelectric gate dielectrics shows good promise for future applications in nonvolatile ferroelectric memory.

Artificial dielectric stepped-refractive-index lens for the terahertz region.

PubMed

Hernandez-Serrano, A I; Mendis, Rajind; Reichel, Kimberly S; Zhang, Wei; Castro-Camus, E; Mittleman, Daniel M

2018-02-05

In this paper we theoretically and experimentally demonstrate a stepped-refractive-index convergent lens made of a parallel stack of metallic plates for terahertz frequencies based on artificial dielectrics. The lens consist of a non-uniformly spaced stack of metallic plates, forming a mirror-symmetric array of parallel-plate waveguides (PPWGs). The operation of the device is based on the TE 1 mode of the PPWG. The effective refractive index of the TE 1 mode is a function of the frequency of operation and the spacing between the plates of the PPWG. By varying the spacing between the plates, we can modify the local refractive index of the structure in every individual PPWG that constitutes the lens producing a stepped refractive index profile across the multi stack structure. The theoretical and experimental results show that this structure is capable of focusing a 1 cm diameter beam to a line focus of less than 4 mm for the design frequency of 0.18 THz. This structure shows that this artificial-dielectric concept is an important technology for the fabrication of next generation terahertz devices.

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors with atomic layer deposited Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Lin, H. C.; Yang, T.; Sharifi, H.; Kim, S. K.; Xuan, Y.; Shen, T.; Mohammadi, S.; Ye, P. D.

2007-11-01

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with ex situ atomic-layer-deposited Al2O3 as gate dielectrics are studied. Maximum drain currents of 211 and 263mA/mm are obtained for 1μm gate-length Al2O3 MOS-HEMTs with 3 and 6nm thick gate oxide, respectively. C-V characteristic shows negligible hysteresis and frequency dispersion. The gate leakage current density of the MOS-HEMTs is 3-5 orders of magnitude lower than the conventional HEMTs under similar bias conditions. The drain current on-off ratio of MOS-HEMTs is ˜3×103 with a subthreshold swing of 90mV/decade. A maximum cutoff frequency (fT) of 27.3GHz and maximum oscillation frequency (fmax) of 39.9GHz and an effective channel mobility of 4250cm2/Vs are measured for the 1μm gate-length Al2O3 MOS-HEMT with 6nm gate oxide. Hooge's constant measured by low frequency noise spectral density characterization is 3.7×10-5 for the same device.

Tunable Mobility in Double-Gated MoTe2 Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites.

PubMed

Ji, Hyunjin; Joo, Min-Kyu; Yi, Hojoon; Choi, Homin; Gul, Hamza Zad; Ghimire, Mohan Kumar; Lim, Seong Chu

2017-08-30

There is a general consensus that the carrier mobility in a field-effect transistor (FET) made of semiconducting transition-metal dichalcogenides (s-TMDs) is severely degraded by the trapping/detrapping and Coulomb scattering of carriers by ionic charges in the gate oxides. Using a double-gated (DG) MoTe 2 FET, we modulated and enhanced the carrier mobility by adjusting the top- and bottom-gate biases. The relevant mechanism for mobility tuning in this device was explored using static DC and low-frequency (LF) noise characterizations. In the investigations, LF-noise analysis revealed that for a strong back-gate bias the Coulomb scattering of carriers by ionized traps in the gate dielectrics is strongly screened by accumulation charges. This significantly reduces the electrostatic scattering of channel carriers by the interface trap sites, resulting in increased mobility. The reduction of the number of effective trap sites also depends on the gate bias, implying that owing to the gate bias, the carriers are shifted inside the channel. Thus, the number of active trap sites decreases as the carriers are repelled from the interface by the gate bias. The gate-controlled Coulomb-scattering parameter and the trap-site density provide new handles for improving the carrier mobility in TMDs, in a fundamentally different way from dielectric screening observed in previous studies.

Electrical Double Layer Capacitance in a Graphene-embedded Al2O3 Gate Dielectric

PubMed Central

Ki Min, Bok; Kim, Seong K.; Jun Kim, Seong; Ho Kim, Sung; Kang, Min-A; Park, Chong-Yun; Song, Wooseok; Myung, Sung; Lim, Jongsun; An, Ki-Seok

2015-01-01

Graphene heterostructures are of considerable interest as a new class of electronic devices with exceptional performance in a broad range of applications has been realized. Here, we propose a graphene-embedded Al2O3 gate dielectric with a relatively high dielectric constant of 15.5, which is about 2 times that of Al2O3, having a low leakage current with insertion of tri-layer graphene. In this system, the enhanced capacitance of the hybrid structure can be understood by the formation of a space charge layer at the graphene/Al2O3 interface. The electrical properties of the interface can be further explained by the electrical double layer (EDL) model dominated by the diffuse layer. PMID:26530817

Improved dc and power performance of AlGaN/GaN high electron mobility transistors with Sc 2O 3 gate dielectric or surface passivation

NASA Astrophysics Data System (ADS)

Luo, B.; Mehandru, R.; Kim, Jihyun; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Gotthold, D.; Birkhahn, R.; Peres, B.; Fitch, R. C.; Moser, N.; Gillespie, J. K.; Jessen, G. H.; Jenkins, T. J.; Yannuzi, M. J.; Via, G. D.; Crespo, A.

2003-10-01

The dc and power characteristics of AlGaN/GaN MOS-HEMTs with Sc 2O 3 gate dielectrics were compared with that of conventional metal-gate HEMTs fabricated on the same material. The MOS-HEMT shows higher saturated drain-source current (˜0.75 A/mm) and significantly better power-added efficiency (PAE, 27%) relative to the HEMT (˜0.6 A/mm and ˜5%). The Sc 2O 3 also provides effective surface passivation, with higher drain current, lower leakage currents and higher three-terminal breakdown voltage in passivated devices relative to unpassivated devices. The PAE also increases (from ˜5% to 12%) on the surface passivated HEMTs, showing that Sc 2O 3 is an attractive option for reducing gate and surface leakage in AlGaN/GaN heterostructure transistors.

Properties of multilayer filters

NASA Technical Reports Server (NTRS)

Baumeister, P. W.

1973-01-01

New methods were investigated of using optical interference coatings to produce bandpass filters for the spectral region 110 nm to 200 nm. The types of filter are: triple cavity metal dielectric filters; all dielectric reflection filters; and all dielectric Fabry Perot type filters. The latter two types use thorium fluoride and either cryolite films or magnesium fluoride films in the stacks. The optical properties of the thorium fluoride were also measured.

Effect of Al gate on the electrical behaviour of Al-doped Ta2O5 stacks

NASA Astrophysics Data System (ADS)

Skeparovski, A.; Novkovski, N.; Atanassova, E.; Paskaleva, A.; Lazarov, V. K.

2011-06-01

The electrical behaviour of Al-doped Ta2O5 films on nitrided silicon and implemented in Al-gated MIS capacitors has been studied. The dopant was introduced into the Ta2O5 through its surface by deposing a thin Al layer on the top of Ta2O5 followed by an annealing process. The HRTEM images reveal that the initial double-layer structure of the stacks composed of doped Ta2O5 and interfacial SiON layer undergoes changes during the formation of the Al gate and transforms into a three-layer structure with an additional layer between the Al electrode and the doped Ta2O5. This layer, being a result of reaction between the Al gate and the Al-doped Ta2O5, affects the overall electrical properties of the stacks. Strong charge trapping/detrapping processes have been established in the vicinity of the doped Ta2O5/SiON interface resulting in a large C-V hysteresis effect. The charge trapping also influences the current conduction in the layers keeping the current density level rather low even at high electric fields (J < 10-6 A cm-2 at 7 MV cm-1). By employing a three-layer model of the stack, the permittivity of both, the Al-doped Ta2O5 and the additional layer, has been estimated and the corresponding conduction mechanisms identified.

Structural and thermodynamic consideration of metal oxide doped GeO{sub 2} for gate stack formation on germanium

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Cimang, E-mail: cimang@adam.t.u-tokyo.ac.jp; Lee, Choong Hyun; Zhang, Wenfeng

2014-11-07

A systematic investigation was carried out on the material and electrical properties of metal oxide doped germanium dioxide (M-GeO{sub 2}) on Ge. We propose two criteria on the selection of desirable M-GeO{sub 2} for gate stack formation on Ge. First, metal oxides with larger cation radii show stronger ability in modifying GeO{sub 2} network, benefiting the thermal stability and water resistance in M-GeO{sub 2}/Ge stacks. Second, metal oxides with a positive Gibbs free energy for germanidation are required for good interface properties of M-GeO{sub 2}/Ge stacks in terms of preventing the Ge-M metallic bond formation. Aggressive equivalent oxide thickness scalingmore » to 0.5 nm is also demonstrated based on these understandings.« less

Logical qubit fusion

NASA Astrophysics Data System (ADS)

Moussa, Jonathan; Ryan-Anderson, Ciaran

The canonical modern plan for universal quantum computation is a Clifford+T gate set implemented in a topological error-correcting code. This plan has the basic disparity that logical Clifford gates are natural for codes in two spatial dimensions while logical T gates are natural in three. Recent progress has reduced this disparity by proposing logical T gates in two dimensions with doubled, stacked, or gauge color codes, but these proposals lack an error threshold. An alternative universal gate set is Clifford+F, where a fusion (F) gate converts two logical qubits into a logical qudit. We show that logical F gates can be constructed by identifying compatible pairs of qubit and qudit codes that stabilize the same logical subspace, much like the original Bravyi-Kitaev construction of magic state distillation. The simplest example of high-distance compatible codes results in a proposal that is very similar to the stacked color code with the key improvement of retaining an error threshold. Sandia National Labs is a multi-program laboratory managed and operated by Sandia Corp, a wholly owned subsidiary of Lockheed Martin Corp, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000.

Graphene-graphite oxide field-effect transistors.

PubMed

Standley, Brian; Mendez, Anthony; Schmidgall, Emma; Bockrath, Marc

2012-03-14

Graphene's high mobility and two-dimensional nature make it an attractive material for field-effect transistors. Previous efforts in this area have used bulk gate dielectric materials such as SiO(2) or HfO(2). In contrast, we have studied the use of an ultrathin layered material, graphene's insulating analogue, graphite oxide. We have fabricated transistors comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. The graphite oxide layers show relatively minimal leakage at room temperature. The breakdown electric field of graphite oxide was found to be comparable to SiO(2), typically ~1-3 × 10(8) V/m, while its dielectric constant is slightly higher, κ ≈ 4.3. © 2012 American Chemical Society

Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Shun; Gao, Xu, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn; Zhong, Ya-Nan

High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio andmore » good memory retention.« less

Realization of a complementary medium using dielectric photonic crystals.

PubMed

Xu, Tao; Fang, Anan; Jia, Ziyuan; Ji, Liyu; Hang, Zhi Hong

2017-12-01

By exploiting the scaling invariance of photonic band diagrams, a complementary photonic crystal slab structure is realized by stacking two uniformly scaled double-zero-index dielectric photonic crystal slabs together. The space cancellation effect in complementary photonic crystals is demonstrated in both numerical simulations and microwave experiments. The refractive index dispersion of double-zero-index dielectric photonic crystal is experimentally measured. Using pure dielectrics, our photonic crystal structure will be an ideal platform to explore various intriguing properties related to a complementary medium.

Fatigue responses of lead zirconate titanate stacks under semibipolar electric cycling with mechanical preload

NASA Astrophysics Data System (ADS)

Wang, Hong; Cooper, Thomas A.; Lin, Hua-Tay; Wereszczak, Andrew A.

2010-10-01

Lead zirconate titanate (PZT) stacks that had an interdigital internal electrode configuration were tested to more than 108 cycles. A 100 Hz semibipolar sine wave with a field range of +4.5/-0.9 kV/mm was used in cycling with a concurrently-applied 20 MPa preload. Significant reductions in piezoelectric and dielectric responses were observed during the cycling depending on the measuring condition. Extensive partial discharges were also observed. These surface events resulted in the erosion of external electrode and the exposure of internal electrodes. Sections prepared by sequential polishing technique revealed a variety of damage mechanisms including delaminations, pores, and etch grooves. The scale of damage was correlated with the degree of fatigue-induced reduction in piezoelectric and dielectric responses. The results from this study demonstrate the feasibility of using a semibipolar mode to drive a PZT stack under a mechanical preload and illustrate the potential fatigue and damages of the stack in service.

Artificial dispersion via high-order homogenization: magnetoelectric coupling and magnetism from dielectric layers

PubMed Central

Liu, Yan; Guenneau, Sébastien; Gralak, Boris

2013-01-01

We investigate a high-order homogenization (HOH) algorithm for periodic multi-layered stacks. The mathematical tool of choice is a transfer matrix method. Expressions for effective permeability, permittivity and magnetoelectric coupling are explored by frequency power expansions. On the physical side, this HOH uncovers a magnetoelectric coupling effect (odd-order approximation) and artificial magnetism (even-order approximation) in moderate contrast photonic crystals. Comparing the effective parameters' expressions of a stack with three layers against that of a stack with two layers, we note that the magnetoelectric coupling effect vanishes while the artificial magnetism can still be achieved in a centre-symmetric periodic structure. Furthermore, we numerically check the effective parameters through the dispersion law and transmission property of a stack with two dielectric layers against that of an effective bianisotropic medium: they are in good agreement throughout the low-frequency (acoustic) band until the first stop band, where the analyticity of the logarithm function of the transfer matrix () breaks down. PMID:24101891

Large-Scale Precise Printing of Ultrathin Sol-Gel Oxide Dielectrics for Directly Patterned Solution-Processed Metal Oxide Transistor Arrays.

PubMed

Lee, Won-June; Park, Won-Tae; Park, Sungjun; Sung, Sujin; Noh, Yong-Young; Yoon, Myung-Han

2015-09-09

Ultrathin and dense metal oxide gate di-electric layers are reported by a simple printing of AlOx and HfOx sol-gel precursors. Large-area printed indium gallium zinc oxide (IGZO) thin-film transistor arrays, which exhibit mobilities >5 cm(2) V(-1) s(-1) and gate leakage current of 10(-9) A cm(-2) at a very low operation voltage of 2 V, are demonstrated by continuous simple bar-coated processes. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Semi-transparent a-IGZO thin-film transistors with polymeric gate dielectric.

PubMed

Hyung, Gun Woo; Wang, Jian-Xun; Li, Zhao-Hui; Koo, Ja-Ryong; Kwon, Sang Jik; Cho, Eou-Sik; Kim, Young Kwan

2013-06-01

We report the fabrication of semi-transparent a-IGZO-based thin-film transistors (TFTs) with crosslinked poly-4-vinylphenol (PVP) gate dielectric layers on PET substrate and thermally-evaporated Al/Ag/Al source and drain (S&D) electrodes, which showed a transmittance of 64% at a 500-nm wavelength and sheet resistance of 16.8 omega/square. The semi-transparent a-IGZO TFTs with a PVP layer exhibited decent saturation mobilities (maximum approximately 5.8 cm2Ns) and on/off current ratios of approximately 10(6).

A complementary organic inverter of porphyrazine thin films: low-voltage operation using ionic liquid gate dielectrics.

PubMed

Fujimoto, Takuya; Miyoshi, Yasuhito; Matsushita, Michio M; Awaga, Kunio

2011-05-28

We studied a complementary organic inverter consisting of a p-type semiconductor, metal-free phthalocyanine (H(2)Pc), and an n-type semiconductor, tetrakis(thiadiazole)porphyrazine (H(2)TTDPz), operated through the ionic-liquid gate dielectrics of N,N-diethyl-N-methyl(2-methoxyethyl)ammonium bis(trifluoromethylsulfonyl)imide (DEME-TFSI). This organic inverter exhibits high performance with a very low operation voltage below 1.0 V and a dynamic response up to 20 Hz. © The Royal Society of Chemistry 2011

Correlation of interface states/border traps and threshold voltage shift on AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Tian-Li, E-mail: Tian-Li.Wu@imec.be; Groeseneken, Guido; Department of Electrical Engineering, KU Leuven, Leuven

2015-08-31

In this paper, three electrical techniques (frequency dependent conductance analysis, AC transconductance (AC-g{sub m}), and positive gate bias stress) were used to evaluate three different gate dielectrics (Plasma-Enhanced Atomic Layer Deposition Si{sub 3}N{sub 4}, Rapid Thermal Chemical Vapor Deposition Si{sub 3}N{sub 4}, and Atomic Layer Deposition (ALD) Al{sub 2}O{sub 3}) for AlGaN/GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistors. From these measurements, the interface state density (D{sub it}), the amount of border traps, and the threshold voltage (V{sub TH}) shift during a positive gate bias stress can be obtained. The results show that the V{sub TH} shift during a positive gate bias stress ismore » highly correlated to not only interface states but also border traps in the dielectric. A physical model is proposed describing that electrons can be trapped by both interface states and border traps. Therefore, in order to minimize the V{sub TH} shift during a positive gate bias stress, the gate dielectric needs to have a lower interface state density and less border traps. However, the results also show that the commonly used frequency dependent conductance analysis technique to extract D{sub it} needs to be cautiously used since the resulting value might be influenced by the border traps and, vice versa, i.e., the g{sub m} dispersion commonly attributed to border traps might be influenced by interface states.« less

Fringing field effects in negative capacitance field-effect transistors with a ferroelectric gate insulator

NASA Astrophysics Data System (ADS)

Hattori, Junichi; Fukuda, Koichi; Ikegami, Tsutomu; Ota, Hiroyuki; Migita, Shinji; Asai, Hidehiro; Toriumi, Akira

2018-04-01

We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal-oxide-semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.

Electric-field-control of magnetic anisotropy of Co0.6Fe0.2B0.2/oxide stacks using reduced voltage

NASA Astrophysics Data System (ADS)

Kita, Koji; Abraham, David W.; Gajek, Martin J.; Worledge, D. C.

2012-08-01

We have demonstrated purely electrical manipulation of the magnetic anisotropy of a Co0.6Fe0.2B0.2 film by applying only 8 V across the CoFeB/oxide stack. A clear transition from in-plane to perpendicular anisotropy was observed. The quantitative relationship between interface anisotropy energy and the applied electric-field was determined from the linear voltage dependence of the saturation field. By comparing the dielectric stacks of MgO/Al2O3 and MgO/HfO2/Al2O3, enhanced voltage control was also demonstrated, due to the higher dielectric constant of the HfO2. These results suggest the feasibility of purely electrical control of magnetization with small voltage bias for spintronics applications.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, S.; Dhar, A., E-mail: adhar@phy.iitkgp.ernet.in

Highlights: • Alternative to chemically crosslinking of PMMA to achieve low leakage in provided. • Effect of LiF in reducing gate leakage through the OFET device is studied. • Effect of gate leakage on transistor performance has been investigated. • Low voltage operable and low temperature processed n-channel OFETs were fabricated. - Abstract: We report low temperature processed, low voltage operable n-channel organic field effect transistors (OFETs) using N,N′-Dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C{sub 8}) organic semiconductor and poly(methylmethacrylate) (PMMA)/lithium fluoride (LiF) bilayer gate dielectric. We have studied the role of LiF buffer dielectric in effectively reducing the gate leakage through the device andmore » thus obtaining superior performance in contrast to the single layer PMMA dielectric devices. The bilayer OFET devices had a low threshold voltage (V{sub t}) of the order of 5.3 V. The typical values of saturation electron mobility (μ{sub s}), on/off ratio and inverse sub-threshold slope (S) for the range of devices made were estimated to be 2.8 × 10{sup −3} cm{sup 2}/V s, 385, and 3.8 V/decade respectively. Our work thus provides a potential substitution for much complicated process of chemically crosslinking PMMA to achieve low leakage, high capacitance, and thus low operating voltage OFETs.« less

Self-Healing Polymer Dielectric for a High Capacitance Gate Insulator.

PubMed

Ko, Jieun; Kim, Young-Jae; Kim, Youn Sang

2016-09-14

Self-healing materials are required for development of various flexible electronic devices to repair cracks and ruptures caused by repetitive bending or folding. Specifically, a self-healing dielectric layer has huge potential to achieve healing electronics without mechanical breakdown in flexible operations. Here, we developed a high performance self-healing dielectric layer with an ionic liquid and catechol-functionalized polymer which exhibited a self-healing ability for both bulk and film states under mild self-healing conditions at 55 °C for 30 min. Due to the sufficient ion mobility of the ionic liquid in the polymer matrix, it had a high capacitance value above 1 μF/cm(2) at 20 Hz. Moreover, zinc oxide (ZnO) thin-film transistors (TFTs) with a self-healing dielectric layer exhibited a high field-effect mobility of 16.1 ± 3.07 cm(2) V(-1) s(-1) at a gate bias of 3 V. Even after repetitive self-healing of the dielectric layer from mechanical breaking, the electrical performance of the TFTs was well-maintained.

A novel application of dielectric stack actuators: a pumping micromixer

NASA Astrophysics Data System (ADS)

Solano-Arana, Susana; Klug, Florian; Mößinger, Holger; Förster-Zügel, Florentine; Schlaak, Helmut F.

2018-07-01

The fabrication of pumping micromixers as a novel application of dielectric stack actuators is proposed in this work. DEA micromixers can be valuable for medical and pharmaceutical applications, due to: firstly, the biocompatibility of the used materials (PDMS and graphite); secondly, the pumping is done with peristaltic movements, allowing only the walls of the channel to be in contact with the liquid, avoiding possible contamination from external parts; and thirdly, the low flow velocity in the micromixers required in many applications. The micromixer based on peristasltic movements will not only mix, but also pump the fluids in and out the device. The developed device is a hybrid micromixer: active, because it needs a voltage source to enhance the quality and speed of the mixing; and passive, with a similar shape to the well-known Y-type micromixers. The proposed micromixer is based on twelve stack actuators distributed in: two pumping chambers, consisting of four stack actuators in series; and a mixing chamber, made of four consecutive stack actuators with 30 layers per stack. The DEA micromixer is able to mix two solutions with a flow rate of 21.5 μl min–1 at the outlet, applying 1500 V at 10 Hz and actuating two actuators at a time.

Comparison of work function variation between FinFET and 3D stacked nanowire FET devices for 6-T SRAM reliability

NASA Astrophysics Data System (ADS)

Ko, Kyul; Son, Dokyun; Kang, Myounggon; Shin, Hyungcheol

2018-02-01

In this work, work-function variation (WFV) on 5 nm node gate-all-around (GAA) silicon 3D stacked nanowire FET (NWFET) and FinFET devices are studied for 6-T SRAM cells through 3D technology computer-aided design (TCAD) simulation. The NWFET devices have strong immunity for the unprecedented short channel effects (SCEs) compared with the FinFET devices owing to increased gate controllability. However, due to the narrow gate area, the single NWFET is more vulnerable to WFV effects than FinFET devices. Our results show that the WFV effects on single NWFETs are larger than the FinFETs by 45-55%. In the case of standard SRAM bit cells (high density: 111 bit cell), the variation of read stability (read static noise margin) on single NWFETs are larger than the FinFETs by 65-75%. Therefore, to improve the performance and having immunity to WFV effects, it is important to analyze the degree of variability in 3D stacked device architectures without area penalty. Moreover, we investigated the WFV effects for an accurate guideline with regard to grain size (GS) and channel area of 3D stacked NWFET in 6-T SRAM bit cells.

Room-Temperature-Processed Flexible Amorphous InGaZnO Thin Film Transistor.

PubMed

Xiao, Xiang; Zhang, Letao; Shao, Yang; Zhou, Xiaoliang; He, Hongyu; Zhang, Shengdong

2017-12-13

A room-temperature flexible amorphous indium-gallium-zinc oxide thin film transistor (a-IGZO TFT) technology is developed on plastic substrates, in which both the gate dielectric and passivation layers of the TFTs are formed by an anodic oxidation (anodization) technique. While the gate dielectric Al 2 O 3 is grown with a conventional anodization on an Al:Nd gate electrode, the channel passivation layer Al 2 O 3 is formed using a localized anodization technique. The anodized Al 2 O 3 passivation layer shows a superior passivation effect to that of PECVD SiO 2 . The room-temperature-processed flexible a-IGZO TFT exhibits a field-effect mobility of 7.5 cm 2 /V·s, a subthreshold swing of 0.44 V/dec, an on-off ratio of 3.1 × 10 8 , and an acceptable gate-bias stability with threshold voltage shifts of 2.65 and -1.09 V under positive gate-bias stress and negative gate-bias stress, respectively. Bending and fatigue tests confirm that the flexible a-IGZO TFT also has a good mechanical reliability, with electrical performances remaining consistent up to a strain of 0.76% as well as after 1200 cycles of fatigue testing.

Pronounced Photovoltaic Response from Multilayered Transition-Metal Dichalcogenides PN-Junctions.

PubMed

Memaran, Shahriar; Pradhan, Nihar R; Lu, Zhengguang; Rhodes, Daniel; Ludwig, Jonathan; Zhou, Qiong; Ogunsolu, Omotola; Ajayan, Pulickel M; Smirnov, Dmitry; Fernández-Domínguez, Antonio I; García-Vidal, Francisco J; Balicas, Luis

2015-11-11

Transition metal dichalcogenides (TMDs) are layered semiconductors with indirect band gaps comparable to Si. These compounds can be grown in large area, while their gap(s) can be tuned by changing their chemical composition or by applying a gate voltage. The experimental evidence collected so far points toward a strong interaction with light, which contrasts with the small photovoltaic efficiencies η ≤ 1% extracted from bulk crystals or exfoliated monolayers. Here, we evaluate the potential of these compounds by studying the photovoltaic response of electrostatically generated PN-junctions composed of approximately 10 atomic layers of MoSe2 stacked onto the dielectric h-BN. In addition to ideal diode-like response, we find that these junctions can yield, under AM-1.5 illumination, photovoltaic efficiencies η exceeding 14%, with fill factors of ~70%. Given the available strategies for increasing η such as gap tuning, improving the quality of the electrical contacts, or the fabrication of tandem cells, our study suggests a remarkable potential for photovoltaic applications based on TMDs.

Deposition temperature dependent optical and electrical properties of ALD HfO{sub 2} gate dielectrics pretreated with tetrakisethylmethylamino hafnium

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, J.; School of Sciences, Anhui University of Science and Technology, Huainan 232001; He, G., E-mail: hegang@ahu.edu.cn

2015-10-15

Highlights: • ALD-derived HfO{sub 2} gate dielectrics have been deposited on Si substrates. • The leakage current mechanism for different deposition temperature was discussed. • Different emission at different field region has been determined precisely. - Abstract: The effect of deposition temperature on the growth rate, band gap energy and electrical properties of HfO{sub 2} thin film deposited by atomic layer deposition (ALD) has been investigated. By means of characterization of spectroscopy ellipsometry and ultraviolet–visible spectroscopy, the growth rate and optical constant of ALD-derived HfO{sub 2} gate dielectrics are determined precisely. The deposition temperature dependent electrical properties of HfO{sub 2}more » films were determined by capacitance–voltage (C–V) and leakage current density–voltage (J–V) measurements. The leakage current mechanism for different deposition temperature has been discussed systematically. As a result, the optimized deposition temperature has been obtained to achieve HfO{sub 2} thin film with high quality.« less

Improved interface properties of Ge metal-oxide-semiconductor capacitor with TaTiO gate dielectric by using in situ TaON passivation interlayer

NASA Astrophysics Data System (ADS)

Ji, F.; Xu, J. P.; Liu, J. G.; Li, C. X.; Lai, P. T.

2011-05-01

TaON is in situ formed as a passivating interlayer in Ge metal-oxide-semiconductor (MOS) capacitors with high-k TaTiO gate dielectric fabricated simply by alternate sputtering of Ta and Ti. Also, postdeposition annealing is performed in wet N2 to suppress the growth of unstable GeOx at the Ge surface. As a result, excellent electrical properties of the Ge MOS devices are demonstrated, such as high equivalent dielectric constant (22.1), low interface-state density (7.3×1011 cm-2 eV), small gate leakage current (8.6×10-4 A cm-2 at Vg-Vfb=1 V), and high device reliability. Transmission electron microscopy and x-ray photoelectron spectroscopy support that all these should be attributed to the fact that the nitrogen barrier in the TaON interlayer can effectively block the interdiffusions of Ge and Ta, and the wet-N2 anneal can significantly suppress the growth of unstable low-k GeOx.

Visible-light-induced instability in amorphous metal-oxide based TFTs for transparent electronics

NASA Astrophysics Data System (ADS)

Ha, Tae-Jun

2014-10-01

We investigate the origin of visible-light-induced instability in amorphous metal-oxide based thin film transistors (oxide-TFTs) for transparent electronics by exploring the shift in threshold voltage (Vth). A large hysteresis window in amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs possessing large optical band-gap (≈3 eV) was observed in a visible-light illuminated condition whereas no hysteresis window was shown in a dark measuring condition. We also report the instability caused by photo irradiation and prolonged gate bias stress in oxide-TFTs. Larger Vth shift was observed after photo-induced stress combined with a negative gate bias than the sum of that after only illumination stress and only negative gate bias stress. Such results can be explained by trapped charges at the interface of semiconductor/dielectric and/or in the gate dielectric which play a role in a screen effect on the electric field applied by gate voltage, for which we propose that the localized-states-assisted transitions by visible-light absorption can be responsible.

Vibrotactile display for mobile applications based on dielectric elastomer stack actuators

NASA Astrophysics Data System (ADS)

Matysek, Marc; Lotz, Peter; Flittner, Klaus; Schlaak, Helmut F.

2010-04-01

Dielectric elastomer stack actuators (DESA) offer the possibility to build actuator arrays at very high density. The driving voltage can be defined by the film thickness, ranging from 80 μm down to 5 μm and driving field strength of 30 V/μm. In this paper we present the development of a vibrotactile display based on multilayer technology. The display is used to present several operating conditions of a machine in form of haptic information to a human finger. As an example the design of a mp3-player interface is introduced. To build up an intuitive and user friendly interface several aspects of human haptic perception have to be considered. Using the results of preliminary user tests the interface is designed and an appropriate actuator layout is derived. Controlling these actuators is important because there are many possibilities to present different information, e.g. by varying the driving parameters. A built demonstrator is used to verify the concept: a high recognition rate of more than 90% validates the concept. A characterization of mechanical and electrical parameters proofs the suitability of dielectric elastomer stack actuators for the use in mobile applications.

Floquet high Chern insulators in periodically driven chirally stacked multilayer graphene

NASA Astrophysics Data System (ADS)

Li, Si; Liu, Cheng-Cheng; Yao, Yugui

2018-03-01

Chirally stacked N-layer graphene is a semimetal with ±p N band-touching at two nonequivalent corners in its Brillioun zone. We predict that an off-resonant circularly polarized light (CPL) drives chirally stacked N-layer graphene into a Floquet Chern insulators (FCIs), aka quantum anomalous Hall insulators, with tunable high Chern number C F = ±N and large gaps. A topological phase transition between such a FCI and a valley Hall (VH) insulator with high valley Chern number C v = ±N induced by a voltage gate can be engineered by the parameters of the CPL and voltage gate. We propose a topological domain wall between the FCI and VH phases, along which perfectly valley-polarized N-channel edge states propagate unidirectionally without backscattering.

Numerical analysis of the reverse blocking enhancement in High-K passivation AlGaN/GaN Schottky barrier diodes with gated edge termination

NASA Astrophysics Data System (ADS)

Bai, Zhiyuan; Du, Jiangfeng; Xin, Qi; Li, Ruonan; Yu, Qi

2018-02-01

We conducted a numerical analysis on high-K dielectric passivated AlGaN/GaN Schottky barrier diodes (HPG-SBDs) with a gated edge termination (GET). The reverse blocking characteristics were significantly enhanced without the stimulation of any parasitic effect by varying the dielectric thickness dge under the GET, thickness TP, and dielectric constant εr of the high-K passivation layer. The leakage current was reduced by increasing εr and decreasing dge. The breakdown voltage of the device was enhanced by increasing εr and TP. The highest breakdown voltage of 970 V and the lowest leakage current of 0.5 nA/mm were achieved under the conditions of εr = 80, TP = 800 nm, and dge = 10 nm. C-V simulation revealed that the HPG-SBDs induced no parasitic capacitance by comparing the integrated charges of the devices with different high-K dielectrics and different dge.

Impact of oxygen precursor flow on the forward bias behavior of MOCVD-Al2O3 dielectrics grown on GaN

NASA Astrophysics Data System (ADS)

Chan, Silvia H.; Bisi, Davide; Liu, Xiang; Yeluri, Ramya; Tahhan, Maher; Keller, Stacia; DenBaars, Steven P.; Meneghini, Matteo; Mishra, Umesh K.

2017-11-01

This paper investigates the effects of the oxygen precursor flow supplied during metalorganic chemical vapor deposition (MOCVD) of Al2O3 films on the forward bias behavior of Al2O3/GaN metal-oxide-semiconductor capacitors. The low oxygen flow (100 sccm) delivered during the in situ growth of Al2O3 on GaN resulted in films that exhibited a stable capacitance under forward stress, a lower density of stress-generated negative fixed charges, and a higher dielectric breakdown strength compared to Al2O3 films grown under high oxygen flow (480 sccm). The low oxygen grown Al2O3 dielectrics exhibited lower gate current transients in stress/recovery measurements, providing evidence of a reduced density of trap states near the GaN conduction band and an enhanced robustness under accumulated gate stress. This work reveals oxygen flow variance in MOCVD to be a strategy for controlling the dielectric properties and performance.

Physical and electrical characterizations of AlGaN/GaN MOS gate stacks with AlGaN surface oxidation treatment

NASA Astrophysics Data System (ADS)

Yamada, Takahiro; Watanabe, Kenta; Nozaki, Mikito; Shih, Hong-An; Nakazawa, Satoshi; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

The impacts of inserting ultrathin oxides into insulator/AlGaN interfaces on their electrical properties were investigated to develop advanced AlGaN/GaN metal–oxide–semiconductor (MOS) gate stacks. For this purpose, the initial thermal oxidation of AlGaN surfaces in oxygen ambient was systematically studied by synchrotron radiation X-ray photoelectron spectroscopy (SR-XPS) and atomic force microscopy (AFM). Our physical characterizations revealed that, when compared with GaN surfaces, aluminum addition promotes the initial oxidation of AlGaN surfaces at temperatures of around 400 °C, followed by smaller grain growth above 850 °C. Electrical measurements of AlGaN/GaN MOS capacitors also showed that, although excessive oxidation treatment of AlGaN surfaces over around 700 °C has an adverse effect, interface passivation with the initial oxidation of the AlGaN surfaces at temperatures ranging from 400 to 500 °C was proven to be beneficial for fabricating high-quality AlGaN/GaN MOS gate stacks.

Direct Interaction between the Voltage Sensors Produces Cooperative Sustained Deactivation in Voltage-gated H+ Channel Dimers*

PubMed Central

Okuda, Hiroko; Yonezawa, Yasushige; Takano, Yu; Okamura, Yasushi; Fujiwara, Yuichiro

2016-01-01

The voltage-gated H+ channel (Hv) is a voltage sensor domain-like protein consisting of four transmembrane segments (S1–S4). The native Hv structure is a homodimer, with the two channel subunits functioning cooperatively. Here we show that the two voltage sensor S4 helices within the dimer directly cooperate via a π-stacking interaction between Trp residues at the middle of each segment. Scanning mutagenesis showed that Trp situated around the original position provides the slow gating kinetics characteristic of the dimer's cooperativity. Analyses of the Trp mutation on the dimeric and monomeric channel backgrounds and analyses with tandem channel constructs suggested that the two Trp residues within the dimer are functionally coupled during Hv deactivation but are less so during activation. Molecular dynamics simulation also showed direct π-stacking of the two Trp residues. These results provide new insight into the cooperative function of voltage-gated channels, where adjacent voltage sensor helices make direct physical contact and work as a single unit according to the gating process. PMID:26755722

Image charge models for accurate construction of the electrostatic self-energy of 3D layered nanostructure devices.

PubMed

Barker, John R; Martinez, Antonio

2018-04-04

Efficient analytical image charge models are derived for the full spatial variation of the electrostatic self-energy of electrons in semiconductor nanostructures that arises from dielectric mismatch using semi-classical analysis. The methodology provides a fast, compact and physically transparent computation for advanced device modeling. The underlying semi-classical model for the self-energy has been established and validated during recent years and depends on a slight modification of the macroscopic static dielectric constants for individual homogeneous dielectric regions. The model has been validated for point charges as close as one interatomic spacing to a sharp interface. A brief introduction to image charge methodology is followed by a discussion and demonstration of the traditional failure of the methodology to derive the electrostatic potential at arbitrary distances from a source charge. However, the self-energy involves the local limit of the difference between the electrostatic Green functions for the full dielectric heterostructure and the homogeneous equivalent. It is shown that high convergence may be achieved for the image charge method for this local limit. A simple re-normalisation technique is introduced to reduce the number of image terms to a minimum. A number of progressively complex 3D models are evaluated analytically and compared with high precision numerical computations. Accuracies of 1% are demonstrated. Introducing a simple technique for modeling the transition of the self-energy between disparate dielectric structures we generate an analytical model that describes the self-energy as a function of position within the source, drain and gated channel of a silicon wrap round gate field effect transistor on a scale of a few nanometers cross-section. At such scales the self-energies become large (typically up to ~100 meV) close to the interfaces as well as along the channel. The screening of a gated structure is shown to reduce the self-energy relative to un-gated nanowires.

Image charge models for accurate construction of the electrostatic self-energy of 3D layered nanostructure devices

NASA Astrophysics Data System (ADS)

Barker, John R.; Martinez, Antonio

2018-04-01

Efficient analytical image charge models are derived for the full spatial variation of the electrostatic self-energy of electrons in semiconductor nanostructures that arises from dielectric mismatch using semi-classical analysis. The methodology provides a fast, compact and physically transparent computation for advanced device modeling. The underlying semi-classical model for the self-energy has been established and validated during recent years and depends on a slight modification of the macroscopic static dielectric constants for individual homogeneous dielectric regions. The model has been validated for point charges as close as one interatomic spacing to a sharp interface. A brief introduction to image charge methodology is followed by a discussion and demonstration of the traditional failure of the methodology to derive the electrostatic potential at arbitrary distances from a source charge. However, the self-energy involves the local limit of the difference between the electrostatic Green functions for the full dielectric heterostructure and the homogeneous equivalent. It is shown that high convergence may be achieved for the image charge method for this local limit. A simple re-normalisation technique is introduced to reduce the number of image terms to a minimum. A number of progressively complex 3D models are evaluated analytically and compared with high precision numerical computations. Accuracies of 1% are demonstrated. Introducing a simple technique for modeling the transition of the self-energy between disparate dielectric structures we generate an analytical model that describes the self-energy as a function of position within the source, drain and gated channel of a silicon wrap round gate field effect transistor on a scale of a few nanometers cross-section. At such scales the self-energies become large (typically up to ~100 meV) close to the interfaces as well as along the channel. The screening of a gated structure is shown to reduce the self-energy relative to un-gated nanowires.

Design of wide-angle solar-selective absorbers using aperiodic metal-dielectric stacks.

PubMed

Sergeant, Nicholas P; Pincon, Olivier; Agrawal, Mukul; Peumans, Peter

2009-12-07

Spectral control of the emissivity of surfaces is essential in applications such as solar thermal and thermophotovoltaic energy conversion in order to achieve the highest conversion efficiencies possible. We investigated the spectral performance of planar aperiodic metal-dielectric multilayer coatings for these applications. The response of the coatings was optimized for a target operational temperature using needle-optimization based on a transfer matrix approach. Excellent spectral selectivity was achieved over a wide angular range. These aperiodic metal-dielectric stacks have the potential to significantly increase the efficiency of thermophotovoltaic and solar thermal conversion systems. Optimal coatings for concentrated solar thermal conversion were modeled to have a thermal emissivity <7% at 720K while absorbing >94% of the incident light. In addition, optimized coatings for solar thermophotovoltaic applications were modeled to have thermal emissivity <16% at 1750K while absorbing >85% of the concentrated solar radiation.

Electronic, Mechanical, and Dielectric Properties of Two-Dimensional Atomic Layers of Noble Metals

NASA Astrophysics Data System (ADS)

Kapoor, Pooja; Kumar, Jagdish; Kumar, Arun; Kumar, Ashok; Ahluwalia, P. K.

2017-01-01

We present density functional theory-based electronic, mechanical, and dielectric properties of monolayers and bilayers of noble metals (Au, Ag, Cu, and Pt) taken with graphene-like hexagonal structure. The Au, Ag, and Pt bilayers stabilize in AA-stacked configuration, while the Cu bilayer favors the AB stacking pattern. The quantum ballistic conductance of the noble-metal mono- and bilayers is remarkably increased compared with their bulk counterparts. Among the studied systems, the tensile strength is found to be highest for the Pt monolayer and bilayer. The noble metals in mono- and bilayer form show distinctly different electron energy loss spectra and reflectance spectra due to the quantum confinement effect on going from bulk to the monolayer limit. Such tunability of the electronic and dielectric properties of noble metals by reducing the degrees of freedom of electrons offers promise for their use in nanoelectronics and optoelectronics applications.

Dynamic signatures of the transition from stacking disordered to hexagonal ice: Dielectric and nuclear magnetic resonance studies

NASA Astrophysics Data System (ADS)

Gainaru, C.; Vynokur, E.; Köster, K. W.; Fuentes-Landete, V.; Spettel, N.; Zollner, J.; Loerting, T.; Böhmer, R.

2018-04-01

Using various temperature-cycling protocols, the dynamics of ice I were studied via dielectric spectroscopy and nuclear magnetic resonance relaxometry on protonated and deuterated samples obtained by heating high-density amorphous ices as well as crystalline ice XII. Previous structural studies of ice I established that at temperatures of about 230 K, the stacking disorder of the cubic/hexagonal oxygen lattice vanishes. The present dielectric and nuclear magnetic resonance investigations of spectral changes disclose that the memory of the existence of a precursor phase is preserved in the hydrogen matrix up to 270 K. This finding of hydrogen mobility lower than that of the undoped hexagonal ice near the melting point highlights the importance of dynamical investigations of the transitions between various ice phases and sheds new light on the dynamics in ice I in general.

Process for 3D chip stacking

DOEpatents

Malba, V.

1998-11-10

A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: (1) holding individual chips for batch processing, (2) depositing a dielectric passivation layer on the top and sidewalls of the chips, (3) opening vias in the dielectric, (4) forming the interconnects by laser pantography, and (5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume. 3 figs.

Process for 3D chip stacking

DOEpatents

Malba, Vincent

1998-01-01

A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: 1) holding individual chips for batch processing, 2) depositing a dielectric passivation layer on the top and sidewalls of the chips, 3) opening vias in the dielectric, 4) forming the interconnects by laser pantography, and 5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume.

Effects of plasma-induced charging damage on random telegraph noise in metal-oxide-semiconductor field-effect transistors with SiO2 and high-k gate dielectrics

NASA Astrophysics Data System (ADS)

Kamei, Masayuki; Takao, Yoshinori; Eriguchi, Koji; Ono, Kouichi

2014-01-01

We clarified in this study how plasma-induced charging damage (PCD) affects the so-called “random telegraph noise (RTN)” — a principal concern in designing ultimately scaled large-scale integrated circuits (LSIs). Metal-oxide-semiconductor field-effect transistors (MOSFETs) with SiO2 and high-k gate dielectric were exposed to an inductively coupled plasma (ICP) with Ar gas. Drain current vs gate voltage (Ids-Vg) characteristics were obtained before and after the ICP plasma exposure for the same device. Then, the time evolution of Ids fluctuation defined as Ids/μIds was measured, where μIds is the mean Ids. This value corresponds to an RTN feature, and RTN was obtained under various gate voltages (Vg) by a customized measurement technique. We focused on the statistical distribution width of (Ids/μIds), δ(Ids/μIds), in order to clarify the effects of PCD on RTN. δ(Ids/μIds) was increased by PCD for both MOSFETs with the SiO2 and high-k gate dielectrics, suggesting that RTN can be used as a measure of PCD, i.e., a distribution width increase directly indicates the presence of PCD. The dependence of δ(Ids/μIds) on the overdrive voltage Vg-Vth, where Vth is the threshold voltage, was investigated by the present technique. It was confirmed that δ(Ids/μIds) increased with a decrease in the overdrive voltage for MOSFETs with the SiO2 and high-k gate dielectrics. The presence of created carrier trap sites with PCD was characterized by the time constants for carrier capture and emission. The threshold voltage shift (ΔVth) induced by PCD was also evaluated and compared with the RTN change, to correlate the RTN increase with ΔVth induced by PCD. Although the estimated time constants exhibited complex behaviors due to the nature of trap sites created by PCD, δ(Ids/μIds) showed a straightforward tendency in accordance with the amount of PCD. These findings provide an in-depth understanding of plasma-induced RTN characteristic changes in future MOSFETs.

Novel Dry-Type Glucose Sensor Based on a Metal-Oxide-Semiconductor Capacitor Structure with Horseradish Peroxidase + Glucose Oxidase Catalyzing Layer

NASA Astrophysics Data System (ADS)

Lin, Jing-Jenn; Wu, You-Lin; Hsu, Po-Yen

2007-10-01

In this paper, we present a novel dry-type glucose sensor based on a metal-oxide-semiconductor capacitor (MOSC) structure using SiO2 as a gate dielectric in conjunction with a horseradish peroxidase (HRP) + glucose oxidase (GOD) catalyzing layer. The tested glucose solution was dropped directly onto the window opened on the SiO2 layer, with a coating of HRP + GOD catalyzing layer on top of the gate dielectric. From the capacitance-voltage (C-V) characteristics of the sensor, we found that the glucose solution can induce an inversion layer on the silicon surface causing a gate leakage current flowing along the SiO2 surface. The gate current changes Δ I before and after the drop of glucose solution exhibits a near-linear relationship with increasing glucose concentration. The Δ I sensitivity is about 1.76 nA cm-2 M-1, and the current is quite stable 20 min after the drop of the glucose solution is tested.

Quasi-Two-Dimensional h-BN/β-Ga2O3 Heterostructure Metal-Insulator-Semiconductor Field-Effect Transistor.

PubMed

Kim, Janghyuk; Mastro, Michael A; Tadjer, Marko J; Kim, Jihyun

2017-06-28

β-gallium oxide (β-Ga 2 O 3 ) and hexagonal boron nitride (h-BN) heterostructure-based quasi-two-dimensional metal-insulator-semiconductor field-effect transistors (MISFETs) were demonstrated by integrating mechanical exfoliation of (quasi)-two-dimensional materials with a dry transfer process, wherein nanothin flakes of β-Ga 2 O 3 and h-BN were utilized as the channel and gate dielectric, respectively, of the MISFET. The h-BN dielectric, which has an extraordinarily flat and clean surface, provides a minimal density of charged impurities on the interface between β-Ga 2 O 3 and h-BN, resulting in superior device performances (maximum transconductance, on/off ratio, subthreshold swing, and threshold voltage) compared to those of the conventional back-gated configurations. Also, double-gating of the fabricated device was demonstrated by biasing both top and bottom gates, achieving the modulation of the threshold voltage. This heterostructured wide-band-gap nanodevice shows a new route toward stable and high-power nanoelectronic devices.

Transparently wrap-gated semiconductor nanowire arrays for studies of gate-controlled photoluminescence

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nylund, Gustav; Storm, Kristian; Torstensson, Henrik

2013-12-04

We present a technique to measure gate-controlled photoluminescence (PL) on arrays of semiconductor nanowire (NW) capacitors using a transparent film of Indium-Tin-Oxide (ITO) wrapping around the nanowires as the gate electrode. By tuning the wrap-gate voltage, it is possible to increase the PL peak intensity of an array of undoped InP NWs by more than an order of magnitude. The fine structure of the PL spectrum reveals three subpeaks whose relative peak intensities change with gate voltage. We interpret this as gate-controlled state-filling of luminescing quantum dot segments formed by zincblende stacking faults in the mainly wurtzite NW crystal structure.

Parsing recursive sentences with a connectionist model including a neural stack and synaptic gating.

PubMed

Fedor, Anna; Ittzés, Péter; Szathmáry, Eörs

2011-02-21

It is supposed that humans are genetically predisposed to be able to recognize sequences of context-free grammars with centre-embedded recursion while other primates are restricted to the recognition of finite state grammars with tail-recursion. Our aim was to construct a minimalist neural network that is able to parse artificial sentences of both grammars in an efficient way without using the biologically unrealistic backpropagation algorithm. The core of this network is a neural stack-like memory where the push and pop operations are regulated by synaptic gating on the connections between the layers of the stack. The network correctly categorizes novel sentences of both grammars after training. We suggest that the introduction of the neural stack memory will turn out to be substantial for any biological 'hierarchical processor' and the minimalist design of the model suggests a quest for similar, realistic neural architectures. Copyright © 2010 Elsevier Ltd. All rights reserved.

Control of interfacial properties of Pr-oxide/Ge gate stack structure by introduction of nitrogen

NASA Astrophysics Data System (ADS)

Kato, Kimihiko; Kondo, Hiroki; Sakashita, Mitsuo; Nakatsuka, Osamu; Zaima, Shigeaki

2011-06-01

We have demonstrated the control of interfacial properties of Pr-oxide/Ge gate stack structure by the introduction of nitrogen. From C- V characteristics of Al/Pr-oxide/Ge 3N 4/Ge MOS capacitors, the interface state density decreases without the change of the accumulation capacitance after annealing. The TEM and TED measurements reveal that the crystallization of Pr-oxide is enhanced with annealing and the columnar structure of cubic-Pr 2O 3 is formed after annealing. From the depth profiles measured using XPS with Ar sputtering for the Pr-oxide/Ge 3N 4/Ge stack structure, the increase in the Ge component is not observed in a Pr-oxide film and near the interface between a Pr-oxide film and a Ge substrate. In addition, the N component segregates near the interface region, amorphous Pr-oxynitride (PrON) is formed at the interface. As a result, Pr-oxide/PrON/Ge stacked structure without the Ge-oxynitride interlayer is formed.

Integration of perovskite oxide dielectrics into complementary metal-oxide-semiconductor capacitor structures using amorphous TaSiN as oxygen diffusion barrier

NASA Astrophysics Data System (ADS)

Mešić, Biljana; Schroeder, Herbert

2011-09-01

The high permittivity perovskite oxides have been intensively investigated for their possible application as dielectric materials for stacked capacitors in dynamic random access memory circuits. For the integration of such oxide materials into the CMOS world, a conductive diffusion barrier is indispensable. An optimized stack p++-Si/Pt/Ta21Si57N21/Ir was developed and used as the bottom electrode for the oxide dielectric. The amorphous TaSiN film as oxygen diffusion barrier showed excellent conductive properties and a good thermal stability up to 700 °C in oxygen ambient. The additional protective iridium layer improved the surface roughness after annealing. A 100-nm-thick (Ba,Sr)TiO3 film was deposited using pulsed laser deposition at 550 °C, showing very promising properties for application; the maximum relative dielectric constant at zero field is κ ≈ 470, and the leakage current density is below 10-6 A/cm2 for fields lower then ± 200 kV/cm, corresponding to an applied voltage of ± 2 V.

Low-temperature sol-gel oxide TFT with a fluoropolymer dielectric to enhance the effective mobility at low operation voltage

NASA Astrophysics Data System (ADS)

Yu, Shang-Yu; Wang, Kuan-Hsun; Zan, Hsiao-Wen; Soppera, Olivier

2017-06-01

In this article, we propose a solution-processed high-performance amorphous indium-zinc oxide (a-IZO) thin-film transistor (TFT) gated with a fluoropolymer dielectric. Compared with a conventional IZO TFT with a silicon nitride dielectric, a fluoropolymer dielectric effectively reduces the operation voltage to less than 3 V and greatly increases the effective mobility 40-fold. We suggest that the dipole layer formed at the dielectric surface facilitates electron accumulation and induces the electric double-layer effect. The dipole-induced hysteresis effect is also investigated.

Nanoindentation investigation of HfO2 and Al2O3 films grown by atomic layer deposition

Treesearch

K. Tapily; Joseph E. Jakes; D. S. Stone; P. Shrestha; D. Gu; H. Baumgart; A. A. Elmustafa

2008-01-01

The challenges of reducing gate leakage current and dielectric breakdown beyond the 45 nm technology node have shifted engineers’ attention from the traditional and proven dielectric SiO2 to materials of higher dielectric constant also known as high-k materials such as hafnium oxide (HfO2) and aluminum oxide (Al2O3). These high-k materials are projected to...

Characterizations of and Radiation Effects in Several Emerging CMOS Technologies

NASA Astrophysics Data System (ADS)

Shufeng Ren

As the conventional scaling of Si based CMOS is approaching its limit at 7 nm technology node, many perceive that the adoption of novel materials and/or device structures are inevitable to keep Moore's law going. High mobility channel materials such as III-V compound semiconductors or Ge are considered promising to replace Si in order to achieve high performance as well as low power consumption. However, interface and oxide traps have become a major obstacle for high-mobility semiconductors (such as Ge, GaAs, InGaAs, GaSb, etc) to replace Si CMOS technology. Therefore novel high-k dielectrics, such as epitaxially grown crystalline oxides, have been explored to be incorporated onto the high mobility channel materials. Moreover, to enable continued scaling, extremely scaled devices structures such as nanowire gate-all-around structure are needed in the near future. Moreover, as the CMOS industry moves into the 7 nm node and beyond, novel lithography techniques such as EUV are believed to be adopted soon, which can bring radiation damage to CMOS devices and circuit during the fabrication process. Therefore radiation hardening technology in future generations of CMOS devices has again become an interesting research topic to deal with the possible process-induced damage as well as damage caused by operating in radiation harsh environment such as outer space, nuclear plant, etc. In this thesis, the electrical properties of a few selected emerging novel CMOS devices are investigated, which include InGaAs based extremely scaled ultra-thin body nanowire gate-all-around MOSFETs, GOI (Ge On Insulator) CMOS with recessed channel and source/drain, GaAs MOSFETs with crystalline La based gate stack, and crystalline SrTiO3, are investigated to extend our understanding of their electrical characteristics, underlying physical mechanisms, and material properties. Furthermore, the radiation responses of these aforementioned novel devices are thoroughly investigated, with a focus on the total ionizing dose (TID) effect, to understand the associated physical mechanisms, and to help to inspire ideas to improve radiation immunity of these novel devices. The experimental methods used in this thesis research include the measurements of C-V, I-V characteristics, where novel gate stack and interface characterization techniques are employed, such as AC Gm method, 1/f low frequency noise method, inelastic electron tunneling spectroscopy (IETS) for chemical bonding and defects detection, and carrier transport modeling. Sentaurus TCAD simulations are also carried out to obtain more physical insight in the complex, extremely scaled, device structures.

Solution-Processed Transistors Using Colloidal Nanocrystals with Composition-Matched Molecular "Solders": Approaching Single Crystal Mobility.

PubMed

Jang, Jaeyoung; Dolzhnikov, Dmitriy S; Liu, Wenyong; Nam, Sooji; Shim, Moonsub; Talapin, Dmitri V

2015-10-14

Crystalline silicon-based complementary metal-oxide-semiconductor transistors have become a dominant platform for today's electronics. For such devices, expensive and complicated vacuum processes are used in the preparation of active layers. This increases cost and restricts the scope of applications. Here, we demonstrate high-performance solution-processed CdSe nanocrystal (NC) field-effect transistors (FETs) that exhibit very high carrier mobilities (over 400 cm(2)/(V s)). This is comparable to the carrier mobilities of crystalline silicon-based transistors. Furthermore, our NC FETs exhibit high operational stability and MHz switching speeds. These NC FETs are prepared by spin coating colloidal solutions of CdSe NCs capped with molecular solders [Cd2Se3](2-) onto various oxide gate dielectrics followed by thermal annealing. We show that the nature of gate dielectrics plays an important role in soldered CdSe NC FETs. The capacitance of dielectrics and the NC electronic structure near gate dielectric affect the distribution of localized traps and trap filling, determining carrier mobility and operational stability of the NC FETs. We expand the application of the NC soldering process to core-shell NCs consisting of a III-V InAs core and a CdSe shell with composition-matched [Cd2Se3](2-) molecular solders. Soldering CdSe shells forms nanoheterostructured material that combines high electron mobility and near-IR photoresponse.

Limitations of threshold voltage engineering of AlGaN/GaN heterostructures by dielectric interface charge density and manipulation by oxygen plasma surface treatments

NASA Astrophysics Data System (ADS)

Lükens, G.; Yacoub, H.; Kalisch, H.; Vescan, A.

2016-05-01

The interface charge density between the gate dielectric and an AlGaN/GaN heterostructure has a significant impact on the absolute value and stability of the threshold voltage Vth of metal-insulator-semiconductor (MIS) heterostructure field effect transistor. It is shown that a dry-etching step (as typically necessary for normally off devices engineered by gate-recessing) before the Al2O3 gate dielectric deposition introduces a high positive interface charge density. Its origin is most likely donor-type trap states shifting Vth to large negative values, which is detrimental for normally off devices. We investigate the influence of oxygen plasma annealing techniques of the dry-etched AlGaN/GaN surface by capacitance-voltage measurements and demonstrate that the positive interface charge density can be effectively compensated. Furthermore, only a low Vth hysteresis is observable making this approach suitable for threshold voltage engineering. Analysis of the electrostatics in the investigated MIS structures reveals that the maximum Vth shift to positive voltages achievable is fundamentally limited by the onset of accumulation of holes at the dielectric/barrier interface. In the case of the Al2O3/Al0.26Ga0.74N/GaN material system, this maximum threshold voltage shift is limited to 2.3 V.

Impact of Lateral Straggle on the Analog/RF Performance of Asymmetric Gate Stack Double Gate MOSFET

NASA Astrophysics Data System (ADS)

Sivaram, Gollamudi Sai; Chakraborty, Shramana; Das, Rahul; Dasgupta, Arpan; Kundu, Atanu; Sarkar, Chandan K.

2016-09-01

This paper presents a systematic comparative study of Analog and RF performances of an underlapped double gate (U-DG) NMOSFET with Gate Stack (GS) for varying straggle lengths. Asymmetric underlap devices (A-U-DG) have been proposed as one of the remedies for reducing Short Channel Effects (SCE's) with the underlap being present towards the source for sub 20 nm devices. However, the Source to Drain (S/D) implant lateral diffusion leads to a variation in the effective underlap length. This paper investigates the impact of variation of straggle length on the Analog and RF parameters of the device. The RF performance is analyzed by considering the intrinsic capacitances (Cgd, Cgs), intrinsic resistances (Rgd, Rgs), transport delay (τm), inductance (Lsd), cutoff frequency (fT), and the maximum frequency of oscillations (fmax). The circuit performance of the devices are also studied. It is seen that the Analog and RF performances of the devices are improved by optimizing the S/D lateral straggle.

Gate-tunable diode-like current rectification and ambipolar transport in multilayer van der Waals ReSe2/WS2 p-n heterojunctions.

PubMed

Wang, Cong; Yang, Shengxue; Xiong, Wenqi; Xia, Congxin; Cai, Hui; Chen, Bin; Wang, Xiaoting; Zhang, Xinzheng; Wei, Zhongming; Tongay, Sefaattin; Li, Jingbo; Liu, Qian

2016-10-12

Vertically stacked van der Waals (vdW) heterojunctions of two-dimensional (2D) transition metal dichalcogenides (TMDs) have attracted a great deal of attention due to their fascinating properties. In this work, we report two important gate-tunable phenomena in new artificial vdW p-n heterojunctions created by vertically stacking p-type multilayer ReSe 2 and n-type multilayer WS 2 : (1) well-defined strong gate-tunable diode-like current rectification across the p-n interface is observed, and the tunability of the electronic processes is attributed to the tunneling-assisted interlayer recombination induced by majority carriers across the vdW interface; (2) the distinct ambipolar behavior under gate voltage modulation both at forward and reverse bias voltages is found in the vdW ReSe 2 /WS 2 heterojunction transistors and a corresponding transport model is proposed for the tunable polarity behaviors. The findings may provide some new opportunities for building nanoscale electronic and optoelectronic devices.

Density-functional theory molecular dynamics simulations of a-HfO2/Ge(100)(2 × 1) and a-ZrO2/Ge(100)(2 × 1) interface passivation.

PubMed

Chagarov, E A; Porter, L; Kummel, A C

2016-02-28

The structural properties of a-HfO2/Ge(2 × 1)-(001) and a-ZrO2/Ge(2 × 1)-(001) interfaces were investigated with and without a GeOx interface interlayer using density-functional theory (DFT) molecular dynamics (MD) simulations. Realistic a-HfO2 and a-ZrO2 samples were generated using a hybrid classical-DFT MD "melt-and-quench" approach and tested against experimental properties. The oxide/Ge stacks were annealed at 700 K, cooled to 0 K, and relaxed providing the system with enough freedom to form realistic interfaces. For each high-K/Ge stack type, two systems with single and double interfaces were investigated. All stacks were free of midgap states; however, stacks with a GeO(x) interlayer had band-edge states which decreased the band gaps by 0%-30%. These band-edge states were mainly produced by under-coordinated Ge atoms in GeO(x) layer or its vicinity due to deformation, intermixing, and bond-breaking. The DFT-MD simulations show that electronically passive interfaces can be formed either directly between high-K dielectrics and Ge or with a monolayer of GeO2 if the processing does not create or properly passivate under-coordinated Ge atoms and Ge's with significantly distorted bonding angles. Comparison to the charge states of the interfacial atoms from DFT to experimental x-ray photoelectron spectroscopy results shows that while most studies of gate oxide on Ge(001) have a GeO(x) interfacial layer, it is possible to form an oxide/Ge interface without a GeO(x) interfacial layer. Comparison to experiments is consistent with the dangling bonds in the suboxide being responsible for midgap state formation.

Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation

NASA Astrophysics Data System (ADS)

Seema; Chauhan, Sudakar Singh

2018-05-01

In this paper, we demonstrate the double gate vertical tunnel field-effect transistor using homo/hetero dielectric buried oxide (HDB) to obtain the optimized device characteristics. In this concern, the existence of double gate, HDB and electrode work-function engineering enhances DC performance and Analog/RF performance. The use of electrostatic doping helps to achieve higher on-current owing to occurrence of higher tunneling generation rate of charge carriers at the source/epitaxial interface. Further, lightly doped drain region and high- k dielectric below channel and drain region are responsible to suppress the ambipolar current. Simulated results clarifies that proposed device have achieved the tremendous performance in terms of driving current capability, steeper subthreshold slope (SS), drain induced barrier lowering (DIBL), hot carrier effects (HCEs) and high frequency parameters for better device reliability.

Topological Quantum Phase Transitions in Two-Dimensional Hexagonal Lattice Bilayers

NASA Astrophysics Data System (ADS)

Zhai, Xuechao; Jin, Guojun

2013-09-01

Since the successful fabrication of graphene, two-dimensional hexagonal lattice structures have become a research hotspot in condensed matter physics. In this short review, we theoretically focus on discussing the possible realization of a topological insulator (TI) phase in systems of graphene bilayer (GBL) and boron nitride bilayer (BNBL), whose band structures can be experimentally modulated by an interlayer bias voltage. Under the bias, a band gap can be opened in AB-stacked GBL but is still closed in AA-stacked GBL and significantly reduced in AA- or AB-stacked BNBL. In the presence of spin-orbit couplings (SOCs), further demonstrations indicate whether the topological quantum phase transition can be realized strongly depends on the stacking orders and symmetries of structures. It is observed that a bulk band gap can be first closed and then reopened when the Rashba SOC increases for gated AB-stacked GBL or when the intrinsic SOC increases for gated AA-stacked BNBL. This gives a distinct signal for a topological quantum phase transition, which is further characterized by a jump of the ℤ2 topological invariant. At fixed SOCs, the TI phase can be well switched by the interlayer bias and the phase boundaries are precisely determined. For AA-stacked GBL and AB-stacked BNBL, no strong TI phase exists, regardless of the strength of the intrinsic or Rashba SOCs. At last, a brief overview is given on other two-dimensional hexagonal materials including silicene and molybdenum disulfide bilayers.

Ultralow-power organic complementary circuits.

PubMed

Klauk, Hagen; Zschieschang, Ute; Pflaum, Jens; Halik, Marcus

2007-02-15

The prospect of using low-temperature processable organic semiconductors to implement transistors, circuits, displays and sensors on arbitrary substrates, such as glass or plastics, offers enormous potential for a wide range of electronic products. Of particular interest are portable devices that can be powered by small batteries or by near-field radio-frequency coupling. The main problem with existing approaches is the large power consumption of conventional organic circuits, which makes battery-powered applications problematic, if not impossible. Here we demonstrate an organic circuit with very low power consumption that uses a self-assembled monolayer gate dielectric and two different air-stable molecular semiconductors (pentacene and hexadecafluorocopperphthalocyanine, F16CuPc). The monolayer dielectric is grown on patterned metal gates at room temperature and is optimized to provide a large gate capacitance and low gate leakage currents. By combining low-voltage p-channel and n-channel organic thin-film transistors in a complementary circuit design, the static currents are reduced to below 100 pA per logic gate. We have fabricated complementary inverters, NAND gates, and ring oscillators that operate with supply voltages between 1.5 and 3 V and have a static power consumption of less than 1 nW per logic gate. These organic circuits are thus well suited for battery-powered systems such as portable display devices and large-surface sensor networks as well as for radio-frequency identification tags with extended operating range.

Investigation of Gate-Stacked In-Ga-Zn-O TFTs with Ga-Zn-O Source/Drain Electrodes by Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition.

PubMed

Wu, Chien-Hung; Chang, Kow-Ming; Chen, Yi-Ming; Huang, Bo-Wen; Zhang, Yu-Xin; Wang, Shui-Jinn; Hsu, Jui-Mei

2018-03-01

Atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) was employed for the fabrication of indium gallium zinc oxide thin-film transistors (IGZO TFTs) with high transparent gallium zinc oxide (GZO) source/drain electrodes. The influence of post-deposition annealing (PDA) temperature on GZO source/drain and device performance was studied. Device with a 300 °C annealing demonstrated excellent electrical characteristics with on/off current ratio of 2.13 × 108, saturation mobility of 10 cm2/V-s, and low subthreshold swing of 0.2 V/dec. The gate stacked LaAlO3/ZrO2 of AP-IGZO TFTs with highly transparent and conductive AP-GZO source/drain electrode show excellent gate control ability at a low operating voltage.

I2 basal stacking fault as a degradation mechanism in reverse gate-biased AlGaN/GaN HEMTs

NASA Astrophysics Data System (ADS)

Lang, A. C.; Hart, J. L.; Wen, J. G.; Miller, D. J.; Meyer, D. J.; Taheri, M. L.

2016-09-01

Here, we present the observation of a bias-induced, degradation-enhancing defect process in plasma-assisted molecular beam epitaxy grown reverse gate-biased AlGaN/GaN high electron mobility transistors (HEMTs), which is compatible with the current theoretical framework of HEMT degradation. Specifically, we utilize both conventional transmission electron microscopy and aberration-corrected transmission electron microscopy to analyze microstructural changes in not only high strained regions in degraded AlGaN/GaN HEMTs but also the extended gate-drain access region. We find a complex defect structure containing an I2 basal stacking fault and offer a potential mechanism for device degradation based on this defect structure. This work supports the reality of multiple failure mechanisms during device operation and identifies a defect potentially involved with device degradation.

Tunable surface plasmon devices

DOEpatents

Shaner, Eric A [Rio Rancho, NM; Wasserman, Daniel [Lowell, MA

2011-08-30

A tunable extraordinary optical transmission (EOT) device wherein the tunability derives from controlled variation of the dielectric constant of a semiconducting material (semiconductor) in evanescent-field contact with a metallic array of sub-wavelength apertures. The surface plasmon resonance wavelength can be changed by changing the dielectric constant of the dielectric material. In embodiments of this invention, the dielectric material is a semiconducting material. The dielectric constant of the semiconducting material in the metal/semiconductor interfacial region is controllably adjusted by adjusting one or more of the semiconductor plasma frequency, the concentration and effective mass of free carriers, and the background high-frequency dielectric constant in the interfacial region. Thermal heating and/or voltage-gated carrier-concentration changes may be used to variably adjust the value of the semiconductor dielectric constant.

Stacked dielectric elastomer actuator (SDEA): casting process, modeling and active vibration isolation

NASA Astrophysics Data System (ADS)

Li, Zhuoyuan; Sheng, Meiping; Wang, Minqing; Dong, Pengfei; Li, Bo; Chen, Hualing

2018-07-01

In this paper, a novel fabrication process of stacked dielectric elastomer actuator (SDEA) is developed based on casting process and elastomeric electrode. The so-fabricated SDEA benefits the advantages of homogenous and reproducible properties as well as little performance degradation after one-year use. A coupling model of SDEA is established by taking into consideration of the elastomeric electrode and the calculated results agree with the experiments. Based on the model, we attain the method to optimize the SDEA’s parameters. Finally, the SDEA is used as an isolator in active vibration isolation system to verify the feasibility in dynamic application. And the experiment results show a great prospect for SDEA in such application.

Nanostructured Anodic Multilayer Dielectric Stacked Metal-Insulator-Metal Capacitors.

PubMed

Karthik, R; Kannadassan, D; Baghini, Maryam Shojaei; Mallick, P S

2015-12-01

This paper presents the fabrication of Al2O3/TiO2/Al2O3 metal-insulator-metal (MIM) capacitor using anodization technique. High capacitance density of > 3.5 fF/μm2, low quadratic voltage coefficient of capacitance of < 115 ppm/V2 and a low leakage current density of 4.457 x 10(-11) A/cm2 at 3 V are achieved which are suitable for analog and mixed signal applications. We found that the anodization voltage played a major role in electrical and structural properties of the thin film. This work suggests that the anodization method can offer crystalline multilayer dielectric stack required for high performance MIM capacitor.

Discharge cell for ozone generator

DOEpatents

Nakatsuka, Suguru

2000-01-01

A discharge cell for use in an ozone generator is provided which can suppress a time-related reduction in ozone concentration without adding a catalytic gas such as nitrogen gas to oxygen gas as a raw material gas. The discharge cell includes a pair of electrodes disposed in an opposed spaced relation with a discharge space therebetween, and a dielectric layer of a three-layer structure consisting of three ceramic dielectric layers successively stacked on at least one of the electrodes, wherein a first dielectric layer of the dielectric layer contacting the one electrode contains no titanium dioxide, wherein a second dielectric layer of the dielectric layer exposed to the discharge space contains titanium dioxide in a metal element ratio of not lower than 10 wt %.

Interfacial phenomena in high-kappa dielectrics

NASA Astrophysics Data System (ADS)

Mathew, Anoop

The introduction of novel high-kappa dielectric materials to replace the traditional SiO2 insulating layer in CMOS transistors is a watershed event in the history of transistor development. Further, replacement of the traditional highly-doped polycrystalline silicon gate electrode with a new set of materials for metal gates complicates the transition and introduces further integration challenges. A whole variety of new material surfaces and interfaces are thus introduced that merit close investigation to determine parameters for optimal device performance. Nitrogen is a key component that improves the performance of a variety of materials for the next generation of these CMOS transistors. Nitrogen is introduced into new gate dielectric materials such as hafnium silicates as well as in potential metal gate materials such as hafnium nitride. A photoemission study of the binding energies of the various atoms in these systems using photoemission reveals the nature of the atomic bonding. The current study compares hafnium silicates of various compositions which were thermally nitrided at different temperatures in ammonia, hafnium nitrides, and thin HfO2 films using photoelectron spectroscopy. A recurring theme that is explored is the competition between oxygen and nitrogen atoms in bonding with hafnium and other atoms. The N 1s photoemission peak is seen to have contributions from its bonding with hafnium, oxygen, and silicon atoms. The Hf 4f and O 1s spectra similarly exhibit signatures of their bonding environment with their neighboring atoms. Angle resolved photoemission and in-situ annealing/argon sputtering experiments are used to elucidate the nature of the bonding and its evolution with processing. A nondestructive profilitng of nitrogen distribution as a function of composition in nitrided hafnium silicates is also constructed using angle resolved photoemission as a function of the take-off angle. These results are corroborated with depth reconstruction obtained using medium energy ion scattering (MEIS). A comparison of samples nitrided at progressively increasing temperatures in an ammonia environment shows substitution of oxygen with nitrogen atoms and increasing penetration of nitrogen into the gate stack. Trends in the binding energy of the the as-prepared hafnium silicates suggest that they are non-phase separated, and the binding energy of the hafnium and silicon track the relative composition. Upon being subject to rapid thermal annealing, the samples are observed to show behavior consistent with phase separation. There is also the evidence of charges at the oxide/Si interface that modify the expected behavior of the shifts in binding energy. In another set of experiments, a one-cycle atomic layer deposition (ALD) growth reaction on the water terminated Si(100) -- (2x1) surface is shown to lead to successful nucleation, high metal oxide coverage, and an abrupt metal-oxide/silicon interface as confirmed by photoemission, reflection high energy electron diffraction (RHEED), and Rutherford back scattering (RBS) measurements. Photoemission results confirm the coordination states of the hafnium and oxygen atoms. A Hf 4f core level shift is observed and assigned to the presence of the Si-O-Hf bonding environment with the more electronegative Si atom inducing the binding energy shift. This Hf 4f shift is smaller than that reported previously for silicates because of the difference of the semiconductor bonding environment. The subspecies *(O)2HfCl2 and *OHfCl3 are seen to be the predominant intermediate species in these reactions and photoemission results provide corroborative evidence for their presence. Experiments indicate that the hydroxyl sites bound to Si(100) are active for adsorption. The abrupt interface could be useful for aggressive Effective Oxide Thickness (EOT) scaling.

Bandwidth enhancement of dielectric resonator antennas

NASA Technical Reports Server (NTRS)

Lee, Richard Q.; Simons, Rainee N.

1993-01-01

An experimental investigation of bandwidth enhancement of dielectric resonator antennas (DRA) using parasitic elements is reported. Substantial bandwidth enhancement for the HE(sub 11delta) mode of the stacked geometry and for the HE(sub 13delta) mode of the coplanar collinear geometry was demonstrated. Excellent radiation patterns for the HE(sub 11delta) mode were also recorded.

MOSFET Electric-Charge Sensor

NASA Technical Reports Server (NTRS)

Robinson, Paul A., Jr.

1988-01-01

Charged-particle probe compact and consumes little power. Proposed modification enables metal oxide/semiconductor field-effect transistor (MOSFET) to act as detector of static electric charges or energetic charged particles. Thickened gate insulation acts as control structure. During measurements metal gate allowed to "float" to potential of charge accumulated in insulation. Stack of modified MOSFET'S constitutes detector of energetic charged particles. Each gate "floats" to potential induced by charged-particle beam penetrating its layer.

Quantum-dot size and thin-film dielectric constant: precision measurement and disparity with simple models.

PubMed

Grinolds, Darcy D W; Brown, Patrick R; Harris, Daniel K; Bulovic, Vladimir; Bawendi, Moungi G

2015-01-14

We study the dielectric constant of lead sulfide quantum dot (QD) films as a function of the volume fraction of QDs by varying the QD size and keeping the ligand constant. We create a reliable QD sizing curve using small-angle X-ray scattering (SAXS), thin-film SAXS to extract a pair-distribution function for QD spacing, and a stacked-capacitor geometry to measure the capacitance of the thin film. Our data support a reduced dielectric constant in nanoparticles.

Remote N2 plasma treatment to deposit ultrathin high-k dielectric as tunneling contact layer for single-layer MoS2 MOSFET

NASA Astrophysics Data System (ADS)

Qian, Qingkai; Zhang, Zhaofu; Hua, Mengyuan; Wei, Jin; Lei, Jiacheng; Chen, Kevin J.

2017-12-01

Remote N2 plasma treatment is explored as a surface functionalization technique to deposit ultrathin high-k dielectric on single-layer MoS2. The ultrathin dielectric is used as a tunneling contact layer, which also serves as an interfacial layer below the gate region for fabricating top-gate MoS2 metal-oxide-semiconductor field-effect transistors (MOSFETs). The fabricated devices exhibited small hysteresis and mobility as high as 14 cm2·V-1·s-1. The contact resistance was significantly reduced, which resulted in the increase of drain current from 20 to 56 µA/µm. The contact resistance reduction can be attributed to the alleviated metal-MoS2 interface reaction and the preserved conductivity of MoS2 below the source/drain metal contact.

Method of using sacrificial materials for fabricating internal cavities in laminated dielectric structures

DOEpatents

Peterson, Kenneth A [Albuquerque, NM

2009-02-24

A method of using sacrificial materials for fabricating internal cavities and channels in laminated dielectric structures, which can be used as dielectric substrates and package mounts for microelectronic and microfluidic devices. A sacrificial mandrel is placed in-between two or more sheets of a deformable dielectric material (e.g., unfired LTCC glass/ceramic dielectric), wherein the sacrificial mandrel is not inserted into a cutout made in any of the sheets. The stack of sheets is laminated together, which deforms the sheet or sheets around the sacrificial mandrel. After lamination, the mandrel is removed, (e.g., during LTCC burnout), thereby creating a hollow internal cavity in the monolithic ceramic structure.

Dielectric elastomer actuators used for pneumatic valve technology

NASA Astrophysics Data System (ADS)

Giousouf, Metin; Kovacs, Gabor

2013-10-01

Dielectric elastomer actuators have been investigated for applications in the field of pneumatic automation technology. We have developed different valve designs with stacked dielectric elastomer actuators and with integrated high voltage converters. The actuators were made using VHB-4910 material and a stacker machine for automated fabrication of the cylindrical actuators. Typical characteristics of pneumatic valves such as flow rate, power consumption and dynamic behaviour are presented. For valve construction the force and stroke parameters of the dielectric elastomer actuator have been measured. Further, benefits for valve applications using dielectric elastomers are shown as well as their potential operational area. Finally, challenges are discussed that are relevant for the use of elastomer actuators in valves for industrial applications.

Insights into thermal diffusion of germanium and oxygen atoms in HfO{sub 2}/GeO{sub 2}/Ge gate stacks and their suppressed reaction with atomically thin AlO{sub x} interlayers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ogawa, Shingo, E-mail: Shingo-Ogawa@trc.toray.co.jp; Graduate School of Engineering, Osaka University, 2-1 Yamadaoka, Suita, Osaka 565-0871; Asahara, Ryohei

2015-12-21

The thermal diffusion of germanium and oxygen atoms in HfO{sub 2}/GeO{sub 2}/Ge gate stacks was comprehensively evaluated by x-ray photoelectron spectroscopy and secondary ion mass spectrometry combined with an isotopic labeling technique. It was found that {sup 18}O-tracers composing the GeO{sub 2} underlayers diffuse within the HfO{sub 2} overlayers based on Fick's law with the low activation energy of about 0.5 eV. Although out-diffusion of the germanium atoms through HfO{sub 2} also proceeded at the low temperatures of around 200 °C, the diffusing germanium atoms preferentially segregated on the HfO{sub 2} surfaces, and the reaction was further enhanced at high temperatures withmore » the assistance of GeO desorption. A technique to insert atomically thin AlO{sub x} interlayers between the HfO{sub 2} and GeO{sub 2} layers was proven to effectively suppress both of these independent germanium and oxygen intermixing reactions in the gate stacks.« less

GaN-on-silicon high-electron-mobility transistor technology with ultra-low leakage up to 3000 V using local substrate removal and AlN ultra-wide bandgap

NASA Astrophysics Data System (ADS)

Dogmus, Ezgi; Zegaoui, Malek; Medjdoub, Farid

2018-03-01

We report on extremely low off-state leakage current in AlGaN/GaN-on-silicon metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) up to a high blocking voltage. Remarkably low off-state gate and drain leakage currents below 1 µA/mm up to 3 kV have been achieved owing to the use of a thick in situ SiN gate dielectric under the gate, and a local Si substrate removal technique combined with a cost effective 15-µm-thick AlN dielectric layer followed by a Cu deposition. This result establishes a manufacturable state-of-the-art high-voltage GaN-on-silicon power transistors while maintaining a low specific on-resistance of approximately 10 mΩ·cm2.

Water-gel for gating graphene transistors.

PubMed

Kim, Beom Joon; Um, Soong Ho; Song, Woo Chul; Kim, Yong Ho; Kang, Moon Sung; Cho, Jeong Ho

2014-05-14

Water, the primary electrolyte in biology, attracts significant interest as an electrolyte-type dielectric material for transistors compatible with biological systems. Unfortunately, the fluidic nature and low ionic conductivity of water prevents its practical usage in such applications. Here, we describe the development of a solid state, megahertz-operating, water-based gate dielectric system for operating graphene transistors. The new electrolyte systems were prepared by dissolving metal-substituted DNA polyelectrolytes into water. The addition of these biocompatible polyelectrolytes induced hydrogelation to provide solid-state integrity to the system. They also enhanced the ionic conductivities of the electrolytes, which in turn led to the quick formation of an electric double layer at the graphene/electrolyte interface that is beneficial for modulating currents in graphene transistors at high frequencies. At the optimized conditions, the Na-DNA water-gel-gated flexible transistors and inverters were operated at frequencies above 1 MHz and 100 kHz, respectively.

Resonant tunneling through discrete quantum states in stacked atomic-layered MoS2.

PubMed

Nguyen, Linh-Nam; Lan, Yann-Wen; Chen, Jyun-Hong; Chang, Tay-Rong; Zhong, Yuan-Liang; Jeng, Horng-Tay; Li, Lain-Jong; Chen, Chii-Dong

2014-05-14

Two-dimensional crystals can be assembled into three-dimensional stacks with atomic layer precision, which have already shown plenty of fascinating physical phenomena and been used for prototype vertical-field-effect-transistors.1,2 In this work, interlayer electron tunneling in stacked high-quality crystalline MoS2 films were investigated. A trilayered MoS2 film was sandwiched between top and bottom electrodes with an adjacent bottom gate, and the discrete energy levels in each layer could be tuned by bias and gate voltages. When the discrete energy levels aligned, a resonant tunneling peak appeared in the current-voltage characteristics. The peak position shifts linearly with perpendicular magnetic field, indicating formation of Landau levels. From this linear dependence, the effective mass and Fermi velocity are determined and are confirmed by electronic structure calculations. These fundamental parameters are useful for exploitation of its unique properties.

Effect of Dielectric Interface on the Performance of MoS2 Transistors.

PubMed

Li, Xuefei; Xiong, Xiong; Li, Tiaoyang; Li, Sichao; Zhang, Zhenfeng; Wu, Yanqing

2017-12-27

Because of their wide bandgap and ultrathin body properties, two-dimensional materials are currently being pursued for next-generation electronic and optoelectronic applications. Although there have been increasing numbers of studies on improving the performance of MoS 2 field-effect transistors (FETs) using various methods, the dielectric interface, which plays a decisive role in determining the mobility, interface traps, and thermal transport of MoS 2 FETs, has not been well explored and understood. In this article, we present a comprehensive experimental study on the effect of high-k dielectrics on the performance of few-layer MoS 2 FETs from 300 to 4.3 K. Results show that Al 2 O 3 /HfO 2 could boost the mobility and drain current. Meanwhile, MoS 2 transistors with Al 2 O 3 /HfO 2 demonstrate a 2× reduction in oxide trap density compared to that of the devices with the conventional SiO 2 substrate. Also, we observe a negative differential resistance effect on the device with 1 μm-channel length when using conventional SiO 2 as the gate dielectric due to self-heating, and this is effectively eliminated by using the Al 2 O 3 /HfO 2 gate dielectric. This dielectric engineering provides a highly viable route to realizing high-performance transition metal dichalcogenide-based FETs.

Through thick and thin: tuning the threshold voltage in organic field-effect transistors.

PubMed

Martínez Hardigree, Josué F; Katz, Howard E

2014-04-15

Organic semiconductors (OSCs) constitute a class of organic materials containing densely packed, overlapping conjugated molecular moieties that enable charge carrier transport. Their unique optical, electrical, and magnetic properties have been investigated for use in next-generation electronic devices, from roll-up displays and radiofrequency identification (RFID) to biological sensors. The organic field-effect transistor (OFET) is the key active element for many of these applications, but the high values, poor definition, and long-term instability of the threshold voltage (V(T)) in OFETs remain barriers to realization of their full potential because the power and control circuitry necessary to compensate for overvoltages and drifting set points decrease OFET practicality. The drifting phenomenon has been widely observed and generally termed "bias stress." Research on the mechanisms responsible for this poor V(T) control has revealed a strong dependence on the physical order and chemical makeup of the interfaces between OSCs and adjacent materials in the OFET architecture. In this Account, we review the state of the art for tuning OFET performance via chemical designs and physical processes that manipulate V(T). This parameter gets to the heart of OFET operation, as it determines the voltage regimes where OFETs are either ON or OFF, the basis for the logical function of the devices. One obvious way to decrease the magnitude and variability of V(T) is to work with thinner and higher permittivity gate dielectrics. From the perspective of interfacial engineering, we evaluate various methods that we and others have developed, from electrostatic poling of gate dielectrics to molecular design of substituted alkyl chains. Corona charging of dielectric surfaces, a method for charging the surface of an insulating material using a constant high-voltage field, is a brute force means of shifting the effective gate voltage applied to a gate dielectric. A gentler and more direct method is to apply surface voltage to dielectric interfaces by direct contact or postprocess biasing; these methods could also be adapted for high throughput printing sequences. Dielectric hydrophobicity is an important chemical property determining the stability of the surface charges. Functional organic monolayers applied to dielectrics, using the surface attachment chemistry made available from "self-assembled" monolayer chemistry, provide local electric fields without any biasing process at all. To the extent that the monolayer molecules can be printed, these are also suitable for high throughput processes. Finally, we briefly consider V(T) control in the context of device integration and reliability, such as the role of contact resistance in affecting this parameter.

Perforated-Layer Implementation Of Radio-Frequency Lenses

NASA Technical Reports Server (NTRS)

Dolgin, Benjamin P.

1996-01-01

Luneberg-type radio-frequency dielectric lenses made of stacked perforated circular dielectric sheets, according to proposal. Perforation pattern designed to achieve required spatial variation of permittivity. Consists of round holes distributed across face of each sheet in "Swiss-cheese" pattern, plus straight or curved slots that break up outer parts into petals in "daisy-wheel" pattern. Holes and slots made by numerically controlled machining.

Indium diffusion through high-k dielectrics in high-k/InP stacks

NASA Astrophysics Data System (ADS)

Dong, H.; Cabrera, W.; Galatage, R. V.; Santosh KC, Brennan, B.; Qin, X.; McDonnell, S.; Zhernokletov, D.; Hinkle, C. L.; Cho, K.; Chabal, Y. J.; Wallace, R. M.

2013-08-01

Evidence of indium diffusion through high-k dielectric (Al2O3 and HfO2) films grown on InP (100) by atomic layer deposition is observed by angle resolved X-ray photoelectron spectroscopy and low energy ion scattering spectroscopy. The analysis establishes that In-out diffusion occurs and results in the formation of a POx rich interface.

Negative refraction and sub-wavelength focusing in the visible range using transparent metallo-dielectric stacks.

PubMed

Scalora, Michael; D'Aguanno, Giuseppe; Mattiucci, Nadia; Bloemer, Mark J; de Ceglia, Domenico; Centini, Marco; Mandatori, Antonio; Sibilia, Concita; Akozbek, Neset; Cappeddu, Mirko G; Fowler, Mark; Haus, Joseph W

2007-01-22

We numerically demonstrate negative refraction of the Poynting vector and sub-wavelength focusing in the visible part of the spectrum using a transparent multilayer, metallo-dielectric photonic band gap structure. Our results reveal that in the wavelength regime of interest evanescent waves are not transmitted by the structure, and that the main underlying physical mechanisms for sub-wavelength focusing are resonance tunneling, field localization, and propagation effects. These structures offer several advantages: tunability and high transmittance (50% or better) across the visible and near IR ranges; large object-image distances, with image planes located beyond the range where the evanescent waves have decayed. From a practical point of view, our findings point to a simpler way to fabricate a material that exhibits negative refraction and maintains high transparency across a broad wavelength range. Transparent metallo-dielectric stacks also provide an opportunity to expand the exploration of wave propagation phenomena in metals, both in the linear and nonlinear regimes.

Artificial dielectric polarizing-beamsplitter and isolator for the terahertz region.

PubMed

Mendis, Rajind; Nagai, Masaya; Zhang, Wei; Mittleman, Daniel M

2017-07-19

We demonstrate a simple and effective strategy for implementing a polarizing beamsplitter for the terahertz spectral region, based on an artificial dielectric medium that is scalable to a range of desired frequencies. The artificial dielectric medium consists of a uniformly spaced stack of metal plates, which is electromagnetically equivalent to a stacked array of parallel-plate waveguides. The operation of the device relies on both the lowest-order, transverse-electric and transverse-magnetic modes of the parallel-plate waveguide. This is in contrast to previous work that relied solely on the transverse-electric mode. The fabricated polarizing beamsplitter exhibits extinction ratios as high as 42 dB along with insertion losses as low as 0.18 dB. Building on the same idea, we also demonstrate an isolator with non-reciprocal transmission, providing high isolation and low insertion loss at a select design frequency. The performance of our isolator far exceeds that of other experimentally demonstrated terahertz isolators, and indeed, even rivals that of commercially available isolators for optical wavelengths. Because these waveguide-based artificial dielectrics are low loss, inexpensive, and easy to fabricate, this approach offers a promising new route for polarization control of free-space terahertz beams.

Effect of Solvent Dielectric Constant on the Formation of Large Flat Bilayer Stacks in a Lecithin/Hexadecanol Hydrogel.

PubMed

Nakagawa, Yasuharu; Nakazawa, Hiromitsu; Kato, Satoru

2016-07-12

We investigated the effect of dielectric properties of the aqueous medium on the novel type of hydrogel composed of a crude lecithin mixture (PC70) and hexadecanol (HD), in which charged sheet-like bilayers are kept far apart due to interbilayer repulsive interaction. We used dipropylene glycol (DPG) as a modifier of the dielectric properties and examined its effect on the hydrogel by synchrotron X-ray diffraction, differential scanning calorimetry (DSC), polarized optical microscopy, and freeze-fracture electron microscopy. We found that at a DPG weight fraction in the aqueous medium WDPG ≈ 0.4, the bilayer organization is transformed into unusually large flat bilayer stacks with a regular lamellar spacing of 6.25 nm and consequently disintegration of the hydrogel takes place. Semiquantitative calculation of the interbilayer interaction energy based on the Deyaguin-Landau-Verwey-Overbeek (DLVO) theory suggested that the reduction of the aqueous medium dielectric constant ε by DPG may lower the energy barrier preventing flat bilayers from coming closer together. We inferred that the size of the bilayer sheet increases because the reduction of ε promotes protonation of acidic lipids that work as edge-capping molecules.

Diamond field effect transistors with a high-dielectric constant Ta2O5 as gate material

NASA Astrophysics Data System (ADS)

Liu, J.-W.; Liao, M.-Y.; Imura, M.; Watanabe, E.; Oosato, H.; Koide, Y.

2014-06-01

A Ta2O5/Al2O3 bilayer gate oxide with a high-dielectric constant (high-k) has been successfully applied to a hydrogenated-diamond (H-diamond) metal-insulator-semiconductor field effect transistor (MISFET). The Ta2O5 layer is prepared by a sputtering-deposition (SD) technique on the Al2O3 buffer layer fabricated by an atomic layer deposition (ALD) technique. The ALD-Al2O3 plays an important role to eliminate plasma damage for the H-diamond surface during SD-Ta2O5 deposition. The dielectric constants of the SD-Ta2O5/ALD-Al2O3 bilayer and single SD-Ta2O5 are as large as 12.7 and 16.5, respectively. The k value of the single SD-Ta2O5 in this study is in good agreement with that of the SD-Ta2O5 on oxygen-terminated diamond. The capacitance-voltage characteristic suggests low interfacial trapped charge density for the SD-Ta2O5/ALD-Al2O3/H-diamond MIS diode. The MISFET with a gate length of 4 µm has a drain current maximum and an extrinsic transconductance of -97.7 mA mm-1 (normalized by gate width) and 31.0 ± 0.1 mS mm-1, respectively. The effective mobility in the H-diamond channel layer is found to be 70.1 ± 0.5 cm2 V-1 s-1.

Electronic Asymmetry by Compositionally Braking Inversion Symmetry

NASA Astrophysics Data System (ADS)

Warusawithana, Maitri

2005-03-01

By stacking molecular layers of 3 different perovskite titanate phases, BaTiO3, SrTiO3 and CaTiO3 with atomic layer control, we construct nanostructures where global inversion symmetry is broken. With the structures clamped to the substrate, the stacking order gives rise to asymmetric strain fields. The dielectric response show asymmetric field tuning consistent with the symmetry of the stacking order. By analyzing the temperature and frequency dependence of the complex dielectric constant, we show that the response comes from activated switching of dipoles between two asymmetric states separated by an energy barrier. We find the size of average dipole units from the temperature dependence of the linewidth of field tuning curves to be around 10 unit cells in all the different nanostructures we investigate. At low temperatures we observe a deviation from the kinetic response suggesting a further growth in correlations. Pyrocurrent measurements confirm this observation indicating a phase transition to a ferro-like state. We explain the high temperature dipoles as single unit cell cross sectional columns correlated via the strain fields in the stacking direction, with the height somewhat short of the film thickness possibly due to some form of weak disorder.

Development of an active isolation mat based on dielectric elastomer stack actuators for mechanical vibration cancellation

NASA Astrophysics Data System (ADS)

Karsten, Roman; Flittner, Klaus; Haus, Henry; Schlaak, Helmut F.

2013-04-01

This paper describes the development of an active isolation mat for cancelation of vibrations on sensitive devices with a mass of up to 500 gram. Vertical disturbing vibrations are attenuated actively while horizontal vibrations are damped passively. The dimensions of the investigated mat are 140 × 140 × 20 mm. The mat contains 5 dielectric elastomer stack actuators (DESA). The design and the optimization of active isolation mat are realized by ANSYS FEM software. The best performance shows a DESA with air cushion mounted on its circumference. Within the mounting encased air increases static and reduces dynamic stiffness. Experimental results show that vibrations with amplitudes up to 200 μm can be actively eliminated.

First-principles studies of electric field effects on the electronic structure of trilayer graphene

NASA Astrophysics Data System (ADS)

Wang, Yun-Peng; Li, Xiang-Guo; Fry, James N.; Cheng, Hai-Ping

2016-10-01

A gate electric field is a powerful way to manipulate the physical properties of nanojunctions made of two-dimensional crystals. To simulate field effects on the electronic structure of trilayer graphene, we used density functional theory in combination with the effective screening medium method, which enables us to understand the field-dependent layer-layer interactions and the fundamental physics underlying band gap variations and the resulting band modifications. Two different graphene stacking orders, Bernal (or ABC) and rhombohedral (or ABA), were considered. In addition to confirming the experimentally observed band gap opening in ABC-stacked and the band overlap in ABA-stacked trilayer systems, our results reveal rich physics in these fascinating systems, where layer-layer couplings are present but some characteristics features of single-layer graphene are partially preserved. For ABC stacking, the electric-field-induced band gap size can be tuned by charge doping, while for ABA band the tunable quantity is the band overlap. Our calculations show that the electronic structures of the two stacking orders respond very differently to charge doping. We find that in the ABA stacking hole doping can reopen a band gap in the band-overlapping region, a phenomenon distinctly different from electron doping. The physical origins of the observed behaviors were fully analyzed, and we conclude that the dual-gate configuration greatly enhances the tunability of the trilayer systems.

Impact of gate geometry on ionic liquid gated ionotronic systems

DOE PAGES

Wong, Anthony T.; Noh, Joo Hyon; Pudasaini, Pushpa Raj; ...

2017-01-23

Ionic liquid electrolytes are gaining widespread application as a gate dielectric used to control ion transport in functional materials. This letter systematically examines the important influence that device geometry in standard “side gate” 3-terminal geometries plays in device performance of a well-known oxygen ion conductor. We show that the most influential component of device design is the ratio between the area of the gate electrode and the active channel, while the spacing between these components and their individual shapes has a negligible contribution. Finally, these findings provide much needed guidance in device design intended for ionotronic gating with ionic liquids.

Small signal measurement of Sc 2O 3 AlGaN/GaN moshemts

NASA Astrophysics Data System (ADS)

Luo, B.; Mehandru, R.; Kang, B. S.; Kim, J.; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Gotthold, D.; Birkhahn, R.; Peres, B.; Fitch, R.; Gillespie, J. K.; Jenkins, T.; Sewell, J.; Via, D.; Crespo, A.

2004-02-01

The rf performance of 1 × 200 μm 2 AlGaN/GaN MOS-HEMTs with Sc 2O 3 used as both the gate dielectric and as a surface passivation layer is reported. A maximum fT of ˜11 GHz and fMAX of 19 GHz were obtained. The equivalent device parameters were extracted by fitting this data to obtain the transconductance, drain resistance, drain-source resistance, transfer time and gate-drain and gate-source capacitance as a function of gate voltage. The transfer time is in the order 0.5-1 ps and decreases with increasing gate voltage.

Arbitrarily shaped dual-stacked patch antennas: A hybrid FEM simulation

NASA Technical Reports Server (NTRS)

Gong, Jian; Volakis, John L.

1995-01-01

A dual-stacked patch antenna is analyzed using a hybrid finite element - boundary integral (FE-BI) method. The metallic patches of the antenna are modeled as perfectly electric conducting (PEC) plates stacked on top of two different dielectric layers. The antenna patches may be of any shape and the lower patch is fed by a coaxial cable from underneath the ground plane or by an aperture coupled microstrip line. The ability of the hybrid FEM technique for the stacked patch antenna characterization will be stressed, and the EM coupling mechanism is also discussed with the aid of the computed near field patterns around the patches.

Investigation of Ultraviolet Light Curable Polysilsesquioxane Gate Dielectric Layers for Pentacene Thin Film Transistors.

PubMed

Shibao, Hideto; Nakahara, Yoshio; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) comprising 3-methacryloxypropyl groups was investigated as an ultraviolet (UV)-light curable gate dielectric-material for pentacene thin film transistors (TFTs). The surface of UV-light cured PSQ films was smoother than that of thermally cured ones, and the pentacene layers deposited on the UV-Iight cured PSQ films consisted of larger grains. However, carrier mobility of the TFTs using the UV-light cured PSQ films was lower than that of the TFTs using the thermally cured ones. It was shown that the cross-linker molecules, which were only added to the UV-light cured PSQ films, worked as a major mobility-limiting factor for the TFTs.

Comparison of structural and electrical properties of Lu{sub 2}O{sub 3} and Lu{sub 2}TiO{sub 5} gate dielectrics for α-InGaZnO thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pan, Tung-Ming, E-mail: tmpan@mail.cgu.edu.tw; Chen, Ching-Hung; Her, Jim-Long

We compared the structural properties and electrical characteristics of high-κ Lu{sub 2}O{sub 3} and Lu{sub 2}TiO{sub 5} gate dielectrics for amorphous indium-gallium-zinc oxide (α-InGaZnO) thin-film transistor (TFT) applications. The Lu{sub 2}O{sub 3} film has a strong Lu{sub 2}O{sub 3} (400) peak in the X-ray diffraction pattern, while the Lu{sub 2}TiO{sub 5} sample shows a relatively weak Lu{sub 2}TiO{sub 5} (102) peak. Atomic force microscopy reveals that the Lu{sub 2}O{sub 3} dielectric exhibits a rougher surface (about three times) than Lu{sub 2}TiO{sub 5} one. In X-ray photoelectron spectroscopy analysis, we found that the intensity of the O 1s peak corresponding tomore » Lu(OH){sub x} for Lu{sub 2}O{sub 3} film was higher than that of Lu{sub 2}TiO{sub 5} film. Furthermore, compared with the Lu{sub 2}O{sub 3} dielectric, the α-InGaZnO TFT using the Lu{sub 2}TiO{sub 5} gate dielectric exhibited a lower threshold voltage (from 0.43 to 0.25 V), a higher I{sub on}/I{sub off} current ratio (from 3.5 × 10{sup 6} to 1.3 × 10{sup 8}), a smaller subthreshold swing (from 276 to 130 mV/decade), and a larger field-effect mobility (from 14.5 to 24.4 cm{sup 2}/V s). These results are probably due to the incorporation of TiO{sub x} into the Lu{sub 2}O{sub 3} film to form a Lu{sub 2}TiO{sub 5} structure featuring a smooth surface, a low moisture absorption, a high dielectric constant, and a low interface state density at the oxide/channel interface. Furthermore, the stability of Lu{sub 2}O{sub 3} and Lu{sub 2}TiO{sub 5} α-InGaZnO TFTs was investigated under positive gate-bias stress (PGBS) and negative gate-bias stress (NGBS). The threshold voltage of the TFT performed under NGBS is more degradation than that under PGBS. This behavior may be attributed to the electron charge trapping at the dielectric–channel interface under PGBS, whereas the oxygen vacancies occurred in the InGaZnO under NGBS.« less

The effects of dielectric decrement and finite ion size on differential capacitance of electrolytically gated graphene

NASA Astrophysics Data System (ADS)

Daniels, Lindsey; Scott, Matthew; Mišković, Z. L.

2018-06-01

We analyze the effects of dielectric decrement and finite ion size in an aqueous electrolyte on the capacitance of a graphene electrode, and make comparisons with the effects of dielectric saturation combined with finite ion size. We first derive conditions for the cross-over from a camel-shaped to a bell-shaped capacitance of the diffuse layer. We show next that the total capacitance is dominated by a V-shaped quantum capacitance of graphene at low potentials. A broad peak develops in the total capacitance at high potentials, which is sensitive to the ion size with dielectric saturation, but is stable with dielectric decrement.

Thin-film morphology of inkjet-printed single-droplet organic transistors using polarized Raman spectroscopy: effect of blending TIPS-pentacene with insulating polymer.

PubMed

James, David T; Kjellander, B K Charlotte; Smaal, Wiljan T T; Gelinck, Gerwin H; Combe, Craig; McCulloch, Iain; Wilson, Richard; Burroughes, Jeremy H; Bradley, Donal D C; Kim, Ji-Seon

2011-12-27

We report thin-film morphology studies of inkjet-printed single-droplet organic thin-film transistors (OTFTs) using angle-dependent polarized Raman spectroscopy. We show this to be an effective technique to determine the degree of molecular order as well as to spatially resolve the orientation of the conjugated backbones of the 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-Pentacene) molecules. The addition of an insulating polymer, polystyrene (PS), does not disrupt the π-π stacking of the TIPS-Pentacene molecules. Blending in fact improves the uniformity of the molecular morphology and the active layer coverage within the device and reduces the variation in molecular orientation between polycrystalline domains. For OTFT performance, blending enhances the saturation mobility from 0.22 ± 0.05 cm(2)/(V·s) (TIPS-Pentacene) to 0.72 ± 0.17 cm(2)/(V·s) (TIPS-Pentacene:PS) in addition to improving the quality of the interface between TIPS-Pentacene and the gate dielectric in the channel, resulting in threshold voltages of ∼0 V and steep subthreshold slopes.

Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

PubMed

Choi, Woo Young; Lee, Hyun Kook

2016-01-01

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

Atomic layer deposition of insulating nitride interfacial layers for germanium metal oxide semiconductor field effect transistors with high-κ oxide/tungsten nitride gate stacks

NASA Astrophysics Data System (ADS)

Kim, Kyoung H.; Gordon, Roy G.; Ritenour, Andrew; Antoniadis, Dimitri A.

2007-05-01

Atomic layer deposition (ALD) was used to deposit passivating interfacial nitride layers between Ge and high-κ oxides. High-κ oxides on Ge surfaces passivated by ultrathin (1-2nm) ALD Hf3N4 or AlN layers exhibited well-behaved C-V characteristics with an equivalent oxide thickness as low as 0.8nm, no significant flatband voltage shifts, and midgap density of interface states values of 2×1012cm-1eV-1. Functional n-channel and p-channel Ge field effect transistors with nitride interlayer/high-κ oxide/metal gate stacks are demonstrated.

Dielectric elastomer generators that stack up

NASA Astrophysics Data System (ADS)

McKay, T. G.; Rosset, S.; Anderson, I. A.; Shea, H.

2015-01-01

This paper reports the design, fabrication, and testing of a soft dielectric elastomer power generator with a volume of less than 1 cm3. The generator is well suited to harvest energy from ambient and from human body motion as it can harvest from low frequency (sub-Hz) motions, and is compact and lightweight. Dielectric elastomers are highly stretchable variable capacitors. Electrical energy is produced when the deformation of a stretched, charged dielectric elastomer is relaxed; like-charges are compressed together and opposite-charges are pushed apart, resulting in an increased voltage. This technology provides an opportunity to produce soft, high energy density generators with unparalleled robustness. Two major issues block this goal: current configurations require rigid frames that maintain the dielectric elastomer in a prestretched state, and high energy densities have come at the expense of short lifetime. This paper presents a self-supporting stacked generator configuration which does not require rigid frames. The generator consists of 48 generator films stacked on top of each other, resulting in a structure that fits within an 11 mm diameter footprint while containing enough active material to produce useful power. To ensure sustainable power production, we also present a mathematical model for designing the electronic control of the generator which optimizes energy production while limiting the electrical stress on the generator below failure limits. When cyclically compressed at 1.6 Hz, our generator produced 1.8 mW of power, which is sufficient for many low-power wireless sensor nodes. This performance compares favorably with similarly scaled electromagnetic, piezoelectric, and electrostatic generators. The generator’s small form factor and ability to harvest useful energy from low frequency motions such as tree swaying or shoe impact provides an opportunity to deliver power to remote wireless sensor nodes or to distributed points in the human body without the need for costly periodic battery replacement.

Gate dielectric surface treatments for performance improvement of poly(3-hexylthiophene-2,5-diyl) based organic field-effect transistors

NASA Astrophysics Data System (ADS)

Nawaz, Ali; de, Cristiane, , Col; Cruz-Cruz, Isidro; Kumar, Anshu; Kumar, Anil; Hümmelgen, Ivo A.

2015-08-01

We report on enhanced performance in poly(3-hexylthiophene-2,5-diyl) (P3HT) based organic field effect transistors (OFETs) achieved by improvement in hole transport along the channel near the insulator/semiconductor (I/S) interface. The improvement in hole transport is demonstrated to occur very close to the I/S interface, after treatment of the insulator layer with sodium dodecyl sulfate (SDS). SDS is an anionic surfactant, with negatively charged heads, known for formation of micelles above critical micelle concentration (CMC), which contribute to the passivation of positively charged traps. Investigation of field-effect mobility (μFET) as a function of channel bottleneck thickness in OFETs reveals the favorable gate voltage regime where mobility is the highest. In addition, it shows that the gate dielectric surface treatment not only leads to an increase in mobility in that regime, but also displaces charge transport closer to the interface, hence pointing toward passivation of the charge traps at I/S interface. OFETs with SDS treatment were compared with untreated and vitamin C or hexadecyltrimethylammonium bromide (CTAB) treated OFETs. All the treatments resulted in significant improvements in specific dielectric capacitance, μFET, on/off current ratio and transconductance.

Epitaxial pentacene films grown on the surface of ion-beam-processed gate dielectric layer

NASA Astrophysics Data System (ADS)

Chou, W. Y.; Kuo, C. W.; Cheng, H. L.; Mai, Y. S.; Tang, F. C.; Lin, S. T.; Yeh, C. Y.; Horng, J. B.; Chia, C. T.; Liao, C. C.; Shu, D. Y.

2006-06-01

The following research describes the process of fabrication of pentacene films with submicron thickness, deposited by thermal evaporation in high vacuum. The films were fabricated with the aforementioned conditions and their characteristics were analyzed using x-ray diffraction, scanning electron microscopy, polarized Raman spectroscopy, and photoluminescence. Organic thin-film transistors (OTFTs) were fabricated on an indium tin oxide coated glass substrate, using an active layer of ordered pentacene molecules, which were grown at room temperature. Pentacene film was aligned using the ion-beam aligned method, which is typically employed to align liquid crystals. Electrical measurements taken on a thin-film transistor indicated an increase in the saturation current by a factor of 15. Pentacene-based OTFTs with argon ion-beam-processed gate dielectric layers of silicon dioxide, in which the direction of the ion beam was perpendicular to the current flow, exhibited a mobility that was up to an order of magnitude greater than that of the controlled device without ion-beam process; current on/off ratios of approximately 106 were obtained. Polarized Raman spectroscopy investigation indicated that the surface of the gate dielectric layer, treated with argon ion beam, enhanced the intermolecular coupling of pentacene molecules. The study also proposes the explanation for the mechanism of carrier transportation in pentacene films.

Magneto-Ionic Control of Interfacial Magnetic Anisotorpy

NASA Astrophysics Data System (ADS)

Bauer, Uwe; Emori, Satoru; Beach, Geoffrey

2014-03-01

Voltage control of magnetism could bring about revolutionary new spintronic memory and logic devices. Here, we examine domain wall (DW) dynamics in ultrathin Co films and nanowires under the influence of a voltage applied across a gadolinium oxide gate dielectric that simultaneously acts as an oxygen ion conductor. We investigate two electrode configurations, one with a continuous gate dielectric and the other with a patterned gate dielectric which exhibits an open oxide edge right underneath the electrode perimeter. We demonstrate that the open oxide edge acts as a fast diffusion path for oxygen ions and allows voltage-induced switching of magnetic anisotropy at the nanoscale by modulating interfacial chemistry rather than charge density. At room temperature this effect is limited to the vicinity of the open oxide edge, but at a temperature of 100°C it allows complete control over magnetic anisotropy across the whole electrode area, due to higher oxygen ion mobility at elevated temperature. We then harness this novel ``magneto-ionic'' effect to create unprecedentedly strong voltage-induced anisotropy modifications of 3000 fJ/Vm and create electrically programmable DW traps with pinning strengths of 650 Oe, enough to bring to a standstill DWs travelling at speeds of at least 20 m/s. This work is supported by the National Science Foundation through grant ECCS-1128439.

Integrated power passives

NASA Technical Reports Server (NTRS)

Xie, Huikai (Inventor); Ngo, Khai D. T. (Inventor)

2013-01-01

A multi-layer film-stack and method for forming the multilayer film-stack is given where a series of alternating layers of conducting and dielectric materials are deposited such that the conducting layers can be selectively addressed. The use of the method to form integratable high capacitance density capacitors and complete the formation of an integrated power system-on-a-chip device including transistors, conductors, inductors, and capacitors is also given.

Study of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) transistor including source drain depletion length: Model for sub-threshold behavior

NASA Astrophysics Data System (ADS)

Kumari, Vandana; Kumar, Ayush; Saxena, Manoj; Gupta, Mridula

2018-01-01

The sub-threshold model formulation of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) FET including source/drain depletion length is reported in the present work under the assumption that the ungated regions are fully depleted. To provide deeper insight into the device performance, the impact of gaussian straggle, channel length, oxide and channel thickness and high-k gate dielectric has been studied using extensive TCAD device simulation.

Reconfigurable and non-volatile vertical magnetic logic gates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Butler, J., E-mail: jbutl001@ucr.edu; Lee, B.; Shachar, M.

2014-04-28

In this paper, we discuss the concept and prototype fabrication of reconfigurable and non-volatile vertical magnetic logic gates. These gates consist of two input layers and a RESET layer. The RESET layer allows the structure to be used as either an AND or an OR gate, depending on its magnetization state. To prove this concept, the gates were fabricated using a multi-layered patterned magnetic media, in which three magnetic layers are stacked and exchange-decoupled via non-magnetic interlayers. We demonstrate the functionality of these logic gates by conducting atomic force microscopy and magnetic force microscopy (MFM) analysis of the multi-layered patternedmore » magnetic media. The logic gates operation mechanism and fabrication feasibility are both validated by the MFM imaging results.« less

Voltage tunable plasmon propagation in dual gated bilayer graphene

NASA Astrophysics Data System (ADS)

Farzaneh, Seyed M.; Rakheja, Shaloo

2017-10-01

In this paper, we theoretically investigate plasmon propagation characteristics in AB and AA stacked bilayer graphene (BLG) in the presence of energy asymmetry due to an electrostatic field oriented perpendicularly to the plane of the graphene sheet. We first derive the optical conductivity of BLG using the Kubo formalism incorporating energy asymmetry and finite electron scattering. All results are obtained for room temperature (300 K) operation. By solving Maxwell's equations in a dual gate device setup, we obtain the wavevector of propagating plasmon modes in the transverse electric (TE) and transverse magnetic (TM) directions at terahertz frequencies. The plasmon wavevector allows us to compare the compression factor, propagation length, and the mode confinement of TE and TM plasmon modes in bilayer and monolayer graphene sheets and also to study the impact of material parameters on plasmon characteristics. Our results show that the energy asymmetry can be harnessed to increase the propagation length of TM plasmons in BLG. AA stacked BLG shows a larger increase in the propagation length than AB stacked BLG; conversely, it is very insensitive to the Fermi level variations. Additionally, the dual gate structure allows independent modulation of the energy asymmetry and the Fermi level in BLG, which is advantageous for reconfiguring plasmon characteristics post device fabrication.

Switchable adhesion for wafer-handling based on dielectric elastomer stack transducers

NASA Astrophysics Data System (ADS)

Grotepaß, T.; Butz, J.; Förster-Zügel, F.; Schlaak, H. F.

2016-04-01

Vacuum grippers are often used for the handling of wafers and small devices. In order to evacuate the gripper, a gas flow is created that can harm the micro structures on the wafer. A promising alternative to vacuum grippers could be adhesive grippers with switchable adhesion. There have been some publications of gecko-inspired adhesive devices. Most of these former works consist of a structured surface which adheres to the object manipulated and an actuator for switching the adhesion. Until now different actuator principles have been investigated, like smart memory alloys and pneumatics. In this work for the first time dielectric elastomer stack transducers (DEST) are combined with a structured surface. DESTs are a promising new transducer technology with many applications in different industry sectors like medical devices, human-machine-interaction and soft robotics. Stacked dielectric elastomer transducers show thickness contraction originating from the electromechanical pressure of two compliant electrodes compressing an elastomeric dielectric when a voltage is applied. Since DESTs and the adhesive surfaces previously described are made of elastomers, it is self-evident to combine both systems in one device. The DESTs are fabricated by a spin coating process. If the flat surface of the spinning carrier is substituted for example by a perforated one, the structured elastomer surface and the DEST can be fabricated in one process. By electrical actuation the DEST contracts and laterally expands which causes the gecko-like cilia to adhere on the object to manipulate. This work describes the assembly and the experimental results of such a device using switchable adhesion. It is intended to be used for the handling of glass wafers.

Insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor devices with Al2O3 or AlTiO gate dielectrics

NASA Astrophysics Data System (ADS)

Le, Son Phuong; Nguyen, Duong Dai; Suzuki, Toshi-kazu

2018-01-01

We have investigated insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor (MIS) devices with Al2O3 or AlTiO (an alloy of Al2O3 and TiO2) gate dielectrics obtained by atomic layer deposition on AlGaN. Analyzing insulator-thickness dependences of threshold voltages for the MIS devices, we evaluated positive interface fixed charges, whose density at the AlTiO/AlGaN interface is significantly lower than that at the Al2O3/AlGaN interface. This and a higher dielectric constant of AlTiO lead to rather shallower threshold voltages for the AlTiO gate dielectric than for Al2O3. The lower interface fixed charge density also leads to the fact that the two-dimensional electron concentration is a decreasing function of the insulator thickness for AlTiO, whereas being an increasing function for Al2O3. Moreover, we discuss the relationship between the interface fixed charges and interface states. From the conductance method, it is shown that the interface state densities are very similar at the Al2O3/AlGaN and AlTiO/AlGaN interfaces. Therefore, we consider that the lower AlTiO/AlGaN interface fixed charge density is not owing to electrons trapped at deep interface states compensating the positive fixed charges and can be attributed to a lower density of oxygen-related interface donors.

Voltage Scaling of Graphene Device on SrTiO3 Epitaxial Thin Film.

PubMed

Park, Jeongmin; Kang, Haeyong; Kang, Kyeong Tae; Yun, Yoojoo; Lee, Young Hee; Choi, Woo Seok; Suh, Dongseok

2016-03-09

Electrical transport in monolayer graphene on SrTiO3 (STO) thin film is examined in order to promote gate-voltage scaling using a high-k dielectric material. The atomically flat surface of thin STO layer epitaxially grown on Nb-doped STO single-crystal substrate offers good adhesion between the high-k film and graphene, resulting in nonhysteretic conductance as a function of gate voltage at all temperatures down to 2 K. The two-terminal conductance quantization under magnetic fields corresponding to quantum Hall states survives up to 200 K at a magnetic field of 14 T. In addition, the substantial shift of charge neutrality point in graphene seems to correlate with the temperature-dependent dielectric constant of the STO thin film, and its effective dielectric properties could be deduced from the universality of quantum phenomena in graphene. Our experimental data prove that the operating voltage reduction can be successfully realized due to the underlying high-k STO thin film, without any noticeable degradation of graphene device performance.

Temperature-dependent field-effect carrier mobility in organic thin-film transistors with a gate SiO2 dielectric modified by H2O2 treatment

NASA Astrophysics Data System (ADS)

Lin, Yow-Jon; Hung, Cheng-Chun

2018-02-01

The effect of the modification of a gate SiO2 dielectric using an H2O2 solution on the temperature-dependent behavior of carrier transport for pentacene-based organic thin-film transistors (OTFTs) is studied. H2O2 treatment leads to the formation of Si(-OH) x (i.e., the formation of a hydroxylated layer) on the SiO2 surface that serves to reduce the SiO2 capacitance and weaken the pentacene-SiO2 interaction, thus increasing the field-effect carrier mobility ( µ) in OTFTs. The temperature-dependent behavior of carrier transport is dominated by the multiple trapping model. Note that H2O2 treatment leads to a reduction in the activation energy. The increased value of µ is also attributed to the weakening of the interactions of the charge carriers with the SiO2 dielectric that serves to reduce the activation energy.

A study on the effect of surface topography on the actuation performance of stacked-rolled dielectric electro active polymer actuator

NASA Astrophysics Data System (ADS)

Sait, Usha; Muthuswamy, Sreekumar

2016-05-01

Dielectric electro active polymer (DEAP) is a suitable actuator material that finds wide applications in the field of robotics and medical areas. This material is highly controllable, flexible, and capable of developing large strain. The influence of geometrical behavior becomes critical when the material is used as miniaturized actuation devices in robotic applications. The present work focuses on the effect of surface topography on the performance of flat (single sheet) and stacked-rolled DEAP actuators. The non-active areas in the form of elliptical spots that affect the performance of the actuator are identified using scanning electron microscope (SEM) and energy dissipated X-ray (EDX) experiments. Performance of DEAP actuation is critically evaluated, compared, and presented with analytical and experimental results.

Green’s Functions for a Theoretical Model of an Aperture Fed Stacked-Patch Microstrip Antenna

DTIC Science & Technology

1989-12-01

44 4 - 1 Normalized values of D bk3b on the real axis for (a) f = 4 GHz, bib = 1.6 mm, b2b = 4.8 mm, Flb = 5 o’ 2b = 2.5 Eo’ 3b = Co, P’lb = 2b...dielectric la. bIb Thickness of dielectric lb. b2b Total thickness of dielectrics lb and 2b. Cli Observer cell on the aperture, i is an index variable...interface 3b (patch 2). Sfj Source current cell on the feedline. tb Thickness of dielectric layer 2b ( b2b - bib). T lj Vector rooftop basis function

Ambipolar transport of silver nanoparticles decorated graphene oxide field effect transistors

NASA Astrophysics Data System (ADS)

Sarkar, Kalyan Jyoti; Sarkar, K.; Pal, B.; Kumar, Aparabal; Das, Anish; Banerji, P.

2018-05-01

In this article, we report ambipolar field effect transistor (FET) by using graphene oxide (GO) as a gate dielectric material for silver nanoparticles (AgNPs) decorated GO channel layer. GO was synthesized by Hummers' method. The AgNPs were prepared via photochemical reduction of silver nitrate solution by using monoethanolamine as a reducing agent. Morphological properties of channel layer were characterized by Field Effect Scanning Electron Microscopy (FESEM). Fourier Transform Infrared Spectroscopy (FTIR) was carried out to characterize GO thin film. For device fabrication gold (Au) was deposited as source-drain contact and aluminum (Al) was taken as bottom contact. Electrical measurements were performed by back gate configuration. Ambipolar transport behavior was explained from transfer characteristics. A maximum electron mobiliy of 6.65 cm2/Vs and a hole mobility of 2.46 cm2/Vs were extracted from the transfer characteristics. These results suggest that GO is a potential candidate as a gate dielectric material for thin film transistor applications and also provides new insights in GO based research.

Compact particle accelerator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Elizondo-Decanini, Juan M.

2017-08-29

A compact particle accelerator having an input portion configured to receive power to produce particles for acceleration, where the input portion includes a switch, is provided. In a general embodiment, a vacuum tube receives particles produced from the input portion at a first end, and a plurality of wafer stacks are positioned serially along the vacuum tube. Each of the plurality of wafer stacks include a dielectric and metal-oxide pair, wherein each of the plurality of wafer stacks further accelerate the particles in the vacuum tube. A beam shaper coupled to a second end of the vacuum tube shapes themore » particles accelerated by the plurality of wafer stacks into a beam and an output portion outputs the beam.« less

Separation and counting of single molecules through nanofluidics, programmable electrophoresis, and nanoelectrode-gated tunneling and dielectric detection

DOEpatents

Lee, James W.; Thundat, Thomas G.

2006-04-25

An apparatus for carrying out the separation, detection, and/or counting of single molecules at nanometer scale. Molecular separation is achieved by driving single molecules through a microfluidic or nanofluidic medium using programmable and coordinated electric fields. In various embodiments, the fluidic medium is a strip of hydrophilic material on nonconductive hydrophobic surface, a trough produced by parallel strips of hydrophobic nonconductive material on a hydrophilic base, or a covered passageway produced by parallel strips of hydrophobic nonconductive material on a hydrophilic base together with a nonconductive cover on the parallel strips of hydrophobic nonconductive material. The molecules are detected and counted using nanoelectrode-gated electron tunneling methods, dielectric monitoring, and other methods.

Large Bandgap Shrinkage from Doping and Dielectric Interface in Semiconducting Carbon Nanotubes

NASA Astrophysics Data System (ADS)

Comfort, Everett; Lee, Ji Ung

2016-06-01

The bandgap of a semiconductor is one of its most important electronic properties. It is often considered to be a fixed property of the semiconductor. As the dimensions of semiconductors reduce, however, many-body effects become dominant. Here, we show that doping and dielectric, two critical features of semiconductor device manufacturing, can dramatically shrink (renormalize) the bandgap. We demonstrate this in quasi-one-dimensional semiconducting carbon nanotubes. Specifically, we use a four-gated device, configured as a p-n diode, to investigate the fundamental electronic structure of individual, partially supported nanotubes of varying diameter. The four-gated construction allows us to combine both electrical and optical spectroscopic techniques to measure the bandgap over a wide doping range.

A first principles approach to magnetic and optical properties in single-layer graphene sandwiched between boron nitride monolayers

NASA Astrophysics Data System (ADS)

Das, Ritwika; Chowdhury, Suman; Jana, Debnarayan

2015-07-01

The dependence of the stability of single-layer graphene (SLG) sandwiched between hexagonal boron nitride bilayers (h-BN) has been described and investigated for different types of stacking in order to provide the fingerprint of the stacking order which affects the optical properties of such trilayer systems. Considering the four stacking models AAA-, AAB-, ABA-, and ABC-type stacking, the static dielectric functions (in case of parallel polarizations) for AAB-type stacking possesses maximum values, and minimum values are noticed for AAA. However, AAA-type stacking structures contribute the maximum magnetic moment while vanishing magnetic moments are observed for ABA and ABC stacking. The observed optical anisotropy and magnetic properties of these trilayer heterostructures (h-BN/SLG/h-BN) can be understood from the crystallographic stacking order and inherent crystal lattice symmetry. These optical and magnetic results suggest that the h-BN/SLG/h-BN could provide a viable route to graphene-based opto-electronic and spintronic devices.

Mechanism of leakage of ion-implantation isolated AlGaN/GaN MIS-high electron mobility transistors on Si substrate

NASA Astrophysics Data System (ADS)

Zhang, Zhili; Song, Liang; Li, Weiyi; Fu, Kai; Yu, Guohao; Zhang, Xiaodong; Fan, Yaming; Deng, Xuguang; Li, Shuiming; Sun, Shichuang; Li, Xiajun; Yuan, Jie; Sun, Qian; Dong, Zhihua; Cai, Yong; Zhang, Baoshun

2017-08-01

In this paper, we systematically investigated the leakage mechanism of the ion-implantation isolated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) on Si substrate. By means of combined DC tests at different temperatures and electric field dependence, we demonstrated the following original results: (1) It is proved that gate leakage is the main contribution to OFF-state leakage of ion-implantation isolated AlGaN/GaN MIS-HEMTs, and the gate leakage path is a series connection of the gate dielectric Si3N4 and Si3N4-GaN interface. (2) The dominant mechanisms of the leakage current through LPCVD-Si3N4 gate dielectric and Si3N4-GaN interface are identified to be Frenkel-Poole emission and two-dimensional variable range hopping (2D-VRH), respectively. (3) A certain temperature annealing could reduce the density of the interface state that produced by ion implantation, and consequently suppress the interface leakage transport, which results in a decrease in OFF-state leakage current of ion-implantation isolated AlGaN/GaN MIS-HEMTs.

Scaling of Device Variability and Subthreshold Swing in Ballistic Carbon Nanotube Transistors

NASA Astrophysics Data System (ADS)

Cao, Qing; Tersoff, Jerry; Han, Shu-Jen; Penumatcha, Ashish V.

2015-08-01

In field-effect transistors, the inherent randomness of dopants and other charges is a major cause of device-to-device variability. For a quasi-one-dimensional device such as carbon nanotube transistors, even a single charge can drastically change the performance, making this a critical issue for their adoption as a practical technology. Here we calculate the effect of the random charges at the gate-oxide surface in ballistic carbon nanotube transistors, finding good agreement with the variability statistics in recent experiments. A combination of experimental and simulation results further reveals that these random charges are also a major factor limiting the subthreshold swing for nanotube transistors fabricated on thin gate dielectrics. We then establish that the scaling of the nanotube device uniformity with the gate dielectric, fixed-charge density, and device dimension is qualitatively different from conventional silicon transistors, reflecting the very different device physics of a ballistic transistor with a quasi-one-dimensional channel. The combination of gate-oxide scaling and improved control of fixed-charge density should provide the uniformity needed for large-scale integration of such novel one-dimensional transistors even at extremely scaled device dimensions.

Electrostatically confined trilayer graphene quantum dots

NASA Astrophysics Data System (ADS)

Mirzakhani, M.; Zarenia, M.; Vasilopoulos, P.; Peeters, F. M.

2017-04-01

Electrically gating of trilayer graphene (TLG) opens a band gap offering the possibility to electrically engineer TLG quantum dots. We study the energy levels of such quantum dots and investigate their dependence on a perpendicular magnetic field B and different types of stacking of the graphene layers. The dots are modeled as circular and confined by a truncated parabolic potential which can be realized by nanostructured gates or position-dependent doping. The energy spectra exhibit the intervalley symmetry EKe(m ) =-EK'h(m ) for the electron (e ) and hole (h ) states, where m is the angular momentum quantum number and K and K ' label the two valleys. The electron and hole spectra for B =0 are twofold degenerate due to the intervalley symmetry EK(m ) =EK'[-(m +1 ) ] . For both ABC [α =1.5 (1.2) for large (small) R ] and ABA (α =1 ) stackings, the lowest-energy levels show approximately a R-α dependence on the dot radius R in contrast with the 1 /R3 one for ABC-stacked dots with infinite-mass boundary. As functions of the field B , the oscillator strengths for dipole-allowed transitions differ drastically for the two types of stackings.

Micromixer based on dielectric stack actuators for medical applications

NASA Astrophysics Data System (ADS)

Solano-Arana, Susana; Klug, Florian; Mößinger, Holger; Förster-Zügel, Florentine; Schlaak, Helmut F.

2017-04-01

Based on a previously developed microperistaltic pump, a micromixer made out of dielectric elastomer stack actuators (DESA) is proposed. The micromixer will be able to mix two fluids at the microscale, pumping both fluids in and out of the device. The device consists of three chambers. In the first and second chambers, fluids A and B are hosted, while in the third chamber, fluids A and B are mixed. The fluid flow regime is laminar. The application of voltage leads to an increase of the size of a gap in the z-axis direction, due to the actuators area expansion. This makes a channel open through which the fluid flows. The frequency of the actuation of the different actuators allows an increase of the flow rate. The micromixer can be used for applications such as drug delivery and synthesis of nucleic acids, the proposed device will be made of Polydimethylsiloxane (PDMS) as dielectric and graphite powder as electrode material. PDMS is a biocompatible material, widely used in the prosthesis field. Mixing fluids at a microscale is also in need in the lab-on-achip technology for complex chemical reactions.

Effect of Polymer Gate Dielectrics on Charge Transport in Carbon Nanotube Network Transistors: Low-k Insulator for Favorable Active Interface.

PubMed

Lee, Seung-Hoon; Xu, Yong; Khim, Dongyoon; Park, Won-Tae; Kim, Dong-Yu; Noh, Yong-Young

2016-11-30

Charge transport in carbon nanotube network transistors strongly depends on the properties of the gate dielectric that is in direct contact with the semiconducting carbon nanotubes. In this work, we investigate the dielectric effects on charge transport in polymer-sorted semiconducting single-walled carbon nanotube field-effect transistors (s-SWNT-FETs) by using three different polymer insulators: A low-permittivity (ε r ) fluoropolymer (CYTOP, ε r = 1.8), poly(methyl methacrylate) (PMMA, ε r = 3.3), and a high-ε r ferroelectric relaxor [P(VDF-TrFE-CTFE), ε r = 14.2]. The s-SWNT-FETs with polymer dielectrics show typical ambipolar charge transport with high ON/OFF ratios (up to ∼10 5 ) and mobilities (hole mobility up to 6.77 cm 2 V -1 s -1 for CYTOP). The s-SWNT-FET with the lowest-k dielectric, CYTOP, exhibits the highest mobility owing to formation of a favorable interface for charge transport, which is confirmed by the lowest activation energies, evaluated by the fluctuation-induced tunneling model (FIT) and the traditional Arrhenius model (E aFIT = 60.2 meV and E aArr = 10 meV). The operational stability of the devices showed a good agreement with the activation energies trend (drain current decay ∼14%, threshold voltage shift ∼0.26 V in p-type regime of CYTOP devices). The poor performance in high-ε r devices is accounted for by a large energetic disorder caused by the randomly oriented dipoles in high-k dielectrics. In conclusion, the low-k dielectric forms a favorable interface with s-SWNTs for efficient charge transport in s-SWNT-FETs.

Structural and Electrical Characterization of SiO2 Gate Dielectrics Deposited from Solutions at Moderate Temperatures in Air.

PubMed

Esro, Mazran; Kolosov, Oleg; Jones, Peter J; Milne, William I; Adamopoulos, George

2017-01-11

Silicon dioxide (SiO 2 ) is the most widely used dielectric for electronic applications. It is usually produced by thermal oxidation of silicon or by using a wide range of vacuum-based techniques. By default, the growth of SiO 2 by thermal oxidation of silicon requires the use of Si substrates whereas the other deposition techniques either produce low quality or poor interface material and mostly require high deposition or annealing temperatures. Recent investigations therefore have focused on the development of alternative deposition paradigms based on solutions. Here, we report the deposition of SiO 2 thin film dielectrics deposited by spray pyrolysis in air at moderate temperatures of ≈350 °C from pentane-2,4-dione solutions of SiCl 4 . SiO 2 dielectrics were investigated by means of UV-vis absorption spectroscopy, spectroscopic ellipsometry, XPS, XRD, UFM/AFM, admittance spectroscopy, and field-effect measurements. Data analysis reveals smooth (R RMS < 1 nm) amorphous films with a dielectric constant of about 3.8, an optical band gap of ≈8.1 eV, leakage current densities in the order of ≈10 -7 A/cm 2 at 1 MV/cm, and high dielectric strength in excess of 5 MV/cm. XPS measurements confirm the SiO 2 stoichiometry and FTIR spectra reveal features related to SiO 2 only. Thin film transistors implementing spray-coated SiO 2 gate dielectrics and C 60 and pentacene semiconducting channels exhibit excellent transport characteristics, i.e., negligible hysteresis, low leakage currents, high on/off current modulation ratio on the order of 10 6 , and high carrier mobility.

Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process

NASA Astrophysics Data System (ADS)

Wang, Yan-Rong; Yang, Hong; Xu, Hao; Wang, Xiao-Lei; Luo, Wei-Chun; Qi, Lu-Wei; Zhang, Shu-Xiang; Wang, Wen-Wu; Yan, Jiang; Zhu, Hui-Long; Zhao, Chao; Chen, Da-Peng; Ye, Tian-Chun

2015-11-01

A multi-deposition multi-annealing technique (MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device’s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown (TDDB) characteristics of positive channel metal oxide semiconductor (PMOS) under different MDMA process conditions, including the deposition/annealing (D&A) cycles, the D&A time, and the total annealing time. The results show that the increases of the number of D&A cycles (from 1 to 2) and D&A time (from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail (TTF) at 63.2% increases by about several times. However, too many D&A cycles (such as 4 cycles) make the equivalent oxide thickness (EOT) increase by about 1 Å and the TTF of PMOS worsen. Moreover, different D&A times and numbers of D&A cycles induce different breakdown mechanisms. Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601) and the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129).

Characterization and Fabrication of High k dielectric-High Mobility Channel Transistors

NASA Astrophysics Data System (ADS)

Sun, Xiao

As the conventional scaling of Si-based MOSFETs would bring negligible or even negative merits for IC's beyond the 7-nm CMOS technology node, many perceive the use of high-mobility channels to be one of the most likely principle changes, in order to achieve higher performance and lower power. However, interface and oxide traps have become a major obstacle for high-mobility semiconductors (such as Ge, InGaAs, GaSb, GaN...) to replace Si CMOS technology. In this thesis, the distinct properties of the traps in the high-k dielectric/high-mobility substrate system is discussed, as well as the challenges to characterize and passivate them. By modifying certain conventional gate admittance methods, both the fast and slow traps in Ge MOS gate stacks is investigated. In addition, a novel ac-transconductance method originated at Yale is introduced and demonstrated with several advanced transistors provided by collaborating groups, such as ultra-thin-body & box SO1 MOSFETs (CEA-LETI), InGaAs MOSFETs (IMEC, UT Austin, Purdue), and GaN MOS-HEMT (MIT). By use of the aforementioned characterization techniques, several effective passivation techniques on high mobility substrates (Ge, InGaAs, GaSb, GeSn, etc.) are evaluated, including a novel Ba sub-monolayer passivation of Ge surface. The key factors that need to be considered in passivating high mobility substrates are revealed. The techniques that we have established for characterizing traps in advanced field-effect transistors, as well as the knowledge gained about these traps by the use of these techniques, have been applied to the study of ionizing radiation effects in high-mobility-channel transistors, because it is very important to understand such effects as these devices are likely to be exposed to radiation-harsh environments, such as in outer space, nuclear plants, and during X-ray or UHV lithography. In this thesis, the total ionizing dose (TD) radiation effects of InGaAs-based MOSFETs and GaN-based MOS-HEMT are studied, and the results help to reveal the underlying mechanisms and inspire ideas for minimizing the TID radiation effects.

Comparative analysis of the effects of tantalum doping and annealing on atomic layer deposited (Ta2O5)x(Al2O3)1-x as potential gate dielectrics for GaN/AlxGa1-xN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Partida-Manzanera, T.; Roberts, J. W.; Bhat, T. N.; Zhang, Z.; Tan, H. R.; Dolmanan, S. B.; Sedghi, N.; Tripathy, S.; Potter, R. J.

2016-01-01

This paper describes a method to optimally combine wide band gap Al2O3 with high dielectric constant (high-κ) Ta2O5 for gate dielectric applications. (Ta2O5)x(Al2O3)1-x thin films deposited by thermal atomic layer deposition (ALD) on GaN-capped AlxGa1-xN/GaN high electron mobility transistor (HEMT) structures have been studied as a function of the Ta2O5 molar fraction. X-ray photoelectron spectroscopy shows that the bandgap of the oxide films linearly decreases from 6.5 eV for pure Al2O3 to 4.6 eV for pure Ta2O5. The dielectric constant calculated from capacitance-voltage measurements also increases linearly from 7.8 for Al2O3 up to 25.6 for Ta2O5. The effect of post-deposition annealing in N2 at 600 °C on the interfacial properties of undoped Al2O3 and Ta-doped (Ta2O5)0.12(Al2O3)0.88 films grown on GaN-HEMTs has been investigated. These conditions are analogous to the conditions used for source/drain contact formation in gate-first HEMT technology. A reduction of the Ga-O to Ga-N bond ratios at the oxide/HEMT interfaces is observed after annealing, which is attributed to a reduction of interstitial oxygen-related defects. As a result, the conduction band offsets (CBOs) of the Al2O3/GaN-HEMT and (Ta2O5)0.16(Al2O3)0.84/GaN-HEMT samples increased by ˜1.1 eV to 2.8 eV and 2.6 eV, respectively, which is advantageous for n-type HEMTs. The results demonstrate that ALD of Ta-doped Al2O3 can be used to control the properties of the gate dielectric, allowing the κ-value to be increased, while still maintaining a sufficient CBO to the GaN-HEMT structure for low leakage currents.

Tunable Electron and Hole Injection Enabled by Atomically Thin Tunneling Layer for Improved Contact Resistance and Dual Channel Transport in MoS2/WSe2 van der Waals Heterostructure.

PubMed

Khan, Muhammad Atif; Rathi, Servin; Lee, Changhee; Lim, Dongsuk; Kim, Yunseob; Yun, Sun Jin; Youn, Doo Hyeb; Kim, Gil-Ho

2018-06-25

Two-dimensional (2D) materials based heterostructures provide a unique platform where interaction between stacked 2D layers can enhance the electrical and opto-electrical properties as well as give rise to interesting new phenomena. Here, operation of a van der Waals heterostructure device comprising of vertically stacked bi-layer MoS 2 and few layered WSe 2 has been demonstrated in which atomically thin MoS 2 layer has been employed as a tunneling layer to the underlying WSe 2 layer. In this way, simultaneous contacts to both MoS 2 and WSe 2 2D layers have been established by forming direct MS (metal semiconductor) to MoS 2 and tunneling based MIS (metal insulator semiconductor) contacts to WSe 2 , respectively. The use of MoS 2 as a dielectric tunneling layer results in improved contact resistance (80 kΩ-µm) for WSe 2 contact, which is attributed to reduction in effective Schottky barrier height and is also confirmed from the temperature dependent measurement. Further, this unique contact engineering and type II band alignment between MoS 2 and WSe 2 enables a selective and independent carrier transport across the respective layers. This contact engineered dual channel heterostructure exhibits an excellent gate control and both channel current and carrier types can be modulated by the vertical electric field of the gate electrode, which is also reflected in on/off ratio of 10 4 for both electrons (MoS 2 ) and holes (WSe 2 ) channels. Moreover, the charge transfer at the heterointerface is studied quantitatively from the shift in the threshold voltage of the pristine MoS 2 and heterostructure device, which agrees with the carrier recombination induced optical quenching as observed in the Raman spectra of the pristine and heterostructure layers. This observation of dual channel ambipolar transport enabled by the hybrid tunneling contacts and strong interlayer coupling can be utilized for high performance opto-electrical devices and applications.

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene-graphene composite layers for flexible thin film transistors with a polymer gate dielectric.

PubMed

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-02-28

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene-graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene-graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm(2) V(-1) s(-1) and a threshold voltage of -0.7 V at V(gs) = -40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm(2) V(-1) s(-1) and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies.

Comparative study on nitridation and oxidation plasma interface treatment for AlGaN/GaN MIS-HEMTs with AlN gate dielectric

NASA Astrophysics Data System (ADS)

Zhu, Jie-Jie; Ma, Xiao-Hua; Hou, Bin; Chen, Li-Xiang; Zhu, Qing; Hao, Yue

2017-02-01

This paper demonstrated the comparative study on interface engineering of AlN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) by using plasma interface pre-treatment in various ambient gases. The 15 nm AlN gate dielectric grown by plasma-enhanced atomic layer deposition significantly suppressed the gate leakage current by about two orders of magnitude and increased the peak field-effect mobility by more than 50%. NH3/N2 nitridation plasma treatment (NPT) was used to remove the 3 nm poor-quality interfacial oxide layer and N2O/N2 oxidation plasma treatment (OPT) to improve the quality of interfacial layer, both resulting in improved dielectric/barrier interface quality, positive threshold voltage (V th) shift larger than 0.9 V, and negligible dispersion. In comparison, however, NPT led to further decrease in interface charges by 3.38 × 1012 cm-2 and an extra positive V th shift of 1.3 V. Analysis with fat field-effect transistors showed that NPT resulted in better sub-threshold characteristics and transconductance linearity for MIS-HEMTs compared with OPT. The comparative study suggested that direct removing the poor interfacial oxide layer by nitridation plasma was superior to improving the quality of interfacial layer by oxidation plasma for the interface engineering of GaN-based MIS-HEMTs.

Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

NASA Astrophysics Data System (ADS)

Okamoto, Shin-ichi; Maekawa, Kei-ichi; Kawashima, Yoshiyuki; Shiba, Kazutoshi; Sugiyama, Hideki; Inoue, Masao; Nishida, Akio

2015-04-01

High quality static random access memory (SRAM) for 40-nm embedded MONOS flash memory with split gate (SG-MONOS) was developed. Marginal failure, which results in threshold voltage/drain current tailing and outliers of SRAM transistors, occurs when using a conventional SRAM structure. These phenomena can be explained by not only gate depletion but also partial depletion and percolation path formation in the MOS channel. A stacked poly-Si gate structure can suppress these phenomena and achieve high quality SRAM without any defects in the 6σ level and with high affinity to the 40-nm SG-MONOS process was developed.

Physical and Electrical Characterization of Aluminum Polymer Capacitors

NASA Technical Reports Server (NTRS)

Liu, David; Sampson, Michael J.

2010-01-01

Polymer aluminum capacitors from several manufacturers with various combinations of capacitance, rated voltage, and ESR values were physically examined and electrically characterized. The physical construction analysis of the capacitors revealed three different capacitor structures, i.e., traditional wound, stacked, and laminated. Electrical characterization results of polymer aluminum capacitors are reported for frequency-domain dielectric response at various temperatures, surge breakdown voltage, and other dielectric properties. The structure-property relations in polymer aluminum capacitors are discussed.

Physical and Electrical Characterization of Polymer Aluminum Capacitors

NASA Technical Reports Server (NTRS)

Liu, David; Sampson, Michael J.

2010-01-01

Polymer aluminum capacitors from several manufacturers with various combinations of capacitance, rated voltage, and ESR values were physically examined and electrically characterized. The physical construction analysis of the capacitors revealed three different capacitor structures, i.e., traditional wound, stacked, and laminated. Electrical characterization results of polymer aluminum capacitors are reported for frequency-domain dielectric response at various temperatures, surge breakdown voltage, and other dielectric properties. The structure-property relations in polymer aluminum capacitors are discussed.

Long range wetting transparency on top of layered metal dielectric substrates

DTIC Science & Technology

2015-11-20

multi-layered stacks were deposited onto glass substrates ( silica -based Micro cover glass , 22mmx22mm from VWR (48366-067), index of refraction n...necessarily endorsed by the United States Government. Long-range wetting transparency on top of layered metal-dielectric substrates M. A...as far as ~100 nm beneath the water/MgF2 interface. We refer to this phenomenon as long range wetting transparency . The latter effect cannot be

Electronic Subsystem Analysis (ESA)

DTIC Science & Technology

1977-01-01

than aluminum for the gate material, 0 Ion implanted source and draia regions, 0 Dielectrically isolated transistors. The use of a doped polysilicon gate...second level of interconnect ( polysilicon ). Ion implantation is essentially a precisely controllable pre-deposition of the required dopants. It’s use...discussed below). Radiation effects on MOS devices include the following: 0 Total Dose ol Dose Rate o Neutrons Because MOS technology is based on

Internal filament modulation in low-dielectric gap design for built-in selector-less resistive switching memory application

NASA Astrophysics Data System (ADS)

Chen, Ying-Chen; Lin, Chih-Yang; Huang, Hui-Chun; Kim, Sungjun; Fowler, Burt; Chang, Yao-Feng; Wu, Xiaohan; Xu, Gaobo; Chang, Ting-Chang; Lee, Jack C.

2018-02-01

Sneak path current is a severe hindrance for the application of high-density resistive random-access memory (RRAM) array designs. In this work, we demonstrate nonlinear (NL) resistive switching characteristics of a HfO x /SiO x -based stacking structure as a realization for selector-less RRAM devices. The NL characteristic was obtained and designed by optimizing the internal filament location with a low effective dielectric constant in the HfO x /SiO x structure. The stacking HfO x /SiO x -based RRAM device as the one-resistor-only memory cell is applicable without needing an additional selector device to solve the sneak path issue with a switching voltage of ~1 V, which is desirable for low-power operating in built-in nonlinearity crossbar array configurations.

Controllable Hysteresis and Threshold Voltage of Single-Walled Carbon Nano-tube Transistors with Ferroelectric Polymer Top-Gate Insulators

PubMed Central

Sun, Yi-Lin; Xie, Dan; Xu, Jian-Long; Zhang, Cheng; Dai, Rui-Xuan; Li, Xian; Meng, Xiang-Jian; Zhu, Hong-Wei

2016-01-01

Double-gated field effect transistors have been fabricated using the SWCNT networks as channel layer and the organic ferroelectric P(VDF-TrFE) film spin-coated as top gate insulators. Standard photolithography process has been adopted to achieve the patterning of organic P(VDF-TrFE) films and top-gate electrodes, which is compatible with conventional CMOS process technology. An effective way for modulating the threshold voltage in the channel of P(VDF-TrFE) top-gate transistors under polarization has been reported. The introduction of functional P(VDF-TrFE) gate dielectric also provides us an alternative method to suppress the initial hysteresis of SWCNT networks and obtain a controllable ferroelectric hysteresis behavior. Applied bottom gate voltage has been found to be another effective way to highly control the threshold voltage of the networked SWCNTs based FETs by electrostatic doping effect. PMID:26980284

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

NASA Astrophysics Data System (ADS)

Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

2009-08-01

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

Reconfigurable ultra-thin film GDNMOS device for ESD protection in 28 nm FD-SOI technology

NASA Astrophysics Data System (ADS)

Athanasiou, Sotirios; Legrand, Charles-Alexandre; Cristoloveanu, Sorin; Galy, Philippe

2017-02-01

We propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fabricated with 28 nm UTBB FD-SOI high-k metal gate technology. By modifying the combination of the diode and transistor gate stacks, the robustness of the device is optimized, achieving a maximum breakdown voltage (VBR) of 4.9 V. In addition, modifications of the gate length modulate the trigger voltage (Vt1) with a minimum value of 3.5 V. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation. A lower doping of the base enhances the bipolar gain, leading to thyristor behavior. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior.

Leakage current conduction in metal gate junctionless nanowire transistors

NASA Astrophysics Data System (ADS)

Oproglidis, T. A.; Karatsori, T. A.; Barraud, S.; Ghibaudo, G.; Dimitriadis, C. A.

2017-05-01

In this paper, the experimental off-state drain leakage current behavior is systematically explored in n- and p-channel junctionless nanowire transistors with HfSiON/TiN/p+-polysilicon gate stack. The analysis of the drain leakage current is based on experimental data of the gate leakage current. It has been shown that the off-state drain leakage current in n-channel devices is negligible, whereas in p-channel devices it is significant and dramatically increases with drain voltage. The overall results indicate that the off-state drain leakage current in p-channel devices is mainly due to trap-assisted Fowler-Nordheim tunneling of electrons through the gate oxide of electrons from the metal gate to the silicon layer near the drain region.

Gate-tunable electron interaction in high-κ dielectric films

DOE PAGES

Kondovych, Svitlana; Luk’yanchuk, Igor; Baturina, Tatyana I.; ...

2017-02-20

The two-dimensional (2D) logarithmic character of Coulomb interaction between charges and the resulting logarithmic confinement is a remarkable inherent property of high dielectric constant (high-k) thin films with far reaching implications. Most and foremost, this is the charge Berezinskii-Kosterlitz-Thouless transition with the notable manifestation, low-temperature superinsulating topological phase. Here we show that the range of the confinement can be tuned by the external gate electrode and unravel a variety of electrostatic interactions in high-k films. Lastly, our findings open a unique laboratory for the in-depth study of topological phase transitions and a plethora of related phenomena, ranging from criticality ofmore » quantum metal- and superconductor-insulator transitions to the effects of charge-trapping and Coulomb scalability in memory nanodevices.« less

Characterization of SiO{sub 2}/SiN{sub x} gate insulators for graphene based nanoelectromechanical systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tóvári, E.; Csontos, M., E-mail: csontos@dept.phy.bme.hu; Kriváchy, T.

2014-09-22

The structural and magnetotransport characterization of graphene nanodevices exfoliated onto Si/SiO{sub 2}/SiN{sub x} heterostructures are presented. Improved visibility of the deposited flakes is achieved by optimal tuning of the dielectric film thicknesses. The conductance of single layer graphene Hall-bar nanostructures utilizing SiO{sub 2}/SiN{sub x} gate dielectrics were characterized in the quantum Hall regime. Our results highlight that, while exhibiting better mechanical and chemical stability, the effect of non-stoichiometric SiN{sub x} on the charge carrier mobility of graphene is comparable to that of SiO{sub 2}, demonstrating the merits of SiN{sub x} as an ideal material platform for graphene based nanoelectromechanical applications.

Study of bulk Hafnium oxide (HfO2) under compression

NASA Astrophysics Data System (ADS)

Pathak, Santanu; Mandal, Guruprasad; Das, Parnika

2018-04-01

Hafnium oxide (HfO2) is a technologically important material. This material has K-value of 25 and band gap 5.8 eV. A k value of 25-30 is preferred for a gate dielectric [1]. As it shows good insulating and capacitive properties, HfO2 is being considered as a replacement to SiO2 in microelectronic devices as gate dielectrics. On the other hand because of toughening mechanism due to phase transformation induced by stress field observed in these oxides, HFO2 has been a material of investigations in various configurations for a very long time. However the controversies about phase transition of HfO2 under pressure still exists. High quality synchrotron radiation has been used to study the structural phase transition of HfO2 under pressure.

Computation of Dielectric Response in Molecular Solids for High Capacitance Organic Dielectrics.

PubMed

Heitzer, Henry M; Marks, Tobin J; Ratner, Mark A

2016-09-20

The dielectric response of a material is central to numerous processes spanning the fields of chemistry, materials science, biology, and physics. Despite this broad importance across these disciplines, describing the dielectric environment of a molecular system at the level of first-principles theory and computation remains a great challenge and is of importance to understand the behavior of existing systems as well as to guide the design and synthetic realization of new ones. Furthermore, with recent advances in molecular electronics, nanotechnology, and molecular biology, it has become necessary to predict the dielectric properties of molecular systems that are often difficult or impossible to measure experimentally. In these scenarios, it is would be highly desirable to be able to determine dielectric response through efficient, accurate, and chemically informative calculations. A good example of where theoretical modeling of dielectric response would be valuable is in the development of high-capacitance organic gate dielectrics for unconventional electronics such as those that could be fabricated by high-throughput printing techniques. Gate dielectrics are fundamental components of all transistor-based logic circuitry, and the combination high dielectric constant and nanoscopic thickness (i.e., high capacitance) is essential to achieving high switching speeds and low power consumption. Molecule-based dielectrics offer the promise of cheap, flexible, and mass producible electronics when used in conjunction with unconventional organic or inorganic semiconducting materials to fabricate organic field effect transistors (OFETs). The molecular dielectrics developed to date typically have limited dielectric response, which results in low capacitances, translating into poor performance of the resulting OFETs. Furthermore, the development of better performing dielectric materials has been hindered by the current highly empirical and labor-intensive pace of synthetic progress. An accurate and efficient theoretical computational approach could drastically decrease this time by screening potential dielectric materials and providing reliable design rules for future molecular dielectrics. Until recently, accurate calculation of dielectric responses in molecular materials was difficult and highly approximate. Most previous modeling efforts relied on classical formalisms to relate molecular polarizability to macroscopic dielectric properties. These efforts often vastly overestimated polarizability in the subject materials and ignored crucial material properties that can affect dielectric response. Recent advances in first-principles calculations via density functional theory (DFT) with periodic boundary conditions have allowed accurate computation of dielectric properties in molecular materials. In this Account, we outline the methodology used to calculate dielectric properties of molecular materials. We demonstrate the validity of this approach on model systems, capturing the frequency dependence of the dielectric response and achieving quantitative accuracy compared with experiment. This method is then used as a guide to new high-capacitance molecular dielectrics by determining what materials and chemical properties are important in maximizing dielectric response in self-assembled monolayers (SAMs). It will be seen that this technique is a powerful tool for understanding and designing new molecular dielectric systems, the properties of which are fundamental to many scientific areas.

Electron Transporting Semiconductor Dielectric Intramolecular

DTIC Science & Technology

2012-04-27

gate dielectric, and the capacitance times mobility was 80 nS/V (10x typical pentacene /oxide), stable to heating to 70 °C in air. Remarkably...oxide/ Pentacene Bilayer Transistors: High Mobility n-Channel, Ambipolar and Nonvolatile Devices” Adv. Funct. Mater. 18, 1832-1839 (2008) Sun, J...case of layered OSC OFETs. This proposal is somewhat different from a model by deLeeuw for amorphous OFETs13 in which carriers would be locally

Direct Effect of Dielectric Surface Energy on Carrier Transport in Organic Field-Effect Transistors.

PubMed

Zhou, Shujun; Tang, Qingxin; Tian, Hongkun; Zhao, Xiaoli; Tong, Yanhong; Barlow, Stephen; Marder, Seth R; Liu, Yichun

2018-05-09

The understanding of the characteristics of gate dielectric that leads to optimized carrier transport remains controversial, and the conventional studies applied organic semiconductor thin films, which introduces the effect of dielectric on the growth of the deposited semiconductor thin films and hence only can explore the indirect effects. Here, we introduce pregrown organic single crystals to eliminate the indirect effect (semiconductor growth) in the conventional studies and to undertake an investigation of the direct effect of dielectric on carrier transport. It is shown that the matching of the polar and dispersive components of surface energy between semiconductor and dielectric is favorable for higher mobility. This new empirical finding may show the direct relationship between dielectric and carrier transport for the optimized mobility of organic field-effect transistors and hence show a promising potential for the development of next-generation high-performance organic electronic devices.

Near-field heat transfer between graphene/hBN multilayers

NASA Astrophysics Data System (ADS)

Zhao, Bo; Guizal, Brahim; Zhang, Zhuomin M.; Fan, Shanhui; Antezza, Mauro

2017-06-01

We study the radiative heat transfer between multilayer structures made by a periodic repetition of a graphene sheet and a hexagonal boron nitride (hBN) slab. Surface plasmons in a monolayer graphene can couple with hyperbolic phonon polaritons in a single hBN film to form hybrid polaritons that can assist photon tunneling. For periodic multilayer graphene/hBN structures, the stacked metallic/dielectric array can give rise to a further effective hyperbolic behavior, in addition to the intrinsic natural hyperbolic behavior of hBN. The effective hyperbolicity can enable more hyperbolic polaritons that enhance the photon tunneling and hence the near-field heat transfer. However, the hybrid polaritons on the surface, i.e., surface plasmon-phonon polaritons, dominate the near-field heat transfer between multilayer structures when the topmost layer is graphene. The effective hyperbolic regions can be well predicted by the effective medium theory (EMT), thought EMT fails to capture the hybrid surface polaritons and results in a heat transfer rate much lower compared to the exact calculation. The chemical potential of the graphene sheets can be tuned through electrical gating and results in an additional modulation of the heat transfer. We found that the near-field heat transfer between multilayer structures does not increase monotonously with the number of layers in the stack, which provides a way to control the heat transfer rate by the number of graphene layers in the multilayer structure. The results may benefit the applications of near-field energy harvesting and radiative cooling based on hybrid polaritons in two-dimensional materials.

Single-electron-occupation metal-oxide-semiconductor quantum dots formed from efficient poly-silicon gate layout

DOE Office of Scientific and Technical Information (OSTI.GOV)

Carroll, Malcolm S.; rochette, sophie; Rudolph, Martin

We introduce a silicon metal-oxide-semiconductor quantum dot structure that achieves dot-reservoir tunnel coupling control without a dedicated barrier gate. The elementary structure consists of two accumulation gates separated spatially by a gap, one gate accumulating a reservoir and the other a quantum dot. Control of the tunnel rate between the dot and the reservoir across the gap is demonstrated in the single electron regime by varying the reservoir accumulation gate voltage while compensating with the dot accumulation gate voltage. The method is then applied to a quantum dot connected in series to source and drain reservoirs, enabling transport down tomore » the single electron regime. Finally, tuning of the valley splitting with the dot accumulation gate voltage is observed. This split accumulation gate structure creates silicon quantum dots of similar characteristics to other realizations but with less electrodes, in a single gate stack subtractive fabrication process that is fully compatible with silicon foundry manufacturing.« less

USPIO-enhanced 3D-cine self-gated cardiac MRI based on a stack-of-stars golden angle short echo time sequence: Application on mice with acute myocardial infarction.

PubMed

Trotier, Aurélien J; Castets, Charles R; Lefrançois, William; Ribot, Emeline J; Franconi, Jean-Michel; Thiaudière, Eric; Miraux, Sylvain

2016-08-01

To develop and assess a 3D-cine self-gated method for cardiac imaging of murine models. A 3D stack-of-stars (SOS) short echo time (STE) sequence with a navigator echo was performed at 7T on healthy mice (n = 4) and mice with acute myocardial infarction (MI) (n = 4) injected with ultrasmall superparamagnetic iron oxide (USPIO) nanoparticles. In all, 402 spokes were acquired per stack with the incremental or the golden angle method using an angle increment of (360/402)° or 222.48°, respectively. A cylindrical k-space was filled and repeated with a maximum number of repetitions (NR) of 10. 3D cine cardiac images at 156 μm resolution were reconstructed retrospectively and compared for the two methods in terms of contrast-to-noise ratio (CNR). The golden angle images were also reconstructed with NR = 10, 6, and 3, to assess cardiac functional parameters (ejection fraction, EF) on both animal models. The combination of 3D SOS-STE and USPIO injection allowed us to optimize the identification of cardiac peaks on navigator signal and generate high CNR between blood and myocardium (15.3 ± 1.0). The golden angle method resulted in a more homogeneous distribution of the spokes inside a stack (P < 0.05), enabling reducing the acquisition time to 15 minutes. EF was significantly different between healthy and MI mice (P < 0.05). The method proposed here showed that 3D-cine images could be obtained without electrocardiogram or respiratory gating in mice. It allows precise measurement of cardiac functional parameters even on MI mice. J. Magn. Reson. Imaging 2016;44:355-365. © 2016 Wiley Periodicals, Inc.

Reliability Evaluation of Base-Metal-Electrode (BME) Multilayer Ceramic Capacitors for Space Applications

NASA Technical Reports Server (NTRS)

Liu, David (Donghang)

2011-01-01

This paper reports reliability evaluation of BME ceramic capacitors for possible high reliability space-level applications. The study is focused on the construction and microstructure of BME capacitors and their impacts on the capacitor life reliability. First, the examinations of the construction and microstructure of commercial-off-the-shelf (COTS) BME capacitors show great variance in dielectric layer thickness, even among BME capacitors with the same rated voltage. Compared to PME (precious-metal-electrode) capacitors, BME capacitors exhibit a denser and more uniform microstructure, with an average grain size between 0.3 and approximately 0.5 micrometers, which is much less than that of most PME capacitors. The primary reasons that a BME capacitor can be fabricated with more internal electrode layers and less dielectric layer thickness is that it has a fine-grained microstructure and does not shrink much during ceramic sintering. This results in the BME capacitors a very high volumetric efficiency. The reliability of BME and PME capacitors was investigated using highly accelerated life testing (HALT) and regular life testing as per MIL-PRF-123. Most BME capacitors were found to fail· with an early dielectric wearout, followed by a rapid wearout failure mode during the HALT test. When most of the early wearout failures were removed, BME capacitors exhibited a minimum mean time-to-failure of more than 10(exp 5) years. Dielectric thickness was found to be a critical parameter for the reliability of BME capacitors. The number of stacked grains in a dielectric layer appears to play a significant role in determining BME capacitor reliability. Although dielectric layer thickness varies for a given rated voltage in BME capacitors, the number of stacked grains is relatively consistent, typically between 10 and 20. This may suggest that the number of grains per dielectric layer is more critical than the thickness itself for determining the rated voltage and the life expectancy of the BME capacitor. Since BME capacitors have a much smaller grain size than PME capacitors, it is reasonable to predict that BME capacitors with thinner dielectric layers may have an equivalent life expectancy to that of PME capacitors with thicker dielectric layers.

Flexible integrated diode-transistor logic (DTL) driving circuits based on printed carbon nanotube thin film transistors with low operation voltage.

PubMed

Liu, Tingting; Zhao, Jianwen; Xu, Weiwei; Dou, Junyan; Zhao, Xinluo; Deng, Wei; Wei, Changting; Xu, Wenya; Guo, Wenrui; Su, Wenming; Jie, Jiansheng; Cui, Zheng

2018-01-03

Fabrication and application of hybrid functional circuits have become a hot research topic in the field of printed electronics. In this study, a novel flexible diode-transistor logic (DTL) driving circuit is proposed, which was fabricated based on a light emitting diode (LED) integrated with printed high-performance single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs). The LED, which is made of AlGaInP on GaAs, is commercial off-the-shelf, which could generate free electrical charges upon white light illumination. Printed top-gate TFTs were made on a PET substrate by inkjet printing high purity semiconducting SWCNTs (sc-SWCNTs) ink as the semiconductor channel materials, together with printed silver ink as the top-gate electrode and printed poly(pyromellitic dianhydride-co-4,4'-oxydianiline) (PMDA/ODA) as gate dielectric layer. The LED, which is connected to the gate electrode of the TFT, generated electrical charge when illuminated, resulting in biased gate voltage to control the TFT from "ON" status to "OFF" status. The TFTs with a PMDA/ODA gate dielectric exhibited low operating voltages of ±1 V, a small subthreshold swing of 62-105 mV dec -1 and ON/OFF ratio of 10 6 , which enabled DTL driving circuits to have high ON currents, high dark-to-bright current ratios (up to 10 5 ) and good stability under repeated white light illumination. As an application, the flexible DTL driving circuit was connected to external quantum dot LEDs (QLEDs), demonstrating its ability to drive and to control the QLED.

Four-dimensional layer-stacking carbon-ion beam dose distribution by use of a lung numeric phantom.

PubMed

Mori, Shinichiro; Kumagai, Motoki; Miki, Kentaro

2015-07-01

To extend layer-stacking irradiation to accommodate intrafractional organ motion, we evaluated the carbon-ion layer-stacking dose distribution using a numeric lung phantom. We designed several types of range compensators. The planning target volume was calculated from the respective respiratory phases for consideration of intrafractional beam range variation. The accumulated dose distribution was calculated by registering of the dose distributions at respective phases to that at the reference phase. We evaluated the dose distribution based on the following six parameters: motion displacement, direction, gating window, respiratory cycle, range-shifter change time, and prescribed dose. All parameters affected the dose conformation to the moving target. By shortening of the gating window, dose metrics for superior-inferior (SI) and anterior-posterior (AP) motions were decreased from a D95 of 94 %, Dmax of 108 %, and homogeneity index (HI) of 23 % at T00-T90, to a D95 of 93 %, Dmax of 102 %, and HI of 20 % at T40-T60. In contrast, all dose metrics except the HI were independent of respiratory cycle. All dose metrics in SI motion were almost the same in respective motion displacement, with a D95 of 94 %, Dmax of 108 %, Dmin of 89 %, and HI of 23 % for the ungated phase, and D95 of 93 %, Dmax of 102 %, Dmin of 85 %, and HI of 20 % for the gated phase. The dose conformation to a moving target was improved by the gating strategy and by an increase in the prescribed dose. A combination of these approaches is a practical means of adding them to existing treatment protocols without modifications.

Poly(vinyl acetate)/clay nanocomposite materials for organic thin film transistor application.

PubMed

Park, B J; Sung, J H; Park, J H; Choi, J S; Choi, H J

2008-05-01

Nanocomposite materials of poly(vinyl acetate) (PVAc) and organoclay were fabricated, in order to be utilized as dielectric materials of the organic thin film transistor (OTFT). Spin coating condition of the nanocomposite solution was examined considering shear viscosity of the composite materials dissolved in chloroform. Intercalated structure of the PVAc/clay nanocomposites was characterized using both wide-angle X-ray diffraction and TEM. Fracture morphology of the composite film on silicon wafer was also observed by SEM. Dielectric constant (4.15) of the nanocomposite materials shows that the PVAc/clay nanocomposites are applicable for the gate dielectric materials.

Continuous adjustment of threshold voltage in carbon nanotube field-effect transistors through gate engineering

NASA Astrophysics Data System (ADS)

Zhong, Donglai; Zhao, Chenyi; Liu, Lijun; Zhang, Zhiyong; Peng, Lian-Mao

2018-04-01

In this letter, we report a gate engineering method to adjust threshold voltage of carbon nanotube (CNT) based field-effect transistors (FETs) continuously in a wide range, which makes the application of CNT FETs especially in digital integrated circuits (ICs) easier. Top-gated FETs are fabricated using solution-processed CNT network films with stacking Pd and Sc films as gate electrodes. By decreasing the thickness of the lower layer metal (Pd) from 20 nm to zero, the effective work function of the gate decreases, thus tuning the threshold voltage (Vt) of CNT FETs from -1.0 V to 0.2 V. The continuous adjustment of threshold voltage through gate engineering lays a solid foundation for multi-threshold technology in CNT based ICs, which then can simultaneously provide high performance and low power circuit modules on one chip.

Eco-Friendly and Biodegradable Biopolymer Chitosan/Y₂O₃ Composite Materials in Flexible Organic Thin-Film Transistors.

PubMed

Du, Bo-Wei; Hu, Shao-Ying; Singh, Ranjodh; Tsai, Tsung-Tso; Lin, Ching-Chang; Ko, Fu-Hsiang

2017-09-03

The waste from semiconductor manufacturing processes causes serious pollution to the environment. In this work, a non-toxic material was developed under room temperature conditions for the fabrication of green electronics. Flexible organic thin-film transistors (OTFTs) on plastic substrates are increasingly in demand due to their high visible transmission and small size for use as displays and wearable devices. This work investigates and analyzes the structured formation of aqueous solutions of the non-toxic and biodegradable biopolymer, chitosan, blended with high-k-value, non-toxic, and biocompatible Y₂O₃ nanoparticles. Chitosan thin films blended with Y₂O₃ nanoparticles were adopted as the gate dielectric thin film in OTFTs, and an improvement in the dielectric properties and pinholes was observed. Meanwhile, the on/off current ratio was increased by 100 times, and a low leakage current was observed. In general, the blended chitosan/Y₂O₃ thin films used as the gate dielectric of OTFTs are non-toxic, environmentally friendly, and operate at low voltages. These OTFTs can be used on surfaces with different curvature radii because of their flexibility.

Transistor-based particle detection systems and methods

DOEpatents

Jain, Ankit; Nair, Pradeep R.; Alam, Muhammad Ashraful

2015-06-09

Transistor-based particle detection systems and methods may be configured to detect charged and non-charged particles. Such systems may include a supporting structure contacting a gate of a transistor and separating the gate from a dielectric of the transistor, and the transistor may have a near pull-in bias and a sub-threshold region bias to facilitate particle detection. The transistor may be configured to change current flow through the transistor in response to a change in stiffness of the gate caused by securing of a particle to the gate, and the transistor-based particle detection system may configured to detect the non-charged particle at least from the change in current flow.

Floating-gate memory based on an organic metal-insulator-semiconductor capacitor

NASA Astrophysics Data System (ADS)

William, S.; Mabrook, M. F.; Taylor, D. M.

2009-08-01

A floating gate memory element is described which incorporates an evaporated gold film embedded in the gate dielectric of a metal-insulator-semiconductor capacitor based on poly(3-hexylthiophene). On exceeding a critical amplitude in the voltage sweep, hysteresis is observed in the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of the device. The anticlockwise hysteresis in C-V is consistent with strong electron trapping during the positive cycle but little hole trapping during the negative cycle. We argue that the clockwise hysteresis observed in the negative cycle of the I-V plot, arises from leakage of trapped holes through the underlying insulator to the control gate.

A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dumitru, L. M.; Manoli, K.; Magliulo, M.

2015-01-01

A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

Electrical characteristics and thermal stability of n+ polycrystalline- Si/ZrO2/SiO2/Si metal-oxide-semiconductor capacitors

NASA Astrophysics Data System (ADS)

Lim, Kwan-Yong; Park, Dae-Gyu; Cho, Heung-Jae; Kim, Joong-Jung; Yang, Jun-Mo; Ii, Choi-Sang; Yeo, In-Seok; Park, Jin Won

2002-01-01

We have investigated the thermal stability of n+ polycrystalline-Si(poly-Si)/ZrO2(50-140 Å)/SiO2(7 Å)/p-Si metal-oxide-semiconductor (MOS) capacitors via electrical and material characterization. The ZrO2 gate dielectric was prepared by atomic layer chemical vapor deposition using ZrCl4 and H2O vapor. Capacitance-voltage hysteresis as small as ˜12 mV with the flatband voltage of -0.5 V and the interface trap density of ˜5×1010cm-2 eV-1 were attained with activation anneal at 750 °C. A high level of gate leakage current was observed at the activation temperatures over 750 °C and attributed to the interfacial reaction of poly-Si and ZrO2 during the poly-Si deposition and the following high temperature anneal. Because of this, the ZrO2 gate dielectric is incompatible with the conventional poly-Si gate process. In the MOS capacitors having a smaller active area (<50×50 μm2), fortunately, the electrical degradation by further severe silicidation does not occur up to an 800 °C anneal in N2 for 30 min.

Increased Multilayer Fabrication and RF Characterization of a High-Density Stacked MIM Capacitor Based on Selective Etching

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tseng, VFG; Xie, HK

2014-07-01

This paper presents the fabrication and characterization of a high-density multilayer stacked metal-insulator-metal (MIM) capacitor based on a novel process of depositing the MIM multilayer on pillars followed by polishing and selective etching steps to form a stacked capacitor with merely three photolithography steps. In this paper, the pillars were made of glass to prevent substrate loss, whereas an oxide-nitride-oxide dielectric was employed for lower leakage, better voltage/frequency linearity, and better stress compensation. MIM capacitors with six dielectric layers were successfully fabricated, yielding capacitance density of 3.8 fF/mu m(2), maximum capacitance of 2.47 nF, and linear and quadratic voltage coefficientsmore » of capacitance below 21.2 ppm/V and 2.31 ppm/V-2. The impedance was measured from 40 Hz to 3 GHz, and characterized by an analytically derived equivalent circuit model to verify the radio frequency applicability. The multilayer stacking-induced plate resistance mismatch and its effect on the equivalent series resistance (ESR) and effective capacitance was also investigated, which can be counteracted by a corrected metal thickness design. A low ESR of 800 m Omega was achieved, whereas the self-resonance frequency was >760 MHz, successfully demonstrating the feasibility of this method to scale up capacitance densities for high-quality-factor, high-frequency, and large-value MIM capacitors.« less

Influence of Chemical Composition and Structure in Silicon Dielectric Materials on Passivation of Thin Crystalline Silicon on Glass.

PubMed

Calnan, Sonya; Gabriel, Onno; Rothert, Inga; Werth, Matteo; Ring, Sven; Stannowski, Bernd; Schlatmann, Rutger

2015-09-02

In this study, various silicon dielectric films, namely, a-SiOx:H, a-SiNx:H, and a-SiOxNy:H, grown by plasma enhanced chemical vapor deposition (PECVD) were evaluated for use as interlayers (ILs) between crystalline silicon and glass. Chemical bonding analysis using Fourier transform infrared spectroscopy showed that high values of oxidant gases (CO2 and/or N2), added to SiH4 during PECVD, reduced the Si-H and N-H bond density in the silicon dielectrics. Various three layer stacks combining the silicon dielectric materials were designed to minimize optical losses between silicon and glass in rear side contacted heterojunction pn test cells. The PECVD grown silicon dielectrics retained their functionality despite being subjected to harsh subsequent processing such as crystallization of the silicon at 1414 °C or above. High values of short circuit current density (Jsc; without additional hydrogen passivation) required a high density of Si-H bonds and for the nitrogen containing films, additionally, a high N-H bond density. Concurrently high values of both Jsc and open circuit voltage Voc were only observed when [Si-H] was equal to or exceeded [N-H]. Generally, Voc correlated with a high density of [Si-H] bonds in the silicon dielectric; otherwise, additional hydrogen passivation using an active plasma process was required. The highest Voc ∼ 560 mV, for a silicon acceptor concentration of about 10(16) cm(-3), was observed for stacks where an a-SiOxNy:H film was adjacent to the silicon. Regardless of the cell absorber thickness, field effect passivation of the buried silicon surface by the silicon dielectric was mandatory for efficient collection of carriers generated from short wavelength light (in the vicinity of the glass-Si interface). However, additional hydrogen passivation was obligatory for an increased diffusion length of the photogenerated carriers and thus Jsc in solar cells with thicker absorbers.

Solution-processable alumina: PVP nanocomposite dielectric layer for high-performance organic thin-film transistors

NASA Astrophysics Data System (ADS)

Lin, Hui; Kong, Xiao; Li, Yiran; Kuang, Peng; Tao, Silu

2018-03-01

In this article, we have investigated the effect of nanocomposite gate dielectric layer built by alumina (Al2O3) and poly(4-vinyphenol) (PVP) with solution method which could enhance the dielectric capability and decrease the surface polarity. Then, we used modify layer to optimize the surface morphology of dielectric layer to further improve the insulation capability, and finally we fabricated the high-performance and low-voltage organic thin-film transistors by using this nanocomposite dielectric layer. The result shows that the devices with Al2O3:10%PVP dielectric layer with a modified layer exhibited a mobility of 0.49 cm2/Vs, I on/Ioff ratio of 7.8 × 104, threshold voltage of - 1.2 V, sub-threshold swing of 0.3 V/dec, and operating voltage as low as - 4 V. The improvement of devices performance was owing to the good insulation capability, appropriate capacitance of dielectric layer, and preferable interface contact, smaller crystalline size of active layer.

Design considerations and emerging challenges for nanotube-, nanowire-, and negative capacitor-field effect transistors

NASA Astrophysics Data System (ADS)

Wahab, Md. Abdul

As the era of classical planar metal-oxide-semiconductor field-effect transistors (MOSFETs) comes to an end, the semiconductor industry is beginning to adopt 3D device architectures, such as FinFETs, starting at the 22 nm technology node. Since physical limits such as short channel effect (SCE) and self-heating may dominate, it may be difficult to scale Si FinFET below 10 nm. In this regard, transistors with different materials, geometries, or operating principles may help. For example, gate has excellent electrostatic control over 2D thin film channel with planar geometry, and 1D nanowire (NW) channel with gate-all-around (GAA) geometry to reduce SCE. High carrier mobility of single wall carbon nanotube (SWNT) or III-V channels may reduce VDD to reduce power consumption. Therefore, as channel of transistor, 2D thin film of array SWNTs and 1D III-V multi NWs are promising for sub 10 nm technology nodes. In this thesis, we analyze the potential of these transistors from process, performance, and reliability perspectives. For SWNT FETs, we discuss a set of challenges (such as how to (i) characterize diameter distribution, (ii) remove metallic (m)-SWNTs, and (iii) avoid electrostatic cross-talk among the neighboring SWNTs), and demonstrate solution strategies both theoretically and experimentally. Regarding self-heating in these new class of devices (SWNT FET and GAA NW FET including state-of-the-art FinFET), higher thermal resistance from poor thermal conducting oxides results significant temperature rise, and reduces the IC life-time. For GAA NW FETs, we discuss accurate self-heating evaluation with good spatial, temporal, and thermal resolutions. The introduction of negative capacitor (NC), as gate dielectric stack of transistor, allows sub 60 mV/dec operation to reduce power consumption significantly. Taken together, our work provides a comprehensive perspective regarding the challenges and opportunities of sub 10 nm technology nodes.

TiN/Al2O3/ZnO gate stack engineering for top-gate thin film transistors by combination of post oxidation and annealing

NASA Astrophysics Data System (ADS)

Kato, Kimihiko; Matsui, Hiroaki; Tabata, Hitoshi; Takenaka, Mitsuru; Takagi, Shinichi

2018-04-01

Control of fabrication processes for a gate stack structure with a ZnO thin channel layer and an Al2O3 gate insulator has been examined for enhancing the performance of a top-gate ZnO thin film transistor (TFT). The Al2O3/ZnO interface and the ZnO layer are defective just after the Al2O3 layer formation by atomic layer deposition. Post treatments such as plasma oxidation, annealing after the Al2O3 deposition, and gate metal formation (PMA) are promising to improve the interfacial and channel layer qualities drastically. Post-plasma oxidation effectively reduces the interfacial defect density and eliminates Fermi level pinning at the Al2O3/ZnO interface, which is essential for improving the cut-off of the drain current of TFTs. A thermal effect of post-Al2O3 deposition annealing at 350 °C can improve the crystalline quality of the ZnO layer, enhancing the mobility. On the other hand, impacts of post-Al2O3 deposition annealing and PMA need to be optimized because the annealing can also accompany the increase in the shallow-level defect density and the resulting electron concentration, in addition to the reduction in the deep-level defect density. The development of the interfacial control technique has realized the excellent TFT performance with a large ON/OFF ratio, steep subthreshold characteristics, and high field-effect mobility.

Low-voltage electric-double-layer paper transistors gated by microporous SiO2 processed at room temperature

NASA Astrophysics Data System (ADS)

Sun, Jia; Wan, Qing; Lu, Aixia; Jiang, Jie

2009-11-01

Battery drivable low-voltage SnO2-based paper thin-film transistors with a near-zero threshold voltage (Vth=0.06 V) gated by microporous SiO2 dielectric with electric-double-layer (EDL) effect are fabricated at room temperature. The operating voltage is found to be as low as 1.5 V due to the huge gate specific capacitance (1.34 μF/cm2 at 40 Hz) related to EDL formation. The subthreshold gate voltage swing and current on/off ratio is found to be 82 mV/decade and 2.0×105, respectively. The electron field-effect mobility is estimated to be 47.3 cm2/V s based on the measured gate specific capacitance at 40 Hz.

Low voltage operation of IGZO thin film transistors enabled by ultrathin Al2O3 gate dielectric

NASA Astrophysics Data System (ADS)

Ma, Pengfei; Du, Lulu; Wang, Yiming; Jiang, Ran; Xin, Qian; Li, Yuxiang; Song, Aimin

2018-01-01

An ultrathin, 5 nm, Al2O3 film grown by atomic-layer deposition was used as a gate dielectric for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The Al2O3 layer showed a low surface roughness of 0.15 nm, a low leakage current, and a high breakdown voltage of 6 V. In particular, a very high gate capacitance of 720 nF/cm2 was achieved, making it possible for the a-IGZO TFTs to not only operate at a low voltage of 1 V but also exhibit desirable properties including a low threshold voltage of 0.3 V, a small subthreshold swing of 100 mV/decade, and a high on/off current ratio of 1.2 × 107. Furthermore, even under an ultralow operation voltage of 0.6 V, well-behaved transistor characteristics were still observed with an on/off ratio as high as 3 × 106. The electron transport through the Al2O3 layer has also been analyzed, indicating the Fowler-Nordheim tunneling mechanism.

Nanoscale Multigate TiN Metal Nanocrystal Memory Using High-k Blocking Dielectric and High-Work-Function Gate Electrode Integrated on Silcon-on-Insulator Substrate

NASA Astrophysics Data System (ADS)

Lu, Chi-Pei; Luo, Cheng-Kei; Tsui, Bing-Yue; Lin, Cha-Hsin; Tzeng, Pei-Jer; Wang, Ching-Chiun; Tsai, Ming-Jinn

2009-04-01

In this study, a charge-trapping-layer-engineered nanoscale n-channel trigate TiN nanocrystal nonvolatile memory was successfully fabricated on silicon-on-insulator (SOI) wafer. An Al2O3 high-k blocking dielectric layer and a P+ polycrystalline silicon gate electrode were used to obtain low operation voltage and suppress the back-side injection effect, respectively. TiN nanocrystals were formed by annealing TiN/Al2O3 nanolaminates deposited by an atomic layer deposition system. The memory characteristics of various samples with different TiN wetting layer thicknesses, post-deposition annealing times, and blocking oxide thicknesses were also investigated. The sample with a thicker wetting layer exhibited a much larger memory window than other samples owing to its larger nanocrystal size. Good retention with a mere 12% charge loss for up to 10 years and high endurance were also obtained. Furthermore, gate disturbance and read disturbance were measured with very small charge migrations after a 103 s stressing bias.

Adhesion enhancement methods for a roll-to-sheet fabrication process of DE stack-transducers and their influences on the electric properties

NASA Astrophysics Data System (ADS)

Bochmann, Helge; von Heckel, Benedikt; Maas, Jürgen

2017-04-01

Transducers made of dielectric elastomers (DE) offer versatile opportunities for many different applications. To gain large strains and forces a multilayer topology is commonly used. DE stack-transducers represent one multilayer topology and can be operated as a sensor, a generator or an actuator simultaneously. They are made of many layers of DE films, like silicone (PDMS) and polyurethane (PUR), stacked on top of each other. The single layers are several micrometers thin and coated with a compliant electrode on both sides. Depending on the application a DE transducer has to withstand tensile forces, which may lead to a delamination of the layers and a ripping of the stack-transducer. This can be prevented by enhancing the adhesion among the layers. Within this contribution a surface plasma jet treatment with an atmospheric plasma beam as well as an adhesive utilized as electrode material was investigated to obtain an adhesion enhancement. The effects of these methods to enhance the adhesion are introduced briefly. Furthermore, various investigations were made to determine the benefits of the enhancement methods with respect to the electromechanical properties of the electrode. Therefore, certain tests regarding the surface resistance of the electrode and the dielectric breakdown strength (DBS) of the DE film were conducted. The tests indicate that the influences are strongly dependent on the composition of the electrode and the used DE material. Finally, improvements for a dry deposition roll-to-sheet manufacturing process for DE stack-transducers are derived from the obtained results.

Visible and infrared optical properties of stacked cone graphite microtubes.

PubMed

Bruce, Charles W; Alyones, Sharhabeel

2012-06-01

The absorptive and scattering optical properties of heat-treated, vapor-grown, graphite microtubes consisting of nanotubes in a "stacked cone" configuration were investigated through the visible and infrared wavelengths using photoacoustic and other spectrometric techniques. However, computations of these properties involved uncertainties that were not easily resolved; the appropriate dielectric coefficients were presumed to be a combination of the published values for the distinct orientations of graphite, but the correct proportions are not evident and none of the reasonable choices produced satisfactory agreement (within the measurement limits of error). Since both of the primary components of the extinction were measured, the appropriate computational codes were employed in reverse to compute the dielectric coefficients for the graphite microtubes. Differences, primarily for the imaginary index, are most distinct for visible and near infrared wavelengths; in this wavelength region, the imaginary index falls progressively to less than half that for the computed mixture.

A small biomimetic quadruped robot driven by multistacked dielectric elastomer actuators

NASA Astrophysics Data System (ADS)

Nguyen, Canh Toan; Phung, Hoa; Dat Nguyen, Tien; Lee, Choonghan; Kim, Uikyum; Lee, Donghyouk; Moon, Hyungpil; Koo, Jachoon; Nam, Jae-do; Ryeol Choi, Hyouk

2014-06-01

A kind of dielectric elastomer (DE) material, called ‘synthetic elastomer’, has been developed based on acrylonitrile butadiene rubber (NBR) to be used as a dielectric elastomer actuator (DEA). By stacking single layers of synthetic elastomer, a linear actuator, called a multistacked actuator, is produced, and used by mechatronic and robotic systems to generate linear motion. In this paper, we demonstrate the application of the multistacked dielectric elastomer actuator in a biomimetic legged robot. A miniature robot driven by a biomimetic actuation system with four 2-DOF (two-degree-of-freedom) legged mechanisms is realized. Based on the experimental results, we evaluate the performance of the proposed robot and validate the feasibility of the multistacked actuator in a locomotion system as a replacement for conventional actuators.

Dielectric properties of graphene/MoS2 heterostructures from ab initio calculations and electron energy-loss experiments

NASA Astrophysics Data System (ADS)

Mohn, Michael J.; Hambach, Ralf; Wachsmuth, Philipp; Giorgetti, Christine; Kaiser, Ute

2018-06-01

High-energy electronic excitations of graphene and MoS2 heterostructures are investigated by momentum-resolved electron energy-loss spectroscopy in the range of 1 to 35 eV. The interplay of excitations on different sheets is understood in terms of long-range Coulomb interactions and is simulated using a combination of ab initio and dielectric model calculations. In particular, the layered electron-gas model is extended to thick layers by including the spatial dependence of the dielectric response in the direction perpendicular to the sheets. We apply this model to the case of graphene/MoS2/graphene heterostructures and discuss the possibility of extracting the dielectric properties of an encapsulated monolayer from measurements of the entire stack.

Efficient III-Nitride MIS-HEMT devices with high-κ gate dielectric for high-power switching boost converter circuits

NASA Astrophysics Data System (ADS)

Mohanbabu, A.; Mohankumar, N.; Godwin Raj, D.; Sarkar, Partha; Saha, Samar K.

2017-03-01

The paper reports the results of a systematic theoretical study on efficient recessed-gate, double-heterostructure, and normally-OFF metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs), HfAlOx/AlGaN on Al2O3 substrate. In device architecture, a thin AlGaN layer is used in the AlGaN graded barrier MIS-HEMTs that offers an excellent enhancement-mode device operation with threshold voltage higher than 5.3 V and drain current above 0.64 A/mm along with high on-current/off-current ratio over 107 and subthreshold slope less than 73 mV/dec. In addition, a high OFF-state breakdown voltage of 1200 V is achieved for a device with a gate-to-drain distance and field-plate length of 15 μm and 5.3 μm, respectively at a drain current of 1 mA/mm with a zero gate bias, and the substrate grounded. The numerical device simulation results show that in comparison to a conventional AlGaN/GaN MIS-HEMT of similar design, a graded barrier MIS-HEMT device exhibits a better interface property, remarkable suppression of leakage current, and a significant improvement of breakdown voltage for HfAlOx gate dielectric. Finally, the benefit of HfAlOx graded-barrier AlGaN MIS-HEMTs based switching devices is evaluated on an ultra-low-loss converter circuit.

High-mobility low-temperature ZnO transistors with low-voltage operation

NASA Astrophysics Data System (ADS)

Bong, Hyojin; Lee, Wi Hyoung; Lee, Dong Yun; Kim, Beom Joon; Cho, Jeong Ho; Cho, Kilwon

2010-05-01

Low voltage high mobility n-type thin film transistors (TFTs) based on sol-gel processed zinc oxide (ZnO) were fabricated using a high capacitance ion gel gate dielectric. The ion gel gated solution-processed ZnO TFTs were found to exhibit excellent electrical properties. TFT carrier mobilities were 13 cm2/V s, ON/OFF current ratios were 105, regardless of the sintering temperature used for the preparation of the ZnO thin films. Ion gel gated ZnO TFTs are successfully demonstrated on plastic substrates for the large area flexible electronics.

Design and characterization of terahertz-absorbing nano-laminates of dielectric and metal thin films.

PubMed

Bolakis, C; Grbovic, D; Lavrik, N V; Karunasiri, G

2010-07-05

A terahertz-absorbing thin-film stack, containing a dielectric Bragg reflector and a thin chromium metal film, was fabricated on a silicon substrate for applications in bi-material terahertz (THz) sensors. The Bragg reflector is to be used for optical readout of sensor deformation under THz illumination. The THz absorption characteristics of the thin-film composite were measured using Fourier transform infrared spectroscopy. The absorption of the structure was calculated both analytically and by finite element modeling and the two approaches agreed well. Finite element modeling provides a convenient way to extract the amount of power dissipation in each layer and is used to quantify the THz absorption in the multi-layer stack. The calculation and the model were verified by experimentally characterizing the multi-layer stack in the 3-5 THz range. The measured and simulated absorption characteristics show a reasonably good agreement. It was found that the composite film absorbed about 20% of the incident THz power. The model was used to optimize the thickness of the chromium film for achieving high THz absorption and found that about 50% absorption can be achieved when film thickness is around 9 nm.

III-V/Ge MOS device technologies for low power integrated systems

NASA Astrophysics Data System (ADS)

Takagi, S.; Noguchi, M.; Kim, M.; Kim, S.-H.; Chang, C.-Y.; Yokoyama, M.; Nishi, K.; Zhang, R.; Ke, M.; Takenaka, M.

2016-11-01

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. The plasma post oxidation to form GeOx interfacial layers is a key gate stack technology for Ge CMOS. Also, direct wafer bonding of ultrathin body quantum well III-V-OI channels, combined with Tri-gate structures, realizes high performance III-V n-MOSFETs on Si. We also demonstrate planar-type InGaAs and Ge/strained SOI TFETs. The defect-less p+-n source junction formation with steep impurity profiles is a key for high performance TFET operation.

Analysis of high-k spacer on symmetric underlap DG-MOSFET with Gate Stack architecture

NASA Astrophysics Data System (ADS)

Das, Rahul; Chakraborty, Shramana; Dasgupta, Arpan; Dutta, Arka; Kundu, Atanu; Sarkar, Chandan K.

2016-09-01

This paper shows the systematic study of underlap double gate (U-DG) NMOSFETs with Gate Stack (GS) under the influence of high-k spacers. In highly scaled devices, underlap is used at the Source and Drain side so as to reduce the short channel effects (SCE's), however, it significantly reduces the on current due to the increased channel resistance. To overcome these drawbacks, the use of high-k spacers is projected as one of the remedies. In this paper, the analog performance of the devices is studied on the basis of parameters like transconductance (gm), transconductance generation factor (gm/Id) and intrinsic gain (gmro). The RF performance is analyzed on the merits of intrinsic capacitance (Cgd, Cgs), resistance (Rgd, Rgs), transport delay (τm), inductance (Lsd), cutoff frequency (fT), and the maximum frequency of oscillation (fmax). The circuit performance of the devices are studied by implementing the device as the driver MOSFET in a Single Stage Common Source Amplifier. The Gain Bandwidth Product (GBW) has been analyzed from the frequency response of the circuit.

Fabrication of arrayed Si nanowire-based nano-floating gate memory devices on flexible plastics.

PubMed

Yoon, Changjoon; Jeon, Youngin; Yun, Junggwon; Kim, Sangsig

2012-01-01

Arrayed Si nanowire (NW)-based nano-floating gate memory (NFGM) devices with Pt nanoparticles (NPs) embedded in Al2O3 gate layers are successfully constructed on flexible plastics by top-down approaches. Ten arrayed Si NW-based NFGM devices are positioned on the first level. Cross-linked poly-4-vinylphenol (PVP) layers are spin-coated on them as isolation layers between the first and second level, and another ten devices are stacked on the cross-linked PVP isolation layers. The electrical characteristics of the representative Si NW-based NFGM devices on the first and second levels exhibit threshold voltage shifts, indicating the trapping and detrapping of electrons in their NPs nodes. They have an average threshold voltage shift of 2.5 V with good retention times of more than 5 x 10(4) s. Moreover, most of the devices successfully retain their electrical characteristics after about one thousand bending cycles. These well-arrayed and stacked Si NW-based NFGM devices demonstrate the potential of nanowire-based devices for large-scale integration.

Wideband analytical equivalent circuit for one-dimensional periodic stacked arrays.

PubMed

Molero, Carlos; Rodríguez-Berral, Raúl; Mesa, Francisco; Medina, Francisco; Yakovlev, Alexander B

2016-01-01

A wideband equivalent circuit is proposed for the accurate analysis of scattering from a set of stacked slit gratings illuminated by a plane wave with transverse magnetic or electric polarization that impinges normally or obliquely along one of the principal planes of the structure. The slit gratings are printed on dielectric slabs of arbitrary thickness, including the case of closely spaced gratings that interact by higher-order modes. A Π-circuit topology is obtained for a pair of coupled arrays, with fully analytical expressions for all the circuit elements. This equivalent Π circuit is employed as the basis to derive the equivalent circuit of finite stacks with any given number of gratings. Analytical expressions for the Brillouin diagram and the Bloch impedance are also obtained for infinite periodic stacks.

Ferroelectric memory based on molybdenum disulfide and ferroelectric hafnium oxide

NASA Astrophysics Data System (ADS)

Yap, Wui Chung; Jiang, Hao; Xia, Qiangfei; Zhu, Wenjuan

Recently, ferroelectric hafnium oxide (HfO2) was discovered as a new type of ferroelectric material with the advantages of high coercive field, excellent scalability (down to 2.5 nm), and good compatibility with CMOS processing. In this work, we demonstrate, for the first time, 2D ferroelectric memories with molybdenum disulfide (MoS2) as the channel material and aluminum doped HfO2 as the ferroelectric gate dielectric. A 16 nm thick layer of HfO2, doped with 5.26% aluminum, was deposited via atomic layer deposition (ALD), then subjected to rapid thermal annealing (RTA) at 1000 °C, and the polarization-voltage characteristics of the resulting metal-ferroelectric-metal (MFM) capacitors were measured, showing a remnant polarization of 0.6 μC/cm2. Ferroelectric memories with embedded ferroelectric hafnium oxide stacks and monolayer MoS2 were fabricated. The transfer characteristics after program and erase pulses revealed a clear ferroelectric memory window. In addition, endurance (up to 10,000 cycles) of the devices were tested and effects associated with ferroelectric materials, such as the wake-up effect and polarization fatigue, were observed. This research can potentially lead to advances of 2D materials in low-power logic and memory applications.

Heterojunction fully depleted SOI-TFET with oxide/source overlap

NASA Astrophysics Data System (ADS)

Chander, Sweta; Bhowmick, B.; Baishya, S.

2015-10-01

In this work, a hetero-junction fully depleted (FD) Silicon-on-Insulator (SOI) Tunnel Field Effect Transistor (TFET) nanostructure with oxide overlap on the Germanium-source region is proposed. Investigations using Synopsys Technology Computer Aided Design (TCAD) simulation tools reveal that the simple oxide overlap on the Germanium-source region increases the tunneling area as well as the tunneling current without degrading the band-to-band tunneling (BTBT) and improves the device performance. More importantly, the improvement is independent of gate overlap. Simulation study shows improvement in ON current, subthreshold swing (SS), OFF current, ION/IOFF ration, threshold voltage and transconductance. The proposed device with hafnium oxide (HfO2)/Aluminium Nitride (AlN) stack dielectric material offers an average subthreshold swing of 22 mV/decade and high ION/IOFF ratio (∼1010) at VDS = 0.4 V. Compared to conventional TFET, the Miller capacitance of the device shows the enhanced performance. The impact of the drain voltage variation on different parameters such as threshold voltage, subthreshold swing, transconductance, and ION/IOFF ration are also found to be satisfactory. From fabrication point of view also it is easy to utilize the existing CMOS process flows to fabricate the proposed device.

Study of Direct-Contact HfO2/Si Interfaces

PubMed Central

Miyata, Noriyuki

2012-01-01

Controlling monolayer Si oxide at the HfO2/Si interface is a challenging issue in scaling the equivalent oxide thickness of HfO2/Si gate stack structures. A concept that the author proposes to control the Si oxide interface by using ultra-high vacuum electron-beam HfO2 deposition is described in this review paper, which enables the so-called direct-contact HfO2/Si structures to be prepared. The electrical characteristics of the HfO2/Si metal-oxide-semiconductor capacitors are reviewed, which suggest a sufficiently low interface state density for the operation of metal-oxide-semiconductor field-effect-transistors (MOSFETs) but reveal the formation of an unexpected strong interface dipole. Kelvin probe measurements of the HfO2/Si structures provide obvious evidence for the formation of dipoles at the HfO2/Si interfaces. The author proposes that one-monolayer Si-O bonds at the HfO2/Si interface naturally lead to a large potential difference, mainly due to the large dielectric constant of the HfO2. Dipole scattering is demonstrated to not be a major concern in the channel mobility of MOSFETs. PMID:28817060

X-ray measurements of the strain and shape of dielectric/metallic wrap-gated InAs nanowires

NASA Astrophysics Data System (ADS)

Eymery, J.; Favre-Nicolin, V.; Fröberg, L.; Samuelson, L.

2009-03-01

Wrap-gate (111) InAs nanowires (NWs) were studied after HfO2 dielectric coating and Cr metallic deposition by a combination of grazing incidence x-ray techniques. In-plane and out-of-plane x-ray diffraction (crystal truncation rod analysis) allow determining the strain tensor. The longitudinal contraction, increasing with HfO2 and Cr deposition, is significantly larger than the radial dilatation. For the Cr coating, the contraction along the growth axis is quite large (-0.95%), and the longitudinal/radial deformation ratio is >10, which may play a role on the NW transport properties. Small angle x-ray scattering shows a smoothening of the initial hexagonal bare InAs NW shape and gives the respective core/shell thicknesses, which are compared to flat surface values.

Electrical properties of solution processed highly transparent ZnO TFT with organic gate dielectric

NASA Astrophysics Data System (ADS)

Pandya, Nirav C.; Joshi, Nikhil G.; Trivedi, U. N.; Joshi, U. S.

2013-02-01

All oxide thin film transistors (TFT) with zinc oxide active layer were fabricated by chemical solution deposition (CSD) using aqueous solutions on glass substrate. Thin film transistors (TFTs) with amorphous zinc oxide as channel layers and poly-vinyl alcohol as dielectric layers were fabricated at low temperatures by chemical solution deposition (CSD). Atomic force microscopy (AFM) confirmed nano grain size with fairly smooth surface topography. Very small leakage currents were achieved in the transfer curves, while soft saturation was observed in the output current voltage (I-V) characteristics of the device. Optical transmission of better than 87% in the visible region was estimated, which is better than the organic gate insulator based ZnO TFTs reported so far. Our results offer lot of promise to TFT based display and optoelectronics.

An Al₂O₃ Gating Substrate for the Greater Performance of Field Effect Transistors Based on Two-Dimensional Materials.

PubMed

Yang, Hang; Qin, Shiqiao; Zheng, Xiaoming; Wang, Guang; Tan, Yuan; Peng, Gang; Zhang, Xueao

2017-09-22

We fabricated 70 nm Al₂O₃ gated field effect transistors based on two-dimensional (2D) materials and characterized their optical and electrical properties. Studies show that the optical contrast of monolayer graphene on an Al₂O₃/Si substrate is superior to that on a traditional 300 nm SiO₂/Si substrate (2.4 times). Significantly, the transconductance of monolayer graphene transistors on the Al₂O₃/Si substrate shows an approximately 10-fold increase, due to a smaller dielectric thickness and a higher dielectric constant. Furthermore, this substrate is also suitable for other 2D materials, such as WS₂, and can enhance the transconductance remarkably by 61.3 times. These results demonstrate a new and ideal substrate for the fabrication of 2D materials-based electronic logic devices.

High performance p-type organic thin film transistors with an intrinsically photopatternable, ultrathin polymer dielectric layer☆

PubMed Central

Petritz, Andreas; Wolfberger, Archim; Fian, Alexander; Krenn, Joachim R.; Griesser, Thomas; Stadlober, Barbara

2013-01-01

A high-performing bottom-gate top-contact pentacene-based oTFT technology with an ultrathin (25–48 nm) and electrically dense photopatternable polymeric gate dielectric layer is reported. The photosensitive polymer poly((±)endo,exo-bicyclo[2.2.1]hept-5-ene-2,3-dicarboxylic acid, diphenylester) (PNDPE) is patterned directly by UV-exposure (λ = 254 nm) at a dose typical for conventionally used negative photoresists without the need for any additional photoinitiator. The polymer itself undergoes a photo-Fries rearrangement reaction under UV illumination, which is accompanied by a selective cross-linking of the macromolecules, leading to a change in solubility in organic solvents. This crosslinking reaction and the negative photoresist behavior are investigated by means of sol–gel analysis. The resulting transistors show a field-effect mobility up to 0.8 cm2 V−1 s−1 at an operation voltage as low as −4.5 V. The ultra-low subthreshold swing in the order of 0.1 V dec−1 as well as the completely hysteresis-free transistor characteristics are indicating a very low interface trap density. It can be shown that the device performance is completely stable upon UV-irradiation and development according to a very robust chemical rearrangement. The excellent interface properties, the high stability and the small thickness make the PNDPE gate dielectric a promising candidate for fast organic electronic circuits. PMID:24748853

Heterointegration of Dissimilar Materials

DTIC Science & Technology

2015-07-28

computing capabilities. This has been possible due to the aggressive scaling undertaken by the Si industry for complementary metal oxide semiconductor...current due to quantum mechanical tunneling. After years of research and development, Hf- based gate dielectric with metal gates is now being used in CMOS...the oxide in this study was 1ML or ~3.9 Å/ min. The native SiO2 was removed using a low temperature process involving the deposition of Sr metal

Dielectric anomaly and relaxation natures in a Zn-Cr pillar−layered metal−organic framework with cages and channels

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xue, Chen; Yao, Zhi-Yuan; Liu, Shao-Xian

A bimetallic metal–organic framework (MOF) with the formula [Zn{sub 3}btc{sub 2}(Cr{sub 3}O(isonic){sub 6}(H{sub 2}O){sub 2}(OH))]·(DMF){sub 15.5}(H{sub 2}O){sub 8} (H{sub 3}btc=1,3,5-benzenetricarboxylic acid; isonic=isonicotinicate) shows a pillar-layered structure. The monolayer consists of hexagon-like rings formed by the [Zn(isonic){sub 2}(btc){sub 2}] tetrahedral and the consecutive monolayers are pillared by trigonal–prismatic clusters of [Cr{sub 3}O(isonic){sub 6}(H{sub 2}O){sub 2}(OH)]through the remaining binding sites of the Zn{sup 2+} ions. DMF and water molecules are confined in the cages and channels. TGA indicates that the lattice DMF and water molecules begin to be released at temperatures above 363 K. Dielectric measurements were carried out in the rangemore » of 173–363 K and 1–10{sup 7} Hz for three successive thermal cycles. The dielectric spectroscopy obtained in the first thermal cycle was different from that observed in the next two thermal cycles, while the dielectric spectra in the last two thermal cycles were almost identical. The dielectric nature of this MOF is discussed in detail for each thermal cycle. Since MOFs are unique host–guest systems in which the structure of the host framework is designable and the guests are exchangeable, it is no doubt those MOFs are materials with a variety of dielectric natures. This study gives a fresh impetus to achieve MOFs–based dielectric materials. - Graphical abstract: The bimetallic MOF [Zn{sub 3}btc{sub 2}(Cr{sub 3}O(isonic){sub 6}(H{sub 2}O){sub 2}(OH))]·(DMF){sub 15.5}(H{sub 2}O){sub 8}1, shows a pillar-layered open-framework structure. The dielectric spectra of 1 are almost identical in the last two thermal cycles, whereas significantly different from that observed in the first thermal cycle. The novel dielectric anomaly associated with a stacked structure transformation of the disordered guests. - Highlights: • A bimetallic metal-organic framework shows a pillar-layered structure. • The MOF displays novel dielectric anomaly and relaxation behaviors. • The dielectric anomaly arises from the stacking structure transformation of guests. • The dielectric relaxation is related to the dipole dynamics of guests.« less

SU-E-T-512: Electromagnetic Simulations of the Dielectric Wall Accelerator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Uselmann, A; Mackie, T

Purpose: To characterize and parametrically study the key components of a dielectric wall accelerator through electromagnetic modeling and particle tracking. Methods: Electromagnetic and particle tracking simulations were performed using a commercial code (CST Microwave Studio, CST Inc.) utilizing the finite integration technique. A dielectric wall accelerator consists of a series of stacked transmission lines sequentially fired in synchrony with an ion pulse. Numerous properties of the stacked transmission lines, including geometric, material, and electronic properties, were analyzed and varied in order to assess their impact on the transverse and axial electric fields. Additionally, stacks of transmission lines were simulated inmore » order to quantify the parasitic effect observed in closely packed lines. Particle tracking simulations using the particle-in-cell method were performed on the various stacks to determine the impact of the above properties on the resultant phase space of the ions. Results: Examination of the simulation results show that novel geometries can shape the accelerating pulse in order to reduce the energy spread and increase the average energy of accelerated ions. Parasitic effects were quantified for various geometries and found to vary with distance from the end of the transmission line and along the beam axis. An optimal arrival time of an ion pulse relative to the triggering of the transmission lines for a given geometry was determined through parametric study. Benchmark simulations of single transmission lines agree well with published experimental results. Conclusion: This work characterized the behavior of the transmission lines used in a dielectric wall accelerator and used this information to improve them in novel ways. Utilizing novel geometries, we were able to improve the accelerating gradient and phase space of the accelerated particle bunch. Through simulation, we were able to discover and optimize design issues with the device at low cost. Funding: Morgridge Institute for Research, Madison WI; Conflict of Interest: Dr. Mackie is an investor and board member at CPAC, a company developing compact accelerator designs similar to those discussed in this work, but designs discussed are not directed by CPAC. Funding: Morgridge Institute for Research, Madison WI; Conflict of Interest: Dr. Mackie is an investor and board member at CPAC, a company developing compact accelerator designs similar to those discussed in this work, but designs discussed are not directed by CPAC.« less

Fabrication of Ta2O5/GeNx gate insulator stack for Ge metal-insulator-semiconductor structures by electron-cyclotron-resonance plasma nitridation and sputtering deposition techniques

NASA Astrophysics Data System (ADS)

Otani, Yohei; Itayama, Yasuhiro; Tanaka, Takuo; Fukuda, Yukio; Toyota, Hiroshi; Ono, Toshiro; Mitsui, Minoru; Nakagawa, Kiyokazu

2007-04-01

The authors have fabricated germanium (Ge) metal-insulator-semiconductor (MIS) structures with a 7-nm-thick tantalum pentaoxide (Ta2O5)/2-nm-thick germanium nitride (GeNx) gate insulator stack by electron-cyclotron-resonance plasma nitridation and sputtering deposition. They found that pure GeNx ultrathin layers can be formed by the direct plasma nitridation of the Ge surface without substrate heating. X-ray photoelectron spectroscopy revealed no oxidation of the GeNx layer after the Ta2O5 sputtering deposition. The fabricated MIS capacitor with a capacitance equivalent thickness of 4.3nm showed excellent leakage current characteristics. The interface trap density obtained by the modified conductance method was 4×1011cm-2eV-1 at the midgap.

Investigation of sensing mechanism and signal amplification in carbon nanotube based microfluidic liquid-gated transistors via pulsating gate bias.

PubMed

Wijaya, I Putu Mahendra; Nie, Tey Ju; Rodriguez, Isabel; Mhaisalkar, Subodh G

2010-06-07

The advent of a carbon nanotube liquid-gated transistor (LGFET) for biosensing applications allows the possibility of real-time and label-free detection of biomolecular interactions. The use of an aqueous solution as dielectric, however, has traditionally restricted the operating gate bias (VG) within |VG| < 1 V, due to the electrolysis of water. Here, we propose pulsed-gating as a facile method to extend the operation window of LGFETs to |VG| > 1 V. A comparison between simulation and experimental results reveals that at voltages in excess of 1 V, the LGFET sensing mechanism has a contribution from two factors: electrostatic gating as well as capacitance modulation. Furthermore, the large IDS drop observed in the |VG| > 1 V region indicates that pulsed-gating may be readily employed as a simple method to amplify the signal in the LGFET and pushes the detection limit down to attomolar concentration levels, an order of magnitude improvement over conventionally employed DC VG biasing.

Influence of gate recess on the electronic characteristics of β-Ga2O3 MOSFETs

NASA Astrophysics Data System (ADS)

Lv, Yuanjie; Mo, Jianghui; Song, Xubo; He, Zezhao; Wang, Yuangang; Tan, Xin; Zhou, Xingye; Gu, Guodong; Guo, Hongyu; Feng, Zhihong

2018-05-01

Gallium oxide (Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with gate recess depths of 110 nm and 220 nm, respectively. The gate recess was formed by dry plasma etching with Cr metal as the mask. The fabricated devices with a 25-nm HfO2 gate dielectric both showed a low off-state drain current of about 1.8 × 10-10 A/mm. The effects of recess depth on the electronic characteristics of Ga2O3 MOSFETs were investigated. Upon increasing the recess depth from 110 nm to 220 nm, the saturated drain current decreased from 20.7 mA/mm to 2.6 mA/mm, while the threshold voltage moved increased to +3 V. Moreover, the breakdown voltage increased from 122 V to 190 V. This is mainly because the inverted-trapezoidal gate played the role of a gate-field plate, which suppressed the peak electric field close to the gate.

Nanocrystal floating gate memory with solution-processed indium-zinc-tin-oxide channel and colloidal silver nanocrystals

NASA Astrophysics Data System (ADS)

Hu, Quanli; Ha, Sang-Hyub; Lee, Hyun Ho; Yoon, Tae-Sik

2011-12-01

A nanocrystal (NC) floating gate memory with solution-processed indium-zinc-tin-oxide (IZTO) channel and silver (Ag) NCs embedded in thin gate dielectric layer (SiO2(30 nm)/Al2O3(3 nm)) was fabricated. Both the IZTO channel and colloidal Ag NC layers were prepared by spin-coating and subsequent annealing, and dip-coating process, respectively. A threshold voltage shift up to ~0.9 V, corresponding to the electron density of 6.5 × 1011 cm-2, at gate pulsing <=10 V was achieved by the charging of high density NCs. These results present the successful non-volatile memory characteristics of an oxide-semiconductor transistor fabricated through solution processes.

Solution-processed nanoparticle super-float-gated organic field-effect transistor as un-cooled ultraviolet and infrared photon counter.

PubMed

Yuan, Yongbo; Dong, Qingfeng; Yang, Bin; Guo, Fawen; Zhang, Qi; Han, Ming; Huang, Jinsong

2013-01-01

High sensitivity photodetectors in ultraviolet (UV) and infrared (IR) range have broad civilian and military applications. Here we report on an un-cooled solution-processed UV-IR photon counter based on modified organic field-effect transistors. This type of UV detectors have light absorbing zinc oxide nanoparticles (NPs) sandwiched between two gate dielectric layers as a floating gate. The photon-generated charges on the floating gate cause high resistance regions in the transistor channel and tune the source-drain output current. This "super-float-gating" mechanism enables very high sensitivity photodetectors with a minimum detectable ultraviolet light intensity of 2.6 photons/μm(2)s at room temperature as well as photon counting capability. Based on same mechansim, infrared photodetectors with lead sulfide NPs as light absorbing materials have also been demonstrated.

Surface Modification of Solution-Processed ZrO2 Films through Double Coating for Pentacene Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Kwon, Jin-Hyuk; Bae, Jin-Hyuk; Lee, Hyeonju; Park, Jaehoon

2018-03-01

We report the modification of surface properties of solution-processed zirconium oxide (ZrO2) dielectric films achieved by using double-coating process. It is proven that the surface properties of the ZrO2 film are modified through the double-coating process; the surface roughness decreases and the surface energy increases. The present surface modification of the ZrO2 film contributes to an increase in grain size of the pentacene film, thereby increasing the field-effect mobility and decreasing the threshold voltage of the pentacene thin-film transistors (TFTs) having the ZrO2 gate dielectric. Herein, the molecular orientation of pentacene film is also studied based on the results of contact angle and X-ray diffraction measurements. Pentacene molecules on the double-coated ZrO2 film are found to be more tilted than those on the single-coated ZrO2 film, which is attributed to the surface modification of the ZrO2 film. However, no significant differences are observed in insulating properties between the single-and the double-coated ZrO2 dielectric films. Consequently, the characteristic improvements of the pentacene TFTs with the double-coated ZrO2 gate dielectric film can be understood through the increase in pentacene grain size and the reduction in grain boundary density.

Direct growth of graphene-dielectric bi-layer structure on device substrates from Si-based polymer

NASA Astrophysics Data System (ADS)

Seo, Hong-Kyu; Kim, Kyunghun; Min, Sung-Yong; Lee, Yeongjun; Eon Park, Chan; Raj, Rishi; Lee, Tae-Woo

2017-06-01

To facilitate the utilization of graphene films in conventional semiconducting devices (e.g. transistors and memories) which includes an insulating layer such as gate dielectric, facile synthesis of bi-layers composed of a graphene film and an insulating layer by one-step thermal conversion will be very important. We demonstrate a simple, inexpensive, scalable and patternable process to synthesize graphene-dielectric bi-layer films from solution-processed polydimethylsiloxane (PDMS) under a Ni capping layer. This method fabricates graphene-dielectric bi-layer structure simultaneously directly on substrate by thermal conversion of PDMS without using additional graphene transfer and patterning process or formation of an expensive dielectric layer, which makes the device fabrication process much easier. The graphene-dielectric bi-layer on a conducting substrate was used in bottom-contact pentacene field-effect transistors that showed ohmic contact and small hysteresis. Our new method will provide a way to fabricate flexible electronic devices simply and inexpensively.

Designing graphene absorption in a multispectral plasmon-enhanced infrared detector

DOE PAGES

Goldflam, Michael D.; Fei, Zhe; Ruiz, Isaac; ...

2017-05-18

Here, we have examined graphene absorption in a range of graphene-based infrared devices that combine either monolayer or bilayer graphene with three different gate dielectrics. Electromagnetic simulations show that the optical absorption in graphene in these devices, an important factor in a functional graphene-based detector, is strongly dielectric-dependent. Our simulations reveal that plasmonic excitation in graphene can significantly influence the percentage of light absorbed in the entire device, as well as the graphene layer itself, with graphene absorption exceeding 25% in regions where plasmonic excitation occurs. Notably, the dielectric environment of graphene has a dramatic influence on the strength andmore » wavelength range over which the plasmons can be excited, making dielectric choice paramount to final detector tunability and sensitivity.« less

Hysteresis in Lanthanide Aluminum Oxides Observed by Fast Pulse CV Measurement

PubMed Central

Zhao, Chun; Zhao, Ce Zhou; Lu, Qifeng; Yan, Xiaoyi; Taylor, Stephen; Chalker, Paul R.

2014-01-01

Oxide materials with large dielectric constants (so-called high-k dielectrics) have attracted much attention due to their potential use as gate dielectrics in Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). A novel characterization (pulse capacitance-voltage) method was proposed in detail. The pulse capacitance-voltage technique was employed to characterize oxide traps of high-k dielectrics based on the Metal Oxide Semiconductor (MOS) capacitor structure. The variation of flat-band voltages of the MOS structure was observed and discussed accordingly. Some interesting trapping/detrapping results related to the lanthanide aluminum oxide traps were identified for possible application in Flash memory technology. After understanding the trapping/detrapping mechanism of the high-k oxides, a solid foundation was prepared for further exploration into charge-trapping non-volatile memory in the future. PMID:28788225

High-mobility and low-operating voltage organic thin film transistor with epoxy based siloxane binder as the gate dielectric

NASA Astrophysics Data System (ADS)

Tewari, Amit; Gandla, Srinivas; Pininti, Anil Reddy; Karuppasamy, K.; Böhm, Siva; Bhattacharyya, Arup R.; McNeill, Christopher R.; Gupta, Dipti

2015-09-01

This paper reports the fabrication of pentacene-based organic thin-film transistors using a dielectric material, Dynasylan ®SIVO110. The devices exhibit excellent performance characterized by a low threshold voltage of -1.4 V (operating voltage: 0 to -4 V) together with a mobility of 1.9 cm2 V-1s-1. These results are promising because it uses only a single layer of dielectric without performing any intermediate treatment. The reason is attributed to the high charge storage capacity of the dielectric (κ ˜ 20.02), a low interfacial trap density (2.56 × 1011cm-2), and favorable pentacene film morphology consisting of large and interconnected grains having an average size of 234 nm.

Designing graphene absorption in a multispectral plasmon-enhanced infrared detector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Goldflam, Michael D.; Fei, Zhe; Ruiz, Isaac

Here, we have examined graphene absorption in a range of graphene-based infrared devices that combine either monolayer or bilayer graphene with three different gate dielectrics. Electromagnetic simulations show that the optical absorption in graphene in these devices, an important factor in a functional graphene-based detector, is strongly dielectric-dependent. Our simulations reveal that plasmonic excitation in graphene can significantly influence the percentage of light absorbed in the entire device, as well as the graphene layer itself, with graphene absorption exceeding 25% in regions where plasmonic excitation occurs. Notably, the dielectric environment of graphene has a dramatic influence on the strength andmore » wavelength range over which the plasmons can be excited, making dielectric choice paramount to final detector tunability and sensitivity.« less

Radiation-Tolerant Intelligent Memory Stack - RTIMS

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong; Herath, Jeffrey A.

2011-01-01

This innovation provides reconfigurable circuitry and 2-Gb of error-corrected or 1-Gb of triple-redundant digital memory in a small package. RTIMS uses circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field-programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuits are stacked into a module of 42.7 42.7 13 mm. Triple module redundancy, current limiting, configuration scrubbing, and single- event function interrupt detection are employed to mitigate radiation effects. The novel self-scrubbing and single event functional interrupt (SEFI) detection allows a relatively soft FPGA to become radiation tolerant without external scrubbing and monitoring hardware

Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors

NASA Astrophysics Data System (ADS)

Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

2016-04-01

In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade-1 and 3.62 × 1011 eV-1 cm-2, respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

Structured organic materials and devices using low-energy particle beams

DOEpatents

Vardeny, Z. Valy; Li, Sergey; Delong, Matthew C.; Jiang, Xiaomei

2005-09-13

Organic materials exposed to an electron beam for patterning a substrate (1) to make an optoelectronic organic device which includes a source, a drain, gate dielectric layer (4), and a substrate for emitting light.

DNA and RNA sequencing by nanoscale reading through programmable electrophoresis and nanoelectrode-gated tunneling and dielectric detection

DOEpatents

Lee, James W.; Thundat, Thomas G.

2005-06-14

An apparatus and method for performing nucleic acid (DNA and/or RNA) sequencing on a single molecule. The genetic sequence information is obtained by probing through a DNA or RNA molecule base by base at nanometer scale as though looking through a strip of movie film. This DNA sequencing nanotechnology has the theoretical capability of performing DNA sequencing at a maximal rate of about 1,000,000 bases per second. This enhanced performance is made possible by a series of innovations including: novel applications of a fine-tuned nanometer gap for passage of a single DNA or RNA molecule; thin layer microfluidics for sample loading and delivery; and programmable electric fields for precise control of DNA or RNA movement. Detection methods include nanoelectrode-gated tunneling current measurements, dielectric molecular characterization, and atomic force microscopy/electrostatic force microscopy (AFM/EFM) probing for nanoscale reading of the nucleic acid sequences.

High Mobility Flexible Amorphous IGZO Thin-Film Transistors with a Low Thermal Budget Ultra-Violet Pulsed Light Process.

PubMed

Benwadih, M; Coppard, R; Bonrad, K; Klyszcz, A; Vuillaume, D

2016-12-21

Amorphous, sol-gel processed, indium gallium zinc oxide (IGZO) transistors on plastic substrate with a printable gate dielectric and an electron mobility of 4.5 cm 2 /(V s), as well as a mobility of 7 cm 2 /(V s) on solid substrate (Si/SiO 2 ) are reported. These performances are obtained using a low temperature pulsed light annealing technique. Ultraviolet (UV) pulsed light system is an innovative technique compared to conventional (furnace or hot-plate) annealing process that we successfully implemented on sol-gel IGZO thin film transistors (TFTs) made on plastic substrate. The photonic annealing treatment has been optimized to obtain IGZO TFTs with significant electrical properties. Organic gate dielectric layers deposited on this pulsed UV light annealed films have also been optimized. This technique is very promising for the development of amorphous IGZO TFTs on plastic substrates.