Plastic straw: future of high-speed signaling

NASA Astrophysics Data System (ADS)

Song, Ha Il; Jin, Huxian; Bae, Hyeon-Min

2015-11-01

The ever-increasing demand for bandwidth triggered by mobile and video Internet traffic requires advanced interconnect solutions satisfying functional and economic constraints. A new interconnect called E-TUBE is proposed as a cost-and-power-effective all-electrical-domain wideband waveguide solution for high-speed high-volume short-reach communication links. The E-TUBE achieves an unprecedented level of performance in terms of bandwidth-per-carrier frequency, power, and density without requiring a precision manufacturing process unlike conventional optical/waveguide solutions. The E-TUBE exhibits a frequency-independent loss-profile of 4 dB/m and has nearly 20-GHz bandwidth over the V band. A single-sideband signal transmission enabled by the inherent frequency response of the E-TUBE renders two-times data throughput without any physical overhead compared to conventional radio frequency communication technologies. This new interconnect scheme would be attractive to parties interested in high throughput links, including but not limited to, 100/400 Gbps chip-to-chip communications.

Low-power, transparent optical network interface for high bandwidth off-chip interconnects.

PubMed

Liboiron-Ladouceur, Odile; Wang, Howard; Garg, Ajay S; Bergman, Keren

2009-04-13

The recent emergence of multicore architectures and chip multiprocessors (CMPs) has accelerated the bandwidth requirements in high-performance processors for both on-chip and off-chip interconnects. For next generation computing clusters, the delivery of scalable power efficient off-chip communications to each compute node has emerged as a key bottleneck to realizing the full computational performance of these systems. The power dissipation is dominated by the off-chip interface and the necessity to drive high-speed signals over long distances. We present a scalable photonic network interface approach that fully exploits the bandwidth capacity offered by optical interconnects while offering significant power savings over traditional E/O and O/E approaches. The power-efficient interface optically aggregates electronic serial data streams into a multiple WDM channel packet structure at time-of-flight latencies. We demonstrate a scalable optical network interface with 70% improvement in power efficiency for a complete end-to-end PCI Express data transfer.

Interconnect Performance Evaluation of SGI Altix 3700 BX2, Cray X1, Cray Opteron Cluster, and Dell PowerEdge

NASA Technical Reports Server (NTRS)

Fatoohi, Rod; Saini, Subbash; Ciotti, Robert

2006-01-01

We study the performance of inter-process communication on four high-speed multiprocessor systems using a set of communication benchmarks. The goal is to identify certain limiting factors and bottlenecks with the interconnect of these systems as well as to compare these interconnects. We measured network bandwidth using different number of communicating processors and communication patterns, such as point-to-point communication, collective communication, and dense communication patterns. The four platforms are: a 512-processor SGI Altix 3700 BX2 shared-memory machine with 3.2 GB/s links; a 64-processor (single-streaming) Cray XI shared-memory machine with 32 1.6 GB/s links; a 128-processor Cray Opteron cluster using a Myrinet network; and a 1280-node Dell PowerEdge cluster with an InfiniBand network. Our, results show the impact of the network bandwidth and topology on the overall performance of each interconnect.

ICE: A Scalable, Low-Cost FPGA-Based Telescope Signal Processing and Networking System

NASA Astrophysics Data System (ADS)

Bandura, K.; Bender, A. N.; Cliche, J. F.; de Haan, T.; Dobbs, M. A.; Gilbert, A. J.; Griffin, S.; Hsyu, G.; Ittah, D.; Parra, J. Mena; Montgomery, J.; Pinsonneault-Marotte, T.; Siegel, S.; Smecher, G.; Tang, Q. Y.; Vanderlinde, K.; Whitehorn, N.

2016-03-01

We present an overview of the ‘ICE’ hardware and software framework that implements large arrays of interconnected field-programmable gate array (FPGA)-based data acquisition, signal processing and networking nodes economically. The system was conceived for application to radio, millimeter and sub-millimeter telescope readout systems that have requirements beyond typical off-the-shelf processing systems, such as careful control of interference signals produced by the digital electronics, and clocking of all elements in the system from a single precise observatory-derived oscillator. A new generation of telescopes operating at these frequency bands and designed with a vastly increased emphasis on digital signal processing to support their detector multiplexing technology or high-bandwidth correlators — data rates exceeding a terabyte per second — are becoming common. The ICE system is built around a custom FPGA motherboard that makes use of an Xilinx Kintex-7 FPGA and ARM-based co-processor. The system is specialized for specific applications through software, firmware and custom mezzanine daughter boards that interface to the FPGA through the industry-standard FPGA mezzanine card (FMC) specifications. For high density applications, the motherboards are packaged in 16-slot crates with ICE backplanes that implement a low-cost passive full-mesh network between the motherboards in a crate, allow high bandwidth interconnection between crates and enable data offload to a computer cluster. A Python-based control software library automatically detects and operates the hardware in the array. Examples of specific telescope applications of the ICE framework are presented, namely the frequency-multiplexed bolometer readout systems used for the South Pole Telescope (SPT) and Simons Array and the digitizer, F-engine, and networking engine for the Canadian Hydrogen Intensity Mapping Experiment (CHIME) and Hydrogen Intensity and Real-time Analysis eXperiment (HIRAX) radio interferometers.

Electronic interconnects and devices with topological surface states and methods for fabricating same

DOEpatents

Yazdani, Ali; Ong, N. Phuan; Cava, Robert J.

2017-04-04

An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having topological surface states. Also disclosed is a method for fabricating such interconnects. Also disclosed is an integrated circuit including such interconnects. Also disclosed is a gated electronic device including a material with charge carriers having topological surface states.

Electronic interconnects and devices with topological surface states and methods for fabricating same

DOEpatents

Yazdani, Ali; Ong, N. Phuan; Cava, Robert J.

2016-05-03

An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having topological surface states. Also disclosed is a method for fabricating such interconnects. Also disclosed is an integrated circuit including such interconnects. Also disclosed is a gated electronic device including a material with charge carriers having topological surface states.

Optical Interconnection Via Computer-Generated Holograms

NASA Technical Reports Server (NTRS)

Liu, Hua-Kuang; Zhou, Shaomin

1995-01-01

Method of free-space optical interconnection developed for data-processing applications like parallel optical computing, neural-network computing, and switching in optical communication networks. In method, multiple optical connections between multiple sources of light in one array and multiple photodetectors in another array made via computer-generated holograms in electrically addressed spatial light modulators (ESLMs). Offers potential advantages of massive parallelism, high space-bandwidth product, high time-bandwidth product, low power consumption, low cross talk, and low time skew. Also offers advantage of programmability with flexibility of reconfiguration, including variation of strengths of optical connections in real time.

A macrochip interconnection network enabled by silicon nanophotonic devices.

PubMed

Zheng, Xuezhe; Cunningham, John E; Koka, Pranay; Schwetman, Herb; Lexau, Jon; Ho, Ron; Shubin, Ivan; Krishnamoorthy, Ashok V; Yao, Jin; Mekis, Attila; Pinguet, Thierry

2010-03-01

We present an advanced wavelength-division multiplexing point-to-point network enabled by silicon nanophotonic devices. This network offers strictly non-blocking all-to-all connectivity while maximizing bisection bandwidth, making it ideal for multi-core and multi-processor interconnections. We introduce one of the key components, the nanophotonic grating coupler, and discuss, for the first time, how this device can be useful for practical implementations of the wavelength-division multiplexing network using optical proximity communications. Finite difference time-domain simulation of the nanophotonic grating coupler device indicates that it can be made compact (20 microm x 50 microm), low loss (3.8 dB), and broadband (100 nm). These couplers require subwavelength material modulation at the nanoscale to achieve the desired functionality. We show that optical proximity communication provides unmatched optical I/O bandwidth density to electrical chips, which enables the application of wavelength-division multiplexing point-to-point network in macrochip with unprecedented bandwidth-density. The envisioned physical implementation is discussed. The benefits of such an interconnect network include a 5-6x improvement in latency when compared to a purely electronic implementation. Performance analysis shows that the wavelength-division multiplexing point-to-point network offers better overall performance over other optical network architectures.

Optical interconnection network for parallel access to multi-rank memory in future computing systems.

PubMed

Wang, Kang; Gu, Huaxi; Yang, Yintang; Wang, Kun

2015-08-10

With the number of cores increasing, there is an emerging need for a high-bandwidth low-latency interconnection network, serving core-to-memory communication. In this paper, aiming at the goal of simultaneous access to multi-rank memory, we propose an optical interconnection network for core-to-memory communication. In the proposed network, the wavelength usage is delicately arranged so that cores can communicate with different ranks at the same time and broadcast for flow control can be achieved. A distributed memory controller architecture that works in a pipeline mode is also designed for efficient optical communication and transaction address processes. The scaling method and wavelength assignment for the proposed network are investigated. Compared with traditional electronic bus-based core-to-memory communication, the simulation results based on the PARSEC benchmark show that the bandwidth enhancement and latency reduction are apparent.

Optoelectronic interconnects for 3D wafer stacks

NASA Astrophysics Data System (ADS)

Ludwig, David E.; Carson, John C.; Lome, Louis S.

1996-01-01

Wafer and chip stacking are envisioned as a means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper provides definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies are discussed.

Optoelectronic interconnects for 3D wafer stacks

NASA Astrophysics Data System (ADS)

Ludwig, David; Carson, John C.; Lome, Louis S.

1996-01-01

Wafer and chip stacking are envisioned as means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper will provide definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies will be discussed.

Feasibility of optically interconnected parallel processors using wavelength division multiplexing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deri, R.J.; De Groot, A.J.; Haigh, R.E.

1996-03-01

New national security demands require enhanced computing systems for nearly ab initio simulations of extremely complex systems and analyzing unprecedented quantities of remote sensing data. This computational performance is being sought using parallel processing systems, in which many less powerful processors are ganged together to achieve high aggregate performance. Such systems require increased capability to communicate information between individual processor and memory elements. As it is likely that the limited performance of today`s electronic interconnects will prevent the system from achieving its ultimate performance, there is great interest in using fiber optic technology to improve interconnect communication. However, little informationmore » is available to quantify the requirements on fiber optical hardware technology for this application. Furthermore, we have sought to explore interconnect architectures that use the complete communication richness of the optical domain rather than using optics as a simple replacement for electronic interconnects. These considerations have led us to study the performance of a moderate size parallel processor with optical interconnects using multiple optical wavelengths. We quantify the bandwidth, latency, and concurrency requirements which allow a bus-type interconnect to achieve scalable computing performance using up to 256 nodes, each operating at GFLOP performance. Our key conclusion is that scalable performance, to {approx}150 GFLOPS, is achievable for several scientific codes using an optical bus with a small number of WDM channels (8 to 32), only one WDM channel received per node, and achievable optoelectronic bandwidth and latency requirements. 21 refs. , 10 figs.« less

3-D integrated heterogeneous intra-chip free-space optical interconnect.

PubMed

Ciftcioglu, Berkehan; Berman, Rebecca; Wang, Shang; Hu, Jianyun; Savidis, Ioannis; Jain, Manish; Moore, Duncan; Huang, Michael; Friedman, Eby G; Wicks, Gary; Wu, Hui

2012-02-13

This paper presents the first chip-scale demonstration of an intra-chip free-space optical interconnect (FSOI) we recently proposed. This interconnect system provides point-to-point free-space optical links between any two communication nodes, and hence constructs an all-to-all intra-chip communication fabric, which can be extended for inter-chip communications as well. Unlike electrical and other waveguide-based optical interconnects, FSOI exhibits low latency, high energy efficiency, and large bandwidth density, and hence can significantly improve the performance of future many-core chips. In this paper, we evaluate the performance of the proposed FSOI interconnect, and compare it to a waveguide-based optical interconnect with wavelength division multiplexing (WDM). It shows that the FSOI system can achieve significantly lower loss and higher energy efficiency than the WDM system, even with optimistic assumptions for the latter. A 1×1-cm2 chip prototype is fabricated on a germanium substrate with integrated photodetectors. Commercial 850-nm GaAs vertical-cavity-surface-emitting-lasers (VCSELs) and fabricated fused silica microlenses are 3-D integrated on top of the substrate. At 1.4-cm distance, the measured optical transmission loss is 5 dB, the crosstalk is less than -20 dB, and the electrical-to-electrical bandwidth is 3.3 GHz. The latter is mainly limited by the 5-GHz VCSEL.

Si photonics technology for future optical interconnection

NASA Astrophysics Data System (ADS)

Zheng, Xuezhe; Krishnamoorthy, Ashok V.

2011-12-01

Scaling of computing systems require ultra-efficient interconnects with large bandwidth density. Silicon photonics offers a disruptive solution with advantages in reach, energy efficiency and bandwidth density. We review our progress in developing building blocks for ultra-efficient WDM silicon photonic links. Employing microsolder based hybrid integration with low parasitics and high density, we optimize photonic devices on SOI platforms and VLSI circuits on more advanced bulk CMOS technology nodes independently. Progressively, we successfully demonstrated single channel hybrid silicon photonic transceivers at 5 Gbps and 10 Gbps, and 80 Gbps arrayed WDM silicon photonic transceiver using reverse biased depletion ring modulators and Ge waveguide photo detectors. Record-high energy efficiency of less than 100fJ/bit and 385 fJ/bit were achieved for the hybrid integrated transmitter and receiver, respectively. Waveguide grating based optical proximity couplers were developed with low loss and large optical bandwidth to enable multi-layer intra/inter-chip optical interconnects. Thermal engineering of WDM devices by selective substrate removal, together with WDM link using synthetic wavelength comb, we significantly improved the device tuning efficiency and reduced the tuning range. Using these innovative techniques, two orders of magnitude tuning power reduction was achieved. And tuning cost of only a few 10s of fJ/bit is expected for high data rate WDM silicon photonic links.

A 25-Gbps high-sensitivity optical receiver with 10-Gbps photodiode using inductive input coupling for optical interconnects

NASA Astrophysics Data System (ADS)

Oku, Hideki; Narita, Kiyomi; Shiraishi, Takashi; Ide, Satoshi; Tanaka, Kazuhiro

2012-01-01

A 25-Gbps high-sensitivity optical receiver with a 10-Gbps photodiode (PD) using inductive input coupling has been demonstrated for optical interconnects. We introduced the inductive input coupling technique to achieve the 25-Gbps optical receiver using a 10-Gbps PD. We implemented an input inductor (Lin) between the PD and trans-impedance amplifier (TIA), and optimized inductance to enhance the bandwidth and reduce the input referred noise current through simulation with the RF PD-model. Near the resonance frequency of the tank circuit formed by PD capacitance, Lin, and TIA input capacitance, the PD photo-current through Lin into the TIA is enhanced. This resonance has the effects of enhancing the bandwidth at TIA input and reducing the input equivalent value of the noise current from TIA. We fabricated the 25-Gbps optical receiver with the 10-Gbps PD using an inductive input coupling technique. Due to the application of an inductor, the receiver bandwidth is enhanced from 10 GHz to 14.2 GHz. Thanks to this wide-band and low-noise performance, we were able to improve the sensitivity at an error rate of 1E-12 from non-error-free to -6.5 dBm. These results indicate that our technique is promising for cost-effective optical interconnects.

Research on Optical Transmitter and Receiver Module Used for High-Speed Interconnection between CPU and Memory

NASA Astrophysics Data System (ADS)

He, Huimin; Liu, Fengman; Li, Baoxia; Xue, Haiyun; Wang, Haidong; Qiu, Delong; Zhou, Yunyan; Cao, Liqiang

2016-11-01

With the development of the multicore processor, the bandwidth and capacity of the memory, rather than the memory area, are the key factors in server performance. At present, however, the new architectures, such as fully buffered DIMM (FBDIMM), hybrid memory cube (HMC), and high bandwidth memory (HBM), cannot be commercially applied in the server. Therefore, a new architecture for the server is proposed. CPU and memory are separated onto different boards, and optical interconnection is used for the communication between them. Each optical module corresponds to each dual inline memory module (DIMM) with 64 channels. Compared to the previous technology, not only can the architecture realize high-capacity and wide-bandwidth memory, it also can reduce power consumption and cost, and be compatible with the existing dynamic random access memory (DRAM). In this article, the proposed module with system-in-package (SiP) integration is demonstrated. In the optical module, the silicon photonic chip is included, which is a promising technology to be applied in the next-generation data exchanging centers. And due to the bandwidth-distance performance of the optical interconnection, SerDes chips are introduced to convert the 64-bit data at 800 Mbps from/to 4-channel data at 12.8 Gbps after/before they are transmitted though optical fiber. All the devices are packaged on cheap organic substrates. To ensure the performance of the whole system, several optimization efforts have been performed on the two modules. High-speed interconnection traces have been designed and simulated with electromagnetic simulation software. Steady-state thermal characteristics of the transceiver module have been evaluated by ANSYS APLD based on finite-element methodology (FEM). Heat sinks are placed at the hotspot area to ensure the reliability of all working chips. Finally, this transceiver system based on silicon photonics is measured, and the eye diagrams of data and clock signals are verified.

Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates

NASA Astrophysics Data System (ADS)

Chappanda, K. N.; Ilyas, S.; Younis, M. I.

2018-05-01

Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5  ×  1012 oscillations.

Bandwidth Management in Resource Constrained Networks

DTIC Science & Technology

2012-03-01

Postgraduate School OSI Open Systems Interconnection QoS Quality of Service TCP Transmission Control Protocol/Internet Protocol TCP/IP Transmission...filtering. B. NORMAL TCP/IP COMMUNICATIONS The Internet is a “complex network WAN that connects LANs and clients around the globe” (Dean, 2009...of the Open Systems Interconnection ( OSI ) model allowing them to route traffic based on MAC address (Kurose & Ross, 2009). While switching

mpiGraph

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moody, Adam

2007-05-22

MpiGraph consists of an MPI application called mpiGraph written in C to measure message bandwidth and an associated crunch_mpiGraph script written in Perl to process the application output into an HTMO report. The mpiGraph application is designed to inspect the health and scalability of a high-performance interconnect while under heavy load. This is useful to detect hardware and software problems in a system, such as slow nodes, links, switches, or contention in switch routing. It is also useful to characterize how interconnect performance changes with different settings or how one interconnect type compares to another.

Next generation space interconnect research and development in space communications

NASA Astrophysics Data System (ADS)

Collier, Charles Patrick

2017-11-01

Interconnect or "bus" is one of the critical technologies in design of spacecraft avionics systems that dictates its architecture and complexity. MIL-STD-1553B has long been used as the avionics backbone technology. As avionics systems become more and more capable and complex, however, limitations of MIL-STD-1553B such as insufficient 1 Mbps bandwidth and separability have forced current avionics architects and designers to use combination of different interconnect technologies in order to meet various requirements: CompactPCI is used for backplane interconnect; LVDS or RS422 is used for low and high-speed direct point-to-point interconnect; and some proprietary interconnect standards are designed for custom interfaces. This results in a very complicated system that consumes significant spacecraft mass and power and requires extensive resources in design, integration and testing of spacecraft systems.

An efficient optical architecture for sparsely connected neural networks

NASA Technical Reports Server (NTRS)

Hine, Butler P., III; Downie, John D.; Reid, Max B.

1990-01-01

An architecture for general-purpose optical neural network processor is presented in which the interconnections and weights are formed by directing coherent beams holographically, thereby making use of the space-bandwidth products of the recording medium for sparsely interconnected networks more efficiently that the commonly used vector-matrix multiplier, since all of the hologram area is in use. An investigation is made of the use of computer-generated holograms recorded on such updatable media as thermoplastic materials, in order to define the interconnections and weights of a neural network processor; attention is given to limits on interconnection densities, diffraction efficiencies, and weighing accuracies possible with such an updatable thin film holographic device.

Analysis of performance improvements for host and GPU interface of the APENet+ 3D Torus network

NASA Astrophysics Data System (ADS)

Ammendola A, R.; Biagioni, A.; Frezza, O.; Lo Cicero, F.; Lonardo, A.; Paolucci, P. S.; Rossetti, D.; Simula, F.; Tosoratto, L.; Vicini, P.

2014-06-01

APEnet+ is an INFN (Italian Institute for Nuclear Physics) project aiming to develop a custom 3-Dimensional torus interconnect network optimized for hybrid clusters CPU-GPU dedicated to High Performance scientific Computing. The APEnet+ interconnect fabric is built on a FPGA-based PCI-express board with 6 bi-directional off-board links showing 34 Gbps of raw bandwidth per direction, and leverages upon peer-to-peer capabilities of Fermi and Kepler-class NVIDIA GPUs to obtain real zero-copy, GPU-to-GPU low latency transfers. The minimization of APEnet+ transfer latency is achieved through the adoption of RDMA protocol implemented in FPGA with specialized hardware blocks tightly coupled with embedded microprocessor. This architecture provides a high performance low latency offload engine for both trasmit and receive side of data transactions: preliminary results are encouraging, showing 50% of bandwidth increase for large packet size transfers. In this paper we describe the APEnet+ architecture, detailing the hardware implementation and discuss the impact of such RDMA specialized hardware on host interface latency and bandwidth.

FPGA-Based Filterbank Implementation for Parallel Digital Signal Processing

NASA Technical Reports Server (NTRS)

Berner, Stephan; DeLeon, Phillip

1999-01-01

One approach to parallel digital signal processing decomposes a high bandwidth signal into multiple lower bandwidth (rate) signals by an analysis bank. After processing, the subband signals are recombined into a fullband output signal by a synthesis bank. This paper describes an implementation of the analysis and synthesis banks using (Field Programmable Gate Arrays) FPGAs.

93-133 GHz Band InP High-Electron-Mobility Transistor Amplifier with Gain-Enhanced Topology

NASA Astrophysics Data System (ADS)

Sato, Masaru; Shiba, Shoichi; Matsumura, Hiroshi; Takahashi, Tsuyoshi; Nakasha, Yasuhiro; Suzuki, Toshihide; Hara, Naoki

2013-04-01

In this study, we developed a new type of high-frequency amplifier topology using 75-nm-gate-length InP-based high-electron-mobility transistors (InP HEMTs). To enhance the gain for a wide frequency range, a common-source common-gate hybrid amplifier topology was proposed. A transformer-based balun placed at the input of the amplifier generates differential signals, which are fed to the gate and source terminals of the transistor. The amplified signal is outputted at the drain node. The simulation results show that the hybrid topology exhibits a higher gain from 90 to 140 GHz than that of the conventional common-source or common-gate amplifier. The two-stage amplifier fabricated using the topology exhibits a small signal gain of 12 dB and a 3-dB bandwidth of 40 GHz (93-133 GHz), which is the largest bandwidth and the second highest gain reported among those of published 120-GHz-band amplifiers. In addition, the measured noise figure was 5 dB from 90 to 100 GHz.

Misalignment corrections in optical interconnects

NASA Astrophysics Data System (ADS)

Song, Deqiang

Optical interconnects are considered a promising solution for long distance and high bitrate data transmissions, outperforming electrical interconnects in terms of loss and dispersion. Due to the bandwidth and distance advantage of optical interconnects, longer links have been implemented with optics. Recent studies show that optical interconnects have clear advantages even at very short distances---intra system interconnects. The biggest challenge for such optical interconnects is the alignment tolerance. Many free space optical components require very precise assembly and installation, and therefore the overall cost could be increased. This thesis studied the misalignment tolerance and possible alignment correction solutions for optical interconnects at backplane or board level. First the alignment tolerance for free space couplers was simulated and the result indicated the most critical alignments occur between the VCSEL, waveguide and microlens arrays. An in-situ microlens array fabrication method was designed and experimentally demonstrated, with no observable misalignment with the waveguide array. At the receiver side, conical lens arrays were proposed to replace simple microlens arrays for a larger angular alignment tolerance. Multilayer simulation models in CodeV were built to optimized the refractive index and shape profiles of the conical lens arrays. Conical lenses fabricated with micro injection molding machine and fiber etching were characterized. Active component VCSOA was used to correct misalignment in optical connectors between the board and backplane. The alignment correction capability were characterized for both DC and AC (1GHz) optical signal. The speed and bandwidth of the VCSOA was measured and compared with a same structure VCSEL. Based on the optical inverter being studied in our lab, an all-optical flip-flop was demonstrated using a pair of VCSOAs. This memory cell with random access ability can store one bit optical signal with set or reset beam. The operating conditions were studied to generate two stable states between the VCSOA pair. The entire functionality test was implemented with free space optical components.

High-speed Si/GeSi hetero-structure Electro Absorption Modulator.

PubMed

Mastronardi, L; Banakar, M; Khokhar, A Z; Hattasan, N; Rutirawut, T; Bucio, T Domínguez; Grabska, K M; Littlejohns, C; Bazin, A; Mashanovich, G; Gardes, F Y

2018-03-19

The ever-increasing demand for integrated, low power interconnect systems is pushing the bandwidth density of CMOS photonic devices. Taking advantage of the strong Franz-Keldysh effect in the C and L communication bands, electro-absorption modulators in Ge and GeSi are setting a new standard in terms of device footprint and power consumption for next generation photonics interconnect arrays. In this paper, we present a compact, low power electro-absorption modulator (EAM) Si/GeSi hetero-structure based on an 800 nm SOI overlayer with a modulation bandwidth of 56 GHz. The device design and fabrication tolerant process are presented, followed by the measurement analysis. Eye diagram measurements show a dynamic ER of 5.2 dB at a data rate of 56 Gb/s at 1566 nm, and calculated modulator power is 44 fJ/bit.

UniBoard: generic hardware for radio astronomy signal processing

NASA Astrophysics Data System (ADS)

Hargreaves, J. E.

2012-09-01

UniBoard is a generic high-performance computing platform for radio astronomy, developed as a Joint Research Activity in the RadioNet FP7 Programme. The hardware comprises eight Altera Stratix IV Field Programmable Gate Arrays (FPGAs) interconnected by a high speed transceiver mesh. Each FPGA is connected to two DDR3 memory modules and three external 10Gbps ports. In addition, a total of 128 low voltage differential input lines permit connection to external ADC cards. The DSP capability of the board exceeds 644E9 complex multiply-accumulate operations per second. The first production run of eight boards was distributed to partners in The Netherlands, France, Italy, UK, China and Korea in May 2011, with a further production runs completed in December 2011 and early 2012. The function of the board is determined by the firmware loaded into its FPGAs. Current applications include beamformers, correlators, digital receivers, RFI mitigation for pulsar astronomy, and pulsar gating and search machines The new UniBoard based correlator for the European VLBI network (EVN) uses an FX architecture with half the resources of the board devoted to station based processing: delay and phase correction and channelization, and half to the correlation function. A single UniBoard can process a 64MHz band from 32 stations, 2 polarizations, sampled at 8 bit. Adding more UniBoards can expand the total bandwidth of the correlator. The design is able to process both prerecorded and real time (eVLBI) data.

Intra-Chip Free-Space Optical Interconnect: System, Device, Integration and Prototyping

NASA Astrophysics Data System (ADS)

Ciftcioglu, Berkehan

Currently, on-chip optical interconnect schemes already proposed utilize circuit switching using wavelength division multiplexing (WDM) or all-optical packet switching, all based on planar optical waveguides and related photonic devices such as microrings. These proposed approaches pose significant challenges in latency, energy efficiency, integration, and scalability. This thesis presents a new alternative approach by utilizing free-space optics. This 3-D integrated intra-chip free-space optical interconnect (FSOI) leverages mature photonic devices such as integrated lasers, photodiodes, microlenses and mirrors. It takes full advantages of the latest developments in 3-D integration technologies. This interconnect system provides point-to-point free-space optical links between any two communication nodes to construct an all-to-all intra-chip communication network with little or no arbitration. Therefore, it has significant networking advantages over conventional electrical and waveguide-based optical interconnects. An FSOI system is evaluated based on the real device parameters, predictive technology models and International Roadmap of Semiconductor's predictions. A single FSOI link achieves 10-Gbps data rate with 0.5-pJ/bit energy efficiency and less than 10--12 bit-error-rate (BER). A system using this individual link can provide scalability up to 36 nodes, providing 10-Tbps aggregate bandwidth. A comparison analysis performed between a WDM-based waveguide interconnect system and the proposed FSOI system shows that FSOI achieves better energy efficiency than the WDM one as the technology scales. Similarly, network simulation on a 16-core microprocessor using the proposed FSOI system instead of mesh networks has been shown to speed up the system by 12% and reduce the energy consumption by 33%. As a part of the development of a 3-D integrated FSOI system, operating at 850 nm with a 10-Gbps data rate per optical link, the photonics devices and optical components are individually designed and fabricated. The photodiodes (PDs) are designed to have large area for efficient light coupling and low capacitance to achieve large bandwidth, while achieving reasonably high responsivity. A metal-semiconductor-metal (MSM) structure is chosen over p-i-n ones to reduce parasitic capacitance per area, to allow less stringent microlens-to-PD alignment for efficient light coupling with a large bandwidth. A novel MSM germanium PD is implemented using an amorphous silicon (a-Si) layer on top of the undoped germanium substrate, serving as a barrier enhancement layer, mitigating the low Schottky barrier height for holes due to fermi level pinning and a surface passivation layer, preventing charge accumulation and image force lowering of the barrier. Therefore, the dark current is reduced and low-frequency gain is eliminated. The PDs achieve a 13-GHz bandwidth with a 0.315-A/W responsivity and a 1.7-nAmum² dark current density. The microlenses are fabricated on a fused silica substrate based on the photoresist melt-and-reflow technique, followed by dry etching into fused silica substrate. The measured focal length of a 220-mum aperture size microlens is 350-mum away from the backside of the substrate. The vertical-cavity surface-emitting lasers (VCSELs) are fabricated on a commercial molecular beam epitaxially (MBE) grown GaAs wafer. The fabricated 8-mum aperture size VCSEL can achieve 0.65-mW optical power at a 1.5-mA forward bias current with a threshold current of 0.48 mA and a 0.67-A/W slope efficiency. Three prototypes are implemented via integrating the individually fabricated components using non-conductive epoxy and wirebonding. The first prototype, built on a printed circuit board (PCB) using commercial VCSEL arrays, achieves a 5-dB transmission loss and less than -30-dB crosstalk at 1-cm distance with a small-signal bandwidth of 10 GHz, limited by the VCSEL. The second board-level prototype uses all fabricated components integrated on a PCB. The prototype achieves a 9-dB transmission loss at 3-cm distance and a 4.4-GHz bandwidth. The chip-level prototype is built on a germanium carrier with integrated MSM Ge PDs, microlenses on fused silica and VCSEL chip on GaAs substrates. The prototype achieves 4-dB transmission loss at 1 cm and 3.3-GHz bandwidth, limited by commercial VCSEL bandwidth. (Abstract shortened by UMI.)

Evaluation of mechanical dyssynchrony and myocardial perfusion using phase analysis of gated SPECT imaging in patients with left ventricular dysfunction

PubMed Central

Trimble, Mark A.; Borges-Neto, Salvador; Honeycutt, Emily F.; Shaw, Linda K.; Pagnanelli, Robert; Chen, Ji; Iskandrian, Ami E.; Garcia, Ernest V.; Velazquez, Eric J.

2010-01-01

Background Using phase analysis of gated single photon emission computed tomography (SPECT) imaging, we examined the relation between myocardial perfusion, degree of electrical dyssynchrony, and degree of SPECT-derived mechanical dyssynchrony in patients with left ventricular (LV) dysfunction. Methods and Results We retrospectively examined 125 patients with LV dysfunction and ejection fraction of 35% or lower. Fourier analysis converts regional myocardial counts into a continuous thickening function, allowing resolution of phase of onset of myocardial thickening. The SD of LV phase distribution (phase SD) and histogram bandwidth describe LV phase dispersion as a measure of dyssynchrony. Heart failure (HF) patients with perfusion abnormalities ities have higher degrees of dyssynchrony measured by median phase SD (45.5° vs 27.7°, P < .0001) and bandwidth (117.0° vs 73.0°, P = .0006). HF patients with prolonged QRS durations have higher degrees of dyssynchrony measured by median phase SD (54.1° vs 34.7°, P < .0001) and bandwidth (136.5° vs 99.0°, P = .0005). Mild to moderate correlations exist between QRS duration and phase analysis indices of phase SD (r = 0.50) and bandwidth (r = 0.40). Mechanical dyssynchrony (phase SD >43°) was 43.2%. Conclusions HF patients with perfusion abnormalities or prolonged QRS durations QRS durations have higher degrees of mechanical dyssynchrony. Gated SPECT myocardial perfusion imaging can quantify myocardial function, perfusion, and dyssynchrony and may help in evaluating patients for cardiac resynchronization therapy. PMID:18761269

Gigascale Silicon Photonic Transmitters Integrating HBT-based Carrier-injection Electroabsorption Modulator Structures

NASA Astrophysics Data System (ADS)

Fu, Enjin

Demand for more bandwidth is rapidly increasing, which is driven by data intensive applications such as high-definition (HD) video streaming, cloud storage, and terascale computing applications. Next-generation high-performance computing systems require power efficient chip-to-chip and intra-chip interconnect yielding densities on the order of 1Tbps/cm2. The performance requirements of such system are the driving force behind the development of silicon integrated optical interconnect, providing a cost-effective solution for fully integrated optical interconnect systems on a single substrate. Compared to conventional electrical interconnect, optical interconnects have several advantages, including frequency independent insertion loss resulting in ultra wide bandwidth and link latency reduction. For high-speed optical transmitter modules, the optical modulator is a key component of the optical I/O channel. This thesis presents a silicon integrated optical transmitter module design based on a novel silicon HBT-based carrier injection electroabsorption modulator (EAM), which has the merits of wide optical bandwidth, high speed, low power, low drive voltage, small footprint, and high modulation efficiency. The structure, mechanism, and fabrication of the modulator structure will be discussed which is followed by the electrical modeling of the post-processed modulator device. The design and realization of a 10Gbps monolithic optical transmitter module integrating the driver circuit architecture and the HBT-based EAM device in a 130nm BiCMOS process is discussed. For high power efficiency, a 6Gbps ultra-low power driver IC implemented in a 130nm BiCMOS process is presented. The driver IC incorporates an integrated 27-1 pseudo-random bit sequence (PRBS) generator for reliable high-speed testing, and a driver circuit featuring digitally-tuned pre-emphasis signal strength. With outstanding drive capability, the driver module can be applied to a wide range of carrier injection modulators and light-emitting diodes (LED) with drive voltage requirements below 1.5V. Measurement results show an optical link based on a 70MHz red LED work well at 300Mbps by using the pre-emphasis driver module. A traveling wave electrode (TWE) modulator structure is presented, including a novel design methodology to address process limitations imposed by a commercial silicon fabrication technology. Results from 3D full wave EM simulation demonstrate the application of the design methodology to achieve specifications, including phase velocity matching, insertion loss, and impedance matching. Results show the HBT-based TWE-EAM system has the bandwidth higher than 60GHz.

Circuit-Switched Memory Access in Photonic Interconnection Networks for High-Performance Embedded Computing

DTIC Science & Technology

2010-07-22

dependent , providing a natural bandwidth match between compute cores and the memory subsystem. • High Bandwidth Dcnsity. Waveguides crossing the chip...simulate this memory access architecture on a 2S6-core chip with a concentrated 64-node network lIsing detailed traces of high-performance embedded...memory modulcs, wc placc memory access poi nts (MAPs) around the pcriphery of the chip connected to thc nctwork. These MAPs, shown in Figure 4, contain

Optical Interconnections for VLSI Computational Systems Using Computer-Generated Holography.

NASA Astrophysics Data System (ADS)

Feldman, Michael Robert

Optical interconnects for VLSI computational systems using computer generated holograms are evaluated in theory and experiment. It is shown that by replacing particular electronic connections with free-space optical communication paths, connection of devices on a single chip or wafer and between chips or modules can be improved. Optical and electrical interconnects are compared in terms of power dissipation, communication bandwidth, and connection density. Conditions are determined for which optical interconnects are advantageous. Based on this analysis, it is shown that by applying computer generated holographic optical interconnects to wafer scale fine grain parallel processing systems, dramatic increases in system performance can be expected. Some new interconnection networks, designed to take full advantage of optical interconnect technology, have been developed. Experimental Computer Generated Holograms (CGH's) have been designed, fabricated and subsequently tested in prototype optical interconnected computational systems. Several new CGH encoding methods have been developed to provide efficient high performance CGH's. One CGH was used to decrease the access time of a 1 kilobit CMOS RAM chip. Another was produced to implement the inter-processor communication paths in a shared memory SIMD parallel processor array.

Sub-50-as isolated extreme ultraviolet continua generated by 1.6-cycle near-infrared pulse combined with double optical gating scheme

NASA Astrophysics Data System (ADS)

Oguri, Katsuya; Mashiko, Hiroki; Ogawa, Tatsuya; Hanada, Yasutaka; Nakano, Hidetoshi; Gotoh, Hideki

2018-04-01

We demonstrate the generation of ultrabroad bandwidth attosecond continua extending to sub-50-as duration in the extreme ultraviolet (EUV) region based on a 1.6-cycle Ti:sapphire laser pulse. The combination of the amplitude gating scheme with a sub-two-cycle driver pulse and the double optical gating scheme achieves the continuum generation with a bandwidth of 70 eV at the full width at half maximum near the peak photon energy of 140 eV, which supports a Fourier-transform-limited pulse duration as short as 32 as. The carrier-envelope-phase (CEP) dependence of the attosecond continua shows a single-peak structure originating from the half-cycle cut-off at appropriate CEP values, which strongly indicates the generation of a single burst of an isolated attosecond pulse. Our approach suggests a possibility for isolated sub-50-as pulse generation in the EUV region by compensating for the intrinsic attosecond chirp with a Zr filter.

Cislan-2 extension final document by University of Twente (Netherlands)

NASA Astrophysics Data System (ADS)

Niemegeers, Ignas; Baumann, Frank; Beuwer, Wim; Jordense, Marcel; Pras, Aiko; Schutte, Leon; Tracey, Ian

1992-01-01

Results of worked performed under the so called Cislan extension contract are presented. The adaptation of the Cislan 2 prototype design to an environment of interconnected Local Area Networks (LAN's) instead of a single 802.5 token ring LAN is considered. In order to extend the network architecture, the Interconnection Function (IF) protocol layer was subdivided into two protocol layers: a new IF layer, and below the Medium Enhancement (ME) protocol layer. Some small enhancements to the distributed bandwidth allocation protocol were developed, which in fact are also applicable to the 'normal' Cislan 2 system. The new services and protocols are described together with some scenarios and requirements for the new internetting Cislan 2 system. How to overcome the degradation of the quality of speech due to packet loss on the LAN subsystem was studied. Experiments were planned in order to measure this speech quality degradation. Simulations were performed of two Cislan subsystems, the bandwidth allocation protocol and the clock synchronization mechanism. Results on both simulations, performed on SUN workstations using QNAP as a simulation tool, are given. Results of the simulations of the clock synchronization mechanism, and results of the simulation of the distributed bandwidth allocation protocol are given.

Integrated MEMS-tunable VCSELs for reconfigurable optical interconnects

NASA Astrophysics Data System (ADS)

Kögel, Benjamin; Debernardi, Pierluigi; Westbergh, Petter; Gustavsson, Johan S.; Haglund, Åsa; Haglund, Erik; Bengtsson, Jörgen; Larsson, Anders

2012-03-01

A simple and low-cost technology for tunable vertical-cavity surface-emitting lasers (VCSELs) with curved movable micromirror is presented. The micro-electro-mechanical system (MEMS) is integrated with the active optical component (so-called half-VCSEL) by means of surface-micromachining using a reflown photoresist droplet as sacrificial layer. The technology is demonstrated for electrically pumped, short-wavelength (850 nm) tunable VCSELs. Fabricated devices with 10 μm oxide aperture are singlemode with sidemode suppression >35 dB, tunable over 24 nm with output power up to 0.5mW, and have a beam divergence angle <6 °. An improved high-speed design with reduced parasitic capacitance enables direct modulation with 3dB-bandwidths up to 6GHz and error-free data transmission at 5Gbit/s. The modulation response of the MEMS under electrothermal actuation has a bandwidth of 400 Hz corresponding to switching times of about 10ms. The thermal crosstalk between MEMS and half-VCSEL is negligible and not degrading the device performance. With these characteristics the integrated MEMS-tunable VCSELs are basically suitable for use in reconfigurable optical interconnects and ready for test in a prototype system. Schemes for improving output power, tuning speed, and modulation bandwidth are briefly discussed.

Performance evaluation of time-aware enhanced software defined networking (TeSDN) for elastic data center optical interconnection.

PubMed

Yang, Hui; Zhang, Jie; Zhao, Yongli; Ji, Yuefeng; Li, Hui; Lin, Yi; Li, Gang; Han, Jianrui; Lee, Young; Ma, Teng

2014-07-28

Data center interconnection with elastic optical networks is a promising scenario to meet the high burstiness and high-bandwidth requirements of data center services. We previously implemented enhanced software defined networking over elastic optical network for data center application [Opt. Express 21, 26990 (2013)]. On the basis of it, this study extends to consider the time-aware data center service scheduling with elastic service time and service bandwidth according to the various time sensitivity requirements. A novel time-aware enhanced software defined networking (TeSDN) architecture for elastic data center optical interconnection has been proposed in this paper, by introducing a time-aware resources scheduling (TaRS) scheme. The TeSDN can accommodate the data center services with required QoS considering the time dimensionality, and enhance cross stratum optimization of application and elastic optical network stratums resources based on spectrum elasticity, application elasticity and time elasticity. The overall feasibility and efficiency of the proposed architecture is experimentally verified on our OpenFlow-based testbed. The performance of TaRS scheme under heavy traffic load scenario is also quantitatively evaluated based on TeSDN architecture in terms of blocking probability and resource occupation rate.

Scalability analysis methodology for passive optical interconnects in data center networks using PAM

NASA Astrophysics Data System (ADS)

Lin, R.; Szczerba, Krzysztof; Agrell, Erik; Wosinska, Lena; Tang, M.; Liu, D.; Chen, J.

2017-11-01

A framework is developed for modeling the fundamental impairments in optical datacenter interconnects, i.e., the power loss and the receiver noises. This framework makes it possible, to analyze the trade-offs between data rates, modulation order, and number of ports that can be supported in optical interconnect architectures, while guaranteeing that the required signal-to-noise ratios are satisfied. To the best of our knowledge, this important assessment methodology is not yet available. As a case study, the trade-offs are investigated for three coupler-based top-of-rack interconnect architectures, which suffer from serious insertion loss. The results show that using single-port transceivers with 10 GHz bandwidth, avalanche photodiode detectors, and quadratical pulse amplitude modulation, more than 500 ports can be supported.

Advances in integrated photonic circuits for packet-switched interconnection

NASA Astrophysics Data System (ADS)

Williams, Kevin A.; Stabile, Ripalta

2014-03-01

Sustained increases in capacity and connectivity are needed to overcome congestion in a range of broadband communication network nodes. Packet routing and switching in the electronic domain are leading to unsustainable energy- and bandwidth-densities, motivating research into hybrid solutions: optical switching engines are introduced for massive-bandwidth data transport while the electronic domain is clocked at more modest GHz rates to manage routing. Commercially-deployed optical switching engines using MEMS technologies are unwieldy and too slow to reconfigure for future packet-based networking. Optoelectronic packet-compliant switch technologies have been demonstrated as laboratory prototypes, but they have so far mostly used discretely pigtailed components, which are impractical for control plane development and product assembly. Integrated photonics has long held the promise of reduced hardware complexity and may be the critical step towards packet-compliant optical switching engines. Recently a number of laboratories world-wide have prototyped optical switching circuits using monolithic integration technology with up to several hundreds of integrated optical components per chip. Our own work has focused on multi-input to multi-output switching matrices. Recently we have demonstrated 8×8×8λ space and wavelength selective switches using gated cyclic routers and 16×16 broadband switching chips using monolithic multi-stage networks. We now operate these advanced circuits with custom control planes implemented with FPGAs to explore real time packet routing in multi-wavelength, multi-port test-beds. We review our contributions in the context of state of the art photonic integrated circuit technology and packet optical switching hardware demonstrations.

All-fibre optical gating system for measuring a complex-shaped periodic broadband signal with picosecond resolution in a nanosecond time window

NASA Astrophysics Data System (ADS)

Andrianov, A. V.

2018-04-01

We have developed an optical gating system for continuously monitoring a complex-shaped periodic optical signal with picosecond resolution in a nanosecond time window using an all-fibre optical gate in the form of a nonlinear loop mirror and a passively mode-locked femtosecond laser. The distinctive features of the system are the possibility of characterizing signals with a very large spectral bandwidth, the possibility of using a gating pulse source with a wavelength falling in the band of the signal under study and its all-fibre design with the use of standard fibres and telecom components.

Silicon quantum processor with robust long-distance qubit couplings

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tosi, Guilherme; Mohiyaddin, Fahd A.; Schmitt, Vivien

Practical quantum computers require a large network of highly coherent qubits, interconnected in a design robust against errors. Donor spins in silicon provide state-of-the-art coherence and quantum gate fidelities, in a platform adapted from industrial semiconductor processing. Here we present a scalable design for a silicon quantum processor that does not require precise donor placement and leaves ample space for the routing of interconnects and readout devices. We introduce the flip-flop qubit, a combination of the electron-nuclear spin states of a phosphorus donor that can be controlled by microwave electric fields. Two-qubit gates exploit a second-order electric dipole-dipole interaction, allowingmore » selective coupling beyond the nearest-neighbor, at separations of hundreds of nanometers, while microwave resonators can extend the entanglement to macroscopic distances. We predict gate fidelities within fault-tolerance thresholds using realistic noise models. This design provides a realizable blueprint for scalable spin-based quantum computers in silicon.« less

Multiscale free-space optical interconnects for intrachip global communication: motivation, analysis, and experimental validation.

PubMed

McFadden, Michael J; Iqbal, Muzammil; Dillon, Thomas; Nair, Rohit; Gu, Tian; Prather, Dennis W; Haney, Michael W

2006-09-01

The use of optical interconnects for communication between points on a microchip is motivated by system-level interconnect modeling showing the saturation of metal wire capacity at the global layer. Free-space optical solutions are analyzed for intrachip communication at the global layer. A multiscale solution comprising microlenses, etched compound slope microprisms, and a curved mirror is shown to outperform a single-scale alternative. Microprisms are designed and fabricated and inserted into an optical setup apparatus to experimentally validate the concept. The multiscale free-space system is shown to have the potential to provide the bandwidth density and configuration flexibility required for global communication in future generations of microchips.

Fully digital routing logic for single-photon avalanche diode arrays in highly efficient time-resolved imaging

NASA Astrophysics Data System (ADS)

Cominelli, Alessandro; Acconcia, Giulia; Ghioni, Massimo; Rech, Ivan

2018-03-01

Time-correlated single-photon counting (TCSPC) is a powerful optical technique, which permits recording fast luminous signals with picosecond precision. Unfortunately, given its repetitive nature, TCSPC is recognized as a relatively slow technique, especially when a large time-resolved image has to be recorded. In recent years, there has been a fast trend toward the development of TCPSC imagers. Unfortunately, present systems still suffer from a trade-off between number of channels and performance. Even worse, the overall measurement speed is still limited well below the saturation of the transfer bandwidth toward the external processor. We present a routing algorithm that enables a smart connection between a 32×32 detector array and five shared high-performance converters able to provide an overall conversion rate up to 10 Gbit/s. The proposed solution exploits a fully digital logic circuit distributed in a tree structure to limit the number and length of interconnections, which is a major issue in densely integrated circuits. The behavior of the logic has been validated by means of a field-programmable gate array, while a fully integrated prototype has been designed in 180-nm technology and analyzed by means of postlayout simulations.

Scaling single-wavelength optical interconnects to 180 Gb/s with PAM-M and pulse shaping

NASA Astrophysics Data System (ADS)

Dris, Stefanos; Bakopoulos, Paraskevas; Argyris, Nikolaos; Spatharakis, Christos; Avramopoulos, Hercules

2016-03-01

Faced with surging datacenter traffic demand, system designers are turning to multi-level optical modulation with direct detection as the means of reaching 100 Gb/s in a single optical lane; a further upgrade to 400 Gb/s is envisaged through wavelength-multiplexing of multiple 100 Gb/s strands. In terms of modulation formats, PAM-4 and PAM-8 are considered the front-runners, striking a good balance between bandwidth-efficiency and implementation complexity. In addition, the emergence of energy-efficient, high-speed CMOS digital-to-analog converters (DACs) opens up new possibilities: Spectral shaping through digital filtering will allow squeezing even more data through low-cost, low-bandwidth electro-optic components. In this work we demonstrate an optical interconnect based on an EAM that is driven directly with sub-volt electrical swing by a 65 GSa/s arbitrary waveform generator (AWG). Low-voltage drive is particularly attractive since it allows direct interfacing with the switch/server ASIC, eliminating the need for dedicated, power-hungry and expensive electrical drivers. Single-wavelength throughputs of 180 and 120 Gb/s are experimentally demonstrated with 60 Gbaud optical PAM-8 and PAM-4 respectively. Successful transmission over 1250 m SMF is achieved with direct-detection, using linear equalization via offline digital signal processing in order to overcome the strong bandwidth limitation of the overall link (~20 GHz). The suitability of Nyquist pulse shaping for optical interconnects is also investigated experimentally with PAM-4 and PAM-8, at a lower symbol rate of 40 Gbaud (limited by the sampling rate of the AWG). To the best of our knowledge, the rates achieved are the highest ever using optical PAM-M formats.

Ultra-compact, flat-top demultiplexer using anti-reflection contra-directional couplers for CWDM networks on silicon.

PubMed

Shi, Wei; Yun, Han; Lin, Charlie; Greenberg, Mark; Wang, Xu; Wang, Yun; Fard, Sahba Talebi; Flueckiger, Jonas; Jaeger, Nicolas A F; Chrostowski, Lukas

2013-03-25

Wavelength-division-multiplexing (WDM) networks with wide channel grids and bandwidths are promising for low-cost, low-power optical interconnects. Wide-bandwidth, single-band (i.e., no free-spectral range) add-drop filters have been developed on silicon using anti-reflection contra-directional couplers with out-of-phase Bragg gratings. Using such filter components, we demonstrate a 4-channel, coarse-WDM demultiplexer with flat passbands of up to 13 nm and an ultra-compact size of 1.2 × 10(-3) mm(2).

Broadband gate-tunable terahertz plasmons in graphene heterostructures

NASA Astrophysics Data System (ADS)

Yao, Baicheng; Liu, Yuan; Huang, Shu-Wei; Choi, Chanyeol; Xie, Zhenda; Flor Flores, Jaime; Wu, Yu; Yu, Mingbin; Kwong, Dim-Lee; Huang, Yu; Rao, Yunjiang; Duan, Xiangfeng; Wong, Chee Wei

2018-01-01

Graphene, a unique two-dimensional material comprising carbon in a honeycomb lattice1, has brought breakthroughs across electronics, mechanics and thermal transport, driven by the quasiparticle Dirac fermions obeying a linear dispersion2,3. Here, we demonstrate a counter-pumped all-optical difference frequency process to coherently generate and control terahertz plasmons in atomic-layer graphene with octave-level tunability and high efficiency. We leverage the inherent surface asymmetry of graphene for strong second-order nonlinear polarizability4,5, which, together with tight plasmon field confinement, enables a robust difference frequency signal at terahertz frequencies. The counter-pumped resonant process on graphene uniquely achieves both energy and momentum conservation. Consequently, we demonstrate a dual-layer graphene heterostructure with terahertz charge- and gate-tunability over an octave, from 4.7 THz to 9.4 THz, bounded only by the pump amplifier optical bandwidth. Theoretical modelling supports our single-volt-level gate tuning and optical-bandwidth-bounded 4.7 THz phase-matching measurements through the random phase approximation, with phonon coupling, saturable absorption and below the Landau damping, to predict and understand graphene plasmon physics.

Electronic Subsystem Analysis (ESA)

DTIC Science & Technology

1977-01-01

than aluminum for the gate material, 0 Ion implanted source and draia regions, 0 Dielectrically isolated transistors. The use of a doped polysilicon gate...second level of interconnect ( polysilicon ). Ion implantation is essentially a precisely controllable pre-deposition of the required dopants. It’s use...discussed below). Radiation effects on MOS devices include the following: 0 Total Dose ol Dose Rate o Neutrons Because MOS technology is based on

Fabrication of magnetic tunnel junctions connected through a continuous free layer to enable spin logic devices

NASA Astrophysics Data System (ADS)

Wan, Danny; Manfrini, Mauricio; Vaysset, Adrien; Souriau, Laurent; Wouters, Lennaert; Thiam, Arame; Raymenants, Eline; Sayan, Safak; Jussot, Julien; Swerts, Johan; Couet, Sebastien; Rassoul, Nouredine; Babaei Gavan, Khashayar; Paredis, Kristof; Huyghebaert, Cedric; Ercken, Monique; Wilson, Christopher J.; Mocuta, Dan; Radu, Iuliana P.

2018-04-01

Magnetic tunnel junctions (MTJs) interconnected via a continuous ferromagnetic free layer were fabricated for spin torque majority gate (STMG) logic. The MTJs are biased independently and show magnetoelectric response under spin transfer torque. The electrical control of these devices paves the way to future spin logic devices based on domain wall (DW) motion. In particular, it is a significant step towards the realization of a majority gate. To our knowledge, this is the first fabrication of a cross-shaped free layer shared by several perpendicular MTJs. The fabrication process can be generalized to any geometry and any number of MTJs. Thus, this framework can be applied to other spin logic concepts based on magnetic interconnect. Moreover, it allows exploration of spin dynamics for logic applications.

Note: A high dynamic range, linear response transimpedance amplifier.

PubMed

Eckel, S; Sushkov, A O; Lamoreaux, S K

2012-02-01

We have built a high dynamic range (nine decade) transimpedance amplifier with a linear response. The amplifier uses junction-gate field effect transistors (JFETs) to switch between three different resistors in the feedback of a low input bias current operational amplifier. This allows for the creation of multiple outputs, each with a linear response and a different transimpedance gain. The overall bandwidth of the transimpedance amplifier is set by the bandwidth of the most sensitive range. For our application, we demonstrate a three-stage amplifier with transimpedance gains of approximately 10(9)Ω, 3 × 10(7)Ω, and 10(4)Ω with a bandwidth of 100 Hz.

40-Gb/s directly-modulated photonic crystal lasers under optical injection-locking

NASA Astrophysics Data System (ADS)

Chen, Chin-Hui; Takeda, Koji; Shinya, Akihiko; Nozaki, Kengo; Sato, Tomonari; Kawaguchi, Yoshihiro; Notomi, Masaya; Matsuo, Shinji

2011-08-01

CMOS integrated circuits (IC) usually requires high data bandwidth for off-chip input/output (I/O) data transport with sufficiently low power consumption in order to overcome pin-count limitation. In order to meet future requirements of photonic network interconnect, we propose an optical output device based on an optical injection-locked photonic crystal (PhC) laser to realize low-power and high-speed off-chip interconnects. This device enables ultralow-power operation and is suitable for highly integrated photonic circuits because of its strong light-matter interaction in the PhC nanocavity and ultra-compact size. High-speed operation is achieved by using the optical injection-locking (OIL) technique, which has been shown as an effective means to enhance modulation bandwidth beyond the relaxation resonance frequency limit. In this paper, we report experimental results of the OIL-PhC laser under various injection conditions and also demonstrate 40-Gb/s large-signal direct modulation with an ultralow energy consumption of 6.6 fJ/bit.

High-rate serial interconnections for embedded and distributed systems with power and resource constraints

NASA Astrophysics Data System (ADS)

Sheynin, Yuriy; Shutenko, Felix; Suvorova, Elena; Yablokov, Evgenej

2008-04-01

High rate interconnections are important subsystems in modern data processing and control systems of many classes. They are especially important in prospective embedded and on-board systems that used to be multicomponent systems with parallel or distributed architecture, [1]. Modular architecture systems of previous generations were based on parallel busses that were widely used and standardised: VME, PCI, CompactPCI, etc. Busses evolution went in improvement of bus protocol efficiency (burst transactions, split transactions, etc.) and increasing operation frequencies. However, due to multi-drop bus nature and multi-wire skew problems the parallel bussing speedup became more and more limited. For embedded and on-board systems additional reason for this trend was in weight, size and power constraints of an interconnection and its components. Parallel interfaces have become technologically more challenging as their respective clock frequencies have increased to keep pace with the bandwidth requirements of their attached storage devices. Since each interface uses a data clock to gate and validate the parallel data (which is normally 8 bits or 16 bits wide), the clock frequency need only be equivalent to the byte rate or word rate being transmitted. In other words, for a given transmission frequency, the wider the data bus, the slower the clock. As the clock frequency increases, more high frequency energy is available in each of the data lines, and a portion of this energy is dissipated in radiation. Each data line not only transmits this energy but also receives some from its neighbours. This form of mutual interference is commonly called "cross-talk," and the signal distortion it produces can become another major contributor to loss of data integrity unless compensated by appropriate cable designs. Other transmission problems such as frequency-dependent attenuation and signal reflections, while also applicable to serial interfaces, are more troublesome in parallel interfaces due to the number of additional cable conductors involved. In order to compensate for these drawbacks, higher quality cables, shorter cable runs and fewer devices on the bus have been the norm. Finally, the physical bulk of the parallel cables makes them more difficult to route inside an enclosure, hinders cooling airflow and is incompatible with the trend toward smaller form-factor devices. Parallel busses worked in systems during the past 20 years, but the accumulated problems dictate the need for change and the technology is available to spur the transition. The general trend in high-rate interconnections turned from parallel bussing to scalable interconnections with a network architecture and high-rate point-to-point links. Analysis showed that data links with serial information transfer could achieve higher throughput and efficiency and it was confirmed in various research and practical design. Serial interfaces offer an improvement over older parallel interfaces: better performance, better scalability, and also better reliability as the parallel interfaces are at their limits of speed with reliable data transfers and others. The trend was implemented in major standards' families evolution: e.g. from PCI/PCI-X parallel bussing to PCIExpress interconnection architecture with serial lines, from CompactPCI parallel bus to ATCA (Advanced Telecommunications Architecture) specification with serial links and network topologies of an interconnection, etc. In the article we consider a general set of characteristics and features of serial interconnections, give a brief overview of serial interconnections specifications. In more details we present the SpaceWire interconnection technology. Have been developed for space on-board systems applications the SpaceWire has important features and characteristics that make it a prospective interconnection for wide range of embedded systems.

Mølmer-Sørensen entangling gate for cavity QED systems

NASA Astrophysics Data System (ADS)

Takahashi, Hiroki; Nevado, Pedro; Keller, Matthias

2017-10-01

The Mølmer-Sørensen gate is a state-of-the-art entangling gate in ion trap quantum computing where the gate fidelity can exceed 99%. Here we propose an analogous implementation in the setting of cavity QED. The cavity photon mode acts as the bosonic degree of freedom in the gate in contrast to that played by the phonon mode in ion traps. This is made possible by utilising cavity assisted Raman transitions interconnecting the logical qubit states embedded in a four-level energy structure, making the ‘anti-Jaynes-Cummings’ term available under the rotating-wave approximation. We identify practical sources of infidelity and discuss their effects on the gate performance. Our proposal not only demonstrates an alternative entangling gate scheme but also sheds new light on the relationship between ion traps and cavity QED, in the sense that many techniques developed in the former are transferable to the latter through our framework.

Next Generation Space Interconnect Standard (NGSIS): a modular open standards approach for high performance interconnects for space

NASA Astrophysics Data System (ADS)

Collier, Charles Patrick

2017-04-01

The Next Generation Space Interconnect Standard (NGSIS) effort is a Government-Industry collaboration effort to define a set of standards for interconnects between space system components with the goal of cost effectively removing bandwidth as a constraint for future space systems. The NGSIS team has selected the ANSI/VITA 65 OpenVPXTM standard family for the physical baseline. The RapidIO protocol has been selected as the basis for the digital data transport. The NGSIS standards are developed to provide sufficient flexibility to enable users to implement a variety of system configurations, while meeting goals for interoperability and robustness for space. The NGSIS approach and effort represents a radical departure from past approaches to achieve a Modular Open System Architecture (MOSA) for space systems and serves as an exemplar for the civil, commercial, and military Space communities as well as a broader high reliability terrestrial market.

TRIGA: Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Arrays

NASA Technical Reports Server (NTRS)

Pang, Jackson; Pingree, Paula J.; Torgerson, J. Leigh

2006-01-01

We present the Telecommunications protocol processing subsystem using Reconfigurable Interoperable Gate Arrays (TRIGA), a novel approach that unifies fault tolerance, error correction coding and interplanetary communication protocol off-loading to implement CCSDS File Delivery Protocol and Datalink layers. The new reconfigurable architecture offers more than one order of magnitude throughput increase while reducing footprint requirements in memory, command and data handling processor utilization, communication system interconnects and power consumption.

VoIPNET: A Software Based Communications Tool for Low-Bandwidth Networks

DTIC Science & Technology

2007-06-01

Plan Suplemental Tools. <http://www.dir.state.tx.us/pubs/framework/gate2/riskplan/ Deitel , H.M. and Deitel , P.J. Java: How To Program . 5th...Up. 3rd Edition. California: McGraw-Hill, 2003. Deitel , H.M. and Deitel , P.J. C++: How to Program . 5th Edition. New Jersey: Prentice Hall...users. It is possible for a single user to consume all available bandwidth. Hop limits are programmed during EPLRS 8 network planning. CSMA

Si-based optical I/O for optical memory interface

NASA Astrophysics Data System (ADS)

Ha, Kyoungho; Shin, Dongjae; Byun, Hyunil; Cho, Kwansik; Na, Kyoungwon; Ji, Hochul; Pyo, Junghyung; Hong, Seokyong; Lee, Kwanghyun; Lee, Beomseok; Shin, Yong-hwack; Kim, Junghye; Kim, Seong-gu; Joe, Insung; Suh, Sungdong; Choi, Sanghoon; Han, Sangdeok; Park, Yoondong; Choi, Hanmei; Kuh, Bongjin; Kim, Kichul; Choi, Jinwoo; Park, Sujin; Kim, Hyeunsu; Kim, Kiho; Choi, Jinyong; Lee, Hyunjoo; Yang, Sujin; Park, Sungho; Lee, Minwoo; Cho, Minchang; Kim, Saebyeol; Jeong, Taejin; Hyun, Seokhun; Cho, Cheongryong; Kim, Jeong-kyoum; Yoon, Hong-gu; Nam, Jeongsik; Kwon, Hyukjoon; Lee, Hocheol; Choi, Junghwan; Jang, Sungjin; Choi, Joosun; Chung, Chilhee

2012-01-01

Optical interconnects may provide solutions to the capacity-bandwidth trade-off of recent memory interface systems. For cost-effective optical memory interfaces, Samsung Electronics has been developing silicon photonics platforms on memory-compatible bulk-Si 300-mm wafers. The waveguide of 0.6 dB/mm propagation loss, vertical grating coupler of 2.7 dB coupling loss, modulator of 10 Gbps speed, and Ge/Si photodiode of 12.5 Gbps bandwidth have been achieved on the bulk-Si platform. 2x6.4 Gbps electrical driver circuits have been also fabricated using a CMOS process.

Grain-size considerations for optoelectronic multistage interconnection networks.

PubMed

Krishnamoorthy, A V; Marchand, P J; Kiamilev, F E; Esener, S C

1992-09-10

This paper investigates, at the system level, the performance-cost trade-off between optical and electronic interconnects in an optoelectronic interconnection network. The specific system considered is a packet-switched, free-space optoelectronic shuffle-exchange multistage interconnection network (MIN). System bandwidth is used as the performance measure, while system area, system power, and system volume constitute the cost measures. A detailed design and analysis of a two-dimensional (2-D) optoelectronic shuffle-exchange routing network with variable grain size K is presented. The architecture permits the conventional 2 x 2 switches or grains to be generalized to larger K x K grain sizes by replacing optical interconnects with electronic wires without affecting the functionality of the system. Thus the system consists of log(k) N optoelectronic stages interconnected with free-space K-shuffles. When K = N, the MIN consists of a single electronic stage with optical input-output. The system design use an effi ient 2-D VLSI layout and a single diffractive optical element between stages to provide the 2-D K-shuffle interconnection. Results indicate that there is an optimum range of grain sizes that provides the best performance per cost. For the specific VLSI/GaAs multiple quantum well technology and system architecture considered, grain sizes larger than 256 x 256 result in a reduced performance, while grain sizes smaller than 16 x 16 have a high cost. For a network with 4096 channels, the useful range of grain sizes corresponds to approximately 250-400 electronic transistors per optical input-output channel. The effect of varying certain technology parameters such as the number of hologram phase levels, the modulator driving voltage, the minimum detectable power, and VLSI minimum feature size on the optimum grain-size system is studied. For instance, results show that using four phase levels for the interconnection hologram is a good compromise for the cost functions mentioned above. As VLSI minimum feature sizes decrease, the optimum grain size increases, whereas, if optical interconnect performance in terms of the detector power or modulator driving voltage requirements improves, the optimum grain size may be reduced. Finally, several architectural modifications to the system, such as K x K contention-free switches and sorting networks, are investigated and optimized for grain size. Results indicate that system bandwidth can be increased, but at the price of reduced performance/cost. The optoelectronic MIN architectures considered thus provide a broad range of performance/cost alternatives and offer a superior performance over purely electronic MIN's.

Linear and passive silicon diodes, isolators, and logic gates

NASA Astrophysics Data System (ADS)

Li, Zhi-Yuan

2013-12-01

Silicon photonic integrated devices and circuits have offered a promising means to revolutionalize information processing and computing technologies. One important reason is that these devices are compatible with conventional complementary metal oxide semiconductor (CMOS) processing technology that overwhelms current microelectronics industry. Yet, the dream to build optical computers has yet to come without the breakthrough of several key elements including optical diodes, isolators, and logic gates with low power, high signal contrast, and large bandwidth. Photonic crystal has a great power to mold the flow of light in micrometer/nanometer scale and is a promising platform for optical integration. In this paper we present our recent efforts of design, fabrication, and characterization of ultracompact, linear, passive on-chip optical diodes, isolators and logic gates based on silicon two-dimensional photonic crystal slabs. Both simulation and experiment results show high performance of these novel designed devices. These linear and passive silicon devices have the unique properties of small fingerprint, low power request, large bandwidth, fast response speed, easy for fabrication, and being compatible with COMS technology. Further improving their performance would open up a road towards photonic logics and optical computing and help to construct nanophotonic on-chip processor architectures for future optical computers.

Ultrahigh Responsivity-Bandwidth Product in a Compact InP Nanopillar Phototransistor Directly Grown on Silicon

NASA Astrophysics Data System (ADS)

Ko, Wai Son; Bhattacharya, Indrasen; Tran, Thai-Truong D.; Ng, Kar Wei; Adair Gerke, Stephen; Chang-Hasnain, Connie

2016-09-01

Highly sensitive and fast photodetectors can enable low power, high bandwidth on-chip optical interconnects for silicon integrated electronics. III-V compound semiconductor direct-bandgap materials with high absorption coefficients are particularly promising for photodetection in energy-efficient optical links because of the potential to scale down the absorber size, and the resulting capacitance and dark current, while maintaining high quantum efficiency. We demonstrate a compact bipolar junction phototransistor with a high current gain (53.6), bandwidth (7 GHz) and responsivity (9.5 A/W) using a single crystalline indium phosphide nanopillar directly grown on a silicon substrate. Transistor gain is obtained at sub-picowatt optical power and collector bias close to the CMOS line voltage. The quantum efficiency-bandwidth product of 105 GHz is the highest for photodetectors on silicon. The bipolar junction phototransistor combines the receiver front end circuit and absorber into a monolithic integrated device, eliminating the wire capacitance between the detector and first amplifier stage.

Ultrahigh Responsivity-Bandwidth Product in a Compact InP Nanopillar Phototransistor Directly Grown on Silicon

PubMed Central

Ko, Wai Son; Bhattacharya, Indrasen; Tran, Thai-Truong D.; Ng, Kar Wei; Adair Gerke, Stephen; Chang-Hasnain, Connie

2016-01-01

Highly sensitive and fast photodetectors can enable low power, high bandwidth on-chip optical interconnects for silicon integrated electronics. III-V compound semiconductor direct-bandgap materials with high absorption coefficients are particularly promising for photodetection in energy-efficient optical links because of the potential to scale down the absorber size, and the resulting capacitance and dark current, while maintaining high quantum efficiency. We demonstrate a compact bipolar junction phototransistor with a high current gain (53.6), bandwidth (7 GHz) and responsivity (9.5 A/W) using a single crystalline indium phosphide nanopillar directly grown on a silicon substrate. Transistor gain is obtained at sub-picowatt optical power and collector bias close to the CMOS line voltage. The quantum efficiency-bandwidth product of 105 GHz is the highest for photodetectors on silicon. The bipolar junction phototransistor combines the receiver front end circuit and absorber into a monolithic integrated device, eliminating the wire capacitance between the detector and first amplifier stage. PMID:27659796

Single-mode glass waveguide technology for optical interchip communication on board level

NASA Astrophysics Data System (ADS)

Brusberg, Lars; Neitz, Marcel; Schröder, Henning

2012-01-01

The large bandwidth demand in long-distance telecom networks lead to single-mode fiber interconnects as result of low dispersion, low loss and dense wavelength multiplexing possibilities. In contrast, multi-mode interconnects are suitable for much shorter lengths up to 300 meters and are promising for optical links between racks and on board level. Active optical cables based on multi-mode fiber links are at the market and research in multi-mode waveguide integration on board level is still going on. Compared to multi-mode, a single-mode waveguide has much more integration potential because of core diameters of around 20% of a multi-mode waveguide by a much larger bandwidth. But light coupling in single-mode waveguides is much more challenging because of lower coupling tolerances. Together with the silicon photonics technology, a single-mode waveguide technology on board-level will be the straight forward development goal for chip-to-chip optical interconnects integration. Such a hybrid packaging platform providing 3D optical single-mode links bridges the gap between novel photonic integrated circuits and the glass fiber based long-distance telecom networks. Following we introduce our 3D photonic packaging approach based on thin glass substrates with planar integrated optical single-mode waveguides for fiber-to-chip and chip-to-chip interconnects. This novel packaging approach merges micro-system packaging and glass integrated optics. It consists of a thin glass substrate with planar integrated singlemode waveguide circuits, optical mirrors and lenses providing an integration platform for photonic IC assembly and optical fiber interconnect. Thin glass is commercially available in panel and wafer formats and characterizes excellent optical and high-frequency properties. That makes it perfect for microsystem packaging. The paper presents recent results in single-mode waveguide technology on wafer level and waveguide characterization. Furthermore the integration in a hybrid packaging process and design issues are discussed.

Analog and RF performance of a multigate FinFET at nano scale

NASA Astrophysics Data System (ADS)

Kumar, Abhishek

2016-12-01

In this paper, analog and RF performance of the Fin field effect transistor (FET) at Nano scale is observed through 3D simulation. FinFET devices like rectangular gate all around (RE-GAA) FinFET, cylindrical gate all around (CY-GAA) FinFET and triple gate (TG) FinFET are observed. The figure of merit (FOMs) such as input-output characteristics, trans-conductance (gm), output-conductance (gd), intrinsic gain (gm/gd), gate capacitance (gate to source and total gate capacitance), unity gain cut-off frequency (ft), trans-conductance generation factor (TGF), gain frequency product (GFP), gain bandwidth product (GBP) and gain transconductance frequency product (GTFP) are observed. The analog performance of a FinFETs are observed by realising source follower circuit with NMOS transistor as a current source. The source follower circuit gain is observed. It has been observed that maximum capacitance is observed in case gate all around condition. Rectangular gate all around has the highest transconductance. In the source follower circuit, the gain curve (Vout/Vin) is sharper for TG-FinFET.

112 Gb/s sub-cycle 16-QAM Nyquist-SCM for intra-datacenter connectivity

NASA Astrophysics Data System (ADS)

Bakopoulos, Paraskevas; Dris, Stefanos; Argyris, Nikolaos; Spatharakis, Christos; Avramopoulos, Hercules

2016-03-01

Datacenter traffic is exploding. Ongoing advancements in network infrastructure that ride on Moore's law are unable to keep up, necessitating the introduction of multiplexing and advanced modulation formats for optical interconnects in order to overcome bandwidth limitations, and scale lane speeds with energy- and cost-efficiency to 100 Gb/s and beyond. While the jury is still out as to how this will be achieved, schemes relying on intensity modulation with direct detection (IM/DD) are regarded as particularly attractive, due to their inherent implementation simplicity. Moreover, the scaling-out of datacenters calls for longer transmission reach exceeding 300 m, requiring single-mode solutions. In this work we advocate using 16-QAM sub-cycle Nyquist-SCM as a simpler alternative to discrete multitone (DMT), but which is still more bandwidth-efficient than PAM-4. The proposed optical interconnect is demonstrated at 112 Gb/s, which, to the best of our knowledge, is the highest rate achieved in a single-polarization implementation of SCM. Off-the-shelf components are used: A DFB laser, a 24.3 GHz electro-absorption modulator (EAM) and a limiting photoreceiver, combined with equalization through digital signal processing (DSP) at the receiver. The EAM is driven by a low-swing (<1 V) arbitrary waveform generator (AWG), which produces a 28 Gbaud 16-QAM electrical signal with carrier frequency at ~15 GHz. Tight spectral shaping is leveraged as a means of maintaining signal fidelity when using low-bandwidth electro-optic components; matched root-raised-cosine transmit and receive filters with 0.1 excess bandwidth are thus employed. Performance is assessed through transmission experiments over 1250 m and 2000 m of SMF.

Interconnect-free parallel logic circuits in a single mechanical resonator

PubMed Central

Mahboob, I.; Flurin, E.; Nishiguchi, K.; Fujiwara, A.; Yamaguchi, H.

2011-01-01

In conventional computers, wiring between transistors is required to enable the execution of Boolean logic functions. This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds. A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable. Here, we demonstrate a novel logic architecture using only a single electromechanical parametric resonator into which multiple channels of binary information are encoded as mechanical oscillations at different frequencies. The parametric resonator can mix these channels, resulting in new mechanical oscillation states that enable the construction of AND, OR and XOR logic gates as well as multibit logic circuits. Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator. PMID:21326230

Interconnect-free parallel logic circuits in a single mechanical resonator.

PubMed

Mahboob, I; Flurin, E; Nishiguchi, K; Fujiwara, A; Yamaguchi, H

2011-02-15

In conventional computers, wiring between transistors is required to enable the execution of Boolean logic functions. This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds. A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable. Here, we demonstrate a novel logic architecture using only a single electromechanical parametric resonator into which multiple channels of binary information are encoded as mechanical oscillations at different frequencies. The parametric resonator can mix these channels, resulting in new mechanical oscillation states that enable the construction of AND, OR and XOR logic gates as well as multibit logic circuits. Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator.

Limits on Interconnection Bandwidth for On-Board Processing

NASA Technical Reports Server (NTRS)

Lux, James P.

2006-01-01

This viewgraph presentation reviews the constraints, and concerns of spacecraft design, in particular spacecraft instrumentation design and the issues concerning space communication. The advantages and disadvantages of several communication options are reviewed. Ultimately there will be spacecraft communication not between boxes on spacecraft, but between spacecraft. The future of spacecraft communication is interplanetary networks.

Thick-SOI Echelle grating for any-to-any wavelength routing interconnection in multi-socket computing environments

NASA Astrophysics Data System (ADS)

Dabos, G.; Pitris, S.; Mitsolidou, C.; Alexoudi, T.; Fitsios, D.; Cherchi, M.; Harjanne, M.; Aalto, T.; Kanellos, G. T.; Pleros, N.

2017-02-01

As data centers constantly expand, electronic switches are facing the challenge of enhanced scalability and the request for increased pin-count and bandwidth. Photonic technology and wavelength division multiplexing have always been a strong alternative for efficient routing and their potential was already proven in the telecoms. CWDM transceivers have emerged in the board-to-board level interconnection, revealing the potential for wavelength-routing to be applied in the datacom and an AWGR-based approach has recently been proposed towards building an optical multi-socket interconnection to offer any-to-any connectivity with high aggregated throughput and reduced power consumption. Echelle gratings have long been recognized as the multiplexing block exhibiting smallest footprint and robustness in a wide number of applications compared to other alternatives such as the Arrayed Waveguide Grating. Such filtering devices can also perform in a similar way to cyclical AWGR and serve as mid-board routing platforms in multi-socket environments. In this communication, we present such a 3x3 Echelle grating integrated on thick SOI platform with aluminum-coated facets that is shown to perform successful wavelength-routing functionality at 10 Gb/s. The device exhibits a footprint of 60x270 μm2, while the static characterization showed a 3 dB on-chip loss for the best channel. The 3 dB-bandwidth of the channels was 4.5 nm and the free spectral range was 90 nm. The echelle was evaluated in a 2x2 wavelength routing topology, exhibiting a power penalty of below 0.4 dB at 10-9 BER for the C-band. Further experimental evaluations of the platform involve commercially available CWDM datacenter transceivers, towards emulating an optically-interconnected multi-socket environment traffic scenario.

Multi-gigabit optical interconnects for next-generation on-board digital equipment

NASA Astrophysics Data System (ADS)

Venet, Norbert; Favaro, Henri; Sotom, Michel; Maignan, Michel; Berthon, Jacques

2017-11-01

Parallel optical interconnects are experimentally assessed as a technology that may offer the high-throughput data communication capabilities required to the next-generation on-board digital processing units. An optical backplane interconnect was breadboarded, on the basis of a digital transparent processor that provides flexible connectivity and variable bandwidth in telecom missions with multi-beam antenna coverage. The unit selected for the demonstration required that more than tens of Gbit/s be supported by the backplane. The demonstration made use of commercial parallel optical link modules at 850 nm wavelength, with 12 channels running at up to 2.5 Gbit/s. A flexible optical fibre circuit was developed so as to route board-to-board connections. It was plugged to the optical transmitter and receiver modules through 12-fibre MPO connectors. BER below 10-14 and optical link budgets in excess of 12 dB were measured, which would enable to integrate broadcasting. Integration of the optical backplane interconnect was successfully demonstrated by validating the overall digital processor functionality.

Multi-gigabit optical interconnects for next-generation on-board digital equipment

NASA Astrophysics Data System (ADS)

Venet, Norbert; Favaro, Henri; Sotom, Michel; Maignan, Michel; Berthon, Jacques

2004-06-01

Parallel optical interconnects are experimentally assessed as a technology that may offer the high-throughput data communication capabilities required to the next-generation on-board digital processing units. An optical backplane interconnect was breadboarded, on the basis of a digital transparent processor that provides flexible connectivity and variable bandwidth in telecom missions with multi-beam antenna coverage. The unit selected for the demonstration required that more than tens of Gbit/s be supported by the backplane. The demonstration made use of commercial parallel optical link modules at 850 nm wavelength, with 12 channels running at up to 2.5 Gbit/s. A flexible optical fibre circuit was developed so as to route board-to-board connections. It was plugged to the optical transmitter and receiver modules through 12-fibre MPO connectors. BER below 10-14 and optical link budgets in excess of 12 dB were measured, which would enable to integrate broadcasting. Integration of the optical backplane interconnect was successfully demonstrated by validating the overall digital processor functionality.

Simulation of the effects of proposed tide gates on circulation, flushing, and water quality in residential canals, Cape Coral Florida

USGS Publications Warehouse

Goodwin, Carl R.

1991-01-01

Decades of dredging and filling of Florida's low-lying coastal wetlands have produced thousands of miles of residential tidal canals and adjacent waterfront property. Typically, these canals are poorly flushed, and over time, accumulated organic-rich bottom materials, contribute to an increasingly severe degraded water quality. One-dimensional hydrodynamic and constituent-transport models were applied to two dead-end canal systems to determine the effects of canal system interconnection using tide gates on water circulation and constituent flushing. The model simulates existing and possible future circulation and flushing conditions in about 29 miles of the approximately 130 miles of tidally influenced canals in Cape Coral, located on the central west coast of peninsular Florida. Model results indicate that tidal water-level differences between the two canal systems can be converted to kinetic energy, in the form of increased water circulation, but the use of one-way tide gate interconnections. Computations show that construction of from one to four tide gates will cause replacement of a volume of water equivalent to the total volume of canals in both systems in 15 to 9 days, respectively. Because some canals flush faster than others, 47 and 21 percent of the original canal water will remain in both systems 50 days after start of operation of one and four tide gates, respectively. Some of the effects that such increased flushing are expected to have include reduced density stratification and associated dissolved-oxygen depletion in canal bottom waters, increased localized reaeration, and more efficient discharge of stormwater runoff entering the canals.

Silicon quantum processor with robust long-distance qubit couplings.

PubMed

Tosi, Guilherme; Mohiyaddin, Fahd A; Schmitt, Vivien; Tenberg, Stefanie; Rahman, Rajib; Klimeck, Gerhard; Morello, Andrea

2017-09-06

Practical quantum computers require a large network of highly coherent qubits, interconnected in a design robust against errors. Donor spins in silicon provide state-of-the-art coherence and quantum gate fidelities, in a platform adapted from industrial semiconductor processing. Here we present a scalable design for a silicon quantum processor that does not require precise donor placement and leaves ample space for the routing of interconnects and readout devices. We introduce the flip-flop qubit, a combination of the electron-nuclear spin states of a phosphorus donor that can be controlled by microwave electric fields. Two-qubit gates exploit a second-order electric dipole-dipole interaction, allowing selective coupling beyond the nearest-neighbor, at separations of hundreds of nanometers, while microwave resonators can extend the entanglement to macroscopic distances. We predict gate fidelities within fault-tolerance thresholds using realistic noise models. This design provides a realizable blueprint for scalable spin-based quantum computers in silicon.Quantum computers will require a large network of coherent qubits, connected in a noise-resilient way. Tosi et al. present a design for a quantum processor based on electron-nuclear spins in silicon, with electrical control and coupling schemes that simplify qubit fabrication and operation.

Distributed fiber optic vibration sensor with enhanced response bandwidth and high signal-to-noise ratio

NASA Astrophysics Data System (ADS)

Chen, Dian; Liu, Qingwen; Fan, Xinyu; He, Zuyuan

2017-04-01

A novel distributed fiber-optic vibration sensor (DVS) is proposed based on multi-pulse time-gated digital optical frequency domain reflectometry (TGD-OFDR), which can solve both the trade-off between the maximum measurable distance and the spatial resolution, and the one between the measurement distance and the vibration response bandwidth. A 21-kHz vibration is detected experimentally over 10-kilometer-long fiber, with a signal-to-noise ratio approaching 25 dB and a spatial resolution of 10 m.

Livermore Big Artificial Neural Network Toolkit

DOE Office of Scientific and Technical Information (OSTI.GOV)

Essen, Brian Van; Jacobs, Sam; Kim, Hyojin

2016-07-01

LBANN is a toolkit that is designed to train artificial neural networks efficiently on high performance computing architectures. It is optimized to take advantages of key High Performance Computing features to accelerate neural network training. Specifically it is optimized for low-latency, high bandwidth interconnects, node-local NVRAM, node-local GPU accelerators, and high bandwidth parallel file systems. It is built on top of the open source Elemental distributed-memory dense and spars-direct linear algebra and optimization library that is released under the BSD license. The algorithms contained within LBANN are drawn from the academic literature and implemented to work within a distributed-memory framework.

Practical Aspects of Access Network Indoor Extensions Using Multimode Glass and Plastic Optical Fibers

NASA Astrophysics Data System (ADS)

Keiser, Gerd; Liu, Hao-Yu; Lu, Shao-Hsi; Devi Pukhrambam, Puspa

2012-07-01

Low-cost multimode glass and plastic optical fibers are attractive for high-capacity indoor telecom networks. Many existing buildings already have glass multimode fibers installed for local area network applications. Future indoor applications will use combinations of glass multimode fibers with plastic optical fibers that have low losses in the 850-nm-1,310-nm range. This article examines real-world link losses when randomly interconnecting glass and plastic fiber segments having factory-installed connectors. Potential interconnection issues include large variations in connector losses among randomly selected fiber segments, asymmetric link losses in bidirectional links, and variations in bandwidths among different types of fibers.

Novel Vertical Interconnects With 180 Degree Phase Shift for Amplifiers, Filters, and Integrated Antennas

NASA Technical Reports Server (NTRS)

Goverdhanam, Kavita; Simons, Rainee N.; Katehi, Linda P. B.; Burke, Thomas P. (Technical Monitor)

2001-01-01

In this paper, novel low loss, wide-band coplanar stripline technology for RF/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semiconductor devices and microelectromechanical systems (MEMS).

Optical-fiber-to-waveguide coupling using carbon-dioxide-laser-induced long-period fiber gratings.

PubMed

Bachim, Brent L; Ogunsola, Oluwafemi O; Gaylord, Thomas K

2005-08-15

Optical fibers are expected to play a role in chip-level and board-level optical interconnects because of limitations on the bandwidth and level of integration of electrical interconnects. Therefore, methods are needed to couple optical fibers directly to waveguides on chips and on boards. We demonstrate optical-fiber-to-waveguide coupling using carbon-dioxide laser-induced long-period fiber gratings (LPFGs). Such gratings can be written in standard fiber and offer wavelength multiplexing-demultiplexing performance. The coupler fabrication process and the characterization apparatus are presented. The operation and the wavelength response of a LPFG-based optical-fiber-to-waveguide directional coupler are demonstrated.

Thin Film Transistors On Plastic Substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

2004-01-20

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

A Novel Threshold Voltage Defined Multiplexer for Interconnect Camouflaging

DTIC Science & Technology

2017-03-01

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Universal programmable logic gate and routing method

NASA Technical Reports Server (NTRS)

Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Mojarradi, Mohammad M. (Inventor); Fijany, Amir (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Toomarian, Nikzad (Inventor)

2009-01-01

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Technical Reports Server (NTRS)

Sewell, James S.; Bozada, Christopher A.

1994-01-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Astrophysics Data System (ADS)

Sewell, James S.; Bozada, Christopher A.

1994-02-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Ultrafast laser inscription of 3D components for spatial multiplexing

NASA Astrophysics Data System (ADS)

Thomson, Robert R.

2016-02-01

The thirst for bandwidth in telecommunications networks is becoming ever larger due to bandwidth hungry applications such as video-on-demand. To further increase the bandwidth capacity, engineers are now seeking to imprint information on the last remaining degree of freedom of the lightwave carrier - space. This has given rise to the field of Space Division Multiplexing (SDM). In essence, the concept of SDM simple; we aim to use the different spatial modes of an optical fibre as multiplexed data transmission channels. These modes could either be in the form of separate singlemodes in a multicore optical fibre, individual spatial modes of a multimode fibre, or indeed the individual spatial modes of a multimode multicore optical fibre. Regardless of the particular "flavour" of SDM in question, it is clear that significant interfacing issues exist between the optical fibres used in SDM and the conventional single-mode planar lightwave circuits that are essential to process the light (e.g. arrayed waveguide gratings and splitters), and efficient interconnect technologies will be required. One fabrication technology that has emerged as a possible route to solve these interconnection issues is ultrafast laser inscription (ULI), which relies on the use of focused ultrashort laser pulses to directly inscribe three-dimensional waveguide structures inside a bulk dielectric. In this paper, I describe some of the work that has been conducted around the world to apply the unique waveguide fabrication capabilities of ULI to the development of 3D photonic components for applications in SDM.

Digital logic circuits in yeast with CRISPR-dCas9 NOR gates

PubMed Central

Gander, Miles W.; Vrana, Justin D.; Voje, William E.; Carothers, James M.; Klavins, Eric

2017-01-01

Natural genetic circuits enable cells to make sophisticated digital decisions. Building equally complex synthetic circuits in eukaryotes remains difficult, however, because commonly used components leak transcriptionally, do not arbitrarily interconnect or do not have digital responses. Here, we designed dCas9-Mxi1-based NOR gates in Saccharomyces cerevisiae that allow arbitrary connectivity and large genetic circuits. Because we used the chromatin remodeller Mxi1, our gates showed minimal leak and digital responses. We built a combinatorial library of NOR gates that directly convert guide RNA (gRNA) inputs into gRNA outputs, enabling the gates to be ‘wired' together. We constructed logic circuits with up to seven gRNAs, including repression cascades with up to seven layers. Modelling predicted the NOR gates have effectively zero transcriptional leak explaining the limited signal degradation in the circuits. Our approach enabled the largest, eukaryotic gene circuits to date and will form the basis for large, synthetic, cellular decision-making systems. PMID:28541304

Fabrication of Fresnel micro lens array in borosilicate glass by F2-laser ablation for glass interposer application

NASA Astrophysics Data System (ADS)

Brusberg, Lars; Neitz, Marcel; Schröder, Henning; Fricke-Begemann, Thomas; Ihlemann, Jürgen

2014-03-01

The future need for more bandwidth forces the development of optical transmission solutions for rack-to-rack, boardto- board and chip-to-chip interconnects. The goals are significant reduction of power consumption, highest density and potential for bandwidth scalability to overcome the limitations of the systems today with mostly copper based interconnects. For system integration the enabling of thin glass as a substrate material for electro-optical components with integrated micro-optics for efficient light coupling to integrated optical waveguides or fibers is becoming important. Our glass based packaging approach merges micro-system packaging and glass integrated optics. This kind of packaging consists of a thin glass substrate with integrated micro lenses providing a platform for photonic component assembly and optical fiber or waveguide interconnection. Thin glass is commercially available in panel and wafer size and characterizes excellent optical and high frequency properties. That makes it perfect for microsystem packaging. A suitable micro lens approach has to be comparable with different commercial glasses and withstand post-processing like soldering. A benefit of using laser ablated Fresnel lenses is the planar integration capability in the substrate for highest integration density. In the paper we introduce our glass based packaging concept and the Fresnel lens design for different scenarios like chip-to-fiber, chip-to-optical-printed-circuit-board coupling. Based on the design the Fresnel lenses were fabricated by using a 157 nm fluorine laser ablation system.

Plate-slot polymer waveguide modulator on silicon-on-insulator.

PubMed

Qiu, Feng; Spring, Andrew M; Hong, Jianxun; Yokoyama, Shiyoshi

2018-04-30

Electro-optic (EO) modulators are vital for efficient "electrical to optical" transitions and high-speed optical interconnects. In this work, we applied an EO polymer to demonstrate modulators on silicon-on-insulator substrates. The fabricated Mach-Zehnder interferometer (MZI) and ring resonator consist of a Si and TiO 2 slot, in which the EO polymer was embedded to realize a low-driving and large bandwidth modulation. The designed optical and electrical constructions are able to provide a highly concentrated TM mode with low propagation loss and effective EO properties. The fabricated MZI modulator shows a π-voltage-length product of 0.66 V·cm and a 3-dB bandwidth of 31 GHz. The measured EO activity is advantageous to exploit the ring modulator with a resonant tunability of 0.065 nm/V and a 3-dB modulation bandwidth up to 13 GHz.

Recent advancements towards green optical networks

NASA Astrophysics Data System (ADS)

Davidson, Alan; Glesk, Ivan; Buis, Adrianus; Wang, Junjia; Chen, Lawrence

2014-12-01

Recent years have seen a rapid growth in demand for ultra high speed data transmission with end users expecting fast, high bandwidth network access. With this rapid growth in demand, data centres are under pressure to provide ever increasing data rates through their networks and at the same time improve the quality of data handling in terms of reduced latency, increased scalability and improved channel speed for users. However as data rates increase, present technology based on well-established CMOS technology is becoming increasingly difficult to scale and consequently data networks are struggling to satisfy current network demand. In this paper the interrelated issues of electronic scalability, power consumption, limited copper interconnect bandwidth and the limited speed of CMOS electronics will be explored alongside the tremendous bandwidth potential of optical fibre based photonic networks. Some applications of photonics to help alleviate the speed and latency in data networks will be discussed.

Optical interconnection networks for high-performance computing systems

NASA Astrophysics Data System (ADS)

Biberman, Aleksandr; Bergman, Keren

2012-04-01

Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. Chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, offer unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of our work, we demonstrate such feasibility of waveguides, modulators, switches and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. We propose novel silicon photonic devices, subsystems, network topologies and architectures to enable unprecedented performance of these photonic interconnection networks. Furthermore, the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers.

Issues of nanoelectronics: a possible roadmap.

PubMed

Wang, Kang L

2002-01-01

In this review, we will discuss a possible roadmap in scaling a nanoelectronic device from today's CMOS technology to the ultimate limit when the device fails. In other words, at the limit, CMOS will have a severe short channel effect, significant power dissipation in its quiescent (standby) state, and problems related to other essential characteristics. Efforts to use structures such as the double gate, vertical surround gate, and SOI to improve the gate control have continually been made. Other types of structures using SiGe source/drain, asymmetric Schottky source/drain, and the like will be investigated as viable structures to achieve ultimate CMOS. In reaching its scaling limit, tunneling will be an issue for CMOS. The tunneling current through the gate oxide and between the source and drain will limit the device operation. When tunneling becomes significant, circuits may incorporate tunneling devices with CMOS to further increase the functionality per device count. We will discuss both the top-down and bottom-up approaches in attaining the nanometer scale and eventually the atomic scale. Self-assembly is used as a bottom-up approach. The state of the art is reviewed, and the challenges of the multiple-step processing in using the self-assembly approach are outlined. Another facet of the scaling trend is to decrease the number of electrons in devices, ultimately leading to single electrons. If the size of a single-electron device is scaled in such a way that the Coulomb self-energy is higher than the thermal energy (at room temperature), a single-electron device will be able to operate at room temperature. In principle, the speed of the device will be fast as long as the capacitance of the load is also scaled accordingly. The single-electron device will have a small drive current, and thus the load capacitance, including those of interconnects and fanouts, must be small to achieve a reasonable speed. However, because the increase in the density (and/or functionality) of integrated circuits is the principal driver, the wiring or interconnects will increase and become the bottleneck for the design of future high-density and high-functionality circuits, particularly for single-electron devices. Furthermore, the massive interconnects needed in the architecture used today will result in an increase in load capacitance. Thus for single-electron device circuits, it is critical to have minimal interconnect loads. And new types of architectures with minimal numbers of global interconnects will be needed. Cellular automata, which need only nearest-neighbor interconnects, are discussed as a plausible example. Other architectures such as neural networks are also possible. Examples of signal processing using cellular automata are discussed. Quantum computing and information processing are based on quantum mechanical descriptions of individual particles correlated among each other. A quantum bit or qubit is described as a linear superposition of the wave functions of a two-state system, for example, the spin of a particle. With the interaction of two qubits, they are connected in a "wireless fashion" using wave functions via quantum mechanical interaction, referred to as entanglement. The interconnection by the nonlocality of wave functions affords a massive parallel nature for computing or so-called quantum parallelism. We will describe the potential and solid-state implementations of quantum computing and information, using electron spin and/or nuclear spin in Si and Ge. Group IV elements have a long coherent time and other advantages. The example of using SiGe for g factor engineering will be described.

Field programmable gate arrays: Evaluation report for space-flight application

NASA Technical Reports Server (NTRS)

Sandoe, Mike; Davarpanah, Mike; Soliman, Kamal; Suszko, Steven; Mackey, Susan

1992-01-01

Field Programmable Gate Arrays commonly called FPGA's are the newer generation of field programmable devices and offer more flexibility in the logic modules they incorporate and in how they are interconnected. The flexibility, the number of logic building blocks available, and the high gate densities achievable are why users find FPGA's attractive. These attributes are important in reducing product development costs and shortening the development cycle. The aerospace community is interested in incorporating this new generation of field programmable technology in space applications. To this end, a consortium was formed to evaluate the quality, reliability, and radiation performance of FPGA's. This report presents the test results on FPGA parts provided by ACTEL Corporation.

A Gaussian framework for modeling effects of frequency-dependent attenuation, frequency-dependent scattering, and gating.

PubMed

Wear, Keith A

2002-11-01

For a wide range of applications in medical ultrasound, power spectra of received signals are approximately Gaussian. It has been established previously that an ultrasound beam with a Gaussian spectrum propagating through a medium with linear attenuation remains Gaussian. In this paper, Gaussian transformations are derived to model the effects of scattering (according to a power law, as is commonly applicable in soft tissues, especially over limited frequency ranges) and gating (with a Hamming window, a commonly used gate function). These approximations are shown to be quite accurate even for relatively broad band systems with fractional bandwidths approaching 100%. The theory is validated by experiments in phantoms consisting of glass particles suspended in agar.

Single channel 112Gbit/sec PAM4 at 56Gbaud with digital signal processing for data centers applications.

PubMed

Sadot, Dan; Dorman, G; Gorshtein, Albert; Sonkin, Eduard; Vidal, Or

2015-01-26

112Gbit/sec DSP-based single channel transmission of PAM4 at 56Gbaud over 15GHz of effective analog bandwidth is experimentally demonstrated. The DSP enables use of mature 25G optoelectronics for 2-10km datacenter intra-connections, and 8Tbit/sec over 80km interconnections between data centers.

High-frequency graphene voltage amplifier.

PubMed

Han, Shu-Jen; Jenkins, Keith A; Valdes Garcia, Alberto; Franklin, Aaron D; Bol, Ageeth A; Haensch, Wilfried

2011-09-14

While graphene transistors have proven capable of delivering gigahertz-range cutoff frequencies, applying the devices to RF circuits has been largely hindered by the lack of current saturation in the zero band gap graphene. Herein, the first high-frequency voltage amplifier is demonstrated using large-area chemical vapor deposition grown graphene. The graphene field-effect transistor (GFET) has a 6-finger gate design with gate length of 500 nm. The graphene common-source amplifier exhibits ∼5 dB low frequency gain with the 3 dB bandwidth greater than 6 GHz. This first AC voltage gain demonstration of a GFET is attributed to the clear current saturation in the device, which is enabled by an ultrathin gate dielectric (4 nm HfO(2)) of the embedded gate structures. The device also shows extrinsic transconductance of 1.2 mS/μm at 1 V drain bias, the highest for graphene FETs using large-scale graphene reported to date.

Monolithic InP strictly non-blocking 8×8 switch for high-speed WDM optical interconnection.

PubMed

Kwack, Myung-Joon; Tanemura, Takuo; Higo, Akio; Nakano, Yoshiaki

2012-12-17

A strictly non-blocking 8 × 8 switch for high-speed WDM optical interconnection is realized on InP by using the phased-array scheme for the first time. The matrix switch architecture consists of over 200 functional devices such as star couplers, phase-shifters and so on without any waveguide cross-section. We demonstrate ultra-broad optical bandwidth covering the entire C-band through several Input/Output ports combination with extinction ratio performance of more than 20dB. Also, nanoseconds reconfiguration time was successfully achieved by dynamic switching experiment. Error-free transmission was verified for 40-Gbps (10-Gbps × 4ch) WDM signal.

Flexible multimode polymer waveguides for high-speed short-reach communication links

NASA Astrophysics Data System (ADS)

Bamiedakis, N.; Shi, F.; Chu, D.; Penty, R. V.; White, I. H.

2018-02-01

Multimode polymer waveguides have attracted great interest for use in high-speed short-reach communication links as they can be cost-effectively integrated onto standard PCBs using conventional methods of the electronics industry and provide low loss (<0.04 dB/cm at 850 nm) and high bandwidth (>30 GHz×m) interconnection. The formation of such waveguides on flexible substrates can further provide flexible low-weight low-thickness interconnects and offer additional freedom in the implementation of high-speed short-reach optical links. These attributes make these flexible waveguides particularly attractive for use in low-cost detachable chip-to-chip links and in environments where weight and shape conformity become important, such as in cars and aircraft. However, the highly-multimoded nature of these waveguides raises important questions about their performance under severe flex due to mode loss and mode coupling. In this work therefore, we investigate the loss, crosstalk and bandwidth performance of such waveguides under out-of plane bending and in-plane twisting under different launch conditions and carry out data transmission tests at 40 Gb/s on a 1 m long spiral flexible waveguide under flexure. Excellent optical transmission characteristics are obtained while robust loss, crosstalk and bandwidth performance are demonstrated under flexure. Error-free (BER<10-12) 40 Gb/s data transmission is achieved over the 1 m long spiral waveguide for a 180° bend with a 4 mm radius. The obtained results demonstrate the excellent optical and mechanical properties of this technology and highlight its potential for use in real-world systems.

Particle Identification on an FPGA Accelerated Compute Platform for the LHCb Upgrade

NASA Astrophysics Data System (ADS)

Fäerber, Christian; Schwemmer, Rainer; Machen, Jonathan; Neufeld, Niko

2017-07-01

The current LHCb readout system will be upgraded in 2018 to a “triggerless” readout of the entire detector at the Large Hadron Collider collision rate of 40 MHz. The corresponding bandwidth from the detector down to the foreseen dedicated computing farm (event filter farm), which acts as the trigger, has to be increased by a factor of almost 100 from currently 500 Gb/s up to 40 Tb/s. The event filter farm will preanalyze the data and will select the events on an event by event basis. This will reduce the bandwidth down to a manageable size to write the interesting physics data to tape. The design of such a system is a challenging task, and the reason why different new technologies are considered and have to be investigated for the different parts of the system. For the usage in the event building farm or in the event filter farm (trigger), an experimental field programmable gate array (FPGA) accelerated computing platform is considered and, therefore, tested. FPGA compute accelerators are used more and more in standard servers such as for Microsoft Bing search or Baidu search. The platform we use hosts a general Intel CPU and a high-performance FPGA linked via the high-speed Intel QuickPath Interconnect. An accelerator is implemented on the FPGA. It is very likely that these platforms, which are built, in general, for high-performance computing, are also very interesting for the high-energy physics community. First, the performance results of smaller test cases performed at the beginning are presented. Afterward, a part of the existing LHCb RICH particle identification is tested and is ported to the experimental FPGA accelerated platform. We have compared the performance of the LHCb RICH particle identification running on a normal CPU with the performance of the same algorithm, which is running on the Xeon-FPGA compute accelerator platform.

AlGaN/GaN-on-Si monolithic power-switching device with integrated gate current booster

NASA Astrophysics Data System (ADS)

Han, Sang-Woo; Jo, Min-Gi; Kim, Hyungtak; Cho, Chun-Hyung; Cha, Ho-Young

2017-08-01

This study investigates the effects of a monolithic gate current booster integrated with an AlGaN/GaN-on-Si power-switching device. The integrated gate current booster was implemented by a single-stage inverter topology consisting of a recessed normally-off AlGaN/GaN MOS-HFET and a mesa resistor. The monolithically integrated gate current booster in a switching FET eliminated the parasitic elements caused by external interconnection and enabled fast switching operation. The gate charging and discharging currents were boosted by the integrated inverter, which significantly reduced both rise and fall times: the rise time was reduced from 626 to 41.26 ns, while the fall time was reduced from 554 to 42.19 ns by the single-stage inverter. When the packaged monolithic power chip was tested under 1 MHz hard-switching operation with VDD = 200 V, the switching loss was found to have been drastically reduced, from 5.27 to 0.55 W.

Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)

DOEpatents

Asaad, Sameh W; Bellofatto, Ralph E; Brezzo, Bernard; Haymes, Charles L; Kapur, Mohit; Parker, Benjamin D; Roewer, Thomas; Tierno, Jose A

2014-01-28

A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.

Improvement of multiprocessing performance by using optical centralized shared bus

NASA Astrophysics Data System (ADS)

Han, Xuliang; Chen, Ray T.

2004-06-01

With the ever-increasing need to solve larger and more complex problems, multiprocessing is attracting more and more research efforts. One of the challenges facing the multiprocessor designers is to fulfill in an effective manner the communications among the processes running in parallel on multiple multiprocessors. The conventional electrical backplane bus provides narrow bandwidth as restricted by the physical limitations of electrical interconnects. In the electrical domain, in order to operate at high frequency, the backplane topology has been changed from the simple shared bus to the complicated switched medium. However, the switched medium is an indirect network. It cannot support multicast/broadcast as effectively as the shared bus. Besides the additional latency of going through the intermediate switching nodes, signal routing introduces substantial delay and considerable system complexity. Alternatively, optics has been well known for its interconnect capability. Therefore, it has become imperative to investigate how to improve multiprocessing performance by utilizing optical interconnects. From the implementation standpoint, the existing optical technologies still cannot fulfill the intelligent functions that a switch fabric should provide as effectively as their electronic counterparts. Thus, an innovative optical technology that can provide sufficient bandwidth capacity, while at the same time, retaining the essential merits of the shared bus topology, is highly desirable for the multiprocessing performance improvement. In this paper, the optical centralized shared bus is proposed for use in the multiprocessing systems. This novel optical interconnect architecture not only utilizes the beneficial characteristics of optics, but also retains the desirable properties of the shared bus topology. Meanwhile, from the architecture standpoint, it fits well in the centralized shared-memory multiprocessing scheme. Therefore, a smooth migration with substantial multiprocessing performance improvement is expected. To prove the technical feasibility from the architecture standpoint, a conceptual emulation of the centralized shared-memory multiprocessing scheme is demonstrated on a generic PCI subsystem with an optical centralized shared bus.

Modularity Induced Gating and Delays in Neuronal Networks

PubMed Central

Shein-Idelson, Mark; Cohen, Gilad; Hanein, Yael

2016-01-01

Neural networks, despite their highly interconnected nature, exhibit distinctly localized and gated activation. Modularity, a distinctive feature of neural networks, has been recently proposed as an important parameter determining the manner by which networks support activity propagation. Here we use an engineered biological model, consisting of engineered rat cortical neurons, to study the role of modular topology in gating the activity between cell populations. We show that pairs of connected modules support conditional propagation (transmitting stronger bursts with higher probability), long delays and propagation asymmetry. Moreover, large modular networks manifest diverse patterns of both local and global activation. Blocking inhibition decreased activity diversity and replaced it with highly consistent transmission patterns. By independently controlling modularity and disinhibition, experimentally and in a model, we pose that modular topology is an important parameter affecting activation localization and is instrumental for population-level gating by disinhibition. PMID:27104350

Monolithic integration of a MOSFET with a MEMS device

DOEpatents

Bennett, Reid; Draper, Bruce

2003-01-01

An integrated microelectromechanical system comprises at least one MOSFET interconnected to at least one MEMS device on a common substrate. A method for integrating the MOSFET with the MEMS device comprises fabricating the MOSFET and MEMS device monolithically on the common substrate. Conveniently, the gate insulator, gate electrode, and electrical contacts for the gate, source, and drain can be formed simultaneously with the MEMS device structure, thereby eliminating many process steps and materials. In particular, the gate electrode and electrical contacts of the MOSFET and the structural layers of the MEMS device can be doped polysilicon. Dopant diffusion from the electrical contacts is used to form the source and drain regions of the MOSFET. The thermal diffusion step for forming the source and drain of the MOSFET can comprise one or more of the thermal anneal steps to relieve stress in the structural layers of the MEMS device.

Design of a scanning gate microscope for mesoscopic electron systems in a cryogen-free dilution refrigerator.

PubMed

Pelliccione, M; Sciambi, A; Bartel, J; Keller, A J; Goldhaber-Gordon, D

2013-03-01

We report on our design of a scanning gate microscope housed in a cryogen-free dilution refrigerator with a base temperature of 15 mK. The recent increase in efficiency of pulse tube cryocoolers has made cryogen-free systems popular in recent years. However, this new style of cryostat presents challenges for performing scanning probe measurements, mainly as a result of the vibrations introduced by the cryocooler. We demonstrate scanning with root-mean-square vibrations of 0.8 nm at 3 K and 2.1 nm at 15 mK in a 1 kHz bandwidth with our design. Using Coulomb blockade thermometry on a GaAs/AlGaAs gate-defined quantum dot, we demonstrate an electron temperature of 45 mK.

Single-channel recordings of RyR1 at microsecond resolution in CMOS-suspended membranes.

PubMed

Hartel, Andreas J W; Ong, Peijie; Schroeder, Indra; Giese, M Hunter; Shekar, Siddharth; Clarke, Oliver B; Zalk, Ran; Marks, Andrew R; Hendrickson, Wayne A; Shepard, Kenneth L

2018-02-20

Single-channel recordings are widely used to explore functional properties of ion channels. Typically, such recordings are performed at bandwidths of less than 10 kHz because of signal-to-noise considerations, limiting the temporal resolution available for studying fast gating dynamics to greater than 100 µs. Here we present experimental methods that directly integrate suspended lipid bilayers with high-bandwidth, low-noise transimpedance amplifiers based on complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC) technology to achieve bandwidths in excess of 500 kHz and microsecond temporal resolution. We use this CMOS-integrated bilayer system to study the type 1 ryanodine receptor (RyR1), a Ca 2+ -activated intracellular Ca 2+ -release channel located on the sarcoplasmic reticulum. We are able to distinguish multiple closed states not evident with lower bandwidth recordings, suggesting the presence of an additional Ca 2+ binding site, distinct from the site responsible for activation. An extended beta distribution analysis of our high-bandwidth data can be used to infer closed state flicker events as fast as 35 ns. These events are in the range of single-file ion translocations.

OM300 Direction Drilling Module

DOE Data Explorer

MacGugan, Doug

2013-08-22

OM300 – Geothermal Direction Drilling Navigation Tool: Design and produce a prototype directional drilling navigation tool capable of high temperature operation in geothermal drilling Accuracies of 0.1° Inclination and Tool Face, 0.5° Azimuth Environmental Ruggedness typical of existing oil/gas drilling Multiple Selectable Sensor Ranges High accuracy for navigation, low bandwidth High G-range & bandwidth for Stick-Slip and Chirp detection Selectable serial data communications Reduce cost of drilling in high temperature Geothermal reservoirs Innovative aspects of project Honeywell MEMS* Vibrating Beam Accelerometers (VBA) APS Flux-gate Magnetometers Honeywell Silicon-On-Insulator (SOI) High-temperature electronics Rugged High-temperature capable package and assembly process

A high performance cost-effective digital complex correlator for an X-band polarimetry survey.

PubMed

Bergano, Miguel; Rocha, Armando; Cupido, Luís; Barbosa, Domingos; Villela, Thyrso; Boas, José Vilas; Rocha, Graça; Smoot, George F

2016-01-01

The detailed knowledge of the Milky Way radio emission is important to characterize galactic foregrounds masking extragalactic and cosmological signals. The update of the global sky models describing radio emissions over a very large spectral band requires high sensitivity experiments capable of observing large sky areas with long integration times. Here, we present the design of a new 10 GHz (X-band) polarimeter digital back-end to map the polarization components of the galactic synchrotron radiation field of the Northern Hemisphere sky. The design follows the digital processing trends in radio astronomy and implements a large bandwidth (1 GHz) digital complex cross-correlator to extract the Stokes parameters of the incoming synchrotron radiation field. The hardware constraints cover the implemented VLSI hardware description language code and the preliminary results. The implementation is based on the simultaneous digitized acquisition of the Cartesian components of the two linear receiver polarization channels. The design strategy involves a double data rate acquisition of the ADC interleaved parallel bus, and field programmable gate array device programming at the register transfer mode. The digital core of the back-end is capable of processing 32 Gbps and is built around an Altera field programmable gate array clocked at 250 MHz, 1 GSps analog to digital converters and a clock generator. The control of the field programmable gate array internal signal delays and a convenient use of its phase locked loops provide the timing requirements to achieve the target bandwidths and sensitivity. This solution is convenient for radio astronomy experiments requiring large bandwidth, high functionality, high volume availability and low cost. Of particular interest, this correlator was developed for the Galactic Emission Mapping project and is suitable for large sky area polarization continuum surveys. The solutions may also be adapted to be used at signal processing subsystem levels for large projects like the square kilometer array testbeds.

A Bandwidth-Optimized Multi-Core Architecture for Irregular Applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Secchi, Simone; Tumeo, Antonino; Villa, Oreste

This paper presents an architecture template for next-generation high performance computing systems specifically targeted to irregular applications. We start our work by considering that future generation interconnection and memory bandwidth full-system numbers are expected to grow by a factor of 10. In order to keep up with such a communication capacity, while still resorting to fine-grained multithreading as the main way to tolerate unpredictable memory access latencies of irregular applications, we show how overall performance scaling can benefit from the multi-core paradigm. At the same time, we also show how such an architecture template must be coupled with specific techniquesmore » in order to optimize bandwidth utilization and achieve the maximum scalability. We propose a technique based on memory references aggregation, together with the related hardware implementation, as one of such optimization techniques. We explore the proposed architecture template by focusing on the Cray XMT architecture and, using a dedicated simulation infrastructure, validate the performance of our template with two typical irregular applications. Our experimental results prove the benefits provided by both the multi-core approach and the bandwidth optimization reference aggregation technique.« less

Results on 3D interconnection from AIDA WP3

NASA Astrophysics Data System (ADS)

Moser, Hans-Günther; AIDA-WP3

2016-09-01

From 2010 to 2014 the EU funded AIDA project established in one of its work packages (WP3) a network of groups working collaboratively on advanced 3D integration of electronic circuits and semiconductor sensors for applications in particle physics. The main motivation came from the severe requirements on pixel detectors for tracking and vertexing at future Particle Physics experiments at LHC, super-B factories and linear colliders. To go beyond the state-of-the-art, the main issues were studying low mass, high bandwidth applications, with radiation hardness capabilities, with low power consumption, offering complex functionality, with small pixel size and without dead regions. The interfaces and interconnects of sensors to electronic readout integrated circuits are a key challenge for new detector applications.

Optimized cross-resonance gate for coupled transmon systems

NASA Astrophysics Data System (ADS)

Kirchhoff, Susanna; Keßler, Torsten; Liebermann, Per J.; Assémat, Elie; Machnes, Shai; Motzoi, Felix; Wilhelm, Frank K.

2018-04-01

The cross-resonance (CR) gate is an entangling gate for fixed-frequency superconducting qubits. While being simple and extensible, it is comparatively slow, at 160 ns, and thus of limited fidelity due to on-going incoherent processes. Using two different optimal control algorithms, we estimate the quantum speed limit for a controlled-not cnot gate in this system to be 10 ns, indicating a potential for great improvements. We show that the ability to approach this limit depends strongly on the choice of ansatz used to describe optimized control pulses and limitations placed on their complexity. Using a piecewise-constant ansatz, with a single carrier and bandwidth constraints, we identify an experimentally feasible 70-ns pulse shape. Further, an ansatz based on the two dominant frequencies involved in the optimal control problem allows for an optimal solution more than twice as fast again, at under 30 ns, with smooth features and limited complexity. This is twice as fast as gate realizations using tunable-frequency, resonantly coupled qubits. Compared to current CR-gate implementations, we project our scheme will provide a sixfold speed-up and thus a sixfold reduction in fidelity loss due to incoherent effects.

Scaling induced performance challenges/limitations of on-chip metal interconnects and comparisons with optical interconnects

NASA Astrophysics Data System (ADS)

Kapur, Pawan

The miniaturization paradigm for silicon integrated circuits has resulted in a tremendous cost and performance advantage. Aggressive shrinking of devices provides faster transistors and a greater functionality for circuit design. However, scaling induced smaller wire cross-sections coupled with longer lengths owing to larger chip areas, result in a steady deterioration of interconnects. This degradation in interconnect trends threatens to slow down the rapid growth along Moore's law. This work predicts that the situation is worse than anticipated. It shows that in the light of technology and reliability constraints, scaling induced increase in electron surface scattering, fractional cross section area occupied by the highly resistive barrier, and realistic interconnect operation temperature will lead to a significant rise in effective resistivity of modern copper based interconnects. We start by discussing various technology factors affecting copper resistivity. We, next, develop simulation tools to model these effects. Using these tools, we quantify the increase in realistic copper resistivity as a function of future technology nodes, under various technology assumptions. Subsequently, we evaluate the impact of these technology effects on delay and power dissipation of global signaling interconnects. Modern long on-chip wires use repeaters, which dramatically improves their delay and bandwidth. We quantify the repeated wire delays and power dissipation using realistic resistance trends at future nodes. With the motivation of reducing power, we formalize a methodology, which trades power with delay very efficiently for repeated wires. Using this method, we find that although the repeater power comes down, the total power dissipation due to wires is still found to be very large at future nodes. Finally, we explore optical interconnects as a possible substitute, for specific interconnect applications. We model an optical receiver and waveguides. Using this we assess future optical system performance. Finally, we compare the delay and power of future metal interconnects with that of optical interconnects for global signaling application. We also compare the power dissipation of the two approaches for an upper level clock distribution application. We find that for long on-chip communication links, optical interconnects have lower latencies than future metal interconnects at comparable levels of power dissipation.

A Fully Reconfigurable Low-Noise Biopotential Sensing Amplifier With 1.96 Noise Efficiency Factor.

PubMed

Tzu-Yun Wang; Min-Rui Lai; Twigg, Christopher M; Sheng-Yu Peng

2014-06-01

A fully reconfigurable biopotential sensing amplifier utilizing floating-gate transistors is presented in this paper. By using the complementary differential pairs along with the current reuse technique, the theoretical limit for the noise efficiency factor of the proposed amplifier is below 1.5. Without consuming any extra power, floating-gate transistors are employed to program the low-frequency cutoff corner of the amplifier and to implement the common-mode feedback. A concept proving prototype chip was designed and fabricated in a 0.35 μm CMOS process occupying 0.17 mm (2) silicon area. With a supply voltage of 2.5 V, the measured midband gain is 40.7 dB and the measured input-referred noise is 2.8 μVrms. The chip was tested under several configurations with the amplifier bandwidth being programmed to 100 Hz, 1 kHz , and 10 kHz. The measured noise efficiency factors in these bandwidth settings are 1.96, 2.01, and 2.25, respectively, which are among the best numbers reported to date. The measured common-mode rejection and the supply rejection are above 70 dB . When the bandwidth is configured to be 10 kHz, the dynamic range measured at 1 kHz is 60 dB with total harmonic distortion less than 0.1%. The proposed amplifier is also demonstrated by recording electromyography (EMG), electrocardiography (ECG), electrooculography (EOG), and electroencephalography (EEG) signals from human bodies.

Wideband Monolithic Tile for Reconfigurable Phased Arrays

DTIC Science & Technology

2017-03-01

has been developed for Reconfigurable Phased Array applications. Low loss and high isolation interconnection of switches within the radiating...there is no ground to connect shunt elements to. An integral part of the design was bias control. Mesa resistors are used for biasing. MIM...highest in resistance had the best performance over bandwidth because of reduced capacitive loading of the “off” arms of the Quad Switch on the central

Neural dynamics in reconfigurable silicon.

PubMed

Basu, A; Ramakrishnan, S; Petre, C; Koziol, S; Brink, S; Hasler, P E

2010-10-01

A neuromorphic analog chip is presented that is capable of implementing massively parallel neural computations while retaining the programmability of digital systems. We show measurements from neurons with Hopf bifurcations and integrate and fire neurons, excitatory and inhibitory synapses, passive dendrite cables, coupled spiking neurons, and central pattern generators implemented on the chip. This chip provides a platform for not only simulating detailed neuron dynamics but also uses the same to interface with actual cells in applications such as a dynamic clamp. There are 28 computational analog blocks (CAB), each consisting of ion channels with tunable parameters, synapses, winner-take-all elements, current sources, transconductance amplifiers, and capacitors. There are four other CABs which have programmable bias generators. The programmability is achieved using floating gate transistors with on-chip programming control. The switch matrix for interconnecting the components in CABs also consists of floating-gate transistors. Emphasis is placed on replicating the detailed dynamics of computational neural models. Massive computational area efficiency is obtained by using the reconfigurable interconnect as synaptic weights, resulting in more than 50 000 possible 9-b accurate synapses in 9 mm(2).

Petahertz optical oscilloscope

NASA Astrophysics Data System (ADS)

Kim, Kyung Taec; Zhang, Chunmei; Shiner, Andrew D.; Schmidt, Bruno E.; Légaré, François; Villeneuve, D. M.; Corkum, P. B.

2013-12-01

The time-dependent field of an electromagnetic pulse can be measured if there is a fast enough gate. For terahertz radiation, femtosecond photoinjection of free carriers into a semiconductor in the presence of the terahertz radiation can serve as the gate. For visible or infrared radiation, attosecond photoionization of a gas target in the presence of the optical field is a direct analogue. Here, we show that nonlinear optical mixing in a medium in which attosecond pulses are being generated can also be used to measure the time-dependent field of an optical pulse. The gate is the phase accumulated by the recollision electron during the subcycle time interval between ionization and recombination. We show that the instantaneous field of an unknown pulse is imprinted onto the deflection of the attosecond extreme ultraviolet pulse using an all-optical set-up with a bandwidth up to 1 PHz.

High-aggregate-capacity visible light communication links using stacked multimode polymer waveguides and micro-pixelated LED arrays

NASA Astrophysics Data System (ADS)

Bamiedakis, N.; McKendry, J. J. D.; Xie, E.; Gu, E.; Dawson, M. D.; Penty, R. V.; White, I. H.

2018-02-01

In recent years, light emitting diodes (LEDs) have gained renewed interest for use in visible light communication links (VLC) owing to their potential use as both high-quality power-efficient illumination sources as well as low-cost optical transmitters in free-space and guided-wave links. Applications that can benefit from their use include optical wireless systems (LiFi and Internet of Things), in-home and automotive networks, optical USBs and short-reach low-cost optical interconnects. However, VLC links suffer from the limited LED bandwidth (typically 100 MHz). As a result, a combination of novel LED devices, advanced modulation formats and multiplexing methods are employed to overcome this limitation and achieve high-speed (>1 Gb/s) data transmission over such links. In this work, we present recent advances in the formation of high-aggregate-capacity low cost guided wave VLC links using stacked polymer multimode waveguides and matching micro-pixelated LED (μLED) arrays. μLEDs have been shown to exhibit larger bandwidths (>200 MHz) than conventional broad-area LEDs and can be formed in large array configurations, while multimode polymer waveguides enable the formation of low-cost optical links onto standard PCBs. Here, three- and four-layered stacks of multimode waveguides, as well as matching GaN μLED arrays, are fabricated in order to generate high-density yet low-cost optical interconnects. Different waveguide topologies are implemented and are investigated in terms of loss and crosstalk performance. The initial results presented herein demonstrate good intrinsic crosstalk performance and indicate the potential to achieve >= 0.5 Tb/s/mm2 aggregate interconnection capacity using this low-cost technology.

Interconnected magnetic tunnel junctions for spin-logic applications

NASA Astrophysics Data System (ADS)

Manfrini, Mauricio; Vaysset, Adrien; Wan, Danny; Raymenants, Eline; Swerts, Johan; Rao, Siddharth; Zografos, Odysseas; Souriau, Laurent; Gavan, Khashayar Babaei; Rassoul, Nouredine; Radisic, Dunja; Cupak, Miroslav; Dehan, Morin; Sayan, Safak; Nikonov, Dmitri E.; Manipatruni, Sasikanth; Young, Ian A.; Mocuta, Dan; Radu, Iuliana P.

2018-05-01

With the rapid progress of spintronic devices, spin-logic concepts hold promises of energy-delay conscious computation for efficient logic gate operations. We report on the electrical characterization of domain walls in interconnected magnetic tunnel junctions. By means of spin-transfer torque effect, domains walls are produced at the common free layer and its propagation towards the output pillar sensed by tunneling magneto-resistance. Domain pinning conditions are studied quasi-statically showing a strong dependence on pillar size, ferromagnetic free layer width and inter-pillar distance. Addressing pinning conditions are detrimental for cascading and fan-out of domain walls across nodes, enabling the realization of domain-wall-based logic technology.

DOE-FG02-00ER62797 Final Report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sweedler, J.V.

2004-12-01

Specific Aims The overall goal of this proposal has been to develop and interface a new technology, molecular gates, with microfabricated systems to add an important capability to microfabricated DNA measurement systems. This project specifically focused on demonstrating how molecular gates could be used to capture a single analyte band, among a stream of bands from a separation or a flow injection analysis experiment, and release it for later measurement, thus allowing further manipulations on the selected analyte. Since the original proposal, the molecular gate concept has been greatly expanded to allow the gates to be used as externally controllablemore » intelligent interconnects in multilayer microfluidic networks. We have demonstrated: (1) the ability of the molecular gates to work with a much wider range of biological molecules including DNA, proteins and small metabolites; and (2) the capability of performing an electrophoretic separation and sequestering individual picoliter volume components (or even classes of components) into separate channels for further analysis. Both capabilities will enable characterization of small mass amounts of complex mixtures of DNA, proteins and even small molecules--allowing them to be further separated and chemically characterized.« less

K-Band Substrate Integrated Waveguide (SIW) Coupler

NASA Astrophysics Data System (ADS)

Khalid, N.; Ibrahim, S. Z.; Hoon, W. F.

2018-03-01

This paper presents a designed coupler by using substrate Roger RO4003. The four port network coupler operates at (18-26 GHz) and designed by using substrate integrated waveguide (SIW) method. Substrate Integrated Waveguide (SIW) are high performance broadband interconnects with excellent immunity to electromagnetic interference and suitable in microwave and millimetre-wave electronics applications, as well as wideband systems. The designs of the coupler are investigated using CST Microwave Studio simulation tool. These proposed couplers are capable of covering the frequency range and provide better performance of scattering parameter (S-parameter). This technology is successfully approached for millimetre-wave and microwave applications. Designs and results are presented and discussed in this paper. The overall simulated percentage bandwidth of the proposed coupler is covered from 18 to 26 GHz with percentage bandwidth of 36.36%.

Review of Microwave Photonics Technique to Generate the Microwave Signal by Using Photonics Technology

NASA Astrophysics Data System (ADS)

Raghuwanshi, Sanjeev Kumar; Srivastav, Akash

2017-12-01

Microwave photonics system provides high bandwidth capabilities of fiber optic systems and also contains the ability to provide interconnect transmission properties, which are virtually independent of length. The low-loss wide bandwidth capability of optoelectronic systems makes them attractive for the transmission and processing of microwave signals, while the development of high-capacity optical communication systems has required the use of microwave techniques in optical transmitters and receivers. These two strands have led to the development of the research area of microwave photonics. So, we can considered microwave photonics as the field that studies the interaction between microwave and optical waves for applications such as communications, radars, sensors and instrumentations. In this paper we have thoroughly reviewed the microwave generation techniques by using photonics technology.

A CWDM photoreceiver module for 10 Gb/s x 4ch interconnection based on a vertical-illumination-type Ge-on-Si photodetectors and a silica-based AWG

NASA Astrophysics Data System (ADS)

Jang, Ki-Seok; Joo, Jiho; Kim, Taeyong; Kim, Sanghoon; Oh, Jin Hyuk; Kim, In Gyoo; Kim, Sun Ae; Kim, Gyungock

2015-03-01

We report a 40 Gb/s photoreceiver based on vertical-illumination type Ge-on-Si photodetectors and a silica-based AWG demultiplexer by employing 4-channel CWDM. The 60um-diameter Ge-on-Si photodetector arrays, grown on a bulk silicon wafer by RPCVD and fabricated with CMOS-compatible process, have ~0.9 A/W responsivity with 13 GHz bandwidth at λ ~ 1330nm. Ge-on-Si photodetector arrays are hybrid-integrated with TIA/LAs and directly-coupled to the AWG. The low-cost FPCB-package based photoreceiver module shows 10.3 Gb/s × 4-channel interconnection with -11 ~ -12.2 dBm sensitivity at a BER = 10-12.

Polymer waveguides for electro-optical integration in data centers and high-performance computers.

PubMed

Dangel, Roger; Hofrichter, Jens; Horst, Folkert; Jubin, Daniel; La Porta, Antonio; Meier, Norbert; Soganci, Ibrahim Murat; Weiss, Jonas; Offrein, Bert Jan

2015-02-23

To satisfy the intra- and inter-system bandwidth requirements of future data centers and high-performance computers, low-cost low-power high-throughput optical interconnects will become a key enabling technology. To tightly integrate optics with the computing hardware, particularly in the context of CMOS-compatible silicon photonics, optical printed circuit boards using polymer waveguides are considered as a formidable platform. IBM Research has already demonstrated the essential silicon photonics and interconnection building blocks. A remaining challenge is electro-optical packaging, i.e., the connection of the silicon photonics chips with the system. In this paper, we present a new single-mode polymer waveguide technology and a scalable method for building the optical interface between silicon photonics chips and single-mode polymer waveguides.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET.

PubMed

Tan, Michael Loong Peng; Lentaris, Georgios; Amaratunga Aj, Gehan

2012-08-19

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.

All-printed thin-film transistors from networks of liquid-exfoliated nanosheets

NASA Astrophysics Data System (ADS)

Kelly, Adam G.; Hallam, Toby; Backes, Claudia; Harvey, Andrew; Esmaeily, Amir Sajad; Godwin, Ian; Coelho, João; Nicolosi, Valeria; Lauth, Jannika; Kulkarni, Aditya; Kinge, Sachin; Siebbeles, Laurens D. A.; Duesberg, Georg S.; Coleman, Jonathan N.

2017-04-01

All-printed transistors consisting of interconnected networks of various types of two-dimensional nanosheets are an important goal in nanoscience. Using electrolytic gating, we demonstrate all-printed, vertically stacked transistors with graphene source, drain, and gate electrodes, a transition metal dichalcogenide channel, and a boron nitride (BN) separator, all formed from nanosheet networks. The BN network contains an ionic liquid within its porous interior that allows electrolytic gating in a solid-like structure. Nanosheet network channels display on:off ratios of up to 600, transconductances exceeding 5 millisiemens, and mobilities of >0.1 square centimeters per volt per second. Unusually, the on-currents scaled with network thickness and volumetric capacitance. In contrast to other devices with comparable mobility, large capacitances, while hindering switching speeds, allow these devices to carry higher currents at relatively low drive voltages.

Low profile, highly configurable, current sharing paralleled wide band gap power device power module

DOEpatents

McPherson, Brice; Killeen, Peter D.; Lostetter, Alex; Shaw, Robert; Passmore, Brandon; Hornberger, Jared; Berry, Tony M

2016-08-23

A power module with multiple equalized parallel power paths supporting multiple parallel bare die power devices constructed with low inductance equalized current paths for even current sharing and clean switching events. Wide low profile power contacts provide low inductance, short current paths, and large conductor cross section area provides for massive current carrying. An internal gate & source kelvin interconnection substrate is provided with individual ballast resistors and simple bolted construction. Gate drive connectors are provided on either left or right size of the module. The module is configurable as half bridge, full bridge, common source, and common drain topologies.

Influence of Germanium source on dopingless tunnel-FET for improved analog/RF performance

NASA Astrophysics Data System (ADS)

Cecil, Kanchan; Singh, Jawar

2017-01-01

Dopingless (DL) and junctionless devices have attracted attention due to their simplified fabrication process and low thermal budget requirements. Therefore, in this work, we investigated the influence of low band gap Germanium (Ge) instead of Silicon (Si) as a "Source region" material in dopingless (DL) tunnel field-effect transistor (DLTFET). We observed that the Ge source DLTFET delivers much better performance in comparison to Si DLTFET under various analog/RF figure of merits (FOMs), such as transconductance (gm), transconductance generation factor (TGF) (gm /Id), output conductance (gd), output resistance (RO), intrinsic gain (gmRO), intrinsic gate delay (τ) and RF FOMs, like unity gain frequency (fT), gain bandwidth product (GBW) along with various gate capacitances. These parameters were extracted using 2D TCAD device simulations through small signal ac analysis. Higher ION /IOFF ratio (1014) of Ge source DLTFET can reduce the dynamic as well as static power in digital circuits, while higher transconductance generation factor (gm /Id) ∼ 2287 V-1 can lower the bias power of an amplifier. Similarly, enhanced RF FOMs i.e unity gain frequency (fT) and gain bandwidth product (GBW) in Gigahertz range projects the proposed device preference for RF circuits.

Electro-optical logic gates based on graphene-silicon waveguides

NASA Astrophysics Data System (ADS)

Chen, Weiwei; Yang, Longzhi; Wang, Pengjun; Zhang, Yawei; Zhou, Liqiang; Yang, Tianjun; Wang, Yang; Yang, Jianyi

2016-08-01

In this paper, designs of electro-optical AND/NAND, OR/ NOR, XOR/XNOR logic gates based on cascaded silicon graphene switches and regular 2×1 multimode interference combiners are presented. Each switch consists of a Mach-Zehnder interferometer in which silicon slot waveguides embedded with graphene flakes are designed for phase shifters. High-speed switching function is achieved by applying an electrical signal to tune the Fermi levels of graphene flakes causing the variation of modal effective index. Calculation results show the crosstalk in the proposed optical switch is lower than -22.9 dB within a bandwidth from 1510 nm to 1600 nm. The designed six electro-optical logic gates with the operation speed of 10 Gbit/s have a minimum extinction ratio of 35.6 dB and a maximum insertion loss of 0.21 dB for transverse electric modes at 1.55 μm.

Flexible power and bandwidth allocation in mobile satellites

NASA Astrophysics Data System (ADS)

Keyes, L. A.

The introduction of L-band mobile communication services by spot beam satellites creates a payload design challenge due to uncertainty in the location and size of the new market to be served. A combination of payload technologies that allow a flexible allocation of power and bandwidth to any portion of the coverage area is described. Power flexibility is achieved by a novel combination of a low-level beam-forming network and a matrix power module which ensures equal sharing of power among individual amplifiers. This eliminates the loss of efficiency and increased mass when an amplifier associated with a beam must be over-designed to meet uncertainties in power distribution between beams. Flexibility in allocation of bandwidth to beams is achieved by intermediate frequency subdivision of the L-band service categories defined by ITU. These spectral subdivisions are assigned to beams by an IF interconnect matrix having beam ports and filter ports as inputs and outputs, respectively. Two such filter switch matrices are required, one for the inbound L-band to feeder link transponder, and one for the outbound feeder link to L-band transponder.

Towards energy-efficient photonic interconnects

NASA Astrophysics Data System (ADS)

Demir, Yigit; Hardavellas, Nikos

2015-03-01

Silicon photonics have emerged as a promising solution to meet the growing demand for high-bandwidth, low-latency, and energy-efficient on-chip and off-chip communication in many-core processors. However, current silicon-photonic interconnect designs for many-core processors waste a significant amount of power because (a) lasers are always on, even during periods of interconnect inactivity, and (b) microring resonators employ heaters which consume a significant amount of power just to overcome thermal variations and maintain communication on the photonic links, especially in a 3D-stacked design. The problem of high laser power consumption is particularly important as lasers typically have very low energy efficiency, and photonic interconnects often remain underutilized both in scientific computing (compute-intensive execution phases underutilize the interconnect), and in server computing (servers in Google-scale datacenters have a typical utilization of less than 30%). We address the high laser power consumption by proposing EcoLaser+, which is a laser control scheme that saves energy by predicting the interconnect activity and opportunistically turning the on-chip laser off when possible, and also by scaling the width of the communication link based on a runtime prediction of the expected message length. Our laser control scheme can save up to 62 - 92% of the laser energy, and improve the energy efficiency of a manycore processor with negligible performance penalty. We address the high trimming (heating) power consumption of the microrings by proposing insulation methods that reduce the impact of localized heating induced by highly-active components on the 3D-stacked logic die.

Optimal wavelength-space crossbar switches for supercomputer optical interconnects.

PubMed

Roudas, Ioannis; Hemenway, B Roe; Grzybowski, Richard R; Karinou, Fotini

2012-08-27

We propose a most economical design of the Optical Shared MemOry Supercomputer Interconnect System (OSMOSIS) all-optical, wavelength-space crossbar switch fabric. It is shown, by analysis and simulation, that the total number of on-off gates required for the proposed N × N switch fabric can scale asymptotically as N ln N if the number of input/output ports N can be factored into a product of small primes. This is of the same order of magnitude as Shannon's lower bound for switch complexity, according to which the minimum number of two-state switches required for the construction of a N × N permutation switch is log2 (N!).

The performance and limitations of FPGA-based digital servos for atomic, molecular, and optical physics experiments

NASA Astrophysics Data System (ADS)

Yu, Shi Jing; Fajeau, Emma; Liu, Lin Qiao; Jones, David J.; Madison, Kirk W.

2018-02-01

In this work, we address the advantages, limitations, and technical subtleties of employing field programmable gate array (FPGA)-based digital servos for high-bandwidth feedback control of lasers in atomic, molecular, and optical physics experiments. Specifically, we provide the results of benchmark performance tests in experimental setups including noise, bandwidth, and dynamic range for two digital servos built with low and mid-range priced FPGA development platforms. The digital servo results are compared to results obtained from a commercially available state-of-the-art analog servo using the same plant for control (intensity stabilization). The digital servos have feedback bandwidths of 2.5 MHz, limited by the total signal latency, and we demonstrate improvements beyond the transfer function offered by the analog servo including a three-pole filter and a two-pole filter with phase compensation to suppress resonances. We also discuss limitations of our FPGA-servo implementation and general considerations when designing and using digital servos.

FPGA cluster for high-performance AO real-time control system

NASA Astrophysics Data System (ADS)

Geng, Deli; Goodsell, Stephen J.; Basden, Alastair G.; Dipper, Nigel A.; Myers, Richard M.; Saunter, Chris D.

2006-06-01

Whilst the high throughput and low latency requirements for the next generation AO real-time control systems have posed a significant challenge to von Neumann architecture processor systems, the Field Programmable Gate Array (FPGA) has emerged as a long term solution with high performance on throughput and excellent predictability on latency. Moreover, FPGA devices have highly capable programmable interfacing, which lead to more highly integrated system. Nevertheless, a single FPGA is still not enough: multiple FPGA devices need to be clustered to perform the required subaperture processing and the reconstruction computation. In an AO real-time control system, the memory bandwidth is often the bottleneck of the system, simply because a vast amount of supporting data, e.g. pixel calibration maps and the reconstruction matrix, need to be accessed within a short period. The cluster, as a general computing architecture, has excellent scalability in processing throughput, memory bandwidth, memory capacity, and communication bandwidth. Problems, such as task distribution, node communication, system verification, are discussed.

The performance and limitations of FPGA-based digital servos for atomic, molecular, and optical physics experiments.

PubMed

Yu, Shi Jing; Fajeau, Emma; Liu, Lin Qiao; Jones, David J; Madison, Kirk W

2018-02-01

In this work, we address the advantages, limitations, and technical subtleties of employing field programmable gate array (FPGA)-based digital servos for high-bandwidth feedback control of lasers in atomic, molecular, and optical physics experiments. Specifically, we provide the results of benchmark performance tests in experimental setups including noise, bandwidth, and dynamic range for two digital servos built with low and mid-range priced FPGA development platforms. The digital servo results are compared to results obtained from a commercially available state-of-the-art analog servo using the same plant for control (intensity stabilization). The digital servos have feedback bandwidths of 2.5 MHz, limited by the total signal latency, and we demonstrate improvements beyond the transfer function offered by the analog servo including a three-pole filter and a two-pole filter with phase compensation to suppress resonances. We also discuss limitations of our FPGA-servo implementation and general considerations when designing and using digital servos.

An Improved Scheduling Algorithm for Data Transmission in Ultrasonic Phased Arrays with Multi-Group Ultrasonic Sensors

PubMed Central

Tang, Wenming; Liu, Guixiong; Li, Yuzhong; Tan, Daji

2017-01-01

High data transmission efficiency is a key requirement for an ultrasonic phased array with multi-group ultrasonic sensors. Here, a novel FIFOs scheduling algorithm was proposed and the data transmission efficiency with hardware technology was improved. This algorithm includes FIFOs as caches for the ultrasonic scanning data obtained from the sensors with the output data in a bandwidth-sharing way, on the basis of which an optimal length ratio of all the FIFOs is achieved, allowing the reading operations to be switched among all the FIFOs without time slot waiting. Therefore, this algorithm enhances the utilization ratio of the reading bandwidth resources so as to obtain higher efficiency than the traditional scheduling algorithms. The reliability and validity of the algorithm are substantiated after its implementation in the field programmable gate array (FPGA) technology, and the bandwidth utilization ratio and the real-time performance of the ultrasonic phased array are enhanced. PMID:29035345

Polyhedral integrated and free space optical interconnection

DOEpatents

Erteza, I.A.

1998-01-06

An optical communication system uses holographic optical elements to provide guided wave and non-guided communication, resulting in high bandwidth, high connectivity optical communications. Holograms within holographic optical elements route optical signals between elements and between nodes connected to elements. Angular and wavelength multiplexing allow the elements to provide high connectivity. The combination of guided and non-guided communication allows compact polyhedral system geometries. Guided wave communications provided by multiplexed substrate-mode holographic optical elements eases system alignment. 7 figs.

Polyhedral integrated and free space optical interconnection

DOEpatents

Erteza, Ireena A.

1998-01-01

An optical communication system uses holographic optical elements to provide guided wave and non-guided communication, resulting in high bandwidth, high connectivity optical communications. Holograms within holographic optical elements route optical signals between elements and between nodes connected to elements. Angular and wavelength multiplexing allow the elements to provide high connectivity. The combination of guided and non-guided communication allows compact polyhedral system geometries. Guided wave communications provided by multiplexed substrate-mode holographic optical elements eases system alignment.

Terahertz MMICs and Antenna-in-Package Technology at 300 GHz for KIOSK Download System

NASA Astrophysics Data System (ADS)

Tajima, Takuro; Kosugi, Toshihiko; Song, Ho-Jin; Hamada, Hiroshi; El Moutaouakil, Amine; Sugiyama, Hiroki; Matsuzaki, Hideaki; Yaita, Makoto; Kagami, Osamu

2016-12-01

Toward the realization of ultra-fast wireless communications systems, the inherent broad bandwidth of the terahertz (THz) band is attracting attention, especially for short-range instant download applications. In this paper, we present our recent progress on InP-based THz MMICs and packaging techniques based on low-temperature co-fibered ceramic (LTCC) technology. The transmitter MMICs are based on 80-nm InP-based high electron mobility transistors (HEMTs). Using the transmitter packaged in an E-plane split-block waveguide and compact lens receiver packaged in LTCC multilayered substrates, we tested wireless data transmission up to 27 Gbps with the simple amplitude key shifting (ASK) modulation scheme. We also present several THz antenna-in-packaging solutions based on substrate integrated waveguide (SIW) technology. A vertical hollow (VH) SIW was applied to a compact medium-gain SIW antenna and low-loss interconnection integrated in LTCC multi-layer substrates. The size of the LTCC antennas with 15-dBi gain is less than 0.1 cm3. For feeding the antenna, we investigated an LTCC-integrated transition and polyimide transition to LTCC VH SIWs. These transitions exhibit around 1-dB estimated loss at 300 GHz and more than 35 GHz bandwidth with 10-dB return loss. The proposed package solutions make antennas and interconnections easy to integrate in a compact LTCC package with an MMIC chip for practical applications.

Nanoantenna couplers for metal-insulator-metal waveguide interconnects

NASA Astrophysics Data System (ADS)

Onbasli, M. Cengiz; Okyay, Ali K.

2010-08-01

State-of-the-art copper interconnects suffer from increasing spatial power dissipation due to chip downscaling and RC delays reducing operation bandwidth. Wide bandwidth, minimized Ohmic loss, deep sub-wavelength confinement and high integration density are key features that make metal-insulator-metal waveguides (MIM) utilizing plasmonic modes attractive for applications in on-chip optical signal processing. Size-mismatch between two fundamental components (micron-size fibers and a few hundred nanometers wide waveguides) demands compact coupling methods for implementation of large scale on-chip optoelectronic device integration. Existing solutions use waveguide tapering, which requires more than 4λ-long taper distances. We demonstrate that nanoantennas can be integrated with MIM for enhancing coupling into MIM plasmonic modes. Two-dimensional finite-difference time domain simulations of antennawaveguide structures for TE and TM incident plane waves ranging from λ = 1300 to 1600 nm were done. The same MIM (100-nm-wide Ag/100-nm-wide SiO2/100-nm-wide Ag) was used for each case, while antenna dimensions were systematically varied. For nanoantennas disconnected from the MIM; field is strongly confined inside MIM-antenna gap region due to Fabry-Perot resonances. Major fraction of incident energy was not transferred into plasmonic modes. When the nanoantennas are connected to the MIM, stronger coupling is observed and E-field intensity at outer end of core is enhanced more than 70 times.

IS Security in a world of lightpaths

NASA Astrophysics Data System (ADS)

Tasker, R.

Security is a cornerstone for the delivery of consistent and reliable services in every aspect of the business of an organisation. The traditional IP network service provided to Institutes is carefully managed and controlled to limit illegal and/or antisocial use to protect the business processes of that Institute. SuperJANET5 has the capability for additional bandwidth circuits lightpaths - to be provided between specific endpoints across the network to meet specific need. Because these are end-to-end circuits they reach right into the heart of an organisation, typically providing a high bandwidth interconnection, and often at rates that are difficult to police. This paper explores this problem space and provides a strategy to minimise any associated risk through the development of an appropriate Security Policy that can sit alongside an Institute's overall approach in this area. .

Multi-resonant wideband energy harvester based on a folded asymmetric M-shaped cantilever

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Meng; Mao, Haiyang; Li, Zhigang

2015-07-15

This article reports a compact wideband piezoelectric vibration energy harvester consisting of three proof masses and an asymmetric M-shaped cantilever. The M-shaped beam comprises a main beam and two folded and dimension varied auxiliary beams interconnected through the proof mass at the end of the main cantilever. Such an arrangement constitutes a three degree-of-freedom vibrating body, which can tune the resonant frequencies of its first three orders close enough to obtain a utility wide bandwidth. The finite element simulation results and the experimental results are well matched. The operation bandwidth comprises three adjacent voltage peaks on account of the frequencymore » interval shortening mechanism. The result shows that the proposed piezoelectric energy harvester could be efficient and adaptive in practical vibration circumstance based on multiple resonant modes.« less

High-bandwidth generation of duobinary and alternate-mark-inversion modulation formats using SOA-based signal processing.

PubMed

Dailey, James M; Power, Mark J; Webb, Roderick P; Manning, Robert J

2011-12-19

We report on the novel all-optical generation of duobinary (DB) and alternate-mark-inversion (AMI) modulation formats at 42.6 Gb/s from an input on-off keyed signal. The modulation converter consists of two semiconductor optical amplifier (SOA)-based Mach-Zehnder interferometer gates. A detailed SOA model numerically confirms the operational principles and experimental data shows successful AMI and DB conversion at 42.6 Gb/s. We also predict that the operational bandwidth can be extended beyond 40 Gb/s by utilizing a new pattern-effect suppression scheme, and demonstrate dramatic reductions in patterning up to 160 Gb/s. We show an increasing trade-off between pattern-effect reduction and mean output power with increasing bitrate.

Design, processing, and testing of lsi arrays for space station

NASA Technical Reports Server (NTRS)

Lile, W. R.; Hollingsworth, R. J.

1972-01-01

The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.

Stretchable carbon nanotube charge-trap floating-gate memory and logic devices for wearable electronics.

PubMed

Son, Donghee; Koo, Ja Hoon; Song, Jun-Kyul; Kim, Jaemin; Lee, Mincheol; Shim, Hyung Joon; Park, Minjoon; Lee, Minbaek; Kim, Ji Hoon; Kim, Dae-Hyeong

2015-05-26

Electronics for wearable applications require soft, flexible, and stretchable materials and designs to overcome the mechanical mismatch between the human body and devices. A key requirement for such wearable electronics is reliable operation with high performance and robustness during various deformations induced by motions. Here, we present materials and device design strategies for the core elements of wearable electronics, such as transistors, charge-trap floating-gate memory units, and various logic gates, with stretchable form factors. The use of semiconducting carbon nanotube networks designed for integration with charge traps and ultrathin dielectric layers meets the performance requirements as well as reliability, proven by detailed material and electrical characterizations using statistics. Serpentine interconnections and neutral mechanical plane layouts further enhance the deformability required for skin-based systems. Repetitive stretching tests and studies in mechanics corroborate the validity of the current approaches.

A Fully Implemented 12 × 12 Data Vortex Optical Packet Switching Interconnection Network

NASA Astrophysics Data System (ADS)

Shacham, Assaf; Small, Benjamin A.; Liboiron-Ladouceur, Odile; Bergman, Keren

2005-10-01

A fully functional optical packet switching (OPS) interconnection network based on the data vortex architecture is presented. The photonic switching fabric uniquely capitalizes on the enormous bandwidth advantage of wavelength division multiplexing (WDM) wavelength parallelism while delivering minimal packet transit latency. Utilizing semiconductor optical amplifier (SOA)-based switching nodes and conventional fiber-optic technology, the 12-port system exhibits a capacity of nearly 1 Tb/s. Optical packets containing an eight-wavelength WDM payload with 10 Gb/s per wavelength are routed successfully to all 12 ports while maintaining a bit error rate (BER) of 10-12 or better. Median port-to-port latencies of 110 ns are achieved with a distributed deflection routing network that resolves packet contention on-the-fly without the use of optical buffers and maintains the entire payload path in the optical domain.

A novel nanoscaled Schottky barrier based transmission gate and its digital circuit applications

NASA Astrophysics Data System (ADS)

Kumar, Sunil; Loan, Sajad A.; Alamoud, Abdulrahman M.

2017-04-01

In this work we propose and simulate a compact nanoscaled transmission gate (TG) employing a single Schottky barrier based transistor in the transmission path and a single transistor based Sajad-Sunil-Schottky (SSS) device as an inverter. Therefore, just two transistors are employed to realize a complete transmission gate which normally consumes four transistors in the conventional technology. The transistors used to realize the transmission path and the SSS inverter in the proposed TG are the double gate Schottky barrier devices, employing stacks of two metal silicides, platinum silicide (PtSi) and erbium silicide (ErSi). It has been observed that the realization of the TG gate by the proposed technology has resulted into a compact structure, with reduced component count, junctions, interconnections and regions in comparison to the conventional technology. The further focus of this work is on the application part of the proposed technology. So for the first time, the proposed technology has been used to realize various combinational circuits, like a two input AND gate, a 2:1 multiplexer and a two input XOR circuits. It has been observed that the transistor count has got reduced by half in a TG, two input AND gate, 2:1 multiplexer and in a two input XOR gate. Therefore, a significant reduction in transistor count and area requirement can be achieved by using the proposed technology. The proposed technology can be also used to perform the compact realization of other combinational and sequential circuitry in future.

Chip-scale integrated optical interconnects: a key enabler for future high-performance computing

NASA Astrophysics Data System (ADS)

Haney, Michael; Nair, Rohit; Gu, Tian

2012-01-01

High Performance Computing (HPC) systems are putting ever-increasing demands on the throughput efficiency of their interconnection fabrics. In this paper, the limits of conventional metal trace-based inter-chip interconnect fabrics are examined in the context of state-of-the-art HPC systems, which currently operate near the 1 GFLOPS/W level. The analysis suggests that conventional metal trace interconnects will limit performance to approximately 6 GFLOPS/W in larger HPC systems that require many computer chips to be interconnected in parallel processing architectures. As the HPC communications bottlenecks push closer to the processing chips, integrated Optical Interconnect (OI) technology may provide the ultra-high bandwidths needed at the inter- and intra-chip levels. With inter-chip photonic link energies projected to be less than 1 pJ/bit, integrated OI is projected to enable HPC architecture scaling to the 50 GFLOPS/W level and beyond - providing a path to Peta-FLOPS-level HPC within a single rack, and potentially even Exa-FLOPSlevel HPC for large systems. A new hybrid integrated chip-scale OI approach is described and evaluated. The concept integrates a high-density polymer waveguide fabric directly on top of a multiple quantum well (MQW) modulator array that is area-bonded to the Silicon computing chip. Grayscale lithography is used to fabricate 5 μm x 5 μm polymer waveguides and associated novel small-footprint total internal reflection-based vertical input/output couplers directly onto a layer containing an array of GaAs MQW devices configured to be either absorption modulators or photodetectors. An external continuous wave optical "power supply" is coupled into the waveguide links. Contrast ratios were measured using a test rider chip in place of a Silicon processing chip. The results suggest that sub-pJ/b chip-scale communication is achievable with this concept. When integrated into high-density integrated optical interconnect fabrics, it could provide a seamless interconnect fabric spanning the intra-

Demonstration of fully enabled data center subsystem with embedded optical interconnect

NASA Astrophysics Data System (ADS)

Pitwon, Richard; Worrall, Alex; Stevens, Paul; Miller, Allen; Wang, Kai; Schmidtke, Katharine

2014-03-01

The evolution of data storage communication protocols and corresponding in-system bandwidth densities is set to impose prohibitive cost and performance constraints on future data storage system designs, fuelling proposals for hybrid electronic and optical architectures in data centers. The migration of optical interconnect into the system enclosure itself can substantially mitigate the communications bottlenecks resulting from both the increase in data rate and internal interconnect link lengths. In order to assess the viability of embedding optical links within prevailing data storage architectures, we present the design and assembly of a fully operational data storage array platform, in which all internal high speed links have been implemented optically. This required the deployment of mid-board optical transceivers, an electro-optical midplane and proprietary pluggable optical connectors for storage devices. We present the design of a high density optical layout to accommodate the midplane interconnect requirements of a data storage enclosure with support for 24 Small Form Factor (SFF) solid state or rotating disk drives and the design of a proprietary optical connector and interface cards, enabling standard drives to be plugged into an electro-optical midplane. Crucially, we have also modified the platform to accommodate longer optical interconnect lengths up to 50 meters in order to investigate future datacenter architectures based on disaggregation of modular subsystems. The optically enabled data storage system has been fully validated for both 6 Gb/s and 12 Gb/s SAS data traffic conveyed along internal optical links.

Multi-scale reflection modulator-based optical interconnects

NASA Astrophysics Data System (ADS)

Nair, Rohit

This dissertation describes the design, analysis, and experimental validation of micro- and macro-optical components for implementing optical interconnects at multiple scales for varied applications. Three distance scales are explored: millimeter, centimeter, and meter-scales. At the millimeter-scale, we propose the use of optical interconnects at the intra-chip level. With the rapid scaling down of CMOS critical dimensions in accordance to Moore's law, the bandwidth requirements of global interconnects in microprocessors has exceeded the capabilities of metal links. These are the wires that connect the most remote parts of the chip and are disproportionately problematic in terms of chip area and power consumption. Consequently, in the mid-2000s, we saw a shift in the chip architecture: a move towards multicore designs. However, this only delays the inevitable communication bottleneck between cores. To satisfy this bandwidth, we propose to replace the global metal interconnects with optical interconnects. We propose to use the hybrid integration of silicon with GaAs/AlAs-based multiple quantum well devices as optical modulators and photodetectors along with polymeric waveguides to transport the light. We use grayscale lithography to fabricate curved facets into the waveguides to couple light into the modulators and photodetectors. Next, at the chip-to-chip level in high-performance multiprocessor computing systems, communication distances vary from a few centimeters to tens of centimeters. An optical design for coupling light from off-chip lasers to on-chip surface-normal modulators is proposed in order to implement chip-to-chip free-space optical interconnects. The method uses a dual-prism module constructed from prisms made of two different glasses. The various alignment tolerances of the proposed system are investigated and found to be well within pick-and-place accuracies. For the off-chip lasers, vertical cavity surface emitting lasers (VCSELs) are proposed. The rationale behind using on-chip modulators rather than VCSELs is to avoid VCSEL thermal loads on chip, and because of higher reliability of modulators than VCSELs. Particularly above 10Gbps, an empirical model developed shows the rapid decrease of VCSEL median time to failure vs. data rate. Thus the proposed interconnect scheme which utilizes continuous wave VCSELs that are externally modulated by on-chip multiple quantum well modulators is applicable for chip-to-chip optical interconnects at 20Gbps and higher line data rates. Finally, for applications such as remote telemetry, where the interrogation distances can vary from a few meters to tens or even hundreds of meters we demonstrate a modulated retroreflector that utilizes InGaAs/InAlAs-based large-area multiple quantum well modulators on all three faces of a retroreflector. The large-area devices, fabricated by metalorganic chemical vapor deposition, are characterized in terms of the yield and leakage currents. A yield higher than that achieved previously using devices fabricated by molecular beam epitaxy is observed. The retroreflector module is constructed using standard FR4 printed circuit boards, thereby simplifying the wiring issue. A high optical contrast ratio of 8.23dB is observed for a drive of 20V. A free-standing PCB retroreflector is explored and found to have insufficient angular tolerances (+/-0.5 degrees). We show that the angular errors in the corner-cube construction can be corrected for using off-the-shelf optical components as opposed to mounting the PCBs on a precision corner cube, as has been done previously.

A random access memory immune to single event upset using a T-Resistor

DOEpatents

Ochoa, A. Jr.

1987-10-28

In a random access memory cell, a resistance ''T'' decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell. 4 figs.

Random access memory immune to single event upset using a T-resistor

DOEpatents

Ochoa, Jr., Agustin

1989-01-01

In a random access memory cell, a resistance "T" decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell.

The 30-GHz monolithic receive module

NASA Technical Reports Server (NTRS)

Bauhahn, P.; Geddes, J.; Sokolov, V.; Contolatis, T.

1988-01-01

The fourth year progress is described on a program to develop a 27.5 to 30 GHz GaAs monolithic receive module for spaceborne-communication antenna feed array applications, and to deliver submodules for experimental evaluation. Program goals include an overall receive module noise figure of 5 dB, a 30 dB RF to IF gain with six levels of intermediate gain control, a five bit phase shifter, and a maximum power consumption of 250 mW. Submicron gate length single and dual gate FETs are described and applied in the development of monolithic gain control amplifiers and low noise amplifiers. A two-stage monolithic gain control amplifier based on ion implanted dual gate MESFETs was designed and fabricated. The gain control amplifier has a gain of 12 dB at 29 GHz with a gain control range of over 13 dB. A two-stage monolithic low noise amplifier based on ion implanted MESFETs which provides 7 dB gain with 6.2 dB noise figure at 29 GHz was also developed. An interconnected receive module containing LNA, gain control, and phase shifter submodules was built using the LNA and gain control ICs as well as a monolithic phase shifter developed previously under this program. The design, fabrication, and evaluation of this interconnected receiver is presented. Progress in the development of an RF/IF submodule containing a unique ion implanted diode mixer diode and a broadband balanced mixer monolithic IC with on-chip IF amplifier and the initial design of circuits for the RF portion of a two submodule receiver are also discussed.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

PubMed Central

2012-01-01

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. PMID:22901374

Naphthacene Based Organic Thin Film Transistor With Rare Earth Oxide

NASA Astrophysics Data System (ADS)

Konwar, K.; Baishya, B.

2010-12-01

Naphthacene based organic thin film transistors (OTFTs) have been fabricated using La2O3, as the gate insulator. All the OTFTs have been fabricated by the process of thermal evaporation in vacuum on perfectly cleaned glass substrates with aluminium as source-drain and gate electrodes. The naphthacene film morphology on the glass substrate has been studied by XRD and found to be polycrystalline in nature. The field effect mobility, output resistance, amplification factor, transconductance and gain bandwidth product of the OTFTs have been calculated by using theoretical TFT model. The highest value of field effect mobility is found to be 0.07×10-3 cm2V-1s-1 for the devices annealed in vacuum at 90° C for 5 hours.

Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation.

PubMed

Dutta, Sourav; Zografos, Odysseas; Gurunarayanan, Surya; Radu, Iuliana; Soree, Bart; Catthoor, Francky; Naeemi, Azad

2017-12-19

Surface-plasmon-polariton waves propagating at the interface between a metal and a dielectric, hold the key to future high-bandwidth, dense on-chip integrated logic circuits overcoming the diffraction limitation of photonics. While recent advances in plasmonic logic have witnessed the demonstration of basic and universal logic gates, these CMOS oriented digital logic gates cannot fully utilize the expressive power of this novel technology. Here, we aim at unraveling the true potential of plasmonics by exploiting an enhanced native functionality - the majority voter. Contrary to the state-of-the-art plasmonic logic devices, we use the phase of the wave instead of the intensity as the state or computational variable. We propose and demonstrate, via numerical simulations, a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate along with a novel referencing scheme that can directly translate the information encoded in the amplitude and phase of the wave into electric field intensity at the output. Our MIM-based 3-input majority gate displays a highly improved overall area of only 0.636 μm 2 for a single-stage compared with previous works on plasmonic logic. The proposed device demonstrates non-Boolean computational capability and can find direct utility in highly parallel real-time signal processing applications like pattern recognition.

Calibration approach for fluorescence lifetime determination for applications using time-gated detection and finite pulse width excitation.

PubMed

Keller, Scott B; Dudley, Jonathan A; Binzel, Katherine; Jasensky, Joshua; de Pedro, Hector Michael; Frey, Eric W; Urayama, Paul

2008-10-15

Time-gated techniques are useful for the rapid sampling of excited-state (fluorescence) emission decays in the time domain. Gated detectors coupled with bright, economical, nanosecond-pulsed light sources like flashlamps and nitrogen lasers are an attractive combination for bioanalytical and biomedical applications. Here we present a calibration approach for lifetime determination that is noniterative and that does not assume a negligible instrument response function (i.e., a negligible excitation pulse width) as does most current rapid lifetime determination approaches. Analogous to a transducer-based sensor, signals from fluorophores of known lifetime (0.5-12 ns) serve as calibration references. A fast avalanche photodiode and a GHz-bandwidth digital oscilloscope is used to detect transient emission from reference samples excited using a nitrogen laser. We find that the normalized time-integrated emission signal is proportional to the lifetime, which can be determined with good reproducibility (typically <100 ps) even for data with poor signal-to-noise ratios ( approximately 20). Results are in good agreement with simulations. Additionally, a new time-gating scheme for fluorescence lifetime imaging applications is proposed. In conclusion, a calibration-based approach is a valuable analysis tool for the rapid determination of lifetime in applications using time-gated detection and finite pulse width excitation.

Novel pre-equalization transimpedance amplifier for 10 Gb/s optical interconnects

NASA Astrophysics Data System (ADS)

Qiwei, Song; Luhong, Mao; Sheng, Xie; Yuzhuo, Kang

2015-07-01

This paper presents a modified regulated cascode (RGC) transimpedance amplifier (TIA) with a novel pre-equalized technique. The pre-equalized circuit employed the broadband series inductive π-network and Gm-boosting technique. The introduction of this technique compensates the transferred signal at the input port of the TIA without an increase in power dissipation. Furthermore, a novel miller capacitance degeneration method is designed in the gain stage for further bandwidth improvement. The TIA is realized in UMC 0.18 πm CMOS technology and tested with an on-chip 0.3 pF capacitor to emulate a photodetector (PD). The measured transimpedance gain amounts to 57 dBΩ with a -3 dB bandwidth of about 8.2 GHz and consumes only 22 mW power from a single 1.8 V supply. Project supported by the National Natural Science Foundation of China (Nos. 61036002, 61474081).

Design and fabrication of hybrid SPP waveguides for ultrahigh-bandwidth low-penalty terabit-scale data transmission.

PubMed

Du, Jing; Wang, Jian

2017-11-27

Here we design and fabricate a hybrid surface plasmon polarities (SPP) waveguide on the silicon-on-insulator (SOI) photonics platform. The designed hybrid SPP waveguide is composed of a metal ridge, an air gap, and a silicon ridge. We simulate the mode characteristics in the structure and design the waveguide with a wide air gap that can simplify the fabrication process and maintain the advantages of the hybrid SPP mode. The performance of ultrahigh-bandwidth data transmission through the proposed waveguide is then investigated using 161 wavelength-division multiplexing (WDM) channels, each carrying a 11.2-Gbit/s orthogonal frequency-division multiplexing (OFDM) 16-ary quadrature amplitude modulation (16-QAM) signal. The bit-error rates (BERs) of all 161 channels are less than 1e-3. The favorable results show the prospect of on-chip optical interconnection using the proposed hybrid SPP waveguide.

Hybridization-induced broadband terahertz wave absorption with graphene metasurfaces.

PubMed

Mou, Nanli; Sun, Shulin; Dong, Hongxing; Dong, Shaohua; He, Qiong; Zhou, Lei; Zhang, Long

2018-04-30

Electromagnetic (EM) wave absorption plays a vital role in photonics. While metasurfaces are proposed to absorb EM waves efficiently, most of them exhibit limited bandwidth and fixed functionalities. Here, we propose a broadband and tunable terahertz (THz) absorber based on a graphene-based metasurface, which is constructed by a single layer of closely patterned graphene concentric double rings and a metallic mirror separated by an ultrathin SiO 2 layer. Plasmonic hybridization between two graphene rings significantly enlarges the absorption bandwidth, which can be further tuned by gating the graphene. Moreover, the specific design also makes our device insensitive to the incident angle and polarization state of impinging EM waves. Our results may inspire certain wave-modulation-related applications, such as THz imaging, smart absorber, tunable sensor, etc.

Optical connections on flexible substrates

NASA Astrophysics Data System (ADS)

Bosman, Erwin; Geerinck, Peter; Christiaens, Wim; Van Steenberge, Geert; Vanfleteren, Jan; Van Daele, Peter

2006-04-01

Optical interconnections integrated on a flexible substrate combine the advantages of optical data transmissions (high bandwidth, no electromagnetic disturbance and low power consumption) and those of flexible substrates (compact, ease of assembly...). Especially the flexible character of the substrates can significantly lower the assembly cost and leads to more compact modules. Especially in automotive-, avionic-, biomedical and sensing applications there is a great potential for these flexible optical interconnections because of the increasing data-rates, increasing use of optical sensors and requirement for smaller size and weight. The research concentrates on the integration of commercially available polymer optical layers (Truemode Backplane TM Polymer, Ormocer®) on a flexible Polyimide film, the fabrication of waveguides and out-of plane deflecting 45° mirrors, the characterization of the optical losses due to the bending of the substrate, and the fabrication of a proof-of-principal demonstrator. The resulting optical structures should be compatible with the standard fabrication of flexible printed circuit boards.

Monolithic optoelectronic integrated broadband optical receiver with graphene photodetectors

NASA Astrophysics Data System (ADS)

Cheng, Chuantong; Huang, Beiju; Mao, Xurui; Zhang, Zanyun; Zhang, Zan; Geng, Zhaoxin; Xue, Ping; Chen, Hongda

2017-07-01

Optical receivers with potentially high operation bandwidth and low cost have received considerable interest due to rapidly growing data traffic and potential Tb/s optical interconnect requirements. Experimental realization of 65 GHz optical signal detection and 262 GHz intrinsic operation speed reveals the significance role of graphene photodetectors (PDs) in optical interconnect domains. In this work, a novel complementary metal oxide semiconductor post-backend process has been developed for integrating graphene PDs onto silicon integrated circuit chips. A prototype monolithic optoelectronic integrated optical receiver has been successfully demonstrated for the first time. Moreover, this is a firstly reported broadband optical receiver benefiting from natural broadband light absorption features of graphene material. This work is a perfect exhibition of the concept of monolithic optoelectronic integration and will pave way to monolithically integrated graphene optoelectronic devices with silicon ICs for three-dimensional optoelectronic integrated circuit chips.

Novel WRM-based architecture of hybrid PON featuring online access and full-fiber-fault protection for smart grid

NASA Astrophysics Data System (ADS)

Li, Xingfeng; Gan, Chaoqin; Liu, Zongkang; Yan, Yuqi; Qiao, HuBao

2018-01-01

In this paper, a novel architecture of hybrid PON for smart grid is proposed by introducing a wavelength-routing module (WRM). By using conventional optical passive components, a WRM with M ports is designed. The symmetry and passivity of the WRM makes it be easily integrated and very cheap in practice. Via the WRM, two types of network based on different ONU-interconnected manner can realize online access. Depending on optical switches and interconnecting fibers, full-fiber-fault protection and dynamic bandwidth allocation are realized in these networks. With the help of amplitude modulation, DPSK modulation and RSOA technology, wavelength triple-reuse is achieved. By means of injecting signals into left and right branches in access ring simultaneously, the transmission delay is decreased. Finally, the performance analysis and simulation of the network verifies the feasibility of the proposed architecture.

Broadband spectroscopy of dynamic impedances with short chirp pulses.

PubMed

Min, M; Land, R; Paavle, T; Parve, T; Annus, P; Trebbels, D

2011-07-01

An impedance spectrum of dynamic systems is time dependent. Fast impedance changes take place, for example, in high throughput microfluidic devices and in operating cardiovascular systems. Measurements must be as short as possible to avoid significant impedance changes during the spectrum analysis, and as long as possible for enlarging the excitation energy and obtaining a better signal-to-noise ratio (SNR). The authors propose to use specific short chirp pulses for excitation. Thanks to the specific properties of the chirp function, it is possible to meet the needs for a spectrum bandwidth, measurement time and SNR so that the most accurate impedance spectrogram can be obtained. The chirp wave excitation can include thousands of cycles when the impedance changes slowly, but in the case of very high speed changes it can be shorter than a single cycle, preserving the same excitation bandwidth. For example, a 100 kHz bandwidth can be covered by the chirp pulse with durations from 10 µs to 1 s; only its excitation energy differs also 10(5) times. After discussing theoretical short chirp properties in detail, the authors show how to generate short chirps in the microsecond range with a bandwidth up to a few MHz by using digital synthesis architectures developed inside a low-cost standard field programmable gate array.

Controlling the ambipolarity and improvement of RF performance using Gaussian Drain Doped TFET

NASA Astrophysics Data System (ADS)

Nigam, Kaushal; Gupta, Sarthak; Pandey, Sunil; Kondekar, P. N.; Sharma, Dheeraj

2018-05-01

Ambipolar conduction in tunnel field-effect transistors (TFETs) has been occurred as an inherent issue due to drain-channel tunneling. It makes TFET less efficient and restricts its application in complementary digital circuits. Therefore, this manuscript reports the application of Gaussian doping profile on nanometer regime silicon channel TFETs to completely eliminate the ambipolarity. For this, Gaussian doping is used in the drain region of conventional gate-drain overlap TFET to control the tunneling of electrons from the valence band of channel to the conduction band of drain. As a result, barrier width at the drain/channel junction increases significantly leading to the suppression of an ambipolar current even when higher doping concentration (1 ? 10 ? cm ?) is considered in the drain region. However, significant improvement in terms of RF figure-of-merits such as cut-off frequency (f ?), gain bandwidth product (GBW), and gate-to-drain capacitance (C ?) is achieved with Gaussian doped gate on drain overlap TFET as compared to its counterpart TFET.

Hydrophobic interactions between the voltage sensor and pore mediate inactivation in Kv11.1 channels

PubMed Central

Perry, Matthew D.; Wong, Sophia; Ng, Chai Ann

2013-01-01

Kv11.1 channels are critical for the maintenance of a normal heart rhythm. The flow of potassium ions through these channels is controlled by two voltage-regulated gates, termed “activation” and “inactivation,” located at opposite ends of the pore. Crucially in Kv11.1 channels, inactivation gating occurs much more rapidly, and over a distinct range of voltages, compared with activation gating. Although it is clear that the fourth transmembrane segments (S4), within each subunit of the tetrameric channel, are important for controlling the opening and closing of the activation gate, their role during inactivation gating is much less clear. Here, we use rate equilibrium free energy relationship (REFER) analysis to probe the contribution of the S4 “voltage-sensor” helix during inactivation of Kv11.1 channels. Contrary to the important role that charged residues play during activation gating, it is the hydrophobic residues (Leu529, Leu530, Leu532, and Val535) that are the key molecular determinants of inactivation gating. Within the context of an interconnected multi-domain model of Kv11.1 inactivation gating, our REFER analysis indicates that the S4 helix and the S4–S5 linker undergo a conformational rearrangement shortly after that of the S5 helix and S5P linker, but before the S6 helix. Combining REFER analysis with double mutant cycle analysis, we provide evidence for a hydrophobic interaction between residues on the S4 and S5 helices. Based on a Kv11.1 channel homology model, we propose that this hydrophobic interaction forms the basis of an intersubunit coupling between the voltage sensor and pore domain that is an important mediator of inactivation gating. PMID:23980196

Limits on silicon nanoelectronics for terascale integration.

PubMed

Meindl, J D; Chen, Q; Davis, J A

2001-09-14

Throughout the past four decades, silicon semiconductor technology has advanced at exponential rates in both performance and productivity. Concerns have been raised, however, that the limits of silicon technology may soon be reached. Analysis of fundamental, material, device, circuit, and system limits reveals that silicon technology has an enormous remaining potential to achieve terascale integration (TSI) of more than 1 trillion transistors per chip. Such massive-scale integration is feasible assuming the development and economical mass production of double-gate metal-oxide-semiconductor field effect transistors with gate oxide thickness of about 1 nanometer, silicon channel thickness of about 3 nanometers, and channel length of about 10 nanometers. The development of interconnecting wires for these transistors presents a major challenge to the achievement of nanoelectronics for TSI.

Photogating in Low Dimensional Photodetectors

PubMed Central

Fang, Hehai

2017-01-01

Abstract Low dimensional materials including quantum dots, nanowires, 2D materials, and so forth have attracted increasing research interests for electronic and optoelectronic devices in recent years. Photogating, which is usually observed in photodetectors based on low dimensional materials and their hybrid structures, is demonstrated to play an important role. Photogating is considered as a way of conductance modulation through photoinduced gate voltage instead of simply and totally attributing it to trap states. This review first focuses on the gain of photogating and reveals the distinction from conventional photoconductive effect. The trap‐ and hybrid‐induced photogating including their origins, formations, and characteristics are subsequently discussed. Then, the recent progress on trap‐ and hybrid‐induced photogating in low dimensional photodetectors is elaborated. Though a high gain bandwidth product as high as 109 Hz is reported in several cases, a trade‐off between gain and bandwidth has to be made for this type of photogating. The general photogating is put forward according to another three reported studies very recently. General photogating may enable simultaneous high gain and high bandwidth, paving the way to explore novel high‐performance photodetectors. PMID:29270342

Performance analysis of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor

NASA Astrophysics Data System (ADS)

Ahish, S.; Sharma, Dheeraj; Vasantha, M. H.; Kumar, Y. B. N.

2017-03-01

In this paper, analog/RF performance of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor (HJTFET) has been explored. A highly doped n+ layer is placed at the Source-Channel junction in order to improve the horizontal electric field component and thus, improve the realiability of the device. The analog performance of the device is analysed by extracting current-voltage characteristics, transcondutance (gm), gate-to-drain capacitance (Cgd) and gate-to-source capacitance (Cgs). Further, RF performance of the device is evaluated by obtaining cut-off frequency (fT) and Gain Bandwidth (GBW) product. ION /IOFF ratio equal to ≈ 109, subthreshold slope of 27 mV/dec, maximum fT of 2.1 THz and maximum GBW of 484 GHz were achieved. Also, the impact of temperature variation on the linearity performance of the device has been investigated. Furthermore, the circuit level performance of the device is performed by implementing a Common Source (CS) amplifier; maximum gain of 31.11 dB and 3-dB cut-off frequency equal to 91.2 GHz were achieved for load resistance (RL) = 17.5 KΩ.

Architecutres, Models, Algorithms, and Software Tools for Configurable Computing

DTIC Science & Technology

2000-03-06

and J.G. Nash. The gated interconnection network for dynamic programming. Plenum, 1988 . [18] Ju wook Jang, Heonchul Park, and Viktor K. Prasanna. A ...Sep. 1997. [2] C. Ebeling, D. C. Cronquist , P. Franklin and C. Fisher, "RaPiD - A configurable computing architecture for compute-intensive...ABSTRACT (Maximum 200 words) The Models, Algorithms, and Architectures for Reconfigurable Computing (MAARC) project developed a sound framework for

Field-programmable logic devices with optical input-output.

PubMed

Szymanski, T H; Saint-Laurent, M; Tyan, V; Au, A; Supmonchai, B

2000-02-10

A field-programmable logic device (FPLD) with optical I/O is described. FPLD's with optical I/O can have their functionality specified in the field by means of downloading a control-bit stream and can be used in a wide range of applications, such as optical signal processing, optical image processing, and optical interconnects. Our device implements six state-of-the-art dynamically programmable logic arrays (PLA's) on a 2 mm x 2 mm die. The devices were fabricated through the Lucent Technologies-Advanced Research Projects Agency-Consortium for Optical and Optoelectronic Technologies in Computing (Lucent/ARPA/COOP) workshop by use of 0.5-microm complementary metal-oxide semiconductor-self-electro-optic device technology and were delivered in 1998. All devices are fully functional: The electronic data paths have been verified at 200 MHz, and optical tests are pending. The device has been programmed to implement a two-stage optical switching network with six 4 x 4 crossbar switches, which can realize more than 190 x 10(6) unique programmable input-output permutations. The same device scaled to a 2 cm x 2 cm substrate could support as many as 4000 optical I/O and 1 Tbit/s of optical I/O bandwidth and offer fully programmable digital functionality with approximately 110,000 programmable logic gates. The proposed optoelectronic FPLD is also ideally suited to realizing dense, statically reconfigurable crossbar switches. We describe an attractive application area for such devices: a rearrangeable three-stage optical switch for a wide-area-network backbone, switching 1000 traffic streams at the OC-48 data rate and supporting several terabits of traffic.

Regenerative switching CMOS system

DOEpatents

Welch, James D.

1998-01-01

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

Regenerative switching CMOS system

DOEpatents

Welch, J.D.

1998-06-02

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

A Frequency Agile, Self-Adaptive Serial Link on Xilinx FPGAs

NASA Astrophysics Data System (ADS)

Aloisio, A.; Giordano, R.; Izzo, V.; Perrella, S.

2015-06-01

In this paper, we focused on the GTX transceiver modules of Xilinx Kintex 7 field-programmable gate arrays (FPGAs), which provide high bandwidth, low jitter on the recovered clock, and an equalization system on the transmitter and the receiver. We present a frequency agile, auto-adaptive serial link. The link is able to take care of the reconfiguration of the GTX parameters in order to fully benefit from the available link bandwidth, by setting the highest line rate. It is designed around an FPGA-embedded microprocessor, which drives the programmable ports of the GTX in order to control the quality of the received data and to easily calculate the bit-error rate in each sampling point of the eye diagram. We present the self-adaptive link project, the description of the test system, and the main results.

Narrow bandwidth detection of vibration signature using fiber lasers

DOEpatents

Moore, Sean; Soh, Daniel B.S.

2018-05-08

The various technologies presented herein relate to extracting a portion of each pulse in a series of pulses reflected from a target to facilitate determination of a Doppler-shifted frequency for each pulse and, subsequently, a vibration frequency for the series of pulses. Each pulse can have a square-wave configuration, whereby each pulse can be time-gated to facilitate discarding the leading edge and the trailing edge (and associated non-linear effects) of each pulse and accordingly, capture of the central portion of the pulse from which the Doppler-shifted frequency, and ultimately, the vibration frequency of the target can be determined. Determination of the vibration velocity facilitates identification of the target being in a state of motion. The plurality of pulses can be formed from a laser beam (e.g., a continuous wave), the laser beam having a narrow bandwidth.

Execution of parallel algorithms on a heterogeneous multicomputer

NASA Astrophysics Data System (ADS)

Isenstein, Barry S.; Greene, Jonathon

1995-04-01

Many aerospace/defense sensing and dual-use applications require high-performance computing, extensive high-bandwidth interconnect and realtime deterministic operation. This paper will describe the architecture of a scalable multicomputer that includes DSP and RISC processors. A single chassis implementation is capable of delivering in excess of 10 GFLOPS of DSP processing power with 2 Gbytes/s of realtime sensor I/O. A software approach to implementing parallel algorithms called the Parallel Application System (PAS) is also presented. An example of applying PAS to a DSP application is shown.

Dual-scale topology optoelectronic processor.

PubMed

Marsden, G C; Krishnamoorthy, A V; Esener, S C; Lee, S H

1991-12-15

The dual-scale topology optoelectronic processor (D-STOP) is a parallel optoelectronic architecture for matrix algebraic processing. The architecture can be used for matrix-vector multiplication and two types of vector outer product. The computations are performed electronically, which allows multiplication and summation concepts in linear algebra to be generalized to various nonlinear or symbolic operations. This generalization permits the application of D-STOP to many computational problems. The architecture uses a minimum number of optical transmitters, which thereby reduces fabrication requirements while maintaining area-efficient electronics. The necessary optical interconnections are space invariant, minimizing space-bandwidth requirements.

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

PubMed

Kwon, Jimin; Takeda, Yasunori; Fukuda, Kenjiro; Cho, Kilwon; Tokito, Shizuo; Jung, Sungjune

2016-11-22

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Leadless Chip Carrier Packaging and CAD/CAM-Supported Wire Wrap Interconnect Technology for Subnanosecond ECL.

DTIC Science & Technology

1981-11-01

Showing Wire . 99 Impregnanted Silicone Rubber Contacts, Chip Carrier, ard Lid 35. Technit Connector For 68-Pad JEDEC Type A Leadless . . 100 Chip Carrier...Points of Various . . . . 124 Solders 4. Composition of Alloys Employed in Dual-In-Line . . . . 128 Package Pins and Plating by Mass Spectrographic...swings, and subnanosecond gate delays and risetimes. Presently, emitter coupled logic (ECL) and current mode logic (CML), both fabricated with silicon tech

Efficient Parallel Algorithms on Restartable Fail-Stop Processors

DTIC Science & Technology

1991-01-01

resource (memory), and ( 3 ) that processors, memory and their interconnection must be The model of parallel computation known as the Par- perfectly...setting), arid ure an(I restart errors. We describe these arguments if] [AAtPS 871 (in a deterministic setting). Fault-tolerance Section 3 . of...grannmarity at the processor level --- for recent work on where Al is the nmber of failures during this step’s gate granilarities see [All 90, Pip 85

Innovative Ge Quantum Dot Functional Sensing and Metrology Devices

DTIC Science & Technology

2017-08-21

information latency and power consumption . In contrast, optical interconnects have shown tremendous promise for replacing electrical wires thanks to...single oxidation step of Si0.85Ge0.15 nano-pillars patterned over a buffer layer of Si3N4 on top of the n-Si substrate. During the high- temperature ...exquisitely-controlled dynamic balance between the fluxes of oxygen and silicon interstitials. Results and Discussion: 1. Self-organized, gate

An Efficient, Highly Flexible Multi-Channel Digital Downconverter Architecture

NASA Technical Reports Server (NTRS)

Goodhart, Charles E.; Soriano, Melissa A.; Navarro, Robert; Trinh, Joseph T.; Sigman, Elliott H.

2013-01-01

In this innovation, a digital downconverter has been created that produces a large (16 or greater) number of output channels of smaller bandwidths. Additionally, this design has the flexibility to tune each channel independently to anywhere in the input bandwidth to cover a wide range of output bandwidths (from 32 MHz down to 1 kHz). Both the flexibility in channel frequency selection and the more than four orders of magnitude range in output bandwidths (decimation rates from 32 to 640,000) presented significant challenges to be solved. The solution involved breaking the digital downconversion process into a two-stage process. The first stage is a 2 oversampled filter bank that divides the whole input bandwidth as a real input signal into seven overlapping, contiguous channels represented with complex samples. Using the symmetry of the sine and cosine functions in a similar way to that of an FFT (fast Fourier transform), this downconversion is very efficient and gives seven channels fixed in frequency. An arbitrary number of smaller bandwidth channels can be formed from second-stage downconverters placed after the first stage of downconversion. Because of the overlapping of the first stage, there is no gap in coverage of the entire input bandwidth. The input to any of the second-stage downconverting channels has a multiplexer that chooses one of the seven wideband channels from the first stage. These second-stage downconverters take up fewer resources because they operate at lower bandwidths than doing the entire downconversion process from the input bandwidth for each independent channel. These second-stage downconverters are each independent with fine frequency control tuning, providing extreme flexibility in positioning the center frequency of a downconverted channel. Finally, these second-stage downconverters have flexible decimation factors over four orders of magnitude The algorithm was developed to run in an FPGA (field programmable gate array) at input data sampling rates of up to 1,280 MHz. The current implementation takes a 1,280-MHz real input, and first breaks it up into seven 160-MHz complex channels, each spaced 80 MHz apart. The eighth channel at baseband was not required for this implementation, and led to more optimization. Afterwards, 16 second stage narrow band channels with independently tunable center frequencies and bandwidth settings are implemented A future implementation in a larger Xilinx FPGA will hold up to 32 independent second-stage channels.

Interconnected ponds operation for flood hazard distribution

NASA Astrophysics Data System (ADS)

Putra, S. S.; Ridwan, B. W.

2016-05-01

The climatic anomaly, which comes with extreme rainfall, will increase the flood hazard in an area within a short period of time. The river capacity in discharging the flood is not continuous along the river stretch and sensitive to the flood peak. This paper contains the alternatives on how to locate the flood retention pond that are physically feasible to reduce the flood peak. The flood ponds were designed based on flood curve number criteria (TR-55, USDA) with the aim of rapid flood peak capturing and gradual flood retuning back to the river. As a case study, the hydrologic condition of upper Ciliwung river basin with several presumed flood pond locations was conceptually designed. A fundamental tank model that reproducing the operation of interconnected ponds was elaborated to achieve the designed flood discharge that will flows to the downstream area. The flood hazard distribution status, as the model performance criteria, will be computed within Ciliwung river reach in Manggarai Sluice Gate spot. The predicted hazard reduction with the operation of the interconnected retention area result had been bench marked with the normal flow condition.

Series resistance compensation for whole-cell patch-clamp studies using a membrane state estimator

PubMed Central

Sherman, AJ; Shrier, A; Cooper, E

1999-01-01

Whole-cell patch-clamp techniques are widely used to measure membrane currents from isolated cells. While suitable for a broad range of ionic currents, the series resistance (R(s)) of the recording pipette limits the bandwidth of the whole-cell configuration, making it difficult to measure rapid ionic currents. To increase bandwidth, it is necessary to compensate for R(s). Most methods of R(s) compensation become unstable at high bandwidth, making them hard to use. We describe a novel method of R(s) compensation that overcomes the stability limitations of standard designs. This method uses a state estimator, implemented with analog computation, to compute the membrane potential, V(m), which is then used in a feedback loop to implement a voltage clamp; we refer to this as state estimator R(s) compensation. To demonstrate the utility of this approach, we built an amplifier incorporating state estimator R(s) compensation. In benchtop tests, our amplifier showed significantly higher bandwidths and improved stability when compared with a commercially available amplifier. We demonstrated that state estimator R(s) compensation works well in practice by recording voltage-gated Na(+) currents under voltage-clamp conditions from dissociated neonatal rat sympathetic neurons. We conclude that state estimator R(s) compensation should make it easier to measure large rapid ionic currents with whole-cell patch-clamp techniques. PMID:10545359

Optical links in handheld multimedia devices

NASA Astrophysics Data System (ADS)

van Geffen, S.; Duis, J.; Miller, R.

2008-04-01

Ever emerging applications in handheld multimedia devices such as mobile phones, laptop computers, portable video games and digital cameras requiring increased screen resolutions are driving higher aggregate bitrates between host processor and display(s) enabling services such as mobile video conferencing, video on demand and TV broadcasting. Larger displays and smaller phones require complex mechanical 3D hinge configurations striving to combine maximum functionality with compact building volumes. Conventional galvanic interconnections such as Micro-Coax and FPC carrying parallel digital data between host processor and display module may produce Electromagnetic Interference (EMI) and bandwidth limitations caused by small cable size and tight cable bends. To reduce the number of signals through a hinge, the mobile phone industry, organized in the MIPI (Mobile Industry Processor Interface) alliance, is currently defining an electrical interface transmitting serialized digital data at speeds >1Gbps. This interface allows for electrical or optical interconnects. Above 1Gbps optical links may offer a cost effective alternative because of their flexibility, increased bandwidth and immunity to EMI. This paper describes the development of optical links for handheld communication devices. A cable assembly based on a special Plastic Optical Fiber (POF) selected for its mechanical durability is terminated with a small form factor molded lens assembly which interfaces between an 850nm VCSEL transmitter and a receiving device on the printed circuit board of the display module. A statistical approach based on a Lean Design For Six Sigma (LDFSS) roadmap for new product development tries to find an optimum link definition which will be robust and low cost meeting the power consumption requirements appropriate for battery operated systems.

High-speed, bi-directional dual-core fiber transmission system for high-density, short-reach optical interconnects

NASA Astrophysics Data System (ADS)

Geng, Ying; Li, Shenping; Li, Ming-Jun; Sutton, Clifford G.; McCollum, Robert L.; McClure, Randy L.; Koklyushkin, Alexander V.; Matthews, Karen I.; Luther, James P.; Butler, Douglas L.

2015-03-01

A complete single mode dual-core fiber system for short-reach optical interconnects is fabricated and tested for high-speed data transmission. It includes dual-core fibers capable of bi-directional data transmission, dual-core simplex LC connectors, and fan-outs. The transmission system offers simplified bi-directional traffic engineering with integrated bidirectional transceivers and compact system design, utilizing simplex dual-core LC connectors that use half the space while increasing the bandwidth density by a factor of two. The fiber has two cores that are compatible with single mode fiber and conforms to the industry standard outer diameter of 125 μm. This reduces operational complexity by reducing the size and number of fibers, cables and connectors. Measured OTDR loss for both cores was 0.34 dB/km at 1310 nm and 0.19 dB/km at 1550 nm. Crosstalk for a piece of 5.8 km long dual-core fiber was measured to be below -75 dB at 1310 nm, and below -40 dB at 1550 nm. Both free-space optics fan-outs and tapered-fiber-coupler based MCF fan-outs were evaluated for the transmission system. Error-free and penalty-free 25 Gb/s bi-directional transmission performance was demonstrated for three different fiber lengths, 200 m, 2 km and 10 km, using the complete all-fiber-based system including connectors and fan-outs. This single mode, dual-core fiber transmission system adds complementary value to systems where additional increases in bandwidth density can come from wavelength division multiplexing and multiple bits per symbol.

Interfacing broadband photonic qubits to on-chip cavity-protected rare-earth ensembles

PubMed Central

Zhong, Tian; Kindem, Jonathan M.; Rochman, Jake; Faraon, Andrei

2017-01-01

Ensembles of solid-state optical emitters enable broadband quantum storage and transduction of photonic qubits, with applications in high-rate quantum networks for secure communications and interconnecting future quantum computers. To transfer quantum states using ensembles, rephasing techniques are used to mitigate fast decoherence resulting from inhomogeneous broadening, but these techniques generally limit the bandwidth, efficiency and active times of the quantum interface. Here, we use a dense ensemble of neodymium rare-earth ions strongly coupled to a nanophotonic resonator to demonstrate a significant cavity protection effect at the single-photon level—a technique to suppress ensemble decoherence due to inhomogeneous broadening. The protected Rabi oscillations between the cavity field and the atomic super-radiant state enable ultra-fast transfer of photonic frequency qubits to the ions (∼50 GHz bandwidth) followed by retrieval with 98.7% fidelity. With the prospect of coupling to other long-lived rare-earth spin states, this technique opens the possibilities for broadband, always-ready quantum memories and fast optical-to-microwave transducers. PMID:28090078

Interfacing broadband photonic qubits to on-chip cavity-protected rare-earth ensembles

NASA Astrophysics Data System (ADS)

Zhong, Tian; Kindem, Jonathan M.; Rochman, Jake; Faraon, Andrei

2017-01-01

Ensembles of solid-state optical emitters enable broadband quantum storage and transduction of photonic qubits, with applications in high-rate quantum networks for secure communications and interconnecting future quantum computers. To transfer quantum states using ensembles, rephasing techniques are used to mitigate fast decoherence resulting from inhomogeneous broadening, but these techniques generally limit the bandwidth, efficiency and active times of the quantum interface. Here, we use a dense ensemble of neodymium rare-earth ions strongly coupled to a nanophotonic resonator to demonstrate a significant cavity protection effect at the single-photon level--a technique to suppress ensemble decoherence due to inhomogeneous broadening. The protected Rabi oscillations between the cavity field and the atomic super-radiant state enable ultra-fast transfer of photonic frequency qubits to the ions (~50 GHz bandwidth) followed by retrieval with 98.7% fidelity. With the prospect of coupling to other long-lived rare-earth spin states, this technique opens the possibilities for broadband, always-ready quantum memories and fast optical-to-microwave transducers.

Femtosecond laser inscription of asymmetric directional couplers for in-fiber optical taps and fiber cladding photonics.

PubMed

Grenier, Jason R; Fernandes, Luís A; Herman, Peter R

2015-06-29

Precise alignment of femtosecond laser tracks in standard single mode optical fiber is shown to enable controllable optical tapping of the fiber core waveguide light with fiber cladding photonic circuits. Asymmetric directional couplers are presented with tunable coupling ratios up to 62% and bandwidths up to 300 nm at telecommunication wavelengths. Real-time fiber monitoring during laser writing permitted a means of controlling the coupler length to compensate for micron-scale alignment errors and to facilitate tailored design of coupling ratio, spectral bandwidth and polarization properties. Laser induced waveguide birefringence was harnessed for polarization dependent coupling that led to the formation of in-fiber polarization-selective taps with 32 dB extinction ratio. This technology enables the interconnection of light propagating in pre-existing waveguides with laser-formed devices, thereby opening a new practical direction for the three-dimensional integration of optical devices in the cladding of optical fibers and planar lightwave circuits.

Analysis of high-k spacer on symmetric underlap DG-MOSFET with Gate Stack architecture

NASA Astrophysics Data System (ADS)

Das, Rahul; Chakraborty, Shramana; Dasgupta, Arpan; Dutta, Arka; Kundu, Atanu; Sarkar, Chandan K.

2016-09-01

This paper shows the systematic study of underlap double gate (U-DG) NMOSFETs with Gate Stack (GS) under the influence of high-k spacers. In highly scaled devices, underlap is used at the Source and Drain side so as to reduce the short channel effects (SCE's), however, it significantly reduces the on current due to the increased channel resistance. To overcome these drawbacks, the use of high-k spacers is projected as one of the remedies. In this paper, the analog performance of the devices is studied on the basis of parameters like transconductance (gm), transconductance generation factor (gm/Id) and intrinsic gain (gmro). The RF performance is analyzed on the merits of intrinsic capacitance (Cgd, Cgs), resistance (Rgd, Rgs), transport delay (τm), inductance (Lsd), cutoff frequency (fT), and the maximum frequency of oscillation (fmax). The circuit performance of the devices are studied by implementing the device as the driver MOSFET in a Single Stage Common Source Amplifier. The Gain Bandwidth Product (GBW) has been analyzed from the frequency response of the circuit.

Optimization of L-shaped tunneling field-effect transistor for ambipolar current suppression and Analog/RF performance enhancement

NASA Astrophysics Data System (ADS)

Li, Cong; Zhao, Xiaolong; Zhuang, Yiqi; Yan, Zhirui; Guo, Jiaming; Han, Ru

2018-03-01

L-shaped tunneling field-effect transistor (LTFET) has larger tunnel area than planar TFET, which leads to enhanced on-current ION . However, LTFET suffers from severe ambipolar behavior, which needs to be further optimized for low power and high-frequency applications. In this paper, both hetero-gate-dielectric (HGD) and lightly doped drain (LDD) structures are introduced into LTFET for suppression of ambipolarity and improvement of analog/RF performance of LTFET. Current-voltage characteristics, the variation of energy band diagrams, distribution of band-to-band tunneling (BTBT) generation and distribution of electric field are analyzed for our proposed HGD-LDD-LTFET. In addition, the effect of LDD on the ambipolar behavior of LTFET is investigated, the length and doping concentration of LDD is also optimized for better suppression of ambipolar current. Finally, analog/RF performance of HGD-LDD-LTFET are studied in terms of gate-source capacitance, gate-drain capacitance, cut-off frequency, and gain bandwidth production. TCAD simulation results show that HGD-LDD-LTFET not only drastically suppresses ambipolar current but also improves analog/RF performance compared with conventional LTFET.

Analysis of DC and analog/RF performance on Cyl-GAA-TFET using distinct device geometry

NASA Astrophysics Data System (ADS)

Vishvakarma, S. K.; Beohar, Ankur; Vijayvargiya, Vikas; Trivedi, Priyal

2017-07-01

In this paper, analysis of DC and analog/RF performance on cylindrical gate-all-around tunnel field-effect transistor (TFET) has been made using distinct device geometry. Firstly, performance parameters of GAA-TFET are analyzed in terms of drain current, gate capacitances, transconductance, source-drain conductance at different radii and channel length. Furthermore, we also produce the geometrical analysis towards the optimized investigation of radio frequency parameters like cut-off frequency, maximum oscillation frequency and gain bandwidth product using a 3D technology computer-aided design ATLAS. Due to band-to-band tunneling based current mechanism unlike MOSFET, gate-bias dependence values as primary parameters of TFET differ. We also analyze that the maximum current occurs when radii of Si is around 8 nm due to high gate controllability over channel with reduced fringing effects and also there is no change in the current of TFET on varying its length from 100 to 40 nm. However current starts to increase when channel length is further reduced for 40 to 30 nm. Both of these trades-offs affect the RF performance of the device. Project supported by the Council of Scientific and Industrial Research (CSIR) Funded Research Project, Grant No. 22/0651/14/EMR-II, Government of India.

Ka-band Ga-As FET noise receiver/device development

NASA Technical Reports Server (NTRS)

Schellenberg, J. M.; Feng, M.; Hackett, L. H.; Watkins, E. T.; Yamasaki, H.

1982-01-01

The development of technology for a 30 GHz low noise receiver utilizing GaAs FET devices exclusively is discussed. This program required single and dual-gate FET devices, low noise FET amplifiers, dual-gate FET mixers, and FET oscillators operating at Ka-band frequencies. A 0.25 micrometer gate FET device, developed with a minimum noise figure of 3.3 dB at 29 GHz and an associated gain of 7.4 dB, was used to fabricate a 3-stage amplifier with a minimum noise figure and associated gain of 4.4 dB and 17 dB, respectively. The 1-dB gain bandwidth of this amplifier extended from below 26.5 GHz to 30.5 GHz. A dual-gate mixer with a 2 dB conversion loss and a minimum noise figure of 10 dB at 29 GHz as well as a dielectric resonator stabilized FET oscillator at 25 GHz for the receiver L0. From these components, a hybrid microwave integrated circuit receiver was constructed which demonstrates a minimum single-side band noise figure of 4.6 dB at 29 GHz with a conversion gain of 17 dB. The output power at the 1-dB gain compression point was -5 dBm.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jin, Zheming; Yoshii, Kazutomo; Finkel, Hal

Open Computing Language (OpenCL) is a high-level language that enables software programmers to explore Field Programmable Gate Arrays (FPGAs) for application acceleration. The Intel FPGA software development kit (SDK) for OpenCL allows a user to specify applications at a high level and explore the performance of low-level hardware acceleration. In this report, we present the FPGA performance and power consumption results of the single-precision floating-point vector add OpenCL kernel using the Intel FPGA SDK for OpenCL on the Nallatech 385A FPGA board. The board features an Arria 10 FPGA. We evaluate the FPGA implementations using the compute unit duplication andmore » kernel vectorization optimization techniques. On the Nallatech 385A FPGA board, the maximum compute kernel bandwidth we achieve is 25.8 GB/s, approximately 76% of the peak memory bandwidth. The power consumption of the FPGA device when running the kernels ranges from 29W to 42W.« less

The time resolved measurement of ultrashort terahertz-band electric fields without an ultrashort probe

DOE Office of Scientific and Technical Information (OSTI.GOV)

Walsh, D. A., E-mail: david.walsh@stfc.ac.uk; Snedden, E. W.; Jamison, S. P.

The time-resolved detection of ultrashort pulsed THz-band electric field temporal profiles without an ultrashort laser probe is demonstrated. A non-linear interaction between a narrow-bandwidth optical probe and the THz pulse transposes the THz spectral intensity and phase information to the optical region, thereby generating an optical pulse whose temporal electric field envelope replicates the temporal profile of the real THz electric field. This optical envelope is characterised via an autocorrelation based FROG (frequency resolved optical gating) measurement, hence revealing the THz temporal profile. The combination of a narrow-bandwidth, long duration, optical probe, and self-referenced FROG makes the technique inherently immunemore » to timing jitter between the optical probe and THz pulse and may find particular application where the THz field is not initially generated via ultrashort laser methods, such as the measurement of longitudinal electron bunch profiles in particle accelerators.« less

Characteristics and instabilities of mode-locked quantum-dot diode lasers.

PubMed

Li, Yan; Lester, Luke F; Chang, Derek; Langrock, Carsten; Fejer, M M; Kane, Daniel J

2013-04-08

Current pulse measurement methods have proven inadequate to fully understand the characteristics of passively mode-locked quantum-dot diode lasers. These devices are very difficult to characterize because of their low peak powers, high bandwidth, large time-bandwidth product, and large timing jitter. In this paper, we discuss the origin for the inadequacies of current pulse measurement techniques while presenting new ways of examining frequency-resolved optical gating (FROG) data to provide insight into the operation of these devices. Under the assumptions of a partial coherence model for the pulsed laser, it is shown that simultaneous time-frequency characterization is a necessary and sufficient condition for characterization of mode-locking. Full pulse characterization of quantum dot passively mode-locked lasers (QD MLLs) was done using FROG in a collinear configuration using an aperiodically poled lithium niobate waveguide-based FROG pulse measurement system.

Classified one-step high-radix signed-digit arithmetic units

NASA Astrophysics Data System (ADS)

Cherri, Abdallah K.

1998-08-01

High-radix number systems enable higher information storage density, less complexity, fewer system components, and fewer cascaded gates and operations. A simple one-step fully parallel high-radix signed-digit arithmetic is proposed for parallel optical computing based on new joint spatial encodings. This reduces hardware requirements and improves throughput by reducing the space-bandwidth produce needed. The high-radix signed-digit arithmetic operations are based on classifying the neighboring input digit pairs into various groups to reduce the computation rules. A new joint spatial encoding technique is developed to present both the operands and the computation rules. This technique increases the spatial bandwidth product of the spatial light modulators of the system. An optical implementation of the proposed high-radix signed-digit arithmetic operations is also presented. It is shown that our one-step trinary signed-digit and quaternary signed-digit arithmetic units are much simpler and better than all previously reported high-radix signed-digit techniques.

Chip-package nano-structured copper and nickel interconnections with metallic and polymeric bonding interfaces

NASA Astrophysics Data System (ADS)

Aggarwal, Ankur

With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 that support computing speed in terabits per second, with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Decreasing I/O pitch together with low cost, high electrical performance and high reliability are the key technological challenges identified by the 2005 International Technology Roadmap for Semiconductors (ITRS). Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. In addition, the materials must be environmentally-friendly, corrosion resistant, thermally stable over a long time, and resistant to electro-migration. A major challenge is also to develop economic processes that can be integrated into back end of the wafer foundry, i.e. with wafer level packaging. Device-to-system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches of the order of 30 microns and less. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. A novel chip-package interconnection technology is developed to address the IC packaging requirements beyond the ITRS projections and to introduce innovative design and fabrication concepts that will further advance the performance of the chip, the package, and the system board. The nano-structured interconnect technology simultaneously packages all the ICs intact in wafer form with quantum jump in the number of interconnections with the lowest electrical parasitics. The intrinsic properties of nano materials also enable several orders of magnitude higher interconnect densities with the best mechanical properties for the highest reliability and yet provide higher current and heat transfer densities. Nano-structured interconnects provides the ability to assemble the packaged parts on the system board without the use of underfill materials and to enable advanced analog/digital testing, reliability testing, and burn-in at wafer level. This thesis investigates the electrical and mechanical performance of nanostructured interconnections through modeling and test vehicle fabrication. The analytical models evaluate the performance improvements over solder and compliant interconnections. Test vehicles with nano-interconnections were fabricated using low cost electro-deposition techniques and assembled with various bonding interfaces. Interconnections were fabricated at 200 micron pitch to compare with the existing solder joints and at 50 micron pitch to demonstrate fabrication processes at fine pitches. Experimental and modeling results show that the proposed nano-interconnections could enhance the reliability and potentially meet all the system performance requirements for the emerging micro/nano-systems.

Development of digital sideband separating down-conversion for Yuan-Tseh Lee Array

NASA Astrophysics Data System (ADS)

Li, Chao-Te; Kubo, Derek; Cheng, Jen-Chieh; Kuroda, John; Srinivasan, Ranjani; Ho, Solomon; Guzzino, Kim; Chen, Ming-Tang

2016-07-01

This report presents a down-conversion method involving digital sideband separation for the Yuan-Tseh Lee Array (YTLA) to double the processing bandwidth. The receiver consists of a MMIC HEMT LNA front end operating at a wavelength of 3 mm, and sub-harmonic mixers that output signals at intermediate frequencies (IFs) of 2-18 GHz. The sideband separation scheme involves an analog 90° hybrid followed by two mixers that provide down-conversion of the IF signal to a pair of in-phase (I) and quadrature (Q) signals in baseband. The I and Q baseband signals are digitized using 5 Giga sample per second (Gsps) analog-to-digital converters (ADCs). A second hybrid is digitally implemented using field-programmable gate arrays (FPGAs) to produce two sidebands, each with a bandwidth of 1.6 GHz. The 2 x 1.6 GHz band can be tuned to cover any 3.6 GHz window within the aforementioned IF range of the array. Sideband rejection ratios (SRRs) above 20 dB can be obtained across the 3.6 GHz bandwidth by equalizing the power and delay between the I and Q baseband signals. Furthermore, SRRs above 30 dB can be achieved when calibration is applied.

Digital Intermediate Frequency Receiver Module For Use In Airborne Sar Applications

DOEpatents

Tise, Bertice L.; Dubbert, Dale F.

2005-03-08

A digital IF receiver (DRX) module directly compatible with advanced radar systems such as synthetic aperture radar (SAR) systems. The DRX can combine a 1 G-Sample/sec 8-bit ADC with high-speed digital signal processor, such as high gate-count FPGA technology or ASICs to realize a wideband IF receiver. DSP operations implemented in the DRX can include quadrature demodulation and multi-rate, variable-bandwidth IF filtering. Pulse-to-pulse (Doppler domain) filtering can also be implemented in the form of a presummer (accumulator) and an azimuth prefilter. An out of band noise source can be employed to provide a dither signal to the ADC, and later be removed by digital signal processing. Both the range and Doppler domain filtering operations can be implemented using a unique pane architecture which allows on-the-fly selection of the filter decimation factor, and hence, the filter bandwidth. The DRX module can include a standard VME-64 interface for control, status, and programming. An interface can provide phase history data to the real-time image formation processors. A third front-panel data port (FPDP) interface can send wide bandwidth, raw phase histories to a real-time phase history recorder for ground processing.

Next-generation optical wireless communications for data centers

NASA Astrophysics Data System (ADS)

Arnon, Shlomi

2015-01-01

Data centers collect and process information with a capacity that has been increasing from year to year at an almost exponential pace. Traditional fiber/cable data center network interconnections suffer from bandwidth overload, as well as flexibility and scalability issues. Therefore, a technology-shift from the fiber and cable to wireless has already been initiated in order to meet the required data-rate, flexibility and scalability demands for next-generation data center network interconnects. In addition, the shift to wireless reduces the volume allocated to the cabling/fiber and increases the cooling efficiency. Optical wireless communication (OWC), or free space optics (FSO), is one of the most effective wireless technologies that could be used in future data centers and could provide ultra-high capacity, very high cyber security and minimum latency, due to the low index of refraction of air in comparison to fiber technologies. In this paper we review the main concepts and configurations for next generation OWC for data centers. Two families of technologies are reviewed: the first technology regards interconnects between rack units in the same rack and the second technology regards the data center network that connects the server top of rack (TOR) to the switch. A comparison between different network technologies is presented.

Performance evaluation of multi-stratum resources integrated resilience for software defined inter-data center interconnect.

PubMed

Yang, Hui; Zhang, Jie; Zhao, Yongli; Ji, Yuefeng; Wu, Jialin; Lin, Yi; Han, Jianrui; Lee, Young

2015-05-18

Inter-data center interconnect with IP over elastic optical network (EON) is a promising scenario to meet the high burstiness and high-bandwidth requirements of data center services. In our previous work, we implemented multi-stratum resources integration among IP networks, optical networks and application stratums resources that allows to accommodate data center services. In view of this, this study extends to consider the service resilience in case of edge optical node failure. We propose a novel multi-stratum resources integrated resilience (MSRIR) architecture for the services in software defined inter-data center interconnect based on IP over EON. A global resources integrated resilience (GRIR) algorithm is introduced based on the proposed architecture. The MSRIR can enable cross stratum optimization and provide resilience using the multiple stratums resources, and enhance the data center service resilience responsiveness to the dynamic end-to-end service demands. The overall feasibility and efficiency of the proposed architecture is experimentally verified on the control plane of our OpenFlow-based enhanced SDN (eSDN) testbed. The performance of GRIR algorithm under heavy traffic load scenario is also quantitatively evaluated based on MSRIR architecture in terms of path blocking probability, resilience latency and resource utilization, compared with other resilience algorithms.

Modeling a Million-Node Slim Fly Network Using Parallel Discrete-Event Simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wolfe, Noah; Carothers, Christopher; Mubarak, Misbah

As supercomputers close in on exascale performance, the increased number of processors and processing power translates to an increased demand on the underlying network interconnect. The Slim Fly network topology, a new lowdiameter and low-latency interconnection network, is gaining interest as one possible solution for next-generation supercomputing interconnect systems. In this paper, we present a high-fidelity Slim Fly it-level model leveraging the Rensselaer Optimistic Simulation System (ROSS) and Co-Design of Exascale Storage (CODES) frameworks. We validate our Slim Fly model with the Kathareios et al. Slim Fly model results provided at moderately sized network scales. We further scale the modelmore » size up to n unprecedented 1 million compute nodes; and through visualization of network simulation metrics such as link bandwidth, packet latency, and port occupancy, we get an insight into the network behavior at the million-node scale. We also show linear strong scaling of the Slim Fly model on an Intel cluster achieving a peak event rate of 36 million events per second using 128 MPI tasks to process 7 billion events. Detailed analysis of the underlying discrete-event simulation performance shows that a million-node Slim Fly model simulation can execute in 198 seconds on the Intel cluster.« less

Performance evaluation of multi-stratum resources integration based on network function virtualization in software defined elastic data center optical interconnect.

PubMed

Yang, Hui; Zhang, Jie; Ji, Yuefeng; Tian, Rui; Han, Jianrui; Lee, Young

2015-11-30

Data center interconnect with elastic optical network is a promising scenario to meet the high burstiness and high-bandwidth requirements of data center services. In our previous work, we implemented multi-stratum resilience between IP and elastic optical networks that allows to accommodate data center services. In view of this, this study extends to consider the resource integration by breaking the limit of network device, which can enhance the resource utilization. We propose a novel multi-stratum resources integration (MSRI) architecture based on network function virtualization in software defined elastic data center optical interconnect. A resource integrated mapping (RIM) scheme for MSRI is introduced in the proposed architecture. The MSRI can accommodate the data center services with resources integration when the single function or resource is relatively scarce to provision the services, and enhance globally integrated optimization of optical network and application resources. The overall feasibility and efficiency of the proposed architecture are experimentally verified on the control plane of OpenFlow-based enhanced software defined networking (eSDN) testbed. The performance of RIM scheme under heavy traffic load scenario is also quantitatively evaluated based on MSRI architecture in terms of path blocking probability, provisioning latency and resource utilization, compared with other provisioning schemes.

Optical interconnects based on VCSELs and low-loss silicon photonics

NASA Astrophysics Data System (ADS)

Aalto, Timo; Harjanne, Mikko; Karppinen, Mikko; Cherchi, Matteo; Sitomaniemi, Aila; Ollila, Jyrki; Malacarne, Antonio; Neumeyr, Christian

2018-02-01

Silicon photonics with micron-scale Si waveguides offers most of the benefits of submicron SOI technology while avoiding most of its limitations. In particular, thick silicon-on-insulator (SOI) waveguides offer 0.1 dB/cm propagation loss, polarization independency, broadband single-mode (SM) operation from 1.2 to >4 µm wavelength and ability to transmit high optical powers (>1 W). Here we describe the feasibility of Thick-SOI technology for advanced optical interconnects. With 12 μm SOI waveguides we demonstrate efficient coupling between standard single-mode fibers, vertical-cavity surface-emitting lasers (VCSELs) and photodetectors (PDs), as well as wavelength multiplexing in small footprint. Discrete VCSELs and PDs already support 28 Gb/s on-off keying (OOK), which shows a path towards 50-100 Gb/s bandwidth per wavelength by using more advanced modulation formats like PAM4. Directly modulated VCSELs enable very power-efficient optical interconnects for up to 40 km distance. Furthermore, with 3 μm SOI waveguides we demonstrate extremely dense and low-loss integration of numerous optical functions, such as multiplexers, filters, switches and delay lines. Also polarization independent and athermal operation is demonstrated. The latter is achieved by using short polymer waveguides to compensate for the thermo-optic effect in silicon. New concepts for isolator integration and polarization rotation are also explained.

Evolution of a designless nanoparticle network into reconfigurable Boolean logic

NASA Astrophysics Data System (ADS)

Bose, S. K.; Lawrence, C. P.; Liu, Z.; Makarenko, K. S.; van Damme, R. M. J.; Broersma, H. J.; van der Wiel, W. G.

2015-12-01

Natural computers exploit the emergent properties and massive parallelism of interconnected networks of locally active components. Evolution has resulted in systems that compute quickly and that use energy efficiently, utilizing whatever physical properties are exploitable. Man-made computers, on the other hand, are based on circuits of functional units that follow given design rules. Hence, potentially exploitable physical processes, such as capacitive crosstalk, to solve a problem are left out. Until now, designless nanoscale networks of inanimate matter that exhibit robust computational functionality had not been realized. Here we artificially evolve the electrical properties of a disordered nanomaterials system (by optimizing the values of control voltages using a genetic algorithm) to perform computational tasks reconfigurably. We exploit the rich behaviour that emerges from interconnected metal nanoparticles, which act as strongly nonlinear single-electron transistors, and find that this nanoscale architecture can be configured in situ into any Boolean logic gate. This universal, reconfigurable gate would require about ten transistors in a conventional circuit. Our system meets the criteria for the physical realization of (cellular) neural networks: universality (arbitrary Boolean functions), compactness, robustness and evolvability, which implies scalability to perform more advanced tasks. Our evolutionary approach works around device-to-device variations and the accompanying uncertainties in performance. Moreover, it bears a great potential for more energy-efficient computation, and for solving problems that are very hard to tackle in conventional architectures.

Interfacing a high performance disk array file server to a Gigabit LAN

NASA Technical Reports Server (NTRS)

Seshan, Srinivasan; Katz, Randy H.

1993-01-01

Our previous prototype, RAID-1, identified several bottlenecks in typical file server architectures. The most important bottleneck was the lack of a high-bandwidth path between disk, memory, and the network. Workstation servers, such as the Sun-4/280, have very slow access to peripherals on busses far from the CPU. For the RAID-2 system, we addressed this problem by designing a crossbar interconnect, Xbus board, that provides a 40MB/s path between disk, memory, and the network interfaces. However, this interconnect does not provide the system CPU with low latency access to control the various interfaces. To provide a high data rate to clients on the network, we were forced to carefully and efficiently design the network software. A block diagram of the system hardware architecture is given. In the following subsections, we describe pieces of the RAID-2 file server hardware that had a significant impact on the design of the network interface.

High-speed ADC and DAC modules with fibre optic interconnections for telecom satellites

NASA Astrophysics Data System (ADS)

Heikkinen, Veli; Juntunen, Eveliina; Karppinen, Mikko; Kautio, Kari; Ollila, Jyrki; Sitomaniemi, Aila; Tanskanen, Antti; Casey, Rory; Scott, Shane; Gachon, Hélène; Sotom, Michel; Venet, Norbert; Toivonen, Jaakko; Tuominen, Taisto; Karafolas, Nikos

2017-11-01

The flexibility required for future telecom payloads calls for the introduction of more and more digital processing capabilities. Aggregate data throughputs of several Tbps will have to be handled onboard, thus creating the need for effective, ADCDSP and DACDSP highspeed links. ADC and DAC modules with optical interconnections is an attractive option as it can solve easily the transmission and routing of the expected huge amount of data. This technique will enable to increase the bandwidth and/or the number of beams/channels to be treated, or to support advanced digital processing architectures including beam forming. We realised electrooptic ADC and DAC modules containing an 8 bit, 2 GSa/s A/D converter and a 12 bit, 2 GSa/s D/A converter. The 4channel parallel fibre optic link employs 850nm VCSELs and GaAs PIN photodiodes coupled to 50/125μm fibre ribbon cable. ADCDSP and DSPDAC links both have an aggregate data rate of 25 Gbps. The paper presents the current status of this development.

Exascale Hardware Architectures Working Group

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hemmert, S; Ang, J; Chiang, P

2011-03-15

The ASC Exascale Hardware Architecture working group is challenged to provide input on the following areas impacting the future use and usability of potential exascale computer systems: processor, memory, and interconnect architectures, as well as the power and resilience of these systems. Going forward, there are many challenging issues that will need to be addressed. First, power constraints in processor technologies will lead to steady increases in parallelism within a socket. Additionally, all cores may not be fully independent nor fully general purpose. Second, there is a clear trend toward less balanced machines, in terms of compute capability compared tomore » memory and interconnect performance. In order to mitigate the memory issues, memory technologies will introduce 3D stacking, eventually moving on-socket and likely on-die, providing greatly increased bandwidth but unfortunately also likely providing smaller memory capacity per core. Off-socket memory, possibly in the form of non-volatile memory, will create a complex memory hierarchy. Third, communication energy will dominate the energy required to compute, such that interconnect power and bandwidth will have a significant impact. All of the above changes are driven by the need for greatly increased energy efficiency, as current technology will prove unsuitable for exascale, due to unsustainable power requirements of such a system. These changes will have the most significant impact on programming models and algorithms, but they will be felt across all layers of the machine. There is clear need to engage all ASC working groups in planning for how to deal with technological changes of this magnitude. The primary function of the Hardware Architecture Working Group is to facilitate codesign with hardware vendors to ensure future exascale platforms are capable of efficiently supporting the ASC applications, which in turn need to meet the mission needs of the NNSA Stockpile Stewardship Program. This issue is relatively immediate, as there is only a small window of opportunity to influence hardware design for 2018 machines. Given the short timeline a firm co-design methodology with vendors is of prime importance.« less

Extreme nonlinear terahertz electro-optics in diamond for ultrafast pulse switching

NASA Astrophysics Data System (ADS)

Shalaby, Mostafa; Vicario, Carlo; Hauri, Christoph P.

2017-03-01

Polarization switching of picosecond laser pulses is a fundamental concept in signal processing [C. Chen and G. Liu, Annu. Rev. Mater. Sci. 16, 203 (1986); V. R. Almeida et al., Nature 431, 1081 (2004); and A. A. P. Pohl et al., Photonics Sens. 3, 1 (2013)]. Conventional switching devices rely on the electro-optical Pockels effect and work at radio frequencies. The ensuing gating time of several nanoseconds is a bottleneck for faster switches which is set by the performance of state-of-the-art high-voltage electronics. Here we show that by substituting the electric field of several kV/cm provided by modern electronics by the MV/cm field of a single-cycle THz laser pulse, the electro-optical gating process can be driven orders of magnitude faster, at THz frequencies. In this context, we introduce diamond as an exceptional electro-optical material and demonstrate a pulse gating time as fast as 100 fs using sub-cycle THz-induced Kerr nonlinearity. We show that THz-induced switching in the insulator diamond is fully governed by the THz pulse shape. The presented THz-based electro-optical approach overcomes the bandwidth and switching speed limits of conventional MHz/GHz electronics and establishes the ultrafast electro-optical gating technology for the first time in the THz frequency range. We finally show that the presented THz polarization gating technique is applicable for advanced beam diagnostics. As a first example, we demonstrate tomographic reconstruction of a THz pulse in three dimensions.

All-optical LAN architectures based on arrayed waveguide grating multiplexers

NASA Astrophysics Data System (ADS)

Woesner, Hagen

1998-10-01

The paper presents optical LAN topologies which are made possible using an Arrayed Waveguide Grating Multiplexer (AWGM) instead of a passive star coupler to interconnect stations in an all-optical LAN. Due to the collision-free nature of an AWGM it offers the n-fold bandwidth compared to the star coupler. Virtual ring topologies appear (one ring on each wavelength) if the number of stations attached to the AWGM is a prime number. A method to construct larger networks using Cayley graphs is shown. An access protocol to avoid collisions on the proposed network is outlined.

GaAs VLSI for aerospace electronics

NASA Technical Reports Server (NTRS)

Larue, G.; Chan, P.

1990-01-01

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

Inorganic nanotubes and electro-fluidic devices fabricated therefrom

DOEpatents

Yang, Peidong [Kensington, CA; Majumdar, Arunava [Orinda, CA; Fan, Rong [Pasadena, CA; Karnik, Rohit [Cambridge, MA

2011-03-01

Nanofluidic devices incorporating inorganic nanotubes fluidly coupled to channels or nanopores for supplying a fluid containing chemical or bio-chemical species are described. In one aspect, two channels are fluidly interconnected with a nanotube. Electrodes on opposing sides of the nanotube establish electrical contact with the fluid therein. A bias current is passed between the electrodes through the fluid, and current changes are detected to ascertain the passage of select molecules, such as DNA, through the nanotube. In another aspect, a gate electrode is located proximal the nanotube between the two electrodes thus forming a nanofluidic transistor. The voltage applied to the gate controls the passage of ionic species through the nanotube selected as either or both ionic polarities. In either of these aspects the nanotube can be modified, or functionalized, to control the selectivity of detection or passage.

Package architecture and component design for an implanted neural stimulator with closed loop control.

PubMed

Bjune, Caroline K; Marinis, Thomas F; Brady, Jeanne M; Moran, James; Wheeler, Jesse; Sriram, Tirunelveli S; Parks, Philip D; Widge, Alik S; Dougherty, Darin D; Eskandar, Emad N

2015-08-01

An implanted neural stimulator with closed loop control requires electrodes for stimulation pulses and recording neuron activity. Our system features arrays of 64 electrodes. Each electrode can be addressed through a cross bar switch, to enable it to be used for stimulation or recording. This electrode switch, a bank of low noise amplifiers with an integrated analog to digital converter, power conditioning electronics, and a communications and control gate array are co-located with the electrode array in a 14 millimeter diameter satellite package that is designed to be flush mounted in a skull burr hole. Our system features five satellite packages connected to a central hub processor-controller via ten conductor cables that terminate in a custom designed, miniaturized connector. The connector incorporates features of high reliability, military grade devices and utilizes three distinct seals to isolate the contacts from fluid permeation. The hub system is comprised of a connector header, hermetic electronics package, and rechargeable battery pack, which are mounted on and electrically interconnected by a flexible circuit board. The assembly is over molded with a compliant silicone rubber. The electronics package contains two antennas, a large coil, used for recharging the battery and a high bandwidth antenna that is used to download data and update software. The package is assembled from two machined alumina pieces, a flat base with brazed in, electrical feed through pins and a rectangular cover with rounded corners. Titanium seal rings are brazed onto these two pieces so that they can be sealed by laser welding. A third system antenna is incorporated in the flexible circuit board. It is used to communicate with an externally worn control package, which monitors the health of the system and allows both the user and clinician to control or modify various system function parameters.

A high speed and high gain CMOS receiver chip for a pulsed time-of-flight laser rangefinder

NASA Astrophysics Data System (ADS)

Yu, Jin-jin; Deng, Ruo-han; Yuan, Hong-hui; Chen, Yong-ping

2011-06-01

An integrated receiver channel for a pulsed time-of-flight (TOF) laser rangefinder has been designed. Pulsed TOF laser range finding devices using a laser diode transmitter can achieve millimeter-level distance measurement accuracy in a measurement range of several tens of meters to non-cooperative targets. The amplifier exploits the regulated cascade (RGC) configuration as the input-stage, thus achieving as large effective input trans-conductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. To enlarge the bandwidth, inductive peaking technology has been adopted. An active inductor (MOS-L) is used instead of spiral inductor in CMOS process. An R-2R resistor ladder is inserting between per-amplifier and post-amplifier as the variable attenuator for digital gain control purpose. The gain-bandwidth of a basic differential pair with resistive load is not large enough for broad band operation. A circuit solution to improve both gain and bandwidth of an amplifying stage is proposed. Traditional and modified Cherry-Hooper amplifiers are discussed and the cascading of several stages to constitute the post-amplifier is designed. The fully integrated one-chip solution is designed with Cadence IC design platform. The simulation result shows the bandwidth of the trans-impedance amplifier is 215MHz with the presence of a 2pF input capacitor and 5pF load capacitor. And the maximum trans-impedance gain is 136dB. The walk error is less than 1ns in 1:1000 dynamic range. The responsive time is less than 2.2ns.

ICE-Based Custom Full-Mesh Network for the CHIME High Bandwidth Radio Astronomy Correlator

NASA Astrophysics Data System (ADS)

Bandura, K.; Cliche, J. F.; Dobbs, M. A.; Gilbert, A. J.; Ittah, D.; Mena Parra, J.; Smecher, G.

2016-03-01

New generation radio interferometers encode signals from thousands of antenna feeds across large bandwidth. Channelizing and correlating this data requires networking capabilities that can handle unprecedented data rates with reasonable cost. The Canadian Hydrogen Intensity Mapping Experiment (CHIME) correlator processes 8-bits from N=2,048 digitizer inputs across 400MHz of bandwidth. Measured in N2× bandwidth, it is the largest radio correlator that is currently commissioning. Its digital back-end must exchange and reorganize the 6.6terabit/s produced by its 128 digitizing and channelizing nodes, and feed it to the 256 graphics processing unit (GPU) node spatial correlator in a way that each node obtains data from all digitizer inputs but across a small fraction of the bandwidth (i.e. ‘corner-turn’). In order to maximize performance and reliability of the corner-turn system while minimizing cost, a custom networking solution has been implemented. The system makes use of Field Programmable Gate Array (FPGA) transceivers to implement direct, passive copper, full-mesh, high speed serial connections between sixteen circuit boards in a crate, to exchange data between crates, and to offload the data to a cluster of 256 GPU nodes using standard 10Gbit/s Ethernet links. The GPU nodes complete the corner-turn by combining data from all crates and then computing visibilities. Eye diagrams and frame error counters confirm error-free operation of the corner-turn network in both the currently operating CHIME Pathfinder telescope (a prototype for the full CHIME telescope) and a representative fraction of the full CHIME hardware providing an end-to-end system validation. An analysis of an equivalent corner-turn system built with Ethernet switches instead of custom passive data links is provided.

TDR method for determine IC's parameters

NASA Astrophysics Data System (ADS)

Timoshenkov, V.; Rodionov, D.; Khlybov, A.

2016-12-01

Frequency domain simulation is a widely used approach for determine integrated circuits parameters. This approach can be found in most of software tools used in IC industry. Time domain simulation approach shows intensive usage last years due to some advantages. In particular it applicable for analysis of nonlinear and nonstationary systems where frequency domain is inapplicable. Resolution of time domain systems allow see heterogeneities on distance 1mm, determine it parameters and properties. Authors used approach based on detecting reflected signals from heterogeneities - time domain reflectometry (TDR). Field effect transistor technology scaling up to 30-60nm gate length and 10nm gate dielectric, heterojunction bi-polar transistors with 10-30nm base width allows fabricate digital IC's with 20GHz clock frequency and RF-IC's with tens GHz bandwidth. Such devices and operation speed suppose transit signal by use microwave lines. There are local heterogeneities can be found inside of the signal path due to connections between different parts of signal lines (stripe line-RF-connector pin, stripe line - IC package pin). These heterogeneities distort signals that cause bandwidth decrease for RF-devices. Time domain research methods of transmission and reflected signals give the opportunities to determine heterogeneities, it properties, parameters and built up equivalent circuits. Experimental results are provided and show possibility for inductance and capacitance measurement up to 25GHz. Measurements contains result of signal path research on IC and printed circuit board (PCB) used for 12GHz RF chips. Also dielectric constant versus frequency was measured up to 35GHz.

Towards the Formal Verification of a Distributed Real-Time Automotive System

NASA Technical Reports Server (NTRS)

Endres, Erik; Mueller, Christian; Shadrin, Andrey; Tverdyshev, Sergey

2010-01-01

We present the status of a project which aims at building, formally and pervasively verifying a distributed automotive system. The target system is a gate-level model which consists of several interconnected electronic control units with independent clocks. This model is verified against the specification as seen by a system programmer. The automotive system is implemented on several FPGA boards. The pervasive verification is carried out using combination of interactive theorem proving (Isabelle/HOL) and model checking (LTL).

ISITE: Automatic Circuit Synthesis for Double-Metal CMOS VLSI (Very Large Scale Integrated) Circuits

DTIC Science & Technology

1989-12-01

rows and columns should be minimized. There are two methodologies for achieving this objective, namely, logic minimization to I I I 15 I A B C D E T...type and N-type polysilicon (Figure 2.5( b )) and interconnecting the gates with metal at a later I processing step. The two layers of aluminum available...polysiliconI ...... .. ... .. .. . .. ... .. ... .. I N polysilicon Iii~~iiiiiiii~~iiiiii (a) ( b ) 3 Figure 2.5. Controlling the Threshold Voltage in

Chip-to-chip interconnects based on 3D stacking of optoelectrical dies on Si

NASA Astrophysics Data System (ADS)

Duan, P.; Raz, O.; Smalbrugge, B. E.; Duis, J.; Dorren, H. J. S.

2012-01-01

We demonstrate a new approach to increase the optical interconnection bandwidth density by stacking the opto-electrical dies directly on the CMOS driver. The suggested implementation is aiming to provide a wafer scale process which will make the use of wire bonding redundant and will allow for impedance matched metallic wiring between the electronic driving circuit and its opto-electronic counter part. We suggest the use of a thick photoresist ramp between CMOS driver and opto-electrical dies surface as the bridge for supporting co-plannar waveguides (CPW) electrically plated with lithographic accuracy. In this way all three dimensions of the interconnecting metal layer, width, length and thickness can be completely controlled. In this 1st demonstration all processing is done on commercially available devices and products, and is compatible with CMOS processing technology. To test the applicability of CPW instead of wire bonds for interconnecting the CMOS circuit and opto-electronic chips, we have made test samples and tested their performance at speeds up to 10 Gbps. In this demonstration, a silicon substrate was used on which we evaporated gold co-planar waveguides (CPW) to mimic a wire on the driver. An optical link consisting of a VCSEL chip and a photodiode chip has been assembled and fully characterized using optical coupling into and out of a multimode fiber (MMF). A 10 Gb/s 27-1 NRZ PRBS signal transmitted from one chip to another chip was detected error free. A 4 dB receiver sensitivity penalty is measured for the integrated device compared to a commercial link.

Mode selecting switch using multimode interference for on-chip optical interconnects.

PubMed

Priti, Rubana B; Pishvai Bazargani, Hamed; Xiong, Yule; Liboiron-Ladouceur, Odile

2017-10-15

A novel mode selecting switch (MSS) is experimentally demonstrated for on-chip mode-division multiplexing (MDM) optical interconnects. The MSS consists of a Mach-Zehnder interferometer with tapered multi-mode interference couplers and TiN thermo-optic phase shifters for conversion and switching between the optical data encoded on the fundamental and first-order quasi-transverse electric (TE) modes. The C-band MSS exhibits a >25  dB switching extinction ratio and < -12 dB crosstalk. We validate the dynamic switching with a 25.8 kHz gating signal measuring switching times for both TE0 and TE1 modes of <10.9  μs. All channels exhibit less than 1.7 dB power penalty at a 10 -12 bit error rate, while switching the non-return-to-zero PRBS-31 data signals at 10  Gb/s.

Assessment of left ventricular mechanical dyssynchrony by phase analysis of gated-SPECT myocardial perfusion imaging and tissue Doppler imaging: comparison between QGS and ECTb software packages.

PubMed

Rastgou, Fereydoon; Shojaeifard, Maryam; Amin, Ahmad; Ghaedian, Tahereh; Firoozabadi, Hasan; Malek, Hadi; Yaghoobi, Nahid; Bitarafan-Rajabi, Ahmad; Haghjoo, Majid; Amouzadeh, Hedieh; Barati, Hossein

2014-12-01

Recently, the phase analysis of gated single-photon emission computed tomography (SPECT) myocardial perfusion imaging (MPI) has become feasible via several software packages for the evaluation of left ventricular mechanical dyssynchrony. We compared two quantitative software packages, quantitative gated SPECT (QGS) and Emory cardiac toolbox (ECTb), with tissue Doppler imaging (TDI) as the conventional method for the evaluation of left ventricular mechanical dyssynchrony. Thirty-one patients with severe heart failure (ejection fraction ≤35%) and regular heart rhythm, who referred for gated-SPECT MPI, were enrolled. TDI was performed within 3 days after MPI. Dyssynchrony parameters derived from gated-SPECT MPI were analyzed by QGS and ECTb and were compared with the Yu index and septal-lateral wall delay measured by TDI. QGS and ECTb showed a good correlation for assessment of phase histogram bandwidth (PHB) and phase standard deviation (PSD) (r = 0.664 and r = 0.731, P < .001, respectively). However, the mean value of PHB and PSD by ECTb was significantly higher than that of QGS. No significant correlation was found between ECTb and QGS and the Yu index. Nevertheless, PHB, PSD, and entropy derived from QGS revealed a significant (r = 0.424, r = 0.478, r = 0.543, respectively; P < .02) correlation with septal-lateral wall delay. Despite a good correlation between QGS and ECTb software packages, different normal cut-off values of PSD and PHB should be defined for each software package. There was only a modest correlation between phase analysis of gated-SPECT MPI and TDI data, especially in the population of heart failure patients with both narrow and wide QRS complex.

Metamaterial-inspired reconfigurable series-fed arrays

NASA Astrophysics Data System (ADS)

Ijaz, Bilal

One of the biggest challenges in modern day wireless communication systems is to attain agility and provide more degrees of freedom in parameters such as frequency, radiation pattern and polarization. Existing phased array antenna technology has limitations in frequency bandwidth and scan angle. So it is important to design frequency reconfigurable antenna arrays which can provide two different frequency bandwidths with a broadside radiation pattern having a lower sidelobe and reduced frequency scanning. The reconfigurable antenna array inspired by the properties of metamaterials presented here provides a solution to attain frequency agility in a wireless communication system. The adaptive change in operating frequency is attained by using RF p-i-n diodes on the antenna array. The artificially made materials having properties of negative permeability and negative permittivity have antiparallel group and phase velocities, and, in consequence of that, they support backward wave propagation. The key idea of this work is to demonstrate that the properties of metamaterial non-radiating phase shifting transmission lines can be utilized to design a series-fed antenna array to operate at two different frequency bands with a broadside radiation pattern in both configurations. In this research, first, a design of a series-fed microstrip array with composite right/left-handed transmission lines (CRLH-TLs) is proposed. To ensure that each element in the array is driven with the same voltage phase, dual-band CRLH-TLs are adopted instead of meander-line microstrip lines to provide a compact interconnect with a zero phase-constant at the frequency of operation. Next, the work is extended to design a reconfigurable series-fed antenna array with reconfigurable metamaterial interconnects, and the expressions for array factor are derived for both switching bands.

PAM4 silicon photonic microring resonator-based transceiver circuits

NASA Astrophysics Data System (ADS)

Palermo, Samuel; Yu, Kunzhi; Roshan-Zamir, Ashkan; Wang, Binhao; Li, Cheng; Seyedi, M. Ashkan; Fiorentino, Marco; Beausoleil, Raymond

2017-02-01

Increased data rates have motivated the investigation of advanced modulation schemes, such as four-level pulseamplitude modulation (PAM4), in optical interconnect systems in order to enable longer transmission distances and operation with reduced circuit bandwidth relative to non-return-to-zero (NRZ) modulation. Employing this modulation scheme in interconnect architectures based on high-Q silicon photonic microring resonator devices, which occupy small area and allow for inherent wavelength-division multiplexing (WDM), offers a promising solution to address the dramatic increase in datacenter and high-performance computing system I/O bandwidth demands. Two ring modulator device structures are proposed for PAM4 modulation, including a single phase shifter segment device driven with a multi-level PAM4 transmitter and a two-segment device driven by two simple NRZ (MSB/LSB) transmitters. Transmitter circuits which utilize segmented pulsed-cascode high swing output stages are presented for both device structures. Output stage segmentation is utilized in the single-segment device design for PAM4 voltage level control, while in the two-segment design it is used for both independent MSB/LSB voltage levels and impedance control for output eye skew compensation. The 65nm CMOS transmitters supply a 4.4Vppd output swing for 40Gb/s operation when driving depletion-mode microring modulators implemented in a 130nm SOI process, with the single- and two-segment designs achieving 3.04 and 4.38mW/Gb/s, respectively. A PAM4 optical receiver front-end is also described which employs a large input-stage feedback resistor transimpedance amplifier (TIA) cascaded with an adaptively-tuned continuous-time linear equalizer (CTLE) for improved sensitivity. Receiver linearity, critical in PAM4 systems, is achieved with a peak-detector-based automatic gain control (AGC) loop.

Realization of optical multimode TSV waveguides for Si-Interposer in 3D-chip-stacks

NASA Astrophysics Data System (ADS)

Killge, S.; Charania, S.; Richter, K.; Neumann, N.; Al-Husseini, Z.; Plettemeier, D.; Bartha, J. W.

2017-05-01

Optical connectivity has the potential to outperform copper-based TSVs in terms of bandwidth at the cost of more complexity due to the required electro-optical and opto-electrical conversion. The continuously increasing demand for higher bandwidth pushes the breakeven point for a profitable operation to shorter distances. To integrate an optical communication network in a 3D-chip-stack optical through-silicon vertical VIAs (TSV) are required. While the necessary effort for the electrical/optical and vice versa conversion makes it hard to envision an on-chip optical interconnect, a chip-to-chip optical link appears practicable. In general, the interposer offers the potential advantage to realize electro-optical transceivers on affordable expense by specific, but not necessarily CMOS technology. We investigated the realization and characterization of optical interconnects as a polymer based waveguide in high aspect ratio (HAR) TSVs proved on waferlevel. To guide the optical field inside a TSV as optical-waveguide or fiber, its core has to have a higher refractive index than the surrounding material. Comparing different material / technology options it turned out that thermal grown silicon dioxide (SiO2) is a perfect candidate for the cladding (nSiO2 = 1.4525 at 850 nm). In combination with SiO2 as the adjacent polymer layer, the negative resist SU-8 is very well suited as waveguide material (nSU-8 = 1.56) for the core. Here, we present the fabrication of an optical polymer based multimode waveguide in TSVs proved on waferlevel using SU-8 as core and SiO2 as cladding. The process resulted in a defect-free filling of waveguide TSVs with SU-8 core and SiO2 cladding up to aspect ratio (AR) 20:1 and losses less than 3 dB.

500 GHz Optical Sampler for Advancing Nonlinear Processing with Generalized Optical Pulses

DTIC Science & Technology

2015-10-19

that obtainable with electronics. Wide bandwidth  pulses have a variety of applications such as in microwave signal processing,  ultra ‐ wideband ...fiber‐based entangled photon source, the first  ultra ‐fast low‐loss single photon switch, and the first  telecom‐band linear optics C‐Not gate. We

Study of radar pulse compression for high resolution satellite altimetry

NASA Technical Reports Server (NTRS)

Dooley, R. P.; Nathanson, F. E.; Brooks, L. W.

1974-01-01

Pulse compression techniques are studied which are applicable to a satellite altimeter having a topographic resolution of + 10 cm. A systematic design procedure is used to determine the system parameters. The performance of an optimum, maximum likelihood processor is analysed, which provides the basis for modifying the standard split-gate tracker to achieve improved performance. Bandwidth considerations lead to the recommendation of a full deramp STRETCH pulse compression technique followed by an analog filter bank to separate range returns. The implementation of the recommended technique is examined.

Normal values and standardization of parameters in nuclear cardiology: Japanese Society of Nuclear Medicine working group database.

PubMed

Nakajima, Kenichi; Matsumoto, Naoya; Kasai, Tokuo; Matsuo, Shinro; Kiso, Keisuke; Okuda, Koichi

2016-04-01

As a 2-year project of the Japanese Society of Nuclear Medicine working group activity, normal myocardial imaging databases were accumulated and summarized. Stress-rest with gated and non-gated image sets were accumulated for myocardial perfusion imaging and could be used for perfusion defect scoring and normal left ventricular (LV) function analysis. For single-photon emission computed tomography (SPECT) with multi-focal collimator design, databases of supine and prone positions and computed tomography (CT)-based attenuation correction were created. The CT-based correction provided similar perfusion patterns between genders. In phase analysis of gated myocardial perfusion SPECT, a new approach for analyzing dyssynchrony, normal ranges of parameters for phase bandwidth, standard deviation and entropy were determined in four software programs. Although the results were not interchangeable, dependency on gender, ejection fraction and volumes were common characteristics of these parameters. Standardization of (123)I-MIBG sympathetic imaging was performed regarding heart-to-mediastinum ratio (HMR) using a calibration phantom method. The HMRs from any collimator types could be converted to the value with medium-energy comparable collimators. Appropriate quantification based on common normal databases and standard technology could play a pivotal role for clinical practice and researches.

Dangling-bond logic gates on a Si(100)-(2 × 1)-H surface.

PubMed

Kawai, Hiroyo; Ample, Francisco; Wang, Qing; Yeo, Yong Kiat; Saeys, Mark; Joachim, Christian

2012-03-07

Atomic-scale Boolean logic gates (LGs) with two inputs and one output (i.e. OR, NOR, AND, NAND) were designed on a Si(100)-(2 × 1)-H surface and connected to the macroscopic scale by metallic nano-pads physisorbed on the Si(100)-(2 × 1)-H surface. The logic inputs are provided by saturating and unsaturating two surface Si dangling bonds, which can, for example, be achieved by adding and extracting two hydrogen atoms per input. Quantum circuit design rules together with semi-empirical elastic-scattering quantum chemistry transport calculations were used to determine the output current intensity of the proposed switches and LGs when they are interconnected to the metallic nano-pads by surface atomic-scale wires. Our calculations demonstrate that the proposed devices can reach ON/OFF ratios of up to 2000 for a running current in the 10 µA range.

The initial characterization of a revised 10-Gsps analog-to-digital converter board for radio telescopes

NASA Astrophysics Data System (ADS)

Jiango, Homin; Liuo, Howard; Guzzino, Kim

2016-07-01

In this study, the design of a 4 bit, 10-gigasamples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was revised, manufactured, and tested. It is used for digitizing radio telescopes. An Adsantec ANST7120-KMA flash ADC chip was used, as in the original design. Associated with the field-programmable gate array platform developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the developed PCBA provides data acquisition systems with a wider bandwidth and simplifies the intermediate frequency section. The current version of the PCBA exhibits an analog bandwidth of up to 10 GHz (3 dB loss), and the chip exhibits an analog bandwidth of up to 18 GHz. This facilitates second and third Nyquist sampling. The following worstcase performance parameters were obtained from the revised PCBA at over 5 GHz: spurious-free dynamic range of 12 dB, signal-to-noise and distortion ratio of 2 dB, and effective number of bits of 0.7. The design bugs in the ADC chip caused the poor performance. The vendor created a new batch run and confirmed that the ADC chips of the new batch will meet the specifications addressed in its data sheet.

Wideband Agile Digital Microwave Radiometer

NASA Technical Reports Server (NTRS)

Gaier, Todd C.; Brown, Shannon T.; Ruf, Christopher; Gross, Steven

2012-01-01

The objectives of this work were to take the initial steps needed to develop a field programmable gate array (FPGA)- based wideband digital radiometer backend (>500 MHz bandwidth) that will enable passive microwave observations with minimal performance degradation in a radiofrequency-interference (RFI)-rich environment. As manmade RF emissions increase over time and fill more of the microwave spectrum, microwave radiometer science applications will be increasingly impacted in a negative way, and the current generation of spaceborne microwave radiometers that use broadband analog back ends will become severely compromised or unusable over an increasing fraction of time on orbit. There is a need to develop a digital radiometer back end that, for each observation period, uses digital signal processing (DSP) algorithms to identify the maximum amount of RFI-free spectrum across the radiometer band to preserve bandwidth to minimize radiometer noise (which is inversely related to the bandwidth). Ultimately, the objective is to incorporate all processing necessary in the back end to take contaminated input spectra and produce a single output value free of manmade signals to minimize data rates for spaceborne radiometer missions. But, to meet these objectives, several intermediate processing algorithms had to be developed, and their performance characterized relative to typical brightness temperature accuracy re quirements for current and future microwave radiometer missions, including those for measuring salinity, soil moisture, and snow pack.

Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system

NASA Astrophysics Data System (ADS)

Ammendola, R.; Biagioni, A.; Frezza, O.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Paolucci, P. S.; Pastorelli, E.; Rossetti, D.; Simula, F.; Tosoratto, L.; Vicini, P.

2015-12-01

In the attempt to develop an interconnection architecture optimized for hybrid HPC systems dedicated to scientific computing, we designed APEnet+, a point-to-point, low-latency and high-performance network controller supporting 6 fully bidirectional off-board links over a 3D torus topology. The first release of APEnet+ (named V4) was a board based on a 40 nm Altera FPGA, integrating 6 channels at 34 Gbps of raw bandwidth per direction and a PCIe Gen2 x8 host interface. It has been the first-of-its-kind device to implement an RDMA protocol to directly read/write data from/to Fermi and Kepler NVIDIA GPUs using NVIDIA peer-to-peer and GPUDirect RDMA protocols, obtaining real zero-copy GPU-to-GPU transfers over the network. The latest generation of APEnet+ systems (now named V5) implements a PCIe Gen3 x8 host interface on a 28 nm Altera Stratix V FPGA, with multi-standard fast transceivers (up to 14.4 Gbps) and an increased amount of configurable internal resources and hardware IP cores to support main interconnection standard protocols. Herein we present the APEnet+ V5 architecture, the status of its hardware and its system software design. Both its Linux Device Driver and the low-level libraries have been redeveloped to support the PCIe Gen3 protocol, introducing optimizations and solutions based on hardware/software co-design.

High-speed highly temperature stable 980 nm VCSELs operating at 25 Gb/s at up to 85 °C for short reach optical interconnects

NASA Astrophysics Data System (ADS)

Mutig, Alex; Lott, James A.; Blokhin, Sergey A.; Moser, Philip; Wolf, Philip; Hofmann, Werner; Nadtochiy, Alexey M.; Bimberg, Dieter

2011-03-01

The progressive penetration of optical communication links into traditional copper interconnect markets greatly expands the applications of vertical cavity surface emitting lasers (VCSELs) for the next-generation of board-to-board, moduleto- module, chip-to-chip, and on-chip optical interconnects. Stability of the VCSEL parameters at high temperatures is indispensable for such applications, since these lasers typically reside directly on or near integrated circuit chips. Here we present 980 nm oxide-confined VCSELs operating error-free at bit rates up to 25 Gbit/s at temperatures as high as 85 °C without adjustment of the drive current and peak-to-peak modulation voltage. The driver design is therefore simplified and the power consumption of the driver electronics is lowered, reducing the production and operational costs. Small and large signal modulation experiments at various temperatures from 20 up to 85 °C for lasers with different oxide aperture diameters are presented in order to analyze the physical processes controlling the performance of the VCSELs. Temperature insensitive maximum -3 dB bandwidths of around 13-15 GHz for VCSELs with aperture diameters of 10 μm and corresponding parasitic cut-off frequencies exceeding 22 GHz are observed. Presented results demonstrate the suitability of our VCSELs for practical high speed and high temperature stable short-reach optical links.

Elastic all-optical multi-hop interconnection in data centers with adaptive spectrum allocation

NASA Astrophysics Data System (ADS)

Hong, Yuanyuan; Hong, Xuezhi; Chen, Jiajia; He, Sailing

2017-01-01

In this paper, a novel flex-grid all-optical interconnect scheme that supports transparent multi-hop connections in data centers is proposed. An inter-rack all-optical multi-hop connection is realized with an optical loop employed at flex-grid wavelength selective switches (WSSs) in an intermediate rack rather than by relaying through optical-electric-optical (O-E-O) conversions. Compared with the conventional O-E-O based approach, the proposed all-optical scheme is able to off-load the traffic at intermediate racks, leading to a reduction of the power consumption and cost. The transmission performance of the proposed flex-grid multi-hop all-optical interconnect scheme with various modulation formats, including both coherently detected and directly detected approaches, are investigated by Monte-Carlo simulations. To enhance the spectrum efficiency (SE), number-of-hop adaptive bandwidth allocation is introduced. Numerical results show that the SE can be improved by up to 33.3% at 40 Gbps, and by up to 25% at 100 Gbps. The impact of parameters, such as targeted bit error rate (BER) level and insertion loss of components, on the transmission performance of the proposed approach are also explored. The results show that the maximum SE improvement of the adaptive approach over the non-adaptive one is enhanced with the decrease of the targeted BER levels and the component insertion loss.

Development of Laser Beam Transmission Strategies for Future Ground-to-Space Optical Communications

NASA Technical Reports Server (NTRS)

Wilson, Keith E.; Kovalik, Joseph M.; Biswas, Abhijit; Roberts, William T.

2007-01-01

Optical communications is a key technology to meet the bandwidth expansion required in the global information grid. High bandwidth bi-directional links between sub-orbital platforms and ground and space terminals can provide a seamless interconnectivity for rapid return of critical data to analysts. The JPL Optical Communications Telescope Laboratory (OCTL) is located in Wrightwood California at an altitude of 2.2.km. This 200 sq-m facility houses a state-of- the-art 1-m telescope and is used to develop operational strategies for ground-to-space laser beam propagation that include safe beam transmission through navigable air space, adaptive optics correction and multi-beam scintillation mitigation, and line of sight optical attenuation monitoring. JPL has received authorization from international satellite owners to transmit laser beams to more than twenty retro-reflecting satellites. This paper presents recent progress in the development of these operational strategies tested by narrow laser beam transmissions from the OCTL to retro-reflecting satellites. We present experimental results and compare our measurements with predicted performance for a variety of atmospheric conditions.

Stanford Hardware Development Program

NASA Technical Reports Server (NTRS)

Peterson, A.; Linscott, I.; Burr, J.

1986-01-01

Architectures for high performance, digital signal processing, particularly for high resolution, wide band spectrum analysis were developed. These developments are intended to provide instrumentation for NASA's Search for Extraterrestrial Intelligence (SETI) program. The real time signal processing is both formal and experimental. The efficient organization and optimal scheduling of signal processing algorithms were investigated. The work is complemented by efforts in processor architecture design and implementation. A high resolution, multichannel spectrometer that incorporates special purpose microcoded signal processors is being tested. A general purpose signal processor for the data from the multichannel spectrometer was designed to function as the processing element in a highly concurrent machine. The processor performance required for the spectrometer is in the range of 1000 to 10,000 million instructions per second (MIPS). Multiple node processor configurations, where each node performs at 100 MIPS, are sought. The nodes are microprogrammable and are interconnected through a network with high bandwidth for neighboring nodes, and medium bandwidth for nodes at larger distance. The implementation of both the current mutlichannel spectrometer and the signal processor as Very Large Scale Integration CMOS chip sets was commenced.

Review on Photonic Generation of Chirp Arbitrary Microwave Waveforms for Remote Sensing Application

NASA Astrophysics Data System (ADS)

Raghuwanshi, Sanjeev Kumar; Srivastav, Akash; Athokpam, Bidhanshel Singh

2017-12-01

A novel technique to generate an arbitrary chirped waveform by harnessing features of lithium niobate (LiNb O_3) Mach-Zehnder modulator is proposed and demonstrated. The most important application of chirped microwave waveform is that, it improves the range resolution of radar. Microwave photonics system provides high bandwidth capabilities of fiber-optic systems and also contains the ability to provide interconnect transmission properties, which are virtually independent of length. The low-loss wide bandwidth capability of optoelectronic systems makes them attractive for the transmission and processing of microwave signals, while the development of high-capacity optical communication systems has required the use of microwave techniques in optical transmitters and receivers. These two strands have led to the development of the research area of microwave photonics. So, it should be consider that microwave photonics as the field that studies the interaction between microwave and optical waves for applications such as communications, radars, sensors and instrumentations. In this paper, we have thoroughly reviewed the arbitrary chirped microwave generation techniques by using photonics technology.

Research on SOI-based micro-resonator devices

NASA Astrophysics Data System (ADS)

Xiao, Xi; Xu, Haihua; Hu, Yingtao; Zhou, Liang; Xiong, Kang; Li, Zhiyong; Li, Yuntao; Fan, Zhongchao; Han, Weihua; Yu, Yude; Yu, Jinzhong

2010-10-01

SOI (silicon-on-insulator)-based micro-resonator is the key building block of silicon photonics, which is considered as a promising solution to alleviate the bandwidth bottleneck of on-chip interconnects. Silicon-based sub-micron waveguide, microring and microdisk devices are investigated in Institute of Semiconductors, Chinese Academy of Sciences. The main progress in recent years is presented in this talk, such as high Q factor single mode microdisk filters, compact thirdorder microring filters with the through/drop port extinctions to be ~ 30/40 dB, fast microring electro-optical switches with the switch time of < 400 ps and crosstalk < -23 dB, and > 10 Gbit/s high speed microring modulators.

A Full Mesh ATCA-based General Purpose Data Processing Board (Pulsar II)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ajuha, S.

The Pulsar II is a custom ATCA full mesh enabled FPGA-based processor board which has been designed with the goal of creating a scalable architecture abundant in flexible, non-blocking, high bandwidth interconnections. The design has been motivated by silicon-based tracking trigger needs for LHC experiments. In this technical memo we describe the Pulsar II hardware and its performance, such as the performance test results with full mesh backplanes from different vendors, how the backplane is used for the development of low-latency time-multiplexed data transfer schemes and how the inter-shelf and intra-shelf synchronization works.

VLSI Implementation of a 2.8 Gevent/s Packet-Based AER Interface with Routing and Event Sorting Functionality

PubMed Central

Scholze, Stefan; Schiefer, Stefan; Partzsch, Johannes; Hartmann, Stephan; Mayr, Christian Georg; Höppner, Sebastian; Eisenreich, Holger; Henker, Stephan; Vogginger, Bernhard; Schüffny, Rene

2011-01-01

State-of-the-art large-scale neuromorphic systems require sophisticated spike event communication between units of the neural network. We present a high-speed communication infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic communication ICs in an field programmable gate arrays (FPGA)-maintained environment. The ICs implement configurable axonal delays, as required for certain types of dynamic processing or for emulating spike-based learning among distant cortical areas. Measurements are presented which show the efficacy of these delays in influencing behavior of neuromorphic benchmarks. The specialized, dedicated address-event-representation communication in most current systems requires separate, low-bandwidth configuration channels. In contrast, the configuration of the waferscale neuromorphic system is also handled by the digital packet-based pulse channel, which transmits configuration data at the full bandwidth otherwise used for pulse transmission. The overall so-called pulse communication subgroup (ICs and FPGA) delivers a factor 25–50 more event transmission rate than other current neuromorphic communication infrastructures. PMID:22016720

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pasquinelli, Ralph J.; /Fermilab; Jansson, Andreas

The LHC Schottky system consists for four independent 4.8 GHz triple down conversion receivers with associated data acquisition systems. Each system is capable of measuring tune, chromaticity, momentum spread in either horizontal or vertical planes; two systems per beam. The hardware commissioning has taken place from spring through fall of 2010. With nominal bunch beam currents of 10{sup 11} protons, the first incoherent Schottky signals were detected and analyzed. This paper will report on these initial commissioning results. A companion paper will report on the data analysis curve fitting and remote control user interface of the system. The Schottky systemmore » for the LHC was proposed in 2004 under the auspices of the LARP collaboration. Similar systems were commissioned in 2003 in the Fermilab Tevatron and Recycler accelerators as a means of measuring tunes noninvasively. The Schottky detector is based on the stochastic cooling pickups that were developed for the Fermilab Antiproton Source Debuncher cooling upgrade completed in 2002. These slotted line waveguide pickups have the advantage of large aperture coupled with high beam coupling characteristics. For stochastic cooling, wide bandwidths are integral to cooling performance. The bandwidth of slotted waveguide pickups can be tailored by choosing the length of the pickup and slot spacing. The Debuncher project covered the 4-8 GHz band with eight bands of pickups, each with approximately 500 MHz of bandwidth. For use as a Schottky detector, bandwidths of 100-200 MHz are required for gating, resulting in higher transfer impedance than those used for stochastic cooling. Details of hardware functionality are reported previously.« less

Genetic expression programming-based DBA for enhancing peer-assisted music-on-demand service in EPON

NASA Astrophysics Data System (ADS)

Liem, Andrew Tanny; Hwang, I.-Shyan; Nikoukar, AliAkbar; Lee, Jhong-Yue

2015-03-01

Today, the popularity of peer-assisted music-on-demand (MoD) has increased significantly worldwide. This service allows users to access large music library tracks, listen to music, and share their playlist with other users. Unlike the conventional voice traffic, such an application maintains music quality that ranges from 160 kbps to 320 kbps, which most likely consumes more bandwidth than other traffics. In the access network, Ethernet passive optical network (EPON) is one of the best candidates for delivering such a service because of being cost-effective and with high bandwidth. To maintain music quality, a stutter needs to be prevented because of either network effects or when the due user was not receiving enough resources to play in a timely manner. Therefore, in this paper, we propose two genetic expression programming (GEP)-based dynamic bandwidth allocations (DBAs). The first DBA is a generic DBA that aims to find an optimum formula for voice, video, and data services. The second DBA aims to find optimum formulas so that Optical Line Terminal (OLT) can satisfy not only the voice and Peer-to-Peer (P2P) MoD traffics but also reduce the stutter. Optical Network Unit (ONU) traits such as REPORT and GATE messages, cycle time, and mean packet delay are set to be predictor variables. Simulation results show that our proposed DBAs can satisfy the voice and P2P MoD services packet delay and monitor other overall system performances such as expedited forwarding (EF) jitter, packet loss, bandwidth waste, and system throughputs.

Frequency-encoded photonic qubits for scalable quantum information processing

DOE PAGES

Lukens, Joseph M.; Lougovski, Pavel

2016-12-21

Among the objectives for large-scale quantum computation is the quantum interconnect: a device that uses photons to interface qubits that otherwise could not interact. However, the current approaches require photons indistinguishable in frequency—a major challenge for systems experiencing different local environments or of different physical compositions altogether. Here, we develop an entirely new platform that actually exploits such frequency mismatch for processing quantum information. Labeled “spectral linear optical quantum computation” (spectral LOQC), our protocol offers favorable linear scaling of optical resources and enjoys an unprecedented degree of parallelism, as an arbitrary Ν-qubit quantum gate may be performed in parallel onmore » multiple Ν-qubit sets in the same linear optical device. Here, not only does spectral LOQC offer new potential for optical interconnects, but it also brings the ubiquitous technology of high-speed fiber optics to bear on photonic quantum information, making wavelength-configurable and robust optical quantum systems within reach.« less

Frequency-encoded photonic qubits for scalable quantum information processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lukens, Joseph M.; Lougovski, Pavel

Among the objectives for large-scale quantum computation is the quantum interconnect: a device that uses photons to interface qubits that otherwise could not interact. However, the current approaches require photons indistinguishable in frequency—a major challenge for systems experiencing different local environments or of different physical compositions altogether. Here, we develop an entirely new platform that actually exploits such frequency mismatch for processing quantum information. Labeled “spectral linear optical quantum computation” (spectral LOQC), our protocol offers favorable linear scaling of optical resources and enjoys an unprecedented degree of parallelism, as an arbitrary Ν-qubit quantum gate may be performed in parallel onmore » multiple Ν-qubit sets in the same linear optical device. Here, not only does spectral LOQC offer new potential for optical interconnects, but it also brings the ubiquitous technology of high-speed fiber optics to bear on photonic quantum information, making wavelength-configurable and robust optical quantum systems within reach.« less

Modified Phasemeter for a Heterodyne Laser Interferometer

NASA Technical Reports Server (NTRS)

Loya, Frank M.

2010-01-01

Modifications have been made in the design of instruments of the type described in "Digital Averaging Phasemeter for Heterodyne Interferometry". A phasemeter of this type measures the difference between the phases of the unknown and reference heterodyne signals in a heterodyne laser interferometer. The phasemeter design lacked immunity to drift of the heterodyne frequency, was bandwidth-limited by computer bus architectures then in use, and was resolution-limited by the nature of field-programmable gate arrays (FPGAs) then available. The modifications have overcome these limitations and have afforded additional improvements in accuracy, speed, and modularity. The modifications are summarized.

Composite pulses robust against charge noise and magnetic field noise for universal control of a singlet-triplet qubit

NASA Astrophysics Data System (ADS)

Wang, Xin; Barnes, Edwin; Kestner, Jason P.; Bishop, Lev S.; Das Sarma, Sankar

2013-03-01

We generalize our SUPCODE pulse sequences for singlet-triplet qubits to correct errors from imperfect control. This yields gates that are simultaneously corrected for both charge noise and magnetic field gradient fluctuations, addressing the two dominant T2* processes. By using this more efficient version of SUPCODE, we are able to introduce this capability while also substantially reducing the overall pulse time compared to the previous sequence. We show that our sequence remains realistic under experimental constraints such as finite bandwidth. This work is supported by LPS-NSA-CMTC, IARPA-MQCO and CNAM.

Field-programmable gate array-controlled sweep velocity-locked laser pulse generator

NASA Astrophysics Data System (ADS)

Chen, Zhen; Hefferman, Gerald; Wei, Tao

2017-05-01

A field-programmable gate array (FPGA)-controlled sweep velocity-locked laser pulse generator (SV-LLPG) design based on an all-digital phase-locked loop (ADPLL) is proposed. A distributed feedback laser with modulated injection current was used as a swept-frequency laser source. An open-loop predistortion modulation waveform was calibrated using a feedback iteration method to initially improve frequency sweep linearity. An ADPLL control system was then implemented using an FPGA to lock the output of a Mach-Zehnder interferometer that was directly proportional to laser sweep velocity to an on-board system clock. Using this system, linearly chirped laser pulses with a sweep bandwidth of 111.16 GHz were demonstrated. Further testing evaluating the sensing utility of the system was conducted. In this test, the SV-LLPG served as the swept laser source of an optical frequency-domain reflectometry system used to interrogate a subterahertz range fiber structure (sub-THz-FS) array. A static strain test was then conducted and linear sensor results were observed.

Simple online recognition of optical data strings based on conservative optical logic

NASA Astrophysics Data System (ADS)

Caulfield, H. John; Shamir, Joseph; Zavalin, Andrey I.; Silberman, Enrique; Qian, Lei; Vikram, Chandra S.

2006-06-01

Optical packet switching relies on the ability of a system to recognize header information on an optical signal. Unless the headers are very short with large Hamming distances, optical correlation fails and optical logic becomes attractive because it can handle long headers with Hamming distances as low as 1. Unfortunately, the only optical logic gates fast enough to keep up with current communication speeds involve semiconductor optical amplifiers and do not lend themselves to the incorporation of large numbers of elements for header recognition and would consume a lot of power as well. The ideal system would operate at any bandwidth with no power consumption. We describe how to design and build such a system by using passive optical logic. This too leads to practical problems that we discuss. We show theoretically various ways to use optical interferometric logic for reliable recognition of long data streams such as headers in optical communication. In addition, we demonstrate one particularly simple experimental approach using interferometric coinc gates.

Asymmetric underlap spacer layer enabled nanoscale double gate MOSFETs for design of ultra-wideband cascode amplifiers

NASA Astrophysics Data System (ADS)

Roy, Debapriya; Biswas, Abhijit

2017-10-01

Using extensive numerical analysis we investigate effects of asymmetric sidewall spacers on various device parameters of 20-nm double gate MOSFETs associated with analog/RF applications. Our studies show that the device with underlap drain-side spacer length LED of 10 nm and source-side spacer length LES of 5 nm shows improvement in terms of the peak value of transconductance efficiency, voltage gain Av, unity-gain cut-off frequency fT and maximum frequency of oscillations fMAX by 8.6%, 51.7%, 5% and 10.3%, respectively compared to the symmetric 5 nm underlap spacer device with HfO2 spacer of dielectric constant k = 22. Additionally, a higher spacer dielectric constant increases the peak Av while decreasing both peak fT and fMAX. The detailed physical insight is exploited to design a cascode amplifier which yields an ultra-wide gain bandwidth of 2.48 THz at LED = 10 nm with a SiO2 spacer.

Fast contactless vibrating structure characterization using real time field programmable gate array-based digital signal processing: demonstrations with a passive wireless acoustic delay line probe and vision.

PubMed

Goavec-Mérou, G; Chrétien, N; Friedt, J-M; Sandoz, P; Martin, G; Lenczner, M; Ballandras, S

2014-01-01

Vibrating mechanical structure characterization is demonstrated using contactless techniques best suited for mobile and rotating equipments. Fast measurement rates are achieved using Field Programmable Gate Array (FPGA) devices as real-time digital signal processors. Two kinds of algorithms are implemented on FPGA and experimentally validated in the case of the vibrating tuning fork. A first application concerns in-plane displacement detection by vision with sampling rates above 10 kHz, thus reaching frequency ranges above the audio range. A second demonstration concerns pulsed-RADAR cooperative target phase detection and is applied to radiofrequency acoustic transducers used as passive wireless strain gauges. In this case, the 250 ksamples/s refresh rate achieved is only limited by the acoustic sensor design but not by the detection bandwidth. These realizations illustrate the efficiency, interest, and potentialities of FPGA-based real-time digital signal processing for the contactless interrogation of passive embedded probes with high refresh rates.

Surface plasmon polaritons in a topological insulator embedded in an optical cavity

NASA Astrophysics Data System (ADS)

Li, L. L.; Xu, W.

2014-03-01

Very recently, the surface plasmons in a topological insulator (TI) have been experimentally observed by exciting these collective modes with polarized light [P. Di Pietro, M. Ortolani, O. Limaj, A. Di Gaspare, V. Giliberti, F. Giorgianni, M. Brahlek, N. Bansal, N. Koirala, S. Oh, P. Calvani, and S. Lupi, Nat. Nanotechnol. 8, 556 (2013)]. Motivated by this experimental work, here we present a theoretical study on the surface plasmon polaritons (SPPs) induced by plasmon-photon interactions in a TI thin film embedded in an optical cavity. It is found that the frequencies of SPP modes are within the terahertz (THz) bandwidth and can be tuned effectively by adjusting the surface electron density and/or the optical cavity length. Since the surface electron density can be well controlled by the gate-voltage applied perpendicular to the TI surface, our theoretical results indicate that gated TI thin films may have potential applications in the electrically tunable THz plasmonic devices.

Generation of high-intensity sub-30 as pulses by inhomogeneous polarization gating technology in bowtie-shaped nanostructure

NASA Astrophysics Data System (ADS)

Feng, Liqiang; Feng, A. Yuanzi

2018-04-01

The generation of high-order harmonics and single attosecond pulses (SAPs) from He atom driven by the inhomogeneous polarization gating technology in a bowtie-shaped nanostructure is theoretically investigated. The results show that by the proper addition of bowtie-shaped nanostructure along the driven laser polarization direction, the harmonic emission becomes sensitive to the position of the laser field, and the harmonics emitted at the maximum orders that generate SAPs occur only at one side of the region inside the nanostructure. As a result, not only the harmonic cutoff can be extended, but also the modulations of the harmonics can be decreased, showing a carrier envelope phase independent harmonic cutoff with a bandwidth of 310 eV. Further, with the proper introduction of an ultraviolet pulse, the harmonic yield can be enhanced by 2 orders of magnitude. Finally, by the Fourier transformation of the selected harmonics, some SAPs with a full width at half maximum of sub-30 as can be obtained.

A three-sided rearrangeable switching network for a binary fat tree

NASA Astrophysics Data System (ADS)

Yen, Mao-Hsu; Yu, Chu; Shin, Haw-Yun; Chen, Sao-Jie

2011-06-01

A binary fat tree needs an internal node to interconnect the left-children, right-children and parent terminals to each other. In this article, we first propose a three-stage, 3-sided rearrangeable switching network for the implementation of a binary fat tree. The main component of this 3-sided switching network (3SSN) consists of a polygonal switch block (PSB) interconnected by crossbars. With the same size and the same number of switches as our 3SSN, a three-stage, 3-sided clique-based switching network is shown to be not rearrangeable. Also, the effects of the rearrangeable structure and the number of terminals on the network switch-efficiency are explored and a proper set of parameters has been determined to minimise the number of switches. We derive that a rearrangeable 3-sided switching network with switches proportional to N 3/2 is most suitable to interconnect N terminals. Moreover, we propose a new Polygonal Field Programmable Gate Array (PFPGA) that consists of logic blocks interconnected by our 3SSN, such that the logic blocks in this PFPGA can be grouped into clusters to implement different logic functions. Since the programmable switches usually have high resistance and capacitance and occupy a large area, we have to consider the effect of the 3SSN structure and the granularity of its cluster logic blocks on the switch efficiency of PFPGA. Experiments on benchmark circuits show that the switch and speed performances are significantly improved. Based on the experimental results, we can determine the parameters of PFPGA for the VLSI implementation.

Multi-Modulator for Bandwidth-Efficient Communication

NASA Technical Reports Server (NTRS)

Gray, Andrew; Lee, Dennis; Lay, Norman; Cheetham, Craig; Fong, Wai; Yeh, Pen-Shu; King, Robin; Ghuman, Parminder; Hoy, Scott; Fisher, Dave

2009-01-01

A modulator circuit board has recently been developed to be used in conjunction with a vector modulator to generate any of a large number of modulations for bandwidth-efficient radio transmission of digital data signals at rates than can exceed 100 Mb/s. The modulations include quadrature phaseshift keying (QPSK), offset quadrature phase-shift keying (OQPSK), Gaussian minimum-shift keying (GMSK), and octonary phase-shift keying (8PSK) with square-root raised-cosine pulse shaping. The figure is a greatly simplified block diagram showing the relationship between the modulator board and the rest of the transmitter. The role of the modulator board is to encode the incoming data stream and to shape the resulting pulses, which are fed as inputs to the vector modulator. The combination of encoding and pulse shaping in a given application is chosen to maximize the bandwidth efficiency. The modulator board includes gallium arsenide serial-to-parallel converters at its input end. A complementary metal oxide/semiconductor (CMOS) field-programmable gate array (FPGA) performs the coding and modulation computations and utilizes parallel processing in doing so. The results of the parallel computation are combined and converted to pulse waveforms by use of gallium arsenide parallel-to-serial converters integrated with digital-to-analog converters. Without changing the hardware, one can configure the modulator to produce any of the designed combinations of coding and modulation by loading the appropriate bit configuration file into the FPGA.

2.75 THz tuning with a triple-DFB laser system at 1550 nm and InGaAs photomixers

NASA Astrophysics Data System (ADS)

Deninger, Anselm J.; Roggenbuck, A.; Schindler, S.; Preu, S.

2015-03-01

To date, exploiting the full bandwidth of state-of-the-art InGaAs photomixers for generation and detection of continuous-wave (CW) THz radiation (typ. ~50 GHz to ~3 THz) required complex and costly external-cavity diode lasers with motorized resonator control. Distributed feedback (DFB) lasers, by contrast, are compact and inexpensive, but the tuning range per diode is limited to ~600 GHz at 1.5 μm. In this paper, we show that a combination of three DFB diodes covers the complete frequency range from 0 - 2750 GHz without any gaps. In combination with InGaAs-based photomixers for terahertz generation and detection, the system achieves a dynamic range of > 100 dB at 56 GHz, 64 dB at 1000 GHz, and 26 dB at 2500 GHz. A field-programmable gate array (FPGA)-based lock-in amplifier permits a flexible adjustment of the integration time from 0.5 ms to 600 ms. Employing an optimized "fast scan" mode, a spectrum of ~1200 GHz - the bandwidth of each subset of two lasers - and 40 MHz steps is acquired in less than one minute, still maintaining a reasonable dynamic range. To the best of our knowledge, the bandwidth of 2.75 THz presents a new record for DFB-based CW-terahertz systems.

Novel Low Loss Wide-Band Multi-Port Integrated Circuit Technology for RF/Microwave Applications

NASA Technical Reports Server (NTRS)

Simons, Rainee N.; Goverdhanam, Kavita; Katehi, Linda P. B.; Burke, Thomas P. (Technical Monitor)

2001-01-01

In this paper, novel low loss, wide-band coplanar stripline technology for radio frequency (RF)/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth, and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semi-conductor devices and microelectromechanical systems (MEMS).

Processing and characterization of device solder interconnection and module attachment for power electronics modules

NASA Astrophysics Data System (ADS)

Haque, Shatil

This research is focused on the processing of an innovative three-dimensional packaging architecture for power electronics building blocks with soldered device interconnections and subsequent characterization of the module's critical interfaces. A low-cost approach termed metal posts interconnected parallel plate structure (MPIPPS) was developed for packaging high-performance modules of power electronics building blocks (PEBB). The new concept implemented direct bonding of copper posts, not wire bonding of fine aluminum wires, to interconnect power devices as well as joining the different circuit planes together. We have demonstrated the feasibility of this packaging approach by constructing PEBB modules (consisting of Insulated Gate Bipolar Transistors (IGBTs), diodes, and a few gate driver elements and passive components). In the 1st phase of module fabrication with IGBTs with Si3N 4 passivation, we had successfully fabricated packaged devices and modules using the MPIPPS technique. These modules were tested electrically and thermally, and they operated at pulse-switch and high power stages up to 6kW. However, in the 2nd phase of module fabrication with polyimide passivated devices, we experienced significant yield problems due to metallization difficulties of these devices. The under-bump metallurgy scheme for the development of a solderable interface involved sputtering of Ti-Ni-Cu and Cr-Cu, and an electroless deposition of Zn-Ni-Au metallization. The metallization process produced excellent yield in the case of Si3N4 passivated devices. However, under the same metallization schemes, devices with a polyimide passivation exhibited inconsistent electrical contact resistance. We found that organic contaminants such as hydrocarbons remain in the form of thin monolayers on the surface, even in the case of as-received devices from the manufacturer. Moreover, in the case of polyimide passivated devices, plasma cleaning introduced a few carbon constituents on the surface, which was not observed in the case of Si3N4 passivated devices. X-Ray Photoelectron Spectroscopy (XPS) Spectra showed evidence of possible carbon contaminants, such as carbide (˜282.9eV) and graphite (˜284.3eV) on the surface at binding energies below the binding energy of the hydrocarbon peak (C 1s at 285eV). Whereas above the hydrocarbon peak energy level, carbon-nitrogen compounds, single bond carbon compounds (˜285.9eV) and double bond carbon compounds (˜288.5eV) were evident. The majority of the carbon composition on the pad surface was associated with hydrocarbons, which were hydrophobic in nature, thus making the device contact pad less wettable. (Abstract shortened by UMI.)

Design and development of cell queuing, processing, and scheduling modules for the iPOINT input-buffered ATM testbed

NASA Astrophysics Data System (ADS)

Duan, Haoran

1997-12-01

This dissertation presents the concepts, principles, performance, and implementation of input queuing and cell-scheduling modules for the Illinois Pulsar-based Optical INTerconnect (iPOINT) input-buffered Asynchronous Transfer Mode (ATM) testbed. Input queuing (IQ) ATM switches are well suited to meet the requirements of current and future ultra-broadband ATM networks. The IQ structure imposes minimum memory bandwidth requirements for cell buffering, tolerates bursty traffic, and utilizes memory efficiently for multicast traffic. The lack of efficient cell queuing and scheduling solutions has been a major barrier to build high-performance, scalable IQ-based ATM switches. This dissertation proposes a new Three-Dimensional Queue (3DQ) and a novel Matrix Unit Cell Scheduler (MUCS) to remove this barrier. 3DQ uses a linked-list architecture based on Synchronous Random Access Memory (SRAM) to combine the individual advantages of per-virtual-circuit (per-VC) queuing, priority queuing, and N-destination queuing. It avoids Head of Line (HOL) blocking and provides per-VC Quality of Service (QoS) enforcement mechanisms. Computer simulation results verify the QoS capabilities of 3DQ. For multicast traffic, 3DQ provides efficient usage of cell buffering memory by storing multicast cells only once. Further, the multicast mechanism of 3DQ prevents a congested destination port from blocking other less- loaded ports. The 3DQ principle has been prototyped in the Illinois Input Queue (iiQueue) module. Using Field Programmable Gate Array (FPGA) devices, SRAM modules, and integrated on a Printed Circuit Board (PCB), iiQueue can process incoming traffic at 800 Mb/s. Using faster circuit technology, the same design is expected to operate at the OC-48 rate (2.5 Gb/s). MUCS resolves the output contention by evaluating the weight index of each candidate and selecting the heaviest. It achieves near-optimal scheduling and has a very short response time. The algorithm originates from a heuristic strategy that leads to 'socially optimal' solutions, yielding a maximum number of contention-free cells being scheduled. A novel mixed digital-analog circuit has been designed to implement the MUCS core functionality. The MUCS circuit maps the cell scheduling computation to the capacitor charging and discharging procedures that are conducted fully in parallel. The design has a uniform circuit structure, low interconnect counts, and low chip I/O counts. Using 2 μm CMOS technology, the design operates on a 100 MHz clock and finds a near-optimal solution within a linear processing time. The circuit has been verified at the transistor level by HSPICE simulation. During this research, a five-port IQ-based optoelectronic iPOINT ATM switch has been developed and demonstrated. It has been fully functional with an aggregate throughput of 800 Mb/s. The second-generation IQ-based switch is currently under development. Equipped with iiQueue modules and MUCS module, the new switch system will deliver a multi-gigabit aggregate throughput, eliminate HOL blocking, provide per-VC QoS, and achieve near-100% link bandwidth utilization. Complete documentation of input modules and trunk module for the existing testbed, and complete documentation of 3DQ, iiQueue, and MUCS for the second-generation testbed are given in this dissertation.

Aerosol-jet-printed, 1 volt H-bridge drive circuit on plastic with integrated electrochromic pixel.

PubMed

Ha, Mingjing; Zhang, Wei; Braga, Daniele; Renn, Michael J; Kim, Chris H; Frisbie, C Daniel

2013-12-26

In this report, we demonstrate a printed, flexible, and low-voltage circuit that successfully drives a polymer electrochromic (EC) pixel as large as 4 mm(2) that is printed on the same substrate. All of the key components of the drive circuitry, namely, resistors, capacitors, and transistors, were aerosol-jet-printed onto a plastic foil; metallic electrodes and interconnects were the only components prepatterned on the plastic by conventional photolithography. The large milliampere drive currents necessary to switch a 4 mm(2) EC pixel were controlled by printed electrolyte-gated transistors (EGTs) that incorporate printable ion gels for the gate insulator layers and poly(3-hexylthiophene) for the semiconductor channels. Upon application of a 1 V input pulse, the circuit switches the printed EC pixel ON (red) and OFF (blue) two times in approximately 4 s. The performance of the circuit and the behavior of the individual resistors, capacitors, EGTs, and the EC pixel are analyzed as functions of the printing parameters and operating conditions.

Improved resolution of single channel dwell times reveals mechanisms of binding, priming, and gating in muscle AChR

PubMed Central

Mukhtasimova, Nuriya; daCosta, Corrie J.B.

2016-01-01

The acetylcholine receptor (AChR) from vertebrate skeletal muscle initiates voluntary movement, and its kinetics of activation are crucial for maintaining the safety margin for neuromuscular transmission. Furthermore, the kinetic mechanism of the muscle AChR serves as an archetype for understanding activation mechanisms of related receptors from the Cys-loop superfamily. Here we record currents through single muscle AChR channels with improved temporal resolution approaching half an order of magnitude over our previous best. A range of concentrations of full and partial agonists are used to elicit currents from human wild-type and gain-of-function mutant AChRs. For each agonist–receptor combination, rate constants are estimated from maximum likelihood analysis using a kinetic scheme comprised of agonist binding, priming, and channel gating steps. The kinetic scheme and rate constants are tested by stochastic simulation, followed by incorporation of the experimental step response, sampling rate, background noise, and filter bandwidth. Analyses of the simulated data confirm all rate constants except those for channel gating, which are overestimated because of the established effect of noise on the briefest dwell times. Estimates of the gating rate constants were obtained through iterative simulation followed by kinetic fitting. The results reveal that the agonist association rate constants are independent of agonist occupancy but depend on receptor state, whereas those for agonist dissociation depend on occupancy but not on state. The priming rate and equilibrium constants increase with successive agonist occupancy, and for a full agonist, the forward rate constant increases more than the equilibrium constant; for a partial agonist, the forward rate and equilibrium constants increase equally. The gating rate and equilibrium constants also increase with successive agonist occupancy, but unlike priming, the equilibrium constants increase more than the forward rate constants. As observed for a full and a partial agonist, the gain-of-function mutation affects the relationship between rate and equilibrium constants for priming but not for channel gating. Thus, resolving brief single channel currents distinguishes priming from gating steps and reveals how the corresponding rate and equilibrium constants depend on agonist occupancy. PMID:27353445

Cross-layer restoration with software defined networking based on IP over optical transport networks

NASA Astrophysics Data System (ADS)

Yang, Hui; Cheng, Lei; Deng, Junni; Zhao, Yongli; Zhang, Jie; Lee, Young

2015-10-01

The IP over optical transport network is a very promising networking architecture applied to the interconnection of geographically distributed data centers due to the performance guarantee of low delay, huge bandwidth and high reliability at a low cost. It can enable efficient resource utilization and support heterogeneous bandwidth demands in highly-available, cost-effective and energy-effective manner. In case of cross-layer link failure, to ensure a high-level quality of service (QoS) for user request after the failure becomes a research focus. In this paper, we propose a novel cross-layer restoration scheme for data center services with software defined networking based on IP over optical network. The cross-layer restoration scheme can enable joint optimization of IP network and optical network resources, and enhance the data center service restoration responsiveness to the dynamic end-to-end service demands. We quantitatively evaluate the feasibility and performances through the simulation under heavy traffic load scenario in terms of path blocking probability and path restoration latency. Numeric results show that the cross-layer restoration scheme improves the recovery success rate and minimizes the overall recovery time.

Adaptive packet switch with an optical core (demonstrator)

NASA Astrophysics Data System (ADS)

Abdo, Ahmad; Bishtein, Vadim; Clark, Stewart A.; Dicorato, Pino; Lu, David T.; Paredes, Sofia A.; Taebi, Sareh; Hall, Trevor J.

2004-11-01

A three-stage opto-electronic packet switch architecture is described consisting of a reconfigurable optical centre stage surrounded by two electronic buffering stages partitioned into sectors to ease memory contention. A Flexible Bandwidth Provision (FBP) algorithm, implemented on a soft-core processor, is used to change the configuration of the input sectors and optical centre stage to set up internal paths that will provide variable bandwidth to serve the traffic. The switch is modeled by a bipartite graph built from a service matrix, which is a function of the arriving traffic. The bipartite graph is decomposed by solving an edge-colouring problem and the resulting permutations are used to configure the switch. Simulation results show that this architecture exhibits a dramatic reduction of complexity and increased potential for scalability, at the price of only a modest spatial speed-up k, 1

Customer premise service study for 30/20 GHz satellite system

NASA Technical Reports Server (NTRS)

Milton, R. T.; Ross, D. P.; Harcar, A. R.; Freedenberg, P.; Schoen, D.

1983-01-01

Satellite systems in which the space segment operates in the 30/20 GHz frequency band are defined and compared as to their potential for providing various types of communications services to customer premises and the economic and technical feasibility of doing so. Technical tasks performed include: market postulation, definition of the ground segment, definition of the space segment, definition of the integrated satellite system, service costs for satellite systems, sensitivity analysis, and critical technology. Based on an analysis of market data, a sufficiently large market for services is projected so as to make the system economically viable. A large market, and hence a high capacity satellite system, is found to be necessary to minimize service costs, i.e., economy of scale is found to hold. The wide bandwidth expected to be available in the 30/20 GHz band, along with frequency reuse which further increases the effective system bandwidth, makes possible the high capacity system. Extensive ground networking is required in most systems to both connect users into the system and to interconnect Earth stations to provide spatial diversity. Earth station spatial diversity is found to be a cost effective means of compensating the large fading encountered in the 30/20 GHz operating band.

The Need for Optical Means as an Alternative for Electronic Computing

NASA Technical Reports Server (NTRS)

Adbeldayem, Hossin; Frazier, Donald; Witherow, William; Paley, Steve; Penn, Benjamin; Bank, Curtis; Whitaker, Ann F. (Technical Monitor)

2001-01-01

An increasing demand for faster computers is rapidly growing to encounter the fast growing rate of Internet, space communication, and robotic industry. Unfortunately, the Very Large Scale Integration technology is approaching its fundamental limits beyond which the device will be unreliable. Optical interconnections and optical integrated circuits are strongly believed to provide the way out of the extreme limitations imposed on the growth of speed and complexity of nowadays computations by conventional electronics. This paper demonstrates two ultra-fast, all-optical logic gates and a high-density storage medium, which are essential components in building the future optical computer.

Digital Logic and Reconfigurable Interconnects Using Aluminum Gallium Arsenide Electro-Optic Fredkin Gates

DTIC Science & Technology

1994-06-01

length and coupling coefficient for the zero-gap directional coupler are obtained by using Eq. 3.2.39. Bums and Milton Effective Index Method In a 1975...nj) with •i wavegulde thicness b. Effective index N1 is then used to find the effective >Vt.,:, ;- 105 c a ¶ 2 n. n_ z n2 - : n4 Three-Dimensional...constant for the TM, modes is determined in a manner similar to the one used for the TEp modes. First, effective index N1 of 2-D Waveguide I is found by

Simple method for assembly of CRISPR synergistic activation mediator gRNA expression array.

PubMed

Vad-Nielsen, Johan; Nielsen, Anders Lade; Luo, Yonglun

2018-05-20

When studying complex interconnected regulatory networks, effective methods for simultaneously manipulating multiple genes expression are paramount. Previously, we have developed a simple method for generation of an all-in-one CRISPR gRNA expression array. We here present a Golden Gate Assembly-based system of synergistic activation mediator (SAM) compatible CRISPR/dCas9 gRNA expression array for the simultaneous activation of multiple genes. Using this system, we demonstrated the simultaneous activation of the transcription factors, TWIST, SNAIL, SLUG, and ZEB1 a human breast cancer cell line. Copyright © 2018 Elsevier B.V. All rights reserved.

A Low-cost 4 Bit, 10 Giga-samples-per-second Analog-to-digital Converter Printed Circuit Board Assembly for FPGA-based Backends

NASA Astrophysics Data System (ADS)

Jiang, Homin; Yu, Chen-Yu; Kubo, Derek; Chen, Ming-Tang; Guzzino, Kim

2016-11-01

In this study, a 4 bit, 10 giga-samples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was designed, manufactured, and characterized for digitizing radio telescopes. For this purpose, an Adsantec ANST7120A-KMA flash ADC chip was used. Together with the field-programmable gate array platform, developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the PCBA enables data acquisition with a wide bandwidth and simplifies the intermediate frequency section. In the current version, the PCBA and the chip exhibit an analog bandwidth of 10 GHz (3 dB loss) and 20 GHz, respectively, which facilitates second, third, and even fourth Nyquist sampling. The following average performance parameters were obtained from the first and second Nyquist zones of the three boards: a spurious-free dynamic range of 31.35/30.45 dB, a signal-to-noise and distortion ratio of 22.95/21.83 dB, and an effective number of bits of 3.65/3.43, respectively.

Hybrid Silicon Photonic Integration using Quantum Well Intermixing

NASA Astrophysics Data System (ADS)

Jain, Siddharth R.

With the push for faster data transfer across all domains of telecommunication, optical interconnects are transitioning into shorter range applications such as in data centers and personal computing. Silicon photonics, with its economic advantages of leveraging well-established silicon manufacturing facilities, is considered the most promising approach to further scale down the cost and size of optical interconnects for chip-to-chip communication. Intrinsic properties of silicon however limit its ability to generate and modulate light, both of which are key to realizing on-chip optical data transfer. The hybrid silicon approach directly addresses this problem by using molecularly bonded III-V epitaxial layers on silicon for optical gain and absorption. This technology includes direct transfer of III-V wafer to a pre-patterned silicon-on-insulator wafer. Several discrete devices for light generation, modulation, amplification and detection have already been demonstrated on this platform. As in the case of electronics, multiple photonic elements can be integrated on a single chip to improve performance and functionality. However, scalable photonic integration requires the ability to control the bandgap for individual devices along with design changes to simplify fabrication. In the research presented here, quantum well intermixing is used as a technique to define multiple bandgaps for integration on the hybrid silicon platform. Implantation enhanced disordering is used to generate four bandgaps spread over 120+ nm. By combining these selectively intermixed III-V layers with pre-defined gratings and waveguides on silicon, we fabricate distributed feedback, distributed Bragg reflector, Fabry-Perot and mode-locked lasers along with photodetectors, electro-absorption modulators and other test structures, all on a single chip. We demonstrate a broadband laser source with continuous-wave operational lasers over a 200 nm bandwidth. Some of these lasers are integrated with modulators with a 3-dB bandwidth above 25 GHz, thus demonstrating coarse wavelength division multiplexing transmitter on silicon.

Data Movement Dominates: Advanced Memory Technology to Address the Real Exascale Power Problem

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bergman, Keren

Energy is the fundamental barrier to Exascale supercomputing and is dominated by the cost of moving data from one point to another, not computation. Similarly, performance is dominated by data movement, not computation. The solution to this problem requires three critical technologies: 3D integration, optical chip-to-chip communication, and a new communication model. The central goal of the Sandia led "Data Movement Dominates" project aimed to develop memory systems and new architectures based on these technologies that have the potential to lower the cost of local memory accesses by orders of magnitude and provide substantially more bandwidth. Only through these transformationalmore » advances can future systems reach the goals of Exascale computing with a manageable power budgets. The Sandia led team included co-PIs from Columbia University, Lawrence Berkeley Lab, and the University of Maryland. The Columbia effort of Data Movement Dominates focused on developing a physically accurate simulation environment and experimental verification for optically-connected memory (OCM) systems that can enable continued performance scaling through high-bandwidth capacity, energy-efficient bit-rate transparency, and time-of-flight latency. With OCM, memory device parallelism and total capacity can scale to match future high-performance computing requirements without sacrificing data-movement efficiency. When we consider systems with integrated photonics, links to memory can be seamlessly integrated with the interconnection network-in a sense, memory becomes a primary aspect of the interconnection network. At the core of the Columbia effort, toward expanding our understanding of OCM enabled computing we have created an integrated modeling and simulation environment that uniquely integrates the physical behavior of the optical layer. The PhoenxSim suite of design and software tools developed under this effort has enabled the co-design of and performance evaluation photonics-enabled OCM architectures on Exascale computing systems.« less

Oxide-confined 2D VCSEL arrays for high-density inter/intra-chip interconnects

NASA Astrophysics Data System (ADS)

King, Roger; Michalzik, Rainer; Jung, Christian; Grabherr, Martin; Eberhard, Franz; Jaeger, Roland; Schnitzer, Peter; Ebeling, Karl J.

1998-04-01

We have designed and fabricated 4 X 8 vertical-cavity surface-emitting laser (VCSEL) arrays intended to be used as transmitters in short-distance parallel optical interconnects. In order to meet the requirements of 2D, high-speed optical links, each of the 32 laser diodes is supplied with two individual top contacts. The metallization scheme allows flip-chip mounting of the array modules junction-side down on silicon complementary metal oxide semiconductor (CMOS) chips. The optical and electrical characteristics across the arrays with device pitch of 250 micrometers are quite homogeneous. Arrays with 3 micrometers , 6 micrometers and 10 micrometers active diameter lasers have been investigated. The small devices show threshold currents of 600 (mu) A, single-mode output powers as high as 3 mW and maximum wavelength deviations of only 3 nm. The driving characteristics of all arrays are fully compatible to advanced 3.3 V CMOS technology. Using these arrays, we have measured small-signal modulation bandwidths exceeding 10 GHz and transmitted pseudo random data at 8 Gbit/s channel over 500 m graded index multimode fiber. This corresponds to a data transmission rate of 256 Gbit/s per array of 1 X 2 mm2 footprint area.

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

NASA Astrophysics Data System (ADS)

Bartelink, Dirk J.

1998-11-01

The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must recognize—test is also performed using IC's. A system interconnection is proposed using multiple chips fabricated with conventional silicon processes, including MEMS technology. The system resembles an MCM that can be joined without committing to final assembly to perform at-speed testing. 50-Ohm test probes never load the circuit; only intended neighboring chips are ever connected. A `back-plane' chip provides the connection layers for both inter- and intra-chip signals and also serves as the probe card, in analogy with membrane probes now used for single-chip testing. Intra-chip connections, which require complicated connections during test that exactly match the product, are then properly made and all waveforms and loading conditions under test will be identical to those of the product. The major benefit is that all front-end chip technologies can be merged—logic, memory, RF, even passives. ESD protection is required only on external system connections. Manufacturing test information will accurately characterize process faults and thus avoid the Known-Good-Die problem that has slowed the arrival of conventional MCM's.

Parallel-Processing CMOS Circuitry for M-QAM and 8PSK TCM

NASA Technical Reports Server (NTRS)

Gray, Andrew; Lee, Dennis; Hoy, Scott; Fisher, Dave; Fong, Wai; Ghuman, Parminder

2009-01-01

There has been some additional development of parts reported in "Multi-Modulator for Bandwidth-Efficient Communication" (NPO-40807), NASA Tech Briefs, Vol. 32, No. 6 (June 2009), page 34. The focus was on 1) The generation of M-order quadrature amplitude modulation (M-QAM) and octonary-phase-shift-keying, trellis-coded modulation (8PSK TCM), 2) The use of square-root raised-cosine pulse-shaping filters, 3) A parallel-processing architecture that enables low-speed [complementary metal oxide/semiconductor (CMOS)] circuitry to perform the coding, modulation, and pulse-shaping computations at a high rate; and 4) Implementation of the architecture in a CMOS field-programmable gate array.

Reduction of CMOS Image Sensor Read Noise to Enable Photon Counting.

PubMed

Guidash, Michael; Ma, Jiaju; Vogelsang, Thomas; Endsley, Jay

2016-04-09

Recent activity in photon counting CMOS image sensors (CIS) has been directed to reduction of read noise. Many approaches and methods have been reported. This work is focused on providing sub 1 e(-) read noise by design and operation of the binary and small signal readout of photon counting CIS. Compensation of transfer gate feed-through was used to provide substantially reduced CDS time and source follower (SF) bandwidth. SF read noise was reduced by a factor of 3 with this method. This method can be applied broadly to CIS devices to reduce the read noise for small signals to enable use as a photon counting sensor.

Terahertz radiation mixer

DOEpatents

Wanke, Michael C [Albuquerque, NM; Allen, S James [Santa Barbara, CA; Lee, Mark [Albuquerque, NM

2008-05-20

A terahertz radiation mixer comprises a heterodyned field-effect transistor (FET) having a high electron mobility heterostructure that provides a gatable two-dimensional electron gas in the channel region of the FET. The mixer can operate in either a broadband pinch-off mode or a narrowband resonant plasmon mode by changing a grating gate bias of the FET. The mixer can beat an RF signal frequency against a local oscillator frequency to generate an intermediate frequency difference signal in the microwave region. The mixer can have a low local oscillator power requirement and a large intermediate frequency bandwidth. The terahertz radiation mixer is particularly useful for terahertz applications requiring high resolution.

MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems

PubMed Central

Pannuto, Pat; Lee, Yoonmyung; Kuo, Ye-Sheng; Foo, ZhiYoong; Kempke, Benjamin; Kim, Gyouho; Dreslinski, Ronald G.; Blaauw, David; Dutta, Prabal

2015-01-01

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized—yet reusable—components with an interconnect that permits tiny, ultra-low power systems. In contrast to today’s interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two “shoot-through” rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient’s power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom chips from three different semiconductor processes. A three-chip, 2.2 mm3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/chip for communication. This is the lowest power for any system bus with MBus’s feature set. PMID:26855555

MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems.

PubMed

Pannuto, Pat; Lee, Yoonmyung; Kuo, Ye-Sheng; Foo, ZhiYoong; Kempke, Benjamin; Kim, Gyouho; Dreslinski, Ronald G; Blaauw, David; Dutta, Prabal

2015-06-01

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus , a new 4-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom chips from three different semiconductor processes. A three-chip, 2.2 mm 3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/chip for communication. This is the lowest power for any system bus with MBus's feature set.

RAID-2: Design and implementation of a large scale disk array controller

NASA Technical Reports Server (NTRS)

Katz, R. H.; Chen, P. M.; Drapeau, A. L.; Lee, E. K.; Lutz, K.; Miller, E. L.; Seshan, S.; Patterson, D. A.

1992-01-01

We describe the implementation of a large scale disk array controller and subsystem incorporating over 100 high performance 3.5 inch disk drives. It is designed to provide 40 MB/s sustained performance and 40 GB capacity in three 19 inch racks. The array controller forms an integral part of a file server that attaches to a Gb/s local area network. The controller implements a high bandwidth interconnect between an interleaved memory, an XOR calculation engine, the network interface (HIPPI), and the disk interfaces (SCSI). The system is now functionally operational, and we are tuning its performance. We review the design decisions, history, and lessons learned from this three year university implementation effort to construct a truly large scale system assembly.

A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

PubMed

Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

2014-02-10

We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

Scalable Motion Estimation Processor Core for Multimedia System-on-Chip Applications

NASA Astrophysics Data System (ADS)

Lai, Yeong-Kang; Hsieh, Tian-En; Chen, Lien-Fei

2007-04-01

In this paper, we describe a high-throughput and scalable motion estimation processor architecture for multimedia system-on-chip applications. The number of processing elements (PEs) is scalable according to the variable algorithm parameters and the performance required for different applications. Using the PE rings efficiently and an intelligent memory-interleaving organization, the efficiency of the architecture can be increased. Moreover, using efficient on-chip memories and a data management technique can effectively decrease the power consumption and memory bandwidth. Techniques for reducing the number of interconnections and external memory accesses are also presented. Our results demonstrate that the proposed scalable PE-ringed architecture is a flexible and high-performance processor core in multimedia system-on-chip applications.

PSAW/MicroSWIS [Microminiature Surface Acoustic Wave (SAW) based Wirelesss Instrumentation System

NASA Technical Reports Server (NTRS)

Heermann, Doug; Krug, Eric

2004-01-01

This Final Report for the PSAW/MicroSWIS Program is provided in compliance with contract number NAS3-01118. This report documents the overall progress of the program and presents project objectives, work carried out, and results obtained. Program Conceptual Design Package stated the following objectives: To develop a sensor/transceiver network that can support networking operations within spacecraft with sufficient bandwidth so that (1) flight control data, (2) avionics data, (3) payload/experiment data, and (4) prognostic health monitoring sensory information can flow to appropriate locations at frequencies that contain the maximum amount of information content but require minimum interconnect and power: a very high speed, low power, programmable modulation, spread-spectrum radio sensor/transceiver.

Holistic design in high-speed optical interconnects

NASA Astrophysics Data System (ADS)

Saeedi, Saman

Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a corresponding increase in inter-chip communication bandwidth. As bandwidth requirements for chip-to-chip interconnection scale, deficiencies of electrical channels become more apparent. Optical links present a viable alternative due to their low frequency-dependent loss and higher bandwidth density in the form of wavelength division multiplexing. As integrated photonics and bonding technologies are maturing, commercialization of hybrid-integrated optical links are becoming a reality. Increasing silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics brings their performance to unprecedented levels. This thesis presents developments in high-speed optical links by co-designing and co-integrating the primary elements of an optical link: receiver, transmitter, and clocking. In the first part of this thesis a 3D-integrated CMOS/Silicon-photonic receiver will be presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. Measured results show -14.9dBm of sensitivity and energy eciency of 170fJ/b at 25Gb/s. The same receiver front-end is also used to implement source-synchronous 4-channel WDM-based parallel optical receiver. Quadrature ILO-based clocking is employed for synchronization and a novel frequency-tracking method that exploits the dynamics of IL in a quadrature ring oscillator to increase the effective locking range. An adaptive body-biasing circuit is designed to maintain the per-bit-energy consumption constant across wide data-rates. The prototype measurements indicate a record-low power consumption of 153fJ/b at 32Gb/s. The receiver sensitivity is measured to be -8.8dBm at 32Gb/s. Next, on the optical transmitter side, three new techniques will be presented. First one is a differential ring modulator that breaks the optical bandwidth/quality factor trade-off known to limit the speed of high-Q ring modulators. This structure maintains a constant energy in the ring to avoid pattern-dependent power droop. As a first proof of concept, a prototype has been fabricated and measured up to 10Gb/s. The second technique is thermal stabilization of micro-ring resonator modulators through direct measurement of temperature using a monolithic PTAT temperature sensor. The measured temperature is used in a feedback loop to adjust the thermal tuner of the ring. A prototype is fabricated and a closed-loop feedback system is demonstrated to operate at 20Gb/s in the presence of temperature fluctuations. The third technique is a switched-capacitor based pre-emphasis technique designed to extend the inherently low bandwidth of carrier injection micro-ring modulators. A measured prototype of the optical transmitter achieves energy efficiency of 342fJ/bit at 10Gb/s and the wavelength stabilization circuit based on the monolithic PTAT sensor consumes 0.29mW. Lastly, a first-order frequency synthesizer that is suitable for high-speed on-chip clock generation will be discussed. The proposed design features an architecture combining an LC quadrature VCO, two sample-and-holds, a PI, digital coarse-tuning, and rotational frequency detection for fine-tuning. In addition to an electrical reference clock, as an extra feature, the prototype chip is capable of receiving a low jitter optical reference clock generated by a high-repetition-rate mode-locked laser. The output clock at 8GHz has an integrated RMS jitter of 490fs, peak-to-peak periodic jitter of 2.06ps, and total RMS jitter of 680fs. The reference spurs are measured to be 64.3dB below the carrier frequency. At 8GHz the system consumes 2.49mW from a 1V supply.

Generation of short and intense attosecond pulses

NASA Astrophysics Data System (ADS)

Khan, Sabih Ud Din

Extremely broad bandwidth attosecond pulses (which can support 16as pulses) have been demonstrated in our lab based on spectral measurements, however, compensation of intrinsic chirp and their characterization has been a major bottleneck. In this work, we developed an attosecond streak camera using a multi-layer Mo/Si mirror (bandwidth can support ˜100as pulses) and position sensitive time-of-flight detector, and the shortest measured pulse was 107.5as using DOG, which is close to the mirror bandwidth. We also developed a PCGPA based FROG-CRAB algorithm to characterize such short pulses, however, it uses the central momentum approximation and cannot be used for ultra-broad bandwidth pulses. To facilitate the characterization of such pulses, we developed PROOF using Fourier filtering and an evolutionary algorithm. We have demonstrated the characterization of pulses with a bandwidth corresponding to ˜20as using synthetic data. We also for the first time demonstrated single attosecond pulses (SAP) generated using GDOG with a narrow gate width from a multi-cycle driving laser without CE-phase lock, which opens the possibility of scaling attosecond photon flux by extending the technique to peta-watt class lasers. Further, we generated intense attosecond pulse trains (APT) from laser ablated carbon plasmas and demonstrated ˜9.5 times more intense pulses as compared to those from argon gas and for the first time demonstrated a broad continuum from a carbon plasma using DOG. Additionally, we demonstrated ˜100 times enhancement in APT from gases by switching to 400 nm (blue) driving pulses instead of 800 nm (red) pulses. We measured the ellipticity dependence of high harmonics from blue pulses in argon, neon and helium, and developed a simple theoretical model to numerically calculate the ellipticity dependence with good agreement with experiments. Based on the ellipticity dependence, we proposed a new scheme of blue GDOG which we predict can be employed to extract intense SAP from an APT driven by blue laser pulses. We also demonstrated compression of long blue pulses into >240 microJ broad-bandwidth pulses using neon filled hollow core fiber, which is the highest reported pulse energy of short blue pulses. However, compression of phase using chirp mirrors is still a technical challenge.

Femtosecond laser inscription of optical circuits in the cladding of optical fibers

NASA Astrophysics Data System (ADS)

Grenier, Jason R.

The aim of this dissertation was to address the question of whether the cladding of single-mode fibers (SMFs) could be modified to enable optical fibers to serve as a more integrated, highly functional platform for optical circuit devices that can efficiently interconnect with the pre-existing fiber core waveguide. The approach adopted in this dissertation was to employ femtosecond laser direct writing (FLDW), an inherently 3D fabrication technique that harnesses non-linear laser-material interactions to modify the fused silica fiber cladding. A fiber mounting and alignment technique was developed along with oil-immersion focusing to address the strong aberrations caused by the cylindrical fiber shape. The development of real-time device monitoring during the FLDW was instrumental to overcome the acute coupling sensitivity to laser alignment errors of +/-1 ?m positional uncertainty, and thereby opened a new practical direction for the precise fabrication of optical devices inside optical fibers. These powerful and flexible laser fabrication and characterization techniques were successfully employed to optimize optical waveguiding devices positioned within the core and cladding of optical fibers. X-, S-Bend, and directional couplers were developed to enable efficient coupling between the laser-formed cladding devices and the pre-existing core waveguide, enabling up to 62% power transfer over bandwidths up to 300 nm at telecommunication wavelengths. Precise alignment of femtosecond laser modification tracks were positioned inside or near the core waveguide of SMFs was further shown to enable a flexible reshaping of the optical properties to create multimode guiding sections arbitrarily along the fiber length. This core waveguide modification facilitated the precise formation of multimode interferometers along the core waveguide to precisely tailor the modal profiles, and control the spectral and polarization response. In-fiber multimode interference (MMI) splitters and couplers were fabricated with coupling ratios from 2% to 50% over a broad 350 nm bandwidth across the telecommunication band. Laser-induced birefringence was harnessed to generate polarization dependent MMI devices for strong polarization filtering (24 dB isolation), or polarization selective taps with up to 50% tapping efficiency over a 25 nm bandwidth. This dissertation is therefore the first demonstration of femtosecond laser direct writing as a flexible and monolithic means of embedding and integrating highly functional optical circuit devices within the cladding of optical fibers that can interconnect efficiently with the pre-existing fiber core waveguide. These developments represent a significant technological advancement for creating new 3D photonic integrated microsystems within the cladding of optical fibers and underpins a new technological platform of fiber cladding photonics.

Factors responsible for remote-frequency masking in children and adultsa)

PubMed Central

Leibold, Lori J.; Buss, Emily

2016-01-01

Susceptibility to remote-frequency masking in children and adults was evaluated with respect to three stimulus features: (1) masker bandwidth, (2) spectral separation of the signal and masker, and (3) gated versus continuous masker presentation. Listeners were 4- to 6-year-olds, 7- to 10-year-olds, and adults. Detection thresholds for a 500-ms, 2000-Hz signal were estimated in quiet or presented with a band of noise in one of four frequency regions: 425–500 Hz, 4000–4075 Hz, 8000–8075 Hz, or 4000–10 000 Hz. In experiment 1, maskers were gated on in each 500-ms interval of a three-interval, forced-choice adaptive procedure. Masking was observed for all ages in all maskers, but the greatest masking was observed for the 4000–4075 Hz masker. These findings suggest that signal/masker spectral proximity plays an important role in remote-frequency masking, even when peripheral excitation associated with the signal and masker does not overlap. Younger children tended to have more masking than older children or adults, consistent with a reduced ability to segregate simultaneous sounds and/or listen in a frequency-selective manner. In experiment 2, detection thresholds were estimated in the same noises, but maskers were presented continuously. Masking was reduced for all ages relative to gated conditions, suggesting improved segregation and/or frequency-selective listening. PMID:28040030

ESR Experiments on a Single Donor Electron in Isotopically Enriched Silicon

NASA Astrophysics Data System (ADS)

Tracy, Lisa; Luhman, Dwight; Carr, Stephen; Borchardt, John; Bishop, Nathaniel; Ten Eyck, Gregory; Pluym, Tammy; Wendt, Joel; Witzel, Wayne; Blume-Kohout, Robin; Nielsen, Erik; Lilly, Michael; Carroll, Malcolm

In this talk we will discuss electron spin resonance experiments in single donor silicon qubit devices fabricated at Sandia National Labs. A self-aligned device structure consisting of a polysilicon gate SET located adjacent to the donor is used for donor electron spin readout. Using a cryogenic HEMT amplifier next to the silicon device, we demonstrate spin readout at 100 kHz bandwidth and Rabi oscillations with 0.96 visibility. Electron spin resonance measurements on these devices show a linewidth of 30 kHz and coherence times T2* = 10 us and T2 = 0.3 ms. We also discuss estimates of the fidelity of our donor electron spin qubit measurements using gate set tomography. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000. ESR Experiments on a Single Donor Electron in Isotopically Enriched Silicon.

Practical issues in ultrashort-laser-pulse measurement using frequency-resolved optical gating

DOE Office of Scientific and Technical Information (OSTI.GOV)

DeLong, K.W.; Fittinghoff, D.N.; Trebino, R.

1996-07-01

The authors explore several practical experimental issues in measuring ultrashort laser pulses using the technique of frequency-resolved optical gating (FROG). They present a simple method for checking the consistency of experimentally measured FROG data with the independently measured spectrum and autocorrelation of the pulse. This method is a powerful way of discovering systematic errors in FROG experiments. They show how to determine the optimum sampling rate for FROG and show that this satisfies the Nyquist criterion for the laser pulse. They explore the low- and high-power limits to FROG and determine that femtojoule operation should be possible, while the effectsmore » of self-phase modulation limit the highest signal efficiency in FROG to 1%. They also show quantitatively that the temporal blurring due to a finite-thickness medium in single-shot geometries does not strongly limit the FROG technique. They explore the limiting time-bandwidth values that can be represented on a FROG trace of a given size. Finally, they report on a new measure of the FROG error that improves convergence in the presence of noise.« less

NASA Tech Briefs, April 2008

NASA Technical Reports Server (NTRS)

2008-01-01

Topics covered include: Gas Sensors Based on Coated and Doped Carbon Nanotubes; Tactile Robotic Topographical Mapping Without Force or Contact Sensors; Thin-Film Magnetic-Field-Response Fluid-Level Sensor for Non-Viscous Fluids; Progress in Development of Improved Ion-Channel Biosensors; Simulating Operation of a Complex Sensor Network; Using Transponders on the Moon to Increase Accuracy of GPS; Controller for Driving a Piezoelectric Actuator at Resonance; Coaxial Electric Heaters; Dual-Input AND Gate From Single-Channel Thin-Film FET; High-Density, High-Bandwidth, Multilevel Holographic Memory; Fabrication of Gate-Electrode Integrated Carbon-Nanotube Bundle Field Emitters; Hydroxide-Assisted Bonding of Ultra-Low-Expansion Glass; Photochemically Synthesized Polyimides; Optimized Carbonate and Ester-Based Li-Ion Electrolytes; Compact 6-DOF Stage for Optical Adjustments; Ultrasonic/Sonic Impacting Penetrators; Miniature, Lightweight, One-Time-Opening Valve; Supplier Management System; Improved CLARAty Functional-Layer/Decision-Layer Interface; JAVA Stereo Display Toolkit; Remote-Sensing Time Series Analysis, a Vegetation Monitoring Tool; PyPele Rewritten To Use MPI; Data Assimilation Cycling for Weather Analysis; Hydrocyclone/Filter for Concentrating Biomarkers from Soil; Activating STAT3 Alpha for Promoting Healing of Neurons; and Probing a Spray Using Frequency-Analyzed Light Scattering.

Generation of single attosecond pulse within one atomic unit by using multi-cycle inhomogeneous polarization gating technology in bowtie-shaped nanostructure

NASA Astrophysics Data System (ADS)

Feng, Liqiang; Liu, Hang

2018-04-01

The generations of high-order harmonic spectra and single attosecond pulses (SAPs) driven by the multi-cycle inhomogeneous polarization gating (PG) technology in the bowtie-shaped nanostructure have been theoretically investigated. It is found that by setting the bowtie-shaped nanostructure along the driven laser polarization direction, not only the extension of the harmonic cutoff can be achieved, caused by the surface plasmon polaritons, but also the modulations of the harmonics can be decreased, caused by the PG technology and the inhomogeneous effect. As a result, the contribution of the harmonic plateau is only from one harmonic emission peak with the dominant short quantum path. Further, by properly adding a half-cycle pulse into the driven laser field, the harmonic emission process can be precisely controlled in the half-cycle duration and a supercontinuum with the bandwidth of 263 eV can be obtained. Finally, by directly superposing the harmonics from this supercontinuum, a SAP with the full width at half maximum of 23 as can be obtained, which is shorter than one atomic unit.

The Development of Design Tools for Fault Tolerant Quantum Dot Cellular Automata Based Logic

NASA Technical Reports Server (NTRS)

Armstrong, Curtis D.; Humphreys, William M.

2003-01-01

We are developing software to explore the fault tolerance of quantum dot cellular automata gate architectures in the presence of manufacturing variations and device defects. The Topology Optimization Methodology using Applied Statistics (TOMAS) framework extends the capabilities of the A Quantum Interconnected Network Array Simulator (AQUINAS) by adding front-end and back-end software and creating an environment that integrates all of these components. The front-end tools establish all simulation parameters, configure the simulation system, automate the Monte Carlo generation of simulation files, and execute the simulation of these files. The back-end tools perform automated data parsing, statistical analysis and report generation.

Submillimeter-Wave Amplifier Module with Integrated Waveguide Transitions

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Chattopadhyay, Goutam; Pukala, David; Gaier, Todd; Soria, Mary; ManFung, King; Deal, William; Mei, Gerry; Radisic, Vesna; Lai, Richard

2009-01-01

To increase the usefulness of monolithic millimeter-wave integrated circuit (MMIC) components at submillimeter-wave frequencies, a chip has been designed that incorporates two integrated, radial E-plane probes with an MMIC amplifier in between, thus creating a fully integrated waveguide module. The integrated amplifier chip has been fabricated in 35-nm gate length InP high-electron-mobility-transistor (HEMT) technology. The radial probes were mated to grounded coplanar waveguide input and output lines in the internal amplifier. The total length of the internal HEMT amplifier is 550 m, while the total integrated chip length is 1,085 m. The chip thickness is 50 m with the chip width being 320 m. The internal MMIC amplifier is biased through wire-bond connections to the gates and drains of the chip. The chip has 3 stages, employing 35-nm gate length transistors in each stage. Wire bonds from the DC drain and gate pads are connected to off-chip shunt 51-pF capacitors, and additional off-chip capacitors and resistors are added to the gate and drain bias lines for low-frequency stability of the amplifier. Additionally, bond wires to the grounded coplanar waveguide pads at the RF input and output of the internal amplifier are added to ensure good ground connections to the waveguide package. The S-parameters of the module, not corrected for input or output waveguide loss, are measured at the waveguide flange edges. The amplifier module has over 10 dB of gain from 290 to 330 GHz, with a peak gain of over 14 dB at 307 GHz. The WR2.2 waveguide cutoff is again observed at 268 GHz. The module is biased at a drain current of 27 mA, a drain voltage of 1.24 V, and a gate voltage of +0.21 V. Return loss of the module is very good between 5 to 25 dB. This result illustrates the usefulness of the integrated radial probe transition, and the wide (over 10-percent) bandwidth that one can expect for amplifier modules with integrated radial probes in the submillimeter-regime (>300 GHz).

Full kinetics of CO entry, internal diffusion, and exit in myoglobin from transition-path theory simulations.

PubMed

Yu, Tang-Qing; Lapelosa, Mauro; Vanden-Eijnden, Eric; Abrams, Cameron F

2015-03-04

We use Markovian milestoning molecular dynamics (MD) simulations on a tessellation of the collective variable space for CO localization in myoglobin to estimate the kinetics of entry, exit, and internal site-hopping. The tessellation is determined by analysis of the free-energy surface in that space using transition-path theory (TPT), which provides criteria for defining optimal milestones, allowing short, independent, cell-constrained MD simulations to provide properly weighted kinetic data. We coarse grain the resulting kinetic model at two levels: first, using crystallographically relevant internal cavities and their predicted interconnections and solvent portals; and second, as a three-state side-path scheme inspired by similar models developed from geminate recombination experiments. We show semiquantitative agreement with experiment on entry and exit rates and in the identification of the so-called "histidine gate" at position 64 through which ≈90% of flux between solvent and the distal pocket passes. We also show with six-dimensional calculations that the minimum free-energy pathway of escape through the histidine gate is a "knock-on" mechanism in which motion of the ligand and the gate are sequential and interdependent. In total, these results suggest that such TPT simulations are indeed a promising approach to overcome the practical time-scale limitations of MD to allow reliable estimation of transition mechanisms and rates among metastable states.

Gbps wireless transceivers for high bandwidth interconnections in distributed cyber physical systems

NASA Astrophysics Data System (ADS)

Saponara, Sergio; Neri, Bruno

2015-05-01

In Cyber Physical Systems there is a growing use of high speed sensors like photo and video camera, radio and light detection and ranging (Radar/Lidar) sensors. Hence Cyber Physical Systems can benefit from the high communication data rate, several Gbps, that can be provided by mm-wave wireless transceivers. At such high frequency the wavelength is few mm and hence the whole transceiver including the antenna can be integrated in a single chip. To this aim this paper presents the design of 60 GHz transceiver architecture to ensure connection distances up to 10 m and data rate up to 4 Gbps. At 60 GHz there are more than 7 GHz of unlicensed bandwidth (available for free for development of new services). By using a CMOS SOI technology RF, analog and digital baseband circuitry can be integrated in the same chip minimizing noise coupling. Even the antenna is integrated on chip reducing cost and size vs. classic off-chip antenna solutions. Therefore the proposed transceiver can enable at physical layer the implementation of low cost nodes for a Cyber Physical System with data rates of several Gbps and with a communication distance suitable for home/office scenarios, or on-board vehicles such as cars, trains, ships, airplanes

Plug-and-play design approach to smart harness for modular small satellites

NASA Astrophysics Data System (ADS)

Mughal, M. Rizwan; Ali, Anwar; Reyneri, Leonardo M.

2014-02-01

A typical satellite involves many different components that vary in bandwidth demand. Sensors that require a very low data rate may reside on a simple two- or three-wire interface such as I2C, SPI, etc. Complex sensors that require high data rate and bandwidth may reside on an optical interface. The AraMiS architecture is an enhanced capability architecture with different satellite configurations. Although keeping the low-cost and COTS approach of CubeSats, it extends the modularity concept as it also targets different satellite shapes and sizes. But modularity moves beyond the mechanical structure: the tiles also have thermo-mechanical, harness and signal-processing functionalities. Further modularizing the system, every tile can also host a variable number of small sensors, actuators or payloads, connected using a plug-and-play approach. Every subsystem is housed in a small daughter board and is supplied, by the main tile, with power and data distribution functions, power and data harness, mechanical support and is attached and interconnected with space-grade spring-loaded connectors. The tile software is also modular and allows a quick adaptation to specific subsystems. The basic software for the CPU is properly hardened to guarantee high level of radiation tolerance at very low cost.

Functional asymmetry and plasticity of electrical synapses interconnecting neurons through a 36-state model of gap junction channel gating

PubMed Central

Kraujalis, Tadas; Maciunas, Kestutis

2017-01-01

We combined the Hodgkin–Huxley equations and a 36-state model of gap junction channel gating to simulate electrical signal transfer through electrical synapses. Differently from most previous studies, our model can account for dynamic modulation of junctional conductance during the spread of electrical signal between coupled neurons. The model of electrical synapse is based on electrical properties of the gap junction channel encompassing two fast and two slow gates triggered by the transjunctional voltage. We quantified the influence of a difference in input resistances of electrically coupled neurons and instantaneous conductance–voltage rectification of gap junctions on an asymmetry of cell-to-cell signaling. We demonstrated that such asymmetry strongly depends on junctional conductance and can lead to the unidirectional transfer of action potentials. The simulation results also revealed that voltage spikes, which develop between neighboring cells during the spread of action potentials, can induce a rapid decay of junctional conductance, thus demonstrating spiking activity-dependent short-term plasticity of electrical synapses. This conclusion was supported by experimental data obtained in HeLa cells transfected with connexin45, which is among connexin isoforms expressed in neurons. Moreover, the model allowed us to replicate the kinetics of junctional conductance under different levels of intracellular concentration of free magnesium ([Mg2+]i), which was experimentally recorded in cells expressing connexin36, a major neuronal connexin. We demonstrated that such [Mg2+]i-dependent long-term plasticity of the electrical synapse can be adequately reproduced through the changes of slow gate parameters of the 36-state model. This suggests that some types of chemical modulation of gap junctions can be executed through the underlying mechanisms of voltage gating. Overall, the developed model accounts for direction-dependent asymmetry, as well as for short- and long-term plasticity of electrical synapses. Our modeling results demonstrate that such complex behavior of the electrical synapse is important in shaping the response of coupled neurons. PMID:28384220

Efficient Multiplexer FPGA Block Structures Based on G4FETs

NASA Technical Reports Server (NTRS)

Vatan, Farrokh; Fijany, Amir

2009-01-01

Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few additional logic gates such as ANDs or ORs. Interconnections are realized by means of programmable switches that may connect the input terminals of a block to output terminals of other blocks, may bridge together some of the inputs, or may connect some of the input terminals to signal sources representing constant logical levels 0 or 1. The left part of the figure depicts a four-to-one G(sup 4)FET-based multiplexer tree; the right part of the figure depicts a functionally equivalent four-to-one multiplexer based on conventional transistors. The G(sup 4)FET version would contains 54 transistors; the conventional version contains 70 transistors.

Subspace projection method for unstructured searches with noisy quantum oracles using a signal-based quantum emulation device

NASA Astrophysics Data System (ADS)

La Cour, Brian R.; Ostrove, Corey I.

2017-01-01

This paper describes a novel approach to solving unstructured search problems using a classical, signal-based emulation of a quantum computer. The classical nature of the representation allows one to perform subspace projections in addition to the usual unitary gate operations. Although bandwidth requirements will limit the scale of problems that can be solved by this method, it can nevertheless provide a significant computational advantage for problems of limited size. In particular, we find that, for the same number of noisy oracle calls, the proposed subspace projection method provides a higher probability of success for finding a solution than does an single application of Grover's algorithm on the same device.

The NASA satellite communication 20 x 20 matrix switches

NASA Technical Reports Server (NTRS)

Saunders, A. L.

1983-01-01

The characteristics of two matrix switches designed for high capacity satellite communications systems are described. The switches provide routing between 20 input and 20 output ports at an IF frequency during TDMA operations. Switching speeds of 10 nsec are projected for dual gate GaAs FETs. The two designs differed in the coupling configurations, bandwidth (2.69-1.2 GHz), off-state isolation (-54 to -40 dB), switching speeds (16-37 nsec), and gain ripple (5.3-2.2 dB). Both designs achieved a 2 nsec reconfiguration rate. Further development is required to reduce the ripple effects and attain the potential 2 nsec switching speed offered by the GaAs FETs.

Reduction of CMOS Image Sensor Read Noise to Enable Photon Counting

PubMed Central

Guidash, Michael; Ma, Jiaju; Vogelsang, Thomas; Endsley, Jay

2016-01-01

Recent activity in photon counting CMOS image sensors (CIS) has been directed to reduction of read noise. Many approaches and methods have been reported. This work is focused on providing sub 1 e− read noise by design and operation of the binary and small signal readout of photon counting CIS. Compensation of transfer gate feed-through was used to provide substantially reduced CDS time and source follower (SF) bandwidth. SF read noise was reduced by a factor of 3 with this method. This method can be applied broadly to CIS devices to reduce the read noise for small signals to enable use as a photon counting sensor. PMID:27070625

Late-Time Evolution of Broad-Bandwidth, Laser-Imposed Nonuniformities in Accelerated Foils

NASA Astrophysics Data System (ADS)

Smalyuk, V. A.; Boehly, T. R.; Bradley, D. K.; Knauer, J. P.; Meyerhofer, D. D.; Oron, D.; Srebro, Y.; Shvarts, D.

1998-11-01

The late-time evolution of broad-bandwidth nonuniformities is studied in planar-foil experiments on the OMEGA laser system. Five beams with ~600-μm-diam uniform region accelerate 20-μm-thick CH foils at an average intensity of 2×10^14\\:W/cm^2 in a 3-ns square pulse. Growth of perturbations seeded by irradiation nonuniformities was observed using time-gated, pinhole photographs of ~1.2-keV x rays from a backlighter. At late times collective saturation is observed at levels similar to Haan's prediction.(S. W. Haan, Phys. Rev. A 39), 5812 (1989). The maximum of the nonuniformity spectrum moves toward longer wavelength in time as expected. Target images taken at different times show the formation of bubbles and spikes from initial elongated ``wormy'' structures. This work was supported by the U.S. Department of Energy Office of Inertial Confinement Fusion under Cooperative Agreement No. DE-FC03-92SF19460, the University of Rochester, and the New York State Energy Research and Development Authority. The support of DOE does not constitute an endorsement by DOE of the views expressed in this article.

Multi-Rate Acquisition for Dead Time Reduction in Magnetic Resonance Receivers: Application to Imaging With Zero Echo Time.

PubMed

Marjanovic, Josip; Weiger, Markus; Reber, Jonas; Brunner, David O; Dietrich, Benjamin E; Wilm, Bertram J; Froidevaux, Romain; Pruessmann, Klaas P

2018-02-01

For magnetic resonance imaging of tissues with very short transverse relaxation times, radio-frequency excitation must be immediately followed by data acquisition with fast spatial encoding. In zero-echo-time (ZTE) imaging, excitation is performed while the readout gradient is already on, causing data loss due to an initial dead time. One major dead time contribution is the settling time of the filters involved in signal down-conversion. In this paper, a multi-rate acquisition scheme is proposed to minimize dead time due to filtering. Short filters and high output bandwidth are used initially to minimize settling time. With increasing time since the signal onset, longer filters with better frequency selectivity enable stronger signal decimation. In this way, significant dead time reduction is accomplished at only a slight increase in the overall amount of output data. Multi-rate acquisition was implemented with a two-stage filter cascade in a digital receiver based on a field-programmable gate array. In ZTE imaging in a phantom and in vivo, dead time reduction by multi-rate acquisition is shown to improve image quality and expand the feasible bandwidth while increasing the amount of data collected by only a few percent.

A survey of tools and resources for the next generation analyst

NASA Astrophysics Data System (ADS)

Hall, David L.; Graham, Jake; Catherman, Emily

2015-05-01

We have previously argued that a combination of trends in information technology (IT) and changing habits of people using IT provide opportunities for the emergence of a new generation of analysts that can perform effective intelligence, surveillance and reconnaissance (ISR) on a "do it yourself" (DIY) or "armchair" approach (see D.L. Hall and J. Llinas (2014)). Key technology advances include: i) new sensing capabilities including the use of micro-scale sensors and ad hoc deployment platforms such as commercial drones, ii) advanced computing capabilities in mobile devices that allow advanced signal and image processing and modeling, iii) intelligent interconnections due to advances in "web N" capabilities, and iv) global interconnectivity and increasing bandwidth. In addition, the changing habits of the digital natives reflect new ways of collecting and reporting information, sharing information, and collaborating in dynamic teams. This paper provides a survey and assessment of tools and resources to support this emerging analysis approach. The tools range from large-scale commercial tools such as IBM i2 Analyst Notebook, Palantir, and GeoSuite to emerging open source tools such as GeoViz and DECIDE from university research centers. The tools include geospatial visualization tools, social network analysis tools and decision aids. A summary of tools is provided along with links to web sites for tool access.

Photonic quantum state transfer between a cold atomic gas and a crystal.

PubMed

Maring, Nicolas; Farrera, Pau; Kutluer, Kutlu; Mazzera, Margherita; Heinze, Georg; de Riedmatten, Hugues

2017-11-22

Interfacing fundamentally different quantum systems is key to building future hybrid quantum networks. Such heterogeneous networks offer capabilities superior to those of their homogeneous counterparts, as they merge the individual advantages of disparate quantum nodes in a single network architecture. However, few investigations of optical hybrid interconnections have been carried out, owing to fundamental and technological challenges such as wavelength and bandwidth matching of the interfacing photons. Here we report optical quantum interconnection of two disparate matter quantum systems with photon storage capabilities. We show that a quantum state can be transferred faithfully between a cold atomic ensemble and a rare-earth-doped crystal by means of a single photon at 1,552  nanometre telecommunication wavelength, using cascaded quantum frequency conversion. We demonstrate that quantum correlations between a photon and a single collective spin excitation in the cold atomic ensemble can be transferred to the solid-state system. We also show that single-photon time-bin qubits generated in the cold atomic ensemble can be converted, stored and retrieved from the crystal with a conditional qubit fidelity of more than 85 per cent. Our results open up the prospect of optically connecting quantum nodes with different capabilities and represent an important step towards the realization of large-scale hybrid quantum networks.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ahn, Wonmi; Zhao, Xin; Hong, Yan

Here, optoplasmonic structures contain plasmonic components embedded in a defined photonic environment to create synergistic interactions between photonic and plasmonic components. Here, we show that chains of optical microspheres containing gold nanoparticles in their evanescent field combine the light guiding properties of a microsphere chain with the light localizing properties of a plasmonic nanoantenna. We implement these materials through template guided self-assembly and investigate their fundamental electromagnetic working principles through combination of electromagnetic simulations and experimental characterization. We demonstrate that optoplasmonic chains implemented by directed self-assembly achieve a significant reduction in guiding losses when compared with conventional plasmonic waveguides and,more » at the same time, retain the light localizing properties of plasmonic antennas at pre-defined locations. The results reinforce the potential of optoplasmonic structures for realizing low-loss optical interconnects with high bandwidth.« less

An Application-Based Performance Characterization of the Columbia Supercluster

NASA Technical Reports Server (NTRS)

Biswas, Rupak; Djomehri, Jahed M.; Hood, Robert; Jin, Hoaqiang; Kiris, Cetin; Saini, Subhash

2005-01-01

Columbia is a 10,240-processor supercluster consisting of 20 Altix nodes with 512 processors each, and currently ranked as the second-fastest computer in the world. In this paper, we present the performance characteristics of Columbia obtained on up to four computing nodes interconnected via the InfiniBand and/or NUMAlink4 communication fabrics. We evaluate floating-point performance, memory bandwidth, message passing communication speeds, and compilers using a subset of the HPC Challenge benchmarks, and some of the NAS Parallel Benchmarks including the multi-zone versions. We present detailed performance results for three scientific applications of interest to NASA, one from molecular dynamics, and two from computational fluid dynamics. Our results show that both the NUMAlink4 and the InfiniBand hold promise for application scaling to a large number of processors.

Real-Time Wavefront Control for the PALM-3000 High Order Adaptive Optics System

NASA Technical Reports Server (NTRS)

Truong, Tuan N.; Bouchez, Antonin H.; Dekany, Richard G.; Guiwits, Stephen R.; Roberts, Jennifer E.; Troy, Mitchell

2008-01-01

We present a cost-effective scalable real-time wavefront control architecture based on off-the-shelf graphics processing units hosted in an ultra-low latency, high-bandwidth interconnect PC cluster environment composed of modules written in the component-oriented language of nesC. The architecture enables full-matrix reconstruction of the wavefront at up to 2 KHz with latency under 250 us for the PALM-3000 adaptive optics systems, a state-of-the-art upgrade on the 5.1 meter Hale Telescope that consists of a 64 x 64 subaperture Shack-Hartmann wavefront sensor and a 3368 active actuator high order deformable mirror in series with a 241 active actuator tweeter DM. The architecture can easily scale up to support much larger AO systems at higher rates and lower latency.

Optical data communication: fundamentals and future directions

NASA Astrophysics Data System (ADS)

DeCusatis, Casimer M.

1998-12-01

An overview of optical data communications is provided, beginning with a brief history and discussion of the unique requirements that distinguish this subfield from related areas such as telecommunications. Each of the major datacom standards is then discussed, including the physical layer specification, distances and data rates, fiber and connector types, data frame structures, and network considerations. These standards can be categorized by their prevailing applications, either storage [Enterprise System Connection, Fiber Channel Connection, and Fiber Channel], coupling (Fiber Channel), or networking [Fiber Distributed Data Interface, Gigabit Ethernet, and asynchronous transfer mode/synchronous optical network]. We also present some emerging technologies and their applications, including parallel optical interconnects, plastic optical fiber, wavelength multiplexing, and free- space optical links. We conclude with some cost/performance trade-offs and predictions of future bandwidth trends.

Model reduction by weighted Component Cost Analysis

NASA Technical Reports Server (NTRS)

Kim, Jae H.; Skelton, Robert E.

1990-01-01

Component Cost Analysis considers any given system driven by a white noise process as an interconnection of different components, and assigns a metric called 'component cost' to each component. These component costs measure the contribution of each component to a predefined quadratic cost function. A reduced-order model of the given system may be obtained by deleting those components that have the smallest component costs. The theory of Component Cost Analysis is extended to include finite-bandwidth colored noises. The results also apply when actuators have dynamics of their own. Closed-form analytical expressions of component costs are also derived for a mechanical system described by its modal data. This is very useful to compute the modal costs of very high order systems. A numerical example for MINIMAST system is presented.

Concepts for 18/30 GHz satellite communication system study. Executive summary

NASA Technical Reports Server (NTRS)

Baker, M.; Davies, R.; Cuccia, L.; Mitchell, C.

1979-01-01

An examination of a multiplicity of interconnected parameters ranging from specific technology details to total system economic costs for satellite communication systems at the 18/30 GHz transmission bands are presented. It was determined that K sub A band systems can incur a small communications outage during very heavy rainfall periods and that reducing the outage to zero would lead to prohibitive system costs. On the other hand, the economics of scale, ie, one spacecraft accommodating 2.5 GHz of bandwidth coupled with multiple beam frequency reuse, leads to very low costs for those users who can tolerate the 5 to 50 hours per year of downtime. A multiple frequency band satellite network can provide the ultimate optimized match to the consumer performance/economics demands.

Parallel scalability of Hartree-Fock calculations

NASA Astrophysics Data System (ADS)

Chow, Edmond; Liu, Xing; Smelyanskiy, Mikhail; Hammond, Jeff R.

2015-03-01

Quantum chemistry is increasingly performed using large cluster computers consisting of multiple interconnected nodes. For a fixed molecular problem, the efficiency of a calculation usually decreases as more nodes are used, due to the cost of communication between the nodes. This paper empirically investigates the parallel scalability of Hartree-Fock calculations. The construction of the Fock matrix and the density matrix calculation are analyzed separately. For the former, we use a parallelization of Fock matrix construction based on a static partitioning of work followed by a work stealing phase. For the latter, we use density matrix purification from the linear scaling methods literature, but without using sparsity. When using large numbers of nodes for moderately sized problems, density matrix computations are network-bandwidth bound, making purification methods potentially faster than eigendecomposition methods.

Design, fabrication, and characterization of high density silicon photonic components

NASA Astrophysics Data System (ADS)

Jones, Adam Michael

Our burgeoning appetite for data relentlessly demands exponential scaling of computing and communications resources leading to an overbearing and ever-present drive to improve eciency while reducing on-chip area even as photonic components expand to ll application spaces no longer satised by their electronic counterparts. With a high index contrast, low optical loss, and compatibility with the CMOS fabrication infrastructure, silicon-on-insulator technology delivers a mechanism by which ecient, sub-micron waveguides can be fabricated while enabling monolithic integration of photonic components and their associated electronic infrastructure. The result is a solution leveraging the superior bandwidth of optical signaling on a platform capable of delivering the optical analogue to Moore's Law scaling of transistor density. Device size is expected to end Moore's Law scaling in photonics as Maxwell's equations limit the extent to which this parameter may be reduced. The focus of the work presented here surrounds photonic device miniaturization and the development of 3D optical interconnects as approaches to optimize performance in densely integrated optical interconnects. In this dissertation, several technological barriers inhibiting widespread adoption of photonics in data communications and telecommunications are explored. First, examination of loss and crosstalk performance in silicon nitride over SOI waveguide crossings yields insight into the feasibility of 3D optical interconnects with the rst experimental analysis of such a structure presented herein. A novel measurement platform utilizing a modied racetrack resonator is then presented enabling extraction of insertion loss data for highly ecient structures while requiring minimal on-chip area. Finally, pioneering work in understanding the statistical nature of doublet formation in microphotonic resonators is delivered with the resulting impact on resonant device design detailed.

Microgroove fabrication with excimer laser ablation techniques for optical fiber array alignment purposes

NASA Astrophysics Data System (ADS)

Naessens, Kris; Van Hove, An; Coosemans, Thierry; Verstuyft, Steven; Vanwassenhove, Luc; Van Daele, Peter; Baets, Roel G.

2000-11-01

Currently, an ever increasing need for bandwidth, compactness and efficiency characterizes the world of interconnect and data communication. This tendency has already led to serial links being gradually replaced by parallel optical interconnect solutions. However, as the maximum capacity for the latter will be reached in the near future, new approaches are required to meet demand. One possible option is to switch to 2D parallel implementations of fiber arrays. In this paper we present the fabrication of a 2D connector for coupling a 4x8 array of plastic optical fibers to RCLED or VCSEL arrays. The connector consists primarily of dedicated PMMA plates in which arrays of 8 precisely dimensioned grooves at a pitch of 250 micrometers are introduced. The trenches are each 127 micrometers deep and their width is optimized to allow fixation of plastic optical fibers. We used excimer laser ablation for prototype fabrication of these alignment microstructures. In a later stage, the plates can be replicated using standard molding techniques. The laser ablation technique is extremely well suited for rapid prototyping and proves to be a versatile process yielding high accuracy dimensioning and repeatability of features in a wide diversity of materials. The dependency of the performance in terms of quality of the trenches (bottom roughness) and wall angle on various parameters (wavelength, energy density, pulse frequency and substrate material) is discussed. The fabricated polymer sheets with grooves are used to hold optical fibers by means of a UV-curable adhesive. In a final phase, the plates are stacked and glued in order to realize the 2D-connector of plastic optical fibers for short distance optical interconnects.

Design Fabrication and Characterization of High Density Silicon Photonic Components

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jones, Adam

2015-02-01

Our burgeoning appetite for data relentlessly demands exponential scaling of computing and communications resources leading to an overbearing and ever-present drive to improve e ciency while reducing on-chip area even as photonic components expand to ll application spaces no longer satis ed by their electronic counterparts. With a high index contrast, low optical loss, and compatibility with the CMOS fabrication infrastructure, silicon-on-insulator technology delivers a mechanism by which e cient, sub-micron waveguides can be fabricated while enabling monolithic integration of photonic components and their associated electronic infrastructure. The result is a solution leveraging the superior bandwidth of optical signaling onmore » a platform capable of delivering the optical analogue to Moore's Law scaling of transistor density. Device size is expected to end Moore's Law scaling in photonics as Maxwell's equations limit the extent to which this parameter may be reduced. The focus of the work presented here surrounds photonic device miniaturization and the development of 3D optical interconnects as approaches to optimize performance in densely integrated optical interconnects. In this dissertation, several technological barriers inhibiting widespread adoption of photonics in data communications and telecommunications are explored. First, examination of loss and crosstalk performance in silicon nitride over SOI waveguide crossings yields insight into the feasibility of 3D optical interconnects with the rst experimental analysis of such a structure presented herein. A novel measurement platform utilizing a modi ed racetrack resonator is then presented enabling extraction of insertion loss data for highly e cient structures while requiring minimal on-chip area. Finally, pioneering work in understanding the statistical nature of doublet formation in microphotonic resonators is delivered with the resulting impact on resonant device design detailed.« less

Ultra-High Capacity Silicon Photonic Interconnects through Spatial Multiplexing

NASA Astrophysics Data System (ADS)

Chen, Christine P.

The market for higher data rate communication is driving the semiconductor industry to develop new techniques of writing at smaller scales, while continuing to scale bandwidth at low power consumption. Silicon photonic (SiPh) devices offer a potential solution to the electronic interconnect bandwidth bottleneck. SiPh leverages the technology commensurate of decades of fabrication development with the unique functionality of next-generation optical interconnects. Finer fabrication techniques have allowed for manufacturing physical characteristics of waveguide structures that can support multiple modes in a single waveguide. By refining modal characteristics in photonic waveguide structures, through mode multiplexing with the asymmetric y-junction and microring resonator, higher aggregate data bandwidth is demonstrated via various combinations of spatial multiplexing, broadening applications supported by the integrated platform. The main contributions of this dissertation are summarized as follows. Experimental demonstrations of new forms of spatial multiplexing combined together exhibit feasibility of data transmission through mode-division multiplexing (MDM), mode-division and wavelength-division multiplexing (MDM-WDM), and mode-division and polarization-division multiplexing (MDM-PDM) through a C-band, Si photonic platform. Error-free operation through mode multiplexers and demultiplexers show how data can be viably scaled on multiple modes and with existing spatial domains simultaneously. Furthermore, we explore expanding device channel support from two to three arms. Finding that a slight mismatch in the third arm can increase crosstalk contributions considerably, especially when increasing data rate, we explore a methodical way to design the asymmetric y-junction device by considering its angles and multiplexer/demultiplexer arm width. By taking into consideration device fabrication variations, we turn towards optimizing device performance post-fabrication. Through ModePROP simulations, optimizing device performance dynamically post-fabrication is analyzed, through either electro-optical or thermo-optical means. By biasing the arm introducing the slight spectral offset, we can quantifiably improve device performance. Scaling bandwidth is experimentally demonstrated through the device at 3 modes, 2 wavelengths, and 40 Gb/s data rate for 240 Gb/s aggregate bandwidth, with the potential to reduce power penalty per the device optimization process we described. A main motivation for this on-chip spatial multiplexing is the need to reduce costs. As the laser source serves as the greatest power consumer in an optical system, mode-division multiplexing and other forms of spatial multiplexing can be implemented to push its potentially prohibitive cost metrics down. In order to demonstrate an intelligent platform capable of dynamically multicasting data and reallocating power as needed by the system, we must first initialize the switch fabric to control with an electronic interface. A dithering mechanism, whereby exact cross, bar, and sub-percentage states are enforced through the device, is described here. Such a method could be employed for actuating the device table of bias values to states automatically. We then employ a dynamic power reallocation algorithm through a data acquisition unit, showing real-time channel recovery for channels experiencing power loss by diverting power from paths that could tolerate it. The data that is being multicast through the system is experimentally shown to be error-free at 40 Gb/s data rate, when transmitting from one to three clients and going from automatic bar/cross states to equalized power distribution. For the last portion of this topic, the switch fabric was inserted into a high-performance computing system. In order to run benchmarks at 10 Gb/s data ontop of the switch fabric, a newer model of the control plane was implemented to toggle states according to the command issued by the server. Such a programmable mechanism will prove necessary in future implementations of optical subsystems embedded inside larger systems, like data centers. Beyond the specific control plane demonstrated, the idea of an intelligent photonic layer can be applied to alleviate many kinds of optical channel abnormalities or accommodate for switching based on different patterns in data transmission. Finally, the experimental demonstration of a coherent perfect absorption Si modulator is exhibited, showing a viable extinction ratio of 24.5 dB. Using this coherent perfect absorption mechanism to demodulate signals, there is the added benefit of differential reception. Currently, an automated process for data collection is employed at a faster time scale than instabilities present in fibers in the setup with future implementations eliminating the off-chip phase modulator for greater signal stability. The field of SiPh has developed to a stage where specific application domains can take off and compete according to industrial-level standards. The work in this dissertation contributes to experimental demonstration of a newly developing area of mode-division multiplexing for substantially increasing bandwidth on-chip. While implementing the discussed photonic devices in dynamic systems, various attributes of integrated photonics are leveraged with existing electronic technologies. Future generations of computing systems should then be designed by implementing both system and device level considerations. (Abstract shortened by ProQuest.).

Subwavelength engineered fiber-to-chip silicon-on-sapphire interconnects for mid-infrared applications (Conference Presentation)

NASA Astrophysics Data System (ADS)

Alonso-Ramos, Carlos; Han, Zhaohong; Le Roux, Xavier; Lin, Hongtao; Singh, Vivek; Lin, Pao Tai; Tan, Dawn; Cassan, Eric; Marris-Morini, Delphine; Vivien, Laurent; Wada, Kazumi; Hu, Juejun; Agarwal, Anuradha; Kimerling, Lionel C.

2016-05-01

The mid-Infrared wavelength range (2-20 µm), so-called fingerprint region, contains the very sharp vibrational and rotational resonances of many chemical and biological substances. Thereby, on-chip absorption-spectrometry-based sensors operating in the mid-Infrared (mid-IR) have the potential to perform high-precision, label-free, real-time detection of multiple target molecules within a single sensor, which makes them an ideal technology for the implementation of lab-on-a-chip devices. Benefiting from the great development realized in the telecom field, silicon photonics is poised to deliver ultra-compact efficient and cost-effective devices fabricated at mass scale. In addition, Si is transparent up to 8 µm wavelength, making it an ideal material for the implementation of high-performance mid-IR photonic circuits. The silicon-on-insulator (SOI) technology, typically used in telecom applications, relies on silicon dioxide as bottom insulator. Unfortunately, silicon dioxide absorbs light beyond 3.6 µm, limiting the usability range of the SOI platform for the mid-IR. Silicon-on-sapphire (SOS) has been proposed as an alternative solution that extends the operability region up to 6 µm (sapphire absorption), while providing a high-index contrast. In this context, surface grating couplers have been proved as an efficient means of injecting and extracting light from mid-IR SOS circuits that obviate the need of cleaving sapphire. However, grating couplers typically have a reduced bandwidth, compared with facet coupling solutions such as inverse or sub-wavelength tapers. This feature limits their feasibility for absorption spectroscopy applications that may require monitoring wide wavelength ranges. Interestingly, sub-wavelength engineering can be used to substantially improve grating coupler bandwidth, as demonstrated in devices operating at telecom wavelengths. Here, we report on the development of fiber-to-chip interconnects to ZrF4 optical fibers and integrated SOS circuits with 500 nm thick Si, operating around 3.8 µm wavelength. Results on facet coupling and sub-wavelength engineered grating coupler solutions in the mid-IR regime will be compared.

Programmable single-cell mammalian biocomputers.

PubMed

Ausländer, Simon; Ausländer, David; Müller, Marius; Wieland, Markus; Fussenegger, Martin

2012-07-05

Synthetic biology has advanced the design of standardized control devices that program cellular functions and metabolic activities in living organisms. Rational interconnection of these synthetic switches resulted in increasingly complex designer networks that execute input-triggered genetic instructions with precision, robustness and computational logic reminiscent of electronic circuits. Using trigger-controlled transcription factors, which independently control gene expression, and RNA-binding proteins that inhibit the translation of transcripts harbouring specific RNA target motifs, we have designed a set of synthetic transcription–translation control devices that could be rewired in a plug-and-play manner. Here we show that these combinatorial circuits integrated a two-molecule input and performed digital computations with NOT, AND, NAND and N-IMPLY expression logic in single mammalian cells. Functional interconnection of two N-IMPLY variants resulted in bitwise intracellular XOR operations, and a combinatorial arrangement of three logic gates enabled independent cells to perform programmable half-subtractor and half-adder calculations. Individual mammalian cells capable of executing basic molecular arithmetic functions isolated or coordinated to metabolic activities in a predictable, precise and robust manner may provide new treatment strategies and bio-electronic interfaces in future gene-based and cell-based therapies.

A clocked high-pass-filter-based offset cancellation technique for high-gain biomedical amplifiers

NASA Astrophysics Data System (ADS)

Pal, Dipankar; Goswami, Manish

2010-05-01

In this article, a simple offset cancellation technique based on a clocked high-pass filter with extremely low output offset is presented. The configuration uses the on-resistance of a complementary metal oxide semiconductor (CMOS) transmission gate (X-gate) and tunes the lower 3-dB cut-off frequency with a matched pair of floating capacitors. The results compare favourably with the more complex auto-zeroing and chopper stabilisation techniques of offset cancellation in terms of power dissipation, component count and bandwidth, while reporting inferior output noise performance. The design is suitable for use in biomedical amplifier systems for applications such as ENG-recording. The system is simulated in Spectre Cadence 5.1.41 using 0.6 μm CMOS technology and the total block gain is ∼83.0 dB while the phase error is <5°. The power consumption is 10.2 mW and the output offset obtained for an input monotone signal of 5 μVpp is 1.28 μV. The input-referred root mean square noise voltage between 1 and 5 kHz is 26.32 nV/√Hz.

Design of frequency-encoded data-based optical master-slave-JK flip-flop using polarization switch

NASA Astrophysics Data System (ADS)

Mandal, Sumana; Mandal, Dhoumendra; Mandal, Mrinal Kanti; Garai, Sisir Kumar

2017-06-01

An optical data processing and communication system provides enormous potential bandwidth and a very high processing speed, and it can fulfill the demands of the present generation. For an optical computing system, several data processing units that work in the optical domain are essential. Memory elements are undoubtedly essential to storing any information. Optical flip-flops can store one bit of optical information. From these flip-flop registers, counters can be developed. Here, the authors proposed an optical master-slave (MS)-JK flip-flop with the help of two-input and three-input optical NAND gates. Optical NAND gates have been developed using semiconductor optical amplifiers (SOAs). The nonlinear polarization switching property of an SOA has been exploited here, and it acts as a polarization switch in the proposed scheme. A frequency encoding technique is adopted for representing data. A specific frequency of an optical signal represents a binary data bit. This technique of data representation is helpful because frequency is the fundamental property of a signal, and it remains unaltered during reflection, refraction, absorption, etc. throughout the data propagation. The simulated results enhance the admissibility of the scheme.

Graphene-based active slow surface plasmon polaritons

PubMed Central

Lu, Hua; Zeng, Chao; Zhang, Qiming; Liu, Xueming; Hossain, Md Muntasir; Reineck, Philipp; Gu, Min

2015-01-01

Finding new ways to control and slow down the group velocity of light in media remains a major challenge in the field of optics. For the design of plasmonic slow light structures, graphene represents an attractive alternative to metals due to its strong field confinement, comparably low ohmic loss and versatile tunability. Here we propose a novel nanostructure consisting of a monolayer graphene on a silicon based graded grating structure. An external gate voltage is applied to graphene and silicon, which are separated by a spacer layer of silica. Theoretical and numerical results demonstrate that the structure exhibits an ultra-high slowdown factor above 450 for the propagation of surface plasmon polaritons (SPPs) excited in graphene, which also enables the spatially resolved trapping of light. Slowdown and trapping occur in the mid-infrared wavelength region within a bandwidth of ~2.1 μm and on a length scale less than 1/6 of the operating wavelength. The slowdown factor can be precisely tuned simply by adjusting the external gate voltage, offering a dynamic pathway for the release of trapped SPPs at room temperature. The presented results will enable the development of highly tunable optoelectronic devices such as plasmonic switches and buffers. PMID:25676462

Silicon photonics for high-performance interconnection networks

NASA Astrophysics Data System (ADS)

Biberman, Aleksandr

2011-12-01

We assert in the course of this work that silicon photonics has the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems, and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. This work showcases that chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, enable unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of this work, we demonstrate such feasibility of waveguides, modulators, switches, and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. Furthermore, we leverage the unique properties of available silicon photonic materials to create novel silicon photonic devices, subsystems, network topologies, and architectures to enable unprecedented performance of these photonic interconnection networks and computing systems. We show that the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers. Furthermore, we explore the immense potential of all-optical functionalities implemented using parametric processing in the silicon platform, demonstrating unique methods that have the ability to revolutionize computation and communication. Silicon photonics enables new sets of opportunities that we can leverage for performance gains, as well as new sets of challenges that we must solve. Leveraging its inherent compatibility with standard fabrication techniques of the semiconductor industry, combined with its capability of dense integration with advanced microelectronics, silicon photonics also offers a clear path toward commercialization through low-cost mass-volume production. Combining empirical validations of feasibility, demonstrations of massive performance gains in large-scale systems, and the potential for commercial penetration of silicon photonics, the impact of this work will become evident in the many decades that follow.

Fabrication of a novel gigabit/second free-space optical interconnect - photodetector characterization and testing and system development

NASA Technical Reports Server (NTRS)

Savich, Gregory R.

2004-01-01

The time when computing power is limited by the copper wire inherent in the computer system and not the speed of the microprocessor is rapidly approaching. With constant advances in computer technology, many researchers believe that in only a few years, optical interconnects will begin to replace copper wires in your Central Processing Unit (CPU). On a more macroscopic scale, the telecommunications industry has already made the switch to optical data transmission as, to date, fiber optic technology is the only reasonable method of reliable, long range data transmission. Within the span of a decade, we will see optical technologies move from the macroscopic world of the telecommunications industry to the microscopic world of the computer chip. Already, the communications industry is marketing commercially available optical links to connect two personal computers, thereby eliminating the need for standard and comparatively slow wired and wireless Ethernet transfers and greatly increasing the distance the computers can be separated. As processing demands continue to increase, the realm of optical communications will continue to move closer to the microprocessor and quite possibly onto the microprocessor itself. A day may come when copper connections are used only to supply power, not transfer data. This summer s work marks some of the beginning stages of a 5 to 10 year, long-term research project to create and study a free-space, 1 Gigabit/sec optical interconnect. The research will result in a novel fabricated, chip-to-chip interconnect consisting of a Vertical Cavity Surface Emitting Laser (VCSEL) Diode linked through free space to a Metal- Semiconductor-Metal (MSM) Photodetector with the possible integration of microlenses for signal focusing and Micro-Electromechanical Systems (MEMS) devices for optical signal steering. The advantages, disadvantages, and practicality of incorporating flip-chip mounting technologies will also be addressed. My work began with the design and construction of a test setup for the experiment and then appropriate characterization of the test system. Specifically, I am involved in the characterization of a commercially available 1550nm wavelength, 5mW diode laser and a study of its modulation bandwidth. Commercially produced photodetectors as well as the incorporation of microwave technology, in the form of RF input and output, are used in the characterization procedure. The next stage involves the use of a probe station and network analyzer to characterize and test a series of photodetectors fabricated on a 2 inch, Indium Gallium Arsenide (InGaAs) wafer in the Branch s microlithography lab. Other project responsibilities include, but are not limited to the incorporation of a transimpedance amplifier to the photodetector circuit; a study of VCSEL technology; bit error rate analysis of an optical interconnect system; and analysis of free space divergence of the VCSEL, optical path length of the interconnect; and any other pertinent optical properties of the one gigabit per second interconnect for fabrication and testing.

A wideband analog correlator system for AMiBA

NASA Astrophysics Data System (ADS)

Li, Chao-Te; Kubo, Derek; Han, Chih-Chiang; Chen, Chung-Cheng; Chen, Ming-Tang; Lien, Chun-Hsien; Wang, Huei; Wei, Ray-Ming; Yang, Chia-Hsiang; Chiueh, Tzi-Dar; Peterson, Jeffrey; Kesteven, Michael; Wilson, Warwick

2004-10-01

A wideband correlator system with a bandwidth of 16 GHz or more is required for Array for Microwave Background Anisotropy (AMiBA) to achieve the sensitivity of 10μK in one hour of observation. Double-balanced diode mixers were used as multipliers in 4-lag correlator modules. Several wideband modules were developed for IF signal distribution between receivers and correlators. Correlator outputs were amplified, and digitized by voltage-to-frequency converters. Data acquisition circuits were designed using field programmable gate arrays (FPGA). Subsequent data transfer and control software were based on the configuration for Australia Telescope Compact Array. Transform matrix method will be adopted during calibration to take into account the phase and amplitude variations of analog devices across the passband.

Splash 2

NASA Technical Reports Server (NTRS)

Arnold, Jeffrey M.; Buell, Duncan A.; Kleinfelder, Walter J.

1993-01-01

Splash 2 is an attached processor system for Sun SPARC 2 workstations that uses Xilinx 4010 Field Programmable Gate Arrays (FPGA's) as its processing elements. The purpose of this paper is to describe Splash 2. The predecessor system, Splash 1, was designed to be used as a systolic processing system. Although it was very successful in that mode, there were many other applications that were not systolic, but which were successful, nonetheless, on Splash 1, or that were not implemented successfully due to one or more architectural limitations, most notably I/O bandwidth and interprocessor communication. Although other uses to increase computational performance have been found for the Xilinx FPGA's that are Splash's processing elements. Splash is unique in its goal to be programmable in a general sense.

Thomson Scattering Diagnostic Data Acquisition Systems for Modern Fusion Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ivanenko, S.V.; Khilchenko, A.D.; Ovchar, V.K.

2015-07-01

Uniquely designed complex data acquisition system for Thomson scattering diagnostic was developed. It allows recording short duration (3-5 ns) scattered pulses with 2 GHz sampling rate and 10-bit total resolution in oscilloscope mode. The system consists up to 48 photo detector modules with 0- 200 MHz bandwidth, 1-48 simultaneously sampling ADC modules and synchronization subsystem. The photo detector modules are based on avalanche photodiodes (APD) and ultra-low noise trans-impedance amplifiers. ADC modules include fast analog to digital converters and digital units based on the FPGA (Field- Programmable Gate Array) for data processing and storage. The synchronization subsystem is used tomore » form triggering pulses and to organize the simultaneously mode of ADC modules operation. (authors)« less

2D array transducers for real-time 3D ultrasound guidance of interventional devices

NASA Astrophysics Data System (ADS)

Light, Edward D.; Smith, Stephen W.

2009-02-01

We describe catheter ring arrays for real-time 3D ultrasound guidance of devices such as vascular grafts, heart valves and vena cava filters. We have constructed several prototypes operating at 5 MHz and consisting of 54 elements using the W.L. Gore & Associates, Inc. micro-miniature ribbon cables. We have recently constructed a new transducer using a braided wiring technology from Precision Interconnect. This transducer consists of 54 elements at 4.8 MHz with pitch of 0.20 mm and typical -6 dB bandwidth of 22%. In all cases, the transducer and wiring assembly were integrated with an 11 French catheter of a Cook Medical deployment device for vena cava filters. Preliminary in vivo and in vitro testing is ongoing including simultaneous 3D ultrasound and x-ray fluoroscopy.

Low-Power Light Guiding and Localization in Optoplasmonic Chains Obtained by Directed Self-Assembly

PubMed Central

Ahn, Wonmi; Zhao, Xin; Hong, Yan; Reinhard, Björn M.

2016-01-01

Optoplasmonic structures contain plasmonic components embedded in a defined photonic environment to create synergistic interactions between photonic and plasmonic components. Here, we show that chains of optical microspheres containing gold nanoparticles in their evanescent field combine the light guiding properties of a microsphere chain with the light localizing properties of a plasmonic nanoantenna. We implement these materials through template guided self-assembly and investigate their fundamental electromagnetic working principles through combination of electromagnetic simulations and experimental characterization. We demonstrate that optoplasmonic chains implemented by directed self-assembly achieve a significant reduction in guiding losses when compared with conventional plasmonic waveguides and, at the same time, retain the light localizing properties of plasmonic antennas at pre-defined locations. The results reinforce the potential of optoplasmonic structures for realizing low-loss optical interconnects with high bandwidth. PMID:26931149

1060-nm VCSEL-based parallel-optical modules for optical interconnects

NASA Astrophysics Data System (ADS)

Nishimura, N.; Nagashima, K.; Kise, T.; Rizky, A. F.; Uemura, T.; Nekado, Y.; Ishikawa, Y.; Nasu, H.

2015-03-01

The capability of mounting a parallel-optical module onto a PCB through solder-reflow process contributes to reduce the number of piece parts, simplify its assembly process, and minimize a foot print for both AOC and on-board applications. We introduce solder-reflow-capable parallel-optical modules employing 1060-nm InGaAs/GaAs VCSEL which leads to the advantages of realizing wider modulation bandwidth, longer transmission distance, and higher reliability. We demonstrate 4-channel parallel optical link performance operated at a bit stream of 28 Gb/s 231-1 PRBS for each channel and transmitted through a 50-μm-core MMF beyond 500 m. We also introduce a new mounting technology of paralleloptical module to realize maintaining good coupling and robust electrical connection during solder-reflow process between an optical module and a polymer-waveguide-embedded PCB.

Programmable on-chip and off-chip network architecture on demand for flexible optical intra-datacenters.

PubMed

Rofoee, Bijan Rahimzadeh; Zervas, Georgios; Yan, Yan; Amaya, Norberto; Qin, Yixuan; Simeonidou, Dimitra

2013-03-11

The paper presents a novel network architecture on demand approach using on-chip and-off chip implementations, enabling programmable, highly efficient and transparent networking, well suited for intra-datacenter communications. The implemented FPGA-based adaptable line-card with on-chip design along with an architecture on demand (AoD) based off-chip flexible switching node, deliver single chip dual L2-Packet/L1-time shared optical network (TSON) server Network Interface Cards (NIC) interconnected through transparent AoD based switch. It enables hitless adaptation between Ethernet over wavelength switched network (EoWSON), and TSON based sub-wavelength switching, providing flexible bitrates, while meeting strict bandwidth, QoS requirements. The on and off-chip performance results show high throughput (9.86Ethernet, 8.68Gbps TSON), high QoS, as well as hitless switch-over.

Optical interconnects for in-plane high-speed signal distribution at 10 Gb/s: Analysis and demonstration

NASA Astrophysics Data System (ADS)

Chang, Yin-Jung

With decreasing transistor size, increasing chip speed, and larger numbers of processors in a system, the performance of a module/system is being limited by the off-chip and off-module bandwidth-distance products. Optical links have moved from fiber-based long distance communications to the cabinet level of 1m--100m, and recently to the backplane-level (10cm--1m). Board-level inter-chip parallel optical interconnects have been demonstrated recently by researchers from Intel, IBM, Fujitsu, NTT and a few research groups in universities. However, the board-level signal/clock distribution function using optical interconnects, the lightwave circuits, the system design, a practically convenient integration scheme committed to the implementation of a system prototype have not been explored or carefully investigated. In this dissertation, the development of a board-level 1 x 4 optical-to-electrical signal distribution at 10Gb/s is presented. In contrast to other prototypes demonstrating board-level parallel optical interconnects that have been drawing much attention for the past decade, the optical link design for the high-speed signal broadcasting is even more complicated and the pitch between receivers could be varying as opposed to fixed-pitch design that has been widely-used in the parallel optical interconnects. New challenges for the board-level high-speed signal broadcasting include, but are not limited to, a new optical link design, a lightwave circuit as a distribution network, and a novel integration scheme that can be a complete radical departure from the traditional assembly method. One of the key building blocks in the lightwave circuit is the distribution network in which a 1 x 4 multimode interference (MMI) splitter is employed. MMI devices operating at high data rates are important in board-level optical interconnects and need to be characterized in the application of board-level signal broadcasting. To determine the speed limitations of MMI devices, the ultra-short pulse response of these devices is modeled based on the guided-mode theory incorporated with Fourier transform technique. For example, for 50 fs Gaussian input pulses into a 1 x 16 splitter, the output pulses are severely degraded in coupling efficiency (48%) and completely broken up in time primarily due to inter-modal and intra-modal (waveguide) dispersion. Material dispersion is found to play only a minor role in the pulse response of MMI devices. However, for 1ps input pulses into the same 1 x 16 splitter, the output pulses are only moderately degraded in coupling efficiency (86%) and only slightly degraded in shape. With the understanding of the necessary condition of the distortionless high-speed signal transmission through MMI devices, high-speed data transmission at 40Gb/s per channel with a total bandwidth of 320Gb/s for 8 output ports is demonstrated for the first time on a 1 x 8 photo-definable polymer-based MMI power splitter. The device is designed with multimode input/output waveguides of 10mum in width and 7.6mum in height for a better input coupling efficiency for which the high-speed testing demands. The eye diagrams are all clear and fully open with an extinction ratio of 10.1dB and a jitter of 1.65 ps. The transmission validity is further confirmed by the bit-error-rate testing at the pseudoramdom binary sequence of 27--1. The fabrication process developed lays the cornerstone of the integration scheme and system design for the prototype of hybrid interconnects. An important problem regarding the guided-mode attenuation associated with optical-interconnect-polymer waveguides fabricated on FR-4 printed-circuit boards is also quantified for the first time. On-board optical waveguides are receiving more attention recently from Fujitsu American Laboratory, IBM Watson Research Center, and Packaging Research Center here at Georgia Tech. This branch of research work is part of the effort in investigating, scientifically, the attenuation mechanism and the effects of the buffer layer thickness on board-level in-plane optical interconnects. The rigorous transmission-line network approach is used and the FR-4 substrate is treated as a long-period substrate grating. A quantitative metric for an appropriate matrix truncation is presented. The peaks of attenuation are shown to occur near the Bragg conditions that characterize the leaky-wave stop bands. For a typical 400mum period FR-4 substrate with an 8mum corrugation depth, a buffer layer thickness of about 40mum is found to be needed to make the attenuation negligibly small. An experimental prototype for on-board optical-to-electrical signal broadcasting operating at 10Gb/s per channel over an interconnect distance of 10cm is demonstrated. An improved 1 x 4 multimode interference (MMI) splitter at 1550nm with linearly-tapered output facet is heterogeneously integrated with four p-i-n photodetectors (PDs) on a Silicon (Si) bench. The Si bench itself is hybrid integrated onto an FR-4 printed-circuit board with four receiver channels. A novel fabrication/integration approach demonstrates the simultaneous alignment between the four waveguides and the four PDs during the MMI fabrication process. The entire system is fully functional at 10Gb/s.

Micromachined High Frequency PMN-PT/Epoxy 1-3 Composite Ultrasonic Annular Array

PubMed Central

Liu, Changgeng; Djuth, Frank; Li, Xiang; Chen, Ruimin; Zhou, Qifa; Shung, K. Kirk

2013-01-01

This paper reports the design, fabrication, and performance of miniature micromachined high frequency PMN-PT/epoxy 1-3 composite ultrasonic annular arrays. The PMN-PT single crystal 1-3 composites were made with micromachining techniques. The area of a single crystal pillar was 9 μm × 9 μm. The width of the kerf among pillars was ~ 5 μm and the kerfs were filled with a polymer. The composite thickness was 25 μm. A six-element annular transducer of equal element area of 0.2 mm2 with 16 μm kerf widths between annuli was produced. The aperture size the array transducer is about 1.5 mm in diameter. A novel electrical interconnection strategy for high density array elements was implemented. After the transducer was attached to the electric connection board and packaged, the array transducer was tested in a pulse/echo arrangement, whereby the center frequency, bandwidth, two-way insertion loss (IL), and cross talk between adjacent elements were measured for each annulus. The center frequency was 50 MHz and -6 dB bandwidth was 90%. The average insertion loss was 19.5 dB at 50 MHz and the crosstalk between adjacent elements was about -35 dB. The micromachining techniques described in this paper are promising for the fabrication of other types of high frequency transducers e.g. 1D and 2D arrays. PMID:22119324

Blueprint for a microwave trapped ion quantum computer.

PubMed

Lekitsch, Bjoern; Weidt, Sebastian; Fowler, Austin G; Mølmer, Klaus; Devitt, Simon J; Wunderlich, Christof; Hensinger, Winfried K

2017-02-01

The availability of a universal quantum computer may have a fundamental impact on a vast number of research fields and on society as a whole. An increasingly large scientific and industrial community is working toward the realization of such a device. An arbitrarily large quantum computer may best be constructed using a modular approach. We present a blueprint for a trapped ion-based scalable quantum computer module, making it possible to create a scalable quantum computer architecture based on long-wavelength radiation quantum gates. The modules control all operations as stand-alone units, are constructed using silicon microfabrication techniques, and are within reach of current technology. To perform the required quantum computations, the modules make use of long-wavelength radiation-based quantum gate technology. To scale this microwave quantum computer architecture to a large size, we present a fully scalable design that makes use of ion transport between different modules, thereby allowing arbitrarily many modules to be connected to construct a large-scale device. A high error-threshold surface error correction code can be implemented in the proposed architecture to execute fault-tolerant operations. With appropriate adjustments, the proposed modules are also suitable for alternative trapped ion quantum computer architectures, such as schemes using photonic interconnects.

Development of a multi-degree-of-freedom micropositioning, vibration isolation and vibration suppression system

NASA Astrophysics Data System (ADS)

Jaensch, M.; Lampérth, M. U.

2007-04-01

This paper describes the design and performance testing of a micropositioning, vibration isolation and suppression system, which can be used to position a piece of equipment with sub-micrometre accuracy and stabilize it against various types of external disturbance. The presented demonstrator was designed as part of a novel extremely open pre-polarization magnetic resonance imaging (MRI) scanner. The active control system utilizes six piezoelectric actuators, wide-bandwidth optical fibre displacement sensors and a very fast digital field programmable gate array (FPGA) controller. A PID feedback control algorithm with emphasis on a very high level of integral gain is employed. Due to the high external forces expected, the whole structure is designed to be as stiff as possible, including a novel hard mount approach with parallel passive damping for the suspension of the payload. The performance of the system is studied theoretically and experimentally. The sensitive equipment can be positioned in six degrees of freedom with an accuracy of ± 0.2 µm. External disturbances acting on the support structure or the equipment itself are attenuated in three degrees of freedom by more than -20 dB within a bandwidth of 0-200 Hz. Excellent impulse rejection and input tracking are demonstrated as well.

Optical wireless communications to OC-768 and beyond

NASA Astrophysics Data System (ADS)

Medved, David B.; Davidovich, Leonid

2001-10-01

Laser and LED-based wireless communication systems are currently providing license-free interconnection for broadband voice, data and video transport. These systems allow for the immediate, reliable and low-cost extension of copper and fiber-based networks to any end user, providing efficient First Mile bypass access to high data rate backbone networks at speeds ranging from T-1 voice to full throughput ATM at 155 Mbps and up to Gigabit Ethernet. These wireless optical beams constitute a Virtual Fiber in the air, providing the capabilities of fiber in situations where wired connectivity is unavailable, impractical, expensive or slow-to-implement, while achieving a combination of low cost, speed and reliability that cannot be matched by microwave, mm wave, spread spectrum or other competing (actually complementary) wireless technologies. The carrier frequency of the optical beam is about 10,000 times higher than the highest frequencies used by the millimeter wave technology. By means of Wavelength Division Multiplexing more than 1000 independent data channels can be projected into the air on a single beam thus providing a potential bandwidth ten million times that of any RF solution. The twin barriers of physics and regulatory bureaucracy to this essentially infinite wireless bandwidth are thus eliminated by this Virtual Fiber. As user density and individual bandwidth needs escalate, the optical wireless will be the preferred medium of choice in both network and cellular interconnection. A mesh topology which integrates our optical wireless systems with the latest Optical Access switches and routing equipment will be described using case study examples from Japan to South America. As the Bandwidth Blowout continues to push the limits of electronics and especially in the case of DWDM (Dense Wavelength Division Multiples), the conventional optical wireless solutions are no longer feasible. Instead of using f.o. transceivers to convert photons to electrons and thence back to photons we have designed a series of airlinks whose transmitters and receivers operate without electronics. At the PATX (Photonic Airlink Transmitter), instead of demodulating the fiber optic input signals from a Network Interface Unit (NIU) we project the light from the polished terminated fiber end into the air using appropriate optics. Any signal being carried by the fiber from the NIU is now airborne without any intermediate processing electronics thus realizing the full potential of the optical carrier. At the receiver end (PARX - Photonic Airlink Receiver), the weak optical signals are collected by the appropriate optics (including combiners using large area MMF) and guided to the NIU (switch, PABX, etc.) by compatible fiber. It is necessary to maintain a large field-of-view at the receiver to ensure reliability, stability and ease of alignment. This is achieved by use of high N.A. fiber. In this paper we discuss the design trade off's, construction and field test results of several systems implementing the all- photonic wireless concept including: Transmission of WDM signals through the air at distances up to 1 km. Results with wireless transmission of Gigabit Ethernet using the Optiswitch modules as the NIU. Providing high speed wireless (Fast Ethernet and beyond) to the home at a cost of less than $250 per node. The paper will conclude with a discussion on the role of the all-photonic wireless technology in the emerging field of Passive Optical Networking.

A wide range real-time synchronous demodulation system for the dispersion interferometer on HL-2M

NASA Astrophysics Data System (ADS)

Wu, Tongyu; Zhang, Wei; Yin, Zejie

2017-09-01

A real-time synchronous demodulation system has been developed for the dispersion interferometer on a HL-2M tokamak. The system is based on the phase extraction method which uses a ratio of modulation amplitudes. A high-performance field programmable gate array with pipeline process capabilities is used to realize the real time synchronous demodulation algorithm. A fringe jump correction algorithm is applied to follow the fast density changes of the plasma. By using the Peripheral Component Interconnect Express protocol, the electronics can perform real-time density feedback with a temporal resolution of 100 ns. Some experimental results presented show that the electronics can obtain a wide measurement range of 2.28 × 1022 m-2 with high precision.

Design and implementation of GaAs HBT circuits with ACME

NASA Technical Reports Server (NTRS)

Hutchings, Brad L.; Carter, Tony M.

1993-01-01

GaAs HBT circuits offer high performance (5-20 GHz) and radiation hardness (500 Mrad) that is attractive for space applications. ACME is a CAD tool specifically developed for HBT circuits. ACME implements a novel physical schematic-capture design technique where designers simultaneously view the structure and physical organization of a circuit. ACME's design interface is similar to schematic capture; however, unlike conventional schematic capture, designers can directly control the physical placement of both function and interconnect at the schematic level. In addition, ACME provides design-time parasitic extraction, complex wire models, and extensions to Multi-Chip Modules (MCM's). A GaAs HBT gate-array and semi-custom circuits have been developed with ACME; several circuits have been fabricated and found to be fully functional .

Generation of isolated attosecond pulses with enhancement cavities—a theoretical study

NASA Astrophysics Data System (ADS)

Högner, M.; Tosa, V.; Pupeza, I.

2017-03-01

The generation of extreme-ultraviolet (XUV) isolated attosecond pulses (IAPs) has enabled experimental access to the fastest phenomena in nature observed so far, namely the dynamics of electrons in atoms, molecules and solids. However, nowadays the highest repetition rates at which IAPs can be generated lies in the {kHz} range. This represents a rather severe restriction for numerous experiments involving the detection of charged particles, where the desired number of generated particles per shot is limited by space charge effects to ideally one. Here, we present a theoretical study on the possibility of efficiently producing IAPs at multi-{MHz} repetition rates via cavity-enhanced high-harmonic generation (HHG). To this end, we assume parameters of state-of-the-art Yb-based femtosecond laser technology to evaluate several time-gating methods which could generate IAPs in enhancement cavities. We identify polarization gating and a new method, employing non-collinear optical gating in a tailored transverse cavity mode, as suitable candidates and analyze these via extensive numerical modeling. The latter, which we dub transverse mode gating (TMG) promises the highest efficiency and robustness. Assuming 0.7 μ {{J}}, 5-cycle pulses from the seeding laser and a state-of-the-art enhancement cavity, we show that TMG bares the potential to generate IAPs with photon energies around 100 {eV} and a photon flux of at least {10}8 {photons} {{{s}}}-1 at repetition rates of 10 {MHz} and higher. This result reveals a roadmap towards a dramatic decrease in measurement time (and, equivalently, an increase in the signal-to-noise ratio) in photoelectron spectroscopy and microscopy. In particular, it paves the way to combining attosecond streaking with photoelectron emission microscopy, affording, for the first time, the spatially and temporally resolved observation of plasmonic fields in nanostructures. Furthermore, it promises the generation of frequency combs with an unprecedented bandwidth for XUV precision spectroscopy.

Flexible, Photopatterned, Colloidal CdSe Semiconductor Nanocrystal Integrated Circuits

NASA Astrophysics Data System (ADS)

Stinner, F. Scott

As semiconductor manufacturing pushes towards smaller and faster transistors, a parallel goal exists to create transistors which are not nearly as small. These transistors are not intended to match the performance of traditional crystalline semiconductors; they are designed to be significantly lower in cost and manufactured using methods that can make them physically flexible for applications where form is more important than speed. One of the developing technologies for this application is semiconductor nanocrystals. We first explore methods to develop CdSe nanocrystal semiconducting "inks" into large-scale, high-speed integrated circuits. We demonstrate photopatterned transistors with mobilities of 10 cm2/Vs on Kapton substrates. We develop new methods for vertical interconnect access holes to demonstrate multi-device integrated circuits including inverting amplifiers with 7 kHz bandwidths, ring oscillators with <10 micros stage delays, and NAND and NOR logic gates. In order to produce higher performance and more consistent transistors, we develop a new hybrid procedure for processing the CdSe nanocrystals. This procedure produces transistors with repeatable performance exceeding 40 cm2/Vs when fabricated on silicon wafers and 16 cm 2/vs when fabricated as part of photopatterned integrated circuits on Kapton substrates. In order to demonstrate the full potential of these transistors, methods to create high-frequency oscillators were developed. These methods allow for transistors to operate at higher voltages as well as provide a means for wirebonding to the Kapton substrate, both of which are required for operating and probing high-frequency oscillators. Simulations of this system show the potential for operation at MHz frequencies. Demonstration of these transistors in this frequency range would open the door for development of CdSe integrated circuits for high-performance sensor, display, and audio applications. To develop further applications of electronics on flexible substrates, procedures are developed for the integration of polychromatic displays on polyethylene terephthalate (PET) substrates and a commercial near field communication (NFC) link. The device draws its power from the NFC transmitter common on smartphones and eliminates the need for a fixed battery. This allows for the mass deployment of flexible, interactive displays on product packaging.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lovell, Jack, E-mail: jack.lovell@durham.ac.uk; Culham Centre for Fusion Energy, Culham Science Centre, Abingdon, Oxon OX14 3DB; Naylor, Graham

A new resistive bolometer system has been developed for MAST-Upgrade. It will measure radiated power in the new Super-X divertor, with millisecond time resolution, along 16 vertical and 16 horizontal lines of sight. The system uses a Xilinx Zynq-7000 series Field-Programmable Gate Array (FPGA) in the D-TACQ ACQ2106 carrier to perform real time data acquisition and signal processing. The FPGA enables AC-synchronous detection using high performance digital filtering to achieve a high signal-to-noise ratio and will be able to output processed data in real time with millisecond latency. The system has been installed on 8 previously unused channels of themore » JET vertical bolometer system. Initial results suggest good agreement with data from existing vertical channels but with higher bandwidth and signal-to-noise ratio.« less

A stethoscope with wavelet separation of cardiac and respiratory sounds for real time telemedicine implemented on field-programmable gate array

NASA Astrophysics Data System (ADS)

Castro, Víctor M.; Muñoz, Nestor A.; Salazar, Antonio J.

2015-01-01

Auscultation is one of the most utilized physical examination procedures for listening to lung, heart and intestinal sounds during routine consults and emergencies. Heart and lung sounds overlap in the thorax. An algorithm was used to separate them based on the discrete wavelet transform with multi-resolution analysis, which decomposes the signal into approximations and details. The algorithm was implemented in software and in hardware to achieve real-time signal separation. The heart signal was found in detail eight and the lung signal in approximation six. The hardware was used to separate the signals with a delay of 256 ms. Sending wavelet decomposition data - instead of the separated full signa - allows telemedicine applications to function in real time over low-bandwidth communication channels.

Radioastronomic signal processing cores for the SKA radio telescope

NASA Astrophysics Data System (ADS)

Comorett, G.; Chiarucc, S.; Belli, C.

Modern radio telescopes require the processing of wideband signals, with sample rates from tens of MHz to tens of GHz, and are composed from hundreds up to a million of individual antennas. Digital signal processing of these signals include digital receivers (the digital equivalent of the heterodyne receiver), beamformers, channelizers, spectrometers. FPGAs present the advantage of providing a relatively low power consumption, relative to GPUs or dedicated computers, a wide signal data path, and high interconnectivity. Efficient algorithms have been developed for these applications. Here we will review some of the signal processing cores developed for the SKA telescope. The LFAA beamformer/channelizer architecture is based on an oversampling channelizer, where the channelizer output sampling rate and channel spacing can be set independently. This is useful where an overlap between adjacent channels is required to provide an uniform spectral coverage. The architecture allows for an efficient and distributed channelization scheme, with a final resolution corresponding to a million of spectral channels, minimum leakage and high out-of-band rejection. An optimized filter design procedure is used to provide an equiripple response with a very large number of spectral channels. A wideband digital receiver has been designed in order to select the processed bandwidth of the SKA Mid receiver. The receiver extracts a 2.5 MHz bandwidth form a 14 GHz input bandwidth. The design allows for non-integer ratios between the input and output sampling rates, with a resource usage comparable to that of a conventional decimating digital receiver. Finally, some considerations on quantization of radioastronomic signals are presented. Due to the stochastic nature of the signal, quantization using few data bits is possible. Good accuracies and dynamic range are possible even with 2-3 bits, but the nonlinearity in the correlation process must be corrected in post-processing. With at least 6 bits it is possible to have a very linear response of the instrument, with nonlinear terms below 80 dB, providing the signal amplitude is kept within bounds.

High-Performance, Multi-Node File Copies and Checksums for Clustered File Systems

NASA Technical Reports Server (NTRS)

Kolano, Paul Z.; Ciotti, Robert B.

2012-01-01

Modern parallel file systems achieve high performance using a variety of techniques, such as striping files across multiple disks to increase aggregate I/O bandwidth and spreading disks across multiple servers to increase aggregate interconnect bandwidth. To achieve peak performance from such systems, it is typically necessary to utilize multiple concurrent readers/writers from multiple systems to overcome various singlesystem limitations, such as number of processors and network bandwidth. The standard cp and md5sum tools of GNU coreutils found on every modern Unix/Linux system, however, utilize a single execution thread on a single CPU core of a single system, and hence cannot take full advantage of the increased performance of clustered file systems. Mcp and msum are drop-in replacements for the standard cp and md5sum programs that utilize multiple types of parallelism and other optimizations to achieve maximum copy and checksum performance on clustered file systems. Multi-threading is used to ensure that nodes are kept as busy as possible. Read/write parallelism allows individual operations of a single copy to be overlapped using asynchronous I/O. Multinode cooperation allows different nodes to take part in the same copy/checksum. Split-file processing allows multiple threads to operate concurrently on the same file. Finally, hash trees allow inherently serial checksums to be performed in parallel. Mcp and msum provide significant performance improvements over standard cp and md5sum using multiple types of parallelism and other optimizations. The total speed-ups from all improvements are significant. Mcp improves cp performance over 27x, msum improves md5sum performance almost 19x, and the combination of mcp and msum improves verified copies via cp and md5sum by almost 22x. These improvements come in the form of drop-in replacements for cp and md5sum, so are easily used and are available for download as open source software at http://mutil.sourceforge.net.

The DoD's High Performance Computing Modernization Program - Ensuing the National Earth Systems Prediction Capability Becomes Operational

NASA Astrophysics Data System (ADS)

Burnett, W.

2016-12-01

The Department of Defense's (DoD) High Performance Computing Modernization Program (HPCMP) provides high performance computing to address the most significant challenges in computational resources, software application support and nationwide research and engineering networks. Today, the HPCMP has a critical role in ensuring the National Earth System Prediction Capability (N-ESPC) achieves initial operational status in 2019. A 2015 study commissioned by the HPCMP found that N-ESPC computational requirements will exceed interconnect bandwidth capacity due to the additional load from data assimilation and passing connecting data between ensemble codes. Memory bandwidth and I/O bandwidth will continue to be significant bottlenecks for the Navy's Hybrid Coordinate Ocean Model (HYCOM) scalability - by far the major driver of computing resource requirements in the N-ESPC. The study also found that few of the N-ESPC model developers have detailed plans to ensure their respective codes scale through 2024. Three HPCMP initiatives are designed to directly address and support these issues: Productivity Enhancement, Technology, Transfer and Training (PETTT), the HPCMP Applications Software Initiative (HASI), and Frontier Projects. PETTT supports code conversion by providing assistance, expertise and training in scalable and high-end computing architectures. HASI addresses the continuing need for modern application software that executes effectively and efficiently on next-generation high-performance computers. Frontier Projects enable research and development that could not be achieved using typical HPCMP resources by providing multi-disciplinary teams access to exceptional amounts of high performance computing resources. Finally, the Navy's DoD Supercomputing Resource Center (DSRC) currently operates a 6 Petabyte system, of which Naval Oceanography receives 15% of operational computational system use, or approximately 1 Petabyte of the processing capability. The DSRC will provide the DoD with future computing assets to initially operate the N-ESPC in 2019. This talk will further describe how DoD's HPCMP will ensure N-ESPC becomes operational, efficiently and effectively, using next-generation high performance computing.

Low power laser driver design in 28nm CMOS for on-chip and chip-to-chip optical interconnect

NASA Astrophysics Data System (ADS)

Belfiore, Guido; Szilagyi, Laszlo; Henker, Ronny; Ellinger, Frank

2015-09-01

This paper discusses the challenges and the trade-offs in the design of laser drivers for very-short distance optical communications. A prototype integrated circuit is designed and fabricated in 28 nm super-low-power CMOS technology. The power consumption of the transmitter is 17.2 mW excluding the VCSEL that in our test has a DC power consumption of 10 mW. The active area of the driver is only 0.0045 mm2. The driver can achieve an error-free (BER < 10 -12) electrical data-rate of 25 Gbit/s using a pseudo random bit sequence of 27 -1. When the driver is connected to the VCSEL module an open optical eye is reported at 15 Gbit/s. In the tested bias point the VCSEL module has a measured bandwidth of 10.7 GHz.

Tropospheric scintillation prediction models for a high elevation angle based on measured data from a tropical region

NASA Astrophysics Data System (ADS)

Abdul Rahim, Nadirah Binti; Islam, Md. Rafiqul; J. S., Mandeep; Dao, Hassan; Bashir, Saad Osman

2013-12-01

The recent rapid evolution of new satellite services, including VSAT for internet access, LAN interconnection and multimedia applications, has triggered an increasing demand for bandwidth usage by satellite communications. However, these systems are susceptible to propagation effects that become significant as the frequency increases. Scintillation is the rapid signal fluctuation of the amplitude and phase of a radio wave, which is significant in tropical climates. This paper presents the analysis of the tropospheric scintillation data for satellite to Earth links at the Ku-band. Twelve months of data (January-December 2011) were collected and analyzed to evaluate the effect of tropospheric scintillation. Statistics were then further analyzed to inspect the seasonal, worst-month, diurnal and rain-induced scintillation effects. By employing the measured scintillation data, a modification of the Karasawa model for scintillation fades and enhancements is proposed based on data measured in Malaysia.

A Control of a Mono and Multi Scale Measurement of a Grid

NASA Astrophysics Data System (ADS)

Elloumi, Imene; Ravelomanana, Sahobimaholy; Jelliti, Manel; Sibilla, Michelle; Desprats, Thierry

The capacity to ensure the seamless mobility with the end-to-end Quality of Service (QoS) represents a vital criterion of success in the grid use. In this paper we hence posit a method of monitoring interconnection network of the grid (cluster, local grid and aggregate grids) in order to control its QoS. Such monitoring can guarantee a persistent control of the system state of health, a diagnostic and an optimization pertinent enough for better real time exploitation. A better exploitation is synonymous with identifying networking problems that affect the application domain. This can be carried out by control measurements as well as mono and multi scale for such metrics as: the bandwidth, CPU speed and load. The solution proposed, which is a management generic solution independently from the technologies, aims to automate human expertise and thereby more autonomy.

Substrate integrated waveguide (SIW) 3 dB coupler for K-Band applications

NASA Astrophysics Data System (ADS)

Khalid, Nurehansafwanah; Zuraidah Ibrahim, Siti; Wee, Fwen Hoon; Shazuani Mahmud, Farah

2017-11-01

This paper presented a designed coupler by using Rogers RO4003C with thickness (h) 0.508 mm and relative permittivity (ɛr) 3.55. The four port network coupler operates in K-band (18-27 GHz) and design by using substrate integrated waveguide (SIW) method. The reflection coefficient and isolation coefficient of propose Substrate Integrated Waveguide (SIW) coupler is below than -10 dB. Meanwhile the coupler requirements are phase shift 90° between coupled port and output. SIW are high performance broadband interconnects with excellent immunity to electromagnetic interference and suitable for use in microwave and communication electronics, as well as increase bandwidth systems. The designs of coupler are investigated using CST Microwave Studio simulation tool. This proposed couplers are varied from parameters that cover the frequency range (21 -24 GHz) and better performance of scattering (S-parameter).

Networking for large-scale science: infrastructure, provisioning, transport and application mapping

NASA Astrophysics Data System (ADS)

Rao, Nageswara S.; Carter, Steven M.; Wu, Qishi; Wing, William R.; Zhu, Mengxia; Mezzacappa, Anthony; Veeraraghavan, Malathi; Blondin, John M.

2005-01-01

Large-scale science computations and experiments require unprecedented network capabilities in the form of large bandwidth and dynamically stable connections to support data transfers, interactive visualizations, and monitoring and steering operations. A number of component technologies dealing with the infrastructure, provisioning, transport and application mappings must be developed and/or optimized to achieve these capabilities. We present a brief account of the following technologies that contribute toward achieving these network capabilities: (a) DOE UltraScienceNet and NSF CHEETAH network testbeds that provide on-demand and scheduled dedicated network connections; (b) experimental results on transport protocols that achieve close to 100% utilization on dedicated 1Gbps wide-area channels; (c) a scheme for optimally mapping a visualization pipeline onto a network to minimize the end-to-end delays; and (d) interconnect configuration and protocols that provides multiple Gbps flows from Cray X1 to external hosts.

Development of a 35-MHz piezo-composite ultrasound array for medical imaging.

PubMed

Cannata, Jonathan M; Williams, Jay A; Zhou, Qifa; Ritter, Timothy A; Shung, K Kirk

2006-01-01

This paper discusses the development of a 64-element 35-MHz composite ultrasonic array. This array was designed primarily for ocular imaging applications, and features 2-2 composite elements mechanically diced out of a fine-grain high-density Navy Type VI ceramic. Array elements were spaced at a 50-micron pitch, interconnected via a custom flexible circuit and matched to the 50-ohm system electronics via a 75-ohm transmission line coaxial cable. Elevation focusing was achieved using a cylindrically shaped epoxy lens. One functional 64-element array was fabricated and tested. Bandwidths averaging 55%, 23-dB insertion loss, and crosstalk less than -24 dB were measured. An image of a tungsten wire target phantom was acquired using a synthetic aperture reconstruction algorithm. The results from this imaging test demonstrate resolution exceeding 50 microm axially and 100 microm laterally.

On-chip photonic synapse.

PubMed

Cheng, Zengguang; Ríos, Carlos; Pernice, Wolfram H P; Wright, C David; Bhaskaran, Harish

2017-09-01

The search for new "neuromorphic computing" architectures that mimic the brain's approach to simultaneous processing and storage of information is intense. Because, in real brains, neuronal synapses outnumber neurons by many orders of magnitude, the realization of hardware devices mimicking the functionality of a synapse is a first and essential step in such a search. We report the development of such a hardware synapse, implemented entirely in the optical domain via a photonic integrated-circuit approach. Using purely optical means brings the benefits of ultrafast operation speed, virtually unlimited bandwidth, and no electrical interconnect power losses. Our synapse uses phase-change materials combined with integrated silicon nitride waveguides. Crucially, we can randomly set the synaptic weight simply by varying the number of optical pulses sent down the waveguide, delivering an incredibly simple yet powerful approach that heralds systems with a continuously variable synaptic plasticity resembling the true analog nature of biological synapses.

Thalamus and Language: What do we know from vascular and degenerative pathologies.

PubMed

Moretti, Rita; Caruso, Paola; Crisman, Elena; Gazzin, Silvia

2018-01-01

Language is a complex cognitive task that is essential in our daily life. For decades, researchers have tried to understand the different role of cortical and subcortical areas in cerebral language representations and language processing. Language-related cortical zones are richly interconnected with other cortical regions (particularly via myelinated fibre tracts), but they also participate in subcortical feedback loops within the basal ganglia (caudate nucleus and putamen) and thalamus. The most relevant thalamic functions are the control and adaptation of cortico-cortical connectivity and bandwidth for information exchange. Despite having the knowledge of thalamic and basal ganglionic involvement in linguistic operations, the specific functions of these subcortical structures remain rather controversial. The aim of this study is to better understand the role of thalamus in language network, exploring the functional configuration of basal network components. The language specificity of subcortical supporting activity and the associated clinical features in thalamic involvement are also highlighted.

Semiconductor nanomembrane-based sensors for high frequency pressure measurements

NASA Astrophysics Data System (ADS)

Ruan, Hang; Kang, Yuhong; Homer, Michelle; Claus, Richard O.; Mayo, David; Sibold, Ridge; Jones, Tyler; Ng, Wing

2017-04-01

This paper demonstrates improvements on semiconductor nanomembrane based high frequency pressure sensors that utilize silicon on insulator techniques in combination with nanocomposite materials. The low-modulus, conformal nanomembrane sensor skins with integrated interconnect elements and electronic devices could be applied to vehicles or wind tunnel models for full spectrum pressure analysis. Experimental data demonstrates that: 1) silicon nanomembrane may be used as single pressure sensor transducers and elements in sensor arrays, 2) the arrays may be instrumented to map pressure over the surfaces of test articles over a range of Reynolds numbers, temperature and other environmental conditions, 3) in the high frequency range, the sensor is comparable to the commercial high frequency sensor, and 4) in the low frequency range, the sensor is much better than the commercial sensor. This supports the claim that nanomembrane pressure sensors may be used for wide bandwidth flow analysis.

The European project Merlin on multi-gigabit, energy-efficient, ruggedized lightwave engines for advanced on-board digital processors

NASA Astrophysics Data System (ADS)

Stampoulidis, L.; Kehayas, E.; Karppinen, M.; Tanskanen, A.; Heikkinen, V.; Westbergh, P.; Gustavsson, J.; Larsson, A.; Grüner-Nielsen, L.; Sotom, M.; Venet, N.; Ko, M.; Micusik, D.; Kissinger, D.; Ulusoy, A. C.; King, R.; Safaisini, R.

2017-11-01

Modern broadband communication networks rely on satellites to complement the terrestrial telecommunication infrastructure. Satellites accommodate global reach and enable world-wide direct broadcasting by facilitating wide access to the backbone network from remote sites or areas where the installation of ground segment infrastructure is not economically viable. At the same time the new broadband applications increase the bandwidth demands in every part of the network - and satellites are no exception. Modern telecom satellites incorporate On-Board Processors (OBP) having analogue-to-digital (ADC) and digital-to-analogue converters (DAC) at their inputs/outputs and making use of digital processing to handle hundreds of signals; as the amount of information exchanged increases, so do the physical size, mass and power consumption of the interconnects required to transfer massive amounts of data through bulk electric wires.

Roadmap of optical communications

NASA Astrophysics Data System (ADS)

Agrell, Erik; Karlsson, Magnus; Chraplyvy, A. R.; Richardson, David J.; Krummrich, Peter M.; Winzer, Peter; Roberts, Kim; Fischer, Johannes Karl; Savory, Seb J.; Eggleton, Benjamin J.; Secondini, Marco; Kschischang, Frank R.; Lord, Andrew; Prat, Josep; Tomkos, Ioannis; Bowers, John E.; Srinivasan, Sudha; Brandt-Pearce, Maïté; Gisin, Nicolas

2016-06-01

Lightwave communications is a necessity for the information age. Optical links provide enormous bandwidth, and the optical fiber is the only medium that can meet the modern society's needs for transporting massive amounts of data over long distances. Applications range from global high-capacity networks, which constitute the backbone of the internet, to the massively parallel interconnects that provide data connectivity inside datacenters and supercomputers. Optical communications is a diverse and rapidly changing field, where experts in photonics, communications, electronics, and signal processing work side by side to meet the ever-increasing demands for higher capacity, lower cost, and lower energy consumption, while adapting the system design to novel services and technologies. Due to the interdisciplinary nature of this rich research field, Journal of Optics has invited 16 researchers, each a world-leading expert in their respective subfields, to contribute a section to this invited review article, summarizing their views on state-of-the-art and future developments in optical communications.

IIIV/Si Nanoscale Lasers and Their Integration with Silicon Photonics

NASA Astrophysics Data System (ADS)

Bondarenko, Olesya

The rapidly evolving global information infrastructure requires ever faster data transfer within computer networks and stations. Integrated chip scale photonics can pave the way to accelerated signal manipulation and boost bandwidth capacity of optical interconnects in a compact and ergonomic arrangement. A key building block for integrated photonic circuits is an on-chip laser. In this dissertation we explore ways to reduce the physical footprint of semiconductor lasers and make them suitable for high density integration on silicon, a standard material platform for today's integrated circuits. We demonstrated the first room temperature metalo-dielectric nanolaser, sub-wavelength in all three dimensions. Next, we demonstrated a nanolaser on silicon, showing the feasibility of its integration with this platform. We also designed and realized an ultracompact feedback laser with edge-emitting structure, amenable for in-plane coupling with a standard silicon waveguide. Finally, we discuss the challenges and propose solutions for improvement of the device performance and practicality.

Latest generation interconnect technologies in APEnet+ networking infrastructure

NASA Astrophysics Data System (ADS)

Ammendola, Roberto; Biagioni, Andrea; Cretaro, Paolo; Frezza, Ottorino; Lo Cicero, Francesca; Lonardo, Alessandro; Martinelli, Michele; Stanislao Paolucci, Pier; Pastorelli, Elena; Rossetti, Davide; Simula, Francesco; Vicini, Piero

2017-10-01

In this paper we present the status of the 3rd generation design of the APEnet board (V5) built upon the 28nm Altera Stratix V FPGA; it features a PCIe Gen3 x8 interface and enhanced embedded transceivers with a maximum capability of 12.5Gbps each. The network architecture is designed in accordance to the Remote DMA paradigm. The APEnet+ V5 prototype is built upon the Stratix V DevKit with the addition of a proprietary, third party IP core implementing multi-DMA engines. Support for zero-copy communication is assured by the possibility of DMA-accessing either host and GPU memory, offloading the CPU from the chore of data copying. The current implementation plateaus to a bandwidth for memory read of 4.8GB/s. Here we describe the hardware optimization to the memory write process which relies on the use of two independent DMA engines and an improved TLB.

Multilevel photonic modules for millimeter-wave phased-array antennas

NASA Astrophysics Data System (ADS)

Paolella, Arthur C.; Joshi, Abhay M.; Wright, James G.; Coryell, Louis A.

1998-11-01

Optical signal distribution for phased array antennas in communication system is advantageous to designers. By distributing the microwave and millimeter wave signal through optical fiber there is the potential for improved performance and lower weight. In addition when applied to communication satellites this weight saving translates into substantially reduced launch costs. The goal of the Phase I Small Business Innovation Research (SBIR) Program is the development of multi-level photonic modules for phased array antennas. The proposed module with ultimately comprise of a monolithic, InGaAs/InP p-i-n photodetector-p-HEMT power amplifier, opto-electronic integrated circuit, that has 44 GHz bandwidth and output power of 50 mW integrated with a planar antenna. The photodetector will have a high quantum efficiency and will be front-illuminated, thereby improved optical performance. Under Phase I a module was developed using standard MIC technology with a high frequency coaxial feed interconnect.

Low-power light guiding and localization in optoplasmonic chains obtained by directed self-assembly

DOE PAGES

Ahn, Wonmi; Zhao, Xin; Hong, Yan; ...

2016-03-02

Here, optoplasmonic structures contain plasmonic components embedded in a defined photonic environment to create synergistic interactions between photonic and plasmonic components. Here, we show that chains of optical microspheres containing gold nanoparticles in their evanescent field combine the light guiding properties of a microsphere chain with the light localizing properties of a plasmonic nanoantenna. We implement these materials through template guided self-assembly and investigate their fundamental electromagnetic working principles through combination of electromagnetic simulations and experimental characterization. We demonstrate that optoplasmonic chains implemented by directed self-assembly achieve a significant reduction in guiding losses when compared with conventional plasmonic waveguides and,more » at the same time, retain the light localizing properties of plasmonic antennas at pre-defined locations. The results reinforce the potential of optoplasmonic structures for realizing low-loss optical interconnects with high bandwidth.« less

On-chip photonic synapse

PubMed Central

Cheng, Zengguang; Ríos, Carlos; Pernice, Wolfram H. P.; Wright, C. David; Bhaskaran, Harish

2017-01-01

The search for new “neuromorphic computing” architectures that mimic the brain’s approach to simultaneous processing and storage of information is intense. Because, in real brains, neuronal synapses outnumber neurons by many orders of magnitude, the realization of hardware devices mimicking the functionality of a synapse is a first and essential step in such a search. We report the development of such a hardware synapse, implemented entirely in the optical domain via a photonic integrated-circuit approach. Using purely optical means brings the benefits of ultrafast operation speed, virtually unlimited bandwidth, and no electrical interconnect power losses. Our synapse uses phase-change materials combined with integrated silicon nitride waveguides. Crucially, we can randomly set the synaptic weight simply by varying the number of optical pulses sent down the waveguide, delivering an incredibly simple yet powerful approach that heralds systems with a continuously variable synaptic plasticity resembling the true analog nature of biological synapses. PMID:28959725

Fan-out Estimation in Spin-based Quantum Computer Scale-up.

PubMed

Nguyen, Thien; Hill, Charles D; Hollenberg, Lloyd C L; James, Matthew R

2017-10-17

Solid-state spin-based qubits offer good prospects for scaling based on their long coherence times and nexus to large-scale electronic scale-up technologies. However, high-threshold quantum error correction requires a two-dimensional qubit array operating in parallel, posing significant challenges in fabrication and control. While architectures incorporating distributed quantum control meet this challenge head-on, most designs rely on individual control and readout of all qubits with high gate densities. We analysed the fan-out routing overhead of a dedicated control line architecture, basing the analysis on a generalised solid-state spin qubit platform parameterised to encompass Coulomb confined (e.g. donor based spin qubits) or electrostatically confined (e.g. quantum dot based spin qubits) implementations. The spatial scalability under this model is estimated using standard electronic routing methods and present-day fabrication constraints. Based on reasonable assumptions for qubit control and readout we estimate 10 2 -10 5 physical qubits, depending on the quantum interconnect implementation, can be integrated and fanned-out independently. Assuming relatively long control-free interconnects the scalability can be extended. Ultimately, the universal quantum computation may necessitate a much higher number of integrated qubits, indicating that higher dimensional electronics fabrication and/or multiplexed distributed control and readout schemes may be the preferredstrategy for large-scale implementation.

Enzyme-regulated the changes of pH values for assembling a colorimetric and multistage interconnection logic network with multiple readouts.

PubMed

Huang, Yanyan; Ran, Xiang; Lin, Youhui; Ren, Jinsong; Qu, Xiaogang

2015-04-22

Based on enzymatic reactions-triggered changes of pH values and biocomputing, a novel and multistage interconnection biological network with multiple easy-detectable signal outputs has been developed. Compared with traditional chemical computing, the enzyme-based biological system could overcome the interference between reactions or the incompatibility of individual computing gates and offer a unique opportunity to assemble multicomponent/multifunctional logic circuitries. Our system included four enzyme inputs: β-galactosidase (β-gal), glucose oxidase (GOx), esterase (Est) and urease (Ur). With the assistance of two signal transducers (gold nanoparticles and acid-base indicators) or pH meter, the outputs of the biological network could be conveniently read by the naked eyes. In contrast to current methods, the approach present here could realize cost-effective, label-free and colorimetric logic operations without complicated instrument. By designing a series of Boolean logic operations, we could logically make judgment of the compositions of the samples on the basis of visual output signals. Our work offered a promising paradigm for future biological computing technology and might be highly useful in future intelligent diagnostics, prodrug activation, smart drug delivery, process control, and electronic applications. Copyright © 2015 Elsevier B.V. All rights reserved.

Battery tester

DOE Office of Scientific and Technical Information (OSTI.GOV)

Poljak, M.D.

1985-08-12

This abstract discloses an improved battery tester for determining the acceptability of a Lithium Sulfur Dioxide (LiSO/sub 2/) storage battery at a given temperature and with one or more cells therein. The tester is generally made up of a first-comparison circuit having a series of series-interconnected components, namely a comparator, first and second flip-flops, and an AND gate. A first resistor is parallel connected to the first-comparison circuit. A second comparison circuit is also parallel connected to the first-comparison circuit and is generally made up of series-interconnected components, namely a second resistor, a capacitor, a buffer, and a second-comparator. Amore » first switch is connected to the first resistor and a second switch is parallel connected to the second-comparison circuit between the capacitor and the buffer. A logic control arrangement controls the operation of both switches, both comparators, and both flip-flops for testing a battery as to its start-up voltage and performance voltage characteristics all in a relatively short time period. In another embodiment of the tester, it is provided with an analog-to-digital converter, a memory, and a sensor arrangement for enhancing the versatility and reliability of the tester in determining the acceptability of a LiSO/sub 2/ battery.« less

Study of G-S/D underlap for enhanced analog performance and RF/circuit analysis of UTB InAs-OI-Si MOSFET using NQS small signal model

NASA Astrophysics Data System (ADS)

Maity, Subir Kumar; Pandit, Soumya

2017-01-01

InGaAs (and its variant) appears to be a promising channel material for high-performance, low-power scaled CMOS applications due to its excellent carrier transport properties. However, MOS transistors made of this suffer from poor electrostatic integrity. In this work, we consider an underlap ultra thin body (UTB) InAs-on-Insulator n-channel MOS transistor, and study the effect of varying the gate-source/drain (G-S/D) underlap length on the analog performance of the device with the help of technology computer-aided design (TCAD) simulation, calibrated with Schrodinger-Poisson solver and experimental results. The underlap technique improves the gate electrostatic integrity which in turn improves the analog performance. We develop a non-quasi-static (NQS) small signal equivalent circuit model of the device which is used for study of the RF performance. With increase of the underlap length, the unity gain cut-off frequency degrades and the maximum oscillation frequency improves beyond a certain value of the underlap length. We further study the gain-frequency response of a common source amplifier using the NQS model, through SPICE simulation and observe that the voltage gain and the gain bandwidth improves.

An Efficient, FPGA-Based, Cluster Detection Algorithm Implementation for a Strip Detector Readout System in a Time Projection Chamber Polarimeter

NASA Technical Reports Server (NTRS)

Gregory, Kyle J.; Hill, Joanne E. (Editor); Black, J. Kevin; Baumgartner, Wayne H.; Jahoda, Keith

2016-01-01

A fundamental challenge in a spaceborne application of a gas-based Time Projection Chamber (TPC) for observation of X-ray polarization is handling the large amount of data collected. The TPC polarimeter described uses the APV-25 Application Specific Integrated Circuit (ASIC) to readout a strip detector. Two dimensional photoelectron track images are created with a time projection technique and used to determine the polarization of the incident X-rays. The detector produces a 128x30 pixel image per photon interaction with each pixel registering 12 bits of collected charge. This creates challenging requirements for data storage and downlink bandwidth with only a modest incidence of photons and can have a significant impact on the overall mission cost. An approach is described for locating and isolating the photoelectron track within the detector image, yielding a much smaller data product, typically between 8x8 pixels and 20x20 pixels. This approach is implemented using a Microsemi RT-ProASIC3-3000 Field-Programmable Gate Array (FPGA), clocked at 20 MHz and utilizing 10.7k logic gates (14% of FPGA), 20 Block RAMs (17% of FPGA), and no external RAM. Results will be presented, demonstrating successful photoelectron track cluster detection with minimal impact to detector dead-time.

On implementation of DCTCP on three-tier and fat-tree data center network topologies.

PubMed

Zafar, Saima; Bashir, Abeer; Chaudhry, Shafique Ahmad

2016-01-01

A data center is a facility for housing computational and storage systems interconnected through a communication network called data center network (DCN). Due to a tremendous growth in the computational power, storage capacity and the number of inter-connected servers, the DCN faces challenges concerning efficiency, reliability and scalability. Although transmission control protocol (TCP) is a time-tested transport protocol in the Internet, DCN challenges such as inadequate buffer space in switches and bandwidth limitations have prompted the researchers to propose techniques to improve TCP performance or design new transport protocols for DCN. Data center TCP (DCTCP) emerge as one of the most promising solutions in this domain which employs the explicit congestion notification feature of TCP to enhance the TCP congestion control algorithm. While DCTCP has been analyzed for two-tier tree-based DCN topology for traffic between servers in the same rack which is common in cloud applications, it remains oblivious to the traffic patterns common in university and private enterprise networks which traverse the complete network interconnect spanning upper tier layers. We also recognize that DCTCP performance cannot remain unaffected by the underlying DCN architecture hence there is a need to test and compare DCTCP performance when implemented over diverse DCN architectures. Some of the most notable DCN architectures are the legacy three-tier, fat-tree, BCube, DCell, VL2, and CamCube. In this research, we simulate the two switch-centric DCN architectures; the widely deployed legacy three-tier architecture and the promising fat-tree architecture using network simulator and analyze the performance of DCTCP in terms of throughput and delay for realistic traffic patterns. We also examine how DCTCP prevents incast and outcast congestion when realistic DCN traffic patterns are employed in above mentioned topologies. Our results show that the underlying DCN architecture significantly impacts DCTCP performance. We find that DCTCP gives optimal performance in fat-tree topology and is most suitable for large networks.

SpaceFibre: The Standard and the Multi-Lane Layer

NASA Astrophysics Data System (ADS)

Parkes, Steve; McClements, Chris; McLaren, David; Florit, Albert Ferrer; Gonzalez Villafranca, Alberto

2016-08-01

SpaceFibre is a new standard for spacecraft on-board data-handling networks, initially designed to deliver multi-Gbit/s data rates for synthetic aperture radar and high-resolution, multi-spectral imaging instruments, The addition of quality of service (QoS) and fault detection, isolation and recovery (FDIR) capabilities to SpaceFibre has resulted in a unified network technology. SpaceFibre provides high bandwidth, low latency, fault isolation and recovery suitable for space applications, and novel QoS that combines priority, bandwidth reservation and scheduling and which provides babbling node protection. SpaceFibre is backwards compatible with the widely used SpaceWire standard at the network level allowing simple interconnection of existing SpaceWire equipment to a SpaceFibre link or network.Developed by STAR-Dundee and the University of Dundee for the European Space Agency (ESA) SpaceFibre is able to operate over fibre-optic and electrical cable. A single lane of SpaceFibre comprises four signals (TX+/- and RX+/-) and supports data rates of 2 Gbits/s (2.5 Gbits/s data signalling rate) with data rates up to 5 Gbits/s already planned.Several lanes can operate together to provide a multi- lane link. Multi-laning increases the data-rate to well over 20 Gbits/s.This paper details the current state of SpaceFibre which is now in the process of formal standardisation by the European Cooperation for Space Standardization (ECSS). The multi-lane layer of SpaceFibre is then described.

Design of a low parasitic inductance SiC power module with double-sided cooling

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Fei; Liang, Zhenxian; Wang, Fei

In this paper, a low-parasitic inductance SiC power module with double-sided cooling is designed and compared with a baseline double-sided cooled module. With the unique 3D layout utilizing vertical interconnection, the power loop inductance is effectively reduced without sacrificing the thermal performance. Both simulations and experiments are carried out to validate the design. Q3D simulation results show a power loop inductance of 1.63 nH, verified by the experiment, indicating more than 60% reduction of power loop inductance compared with the baseline module. With 0Ω external gate resistance turn-off at 600V, the voltage overshoot is less than 9% of the busmore » voltage at a load of 44.6A.« less

Monolithically integrated bacteriorhodopsin-GaAs/GaAlAs phototransceiver.

PubMed

Shin, Jonghyun; Bhattacharya, Pallab; Xu, Jian; Váró, György

2004-10-01

A monolithically integrated bacteriorhodopsin-semiconductor phototransceiver is demonstrated for the first time to the authors' knowledge. In this novel biophotonic optical interconnect, the input photoexcitation is detected by bacteriorhodopsin (bR) that has been selectively deposited onto the gate of a GaAs-based field-effect transistor. The photovoltage developed across the bR is converted by the transistor into an amplified photocurrent, which drives an integrated light-emitting diode with a Ga0.37Al0.63As active region. Advantage is taken of the high-input impedance of the field-effect transistor, which matches the high internal resistance of bR. The input and output wavelengths are 594 and 655 nm, respectively. The transient response of the optoelectronic circuit to modulated input light has also been studied.

Scalable digital hardware for a trapped ion quantum computer

NASA Astrophysics Data System (ADS)

Mount, Emily; Gaultney, Daniel; Vrijsen, Geert; Adams, Michael; Baek, So-Young; Hudek, Kai; Isabella, Louis; Crain, Stephen; van Rynbach, Andre; Maunz, Peter; Kim, Jungsang

2016-12-01

Many of the challenges of scaling quantum computer hardware lie at the interface between the qubits and the classical control signals used to manipulate them. Modular ion trap quantum computer architectures address scalability by constructing individual quantum processors interconnected via a network of quantum communication channels. Successful operation of such quantum hardware requires a fully programmable classical control system capable of frequency stabilizing the continuous wave lasers necessary for loading, cooling, initialization, and detection of the ion qubits, stabilizing the optical frequency combs used to drive logic gate operations on the ion qubits, providing a large number of analog voltage sources to drive the trap electrodes, and a scheme for maintaining phase coherence among all the controllers that manipulate the qubits. In this work, we describe scalable solutions to these hardware development challenges.

High-mobility and low-operating voltage organic thin film transistor with epoxy based siloxane binder as the gate dielectric

NASA Astrophysics Data System (ADS)

Tewari, Amit; Gandla, Srinivas; Pininti, Anil Reddy; Karuppasamy, K.; Böhm, Siva; Bhattacharyya, Arup R.; McNeill, Christopher R.; Gupta, Dipti

2015-09-01

This paper reports the fabrication of pentacene-based organic thin-film transistors using a dielectric material, Dynasylan ®SIVO110. The devices exhibit excellent performance characterized by a low threshold voltage of -1.4 V (operating voltage: 0 to -4 V) together with a mobility of 1.9 cm2 V-1s-1. These results are promising because it uses only a single layer of dielectric without performing any intermediate treatment. The reason is attributed to the high charge storage capacity of the dielectric (κ ˜ 20.02), a low interfacial trap density (2.56 × 1011cm-2), and favorable pentacene film morphology consisting of large and interconnected grains having an average size of 234 nm.

OZSPEC-2: an improved broadband high-resolution elliptical crystal x-ray spectrometer for high-energy density physics experiments (invited).

PubMed

Heeter, R F; Anderson, S G; Booth, R; Brown, G V; Emig, J; Fulkerson, S; McCarville, T; Norman, D; Schneider, M B; Young, B K F

2008-10-01

A novel time, space, and energy-resolved x-ray spectrometer has been developed which produces, in a single snapshot, a broadband and relatively calibrated spectrum of the x-ray emission from a high-energy density laboratory plasma. The opacity zipper spectrometer (OZSPEC-1) records a nearly continuous spectrum for x-ray energies from 240 to 5800 eV in a single shot. The second-generation OZSPEC-2, detailed in this work, records fully continuous spectra on a single shot from any two of these three bands: 270-650, 660-1580, and 1960-4720 eV. These instruments thus record thermal and line radiation from a wide range of plasmas. These instruments' single-shot bandwidth is unmatched in a time-gated spectrometer; conversely, other broadband instruments are either time-integrated (using crystals or gratings), lack spectral resolution (diode arrays), or cover a lower energy band (gratings). The OZSPECs are based on the zipper detector, a large-format (100x35 mm) gated microchannel plate detector, with spectra dispersed along the 100 mm dimension. OZSPEC-1 and -2 both use elliptically bent crystals of OHM, RAP, and/or PET. Individual spectra are gated in 100 ps. OZSPEC-2 provides one-dimensional spatial imaging with 30-50 microm resolution over a 1500 microm field of view at the source. The elliptical crystal design yields broad spectral coverage with resolution E/DeltaE>500, strong rejection of hard x-ray backgrounds, and negligible source broadening for extended sources. Near-term applications include plasma opacity measurements, detailed spectra of inertial fusion Hohlraums, and laboratory astrophysics experiments.

Improved passive optical network architectures to support local area network emulation and protection

NASA Astrophysics Data System (ADS)

Wong, Elaine; Nadarajah, Nishaanthan; Chae, Chang-Joon; Nirmalathas, Ampalavanapillai; Attygalle, Sanjeewa M.

2006-01-01

We describe two optical layer schemes which simultaneously facilitate local area network emulation and automatic protection switching against distribution fiber breaks in passive optical networks. One scheme employs a narrowband fiber Bragg grating placed close to the star coupler in the feeder fiber of the passive optical network, while the other uses an additional short length distribution fiber from the star coupler to each customer for the redirection of the customer traffic. Both schemes use RF subcarrier multiplexed transmission for intercommunication between customers in conjunction with upstream access to the central office at baseband. Failure detection and automatic protection switching are performed independently by each optical network unit that is located at the customer premises in a distributed manner. The restoration of traffic transported between the central office and an optical network unit in the event of the distribution fiber break is performed by interconnecting adjacent optical network units and carrying out signal transmissions via an independent but interconnected optical network unit. Such a protection mechanism enables multiple adjacent optical network units to be simultaneously protected by a single optical network unit utilizing its maximum available bandwidth. We experimentally verify the feasibility of both schemes with 1.25 Gb/s upstream baseband transmission to the central office and 155 Mb/s local area network data transmission on a RF subcarrier frequency. The experimental results obtained from both schemes are compared, and the power budgets are calculated to analyze the scalability of each scheme.

UAVSAR Phased Array Aperture

NASA Technical Reports Server (NTRS)

Chamberlain, Neil; Zawadzki, Mark; Sadowy, Greg; Oakes, Eric; Brown, Kyle; Hodges, Richard

2009-01-01

This paper describes the development of a patch antenna array for an L-band repeat-pass interferometric synthetic aperture radar (InSAR) instrument that is to be flown on an unmanned aerial vehicle (UAV). The antenna operates at a center frequency of 1.2575 GHz and with a bandwidth of 80 MHz, consistent with a number of radar instruments that JPL has previously flown. The antenna is designed to radiate orthogonal linear polarizations in order to facilitate fully-polarimetric measurements. Beam-pointing requirements for repeat-pass SAR interferometry necessitate electronic scanning in azimuth over a range of -20degrees in order to compensate for aircraft yaw. Beam-steering is accomplished by transmit/receive (T/R) modules and a beamforming network implemented in a stripline circuit board. This paper, while providing an overview of phased array architecture, focuses on the electromagnetic design of the antenna tiles and associated interconnects. An important aspect of the design of this antenna is that it has an amplitude taper of 10dB in the elevation direction. This is to reduce multipath reflections from the wing that would otherwise be detrimental to interferometric radar measurements. This taper is provided by coupling networks in the interconnect circuits as opposed to attenuating the output of the T/R modules. Details are given of material choices and fabrication techniques that meet the demanding environmental conditions that the antenna must operate in. Predicted array performance is reported in terms of co-polarized and crosspolarized far-field antenna patterns, and also in terms of active reflection coefficient.

Statistical evaluation of metal fill widths for emulated metal fill in parasitic extraction methodology

NASA Astrophysics Data System (ADS)

J-Me, Teh; Noh, Norlaili Mohd.; Aziz, Zalina Abdul

2015-05-01

In the chip industry today, the key goal of a chip development organization is to develop and market chips within a short time frame to gain foothold on market share. This paper proposes a design flow around the area of parasitic extraction to improve the design cycle time. The proposed design flow utilizes the usage of metal fill emulation as opposed to the current flow which performs metal fill insertion directly. By replacing metal fill structures with an emulation methodology in earlier iterations of the design flow, this is targeted to help reduce runtime in fill insertion stage. Statistical design of experiments methodology utilizing the randomized complete block design was used to select an appropriate emulated metal fill width to improve emulation accuracy. The experiment was conducted on test cases of different sizes, ranging from 1000 gates to 21000 gates. The metal width was varied from 1 x minimum metal width to 6 x minimum metal width. Two-way analysis of variance and Fisher's least significant difference test were used to analyze the interconnect net capacitance values of the different test cases. This paper presents the results of the statistical analysis for the 45 nm process technology. The recommended emulated metal fill width was found to be 4 x the minimum metal width.

Blueprint for a microwave trapped ion quantum computer

PubMed Central

Lekitsch, Bjoern; Weidt, Sebastian; Fowler, Austin G.; Mølmer, Klaus; Devitt, Simon J.; Wunderlich, Christof; Hensinger, Winfried K.

2017-01-01

The availability of a universal quantum computer may have a fundamental impact on a vast number of research fields and on society as a whole. An increasingly large scientific and industrial community is working toward the realization of such a device. An arbitrarily large quantum computer may best be constructed using a modular approach. We present a blueprint for a trapped ion–based scalable quantum computer module, making it possible to create a scalable quantum computer architecture based on long-wavelength radiation quantum gates. The modules control all operations as stand-alone units, are constructed using silicon microfabrication techniques, and are within reach of current technology. To perform the required quantum computations, the modules make use of long-wavelength radiation–based quantum gate technology. To scale this microwave quantum computer architecture to a large size, we present a fully scalable design that makes use of ion transport between different modules, thereby allowing arbitrarily many modules to be connected to construct a large-scale device. A high error–threshold surface error correction code can be implemented in the proposed architecture to execute fault-tolerant operations. With appropriate adjustments, the proposed modules are also suitable for alternative trapped ion quantum computer architectures, such as schemes using photonic interconnects. PMID:28164154

Sensitive Precise p H Measurement with Large-Area Graphene Field-Effect Transistors at the Quantum-Capacitance Limit

NASA Astrophysics Data System (ADS)

Fakih, Ibrahim; Mahvash, Farzaneh; Siaj, Mohamed; Szkopek, Thomas

2017-10-01

A challenge for p H sensing is decreasing the minimum measurable p H per unit bandwidth in an economical fashion. Minimizing noise to reach the inherent limit imposed by charge fluctuation remains an obstacle. We demonstrate here graphene-based ion-sensing field-effect transistors that saturate the physical limit of sensitivity, defined here as the change in electrical response with respect to p H , and achieve a precision limited by charge-fluctuation noise at the sensing layer. We present a model outlining the necessity for maximizing the device carrier mobility, active sensing area, and capacitive coupling in order to minimize noise. We encapsulate large-area graphene with an ultrathin layer of parylene, a hydrophobic polymer, and deposit an ultrathin, stoichiometric p H -sensing layer of either aluminum oxide or tantalum pentoxide. With these structures, we achieve gate capacitances ˜0.6 μ F /cm2 , approaching the quantum-capacitance limit inherent to graphene, along with a near-Nernstian p H response of ˜55 ±2 mV /p H . We observe field-effect mobilities as high as 7000 cm2 V-1 s-1 with minimal hysteresis as a result of the parylene encapsulation. A detection limit of 0.1 m p H in a 60-Hz electrical bandwidth is observed in optimized graphene transistors.

Digital Front End for Wide-Band VLBI Science Receiver

NASA Technical Reports Server (NTRS)

Jongeling, Andre; Sigman, Elliott; Navarro, Robert; Goodhart, Charles; Rogstad, Steve; Chandra, Kumar; Finley, Sue; Trinh, Joseph; Soriano, Melissa; White, Les;

Signal and Noise in FET-Nanopore Devices.

PubMed

Parkin, William M; Drndić, Marija

2018-02-23

The combination of a nanopore with a local field-effect transistor (FET-nanopore), like a nanoribbon, nanotube, or nanowire, in order to sense single molecules translocating through the pore is promising for DNA sequencing at megahertz bandwidths. Previously, it was experimentally determined that the detection mechanism was due to local potential fluctuations that arise when an analyte enters a nanopore and constricts ion flow through it, rather than the theoretically proposed mechanism of direct charge coupling between the DNA and nanowire. However, there has been little discussion on the experimentally observed detection mechanism and its relation to the operation of real devices. We model the intrinsic signal and noise in such an FET-nanopore device and compare the results to the ionic current signal. The physical dimensions of DNA molecules limit the change in gate voltage on the FET to below 40 mV. We discuss the low-frequency flicker noise (<10 kHz), medium-frequency thermal noise (<100 kHz), and high-frequency capacitive noise (>100 kHz) in FET-nanopore devices. At bandwidths dominated by thermal noise, the signal-to-noise ratio in FET-nanopore devices is lower than in the ionic current signal. At high frequencies, where noise due to parasitic capacitances in the amplifier and chip is the dominant source of noise in ionic current measurements, high-transconductance FET-nanopore devices can outperform ionic current measurements.

Prospects for in vivo blood velocimetry using acoustic resolution photoacoustic Doppler

NASA Astrophysics Data System (ADS)

Brunker, J.; Beard, P.

2016-03-01

Acoustic resolution photoacoustic Doppler flowmetry (AR-PAF) is a technique that has the potential to overcome the spatial resolution and depth penetration limitations of current blood flow measuring methods. Previous work has shown the potential of the technique using blood-mimicking phantoms, but it has proved difficult to make accurate measurements in blood, and thus in vivo application has not yet been possible. One explanation for this difficulty is that whole blood is insufficiently heterogeneous. Through experimental measurements in red blood cell suspensions of different concentrations, as well as in whole blood, we provide new insight and evidence that refutes this assertion. We show that the velocity measurement accuracy is influenced by bandlimiting not only due to the detector frequency response, but also due to spatial averaging of absorbers within the detector field-of-view. In addition, there is a detrimental effect of limited light penetration, but this can be mitigated by selecting less attenuated wavelengths of light, and also by employing range-gating signal processing. By careful choice of these parameters as well as the detector centre frequency, bandwidth and field-of-view, it is possible to make AR-PAF measurements in whole blood using transducers with bandwidths in the tens of MHz range. These findings have profound implications for the prospects of making deep tissue measurements of blood flow relevant to the study of microcirculatory abnormalities associated with cancer, diabetes, atherosclerosis and other conditions.

1-GHz repetition rate femtosecond OPO with stabilized offset between signal and idler frequency combs.

PubMed

Gebs, R; Dekorsy, T; Diddams, S A; Bartels, A

2008-04-14

We report an optical parametric oscillator (OPO) based on periodically poled lithium niobate (PPLN) that is synchronously pumped by a femtosecond Ti:sapphire laser at 1 GHz repetition rate. The signal output has a center wavelength of 1558 nm and its spectral bandwidth amounts to 40 nm. The OPO operates in a regime where the signal- and idler frequency combs exhibit a partial overlap around 1600 nm. In this near-degeneracy region, a beat at the offset between the signal and idler frequency combs is detected. Phase-locking this beat to an external reference stabilizes the spectral envelopes of the signal- and idler output. At the same time, the underlying frequency combs are stabilized relative to each other with an instability of 1.5x10(-17) at 1 s gate time.

160-190 GHz Monolithic Low Noise Amplifiers

NASA Technical Reports Server (NTRS)

Kok, Y. L.; Wang, H.; Huang, T. W.; Lai, R.; Chen, Y. C.; Sholley, M.; Block, T.; Streit, D. C.; Liu, P. H.; Allen, B. R.;

Radio-frequency measurement in semiconductor quantum computation

NASA Astrophysics Data System (ADS)

Han, TianYi; Chen, MingBo; Cao, Gang; Li, HaiOu; Xiao, Ming; Guo, GuoPing

2017-05-01

Semiconductor quantum dots have attracted wide interest for the potential realization of quantum computation. To realize efficient quantum computation, fast manipulation and the corresponding readout are necessary. In the past few decades, considerable progress of quantum manipulation has been achieved experimentally. To meet the requirements of high-speed readout, radio-frequency (RF) measurement has been developed in recent years, such as RF-QPC (radio-frequency quantum point contact) and RF-DGS (radio-frequency dispersive gate sensor). Here we specifically demonstrate the principle of the radio-frequency reflectometry, then review the development and applications of RF measurement, which provides a feasible way to achieve high-bandwidth readout in quantum coherent control and also enriches the methods to study these artificial mesoscopic quantum systems. Finally, we prospect the future usage of radio-frequency reflectometry in scaling-up of the quantum computing models.

An FPGA-based bolometer for the MAST-U Super-X divertor.

PubMed

Lovell, Jack; Naylor, Graham; Field, Anthony; Drewelow, Peter; Sharples, Ray

2016-11-01

A new resistive bolometer system has been developed for MAST-Upgrade. It will measure radiated power in the new Super-X divertor, with millisecond time resolution, along 16 vertical and 16 horizontal lines of sight. The system uses a Xilinx Zynq-7000 series Field-Programmable Gate Array (FPGA) in the D-TACQ ACQ2106 carrier to perform real time data acquisition and signal processing. The FPGA enables AC-synchronous detection using high performance digital filtering to achieve a high signal-to-noise ratio and will be able to output processed data in real time with millisecond latency. The system has been installed on 8 previously unused channels of the JET vertical bolometer system. Initial results suggest good agreement with data from existing vertical channels but with higher bandwidth and signal-to-noise ratio.

Block QCA Fault-Tolerant Logic Gates

NASA Technical Reports Server (NTRS)

Firjany, Amir; Toomarian, Nikzad; Modarres, Katayoon

2003-01-01

Suitably patterned arrays (blocks) of quantum-dot cellular automata (QCA) have been proposed as fault-tolerant universal logic gates. These block QCA gates could be used to realize the potential of QCA for further miniaturization, reduction of power consumption, increase in switching speed, and increased degree of integration of very-large-scale integrated (VLSI) electronic circuits. The limitations of conventional VLSI circuitry, the basic principle of operation of QCA, and the potential advantages of QCA-based VLSI circuitry were described in several NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35; and Hybrid VLSI/QCA Architecture for Computing FFTs (NPO-20923), which follows this article. To recapitulate the principle of operation (greatly oversimplified because of the limitation on space available for this article): A quantum-dot cellular automata contains four quantum dots positioned at or between the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the quantummechanical sense) between neighboring dots within the cell. The Coulomb repulsion between the two electrons tends to make them occupy antipodal dots in the cell. For an isolated cell, there are two energetically equivalent arrangements (denoted polarization states) of the extra electrons. The cell polarization is used to encode binary information. Because the polarization of a nonisolated cell depends on Coulomb-repulsion interactions with neighboring cells, universal logic gates and binary wires could be constructed, in principle, by arraying QCA of suitable design in suitable patterns. Heretofore, researchers have recognized two major obstacles to realization of QCA-based logic gates: One is the need for (and the difficulty of attaining) operation of QCA circuitry at room temperature or, for that matter, at any temperature above a few Kelvins. It has been theorized that room-temperature operation could be made possible by constructing QCA as molecular-scale devices. However, in approaching the lower limit of miniaturization at the molecular level, it becomes increasingly imperative to overcome the second major obstacle, which is the need for (and the difficulty of attaining) high precision in the alignments of adjacent QCA in order to ensure the correct interactions among the quantum dots.

Extending the BEAGLE library to a multi-FPGA platform.

PubMed

Jin, Zheming; Bakos, Jason D

2013-01-19

Maximum Likelihood (ML)-based phylogenetic inference using Felsenstein's pruning algorithm is a standard method for estimating the evolutionary relationships amongst a set of species based on DNA sequence data, and is used in popular applications such as RAxML, PHYLIP, GARLI, BEAST, and MrBayes. The Phylogenetic Likelihood Function (PLF) and its associated scaling and normalization steps comprise the computational kernel for these tools. These computations are data intensive but contain fine grain parallelism that can be exploited by coprocessor architectures such as FPGAs and GPUs. A general purpose API called BEAGLE has recently been developed that includes optimized implementations of Felsenstein's pruning algorithm for various data parallel architectures. In this paper, we extend the BEAGLE API to a multiple Field Programmable Gate Array (FPGA)-based platform called the Convey HC-1. The core calculation of our implementation, which includes both the phylogenetic likelihood function (PLF) and the tree likelihood calculation, has an arithmetic intensity of 130 floating-point operations per 64 bytes of I/O, or 2.03 ops/byte. Its performance can thus be calculated as a function of the host platform's peak memory bandwidth and the implementation's memory efficiency, as 2.03 × peak bandwidth × memory efficiency. Our FPGA-based platform has a peak bandwidth of 76.8 GB/s and our implementation achieves a memory efficiency of approximately 50%, which gives an average throughput of 78 Gflops. This represents a ~40X speedup when compared with BEAGLE's CPU implementation on a dual Xeon 5520 and 3X speedup versus BEAGLE's GPU implementation on a Tesla T10 GPU for very large data sizes. The power consumption is 92 W, yielding a power efficiency of 1.7 Gflops per Watt. The use of data parallel architectures to achieve high performance for likelihood-based phylogenetic inference requires high memory bandwidth and a design methodology that emphasizes high memory efficiency. To achieve this objective, we integrated 32 pipelined processing elements (PEs) across four FPGAs. For the design of each PE, we developed a specialized synthesis tool to generate a floating-point pipeline with resource and throughput constraints to match the target platform. We have found that using low-latency floating-point operators can significantly reduce FPGA area and still meet timing requirement on the target platform. We found that this design methodology can achieve performance that exceeds that of a GPU-based coprocessor.

Introduction to the Special Issue on Digital Signal Processing in Radio Astronomy

NASA Astrophysics Data System (ADS)

Price, D. C.; Kocz, J.; Bailes, M.; Greenhill, L. J.

2016-03-01

Advances in astronomy are intimately linked to advances in digital signal processing (DSP). This special issue is focused upon advances in DSP within radio astronomy. The trend within that community is to use off-the-shelf digital hardware where possible and leverage advances in high performance computing. In particular, graphics processing units (GPUs) and field programmable gate arrays (FPGAs) are being used in place of application-specific circuits (ASICs); high-speed Ethernet and Infiniband are being used for interconnect in place of custom backplanes. Further, to lower hurdles in digital engineering, communities have designed and released general-purpose FPGA-based DSP systems, such as the CASPER ROACH board, ASTRON Uniboard, and CSIRO Redback board. In this introductory paper, we give a brief historical overview, a summary of recent trends, and provide an outlook on future directions.

Multicolor, time-gated, soft x-ray pinhole imaging of wire array and gas puff Z pinches on the Z and Saturn pulsed power generators.

PubMed

Jones, B; Coverdale, C A; Nielsen, D S; Jones, M C; Deeney, C; Serrano, J D; Nielsen-Weber, L B; Meyer, C J; Apruzese, J P; Clark, R W; Coleman, P L

2008-10-01

A multicolor, time-gated, soft x-ray pinhole imaging instrument is fielded as part of the core diagnostic set on the 25 MA Z machine [M. E. Savage et al., in Proceedings of the Pulsed Power Plasma Sciences Conference (IEEE, New York, 2007), p. 979] for studying intense wire array and gas puff Z-pinch soft x-ray sources. Pinhole images are reflected from a planar multilayer mirror, passing 277 eV photons with <10 eV bandwidth. An adjacent pinhole camera uses filtration alone to view 1-10 keV photons simultaneously. Overlaying these data provides composite images that contain both spectral as well as spatial information, allowing for the study of radiation production in dense Z-pinch plasmas. Cu wire arrays at 20 MA on Z show the implosion of a colder cloud of material onto a hot dense core where K-shell photons are excited. A 528 eV imaging configuration has been developed on the 8 MA Saturn generator [R. B. Spielman et al., and A. I. P. Conf, Proc. 195, 3 (1989)] for imaging a bright Li-like Ar L-shell line. Ar gas puff Z pinches show an intense K-shell emission from a zippering stagnation front with L-shell emission dominating as the plasma cools.

Advanced modulation technology development for earth station demodulator applications. Coded modulation system development

NASA Technical Reports Server (NTRS)

Miller, Susan P.; Kappes, J. Mark; Layer, David H.; Johnson, Peter N.

1990-01-01

A jointly optimized coded modulation system is described which was designed, built, and tested by COMSAT Laboratories for NASA LeRC which provides a bandwidth efficiency of 2 bits/s/Hz at an information rate of 160 Mbit/s. A high speed rate 8/9 encoder with a Viterbi decoder and an Octal PSK modem are used to achieve this. The BER performance is approximately 1 dB from the theoretically calculated value for this system at a BER of 5 E-7 under nominal conditions. The system operates in burst mode for downlink applications and tests have demonstrated very little degradation in performance with frequency and level offset. Unique word miss rate measurements were conducted which demonstrate reliable acquisition at low values of Eb/No. Codec self tests have verified the performance of this subsystem in a stand alone mode. The codec is capable of operation at a 200 Mbit/s information rate as demonstrated using a codec test set which introduces noise digitally. The measured performance is within 0.2 dB of the computer simulated predictions. A gate array implementation of the most time critical element of the high speed Viterbi decoder was completed. This gate array add-compare-select chip significantly reduces the power consumption and improves the manufacturability of the decoder. This chip has general application in the implementation of high speed Viterbi decoders.

Integrating silicon photonic interconnects with CMOS: Fabrication to architecture

NASA Astrophysics Data System (ADS)

Sherwood, Nicholas Ramsey

While it was for many years the goal of microelectronics to speed up our daily tasks, the focus of today's technological developments is heavily centered on electronic media. Anyone can share their thoughts as text, sound, images or full videos, they can even make phone calls and download full movies on their computers, tablets and phones. The impact of this upsurge in bandwidth is directly on the infrastructure that carries this data. Long distance telecom lines were long ago replaced by optical fibers; now shorter and shorter distance connections have moved to optical transmission to keep up with the bandwidth requirements. Yet microprocessors that make up the switching nodes as well as the endpoints are not only stagnant in terms of processing speed, but also unlikely to continue Moore's transistor-doubling trend for much longer. Silicon photonics stands to make a technical leap in microprocessor technology by allowing monolithic communication speeds between arbitrarily spaced processing elements. The improvement in on-chip communication could reduce power and enable new improvements in this field. This work explores a few aspects involved in making such a leap practical in real life. The first part of the thesis develops process techniques and materials to make silicon photonics truly compatible with CMOS electronics, for two different stack layouts, including a glimpse into multilayerd photonics. Following this is an evaluation of the limitations of integrated devices and a post-fabrication/stabilizing solution using thermal index shifting. In the last parts we explore higher level device design and architecture on the SOI platform.

Fiber-Optic Network Architectures for Onboard Avionics Applications Investigated

NASA Technical Reports Server (NTRS)

Nguyen, Hung D.; Ngo, Duc H.

2003-01-01

This project is part of a study within the Advanced Air Transportation Technologies program undertaken at the NASA Glenn Research Center. The main focus of the program is the improvement of air transportation, with particular emphasis on air transportation safety. Current and future advances in digital data communications between an aircraft and the outside world will require high-bandwidth onboard communication networks. Radiofrequency (RF) systems, with their interconnection network based on coaxial cables and waveguides, increase the complexity of communication systems onboard modern civil and military aircraft with respect to weight, power consumption, and safety. In addition, safety and reliability concerns from electromagnetic interference between the RF components embedded in these communication systems exist. A simple, reliable, and lightweight network that is free from the effects of electromagnetic interference and capable of supporting the broadband communications needs of future onboard digital avionics systems cannot be easily implemented using existing coaxial cable-based systems. Fiber-optical communication systems can meet all these challenges of modern avionics applications in an efficient, cost-effective manner. The objective of this project is to present a number of optical network architectures for onboard RF signal distribution. Because of the emergence of a number of digital avionics devices requiring high-bandwidth connectivity, fiber-optic RF networks onboard modern aircraft will play a vital role in ensuring a low-noise, highly reliable RF communication system. Two approaches are being used for network architectures for aircraft onboard fiber-optic distribution systems: a hybrid RF-optical network and an all-optical wavelength division multiplexing (WDM) network.

Gbit/s-operation of graphene electro-absorption modulators in a passive polymer waveguide platform for data and telecommunications

NASA Astrophysics Data System (ADS)

Kleinert, M.; Reinke, P.; Bach, H.-G.; Brinker, W.; Zawadzki, C.; Dietrich, A.; de Felipe, D.; Keil, N.; Schell, M.

2017-02-01

Graphene with its high carrier mobility as well as its tunable light absorption is an attractive active material for highspeed electro-absorption modulators (EAMs). Large-area CVD-grown graphene monolayers can be transferred onto arbitrary substrates to add active optoelectronic properties to intrinsically passive photonic integration platforms. In this work, we present graphene-based EAMs integrated in passive polymer waveguides. To facilitate modulation frequencies in the GHz range, a 50 Ω termination resistor as well as a DC blocking capacitor are integrated with graphene EAMs for the first time. Large signal data transmission experiments were carried out across the O, C and L optical communications bands. The fastest devices exhibit a 3-dB bandwidth of more than 4 GHz. Our analytical model of the modulation response for the graphene-based EAMs is in good agreement with the measurement results. It predicts that bandwidths greater than 50 GHz are possible with future device iterations. Owing to the absorption properties of the graphene layers, the devices are expected to be functional at smaller wavelengths of interest for optical interconnects and data-communications as well, offering a novel flexibility for the integration of high-speed functionalities in optoelectronic integrated circuits. Our work is the first step towards an Active Optical Printed Circuit Board, hiding the optics completely inside the board and thus removing entry barriers in manufacturing. We believe this will lead to the same success as observed in Active Optical Cables for short range optically wired connections.

Initial Performance Results on IBM POWER6

NASA Technical Reports Server (NTRS)

Saini, Subbash; Talcott, Dale; Jespersen, Dennis; Djomehri, Jahed; Jin, Haoqiang; Mehrotra, Piysuh

2008-01-01

The POWER5+ processor has a faster memory bus than that of the previous generation POWER5 processor (533 MHz vs. 400 MHz), but the measured per-core memory bandwidth of the latter is better than that of the former (5.7 GB/s vs. 4.3 GB/s). The reason for this is that in the POWER5+, the two cores on the chip share the L2 cache, L3 cache and memory bus. The memory controller is also on the chip and is shared by the two cores. This serializes the path to memory. For consistently good performance on a wide range of applications, the performance of the processor, the memory subsystem, and the interconnects (both latency and bandwidth) should be balanced. Recognizing this, IBM has designed the Power6 processor so as to avoid the bottlenecks due to the L2 cache, memory controller and buffer chips of the POWER5+. Unlike the POWER5+, each core in the POWER6 has its own L2 cache (4 MB - double that of the Power5+), memory controller and buffer chips. Each core in the POWER6 runs at 4.7 GHz instead of 1.9 GHz in POWER5+. In this paper, we evaluate the performance of a dual-core Power6 based IBM p6-570 system, and we compare its performance with that of a dual-core Power5+ based IBM p575+ system. In this evaluation, we have used the High- Performance Computing Challenge (HPCC) benchmarks, NAS Parallel Benchmarks (NPB), and four real-world applications--three from computational fluid dynamics and one from climate modeling.

Nanocomposites for high-speed optical modulators and plasmonic thermal mid-infrared emitters

NASA Astrophysics Data System (ADS)

Demir, Veysi

Demand for high-speed optical modulators and narrow-bandwidth infrared thermal emitters for numerous applications continues to rise and new optical devices are needed to deal with massive data flows, processing powers, and fabrication costs. Conventional techniques are usually hindered by material limitations or electronic interconnects and advances in organic nanocomposite materials and their integration into photonic integrated circuits (PICs) have been acknowledged as a promising alternative to single crystal techniques. The work presented in this thesis uses plasmonic and magneto-optic effects towards the development of novel optical devices for harnessing light and generating high bandwidth signals (>40GHz) at room and cryogenic temperatures (4.2°K). Several publications have resulted from these efforts and are listed at the end of the abstract. In our first published research we developed a narrow-bandwidth mid-infrared thermal emitter using an Ag/dielectric/Ag thin film structure arranged in hexagonal planar lattice structures. PECVD produced nanoamorphous carbon (NAC) is used as a dielectric layer. Spectrally tunable (>2 mum) and narrow bandwidth (<0.5 mum) emission peaks in the range of 4-7 mum were demonstrated by decreasing the resistivity of NAC from 1012 and 109 O.cm with an MoSi2 dopant and increasing the emitter lattice constant from 4 to 7 mum. This technique offers excellent flexibility for developing cost-effective mid-IR sources as compared to costly fiber and quantum cascade lasers (QCLs). Next, the effect of temperature on the Verdet constant for cobalt-ferrite polymer nanocomposites was measured for a series of temperatures ranging from 40 to 200°K with a Faraday rotation polarimeter. No visual change was observed in the films during thermal cycling, and ˜4x improvement was achieved at 40°K. The results are promising and further analysis is merited at 4.2°K to assess the performance of this material for cryogenic magneto-optic modulators for supercomputers. Finally, the dielectric constant and loss tangent of MAPTMS sol-gel films were measured over a wide range of microwave frequencies. The test structures were prepared by spin-coating sol-gel films onto metallized glass substrates. The dielectric properties of the sol-gel were probed with several different sets of coplanar waveguides (CPWs) electroplated onto sol-gel films. The dielectric constant and loss-tangent of these films were determined to be ˜3.1 and 3 x 10-3 at 35GHz. These results are very promising indicating that sol-gels are viable cladding materials for high-speed electro-optic polymer modulators (>40GHz).

Add/drop filters based on SiC technology for optical interconnects

NASA Astrophysics Data System (ADS)

Vieira, M.; Vieira, M. A.; Louro, P.; Fantoni, A.; Silva, V.

2014-03-01

In this paper we demonstrate an add/drop filter based on SiC technology. Tailoring of the channel bandwidth and wavelength is experimentally demonstrated. The concept is extended to implement a 1 by 4 wavelength division multiplexer with channel separation in the visible range. The device consists of a p-i'(a-SiC:H)-n/p-i(a-Si:H)-n heterostructure. Several monochromatic pulsed lights, separately or in a polychromatic mixture illuminated the device. Independent tuning of each channel is performed by steady state violet bias superimposed either from the front and back sides. Results show that, front background enhances the light-to-dark sensitivity of the long and medium wavelength channels and quench strongly the others. Back violet background has the opposite behaviour. This nonlinearity provides the possibility for selective removal or addition of wavelengths. An optoelectronic model is presented and explains the light filtering properties of the add/drop filter, under different optical bias conditions.

Field programmable analog array based on current differencing transconductance amplifiers and its application to high-order filter

NASA Astrophysics Data System (ADS)

He, Haizhen; Luo, Rongming; Hu, Zhenhua; Wen, Lei

2017-07-01

A current-mode field programmable analog array(FPAA) is presented in this paper. The proposed FPAA consists of 9 configurable analog blocks(CABs) which are based on current differencing transconductance amplifiers (CDTA) and trans-impedance amplifier (TIA). The proposed CABs interconnect through global lines. These global lines contain some bridge switches, which used to reduce the parasitic capacitance effectively. High-order current-mode low-pass and band-pass filter with transmission zeros based on the simulation of general passive RLC ladder prototypes is proposed and mapped into the FPAA structure in order to demonstrate the versatility of the FPAA. These filters exhibit good performance on bandwidth. Filter's cutoff frequency can be tuned from 1.2MHz to 40MHz.The proposed FPAA is simulated in a standard Charted 0.18μm CMOS process with +/-1.2V power supply to confirm the presented theory, and the results have good agreement with the theoretical analysis.

Antenna-coupled photon emission from hexagonal boron nitride tunnel junctions.

PubMed

Parzefall, M; Bharadwaj, P; Jain, A; Taniguchi, T; Watanabe, K; Novotny, L

2015-12-01

The ultrafast conversion of electrical signals to optical signals at the nanoscale is of fundamental interest for data processing, telecommunication and optical interconnects. However, the modulation bandwidths of semiconductor light-emitting diodes are limited by the spontaneous recombination rate of electron-hole pairs, and the footprint of electrically driven ultrafast lasers is too large for practical on-chip integration. A metal-insulator-metal tunnel junction approaches the ultimate size limit of electronic devices and its operating speed is fundamentally limited only by the tunnelling time. Here, we study the conversion of electrons (localized in vertical gold-hexagonal boron nitride-gold tunnel junctions) to free-space photons, mediated by resonant slot antennas. Optical antennas efficiently bridge the size mismatch between nanoscale volumes and far-field radiation and strongly enhance the electron-photon conversion efficiency. We achieve polarized, directional and resonantly enhanced light emission from inelastic electron tunnelling and establish a novel platform for studying the interaction of electrons with strongly localized electromagnetic fields.

A new planar broadband antenna based on meandered line loops for portable wireless communication devices

NASA Astrophysics Data System (ADS)

Alibakhshi-Kenari, Mohammad; Naser-Moghadasi, Mohammad; Sadeghzadeh, R. A.; Virdee, Bal S.; Limiti, Ernesto

2016-07-01

This article presents the design of a novel planar antenna structure comprising two pairs of interconnected meandered line loops that are grounded to a truncated T-shaped ground plane through two via holes. The T-shaped ground plane is used as a reflector to enhance the performance of the antenna. The resulting antenna is compact occupying an area of 38.5 × 36.6 mm2 (0.070λo × 0.067λo), where free-space wavelength is 550 MHz. The antenna radiates omnidirectionally in the E plane across its operational bandwidth (550 MHz to 3.85 GHz) with peak gain and efficiency of 5.5 dBi and 90.1%, respectively, at 2.35 GHz and reflection coefficient better than -10 dB. These characteristics make the antenna suitable for numerous applications, in particular, JCDMA, UHF RFID, GSM 900, GPS, KPCS, DCS, IMT-2000, WiMAX, WiFi, and Bluetooth.

Photonics for aerospace sensors

NASA Astrophysics Data System (ADS)

Pellegrino, John; Adler, Eric D.; Filipov, Andree N.; Harrison, Lorna J.; van der Gracht, Joseph; Smith, Dale J.; Tayag, Tristan J.; Viveiros, Edward A.

1992-11-01

The maturation in the state-of-the-art of optical components is enabling increased applications for the technology. Most notable is the ever-expanding market for fiber optic data and communications links, familiar in both commercial and military markets. The inherent properties of optics and photonics, however, have suggested that components and processors may be designed that offer advantages over more commonly considered digital approaches for a variety of airborne sensor and signal processing applications. Various academic, industrial, and governmental research groups have been actively investigating and exploiting these properties of high bandwidth, large degree of parallelism in computation (e.g., processing in parallel over a two-dimensional field), and interconnectivity, and have succeeded in advancing the technology to the stage of systems demonstration. Such advantages as computational throughput and low operating power consumption are highly attractive for many computationally intensive problems. This review covers the key devices necessary for optical signal and image processors, some of the system application demonstration programs currently in progress, and active research directions for the implementation of next-generation architectures.

A self-assembled microbonded germanium/silicon heterojunction photodiode for 25 Gb/s high-speed optical interconnects

PubMed Central

Tseng, Chih-Kuo; Chen, Wei-Ting; Chen, Ku-Hung; Liu, Han-Din; Kang, Yimin; Na, Neil; Lee, Ming-Chang M.

2013-01-01

A novel technique using surface tension to locally bond germanium (Ge) on silicon (Si) is presented for fabricating high performance Ge/Si photodiodes. Surface tension is a cohesive force among liquid molecules that tends to bring contiguous objects in contact to maintain a minimum surface energy. We take advantage of this phenomenon to fabricate a heterojunction optoelectronic device where the lattice constants of joined semiconductors are different. A high-speed Ge/Si heterojunction waveguide photodiode is presented by microbonding a beam-shaped Ge, first grown by rapid-melt-growth (RMG) method, on top of a Si waveguide via surface tension. Excellent device performances such as an operating bandwidth of 17 GHz and a responsivity of 0.66 and 0.70 A/W at the reverse bias of −4 and −6 V, respectively, are demonstrated. This technique can be simply implemented via modern complementary metal-oxide-semiconductor (CMOS) fabrication technologies for integrating Ge on Si devices. PMID:24232956

Design and Benchmarking of a Network-In-the-Loop Simulation for Use in a Hardware-In-the-Loop System

NASA Technical Reports Server (NTRS)

Aretskin-Hariton, Eliot; Thomas, George; Culley, Dennis; Kratz, Jonathan

2017-01-01

Distributed engine control (DEC) systems alter aircraft engine design constraints because of fundamental differences in the input and output communication between DEC and centralized control architectures. The change in the way communication is implemented may create new optimum engine-aircraft configurations. This paper continues the exploration of digital network communication by demonstrating a Network-In-the-Loop simulation at the NASA Glenn Research Center. This simulation incorporates a real-time network protocol, the Engine Area Distributed Interconnect Network Lite (EADIN Lite), with the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k) software. The objective of this study is to assess digital control network impact to the control system. Performance is evaluated relative to a truth model for large transient maneuvers and a typical flight profile for commercial aircraft. Results show that a decrease in network bandwidth from 250 Kbps (sampling all sensors every time step) to 40 Kbps, resulted in very small differences in control system performance.

Design and Benchmarking of a Network-In-the-Loop Simulation for Use in a Hardware-In-the-Loop System

NASA Technical Reports Server (NTRS)

Aretskin-Hariton, Eliot D.; Thomas, George Lindsey; Culley, Dennis E.; Kratz, Jonathan L.

2017-01-01

Distributed engine control (DEC) systems alter aircraft engine design constraints be- cause of fundamental differences in the input and output communication between DEC and centralized control architectures. The change in the way communication is implemented may create new optimum engine-aircraft configurations. This paper continues the exploration of digital network communication by demonstrating a Network-In-the-Loop simulation at the NASA Glenn Research Center. This simulation incorporates a real-time network protocol, the Engine Area Distributed Interconnect Network Lite (EADIN Lite), with the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k) software. The objective of this study is to assess digital control network impact to the control system. Performance is evaluated relative to a truth model for large transient maneuvers and a typical flight profile for commercial aircraft. Results show that a decrease in network bandwidth from 250 Kbps (sampling all sensors every time step) to 40 Kbps, resulted in very small differences in control system performance.

Surface-Wave Pulse Routing around Sharp Right Angles

NASA Astrophysics Data System (ADS)

Gao, Z.; Xu, H.; Gao, F.; Zhang, Y.; Luo, Y.; Zhang, B.

2018-04-01

Surface-plasmon polaritons (SPPs), or localized electromagnetic surface waves propagating on a metal-dielectric interface, are deemed promising information carriers for future subwavelength terahertz and optical photonic circuitry. However, surface waves fundamentally suffer from scattering loss when encountering sharp corners in routing and interconnection of photonic signals. Previous approaches enabling scattering-free surface-wave guidance around sharp corners are limited to either volumetric waveguide environments or extremely narrow bandwidth, being unable to guide a surface-wave pulse (SPP wave packet) on an on-chip platform. Here, in a surface-wave band-gap crystal implemented on a single metal surface, we demonstrate in time-domain routing a surface-wave pulse around multiple sharp right angles without perceptible scattering. Our work not only offers a solution to on-chip surface-wave pulse routing along an arbitrary path, but it also provides spatiotemporal information on the interplay between surface-wave pulses and sharp corners, both of which are desirable in developing high-performance large-scale integrated photonic circuits.

A Gigabit-per-Second Ka-Band Demonstration Using a Reconfigurable FPGA Modulator

NASA Technical Reports Server (NTRS)

Lee, Dennis; Gray, Andrew A.; Kang, Edward C.; Tsou, Haiping; Lay, Norman E.; Fong, Wai; Fisher, Dave; Hoy, Scott

2005-01-01

Gigabit-per-second communications have been a desired target for future NASA Earth science missions, and for potential manned lunar missions. Frequency bandwidth at S-band and X-band is typically insufficient to support missions at these high data rates. In this paper, we present the results of a 1 Gbps 32-QAM end-to-end experiment at Ka-band using a reconfigurable Field Programmable Gate Array (FPGA) baseband modulator board. Bit error rate measurements of the received signal using a software receiver demonstrate the feasibility of using ultra-high data rates at Ka-band, although results indicate that error correcting coding and/or modulator predistortion must be implemented in addition. Also, results of the demonstration validate the low-cost, MOS-based reconfigurable modulator approach taken to development of a high rate modulator, as opposed to more expensive ASIC or pure analog approaches.

Advances in HgCdTe APDs and LADAR Receivers

NASA Technical Reports Server (NTRS)

Bailey, Steven; McKeag, William; Wang, Jinxue; Jack, Michael; Amzajerdian, Farzin

2010-01-01

Raytheon is developing NIR sensor chip assemblies (SCAs) for scanning and staring 3D LADAR systems. High sensitivity is obtained by integrating high performance detectors with gain i.e. APDs with very low noise Readout Integrated Circuits. Unique aspects of these designs include: independent acquisition (non-gated) of pulse returns, multiple pulse returns with both time and intensity reported to enable full 3D reconstruction of the image. Recent breakthrough in device design has resulted in HgCdTe APDs operating at 300K with essentially no excess noise to gains in excess of 100, low NEP <1nW and GHz bandwidths and have demonstrated linear mode photon counting. SCAs utilizing these high performance APDs have been integrated and demonstrated excellent spatial and range resolution enabling detailed 3D imagery both at short range and long ranges. In this presentation we will review progress in high resolution scanning, staring and ultra-high sensitivity photon counting LADAR sensors.

Chaos Through-Wall Imaging Radar

NASA Astrophysics Data System (ADS)

Xu, Hang; Wang, Bingjie; Zhang, Jianguo; Liu, Li; Li, Ying; Wang, Yuncai; Wang, Anbang

2017-12-01

We experimentally demonstrate a chaos through-wall imaging radar using ultra-wideband chaotic-pulse-position modulation (CPPM) microwave signal. The CPPM signal based on logistic map with 1-ns pulse width and 1-GHz bandwidth is implemented by a field programmable gate array (FPGA) and then up-converted as the radar transmitting signal. Two-dimensional image of human objects behind obstacles is obtained by correlation method and back projection algorithm. Our experiments successfully perform through-wall imaging for single and multiple human objects through 20-cm thick wall. The down-range resolution of the proposed radar is 15 cm. Furthermore, the anti-jamming properties of the proposed radar in CPPM jamming, linear frequency-modulated jamming, and Gaussian noise jamming environments are demonstrated by electromagnetic simulations using the finite-difference time-domain. The simulation results show the CPPM microwave signal possesses excellent jamming immunity to the noise and radio frequency interference, which makes it perform superbly in multiradar environments.

The versatile GBT astronomical spectrometer (VEGAS): Current status and future plans

NASA Astrophysics Data System (ADS)

Prestage, Richard M.; Bloss, Marty; Brandt, Joe; Chen, Hong; Creager, Ray; Demorest, Paul; Ford, John; Jones, Glenn; Kepley, Amanda; Kobelski, Adam; Marganian, Paul; Mello, Melinda; McMahon, David; McCullough, Randy; Ray, Jason; Roshi, D. Anish; Werthimer, Dan; Whitehead, Mark

2015-07-01

The VEGAS multi-beam spectrometer (VEGAS) was built for the Green Bank Telescope (GBT) through a partnership between the National Radio Astronomy Observatory (NRAO) and the University of California at Berkeley. VEGAS is based on a Field Programmable Gate Array (FPGA) frontend and a heterogeneous computing backend comprised of Graphical Processing Units (GPUs) and CPUs. This system provides processing power to analyze up to 8 dual-polarization or 16 single-polarization inputs at bandwidths of up to 1.25 GHz per input. VEGAS was released for "shared-risk" observing in March 2014 and it became the default GBT spectral line backend in August 2014. Some of the early VEGAS observations include the Radio Ammonia Mid-Plane Survey, mapping of HCN/HCO+ in nearby galaxies, and a variety of radio-recombination line and pulsar projects. We will present some of the latest VEGAS science highlights.

A wideband CMOS single-ended low noise amplifier employing negative resistance technique

NASA Astrophysics Data System (ADS)

Guo, Benqing; Chen, Hongpeng; Wang, Xuebing; Chen, Jun; Li, Yueyue; Jin, Haiyan; Yang, Yongjun

2018-02-01

A wideband common-gate CMOS low noise amplifier with negative resistance technique is proposed. A novel single-ended negative resistance structure is employed to improve gain and noise of the LNA. The inductor resonating is adopted at the input stage and load stage to meet wideband matching and compensate gain roll-off at higher frequencies. Implemented in a 0.18 μm CMOS technology, the proposed LNA demonstrates in simulations a maximal gain of 16.4 dB across the 3 dB bandwidth of 0.2-3 GHz. The in-band noise figure of 3.4-4.7 dB is obtained while the IIP3 of 5.3-6.8 dBm and IIP2 of 12.5-17.2 dBm are post-simulated in the designed frequency band. The LNA core consumes a power dissipation of 3.8 mW under a 1.5 V power supply.

Device simulation of GeSn/GeSiSn pocket n-type tunnel field-effect transistor for analog and RF applications

NASA Astrophysics Data System (ADS)

Wang, Suyuan; Zheng, Jun; Xue, Chunlai; Li, Chuanbo; Zuo, Yuhua; Cheng, Buwen; Wang, Qiming

2017-11-01

We present the device simulations of analog and radio frequency (RF) performances of four double-gate pocket n-type tunneling field-effect transistors (NTFETs). The direct current (DC), analog and RF performances of the Ge-homo, GeSn-homo, GeSn/Ge and GeSn/GeSiSn NTFETs, are compared. The GeSn NTFETs greatly improve the on-state current (ION) and average subthreshold slope (SS), when compared with the Ge NTFET. Moreover, the GeSn/GeSiSn NTFET has the largest intrinsic gain (Av), and exhibits a suppressed ambipolar behavior, improved cut-off frequency (fT), and gain bandwidth product (GBW), according to the analyzed analog and RF figures of merit (FOM). Therefore, it can be concluded that the GeSn/GeSiSn NTFET has great potential as a promising candidate for the realization of future generation low-power analog/RF applications.

Fast, noise-free memory for photon synchronization at room temperature.

PubMed

Finkelstein, Ran; Poem, Eilon; Michel, Ohad; Lahad, Ohr; Firstenberg, Ofer

2018-01-01

Future quantum photonic networks require coherent optical memories for synchronizing quantum sources and gates of probabilistic nature. We demonstrate a fast ladder memory (FLAME) mapping the optical field onto the superposition between electronic orbitals of rubidium vapor. Using a ladder-level system of orbital transitions with nearly degenerate frequencies simultaneously enables high bandwidth, low noise, and long memory lifetime. We store and retrieve 1.7-ns-long pulses, containing 0.5 photons on average, and observe short-time external efficiency of 25%, memory lifetime (1/ e ) of 86 ns, and below 10 -4 added noise photons. Consequently, coupling this memory to a probabilistic source would enhance the on-demand photon generation probability by a factor of 12, the highest number yet reported for a noise-free, room temperature memory. This paves the way toward the controlled production of large quantum states of light from probabilistic photon sources.

Measurement of Spectral Broadening in PTS-Polydiacetylene

NASA Astrophysics Data System (ADS)

Bhowmik, Achintya; Thakur, Mrinal

1998-03-01

PTS-polydiacetylene has significant potential for future applications in ultrafast all-optical switches and logic gates.(R. Quintero-Torres and M. Thakur, Appl. Phys. Lett., 66, 1310 (1995).) In this work, we have made detailed measurements of the instantaneous spectral line broadening in a 500 μm thick PTS single-crystal as a function of intensity and wavelength. A mode-locked Ti-Sapphire laser with 2 ps pulse-width at 82 MHz repetition rate, and a Nd:YAG laser with 60 ps pulse-width at 10 Hz repetition rate were used for measurements at 720-840 nm and 1064 nm wavelength respectively. The spectral bandwidth of the beam was recorded before and after passing through the PTS single-crystal by a high-resolution spectrometer. The nonlinear refractive index (n_2) of PTS as a function of wavelength has been determined from the spectral broadening data.

System-level power optimization for real-time distributed embedded systems

NASA Astrophysics Data System (ADS)

Luo, Jiong

Power optimization is one of the crucial design considerations for modern electronic systems. In this thesis, we present several system-level power optimization techniques for real-time distributed embedded systems, based on dynamic voltage scaling, dynamic power management, and management of peak power and variance of the power profile. Dynamic voltage scaling has been widely acknowledged as an important and powerful technique to trade off dynamic power consumption and delay. Efficient dynamic voltage scaling requires effective variable-voltage scheduling mechanisms that can adjust voltages and clock frequencies adaptively based on workloads and timing constraints. For this purpose, we propose static variable-voltage scheduling algorithms utilizing criticalpath driven timing analysis for the case when tasks are assumed to have uniform switching activities, as well as energy-gradient driven slack allocation for a more general scenario. The proposed techniques can achieve closeto-optimal power savings with very low computational complexity, without violating any real-time constraints. We also present algorithms for power-efficient joint scheduling of multi-rate periodic task graphs along with soft aperiodic tasks. The power issue is addressed through both dynamic voltage scaling and power management. Periodic task graphs are scheduled statically. Flexibility is introduced into the static schedule to allow the on-line scheduler to make local changes to PE schedules through resource reclaiming and slack stealing, without interfering with the validity of the global schedule. We provide a unified framework in which the response times of aperiodic tasks and power consumption are dynamically optimized simultaneously. Interconnection network fabrics point to a new generation of power-efficient and scalable interconnection architectures for distributed embedded systems. As the system bandwidth continues to increase, interconnection networks become power/energy limited as well. Variable-frequency links have been designed by circuit designers for both parallel and serial links, which can adaptively regulate the supply voltage of transceivers to a desired link frequency, to exploit the variations in bandwidth requirement for power savings. We propose solutions for simultaneous dynamic voltage scaling of processors and links. The proposed solution considers real-time scheduling, flow control, and packet routing jointly. It can trade off the power consumption on processors and communication links via efficient slack allocation, and lead to more power savings than dynamic voltage scaling on processors alone. For battery-operated systems, the battery lifespan is an important concern. Due to the effects of discharge rate and battery recovery, the discharge pattern of batteries has an impact on the battery lifespan. Battery models indicate that even under the same average power consumption, reducing peak power current and variance in the power profile can increase the battery efficiency and thereby prolong battery lifetime. To take advantage of these effects, we propose battery-driven scheduling techniques for embedded applications, to reduce the peak power and the variance in the power profile of the overall system under real-time constraints. The proposed scheduling algorithms are also beneficial in addressing reliability and signal integrity concerns by effectively controlling peak power and variance of the power profile.

Hidden Markov analysis of mechanosensitive ion channel gating.

PubMed

Khan, R Nazim; Martinac, Boris; Madsen, Barry W; Milne, Robin K; Yeo, Geoffrey F; Edeson, Robert O

2005-02-01

Patch clamp data from the large conductance mechanosensitive channel (MscL) in E. coli was studied with the aim of developing a strategy for statistical analysis based on hidden Markov models (HMMs) and determining the number of conductance levels of the channel, together with mean current, mean dwell time and equilibrium probability of occupancy for each level. The models incorporated state-dependent white noise and moving average adjustment for filtering, with maximum likelihood parameter estimates obtained using an EM (expectation-maximisation) based iteration. Adjustment for filtering was included as it could be expected that the electronic filter used in recording would have a major effect on obviously brief intermediate conductance level sojourns. Preliminary data analysis revealed that the brevity of intermediate level sojourns caused difficulties in assignment of data points to levels as a result of over-estimation of noise variances. When reasonable constraints were placed on these variances using the better determined noise variances for the closed and fully open levels, idealisation anomalies were eliminated. Nevertheless, simulations suggested that mean sojourn times for the intermediate levels were still considerably over-estimated, and that recording bandwidth was a major limitation; improved results were obtained with higher bandwidth data (10 kHz sampled at 25 kHz). The simplest model consistent with these data had four open conductance levels, intermediate levels being approximately 20%, 51% and 74% of fully open. The mean lifetime at the fully open level was about 1 ms; estimates for the three intermediate levels were 54-92 micros, probably still over-estimates.

Bioelectrical coupling in multicellular domains regulated by gap junctions: A conceptual approach.

PubMed

Cervera, Javier; Pietak, Alexis; Levin, Michael; Mafe, Salvador

2018-04-21

We review the basic concepts involved in bioelectrically-coupled multicellular domains, focusing on the role of membrane potentials (V mem ). In the first model, single-cell V mem is modulated by two generic polarizing and depolarizing ion channels, while intercellular coupling is implemented via voltage-gated gap junctions. Biochemical and bioelectrical signals are integrated via a feedback loop between V mem and the transcription and translation of a protein forming an ion channel. The effective rate constants depend on the single-cell V mem because these potentials modulate the local concentrations of signaling molecules and ions. This electrochemically-based idealization of the complex biophysical problem suggests that the spatio-temporal map of single-cell potentials can influence downstream patterning processes by means of the voltage-gated gap junction interconnectivity, much as in the case of electronic devices where the control of electric potentials and currents allows the local modulation of the circuitry to achieve full functionality. An alternative theoretical approach, the BioElectrical Tissue Simulation Engine (BETSE), is also presented. The BETSE modeling environment utilizes finite volume techniques to simulate bioelectric states from the perspective of ion concentrations and fluxes. This model has been successfully applied to make predictions and explain experimental observations in a variety of embryonic, regenerative, and oncogenic contexts. Copyright © 2018 Elsevier B.V. All rights reserved.

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

1989-01-01

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Quartz crystal fabrication facility

NASA Astrophysics Data System (ADS)

Ney, R. J.

1980-05-01

The report describes the design and operation of a five chamber, interconnected vacuum system, which is capable of cleaning, plating, and sealing precision quartz crystal units in ceramic flatpack enclosures continuously in a high vacuum environment. The production rate design goal was 200 units per eight hour day. A unique nozzle beam gold deposition source was developed to operate for extended periods of time without reloading. The source puts out a narrow beam of gold typically in the order of 2 1/2 deg included cone angle. Maximum deposition rates are in the order of 400 a/min at 5.5 in. 'throw' distance used. Entrance and exit air lock chambers expedite the material throughput, so that the processing chambers are at high vacuum for extended periods of time. A stainless steel conveyor belt, in conjunction with three vacuum manipulators, transport the resonator components to the various work stations. Individual chambers are normally separated from each other by gate valves. The crystal resonators, mounted in flatpack frames but unplated, are loaded into transport trays in a lid-frame-lid sequency for insertion into the system and exit as completed crystal units. The system utilizes molybdenum coated ball bearings at essentially all friction surfaces. The gold sources and plating mask heads are equipped with elevators and gate valves, so that they can be removed from the system for maintenance without exposing the chambers to atmosphere.

Heterogeneous integration of low-temperature metal-oxide TFTs

NASA Astrophysics Data System (ADS)

Schuette, Michael L.; Green, Andrew J.; Leedy, Kevin D.; McCandless, Jonathan P.; Jessen, Gregg H.

2017-02-01

The breadth of circuit fabrication opportunities enabled by metal-oxide thin-film transistors (MO-TFTs) is unprecedented. Large-area deposition techniques and high electron mobility are behind their adoption in the display industry, and substrate agnosticism and low process temperatures enabled the present wave of flexible electronics research. Reports of circuits involving complementaryMO-TFTs, oxide-organic hybrid combinations, and even MO-TFTs integrated onto Si LSI back end of line interconnects demonstrate this technology's utility in 2D and 3D monolithic heterogeneous integration (HI). In addition to a brief literature review focused on functional HI between MO-TFTs and a variety of dissimilar active devices, we share progress toward integrating MO-TFTs with compound semiconductor devices, namely GaN HEMTs. A monolithically integrated cascode topology was used to couple a HEMT's >200 V breakdown characteristic with the gate driving characteristic of an IGZO TFT, effectively shifting the HEMT threshold voltage from -3 V to +1 V.

Electrical control of spin dynamics in finite one-dimensional systems

NASA Astrophysics Data System (ADS)

Pertsova, A.; Stamenova, M.; Sanvito, S.

2011-10-01

We investigate the possibility of the electrical control of spin transfer in monoatomic chains incorporating spin impurities. Our theoretical framework is the mixed quantum-classical (Ehrenfest) description of the spin dynamics, in the spirit of the s-d model, where the itinerant electrons are described by a tight-binding model while localized spins are treated classically. Our main focus is on the dynamical exchange interaction between two well-separated spins. This can be quantified by the transfer of excitations in the form of transverse spin oscillations. We systematically study the effect of an electrostatic gate bias Vg on the interconnecting channel and we map out the long-range dynamical spin transfer as a function of Vg. We identify regions of Vg giving rise to significant amplification of the spin transmission at low frequencies and relate this to the electronic structure of the channel.

Spin switches for compact implementation of neuron and synapse

NASA Astrophysics Data System (ADS)

Quang Diep, Vinh; Sutton, Brian; Behin-Aein, Behtash; Datta, Supriyo

2014-06-01

Nanomagnets driven by spin currents provide a natural implementation for a neuron and a synapse: currents allow convenient summation of multiple inputs, while the magnet provides the threshold function. The objective of this paper is to explore the possibility of a hardware neural network implementation using a spin switch (SS) as its basic building block. SS is a recently proposed device based on established technology with a transistor-like gain and input-output isolation. This allows neural networks to be constructed with purely passive interconnections without intervening clocks or amplifiers. The weights for the neural network are conveniently adjusted through analog voltages that can be stored in a non-volatile manner in an underlying CMOS layer using a floating gate low dropout voltage regulator. The operation of a multi-layer SS neural network designed for character recognition is demonstrated using a standard simulation model based on coupled Landau-Lifshitz-Gilbert equations, one for each magnet in the network.

Voltage regulation and power losses reduction in a wind farm integrated MV distribution network

NASA Astrophysics Data System (ADS)

Fandi, Ghaeth; Igbinovia, Famous Omar; Tlusty, Josef; Mahmoud, Rateb

2018-01-01

A medium-voltage (MV) wind production system is proposed in this paper. The system applies a medium-voltage permanent magnet synchronous generator (PMSG) as well as MV interconnection and distribution networks. The simulation scheme of an existing commercial electric-power system (Case A) and a proposed wind farm with a gearless PMSG insulated gate bipolar transistor (IGBT) power electronics converter scheme (Case B) is compared. The analyses carried out in MATLAB/Simulink environment shows an enhanced voltage profile and reduced power losses, thus, efficiency in installed IGBT power electronics devices in the wind farm. The resulting wind energy transformation scheme is a simple and controllable medium voltage application since it is not restrained by the IGBT power electronics voltage source converter (VSC) arrangement. Active and reactive power control is made possible with the aid of the gearless PMSG IGBT power converters.

PCI-based WILDFIRE reconfigurable computing engines

NASA Astrophysics Data System (ADS)

Fross, Bradley K.; Donaldson, Robert L.; Palmer, Douglas J.

1996-10-01

WILDFORCE is the first PCI-based custom reconfigurable computer that is based on the Splash 2 technology transferred from the National Security Agency and the Institute for Defense Analyses, Supercomputing Research Center (SRC). The WILDFORCE architecture has many of the features of the WILDFIRE computer, such as field- programmable gate array (FPGA) based processing elements, linear array and crossbar interconnection, and high- performance memory and I/O subsystems. New features introduced in the PCI-based WILDFIRE systems include memory/processor options that can be added to any processing element. These options include static and dynamic memory, digital signal processors (DSPs), FPGAs, and microprocessors. In addition to memory/processor options, many different application specific connectors can be used to extend the I/O capabilities of the system, including systolic I/O, camera input and video display output. This paper also discusses how this new PCI-based reconfigurable computing engine is used for rapid-prototyping, real-time video processing and other DSP applications.

Monolithic integration of GaN-based light-emitting diodes and metal-oxide-semiconductor field-effect transistors.

PubMed

Lee, Ya-Ju; Yang, Zu-Po; Chen, Pin-Guang; Hsieh, Yung-An; Yao, Yung-Chi; Liao, Ming-Han; Lee, Min-Hung; Wang, Mei-Tan; Hwang, Jung-Min

2014-10-20

In this study, we report a novel monolithically integrated GaN-based light-emitting diode (LED) with metal-oxide-semiconductor field-effect transistor (MOSFET). Without additionally introducing complicated epitaxial structures for transistors, the MOSFET is directly fabricated on the exposed n-type GaN layer of the LED after dry etching, and serially connected to the LED through standard semiconductor-manufacturing technologies. Such monolithically integrated LED/MOSFET device is able to circumvent undesirable issues that might be faced by other kinds of integration schemes by growing a transistor on an LED or vice versa. For the performances of resulting device, our monolithically integrated LED/MOSFET device exhibits good characteristics in the modulation of gate voltage and good capability of driving injected current, which are essential for the important applications such as smart lighting, interconnection, and optical communication.

Hybrid quantum systems: Outsourcing superconducting qubits

NASA Astrophysics Data System (ADS)

Cleland, Andrew

Superconducting qubits offer excellent prospects for manipulating quantum information, with good qubit lifetimes, high fidelity single- and two-qubit gates, and straightforward scalability (admittedly with multi-dimensional interconnect challenges). One interesting route for experimental development is the exploration of hybrid systems, i.e. coupling superconducting qubits to other systems. I will report on our group's efforts to develop approaches that will allow interfacing superconducting qubits in a quantum-coherent fashion to spin defects in solids, to optomechanical devices, and to resonant nanomechanical structures. The longer term goals of these efforts include transferring quantum states between different qubit systems; generating and receiving ``flying'' acoustic phonon-based as well as optical photon-based qubits; and ultimately developing systems that can be used for quantum memory, quantum computation and quantum communication, the last in both the microwave and fiber telecommunications bands. Work is supported by Grants from AFOSR, ARO, DOE and NSF.

Optical, analog and digital domain architectural considerations for visual communications

NASA Astrophysics Data System (ADS)

Metz, W. A.

2008-01-01

The end of the performance entitlement historically achieved by classic scaling of CMOS devices is within sight, driven ultimately by fundamental limits. Performance entitlements predicted by classic CMOS scaling have progressively failed to be realized in recent process generations due to excessive leakage, increasing interconnect delays and scaling of gate dielectrics. Prior to reaching fundamental limits, trends in technology, architecture and economics will pressure the industry to adopt new paradigms. A likely response is to repartition system functions away from digital implementations and into new architectures. Future architectures for visual communications will require extending the implementation into the optical and analog processing domains. The fundamental properties of these domains will in turn give rise to new architectural concepts. The limits of CMOS scaling and impact on architectures will be briefly reviewed. Alternative approaches in the optical, electronic and analog domains will then be examined for advantages, architectural impact and drawbacks.

Flexible Peripheral Component Interconnect Input/Output Card

NASA Technical Reports Server (NTRS)

Bigelow, Kirk K.; Jerry, Albert L.; Baricio, Alisha G.; Cummings, Jon K.

2010-01-01

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

Preface

NASA Astrophysics Data System (ADS)

Zhuge, Qunbi; Chen, Xi

2018-02-01

Global IP traffic is predicted to increase nearly threefold over the next 5 years, driven by emerging high-bandwidth-demanding applications, such as cloud computing, 5G wireless, high-definition video streaming, and virtual reality. This results in a continuously increasing demand on the capacity of backbone optical networks. During the past decade, advanced digital signal processing (DSP), modulation formats, and forward error correction (FEC) were commercially realized to exploit the capacity potential of long-haul fiber channels, and have increased per channel data rate from 10 Gb/s to 400 Gb/s. DSP has played a crucial role in coherent transceivers to accommodate channel impairments including chromatic dispersion (CD), polarization mode dispersion (PMD), laser phase noise, fiber nonlinearities, clock jitter, and so forth. The advance of DSP has also enabled innovations in modulation formats to increase spectral efficiency, improve linear/nonlinear noise tolerance, and realize flexible bandwidth. Moving forward to next generation 1 Tb/s systems on conventional single mode fiber (SMF) platform, more innovations in DSP techniques are needed to further reduce cost per bit, increase network efficiency, and close the gap to the Shannon limit. To further increase capacity per fiber, spatial-division multiplexing (SDM) systems can be used. DSP techniques such as advanced channel equalization methods and distortion compensation can help SDM systems to achieve higher system capacity. In the area of short-reach transmission, the rapid increase of data center network traffic has driven the development of optical technologies for both intra- and inter-data center interconnects (DCI). In particular, DSP has been exploited in intensity-modulation direct detection (IM/DD) systems to realize 400 Gb/s pluggable optical transceivers. In addition, multi-dimensional direct detection modulation schemes are being investigated to increase the data rate per wavelength targeting 1 Tb/s interface.

The DYNES Instrument: A Description and Overview

NASA Astrophysics Data System (ADS)

Zurawski, Jason; Ball, Robert; Barczyk, Artur; Binkley, Mathew; Boote, Jeff; Boyd, Eric; Brown, Aaron; Brown, Robert; Lehman, Tom; McKee, Shawn; Meekhof, Benjeman; Mughal, Azher; Newman, Harvey; Rozsa, Sandor; Sheldon, Paul; Tackett, Alan; Voicu, Ramiro; Wolff, Stephen; Yang, Xi

2012-12-01

Scientific innovation continues to increase requirements for the computing and networking infrastructures of the world. Collaborative partners, instrumentation, storage, and processing facilities are often geographically and topologically separated, as is the case with LHC virtual organizations. These separations challenge the technology used to interconnect available resources, often delivered by Research and Education (R&E) networking providers, and leads to complications in the overall process of end-to-end data management. Capacity and traffic management are key concerns of R&E network operators; a delicate balance is required to serve both long-lived, high capacity network flows, as well as more traditional end-user activities. The advent of dynamic circuit services, a technology that enables the creation of variable duration, guaranteed bandwidth networking channels, allows for the efficient use of common network infrastructures. These gains are seen particularly in locations where overall capacity is scarce compared to the (sustained peak) needs of user communities. Related efforts, including those of the LHCOPN [3] operations group and the emerging LHCONE [4] project, may take advantage of available resources by designating specific network activities as a “high priority”, allowing reservation of dedicated bandwidth or optimizing for deadline scheduling and predicable delivery patterns. This paper presents the DYNES instrument, an NSF funded cyberinfrastructure project designed to facilitate end-to-end dynamic circuit services [2]. This combination of hardware and software innovation is being deployed across R&E networks in the United States at selected end-sites located on University Campuses. DYNES is peering with international efforts in other countries using similar solutions, and is increasing the reach of this emerging technology. This global data movement solution could be integrated into computing paradigms such as cloud and grid computing platforms, and through the use of APIs can be integrated into existing data movement software.

VCSELs for optical communication at Fuji Xerox

NASA Astrophysics Data System (ADS)

Kondo, Takashi; Hayakawa, Junichiro; Jogan, Naoki; Murakami, Akemi; Sakurai, Jun; Gu, Xiaodong; Koyama, Fumio

2017-02-01

We introduce the characteristics of vertical-cavity surface-emitting lasers (VCSELs) for use in optical communications. In the field of optical interconnections and networks, 850 nm VCSELs are key optical transmitters due to their high-speed modulation and low power consumption. One promising candidate for achieving high-speed modulations exceeding 50 Gbps is the transverse-coupled-cavity (TCC) VCSEL. In this talk, we demonstrate the characteristics of 850 nm transverse-coupled-cavity VCSELs, which helped us achieve a high 3dB modulation bandwidth (30 GHz) at 0 °C and realize eye-opening at the large-signal modulation rate of 48 Gbps. The VCSEL's epilayer structure was grown by MOCVD. The active region consists of three strained InGaAs QWs surrounded by AlGaAs barriers. The n-type and p-type DBRs are composed of AlGaAs/AlGaAs, respectively. A line-shaped H+ ion was implanted at the center of the bowtie-shaped post, dividing it into two cavities. The threshold current of the TCC VCSEL with an oxide aperture of 3.6 μm is 0.33 mA. Only the left-side cavity is pumped, while the right cavity is unpumped. The effect of modulation bandwidth enhancement was observed over a wide temperature range of 120K thanks to an optical feedback in the coupled cavities. These results show the possibility of achieving high-speed VCSELs without any temperature or bias control. We also demonstrate an ultra-compact photodetector-integrated VCSEL with two laterally-coupled cavities. An output power and a photocurrent exhibit similar tendencies under a wide range of temperature changes. This device could be also used for monitoring output power without a conventional photodetector mounted separately.

Extending the BEAGLE library to a multi-FPGA platform

PubMed Central

2013-01-01

Background Maximum Likelihood (ML)-based phylogenetic inference using Felsenstein’s pruning algorithm is a standard method for estimating the evolutionary relationships amongst a set of species based on DNA sequence data, and is used in popular applications such as RAxML, PHYLIP, GARLI, BEAST, and MrBayes. The Phylogenetic Likelihood Function (PLF) and its associated scaling and normalization steps comprise the computational kernel for these tools. These computations are data intensive but contain fine grain parallelism that can be exploited by coprocessor architectures such as FPGAs and GPUs. A general purpose API called BEAGLE has recently been developed that includes optimized implementations of Felsenstein’s pruning algorithm for various data parallel architectures. In this paper, we extend the BEAGLE API to a multiple Field Programmable Gate Array (FPGA)-based platform called the Convey HC-1. Results The core calculation of our implementation, which includes both the phylogenetic likelihood function (PLF) and the tree likelihood calculation, has an arithmetic intensity of 130 floating-point operations per 64 bytes of I/O, or 2.03 ops/byte. Its performance can thus be calculated as a function of the host platform’s peak memory bandwidth and the implementation’s memory efficiency, as 2.03 × peak bandwidth × memory efficiency. Our FPGA-based platform has a peak bandwidth of 76.8 GB/s and our implementation achieves a memory efficiency of approximately 50%, which gives an average throughput of 78 Gflops. This represents a ~40X speedup when compared with BEAGLE’s CPU implementation on a dual Xeon 5520 and 3X speedup versus BEAGLE’s GPU implementation on a Tesla T10 GPU for very large data sizes. The power consumption is 92 W, yielding a power efficiency of 1.7 Gflops per Watt. Conclusions The use of data parallel architectures to achieve high performance for likelihood-based phylogenetic inference requires high memory bandwidth and a design methodology that emphasizes high memory efficiency. To achieve this objective, we integrated 32 pipelined processing elements (PEs) across four FPGAs. For the design of each PE, we developed a specialized synthesis tool to generate a floating-point pipeline with resource and throughput constraints to match the target platform. We have found that using low-latency floating-point operators can significantly reduce FPGA area and still meet timing requirement on the target platform. We found that this design methodology can achieve performance that exceeds that of a GPU-based coprocessor. PMID:23331707

Porous Diblock Copolymer Thin Films in High-Performance Semiconductor Microelectronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Black, C.T.

2011-02-01

The engine fueling more than 40 years of performance improvements in semiconductor integrated circuits (ICs) has been industry's ability to pattern circuit elements at ever-higher resolution and with ever-greater precision. Steady advances in photolithography - the process wherein ultraviolet light chemically changes a photosensitive polymer resist material in order to create a latent image - have resulted in scaling of minimum printed feature sizes from tens of microns during the 1980s to sub-50 nanometer transistor gate lengths in today's state-of-the-art ICs. The history of semiconductor technology scaling as well as future technology requirements is documented in the International Technology Roadmapmore » for Semiconductors (ITRS). The progression of the semiconductor industry to the realm of nanometer-scale sizes has brought enormous challenges to device and circuit fabrication, rendering performance improvements by conventional scaling alone increasingly difficult. Most often this discussion is couched in terms of field effect transistor (FET) feature sizes such as the gate length or gate oxide thickness, however these challenges extend to many other aspects of the IC, including interconnect dimensions and pitch, device packing density, power consumption, and heat dissipation. The ITRS Technology Roadmap forecasts a difficult set of scientific and engineering challenges with no presently-known solutions. The primary focus of this chapter is the research performed at IBM on diblock copolymer films composed of polystyrene (PS) and poly(methyl-methacrylate) (PMMA) (PS-b-PMMA) with total molecular weights M{sub n} in the range of {approx}60K (g/mol) and polydispersities (PD) of {approx}1.1. These materials self assemble to form patterns having feature sizes in the range of 15-20nm. PS-b-PMMA was selected as a self-assembling patterning material due to its compatibility with the semiconductor microelectronics manufacturing infrastructure, as well as the significant body of existing research on understanding its material properties.« less

The LER/LWR metrology challenge for advance process control through 3D-AFM and CD-SEM

NASA Astrophysics Data System (ADS)

Faurie, P.; Foucher, J.; Foucher, A.-L.

2009-12-01

The continuous shrinkage in dimensions of microelectronic devices has reached such level, with typical gate length in advance R&D of less than 20nm combine with the introduction of new architecture (FinFET, Double gate...) and new materials (porous interconnect material, 193 immersion resist, metal gate material, high k materials...), that new process parameters have to be well understood and well monitored to guarantee sufficient production yield in a near future. Among these parameters, there are the critical dimensions (CD) associated to the sidewall angle (SWA) values, the line edge roughness (LER) and the line width roughness (LWR). Thus, a new metrology challenge has appeared recently and consists in measuring "accurately" the fabricated patterns on wafers in addition to measure the patterns on a repeatable way. Therefore, a great effort has to be done on existing techniques like CD-SEM, Scatterometry and 3D-AFM in order to develop them following the two previous criteria: Repeatability and Accuracy. In this paper, we will compare the 3D-AFM and CD-SEM techniques as a mean to measure LER and LWR on silicon and 193 resist and point out CD-SEM impact on the material during measurement. Indeed, depending on the material type, the interaction between the electron beam and the material or between the AFM tip and the material can vary a lot and subsequently can generate measurements bias. The first results tend to show that depending on CD-SEM conditions (magnification, number of acquisition frames) the final outputs can vary on a large range and therefore show that accuracy in such measurements are really not obvious to obtain. On the basis of results obtained on various materials that present standard sidewall roughness, we will show the limit of each technique and will propose different ways to improve them in order to fulfil advance roadmap requirements for the development of the next IC generation.

Field-Programmable Gate Array Computer in Structural Analysis: An Initial Exploration

NASA Technical Reports Server (NTRS)

Singleterry, Robert C., Jr.; Sobieszczanski-Sobieski, Jaroslaw; Brown, Samuel

2002-01-01

This paper reports on an initial assessment of using a Field-Programmable Gate Array (FPGA) computational device as a new tool for solving structural mechanics problems. A FPGA is an assemblage of binary gates arranged in logical blocks that are interconnected via software in a manner dependent on the algorithm being implemented and can be reprogrammed thousands of times per second. In effect, this creates a computer specialized for the problem that automatically exploits all the potential for parallel computing intrinsic in an algorithm. This inherent parallelism is the most important feature of the FPGA computational environment. It is therefore important that if a problem offers a choice of different solution algorithms, an algorithm of a higher degree of inherent parallelism should be selected. It is found that in structural analysis, an 'analog computer' style of programming, which solves problems by direct simulation of the terms in the governing differential equations, yields a more favorable solution algorithm than current solution methods. This style of programming is facilitated by a 'drag-and-drop' graphic programming language that is supplied with the particular type of FPGA computer reported in this paper. Simple examples in structural dynamics and statics illustrate the solution approach used. The FPGA system also allows linear scalability in computing capability. As the problem grows, the number of FPGA chips can be increased with no loss of computing efficiency due to data flow or algorithmic latency that occurs when a single problem is distributed among many conventional processors that operate in parallel. This initial assessment finds the FPGA hardware and software to be in their infancy in regard to the user conveniences; however, they have enormous potential for shrinking the elapsed time of structural analysis solutions if programmed with algorithms that exhibit inherent parallelism and linear scalability. This potential warrants further development of FPGA-tailored algorithms for structural analysis.

Photonic crystal lasers using wavelength-scale embedded active region

NASA Astrophysics Data System (ADS)

Matsuo, Shinji; Sato, Tomonari; Takeda, Koji; Shinya, Akihiko; Nozaki, Kengo; Kuramochi, Eiichi; Taniyama, Hideaki; Notomi, Masaya; Fujii, Takuro; Hasebe, Koichi; Kakitsuka, Takaaki

2014-01-01

Lasers with ultra-low operating energy are desired for use in chip-to-chip and on-chip optical interconnects. If we are to reduce the operating energy, we must reduce the active volume. Therefore, a photonic crystal (PhC) laser with a wavelength-scale cavity has attracted a lot of attention because a PhC provides a large Q-factor with a small volume. To improve this device's performance, we employ an embedded active region structure in which the wavelength-scale active region is buried with an InP PhC slab. This structure enables us to achieve effective confinement of both carriers and photons, and to improve the thermal resistance of the device. Thus, we have obtained a large external differential quantum efficiency of 55% and an output power of -10 dBm by optical pumping. For electrical pumping, we use a lateral p-i-n structure that employs Zn diffusion and Si ion implantation for p-type and n-type doping, respectively. We have achieved room-temperature continuous-wave operation with a threshold current of 7.8 µA and a maximum 3 dB bandwidth of 16.2 GHz. The results of an experimental bit error rate measurement with a 10 Gbit s-1 NRZ signal reveal the minimum operating energy for transferring a single bit of 5.5 fJ. These results show the potential of this laser to be used for very short reach interconnects. We also describe the optimal design of cavity quality (Q) factor in terms of achieving a large output power with a low operating energy using a calculation based on rate equations. When we assume an internal absorption loss of 20 cm-1, the optimized coupling Q-factor is 2000.

Integration of the White Sands Complex into a Wide Area Network

NASA Technical Reports Server (NTRS)

Boucher, Phillip Larry; Horan, Sheila, B.

1996-01-01

The NASA White Sands Complex (WSC) satellite communications facility consists of two main ground stations, an auxiliary ground station, a technical support facility, and a power plant building located on White Sands Missile Range. When constructed, terrestrial communication access to these facilities was limited to copper telephone circuits. There was no local or wide area communications network capability. This project incorporated a baseband local area network (LAN) topology at WSC and connected it to NASA's wide area network using the Program Support Communications Network-Internet (PSCN-I). A campus-style LAN is configured in conformance with the International Standards Organization (ISO) Open Systems Interconnect (ISO) model. Ethernet provides the physical and data link layers. Transmission Control Protocol and Internet Protocol (TCP/IP) are used for the network and transport layers. The session, presentation, and application layers employ commercial software packages. Copper-based Ethernet collision domains are constructed in each of the primary facilities and these are interconnected by routers over optical fiber links. The network and each of its collision domains are shown to meet IEEE technical configuration guidelines. The optical fiber links are analyzed for the optical power budget and bandwidth allocation and are found to provide sufficient margin for this application. Personal computers and work stations attached to the LAN communicate with and apply a wide variety of local and remote administrative software tools. The Internet connection provides wide area network (WAN) electronic access to other NASA centers and the world wide web (WWW). The WSC network reduces and simplifies the administrative workload while providing enhanced and advanced inter-communications capabilities among White Sands Complex departments and with other NASA centers.

FPGA-accelerated adaptive optics wavefront control

NASA Astrophysics Data System (ADS)

Mauch, S.; Reger, J.; Reinlein, C.; Appelfelder, M.; Goy, M.; Beckert, E.; Tünnermann, A.

2014-03-01

The speed of real-time adaptive optical systems is primarily restricted by the data processing hardware and computational aspects. Furthermore, the application of mirror layouts with increasing numbers of actuators reduces the bandwidth (speed) of the system and, thus, the number of applicable control algorithms. This burden turns out a key-impediment for deformable mirrors with continuous mirror surface and highly coupled actuator influence functions. In this regard, specialized hardware is necessary for high performance real-time control applications. Our approach to overcome this challenge is an adaptive optics system based on a Shack-Hartmann wavefront sensor (SHWFS) with a CameraLink interface. The data processing is based on a high performance Intel Core i7 Quadcore hard real-time Linux system. Employing a Xilinx Kintex-7 FPGA, an own developed PCie card is outlined in order to accelerate the analysis of a Shack-Hartmann Wavefront Sensor. A recently developed real-time capable spot detection algorithm evaluates the wavefront. The main features of the presented system are the reduction of latency and the acceleration of computation For example, matrix multiplications which in general are of complexity O(n3 are accelerated by using the DSP48 slices of the field-programmable gate array (FPGA) as well as a novel hardware implementation of the SHWFS algorithm. Further benefits are the Streaming SIMD Extensions (SSE) which intensively use the parallelization capability of the processor for further reducing the latency and increasing the bandwidth of the closed-loop. Due to this approach, up to 64 actuators of a deformable mirror can be handled and controlled without noticeable restriction from computational burdens.

Broadband Ground Penetrating Radar with conformal antennas for subsurface imaging from a rover

NASA Astrophysics Data System (ADS)

Stillman, D. E.; Oden, C. P.; Grimm, R. E.; Ragusa, M.

2015-12-01

Ground-Penetrating Radar (GPR) allows subsurface imaging to provide geologic context and will be flown on the next two martian rovers (WISDOM on ExoMars and RIMFAX on Mars 2020). The motivation of our research is to minimize the engineering challenges of mounting a GPR antenna to a spacecraft, while maximizing the scientific capabilities of the GPR. The scientific capabilities increase with the bandwidth as it controls the resolution. Furthermore, ultra-wide bandwidth surveys allow certain mineralogies and rock units to be discriminated based on their frequency-dependent EM or scattering properties. We have designed and field-tested a prototype GPR that utilizes bi-static circularly polarized spiral antennas. Each antenna has a physical size of 61 x 61 x 4 cm, therefore two antennas could be mounted to the underbelly of a MSL-class rover. Spiral antennas were chosen because they have an inherent broadband response and provide a better low frequency response compared with similarly sized linearly polarized antennas. A horizontal spiral radiator emits energy both upward and downward directions. After the radiator is mounted to a metal surface (i.e. the underside of a rover), a cavity is formed that causes the upward traveling energy to reverberate and cause unwanted interference. This interference is minimized by 1) using a high metallization ratio on the spiral to reduce cavity emissions, and 2) placing absorbing material inside the cavity. The resulting antennas provide high gain (0 to 8 dBi) from 200 to 1000 MHz. The low frequency response can be improved by increasing the antenna thickness (i.e., cavity depth). In an initial field test, the antennas were combined with impulse GPR electronics that had ~140 dB of dynamic range (not including antennas) and a sand/clay interface 7 feet deep was detected. To utilize the full bandwidth the antennas, a gated Frequency Modulated Continuous Waveform system will be developed - similar to RIMFAX. The goal is to reach a total system dynamic range of 180 dB in order to provide significant penetration.

Outlook and emerging semiconducting materials for ambipolar transistors.

PubMed

Bisri, Satria Zulkarnaen; Piliego, Claudia; Gao, Jia; Loi, Maria Antonietta

2014-02-26

Ambipolar or bipolar transistors are transistors in which both holes and electrons are mobile inside the conducting channel. This device allows switching among several states: the hole-dominated on-state, the off-state, and the electron-dominated on-state. In the past year, it has attracted great interest in exotic semiconductors, such as organic semiconductors, nanostructured materials, and carbon nanotubes. The ability to utilize both holes and electrons inside one device opens new possibilities for the development of more compact complementary metal-oxide semiconductor (CMOS) circuits, and new kinds of optoelectronic device, namely, ambipolar light-emitting transistors. This progress report highlights the recent progresses in the field of ambipolar transistors, both from the fundamental physics and application viewpoints. Attention is devoted to the challenges that should be faced for the realization of ambipolar transistors with different material systems, beginning with the understanding of the importance of interface modification, which heavily affects injections and trapping of both holes and electrons. The recent development of advanced gating applications, including ionic liquid gating, that open up more possibility to realize ambipolar transport in materials in which one type of charge carrier is highly dominant is highlighted. Between the possible applications of ambipolar field-effect transistors, we focus on ambipolar light-emitting transistors. We put this new device in the framework of its prospective for general lightings, embedded displays, current-driven laser, as well as for photonics-electronics interconnection. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Energy reduction through voltage scaling and lightweight checking

NASA Astrophysics Data System (ADS)

Kadric, Edin

As the semiconductor roadmap reaches smaller feature sizes and the end of Dennard Scaling, design goals change, and managing the power envelope often dominates delay minimization. Voltage scaling remains a powerful tool to reduce energy. We find that it results in about 60% geomean energy reduction on top of other common low-energy optimizations with 22nm CMOS technology. However, when voltage is reduced, it becomes easier for noise and particle strikes to upset a node, potentially causing Silent Data Corruption (SDC). The 60% energy reduction, therefore, comes with a significant drop in reliability. Duplication with checking and triple-modular redundancy are traditional approaches used to combat transient errors, but spending 2--3x the energy for redundant computation can diminish or reverse the benefits of voltage scaling. As an alternative, we explore the opportunity to use checking operations that are cheaper than the base computation they are guarding. We devise a classification system for applications and their lightweight checking characteristics. In particular, we identify and evaluate the effectiveness of lightweight checks in a broad set of common tasks in scientific computing and signal processing. We find that the lightweight checks cost only a fraction of the base computation (0-25%) and allow us to recover the reliability losses from voltage scaling. Overall, we show about 50% net energy reduction without compromising reliability compared to operation at the nominal voltage. We use FPGAs (Field-Programmable Gate Arrays) in our work, although the same ideas can be applied to different systems. On top of voltage scaling, we explore other common low-energy techniques for FPGAs: transmission gates, gate boosting, power gating, low-leakage (high-Vth) processes, and dual-V dd architectures. We do not scale voltage for memories, so lower voltages help us reduce logic and interconnect energy, but not memory energy. At lower voltages, memories become dominant, and we get diminishing returns from continuing to scale voltage. To ensure that memories do not become a bottleneck, we also design an energy-robust FPGA memory architecture, which attempts to minimize communication energy due to mismatches between application and architecture. We do this alongside application parallelism tuning. We show our techniques on a wide range of applications, including a large real-time system used for Wide-Area Motion Imaging (WAMI).

47 CFR 24.133 - Emission limits.

Code of Federal Regulations, 2012 CFR

2012-10-01

... outside the authorized bandwidth and removed from the edge of the authorized bandwidth by a displacement... the authorized bandwidth and removed from the edge of the authorized bandwidth by a displacement... outside the authorized bandwidth and removed from the edge of the authorized bandwidth by a displacement...

47 CFR 24.133 - Emission limits.

Code of Federal Regulations, 2013 CFR

2013-10-01

... outside the authorized bandwidth and removed from the edge of the authorized bandwidth by a displacement... the authorized bandwidth and removed from the edge of the authorized bandwidth by a displacement... outside the authorized bandwidth and removed from the edge of the authorized bandwidth by a displacement...

47 CFR 24.133 - Emission limits.

Code of Federal Regulations, 2011 CFR

2011-10-01

... outside the authorized bandwidth and removed from the edge of the authorized bandwidth by a displacement... the authorized bandwidth and removed from the edge of the authorized bandwidth by a displacement... outside the authorized bandwidth and removed from the edge of the authorized bandwidth by a displacement...

47 CFR 24.133 - Emission limits.

Code of Federal Regulations, 2010 CFR

2010-10-01

... outside the authorized bandwidth and removed from the edge of the authorized bandwidth by a displacement... the authorized bandwidth and removed from the edge of the authorized bandwidth by a displacement... outside the authorized bandwidth and removed from the edge of the authorized bandwidth by a displacement...

47 CFR 24.133 - Emission limits.

Code of Federal Regulations, 2014 CFR

2014-10-01

... outside the authorized bandwidth and removed from the edge of the authorized bandwidth by a displacement... the authorized bandwidth and removed from the edge of the authorized bandwidth by a displacement... outside the authorized bandwidth and removed from the edge of the authorized bandwidth by a displacement...

MPNACK: an optical switching scheme enabling the buffer-less reliable transmission

NASA Astrophysics Data System (ADS)

Yu, Xiaoshan; Gu, Huaxi; Wang, Kun; Xu, Meng; Guo, Yantao

2016-01-01

Optical data center networks are becoming an increasingly promising solution to solve the bottlenecks faced by electrical networks, such as low transmission bandwidth, high wiring complexity, and unaffordable power consumption. However, the optical circuit switching (OCS) network is not flexible enough to carry the traffic burst while the optical packet switching (OPS) network cannot solve the packet contention in an efficient way. To this end, an improved switching strategy named OPS with multi-hop Negative Acknowledgement (MPNACK) is proposed. This scheme uses a feedback mechanism, rather than the buffering structure, to handle the optical packet contention. The collided packet is treated as a NACK packet and sent back to the source server. When the sender receives this NACK packet, it knows a collision happens in the transmission path and a retransmission procedure is triggered. Overall, the OPS-NACK scheme enables a reliable transmission in the buffer-less optical network. Furthermore, with this scheme, the expensive and energy-hungry elements, optical or electrical buffers, can be removed from the optical interconnects, thus a more scalable and cost-efficient network can be constructed for cloud computing data centers.

Architectural and engineering issues for building an optical Internet

NASA Astrophysics Data System (ADS)

St. Arnaud, Bill

1998-10-01

Recent developments in high density Wave Division Multiplexing fiber systems allows for the deployment of a dedicated optical Internet network for large volume backbone pipes that does not require an underlying multi-service SONET/SDH and ATM transport protocol. Some intrinsic characteristics of Internet traffic such as its self similar nature, server bound congestion, routing and data asymmetry allow for highly optimized traffic engineered networks using individual wavelengths. By transmitting GigaBit Ethernet or SONET/SDH frames natively over WDM wavelengths that directly interconnect high performance routers the original concept of the Internet as an intrinsically survivable datagram network is possible. Traffic engineering, restoral, protection and bandwidth management of the network must now be carried out at the IP layer and so new routing or switching protocols such as MPLS that allow for uni- directional paths with fast restoral and protection at the IP layer become essential for a reliable production network. The deployment of high density WDM municipal and campus networks also gives carriers and ISPs the flexibility to offer customers as integrated and seamless set of optical Internet services.

Innovative Networking Concepts Tested on the Advanced Communications Technology Satellite

NASA Technical Reports Server (NTRS)

Friedman, Daniel; Gupta, Sonjai; Zhang, Chuanguo; Ephremides, Anthony

1996-01-01

This paper describes a program of experiments conducted over the advanced communications technology satellite (ACTS) and the associated TI-VSAT (very small aperture terminal). The experiments were motivated by the commercial potential of low-cost receive only satellite terminals that can operate in a hybrid network environment, and by the desire to demonstrate frame relay technology over satellite networks. The first experiment tested highly adaptive methods of satellite bandwidth allocation in an integrated voice-data service environment. The second involved comparison of forward error correction (FEC) and automatic repeat request (ARQ) methods of error control for satellite communication with emphasis on the advantage that a hybrid architecture provides, especially in the case of multicasts. Finally, the third experiment demonstrated hybrid access to databases and compared the performance of internetworking protocols for interconnecting local area networks (LANs) via satellite. A custom unit termed frame relay access switch (FRACS) was developed by COMSAT Laboratories for these experiments; the preparation and conduct of these experiments involved a total of 20 people from the University of Maryland, the University of Colorado and COMSAT Laboratories, from late 1992 until 1995.

Investigation of a stripline transmission line structure for gyromagnetic nonlinear transmission line high power microwave sources.

PubMed

Reale, D V; Parson, J M; Neuber, A A; Dickens, J C; Mankowski, J J

2016-03-01

A stripline gyromagnetic nonlinear transmission line (NLTL) was constructed out of yttrium iron garnet ferrite and tested at charge voltages of 35 kV-55 kV with bias fields ranging from 10 kA/m to 20 kA/m. Typically, high power gyromagnetic NLTLs are constructed in a coaxial geometry. While this approach has many advantages, including a uniform transverse electromagnetic (TEM) mode, simple interconnection between components, and the ability to use oil or pressurized gas as an insulator, the coaxial implementation suffers from complexity of construction, especially when using a solid insulator. By moving to a simpler transmission line geometry, NLTLs can be constructed more easily and arrayed on a single substrate. This work represents a first step in exploring the suitability of various transmission line structures, such as microstrips and coplanar waveguides. The resulting high power microwave (HPM) source operates in ultra high frequency (UHF) band with an average bandwidth of 40.1% and peak rf power from 2 MW to 12.7 MW.

Announcing Supercomputer Summit

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wells, Jack; Bland, Buddy; Nichols, Jeff

Summit is the next leap in leadership-class computing systems for open science. With Summit we will be able to address, with greater complexity and higher fidelity, questions concerning who we are, our place on earth, and in our universe. Summit will deliver more than five times the computational performance of Titan’s 18,688 nodes, using only approximately 3,400 nodes when it arrives in 2017. Like Titan, Summit will have a hybrid architecture, and each node will contain multiple IBM POWER9 CPUs and NVIDIA Volta GPUs all connected together with NVIDIA’s high-speed NVLink. Each node will have over half a terabyte ofmore » coherent memory (high bandwidth memory + DDR4) addressable by all CPUs and GPUs plus 800GB of non-volatile RAM that can be used as a burst buffer or as extended memory. To provide a high rate of I/O throughput, the nodes will be connected in a non-blocking fat-tree using a dual-rail Mellanox EDR InfiniBand interconnect. Upon completion, Summit will allow researchers in all fields of science unprecedented access to solving some of the world’s most pressing challenges.« less

Self-focused ZnO transducers for ultrasonic biomicroscopy

NASA Astrophysics Data System (ADS)

Cannata, J. M.; Williams, J. A.; Zhou, Q. F.; Sun, L.; Shung, K. K.; Yu, H.; Kim, E. S.

2008-04-01

A simple fabrication technique was developed to produce high frequency (100MHz) self-focused single element transducers with sputtered zinc oxide (ZnO) crystal films. This technique requires the sputtering of a ZnO film directly onto a curved backing substrate. Transducers were fabricated by sputtering an 18μm thick ZnO layer on 2mm diameter aluminum rods with ends shaped and polished to produce a 2mm focus or f-number equal to one. The aluminum rod served a dual purpose as the backing layer and positive electrode for the resultant transducers. A 4μm Parylene matching layer was deposited on the transducers after housing and interconnect. This matching layer was used to protect the substrate and condition the transfer of acoustic energy between the ZnO film and the load medium. The pulse-echo response for a representative transducer was centered at 101MHz with a -6dB bandwidth of 49%. The measured two way insertion loss was 44dB. A tungsten wire phantom and an adult zebrafish eye were imaged to show the capability of these transducers.

Mass storage: The key to success in high performance computing

NASA Technical Reports Server (NTRS)

Lee, Richard R.

1993-01-01

There are numerous High Performance Computing & Communications Initiatives in the world today. All are determined to help solve some 'Grand Challenges' type of problem, but each appears to be dominated by the pursuit of higher and higher levels of CPU performance and interconnection bandwidth as the approach to success, without any regard to the impact of Mass Storage. My colleagues and I at Data Storage Technologies believe that all will have their performance against their goals ultimately measured by their ability to efficiently store and retrieve the 'deluge of data' created by end-users who will be using these systems to solve Scientific Grand Challenges problems, and that the issue of Mass Storage will become then the determinant of success or failure in achieving each projects goals. In today's world of High Performance Computing and Communications (HPCC), the critical path to success in solving problems can only be traveled by designing and implementing Mass Storage Systems capable of storing and manipulating the truly 'massive' amounts of data associated with solving these challenges. Within my presentation I will explore this critical issue and hypothesize solutions to this problem.

Investigation of a stripline transmission line structure for gyromagnetic nonlinear transmission line high power microwave sources

DOE Office of Scientific and Technical Information (OSTI.GOV)

Reale, D. V., E-mail: david.reale@ttu.edu; Parson, J. M.; Neuber, A. A.

2016-03-15

A stripline gyromagnetic nonlinear transmission line (NLTL) was constructed out of yttrium iron garnet ferrite and tested at charge voltages of 35 kV–55 kV with bias fields ranging from 10 kA/m to 20 kA/m. Typically, high power gyromagnetic NLTLs are constructed in a coaxial geometry. While this approach has many advantages, including a uniform transverse electromagnetic (TEM) mode, simple interconnection between components, and the ability to use oil or pressurized gas as an insulator, the coaxial implementation suffers from complexity of construction, especially when using a solid insulator. By moving to a simpler transmission line geometry, NLTLs can be constructedmore » more easily and arrayed on a single substrate. This work represents a first step in exploring the suitability of various transmission line structures, such as microstrips and coplanar waveguides. The resulting high power microwave (HPM) source operates in ultra high frequency (UHF) band with an average bandwidth of 40.1% and peak rf power from 2 MW to 12.7 MW.« less

Role of superconducting electronics in advancing science and technology (invited) (abstract)

NASA Astrophysics Data System (ADS)

Faris, S. M.

1988-08-01

The promises of the ultrahigh-performance properties of superconductivity and Josephson junction technologies have been known for quite some time. This presentation describes the first superconducting electronics and measurement system and its important role as a major tool to advance microwave and millimeter wave technologies. This breakthrough tool is a sampling oscilloscope with 5-ps rise time, 50-μV sensitivity, and a time domain reflectometer with 8-ps rise time. In order to achieve these performance goals, several technological hurdles had to be overcome including perfecting a manufacturing process for building Josephson junction IC chips, developing an innovative cooling technique, developing interfaces and interconnections with bandwidths in excess of 70 GHz, and developing the room-temperature hardware and software necessary to make the instruments convenient, easy to use, easy to learn, in addition to making available functions and features users have come to expect from sophisticated digital test instrumentation. These technological developments are stepping stones leading to the realization of more sophisticated and complex electronic systems satisfying the needs of scientists, technologists, and engineers. The unprecedented speed and sensitivity make it possible to attack new frontiers.

A new perspective on plasmonics: Confinement and propagation length of surface plasmons for different materials and geometries [A new perspective on materials for plasmonics

DOE PAGES

Dastmalchi, Babak; Tassin, Philippe; Koschny, Thomas; ...

2015-09-21

Surface-plasmon polaritons are electromagnetic waves propagating on the surface of a metal. Thanks to subwavelength confinement, they can concentrate optical energy on the micrometer or even nanometer scale, enabling new applications in bio-sensing, optical interconnects, and nonlinear optics, where small footprint and strong field concentration are essential. The major obstacle in developing plasmonic applications is dissipative loss, which limits the propagation length of surface plasmons and broadens the bandwidth of surface-plasmon resonances. Here, a new analysis of plasmonic materials and geometries is presented which fully considers the tradeoff between propagation length and degree of confinement. It is based on amore » two-dimensional analysis of two independent figures of merit and the analysis is applied to relevant plasmonic materials, e.g., noble metals, aluminum, silicon carbide, doped semiconductors, graphene, etc. Furthermore, the analysis provides guidance on how to improve the performance of any particular plasmonic application and substantially eases the selection of the plasmonic material.« less

Novel AlInN/GaN integrated circuits operating up to 500 °C

NASA Astrophysics Data System (ADS)

Gaska, R.; Gaevski, M.; Jain, R.; Deng, J.; Islam, M.; Simin, G.; Shur, M.

2015-11-01

High electron concentration in 2DEG channel of AlInN/GaN devices is remarkably stable over a broad temperature range, enabling device operation above 500 °C. The developed IC technology is based on three key elements: (1) exceptional quality AlInN/GaN heterostructure with very high carrier concentration and mobility enables IC fast operation in a broad temperature range; (2) heterostructure field effect transistor approach t provides fully planar IC structure which is easy to scale and to combine with the other high temperature electronic components; (3) fabrication advancements including novel metallization scheme and high-K passivation/gate dielectrics enable high temperature operation. The feasibility of the developed technology was confirmed by fabrication and testing of the high temperature inverter and differential amplifier ICs using AlInN/GaN heterostructures. The developed ICs showed stable performance with unit-gain bandwidth above 1 MHz and internal response time 45 ns at temperatures as high as 500 °C.

Digitally balanced detection for optical tomography.

PubMed

Hafiz, Rehan; Ozanyan, Krikor B

2007-10-01

Analog balanced Photodetection has found extensive usage for sensing of a weak absorption signal buried in laser intensity noise. This paper proposes schemes for compact, affordable, and flexible digital implementation of the already established analog balanced detection, as part of a multichannel digital tomography system. Variants of digitally balanced detection (DBD) schemes, suitable for weak signals on a largely varying background or weakly varying envelopes of high frequency carrier waves, are introduced analytically and elaborated in terms of algorithmic and hardware flow. The DBD algorithms are implemented on a low-cost general purpose reconfigurable hardware (field-programmable gate array), utilizing less than half of its resources. The performance of the DBD schemes compare favorably with their analog counterpart: A common mode rejection ratio of 50 dB was observed over a bandwidth of 300 kHz, limited mainly by the host digital hardware. The close relationship between the DBD outputs and those of known analog balancing circuits is discussed in principle and shown experimentally in the example case of propane gas detection.

Rapid and highly integrated FPGA-based Shack-Hartmann wavefront sensor for adaptive optics system

NASA Astrophysics Data System (ADS)

Chen, Yi-Pin; Chang, Chia-Yuan; Chen, Shean-Jen

2018-02-01

In this study, a field programmable gate array (FPGA)-based Shack-Hartmann wavefront sensor (SHWS) programmed on LabVIEW can be highly integrated into customized applications such as adaptive optics system (AOS) for performing real-time wavefront measurement. Further, a Camera Link frame grabber embedded with FPGA is adopted to enhance the sensor speed reacting to variation considering its advantage of the highest data transmission bandwidth. Instead of waiting for a frame image to be captured by the FPGA, the Shack-Hartmann algorithm are implemented in parallel processing blocks design and let the image data transmission synchronize with the wavefront reconstruction. On the other hand, we design a mechanism to control the deformable mirror in the same FPGA and verify the Shack-Hartmann sensor speed by controlling the frequency of the deformable mirror dynamic surface deformation. Currently, this FPGAbead SHWS design can achieve a 266 Hz cyclic speed limited by the camera frame rate as well as leaves 40% logic slices for additionally flexible design.

Height-selective etching for regrowth of self-aligned contacts using MBE

NASA Astrophysics Data System (ADS)

Burek, G. J.; Wistey, M. A.; Singisetti, U.; Nelson, A.; Thibeault, B. J.; Bank, S. R.; Rodwell, M. J. W.; Gossard, A. C.

2009-03-01

Advanced III-V transistors require unprecedented low-resistance contacts in order to simultaneously scale bandwidth, fmax and ft with the physical active region [M.J.W. Rodwell, M. Le, B. Brar, in: Proceedings of the IEEE, 96, 2008, p. 748]. Low-resistance contacts have been previously demonstrated using molecular beam epitaxy (MBE), which provides active doping above 4×10 19 cm -3 and permits in-situ metal deposition for the lowest resistances [U. Singisetti, M.A. Wistey, J.D. Zimmerman, B.J. Thibeault, M.J.W. Rodwell, A.C. Gossard, S.R. Bank, Appl. Phys. Lett., submitted]. But MBE is a blanket deposition technique, and applying MBE regrowth to deep-submicron lateral device dimensions is difficult even with advanced lithography techniques. We present a simple method for selectively etching undesired regrowth from the gate or mesa of a III-V MOSFET or laser, resulting in self-aligned source/drain contacts regardless of the device dimensions. This turns MBE into an effectively selective area growth technique.

Towards on-chip integration of brain imaging photodetectors using standard CMOS process.

PubMed

Kamrani, Ehsan; Lesage, Frederic; Sawan, Mohamad

2013-01-01

The main effects of on-chip integration on the performance and efficiency of silicon avalanche photodiode (SiAPD) and photodetector front-end is addressed in this paper based on the simulation and fabrication experiments. Two different silicon APDs are fabricated separately and also integrated with a transimpedance amplifier (TIA) front-end using standard CMOS technology. SiAPDs are designed in p+/n-well structure with guard rings realized in different shapes. The TIA front-end has been designed using distributed-gain concept combined with resistive-feedback and common-gate topology to reach low-noise and high gain-bandwidth product (GBW) characteristics. The integrated SiAPDs show higher signal-to-noise ratio (SNR), sensitivity and detection efficiency comparing to the separate SiAPDs. The integration does not show a significant effect on the gain and preserves the low power consumption. Using APDs with p-well guard-ring is preferred due to the higher observed efficiency after integration.

Stationary echo canceling in velocity estimation by time-domain cross-correlation.

PubMed

Jensen, J A

1993-01-01

The application of stationary echo canceling to ultrasonic estimation of blood velocities using time-domain cross-correlation is investigated. Expressions are derived that show the influence from the echo canceler on the signals that enter the cross-correlation estimator. It is demonstrated that the filtration results in a velocity-dependent degradation of the signal-to-noise ratio. An analytic expression is given for the degradation for a realistic pulse. The probability of correct detection at low signal-to-noise ratios is influenced by signal-to-noise ratio, transducer bandwidth, center frequency, number of samples in the range gate, and number of A-lines employed in the estimation. Quantitative results calculated by a simple simulation program are given for the variation in probability from these parameters. An index reflecting the reliability of the estimate at hand can be calculated from the actual cross-correlation estimate by a simple formula and used in rejecting poor estimates or in displaying the reliability of the velocity estimated.

Athermal Photonic Devices and Circuits on a Silicon Platform

NASA Astrophysics Data System (ADS)

Raghunathan, Vivek

In recent years, silicon based optical interconnects has been pursued as an effective solution that can offer cost, energy, distance and bandwidth density improvements over copper. Monolithic integration of optics and electronics has been enabled by silicon photonic devices that can be fabricated using CMOS technology. However, high levels of device integration result in significant local and global temperature fluctuations that prove problematic for silicon based photonic devices. In particular, high temperature dependence of Si refractive index (thermo-optic (TO) coefficient) shifts the filter response of resonant devices that limit wavelength resolution in various applications. Active thermal compensation using heaters and thermo-electric coolers are the legacy solution for low density integration. However, the required electrical power, device foot print and number of input/output (I/O) lines limit the integration density. We present a passive approach to an athermal design that involves compensation of positive TO effects from a silicon core by negative TO effects of the polymer cladding. In addition, the design rule involves engineering the waveguide core geometry depending on the resonance wavelength under consideration to ensure desired amount of light in the polymer. We develop exact design requirements for a TO peak stability of 0 pm/K and present prototype performance of 0.5 pm/K. We explore the material design space through initiated chemical vapor deposition (iCVD) of 2 polymer cladding choices. We study the effect of cross-linking on the optical properties of a polymer and establish the superior performance of the co-polymer cladding compared to the homo-polymer. Integration of polymer clad devices in an electronic-photonic architecture requires the possibility of multi-layer stacking capability. We use a low temperature, high density plasma chemical vapor deposition of SiO2/SiN x to hermetically seal the athermal. Further, we employ visible light for post-fabrication trimming of athermal rings by sandwiching a thin photosensitive layer of As2S3 in between amorphous Si core and polymer top cladding. System design of an add-drop filter requires an optimum combination of channel counts performance and power handling capacity for maximum aggregate bandwidth. We establish the superior performance of athermal add-drop filter compared to a standard filter treating bandwidth as the figure-of-merit. (Copies available exclusively from MIT Libraries, libraries.mit.edu/docs - docs mit.edu)

High-performance, scalable optical network-on-chip architectures

NASA Astrophysics Data System (ADS)

Tan, Xianfang

The rapid advance of technology enables a large number of processing cores to be integrated into a single chip which is called a Chip Multiprocessor (CMP) or a Multiprocessor System-on-Chip (MPSoC) design. The on-chip interconnection network, which is the communication infrastructure for these processing cores, plays a central role in a many-core system. With the continuously increasing complexity of many-core systems, traditional metallic wired electronic networks-on-chip (NoC) became a bottleneck because of the unbearable latency in data transmission and extremely high energy consumption on chip. Optical networks-on-chip (ONoC) has been proposed as a promising alternative paradigm for electronic NoC with the benefits of optical signaling communication such as extremely high bandwidth, negligible latency, and low power consumption. This dissertation focus on the design of high-performance and scalable ONoC architectures and the contributions are highlighted as follow: 1. A micro-ring resonator (MRR)-based Generic Wavelength-routed Optical Router (GWOR) is proposed. A method for developing any sized GWOR is introduced. GWOR is a scalable non-blocking ONoC architecture with simple structure, low cost and high power efficiency compared to existing ONoC designs. 2. To expand the bandwidth and improve the fault tolerance of the GWOR, a redundant GWOR architecture is designed by cascading different type of GWORs into one network. 3. The redundant GWOR built with MRR-based comb switches is proposed. Comb switches can expand the bandwidth while keep the topology of GWOR unchanged by replacing the general MRRs with comb switches. 4. A butterfly fat tree (BFT)-based hybrid optoelectronic NoC (HONoC) architecture is developed in which GWORs are used for global communication and electronic routers are used for local communication. The proposed HONoC uses less numbers of electronic routers and links than its counterpart of electronic BFT-based NoC. It takes the advantages of GWOR in optical communication and BFT in non-uniform traffic communication and three-dimension (3D) implementation. 5. A cycle-accurate NoC simulator is developed to evaluate the performance of proposed HONoC architectures. It is a comprehensive platform that can simulate both electronic and optical NoCs. Different size HONoC architectures are evaluated in terms of throughput, latency and energy dissipation. Simulation results confirm that HONoC achieves good network performance with lower power consumption.

Technologies for Elastic Optical Networking Systems in Spatial, Temporal and Spectral Domains

NASA Astrophysics Data System (ADS)

Qin, Chuan

As the demand for more data capacity keeps increasing, the need for the more efficient use of the data channel becomes more imperative. The fixed wavelength grid which has been in use for more than ten years in conventional wavelength division multiplexing (WDM) is a bottleneck that prevents the capacity from upgrading towards 400 Gb/s and above. A new elastic optical networking scheme where both transceivers and interconnects become flexible break the boundary of wavelength grids and allow a more efficient use of the limited optical bands for communication. This dissertation focuses on a few enabling technologies for elastic optical networking systems. Optical arbitrary waveform generation (OAWG) uses Fourier synthesis and generates user-defined broad-band scalable optical waveforms with high-fidelity through line-by-line full field control of a coherent optical frequency comb. OAWG finds its niche in elastic optical networking since it provides no grids, and scales to user-defined bandwidth. When elastic optical networking builds various connections to use an arbitrary number of subcarriers depending on the users' bandwidth needs, the flexibility also creates non-contiguous spectral fragmentation, much like a computer hard disk generating fragments. Spectral defragmentation aims to re-optimize and re-assign the optical spectrum to achieve more efficient use of the spectrum. One of the technologies is "hop tuning" defragmentation method with a fast auto-tracking local oscillator (LO). In the demonstrated defragmentation experiment, I used a field-programmable gate array (FPGA) to monitor the wavelength change in the signal laser and tune the front and rear current that controls the wavelength of the local oscillator laser. However, the control of the front and rear current needs a complete and accurate calibration of the LO laser and may not apply to a larger number of coherent communication links. A single-tone optical frequency shifter can shift the LO laser wavelength to track the signal wavelength, thus providing a technique for authentically automatic wavelength tracking. I also explored different materials and crystal orientations to reduce the radio-frequency (RF) power consumption required to shift the wavelengths. Based on the elastic optical networking in the temporal, spectral and spatial domains, an additional degree of freedom has been investigated recently to increase the data capacity. The exploration to use the spatial domain to carry more data is termed as spatial division multiplexing (SDM). One such SDM method is orbital angular momentum(OAM), which is a group of orthogonal light beams carrying orbital angular momentum exhibiting an azimuthal phase variation. The utilization of OAM states has the potential to significantly increase the spectral efficiency and channel capacity. The thesis also includes the demonstration to establish a connection by exploiting the elasticity steering in spatial, temporal and spectral domains. Beam steering based on optical phased array (OPA) is also a potential candidate of SDM to carry information when a different linear phase will distribute light to different spatial locations. The states are intrinsically orthogonal to one another. Using 4x4 3-D waveguides written by ultrafast laser inscription (ULI), we demonstrated 2-D optical phased array (OPA) beam steering that shows steering in both vertical and horizontal directions. Enabling technologies provide future pathways for elastic optical networking and will fundamentally impact optical communication systems in many ways.

[Estimation of rice LAI by using NDVI at different spectral bandwidths].

PubMed

Wang, Fu-min; Huang, Jing-feng; Tang, Yan-lin; Wang, Xiu-zhen

2007-11-01

The canopy hyperspectral reflectance data of rice at its different development stages were collected from field measurement, and the corresponding NDVIs as well as the correlation coefficients of NDVIs and LAI were computed at extending bandwidth of TM red and near-infrared (NIR) spectra. According to the variation characteristics of best fitted R2 with spectral bandwidth, the optimal bandwidth was determined. The results showed that the correlation coefficients of LAI and ND-VI and the maximum R2 of the best fitted functions at different spectral bandwidths had the same variation trend, i.e., decreased with increasing bandwidth when the bandwidth was less than 60 nm. However, when the bandwidth was beyond 60 nm, the maximum R2 somewhat fluctuated due to the effect of NIR. The analysis of R2 variation with bandwidth indicated that 15 nm was the optimal bandwidth for the estimation of rice LAI by using NDVI.

Efficient Graph Based Assembly of Short-Read Sequences on Hybrid Core Architecture

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sczyrba, Alex; Pratap, Abhishek; Canon, Shane

2011-03-22

Advanced architectures can deliver dramatically increased throughput for genomics and proteomics applications, reducing time-to-completion in some cases from days to minutes. One such architecture, hybrid-core computing, marries a traditional x86 environment with a reconfigurable coprocessor, based on field programmable gate array (FPGA) technology. In addition to higher throughput, increased performance can fundamentally improve research quality by allowing more accurate, previously impractical approaches. We will discuss the approach used by Convey?s de Bruijn graph constructor for short-read, de-novo assembly. Bioinformatics applications that have random access patterns to large memory spaces, such as graph-based algorithms, experience memory performance limitations on cache-based x86more » servers. Convey?s highly parallel memory subsystem allows application-specific logic to simultaneously access 8192 individual words in memory, significantly increasing effective memory bandwidth over cache-based memory systems. Many algorithms, such as Velvet and other de Bruijn graph based, short-read, de-novo assemblers, can greatly benefit from this type of memory architecture. Furthermore, small data type operations (four nucleotides can be represented in two bits) make more efficient use of logic gates than the data types dictated by conventional programming models.JGI is comparing the performance of Convey?s graph constructor and Velvet on both synthetic and real data. We will present preliminary results on memory usage and run time metrics for various data sets with different sizes, from small microbial and fungal genomes to very large cow rumen metagenome. For genomes with references we will also present assembly quality comparisons between the two assemblers.« less

All-electric control of donor nuclear spin qubits in silicon

NASA Astrophysics Data System (ADS)

Sigillito, Anthony J.; Tyryshkin, Alexei M.; Schenkel, Thomas; Houck, Andrew A.; Lyon, Stephen A.

2017-10-01

The electronic and nuclear spin degrees of freedom of donor impurities in silicon form ultra-coherent two-level systems that are potentially useful for applications in quantum information and are intrinsically compatible with industrial semiconductor processing. However, because of their smaller gyromagnetic ratios, nuclear spins are more difficult to manipulate than electron spins and are often considered too slow for quantum information processing. Moreover, although alternating current magnetic fields are the most natural choice to drive spin transitions and implement quantum gates, they are difficult to confine spatially to the level of a single donor, thus requiring alternative approaches. In recent years, schemes for all-electrical control of donor spin qubits have been proposed but no experimental demonstrations have been reported yet. Here, we demonstrate a scalable all-electric method for controlling neutral 31P and 75As donor nuclear spins in silicon. Using coplanar photonic bandgap resonators, we drive Rabi oscillations on nuclear spins exclusively using electric fields by employing the donor-bound electron as a quantum transducer, much in the spirit of recent works with single-molecule magnets. The electric field confinement leads to major advantages such as low power requirements, higher qubit densities and faster gate times. Additionally, this approach makes it possible to drive nuclear spin qubits either at their resonance frequency or at its first subharmonic, thus reducing device bandwidth requirements. Double quantum transitions can be driven as well, providing easy access to the full computational manifold of our system and making it convenient to implement nuclear spin-based qudits using 75As donors.

Fault tolerant high-performance PACS network design and implementation

NASA Astrophysics Data System (ADS)

Chimiak, William J.; Boehme, Johannes M.

1998-07-01

The Wake Forest University School of Medicine and the Wake Forest University/Baptist Medical Center (WFUBMC) are implementing a second generation PACS. The first generation PACS provided helpful information about the functional and temporal requirements of the system. It highlighted the importance of image retrieval speed, system availability, RIS/HIS integration, the ability to rapidly view images on any PACS workstation, network bandwidth, equipment redundancy, and the ability for the system to evolve using standards-based components. This paper deals with the network design and implementation of the PACS. The physical layout of the hospital areas served by the PACS, the choice of network equipment and installation issues encountered are addressed. Efforts to optimize fault tolerance are discussed. The PACS network is a gigabit, mixed-media network based on LAN emulation over ATM (LANE) with a rapid migration from LANE to Multiple Protocols Over ATM (MPOA) planned. Two fault-tolerant backbone ATM switches serve to distribute network accesses with two load-balancing 622 megabit per second (Mbps) OC-12 interconnections. The switch was sized to be upgradable to provide a 2.54 Gbps OC-48 interconnection with an OC-12 interconnection as a load-balancing backup. Modalities connect with legacy network interface cards to a switched-ethernet device. This device has two 155 Mbps OC-3 load-balancing uplinks to each of the backbone ATM switches of the PACS. This provides a fault-tolerant logical connection to the modality servers which pass verified DICOM images to the PACS servers and proper PACS diagnostic workstations. Where fiber pulls were prohibitively expensive, edge ATM switches were installed with an OC-12 uplink to a backbone ATM switches. The PACS and data base servers are fault-tolerant, hot-swappable Sun Enterprise Servers with an OC-12 connection to a backbone ATM switch and a fast-ethernet connection to a back-up network. The workstations come with 10/100 BASET autosense cards. A redundant switched-ethernet network will be installed to provide yet another degree of network fault-tolerance. The switched-ethernet devices are connected to each of the backbone ATM switches with two-load-balancing OC-3 connections to provide fault-tolerant connectivity in the event of a primary network failure.

Data analysis-based autonomic bandwidth adjustment in software defined multi-vendor optical transport networks.

PubMed

Li, Yajie; Zhao, Yongli; Zhang, Jie; Yu, Xiaosong; Jing, Ruiquan

2017-11-27

Network operators generally provide dedicated lightpaths for customers to meet the demand for high-quality transmission. Considering the variation of traffic load, customers usually rent peak bandwidth that exceeds the practical average traffic requirement. In this case, bandwidth provisioning is unmetered and customers have to pay according to peak bandwidth. Supposing that network operators could keep track of traffic load and allocate bandwidth dynamically, bandwidth can be provided as a metered service and customers would pay for the bandwidth that they actually use. To achieve cost-effective bandwidth provisioning, this paper proposes an autonomic bandwidth adjustment scheme based on data analysis of traffic load. The scheme is implemented in a software defined networking (SDN) controller and is demonstrated in the field trial of multi-vendor optical transport networks. The field trial shows that the proposed scheme can track traffic load and realize autonomic bandwidth adjustment. In addition, a simulation experiment is conducted to evaluate the performance of the proposed scheme. We also investigate the impact of different parameters on autonomic bandwidth adjustment. Simulation results show that the step size and adjustment period have significant influences on bandwidth savings and packet loss. A small value of step size and adjustment period can bring more benefits by tracking traffic variation with high accuracy. For network operators, the scheme can serve as technical support of realizing bandwidth as metered service in the future.

Interconnect assembly for an electronic assembly and assembly method therefor

DOEpatents

Gerbsch, Erich William

2003-06-10

An interconnect assembly and method for a semiconductor device, in which the interconnect assembly can be used in lieu of wirebond connections to form an electronic assembly. The interconnect assembly includes first and second interconnect members. The first interconnect member has a first surface with a first contact and a second surface with a second contact electrically connected to the first contact, while the second interconnect member has a flexible finger contacting the second contact of the first interconnect member. The first interconnect member is adapted to be aligned and registered with a semiconductor device having a contact on a first surface thereof, so that the first contact of the first interconnect member electrically contacts the contact of the semiconductor device. Consequently, the assembly method does not require any wirebonds, but instead merely entails aligning and registering the first interconnect member with the semiconductor device so that the contacts of the first interconnect member and the semiconductor device make electrically contact, and then contacting the second contact of the first interconnect member with the flexible finger of the second interconnect member.

Systems and Methods for Radar Data Communication

NASA Technical Reports Server (NTRS)

Bunch, Brian (Inventor); Szeto, Roland (Inventor); Miller, Brad (Inventor)

2013-01-01

A radar information processing system is operable to process high bandwidth radar information received from a radar system into low bandwidth radar information that may be communicated to a low bandwidth connection coupled to an electronic flight bag (EFB). An exemplary embodiment receives radar information from a radar system, the radar information communicated from the radar system at a first bandwidth; processes the received radar information into processed radar information, the processed radar information configured for communication over a connection operable at a second bandwidth, the second bandwidth lower than the first bandwidth; and communicates the radar information from a radar system, the radar information communicated from the radar system at a first bandwidth.

Mechanotransduction current is essential for stability of the transducing stereocilia in mammalian auditory hair cells

PubMed Central

Vélez-Ortega, A Catalina; Freeman, Mary J; Indzhykulian, Artur A; Grossheim, Jonathan M; Frolenkov, Gregory I

2017-01-01

Mechanotransducer channels at the tips of sensory stereocilia of inner ear hair cells are gated by the tension of 'tip links' interconnecting stereocilia. To ensure maximal sensitivity, tip links are tensioned at rest, resulting in a continuous influx of Ca2+ into the cell. Here, we show that this constitutive Ca2+ influx, usually considered as potentially deleterious for hair cells, is in fact essential for stereocilia stability. In the auditory hair cells of young postnatal mice and rats, a reduction in mechanotransducer current, via pharmacological channel blockers or disruption of tip links, leads to stereocilia shape changes and shortening. These effects occur only in stereocilia that harbor mechanotransducer channels, recover upon blocker washout or tip link regeneration and can be replicated by manipulations of extracellular Ca2+ or intracellular Ca2+ buffering. Thus, our data provide the first experimental evidence for the dynamic control of stereocilia morphology by the mechanotransduction current. DOI: http://dx.doi.org/10.7554/eLife.24661.001 PMID:28350294

Soft valves in plants

NASA Astrophysics Data System (ADS)

Park, Keunhwan; Tixier, Aude; Christensen, Anneline; Arnbjerg-Nielsen, Sif; Zwieniecki, Maciej; Jensen, Kaare

2017-11-01

Water and minerals flow from plant roots to leaves in the xylem, an interconnected network of vascular conduits that spans the full length of the organism. When a plant is subjected to drought stress, air pockets can spread inside the xylem, threatening the survival of the plant. Many plants prevent propagation of air by using hydrophobic nano-membranes in the ``pit'' pores that link adjacent xylem cells. This adds considerable resistance to flow. Interestingly, torus-margo pit pores in conifers are open and offer less resistance. To prevent propagation of air, conifers use a soft gating mechanism, which relies on hydrodynamic interactions between the xylem liquid and the elastic pit. However, it is unknown exactly how it is able to combine the seemingly antagonist functions of high permeability and resistance to propagation of air. We conduct experiments on biomimetic pores to elucidate the flow regulation mechanism. The design of plant valves is compared to other natural systems and optimal strategies are discussed. This work was supported by a research Grant (13166) from VILLUM FONDEN.

Synthesizing a novel genetic sequential logic circuit: a push-on push-off switch

PubMed Central

Lou, Chunbo; Liu, Xili; Ni, Ming; Huang, Yiqi; Huang, Qiushi; Huang, Longwen; Jiang, Lingli; Lu, Dan; Wang, Mingcong; Liu, Chang; Chen, Daizhuo; Chen, Chongyi; Chen, Xiaoyue; Yang, Le; Ma, Haisu; Chen, Jianguo; Ouyang, Qi

2010-01-01

Design and synthesis of basic functional circuits are the fundamental tasks of synthetic biologists. Before it is possible to engineer higher-order genetic networks that can perform complex functions, a toolkit of basic devices must be developed. Among those devices, sequential logic circuits are expected to be the foundation of the genetic information-processing systems. In this study, we report the design and construction of a genetic sequential logic circuit in Escherichia coli. It can generate different outputs in response to the same input signal on the basis of its internal state, and ‘memorize' the output. The circuit is composed of two parts: (1) a bistable switch memory module and (2) a double-repressed promoter NOR gate module. The two modules were individually rationally designed, and they were coupled together by fine-tuning the interconnecting parts through directed evolution. After fine-tuning, the circuit could be repeatedly, alternatively triggered by the same input signal; it functions as a push-on push-off switch. PMID:20212522

Synthesizing a novel genetic sequential logic circuit: a push-on push-off switch.

PubMed

Lou, Chunbo; Liu, Xili; Ni, Ming; Huang, Yiqi; Huang, Qiushi; Huang, Longwen; Jiang, Lingli; Lu, Dan; Wang, Mingcong; Liu, Chang; Chen, Daizhuo; Chen, Chongyi; Chen, Xiaoyue; Yang, Le; Ma, Haisu; Chen, Jianguo; Ouyang, Qi

2010-01-01

Design and synthesis of basic functional circuits are the fundamental tasks of synthetic biologists. Before it is possible to engineer higher-order genetic networks that can perform complex functions, a toolkit of basic devices must be developed. Among those devices, sequential logic circuits are expected to be the foundation of the genetic information-processing systems. In this study, we report the design and construction of a genetic sequential logic circuit in Escherichia coli. It can generate different outputs in response to the same input signal on the basis of its internal state, and 'memorize' the output. The circuit is composed of two parts: (1) a bistable switch memory module and (2) a double-repressed promoter NOR gate module. The two modules were individually rationally designed, and they were coupled together by fine-tuning the interconnecting parts through directed evolution. After fine-tuning, the circuit could be repeatedly, alternatively triggered by the same input signal; it functions as a push-on push-off switch.

High-Responsivity Graphene-Boron Nitride Photodetector and Autocorrelator in a Silicon Photonic Integrated Circuit.

PubMed

Shiue, Ren-Jye; Gao, Yuanda; Wang, Yifei; Peng, Cheng; Robertson, Alexander D; Efetov, Dmitri K; Assefa, Solomon; Koppens, Frank H L; Hone, James; Englund, Dirk

2015-11-11

Graphene and other two-dimensional (2D) materials have emerged as promising materials for broadband and ultrafast photodetection and optical modulation. These optoelectronic capabilities can augment complementary metal-oxide-semiconductor (CMOS) devices for high-speed and low-power optical interconnects. Here, we demonstrate an on-chip ultrafast photodetector based on a two-dimensional heterostructure consisting of high-quality graphene encapsulated in hexagonal boron nitride. Coupled to the optical mode of a silicon waveguide, this 2D heterostructure-based photodetector exhibits a maximum responsivity of 0.36 A/W and high-speed operation with a 3 dB cutoff at 42 GHz. From photocurrent measurements as a function of the top-gate and source-drain voltages, we conclude that the photoresponse is consistent with hot electron mediated effects. At moderate peak powers above 50 mW, we observe a saturating photocurrent consistent with the mechanisms of electron-phonon supercollision cooling. This nonlinear photoresponse enables optical on-chip autocorrelation measurements with picosecond-scale timing resolution and exceptionally low peak powers.

Spin switches for compact implementation of neuron and synapse

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quang Diep, Vinh, E-mail: vdiep@purdue.edu; Sutton, Brian; Datta, Supriyo

2014-06-02

Nanomagnets driven by spin currents provide a natural implementation for a neuron and a synapse: currents allow convenient summation of multiple inputs, while the magnet provides the threshold function. The objective of this paper is to explore the possibility of a hardware neural network implementation using a spin switch (SS) as its basic building block. SS is a recently proposed device based on established technology with a transistor-like gain and input-output isolation. This allows neural networks to be constructed with purely passive interconnections without intervening clocks or amplifiers. The weights for the neural network are conveniently adjusted through analog voltagesmore » that can be stored in a non-volatile manner in an underlying CMOS layer using a floating gate low dropout voltage regulator. The operation of a multi-layer SS neural network designed for character recognition is demonstrated using a standard simulation model based on coupled Landau-Lifshitz-Gilbert equations, one for each magnet in the network.« less

Controlled fabrication of high-quality carbon nanoscrolls from monolayer graphene.

PubMed

Xie, Xu; Ju, Long; Feng, Xiaofeng; Sun, Yinghui; Zhou, Ruifeng; Liu, Kai; Fan, Shoushan; Li, Qunqing; Jiang, Kaili

2009-07-01

We report a simple and effective way of fabricating high-quality carbon nanoscrolls (CNSs), using isopropyl alcohol solution to roll up monolayer graphene predefined on SiO(2)/Si substrates. Transmission electron microscopy studies reveal that the CNS has a tube-like structure with a hollow core surrounded by graphene walls 0.35 nm apart. Raman spectroscopy studies show that the CNS is free of significant defects, and the electronic structure and phonon dispersion are slightly different from those of two-dimensional graphene. Finally, the CNS-based device is fabricated, directly on the SiO(2)/Si substrate. Electrical-transport measurements show that its resistance is weakly gate-dependent but strongly temperature-dependent. In addition, the CNS can sustain a high current density up to 5 x 10(7) A/cm(2), indicating that it is a good candidate for microcircuit interconnects. The controlled fabrication of high-quality CNSs may open up new opportunities for both fundamental and applied research of CNSs.

Development of the automatic test pattern generation for NPP digital electronic circuits using the degree of freedom concept

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, D.S.; Seong, P.H.

1995-08-01

In this paper, an improved algorithm for automatic test pattern generation (ATG) for nuclear power plant digital electronic circuits--the combinational type of logic circuits is presented. For accelerating and improving the ATG process for combinational circuits the presented ATG algorithm has the new concept--the degree of freedom (DF). The DF, directly computed from the system descriptions such as types of gates and their interconnections, is the criterion to decide which among several alternate lines` logic values required along each path promises to be the most effective in order to accelerate and improve the ATG process. Based on the DF themore » proposed ATG algorithm is implemented in the automatic fault diagnosis system (AFDS) which incorporates the advanced fault diagnosis method of artificial intelligence technique, it is shown that the AFDS using the ATG algorithm makes Universal Card (UV Card) testing much faster than the present testing practice or by using exhaustive testing sets.« less

On-demand semiconductor single-photon source with near-unity indistinguishability.

PubMed

He, Yu-Ming; He, Yu; Wei, Yu-Jia; Wu, Dian; Atatüre, Mete; Schneider, Christian; Höfling, Sven; Kamp, Martin; Lu, Chao-Yang; Pan, Jian-Wei

2013-03-01

Single-photon sources based on semiconductor quantum dots offer distinct advantages for quantum information, including a scalable solid-state platform, ultrabrightness and interconnectivity with matter qubits. A key prerequisite for their use in optical quantum computing and solid-state networks is a high level of efficiency and indistinguishability. Pulsed resonance fluorescence has been anticipated as the optimum condition for the deterministic generation of high-quality photons with vanishing effects of dephasing. Here, we generate pulsed single photons on demand from a single, microcavity-embedded quantum dot under s-shell excitation with 3 ps laser pulses. The π pulse-excited resonance-fluorescence photons have less than 0.3% background contribution and a vanishing two-photon emission probability. Non-postselective Hong-Ou-Mandel interference between two successively emitted photons is observed with a visibility of 0.97(2), comparable to trapped atoms and ions. Two single photons are further used to implement a high-fidelity quantum controlled-NOT gate.

Recent Advances in Photonic Devices for Optical Computing and the Role of Nonlinear Optics-Part II

NASA Technical Reports Server (NTRS)

Abdeldayem, Hossin; Frazier, Donald O.; Witherow, William K.; Banks, Curtis E.; Paley, Mark S.

2007-01-01

The twentieth century has been the era of semiconductor materials and electronic technology while this millennium is expected to be the age of photonic materials and all-optical technology. Optical technology has led to countless optical devices that have become indispensable in our daily lives in storage area networks, parallel processing, optical switches, all-optical data networks, holographic storage devices, and biometric devices at airports. This chapters intends to bring some awareness to the state-of-the-art of optical technologies, which have potential for optical computing and demonstrate the role of nonlinear optics in many of these components. Our intent, in this Chapter, is to present an overview of the current status of optical computing, and a brief evaluation of the recent advances and performance of the following key components necessary to build an optical computing system: all-optical logic gates, adders, optical processors, optical storage, holographic storage, optical interconnects, spatial light modulators and optical materials.

SIFT-based dense pixel tracking on 0.35 T cine-MR images acquired during image-guided radiation therapy with application to gating optimization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mazur, Thomas R., E-mail: tmazur@radonc.wustl.edu, E-mail: hli@radonc.wustl.edu; Fischer-Valuck, Benjamin W.; Wang, Yuhe

Purpose: To first demonstrate the viability of applying an image processing technique for tracking regions on low-contrast cine-MR images acquired during image-guided radiation therapy, and then outline a scheme that uses tracking data for optimizing gating results in a patient-specific manner. Methods: A first-generation MR-IGRT system—treating patients since January 2014—integrates a 0.35 T MR scanner into an annular gantry consisting of three independent Co-60 sources. Obtaining adequate frame rates for capturing relevant patient motion across large fields-of-view currently requires coarse in-plane spatial resolution. This study initially (1) investigate the feasibility of rapidly tracking dense pixel correspondences across single, sagittal planemore » images (with both moderate signal-to-noise and spatial resolution) using a matching objective for highly descriptive vectors called scale-invariant feature transform (SIFT) descriptors associated to all pixels that describe intensity gradients in local regions around each pixel. To more accurately track features, (2) harmonic analysis was then applied to all pixel trajectories within a region-of-interest across a short training period. In particular, the procedure adjusts the motion of outlying trajectories whose relative spectral power within a frequency bandwidth consistent with respiration (or another form of periodic motion) does not exceed a threshold value that is manually specified following the training period. To evaluate the tracking reliability after applying this correction, conventional metrics—including Dice similarity coefficients (DSCs), mean tracking errors (MTEs), and Hausdorff distances (HD)—were used to compare target segmentations obtained via tracking to manually delineated segmentations. Upon confirming the viability of this descriptor-based procedure for reliably tracking features, the study (3) outlines a scheme for optimizing gating parameters—including relative target position and a tolerable margin about this position—derived from a probability density function that is constructed using tracking results obtained just prior to treatment. Results: The feasibility of applying the matching objective for SIFT descriptors toward pixel-by-pixel tracking on cine-MR acquisitions was first retrospectively demonstrated for 19 treatments (spanning various sites). Both with and without motion correction based on harmonic analysis, sub-pixel MTEs were obtained. A mean DSC value spanning all patients of 0.916 ± 0.001 was obtained without motion correction, with DSC values exceeding 0.85 for all patients considered. While most patients show accurate tracking without motion correction, harmonic analysis does yield substantial gain in accuracy (defined using HDs) for three particularly challenging subjects. An application of tracking toward a gating optimization procedure was then demonstrated that should allow a physician to balance beam-on time and tissue sparing in a patient-specific manner by tuning several intuitive parameters. Conclusions: Tracking results show high fidelity in assessing intrafractional motion observed on cine-MR acquisitions. Incorporating harmonic analysis during a training period improves the robustness of the tracking for challenging targets. The concomitant gating optimization procedure should allow for physicians to quantitatively assess gating effectiveness quickly just prior to treatment in a patient-specific manner.« less

A compressive-sensing Fourier-transform on-chip Raman spectrometer

NASA Astrophysics Data System (ADS)

Podmore, Hugh; Scott, Alan; Lee, Regina

2018-02-01

We demonstrate a novel compressive sensing Fourier-transform spectrometer (FTS) for snapshot Raman spectroscopy in a compact format. The on-chip FTS consists of a set of planar-waveguide Mach-Zehnder interferometers (MZIs) arrayed on a photonic chip, effecting a discrete Fourier-transform of the input spectrum. Incoherence between the sampling domain (time), and the spectral domain (frequency) permits compressive sensing retrieval using undersampled interferograms for sparse spectra such as Raman emission. In our fabricated device we retain our chosen bandwidth and resolution while reducing the number of MZIs, e.g. the size of the interferogram, to 1/4th critical sampling. This architecture simultaneously reduces chip footprint and concentrates the interferogram in fewer pixels to improve the signal to noise ratio. Our device collects interferogram samples simultaneously, therefore a time-gated detector may be used to separate Raman peaks from sample fluorescence. A challenge for FTS waveguide spectrometers is to achieve multi-aperture high throughput broadband coupling to a large number of single-mode waveguides. A multi-aperture design allows one to increase the bandwidth and spectral resolution without sacrificing optical throughput. In this device, multi-aperture coupling is achieved using an array of microlenses bonded to the surface of the chip, and aligned with a grid of vertically illuminated waveguide apertures. The microlens array accepts a collimated beam with near 100% fill-factor, and the resulting spherical wavefronts are coupled into the single-mode waveguides using 45& mirrors etched into the waveguide layer via focused ion-beam (FIB). The interferogram from the waveguide outputs is imaged using a CCD, and inverted via l1-norm minimization to correctly retrieve a sparse input spectrum.

New data acquisition system for beam loss monitor used in J-PARC main ring

NASA Astrophysics Data System (ADS)

Satou, K.; Toyama, T.; Kamikubota, N.; Yoshida, S.; Matsushita, J.; Wakita, T.; Sugiyama, M.; Morino, T.

2018-04-01

A new data acquisition system has been developed continually as a part of the development of a new beam loss monitor (BLM) system for the J-PARC main ring. This development includes a newly designed front-end isolation amp that uses photo-couplers and a VME-based new analog-to-digital converter (ADC) system. Compared to the old amp, the new amp has a 10 times higher conversion impedance for the input current to the output voltage; this value is 1 M Ω. Moreover, the bandwidth was improved to from DC to 50 kHz, which is about two orders of magnitude greater than the previously used bandwidth. The theoretical estimations made in this study roughly agree with the frequency response obtained for the new system. The new ADC system uses an on-board field-programmable gate array chip for signal processing. By replacing the firmware of this chip, changes pertaining to future accelerator upgrade plans may be introduced into the new ADC system; in addition, the ADC system can be used in other applications. The sampling speed of the system is 1 MS/s, and it exhibits a 95 dBc spurious-free dynamic range and 16.5 effective number of bits. The obtained waveform and integrated charge data are compared with two reference levels in the ADC system. If the data exceeds the reference level, the system generates an alarm to dump the beams. By using the new data acquisition system, it was proved that the new BLM system shows a wide dynamic range of 160 dB. In this study, the details of the new data acquisition system are described.

Broad-Bandwidth FPGA-Based Digital Polyphase Spectrometer

NASA Technical Reports Server (NTRS)

Jamot, Robert F.; Monroe, Ryan M.

2012-01-01

With present concern for ecological sustainability ever increasing, it is desirable to model the composition of Earth s upper atmosphere accurately with regards to certain helpful and harmful chemicals, such as greenhouse gases and ozone. The microwave limb sounder (MLS) is an instrument designed to map the global day-to-day concentrations of key atmospheric constituents continuously. One important component in MLS is the spectrometer, which processes the raw data provided by the receivers into frequency-domain information that cannot only be transmitted more efficiently, but also processed directly once received. The present-generation spectrometer is fully analog. The goal is to include a fully digital spectrometer in the next-generation sensor. In a digital spectrometer, incoming analog data must be converted into a digital format, processed through a Fourier transform, and finally accumulated to reduce the impact of input noise. While the final design will be placed on an application specific integrated circuit (ASIC), the building of these chips is prohibitively expensive. To that end, this design was constructed on a field-programmable gate array (FPGA). A family of state-of-the-art digital Fourier transform spectrometers has been developed, with a combination of high bandwidth and fine resolution. Analog signals consisting of radiation emitted by constituents in planetary atmospheres or galactic sources are downconverted and subsequently digitized by a pair of interleaved analog-to-digital converters (ADCs). This 6-Gsps (gigasample per second) digital representation of the analog signal is then processed through an FPGA-based streaming fast Fourier transform (FFT). Digital spectrometers have many advantages over previously used analog spectrometers, especially in terms of accuracy and resolution, both of which are particularly important for the type of scientific questions to be addressed with next-generation radiometers.

Intermediate frequency band digitized high dynamic range radiometer system for plasma diagnostics and real-time Tokamak control

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bongers, W. A.; Beveren, V. van; Westerhof, E.

2011-06-15

An intermediate frequency (IF) band digitizing radiometer system in the 100-200 GHz frequency range has been developed for Tokamak diagnostics and control, and other fields of research which require a high flexibility in frequency resolution combined with a large bandwidth and the retrieval of the full wave information of the mm-wave signals under investigation. The system is based on directly digitizing the IF band after down conversion. The enabling technology consists of a fast multi-giga sample analog to digital converter that has recently become available. Field programmable gate arrays (FPGA) are implemented to accomplish versatile real-time data analysis. A prototypemore » system has been developed and tested and its performance has been compared with conventional electron cyclotron emission (ECE) spectrometer systems. On the TEXTOR Tokamak a proof of principle shows that ECE, together with high power injected and scattered radiation, becomes amenable to measurement by this device. In particular, its capability to measure the phase of coherent signals in the spectrum offers important advantages in diagnostics and control. One case developed in detail employs the FPGA in real-time fast Fourier transform (FFT) and additional signal processing. The major benefit of such a FFT-based system is the real-time trade-off that can be made between frequency and time resolution. For ECE diagnostics this corresponds to a flexible spatial resolution in the plasma, with potential application in smart sensing of plasma instabilities such as the neoclassical tearing mode (NTM) and sawtooth instabilities. The flexible resolution would allow for the measurement of the full mode content of plasma instabilities contained within the system bandwidth.« less

Use of Field Programmable Gate Array Technology in Future Space Avionics

NASA Technical Reports Server (NTRS)

Ferguson, Roscoe C.; Tate, Robert

2005-01-01

Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.

A large ungated TPC with GEM amplification

NASA Astrophysics Data System (ADS)

Berger, M.; Ball, M.; Fabbietti, L.; Ketzer, B.; Arora, R.; Beck, R.; Böhmer, F. V.; Chen, J.-C.; Cusanno, F.; Dørheim, S.; García, F.; Hehner, J.; Herrmann, N.; Höppner, C.; Kaiser, D.; Kis̆, M.; Kleipa, V.; Konorov, I.; Kunkel, J.; Kurz, N.; Leifels, Y.; Müllner, P.; Münzer, R.; Neubert, S.; Rauch, J.; Schmidt, C. J.; Schmitz, R.; Soyk, D.; Vandenbroucke, M.; Voss, B.; Walther, D.; Zmeskal, J.

2017-10-01

A Time Projection Chamber (TPC) is an ideal device for the detection of charged particle tracks in a large volume covering a solid angle of almost 4 π. The high density of hits on a given particle track facilitates the task of pattern recognition in a high-occupancy environment and in addition provides particle identification by measuring the specific energy loss for each track. For these reasons, TPCs with Multiwire Proportional Chamber (MWPC) amplification have been and are widely used in experiments recording heavy-ion collisions. A significant drawback, however, is the large dead time of the order of 1 ms per event generated by the use of a gating grid, which is mandatory to prevent ions created in the amplification region from drifting back into the drift volume, where they would severely distort the drift path of subsequent tracks. For experiments with higher event rates this concept of a conventional TPC operating with a triggered gating grid can therefore not be applied without a significant loss of data. A continuous readout of the signals is the more appropriate way of operation. This, however, constitutes a change of paradigm with considerable challenges to be met concerning the amplification region, the design and bandwidth of the readout electronics, and the data handling. A mandatory prerequisite for such an operation is a sufficiently good suppression of the ion backflow from the avalanche region, which otherwise limits the tracking and particle identification capabilities of such a detector. Gas Electron Multipliers (GEM) are a promising candidate to combine excellent spatial resolution with an intrinsic suppression of ions. In this paper we describe the design, construction and the commissioning of a large TPC with GEM amplification and without gating grid (GEM-TPC). The design requirements have driven innovations in the construction of a light-weight field-cage, a supporting media flange, the GEM amplification and the readout system, which are presented in this paper. We further describe the support infrastructure such as gas, cooling and slow control. Finally, we report on the operation of the GEM-TPC in the FOPI experiment, and describe the calibration procedures which are applied to achieve the design performance of the device.

Transport properties of silicon complementary-metal-oxide semiconductor quantum well field-effect transistors

NASA Astrophysics Data System (ADS)

Naquin, Clint Alan

Introducing explicit quantum transport into silicon (Si) transistors in a manner compatible with industrial fabrication has proven challenging, yet has the potential to transform the performance horizons of large scale integrated Si devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors fabricated using industrial silicon complementary MOS processing. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (VG) spacing between NDTCs. The VG spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background. A folding amplifier frequency multiplier circuit using a single QW NMOS transistor to generate a folded current-voltage transfer function via a NDTC was demonstrated. Time domain data shows frequency doubling in the kHz range at room temperature, and Fourier analysis confirms that the output is dominated by the second harmonic of the input. De-embedding the circuit response characteristics from parasitic cable and contact impedances suggests that in the absence of parasitics the doubling bandwidth could be as high as 10 GHz in a monolithic integrated circuit, limited by the transresistance magnitude of the QW NMOS. This is the first example of a QW device fabricated by mainstream Si CMOS technology being used in a circuit application and establishes the feasibility of scalable CMOS circuits that exploit explicit quantum transport. Ongoing quantum transport simulations based off of the spatial dopant distribution suggests a quasi-parabolic potential profile. Energy spacings between resonant transmission states are not consistent with experimental data, suggesting that either the assumed transport model is incomplete, or scattering mechanisms significantly mix the quasi-bound states and broaden the energy spacings.

Interconnections Seam Study | Energy Analysis | NREL

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Interconnections Seam Study Interconnections Seam Study Through the Interconnections Seam Study between the interconnections. This study will quantify the value of strengthening the connections (or Peer Review - Interconnections Seam Study to learn more. Our Approach To quantify the value of

Paired comparisons of nonlinear frequency compression, extended bandwidth, and restricted bandwidth hearing-aid processing for children and adults with hearing loss

PubMed Central

Brennan, Marc A.; McCreery, Ryan; Kopun, Judy; Hoover, Brenda; Alexander, Joshua; Lewis, Dawna; Stelmachowicz, Patricia G.

2014-01-01

Background Preference for speech and music processed with nonlinear frequency compression and two controls (restricted and extended bandwidth hearing-aid processing) was examined in adults and children with hearing loss. Purpose Determine if stimulus type (music, sentences), age (children, adults) and degree of hearing loss influence listener preference for nonlinear frequency compression, restricted bandwidth and extended bandwidth. Research Design Within-subject, quasi-experimental study. Using a round-robin procedure, participants listened to amplified stimuli that were 1) frequency-lowered using nonlinear frequency compression, 2) low-pass filtered at 5 kHz to simulate the restricted bandwidth of conventional hearing aid processing, or 3) low-pass filtered at 11 kHz to simulate extended bandwidth amplification. The examiner and participants were blinded to the type of processing. Using a two-alternative forced-choice task, participants selected the preferred music or sentence passage. Study Sample Sixteen children (8–16 years) and 16 adults (19–65 years) with mild-to-severe sensorineural hearing loss. Intervention All subjects listened to speech and music processed using a hearing-aid simulator fit to the Desired Sensation Level algorithm v.5.0a (Scollie et al, 2005). Results Children and adults did not differ in their preferences. For speech, participants preferred extended bandwidth to both nonlinear frequency compression and restricted bandwidth. Participants also preferred nonlinear frequency compression to restricted bandwidth. Preference was not related to degree of hearing loss. For music, listeners did not show a preference. However, participants with greater hearing loss preferred nonlinear frequency compression to restricted bandwidth more than participants with less hearing loss. Conversely, participants with greater hearing loss were less likely to prefer extended bandwidth to restricted bandwidth. Conclusion Both age groups preferred access to high frequency sounds, as demonstrated by their preference for either the extended bandwidth or nonlinear frequency compression conditions over the restricted bandwidth condition. Preference for extended bandwidth can be limited for those with greater degrees of hearing loss, but participants with greater hearing loss may be more likely to prefer nonlinear frequency compression. Further investigation using participants with more severe hearing loss may be warranted. PMID:25514451