a High-Level Technique for Estimation and Optimization of Leakage Power for Full Adder

NASA Astrophysics Data System (ADS)

Shrivas, Jayram; Akashe, Shyam; Tiwari, Nitesh

2013-06-01

Optimization of power is a very important issue in low-voltage and low-power application. In this paper, we have proposed power gating technique to reduce leakage current and leakage power of one-bit full adder. In this power gating technique, we use two sleep transistors i.e., PMOS and NMOS. PMOS sleep transistor is inserted between power supply and pull up network. And NMOS sleep transistor is inserted between pull down network and ground terminal. These sleep transistors (PMOS and NMOS) are turned on when the circuit is working in active mode. And sleep transistors (PMOS and NMOS) are turned off when circuit is working in standby mode. We have simulated one-bit full adder and compared with the power gating technique using cadence virtuoso tool in 45 nm technology at 0.7 V at 27°C. By applying this technique, we have reduced leakage current from 2.935 pA to 1.905 pA and leakage power from 25.04μw to 9.233μw. By using this technique, we have reduced leakage power up to 63.12%.

Leakage and field emission in side-gate graphene field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Di Bartolomeo, A., E-mail: dibant@sa.infn.it; Iemmo, L.; Romeo, F.

We fabricate planar graphene field-effect transistors with self-aligned side-gate at 100 nm from the 500 nm wide graphene conductive channel, using a single lithographic step. We demonstrate side-gating below 1 V with conductance modulation of 35% and transconductance up to 0.5 mS/mm at 10 mV drain bias. We measure the planar leakage along the SiO{sub 2}/vacuum gate dielectric over a wide voltage range, reporting rapidly growing current above 15 V. We unveil the microscopic mechanisms driving the leakage, as Frenkel-Poole transport through SiO{sub 2} up to the activation of Fowler-Nordheim tunneling in vacuum, which becomes dominant at higher voltages. We report a field-emission current densitymore » as high as 1 μA/μm between graphene flakes. These findings are important for the miniaturization of atomically thin devices.« less

Mechanism of oxide thickness and temperature dependent current conduction in n+-polySi/SiO2/p-Si structures — a new analysis

NASA Astrophysics Data System (ADS)

Samanta, Piyas

2017-10-01

The conduction mechanism of gate leakage current through thermally grown silicon dioxide (SiO2) films on (100) p-type silicon has been investigated in detail under negative bias on the degenerately doped n-type polysilicon (n+-polySi) gate. The analysis utilizes the measured gate current density J G at high oxide fields E ox in 5.4 to 12 nm thick SiO2 films between 25 and 300 °C. The leakage current measured up to 300 °C was due to Fowler-Nordheim (FN) tunneling of electrons from the accumulated n +-polySi gate in conjunction with Poole Frenkel (PF) emission of trapped-electrons from the electron traps located at energy levels ranging from 0.6 to 1.12 eV (depending on the oxide thickness) below the SiO2 conduction band (CB). It was observed that PF emission current I PF dominates FN electron tunneling current I FN at oxide electric fields E ox between 6 and 10 MV/cm and throughout the temperature range studied here. Understanding of the mechanism of leakage current conduction through SiO2 films plays a crucial role in simulation of time-dependent dielectric breakdown (TDDB) of metaloxide-semiconductor (MOS) devices and to precisely predict the normal operating field or applied gate voltage for lifetime projection of the MOS integrated circuits.

Low dislocation density InAlN/AlN/GaN heterostructures grown on GaN substrates and the effects on gate leakage characteristics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kotani, Junji, E-mail: kotani.junji-01@jp.fujitsu.com; Yamada, Atsushi; Ishiguro, Tetsuro

2016-04-11

This paper reports on the electrical characterization of Ni/Au Schottky diodes fabricated on InAlN high-electron-mobility transistor (HEMT) structures grown on low dislocation density free-standing GaN substrates. InAlN HEMT structures were grown on sapphire and GaN substrates by metal-organic vapor phase epitaxy, and the effects of threading dislocation density on the leakage characteristics of Ni/Au Schottky diodes were investigated. Threading dislocation densities were determined to be 1.8 × 10{sup 4 }cm{sup −2} and 1.2 × 10{sup 9 }cm{sup −2} by the cathodoluminescence measurement for the HEMT structures grown on GaN and sapphire substrates, respectively. Leakage characteristics of Ni/Au Schottky diodes were compared between the two samples, andmore » a reduction of the leakage current of about three to four orders of magnitude was observed in the forward bias region. For the high reverse bias region, however, no significant improvement was confirmed. We believe that the leakage current in the low bias region is governed by a dislocation-related Frenkel–Poole emission, and the leakage current in the high reverse bias region originates from field emission due to the large internal electric field in the InAlN barrier layer. Our results demonstrated that the reduction of dislocation density is effective in reducing leakage current in the low bias region. At the same time, it was also revealed that another approach will be needed, for instance, band modulation by impurity doping and insertion of insulating layers beneath the gate electrodes for a substantial reduction of the gate leakage current.« less

Open-Gated pH Sensor Fabricated on an Undoped-AlGaN/GaN HEMT Structure

PubMed Central

Abidin, Mastura Shafinaz Zainal; Hashim, Abdul Manaf; Sharifabad, Maneea Eizadi; Rahman, Shaharin Fadzli Abd; Sadoh, Taizoh

2011-01-01

The sensing responses in aqueous solution of an open-gated pH sensor fabricated on an AlGaN/GaN high-electron-mobility-transistor (HEMT) structure are investigated. Under air-exposed ambient conditions, the open-gated undoped AlGaN/GaN HEMT only shows the presence of a linear current region. This seems to show that very low Fermi level pinning by surface states exists in the undoped AlGaN/GaN sample. In aqueous solution, typical current-voltage (I-V) characteristics with reasonably good gate controllability are observed, showing that the potential of the AlGaN surface at the open-gated area is effectively controlled via aqueous solution by the Ag/AgCl gate electrode. The open-gated undoped AlGaN/GaN HEMT structure is capable of distinguishing pH level in aqueous electrolytes and exhibits linear sensitivity, where high sensitivity of 1.9 mA/pH or 3.88 mA/mm/pH at drain-source voltage, VDS = 5 V is obtained. Due to the large leakage current where it increases with the negative gate voltage, Nernstian like sensitivity cannot be determined as commonly reported in the literature. This large leakage current may be caused by the technical factors rather than any characteristics of the devices. Surprisingly, although there are some imperfections in the device preparation and measurement, the fabricated devices work very well in distinguishing the pH levels. Suppression of current leakage by improving the device preparation is likely needed to improve the device performance. The fabricated device is expected to be suitable for pH sensing applications. PMID:22163786

Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

NASA Astrophysics Data System (ADS)

Park, Hyeonwoo; Teramoto, Akinobu; Kuroda, Rihito; Suwa, Tomoyuki; Sugawa, Shigetoshi

2018-04-01

Localized stress-induced leakage current (SILC) has become a major problem in the reliability of flash memories. To reduce it, clarifying the SILC mechanism is important, and statistical measurement and analysis have to be carried out. In this study, we applied an array test circuit that can measure the SILC distribution of more than 80,000 nMOSFETs with various gate areas at a high speed (within 80 s) and a high accuracy (on the 10-17 A current order). The results clarified that the distributions of localized SILC in different gate areas follow a universal distribution assuming the same SILC defect density distribution per unit area, and the current of localized SILC defects does not scale down with the gate area. Moreover, the distribution of SILC defect density and its dependence on the oxide field for measurement (E OX-Measure) were experimentally determined for fabricated devices.

Fabrication and characterization of tensile In0.3Al0.7As barrier and compressive In0.7Ga0.3As channel pHEMTs having extremely low gate leakage for low-noise applications

NASA Astrophysics Data System (ADS)

Packeer, F.; Mohamad Isa, M.; Mat Jubadi, W.; Ian, K. W.; Missous, M.

2013-07-01

This study focuses on the area of the epitaxial design, fabrication and characterization of a 1 µm gate-length InP-based pseudomorphic high electron mobility transistor (pHEMT) using InGaAs-InAlAs material systems. The advanced epitaxial layer design incorporates a highly strained aluminum-rich Schottky contact barrier, an indium-rich channel and a double delta-doped structure, which significantly improves upon the conventional low-noise pHEMT which suffers from high gate current leakage and low breakdown voltage. The outstanding achievements of the new design approach are 99% less gate current leakage and a 73% increase in breakdown voltage, compared with the conventional design. Furthermore, no degradation in RF performance is observed in terms of the cut-off frequency in this new highly tensile strained design. The remarkable performance of this advanced pHEMT design facilitates the implementation of outstanding low-noise devices.

Reduction of leakage current at the gate edge of SDB SOI NMOS transistor

NASA Astrophysics Data System (ADS)

Kang, Sung-Weon; Lyu, Jong-Son; Kang, Jin-Young; Kang, Sang-Won; Lee, Jin-Hyo

1995-06-01

Leakage current through the parasitic channel formed at the sidewall of the SOI active region has been investigated by measuring the subthreshold I-V characteristics. Partially depleted (PD, approximately 2500 Angstrom) and fully depleted (FD, approximately 800 Angstrom) SOI NMOS transistors of enhancement mode have been fabricated using the silicon direct bonding (SDB) technology. Isolation processes for the SOI devices were LOCOS, LOCOS with channel stop ion implantation or fully recessed trench (FRT). The electron concentration of the parasitic channel is calculated by the PISCES Ilb simulation. As a result, leakage current of the FD mode SOI device with FRT isolation at the front and back gate biases of 0 V was reduced to approximately pA and no hump was seen on the drain current curve.

Band to Band Tunneling (BBT) Induced Leakage Current Enhancement in Irradiated Fully Depleted SOI Devices

NASA Technical Reports Server (NTRS)

Adell, Phillipe C.; Barnaby, H. J.; Schrimpf, R. D.; Vermeire, B.

2007-01-01

We propose a model, validated with simulations, describing how band-to-band tunneling (BBT) affects the leakage current degradation in some irradiated fully-depleted SOI devices. The dependence of drain current on gate voltage, including the apparent transition to a high current regime is explained.

Fabrication and Benchmarking of a Stratix V FPGA with Monolithic Integrated Microfluidic Cooling

DTIC Science & Technology

2017-03-01

run. The output from all cores were monitored through the Altera Signaltap tool in order to detect glitches which occurred in the output...dependence on temperature, and static/ leakage power, which comes from several components, such as subthreshold leakage , gate leakage , and reverse bias 220...junction current. Subthreshold leakage current tends to be the most significant temperature dependent component of the power [6,7] and is given by

GaN-on-silicon high-electron-mobility transistor technology with ultra-low leakage up to 3000 V using local substrate removal and AlN ultra-wide bandgap

NASA Astrophysics Data System (ADS)

Dogmus, Ezgi; Zegaoui, Malek; Medjdoub, Farid

2018-03-01

We report on extremely low off-state leakage current in AlGaN/GaN-on-silicon metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) up to a high blocking voltage. Remarkably low off-state gate and drain leakage currents below 1 µA/mm up to 3 kV have been achieved owing to the use of a thick in situ SiN gate dielectric under the gate, and a local Si substrate removal technique combined with a cost effective 15-µm-thick AlN dielectric layer followed by a Cu deposition. This result establishes a manufacturable state-of-the-art high-voltage GaN-on-silicon power transistors while maintaining a low specific on-resistance of approximately 10 mΩ·cm2.

An “ohmic-first” self-terminating gate-recess technique for normally-off Al2O3/GaN MOSFET

NASA Astrophysics Data System (ADS)

Wang, Hongyue; Wang, Jinyan; Li, Mengjun; He, Yandong; Wang, Maojun; Yu, Min; Wu, Wengang; Zhou, Yang; Dai, Gang

2018-04-01

In this article, an ohmic-first AlGaN/GaN self-terminating gate-recess etching technique was demonstrated where ohmic contact formation is ahead of gate-recess-etching/gate-dielectric-deposition (GRE/GDD) process. The ohmic contact exhibits few degradations after the self-terminating gate-recess process. Besides, when comparing with that using the conventional fabrication process, the fabricated device using the ohmic-first fabrication process shows a better gate dielectric quality in terms of more than 3 orders lower forward gate leakage current, more than twice higher reverse breakdown voltage as well as better stability. Based on this proposed technique, the normally-off Al2O3/GaN MOSFET exhibits a threshold voltage (V th) of ˜1.8 V, a maximum drain current of ˜328 mA/mm, a forward gate leakage current of ˜10-6 A/mm and an off-state breakdown voltage of 218 V at room temperature. Meanwhile, high temperature characteristics of the device was also evaluated and small variations (˜7.6%) of the threshold voltage was confirmed up to 300 °C.

Improved dc and power performance of AlGaN/GaN high electron mobility transistors with Sc 2O 3 gate dielectric or surface passivation

NASA Astrophysics Data System (ADS)

Luo, B.; Mehandru, R.; Kim, Jihyun; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Gotthold, D.; Birkhahn, R.; Peres, B.; Fitch, R. C.; Moser, N.; Gillespie, J. K.; Jessen, G. H.; Jenkins, T. J.; Yannuzi, M. J.; Via, G. D.; Crespo, A.

2003-10-01

The dc and power characteristics of AlGaN/GaN MOS-HEMTs with Sc 2O 3 gate dielectrics were compared with that of conventional metal-gate HEMTs fabricated on the same material. The MOS-HEMT shows higher saturated drain-source current (˜0.75 A/mm) and significantly better power-added efficiency (PAE, 27%) relative to the HEMT (˜0.6 A/mm and ˜5%). The Sc 2O 3 also provides effective surface passivation, with higher drain current, lower leakage currents and higher three-terminal breakdown voltage in passivated devices relative to unpassivated devices. The PAE also increases (from ˜5% to 12%) on the surface passivated HEMTs, showing that Sc 2O 3 is an attractive option for reducing gate and surface leakage in AlGaN/GaN heterostructure transistors.

Free energy dissipation of the spontaneous gating of a single voltage-gated potassium channel.

PubMed

Wang, Jia-Zeng; Wang, Rui-Zhen

2018-02-01

Potassium channels mainly contribute to the resting potential and re-polarizations, with the potassium electrochemical gradient being maintained by the pump Na + /K + -ATPase. In this paper, we construct a stochastic model mimicking the kinetics of a potassium channel, which integrates temporal evolving of the membrane voltage and the spontaneous gating of the channel. Its stationary probability density functions (PDFs) are found to be singular at the boundaries, which result from the fact that the evolving rates of voltage are greater than the gating rates of the channel. We apply PDFs to calculate the power dissipations of the potassium current, the leakage, and the gating currents. On a physical perspective, the essential role of the system is the K + -battery charging the leakage (L-)battery. A part of power will inevitably be dissipated among the process. So, the efficiency of energy transference is calculated.

Free energy dissipation of the spontaneous gating of a single voltage-gated potassium channel

NASA Astrophysics Data System (ADS)

Wang, Jia-Zeng; Wang, Rui-Zhen

2018-02-01

Potassium channels mainly contribute to the resting potential and re-polarizations, with the potassium electrochemical gradient being maintained by the pump Na+/K+-ATPase. In this paper, we construct a stochastic model mimicking the kinetics of a potassium channel, which integrates temporal evolving of the membrane voltage and the spontaneous gating of the channel. Its stationary probability density functions (PDFs) are found to be singular at the boundaries, which result from the fact that the evolving rates of voltage are greater than the gating rates of the channel. We apply PDFs to calculate the power dissipations of the potassium current, the leakage, and the gating currents. On a physical perspective, the essential role of the system is the K+-battery charging the leakage (L-)battery. A part of power will inevitably be dissipated among the process. So, the efficiency of energy transference is calculated.

Suppression of gate leakage current in in-situ grown AlN/InAlN/AlN/GaN heterostructures based on the control of internal polarization fields

NASA Astrophysics Data System (ADS)

Kotani, Junji; Yamada, Atsushi; Ishiguro, Tetsuro; Yamaguchi, Hideshi; Nakamura, Norikazu

2017-03-01

This paper investigates the gate leakage characteristics of in-situ AlN capped InAlN/AlN/GaN heterostructures grown by metal-organic vapor phase epitaxy. It was revealed that the leakage characteristics of AlN capped InAlN/AlN/GaN heterostructures are strongly dependent on the growth temperature of the AlN cap. For an AlN capped structure with an AlN growth temperature of 740 °C, the leakage current even increased although there exists a large bandgap material on InAlN/AlN/GaN heterostructures. On the other hand, a large reduction of the gate leakage current by 4-5 orders of magnitudes was achieved with a very low AlN growth temperature of 430 °C. X-ray diffraction analysis of the AlN cap grown at 740 °C indicated that the AlN layer is tensile-strained. In contrast to this result, the amorphous structure was confirmed for the AlN cap grown at 430 °C by transmission electron microscopy. Furthermore, theoretical analysis based on one-dimensional band simulation was carried out, and the large increase in two-dimensional electron gas (2DEG) observed in Hall measurements was well reproduced by taking into account the spontaneous and piezo-electric polarization in the AlN layer grown at 740 °C. For the AlN capped structure grown at 430 °C, it is believed that the reduced polarization field in the AlN cap suppressed the penetration of 2DEG into the InAlN barrier layer, resulting in a small impact on 2DEG mobility and density. We believe that an in-situ grown AlN cap with a very low growth temperature of 430 °C is a promising candidate for high-frequency/high-power GaN-based devices with low gate leakage current.

Short-Channel Tunneling Field-Effect Transistor with Drain-Overlap and Dual-Metal Gate Structure for Low-Power and High-Speed Operations.

PubMed

Yoon, Young Jun; Eun, Hye Rim; Seo, Jae Hwa; Kang, Hee-Sung; Lee, Seong Min; Lee, Jeongmin; Cho, Seongjae; Tae, Heung-Sik; Lee, Jung-Hee; Kang, In Man

2015-10-01

We have investigated and proposed a highly scaled tunneling field-effect transistor (TFET) based on Ge/GaAs heterojunction with a drain overlap to suppress drain-induced barrier thinning (DIBT) and improve low-power (LP) performance. The highly scaled TFET with a drain overlap achieves lower leakage tunneling current because of the decrease in tunneling events between the source and drain, whereas a typical short-channel TFET suffers from a great deal of tunneling leakage current due to the DIBT at the off-state. However, the drain overlap inevitably increases the gate-to-drain capacitance (Cgd) because of the increase in the overlap capacitance (Cov) and inversion capacitance (Cinv). Thus, in this work, a dual-metal gate structure is additionally applied along with the drain overlap. The current performance and the total gate capacitance (Cgg) of the device with a dual-metal gate can be possibly controlled by adjusting the metal gate workfunction (φgate) and φoverlap-gate in the overlapping regions. As a result, the intrinsic delay time (τ) is greatly reduced by obtaining lower Cgg divided by the on-state current (Ion), i.e., Cgg/Ion. We have successfully demonstrated excellent LP and high-speed performance of a highly scaled TFET by adopting both drain overlap and dual-metal gate with DIBT minimization.

Design and simulation of nanoscale double-gate TFET/tunnel CNTFET

NASA Astrophysics Data System (ADS)

Bala, Shashi; Khosla, Mamta

2018-04-01

A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si), gallium arsenide (GaAs), alminium gallium arsenide (Al x Ga1‑x As) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are compared on the basis of inverse subthreshold slope (SS), I ON/I OFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the Al x Ga1‑x As based DG tunnel FET provides a better I ON/I OFF current ratio (2.51 × 106) as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE PAGES

King, M. P.; Wu, X.; Eller, Manfred; ...

2016-12-07

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

King, M. P.; Wu, X.; Eller, Manfred

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Deposition temperature dependent optical and electrical properties of ALD HfO{sub 2} gate dielectrics pretreated with tetrakisethylmethylamino hafnium

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, J.; School of Sciences, Anhui University of Science and Technology, Huainan 232001; He, G., E-mail: hegang@ahu.edu.cn

2015-10-15

Highlights: • ALD-derived HfO{sub 2} gate dielectrics have been deposited on Si substrates. • The leakage current mechanism for different deposition temperature was discussed. • Different emission at different field region has been determined precisely. - Abstract: The effect of deposition temperature on the growth rate, band gap energy and electrical properties of HfO{sub 2} thin film deposited by atomic layer deposition (ALD) has been investigated. By means of characterization of spectroscopy ellipsometry and ultraviolet–visible spectroscopy, the growth rate and optical constant of ALD-derived HfO{sub 2} gate dielectrics are determined precisely. The deposition temperature dependent electrical properties of HfO{sub 2}more » films were determined by capacitance–voltage (C–V) and leakage current density–voltage (J–V) measurements. The leakage current mechanism for different deposition temperature has been discussed systematically. As a result, the optimized deposition temperature has been obtained to achieve HfO{sub 2} thin film with high quality.« less

Atomic layer deposition of sub-10 nm high-K gate dielectrics on top-gated MoS2 transistors without surface functionalization

NASA Astrophysics Data System (ADS)

Lin, Yu-Shu; Cheng, Po-Hsien; Huang, Kuei-Wen; Lin, Hsin-Chih; Chen, Miin-Jang

2018-06-01

Sub-10 nm high-K gate dielectrics are of critical importance in two-dimensional transition metal dichalcogenides (TMDs) transistors. However, the chemical inertness of TMDs gives rise to a lot of pinholes in gate dielectrics, resulting in large gate leakage current. In this study, sub-10 nm, uniform and pinhole-free Al2O3 high-K gate dielectrics on MoS2 were achieved by atomic layer deposition without surface functionalization, in which an ultrathin Al2O3 layer prepared with a short purge time at a low temperature of 80 °C offers the nucleation cites for the deposition of the overlaying oxide at a higher temperature. Conductive atomic force microscopy reveals the significant suppression of gate leakage current in the sub-10 nm Al2O3 gate dielectrics with the low-temperature nucleation layer. Raman and X-ray photoelectron spectroscopies indicate that no oxidation occurred during the deposition of the low-temperature Al2O3 nucleation layer on MoS2. With the high-quality sub-10 nm Al2O3 high-K gate dielectrics, low hysteresis and subthreshold swing were demonstrated on the normally-off top-gated MoS2 transistors.

Leakage effects in n-GaAs MESFET with n-GaAs buffer layer

NASA Technical Reports Server (NTRS)

Wang, Y. C.; Bahrami, M.

1983-01-01

Whereas improvement of the interface between the active layer and the buffer layer has been demonstrated, the leakage effects can be important if the buffer layer resistivity is not sufficiently high and/or the buffer layer thickness is not sufficiently small. It was found that two buffer leakage currents exist from the channel under the gate to the source and from drain to the channel in addition to the buffer leakage resistance between drain and source. It is shown that for a 1 micron gate-length n-GaAs MESFET, if the buffer layer resistivity is 12 OHM-CM and the buffer layer thickness h is 2 microns, the performance of the device degrades drastically. It is suggested that h should be below 2 microns.

Sulfuric acid and hydrogen peroxide surface passivation effects on AlGaN/GaN high electron mobility transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zaidi, Z. H., E-mail: zaffar.zaidi@sheffield.ac.uk; Lee, K. B.; Qian, H.

2014-12-28

In this work, we have compared SiN{sub x} passivation, hydrogen peroxide, and sulfuric acid treatment on AlGaN/GaN HEMTs surface after full device fabrication on Si substrate. Both the chemical treatments resulted in the suppression of device pinch-off gate leakage current below 1 μA/mm, which is much lower than that for SiN{sub x} passivation. The greatest suppression over the range of devices is observed with the sulfuric acid treatment. The device on/off current ratio is improved (from 10{sup 4}–10{sup 5} to 10{sup 7}) and a reduction in the device sub-threshold (S.S.) slope (from ∼215 to 90 mV/decade) is achieved. The sulfuric acid ismore » believed to work by oxidizing the surface which has a strong passivating effect on the gate leakage current. The interface trap charge density (D{sub it}) is reduced (from 4.86 to 0.90 × 10{sup 12 }cm{sup −2} eV{sup −1}), calculated from the change in the device S.S. The gate surface leakage current mechanism is explained by combined Mott hopping conduction and Poole Frenkel models for both untreated and sulfuric acid treated devices. Combining the sulfuric acid treatment underneath the gate with the SiN{sub x} passivation after full device fabrication results in the reduction of D{sub it} and improves the surface related current collapse.« less

Push the flash floating gate memories toward the future low energy application

NASA Astrophysics Data System (ADS)

Della Marca, V.; Just, G.; Regnier, A.; Ogier, J.-L.; Simola, R.; Niel, S.; Postel-Pellerin, J.; Lalande, F.; Masoero, L.; Molas, G.

2013-01-01

In this paper the energy consumption of flash floating gate cell, during a channel hot electron operation, is investigated. We characterize the device using different ramp and box pulses on control gate, to find the best solution to have low energy consumption and good cell performances. We use a new dynamic method to measure the drain current absorption in order to evaluate the impact of different bias conditions, and to study the cell behavior. The programming window and the energy consumption are considered as fundamental parameters. Using this dynamic technique, three zones of work are found; it is possible to optimize the drain voltage during the programming operation to minimize the energy consumption. Moreover, the cell's performances are improved using the CHISEL effect, with a reverse body bias. After the study concerning the programming pulses adjusting, we show the results obtained by increasing the channel doping dose parameter. Considering a channel hot electron programming operation, it is important to focus our attention on the bitline leakage consumption contribution. We measured it for the unselected bitline cells, and we show the effects of the lightly doped drain implantation energy on the leakage current. In this way the impact of gate induced drain leakage in band-to-band tunneling regime decreases, improving the cell's performances in a memory array.

Enhanced performance of solution-processed organic thin-film transistors with a low-temperature-annealed alumina interlayer between the polyimide gate insulator and the semiconductor.

PubMed

Yoon, Jun-Young; Jeong, Sunho; Lee, Sun Sook; Kim, Yun Ho; Ka, Jae-Won; Yi, Mi Hye; Jang, Kwang-Suk

2013-06-12

We studied a low-temperature-annealed sol-gel-derived alumina interlayer between the organic semiconductor and the organic gate insulator for high-performance organic thin-film transistors. The alumina interlayer was deposited on the polyimide gate insulator by a simple spin-coating and 200 °C-annealing process. The leakage current density decreased by the interlayer deposition: at 1 MV/cm, the leakage current densities of the polyimide and the alumina/polyimide gate insulators were 7.64 × 10(-7) and 3.01 × 10(-9) A/cm(2), respectively. For the first time, enhancement of the organic thin-film transistor performance by introduction of an inorganic interlayer between the organic semiconductor and the organic gate insulator was demonstrated: by introducing the interlayer, the field-effect mobility of the solution-processed organic thin-film transistor increased from 0.35 ± 0.15 to 1.35 ± 0.28 cm(2)/V·s. Our results suggest that inorganic interlayer deposition could be a simple and efficient surface treatment of organic gate insulators for enhancing the performance of solution-processed organic thin-film transistors.

Gate length scaling optimization of FinFETs

NASA Astrophysics Data System (ADS)

Chen, Shoumian; Shang, Enming; Hu, Shaojian

2018-06-01

This paper introduces a device performance optimization approach for the FinFET through optimization of the gate length. As a result of reducing the gate length, the leakage current (Ioff) increases, and consequently, the stress along the channel enhances which leads to an increase in the drive current (Isat) of the PMOS. In order to sustain Ioff, work function is adjusted to offset the effect of the increased stress. Changing the gate length of the transistor yields different drive currents when the leakage current is fixed by adjusting the work function. For a given device, an optimal gate length is found to provide the highest drive current. As an example, for a standard performance device with Ioff = 1 nA/um, the best performance Isat = 856 uA/um is at L = 34 nm for 14 nm FinFET and Isat = 1130 uA/um at L = 21 nm for 7 nm FinFET. A 7 nm FinFET will exhibit performance boost of 32% comparing with 14 nm FinFET. However, applying the same method to a 5 nm FinFET, the performance boosting is out of expectance comparing to the 7 nm FinFET, which is due to the severe short-channel-effect and the exhausted channel stress in the FinFET.

First-principles study on leakage current caused by oxygen vacancies at HfO2/SiO2/Si interface

NASA Astrophysics Data System (ADS)

Takagi, Kensuke; Ono, Tomoya

2018-06-01

The relationship between the position of oxygen vacancies in HfO2/SiO2/Si gate stacks and the leakage current is studied by first-principles electronic-structure and electron-conduction calculations. We find that the increase in the leakage current due to the creation of oxygen vacancies in the HfO2 layer is much larger than that in the SiO2 interlayer. According to previous first-principles total energy calculations, the formation energy of oxygen vacancies is smaller in the SiO2 interlayer than that in the HfO2 layer under the same conditions. Therefore, oxygen vacancies will be attracted from the SiO2 interlayer to minimize the energy, thermodynamically justifying the scavenging technique. Thus, the scavenging process efficiently improves the dielectric constant of HfO2-based gate stacks without increasing the number of oxygen vacancies, which cause the dielectric breakdown.

Effect of high-pressure H{sub 2}O treatment on elimination of interfacial GeO{sub X} layer between ZrO{sub 2} and Ge stack

DOE Office of Scientific and Technical Information (OSTI.GOV)

Huang, Chen-Shuo; Liu, Po-Tsun

2011-08-22

This investigation demonstrates the effect of high-pressure H{sub 2}O treatment on the elimination of the interfacial germanium suboxide (GeO{sub X}) layer between ZrO{sub 2} and Ge. The formation of GeO{sub X} interlayer increases the gate-leakage current and worsen the controllability of the gate during deposition or thermal cycles. X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy reveal that high-pressure H{sub 2}O treatment eliminates the interfacial GeO{sub X} layer. The physical mechanism involves the oxidation of non-oxidized Zr with H{sub 2}O and the reduction of GeO{sub X} by H{sub 2}. Treatment with H{sub 2}O reduces the gate-leakage current of a ZrO{submore » 2}/Ge capacitor by a factor of 1000.« less

Physical understanding of trends in current collapse with atomic layer deposited dielectrics in AlGaN/GaN MOS heterojunction FETs

NASA Astrophysics Data System (ADS)

Ramanan, Narayanan; Lee, Bongmook; Misra, Veena

2016-03-01

Many passivation dielectrics are pursued for suppressing current collapse due to trapping/detrapping of access-region surface traps in AlGaN/GaN based metal oxide semiconductor heterojuction field effect transistors (MOS-HFETs). The suppression of current collapse can potentially be achieved either by reducing the interaction of surface traps with the gate via surface leakage current reduction, or by eliminating surface traps that can interact with the gate. But, the latter is undesirable since a high density of surface donor traps is required to sustain a high 2D electron gas density at the AlGaN/GaN heterointerface and provide a low ON-resistance. This presents a practical trade-off wherein a passivation dielectric with the optimal surface trap characteristics and minimal surface leakage is to be chosen. In this work, we compare MOS-HFETs fabricated with popular ALD gate/passivation dielectrics like SiO2, Al2O3, HfO2 and HfAlO along with an additional thick plasma-enhanced chemical vapor deposition SiO2 passivation. It is found that after annealing in N2 at 700 °C, the stack containing ALD HfAlO provides a combination of low surface leakage and a high density of shallow donor traps. Physics-based TCAD simulations confirm that this combination of properties helps quick de-trapping and minimal current collapse along with a low ON resistance.

2 kV slanted tri-gate GaN-on-Si Schottky barrier diodes with ultra-low leakage current

NASA Astrophysics Data System (ADS)

Ma, Jun; Matioli, Elison

2018-01-01

This letter reports lateral GaN-on-Si power Schottky barrier diodes (SBDs) with unprecedented voltage-blocking performance by integrating 3-dimensionally a hybrid of tri-anode and slanted tri-gate architectures in their anode. The hybrid tri-anode pins the voltage drop at the Schottky junction (VSCH), despite a large applied reverse bias, fixing the reverse leakage current (IR) of the SBD. Such architecture led to an ultra-low IR of 51 ± 5.9 nA/mm at -1000 V, in addition to a small turn-on voltage (VON) of 0.61 ± 0.03 V. The slanted tri-gate effectively distributes the electric field in OFF state, leading to a remarkably high breakdown voltage (VBR) of -2000 V at 1 μA/mm, constituting a significant breakthrough from existing technologies. The approach pursued in this work reduces the IR and increases the VBR without sacrificing the VON, which provides a technology for high-voltage SBDs, and unveils the unique advantage of tri-gates for advanced power applications.

Efficient Z gates for quantum computing

NASA Astrophysics Data System (ADS)

McKay, David C.; Wood, Christopher J.; Sheldon, Sarah; Chow, Jerry M.; Gambetta, Jay M.

2017-08-01

For superconducting qubits, microwave pulses drive rotations around the Bloch sphere. The phase of these drives can be used to generate zero-duration arbitrary virtual Z gates, which, combined with two Xπ /2 gates, can generate any SU(2) gate. Here we show how to best utilize these virtual Z gates to both improve algorithms and correct pulse errors. We perform randomized benchmarking using a Clifford set of Hadamard and Z gates and show that the error per Clifford is reduced versus a set consisting of standard finite-duration X and Y gates. Z gates can correct unitary rotation errors for weakly anharmonic qubits as an alternative to pulse-shaping techniques such as derivative removal by adiabatic gate (DRAG). We investigate leakage and show that a combination of DRAG pulse shaping to minimize leakage and Z gates to correct rotation errors realizes a 13.3 ns Xπ /2 gate characterized by low error [1.95 (3 ) ×10-4] and low leakage [3.1 (6 ) ×10-6] . Ultimately leakage is limited by the finite temperature of the qubit, but this limit is two orders of magnitude smaller than pulse errors due to decoherence.

2D Quantum Transport Modeling in Nanoscale MOSFETs

NASA Technical Reports Server (NTRS)

Svizhenko, Alexei; Anantram, M. P.; Govindan, T. R.; Biegel, Bryan

2001-01-01

With the onset of quantum confinement in the inversion layer in nanoscale MOSFETs, behavior of the resonant level inevitably determines all device characteristics. While most classical device simulators take quantization into account in some simplified manner, the important details of electrostatics are missing. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL, and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density- gradient and quantum-corrected MEDICI). We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions, oxide tunneling and phase-breaking scattering are treated on equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. Quantum simulations are focused on MIT 25, 50 and 90 nm "well- tempered" MOSFETs and compared to classical and quantum corrected models. The important feature of quantum model is smaller slope of Id-Vg curve and consequently higher threshold voltage. These results are quantitatively consistent with I D Schroedinger-Poisson calculations. The effect of gate length on gate-oxide leakage and sub-threshold current has been studied. The shorter gate length device has an order of magnitude smaller current at zero gate bias than the longer gate length device without a significant trade-off in on-current. This should be a device design consideration.

Improvement on the electrical characteristics of Pd/HfO2/6H-SiC MIS capacitors using post deposition annealing and post metallization annealing

NASA Astrophysics Data System (ADS)

Esakky, Papanasam; Kailath, Binsu J.

2017-08-01

HfO2 as a gate dielectric enables high electric field operation of SiC MIS structure and as gas sensor HfO2/SiC capacitors offer higher sensitivity than SiO2/SiC capacitors. The issue of higher density of oxygen vacancies and associated higher leakage current necessitates better passivation of HfO2/SiC interface. Effect of post deposition annealing in N2O plasma and post metallization annealing in forming gas on the structural and electrical characteristics of Pd/HfO2/SiC MIS capacitors are reported in this work. N2O plasma annealing suppresses crystallization during high temperature annealing thereby improving the thermal stability and plasma annealing followed by rapid thermal annealing in N2 result in formation of Hf silicate at the HfO2/SiC interface resulting in order of magnitude lower density of interface states and gate leakage current. Post metallization annealing in forming gas for 40 min reduces interface state density by two orders while gate leakage current density is reduced by thrice. Post deposition annealing in N2O plasma and post metallization annealing in forming gas are observed to be effective passivation techniques improving the electrical characteristics of HfO2/SiC capacitors.

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

PubMed

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Zhi, Jiang; Yi-Qi, Zhuang; Cong, Li; Ping, Wang; Yu-Qi, Liu

2016-02-01

Trap-assisted tunneling (TAT) has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor (TFET). In this paper, we assess subthreshold performance of double gate TFET (DG-TFET) through a band-to-band tunneling (BTBT) model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile (Dit) and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current. Project supported by the National Natural Science Foundation of China (Grant Nos. 61574109 and 61204092).

Effect of nickel silicide gettering on metal-induced crystallized polycrystalline-silicon thin-film transistors

NASA Astrophysics Data System (ADS)

Kim, Hyung Yoon; Seok, Ki Hwan; Chae, Hee Jae; Lee, Sol Kyu; Lee, Yong Hee; Joo, Seung Ki

2017-06-01

Low-temperature polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) fabricated via metal-induced crystallization (MIC) are attractive candidates for use in active-matrix flat-panel displays. However, these exhibit a large leakage current due to the nickel silicide being trapped at the grain boundaries of the poly-Si. We reduced the leakage current of the MIC poly-Si TFTs by developing a gettering method to remove the Ni impurities using a Si getter layer and natively-formed SiO2 as the etch stop interlayer. The Ni trap state density (Nt) in the MIC poly-Si film decreased after the Ni silicide gettering, and as a result, the leakage current of the MIC poly-Si TFTs decreased. Furthermore, the leakage current of MIC poly-Si TFTs gradually decreased with additional gettering. To explain the gettering effect on MIC poly-Si TFTs, we suggest an appropriate model. He received the B.S. degree in School of Advanced Materials Engineering from Kookmin University, Seoul, South Korea in 2012, and the M.S. degree in Department of Materials Science and Engineering from Seoul National University, Seoul, South Korea in 2014. He is currently pursuing the Ph.D. degree with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and top-gate polycrystalline-silicon thin-film transistors. He received the M.S. degree in innovation technology from Ecol Polytechnique, Palaiseau, France in 2013. He is currently pursuing the Ph.D. degree with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and bottom-gate polycrystalline-silicon thin-film transistors. He is currently pursuing the integrated M.S and Ph.D course with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and copper-gate polycrystalline-silicon thin-film transistors. He is currently pursuing the integrated M.S and Ph.D course with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and bottom-gate polycrystalline-silicon thin-film transistors. He is currently pursuing the integrated M.S and Ph.D course with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and bottom-gate polycrystalline-silicon thin-film transistors. He received the B.S. degree in metallurgical engineering from Seoul National University, Seoul, South Korea, in 1974, and the M.S. and Ph.D. degrees in material science and engineering from Stanford University, Stanford, CA, USA, in 1980 and 1983, respectively. He is currently a Professor with the Department of Materials Science and Engineering, Seoul National University, Seoul.

Improved integration of ultra-thin high-k dielectrics in few-layer MoS2 FET by remote forming gas plasma pretreatment

NASA Astrophysics Data System (ADS)

Wang, Xiao; Zhang, Tian-Bao; Yang, Wen; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

2017-01-01

The effective and high-quality integration of high-k dielectrics on two-dimensional (2D) crystals is essential to the device structure engineering and performance improvement of field-effect transistor (FET) based on the 2D semiconductors. We report a 2D MoS2 transistor with ultra-thin Al2O3 top-gate dielectric (6.1 nm) and extremely low leakage current. Remote forming gas plasma pretreatment was carried out prior to the atomic layer deposition, providing nucleation sites with the physically adsorbed ions on the MoS2 surface. The top gate MoS2 FET exhibited excellent electrical performance, including high on/off current ratio over 109, subthreshold swing of 85 mV/decade and field-effect mobility of 45.03 cm2/V s. Top gate leakage current less than 0.08 pA/μm2 at 4 MV/cm has been obtained, which is the smallest compared with the reported top-gated MoS2 transistors. Such an optimized integration of high-k dielectric in 2D semiconductor FET with enhanced performance is very attractive, and it paves the way towards the realization of more advanced 2D nanoelectronic devices and integrated circuits.

Method for producing silicon thin-film transistors with enhanced forward current drive

DOEpatents

Weiner, K.H.

1998-06-30

A method is disclosed for fabricating amorphous silicon thin film transistors (TFTs) with a polycrystalline silicon surface channel region for enhanced forward current drive. The method is particularly adapted for producing top-gate silicon TFTs which have the advantages of both amorphous and polycrystalline silicon TFTs, but without problem of leakage current of polycrystalline silicon TFTs. This is accomplished by selectively crystallizing a selected region of the amorphous silicon, using a pulsed excimer laser, to create a thin polycrystalline silicon layer at the silicon/gate-insulator surface. The thus created polysilicon layer has an increased mobility compared to the amorphous silicon during forward device operation so that increased drive currents are achieved. In reverse operation the polysilicon layer is relatively thin compared to the amorphous silicon, so that the transistor exhibits the low leakage currents inherent to amorphous silicon. A device made by this method can be used, for example, as a pixel switch in an active-matrix liquid crystal display to improve display refresh rates. 1 fig.

Method for producing silicon thin-film transistors with enhanced forward current drive

DOEpatents

Weiner, Kurt H.

1998-01-01

A method for fabricating amorphous silicon thin film transistors (TFTs) with a polycrystalline silicon surface channel region for enhanced forward current drive. The method is particularly adapted for producing top-gate silicon TFTs which have the advantages of both amorphous and polycrystalline silicon TFTs, but without problem of leakage current of polycrystalline silicon TFTs. This is accomplished by selectively crystallizing a selected region of the amorphous silicon, using a pulsed excimer laser, to create a thin polycrystalline silicon layer at the silicon/gate-insulator surface. The thus created polysilicon layer has an increased mobility compared to the amorphous silicon during forward device operation so that increased drive currents are achieved. In reverse operation the polysilicon layer is relatively thin compared to the amorphous silicon, so that the transistor exhibits the low leakage currents inherent to amorphous silicon. A device made by this method can be used, for example, as a pixel switch in an active-matrix liquid crystal display to improve display refresh rates.

Microdose Induced Drain Leakage Effects in Power Trench MOSFETs: Experiment and Modeling

NASA Astrophysics Data System (ADS)

Zebrev, Gennady I.; Vatuev, Alexander S.; Useinov, Rustem G.; Emeliyanov, Vladimir V.; Anashin, Vasily S.; Gorbunov, Maxim S.; Turin, Valentin O.; Yesenkov, Kirill A.

2014-08-01

We study experimentally and theoretically the micro-dose induced drain-source leakage current in the trench power MOSFETs under irradiation with high-LET heavy ions. We found experimentally that cumulative increase of leakage current occurs by means of stochastic spikes corresponding to a strike of single heavy ion into the MOSFET gate oxide. We simulate this effect with the proposed analytic model allowing to describe (including Monte Carlo methods) both the deterministic (cumulative dose) and stochastic (single event) aspects of the problem. Based on this model the survival probability assessment in space heavy ion environment with high LETs was proposed.

Nonstoichiometric Solution-Processed BaTiO₃ Film for Gate Insulator Applications.

PubMed

Lau, Joyce; Kim, Sangsub; Kim, Hyunki; Koo, Kwangjun; Lee, Jaeseob; Kim, Sangsoo; Choi, Byoungdeog

2018-09-01

Solution processed barium titanate (BTO) was used to fabricate an Al/BaTiO3/p-Si metal-insulator-semiconductor (MIS) structure, which was used as a gate insulator. Changes in the electrical characteristics of the film were investigated as a function of the film thickness and post deposition annealing conditions. Our results showed that a thickness of 5 layers and an annealing temperature of 650 °C produced the highest electrical performance. BaxTi1-xO3 was altered at x = 0.10, 0.30, 0.50, 0.70, 0.90, and 1.0 to investigate changes in the electrical properties as a function of composition. The highest dielectric constant of 87 was obtained for x = 0.10, while the leakage current density was suppressed as Ba content increased. The lowest leakage current density was 1.34×10-10 A/cm2, which was observed at x = 0.90. The leakage current was related to the resistivity of the film, the interface states, and grain densification. Space charge limited current (SCLC) was the dominant leakage mechanism in BTO films based on leakage current analysis. Although a Ba content of x = 0.90 had the highest trap density, the traps were mainly composed of Ti-vacancies, which acted as strong electron traps and affected the film resistivity. A secondary phase, Ba2TiO4, which was observed in cases of excess Ba, acted as a grain refiner and provided faster densification of the film during the thermal process. The absence of a secondary phase in BaO (x = 1.0) led to the formation of many interface states and degradation in the electrical properties. Overall, the insulator properties of BTO were improved when the composition ratio was x = 0.90.

2D Quantum Mechanical Study of Nanoscale MOSFETs

NASA Technical Reports Server (NTRS)

Svizhenko, Alexei; Anantram, M. P.; Govindan, T. R.; Biegel, B.; Kwak, Dochan (Technical Monitor)

2000-01-01

With the onset of quantum confinement in the inversion layer in nanoscale MOSFETs, behavior of the resonant level inevitably determines all device characteristics. While most classical device simulators take quantization into account in some simplified manner, the important details of electrostatics are missing. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL, and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density-gradient and quantum-corrected MEDICI). We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions and oxide tunneling are treated on an equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. We present the results of our simulations of MIT 25, 50 and 90 nm "well-tempered" MOSFETs and compare them to those of classical and quantum corrected models. The important feature of quantum model is smaller slope of Id-Vg curve and consequently higher threshold voltage. Surprisingly, the self-consistent potential profile shows lower injection barrier in the channel in quantum case. These results are qualitatively consistent with ID Schroedinger-Poisson calculations. The effect of gate length on gate-oxide leakage and subthreshold current has been studied. The shorter gate length device has an order of magnitude smaller current at zero gate bias than the longer gate length device without a significant trade-off in on-current. This should be a device design consideration.

Investigation of defect-induced abnormal body current in fin field-effect-transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Kuan-Ju; Tsai, Jyun-Yu; Lu, Ying-Hsin

2015-08-24

This letter investigates the mechanism of abnormal body current at the linear region in n-channel high-k/metal gate stack fin field effect transistors. Unlike body current, which is generated by impact ionization at high drain voltages, abnormal body current was found to increase with decreasing drain voltages. Notably, the unusual body leakage only occurs in three-dimensional structure devices. Based on measurements under different operation conditions, the abnormal body current can be attributed to fin surface defect-induced leakage current, and the mechanism is electron tunneling to the fin via the defects, resulting in holes left at the body terminal.

Osteoblastic cells trigger gate currents on nanocrystalline diamond transistor.

PubMed

Izak, Tibor; Krátká, Marie; Kromka, Alexander; Rezek, Bohuslav

2015-05-01

We show the influence of osteoblastic SAOS-2 cells on the transfer characteristics of nanocrystalline diamond solution-gated field-effect transistors (SGFET) prepared on glass substrates. Channels of these fully transparent SGFETs are realized by hydrogen termination of undoped diamond film. After cell cultivation, the transistors exhibit about 100× increased leakage currents (up to 10nA). During and after the cell delamination, the transistors return to original gate currents. We propose a mechanism where this triggering effect is attributed to ions released from adhered cells, which depends on the cell adhesion morphology, and could be used for cell culture monitoring. Copyright © 2015 Elsevier B.V. All rights reserved.

All-ion-implanted planar-gate current aperture vertical Ga2O3 MOSFETs with Mg-doped blocking layer

NASA Astrophysics Data System (ADS)

Wong, Man Hoi; Goto, Ken; Morikawa, Yoji; Kuramata, Akito; Yamakoshi, Shigenobu; Murakami, Hisashi; Kumagai, Yoshinao; Higashiwaki, Masataka

2018-06-01

A vertical β-Ga2O3 metal–oxide–semiconductor field-effect transistor featuring a planar-gate architecture is presented. The device was fabricated by an all-ion-implanted process without requiring trench etching or epitaxial regrowth. A Mg-ion-implanted current blocking layer (CBL) provided electrical isolation between the source and the drain except at an aperture opening through which drain current was conducted. Successful transistor action was realized by gating a Si-ion-implanted channel above the CBL. Thermal diffusion of Mg induced a large source–drain leakage current through the CBL, which resulted in compromised off-state device characteristics as well as a reduced peak extrinsic transconductance compared with the results of simulations.

Measurements of leakage from Lake Michigan through three control structures near Chicago, Illinois, April-October 1993

USGS Publications Warehouse

Oberg, K.A.; Schmidt, A.R.

1994-01-01

A total of 213 measurements of leakage were made at three control structures near Chicago, Ill.--the Chicago River Controlling Works (CRCW), Thomas J. O'Brien Lock and Dam (O'Brien), and Wilmette Pumping Station (Wilmette)--using acoustic Doppler current profilers (ADCP's) and dye-dilution techniques. The CRCW consists of the Chicago Lock and two sets of sluice gates connected by a network of harbor walls. Leakage measurements were made in April, May, July, September, and October 1993 using an ADCP. The mean and standard deviation of leakage measured by the ADCP for the Chicago Lock river gate were 133 and 39 cubic feet per second, respectively. The mean and standard deviation of the leakage measurements at CRCW were 204 and 70 cubic feet per second, respectively. The mean and standard deviation of leakage measurements at O'Brien on September 17, 1993, were 21 and 10 cubic feet per second, respectively. The mean and standard deviation leakage measured at Wilmette using the ADCP were 59 and 8 cubic feet per second, respectively, in April 1993. After the pump bays at Wilmette were sealed in July 1993, the leakage dropped to less than 15 cubic feet per second in September 1993. Discharge estimated by dye-dilution at the Chicago Lock on July 15, 1993, was 160 cubic feet per second, or within 8 percent of the discharge measured with the ADCP. (USGS)

Recovery Characteristics of Anomalous Stress-Induced Leakage Current of 5.6 nm Oxide Films

NASA Astrophysics Data System (ADS)

Inatsuka, Takuya; Kumagai, Yuki; Kuroda, Rihito; Teramoto, Akinobu; Sugawa, Shigetoshi; Ohmi, Tadahiro

2012-04-01

Anomalous stress-induced leakage current (SILC), which has a much larger current density than average SILC, causes severe bit error in flash memories. To suppress anomalous SILC, detailed evaluations are strongly required. We evaluate the characteristics of anomalous SILC of 5.6 nm oxide films using a fabricated array test pattern, and recovery characteristics are observed. Some characteristics of typical anomalous cells in the time domain are measured, and the recovery characteristics of average and anomalous SILCs are examined. Some of the anomalous cells have random telegraph signals (RTSs) of gate leakage current, which are characterized as discrete and random switching phenomena. The dependence of RTSs on the applied electric field is investigated, and the recovery tendency of anomalous SILC with and without RTSs are also discussed.

Enabling Energy Efficiency and Polarity Control in Germanium Nanowire Transistors by Individually Gated Nanojunctions.

PubMed

Trommer, Jens; Heinzig, André; Mühle, Uwe; Löffler, Markus; Winzer, Annett; Jordan, Paul M; Beister, Jürgen; Baldauf, Tim; Geidel, Marion; Adolphi, Barbara; Zschech, Ehrenfried; Mikolajick, Thomas; Weber, Walter M

2017-02-28

Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finite-element drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems.

Designing hybrid gate dielectric for fully printing high-performance carbon nanotube thin film transistors

NASA Astrophysics Data System (ADS)

Li, Qian; Li, Shilong; Yang, Dehua; Su, Wei; Wang, Yanchun; Zhou, Weiya; Liu, Huaping; Xie, Sishen

2017-10-01

The electrical characteristics of carbon nanotube (CNT) thin-film transistors (TFTs) strongly depend on the properties of the gate dielectric that is in direct contact with the semiconducting CNT channel materials. Here, we systematically investigated the dielectric effects on the electrical characteristics of fully printed semiconducting CNT-TFTs by introducing the organic dielectrics of poly(methyl methacrylate) (PMMA) and octadecyltrichlorosilane (OTS) to modify SiO2 dielectric. The results showed that the organic-modified SiO2 dielectric formed a favorable interface for the efficient charge transport in s-SWCNT-TFTs. Compared to single-layer SiO2 dielectric, the use of organic-inorganic hybrid bilayer dielectrics dramatically improved the performances of SWCNT-TFTs such as mobility, threshold voltage, hysteresis and on/off ratio due to the suppress of charge scattering, gate leakage current and charge trapping. The transport mechanism is related that the dielectric with few charge trapping provided efficient percolation pathways for charge carriers, while reduced the charge scattering. High density of charge traps which could directly act as physical transport barriers and significantly restrict the charge carrier transport and, thus, result in decreased mobile carriers and low device performance. Moreover, the gate leakage phenomenon is caused by conduction through charge traps. So, as a component of TFTs, the gate dielectric is of crucial importance to the manufacture of high quality TFTs from the aspects of affecting the gate leakage current and device operation voltage, as well as the charge carrier transport. Interestingly, the OTS-modified SiO2 allows to directly print horizontally aligned CNT film, and the corresponding devices exhibited a higher mobility than that of the devices with the hybrid PMMA/SiO2 dielectric although the thickness of OTS layer is only ˜2.5 nm. Our present result may provide key guidance for the further development of printed nanomaterial electronics.

Al 0.85Ga 0.15N/Al 0.70Ga 0.30N High Electron Mobility Transistors with Schottky Gates and Large On/Off Current Ratio over Temperature

DOE PAGES

Baca, Albert G.; Klein, Brianna A.; Allerman, Andrew A.; ...

2017-12-09

AlGaN-channel high electron mobility transistors (HEMTs) are among a class of ultra wide-bandgap transistors that are promising candidates for RF and power applications. Long-channel Al xGa 1-xN HEMTs with x = 0.7 in the channel have been built and evaluated across the -50°C to +200°C temperature range. These devices achieved room temperature drain current as high as 46 mA/mm and were absent of gate leakage until the gate diode forward bias turn-on at ~2.8 V, with a modest -2.2 V threshold voltage. A very large I on/I off current ratio, of 8 × 10 9 was demonstrated. A near idealmore » subthreshold slope that is just 35% higher than the theoretical limit across the temperature range was characterized. The ohmic contact characteristics were rectifying from -50°C to +50°C and became nearly linear at temperatures above 100°C. An activation energy of 0.55 eV dictates the temperature dependence of off-state leakage.« less

Al 0.85Ga 0.15N/Al 0.70Ga 0.30N High Electron Mobility Transistors with Schottky Gates and Large On/Off Current Ratio over Temperature

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baca, Albert G.; Klein, Brianna A.; Allerman, Andrew A.

AlGaN-channel high electron mobility transistors (HEMTs) are among a class of ultra wide-bandgap transistors that are promising candidates for RF and power applications. Long-channel Al xGa 1-xN HEMTs with x = 0.7 in the channel have been built and evaluated across the -50°C to +200°C temperature range. These devices achieved room temperature drain current as high as 46 mA/mm and were absent of gate leakage until the gate diode forward bias turn-on at ~2.8 V, with a modest -2.2 V threshold voltage. A very large I on/I off current ratio, of 8 × 10 9 was demonstrated. A near idealmore » subthreshold slope that is just 35% higher than the theoretical limit across the temperature range was characterized. The ohmic contact characteristics were rectifying from -50°C to +50°C and became nearly linear at temperatures above 100°C. An activation energy of 0.55 eV dictates the temperature dependence of off-state leakage.« less

Poole Frenkel current and Schottky emission in SiN gate dielectric in AlGaN/GaN metal insulator semiconductor heterostructure field effect transistors

NASA Astrophysics Data System (ADS)

Hanna, Mina J.; Zhao, Han; Lee, Jack C.

2012-10-01

We analyze the anomalous I-V behavior in SiN prepared by plasma enhanced chemical vapor deposition for use as a gate insulator in AlGaN/GaN metal insulator semiconductor heterostructure filed effect transistors (HFETs). We observe leakage current across the dielectric with opposite polarity with respect to the applied electric field once the voltage sweep reaches a level below a determined threshold. This is observed as the absolute minimum of the leakage current does not occur at minimum voltage level (0 V) but occurs earlier in the sweep interval. Curve-fitting analysis suggests that the charge-transport mechanism in this region is Poole-Frenkel current, followed by Schottky emission due to band bending. Despite the current anomaly, the sample devices have shown a notable reduction of leakage current of over 2 to 6 order of magnitudes compared to the standard Schottky HFET. We show that higher pressures and higher silane concentrations produce better films manifesting less trapping. This conforms to our results that we reported in earlier publications. We found that higher chamber pressure achieves higher sheet carrier concentration that was found to be strongly dependent on the trapped space charge at the SiN/GaN interface. This would suggest that a lower chamber pressure induces more trap states into the SiN/GaN interface.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Gate length variation effect on performance of gate-first self-aligned In₀.₅₃Ga₀.₄₇As MOSFET.

PubMed

Mohd Razip Wee, Mohd F; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y

2013-01-01

A multi-gate n-type In₀.₅₃Ga₀.₄₇As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm(2)/Vs are achieved for the gate length and width of 0.2 µm and 30 µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10(-8) A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared.

Gate Length Variation Effect on Performance of Gate-First Self-Aligned In0.53Ga0.47As MOSFET

PubMed Central

Mohd Razip Wee, Mohd F.; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y.

2013-01-01

A multi-gate n-type In0.53Ga0.47As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm2/Vs are achieved for the gate length and width of 0.2 µm and 30µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10−8 A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared. PMID:24367548

Bottom-gate poly-Si thin-film transistors by nickel silicide seed-induced lateral crystallization with self-aligned lightly doped layer

NASA Astrophysics Data System (ADS)

Lee, Sol Kyu; Seok, Ki Hwan; Chae, Hee Jae; Lee, Yong Hee; Han, Ji Su; Jo, Hyeon Ah; Joo, Seung Ki

2017-03-01

We report a novel method to reduce source and drain (S/D) resistances, and to form a lightly doped layer (LDL) of bottom-gate polycrystalline silicon (poly-Si) thin-film transistors (TFTs). For application in driving TFTs, which operate under high drain voltage condition, poly-Si TFTs are needed in order to attain reliability against hot-carriers as well as high field-effect mobility (μFE). With an additional doping on the p+ Si layer, sheet resistance on S/D was reduced by 37.5% and an LDL was introduced between the channel and drain. These results contributed to not only a lower leakage current and gate-induced drain leakage, but also high immunity of kink-effect and hot-carrier stress. Furthermore, the measured electrical characteristics exhibited a steep subthreshold slope of 190 mV/dec and high μFE of 263 cm2/Vs.

Effect of atomic layer deposition temperature on current conduction in Al2O3 films formed using H2O oxidant

NASA Astrophysics Data System (ADS)

Hiraiwa, Atsushi; Matsumura, Daisuke; Kawarada, Hiroshi

2016-08-01

To develop high-performance, high-reliability gate insulation and surface passivation technologies for wide-bandgap semiconductor devices, the effect of atomic layer deposition (ALD) temperature on current conduction in Al2O3 films is investigated based on the recently proposed space-charge-controlled field emission model. Leakage current measurement shows that Al2O3 metal-insulator-semiconductor capacitors formed on the Si substrates underperform thermally grown SiO2 capacitors at the same average field. However, using equivalent oxide field as a more practical measure, the Al2O3 capacitors are found to outperform the SiO2 capacitors in the cases where the capacitors are negatively biased and the gate material is adequately selected to reduce virtual dipoles at the gate/Al2O3 interface. The Al2O3 electron affinity increases with the increasing ALD temperature, but the gate-side virtual dipoles are not affected. Therefore, the leakage current of negatively biased Al2O3 capacitors is approximately independent of the ALD temperature because of the compensation of the opposite effects of increased electron affinity and permittivity in Al2O3. By contrast, the substrate-side sheet of charge increases with increasing ALD temperature above 210 °C and hence enhances the current of positively biased Al2O3 capacitors more significantly at high temperatures. Additionally, an anomalous oscillatory shift of the current-voltage characteristics with ALD temperature was observed in positively biased capacitors formed by low-temperature (≤210 °C) ALD. This shift is caused by dipoles at the Al2O3/underlying SiO2 interface. Although they have a minimal positive-bias leakage current, the low-temperature-grown Al2O3 films cause the so-called blisters problem when heated above 400 °C. Therefore, because of the absence of blistering, a 450 °C ALD process is presently the most promising technology for growing high-reliability Al2O3 films.

Quantification and characterization of leakage errors

NASA Astrophysics Data System (ADS)

Wood, Christopher J.; Gambetta, Jay M.

2018-03-01

We present a general framework for the quantification and characterization of leakage errors that result when a quantum system is encoded in the subspace of a larger system. To do this we introduce metrics for quantifying the coherent and incoherent properties of the resulting errors and we illustrate this framework with several examples relevant to superconducting qubits. In particular, we propose two quantities, the leakage and seepage rates, which together with average gate fidelity allow for characterizing the average performance of quantum gates in the presence of leakage and show how the randomized benchmarking protocol can be modified to enable the robust estimation of all three quantities for a Clifford gate set.

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

NASA Astrophysics Data System (ADS)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

Direct current performance and current collapse in AlGaN/GaN insulated gate high-electron mobility transistors on Si (1 1 1) substrate with very thin SiO2 gate dielectric

NASA Astrophysics Data System (ADS)

Lachab, M.; Sultana, M.; Fatima, H.; Adivarahan, V.; Fareed, Q.; Khan, M. A.

2012-12-01

This work reports on the dc performance of AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) grown on Si (1 1 1) substrate and the study of current dispersion in these devices using various widely adopted methods. The MOSHEMTs were fabricated using a very thin (4.2 nm) SiO2 film as the gate insulator and were subsequently passivated with about 30 nm thick Si3N4 layer. For devices with 2.5 µm long gates and a 4 µm drain-to-source spacing, the maximum saturation drain current density was 822 mA mm-1 at + 4 V gate bias and the peak external transconductance was ˜100 mS mm-1. Furthermore, the oxide layer successfully suppressed the drain and gate leakage currents with the subthreshold current and the gate diode current levels exceeding by more than three orders of magnitude the levels found in their Schottky gate counterparts. Capacitance-voltage and dynamic current-voltage measurements were carried out to assess the oxide quality as well as the devices’ surface properties after passivation. The efficacy of each of these characterization techniques to probe the presence of interface traps and oxide charge in the nitride-based transistors is also discussed.

Characterization of Plasma-Induced Damage of Selectively Recessed GaN/InAlN/AlN/GaN Heterostructures Using SiCl4 and SF6

NASA Astrophysics Data System (ADS)

Ostermaier, Clemens; Pozzovivo, Gianmauro; Basnar, Bernhard; Schrenk, Werner; Carlin, Jean-François; Gonschorek, Marcus; Grandjean, Nicolas; Vincze, Andrej; Tóth, Lajos; Pécz, Bela; Strasser, Gottfried; Pogany, Dionyz; Kuzmik, Jan

2010-11-01

We have investigated an inductively coupled plasma etching recipe using SiCl4 and SF6 with a resulting selectivity >10 for GaN in respect to InAlN. The formation of an etch-resistant layer of AlF3 on InAlN required about 1 min and was noticed by a 4-times-higher initial etch rate on bare InAlN barrier high electron mobility transistors (HEMTs). Comparing devices with and without plasma-treatment below the gate showed no degradation in drain current and gate leakage current for plasma exposure durations shorter than 30 s, indicating no plasma-induced damage of the InAlN barrier. Devices etched longer than the required time for the formation of the etch-resistant barrier exhibited a slight decrease in drain current and an increase in gate leakage current which saturated for longer etching-time durations. Finally, we could prove the quality of the recipe by recessing the highly doped 6 nm GaN cap layer of a GaN/InAlN/AlN/GaN heterostructure down to the 2 nm thin InAlN/AlN barrier layer.

Low Temperature Noise and Electrical Characterization of the Company Heterojunction Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.; Gee, Russell C.; Fossum, Eric R.; Baier, Steven M.

1993-01-01

This paper discusses the electrical properties of the complementary heterojunction field-effect transistor (CHFET) at 4K, including the gate leakage current, the subthreshold transconductance, and the input-referred noise voltage.

Electrical and ferroelectric properties of RF sputtered PZT/SBN on silicon for non-volatile memory applications

NASA Astrophysics Data System (ADS)

Singh, Prashant; Jha, Rajesh Kumar; Singh, Rajat Kumar; Singh, B. R.

2018-02-01

We report the integration of multilayer ferroelectric film deposited by RF magnetron sputtering and explore the electrical characteristics for its application as the gate of ferroelectric field effect transistor for non-volatile memories. PZT (Pb[Zr0.35Ti0.65]O3) and SBN (SrBi2Nb2O9) ferroelectric materials were selected for the stack fabrication due to their large polarization and fatigue free properties respectively. Electrical characterization has been carried out to obtain memory window, leakage current density, PUND and endurance characteristics. Fabricated multilayer ferroelectric film capacitor structure shows large memory window of 17.73 V and leakage current density of the order 10-6 A cm-2 for the voltage sweep of -30 to +30 V. This multilayer gate stack of PZT/SBN shows promising endurance property with no degradation in the remnant polarization for the read/write iteration cycles upto 108.

Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI

NASA Technical Reports Server (NTRS)

Duong, Tuan A.

2012-01-01

For miniaturization of electronics systems, power consumption plays a key role in the realm of constraints. Considering the very large scale integration (VLSI) design aspect, as transistor feature size is decreased to 50 nm and below, there is sizable increase in the number of transistors as more functional building blocks are embedded in the same chip. However, the consequent increase in power consumption (dynamic and leakage) will serve as a key constraint to inhibit the advantages of transistor feature size reduction. Power consumption can be reduced by minimizing the voltage supply (for dynamic power consumption) and/or increasing threshold voltage (V(sub th), for reducing leakage power). When the feature size of the transistor is reduced, supply voltage (V(sub dd)) and threshold voltage (V(sub th)) are also reduced accordingly; then, the leakage current becomes a bigger factor of the total power consumption. To maintain low power consumption, operation of electronics at sub-threshold levels can be a potentially strong contender; however, there are two obstacles to be faced: more leakage current per transistor will cause more leakage power consumption, and slow response time when the transistor is operated in weak inversion region. To enable low power consumption and yet obtain high performance, the CMOS (complementary metal oxide semiconductor) transistor as a basic element is viewed and controlled as a four-terminal device: source, drain, gate, and body, as differentiated from the traditional approach with three terminals: i.e., source and body, drain, and gate. This technique features multiple voltage sources to supply the dynamic control, and uses dynamic control to enable low-threshold voltage when the channel (N or P) is active, for speed response enhancement and high threshold voltage, and when the transistor channel (N or P) is inactive, to reduce the leakage current for low-leakage power consumption.

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

NASA Astrophysics Data System (ADS)

Nedic, Stanko; Tea Chun, Young; Hong, Woong-Ki; Chu, Daping; Welland, Mark

2014-01-01

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ˜16.5 V, a high drain current on/off ratio of ˜105, a gate leakage current below ˜300 pA, and excellent retention characteristics for over 104 s.

GIDL analysis of the process variation effect in gate-all-around nanowire FET

NASA Astrophysics Data System (ADS)

Kim, Shinkeun; Seo, Youngsoo; Lee, Jangkyu; Kang, Myounggon; Shin, Hyungcheol

2018-02-01

In this paper, the gate-induced drain leakage (GIDL) is analyzed on gate-all-around (GAA) Nanowire FET (NW FET) with ellipse-shaped channel induced by process variation effect (PVE). The fabrication process of nanowire can lead to change the shape of channel cross section from circle to ellipse. The effect of distorted channel shape is investigated and verified by technology computer-aided design (TCAD) simulation in terms of the GIDL current. The simulation results demonstrate that the components of GIDL current are two mechanisms of longitudinal band-to-band tunneling (L-BTBT) at body/drain junction and transverse band-to-band tunneling (T-BTBT) at gate/drain junction. These two mechanisms are investigated on channel radius (rnw) and aspect ratio of ellipse-shape respectively and together.

Novel technique of source and drain engineering for dual-material double-gate (DMDG) SOI MOSFETS

NASA Astrophysics Data System (ADS)

Yadav, Himanshu; Malviya, Abhishek Kumar; Chauhan, R. K.

2018-04-01

The dual-metal dual-gate (DMDG) SOI has been used with Dual Sided Source and Drain Engineered 50nm SOI MOSFET with various high-k gate oxide. It has been scrutinized in this work to enhance its electrical performance. The proposed structure is designed by creating Dual Sided Source and Drain Modification and its characteristics are evaluated on ATLAS device simulator. The consequence of this dual sided assorted doping on source and drain side of the DMDG transistor has better leakage current immunity and heightened ION current with higher ION to IOFF Ratio. Which thereby vesting the proposed device appropriate for low power digital applications.

Application of high-quality SiO2 grown by multipolar ECR source to Si/SiGe MISFET

NASA Technical Reports Server (NTRS)

Sung, K. T.; Li, W. Q.; Li, S. H.; Pang, S. W.; Bhattacharya, P. K.

1993-01-01

A 5 nm-thick SiO2 gate was grown on an Si(p+)/Si(0.8)Ge(0.2) modulation-doped heterostructure at 26 C with an oxygen plasma generated by a multipolar electron cyclotron resonance source. The ultrathin oxide has breakdown field above 12 MV/cm and fixed charge density about 3 x 10 exp 10/sq cm. Leakage current as low as 1/micro-A was obtained with the gate biased at 4 V. The MISFET with 0.25 x 25 sq m gate shows maximum drain current of 41.6 mA/mm and peak transconductance of 21 mS/mm.

Mechanistic analysis of temperature-dependent current conduction through thin tunnel oxide in n+-polySi/SiO2/n+-Si structures

NASA Astrophysics Data System (ADS)

Samanta, Piyas

2017-09-01

We present a detailed investigation on temperature-dependent current conduction through thin tunnel oxides grown on degenerately doped n-type silicon (n+-Si) under positive bias ( VG ) on heavily doped n-type polycrystalline silicon (n+-polySi) gate in metal-oxide-semiconductor devices. The leakage current measured between 298 and 573 K and at oxide fields ranging from 6 to 10 MV/cm is primarily attributed to Poole-Frenkel (PF) emission of trapped electrons from the neutral electron traps located in the silicon dioxide (SiO2) band gap in addition to Fowler-Nordheim (FN) tunneling of electrons from n+-Si acting as the drain node in FLOating gate Tunnel OXide Electrically Erasable Programmable Read-Only Memory devices. Process-induced neutral electron traps are located at 0.18 eV and 0.9 eV below the SiO2 conduction band. Throughout the temperature range studied here, PF emission current IPF dominates FN electron tunneling current IFN at oxide electric fields Eox between 6 and 10 MV/cm. A physics based new analytical formula has been developed for FN tunneling of electrons from the accumulation layer of degenerate semiconductors at a wide range of temperatures incorporating the image force barrier rounding effect. FN tunneling has been formulated in the framework of Wentzel-Kramers-Brilloiun taking into account the correction factor due to abrupt variation of the energy barrier at the cathode/oxide interface. The effect of interfacial and near-interfacial trapped-oxide charges on FN tunneling has also been investigated in detail at positive VG . The mechanism of leakage current conduction through SiO2 films plays a crucial role in simulation of time-dependent dielectric breakdown of the memory devices and to precisely predict the normal operating field or applied floating gate (FG) voltage for lifetime projection of the devices. In addition, we present theoretical results showing the effect of drain doping concentration on the FG leakage current.

Discharge ratings for tainter gates and roller gates at Lock and Dam No. 7 on the Mississippi River, La Crescent, Minnesota

USGS Publications Warehouse

Corsi, Steven R.; Schuler, J.G.

1995-01-01

Coefficients of discharge (Cgs) ranged fron 0.126 (hg = 1 foot) to 1.089 (hg = 10 feet) for tainter gates and from 0.050 (hg = 1 foot) to 0.302 (hg = 14 feet) for roller gates. Disch^ge was measured at three different tainter gates with the gates closed (hg = 0) to evaluate tH tainter-gate leakage-discharge relations. No measurable leakage was observed. The resulting equations can be used to compute discharge at Lock and Dam No. 7 for the tainter and re Her gates under normal flow conditions. Discharge rating tables for the tainter and roller gates are given with a headwater elevation of 639.00 feet normal pool elevation for selected tailwate" elevations and gate openings.

Improved performance of nanoscale junctionless tunnel field-effect transistor based on gate engineering approach

NASA Astrophysics Data System (ADS)

Molaei Imen Abadi, Rouzbeh; Sedigh Ziabari, Seyed Ali

2016-11-01

In this paper, a first qualitative study on the performance characteristics of dual-work function gate junctionless TFET (DWG-JLTFET) on the basis of energy band profile modulation is investigated. A dual-work function gate technique is used in a JLTFET in order to create a downward band bending on the source side similar to PNPN structure. Compared with the single-work function gate junctionless TFET (SWG-JLTFET), the numerical simulation results demonstrated that the DWG-JLTFET simultaneously optimizes the ON-state current, the OFF-state leakage current, and the threshold voltage and also improves average subthreshold slope. It is illustrated that if appropriate work functions are selected for the gate materials on the source side and the drain side, the JLTFET exhibits a considerably improved performance. Furthermore, the optimization design of the tunnel gate length ( L Tun) for the proposed DWG-JLTFET is studied. All the simulations are done in Silvaco TCAD for a channel length of 20 nm using the nonlocal band-to-band tunneling (BTBT) model.

MOCVD of HfO2 and ZrO2 high-k gate dielectrics for InAlN/AlN/GaN MOS-HEMTs

NASA Astrophysics Data System (ADS)

Abermann, S.; Pozzovivo, G.; Kuzmik, J.; Strasser, G.; Pogany, D.; Carlin, J.-F.; Grandjean, N.; Bertagnolli, E.

2007-12-01

We apply metal organic chemical vapour deposition (MOCVD) of HfO2 and of ZrO2 from β-diketonate precursors to grow high-k gate dielectrics for InAlN/AlN/GaN metal oxide semiconductor (MOS)-high electron mobility transistors (HEMTs). High-k oxides of about 12 nm-14 nm are deposited for the MOS-HEMTs incorporating Ni/Au gates, whereas as a reference, Ni-contact-based 'conventional' Schottky-barrier (SB)-HEMTs are processed. The processed dielectrics decrease the gate current leakage of the HEMTs by about four orders of magnitude if compared with the SB-gated HEMTs and show superior device characteristics in terms of IDS and breakdown.

A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects

NASA Astrophysics Data System (ADS)

Ramezani, Zeinab; Orouji, Ali A.

2018-03-01

In this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors with atomic layer deposited Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Lin, H. C.; Yang, T.; Sharifi, H.; Kim, S. K.; Xuan, Y.; Shen, T.; Mohammadi, S.; Ye, P. D.

2007-11-01

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with ex situ atomic-layer-deposited Al2O3 as gate dielectrics are studied. Maximum drain currents of 211 and 263mA/mm are obtained for 1μm gate-length Al2O3 MOS-HEMTs with 3 and 6nm thick gate oxide, respectively. C-V characteristic shows negligible hysteresis and frequency dispersion. The gate leakage current density of the MOS-HEMTs is 3-5 orders of magnitude lower than the conventional HEMTs under similar bias conditions. The drain current on-off ratio of MOS-HEMTs is ˜3×103 with a subthreshold swing of 90mV/decade. A maximum cutoff frequency (fT) of 27.3GHz and maximum oscillation frequency (fmax) of 39.9GHz and an effective channel mobility of 4250cm2/Vs are measured for the 1μm gate-length Al2O3 MOS-HEMT with 6nm gate oxide. Hooge's constant measured by low frequency noise spectral density characterization is 3.7×10-5 for the same device.

2-D Modeling of Nanoscale MOSFETs: Non-Equilibrium Green's Function Approach

NASA Technical Reports Server (NTRS)

Svizhenko, Alexei; Anantram, M. P.; Govindan, T. R.; Biegel, Bryan

2001-01-01

We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions and oxide tunneling are treated on an equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. Electron-electron interaction is treated within Hartree approximation by solving NEGF and Poisson equations self-consistently. For the calculations presented here, parallelization is performed by distributing the solution of NEGF equations to various processors, energy wise. We present simulation of the "benchmark" MIT 25nm and 90nm MOSFETs and compare our results to those from the drift-diffusion simulator and the quantum-corrected results available. In the 25nm MOSFET, the channel length is less than ten times the electron wavelength, and the electron scattering time is comparable to its transit time. Our main results are: (1) Simulated drain subthreshold current characteristics are shown, where the potential profiles are calculated self-consistently by the corresponding simulation methods. The current predicted by our quantum simulation has smaller subthreshold slope of the Vg dependence which results in higher threshold voltage. (2) When gate oxide thickness is less than 2 nm, gate oxide leakage is a primary factor which determines off-current of a MOSFET (3) Using our 2-D NEGF simulator, we found several ways to drastically decrease oxide leakage current without compromising drive current. (4) Quantum mechanically calculated electron density is much smaller than the background doping density in the poly silicon gate region near oxide interface. This creates an additional effective gate voltage. Different ways to. include this effect approximately will be discussed.

Simulation study of short-channel effects of tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Fukuda, Koichi; Asai, Hidehiro; Hattori, Junichi; Mori, Takahiro; Morita, Yukinori; Mizubayashi, Wataru; Masahara, Meishoku; Migita, Shinji; Ota, Hiroyuki; Endo, Kazuhiro; Matsukawa, Takashi

2018-04-01

Short-channel effects of tunnel field-effect transistors (FETs) are investigated in detail using simulations of a nonlocal band-to-band tunneling model. Discussion is limited to silicon. Several simulation scenarios were considered to address different effects, such as source overlap and drain offset effects. Adopting the drain offset to suppress the drain leakage current suppressed the short channel effects. The physical mechanism underlying the short-channel behavior of the tunnel FETs (TFETs) was very different from that of metal-oxide-semiconductor FETs (MOSFETs). The minimal gate lengths that do not lose on-state current by one order are shown to be 3 nm for single-gate structures and 2 nm for double gate structures, as determined from the drain offset structure.

Effect of atomic layer deposition temperature on current conduction in Al{sub 2}O{sub 3} films formed using H{sub 2}O oxidant

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hiraiwa, Atsushi, E-mail: hiraiwa@aoni.waseda.jp, E-mail: qs4a-hriw@asahi-net.or.jp; Matsumura, Daisuke; Kawarada, Hiroshi, E-mail: kawarada@waseda.jp

To develop high-performance, high-reliability gate insulation and surface passivation technologies for wide-bandgap semiconductor devices, the effect of atomic layer deposition (ALD) temperature on current conduction in Al{sub 2}O{sub 3} films is investigated based on the recently proposed space-charge-controlled field emission model. Leakage current measurement shows that Al{sub 2}O{sub 3} metal-insulator-semiconductor capacitors formed on the Si substrates underperform thermally grown SiO{sub 2} capacitors at the same average field. However, using equivalent oxide field as a more practical measure, the Al{sub 2}O{sub 3} capacitors are found to outperform the SiO{sub 2} capacitors in the cases where the capacitors are negatively biased andmore » the gate material is adequately selected to reduce virtual dipoles at the gate/Al{sub 2}O{sub 3} interface. The Al{sub 2}O{sub 3} electron affinity increases with the increasing ALD temperature, but the gate-side virtual dipoles are not affected. Therefore, the leakage current of negatively biased Al{sub 2}O{sub 3} capacitors is approximately independent of the ALD temperature because of the compensation of the opposite effects of increased electron affinity and permittivity in Al{sub 2}O{sub 3}. By contrast, the substrate-side sheet of charge increases with increasing ALD temperature above 210 °C and hence enhances the current of positively biased Al{sub 2}O{sub 3} capacitors more significantly at high temperatures. Additionally, an anomalous oscillatory shift of the current-voltage characteristics with ALD temperature was observed in positively biased capacitors formed by low-temperature (≤210 °C) ALD. This shift is caused by dipoles at the Al{sub 2}O{sub 3}/underlying SiO{sub 2} interface. Although they have a minimal positive-bias leakage current, the low-temperature-grown Al{sub 2}O{sub 3} films cause the so-called blisters problem when heated above 400 °C. Therefore, because of the absence of blistering, a 450 °C ALD process is presently the most promising technology for growing high-reliability Al{sub 2}O{sub 3} films.« less

Pentacene-based low voltage organic field-effect transistors with anodized Ta2O5 gate dielectric

NASA Astrophysics Data System (ADS)

Jeong, Yeon Taek; Dodabalapur, Ananth

2007-11-01

Pentacene-based low voltage organic field-effect transistors were realized using an anodized Ta2O5 gate dielectric. The Ta2O5 gate dielectric layer with a surface roughness of 1.3Å was obtained by anodizing an e-beam evaporated Ta film. The device exhibited values of saturation mobility, threshold voltage, and Ion/Ioff ratio of 0.45cm2/Vs, 0.56V, and 7.5×101, respectively. The gate leakage current was reduced by more than 70% with a hexamethyldisilazane (HMDS) treatment on the Ta2O5 layer. The HMDS treatment also resulted in enhanced mobility values and a larger pentacene grain size.

Floating-gate memory based on an organic metal-insulator-semiconductor capacitor

NASA Astrophysics Data System (ADS)

William, S.; Mabrook, M. F.; Taylor, D. M.

2009-08-01

A floating gate memory element is described which incorporates an evaporated gold film embedded in the gate dielectric of a metal-insulator-semiconductor capacitor based on poly(3-hexylthiophene). On exceeding a critical amplitude in the voltage sweep, hysteresis is observed in the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of the device. The anticlockwise hysteresis in C-V is consistent with strong electron trapping during the positive cycle but little hole trapping during the negative cycle. We argue that the clockwise hysteresis observed in the negative cycle of the I-V plot, arises from leakage of trapped holes through the underlying insulator to the control gate.

Measurements and sensitivities of LWR in poly spacers

NASA Astrophysics Data System (ADS)

Ayal, Guy; Shauly, Eitan; Levi, Shimon; Siany, Amit; Adan, Ofer; Shacham-Diamand, Yosi

2010-03-01

LER and LWR have long been considered a primary issue in process development and monitoring. Development of a low power process flavors emphasizes the effect of LER, LWR on different aspects of the device. Gate level performance, particularly leakage current at the front end of line, resistance and reliability in the back-end layers. Traditionally as can be seen in many publications, for the front end of line the focus is mainly on Poly and Active area layers. Poly spacers contribution to the gate leakage, for example, is rarely discussed. Following our research done on sources of gate leakage, we found leakage current (Ioff) in some processes to be highly sensitive to changes in the width of the Poly spacers - even more strongly to the actual Poly gate CDs. Therefore we decided to measure Poly spacers LWR, its correlation to the LWR in the poly, and its sensitivity to changes in layout and OPC. In our last year publication, we defined the terms LLER (Local Line Edge Roughness) and LLWR (Local Line Width Roughness). The local roughness is measured as the 3-sigma value of the line edge/width in a 5-nm segment around the measurement point. We will use these terms in this paper to evaluate the Poly roughness impact on Poly spacer's roughness. A dedicated test chip was designed for the experiments, having various transistors layout configurations with different densities to cover the all range of process design rules. Applied Materials LER and LWR innovative algorithms were used to measure and characterize the spacer roughness relative to the distance from the active edges and from other spaces. To accurately measure all structures in a reasonable time, the recipes were automatically generated from CAD. On silicon, after poly spacers generation, the transistors no longer resemble the Poly layer CAD layout, their morphology is different compared with Photo/Etch traditional structures , and dimensions vary significantly. In this paper we present metrology and characterization of poly spacer LLWR and LLER compared to that of the poly gate in various transistor shapes, showing that the relation between them depends on the transistor architecture (final layout, including OPC). We will show how the spacer deposition may reduce, keep or even enlarge the roughness measured on Poly, depending on transistor layout , but surprisingly, not dependent on proximity effects.

A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

NASA Astrophysics Data System (ADS)

Sharma, Vijay Kumar; Pattanaik, Manisha

2015-11-01

Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.

The ``Leakage Current Sentinel'': A novel plug-in socket device for online biomedical equipment electrical safety surveillance

NASA Astrophysics Data System (ADS)

Cappa, Paolo; Marinozzi, Franco; Sciuto, Salvatore Andrea

2000-07-01

The Leakage Current Sentinel (LCS) has been designed and implemented for the detection of hazardous situations caused by dangerous earth leakage current values in intensive care units and operating theaters. The device, designed and manufactured with full compliance of the high risk environment requirements, is able to monitor online the earth leakage current and detect ground wire faults. Operation utilizes a microammeter with an overall sensitivity of 2.5×104 V/A. In order to assure the reliability of the device in providing alarm signals, the simultaneous presence of absorbed power current is monitored by means of another ammeter with decreased sensitivity (3.0 V/A). The measured root mean square current values are compared with reference values in order to send signals to NAND and OR complementary metal-oxide-semiconductor gates to enable audible and visible alarms according to the possible hazardous cases examined in the article. The final LCS packaging was shaped as a wall socket adapter for common electromedical device power cord plugs, with particular attention to minimizing its dimensions and to provide analog voltage outputs for both measured leakage and power currents, in order to allow automatic data acquisition and computerized hazardous situation management. Finally, a personal computer based automatic measuring system has been configured to simultaneously monitor several LCSs installed in the same intensive care unit room and, as a consequence, to distinguish different hazardous scenarios and provide an adequate alert to the clinical personnel whose final decision is still required. The test results confirm the effectiveness and reliability of the LCS in giving an alert in case of leakage current anomalous values, either in case of a ground fault or in case of a dangerous leakage current.

Achievement of normally-off AlGaN/GaN high-electron mobility transistor with p-NiOx capping layer by sputtering and post-annealing

NASA Astrophysics Data System (ADS)

Huang, Shyh-Jer; Chou, Cheng-Wei; Su, Yan-Kuin; Lin, Jyun-Hao; Yu, Hsin-Chieh; Chen, De-Long; Ruan, Jian-Long

2017-04-01

In this paper, we present a technique to fabricate normally off GaN-based high-electron mobility transistor (HEMT) by sputtering and post-annealing p-NiOx capping layer. The p-NiOx layer is produced by sputtering at room temperature and post-annealing at 500 °C for 30 min in pure O2 environment to achieve high hole concentration. The Vth shifts from -3 V in the conventional transistor to 0.33 V, and on/off current ratio became 107. The forward and reverse gate breakdown increase from 3.5 V and -78 V to 10 V and -198 V, respectively. The reverse gate leakage current is 10-9 A/mm, and the off-state drain-leakage current is 10-8 A/mm. The Vth hysteresis is extremely small at about 33 mV. We also investigate the mechanism that increases hole concentration of p-NiOx after annealing in oxygen environment resulted from the change of Ni2+ to Ni3+ and the surge of (111)-orientation.

Numerical analysis of the reverse blocking enhancement in High-K passivation AlGaN/GaN Schottky barrier diodes with gated edge termination

NASA Astrophysics Data System (ADS)

Bai, Zhiyuan; Du, Jiangfeng; Xin, Qi; Li, Ruonan; Yu, Qi

2018-02-01

We conducted a numerical analysis on high-K dielectric passivated AlGaN/GaN Schottky barrier diodes (HPG-SBDs) with a gated edge termination (GET). The reverse blocking characteristics were significantly enhanced without the stimulation of any parasitic effect by varying the dielectric thickness dge under the GET, thickness TP, and dielectric constant εr of the high-K passivation layer. The leakage current was reduced by increasing εr and decreasing dge. The breakdown voltage of the device was enhanced by increasing εr and TP. The highest breakdown voltage of 970 V and the lowest leakage current of 0.5 nA/mm were achieved under the conditions of εr = 80, TP = 800 nm, and dge = 10 nm. C-V simulation revealed that the HPG-SBDs induced no parasitic capacitance by comparing the integrated charges of the devices with different high-K dielectrics and different dge.

Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance

NASA Astrophysics Data System (ADS)

Yadav, Dharmendra Singh; Verma, Abhishek; Sharma, Dheeraj; Tirkey, Sukeshni; Raad, Bhagwan Ram

2017-11-01

Tunnel-field-effect-transistor (TFET) has emerged as one of the most prominent devices to replace conventional MOSFET due to its ability to provide sub-threshold slope below 60 mV/decade (SS ≤ 60 mV/decade) and low leakage current. Despite this, TFETs suffer from ambipolar behavior, lower ON-state current, and poor RF performance. To address these issues, we have introduced drain and gate work function engineering with hetero gate dielectric for the first time in charge plasma based doping-less TFET (DL TFET). In this, the usage of dual work functionality over the drain region significantly reduces the ambipolar behavior of the device by varying the energy barrier at drain/channel interface. Whereas, the presence of dual work function at the gate terminal increases the ON-state current (ION). The combined effect of dual work function at the gate and drain electrode results in the increment of ON-state current (ION) and decrement of ambipolar conduction (Iambi) respectively. Furthermore, the incorporation of hetero gate dielectric along with dual work functionality at the drain and gate electrode provides an overall improvement in the performance of the device in terms of reduction in ambipolarity, threshold voltage and sub-threshold slope along with improved ON-state current and high frequency figures of merit.

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE PAGES

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.; ...

2014-10-15

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Thickness engineering of atomic layer deposited Al2O3 films to suppress interfacial reaction and diffusion of Ni/Au gate metal in AlGaN/GaN HEMTs up to 600 °C in air

NASA Astrophysics Data System (ADS)

Suria, Ateeq J.; Yalamarthy, Ananth Saran; Heuser, Thomas A.; Bruefach, Alexandra; Chapin, Caitlin A.; So, Hongyun; Senesky, Debbie G.

2017-06-01

In this paper, we describe the use of 50 nm atomic layer deposited (ALD) Al2O3 to suppress the interfacial reaction and inter-diffusion between the gate metal and semiconductor interface, to extend the operation limit up to 600 °C in air. Suppression of diffusion is verified through Auger electron spectroscopy (AES) depth profiling and X-ray diffraction (XRD) and is further supported with electrical characterization. An ALD Al2O3 thin film (10 nm and 50 nm), which functions as a dielectric layer, was inserted between the gate metal (Ni/Au) and heterostructure-based semiconductor material (AlGaN/GaN) to form a metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). This extended the 50 nm ALD Al2O3 MIS-HEMT (50-MIS) current-voltage (Ids-Vds) and gate leakage (Ig,leakage) characteristics up to 600 °C. Both, the 10 nm ALD Al2O3 MIS-HEMT (10-MIS) and HEMT, failed above 350 °C, as evidenced by a sudden increase of approximately 50 times and 5.3 × 106 times in Ig,leakage, respectively. AES on the HEMT revealed the formation of a Ni-Au alloy and Ni present in the active region. Additionally, XRD showed existence of metal gallides in the HEMT. The 50-MIS enables the operation of AlGaN/GaN based electronics in oxidizing high-temperature environments, by suppressing interfacial reaction and inter-diffusion of the gate metal with the semiconductor.

Novel Dry-Type Glucose Sensor Based on a Metal-Oxide-Semiconductor Capacitor Structure with Horseradish Peroxidase + Glucose Oxidase Catalyzing Layer

NASA Astrophysics Data System (ADS)

Lin, Jing-Jenn; Wu, You-Lin; Hsu, Po-Yen

2007-10-01

In this paper, we present a novel dry-type glucose sensor based on a metal-oxide-semiconductor capacitor (MOSC) structure using SiO2 as a gate dielectric in conjunction with a horseradish peroxidase (HRP) + glucose oxidase (GOD) catalyzing layer. The tested glucose solution was dropped directly onto the window opened on the SiO2 layer, with a coating of HRP + GOD catalyzing layer on top of the gate dielectric. From the capacitance-voltage (C-V) characteristics of the sensor, we found that the glucose solution can induce an inversion layer on the silicon surface causing a gate leakage current flowing along the SiO2 surface. The gate current changes Δ I before and after the drop of glucose solution exhibits a near-linear relationship with increasing glucose concentration. The Δ I sensitivity is about 1.76 nA cm-2 M-1, and the current is quite stable 20 min after the drop of the glucose solution is tested.

Ultra-low voltage and ultra-low power consumption nonvolatile operation of a three-terminal atomic switch.

PubMed

Wang, Qi; Itoh, Yaomi; Tsuruoka, Tohru; Aono, Masakazu; Hasegawa, Tsuyoshi

2015-10-21

Nonvolatile three-terminal operation, with a very small range of bias sweeping (-80 to 250 mV), a high on/off ratio of up to six orders of magnitude, and a very small gate leakage current (<1 pA), is demonstrated using an Ag (gate)/Ta2 O5 (ionic transfer layer)/Pt (source), Pt (drain) three-terminal atomic switch structure. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Device optimization and scaling properties of a gate-on-germanium source tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Chattopadhyay, Avik; Mallik, Abhijit; Omura, Yasuhisa

2015-06-01

A gate-on-germanium source (GoGeS) tunnel field-effect transistor (TFET) shows great promise for low-power (sub-0.5 V) applications. A detailed investigation, with the help of a numerical device simulator, on the effects of variation in different structural parameters of a GoGeS TFET on its electrical performance is reported in this paper. Structural parameters such as κ-value of the gate dielectric, length and κ-value of the spacer, and doping concentrations of both the substrate and source are considered. A low-κ symmetric spacer and a high-κ gate dielectric are found to yield better device performance. The substrate doping influences only the p-i-n leakage floor. The source doping is found to significantly affect performance parameters such as OFF-state current, ON-state current and subthreshold swing, in addition to a threshold voltage shift. Results of the investigation on the gate length scaling of such devices are also reported in this paper.

Highly conducting leakage-free electrolyte for SrCoOx-based non-volatile memory device

NASA Astrophysics Data System (ADS)

Katase, Takayoshi; Suzuki, Yuki; Ohta, Hiromichi

2017-10-01

The electrochemical switching of SrCoOx-based non-volatile memory with a thin-film-transistor structure was examined by using liquid-leakage-free electrolytes with different conductivities (σ) as the gate insulator. We first examined leakage-free water, which is incorporated in the amorphous (a-) 12CaO.7Al2O3 film with a nanoporous structure (Calcium Aluminate with Nanopore), but the electrochemical oxidation/reduction of the SrCoOx layer required the application of a high gate voltage (Vg) up to 20 V for a very long current-flowing-time (t) ˜40 min, primarily due to the low σ [2.0 × 10-8 S cm-1 at room temperature (RT)] of leakage-free water. We then controlled the σ of the leakage-free electrolyte, infiltrated in the a-NaxTaO3 film with a nanopillar array structure, from 8.0 × 10-8 S cm-1 to 2.5 × 10-6 S cm-1 at RT by changing the x = 0.01-1.0. As the result, the t, required for the metallization of the SrCoOx layer under small Vg = -3 V, becomes two orders of magnitude shorter with increase of the σ of the a-NaxTaO3 leakage-free electrolyte. These results indicate that the ion migration in the leakage-free electrolyte is the rate-determining step for the electrochemical switching, compared to the other electrochemical process, and the high σ of the leakage-free electrolyte is the key factor for the development of the non-volatile SrCoOx-based electro-magnetic phase switching device.

Leakage current conduction, hole injection, and time-dependent dielectric breakdown of n-4H-SiC MOS capacitors during positive bias temperature stress

NASA Astrophysics Data System (ADS)

Samanta, Piyas; Mandal, Krishna C.

2017-01-01

The conduction mechanism(s) of gate leakage current JG through thermally grown silicon dioxide (SiO2) films on the silicon (Si) face of n-type 4H-silicon carbide (4H-SiC) has been studied in detail under positive gate bias. It was observed that at an oxide field above 5 MV/cm, the leakage current measured up to 303 °C can be explained by Fowler-Nordheim (FN) tunneling of electrons from the accumulated n-4H-SiC and Poole-Frenkel (PF) emission of trapped electrons from the localized neutral traps located at ≈2.5 eV below the SiO2 conduction band. However, the PF emission current IPF dominates the FN electron tunneling current IFN at oxide electric fields Eox between 5 and 10 MV/cm and in the temperature ranging from 31 to 303 °C. In addition, we have presented a comprehensive analysis of injection of holes and their subsequent trapping into as-grown oxide traps eventually leading to time-dependent dielectric breakdown during electron injection under positive bias temperature stress (PBTS) in n-4H-SiC metal-oxide-silicon carbide structures. Holes were generated in the heavily doped n-type polycrystalline silicon (n+-polySi) gate (anode) as well as in the oxide bulk via band-to-band ionization by the hot-electrons depending on their energy and SiO2 film thickness at Eox between 6 and 10 MV/cm (prior to the intrinsic oxide breakdown field). Transport of hot electrons emitted via both FN and PF mechanisms was taken into account. On the premise of the hole-induced oxide breakdown model, the time- and charge-to-breakdown ( tBD and QBD ) of 8.5 to 47 nm-thick SiO2 films on n-4H-SiC were estimated at a wide range of temperatures. tBD follows the Arrhenius law with activation energies varying inversely with initial applied constant field Eox supporting the reciprocal field ( 1 /E ) model of breakdown irrespective of SiO2 film thicknesses. We obtained an excellent margin (6.66 to 6.33 MV/cm at 31 °C and 5.11 to 4.55 MV/cm at 303 °C) of normal operating field for a 10-year projected lifetime of 8.5 to 47 nm-thick SiO2 films on n-4H-SiC under positive bias on the n+-polySi gate. Furthermore, the projected maximum operating oxide field was little higher in metal gate devices compared to n+-polySi gate devices having an identically thick thermal SiO2 films under PBTS.

A high-performance channel engineered charge-plasma-based MOSFET with high-κ spacer

NASA Astrophysics Data System (ADS)

Shan, Chan; Wang, Ying; Luo, Xin; Bao, Meng-tian; Yu, Cheng-hao; Cao, Fei

2017-12-01

In this paper, the performance of graded channel double-gate MOSFET (GC-DGFET) that utilizes the charge-plasma concept and a high-κ spacer is investigated through 2-D device simulations. The results demonstrate that GC-DGFET with high-κ spacer can effectively improve the ON-state driving current (ION) and reduce the OFF-leakage current (IOFF). We find that reduction of the initial energy barrier between the source and channel is the origin of this ION enhancement. The reason for the IOFF reduction is identified to be the extension of the effective channel length owing to the fringing field via high-κ spacers. Consequently, these devices offer enhanced performance by reducing the total gate-to-gate capacitance (Cgg) and decreasing the intrinsic delay (τ).

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

NASA Astrophysics Data System (ADS)

Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Wang, Qianqiong

2017-09-01

The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure has the superior performance-higher retention time (RT) and weak temperature dependence. But the performance of TFET DRAM cell is sensitive to programming condition. In this paper, the guideline of programming optimization is discussed in detail by using simulation tool—Silvaco Atlas. Both the writing and reading operations of DG-TFET DRAM depend on the band-to-band tunneling (BTBT). During the writing operation, the holes coming from BTBT governed by Gate2 are stored in potential well under Gate2. A small negative voltage is applied at Gate2 to retain holes for a long time during holding "1". The BTBT governed by Gate1 mainly influences the reading current. Using the optimized programming condition, the DG-TFET DRAM obtains the higher current ratio of reading "1" to reading "0" (107) and RT of more than 2 s. The higher RT reduces the refresh rate and dynamic power consumption of DRAM.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

NASA Astrophysics Data System (ADS)

Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

Leakage current conduction and reliability assessment of passivating thin silicon dioxide films on n-4H-SiC

NASA Astrophysics Data System (ADS)

Samanta, Piyas; Mandal, Krishna C.

2016-09-01

We have analyzed the mechanisms of leakage current conduction in passivating silicon dioxide (SiO2) films grown on (0 0 0 1) silicon (Si) face of n-type 4H-SiC (silicon carbide). It was observed that the experimentally measured gate current density in metal-oxide-silicon carbide (MOSiC) structures under positive gate bias at an oxide field Eox above 5 MV/cm is comprised of Fowler-Nordheim (FN) tunneling of electrons from the accumulated n-4H-SiC and Poole-Frenkel (PF) emission of trapped electrons from the localized neutral traps in the SiO2 gap, IFN and IPF, respectively at temperatures between 27 and 200 °C. In MOSiC structures, PF mechanism dominates FN tunneling of electrons from the accumulation layer of n-4H-SiC due to high density (up to 1013 cm-2) of carbon-related acceptor-like traps located at about 2.5 eV below the SiO2 conduction band (CB). These current conduction mechanisms were taken into account in studying hole injection/trapping into 10 nm-thick tunnel oxide on the Si face of 4H-SiC during electron injection from n-4H-SiC under high-field electrical stress with positive bias on the heavily doped n-type polysilicon (n+-polySi) gate at a wide range of temperatures between 27 and 200 °C. Holes were generated in the n+-polySi anode material by the hot-electrons during their transport through thin oxide films at oxide electric fields Eox from 5.6 to 8.0 MV/cm (prior to the intrinsic oxide breakdown field). Time-to-breakdown tBD of the gate dielectric was found to follow reciprocal field (1/E) model irrespective of stress temperatures. Despite the significant amount of process-induced interfacial electron traps contributing to a large amount of leakage current via PF emission in thermally grown SiO2 on the Si-face of n-4H-SiC, MOSiC devices having a 10 nm-thick SiO2 film can be safely used in 5 V TTL logic circuits over a period of 10 years.

High-performance enhancement-mode Al2O3/InAlGaN/GaN MOS high-electron mobility transistors with a self-aligned gate recessing technology

NASA Astrophysics Data System (ADS)

Zhang, Kai; Kong, Cen; Zhou, Jianjun; Kong, Yuechan; Chen, Tangsheng

2017-02-01

The paper reports high-performance enhancement-mode MOS high-electron mobility transistors (MOS-HEMTs) based on a quaternary InAlGaN barrier. Self-aligned gate technology is used for gate recessing, dielectric deposition, and gate electrode formation. An improved digital recessing process is developed, and an Al2O3 gate dielectric grown with O2 plasma is used. Compared to results with AlGaN barrier, the fabricated E-mode MOS-HEMT with InAlGaN barrier delivers a record output current density of 1.7 A/mm with a threshold voltage (V TH) of 1.5 V, and a small on-resistance (R on) of 2.0 Ω·mm. Excellent V TH hysteresis and greatly improved gate leakage characteristics are also demonstrated.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, S.; Dhar, A., E-mail: adhar@phy.iitkgp.ernet.in

Highlights: • Alternative to chemically crosslinking of PMMA to achieve low leakage in provided. • Effect of LiF in reducing gate leakage through the OFET device is studied. • Effect of gate leakage on transistor performance has been investigated. • Low voltage operable and low temperature processed n-channel OFETs were fabricated. - Abstract: We report low temperature processed, low voltage operable n-channel organic field effect transistors (OFETs) using N,N′-Dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C{sub 8}) organic semiconductor and poly(methylmethacrylate) (PMMA)/lithium fluoride (LiF) bilayer gate dielectric. We have studied the role of LiF buffer dielectric in effectively reducing the gate leakage through the device andmore » thus obtaining superior performance in contrast to the single layer PMMA dielectric devices. The bilayer OFET devices had a low threshold voltage (V{sub t}) of the order of 5.3 V. The typical values of saturation electron mobility (μ{sub s}), on/off ratio and inverse sub-threshold slope (S) for the range of devices made were estimated to be 2.8 × 10{sup −3} cm{sup 2}/V s, 385, and 3.8 V/decade respectively. Our work thus provides a potential substitution for much complicated process of chemically crosslinking PMMA to achieve low leakage, high capacitance, and thus low operating voltage OFETs.« less

Conduction mechanism of leakage current due to the traps in ZrO2 thin film

NASA Astrophysics Data System (ADS)

Seo, Yohan; Lee, Sangyouk; An, Ilsin; Song, Chulgi; Jeong, Heejun

2009-11-01

In this work, a metal-oxide-semiconductor capacitor with zirconium oxide (ZrO2) gate dielectric was fabricated by an atomic layer deposition (ALD) technique and the leakage current characteristics under negative bias were studied. From the result of current-voltage curves there are two possible conduction mechanisms to explain the leakage current in the ZrO2 thin film. The dominant mechanism is the space charge limited conduction in the high-electric field region (1.5-5.0 MV cm-1) while the trap-assisted tunneling due to the existence of traps is prevailed in the low-electric field region (0.8-1.5 MV cm-1). Conduction caused by the trap-assisted tunneling is found from the experimental results of a weak temperature dependence of current, and the trap barrier height is obtained. The space charge limited conduction is evidenced, for different temperatures, by Child's law dependence of current density versus voltage. Child's law dependence can be explained by considering a single discrete trapping level and we can obtain the activation energy of 0.22 eV.

Study of fully-depleted Ge double-gate n-type Tunneling Field-Effect Transistors for improvement in on-state current and sub-threshold swing

NASA Astrophysics Data System (ADS)

Liu, Xiangyu; Hu, Huiyong; Wang, Meng; Zhang, Heming; Cui, Shimin; Shu, Bin; Wang, Bin

2018-01-01

In this paper, a fully-depleted (FD) Ge double-gate (DG) n-type Tunneling Field-Effect Transistors (TFET) structure is studied in detail by two-dimensional numerical simulation. The simulation results indicated that the on-state current Ion and on-off ratio of the FD Ge DG-TFET increases about 1 order of magnitude comparing with the Conventional Ge DG-TFET, and Ion=3.95×10-5 A/μm and the below 60 mV/decade subthreshold swing S=26.4 mV/decade are achieved with the length of gate LD=20 nm, the workfuntion of metal gate Φm=0.2 eV and the doping concentration of n+-type-channel ND=1×1018 cm-3. Moreover, the impacts of Φm, ND and LD are investigated. The simulation results indicated that the off-state current Ioff includes the tunneling current at the middle of channel IB the gated-induced drain leakage (GIDL) current IGIDL. With optimized Φm and ND, Ioff is reduced about 2 orders of magnitude to 2.5×10-13 A/μm with LD increasing from 40 nm to 100 nm, and on-off ratio is increased to 1.58×107.

Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process

NASA Astrophysics Data System (ADS)

Wang, Yan-Rong; Yang, Hong; Xu, Hao; Wang, Xiao-Lei; Luo, Wei-Chun; Qi, Lu-Wei; Zhang, Shu-Xiang; Wang, Wen-Wu; Yan, Jiang; Zhu, Hui-Long; Zhao, Chao; Chen, Da-Peng; Ye, Tian-Chun

2015-11-01

A multi-deposition multi-annealing technique (MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device’s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown (TDDB) characteristics of positive channel metal oxide semiconductor (PMOS) under different MDMA process conditions, including the deposition/annealing (D&A) cycles, the D&A time, and the total annealing time. The results show that the increases of the number of D&A cycles (from 1 to 2) and D&A time (from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail (TTF) at 63.2% increases by about several times. However, too many D&A cycles (such as 4 cycles) make the equivalent oxide thickness (EOT) increase by about 1 Å and the TTF of PMOS worsen. Moreover, different D&A times and numbers of D&A cycles induce different breakdown mechanisms. Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601) and the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129).

Pulse sequences for suppressing leakage in single-qubit gate operations

NASA Astrophysics Data System (ADS)

Ghosh, Joydip; Coppersmith, S. N.; Friesen, Mark

2017-06-01

Many realizations of solid-state qubits involve couplings to leakage states lying outside the computational subspace, posing a threat to high-fidelity quantum gate operations. Mitigating leakage errors is especially challenging when the coupling strength is unknown, e.g., when it is caused by noise. Here we show that simple pulse sequences can be used to strongly suppress leakage errors for a qubit embedded in a three-level system. As an example, we apply our scheme to the recently proposed charge quadrupole (CQ) qubit for quantum dots. These results provide a solution to a key challenge for fault-tolerant quantum computing with solid-state elements.

Modeling of Dual Gate Material Hetero-dielectric Strained PNPN TFET for Improved ON Current

NASA Astrophysics Data System (ADS)

Kumari, Tripty; Saha, Priyanka; Dash, Dinesh Kumar; Sarkar, Subir Kumar

2018-01-01

The tunnel field effect transistor (TFET) is considered to be a promising alternative device for future low-power VLSI circuits due to its steep subthreshold slope, low leakage current and its efficient performance at low supply voltage. However, the main challenging issue associated with realizing TFET for wide scale applications is its low ON current. To overcome this, a dual gate material with the concept of dielectric engineering has been incorporated into conventional TFET structure to tune the tunneling width at source-channel interface allowing significant flow of carriers. In addition to this, N+ pocket is implanted at source-channel junction of the proposed structure and the effect of strain is added for exploring the performance of the model in nanoscale regime. All these added features upgrade the device characteristics leading to higher ON current, low leakage and low threshold voltage. The present work derives the surface potential, electric field expression and drain current by solving 2D Poisson's equation at different boundary conditions. A comparative analysis of proposed model with conventional TFET has been done to establish the superiority of the proposed structure. All analytical results have been compared with the results obtained in SILVACO ATLAS device simulator to establish the accuracy of the derived analytical model.

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

NASA Astrophysics Data System (ADS)

Kumar, Manoj; Pratap, Yogesh; Haldar, Subhasis; Gupta, Mridula; Gupta, R. S.

2017-12-01

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported, to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions. This novel structure offers low barrier height at the source and offers high ON-state current. The I ON/I OFF of ISE-CGAA-SB-MOSFET increases by 1177 times and offers steeper subthreshold slope (~60 mV/decade). However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate, dual metal gate, single metal gate with ISE, and dual metal gate with ISE has been presented. The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design. The numerical simulation is performed using the ATLAS-3D device simulator.

III-V Ultra-Thin-Body InGaAs/InAs MOSFETs for Low Standby Power Logic Applications

NASA Astrophysics Data System (ADS)

Huang, Cheng-Ying

As device scaling continues to sub-10-nm regime, III-V InGaAs/InAs metal- oxide-semiconductor ?eld-e?ect transistors (MOSFETs) are promising candidates for replacing Si-based MOSFETs for future very-large-scale integration (VLSI) logic applications. III-V InGaAs materials have low electron effective mass and high electron velocity, allowing higher on-state current at lower VDD and reducing the switching power consumption. However, III-V InGaAs materials have a narrower band gap and higher permittivity, leading to large band-to-band tunneling (BTBT) leakage or gate-induced drain leakage (GIDL) at the drain end of the channel, and large subthreshold leakage due to worse electrostatic integrity. To utilize III-V MOSFETs in future logic circuits, III-V MOSFETs must have high on-state performance over Si MOSFETs as well as very low leakage current and low standby power consumption. In this dissertation, we will report InGaAs/InAs ultra-thin-body MOSFETs. Three techniques for reducing the leakage currents in InGaAs/InAs MOSFETs are reported as described below. 1) Wide band-gap barriers: We developed AlAs0.44Sb0.56 barriers lattice-match to InP by molecular beam epitaxy (MBE), and studied the electron transport in In0.53Ga0.47As/AlAs 0.44Sb0.56 heterostructures. The InGaAs channel MOSFETs using AlAs0.44Sb0.56 bottom barriers or p-doped In0.52 Al0.48As barriers were demonstrated, showing significant suppression on the back barrier leakage. 2) Ultra-thin channels: We investigated the electron transport in InGaAs and InAs ultra-thin quantum wells and ultra-thin body MOSFETs (t ch ~ 2-4 nm). For high performance logic, InAs channels enable higher on-state current, while for low power logic, InGaAs channels allow lower BTBT leakage current. 3) Source/Drain engineering: We developed raised InGaAs and recessed InP source/drain spacers. The raised InGaAs source/drain spacers improve electrostatics, reducing subthreshold leakage, and smooth the electric field near drain, reducing BTBT leakage. With further replacement of raised InGaAs spacers by recessed, doping-graded InP spacers at high field regions, BTBT leakage can be reduced ~100:1. Using the above-mentioned techniques, record high performance InAs MOSFETs with a 2.7 nm InAs channel and a ZrO2 gate dielectric were demonstrated with Ion = 500 microA/microm at Ioff = 100 nA/microm and VDS =0.5 V, showing the highest on-state performance among all the III-V MOSFETs and comparable performance to 22 nm Si FinFETs. Record low leakage InGaAs MOSFETs with recessed InP source/drain spacers were also demonstrated with minimum I off = 60 pA/microm at 30 nm-Lg , and Ion = 150 microA/microm at I off = 1 nA/microm and VDS =0.5 V. This recessed InP source/drain spacer technique improves device scalability and enables III-V MOSFETs for low standby power logic applications. Furthermore, ultra-thin InAs channel MOSFETs were fabricated on Si substrates, exhibiting high yield and high transconductance gm ~2.0 mS/microm at 20 nm- Lg and VDS =0.5 V. With further scaling of gate lengths, a 12 nm-Lg III-V MOSFET has shown maximum Ion/Ioff ratio ~8.3x105 , confirming that III-V MOSFETs are scalable to sub-10-nm technology nodes.

Dysregulated Zn2+ homeostasis impairs cardiac type-2 ryanodine receptor and mitsugumin 23 functions, leading to sarcoplasmic reticulum Ca2+ leakage.

PubMed

Reilly-O'Donnell, Benedict; Robertson, Gavin B; Karumbi, Angela; McIntyre, Connor; Bal, Wojciech; Nishi, Miyuki; Takeshima, Hiroshi; Stewart, Alan J; Pitt, Samantha J

2017-08-11

Aberrant Zn 2+ homeostasis is associated with dysregulated intracellular Ca 2+ release, resulting in chronic heart failure. In the failing heart a small population of cardiac ryanodine receptors (RyR2) displays sub-conductance-state gating leading to Ca 2+ leakage from sarcoplasmic reticulum (SR) stores, which impairs cardiac contractility. Previous evidence suggests contribution of RyR2-independent Ca 2+ leakage through an uncharacterized mechanism. We sought to examine the role of Zn 2+ in shaping intracellular Ca 2+ release in cardiac muscle. Cardiac SR vesicles prepared from sheep or mouse ventricular tissue were incorporated into phospholipid bilayers under voltage-clamp conditions, and the direct action of Zn 2+ on RyR2 channel function was examined. Under diastolic conditions, the addition of pathophysiological concentrations of Zn 2+ (≥2 nm) caused dysregulated RyR2-channel openings. Our data also revealed that RyR2 channels are not the only SR Ca 2+ -permeable channels regulated by Zn 2+ Elevating the cytosolic Zn 2+ concentration to 1 nm increased the activity of the transmembrane protein mitsugumin 23 (MG23). The current amplitude of the MG23 full-open state was consistent with that previously reported for RyR2 sub-conductance gating, suggesting that in heart failure in which Zn 2+ levels are elevated, RyR2 channels do not gate in a sub-conductance state, but rather MG23-gating becomes more apparent. We also show that in H9C2 cells exposed to ischemic conditions, intracellular Zn 2+ levels are elevated, coinciding with increased MG23 expression. In conclusion, these data suggest that dysregulated Zn 2+ homeostasis alters the function of both RyR2 and MG23 and that both ion channels play a key role in diastolic SR Ca 2+ leakage. © 2017 by The American Society for Biochemistry and Molecular Biology, Inc.

High-performance SEGISFET pH Sensor using the structure of double-gate a-IGZO TFTs with engineered gate oxides

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2017-03-01

In this paper, we propose a high-performance separative extended gate ion-sensitive field-effect transistor (SEGISFET) that consists of a tin dioxide (SnO2) SEG sensing part and a double-gate structure amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with tantalum pentoxide/silicon dioxide (Ta2O5/SiO2)-engineered top-gate oxide. To increase sensitivity, we maximized the capacitive coupling ratio by applying high-k dielectric at the top-gate oxide layer. As an engineered top-gate oxide, a stack of 25 nm-thick Ta2O5 and 10 nm-thick SiO2 layers was found to simultaneously satisfy a small equivalent oxide thickness (˜17.14 nm), a low leakage current, and a stable interfacial property. The threshold-voltage instability, which is a fundamental issue in a-IGZO TFTs, was improved by low-temperature post-deposition annealing (˜87 °C) using microwave irradiation. The double-gate structure a-IGZO TFTs with engineered top-gate oxide exhibited high mobility, small subthreshold swing, high drive current, and larger on/off current ratio. The a-IGZO SEGISFETs with a dual-gate sensing mode showed a pH sensitivity of 649.04 mV pH-1, which is far beyond the Nernst limit. The non-ideal behavior of ISFETs, hysteresis, and drift effect also improved. These results show that the double-gate structure a-IGZO TFTs with engineered top-gate oxide can be a good candidate for cheap and disposable SEGISFET sensors.

Electronic Properties and Device Applications of III-V Compound Semiconductor Native Oxides

DTIC Science & Technology

2006-03-02

MRD X-ray diffractometer with CuKa as the radiation source. The doping level in GaAs was meassured by electrochemical voltage (ECV) using an Accent... hard to prevent the gate metal from overlapping the mesa edge thus creating a parasitic leakage path to the channel42. To reduce the gate leakage

Leakage of The Quantum Dot Hybrid Qubit in The Strong Driving Regime

NASA Astrophysics Data System (ADS)

Yang, Yuan-Chi; Friesen, Mark; Coppersmith, S. N.

Recent experimental demonstrations of high-fidelity single-qubit gates suggest that the quantum dot hybrid qubit is a promising candidate for large-scale quantum computing. The qubit is comprised of three electrons in a double quantum dot, and can be protected from charge noise by operating in an extended sweet-spot regime. Gate operations are based on exchange interactions mediated by an excited state. However, strong resonant driving causes unwanted leakage into the excited state. Here, we theoretically analyze leakage caused by strong driving, and explore methods for increasing gate fidelities. This work was supported in part by ARO (W911NF-12-0607), NSF (PHY-1104660), ONR (N00014-15-1-0029), and the University of Wisconsin-Madison.

A novel thin-film transistor with step gate-overlapped lightly doped drain and raised source/drain design

NASA Astrophysics Data System (ADS)

Chien, Feng-Tso; Chen, Jian-Liang; Chen, Chien-Ming; Chen, Chii-Wen; Cheng, Ching-Hwa; Chiu, Hsien-Chin

2017-11-01

In this paper, a novel step gate-overlapped lightly doped drain (GOLDD) with raised source/drain (RSD) structure (SGORSD) is proposed for TFT electronic device application. The new SGORSD structure could obtain a low electric field at channel near the drain side owing to a step GOLDD design. Compared to the conventional device, the SGORSD TFT exhibits a better kink effect and higher breakdown performance due to the reduced drain electric field (D-EF). In addition, the leakage current also can be suppressed. Moreover, the device stability, such as the threshold voltage shift and drain current degradation under a high gate bias, is improved by the design of SGORSD structure. Therefore, this novel step GOLDD structure can be a promising design to be used in active-matrix flat panel electronics.

Large-Scale Precise Printing of Ultrathin Sol-Gel Oxide Dielectrics for Directly Patterned Solution-Processed Metal Oxide Transistor Arrays.

PubMed

Lee, Won-June; Park, Won-Tae; Park, Sungjun; Sung, Sujin; Noh, Yong-Young; Yoon, Myung-Han

2015-09-09

Ultrathin and dense metal oxide gate di-electric layers are reported by a simple printing of AlOx and HfOx sol-gel precursors. Large-area printed indium gallium zinc oxide (IGZO) thin-film transistor arrays, which exhibit mobilities >5 cm(2) V(-1) s(-1) and gate leakage current of 10(-9) A cm(-2) at a very low operation voltage of 2 V, are demonstrated by continuous simple bar-coated processes. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Double gate impact ionization MOS transistor: Proposal and investigation

NASA Astrophysics Data System (ADS)

Yang, Zhaonian; Zhang, Yue; Yang, Yuan; Yu, Ningmei

2017-02-01

In this paper, a double gate impact ionization MOS (DG-IMOS) transistor with improved performance is proposed and investigated by TCAD simulation. In the proposed design, a second gate is introduced in a conventional impact ionization MOS (IMOS) transistor that lengthens the equivalent channel length and suppresses the band-to-band tunneling. The OFF-state leakage current is reduced by over four orders of magnitude. At the ON-state, the second gate is negatively biased in order to enhance the electric field in the intrinsic region. As a result, the operating voltage does not increase with the increase in the channel length. The simulation result verifies that the proposed DG-IMOS achieves a better switching characteristic than the conventional is achieved. Lastly, the application of the DG-IMOS is discussed theoretically.

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET.

PubMed

Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Wang, Qianqiong

2017-09-06

The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure has the superior performance-higher retention time (RT) and weak temperature dependence. But the performance of TFET DRAM cell is sensitive to programming condition. In this paper, the guideline of programming optimization is discussed in detail by using simulation tool-Silvaco Atlas. Both the writing and reading operations of DG-TFET DRAM depend on the band-to-band tunneling (BTBT). During the writing operation, the holes coming from BTBT governed by Gate2 are stored in potential well under Gate2. A small negative voltage is applied at Gate2 to retain holes for a long time during holding "1". The BTBT governed by Gate1 mainly influences the reading current. Using the optimized programming condition, the DG-TFET DRAM obtains the higher current ratio of reading "1" to reading "0" (10 7 ) and RT of more than 2 s. The higher RT reduces the refresh rate and dynamic power consumption of DRAM.

A novel hetero-material gate-underlap electrically doped TFET for improving DC/RF and ambipolar behaviour

NASA Astrophysics Data System (ADS)

Yadav, Shivendra; Sharma, Dheeraj; Chandan, Bandi Venkata; Aslam, Mohd; Soni, Deepak; Sharma, Neeraj

2018-05-01

In this article, the impact of gate-underlap with hetero material (low band gap) has been investigated in terms of DC and Analog/RF parameters by proposed device named as hetero material gate-underlap electrically doped TFET (HM-GUL-ED-TFET). Gate-underlap resolves the problem of ambipolarity, gate leakage current (Ig) and slightly improves the gate to drain capacitance, but DC performance is almost unaffected. Further, the use of low band gap material (Si0.5 Ge) in proposed device causes a drastic improvement in the DC as well as RF figures of merit. We have investigated the Si0.5 Ge as a suitable candidate among different low band gap materials. In addition, the sensitivity of gate-underlap in terms of gate to drain inversion and parasitic capacitances has been studied for HM-GUL-ED-TFET. Further, relatively it is observed that gate-underlap is a better way than drain-underlap in the proposed structure to improve Analog/RF performances without degrading the DC parameters of device. Additionally, hetero-junction alignment analysis has been done for fabrication feasibility.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Le, Son Phuong; Ui, Toshimasa; Nguyen, Tuan Quy

Using aluminum titanium oxide (AlTiO, an alloy of Al{sub 2}O{sub 3} and TiO{sub 2}) as a high-k gate insulator, we fabricated and investigated AlTiO/AlGaN/GaN metal-insulator-semiconductor heterojunction field-effect transistors. From current low-frequency noise (LFN) characterization, we find Lorentzian spectra near the threshold voltage, in addition to 1/f spectra for the well-above-threshold regime. The Lorentzian spectra are attributed to electron trapping/detrapping with two specific time constants, ∼25 ms and ∼3 ms, which are independent of the gate length and the gate voltage, corresponding to two trap level depths of 0.5–0.7 eV with a 0.06 eV difference in the AlTiO insulator. In addition, gate leakage currents aremore » analyzed and attributed to the Poole-Frenkel mechanism due to traps in the AlTiO insulator, where the extracted trap level depth is consistent with the Lorentzian LFN.« less

Performance and Design Considerations of a Novel Dual-Material Gate Carbon Nanotube Field-Effect Transistors: Nonequilibrium Green's Function Approach

NASA Astrophysics Data System (ADS)

Arefinia, Zahra; Orouji, Ali A.

2009-02-01

The concept of dual-material gate (DMG) is applied to the carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions, and the features exhibited by the resulting new structure, i.e., the DMG-CNTFET structure, have been examined for the first time by developing a two-dimensional (2D) full quantum simulation. The simulations have been done by the self-consistent solution of 2D Poisson-Schrödinger equations, within the nonequilibrium Green's function (NEGF) formalism. The results show DMG-CNTFET decreases significantly leakage current and drain conductance and increases on-off current ratio and voltage gain as compared to the single material gate counterparts CNTFET. It is seen that short channel effects in this structure are suppressed because of the perceivable step in the surface potential profile, which screens the drain potential. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate metals. Therefore, this work provides an incentive for further experimental exploration.

HIGH-k GATE DIELECTRIC: AMORPHOUS Ta/La2O3 FILMS GROWN ON Si AT LOW PRESSURE

NASA Astrophysics Data System (ADS)

Bahari, Ali; Khorshidi, Zahra

2014-09-01

In the present study, Ta/La2O3 films (La2O3 doped with Ta2O5) as a gate dielectric were prepared using a sol-gel method at low pressure. Ta/La2O3 film has some hopeful properties as a gate dielectric of logic device. The structure and morphology of Ta/La2O3 films were studied using X-ray diffraction (XRD), atomic force microscopy (AFM) and scanning electron microscopy (SEM). Electrical properties of films were performed using capacitance-voltage (C-V) and current density-voltage (J-V) measurements. The optical bandgap of samples was studied by UV-visible optical absorbance measurement. The optical bandgap, Eopt, is determined from the absorbance spectra. The obtained results show that Ta/La2O3 film as a good gate dielectric has amorphous structure, good thermal stability, high dielectric constant (≈ 25), low leakage current and wide bandgap (≈ 4.7 eV).

Chemical vapor deposited monolayer MoS2 top-gate MOSFET with atomic-layer-deposited ZrO2 as gate dielectric

NASA Astrophysics Data System (ADS)

Hu, Yaoqiao; Jiang, Huaxing; Lau, Kei May; Li, Qiang

2018-04-01

For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec-1, and a field-effect electron mobility of 12.1 cm2 V-1 s-1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm-1 at V DS = 5 V. The gate leakage current is below 10-2 A cm-2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm-1 is obtained. Gate hysteresis and frequency-dependent capacitance-voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ˜3 × 1012 cm-2 eV-1.

Growth and Implementation of Carbon-Doped AlGaN Layers for Enhancement-Mode HEMTs on 200 mm Si Substrates

NASA Astrophysics Data System (ADS)

Su, Jie; Posthuma, Niels; Wellekens, Dirk; Saripalli, Yoga N.; Decoutere, Stefaan; Arif, Ronald; Papasouliotis, George D.

2016-12-01

We are reporting the growth of AlGaN based enhancement-mode high electron mobility transistors (HEMTs) on 200 mm silicon (111) substrates using a single wafer metalorganic chemical vapor deposition reactor. It is found that TMAl pre-dosing conditions are critical in controlling the structural quality, surface morphology, and wafer bow of the HEMT stack. Optimal structural quality and pit-free surface are demonstrated for AlGaN HEMTs with pre-dosing temperature at 750°C. Intrinsically, carbon-doped AlGaN, is used as the current blocking layer in the HEMT structures. The lateral buffer breakdown and device breakdown characteristics, reach 400 V at a leakage current of 1 μA/mm measured at 150°C. The fabricated HEMT devices, with a Mg doped p-GaN gate layer, are operating in enhancement mode reaching a positive threshold voltage of 2-2.5 V, a low on-resistance of 10.5 Ω mm with a high drain saturation current of 0.35 A/mm, and a low forward bias gate leakage current of 0.5 × 10-6 A/mm ( V gs = 7 V). Tight distribution of device parameters across the 200 mm wafers and over repeat process runs is observed.

Lanthanide-based oxides and silicates for high-kappa gate dielectric applications

NASA Astrophysics Data System (ADS)

Jur, Jesse Stephen

The ability to improve performance of the high-end metal oxide semiconductor field effect transistor (MOSFET) is highly reliant on the dimensional scaling of such a device. In scaling, a decrease in dielectric thickness results in high current leakage between the electrode and the substrate by way of direct tunneling through the gate dielectric. Observation of a high leakage current when the standard gate dielectric, SiO2, is decreased below a thickness of 1.5 nm requires engineering of a replacement dielectric that is much more scalable. This high-kappa dielectric allows for a physically thicker oxide, reducing leakage current. Integration of select lanthanide-based oxides and silicates, in particular lanthanum oxide and silicate, into MOS gate stack devices is examined. The quality of the high-kappa dielectrics is monitored electrically to determine properties such as equivalent oxide thickness, leakage current density and defect densities. In addition, analytical characterization of the dielectric and the gate stack is provided to examine the materialistic significance to the change of the electrical properties of the devices. In this work, lanthanum oxide films have been deposited by thermal evaporation on to a pre-grown chemical oxide layer on silicon. It is observed that the SiO2 interfacial layer can be consumed by a low-temperature reaction with lanthanum oxide to produce a high-quality silicate. This is opposed to depositing lanthanum oxide directly on silicon, which can possibly favor silicide formation. The importance of oxygen regulation in the surrounding environment of the La2O3-SiO2 reaction-anneal is observed. By controlling the oxygen available during the reaction, SiO2 growth can be limited to achieve high stoichiometric ratios of La2O 3 to SiO2. As a result, MOS devices with an equivalent oxide thickness (EOT) of 5 A and a leakage current density of 5.0 A/cm 2 are attained. This data equals the best value achieved in this field and is a substantial improvement over SiO(N) dielectrics, allowing for increased device scaling. High-temperature processing, consistent with the source/drain activation anneal in MOSFET processing, is performed on lanthanum-silicate based MOS devices with Ta or TaN gate electrodes and a W metal capping layer. The thermal limit of Ta is observed to be less than 800°C, resulting in a phase transformation that can result in uncontrolled shifting of the MOS device flat-band voltage. TaN is observed to be more thermally stable (up to 1000°C) and results in an increase in the capacitance density suggesting that it impedes oxygen reaction with silicon to produce SiO2. It is later observed that a W metal capping layer can serve as a high-oxygen source, which results in an increased interfacial SiO2 formation. By limiting the oxygen content in the W capping layer and by utilizing a thermally stable TaN gate electrode, control over the electrical properties of the MOS device is acquired. To determine the stability of amorphous lanthanum-silicate in contact with investigated by means of back-side secondary ion mass spectroscopy profiling. The results are the first reported data showing that the lanthanum incorporated in the silica matrix doe not diffuse into the silicon substrate after high temperature processing. The decrease in the device effective work function (φM,eff ) observed in these samples is examined in detail. First, as a La 2O3 capping layer on HfSiO(N), the shift yields ideal-φ M,eff values for nMOSFET deices (4.0 eV) that were previously inaccessible. Other lanthanide oxides (Dy, Ho and Yb) used as capping layers show similar effects. It is also shown that tuning of φM,eff can be realized by controlling the extent of lanthanide-silicate formation. This research, conducted in conjunction with SEMATECH and the SRC, represents a significant technological advancement in realizing 45 and sub-45 nm MOSFET device nodes.

SiO2/AlON stacked gate dielectrics for AlGaN/GaN MOS heterojunction field-effect transistors

NASA Astrophysics Data System (ADS)

Watanabe, Kenta; Terashima, Daiki; Nozaki, Mikito; Yamada, Takahiro; Nakazawa, Satoshi; Ishida, Masahiro; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

Stacked gate dielectrics consisting of wide bandgap SiO2 insulators and thin aluminum oxynitride (AlON) interlayers were systematically investigated in order to improve the performance and reliability of AlGaN/GaN metal–oxide–semiconductor (MOS) devices. A significantly reduced gate leakage current compared with that in a single AlON layer was achieved with these structures, while maintaining the superior thermal stability and electrical properties of the oxynitride/AlGaN interface. Consequently, distinct advantages in terms of the reliability of the gate dielectrics, such as an improved immunity against electron injection and an increased dielectric breakdown field, were demonstrated for AlGaN/GaN MOS capacitors with optimized stacked structures having a 3.3-nm-thick AlON interlayer.

An improved large signal model of InP HEMTs

NASA Astrophysics Data System (ADS)

Li, Tianhao; Li, Wenjun; Liu, Jun

2018-05-01

An improved large signal model for InP HEMTs is proposed in this paper. The channel current and charge model equations are constructed based on the Angelov model equations. Both the equations for channel current and gate charge models were all continuous and high order drivable, and the proposed gate charge model satisfied the charge conservation. For the strong leakage induced barrier reduction effect of InP HEMTs, the Angelov current model equations are improved. The channel current model could fit DC performance of devices. A 2 × 25 μm × 70 nm InP HEMT device is used to demonstrate the extraction and validation of the model, in which the model has predicted the DC I–V, C–V and bias related S parameters accurately. Project supported by the National Natural Science Foundation of China (No. 61331006).

Self-Aligned ALD AlOx T-gate Insulator for Gate Leakage Current Suppression in SiNx-Passivated AlGaN/GaN HEMTs

DTIC Science & Technology

2010-01-01

Heterostructure epitaxial material growth was performed by RF plasma-assisted molecular - beam epitaxy (MBE) on a 2-in. semi- insulating 4H SiC wafer. From... beam epitaxy of beryllium-doped GaN buffer layers for AlGaN/GaN HEMTs . J Cryst Growth 2003;251:481–6. [25] Storm DF, Katzer DS, Binari SC, Glaser ER...Shanabrook BV, Roussos JA. Reduction of buffer layer conduction near plasma-assisted molecular - beam epitaxy grown GaN/AlN interfaces by beryllium

Nano-scale zirconia and hafnia dielectrics grown by atomic layer deposition: Crystallinity, interface structures and electrical properties

NASA Astrophysics Data System (ADS)

Kim, Hyoungsub

With the continued scaling of transistors, leakage current densities across the SiO2 gate dielectric have increased enormously through direct tunneling. Presently, metal oxides having higher dielectric constants than SiO2 are being investigated to reduce the leakage current by increasing the physical thickness of the dielectric. Many possible techniques exist for depositing high-kappa gate dielectrics. Atomic layer deposition (ALD) has drawn attention as a method for preparing ultrathin metal oxide layers with excellent electrical characteristics and near-perfect film conformality due to the layer-by-layer nature of the deposition mechanism. For this research, an ALD system using ZrCl4/HfCl4 and H2O was built and optimized. The microstructural and electrical properties of ALD-ZrO2 and HfO2 grown on SiO2/Si substrates were investigated and compared using various characterization tools. In particular, the crystallization kinetics of amorphous ALD-HfO2 films were studied using in-situ annealing experiments in a TEM. The effect of crystallization on the electrical properties of ALD-HfO 2 was also investigated using various in-situ and ex-situ post-deposition anneals. Our results revealed that crystallization had little effect on the magnitude of the gate leakage current or on the conduction mechanisms. Building upon the results for each metal oxide separately, more advanced investigations were made. Several nanolaminate structures using ZrO2 and HfO2 with different sequences and layer thicknesses were characterized. The effects of the starting microstructure on the microstructural evolution of nanolaminate stacks were studied. Additionally, a promising new approach for engineering the thickness of the SiO2-based interface layer between the metal oxide and silicon substrate after deposition of the metal oxide layer was suggested. Through experimental measurements and thermodynamic analysis, it is shown that a Ti overlayer, which exhibits a high oxygen solubility, can effectively getter oxygen from the interface layer, thus decomposing SiO2 and reducing the interface layer thickness in a controllable fashion. As one of several possible applications, ALD-ZrO2 and HfO 2 gate dielectric films were deposited on Ge (001) substrates with different surface passivations. After extensive characterization using various microstructural, electrical, and chemical analyses, excellent MOS electrical properties of high-kappa gate dielectrics on Ge were successfully demonstrated with optimized surface nitridation of the Ge substrates.

Single-Walled Carbon Nanotube Dominated Micron-Wide Stripe Patterned-Based Ferroelectric Field-Effect Transistors with HfO2 Defect Control Layer

NASA Astrophysics Data System (ADS)

Tan, Qiuhong; Wang, Qianjin; Liu, Yingkai; Yan, Hailong; Cai, Wude; Yang, Zhikun

2018-04-01

Ferroelectric field-effect transistors (FeFETs) with single-walled carbon nanotube (SWCNT) dominated micron-wide stripe patterned as channel, (Bi,Nd)4Ti3O12 films as insulator, and HfO2 films as defect control layer were developed and fabricated. The prepared SWCNT-FeFETs possess excellent properties such as large channel conductance, high on/off current ratio, high channel carrier mobility, great fatigue endurance performance, and data retention. Despite its thin capacitance equivalent thickness, the gate insulator with HfO2 defect control layer shows a low leakage current density of 3.1 × 10-9 A/cm2 at a gate voltage of - 3 V.

Single-Walled Carbon Nanotube Dominated Micron-Wide Stripe Patterned-Based Ferroelectric Field-Effect Transistors with HfO2 Defect Control Layer.

PubMed

Tan, Qiuhong; Wang, Qianjin; Liu, Yingkai; Yan, Hailong; Cai, Wude; Yang, Zhikun

2018-04-27

Ferroelectric field-effect transistors (FeFETs) with single-walled carbon nanotube (SWCNT) dominated micron-wide stripe patterned as channel, (Bi,Nd) 4 Ti 3 O 12 films as insulator, and HfO 2 films as defect control layer were developed and fabricated. The prepared SWCNT-FeFETs possess excellent properties such as large channel conductance, high on/off current ratio, high channel carrier mobility, great fatigue endurance performance, and data retention. Despite its thin capacitance equivalent thickness, the gate insulator with HfO 2 defect control layer shows a low leakage current density of 3.1 × 10 -9  A/cm 2 at a gate voltage of - 3 V.

Static Noise Margin Enhancement by Flex-Pass-Gate SRAM

NASA Astrophysics Data System (ADS)

O'Uchi, Shin-Ichi; Masahara, Meishoku; Sakamoto, Kunihiro; Endo, Kazuhiko; Liu, Yungxun; Matsukawa, Takashi; Sekigawa, Toshihiro; Koike, Hanpei; Suzuki, Eiichi

A Flex-Pass-Gate SRAM, i.e. a fin-type-field-effect-transistor- (FinFET-) based SRAM, is proposed to enhance noise margin during both read and write operations. In its cell, the flip-flop is composed of usual three-terminal- (3T-) FinFETs while pass gates are composed of four-terminal- (4T-) FinFETs. The 4T-FinFETs enable to adopt a dynamic threshold-voltage control in the pass gates. During a write operation, the threshold voltage of the pass gates is lowered to enhance the writing speed and stability. During the read operation, on the other hand, the threshold voltage is raised to enhance the static noise margin. An asymmetric-oxide 4T-FinFET is helpful to manage the leakage current through the pass gate. In this paper, a design strategy of the pass gate with an asymmetric gate oxide is considered, and a TCAD-based Monte Carlo simulation reveals that the Flex-Pass-Gate SRAM based on that design strategy is expected to be effective in half-pitch 32-nm technology for low-standby-power (LSTP) applications, even taking into account the variability in the device performance.

Noise Reduction Techniques and Scaling Effects towards Photon Counting CMOS Image Sensors

PubMed Central

Boukhayma, Assim; Peizerat, Arnaud; Enz, Christian

2016-01-01

This paper presents an overview of the read noise in CMOS image sensors (CISs) based on four-transistors (4T) pixels, column-level amplification and correlated multiple sampling. Starting from the input-referred noise analytical formula, process level optimizations, device choices and circuit techniques at the pixel and column level of the readout chain are derived and discussed. The noise reduction techniques that can be implemented at the column and pixel level are verified by transient noise simulations, measurement and results from recently-published low noise CIS. We show how recently-reported process refinement, leading to the reduction of the sense node capacitance, can be combined with an optimal in-pixel source follower design to reach a sub-0.3erms- read noise at room temperature. This paper also discusses the impact of technology scaling on the CIS read noise. It shows how designers can take advantage of scaling and how the Metal-Oxide-Semiconductor (MOS) transistor gate leakage tunneling current appears as a challenging limitation. For this purpose, both simulation results of the gate leakage current and 1/f noise data reported from different foundries and technology nodes are used.

Gate oxide thickness dependence of the leakage current mechanism in Ru/Ta2O5/SiON/Si structures

NASA Astrophysics Data System (ADS)

Ťapajna, M.; Paskaleva, A.; Atanassova, E.; Dobročka, E.; Hušeková, K.; Fröhlich, K.

2010-07-01

Leakage conduction mechanisms in Ru/Ta2O5/SiON/Si structures with rf-sputtered Ta2O5 with thicknesses ranging from 13.5 to 1.8 nm were systematically studied. Notable reaction at the Ru/Ta2O5 interface was revealed by capacitance-voltage measurements. Temperature-dependent current-voltage characteristics suggest the bulk-limited conduction mechanism in all metal-oxide-semiconductor structures. Under gate injection, Poole-Frenkel emission was identified as a dominant mechanism for 13.5 nm thick Ta2O5. With an oxide thickness decreasing down to 3.5 nm, the conduction mechanism transforms to thermionic trap-assisted tunnelling through the triangular barrier. Under substrate injection, the dominant mechanism gradually changes with decreasing thickness from thermionic trap-assisted tunnelling to trap-assisted tunnelling through the triangular barrier; Poole-Frenkel emission was not observed at all. A 0.7 eV deep defect level distributed over Ta2O5 is assumed to be responsible for bulk-limited conduction mechanisms and is attributed to H-related defects or oxygen vacancies in Ta2O5.

Protection of MOS capacitors during anodic bonding

NASA Astrophysics Data System (ADS)

Schjølberg-Henriksen, K.; Plaza, J. A.; Rafí, J. M.; Esteve, J.; Campabadal, F.; Santander, J.; Jensen, G. U.; Hanneborg, A.

2002-07-01

We have investigated the electrical damage by anodic bonding on CMOS-quality gate oxide and methods to prevent this damage. n-type and p-type MOS capacitors were characterized by quasi-static and high-frequency CV-curves before and after anodic bonding. Capacitors that were bonded to a Pyrex wafer with 10 μm deep cavities enclosing the capacitors exhibited increased leakage current and interface trap density after bonding. Two different methods were successful in protecting the capacitors from such damage. Our first approach was to increase the cavity depth from 10 μm to 50 μm, thus reducing the electric field across the gate oxide during bonding from approximately 2 × 105 V cm-1 to 4 × 104 V cm-1. The second protection method was to coat the inside of a 10 μm deep Pyrex glass cavity with aluminium, forming a Faraday cage that removed the electric field across the cavity during anodic bonding. Both methods resulted in capacitors with decreased interface trap density and unchanged leakage current after bonding. No change in effective oxide charge or mobile ion contamination was observed on any of the capacitors in the study.

Device performance of in situ steam generated gate dielectric nitrided by remote plasma nitridation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Al-Shareef, H. N.; Karamcheti, A.; Luo, T. Y.

2001-06-11

In situ steam generated (ISSG) oxides have recently attracted interest for use as gate dielectrics because of their demonstrated reliability improvement over oxides formed by dry oxidation. [G. Minor, G. Xing, H. S. Joo, E. Sanchez, Y. Yokota, C. Chen, D. Lopes, and A. Balakrishna, Electrochem. Soc. Symp. Proc. 99-10, 3 (1999); T. Y. Luo, H. N. Al-Shareef, G. A. Brown, M. Laughery, V. Watt, A. Karamcheti, M. D. Jackson, and H. R. Huff, Proc. SPIE 4181, 220 (2000).] We show in this letter that nitridation of ISSG oxide using a remote plasma decreases the gate leakage current of ISSGmore » oxide by an order of magnitude without significantly degrading transistor performance. In particular, it is shown that the peak normalized transconductance of n-channel devices with an ISSG oxide gate dielectric decreases by only 4% and the normalized drive current by only 3% after remote plasma nitridation (RPN). In addition, it is shown that the reliability of the ISSG oxide exhibits only a small degradation after RPN. These observations suggest that the ISSG/RPN process holds promise for gate dielectric applications. {copyright} 2001 American Institute of Physics.« less

Threshold voltage tuning in AlGaN/GaN HFETs with p-type Cu2O gate synthesized by magnetron reactive sputtering

NASA Astrophysics Data System (ADS)

Wang, Lei; Li, Liuan; Xie, Tian; Wang, Xinzhi; Liu, Xinke; Ao, Jin-Ping

2018-04-01

In present study, copper oxide films were prepared at different sputtering powers (10-100 W) using magnetron reactive sputtering. The crystalline structure, surface morphologies, composition, and optical band gap of the as-grown films are dependent on sputtering power. As the sputtering power decreasing from 100 to 10 W, the composition of films changed from CuO to quasi Cu2O domination. Moreover, when the sputtering power is 10 W, a relative high hole carrier density and high-surface-quality quasi Cu2O thin film can be achieved. AlGaN/GaN HFETs were fabricated with the optimized p-type quasi Cu2O film as gate electrode, the threshold voltage of the device shows a 0.55 V positive shift, meanwhile, a lower gate leakage current, a higher ON/OFF drain current ratio of ∼108, a higher electron mobility (1465 cm2/Vs), and a lower subthreshold slope of 74 mV/dec are also achieved, compared with the typical Ni/Au-gated HFETs. Therefore, Cu2O have a great potential to develop high performance p-type gate AlGaN/GaN HFETs.

Influence of high energy electron irradiation on the characteristics of polysilicon thin film transistors

NASA Astrophysics Data System (ADS)

Aleksandrova, P. V.; Gueorguiev, V. K.; Ivanov, Tz. E.; Kaschieva, S.

2006-08-01

The influence of high energy electron (23 MeV) irradiation on the electrical characteristics of p-channel polysilicon thin film transistors (PSTFTs) was studied. The channel 220 nm thick LPCVD (low pressure chemical vapor deposition) deposited polysilicon layer was phosphorus doped by ion implantation. A 45 nm thick, thermally grown, SiO2 layer served as gate dielectric. A self-alignment technology for boron doping of the source and drain regions was used. 200 nm thick polysilicon film was deposited as a gate electrode. The obtained p-channel PSTFTs were irradiated with different high energy electron doses. Leakage currents through the gate oxide and transfer characteristics of the transistors were measured. A software model describing the field enhancement and the non-uniform current distribution at textured polysilicon/oxide interface was developed. In order to assess the irradiation-stimulated changes of gate oxide parameters the gate oxide tunneling conduction and transistor characteristics were studied. At MeV dose of 6×1013 el/cm2, a negligible degradation of the transistor properties was found. A significant deterioration of the electrical properties of PSTFTs at MeV irradiation dose of 3×1014 el/cm2 was observed.

Combinatorial study of Ni-Ti-Pt ternary metal gate electrodes on HfO{sub 2} for the advanced gate stack

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chang, K.-S.; Green, M. L.; Suehle, J.

2006-10-02

The authors have fabricated combinatorial Ni-Ti-Pt ternary metal gate thin film libraries on HfO{sub 2} using magnetron co-sputtering to investigate flatband voltage shift ({delta}V{sub fb}), work function ({phi}{sub m}), and leakage current density (J{sub L}) variations. A more negative {delta}V{sub fb} is observed close to the Ti-rich corner than at the Ni- and Pt-rich corners, implying smaller {phi}{sub m} near the Ti-rich corners and higher {phi}{sub m} near the Ni- and Pt-rich corners. In addition, measured J{sub L} values can be explained consistently with the observed {phi}{sub m} variations. Combinatorial methodologies prove to be useful in surveying the large compositionalmore » space of ternary alloy metal gate electrode systems.« less

Nanocomposites of polyimide and mixed oxide nanoparticles for high performance nanohybrid gate dielectrics in flexible thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Ju Hyun; Hwang, Byeong-Ung; Kim, Do-Il; Kim, Jin Soo; Seol, Young Gug; Kim, Tae Woong; Lee, Nae-Eung

2017-05-01

Organic gate dielectrics in thin film transistors (TFTs) for flexible display have advantages of high flexibility yet have the disadvantage of low dielectric constant (low- k). To supplement low- k characteristics of organic gate dielectrics, an organic/inorganic nanocomposite insulator loaded with high- k inorganic oxide nanoparticles (NPs) has been investigated but high loading of high- k NPs in polymer matrix is essential. Herein, compositing of over-coated polyimide (PI) on self-assembled (SA) layer of mixed HfO2 and ZrO2 NPs as inorganic fillers was used to make dielectric constant higher and leakage characteristics lower. A flexible TFT with lower the threshold voltage and high current on/off ratio could be fabricated by using the hybrid gate dielectric structure of the nanocomposite with SA layer of mixed NPs on ultrathin atomic-layer deposited Al2O3. [Figure not available: see fulltext.

Investigation and statistical modeling of InAs-based double gate tunnel FETs for RF performance enhancement

NASA Astrophysics Data System (ADS)

Poorvasha, S.; Lakshmi, B.

2018-05-01

In this paper, RF performance analysis of InAs-based double gate (DG) tunnel field effect transistors (TFETs) is investigated in both qualitative and quantitative fashion. This investigation is carried out by varying the geometrical and doping parameters of TFETs to extract various RF parameters, unity gain cut-off frequency (f t), maximum oscillation frequency (f max), intrinsic gain and admittance (Y) parameters. An asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. Higher ON-current (I ON) of about 0.2 mA and less leakage current (I OFF) of 29 fA is achieved for DG TFET with gate-drain overlap. Due to increase in transconductance (g m), higher f t and intrinsic gain is attained for DG TFET with gate-drain overlap. Higher f max of 985 GHz is obtained for drain doping of 5 × 1017 cm‑3 because of the reduced gate-drain capacitance (C gd) with DG TFET with gate-drain overlap. In terms of Y-parameters, gate oxide thickness variation offers better performance due to the reduced values of C gd. A second order numerical polynomial model is generated for all the RF responses as a function of geometrical and doping parameters. The simulation results are compared with this numerical model where the predicted values match with the simulated values. Project supported by the Department of Science and Technology, Government of India under SERB Scheme (No. SERB/F/2660).

Efficient III-Nitride MIS-HEMT devices with high-κ gate dielectric for high-power switching boost converter circuits

NASA Astrophysics Data System (ADS)

Mohanbabu, A.; Mohankumar, N.; Godwin Raj, D.; Sarkar, Partha; Saha, Samar K.

2017-03-01

The paper reports the results of a systematic theoretical study on efficient recessed-gate, double-heterostructure, and normally-OFF metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs), HfAlOx/AlGaN on Al2O3 substrate. In device architecture, a thin AlGaN layer is used in the AlGaN graded barrier MIS-HEMTs that offers an excellent enhancement-mode device operation with threshold voltage higher than 5.3 V and drain current above 0.64 A/mm along with high on-current/off-current ratio over 107 and subthreshold slope less than 73 mV/dec. In addition, a high OFF-state breakdown voltage of 1200 V is achieved for a device with a gate-to-drain distance and field-plate length of 15 μm and 5.3 μm, respectively at a drain current of 1 mA/mm with a zero gate bias, and the substrate grounded. The numerical device simulation results show that in comparison to a conventional AlGaN/GaN MIS-HEMT of similar design, a graded barrier MIS-HEMT device exhibits a better interface property, remarkable suppression of leakage current, and a significant improvement of breakdown voltage for HfAlOx gate dielectric. Finally, the benefit of HfAlOx graded-barrier AlGaN MIS-HEMTs based switching devices is evaluated on an ultra-low-loss converter circuit.

Effects of Energy Relaxation via Quantum Coupling Among Three-Dimensional Motion on the Tunneling Current of Graphene Field-Effect Transistors.

PubMed

Mao, Ling-Feng; Ning, Huansheng; Li, Xijun

2015-12-01

We report theoretical study of the effects of energy relaxation on the tunneling current through the oxide layer of a two-dimensional graphene field-effect transistor. In the channel, when three-dimensional electron thermal motion is considered in the Schrödinger equation, the gate leakage current at a given oxide field largely increases with the channel electric field, electron mobility, and energy relaxation time of electrons. Such an increase can be especially significant when the channel electric field is larger than 1 kV/cm. Numerical calculations show that the relative increment of the tunneling current through the gate oxide will decrease with increasing the thickness of oxide layer when the oxide is a few nanometers thick. This highlights that energy relaxation effect needs to be considered in modeling graphene transistors.

Combining a multi deposition multi annealing technique with a scavenging (Ti) to improve the high-k/metal gate stack performance for a gate-last process

NASA Astrophysics Data System (ADS)

ShuXiang, Zhang; Hong, Yang; Bo, Tang; Zhaoyun, Tang; Yefeng, Xu; Jing, Xu; Jiang, Yan

2014-10-01

ALD HfO2 films fabricated by a novel multi deposition multi annealing (MDMA) technique are investigated, we have included samples both with and without a Ti scavenging layer. As compared to the reference gate stack treated by conventional one-time deposition and annealing (D&A), devices receiving MDMA show a significant reduction in leakage current. Meanwhile, EOT growth is effectively controlled by the Ti scavenging layer. This improvement strongly correlates with the cycle number of D&A (while keeping the total annealing time and total dielectrics thickness the same). Transmission electron microscope and energy-dispersive X-ray spectroscopy analysis suggests that oxygen incorporation into both the high-k film and the interfacial layer is likely to be responsible for the improvement of the device. This novel MDMA is promising for the development of gate stack technology in a gate last integration scheme.

Low-voltage organic strain sensor on plastic using polymer/high- K inorganic hybrid gate dielectrics

NASA Astrophysics Data System (ADS)

Jung, Soyoun; Ji, Taeksoo; Varadan, Vijay K.

2007-12-01

In this paper, gate-induced pentacene semiconductor strain sensors based on hybrid-gate dielectrics using poly-vinylphenol (PVP) and high-K inorganic, Ta IIO 5 are fabricated on flexible substrates, polyethylene naphthalate (PEN). The Ta IIO 5 gate dielectric layer is combined with a thin PVP layer to obtain very smooth and hydrophobic surfaces which improve the molecular structures of pentacene films. The PVP-Ta IIO 5 hybrid-gate dielectric films exhibit a high dielectric capacitance and low leakage current. The sensors adopting thin film transistor (TFT)-like structures show a significantly reduced operating voltage (~6V), and good device characteristics with a field-effect mobility of 1.89 cm2/V•s, a threshold voltage of -0.5 V, and an on/off ratio of 10 3. The strain sensor, one of the practical applications in large-area organic electronics, was characterized with different bending radii of 50, 40, 30, and 20 mm. The sensor output signals were significantly improved with low-operating voltages.

Ultralow-power organic complementary circuits.

PubMed

Klauk, Hagen; Zschieschang, Ute; Pflaum, Jens; Halik, Marcus

2007-02-15

The prospect of using low-temperature processable organic semiconductors to implement transistors, circuits, displays and sensors on arbitrary substrates, such as glass or plastics, offers enormous potential for a wide range of electronic products. Of particular interest are portable devices that can be powered by small batteries or by near-field radio-frequency coupling. The main problem with existing approaches is the large power consumption of conventional organic circuits, which makes battery-powered applications problematic, if not impossible. Here we demonstrate an organic circuit with very low power consumption that uses a self-assembled monolayer gate dielectric and two different air-stable molecular semiconductors (pentacene and hexadecafluorocopperphthalocyanine, F16CuPc). The monolayer dielectric is grown on patterned metal gates at room temperature and is optimized to provide a large gate capacitance and low gate leakage currents. By combining low-voltage p-channel and n-channel organic thin-film transistors in a complementary circuit design, the static currents are reduced to below 100 pA per logic gate. We have fabricated complementary inverters, NAND gates, and ring oscillators that operate with supply voltages between 1.5 and 3 V and have a static power consumption of less than 1 nW per logic gate. These organic circuits are thus well suited for battery-powered systems such as portable display devices and large-surface sensor networks as well as for radio-frequency identification tags with extended operating range.

Radiation Effects On Emerging Electronic Materials And Devices

DTIC Science & Technology

2010-01-17

RADIATION EFFECTS ON EMERGING ELECTRONIC MATERIALS AND DEVICES FINAL PERFORMANCE REPORT PREPARED FOR: Kitt Reinhardt AFOSR/NE 875 N...and the other with metal gates and a high-K gate dielectric. These devices were programmed using both back-gate pulse and gate induced drain leakage... metal gate process GIDL method Fig. 1. Sensing margin as a function of total ionizing dose for nMOS 1T-DRAM cells programmed by back-gate pulse and

Burner ignition system

DOEpatents

Carignan, Forest J.

1986-01-21

An electronic ignition system for a gas burner is battery operated. The battery voltage is applied through a DC-DC chopper to a step-up transformer to charge a capacitor which provides the ignition spark. The step-up transformer has a significant leakage reactance in order to limit current flow from the battery during initial charging of the capacitor. A tank circuit at the input of the transformer returns magnetizing current resulting from the leakage reactance to the primary in succeeding cycles. An SCR in the output circuit is gated through a voltage divider which senses current flow through a flame. Once the flame is sensed, further sparks are precluded. The same flame sensor enables a thermopile driven main valve actuating circuit. A safety valve in series with the main gas valve responds to a control pressure thermostatically applied through a diaphragm. The valve closes after a predetermined delay determined by a time delay orifice if the pilot gas is not ignited.

Progressive failure site generation in AlGaN/GaN high electron mobility transistors under OFF-state stress: Weibull statistics and temperature dependence

NASA Astrophysics Data System (ADS)

Sun, Huarui; Bajo, Miguel Montes; Uren, Michael J.; Kuball, Martin

2015-01-01

Gate leakage degradation of AlGaN/GaN high electron mobility transistors under OFF-state stress is investigated using a combination of electrical, optical, and surface morphology characterizations. The generation of leakage "hot spots" at the edge of the gate is found to be strongly temperature accelerated. The time for the formation of each failure site follows a Weibull distribution with a shape parameter in the range of 0.7-0.9 from room temperature up to 120 °C. The average leakage per failure site is only weakly temperature dependent. The stress-induced structural degradation at the leakage sites exhibits a temperature dependence in the surface morphology, which is consistent with a surface defect generation process involving temperature-associated changes in the breakdown sites.

Role of Oxygen in Ionic Liquid Gating on Two-Dimensional Cr2Ge2Te6: A Non-oxide Material.

PubMed

Chen, Yangyang; Xing, Wenyu; Wang, Xirui; Shen, Bowen; Yuan, Wei; Su, Tang; Ma, Yang; Yao, Yunyan; Zhong, Jiangnan; Yun, Yu; Xie, X C; Jia, Shuang; Han, Wei

2018-01-10

Ionic liquid gating can markedly modulate a material's carrier density so as to induce metallization, superconductivity, and quantum phase transitions. One of the main issues is whether the mechanism of ionic liquid gating is an electrostatic field effect or an electrochemical effect, especially for oxide materials. Recent observation of the suppression of the ionic liquid gate-induced metallization in the presence of oxygen for oxide materials suggests the electrochemical effect. However, in more general scenarios, the role of oxygen in the ionic liquid gating effect is still unclear. Here, we perform ionic liquid gating experiments on a non-oxide material: two-dimensional ferromagnetic Cr 2 Ge 2 Te 6 . Our results demonstrate that despite the large increase of the gate leakage current in the presence of oxygen, the oxygen does not affect the ionic liquid gating effect on  the channel resistance of Cr 2 Ge 2 Te 6 devices (<5% difference), which suggests the electrostatic field effect as the mechanism on non-oxide materials. Moreover, our results show that ionic liquid gating is more effective on the modulation of the channel resistances compared to the back gating across the 300 nm thick SiO 2 .

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1980-01-01

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Utilizing self-assembled-monolayer-based gate dielectrics to fabricate molybdenum disulfide field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kawanago, Takamasa, E-mail: kawanago.t.ab@m.titech.ac.jp; Oda, Shunri

In this study, we apply self-assembled-monolayer (SAM)-based gate dielectrics to the fabrication of molybdenum disulfide (MoS{sub 2}) field-effect transistors. A simple fabrication process involving the selective formation of a SAM on metal oxides in conjunction with the dry transfer of MoS{sub 2} flakes was established. A subthreshold slope (SS) of 69 mV/dec and no hysteresis were demonstrated with the ultrathin SAM-based gate dielectrics accompanied by a low gate leakage current. The small SS and no hysteresis indicate the superior interfacial properties of the MoS{sub 2}/SAM structure. Cross-sectional transmission electron microscopy revealed a sharp and abrupt interface of the MoS{sub 2}/SAM structure.more » The SAM-based gate dielectrics are found to be applicable to the fabrication of low-voltage MoS{sub 2} field-effect transistors and can also be extended to various layered semiconductor materials. This study opens up intriguing possibilities of SAM-based gate dielectrics in functional electronic devices.« less

Comparison between the effects of positive noncatastrophic HMB ESD stress in n-channel and p-channel power MOSFET's

NASA Astrophysics Data System (ADS)

Zupac, Dragan; Kosier, Steven L.; Schrimpf, Ronald D.; Galloway, Kenneth F.; Baum, Keith W.

1991-10-01

The effect of noncatastrophic positive human body model (HBM) electrostatic discharge (ESD) stress on n-channel power MOSFETs is radically different from that on p-channel MOSFETs. In n-channel transistors, the stress causes negative shifts of the current-voltage characteristics indicative of positive charge trapping in the gate oxide. In p-channel transistors, the stress increases the drain-to-source leakage current, probably due to localized avalanche electron injection from the p-doped drain.

A III-V nanowire channel on silicon for high-performance vertical transistors.

PubMed

Tomioka, Katsuhiro; Yoshimura, Masatoshi; Fukui, Takashi

2012-08-09

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

Progressive failure site generation in AlGaN/GaN high electron mobility transistors under OFF-state stress: Weibull statistics and temperature dependence

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sun, Huarui, E-mail: huarui.sun@bristol.ac.uk; Bajo, Miguel Montes; Uren, Michael J.

2015-01-26

Gate leakage degradation of AlGaN/GaN high electron mobility transistors under OFF-state stress is investigated using a combination of electrical, optical, and surface morphology characterizations. The generation of leakage “hot spots” at the edge of the gate is found to be strongly temperature accelerated. The time for the formation of each failure site follows a Weibull distribution with a shape parameter in the range of 0.7–0.9 from room temperature up to 120 °C. The average leakage per failure site is only weakly temperature dependent. The stress-induced structural degradation at the leakage sites exhibits a temperature dependence in the surface morphology, which ismore » consistent with a surface defect generation process involving temperature-associated changes in the breakdown sites.« less

Transferred wrinkled Al2O3 for highly stretchable and transparent graphene-carbon nanotube transistors

NASA Astrophysics Data System (ADS)

Chae, Sang Hoon; Yu, Woo Jong; Bae, Jung Jun; Duong, Dinh Loc; Perello, David; Jeong, Hye Yun; Ta, Quang Huy; Ly, Thuc Hue; Vu, Quoc An; Yun, Minhee; Duan, Xiangfeng; Lee, Young Hee

2013-05-01

Despite recent progress in producing transparent and bendable thin-film transistors using graphene and carbon nanotubes, the development of stretchable devices remains limited either by fragile inorganic oxides or polymer dielectrics with high leakage current. Here we report the fabrication of highly stretchable and transparent field-effect transistors combining graphene/single-walled carbon nanotube (SWCNT) electrodes and a SWCNT-network channel with a geometrically wrinkled inorganic dielectric layer. The wrinkled Al2O3 layer contained effective built-in air gaps with a small gate leakage current of 10-13 A. The resulting devices exhibited an excellent on/off ratio of ~105, a high mobility of ~40 cm2 V-1 s-1 and a low operating voltage of less than 1 V. Importantly, because of the wrinkled dielectric layer, the transistors retained performance under strains as high as 20% without appreciable leakage current increases or physical degradation. No significant performance loss was observed after stretching and releasing the devices for over 1,000 times. The sustainability and performance advances demonstrated here are promising for the adoption of stretchable electronics in a wide variety of future applications.

Nanoindentation investigation of HfO2 and Al2O3 films grown by atomic layer deposition

Treesearch

K. Tapily; Joseph E. Jakes; D. S. Stone; P. Shrestha; D. Gu; H. Baumgart; A. A. Elmustafa

2008-01-01

The challenges of reducing gate leakage current and dielectric breakdown beyond the 45 nm technology node have shifted engineers’ attention from the traditional and proven dielectric SiO2 to materials of higher dielectric constant also known as high-k materials such as hafnium oxide (HfO2) and aluminum oxide (Al2O3). These high-k materials are projected to...

Investigating compositional effects of atomic layer deposition ternary dielectric Ti-Al-O on metal-insulator-semiconductor heterojunction capacitor structure for gate insulation of InAlN/GaN and AlGaN/GaN

DOE Office of Scientific and Technical Information (OSTI.GOV)

Colon, Albert; Stan, Liliana; Divan, Ralu

Gate insulation/surface passivation in AlGaN/GaN and InAlN/GaN heterojunction field-effect transistors is a major concern for passivation of surface traps and reduction of gate leakage current. However, finding the most appropriate gate dielectric materials is challenging and often involves a compromise of the required properties such as dielectric constant, conduction/valence band-offsets, or thermal stability. Creating a ternary compound such as Ti-Al-O and tailoring its composition may result in a reasonably good gate material in terms of the said properties. To date, there is limited knowledge of the performance of ternary dielectric compounds on AlGaN/GaN and even less on InAlN/GaN. To approachmore » this problem, the authors fabricated metal-insulator-semiconductor heterojunction (MISH) capacitors with ternary dielectrics Ti-Al-O of various compositions, deposited by atomic layer deposition (ALD). The film deposition was achieved by alternating cycles of TiO2 and Al2O3 using different ratios of ALD cycles. TiO2 was also deposited as a reference sample. The electrical characterization of the MISH capacitors shows an overall better performance of ternary compounds compared to the pure TiO2. The gate leakage current density decreases with increasing Al content, being similar to 2-3 orders of magnitude lower for a TiO2:Al2O3 cycle ratio of 2:1. Although the dielectric constant has the highest value of 79 for TiO2 and decreases with increasing the number of Al2O3 cycles, it is maintaining a relatively high value compared to an Al2O3 film. Capacitance voltage sweeps were also measured in order to characterize the interface trap density. A decreasing trend in the interface trap density was found while increasing Al content in the film. In conclusion, our study reveals that the desired high-kappa properties of TiO2 can be adequately maintained while improving other insulator performance factors. The ternary compounds may be an excellent choice as a gate material for both AlGaN/GaN and InAlN/GaN based devices.« less

High Temperature Operation of Al 0.45Ga 0.55N/Al 0.30Ga 0.70 N High Electron Mobility Transistors

DOE PAGES

Baca, Albert G.; Armstrong, Andrew M.; Allerman, Andrew A.; ...

2017-08-01

AlGaN-channel high electron mobility transistors (HEMTs) are among a class of ultra wide-bandgap transistors that have a bandgap greater than ~3.4 eV, beyond that of GaN and SiC, and are promising candidates for RF and power applications. Long-channel Al xGa 1-xN HEMTs with x = 0.3 in the channel have been built and evaluated across the -50°C to +200°C temperature range. Room temperature drain current of 70 mA/mm, absent of gate leakage, and with a modest -1.3 V threshold voltage was measured. A very large I on/I off current ratio, greater than 10 8 was demonstrated over the entire temperaturemore » range, indicating that off-state leakage is below the measurement limit even at 200°C. Finally, combined with near ideal subthreshold slope factor that is just 1.3× higher than the theoretical limit across the temperature range, the excellent leakage properties are an attractive characteristic for high temperature operation.« less

High Temperature Operation of Al 0.45Ga 0.55N/Al 0.30Ga 0.70 N High Electron Mobility Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baca, Albert G.; Armstrong, Andrew M.; Allerman, Andrew A.

AlGaN-channel high electron mobility transistors (HEMTs) are among a class of ultra wide-bandgap transistors that have a bandgap greater than ~3.4 eV, beyond that of GaN and SiC, and are promising candidates for RF and power applications. Long-channel Al xGa 1-xN HEMTs with x = 0.3 in the channel have been built and evaluated across the -50°C to +200°C temperature range. Room temperature drain current of 70 mA/mm, absent of gate leakage, and with a modest -1.3 V threshold voltage was measured. A very large I on/I off current ratio, greater than 10 8 was demonstrated over the entire temperaturemore » range, indicating that off-state leakage is below the measurement limit even at 200°C. Finally, combined with near ideal subthreshold slope factor that is just 1.3× higher than the theoretical limit across the temperature range, the excellent leakage properties are an attractive characteristic for high temperature operation.« less

Electrical Properties and Interfacial Studies of HfxTi1–xO2 High Permittivity Gate Insulators Deposited on Germanium Substrates

PubMed Central

Lu, Qifeng; Mu, Yifei; Roberts, Joseph W.; Althobaiti, Mohammed; Dhanak, Vinod R.; Wu, Jingjin; Zhao, Chun; Zhao, Ce Zhou; Zhang, Qian; Yang, Li; Mitrovic, Ivona Z.; Taylor, Stephen; Chalker, Paul R.

2015-01-01

In this research, the hafnium titanate oxide thin films, TixHf1–xO2, with titanium contents of x = 0, 0.25, 0.9, and 1 were deposited on germanium substrates by atomic layer deposition (ALD) at 300 °C. The approximate deposition rates of 0.2 Å and 0.17 Å per cycle were obtained for titanium oxide and hafnium oxide, respectively. X-ray Photoelectron Spectroscopy (XPS) indicates the formation of GeOx and germanate at the interface. X-ray diffraction (XRD) indicates that all the thin films remain amorphous for this deposition condition. The surface roughness was analyzed using an atomic force microscope (AFM) for each sample. The electrical characterization shows very low hysteresis between ramp up and ramp down of the Capacitance-Voltage (CV) and the curves are indicative of low trap densities. A relatively large leakage current is observed and the lowest leakage current among the four samples is about 1 mA/cm2 at a bias of 0.5 V for a Ti0.9Hf0.1O2 sample. The large leakage current is partially attributed to the deterioration of the interface between Ge and TixHf1–xO2 caused by the oxidation source from HfO2. Consideration of the energy band diagrams for the different materials systems also provides a possible explanation for the observed leakage current behavior. PMID:28793705

Plasma-assisted ohmic contact for AlGaN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Zhang, Jiaqi; Wang, Lei; Wang, Qingpeng; Jiang, Ying; Li, Liuan; Zhu, Huichao; Ao, Jin-Ping

2016-03-01

An Al-based ohmic process assisted by an inductively coupled plasma (ICP) recess treatment is proposed for AlGaN/GaN heterostructure field-effect transistors (HFETs) to realize ohmic contact, which is only needed to anneal at 500 °C. The recess treatment was done with SiCl4 plasma with 100 W ICP power for 20 s and annealing at 575 °C for 1 min. Under these conditions, contact resistance of 0.52 Ωmm was confirmed. To suppress the ball-up phenomenon and improve the surface morphology, an Al/TiN structure was also fabricated with the same conditions. The contact resistance was further improved to 0.30 Ωmm. By using this plasma-assisted ohmic process, a gate-first HFET was fabricated. The device showed high drain current density and high transconductance. The leakage current of the TiN-gate device decreased to 10-9 A, which was 5 orders of magnitude lower than that of the device annealed at 800 °C. The results showed that the low-temperature ohmic contact process assisted by ICP treatment is promising for the fabrication of gate-first and self-aligned gate HFETs.

Surface modification of polyimide gate insulators for solution-processed 2,7-didecyl[1]benzothieno[3,2-b][1]benzothiophene (C10-BTBT) thin-film transistors.

PubMed

Jang, Kwang-Suk; Kim, Won Soo; Won, Jong-Myung; Kim, Yun-Ho; Myung, Sung; Ka, Jae-Won; Kim, Jinsoo; Ahn, Taek; Yi, Mi Hye

2013-01-21

The surface property of a polyimide gate insulator was successfully modified with an n-octadecyl side-chain. Alkyl chain-grafted poly(amic acid), the polyimide precursor, was synthesized using the diamine comonomer with an alkyl side-chain. By adding a base catalyst to the poly(amic acid) coating solution, the imidization temperature of the spin-coated film could be reduced to 200 °C. The 350 nm-thick polyimide film had a dielectric constant of 3.3 at 10 kHz and a leakage current density of less than 8.7 × 10(-10) A cm(-2), while biased from 0 to 100 V. To investigate the potential of the alkyl chain-grafted polyimide film as a gate insulator for solution-processed organic thin-film transistors (TFTs), we fabricated C(10)-BTBT TFTs. C(10)-BTBT was deposited on the alkyl chain-grafted polyimide gate insulator by spin-coating, forming a well-ordered crystal structure. The field-effect mobility and the on/off current ratio of the TFT device were measured to be 0.20-0.56 cm(2) V(-1) s(-1) and >10(5), respectively.

1T1R Nonvolatile Memory with Al/TiO₂/Au and Sol-Gel-Processed Insulator for Barium Zirconate Nickelate Gate in Pentacene Thin Film Transistor.

PubMed

Lee, Ke-Jing; Chang, Yu-Chi; Lee, Cheng-Jung; Wang, Li-Wen; Wang, Yeong-Her

2017-12-09

A one-transistor and one-resistor (1T1R) architecture with a resistive random access memory (RRAM) cell connected to an organic thin-film transistor (OTFT) device is successfully demonstrated to avoid the cross-talk issues of only one RRAM cell. The OTFT device, which uses barium zirconate nickelate (BZN) as a dielectric layer, exhibits favorable electrical properties, such as a high field-effect mobility of 5 cm²/Vs, low threshold voltage of -1.1 V, and low leakage current of 10 -12 A, for a driver in the 1T1R operation scheme. The 1T1R architecture with a TiO₂-based RRAM cell connected with a BZN OTFT device indicates a low operation current (10 μA) and reliable data retention (over ten years). This favorable performance of the 1T1R device can be attributed to the additional barrier heights introduced by using Ni (II) acetylacetone as a substitute for acetylacetone, and the relatively low leakage current of a BZN dielectric layer. The proposed 1T1R device with low leakage current OTFT and excellent uniform resistance distribution of RRAM exhibits a good potential for use in practical low-power electronic applications.

Electrical properties of solution processed highly transparent ZnO TFT with organic gate dielectric

NASA Astrophysics Data System (ADS)

Pandya, Nirav C.; Joshi, Nikhil G.; Trivedi, U. N.; Joshi, U. S.

2013-02-01

All oxide thin film transistors (TFT) with zinc oxide active layer were fabricated by chemical solution deposition (CSD) using aqueous solutions on glass substrate. Thin film transistors (TFTs) with amorphous zinc oxide as channel layers and poly-vinyl alcohol as dielectric layers were fabricated at low temperatures by chemical solution deposition (CSD). Atomic force microscopy (AFM) confirmed nano grain size with fairly smooth surface topography. Very small leakage currents were achieved in the transfer curves, while soft saturation was observed in the output current voltage (I-V) characteristics of the device. Optical transmission of better than 87% in the visible region was estimated, which is better than the organic gate insulator based ZnO TFTs reported so far. Our results offer lot of promise to TFT based display and optoelectronics.

Scalable quantum computing based on stationary spin qubits in coupled quantum dots inside double-sided optical microcavities

NASA Astrophysics Data System (ADS)

Wei, Hai-Rui; Deng, Fu-Guo

2014-12-01

Quantum logic gates are the key elements in quantum computing. Here we investigate the possibility of achieving a scalable and compact quantum computing based on stationary electron-spin qubits, by using the giant optical circular birefringence induced by quantum-dot spins in double-sided optical microcavities as a result of cavity quantum electrodynamics. We design the compact quantum circuits for implementing universal and deterministic quantum gates for electron-spin systems, including the two-qubit CNOT gate and the three-qubit Toffoli gate. They are compact and economic, and they do not require additional electron-spin qubits. Moreover, our devices have good scalability and are attractive as they both are based on solid-state quantum systems and the qubits are stationary. They are feasible with the current experimental technology, and both high fidelity and high efficiency can be achieved when the ratio of the side leakage to the cavity decay is low.

Scalable quantum computing based on stationary spin qubits in coupled quantum dots inside double-sided optical microcavities.

PubMed

Wei, Hai-Rui; Deng, Fu-Guo

2014-12-18

Quantum logic gates are the key elements in quantum computing. Here we investigate the possibility of achieving a scalable and compact quantum computing based on stationary electron-spin qubits, by using the giant optical circular birefringence induced by quantum-dot spins in double-sided optical microcavities as a result of cavity quantum electrodynamics. We design the compact quantum circuits for implementing universal and deterministic quantum gates for electron-spin systems, including the two-qubit CNOT gate and the three-qubit Toffoli gate. They are compact and economic, and they do not require additional electron-spin qubits. Moreover, our devices have good scalability and are attractive as they both are based on solid-state quantum systems and the qubits are stationary. They are feasible with the current experimental technology, and both high fidelity and high efficiency can be achieved when the ratio of the side leakage to the cavity decay is low.

A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered Zr x Si1- x O2 Gate dielectric and improved electrical and hysteresis performance

NASA Astrophysics Data System (ADS)

Hung, Chien-Hsiung; Wang, Shui-Jinn; Liu, Pang-Yi; Wu, Chien-Hung; Wu, Nai-Sheng; Yan, Hao-Ping; Lin, Tseng-Hsing

2017-04-01

The use of co-sputtered zirconium silicon oxide (Zr x Si1- x O2) gate dielectrics to improve the gate controllability of amorphous indium gallium zinc oxide (α-IGZO) thin-film transistors (TFTs) through a room-temperature fabrication process is proposed and demonstrated. With the sputtering power of the SiO2 target in the range of 0-150 W and with that of the ZrO2 target kept at 100 W, a dielectric constant ranging from approximately 28.1 to 7.8 is obtained. The poly-structure formation immunity of the Zr x Si1- x O2 dielectrics, reduction of the interface trap density suppression, and gate leakage current are examined. Our experimental results reveal that the Zr0.85Si0.15O2 gate dielectric can lead to significantly improved TFT subthreshold swing performance (103 mV/dec) and field effect mobility (33.76 cm2 V-1 s-1).

Ultra-low noise high electron mobility transistors for high-impedance and low-frequency deep cryogenic readout electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dong, Q.; Liang, Y. X.; Ferry, D.

2014-07-07

We report on the results obtained from specially designed high electron mobility transistors at 4.2 K: the gate leakage current can be limited lower than 1 aA, and the equivalent input noise-voltage and noise-current at 1 Hz can reach 6.3 nV/Hz{sup 1∕2} and 20 aA/Hz{sup 1∕2}, respectively. These results open the way to realize high performance low-frequency readout electronics under very low-temperature conditions.

Low-frequency noise in AlN/AlGaN/GaN metal-insulator-semiconductor devices: A comparison with Schottky devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Le, Son Phuong; Nguyen, Tuan Quy; Shih, Hong-An

2014-08-07

We have systematically investigated low-frequency noise (LFN) in AlN/AlGaN/GaN metal-insulator-semiconductor (MIS) devices, where the AlN gate insulator layer was sputtering-deposited on the AlGaN surface, in comparison with LFN in AlGaN/GaN Schottky devices. By measuring LFN in ungated two-terminal devices and heterojunction field-effect transistors (HFETs), we extracted LFN characteristics in the intrinsic gated region of the HFETs. Although there is a bias regime of the Schottky-HFETs in which LFN is dominated by the gate leakage current, LFN in the MIS-HFETs is always dominated by only the channel current. Analyzing the channel-current-dominated LFN, we obtained Hooge parameters α for the gated regionmore » as a function of the sheet electron concentration n{sub s} under the gate. In a regime of small n{sub s}, both the MIS- and Schottky-HFETs exhibit α∝n{sub s}{sup −1}. On the other hand, in a middle n{sub s} regime of the MIS-HFETs, α decreases rapidly like n{sub s}{sup −ξ} with ξ ∼ 2-3, which is not observed for the Schottky-HFETs. In addition, we observe strong increase in α∝n{sub s}{sup 3} in a large n{sub s} regime for both the MIS- and Schottky-HFETs.« less

Low voltage operation of IGZO thin film transistors enabled by ultrathin Al2O3 gate dielectric

NASA Astrophysics Data System (ADS)

Ma, Pengfei; Du, Lulu; Wang, Yiming; Jiang, Ran; Xin, Qian; Li, Yuxiang; Song, Aimin

2018-01-01

An ultrathin, 5 nm, Al2O3 film grown by atomic-layer deposition was used as a gate dielectric for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The Al2O3 layer showed a low surface roughness of 0.15 nm, a low leakage current, and a high breakdown voltage of 6 V. In particular, a very high gate capacitance of 720 nF/cm2 was achieved, making it possible for the a-IGZO TFTs to not only operate at a low voltage of 1 V but also exhibit desirable properties including a low threshold voltage of 0.3 V, a small subthreshold swing of 100 mV/decade, and a high on/off current ratio of 1.2 × 107. Furthermore, even under an ultralow operation voltage of 0.6 V, well-behaved transistor characteristics were still observed with an on/off ratio as high as 3 × 106. The electron transport through the Al2O3 layer has also been analyzed, indicating the Fowler-Nordheim tunneling mechanism.

Way-Scaling to Reduce Power of Cache with Delay Variation

NASA Astrophysics Data System (ADS)

Goudarzi, Maziar; Matsumura, Tadayuki; Ishihara, Tohru

The share of leakage in cache power consumption increases with technology scaling. Choosing a higher threshold voltage (Vth) and/or gate-oxide thickness (Tox) for cache transistors improves leakage, but impacts cell delay. We show that due to uncorrelated random within-die delay variation, only some (not all) of cells actually violate the cache delay after the above change. We propose to add a spare cache way to replace delay-violating cache-lines separately in each cache-set. By SPICE and gate-level simulations in a commercial 90nm process, we show that choosing higher Vth, Tox and adding one spare way to a 4-way 16KB cache reduces leakage power by 42%, which depending on the share of leakage in total cache power, gives up to 22.59% and 41.37% reduction of total energy respectively in L1 instruction- and L2 unified-cache with a negligible delay penalty, but without sacrificing cache capacity or timing-yield.

An AlN/Al 0.85Ga 0.15N high electron mobility transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baca, Albert G.; Armstrong, Andrew M.; Allerman, Andrew A.

2016-07-22

An AlN barrier high electron mobility transistor (HEMT) based on the AlN/Al 0.85Ga 0.15N heterostructure was grown, fabricated, and electrically characterized, thereby extending the range of Al composition and bandgap for AlGaN channel HEMTs. An etch and regrowth procedure was implemented for source and drain contact formation. A breakdown voltage of 810 V was achieved without a gate insulator or field plate. Excellent gate leakage characteristics enabled a high I on/I off current ratio greater than 10 7 and an excellent subthreshold slope of 75 mV/decade. A large Schottky barrier height of 1.74 eV contributed to these results. In conclusion,more » the room temperature voltage-dependent 3-terminal off-state drain current was adequately modeled with Frenkel-Poole emission.« less

An AlN/Al{sub 0.85}Ga{sub 0.15}N high electron mobility transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baca, Albert G.; Armstrong, Andrew M.; Allerman, Andrew A.

2016-07-18

An AlN barrier high electron mobility transistor (HEMT) based on the AlN/Al{sub 0.85}Ga{sub 0.15}N heterostructure was grown, fabricated, and electrically characterized, thereby extending the range of Al composition and bandgap for AlGaN channel HEMTs. An etch and regrowth procedure was implemented for source and drain contact formation. A breakdown voltage of 810 V was achieved without a gate insulator or field plate. Excellent gate leakage characteristics enabled a high I{sub on}/I{sub off} current ratio greater than 10{sup 7} and an excellent subthreshold slope of 75 mV/decade. A large Schottky barrier height of 1.74 eV contributed to these results. The room temperature voltage-dependent 3-terminalmore » off-state drain current was adequately modeled with Frenkel-Poole emission.« less

Effect of surface roughness of trench sidewalls on electrical properties in 4H-SiC trench MOSFETs

NASA Astrophysics Data System (ADS)

Kutsuki, Katsuhiro; Murakami, Yuki; Watanabe, Yukihiko; Onishi, Toru; Yamamoto, Kensaku; Fujiwara, Hirokazu; Ito, Takahiro

2018-04-01

The effects of the surface roughness of trench sidewalls on electrical properties have been investigated in 4H-SiC trench MOSFETs. The surface roughness of trench sidewalls was well controlled and evaluated by atomic force microscopy. The effective channel mobility at each measurement temperature was analyzed on the basis of the mobility model including optical phonon scattering. The results revealed that surface roughness scattering had a small contribution to channel mobility, and at the arithmetic average roughness in the range of 0.4-1.4 nm, there was no correlation between the experimental surface roughness and the surface roughness scattering mobility. On the other hand, the characteristics of the gate leakage current and constant current stress time-dependent dielectric breakdown tests demonstrated that surface morphology had great impact on the long-term reliability of gate oxides.

Impact of random discrete dopant in extension induced fluctuation in gate-source/drain underlap FinFET

NASA Astrophysics Data System (ADS)

Wang, Yijiao; Huang, Peng; Xin, Zheng; Zeng, Lang; Liu, Xiaoyan; Du, Gang; Kang, Jinfeng

2014-01-01

In this work, three dimensional technology computer-aided design (TCAD) simulations are performed to investigate the impact of random discrete dopant (RDD) including extension induced fluctuation in 14 nm silicon-on-insulator (SOI) gate-source/drain (G-S/D) underlap fin field effect transistor (FinFET). To fully understand the RDD impact in extension, RDD effect is evaluated in channel and extension separately and together. The statistical variability of FinFET performance parameters including threshold voltage (Vth), subthreshold slope (SS), drain induced barrier lowering (DIBL), drive current (Ion), and leakage current (Ioff) are analyzed. The results indicate that RDD in extension can lead to substantial variability, especially for SS, DIBL, and Ion and should be taken into account together with that in channel to get an accurate estimation on RDF. Meanwhile, higher doping concentration of extension region is suggested from the perspective of overall variability control.

Novel trench gate field stop IGBT with trench shorted anode

NASA Astrophysics Data System (ADS)

Xudong, Chen; Jianbing, Cheng; Guobing, Teng; Houdong, Guo

2016-05-01

A novel trench field stop (FS) insulated gate bipolar transistor (IGBT) with a trench shorted anode (TSA) is proposed. By introducing a trench shorted anode, the TSA-FS-IGBT can obviously improve the breakdown voltage. As the simulation results show, the breakdown voltage is improved by a factor of 19.5% with a lower leakage current compared with the conventional FS-IGBT. The turn off time of the proposed structure is 50% lower than the conventional one with less than 9% voltage drop increased at a current density of 150 A/cm2. Additionally, there is no snapback observed. As a result, the TSA-FS-IGBT has a better trade-off relationship between the turn off loss and forward drop. Project supported by the National Natural Science Foundation of China (No. 61274080) and the Postdoctoral Science Foundation of China (No. 2013M541585).

p-MOSFET total dose dosimeter

NASA Technical Reports Server (NTRS)

Buehler, Martin G. (Inventor); Blaes, Brent R. (Inventor)

1994-01-01

A p-MOSFET total dose dosimeter where the gate voltage is proportional to the incident radiation dose. It is configured in an n-WELL of a p-BODY substrate. It is operated in the saturation region which is ensured by connecting the gate to the drain. The n-well is connected to zero bias. Current flow from source to drain, rather than from peripheral leakage, is ensured by configuring the device as an edgeless MOSFET where the source completely surrounds the drain. The drain junction is the only junction not connected to zero bias. The MOSFET is connected as part of the feedback loop of an operational amplifier. The operational amplifier holds the drain current fixed at a level which minimizes temperature dependence and also fixes the drain voltage. The sensitivity to radiation is made maximum by operating the MOSFET in the OFF state during radiation soak.

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

NASA Astrophysics Data System (ADS)

Maheran, A. H. Afifah; Menon, P. S.; Ahmad, I.; Shaari, S.; Faizah, Z. A. Noor

2015-04-01

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (ILEAK) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO2) and tungsten silicide (WSix). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum ILEAK where the maximum predicted ILEAK value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/µm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device's leakage current. The absolute process parameters combination results in ILEAK mean value of 3.96821 nA/µm where is far lower than the predicted value.

Flexible, Low-Power Thin-Film Transistors Made of Vapor-Phase Synthesized High-k, Ultrathin Polymer Gate Dielectrics.

PubMed

Choi, Junhwan; Joo, Munkyu; Seong, Hyejeong; Pak, Kwanyong; Park, Hongkeun; Park, Chan Woo; Im, Sung Gap

2017-06-21

A series of high-k, ultrathin copolymer gate dielectrics were synthesized from 2-cyanoethyl acrylate (CEA) and di(ethylene glycol) divinyl ether (DEGDVE) monomers by a free radical polymerization via a one-step, vapor-phase, initiated chemical vapor deposition (iCVD) method. The chemical composition of the copolymers was systematically optimized by tuning the input ratio of the vaporized CEA and DEGDVE monomers to achieve a high dielectric constant (k) as well as excellent dielectric strength. Interestingly, DEGDVE was nonhomopolymerizable but it was able to form a copolymer with other kinds of monomers. Utilizing this interesting property of the DEGDVE cross-linker, the dielectric constant of the copolymer film could be maximized with minimum incorporation of the cross-linker moiety. To our knowledge, this is the first report on the synthesis of a cyanide-containing polymer in the vapor phase, where a high-purity polymer film with a maximized dielectric constant was achieved. The dielectric film with the optimized composition showed a dielectric constant greater than 6 and extremely low leakage current densities (<3 × 10 -8 A/cm 2 in the range of ±2 MV/cm), with a thickness of only 20 nm, which is an outstanding thickness for down-scalable cyanide polymer dielectrics. With this high-k dielectric layer, organic thin-film transistors (OTFTs) and oxide TFTs were fabricated, which showed hysteresis-free transfer characteristics with an operating voltage of less than 3 V. Furthermore, the flexible OTFTs retained their low gate leakage current and ideal TFT characteristics even under 2% applied tensile strain, which makes them some of the most flexible OTFTs reported to date. We believe that these ultrathin, high-k organic dielectric films with excellent mechanical flexibility will play a crucial role in future soft electronics.

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maheran, A. H. Afifah; Menon, P. S.; Shaari, S.

2015-04-24

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (I{sub LEAK}) onmore » PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO{sub 2}) and tungsten silicide (WSi{sub x}). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum I{sub LEAK} where the maximum predicted I{sub LEAK} value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/µm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device’s leakage current. The absolute process parameters combination results in I{sub LEAK} mean value of 3.96821 nA/µm where is far lower than the predicted value.« less

Electrical Double Layer Capacitance in a Graphene-embedded Al2O3 Gate Dielectric

PubMed Central

Ki Min, Bok; Kim, Seong K.; Jun Kim, Seong; Ho Kim, Sung; Kang, Min-A; Park, Chong-Yun; Song, Wooseok; Myung, Sung; Lim, Jongsun; An, Ki-Seok

2015-01-01

Graphene heterostructures are of considerable interest as a new class of electronic devices with exceptional performance in a broad range of applications has been realized. Here, we propose a graphene-embedded Al2O3 gate dielectric with a relatively high dielectric constant of 15.5, which is about 2 times that of Al2O3, having a low leakage current with insertion of tri-layer graphene. In this system, the enhanced capacitance of the hybrid structure can be understood by the formation of a space charge layer at the graphene/Al2O3 interface. The electrical properties of the interface can be further explained by the electrical double layer (EDL) model dominated by the diffuse layer. PMID:26530817

Electrical Properties of Ultrathin Hf-Ti-O Higher k Gate Dielectric Films and Their Application in ETSOI MOSFET.

PubMed

Xiong, Yuhua; Chen, Xiaoqiang; Wei, Feng; Du, Jun; Zhao, Hongbin; Tang, Zhaoyun; Tang, Bo; Wang, Wenwu; Yan, Jiang

2016-12-01

Ultrathin Hf-Ti-O higher k gate dielectric films (~2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) ~9.4%, low equivalent gate oxide thickness (EOT) of ~0.69 nm and acceptable gate leakage current density of 0.61 A/cm 2 @ (V fb  - 1)V could be obtained. The conduction mechanism through the gate dielectric is dominated by the F-N tunneling in the gate voltage range of -0.5 to -2 V. Under the same physical thickness and process flow, lower EOT and higher I on /I off ratio could be obtained while using Hf-Ti-O as gate dielectric compared with HfO 2 . With Hf-Ti-O as gate dielectric, two ETSOI PMOSFETs with gate width/gate length (W/L) of 0.5 μm/25 nm and 3 μm/40 nm show good performances such as high I on , I on /I off ratio in the magnitude of 10 5 , and peak transconductance, as well as suitable threshold voltage (-0.3~-0.2 V). Particularly, ETSOI PMOSFETs show superior short-channel control capacity with DIBL <82 mV/V and subthreshold swing <70 mV/decade.

Characteristics of enhanced-mode AlGaN/GaN MIS HEMTs for millimeter wave applications

NASA Astrophysics Data System (ADS)

Lee, Jong-Min; Ahn, Ho-Kyun; Jung, Hyun-Wook; Shin, Min Jeong; Lim, Jong-Won

2017-09-01

In this paper, an enhanced-mode (E-mode) AlGaN/GaN high electron mobility transistor (HEMT) was developed by using 4-inch GaN HEMT process. We designed and fabricated Emode HEMTs and characterized device performance. To estimate the possibility of application for millimeter wave applications, we focused on the high frequency performance and power characteristics. To shift the threshold voltage of HEMTs we applied the Al2O3 insulator to the gate structure and adopted the gate recess technique. To increase the frequency performance the e-beam lithography technique was used to define the 0.15 um gate length. To evaluate the dc and high frequency performance, electrical characterization was performed. The threshold voltage was measured to be positive value by linear extrapolation from the transfer curve. The device leakage current is comparable to that of the depletion mode device. The current gain cut-off frequency and the maximum oscillation frequency of the E-mode device with a total gate width of 150 um were 55 GHz and 168 GHz, respectively. To confirm the power performance for mm-wave applications the load-pull test was performed. The measured power density of 2.32 W/mm was achieved at frequencies of 28 and 30 GHz.

1T1R Nonvolatile Memory with Al/TiO2/Au and Sol-Gel-Processed Insulator for Barium Zirconate Nickelate Gate in Pentacene Thin Film Transistor

PubMed Central

Lee, Ke-Jing; Chang, Yu-Chi; Lee, Cheng-Jung; Wang, Li-Wen; Wang, Yeong-Her

2017-01-01

A one-transistor and one-resistor (1T1R) architecture with a resistive random access memory (RRAM) cell connected to an organic thin-film transistor (OTFT) device is successfully demonstrated to avoid the cross-talk issues of only one RRAM cell. The OTFT device, which uses barium zirconate nickelate (BZN) as a dielectric layer, exhibits favorable electrical properties, such as a high field-effect mobility of 2.5 cm2/Vs, low threshold voltage of −2.8 V, and low leakage current of 10−12 A, for a driver in the 1T1R operation scheme. The 1T1R architecture with a TiO2-based RRAM cell connected with a BZN OTFT device indicates a low operation current (10 μA) and reliable data retention (over ten years). This favorable performance of the 1T1R device can be attributed to the additional barrier heights introduced by using Ni (II) acetylacetone as a substitute for acetylacetone, and the relatively low leakage current of a BZN dielectric layer. The proposed 1T1R device with low leakage current OTFT and excellent uniform resistance distribution of RRAM exhibits a good potential for use in practical low-power electronic applications. PMID:29232828

Interfacial and electrical properties of InGaAs metal-oxide-semiconductor capacitor with TiON/TaON multilayer composite gate dielectric

NASA Astrophysics Data System (ADS)

Wang, L. S.; Xu, J. P.; Liu, L.; Lu, H. H.; Lai, P. T.; Tang, W. M.

2015-03-01

InGaAs metal-oxide-semiconductor (MOS) capacitors with composite gate dielectric consisting of Ti-based oxynitride (TiON)/Ta-based oxynitride (TaON) multilayer are fabricated by RF sputtering. The interfacial and electrical properties of the TiON/TaON/InGaAs and TaON/TiON/InGaAs MOS structures are investigated and compared. Experimental results show that the former exhibits lower interface-state density (1.0 × 1012 cm-2 eV-1 at midgap), smaller gate leakage current (9.5 × 10-5 A/cm2 at a gate voltage of 2 V), larger equivalent dielectric constant (19.8), and higher reliability under electrical stress than the latter. The involved mechanism lies in the fact that the ultrathin TaON interlayer deposited on the sulfur-passivated InGaAs surface can effectively reduce the defective states and thus unpin the Femi level at the TaON/InGaAs interface, improving the electrical properties of the device.

A wide bandgap silicon carbide (SiC) gate driver for high-temperature and high-voltage applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lamichhane, Ranjan; Ericson, Milton Nance; Frank, Steven Shane

2014-01-01

Limitations of silicon (Si) based power electronic devices can be overcome with Silicon Carbide (SiC) because of its remarkable material properties. SiC is a wide bandgap semiconductor material with larger bandgap, lower leakage currents, higher breakdown electric field, and higher thermal conductivity, which promotes higher switching frequencies for high power applications, higher temperature operation, and results in higher power density devices relative to Si [1]. The proposed work is focused on design of a SiC gate driver to drive a SiC power MOSFET, on a Cree SiC process, with rise/fall times (less than 100 ns) suitable for 500 kHz tomore » 1 MHz switching frequency applications. A process optimized gate driver topology design which is significantly different from generic Si circuit design is proposed. The ultimate goal of the project is to integrate this gate driver into a Toyota Prius plug-in hybrid electric vehicle (PHEV) charger module. The application of this high frequency charger will result in lighter, smaller, cheaper, and a more efficient power electronics system.« less

Air-gating and chemical-gating in transistors and sensing devices made from hollow TiO2 semiconductor nanotubes

NASA Astrophysics Data System (ADS)

Alivov, Yahya; Funke, Hans; Nagpal, Prashant

2015-07-01

Rapid miniaturization of electronic devices down to the nanoscale, according to Moore’s law, has led to some undesirable effects like high leakage current in transistors, which can offset additional benefits from scaling down. Development of three-dimensional transistors, by spatial extension in the third dimension, has allowed higher contact area with a gate electrode and better control over conductivity in the semiconductor channel. However, these devices do not utilize the large surface area and interfaces for new electronic functionality. Here, we demonstrate air gating and chemical gating in hollow semiconductor nanotube devices and highlight the potential for development of novel transistors that can be modulated using channel bias, gate voltage, chemical composition, and concentration. Using chemical gating, we reversibly altered the conductivity of nanoscaled semiconductor nanotubes (10-500 nm TiO2 nanotubes) by six orders of magnitude, with a tunable rectification factor (ON/OFF ratio) ranging from 1-106. While demonstrated air- and chemical-gating speeds were slow here (˜seconds) due to the mechanical-evacuation rate and size of our chamber, the small nanoscale volume of these hollow semiconductors can enable much higher switching speeds, limited by the rate of adsorption/desorption of molecules at semiconductor interfaces. These chemical-gating effects are completely reversible, additive between different chemical compositions, and can enable semiconductor nanoelectronic devices for ‘chemical transistors’, ‘chemical diodes’, and very high-efficiency sensing applications.

Surface stoichiometry modification and improved DC/RF characteristics by plasma treated and annealed AlGaN/GaN HEMTs

NASA Astrophysics Data System (ADS)

Upadhyay, Bhanu B.; Takhar, Kuldeep; Jha, Jaya; Ganguly, Swaroop; Saha, Dipankar

2018-03-01

We demonstrate that N2 and O2 plasma treatment followed by rapid thermal annealing leads to surface stoichiometry modification in a AlGaN/GaN high electron mobility transistor. Both the source/drain access and gate regions respond positively improving the transistor characteristics albeit to different extents. Characterizations indicate that the surface show the characteristics of that of a higher band-gap material like AlxOy and GaxOy along with N-vacancy in the sub-surface region. The N-vacancy leads to an increased two-dimensional electron gas density. The formation of oxides lead to a reduced gate leakage current and surface passivation. The DC characteristics show increased transconductance, saturation drain current, ON/OFF current ratio, sub-threshold swing and lower ON resistance by a factor of 2.9, 2.0, 103.3 , 2.3, and 2.1, respectively. The RF characteristics show an increase in unity current gain frequency by a factor of 1.7 for a 500 nm channel length device.

Double gate graphene nanoribbon field effect transistor with single halo pocket in channel region

NASA Astrophysics Data System (ADS)

Naderi, Ali

2016-01-01

A new structure for graphene nanoribbon field-effect transistors (GNRFETs) is proposed and investigated using quantum simulation with a nonequilibrium Green's function (NEGF) method. Tunneling leakage current and ambipolar conduction are known effects for MOSFET-like GNRFETs. To minimize these issues a novel structure with a simple change of the GNRFETs by using single halo pocket in the intrinsic channel region, "Single Halo GNRFET (SH-GNRFET)", is proposed. An appropriate halo pocket at source side of channel is used to modify potential distribution of the gate region and weaken band to band tunneling (BTBT). In devices with materials like Si in channel region, doping type of halo and source/drain regions are different. But, here, due to the smaller bandgap of graphene, the mentioned doping types should be the same to reduce BTBT. Simulations have shown that in comparison with conventional GNRFET (C-GNRFET), an SH-GNRFET with appropriately halo doping results in a larger ON current (Ion), smaller OFF current (Ioff), a larger ON-OFF current ratio (Ion/Ioff), superior ambipolar characteristics, a reduced power-delay product and lower delay time.

Device Performance and Reliability Improvements of AlGaBN/GaN/Si MOSFET

DTIC Science & Technology

2016-02-04

Metal insulator semiconductor AlGaN /GaN high electron mobility transistors (MISHEMTs) are promising for power device applications due to a lower leakage...current than the conventional Schottky AlGaN/GaN HEMTs.1–3 Among a large number of insulator materials, an Al2O3 dielectric layer, deposited by...atomic layer deposition (ALD), is often employed as the gate insulator because of a large band gap (and the resultant high conduction band offset on

Nanoscale MOS devices: device parameter fluctuations and low-frequency noise (Invited Paper)

NASA Astrophysics Data System (ADS)

Wong, Hei; Iwai, Hiroshi; Liou, J. J.

2005-05-01

It is well-known in conventional MOS transistors that the low-frequency noise or flicker noise is mainly contributed by the trapping-detrapping events in the gate oxide and the mobility fluctuation in the surface channel. In nanoscale MOS transistors, the number of trapping-detrapping events becomes less important because of the large direct tunneling current through the ultrathin gate dielectric which reduces the probability of trapping-detrapping and the level of leakage current fluctuation. Other noise sources become more significant in nanoscale devices. The source and drain resistance noises have greater impact on the drain current noise. Significant contribution of the parasitic bipolar transistor noise in ultra-short channel and channel mobility fluctuation to the channel noise are observed. The channel mobility fluctuation in nanoscale devices could be due to the local composition fluctuation of the gate dielectric material which gives rise to the permittivity fluctuation along the channel and results in gigantic channel potential fluctuation. On the other hand, the statistical variations of the device parameters across the wafer would cause the noise measurements less accurate which will be a challenge for the applicability of analytical flicker noise model as a process or device evaluation tool for nanoscale devices. Some measures for circumventing these difficulties are proposed.

Temperature-Dependent Short-Circuit Capability of Silicon Carbide Power MOSFETs

DOE PAGES

Wang, Zhiqiang; Shi, Xiaojie; Tolbert, Leon M.; ...

2016-02-01

Our paper presents a comprehensive short-circuit ruggedness evaluation and numerical investigation of up-to-date commercial silicon carbide (SiC) MOSFETs. The short-circuit capability of three types of commercial 1200-V SiC MOSFETs is tested under various conditions, with case temperatures from 25 to 200 degrees C and dc bus voltages from 400 to 750 V. It is found that the commercial SiC MOSFETs can withstand short-circuit current for only several microseconds with a dc bus voltage of 750 V and case temperature of 200 degrees C. Moreover, the experimental short-circuit behaviors are compared, and analyzed through numerical thermal dynamic simulation. Specifically, an electrothermalmore » model is built to estimate the device internal temperature distribution, considering the temperature-dependent thermal properties of SiC material. Based on the temperature information, a leakage current model is derived to calculate the main leakage current components (i.e., thermal, diffusion, and avalanche generation currents). Finally, numerical results show that the short-circuit failure mechanisms of SiC MOSFETs can be thermal generation current induced thermal runaway or high-temperature-related gate oxide damage.« less

Power reduction by power gating in differential pair type spin-transfer-torque magnetic random access memories for low-power nonvolatile cache memories

NASA Astrophysics Data System (ADS)

Ohsawa, Takashi; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2014-01-01

Array operation currents in spin-transfer-torque magnetic random access memories (STT-MRAMs) that use four differential pair type magnetic tunnel junction (MTJ)-based memory cells (4T2MTJ, two 6T2MTJs and 8T2MTJ) are simulated and compared with that in SRAM. With L3 cache applications in mind, it is assumed that the memories are composed of 32 Mbyte capacity to be accessed in 64 byte in parallel. All the STT-MRAMs except for the 8T2MTJ one are designed with 32 bit fine-grained power gating scheme applied to eliminate static currents in the memory cells that are not accessed. The 8T2MTJ STT-MRAM, the cell’s design concept being not suitable for the fine-grained power gating, loads and saves 32 Mbyte data in 64 Mbyte unit per 1 Mbit sub-array in 2 × 103 cycles. It is shown that the array operation current of the 4T2MTJ STT-MRAM is 70 mA averaged in 15 ns write cycles at Vdd = 0.9 V. This is the smallest among the STT-MRAMs, about the half of the low standby power (LSTP) SRAM whose array operation current is totally dominated by the cells’ subthreshold leakage.

Interface Si donor control to improve dynamic performance of AlGaN/GaN MIS-HEMTs

NASA Astrophysics Data System (ADS)

Song, Liang; Fu, Kai; Zhang, Zhili; Sun, Shichuang; Li, Weiyi; Yu, Guohao; Hao, Ronghui; Fan, Yaming; Shi, Wenhua; Cai, Yong; Zhang, Baoshun

2017-12-01

In this letter, we have studied the performance of AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) with different interface Si donor incorporation which is tuned during the deposition process of LPCVD-SiNx which is adopted as gate dielectric and passivation layer. Current collapse of the MIS-HEMTs without field plate is suppressed more effectively by increasing the SiH2Cl2/NH3 flow ratio and the normalized dynamic on-resistance (RON) is reduced two orders magnitude after off-state VDS stress of 600 V for 10 ms. Through interface characterization, we have found that the interface deep-level traps distribution with high Si donor incorporation by increasing the SiH2Cl2/NH3 flow ratio is lowered. It's indicated that the Si donors are most likely to fill and screen the deep-level traps at the interface resulting in the suppression of slow trapping process and the virtual gate effect. Although the Si donor incorporation brings about the increase of gate leakage current (IGS), no clear degradation of breakdown voltage can be seen by choosing appropriate SiH2Cl2/NH3 flow ratio.

Selective area deposited n-Al0.5Ga0.5N channel field effect transistors with high solar-blind ultraviolet photo-responsivity

NASA Astrophysics Data System (ADS)

Muhtadi, S.; Hwang, S.; Coleman, A.; Asif, F.; Lunev, A.; Chandrashekhar, M. V. S.; Khan, A.

2017-04-01

We report on AlGaN field effect transistors over AlN/sapphire templates with selective area grown n-Al0.5Ga0.5N channel layers for which a field-effect mobility of 55 cm2/V-sec was measured. Using a pulsed plasma enhanced chemical vapor deposition deposited 100 A thick SiO2 layer as the gate-insulator, the gate-leakage currents were reduced by three orders of magnitude. These devices with or without gate insulators are excellent solar-blind ultraviolet detectors, and they can be operated either in the photoconductive or the photo-voltaic modes. In the photo-conductive mode, gain arising from hole-trapping in the depletion region leads to steady-state photoresponsivity as high as 1.2 × 106A/W at 254 nm, which drops sharply below 290 nm. A hole-trapping limited detector response time of 34 ms, fast enough for real-time flame-detection and imaging applications, was estimated.

Improved interfacial and electrical properties of GaAs metal-oxide-semiconductor capacitors with HfTiON as gate dielectric and TaON as passivation interlayer

NASA Astrophysics Data System (ADS)

Wang, L. S.; Xu, J. P.; Zhu, S. Y.; Huang, Y.; Lai, P. T.

2013-08-01

The interfacial and electrical properties of sputtered HfTiON on sulfur-passivated GaAs with or without TaON as interfacial passivation layer (IPL) are investigated. Experimental results show that the GaAs metal-oxide-semiconductor capacitor with HfTiON/TaON stacked gate dielectric annealed at 600 °C exhibits low interface-state density (1.0 × 1012 cm-2 eV-1), small gate leakage current (7.3 × 10-5 A cm-2 at Vg = Vfb + 1 V), small capacitance equivalent thickness (1.65 nm), and large equivalent dielectric constant (26.2). The involved mechanisms lie in the fact that the TaON IPL can effectively block the diffusions of Hf, Ti, and O towards GaAs surface and suppress the formation of interfacial As-As bonds, Ga-/As-oxides, thus unpinning the Femi level at the TaON/GaAs interface and improving the interface quality and electrical properties of the device.

Experimental determination of the impact of polysilicon LER on sub-100-nm transistor performance

NASA Astrophysics Data System (ADS)

Patterson, Kyle; Sturtevant, John L.; Alvis, John R.; Benavides, Nancy; Bonser, Douglas; Cave, Nigel; Nelson-Thomas, Carla; Taylor, William D.; Turnquest, Karen L.

2001-08-01

Photoresist line edge roughness (LER) has long been feared as a potential limitation to the application of various patterning technologies to actual devices. While this concern seems reasonable, experimental verification has proved elusive and thus LER specifications are typically without solid parametric rationale. We report here the transistor device performance impact of deliberate variations of polysilicon gate LER. LER magnitude was attenuated by more than a factor of 5 by altering the photoresist type and thickness, substrate reflectivity, masking approach, and etch process. The polysilicon gate LER for nominally 70 - 150 nm devices was quantified using digital image processing of SEM images, and compared to gate leakage and drive current for variable length and width transistors. With such comparisons, realistic LER specifications can be made for a given transistor. It was found that subtle cosmetic LER differences are often not discernable electrically, thus providing hope that LER will not limit transistor performance as the industry migrates to sub-100 nm patterning.

Passivation of oxide traps and interface states in GaAs metal-oxide-semiconductor capacitor by LaTaON passivation layer and fluorine incorporation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, L. N.; Choi, H. W.; Lai, P. T., E-mail: laip@eee.hku.hk

2015-11-23

GaAs metal-oxide-semiconductor capacitor with TaYON/LaTaON gate-oxide stack and fluorine-plasma treatment is fabricated and compared with its counterparts without the LaTaON passivation interlayer or the fluorine treatment. Experimental results show that the sample exhibits better characteristics: low interface-state density (8 × 10{sup 11 }cm{sup −2}/eV), small flatband voltage (0.69 V), good capacitance-voltage behavior, small frequency dispersion, and small gate leakage current (6.35 × 10{sup −6} A/cm{sup 2} at V{sub fb} + 1 V). These should be attributed to the suppressed growth of unstable Ga and As oxides on the GaAs surface during gate-oxide annealing by the LaTaON interlayer and fluorine incorporation, and the passivating effects of fluorine atoms on the acceptor-likemore » interface and near-interface traps.« less

Effects of trap-assisted tunneling on gate-induced drain leakage in silicon-germanium channel p-type FET for scaled supply voltages

NASA Astrophysics Data System (ADS)

Tiwari, Vishal A.; Divakaruni, Rama; Hook, Terence B.; Nair, Deleep R.

2016-04-01

Silicon-germanium is considered as an alternative channel material to silicon p-type FET (pFET) for the development of energy efficient high performance transistors for 28 nm and beyond in a high-k metal gate technology because of its lower threshold voltage and higher mobility. However, gate-induced drain leakage (GIDL) is a concern for high threshold voltage device design because of tunneling at reduced bandgap. In this work, the trap-assisted tunneling and band-to-band tunneling (BTBT) effects on GIDL is analyzed and modeled for SiGe pFETs. Experimental results and Monte Carlo simulation results reveal that the pre-halo germanium pre-amorphization implant used to contain the short channel effects contribute to GIDL at the drain sidewall in addition to GIDL due to BTBT in SiGe devices. The results are validated by comparing the experimental observations with the numerical simulation and a set of calibrated models are used to describe the GIDL mechanisms for various drain and gate bias.

Error budgeting single and two qubit gates in a superconducting qubit

NASA Astrophysics Data System (ADS)

Chen, Z.; Chiaro, B.; Dunsworth, A.; Foxen, B.; Neill, C.; Quintana, C.; Wenner, J.; Martinis, John. M.; Google Quantum Hardware Team Team

Superconducting qubits have shown promise as a platform for both error corrected quantum information processing and demonstrations of quantum supremacy. High fidelity quantum gates are crucial to achieving both of these goals, and superconducting qubits have demonstrated two qubit gates exceeding 99% fidelity. In order to improve gate fidelity further, we must understand the remaining sources of error. In this talk, I will demonstrate techniques for quantifying the contributions of control, decoherence, and leakage to gate error, for both single and two qubit gates. I will also discuss the near term outlook for achieving quantum supremacy using a gate-based approach in superconducting qubits. This work is supported Google Inc., and by the National Science Foundation Graduate Research Fellowship under Grant No. DGE 1605114.

Medium band gap polymer based solution-processed high-κ composite gate dielectrics for ambipolar OFET

NASA Astrophysics Data System (ADS)

Canımkurbey, Betül; Unay, Hande; Çakırlar, Çiğdem; Büyükköse, Serkan; Çırpan, Ali; Berber, Savas; Altürk Parlak, Elif

2018-03-01

The authors present a novel ambipolar organic filed-effect transistors (OFETs) composed of a hybrid dielectric thin film of Ta2O5:PMMA nanocomposite material, and solution processed poly(selenophene, benzotriazole and dialkoxy substituted [1,2-b:4, 5-b‧] dithiophene (P-SBTBDT)-based organic semiconducting material as the active layer of the device. We find that the Ta2O5:PMMA insulator shows n-type conduction character, and its combination with the p-type P-SBTBDT organic semiconductor leads to an ambipolar OFET device. Top-gated OFETs were fabricated on glass substrate consisting of interdigitated ITO electrodes. P-SBTBDT-based material was spin coated on the interdigitated ITO electrodes. Subsequently, a solution processed Ta2O5:PMMA nanocomposite material was spin coated, thereby creating the gate dielectric layer. Finally, as a gate metal, an aluminum layer was deposited by thermal evaporation. The fabricated OFETs exhibited an ambipolar performance with good air-stability, high field-induced current and relatively high electron and hole mobilities although Ta2O5:PMMA nanocomposite films have slightly higher leakage current compared to the pure Ta2O5 films. Dielectric properties of the devices with different ratios of Ta2O5:PMMA were also investigated. The dielectric constant varied between 3.6 and 5.3 at 100 Hz, depending on the Ta2O5:PMMA ratio.

Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors

NASA Astrophysics Data System (ADS)

Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

2016-04-01

In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade-1 and 3.62 × 1011 eV-1 cm-2, respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

An AlGaN/GaN high-electron-mobility transistor with an AlN sub-buffer layer

NASA Astrophysics Data System (ADS)

Shealy, J. R.; Kaper, V.; Tilak, V.; Prunty, T.; Smart, J. A.; Green, B.; Eastman, L. F.

2002-04-01

The AlGaN/GaN high-electron-mobility transistor requires a thermally conducting, semi-insulating substrate to achieve the best possible microwave performance. The semi-insulating SiC substrate is currently the best choice for this device technology; however, fringing fields which penetrate the GaN buffer layer at pinch-off introduce significant substrate conduction at modest drain bias if channel electrons are not well confined to the nitride structure. The addition of an insulating AlN sub-buffer on the semi-insulating SiC substrate suppresses this parasitic conduction, which results in dramatic improvements in the AlGaN/GaN transistor performance. A pronounced reduction in both the gate-lag and the gate-leakage current are observed for structures with the AlN sub-buffer layer. These structures operate up to 50 V drain bias under drive, corresponding to a peak voltage of 80 V, for a 0.30 µm gate length device. The devices have achieved high-efficiency operation at 10 GHz (>70% power-added efficiency in class AB mode at 15 V drain bias) and the highest output power density observed thus far (11.2 W mm-1). Large-periphery devices (1.5 mm gate width) deliver 10 W (continuous wave) of maximum saturated output power at 10 GHz. The growth, processing, and performance of these devices are briefly reviewed.

Epitaxial GeSn film formed by solid phase epitaxy and its application to Yb{sub 2}O{sub 3}-gated GeSn metal-oxide-semiconductor capacitors with sub-nm equivalent oxide thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Ching-Wei; Wu, Yung-Hsien; Hsieh, Ching-Heng

2014-11-17

Through the technique of solid phase epitaxy (SPE), an epitaxial Ge{sub 0.955}Sn{sub 0.045} film was formed on a Ge substrate by depositing an amorphous GeSn film followed by a rapid thermal annealing at 550 °C. A process that uses a SiO{sub 2} capping layer on the amorphous GeSn film during SPE was proposed and it prevents Sn precipitation from occurring while maintaining a smooth surface due to the reduced surface mobility of Sn atoms. The high-quality epitaxial GeSn film was observed to have single crystal structure, uniform thickness and composition, and tiny surface roughness with root mean square of 0.56 nm. Withmore » a SnO{sub x}-free surface, Yb{sub 2}O{sub 3}-gated GeSn metal-oxide-semiconductor (MOS) capacitors with equivalent oxide thickness (EOT) of 0.55 nm were developed. A small amount of traps inside the Yb{sub 2}O{sub 3} was verified by negligible hysteresis in capacitance measurement. Low leakage current of 0.4 A/cm{sup 2} at gate bias of flatband voltage (V{sub FB})-1 V suggests the high quality of the gate dielectric. In addition, the feasibility of using Yb{sub 2}O{sub 3} to well passivate GeSn surface was also evidenced by the small interface trap density (D{sub it}) of 4.02 × 10{sup 11} eV{sup −1} cm{sup −2}, which can be attributed to smooth GeSn surface and Yb{sub 2}O{sub 3} valency passivation. Both leakage current and D{sub it} performance outperform other passivation techniques at sub-nm EOT regime. The proposed epitaxial GeSn film along with Yb{sub 2}O{sub 3} dielectric paves an alternative way to enable high-performance GeSn MOS devices.« less

Development and characterization of ultrathin hafnium titanates as high permittivity gate insulators

NASA Astrophysics Data System (ADS)

Li, Min

High permittivity or high-kappa materials are being developed for use as gate insulators for future ultrascaled metal oxide semiconductor field effect transistors (MOSFETs). Hafnium containing compounds are the leading candidates. Due to its moderate permittivity, however, it is difficult to achieve HfO2 gate structures with an EOT well below 1.0 nm. One approach to increase HfO2 permittivity is combining it with a very high-kappa material, such as TiO2. In this thesis, we systematically studied the electrical and physical characteristics of high-kappa hafnium titanates films as gate insulators. A series of HfxTi1-xO2 films with well-controlled composition were deposited using an MOCVD system. The physical properties of the films were analyzed using a variety of characterization techniques. X-ray micro diffraction indicates that the Ti-rich thin film is more immune to crystallization. TEM analysis showed that the thick stoichiometric HfTiO 4 film has an orthorhombic structure and large anisotropic grains. The C-V curves from the devices with the hafnium titanates films displayed relatively low hysteresis. In a certain composition range, the interfacial layer (IL) EOT and permittivity of HfxTi1-x O2 increases linearly with increasing Ti. The charge is negative for HfxTi1-xO2/IL and positive for Si/IL interface, and the magnitude increases as Hf increases. For ultra-thin films (less than 2 nm EOT), the leakage current increases with increasing HE Moreover, the Hf-rich sample has weaker temperature dependence of the current. In the MOSFET devices with the hafnium titanates films, normal transistor characteristics were observed, also electron mobility degradation. Next, we investigated the effects that different pre-deposition surface treatments, including HF dipping, NH3 surface nitridation, and HfO2 deposition, have on the electrical properties of hafnium titanates. Surface nitridation shows stronger effect than the thin HfO2 layer. The nitrided samples displayed a negative flat band voltage shift and larger hysteresis relative to the HF-dipped samples. The IL EOT reduction by mtridation increases with increasing HE Surface nitridation also induces extra charge, more considerable at the Si/IL interface. The leakage current is reduced in the Hf-rich samples with a nitride layer. Electron mobility degradation by surface nitridation was also observed.

Device and material characterization and analytic modeling of amorphous silicon thin film transistors

NASA Astrophysics Data System (ADS)

Slade, Holly Claudia

Hydrogenated amorphous silicon thin film transistors (TFTs) are now well-established as switching elements for a variety of applications in the lucrative electronics market, such as active matrix liquid crystal displays, two-dimensional imagers, and position-sensitive radiation detectors. These applications necessitate the development of accurate characterization and simulation tools. The main goal of this work is the development of a semi- empirical, analytical model for the DC and AC operation of an amorphous silicon TFT for use in a manufacturing facility to improve yield and maintain process control. The model is physically-based, in order that the parameters scale with gate length and can be easily related back to the material and device properties. To accomplish this, extensive experimental data and 2D simulations are used to observe and quantify non- crystalline effects in the TFTs. In particular, due to the disorder in the amorphous network, localized energy states exist throughout the band gap and affect all regimes of TFT operation. These localized states trap most of the free charge, causing a gate-bias-dependent field effect mobility above threshold, a power-law dependence of the current on gate bias below threshold, very low leakage currents, and severe frequency dispersion of the TFT gate capacitance. Additional investigations of TFT instabilities reveal the importance of changes in the density of states and/or back channel conduction due to bias and thermal stress. In the above threshold regime, the model is similar to the crystalline MOSFET model, considering the drift component of free charge. This approach uses the field effect mobility to take into account the trap states and must utilize the correct definition of threshold voltage. In the below threshold regime, the density of deep states is taken into account. The leakage current is modeled empirically, and the parameters are temperature dependent to 150oC. The capacitance of the TFT can be modeled using a transmission line model, which is implemented using a small signal circuit with access resistors in series with the source and drain capacitances. This correctly reproduces the frequency dispersion in the TFT. Automatic parameter extraction routines are provided and are used to test the robustness of the model on a variety of devices from different research laboratories. The results demonstrate excellent agreement, showing that the model is suitable for device design, scaling, and implementation in the manufacturing process.

A Low Temperature, Solution-Processed Poly(4-vinylphenol), YO(x) Nanoparticle Composite/Polysilazane Bi-Layer Gate Insulator for ZnO Thin Film Transistor.

PubMed

Shin, Hyeonwoo; Kang, Chan-Mo; Chae, Hyunsik; Kim, Hyun-Gwan; Baek, Kyu-Ha; Choi, Hyoung Jin; Park, Man-Young; Do, Lee-Mi; Lee, Changhee

2016-03-01

Low temperature, solution-processed metal oxide thin film transistors (MEOTFTs) have been widely investigated for application in low-cost, transparent, and flexible electronics. To enlarge the application area, solution-processed gate insulators (GI) have been investigated in recent years. We investigated the effects of the organic/inorganic bi-layer GI to ZnO thin film transistors (TFTs). PVP, YO(x) nanoparticle composite, and polysilazane bi-layer showed low leakage current (-10(-8) A/cm2 in 2 MV), which are applicable in low temperature processed MEOTFTs. Polysilazane was used as an interlayer between ZnO and PVP, YO(x) nanoparticle composite as a good charge transport interface with ZnO. By applying the PVP, YO(x), nanoparticle composite/polysilazane bi-layer structure to ZnO TFTs, we successfully suppressed the off current (I(off)) to -10(-11) and fabricated good MEOTFTs in 180 degrees C.

A high-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices.

PubMed

Hashemi, S Saeid; Sawan, Mohamad; Savaria, Yvon

2012-08-01

We present, in this paper, a new full-wave CMOS rectifier dedicated for wirelessly-powered low-voltage biomedical implants. It uses bootstrapped capacitors to reduce the effective threshold voltage of selected MOS switches. It achieves a significant increase in its overall power efficiency and low voltage-drop. Therefore, the rectifier is good for applications with low-voltage power supplies and large load current. The rectifier topology does not require complex circuit design. The highest voltages available in the circuit are used to drive the gates of selected transistors in order to reduce leakage current and to lower their channel on-resistance, while having high transconductance. The proposed rectifier was fabricated using the standard TSMC 0.18 μm CMOS process. When connected to a sinusoidal source of 3.3 V peak amplitude, it allows improving the overall power efficiency by 11% compared to the best recently published results given by a gate cross-coupled-based structure.

Introduction of performance boosters like Ge as channel material for the future of CMOS

DOE Office of Scientific and Technical Information (OSTI.GOV)

Samia, Slimani, E-mail: slimani.samia@gmail.com; Laboratoire de Modélisation et Méthodes de calcul LMMC,20002 Saida; Bouaza, Djellouli, E-mail: djelbou@hotmail.fr

High mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. Ge is one of new attractive channel materials that require CMOS scaling For future technology nodes and future high performance P-MOSFETS, we have studied a nanoscale SOI DG MOSFETs using quantum simulation approach on DG MOSFETs within the variation of Ge channel concentration and in the presence of source and drain doping by replacing Silicon in the channel by Ge using various dielectric constant. The use of high mobility channel (like Ge) to maximize the MOSFET IDsat and simultaneously circumventmore » the poor electrostatic control to suppress short-channel effects and enhance source injection velocity. The leakage current (I{sub off}) can be controlled by different gates oxide thickness more ever the required threshold voltage (V{sub TH}) can be achieved by keeping gate work function and altering the doping channel.« less

Fabrication and Analysis of a Selectively Contacted Dual Channel High Electron Mobility Field-Effect Transistor

NASA Astrophysics Data System (ADS)

Khanna, Ravi

1992-01-01

A selectively contacted dual-channel high electron mobility transistor (SCD-CHEMT) has been designed, fabricated, and electrically characterized, in order to better understand the properties of two layers of two-dimensional electron gases (2DEGs) confined within a quantum well. The 2DEGs are placed under a Schottky barrier control gate which modulates their sheet charge densities, and by use of auxiliary Schottky barrier gates and two levels of ohmic contacts, electrical contacts to the individual channels in which each 2DEG resides is achieved. The design of the dual channel FET structure, and its practical realization by recourse to process development and fabrication are described, as are the techniques, results, and interpretations of electrical characterizations used to analyze the completed device. Critical fabrication procedures involving photolithography, etching, deposition, shallow and deep ohmic contact formation, and gate formation are developed, and a simple technique to reduce gate leakage by photo-oxidation is demonstrated. Analysis of the completed device is performed using one-dimensional band diagram simulations, magnetotransport and electrical measurements. Magnetotransport studies establish the existence of two 2DEGs within the quantum well at 4K. Drain current vs. drain voltage, and transconductance vs. gate voltage characteristics at room temperature confirm the presence of two 2DEGs and show that current flow between them occurs easily at room temperature. Carrier electron mobility profiles are taken of the 2DEGs and show that the lower 2DEG has a mobility comparable to that of a 2DEG formed at a normal interface, indicating that the "inverted interface problem" has been overcome. Capacitance vs. gate voltage measurements are taken, which are consistent with a simple device model consisting of gate depletion and interelectrode parasitic capacitances. It is concluded from the analysis that the dual channel system resides in three basic states: (1) Both channels are occupied by 2DEGs or (2) The upper channel is depleted, or (3) Both channels depleted. Finally, increase in isolation between the two 2DEGs is dramatically demonstrated at 77K by the drain current vs. drain voltage, and transconductance vs. gate voltage characteristics.

Fabrication of Ta2O5/GeNx gate insulator stack for Ge metal-insulator-semiconductor structures by electron-cyclotron-resonance plasma nitridation and sputtering deposition techniques

NASA Astrophysics Data System (ADS)

Otani, Yohei; Itayama, Yasuhiro; Tanaka, Takuo; Fukuda, Yukio; Toyota, Hiroshi; Ono, Toshiro; Mitsui, Minoru; Nakagawa, Kiyokazu

2007-04-01

The authors have fabricated germanium (Ge) metal-insulator-semiconductor (MIS) structures with a 7-nm-thick tantalum pentaoxide (Ta2O5)/2-nm-thick germanium nitride (GeNx) gate insulator stack by electron-cyclotron-resonance plasma nitridation and sputtering deposition. They found that pure GeNx ultrathin layers can be formed by the direct plasma nitridation of the Ge surface without substrate heating. X-ray photoelectron spectroscopy revealed no oxidation of the GeNx layer after the Ta2O5 sputtering deposition. The fabricated MIS capacitor with a capacitance equivalent thickness of 4.3nm showed excellent leakage current characteristics. The interface trap density obtained by the modified conductance method was 4×1011cm-2eV-1 at the midgap.

Two-Dimensional Quantum Model of a Nanotransistor

NASA Technical Reports Server (NTRS)

Govindan, T. R.; Biegel, B.; Svizhenko, A.; Anantram, M. P.

2009-01-01

A mathematical model, and software to implement the model, have been devised to enable numerical simulation of the transport of electric charge in, and the resulting electrical performance characteristics of, a nanotransistor [in particular, a metal oxide/semiconductor field-effect transistor (MOSFET) having a channel length of the order of tens of nanometers] in which the overall device geometry, including the doping profiles and the injection of charge from the source, gate, and drain contacts, are approximated as being two-dimensional. The model and software constitute a computational framework for quantitatively exploring such device-physics issues as those of source-drain and gate leakage currents, drain-induced barrier lowering, and threshold voltage shift due to quantization. The model and software can also be used as means of studying the accuracy of quantum corrections to other semiclassical models.

Enhanced ZnO Thin-Film Transistor Performance Using Bilayer Gate Dielectrics.

PubMed

Alshammari, Fwzah H; Nayak, Pradipta K; Wang, Zhenwei; Alshareef, Husam N

2016-09-07

We report ZnO TFTs using Al2O3/Ta2O5 bilayer gate dielectrics grown by atomic layer deposition. The saturation mobility of single layer Ta2O5 dielectric TFT was 0.1 cm(2) V(-1) s(-1), but increased to 13.3 cm(2) V(-1) s(-1) using Al2O3/Ta2O5 bilayer dielectric with significantly lower leakage current and hysteresis. We show that point defects present in ZnO film, particularly VZn, are the main reason for the poor TFT performance with single layer dielectric, although interfacial roughness scattering effects cannot be ruled out. Our approach combines the high dielectric constant of Ta2O5 and the excellent Al2O3/ZnO interface quality, resulting in improved device performance.

1.8V Operation Power Amplifier IC for Bluetooth Class 1 Utilizing p+-GaAs Gate Hetero-Junction FET

NASA Astrophysics Data System (ADS)

Harima, Fumio; Bito, Yasunori; Takahashi, Hidemasa; Iwata, Naotaka

We have developed a power amplifier IC for Bluetooth Class 1 operating at single low voltage of 1.8V for both control and drain voltages. We can realize it due to fully enhancement-mode hetero-junction FETs utilizing a re-grown p+-GaAs gate technology. The power amplifier is a highly compact design as a small package of 1.5mm×1.5mm×0.4mm with fully integrated gain control and shutdown functions. An impressive power added efficiency of 52% at an output power of 20dBm is achieved with an associated gain of 22dB. Also, sufficiently low leakage current of 0.25μA at 27°C is exhibited, which is comparable to conventional HBT power amplifiers.

Abrupt current switching in graphene bilayer tunnel transistors enabled by van Hove singularities.

PubMed

Alymov, Georgy; Vyurkov, Vladimir; Ryzhii, Victor; Svintsov, Dmitry

2016-04-21

In a continuous search for the energy-efficient electronic switches, a great attention is focused on tunnel field-effect transistors (TFETs) demonstrating an abrupt dependence of the source-drain current on the gate voltage. Among all TFETs, those based on one-dimensional (1D) semiconductors exhibit the steepest current switching due to the singular density of states near the band edges, though the current in 1D structures is pretty low. In this paper, we propose a TFET based on 2D graphene bilayer which demonstrates a record steep subthreshold slope enabled by van Hove singularities in the density of states near the edges of conduction and valence bands. Our simulations show the accessibility of 3.5 × 10(4) ON/OFF current ratio with 150 mV gate voltage swing, and a maximum subthreshold slope of (20 μV/dec)(-1) just above the threshold. The high ON-state current of 0.8 mA/μm is enabled by a narrow (~0.3 eV) extrinsic band gap, while the smallness of the leakage current is due to an all-electrical doping of the source and drain contacts which suppresses the band tailing and trap-assisted tunneling.

Abrupt current switching in graphene bilayer tunnel transistors enabled by van Hove singularities

PubMed Central

Alymov, Georgy; Vyurkov, Vladimir; Ryzhii, Victor; Svintsov, Dmitry

2016-01-01

In a continuous search for the energy-efficient electronic switches, a great attention is focused on tunnel field-effect transistors (TFETs) demonstrating an abrupt dependence of the source-drain current on the gate voltage. Among all TFETs, those based on one-dimensional (1D) semiconductors exhibit the steepest current switching due to the singular density of states near the band edges, though the current in 1D structures is pretty low. In this paper, we propose a TFET based on 2D graphene bilayer which demonstrates a record steep subthreshold slope enabled by van Hove singularities in the density of states near the edges of conduction and valence bands. Our simulations show the accessibility of 3.5 × 104 ON/OFF current ratio with 150 mV gate voltage swing, and a maximum subthreshold slope of (20 μV/dec)−1 just above the threshold. The high ON-state current of 0.8 mA/μm is enabled by a narrow (~0.3 eV) extrinsic band gap, while the smallness of the leakage current is due to an all-electrical doping of the source and drain contacts which suppresses the band tailing and trap-assisted tunneling. PMID:27098051

Anomalous radiation effects in fully depleted SOI MOSFETs fabricated on SIMOX

NASA Astrophysics Data System (ADS)

Li, Ying; Niu, Guofu; Cressler, J. D.; Patel, J.; Marshall, C. J.; Marshall, P. W.; Kim, H. S.; Reed, R. A.; Palmer, M. J.

2001-12-01

We investigate the proton tolerance of fully depleted silicon-on-insulator (SOI) MOSFETs with H-gate and regular-gate structural configurations. For the front-gate characteristics, the H-gate does not show the edge leakage observed in the regular-gate transistor. An anomalous kink in the back-gate linear I/sub D/-V/sub GS/ characteristics of the fully depleted SOI nFETs has been observed at high radiation doses. This kink is attributed to charged traps generated in the bandgap at the buried oxide/silicon film interface during irradiation. Extensive two-dimensional simulations with MEDICI were used to understand the physical origin of this kink. We also report unusual self-annealing effects in the devices when they are cooled to liquid nitrogen temperature.

Characterization of ultrathin insulators in CMOS technology: Wearout and failure mechanisms due to processing and operation

NASA Astrophysics Data System (ADS)

Okandan, Murat

In the CMOS technology the gate dielectric is the most critical layer, as its condition directly dictates the ultimate performance of the devices. In this thesis, the wear-out and failure mechanisms in ultra-thin (around 50A and lower) oxides are investigated. A new degradation phenomenon, quasi-breakdown (or soft-breakdown), and the annealing and stressing behavior of devices after quasi-breakdown are considered in detail. Devices that are in quasi-breakdown continue to operate as switches, but the gate leakage current is two orders of magnitude higher than the leakage in healthy devices and the stressing/annealing behavior of the devices are completely altered. This phenomenon is of utmost interest, since the reduction in SiO2 dielectric thickness has reached its physical limits, and the quasi-breakdown behavior is seen to dominate as a failure mode in this regime. The quasi-breakdown condition can be brought on by stresses during operation or processing. To further study this evolution through stresses and anneals, cyclic current-voltage (I-V) measurement has been further developed and utilized in this thesis. Cyclic IV is a simple and fast, two terminal measurement technique that looks at the transient current flowing in an MOS system during voltage sweeps from accumulation to inversion and back. During these sweeps, carrier trapping/detrapping, generation and recombination are observed. An experimental setup using a fast electrometer and analog to digital conversion (A/D) card and the software for control of the setup and data analysis were also developed to gain further insight into the detailed physics involved. Overall, the crucial aspects of wear-out and quasi-breakdown of ultrathin dielectrics, along with the methods for analyzing this evolution are presented in this thesis.

Structural and Electrical Characterization of SiO2 Gate Dielectrics Deposited from Solutions at Moderate Temperatures in Air.

PubMed

Esro, Mazran; Kolosov, Oleg; Jones, Peter J; Milne, William I; Adamopoulos, George

2017-01-11

Silicon dioxide (SiO 2 ) is the most widely used dielectric for electronic applications. It is usually produced by thermal oxidation of silicon or by using a wide range of vacuum-based techniques. By default, the growth of SiO 2 by thermal oxidation of silicon requires the use of Si substrates whereas the other deposition techniques either produce low quality or poor interface material and mostly require high deposition or annealing temperatures. Recent investigations therefore have focused on the development of alternative deposition paradigms based on solutions. Here, we report the deposition of SiO 2 thin film dielectrics deposited by spray pyrolysis in air at moderate temperatures of ≈350 °C from pentane-2,4-dione solutions of SiCl 4 . SiO 2 dielectrics were investigated by means of UV-vis absorption spectroscopy, spectroscopic ellipsometry, XPS, XRD, UFM/AFM, admittance spectroscopy, and field-effect measurements. Data analysis reveals smooth (R RMS < 1 nm) amorphous films with a dielectric constant of about 3.8, an optical band gap of ≈8.1 eV, leakage current densities in the order of ≈10 -7 A/cm 2 at 1 MV/cm, and high dielectric strength in excess of 5 MV/cm. XPS measurements confirm the SiO 2 stoichiometry and FTIR spectra reveal features related to SiO 2 only. Thin film transistors implementing spray-coated SiO 2 gate dielectrics and C 60 and pentacene semiconducting channels exhibit excellent transport characteristics, i.e., negligible hysteresis, low leakage currents, high on/off current modulation ratio on the order of 10 6 , and high carrier mobility.

Low-voltage organic thin film transistors (OTFTs) using crosslinked polyvinyl alcohol (PVA)/neodymium oxide (Nd2O3) bilayer gate dielectrics

NASA Astrophysics Data System (ADS)

Khound, Sagarika; Sarma, Ranjit

2018-01-01

We have reported here on the design, processing and dielectric properties of pentacene-based organic thin film transitors (OTFTs) with a bilayer gate dilectrics of crosslinked PVA/Nd2O3 which enables low-voltage organic thin film operations. The dielectric characteristics of PVA/Nd2O3 bilayer films are studied by capacitance-voltage ( C- V) and current-voltage ( I- V) curves in the metal-insulator-metal (MIM) structure. We have analysed the output electrical responses and transfer characteristics of the OTFT devices to determine their performance of OTFT parameters. The mobility of 0.94 cm2/Vs, the threshold voltage of - 2.8 V, the current on-off ratio of 6.2 × 105, the subthreshold slope of 0.61 V/decade are evaluated. Low leakage current of the device is observed from current density-electric field ( J- E) curve. The structure and the morphology of the device are studied using X-ray diffraction (XRD) and atomic force microscope (AFM), respectively. The study demonstrates an effective way to realize low-voltage, high-performance OTFTs at low cost.

Effect of surface fields on the dynamic resistance of planar HgCdTe mid-wavelength infrared photodiodes

DOE Office of Scientific and Technical Information (OSTI.GOV)

He, Kai; Wang, Xi; Zhang, Peng

2015-05-28

This work investigates the effect of surface fields on the dynamic resistance of a planar HgCdTe mid-wavelength infrared photodiode from both theoretical and experimental aspects, considering a gated n-on-p diode with the surface potential of its p-region modulated. Theoretical models of the surface leakage current are developed, where the surface tunnelling current in the case of accumulation is expressed by modifying the formulation of bulk tunnelling currents, and the surface channel current for strong inversion is simulated with a transmission line method. Experimental data from the fabricated devices show a flat-band voltage of V{sub FB}=−5.7 V by capacitance-voltage measurement, and thenmore » the physical parameters for bulk properties are determined from the resistance-voltage characteristics of the diode working at a flat-band gate voltage. With proper values of the modeling parameters such as surface trap density and channel electron mobility, the theoretical R{sub 0}A product and corresponding dark current calculated from the proposed model as functions of the gate voltage V{sub g} demonstrate good consistency with the measured values. The R{sub 0}A product remarkably degenerates when V{sub g} is far below or above V{sub FB} because of the surface tunnelling current or channel current, respectively; and it attains the maximum value of 5.7×10{sup 7} Ω · cm{sup 2} around the transition between surface depletion and weak inversion when V{sub g}≈−4 V, which might result from reduced generation-recombination current.« less

Electrical characterization of 4H-SiC metal-oxide-semiconductor structure with Al2O3 stacking layers as dielectric

NASA Astrophysics Data System (ADS)

Chang, P. K.; Hwu, J. G.

2018-02-01

Interface defects and oxide bulk traps conventionally play important roles in the electrical performance of SiC MOS device. Introducing the Al2O3 stack grown by repeated anodization of Al films can notably lower the leakage current in comparison to the SiO2 structure, and enhance the minority carrier response at low frequency when the number of Al2O3 layers increase. In addition, the interface quality is not deteriorated by the stacking of Al2O3 layers because the stacked Al2O3 structure grown by anodization possesses good uniformity. In this work, the capacitance equivalent thickness (CET) of stacking Al2O3 will be up to 19.5 nm and the oxidation process can be carried out at room temperature. For the Al2O3 gate stack with CET 19.5 nm on n-SiC substrate, the leakage current at 2 V is 2.76 × 10-10 A/cm2, the interface trap density at the flatband voltage is 3.01 × 1011 eV-1 cm-2, and the effective breakdown field is 11.8 MV/cm. Frequency dispersion and breakdown characteristics may thus be improved as a result of the reduction in trap density. The Al2O3 stacking layers are capable of maintaining the leakage current as low as possible even after constant voltage stress test, which will further ameliorate reliability characteristics.

Atomic-layer-deposited Al2O3 and HfO2 on InAlAs: A comparative study of interfacial and electrical characteristics

NASA Astrophysics Data System (ADS)

Wu, Li-Fan; Zhang, Yu-Ming; Lv, Hong-Liang; Zhang, Yi-Men

2016-10-01

Al2O3 and HfO2 thin films are separately deposited on n-type InAlAs epitaxial layers by using atomic layer deposition (ALD). The interfacial properties are revealed by angle-resolved x-ray photoelectron spectroscopy (AR-XPS). It is demonstrated that the Al2O3 layer can reduce interfacial oxidation and trap charge formation. The gate leakage current densities are 1.37 × 10-6 A/cm2 and 3.22 × 10-6 A/cm2 at +1 V for the Al2O3/InAlAs and HfO2/InAlAs MOS capacitors respectively. Compared with the HfO2/InAlAs metal-oxide-semiconductor (MOS) capacitor, the Al2O3/InAlAs MOS capacitor exhibits good electrical properties in reducing gate leakage current, narrowing down the hysteresis loop, shrinking stretch-out of the C-V characteristics, and significantly reducing the oxide trapped charge (Q ot) value and the interface state density (D it). Project supported by the National Basic Research Program of China (Grant No. 2010CB327505), the Advanced Research Foundation of China (Grant No. 914xxx803-051xxx111), the National Defense Advance Research Project, China (Grant No. 513xxxxx306), the National Natural Science Foundation of China (Grant No. 51302215), the Scientific Research Program Funded by Shaanxi Provincial Education Department, China (Grant No. 14JK1656), and the Science and Technology Project of Shaanxi Province, China (Grant No. 2016KRM029).

Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography.

PubMed

Lim, Cheol-Min; Lee, In-Kyu; Lee, Ki Joong; Oh, Young Kyoung; Shin, Yong-Beom; Cho, Won-Ju

2017-01-01

This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.

Interfacial Cation-Defect Charge Dipoles in Stacked TiO2/Al2O3 Gate Dielectrics.

PubMed

Zhang, Liangliang; Janotti, Anderson; Meng, Andrew C; Tang, Kechao; Van de Walle, Chris G; McIntyre, Paul C

2018-02-14

Layered atomic-layer-deposited and forming-gas-annealed TiO 2 /Al 2 O 3 dielectric stacks, with the Al 2 O 3 layer interposed between the TiO 2 and a p-type germanium substrate, are found to exhibit a significant interface charge dipole that causes a ∼-0.2 V shift of the flat-band voltage and suppresses the leakage current density for gate injection of electrons. These effects can be eliminated by the formation of a trilayer dielectric stack, consistent with the cancellation of one TiO 2 /Al 2 O 3 interface dipole by the addition of another dipole of opposite sign. Density functional theory calculations indicate that the observed interface-dependent properties of TiO 2 /Al 2 O 3 dielectric stacks are consistent in sign and magnitude with the predicted behavior of Al Ti and Ti Al point-defect dipoles produced by local intermixing of the Al 2 O 3 /TiO 2 layers across the interface. Evidence for such intermixing is found in both electrical and physical characterization of the gate stacks.

Improved interface properties of Ge metal-oxide-semiconductor capacitor with TaTiO gate dielectric by using in situ TaON passivation interlayer

NASA Astrophysics Data System (ADS)

Ji, F.; Xu, J. P.; Liu, J. G.; Li, C. X.; Lai, P. T.

2011-05-01

TaON is in situ formed as a passivating interlayer in Ge metal-oxide-semiconductor (MOS) capacitors with high-k TaTiO gate dielectric fabricated simply by alternate sputtering of Ta and Ti. Also, postdeposition annealing is performed in wet N2 to suppress the growth of unstable GeOx at the Ge surface. As a result, excellent electrical properties of the Ge MOS devices are demonstrated, such as high equivalent dielectric constant (22.1), low interface-state density (7.3×1011 cm-2 eV), small gate leakage current (8.6×10-4 A cm-2 at Vg-Vfb=1 V), and high device reliability. Transmission electron microscopy and x-ray photoelectron spectroscopy support that all these should be attributed to the fact that the nitrogen barrier in the TaON interlayer can effectively block the interdiffusions of Ge and Ta, and the wet-N2 anneal can significantly suppress the growth of unstable low-k GeOx.

Effects of protein inter-layers on cell-diamond FET characteristics.

PubMed

Rezek, Bohuslav; Krátká, Marie; Kromka, Alexander; Kalbacova, Marie

2010-12-15

Diamond is recognized as an attractive material for merging solid-state and biological systems. The advantage of diamond field-effect transistors (FET) is that they are chemically resistant, bio-compatible, and can operate without gate oxides. Solution-gated FETs based on H-terminated nanocrystalline diamond films exhibiting surface conductivity are employed here for studying effects of fetal bovine serum (FBS) proteins and osteoblastic SAOS-2 cells on diamond electronic properties. FBS proteins adsorbed on the diamond FETs permanently decrease diamond conductivity as reflected by the -45 mV shift of the FET transfer characteristics. Cell cultivation for 2 days results in a further shift by another -78 mV. We attribute it to a change of diamond material properties rather than purely to the field-effect. Increase in gate leakage currents (by a factor of 4) indicates that the FBS proteins also decrease the diamond-electrolyte electronic barrier induced by C-H surface dipoles. We propose a model where the proteins replace ions in the very vicinity of the H-terminated diamond surface. Copyright © 2010 Elsevier B.V. All rights reserved.

Optimization of a Solution-Processed SiO2 Gate Insulator by Plasma Treatment for Zinc Oxide Thin Film Transistors.

PubMed

Jeong, Yesul; Pearson, Christopher; Kim, Hyun-Gwan; Park, Man-Young; Kim, Hongdoo; Do, Lee-Mi; Petty, Michael C

2016-01-27

We report on the optimization of the plasma treatment conditions for a solution-processed silicon dioxide gate insulator for application in zinc oxide thin film transistors (TFTs). The SiO2 layer was formed by spin coating a perhydropolysilazane (PHPS) precursor. This thin film was subsequently thermally annealed, followed by exposure to an oxygen plasma, to form an insulating (leakage current density of ∼10(-7) A/cm(2)) SiO2 layer. Optimized ZnO TFTs (40 W plasma treatment of the gate insulator for 10 s) possessed a carrier mobility of 3.2 cm(2)/(V s), an on/off ratio of ∼10(7), a threshold voltage of -1.3 V, and a subthreshold swing of 0.2 V/decade. In addition, long-term exposure (150 min) of the pre-annealed PHPS to the oxygen plasma enabled the maximum processing temperature to be reduced from 180 to 150 °C. The resulting ZnO TFT exhibited a carrier mobility of 1.3 cm(2)/(V s) and on/off ratio of ∼10(7).

Study of novel junctionless Ge n-Tunneling Field-Effect Transistors with lightly doped drain (LDD) region

NASA Astrophysics Data System (ADS)

Liu, Xiangyu; Hu, Huiyong; Wang, Bin; Wang, Meng; Han, Genquan; Cui, Shimin; Zhang, Heming

2017-02-01

In this paper, a novel junctionless Ge n-Tunneling Field-Effect Transistors (TFET) structure is proposed. The simulation results show that Ion = 5.5 × 10-5A/μm is achieved. The junctionless device structure enhances Ion effectively and increases the region where significant BTBT occurs, comparing with the normal Ge-nTEFT. The impact of the lightly doped drain (LDD) region is investigated. A comparison of Ion and Ioff of the junctionless Ge n-TFET with different channel doping concentration ND and LDD doping concentration NLDD is studied. Ioff is reduced 1 order of magnitude with the optimized ND and NLDD are 1 × 1018cm-3 and 1 × 1017 cm-3, respectively. To reduce the gate induced drain leakage (GIDL) current, the impact of the sloped gate oxide structure is also studied. By employing the sloped gate oxide structure, the below 60 mV/decade subthreshold swing S = 46.2 mV/decade is achieved at Ion = 4.05 × 10-5A/μm and Ion/Ioff = 5.7 × 106.

Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography

NASA Astrophysics Data System (ADS)

Lim, Cheol-Min; Lee, In-Kyu; Lee, Ki Joong; Oh, Young Kyoung; Shin, Yong-Beom; Cho, Won-Ju

2017-12-01

This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.

Models for Total-Dose Radiation Effects in Non-Volatile Memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Campbell, Philip Montgomery; Wix, Steven D.

The objective of this work is to develop models to predict radiation effects in non- volatile memory: flash memory and ferroelectric RAM. In flash memory experiments have found that the internal high-voltage generators (charge pumps) are the most sensitive to radiation damage. Models are presented for radiation effects in charge pumps that demonstrate the experimental results. Floating gate models are developed for the memory cell in two types of flash memory devices by Intel and Samsung. These models utilize Fowler-Nordheim tunneling and hot electron injection to charge and erase the floating gate. Erase times are calculated from the models andmore » compared with experimental results for different radiation doses. FRAM is less sensitive to radiation than flash memory, but measurements show that above 100 Krad FRAM suffers from a large increase in leakage current. A model for this effect is developed which compares closely with the measurements.« less

Pros and cons of symmetrical dual-k spacer technology in hybrid FinFETs

NASA Astrophysics Data System (ADS)

Pradhan, K. P.; Andrade, M. G. C.; Sahu, P. K.

2016-12-01

The symmetrical dual-k spacer technology in hybrid FinFETs has been widely explored for better electrostatic control of the fin-based devices in nanoscale region. Since, high-k tangible spacer materials are broadly became a matter of study due to their better immunity to the short channel effects (SCEs) in nano devices. However, the only cause that restricts the circuit designers from using high-k spacer is the unreasonable increasing fringing capacitances. This work quantitatively analyzed the benefits and drawbacks of considering two different dielectric spacer materials symmetrically in either sides of the channel for the hybrid device. From the demonstrated results, the inclusion of high-k spacer predicts an effective reduction in off-state leakage along with an improvement in drive current. However, these devices have paid the cost in terms of a high total gate-to-gate capacitance (Cgg) that consequently results poor cutoff frequency (fT) and delay.

Advanced detectors and signal processing for bubble memories

NASA Technical Reports Server (NTRS)

Kryder, M. H.; Rasky, P. H. L.; Greve, D. W.

1985-01-01

The feasibility of combining silicon and magnetic bubble technologies is demonstrated. Results of bubble film annealing indicate that a low temperature silicon on garnet technology is the most likely one to succeed commercially. Annealing ambients are also shown to have a major effect on the magnetic properties of bubble films. Functional MOSFETs were fabricated on bubble films coated with thick (approximately 1 micron) SiO2 layers. The two main problems with these silicon on garnet MOSFETs are low electron mobilities and large gate leakage currents. Results indicate that the laser recrystallized silicon and gate oxide (SiO2) layers are contaminated. The data suggest that part of the contaminating ions originate in the sputtered oxide spacer layer and part originates in the bubble film itself. A diffusion barrier, such as silicon nitride, placed between the bubble film and the silicon layer should eliminate the contamination induced problem.

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors

PubMed Central

Fan, Ching-Lin; Shang, Ming-Chi; Wang, Shea-Jue; Hsia, Mao-Yuan; Lee, Win-Der; Huang, Bohr-Ran

2017-01-01

In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W). PMID:28773101

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors.

PubMed

Fan, Ching-Lin; Shang, Ming-Chi; Wang, Shea-Jue; Hsia, Mao-Yuan; Lee, Win-Der; Huang, Bohr-Ran

2017-07-03

In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W).

Recessed Slant Gate AlGaN/GaN High Electron Mobility Transistors with 20.9 W/mm at 10 GHz

NASA Astrophysics Data System (ADS)

Pei, Yi; Chu, Rongming; Fichtenbaum, Nicholas A.; Chen, Zhen; Brown, David; Shen, Likun; Keller, Stacia; DenBaars, Steven P.; Mishra, Umesh K.

2007-12-01

A recessed slant gate processing has been used in AlGaN/GaN high electron mobility transistors (HEMTs) to mitigate the electric field, minimize the dispersion and increase the breakdown voltage. More than one order of magnitude of decrease in gate leakage has been observed by recessing the slant gate. For a 0.65 μm gate-length device, an extrinsic fT of 18 GHz and extrinsic fMAX of 52 GHz at a drain bias of 25 V were achieved. At 10 GHz, a state-of-the-art power density of 20.9 W/mm, with a power-added efficiency (PAE) of 40% at a drain bias of 83 V, was demonstrated.

Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure

PubMed Central

Khan, Z. N.; Ahmed, S.; Ali, M.

2016-01-01

Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application. PMID:27571412

Electrical characteristics and thermal stability of n+ polycrystalline- Si/ZrO2/SiO2/Si metal-oxide-semiconductor capacitors

NASA Astrophysics Data System (ADS)

Lim, Kwan-Yong; Park, Dae-Gyu; Cho, Heung-Jae; Kim, Joong-Jung; Yang, Jun-Mo; Ii, Choi-Sang; Yeo, In-Seok; Park, Jin Won

2002-01-01

We have investigated the thermal stability of n+ polycrystalline-Si(poly-Si)/ZrO2(50-140 Å)/SiO2(7 Å)/p-Si metal-oxide-semiconductor (MOS) capacitors via electrical and material characterization. The ZrO2 gate dielectric was prepared by atomic layer chemical vapor deposition using ZrCl4 and H2O vapor. Capacitance-voltage hysteresis as small as ˜12 mV with the flatband voltage of -0.5 V and the interface trap density of ˜5×1010cm-2 eV-1 were attained with activation anneal at 750 °C. A high level of gate leakage current was observed at the activation temperatures over 750 °C and attributed to the interfacial reaction of poly-Si and ZrO2 during the poly-Si deposition and the following high temperature anneal. Because of this, the ZrO2 gate dielectric is incompatible with the conventional poly-Si gate process. In the MOS capacitors having a smaller active area (<50×50 μm2), fortunately, the electrical degradation by further severe silicidation does not occur up to an 800 °C anneal in N2 for 30 min.

Nano-Transistor Modeling: Two Dimensional Green's Function Method

NASA Technical Reports Server (NTRS)

Svizhenko, Alexei; Anantram, M. P.; Govindan, T. R.; Biegel, Bryan

2001-01-01

Two quantum mechanical effects that impact the operation of nanoscale transistors are inversion layer energy quantization and ballistic transport. While the qualitative effects of these features are reasonably understood, a comprehensive study of device physics in two dimensions is lacking. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL (Drain Induced Barrier Lowering), and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density-gradient and quantum-corrected MEDICI).

Normally-off p-GaN/AlGaN/GaN high electron mobility transistors using hydrogen plasma treatment

NASA Astrophysics Data System (ADS)

Hao, Ronghui; Fu, Kai; Yu, Guohao; Li, Weiyi; Yuan, Jie; Song, Liang; Zhang, Zhili; Sun, Shichuang; Li, Xiajun; Cai, Yong; Zhang, Xinping; Zhang, Baoshun

2016-10-01

In this letter, we report a method by introducing hydrogen plasma treatment to realize normally-off p-GaN/AlGaN/GaN HEMT devices. Instead of using etching technology, hydrogen plasma was adopted to compensate holes in the p-GaN above the two dimensional electron gas (2DEG) channel to release electrons in the 2DEG channel and form high-resistivity area to reduce leakage current and increase gate control capability. The fabricated p-GaN/AlGaN/GaN HEMT exhibits normally-off operation with a threshold voltage of 1.75 V, a subthreshold swing of 90 mV/dec, a maximum transconductance of 73.1 mS/mm, an ON/OFF ratio of 1 × 107, a breakdown voltage of 393 V, and a maximum drain current density of 188 mA/mm at a gate bias of 6 V. The comparison of the two processes of hydrogen plasma treatment and p-GaN etching has also been made in this work.

Eco-Friendly and Biodegradable Biopolymer Chitosan/Y₂O₃ Composite Materials in Flexible Organic Thin-Film Transistors.

PubMed

Du, Bo-Wei; Hu, Shao-Ying; Singh, Ranjodh; Tsai, Tsung-Tso; Lin, Ching-Chang; Ko, Fu-Hsiang

2017-09-03

The waste from semiconductor manufacturing processes causes serious pollution to the environment. In this work, a non-toxic material was developed under room temperature conditions for the fabrication of green electronics. Flexible organic thin-film transistors (OTFTs) on plastic substrates are increasingly in demand due to their high visible transmission and small size for use as displays and wearable devices. This work investigates and analyzes the structured formation of aqueous solutions of the non-toxic and biodegradable biopolymer, chitosan, blended with high-k-value, non-toxic, and biocompatible Y₂O₃ nanoparticles. Chitosan thin films blended with Y₂O₃ nanoparticles were adopted as the gate dielectric thin film in OTFTs, and an improvement in the dielectric properties and pinholes was observed. Meanwhile, the on/off current ratio was increased by 100 times, and a low leakage current was observed. In general, the blended chitosan/Y₂O₃ thin films used as the gate dielectric of OTFTs are non-toxic, environmentally friendly, and operate at low voltages. These OTFTs can be used on surfaces with different curvature radii because of their flexibility.

Recovery in dc and rf performance of off-state step-stressed AlGaN/GaN high electron mobility transistors with thermal annealing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Byung-Jae; Hwang, Ya-Hsi; Ahn, Shihyun

The recovery effects of thermal annealing on dc and rf performance of off-state step-stressed AlGaN/GaN high electron mobility transistors were investigated. After stress, reverse gate leakage current and sub-threshold swing increased and drain current on-off ratio decreased. However, these degradations were completely recovered after thermal annealing at 450 °C for 10 mins for devices stressed either once or twice. The trap densities, which were estimated by temperature-dependent drain-current sub-threshold swing measurements, increased after off-state step-stress and were reduced after subsequent thermal annealing. In addition, the small signal rf characteristics of stressed devices were completely recovered after thermal annealing.

Analysis of source/drain engineered 22nm FDSOI using high-k spacers

NASA Astrophysics Data System (ADS)

Malviya, Abhishek Kumar; Chauhan, R. K.

2018-04-01

While looking at the current classical scaling of devices there are lots of short channel effects come into consideration. In this paper, a novel device structure is proposed that is an improved structure of Modified Source(MS) FDSOI in terms of better electrical performance, on current and reduced off state leakage current with a higher Ion/Ioff ratio that helps in fast switching of low power nano electronic devices. Proposed structure has Modified drain and source regions with two different type to doping profile at 22nm gate length. In the upper part of engineered region (MD and MS) the doping concentration is kept high and less in the lower region. The purpose was to achieve low parasitic capacitance in source and drain region by reducing doping concentration [1].

The Current Collapse in AlGaN/GaN High-Electron Mobility Transistors Can Originate from the Energy Relaxation of Channel Electrons?

PubMed Central

Mao, Ling-Feng; Ning, Huan-Sheng; Wang, Jin-Yan

2015-01-01

Influence of the energy relaxation of the channel electrons on the performance of AlGaN/GaN high-electron mobility transistors (HEMTs) has been investigated using self-consistent solution to the coupled Schrödinger equation and Poisson equation. The first quantized energy level in the inversion layer rises and the average channel electron density decreases when the channel electric field increases from 20 kV/cm to 120 kV/cm. This research also demonstrates that the energy relaxation of the channel electrons can lead to current collapse and suggests that the energy relaxation should be considered in modeling the performance of AlGaN/GaN HEMTs such as, the gate leakage current, threshold voltage, source-drain current, capacitance-voltage curve, etc. PMID:26039589

The Current Collapse in AlGaN/GaN High-Electron Mobility Transistors Can Originate from the Energy Relaxation of Channel Electrons?

PubMed

Mao, Ling-Feng; Ning, Huan-Sheng; Wang, Jin-Yan

2015-01-01

Influence of the energy relaxation of the channel electrons on the performance of AlGaN/GaN high-electron mobility transistors (HEMTs) has been investigated using self-consistent solution to the coupled Schrödinger equation and Poisson equation. The first quantized energy level in the inversion layer rises and the average channel electron density decreases when the channel electric field increases from 20 kV/cm to 120 kV/cm. This research also demonstrates that the energy relaxation of the channel electrons can lead to current collapse and suggests that the energy relaxation should be considered in modeling the performance of AlGaN/GaN HEMTs such as, the gate leakage current, threshold voltage, source-drain current, capacitance-voltage curve, etc.

The role of cleaning conditions and epitaxial layer structure on reliability of Sc 2O 3 and MgO passivation on AlGaN/GaN HEMTS

NASA Astrophysics Data System (ADS)

Luo, B.; Mehandru, R. M.; Kim, Jihyun; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Fitch, R. C.; Gillespie, J.; Dellmer, R.; Jenkins, T.; Sewell, J.; Via, D.; Crespo, A.

2002-12-01

The effect of layer structure (GaN versus AlGaN cap) and cleaning procedure prior to Sc 2O 3 or MgO deposition at 100 °C were examined for their effects on the long-term bias-stress stability of AlGaN/GaN high electron mobility transistors (HEMTs). Surface cleaning by itself was not sufficient to prevent current collapse in the devices. The forward and reverse gate leakage currents were decreased under most conditions upon deposition of the oxide passivation layers. After ≈13 h of bias-stressing, the MgO-passivated HEMTs retain ⩾90% their initial drain-source current. The Sc 2O 3-passivated devices retained ˜80% recovery of the current under the same conditions.

Feedback-tuned, noise resilient gates for encoded spin qubits

NASA Astrophysics Data System (ADS)

Bluhm, Hendrik

Spin 1/2 particles form native two level systems and thus lend themselves as a natural qubit implementation. However, encoding a single qubit in several spins entails benefits, such as reducing the resources necessary for qubit control and protection from certain decoherence channels. While several varieties of such encoded spin qubits have been implemented, accurate control remains challenging, and leakage out of the subspace of valid qubit states is a potential issue. Optimal performance typically requires large pulse amplitudes for fast control, which is prone to systematic errors and prohibits standard control approaches based on Rabi flopping. Furthermore, the exchange interaction typically used to electrically manipulate encoded spin qubits is inherently sensitive to charge noise. I will discuss all-electrical, high-fidelity single qubit operations for a spin qubit encoded in two electrons in a GaAs double quantum dot. Starting from a set of numerically optimized control pulses, we employ an iterative tuning procedure based on measured error syndromes to remove systematic errors.Randomized benchmarking yields an average gate fidelity exceeding 98 % and a leakage rate into invalid states of 0.2 %. These gates exhibit a certain degree of resilience to both slow charge and nuclear spin fluctuations due to dynamical correction analogous to a spin echo. Furthermore, the numerical optimization minimizes the impact of fast charge noise. Both types of noise make relevant contributions to gate errors. The general approach is also adaptable to other qubit encodings and exchange based two-qubit gates.

Impact of scaling voltage and size on the performance of Side-contacted Field Effect Diode

NASA Astrophysics Data System (ADS)

Touchaei, Behnam Jafari; Manavizadeh, Negin

2018-05-01

Side-contacted Fild Effect Diode (S-FED), with low leakage current and high Ion/Ioff ratio, has been recently introduced to suppress short channel effects in nanoscale regime. The voltage and size scalability of S-FEDs and effects on the power consumption, propagation delay time, and power delay product have been studied in this article. The most attractive properties are related to channel length to channel thickness ratio in the S-FED which reduces in comparison with MOSFET significantly, while gates control over the channel improve and the off-state current reduces dramatically. This promising advantage is not only capable to improve important S-FED's characteristics such as subthreshold slope but also eliminate Latch-up and floating body effect.

Radiation hardness of β-Ga2O3 metal-oxide-semiconductor field-effect transistors against gamma-ray irradiation

NASA Astrophysics Data System (ADS)

Wong, Man Hoi; Takeyama, Akinori; Makino, Takahiro; Ohshima, Takeshi; Sasaki, Kohei; Kuramata, Akito; Yamakoshi, Shigenobu; Higashiwaki, Masataka

2018-01-01

The effects of ionizing radiation on β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated. A gamma-ray tolerance as high as 1.6 MGy(SiO2) was demonstrated for the bulk Ga2O3 channel by virtue of weak radiation effects on the MOSFETs' output current and threshold voltage. The MOSFETs remained functional with insignificant hysteresis in their transfer characteristics after exposure to the maximum cumulative dose. Despite the intrinsic radiation hardness of Ga2O3, radiation-induced gate leakage and drain current dispersion ascribed respectively to dielectric damage and interface charge trapping were found to limit the overall radiation hardness of these devices.

Noise characterization of enhancement-mode AlGaN graded barrier MIS-HEMT devices

NASA Astrophysics Data System (ADS)

Mohanbabu, A.; Saravana Kumar, R.; Mohankumar, N.

2017-12-01

This paper reports a systematic theoretical study on the microwave noise performance of graded AlGaN/GaN metal-insulator semiconductor high-electron mobility transistors (MIS-HEMTs) built on an Al2O3 substrate. The HfAlOx/AlGaN/GaN MIS-HEMT devices designed for this study show an outstanding small signal analog/RF and noise performance. The results on 1 μm gate length device show an enhancement mode operation with threshold voltage, VT = + 5.3 V, low drain leakage current, Ids,LL in the order of 1 × 10-9 A/mm along with high current gain cut-off frequency, fT of 17 GHz and maximum oscillation frequency fmax of 47 GHz at Vds = 10 V. The device Isbnd V and low-frequency noise estimation of the gate and drain noise spectral density and their correlation are evaluated using a Green's function method under different biasing conditions. The devices show a minimum noise figure (NFmin) of 1.053 dB in combination with equivalent noise resistance (Rn) of 23 Ω at 17 GHz, at Vgs = 6 V and Vds = 5 V which is relatively low and is suitable for broad-band low-noise amplifiers. This study shows that the graded AlGaN MIS-HEMT with HfAlOX gate insulator is appropriate for application requiring high-power and low-noise.

High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

PubMed

Jaehnike, Felix; Pham, Duy Vu; Anselmann, Ralf; Bock, Claudia; Kunze, Ulrich

2015-07-01

A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications.

Electrical Characterization of Semiconductor and Dielectric Materials with a Non-Damaging FastGateTM Probe

NASA Astrophysics Data System (ADS)

Robert, Hillard; William, Howland; Bryan, Snyder

2002-03-01

Determination of the electrical properties of semiconductor materials and dielectrics is highly desirable since these correlate best to final device performance. The properties of SiO2 and high k dielectrics such as Equivalent Oxide Thickness(EOT), Interface Trap Density(Dit), Oxide Effective Charge(Neff), Flatband Voltage Hysteresis(Delta Vfb), Threshold Voltage(VT) and, bulk properties such as carrier density profile and channel dose are all important parameters that require monitoring during front end processing. Conventional methods for determining these parameters involve the manufacturing of polysilicon or metal gate MOS capacitors and subsequent measurements of capacitance-voltage(CV) and/or current-voltage(IV). These conventional techniques are time consuming and can introduce changes to the materials being monitored. Also, equivalent circuit effects resulting from excessive leakage current, series resistance and stray inductance can introduce large errors in the measured results. In this paper, a new method is discussed that provides rapid determination of these critical parameters and is robust against equivalent circuit errors. This technique uses a small diameter(30 micron), elastically deformed probe to form a gate for MOSCAP CV and IV and can be used to measure either monitor wafers or test areas within scribe lines on product wafers. It allows for measurements of dielectrics thinner than 10 Angstroms. A detailed description and applications such as high k dielectrics, will be presented.

High-k dielectric Al2O3 nanowire and nanoplate field effect sensors for improved pH sensing

PubMed Central

Reddy, Bobby; Dorvel, Brian R.; Go, Jonghyun; Nair, Pradeep R.; Elibol, Oguz H.; Credo, Grace M.; Daniels, Jonathan S.; Chow, Edmond K. C.; Su, Xing; Varma, Madoo; Alam, Muhammad A.

2011-01-01

Over the last decade, field-effect transistors (FETs) with nanoscale dimensions have emerged as possible label-free biological and chemical sensors capable of highly sensitive detection of various entities and processes. While significant progress has been made towards improving their sensitivity, much is yet to be explored in the study of various critical parameters, such as the choice of a sensing dielectric, the choice of applied front and back gate biases, the design of the device dimensions, and many others. In this work, we present a process to fabricate nanowire and nanoplate FETs with Al2O3 gate dielectrics and we compare these devices with FETs with SiO2 gate dielectrics. The use of a high-k dielectric such as Al2O3 allows for the physical thickness of the gate dielectric to be thicker without losing sensitivity to charge, which then reduces leakage currents and results in devices that are highly robust in fluid. This optimized process results in devices stable for up to 8 h in fluidic environments. Using pH sensing as a benchmark, we show the importance of optimizing the device bias, particularly the back gate bias which modulates the effective channel thickness. We also demonstrate that devices with Al2O3 gate dielectrics exhibit superior sensitivity to pH when compared to devices with SiO2 gate dielectrics. Finally, we show that when the effective electrical silicon channel thickness is on the order of the Debye length, device response to pH is virtually independent of device width. These silicon FET sensors could become integral components of future silicon based Lab on Chip systems. PMID:21203849

Electric Field Controlled Spin Interference in a System with Rashba Spin-Orbit Coupling

DTIC Science & Technology

2016-08-29

conducting semi-circular channels. The strength of the confinement energy on the quantum dots is tuned by gate potentials that allow “ leakage ” of electrons...interesting applications. A detectable SO effect requires a strong electric field (as well as a semiconductor host for the electrons that satisfies a...quantum dots (which may be considered identical) are confined by an electrostatically created potential that can be tuned to allow “ leakage ” of

Asymmetric underlap optimization of sub-10nm finfets for realizing energy-efficient logic and robust memories

NASA Astrophysics Data System (ADS)

Akkala, Arun Goud

Leakage currents in CMOS transistors have risen dramatically with technology scaling leading to significant increase in standby power consumption. Among the various transistor candidates, the excellent short channel immunity of Silicon double gate FinFETs have made them the best contender for successful scaling to sub-10nm nodes. For sub-10nm FinFETs, new quantum mechanical leakage mechanisms such as direct source to drain tunneling (DSDT) of charge carriers through channel potential energy barrier arising due to proximity of source/drain regions coupled with the high transport direction electric field is expected to dominate overall leakage. To counter the effects of DSDT and worsening short channel effects and to maintain Ion/ Ioff, performance and power consumption at reasonable values, device optimization techniques are necessary for deeply scaled transistors. In this work, source/drain underlapping of FinFETs has been explored using quantum mechanical device simulations as a potentially promising method to lower DSDT while maintaining the Ion/ Ioff ratio at acceptable levels. By adopting a device/circuit/system level co-design approach, it is shown that asymmetric underlapping, where the drain side underlap is longer than the source side underlap, results in optimal energy efficiency for logic circuits in near-threshold as well as standard, super-threshold operating regimes. In addition, read/write conflict in 6T SRAMs and the degradation in cell noise margins due to the low supply voltage can be mitigated by using optimized asymmetric underlapped n-FinFETs for the access transistor, thereby leading to robust cache memories. When gate-workfunction tuning is possible, using asymmetric underlapped n-FinFETs for both access and pull-down devices in an SRAM bit cell can lead to high-speed and low-leakage caches. Further, it is shown that threshold voltage degradation in the presence of Hot Carrier Injection (HCI) is less severe in asymmetric underlap n-FinFETs. A lifetime projection is carried out assuming that HCI is the major degradation mechanism and it is shown that a 3.4x improvement in device lifetime is possible over symmetric underlapped n-FinFET.

Amorphous indium-gallium-zinc-oxide thin-film transistors using organic-inorganic hybrid films deposited by low-temperature plasma-enhanced chemical vapor deposition for all dielectric layers

NASA Astrophysics Data System (ADS)

Hsu, Chao-Jui; Chang, Ching-Hsiang; Chang, Kuei-Ming; Wu, Chung-Chih

2017-01-01

We investigated the deposition of high-performance organic-inorganic hybrid dielectric films by low-temperature (close to room temperature) inductively coupled plasma chemical vapor deposition (ICP-CVD) with hexamethyldisiloxane (HMDSO)/O2 precursor gas. The hybrid films exhibited low leakage currents and high breakdown fields, suitable for thin-film transistor (TFT) applications. They were successfully integrated into the gate insulator, the etch-stop layer, and the passivation layer for bottom-gate staggered amorphous In-Ga-Zn-O (a-IGZO) TFTs having the etch-stop configuration. With the double-active-layer configuration having a buffer a-IGZO back-channel layer grown in oxygen-rich atmosphere for better immunity against plasma damage, the etch-stop-type bottom-gate staggered a-IGZO TFTs with good TFT characteristics were successfully demonstrated. The TFTs showed good field-effect mobility (μFE), threshold voltage (V th), subthreshold swing (SS), and on/off ratio (I on/off) of 7.5 cm2 V-1 s-1, 2.38 V, 0.38 V/decade, and 2.2 × 108, respectively, manifesting their usefulness for a-IGZO TFTs.

Experimental Study of Floating-Gate-Type Metal-Oxide-Semiconductor Capacitors with Nanosize Triangular Cross-Sectional Tunnel Areas for Low Operating Voltage Flash Memory Application

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Guo, Ruofeng; Kamei, Takahiro; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Hayashida, Tetsuro; Sakamoto, Kunihiro; Ogura, Atsushi; Masahara, Meishoku

2012-06-01

The floating-gate (FG)-type metal-oxide-semiconductor (MOS) capacitors with planar (planar-MOS) and three-dimensional (3D) nanosize triangular cross-sectional tunnel areas (3D-MOS) have successfully been fabricated by introducing rapid thermal oxidation (RTO) and postdeposition annealing (PDA), and their electrical characteristics between the control gate (CG) and FG have been systematically compared. It was experimentally found in both planar- and 3D-MOS capacitors that the uniform and higher breakdown voltages are obtained by introducing RTO owing to the high-quality thermal oxide formation on the surface and etched edge regions of the n+ polycrystalline silicon (poly-Si) FG, and the leakage current is highly suppressed after PDA owing to the improved quality of the tetraethylorthosilicate (TEOS) silicon dioxide (SiO2) between CG and FG. Moreover, a lower breakdown voltage between CG and FG was obtained in the fabricated 3D-MOS capacitors as compared with that of planar-MOS capacitors thanks to the enhanced local electric field at the tips of triangular tunnel areas. The developed nanosize triangular cross-sectional tunnel area is useful for the fabrication of low operating voltage flash memories.

A Simple Method for High-Performance, Solution-Processed, Amorphous ZrO2 Gate Insulator TFT with a High Concentration Precursor

PubMed Central

Cai, Wei; Zhu, Zhennan; Wei, Jinglin; Fang, Zhiqiang; Zheng, Zeke; Zhou, Shangxiong; Peng, Junbiao; Lu, Xubing

2017-01-01

Solution-processed high-k dielectric TFTs attract much attention since they cost relatively little and have a simple fabrication process. However, it is still a challenge to reduce the leakage of the current density of solution-processed dielectric TFTs. Here, a simple solution method is presented towards enhanced performance of ZrO2 films by intentionally increasing the concentration of precursor. The ZrO2 films not only exhibit a low leakage current density of 10−6 A/cm2 at 10 V and a breakdown field of 2.5 MV/cm, but also demonstrate a saturation mobility of 12.6 cm2·V−1·s−1 and a Ion/Ioff ratio of 106 in DC pulse sputtering IGZO-TFTs based on these films. Moreover, the underlying mechanism of influence of precursor concentration on film formation is presented. Higher concentration precursor results in a thicker film within same coating times with reduced ZrO2/IGZO interface defects and roughness. It shows the importance of thickness, roughness, and annealing temperature in solution-processed dielectric oxide TFT and provides an approach to precisely control solution-processed oxide films thickness. PMID:28825652

A Simple Method for High-Performance, Solution-Processed, Amorphous ZrO₂ Gate Insulator TFT with a High Concentration Precursor.

PubMed

Cai, Wei; Zhu, Zhennan; Wei, Jinglin; Fang, Zhiqiang; Ning, Honglong; Zheng, Zeke; Zhou, Shangxiong; Yao, Rihui; Peng, Junbiao; Lu, Xubing

2017-08-21

Solution-processed high-k dielectric TFTs attract much attention since they cost relatively little and have a simple fabrication process. However, it is still a challenge to reduce the leakage of the current density of solution-processed dielectric TFTs. Here, a simple solution method is presented towards enhanced performance of ZrO₂ films by intentionally increasing the concentration of precursor. The ZrO₂ films not only exhibit a low leakage current density of 10 -6 A/cm² at 10 V and a breakdown field of 2.5 MV/cm, but also demonstrate a saturation mobility of 12.6 cm²·V -1 ·s -1 and a I on /I off ratio of 10⁶ in DC pulse sputtering IGZO-TFTs based on these films. Moreover, the underlying mechanism of influence of precursor concentration on film formation is presented. Higher concentration precursor results in a thicker film within same coating times with reduced ZrO₂/IGZO interface defects and roughness. It shows the importance of thickness, roughness, and annealing temperature in solution-processed dielectric oxide TFT and provides an approach to precisely control solution-processed oxide films thickness.

Fabrication and characterization of heterojunction transistors

NASA Astrophysics Data System (ADS)

Lo, Chien-Fong

2011-12-01

Submircon emitter finger high-speed double heterojunction InAlAs/InGaAsSb/InGaAs bipolar transistors (DHBTs) and a variety of nitride high electron mobility transistors (HEMTs) including AlGaN/GaN, InAlN/GaN, and AlN/GaN were fabricated and characterized. DHBT structures were grown by solid source molecular beam epitaxy (SSMBE) on Fe-doped semiinsulating InP substrates and nitride HEMTs were grown with a metal organic chemical vapor deposition (MOCVD) system on sapphire or SiC substrates. AlN/GaN HEMTs were grown with a RF-VMBE on sapphire substrates. Ultra low base contact resistance of 3.7 x 10-7 ohm-cm2 after 1 min 250¢XC thermal treatment on noval InGaAsSb base of DHBTs was achieved and a long-term thermal stability of base metallization was studied. Regarding small scale DHBT fabrication, tri-layer system was introduced to improve the resolution for submicron emitter patterning and help to pile up a thicker emitter metal stack; guard-ring technique was applied around the emitter periphery in order to preserve the current gain at small emitter dimensions. Ultra low turn-on voltage and high current gain can be realized with InGaAsSb-base DHBTs as compared to the conventional InGaAs-base DHBTs. A peak current gain cutoff frequency (fT) of 268 GHz and power gain cutoff frequency (fmax) of 485 GHz were achieved. GaN-based HEMTs herein were fabricated with gate lengths from 400 nm to 1im, and were deposited Ti/Al/Ni/Au as their Ohmic contact metallization. Effects of the Ohmic contact annealing for lattice-matched InAlN/GaN HEMTs with and without a thin GaN cap layer were exhibited and their optimal annealing temperature were obtained. A maximum drain current of 1.3 A/mm and an extrinsic transconductance of 366 mS/mm were demonstrated for InAlN/GaN HEMTs with the shortest gate length. A unity-gain cutoff frequency (fT) of 69 GHz and a maximum frequency of oscillation (fmax) of 80 GHz for InAlN/GaN HEMTs were extracted from measured scattering parameters. Passivation is one of the most important parts in device processing for preventing degradation from various environmental conditions and promising a better device performance. Simply, ozone treatment of AlN on AlN/GaN heterostructures produced effective aluminum oxide surface passivation and chemical resistance to the AZ positive photoresist developer used for subsequent device fabrication. Metal oxide semiconductor diode-like gate current-voltage characteristics and minimal drain current degradation during gate pulse measurements were observed. With an additional oxygen plasma treatment on the gate area prior to the gate metal deposition, enhancement-mode AlN/GaN HEMTs were realized. In addition, for AlGaN/GaN HEMTs in high electrical field applications, a high-dielectric-strength SiNx passivation over an optimum thickness was needed to suppress surface flashover during a high voltage or high power operation. An excellent isolation blocking voltage of 900 V with a leakage current at 1 muA/mm was obtained across a nitrogen-implanted isolation-gap of 10 mum between two Ohmic pads. The radiation hardness of HBTs and HEMTs is one of the critical factors that need to be established for military, space, and nuclear industry applications. The effects of proton radiation on the dc performance of InAlAs/InGaAsSb/InGaAs HBTs and AlN/GaN HEMTs were investigated. Both of these devices showed a remarkable resistance to high energy protoninduced degradation and appeared very promising for terrestrial or space-borne applications. The proton-irradiated devices with a dose of 2 x 1011 cm-2 (estimated to be equivalent to more than 40 years of exposure in low-earth orbit) showed only small changes in dc transfer characteristics, threshold voltage shift, and gate-lag with a high frequency pulse on the gate of the HEMTs and showed small changes in junction ideality factor, generation recombination leakage current, and output conductance for the HBTs. The effect the gate metallization on the nitride HEMT reliability was also examined. By replacing the conventional Ni/Au gate metallization with Pt/Ti/Au, the critical voltage for degradation of AlGaN/GaN HEMTs during off-state biasing stress was significantly improved from -55 V to over larger than -100 V. Besides the irradiation or high voltage stresses, the effects of ambient on the Pt-gated HEMT sensor for gas sensing application were also explored. For the hydrogen sensing, the sensitivity decreased proportional to the relative humidity but the presence of humidity dramatically improved the sensor recovery characteristics after exposure to the hydrogen ambient.

Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs

NASA Astrophysics Data System (ADS)

Lahgere, Avinash; Panchore, Meena; Singh, Jawar

2016-08-01

In this paper, we propose a novel tunnel field-effect transistor (TFET) based on charge plasma (CP) and negative capacitance (NC) for enhanced ON-current and steep subthreshold swing (SS). It is shown that the replacement of standard insulator for gate stack with ferroelectric (Fe) insulator yields NC and high electric field at the tunneling junction. Similarly, use of dopingless silicon nanowire with CP has a genuine advantage in process engineering. Therefore, combination of both technology boosters (CP and NC) in the proposed device enable low thermal budget, process variation immunity, and excellent electrical characteristics in contrast with its counterpart dopingless (DL) TFET (DL-TFET). An optimized device accomplishes an impressive 10× improvement in on-current, 100× reduced leakage current, 3× more transconductance (gm), and on-off current ratio of ∼1011 as compared to DL-TFET.

Structured back gates for high-mobility two-dimensional electron systems using oxygen ion implantation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berl, M., E-mail: mberl@phys.ethz.ch; Tiemann, L.; Dietsche, W.

2016-03-28

We present a reliable method to obtain patterned back gates compatible with high mobility molecular beam epitaxy via local oxygen ion implantation that suppresses the conductivity of an 80 nm thick silicon doped GaAs epilayer. Our technique was optimized to circumvent several constraints of other gating and implantation methods. The ion-implanted surface remains atomically flat which allows unperturbed epitaxial overgrowth. We demonstrate the practical application of this gating technique by using magneto-transport spectroscopy on a two-dimensional electron system (2DES) with a mobility exceeding 20 × 10{sup 6} cm{sup 2}/V s. The back gate was spatially separated from the Ohmic contacts of the 2DES,more » thus minimizing the probability for electrical shorts or leakage and permitting simple contacting schemes.« less

Characterization of electrokinetic gating valve in microfluidic channels.

PubMed

Zhang, Guiseng; Du, Wei; Liu, Bi-Feng; Hisamoto, Hideaki; Terabe, Shigeru

2007-02-12

Electrokinetic gating, functioning as a micro-valve, has been widely employed in microfluidic chips for sample injection and flow switch. Investigating its valving performance is fundamentally vital for microfluidics and microfluidics-based chemical analysis. In this paper, electrokinetic gating valve in microchannels was evaluated using optical imaging technique. Microflow profiles at channels junction were examined, revealing that molecular diffusion played a significant role in the valving disable; which could cause analyte leakage in sample injection. Due to diffusion, the analyte crossed the interface of the analyte flow and gating flow, and then formed a cometic tail-like diffusion area at channels junction. From theoretical calculation and some experimental evidences, the size of the area was related to the diffusion coefficient and the velocity of analytes. Additionally, molecular diffusion was also believed to be another reason of sampling bias in gated injection.

Poly(methyl methacrylate) as a self-assembled gate dielectric for graphene field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sanne, A.; Movva, H. C. P.; Kang, S.

We investigate poly(methyl methacrylate) (PMMA) as a low thermal budget organic gate dielectric for graphene field effect-transistors (GFETs) based on a simple process flow. We show that high temperature baking steps above the glass transition temperature (∼130 °C) can leave a self-assembled, thin PMMA film on graphene, where we get a gate dielectric almost for “free” without additional atomic layer deposition type steps. Electrical characterization of GFETs with PMMA as a gate dielectric yields a dielectric constant of k = 3.0. GFETs with thinner PMMA dielectrics have a lower dielectric constant due to decreased polarization arising from neutralization of dipoles and charged carriersmore » as baking temperatures increase. The leakage through PMMA gate dielectric increases with decreasing dielectric thickness and increasing electric field. Unlike conventional high-k gate dielectrics, such low-k organic gate dielectrics are potentially attractive for devices such as the proposed Bilayer pseudoSpin Field-Effect Transistor or flexible high speed graphene electronics.« less

Prototype of IGZO-TFT preamplifier and analog counter for pixel detector

NASA Astrophysics Data System (ADS)

Shimazoe, K.; Koyama, A.; Takahashi, H.; Shindoh, T.; Miyoshi, H.

2017-02-01

IGZO-TFT (Indium Galium Zinc Oxide-Thin Film Transistor) is a promising technology for controlling large display areas and large area sensors because of its very low leakage current in the off state and relatively low cost. IGZO has been used as a switching gate for a large area flat-panel detector. The photon counting capability for X-ray medical imaging has been investigated and expected for low-dose exposure and material determination. Here the design and fabrication of a charge sensitive preamplifier and analog counter using IGZO-TFT processes and its performance are reported for the first time to be used for radiation photon counting applications.

LaAlO{sub 3}/Si capacitors: Comparison of different molecular beam deposition conditions and their impact on electrical properties

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pelloquin, Sylvain; Baboux, Nicolas; Albertini, David

2013-01-21

A study of the structural and electrical properties of amorphous LaAlO{sub 3} (LAO)/Si thin films fabricated by molecular beam deposition (MBD) is presented. Two substrate preparation procedures have been explored namely a high temperature substrate preparation technique-leading to a step and terraces surface morphology-and a chemical HF-based surface cleaning. The LAO deposition conditions were improved by introducing atomic plasma-prepared oxygen instead of classical molecular O{sub 2} in the chamber. An Au/Ni stack was used as the top electrode for its electrical characteristics. The physico-chemical properties (surface topography, thickness homogeneity, LAO/Si interface quality) and electrical performance (capacitance and current versus voltagemore » and TunA current topography) of the samples were systematically evaluated. Deposition conditions (substrate temperature of 550 Degree-Sign C, oxygen partial pressure settled at 10{sup -6} Torr, and 550 W of power applied to the O{sub 2} plasma) and post-depositions treatments were investigated to optimize the dielectric constant ({kappa}) and leakage currents density (J{sub Gate} at Double-Vertical-Line V{sub Gate} Double-Vertical-Line = Double-Vertical-Line V{sub FB}- 1 Double-Vertical-Line ). In the best reproducible conditions, we obtained a LAO/Si layer with a dielectric constant of 16, an equivalent oxide thickness of 8.7 A, and J{sub Gate} Almost-Equal-To 10{sup -2}A/cm{sup 2}. This confirms the importance of LaAlO{sub 3} as an alternative high-{kappa} for ITRS sub-22 nm technology node.« less

Blue Marsh Dam and Reservoir Condition Report. Dam, Outlet Works, Spillway and Bernville Protective Works. Periodic Inspection Report Number 2, September 1979. Schuylkill River Basin. Tulpehocken Creek, Pennsylvania.

DTIC Science & Technology

1980-04-01

Low flow gate in No. I service gate has considerable leakage. Recommend exercising of this small gate to improve seating of its seals. (6) Water ...During periods of low pools (below E1.260), these piezometers indicated ground water elevations above the pool level, while during higher pool levels of...Periodic I year 1981 5th Periodic I year 1982 6th Periodic 1 year 1983 7th Periodic 2 years 1985 8th Periodic 2 years 1987 9th Periodic 5 years 1992

Performance evaluation of bottom gate ZnO based thin film transistors with different W/L ratios for UV sensing

NASA Astrophysics Data System (ADS)

Varma, Tarun; Periasamy, C.; Boolchandani, Dharmendar

2018-02-01

In this paper, we report the simulation, fabrication and characterisation of UV photo-detectors with bottom gate ZnO Thin Film Transistors (TFTs), grown on silicon at room temperature using RF magnetron sputtering process. The static performance of these detectors have been explored by varying the channel lengths (6 μm and 12 μm). The fabricated devices show low leakage currents with threshold voltages of 1.18 & 2.33 V, sub-threshold swings of 13.5 & 12.8 V/dec for channel lengths of 6 μm and 12 μm TFT, respectively. They also exhibit superior electrical characteristics with an ON-OFF ratio of the order of 3. The detector was also tested for device stability, with the transfer characteristics of the TFTs, which got deteriorated mainly by the negative bias-stress. The TFTs were further tested for UV detector applications and found to exhibit good photo-response.

Neutral beam and ICP etching of HKMG MOS capacitors: Observations and a plasma-induced damage model

NASA Astrophysics Data System (ADS)

Kuo, Tai-Chen; Shih, Tzu-Lang; Su, Yin-Hsien; Lee, Wen-Hsi; Current, Michael Ira; Samukawa, Seiji

2018-04-01

In this study, TiN/HfO2/Si metal-oxide-semiconductor (MOS) capacitors were etched by a neutral beam etching technique under two contrasting conditions. The configurations of neutral beam etching technique were specially designed to demonstrate a "damage-free" condition or to approximate "reactive-ion-etching-like" conditions to verify the effect of plasma-induced damage on electrical characteristics of MOS capacitors. The results show that by neutral beam etching (NBE), the interface state density (Dit) and the oxide trapped charge (Qot) were lower than routine plasma etching. Furthermore, the decrease in capacitor size does not lead to an increase in leakage current density, indicating less plasma induced side-wall damage. We present a plasma-induced gate stack damage model which we demonstrate by using these two different etching configurations. These results show that NBE is effective in preventing plasma-induced damage at the high-k/Si interface and on the high-k oxide sidewall and thus improve the electrical performance of the gate structure.

On the design of GaN vertical MESFETs on commercial LED sapphire wafers

NASA Astrophysics Data System (ADS)

Atalla, Mahmoud R. M.; Noor Elahi, Asim M.; Mo, Chen; Jiang, Zhenyu; Liu, Jie; Ashok, S.; Xu, Jian

2016-12-01

Design of GaN-based vertical metal-semiconductor field-effect transistors (MESFETs) on commercial light-emitting-diode (LED) epi-wafers has been proposed and proof of principle devices have been fabricated. In order to better understand the IV curves, these devices have been simulated using the charge transport model. It was found that shrinking the drain pillar size would significantly help in reaching cut-off at much lower gate bias even at high carrier concentration of unintentionally doped GaN and considerable leakage current caused by the Schottky barrier lowering. The realization of these vertical MESFETs on LED wafers would allow their chip-level integration. This would open a way to many intelligent lighting applications like on-chip current regulator and signal regulation/communication in display technology.

Interfacial characteristics and leakage current transfer mechanisms in organometal trihalide perovskite gate-controlled devices via doping of PCBM

NASA Astrophysics Data System (ADS)

Wang, Yucheng; Zhang, Yuming; Liu, Yintao; Pang, Tiqiang; Hu, Ziyang; Zhu, Yuejin; Luan, Suzhen; Jia, Renxu

2017-11-01

Two types of perovskite (with and without doping of PCBM) based metal-oxide-semiconductor (MOS) gate-controlled devices were fabricated and characterized. The study of the interfacial characteristics and charge transfer mechanisms by doping of PCBM were analyzed by material and electrical measurements. Doping of PCBM does not affect the size and crystallinity of perovskite films, but has an impact on carrier extraction in perovskite MOS devices. The electrical hysteresis observed in capacitance-voltage and current-voltage measurements can be alleviated by doping of PCBM. Experimental results demonstrate that extremely low trap densities are found for the perovskite device without doping, while the doped sample leads to higher density of interface state. Three mechanisms including Ohm’s law, trap-filled-limit (TFL) emission, and child’s law were used to analyze possible charge transfer mechanisms. Ohm’s law mechanism is well suitable for charge transfer of both the perovskite MOS devices under light condition at large voltage, while TFL emission well addresses the behavior of charge transfer under dark at small voltage. This change of charge transfer mechanism is attributed to the impact of the ion drift within perovskites.

Low-Power and High-Speed Technique for logic Gates in 20nm Double-Gate FinFET Technology

NASA Astrophysics Data System (ADS)

Priydarshi, A.; Chattopadhyay, M. K.

2016-10-01

The FinFET is the leading example of multigate MOSFETS to substitute conventional single gate MOSFETs for ultimate scaling [1], The FinFET structure is a combination of a thin channel region and a double gate to suppress the short channel effects (SCEs) and Vthvariation [2], By using FinFET,figure of merits viz, ION, IOFF, output resistance, propagation delay, noise margin and leakage power, can be improved for ultra low power and high performance applications[3]. In this paper, a new high speed low power dynamic circuit design technique has been proposed using 20nm FinFETs. By applying the appropriate clock and sleep signal to the back gates of the FinFETs, the proposed circuit can efficiently control the dynamic power, During the pre-charging period, Vth of PMOS is controlled low so that a fast precharging can occur;

Driving qubit phase gates with sech shaped pulses

NASA Astrophysics Data System (ADS)

Long, Junling; Ku, Hsiang-Sheng; Wu, Xian; Lake, Russell; Barnes, Edwin; Economou, Sophia; Pappas, David

As shown in 1932 by Rozen and Zener, the Rabi model has a unique solution whereby, for a given pulse length or amplitude, a sech(t/sigma) shaped pulse can be used to drive complete oscillations around the Bloch sphere that are independent of detuning with only a resultant detuning-dependent phase accumulation. Using this property, single qubit phase gates and two-qubit CZ gates have been proposed. In this work we explore the effect of different drive pulse shapes, i.e. square, Gaussian, and sech, as a function of detuning for Rabi oscillations of a superconducting transmon qubit. An arbitrary, single-qubit phase gate is demonstrated with the sech(t/sigma) pulse, and full tomography is performed to extract the fidelity. This is the first step towards high fidelity, low leakage two qubit CZ gates, and illustrates the efficacy of using analytic solutions of the qubit drive prior to optimal pulse shaping.

Two-qubit gates and coupling with low-impedance flux qubits

NASA Astrophysics Data System (ADS)

Chow, Jerry; Corcoles, Antonio; Rigetti, Chad; Rozen, Jim; Keefe, George; Rothwell, Mary-Beth; Rohrs, John; Borstelmann, Mark; Divincenzo, David; Ketchen, Mark; Steffen, Matthias

2011-03-01

We experimentally demonstrate the coupling of two low-impedance flux qubits mediated via a transmission line resonator. We explore the viability of experimental coupling protocols which involve selective microwave driving on the qubits independently as well as fast frequency tuning through on-chip flux-bias. Pulse-shaping techniques for single-qubit and two-qubit gates are employed for reducing unwanted leakage and phase errors. A joint readout through the transmission line resonator is used for characterizing single-qubit and two-qubit states.

High-voltage lateral double-implanted MOSFETs implemented on high-purity semi-insulating 4H-SiC substrates with gate field plates

NASA Astrophysics Data System (ADS)

Seok, Ogyun; Kim, Hyoung Woo; Moon, Jeong Hyun; Lee, Hyun-Su; Bahng, Wook

2018-06-01

Lateral double-implanted MOSFETs (LDIMOSFETs) fabricated on on-axis high-purity semi-insulating (HPSI) 4H-SiC substrates with gate field plates have been demonstrated for the enhancement of reverse blocking capability. The effects of gate field plate on LDIMOSFET were analyzed by simulation and experimental methods. The electric field concentration at the gate edge was successfully suppressed by a gate field plate. A high breakdown voltage of 934 V and a figure of merit of 14.6 MW/cm2 were achieved at L FP of 2 µm and L drift of 15 µm, while those of the conventional device without a gate field plate were 744 V and 13.3 MW/cm2, respectively. Also, the fabricated device shows stable blocking characteristics at a high temperature of 250 °C. The drain leakage was increased by only 22% at 250 °C compared with that at room temperature.

Improvement in negative bias illumination stress stability of In-Ga-Zn-O thin film transistors using HfO2 gate insulators by controlling atomic-layer-deposition conditions

NASA Astrophysics Data System (ADS)

Na, So-Yeong; Kim, Yeo-Myeong; Yoon, Da-Jeong; Yoon, Sung-Min

2017-12-01

The effects of atomic layer deposition (ALD) conditions for the HfO2 gate insulators (GI) on the device characteristics of the InGaZnO (IGZO) thin film transistors (TFTs) were investigated when the ALD temperature and Hf precursor purge time were varied to 200, 225, and 250 °C, and 15 and 30 s, respectively. The HfO2 thin films showed low leakage current density of 10-8 A cm-2, high dielectric constant of over 20, and smooth surface roughness at all ALD conditions. The IGZO TFTs using the HfO2 GIs showed good device characteristics such as a saturation mobility as high as 11 cm2 V-1 s-1, a subthreshold swing as low as 0.10 V/dec, and all the devices could be operated at a gate voltage as low as  ±3 V. While there were no marked differences in transfer characteristics and PBS stabilities among the fabricated devices, the NBIS instabilities could be improved by increasing the ALD temperature for the formation of HfO2 GIs by reducing the oxygen vacancies within the IGZO channel.

A transparent electrochromic metal-insulator switching device with three-terminal transistor geometry

NASA Astrophysics Data System (ADS)

Katase, Takayoshi; Onozato, Takaki; Hirono, Misako; Mizuno, Taku; Ohta, Hiromichi

2016-05-01

Proton and hydroxyl ion play an essential role for tuning functionality of oxides because their electronic state can be controlled by modifying oxygen off-stoichiometry and/or protonation. Tungsten trioxide (WO3), a well-known electrochromic (EC) material for smart window, is a wide bandgap insulator, whereas it becomes a metallic conductor HxWO3 by protonation. Although one can utilize electrochromism together with metal-insulator (MI) switching for one device, such EC-MI switching cannot be utilized in current EC devices because of their two-terminal structure with parallel-plate configuration. Here we demonstrate a transparent EC-MI switchable device with three-terminal TFT-type structure using amorphous (a-) WO3 channel layer, which was fabricated on glass substrate at room temperature. We used water-infiltrated nano-porous glass, CAN (calcium aluminate with nano-pores), as a liquid-leakage-free solid gate insulator. At virgin state, the device was fully transparent in the visible-light region. For positive gate voltage, the active channel became dark blue, and electrical resistivity of the a-WO3 layer drastically decreased with protonation. For negative gate voltage, deprotonation occurred and the active channel returned to transparent insulator. Good cycleability of the present transparent EC-MI switching device would have potential for the development of advanced smart windows.

Design and simulation of a novel 1400 V-4000 V enhancement mode buried gate GaN HEMT for power applications

NASA Astrophysics Data System (ADS)

Faramehr, Soroush; Kalna, Karol; Igić, Petar

2014-11-01

A novel enhancement mode structure, a buried gate gallium nitride (GaN) high electron mobility transistor (HEMT) with a breakdown voltage (BV) of 1400 V-4000 V for a source-to-drain spacing (LSD) of 6 μm-32 μm, is investigated using simulations by Silvaco Atlas. The simulations are based on meticulous calibration of a conventional lateral 1 μm gate length GaN HEMT with a source-to-drain spacing of 6 μm against its experimental transfer characteristics and BV. The specific on-resistance RS for the new power transistor with the source-to-drain spacing of 6 μm showing BV = 1400 V and the source-to-drain spacing of 8 μm showing BV = 1800 V is found to be 2.3 mΩ · cm2 and 3.5 mΩ · cm2, respectively. Further improvement up to BV = 4000 V can be achieved by increasing the source-to-drain spacing to 32 μm with the specific on-resistance of RS = 35.5 mΩ · cm2. The leakage current in the proposed devices stays in the range of ˜5 × 10-9 mA mm-1.

Improved modeling on the RF behavior of InAs/AlSb HEMTs

NASA Astrophysics Data System (ADS)

Guan, He; Lv, Hongliang; Zhang, Yuming; Zhang, Yimen

2015-12-01

The leakage current and the impact ionization effect causes a drawback for the performance of InAs/AlSb HEMTs due to the InAs channel with a very narrow band gap of 0.35 eV. In this paper, the conventional HEMT small-signal model was enhanced to characterize the RF behavior for InAs/AlSb HEMTs. The additional gate leakage current induced by the impact ionization was modeled by adding two resistances RGh1 and RGh2 shunting the Cgs-Ri and Cgd-Rj branches, respectively, and the ionized-drain current was characterized by an additional resistance Rmi parallel with the output resistance Rds, meanwhile the influence of the impact ionization on the transconductance was modeled by an additional current source gmi controlled by Vgs. The additional inductance, evaluated as a function of f(ω, R), was introduced to characterize the frequency dependency of impact ionization by using the impact ionization effective rate 1/τi and a new frequency response rate factor n, which guaranteed the enhanced model reliable for a wide frequency range. As a result, the enhanced model achieved good agreement with the measurements of the S-parameters and Y-parameters for a wide frequency range, moreover, the simulated results of the stability factor K, the cutoff frequency fT, the maximum frequency of oscillation fmax, and the unilateral Mason's gain U were estimated to approach the experimental results with a high degree.

Top-gated field-effect LaAlO{sub 3}/SrTiO{sub 3} devices made by ion-irradiation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hurand, S.; Jouan, A.; Feuillet-Palma, C.

2016-02-01

We present a method to fabricate top-gated field-effect devices in a LaAlO{sub 3}/SrTiO{sub 3} two-dimensional electron gas (2-DEG). Prior to the gate deposition, the realisation of micron size conducting channels in the 2-DEG is achieved by an ion-irradiation with high-energy oxygen ions. After identifying the ion fluence as the key parameter that determines the electrical transport properties of the channels, we demonstrate the field-effect operation. At low temperature, the normal state resistance and the superconducting T{sub c} can be tuned over a wide range by a top-gate voltage without any leakage. A superconductor-to-insulator quantum phase transition is observed for amore » strong depletion of the 2-DEG.« less

Low-temperature fabrication of sputtered high-k HfO2 gate dielectric for flexible a-IGZO thin film transistors

NASA Astrophysics Data System (ADS)

Yao, Rihui; Zheng, Zeke; Xiong, Mei; Zhang, Xiaochen; Li, Xiaoqing; Ning, Honglong; Fang, Zhiqiang; Xie, Weiguang; Lu, Xubing; Peng, Junbiao

2018-03-01

In this work, low temperature fabrication of a sputtered high-k HfO2 gate dielectric for flexible a-IGZO thin film transistors (TFTs) on polyimide substrates was investigated. The effects of Ar-pressure during the sputtering process and then especially the post-annealing treatments at low temperature (≤200 °C) for HfO2 on reducing the density of defects in the bulk and on the surface were systematically studied. X-ray reflectivity, UV-vis and X-ray photoelectron spectroscopy, and micro-wave photoconductivity decay measurements were carried out and indicated that the high quality of optimized HfO2 film and its high dielectric properties contributed to the low concentration of structural defects and shallow localized defects such as oxygen vacancies. As a result, the well-structured HfO2 gate dielectric exhibited a high density of 9.7 g/cm3, a high dielectric constant of 28.5, a wide optical bandgap of 4.75 eV, and relatively low leakage current. The corresponding flexible a-IGZO TFT on polyimide exhibited an optimal device performance with a saturation mobility of 10.3 cm2 V-1 s-1, an Ion/Ioff ratio of 4.3 × 107, a SS value of 0.28 V dec-1, and a threshold voltage (Vth) of 1.1 V, as well as favorable stability under NBS/PBS gate bias and bending stress.

Fabrication of Amorphous Indium Gallium Zinc Oxide Thin Film Transistor by using Focused Ion Beam

NASA Astrophysics Data System (ADS)

Zhu, Wencong

Compared with other transparent semiconductors, amorphous indium gallium zinc oxide (a-IGZO) has both good uniformity and high electron mobility, which make it as a good candidate for displays or large-scale transparent circuit. The goal of this research is to fabricate alpha-IGZO thin film transistor (TFT) with channel milled by focused ion beam (FIB). TFTs with different channel geometries can be achieved by applying different milling strategies, which facilitate modifying complex circuit. Technology Computer-Aided Design (TCAD) was also introduced to understand the effect of trapped charges on the device performance. The investigation of the trapped charge at IGZO/SiO2 interface was performed on the IGZO TFT on p-Silicon substrate with thermally grown SiO2 as dielectric. The subgap density-of-state model was used for the simulation, which includes conduction band-tail trap states and donor-like state in the subgap. The result shows that the de-trapping and donor-state ionization determine the interface trapped charge density at various gate biases. Simulation of IGZO TFT with FIB defined channel on the same substrate was also applied. The drain and source were connected intentionally during metal deposition and separated by FIB milling. Based on the simulation, the Ga ions in SiO2 introduced by the ion beam was drifted by gate bias and affects the saturation drain current. Both side channel and direct channel transparent IGZO TFTs were fabricated on the glass substrate with coated ITO. Higher ion energy (30 keV) was used to etch through the substrate between drain and source and form side channels at the corner of milled trench. Lower ion energy (16 keV) was applied to stop the milling inside IGZO thin film and direct channel between drain and source was created. Annealing after FIB milling removed the residual Ga ions and the devices show switch feature. Direct channel shows higher saturation drain current (~10-6 A) compared with side channel (~10-7 A) because of its shorter channel length and wider width, however, it also exhibit higher gate leakage current (>10-7 A) than side channel (<10-7 A) due to larger Ga ion implantation and diffusion region in SiO2 after annealing. Hysteresis window increase and positive VON shift were also observed due to the interface trap density increase and carrier density suppression both by Ga ions. Laser interference lithography was applied to define the IGZO active region, which gives more flexibility on TFT channel dimension and circuit modification. He-Cd laser with 325 nm wavelength was used to define 2D array of IGZO islands with period of 2.5 im. Logic gate array was designed and fabricated by combining this 2D array of IGZO islands and FIB direct channel milling. After annealing, device shows on-off feature, but high temperature (400 °C) release more free carrier and results in negative shift of VON. The row selection voltage was also introduced in the design of logic gate array to act as switch of input signals to each row separately. However, due to the long input signal sweeping time, the leakage current cannot be overlooked. The idea can be verified by AC or short pulse input signal.

Metal oxide, Group V-VI chalcogenides and GaN/AlGaN photodetectors

NASA Astrophysics Data System (ADS)

Hasan, Md. Rezaul

In this work, a simple, low-cost and catalyst free one-step solution processing of onedimensional Sb2S3 nanostructures on polyimide substrates was done. This structure demonstrated its potential application as a photoconductor in the UV and visible regime. Using-field emission scanning electron microscopy (SEM), grazing incidence X-Ray diffraction, Raman spectra and transmission electron microscopy measurements, it was shown that the Sb 2S3 films have high crystallinity, uniform morphology and nearstoichiometric composition. Further, using tauc plot, it was found that the films have a direct bandgap of 1.67 eV. MSM photodetectors, fabricated using these films showed a clear photo response in both UV as well as visible wavelength. These devices showed UV on/off ratio as high as 160 under the light intensity of 30 mW/cm2 and a small rise time and fall time of 44 ms 28 ms respectively. The effect of geometry of metal pad and bonding wire orientation of a multi-channel FET on the coupling of THz radiation was studied. The spatial variation images were taken by raster scan with the resolution of 0.07 mm steps in both x and y directions. An effective gate bias, where the effect of noise is minimum and photoresponse is maximum, was used for imaging. By applying VGS =-2.8V and VDS =380mV, the images were taken for all different combinations of activated bonding wires and metal pads. It was observed that, effect of bonding wire orientation is negligible for the large source pad as the radiation is coupled basically between drain and gate pad. Effect of drain bonding wire on coupling depends on the maximum width or diameter of metal pad and the incoming wavelength. In this work, Position of activated Drain pad and orientation of respective bonding wire defined the image tilting angle. Voltage drop across the shorting metal between drain pads, also played a role in increasing the asymmetry by selectively exciting a certain portion of FET Channels more than the other portion. Position of gate pad defined the center point of the image without tilting the image as the geometry of the gate pads were parallel to each other. And there was no effect of gate pad bonding wire orientation because of the larger width of gate pads. For the GaN/AlGaNHEMT, the effect of Al mole fraction in AlGaN layer and the effect of gate oxide on the DC and low frequency noise characterization was studied. MOSHEMT with SiO2 improved the Id(on)/I d(off) ratio up to more than 8 orders, while it is only 10 times in conventional HEMT. It was shown that the gate leakage and isolation leakage suppression efficiency improved dramatically with the oxide. Subthreshold swing (SS) of MOS-HEMTs with different Al mole fraction (from 20% to 35%) vary slightly from 72 mV/decade to 79 mV/decade, but the conventional GaN/AlGaN HEMT showed SS of 2.4V/decade. Low frequency noise study revealed the difference in transport mechanism between HEMT and MOS-HEMTs. By using Carrier Number Fluctuation (CNF) model on the measured data, it was found that the noise is predominantly coming from the surface states. While generation-recombination is very prominent in conventional HEMT, it is very weak and insignificant in both MOS-HEMTs at much higher frequencies. This study reveals that very high number of surface states assisting the tunneling in schottky/AlGaN barrier is responsible for unusually high leakage and higher noise level in conventional HEMT. Leakage level is improved from mA/mm range for HEMT to pA/mm range for MOS-HEMTs. Leakage suppression improvement and minimization of noise level can be mainly attributed to high quality SiO2. Hooge's constant was in the order of 5-6x10-3 in MOS-HEMTs, which is 5x10 -2 for conventional HEMT indicating much lower noise level in the MOS-HEMTs. (Abstract shortened by ProQuest.).

Leakage and sweet spots in triple-quantum-dot spin qubits: A molecular-orbital study

NASA Astrophysics Data System (ADS)

Zhang, Chengxian; Yang, Xu-Chen; Wang, Xin

2018-04-01

A triple-quantum-dot system can be operated as either an exchange-only qubit or a resonant-exchange qubit. While it is generally believed that the decisive advantage of the resonant-exchange qubit is the suppression of charge noise because it is operated at a sweet spot, we show that the leakage is also an important factor. Through molecular-orbital-theoretic calculations, we show that when the system is operated in the exchange-only scheme, the leakage to states with double electron occupancy in quantum dots is severe when rotations around the axis 120∘ from z ̂ is performed. While this leakage can be reduced by either shrinking the dots or separating them further, the exchange interactions are also suppressed at the same time, making the gate operations unfavorably slow. When the system is operated as a resonant-exchange qubit, the leakage is three to five orders of magnitude smaller. We have also calculated the optimal detuning point which minimizes the leakage for the resonant-exchange qubit, and have found that although it does not coincide with the double sweet spot for the charge noise, they are rather close. Our results suggest that the resonant-exchange qubit has another advantage, that leakage can be greatly suppressed compared to the exchange-only qubit, and operating at the double sweet spot point should be optimal both for reducing charge noise and suppressing leakage.

Low temperature solution processed high-κ ZrO2 gate dielectrics for nanoelectonics

NASA Astrophysics Data System (ADS)

Kumar, Arvind; Mondal, Sandip; Rao, K. S. R. Koteswara

2016-05-01

The high-κ gate dielectrics, specifically amorphous films offer salient features such as exceptional mechanical flexibility, smooth surfaces and better uniformity associated with low leakage current density. In this work, ∼35 nm thick amorphous ZrO2 films were deposited on silicon substrate at low temperature (300 °C, 1 h) from facile spin-coating method and characterized by various analytical techniques. The X-ray diffraction and X-ray photoelectron spectroscopy reveal the formation of amorphous phase ZrO2, while ellipsometry analysis together with the Atomic Force Microscope suggest the formation of dense film with surface roughness of 1.5 Å, respectively. The fabricated films were integrated in metal-oxide-semiconductor (MOS) structures to check the electrical capabilities. The oxide capacitance (Cox), flat band capacitance (CFB), flat band voltage (VFB), dielectric constant (κ) and oxide trapped charges (Qot) extracted from high frequency (1 MHz) C-V curve are 186 pF, 104 pF, 0.37 V, 15 and 2 × 10-11 C, respectively. The small flat band voltage 0.37 V, narrow hysteresis and very little frequency dispersion between 10 kHz-1 MHz suggest an excellent a-ZrO2/Si interface with very less trapped charges in the oxide. The films exhibit a low leakage current density 4.7 × 10-9 A/cm2 at 1 V. In addition, the charge transport mechanism across the MOSC is analyzed and found to have a strong bias dependence. The space charge limited conduction mechanism is dominant in the high electric field region (1.3-5 V) due to the presence of traps, while the trap-supported tunneling is prevailed in the intermediate region (0.35-1.3 V). Low temperature solution processed ZrO2 thin films obtained are of high quality and find their importance as a potential dielectric layer on Si and polymer based flexible electronics.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure.

PubMed

Chen, Szu-Hung; Liao, Wen-Shiang; Yang, Hsin-Chia; Wang, Shea-Jue; Liaw, Yue-Gie; Wang, Hao; Gu, Haoshuang; Wang, Mu-Chun

2012-08-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal-semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

PubMed Central

2012-01-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials. PMID:22853458

Graphene-graphite oxide field-effect transistors.

PubMed

Standley, Brian; Mendez, Anthony; Schmidgall, Emma; Bockrath, Marc

2012-03-14

Graphene's high mobility and two-dimensional nature make it an attractive material for field-effect transistors. Previous efforts in this area have used bulk gate dielectric materials such as SiO(2) or HfO(2). In contrast, we have studied the use of an ultrathin layered material, graphene's insulating analogue, graphite oxide. We have fabricated transistors comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. The graphite oxide layers show relatively minimal leakage at room temperature. The breakdown electric field of graphite oxide was found to be comparable to SiO(2), typically ~1-3 × 10(8) V/m, while its dielectric constant is slightly higher, κ ≈ 4.3. © 2012 American Chemical Society

Temperature-dependent degradation mechanisms of threshold voltage in La2O3-gated n-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Ming-Tsong; Hsu, De-Cheng; Juan, Pi-Chun; Wang, Y. L.; Lee, Joseph Ya-min

2010-09-01

Metal-oxide-semiconductor capacitors and n-channel metal-oxide-semiconductor field-effect transistors with La2O3 gate dielectric were fabricated. The positive bias temperature instability was studied. The degradation of threshold voltage (ΔVT) showed an exponential dependence on the stress time in the temperature range from 25 to 75 °C. The degradation of subthreshold slope (ΔS) and gate leakage (IG) with stress voltage was also measured. The degradation of VT is attributed to the oxide trap charges Qot. The extracted activation energy of 0.2 eV is related to a degradation dominated by the release of atomic hydrogen in La2O3 thin films.

Non-localized trapping effects in AlGaN/GaN heterojunction field-effect transistors subjected to on-state bias stress

NASA Astrophysics Data System (ADS)

Hu, Cheng-Yu; Hashizume, Tamotsu

2012-04-01

For AlGaN/GaN heterojunction field-effect transistors, on-state-bias-stress (on-stress)-induced trapping effects were observed across the entire drain access region, not only at the gate edge. However, during the application of on-stress, the highest electric field was only localized at the drain side of the gate edge. Using the location of the highest electric field as a reference, the trapping effects at the gate edge and at the more distant access region were referred to as localized and non-localized trapping effect, respectively. Using two-dimensional-electron-gas sensing-bar (2DEG-sensing-bar) and dual-gate structures, the non-localized trapping effects were investigated and the trap density was measured to be ˜1.3 × 1012 cm-2. The effect of passivation was also discussed. It was found that both surface leakage currents and hot electrons are responsible for the non-localized trapping effects with hot electrons having the dominant effect. Since hot electrons are generated from the 2DEG channel, it is highly likely that the involved traps are mainly in the GaN buffer layer. Using monochromatic irradiation (1.24-2.81 eV), the trap levels responsible for the non-localized trapping effects were found to be located at 0.6-1.6 eV from the valence band of GaN. Both trap-assisted impact ionization and direct channel electron injection are proposed as the possible mechanisms of the hot-electron-related non-localized trapping effect. Finally, using the 2DEG-sensing-bar structure, we directly confirmed that blocking gate injected electrons is an important mechanism of Al2O3 passivation.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Jun; Zhang, Zhi-Lin; Key Laboratory of Advanced Display and System Applications, Ministry of Education, Shanghai University, Shanghai 200072

RF magnetron sputtered HfInZnO film and atomic layer deposition (ALD) Al{sub 2}O{sub 3} film were employed for thin film transistors (TFTs) as channel layer and gate insulator, respectively. To achieve HfInZnO-TFT with high performance and good bias stability, the thickness of HfInZnO active layer was optimized. The performance of HfInZnO-TFTs was found to be thickness dependent. As the HfInZnO active layer got thicker, the leakage current greatly increased from 1.73 × 10{sup −12} to 2.54 × 10{sup −8} A, the threshold voltage decreased from 7.4 to −4.7 V, while the subthreshold swing varied from 0.41 to 1.07 V/decade. Overall, themore » HfInZnO film showed superior performance, such as saturation mobility of 6.4 cm{sup 2}/V s, threshold voltage of 4.2 V, subthreshold swing of 0.43 V/decade, on/off current ratio of 3 × 10{sup 7} and V{sub th} shift of 3.6 V under V{sub GS}= 10 V for 7200 s. The results demonstrate the possibility of fabricating TFTs using HfInZnO film as active layer and using ALD Al{sub 2}O{sub 3} as gate insulator.« less

ALD Al2O3 passivation of Lg = 100 nm metamorphic InAlAs/InGaAs HEMTs with Si-doped Schottky layers on GaAs substrates

NASA Astrophysics Data System (ADS)

Sun, Bing; Chang, Hudong; Wang, Shengkai; Niu, Jiebin; Liu, Honggang

2017-12-01

In0.52Al0.48As/In0.7Ga0.3As metamorphic high-electron-mobility transistors (mHEMTs) on GaAs substrates have been demonstrated. The devices feature an epitaxial structure with Si-doped InP/In0.52Al0.48As Schottky layers, together with an atomic layer deposition (ALD) Al2O3 passivation process. In comparison to the GaAs mHEMTs with plasma enhanced chemical vapor deposition (PECVD) SiN passivation, the devices with ALD Al2O3 passivation exhibit more than one order of magnitude lower gate leakage current (Jg) and much lower contact resistance (RC) and specific contact resistivity (ρC). 100-nm gate length (Lg) In0.52Al0.48As/In0.7Ga0.3As mHEMTs with Si-doped InP/In0.52Al0.48As Schottky layers and ALD Al2O3 passivation exhibit excellent DC and RF characteristics, such as a maximum oscillation frequency (fmax) of 388.2 GHz.

Chemical shift and surface characteristics of Al-doped ZnO thin film on SiOC dielectrics.

PubMed

Oh, Teresa; Lee, Sang Yeol

2013-10-01

Aluminum doped zinc oxide (AZO) films were fabricated on SiOC/p-Si wafer and SiOC film was prepared on a p-type Si substrate with the SiC target at oxygen ambient with the gas flow rate of 5-30 sccm by a RF magnetron sputter. C-V curve of SiOC/Si wafer was measured to observe the relationship between the polarity of SiOC dielectrics and the change of capacitance depending on oxygen gas flow rate. The SiOC film could be controlled to be polar or nonpolar, and their surface energy was changed depending on the polarity. Smooth surface is essential to improve the TFT performance. AZO-TFTs used smooth SiOC film with low polarity as a gate insulator was observed to show low leakage current (IL) and low subthreshold voltage swing. It is proposed that SiOC film with high degree amorphous structure as a gate insulator between AZO and Si wafer could solve problems of the mismatched interfaces, which was originated from the electron scattering due to the grain boundary.

Reverse leakage current characteristics of InGaN/GaN multiple quantum well ultraviolet/blue/green light-emitting diodes

NASA Astrophysics Data System (ADS)

Zhou, Shengjun; Lv, Jiajiang; Wu, Yini; Zhang, Yuan; Zheng, Chenju; Liu, Sheng

2018-05-01

We investigated the reverse leakage current characteristics of InGaN/GaN multiple quantum well (MQW) near-ultraviolet (NUV)/blue/green light-emitting diodes (LEDs). Experimental results showed that the NUV LED has the smallest reverse leakage current whereas the green LED has the largest. The reason is that the number of defects increases with increasing nominal indium content in InGaN/GaN MQWs. The mechanism of the reverse leakage current was analyzed by temperature-dependent current–voltage measurement and capacitance–voltage measurement. The reverse leakage currents of NUV/blue/green LEDs show similar conduction mechanisms: at low temperatures, the reverse leakage current of these LEDs is attributed to variable-range hopping (VRH) conduction; at high temperatures, the reverse leakage current of these LEDs is attributed to nearest-neighbor hopping (NNH) conduction, which is enhanced by the Poole–Frenkel effect.

Effect of Post-HALT Annealing on Leakage Currents in Solid Tantalum Capacitors

NASA Technical Reports Server (NTRS)

Teverovsky, Alexander

2010-01-01

Degradation of leakage currents is often observed during life testing of tantalum capacitors and is sometimes attributed to the field-induced crystallization in amorphous anodic tantalum pentoxide dielectrics. However, degradation of leakage currents and the possibility of annealing of degraded capacitors have not been investigated yet. In this work the effect of annealing after highly accelerated life testing (HALT) on leakage currents in various types of solid tantalum capacitors was analyzed. Variations of leakage currents with time during annealing at temperatures from 125 oC to 180 oC, thermally stimulated depolarization (TSD) currents, and I-V characteristics were measured to understand the conduction mechanism and the reason for current degradation. Annealing resulted in a gradual decrease of leakage currents and restored their initial values. Repeat HALT after annealing resulted in reproducible degradation of leakage currents. The observed results are explained based on ionic charge instability (drift/diffusion of oxygen vacancies) in the tantalum pentoxide dielectrics using a modified Schottky conduction mechanism.

Generation of large scale GHZ states with the interactions of photons and quantum-dot spins

NASA Astrophysics Data System (ADS)

Miao, Chun; Fang, Shu-Dong; Dong, Ping; Yang, Ming; Cao, Zhuo-Liang

2018-03-01

We present a deterministic scheme for generating large scale GHZ states in a cavity-quantum dot system. A singly charged quantum dot is embedded in a double-sided optical microcavity with partially reflective top and bottom mirrors. The GHZ-type Bell spin state can be created and two n-spin GHZ states can be perfectly fused to a 2n-spin GHZ state with the help of n ancilla single-photon pulses. The implementation of the current scheme only depends on the photon detection and its need not to operate multi-qubit gates and multi-qubit measurements. Discussions about the effect of the cavity loss, side leakage and exciton cavity coupling strength for the fidelity of generated states show that the fidelity can remain high enough by controlling system parameters. So the current scheme is simple and feasible in experiment.

Electrical hysteresis in p-GaN metal-oxide-semiconductor capacitor with atomic-layer-deposited Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Zhang, Kexiong; Liao, Meiyong; Imura, Masataka; Nabatame, Toshihide; Ohi, Akihiko; Sumiya, Masatomo; Koide, Yasuo; Sang, Liwen

2016-12-01

The electrical hysteresis in current-voltage (I-V) and capacitance-voltage characteristics was observed in an atomic-layer-deposited Al2O3/p-GaN metal-oxide-semiconductor capacitor (PMOSCAP). The absolute minimum leakage currents of the PMOSCAP for forward and backward I-V scans occurred not at 0 V but at -4.4 and +4.4 V, respectively. A negative flat-band voltage shift of 5.5 V was acquired with a capacitance step from +4.4 to +6.1 V during the forward scan. Mg surface accumulation on p-GaN was demonstrated to induce an Mg-Ga-Al-O oxidized layer with a trap density on the order of 1013 cm-2. The electrical hysteresis is attributed to the hole trapping and detrapping process in the traps of the Mg-Ga-Al-O layer via the Poole-Frenkel mechanism.

Structural and electrical properties of single crystalline SrZrO3 epitaxially grown on Ge (001)

NASA Astrophysics Data System (ADS)

Lim, Z. H.; Ahmadi-Majlan, K.; Grimley, E. D.; Du, Y.; Bowden, M.; Moghadam, R.; LeBeau, J. M.; Chambers, S. A.; Ngai, J. H.

2017-08-01

We present structural and electrical characterization of SrZrO3 that has been epitaxially grown on Ge(001) by oxide molecular beam epitaxy. Single crystalline SrZrO3 can be nucleated on Ge via deposition at low temperatures followed by annealing at 550 °C in ultra-high vacuum. Photoemission spectroscopy measurements reveal that SrZrO3 exhibits a type-I band arrangement with respect to Ge, with conduction and valence band offsets of 1.4 eV and 3.66 eV, respectively. Capacitance-voltage and current-voltage measurements on 4 nm thick films reveal low leakage current densities and an unpinned Fermi level at the interface that allows modulation of the surface potential of Ge. Ultra-thin films of epitaxial SrZrO3 can thus be explored as a potential gate dielectric for Ge.

CT attenuation measurements are valuable to discriminate pledgets used in prosthetic heart valve implantation from paravalvular leakage

PubMed Central

Habets, J; Meijer, T S; Meijer, R C A; Mali, W P Th M; Vonken, E-J P A; Budde, R P J

2012-01-01

Objectives Sutures with polytetrafluorethylene (PTFE) felt pledgets are commonly used in prosthetic heart valve (PHV) implantation. Paravalvular leakage can be difficult to distinguish from PTFE felt pledgets on multislice CT because both present as hyperdense structures. We assessed whether pledgets can be discriminated from contrast-enhanced solutions (blood/saline) on CT images based on attenuation difference in an ex vivo experiment and under in vivo conditions. Methods PTFE felt pledgets were sutured to the suture ring of a mechanical PHV and porcine aortic annulus, and immersed and scanned in four different contrast-enhanced (Ultravist®; 300 mg jopromide ml−1) saline concentrations (10.0, 12.0, 13.6 and 15.0 mg ml−1). Scanning was performed on a 256-slice scanner with eight different scan protocols with various tube voltage (100 kV, 120 kV) and tube current (400 mAs, 600 mAs, 800 mAs, 1000 mAs) settings. Attenuation of the pledgets and surrounding contrast-enhanced saline were measured. Additionally, the attenuation of pledgets and contrast-enhanced blood was measured on electrocardiography (ECG)-gated CTA scans of 19 patients with 22 PHVs. Results Ex vivo CT attenuation differences between the pledgets and contrast-enhanced solutions were larger by using higher tube voltages. CT attenuation values of the pledgets were higher than contrast-enhanced blood in patients: 420±26 Hounsfield units (mean±SD, range 383–494) and 288±41 Hounsfield units (range 202–367), respectively. Conclusions PTFE felt pledgets have consistently higher attenuation than surrounding contrast-enhanced blood. CT attenuation measurements therefore may help to differentiate pledgets from paravalvular leakage, and detect paravalvular leakage in patients with suspected PHV dysfunction. PMID:22919014

Investigation on interfacial and electrical properties of Ge MOS capacitor with different NH3-plasma treatment procedure

NASA Astrophysics Data System (ADS)

Liu, Xiaoyu; Xu, Jingping; Liu, Lu; Cheng, Zhixiang; Huang, Yong; Gong, Jingkang

2017-08-01

The effects of different NH3-plasma treatment procedures on interfacial and electrical properties of Ge MOS capacitors with stacked gate dielectric of HfTiON/TaON were investigated. The NH3-plasma treatment was performed at different steps during fabrication of the stacked gate dielectric, i.e. before or after interlayer (TaON) deposition, or after deposition of high-k dielectric (HfTiON). It was found that the excellent interface quality with an interface-state density of 4.79 × 1011 eV-1 cm-2 and low gate leakage current (3.43 × 10-5 A/cm2 at {V}{{g}}=1 {{V}}) could be achieved for the sample with NH3-plasma treatment directly on the Ge surface before TaON deposition. The involved mechanisms are attributed to the fact that the NH3-plasma can directly react with the Ge surface to form more Ge-N bonds, i.e. more GeO x Ny, which effectively blocks the inter-diffusion of elements and suppresses the formation of unstable GeO x interfacial layer, and also passivates oxygen vacancies and dangling bonds near/at the interface due to more N incorporation and decomposed H atoms from the NH3-plasma. Project supported by the National Natural Science Foundation of China (Nos. 61176100, 61274112).

Accurate characterization and understanding of interface trap density trends between atomic layer deposited dielectrics and AlGaN/GaN with bonding constraint theory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ramanan, Narayanan; Lee, Bongmook; Misra, Veena, E-mail: vmisra@ncsu.edu

2015-06-15

Many dielectrics have been proposed for the gate stack or passivation of AlGaN/GaN based metal oxide semiconductor heterojunction field effect transistors, to reduce gate leakage and current collapse, both for power and RF applications. Atomic Layer Deposition (ALD) is preferred for dielectric deposition as it provides uniform, conformal, and high quality films with precise monolayer control of film thickness. Identification of the optimum ALD dielectric for the gate stack or passivation requires a critical investigation of traps created at the dielectric/AlGaN interface. In this work, a pulsed-IV traps characterization method has been used for accurate characterization of interface traps withmore » a variety of ALD dielectrics. High-k dielectrics (HfO{sub 2}, HfAlO, and Al{sub 2}O{sub 3}) are found to host a high density of interface traps with AlGaN. In contrast, ALD SiO{sub 2} shows the lowest interface trap density (<2 × 10{sup 12 }cm{sup −2}) after annealing above 600 °C in N{sub 2} for 60 s. The trend in observed trap densities is subsequently explained with bonding constraint theory, which predicts a high density of interface traps due to a higher coordination state and bond strain in high-k dielectrics.« less

Solution processed lanthanum aluminate gate dielectrics for use in metal oxide-based thin film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Esro, M.; Adamopoulos, G., E-mail: g.adamopoulos@lancaster.ac.uk; Mazzocco, R.

2015-05-18

We report on ZnO-based thin-film transistors (TFTs) employing lanthanum aluminate gate dielectrics (La{sub x}Al{sub 1−x}O{sub y}) grown by spray pyrolysis in ambient atmosphere at 440 °C. The structural, electronic, optical, morphological, and electrical properties of the La{sub x}Al{sub 1−x}O{sub y} films and devices as a function of the lanthanum to aluminium atomic ratio were investigated using a wide range of characterization techniques such as UV-visible absorption spectroscopy, impedance spectroscopy, spectroscopic ellipsometry, atomic force microscopy, x-ray diffraction, and field-effect measurements. As-deposited LaAlO{sub y} dielectrics exhibit a wide band gap (∼6.18 eV), high dielectric constant (k ∼ 16), low roughness (∼1.9 nm), and very low leakage currentsmore » (<3 nA/cm{sup 2}). TFTs employing solution processed LaAlO{sub y} gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with hysteresis-free operation, low operation voltages (∼10 V), high on/off current modulation ratio of >10{sup 6}, subthreshold swing of ∼650 mV dec{sup −1}, and electron mobility of ∼12 cm{sup 2} V{sup −1} s{sup −1}.« less

Comparative study on nitridation and oxidation plasma interface treatment for AlGaN/GaN MIS-HEMTs with AlN gate dielectric

NASA Astrophysics Data System (ADS)

Zhu, Jie-Jie; Ma, Xiao-Hua; Hou, Bin; Chen, Li-Xiang; Zhu, Qing; Hao, Yue

2017-02-01

This paper demonstrated the comparative study on interface engineering of AlN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) by using plasma interface pre-treatment in various ambient gases. The 15 nm AlN gate dielectric grown by plasma-enhanced atomic layer deposition significantly suppressed the gate leakage current by about two orders of magnitude and increased the peak field-effect mobility by more than 50%. NH3/N2 nitridation plasma treatment (NPT) was used to remove the 3 nm poor-quality interfacial oxide layer and N2O/N2 oxidation plasma treatment (OPT) to improve the quality of interfacial layer, both resulting in improved dielectric/barrier interface quality, positive threshold voltage (V th) shift larger than 0.9 V, and negligible dispersion. In comparison, however, NPT led to further decrease in interface charges by 3.38 × 1012 cm-2 and an extra positive V th shift of 1.3 V. Analysis with fat field-effect transistors showed that NPT resulted in better sub-threshold characteristics and transconductance linearity for MIS-HEMTs compared with OPT. The comparative study suggested that direct removing the poor interfacial oxide layer by nitridation plasma was superior to improving the quality of interfacial layer by oxidation plasma for the interface engineering of GaN-based MIS-HEMTs.

Scalable photonic quantum computing assisted by quantum-dot spin in double-sided optical microcavity.

PubMed

Wei, Hai-Rui; Deng, Fu-Guo

2013-07-29

We investigate the possibility of achieving scalable photonic quantum computing by the giant optical circular birefringence induced by a quantum-dot spin in a double-sided optical microcavity as a result of cavity quantum electrodynamics. We construct a deterministic controlled-not gate on two photonic qubits by two single-photon input-output processes and the readout on an electron-medium spin confined in an optical resonant microcavity. This idea could be applied to multi-qubit gates on photonic qubits and we give the quantum circuit for a three-photon Toffoli gate. High fidelities and high efficiencies could be achieved when the side leakage to the cavity loss rate is low. It is worth pointing out that our devices work in both the strong and the weak coupling regimes.

Enhanced performance of amorphous In-Ga-Zn-O thin-film transistors using different metals for source/drain electrodes

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2017-09-01

In this paper, we propose an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with off-planed source/drain electrodes. We applied different metals for the source/drain electrodes with Ni and Ti to control the work function as high and low. When we measured the configuration of Ni to drain and source to Ti, the a-IGZO TFT showed increased driving current, decreased leakage current, a high on/off current ratio, low subthreshold swing, and high mobility. In addition, we conducted a reliability test with a gate bias stress test at various temperatures. The results of the reliability test showed the Ni drain and Ti drain had an equivalent effective energy barrier height. Thus, we confirmed that the proposed off-planed structure improved the electrical characteristics of the fabricated devices without any degradation of characteristics. Through the a-IGZO TFT with different source/drain electrode metal engineering, we realized high-performance TFTs for next-generation display devices.

Organic field effect transistors - Study of performance parameters for different dielectric layer thickness

NASA Astrophysics Data System (ADS)

Assis, Anu; Shahul Hameed T., A.; Predeep, P.

2017-06-01

Mobility and current handling capabilities of Organic Field Effect Transistor (OFET) are vitally important parameters in the electrical performance where the material parameters and thickness of different layers play significant role. In this paper, we report the simulation of an OFET using multi physics tool, where the active layer is pentacene and Poly Methyl Methacrylate (PMMA) forms the dielectric. Electrical characterizations of the OFET on varying the thickness of the dielectric layer from 600nm to 400nm are simulated and drain current, transconductance and mobility are analyzed. In the study it is found that even though capacitance increases with reduction in dielectric layer thickness, the transconductance effect is reflected many more times in the mobility which in turn could be attributed to the variations in transverse electric field. The layer thickness below 300nm may result in gate leakage current points to the requirement of optimizing the thickness of different layers for better performance.

Simulation of temperature dependent dielectric breakdown in n{sup +}-polySi/SiO{sub 2}/n-6H-SiC structures during Poole-Frenkel stress at positive gate bias

DOE Office of Scientific and Technical Information (OSTI.GOV)

Samanta, Piyas, E-mail: piyas@vcfw.org; Mandal, Krishna C., E-mail: mandalk@cec.sc.edu

2016-08-14

We present for the first time a thorough investigation of trapped-hole induced gate oxide deterioration and simulation results of time-dependent dielectric breakdown (TDDB) of thin (7–25 nm) silicon dioxide (SiO{sub 2}) films thermally grown on (0 0 0 1) silicon (Si) face of n-type 6H-silicon carbide (n-6H-SiC). Gate oxide reliability was studied during both constant voltage and current stress with positive bias on the degenerately doped n-type poly-crystalline silicon (n{sup +}-polySi) gate at a wide range of temperatures between 27 and 225 °C. The gate leakage current was identified as the Poole-Frenkel (PF) emission of electrons trapped at an energy 0.92 eV belowmore » the SiO{sub 2} conduction band. Holes were generated in the n{sup +}-polySi anode material as well as in the oxide bulk via band-to-band ionization depending on the film thickness t{sub ox} and the energy of the hot-electrons (emitted via PF mechanism) during their transport through oxide films at oxide electric fields E{sub ox} ranging from 5 to 10 MV/cm. Our simulated time-to-breakdown (t{sub BD}) results are in excellent agreement with those obtained from time consuming TDDB measurements. It is observed that irrespective of stress temperatures, the t{sub BD} values estimated in the field range between 5 and 9 MV/cm better fit to reciprocal field (1/E) model for the thickness range studied here. Furthermore, for a 10 year projected device lifetime, a good reliability margin of safe operating field from 8.5 to 7.5 MV/cm for 7 nm and 8.1 to 6.9 MV/cm for 25 nm thick SiO{sub 2} was observed between 27 and 225 °C.« less

Hysteresis in Lanthanide Zirconium Oxides Observed Using a Pulse CV Technique and including the Effect of High Temperature Annealing.

PubMed

Lu, Qifeng; Zhao, Chun; Mu, Yifei; Zhao, Ce Zhou; Taylor, Stephen; Chalker, Paul R

2015-07-29

A powerful characterization technique, pulse capacitance-voltage (CV) technique, was used to investigate oxide traps before and after annealing for lanthanide zirconium oxide thin films deposited on n-type Si (111) substrates at 300 °C by liquid injection Atomic Layer Deposition (ALD). The results indicated that: (1) more traps were observed compared to the conventional capacitance-voltage characterization method in LaZrO x ; (2) the time-dependent trapping/de-trapping was influenced by the edge time, width and peak-to-peak voltage of a gate voltage pulse. Post deposition annealing was performed at 700 °C, 800 °C and 900 °C in N₂ ambient for 15 s to the samples with 200 ALD cycles. The effect of the high temperature annealing on oxide traps and leakage current were subsequently explored. It showed that more traps were generated after annealing with the trap density increasing from 1.41 × 10 12 cm -2 for as-deposited sample to 4.55 × 10 12 cm -2 for the 800 °C annealed one. In addition, the leakage current density increase from about 10 - ⁶ A/cm² at V g = +0.5 V for the as-deposited sample to 10 -3 A/cm² at V g = +0.5 V for the 900 °C annealed one.

Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

NASA Astrophysics Data System (ADS)

Jayanti, Srikant

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG in the form of PVD TaN was investigated along with high-k blocking dielectric. The material properties of TaN metal and high-k / low-k dielectric engineering were systematically studied. And the resulting memory structures exhibit excellent memory characteristics and scalability of the metal FG down to ˜1nm, which is promising in order to reduce the unwanted FG-FG interferences. In the later part of the study, the thermal stability of the combined stack was examined and various approaches to improve the stability and understand the cause of instability were explored. The performance of the high-k IPD metal FG memory structure was observed to degrade with higher annealing conditions and the deteriorated behavior was attributed to the leakage instability of the high-k /TaN capacitor. While the degradation is pronounced in both MIM and MIS capacitors, a higher leakage increment was seen in MIM, which was attributed to the higher degree of dielectric crystallization. In an attempt to improve the thermal stability, the trade-off in using amorphous interlayers to reduce the enhanced dielectric crystallization on metal was highlighted. Also, the effect of oxygen vacancies and grain growth on the dielectric leakage was studied through a multi-deposition-multi-anneal technique. Multi step deposition and annealing in a more electronegative ambient was observed to have a positive impact on the dielectric performance.

Insulation Resistance and Leakage Currents in Low-Voltage Ceramic Capacitors with Cracks

NASA Technical Reports Server (NTRS)

Teverovsky, Alexander A.

2014-01-01

Measurement of insulation resistance (IR) in multilayer ceramic capacitors (MLCCs) is considered a screening technique that ensures the dielectric is defect-free. This work analyzes the effectiveness of this technique for revealing cracks in ceramic capacitors. It is shown that absorption currents prevail over the intrinsic leakage currents during standard IR measurements at room temperature. Absorption currents, and consequently IR, have a weak temperature dependence, increase linearly with voltage (before saturation), and are not sensitive to the presence of mechanical defects. In contrary, intrinsic leakage currents increase super-linearly with voltage and exponentially with temperature (activation energy is in the range from 0.6 eV to 1.1 eV). Leakage currents associated with the presence of cracks have a weaker dependence on temperature and voltage compared to the intrinsic leakage currents. For this reason, intrinsic leakage currents prevail at high temperatures and voltages, thus masking the presence of defects.

Insulation Resistance and Leakage Currents in Low-Voltage Ceramic Capacitors with Cracks

NASA Technical Reports Server (NTRS)

Teverovsky, Alexander A.

2016-01-01

Measurement of insulation resistance (IR) in multilayer ceramic capacitors (MLCCs) is considered a screening technique that ensures the dielectric is defect-free. This work analyzes the effectiveness of this technique for revealing cracks in ceramic capacitors. It is shown that absorption currents prevail over the intrinsic leakage currents during standard IR measurements at room temperature. Absorption currents, and consequently IR, have a weak temperature dependence, increase linearly with voltage (before saturation), and are not sensitive to the presence of mechanical defects. In contrary, intrinsic leakage currents increase super-linearly with voltage and exponentially with temperature (activation energy is in the range from 0.6 eV to 1.1 eV). Leakage currents associated with the presence of cracks have a weaker dependence on temperature and voltage compared to the intrinsic leakage currents. For this reason, intrinsic leakage currents prevail at high temperatures and voltages, thus masking the presence of defects.

Using granular film to suppress charge leakage in a single-electron latch.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Orlov, A. O.; Luo, X.; Yadavalli, K. K.

2008-01-01

A single-electron latch is a device that can be used as a building block for quantum-dot cellular automata circuits. It consists of three nanoscale metal 'dots' connected in series by tunnel junctions; charging of the dots is controlled by three electrostatic gates. One very important feature of a single-electron latch is its ability to store ('latch') information represented by the location of a single electron within the three dots. To obtain latching, the undesirable leakage of charge during the retention time must be suppressed. Previously, to achieve this goal, multiple tunnel junctions were used to connect the three dots. However,more » this method of charge leakage suppression requires an additional compensation of the background charges affecting each parasitic dot in the array of junctions. We report a single-electron latch where a granular metal film is used to fabricate the middle dot in the latch which concurrently acts as a charge leakage suppressor. This latch has no parasitic dots, therefore the background charge compensation procedure is greatly simplified. We discuss the origins of charge leakage suppression and possible applications of granular metal dots for various single-electron circuits.« less

Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length

NASA Astrophysics Data System (ADS)

Jain, Neeraj; Raj, Balwinder

2017-12-01

Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects (SCEs), leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SOI FinFET is one of the best multigate structures that has gained importance in all electronic design automation (EDA) industries due to its improved short channel effects (SCEs), because of its more effective gate-controlling capabilities. In this paper, our aim is to explore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evaluated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope (SS), ON current (I on), OFF current (I off) and I on/I off ratio. The potential benefits of SOI FinFET at drain-to-source voltage, V DS = 0.05 V and V DS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain (A V), output conductance (g d), trans-conductance (g m), gate capacitance (C gg), and cut-off frequency (f T = g m/2πC gg) with spacer region variations.

Two-qubit logical operations in three quantum dots system.

PubMed

Łuczak, Jakub; Bułka, Bogdan R

2018-06-06

We consider a model of two interacting always-on, exchange-only qubits for which controlled phase (CPHASE), controlled NOT (CNOT), quantum Fourier transform (QFT) and SWAP operations can be implemented only in a few electrical pulses in a nanosecond time scale. Each qubit is built of three quantum dots (TQD) in a triangular geometry with three electron spins which are always kept coupled by exchange interactions only. The qubit states are encoded in a doublet subspace and are fully electrically controlled by a voltage applied to gate electrodes. The two qubit quantum gates are realized by short electrical pulses which change the triangular symmetry of TQD and switch on exchange interaction between the qubits. We found an optimal configuration to implement the CPHASE gate by a single pulse of the order 2.3 ns. Using this gate, in combination with single qubit operations, we searched for optimal conditions to perform the other gates: CNOT, QFT and SWAP. Our studies take into account environment effects and leakage processes as well. The results suggest that the system can be implemented for fault tolerant quantum computations.

Effects of substrate heating and post-deposition annealing on characteristics of thin MOCVD HfO2 films

NASA Astrophysics Data System (ADS)

Gopalan, Sundararaman; Ramesh, Sivaramakrishnan; Dutta, Shibesh; Virajit Garbhapu, Venkata

2018-02-01

It is well known that Hf-based dielectrics have replaced the traditional SiO2 and SiON as gate dielectric materials for conventional CMOS devices. By using thicker high-k materials such as HfO2 rather than ultra-thin SiO2, we can bring down leakage current densities in MOS devices to acceptable levels. HfO2 is also one of the potential candidates as a blocking dielectric for Flash memory applications for the same reason. In this study, effects of substrate heating and oxygen flow rate while depositing HfO2 thin films using CVD and effects of post deposition annealing on the physical and electrical characteristics of HfO2 thin films are presented. It was observed that substrate heating during deposition helps improve the density and electrical characteristics of the films. At higher substrate temperature, Vfb moved closer to zero and also resulted in significant reduction in hysteresis. Higher O2 flow rates may improve capacitance, but also results in slightly higher leakage. The effect of PDA depended on film thickness and O2 PDA improved characteristics only for thick films. For thinner films forming gas anneal resulted in better electrical characteristics.

49 CFR 236.735 - Current, leakage.

Code of Federal Regulations, 2010 CFR

2010-10-01

... 49 Transportation 4 2010-10-01 2010-10-01 false Current, leakage. 236.735 Section 236.735 Transportation Other Regulations Relating to Transportation (Continued) FEDERAL RAILROAD ADMINISTRATION... Current, leakage. A stray electric current of relatively small value which flows through or across the...

49 CFR 236.735 - Current, leakage.

Code of Federal Regulations, 2011 CFR

2011-10-01

... Current, leakage. A stray electric current of relatively small value which flows through or across the... 49 Transportation 4 2011-10-01 2011-10-01 false Current, leakage. 236.735 Section 236.735 Transportation Other Regulations Relating to Transportation (Continued) FEDERAL RAILROAD ADMINISTRATION...

49 CFR 236.735 - Current, leakage.

Code of Federal Regulations, 2014 CFR

2014-10-01

... Current, leakage. A stray electric current of relatively small value which flows through or across the... 49 Transportation 4 2014-10-01 2014-10-01 false Current, leakage. 236.735 Section 236.735 Transportation Other Regulations Relating to Transportation (Continued) FEDERAL RAILROAD ADMINISTRATION...

49 CFR 236.735 - Current, leakage.

Code of Federal Regulations, 2013 CFR

2013-10-01

... Current, leakage. A stray electric current of relatively small value which flows through or across the... 49 Transportation 4 2013-10-01 2013-10-01 false Current, leakage. 236.735 Section 236.735 Transportation Other Regulations Relating to Transportation (Continued) FEDERAL RAILROAD ADMINISTRATION...

49 CFR 236.735 - Current, leakage.

Code of Federal Regulations, 2012 CFR

2012-10-01

... Current, leakage. A stray electric current of relatively small value which flows through or across the... 49 Transportation 4 2012-10-01 2012-10-01 false Current, leakage. 236.735 Section 236.735 Transportation Other Regulations Relating to Transportation (Continued) FEDERAL RAILROAD ADMINISTRATION...

Temperature-dependent analysis of conduction mechanism of leakage current in thermally grown oxide on 4H-SiC

NASA Astrophysics Data System (ADS)

Sometani, Mitsuru; Okamoto, Dai; Harada, Shinsuke; Ishimori, Hitoshi; Takasu, Shinji; Hatakeyama, Tetsuo; Takei, Manabu; Yonezawa, Yoshiyuki; Fukuda, Kenji; Okumura, Hajime

2015-01-01

The conduction mechanism of the leakage current of a thermally grown oxide on 4H silicon carbide (4H-SiC) was investigated. The dominant carriers of the leakage current were found to be electrons by the carrier-separation current-voltage method. The current-voltage and capacitance-voltage characteristics, which were measured over a wide temperature range, revealed that the leakage current in SiO2/4H-SiC on the Si-face can be explained as the sum of the Fowler-Nordheim (FN) tunneling and Poole-Frenkel (PF) emission leakage currents. A rigorous FN analysis provided the true barrier height for the SiO2/4H-SiC interface. On the basis of Arrhenius plots of the PF current separated from the total leakage current, the existence of carbon-related defects and/or oxygen vacancy defects was suggested in thermally grown SiO2 films on the Si-face of 4H-SiC.

Temperature-dependent analysis of conduction mechanism of leakage current in thermally grown oxide on 4H-SiC

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sometani, Mitsuru; Takei, Manabu; Fuji Electric Co. Ltd., 1 Fuji-machi, Hino, 191-8502 Tokyo

The conduction mechanism of the leakage current of a thermally grown oxide on 4H silicon carbide (4H-SiC) was investigated. The dominant carriers of the leakage current were found to be electrons by the carrier-separation current-voltage method. The current-voltage and capacitance-voltage characteristics, which were measured over a wide temperature range, revealed that the leakage current in SiO{sub 2}/4H-SiC on the Si-face can be explained as the sum of the Fowler-Nordheim (FN) tunneling and Poole-Frenkel (PF) emission leakage currents. A rigorous FN analysis provided the true barrier height for the SiO{sub 2}/4H-SiC interface. On the basis of Arrhenius plots of the PFmore » current separated from the total leakage current, the existence of carbon-related defects and/or oxygen vacancy defects was suggested in thermally grown SiO{sub 2} films on the Si-face of 4H-SiC.« less

Suppression of TFT leakage current effect on active matrix displays by employing a new circular switch

NASA Astrophysics Data System (ADS)

Lee, Jae-Hoon; Park, Hyun-Sang; Jeon, Jae-Hong; Han, Min-Koo

2008-03-01

We have proposed a new poly-Si TFT pixel, which can suppress TFT leakage current effect on active matrix organic diode (AMOLED) displays, by employing a new circular switching TFT and additional signal line for compensating the leakage current. When the leakage current of switching TFT is increased, the VGS of the current driving TFT in the proposed pixel is not altered by the variable data voltages due to the circular switching TFT. Our simulation results show that OLED current variation of the proposed pixel can be suppressed less than 3%, while that of conventional pixel exceeds 30%. The proposed pixel may be suitable to suppress the leakage current effect on AMOLED display.

Synthesis and Characterization of the 2-Dimensional Transition Metal Dichalcogenides

NASA Astrophysics Data System (ADS)

Browning, Robert

In the last 50 years, the semiconductor industry has been scaling the silicon transistor to achieve faster devices, lower power consumption, and improve device performance. Transistor gate dimensions have become so small that short channel effects and gate leakage have become a significant problem. To address these issues, performance enhancement techniques such as strained silicon are used to improve mobility, while new high-k gate dielectric materials replace silicon oxide to reduce gate leakage. At some point the fundamental limit of silicon will be reached and the semiconductor industry will need to find an alternate solution. The advent of graphene led to the discovery of other layered materials such as the transition metal dichalcogenides. These materials have a layered structure similar to graphene and therefore possess some of the same qualities, but unlike graphene, these materials possess sizeable bandgaps between 1-2 eV making them useful for digital electronic applications. Since initially discovered, most of the research on these films has been from mechanically exfoliated flakes, which are easily produced due to the weak van der Waals force binding the layers together. For these materials to be considered for use in mainstream semiconductor technology, methods need to be explored to grow these films uniformly over a large area. In this research, atomic layer deposition (ALD) was employed as the growth technique used to produce large area uniform thin films of several different transition metal dichalcogenides. By optimizing the ALD growth parameters, it is possible to grow high quality films a few to several monolayers thick over a large area with good uniformity. This has been demonstrated and verified using several physical analytical tests such as Raman spectroscopy, photoluminescence, x-ray photoelectron spectroscopy, x-ray diffraction, transmission electron spectroscopy, and scanning electron microscopy, which show that these films possess the same qualities as those of the mechanically exfoliated films. Back-gated field effect transistors were created and electrical characterization was performed to determine if ALD grown films possess the same electronic properties as films produced from other methods. The tests revealed that the ALD grown films have high field effect mobility and high current on/off ratios. The WSe2 films also exhibited ambipolar electrical behavior making them a possible candidate for complementary metal-oxide semiconductor (CMOS) technology. Ab-initio density functional theory calculations were performed and compared to experimental properties of MoS2 and WSe2 films, which show that the ALD films grown in this research match theoretical predictions. The transconductance measurements from the WSe2 devices used, matched very well with the theoretical calculations, bridging the gap between experimental data and theoretical predictions. Based upon this research, ALD growth of TMD films proves to be a viable alternative for silicon based digital electronics.

Modeling and simulation of floating gate nanocrystal FET devices and circuits

NASA Astrophysics Data System (ADS)

Hasaneen, El-Sayed A. M.

The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to nanocrystal charge has a strong effect on the memory characteristics. Also, the programming operation of the memory cell has been investigated. The tunneling rate from quantum well channel to quantum dot (nanocrystal) gate is calculated. The calculations include various memory parameters, wavefunctions, and energies of quantum well channel and quantum dot gate. The use of floating gate nanocrystal memory as a transistor with a programmable threshold voltage has been demonstrated. The incorporation of FG-NCFETs to design programmable integrated circuit building blocks has been discussed. This includes the design of programmable current and voltage reference circuits. Finally, we demonstrated the design of tunable gain op-amp incorporating FG-NCFETs. Programmable integrated circuit building blocks can be used in intelligent analog and digital systems.

Comparative Study of HfTa-based gate-dielectric Ge metal-oxide-semiconductor capacitors with and without AlON interlayer

NASA Astrophysics Data System (ADS)

Xu, J. P.; Zhang, X. F.; Li, C. X.; Chan, C. L.; Lai, P. T.

2010-04-01

The electrical properties and high-field reliability of HfTa-based gate-dielectric metal-oxide-semiconductor (MOS) devices with and without AlON interlayer on Ge substrate are investigated. Experimental results show that the MOS capacitor with HfTaON/AlON stack gate dielectric exhibits low interface-state/oxide-charge densities, low gate leakage, small capacitance equivalent thickness (˜1.1 nm), and high dielectric constant (˜20). All of these should be attributed to the blocking role of the ultrathin AlON interlayer against interdiffusions of Ge, Hf, and Ta and penetration of O into the Ge substrate, with the latter effectively suppressing the unintentional formation of unstable poor-quality low- k GeO x and giving a superior AlON/Ge interface. Moreover, incorporation of N into both the interlayer and high- k dielectric further improves the device reliability under high-field stress through the formation of strong N-related bonds.

Leakage current evaluation for pn junctions formed in DC and RF MeV ion implanted wells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yanagisawa, Yasunobu; Honda, Mitsuharu; Ogasawara, Makota

1996-12-31

The leakage current of pn junctions formed in DC and RF MeV implanted wells have been evaluated. There is no substantial difference in the leakage current levels between the continuous and pulsive beam implantations. However, the leakage current, so called diffusion current, for RF implanted wells is slightly higher than that for DC implanted wells on some condition. This suggests a possibility that relatively higher density of residual defects remains in the case of RIF implant.

Printed indium gallium zinc oxide transistors. Self-assembled nanodielectric effects on low-temperature combustion growth and carrier mobility.

PubMed

Everaerts, Ken; Zeng, Li; Hennek, Jonathan W; Camacho, Diana I; Jariwala, Deep; Bedzyk, Michael J; Hersam, Mark C; Marks, Tobin J

2013-11-27

Solution-processed amorphous oxide semiconductors (AOSs) are emerging as important electronic materials for displays and transparent electronics. We report here on the fabrication, microstructure, and performance characteristics of inkjet-printed, low-temperature combustion-processed, amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) grown on solution-processed hafnia self-assembled nanodielectrics (Hf-SANDs). TFT performance for devices processed below 300 °C includes >4× enhancement in electron mobility (μFE) on Hf-SAND versus SiO2 or ALD-HfO2 gate dielectrics, while other metrics such as subthreshold swing (SS), current on:off ratio (ION:IOFF), threshold voltage (Vth), and gate leakage current (Ig) are unchanged or enhanced. Thus, low voltage IGZO/SAND TFT operation (<2 V) is possible with ION:IOFF = 10(7), SS = 125 mV/dec, near-zero Vth, and large electron mobility, μFE(avg) = 20.6 ± 4.3 cm(2) V(-1) s(-1), μFE(max) = 50 cm(2) V(-1) s(-1). Furthermore, X-ray diffraction analysis indicates that the 300 °C IGZO combustion processing leaves the underlying Hf-SAND microstructure and capacitance intact. This work establishes the compatibility and advantages of all-solution, low-temperature fabrication of inkjet-printed, combustion-derived high-mobility IGZO TFTs integrated with self-assembled hybrid organic-inorganic nanodielectrics.

Oxygen vacancy defect engineering using atomic layer deposited HfAlOx in multi-layered gate stack

NASA Astrophysics Data System (ADS)

Bhuyian, M. N.; Sengupta, R.; Vurikiti, P.; Misra, D.

2016-05-01

This work evaluates the defects in high quality atomic layer deposited (ALD) HfAlOx with extremely low Al (<3% Al/(Al + Hf)) incorporation in the Hf based high-k dielectrics. The defect activation energy estimated by the high temperature current voltage measurement shows that the charged oxygen vacancies, V+/V2+, are the primary source of defects in these dielectrics. When Al is added in HfO2, the V+ type defects with a defect activation energy of Ea ˜ 0.2 eV modify to V2+ type to Ea ˜ 0.1 eV with reference to the Si conduction band. When devices were stressed in the gate injection mode for 1000 s, more V+ type defects are generated and Ea reverts back to ˜0.2 eV. Since Al has a less number of valence electrons than do Hf, the change in the co-ordination number due to Al incorporation seems to contribute to the defect level modifications. Additionally, the stress induced leakage current behavior observed at 20 °C and at 125 °C demonstrates that the addition of Al in HfO2 contributed to suppressed trap generation process. This further supports the defect engineering model as reduced flat-band voltage shifts were observed at 20 °C and at 125 °C.

Synthesis and Characterization of Hexagonal Boron Nitride as a Gate Dielectric

PubMed Central

Jang, Sung Kyu; Youn, Jiyoun; Song, Young Jae; Lee, Sungjoo

2016-01-01

Two different growth modes of large-area hexagonal boron nitride (h-BN) film, a conventional chemical vapor deposition (CVD) growth mode and a high-pressure CVD growth mode, were compared as a function of the precursor partial pressure. Conventional self-limited CVD growth was obtained below a critical partial pressure of the borazine precursor, whereas a thick h-BN layer (thicker than a critical thickness of 10 nm) was grown beyond a critical partial pressure. An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the CVD h-BN film depended significantly on the film growth mode and the resultant film quality. PMID:27458024

Highly scaled equivalent oxide thickness of 0.66 nm for TiN/HfO2/GaSb MOS capacitors by using plasma-enhanced atomic layer deposition

NASA Astrophysics Data System (ADS)

Tsai, Ming-Li; Wang, Shin-Yuan; Chien, Chao-Hsin

2017-08-01

Through in situ hydrogen plasma treatment (HPT) and plasma-enhanced atomic-layer-deposited TiN (PEALD-TiN) layer capping, we successfully fabricated TiN/HfO2/GaSb metal-oxide-semiconductor capacitors with an ultrathin equivalent oxide thickness of 0.66 nm and a low density of states of approximately 2 × 1012 cm-2 eV-1 near the valence band edge. After in situ HPT, a native oxide-free surface was obtained through efficient etching. Moreover, the use of the in situ PEALD-TiN layer precluded high-κ dielectric damage that would have been caused by conventional sputtering, thereby yielding a superior high-κ dielectric and low gate leakage current.

Thermal Stress Analysis of Floating-Gate Tunneling Oxide Electrically Erasable Programmable Read Only Memory During Manufacturing Process

NASA Astrophysics Data System (ADS)

Zong, Xiang-fu; Wang, Xu; Weng, Yu-min; Yan, Ren-jin; Tang, Guo-an; Zhang, Zhao-qiang

1998-10-01

In this study, finite element modeling was used to evaluate the residual thermal stress in floating-gate tunneling oxide electrically erasable programmable read only memory (FLOTOX E2 PROMs) manufacturing process. Special attention is paid to the tunnel oxide region, in which high field electron injection is the basis to E2 PROMs operation. Calculated results show the presence of large stresses and stress gradients at the fringe. This may contribute to the invalidation of E2 PROMs. A possible failure mechanism of E2 PROM related to residual thermal stress-induced leakage is proposed.

An LOD with improved breakdown voltage in full-frame CCD devices

NASA Astrophysics Data System (ADS)

Banghart, Edmund K.; Stevens, Eric G.; Doan, Hung Q.; Shepherd, John P.; Meisenzahl, Eric J.

2005-02-01

In full-frame image sensors, lateral overflow drain (LOD) structures are typically formed along the vertical CCD shift registers to provide a means for preventing charge blooming in the imager pixels. In a conventional LOD structure, the n-type LOD implant is made through the thin gate dielectric stack in the device active area and adjacent to the thick field oxidation that isolates the vertical CCD columns of the imager. In this paper, a novel LOD structure is described in which the n-type LOD impurities are placed directly under the field oxidation and are, therefore, electrically isolated from the gate electrodes. By reducing the electrical fields that cause breakdown at the silicon surface, this new structure permits a larger amount of n-type impurities to be implanted for the purpose of increasing the LOD conductivity. As a consequence of the improved conductance, the LOD width can be significantly reduced, enabling the design of higher resolution imaging arrays without sacrificing charge capacity in the pixels. Numerical simulations with MEDICI of the LOD leakage current are presented that identify the breakdown mechanism, while three-dimensional solutions to Poisson's equation are used to determine the charge capacity as a function of pixel dimension.

Engineering epitaxial γ-Al2O3 gate dielectric films on 4H-SiC

NASA Astrophysics Data System (ADS)

Tanner, Carey M.; Toney, Michael F.; Lu, Jun; Blom, Hans-Olof; Sawkar-Mathur, Monica; Tafesse, Melat A.; Chang, Jane P.

2007-11-01

The formation of epitaxial γ-Al2O3 thin films on 4H-SiC was found to be strongly dependent on the film thickness. An abrupt interface was observed in films up to 200 Å thick with an epitaxial relationship of γ-Al2O3(111)‖4H-SiC(0001) and γ-Al2O3(44¯0)‖4H-SiC(112¯0). The in-plane alignment between the film and the substrate is nearly complete for γ-Al2O3 films up to 115 Å thick, but quickly diminishes in thicker films. The films are found to be slightly strained laterally in tension; the strain increases with thickness and then decreases in films thicker than 200 Å, indicating strain relaxation which is accompanied by increased misorientation. By controlling the structure of ultrathin Al2O3 films, metal-oxide-semiconductor capacitors with Al2O3 gate dielectrics on 4H-SiC were found to have a very low leakage current density, suggesting suitability of Al2O3 for SiC device integration.

Simulation design of high reverse blocking high-K/low-K compound passivation AlGaN/GaN Schottky barrier diode with gated edge termination

NASA Astrophysics Data System (ADS)

Bai, Zhiyuan; Du, Jiangfeng; Xin, Qi; Li, Ruonan; Yu, Qi

2017-11-01

In this paper, a novel high-K/low-K compound passivation AlGaN/GaN Schottky Barrier Diode (CPG-SBD) is proposed to improve the off-state characteristics of AlGaN/GaN schottky barrier diode with gated edge termination (GET-SBD) by adding low-K blocks in to the high-K passivation layer. The reverse leakage current of CPG-SBD can be reduced to 1.6 nA/mm by reducing the thickness of high-K dielectric under GET region to 5 nm, while the forward voltage and on-state resistance keep 1 V and 3.8 Ω mm, respectively. Breakdown voltage of CPG-SBDs can be improved by inducing discontinuity of the electric field at the high-K/low-K interface. The breakdown voltage of the optimized CPG-SBD with 4 blocks of low-K can reach 1084 V with anode to cathode distance of 5 μm yielding a high FOM of 5.9 GW/cm2. From the C-V simulation results, CPG-SBDs induce no parasitic capacitance by comparison of the GET-SBDs.

Four Terminal Gallium Nitride MOSFETs

NASA Astrophysics Data System (ADS)

Veety, Matthew Thomas

All reported gallium nitride (GaN) transistors to date have been three-terminal devices with source, drain, and gate electrodes. In the case of GaN MOSFETs, this leaves the bulk of the device at a floating potential which can impact device threshold voltage. In more traditional silicon-based MOSFET fabrication a bulk contact can be made on the back side of the silicon wafer. For GaN grown on sapphire substrates, however, this is not possible and an alternate, front-side bulk contact must be investigated. GaN is a III-V, wide band gap semiconductor that as promising material parameters for use in high frequency and high power applications. Possible applications are in the 1 to 10 GHz frequency band and power inverters for next generation grid solid state transformers and inverters. GaN has seen significant academic and commercial research for use in Heterojunction Field Effect Transistors (HFETs). These devices however are depletion-mode, meaning the device is considered "on" at zero gate bias. A MOSFET structure allows for enhancement mode operation, which is normally off. This mode is preferrable in high power applications as the device has lower off-state power consumption and is easier to implement in circuits. Proper surface passivation of seminconductor surface interface states is an important processing step for any device. Preliminary research on surface treatments using GaN wet etches and depletion-mode GaN devices utilizing this process are discussed. Devices pretreated with potassium pursulfate prior to gate dielectric deposition show significant device improvements. This process can be applied to any current GaN FET. Enhancement-mode GaN MOSFETs were fabricated on magnesium doped p-type Wurtzite gallium nitride grown by Metal Organic Chemical Vapor Deposition (MOCVD) on c-plane sapphire substrates. Devices utilized ion implant source and drain which was activated under NH3 overpressure in MOCVD. Also, devices were fabricated with a SiO2 gate dielectric and metal gate. Preliminary devices exhibited high GaN-oxide interface state density, Dit, on the order of 1013 cm-2· eV-1. Additional experiments and device fabrication was focused on improving device performance through optimization of the ion implantation activation anneal as well as incorporation of a bulk p-type ohmic contact and migration to a thicker, lower defect density, HVPE-grown template substrate. The first reported MOSFET on HVPE grown GaN substrates (templates) is reported with peak measured drain current of 1.05 mA/mm and a normalized transconductance of 57 muS/mm. Fabricated devices exhibited large (greater than 1 muA) source-to-drain junction leakage which is attributed to low activated doping density in the MOCVD-grown p-type bulk. MOSFETs fabricated on template substrates show more than twice the measured drain current as similar devices fabricated on traditional MOCVD GaN on sapphire substrates for the same bias conditions. Also, template MOSFETs have decreased gate leakage which allowed for a much greater range of operation. This performance increase is attributed to a more than doubled effective channel mobility on template GaN MOSFETs due to decreased crystal defect scattering when compared to a MOCVD-grown GaN-on-sapphire MOSFET. Fabricated MOSFETs also exhibit decreased interface state density with lower bound of 2.2x1011 cm-2·eV-1 when compared to prelimary MOSFETs. This decrease is associated with the use of a sacrificial oxide cap during source/drain activation. Suggested work for continued research is also presented which includes experiments to improve source/drain ion implantation profile, utilization of selective area growth for the active area, improved n- and p-type ohmic contact resistance and investigation of alternate oxides.

Synthesis and Characterization of Cross-Linked Nanocomposite as a Gate Dielectric for p-Type Silicon Field-Effect Transistor

NASA Astrophysics Data System (ADS)

Hashemi, Adeleh; Bahari, Ali; Ghasemi, Shahram

2018-03-01

A good cross-linking between a povidone-silicon oxide nanocomposite has been created using a polar solvent. Furthermore, the effect of annealing temperatures (150°C, 200°C, and 240°C) on the solution-processed povidone-silicon oxide dielectric films has been studied. Fourier transform infrared spectroscopy and x-ray photoelectron spectroscopy were applied to identify the chemical interactions of the nanocomposite. Morphology of the thin films was examined using atomic force microscopy. Electrical parameters of field effect transistors (FETs) were calculated on the basis of the information obtained from current-voltage (I-V) and capacitance-voltage (C-V) measurements in the metal-insulator-semiconductor structure. Nanocomposite films had very low surface roughness (0.036-0.084 nm). Si-O-Si and Si-O-C covalent bonds as well as Si-OH hydrogen bonds were formed in the nanocomposite structure. High hole mobilities (1.15-3.87 cm2 V-1 s-1) and low leakage current densities were obtained for the p-type Si FETs. The decrease in the Si-OH hydrogen bonds in the dielectric film annealed at 150°C led to a decrease in capacitance and leakage current as well as threshold voltage, and resulted in an increase in mobility and on/off current ratio. By further increasing the annealing temperatures (200°C and 240°C), the binding energies of all the bonds were shifted toward lower values. Therefore, it was concluded that many bonds could have degraded and that defects might have formed in the dielectric film nanostructure leading to a decline in the electrical parameters of the FETs.

Leakage current conduction mechanisms and electrical properties of atomic-layer-deposited HfO2/Ga2O3 MOS capacitors

NASA Astrophysics Data System (ADS)

Zhang, Hongpeng; Jia, Renxu; Lei, Yuan; Tang, Xiaoyan; Zhang, Yimen; Zhang, Yuming

2018-02-01

In this paper, current conduction mechanisms in HfO2/β-Ga2O3 metal-oxide-semiconductor (MOS) capacitors under positive and negative biases are investigated using the current-voltage (I-V) measurements conducted at temperatures from 298 K to 378 K. The Schottky emission is dominant under positively biased electric fields of 0.37-2.19 MV cm-1, and the extracted Schottky barrier height ranged from 0.88 eV to 0.91 eV at various temperatures. The Poole-Frenkel emission dominates under negatively biased fields of 1.92-4.83 MV cm-1, and the trap energy levels are from 0.71 eV to 0.77 eV at various temperatures. The conduction band offset (ΔE c) of HfO2/β-Ga2O3 is extracted to be 1.31  ±  0.05 eV via x-ray photoelectron spectroscopy, while a large negative sheet charge density of 1.04  ×  1013 cm-2 is induced at the oxide layer and/or HfO2/β-Ga2O3 interface. A low C-V hysteresis of 0.76 V, low interface state density (D it) close to 1  ×  1012 eV-1 cm-2, and low leakage current density of 2.38  ×  10-5 A cm-2 at a gate voltage of 7 V has been obtained, suggesting the great electrical properties of HfO2/β-Ga2O3 MOSCAP. According to the above analysis, ALD-HfO2 is an attractive candidate for high voltage β-Ga2O3 power devices.

Leakage current reduction of vertical GaN junction barrier Schottky diodes using dual-anode process

NASA Astrophysics Data System (ADS)

Hayashida, Tetsuro; Nanjo, Takuma; Furukawa, Akihiko; Watahiki, Tatsuro; Yamamuka, Mikio

2018-04-01

The origin of the leakage current of a trench-type vertical GaN diode was discussed. We found that the edge of p-GaN is the main leakage spot. To reduce the reverse leakage current at the edge of p-GaN, a dual-anode process was proposed. As a result, the reverse blocking voltage defined at the leakage current density of 1 mA/cm2 of a vertical GaN junction barrier Schottky (JBS) diode was improved from 780 to 1,190 V, which is the highest value ever reported for vertical GaN Schottky barrier diodes (SBDs).

Interfacial, Electrical, and Band Alignment Characteristics of HfO2/Ge Stacks with In Situ-Formed SiO2 Interlayer by Plasma-Enhanced Atomic Layer Deposition

NASA Astrophysics Data System (ADS)

Cao, Yan-Qiang; Wu, Bing; Wu, Di; Li, Ai-Dong

2017-05-01

In situ-formed SiO2 was introduced into HfO2 gate dielectrics on Ge substrate as interlayer by plasma-enhanced atomic layer deposition (PEALD). The interfacial, electrical, and band alignment characteristics of the HfO2/SiO2 high-k gate dielectric stacks on Ge have been well investigated. It has been demonstrated that Si-O-Ge interlayer is formed on Ge surface during the in situ PEALD SiO2 deposition process. This interlayer shows fantastic thermal stability during annealing without obvious Hf-silicates formation. In addition, it can also suppress the GeO2 degradation. The electrical measurements show that capacitance equivalent thickness of 1.53 nm and a leakage current density of 2.1 × 10-3 A/cm2 at gate bias of Vfb + 1 V was obtained for the annealed sample. The conduction (valence) band offsets at the HfO2/SiO2/Ge interface with and without PDA are found to be 2.24 (2.69) and 2.48 (2.45) eV, respectively. These results indicate that in situ PEALD SiO2 may be a promising interfacial control layer for the realization of high-quality Ge-based transistor devices. Moreover, it can be demonstrated that PEALD is a much more powerful technology for ultrathin interfacial control layer deposition than MOCVD.

Interfacial, Electrical, and Band Alignment Characteristics of HfO2/Ge Stacks with In Situ-Formed SiO2 Interlayer by Plasma-Enhanced Atomic Layer Deposition.

PubMed

Cao, Yan-Qiang; Wu, Bing; Wu, Di; Li, Ai-Dong

2017-12-01

In situ-formed SiO 2 was introduced into HfO 2 gate dielectrics on Ge substrate as interlayer by plasma-enhanced atomic layer deposition (PEALD). The interfacial, electrical, and band alignment characteristics of the HfO 2 /SiO 2 high-k gate dielectric stacks on Ge have been well investigated. It has been demonstrated that Si-O-Ge interlayer is formed on Ge surface during the in situ PEALD SiO 2 deposition process. This interlayer shows fantastic thermal stability during annealing without obvious Hf-silicates formation. In addition, it can also suppress the GeO 2 degradation. The electrical measurements show that capacitance equivalent thickness of 1.53 nm and a leakage current density of 2.1 × 10 -3 A/cm 2 at gate bias of V fb  + 1 V was obtained for the annealed sample. The conduction (valence) band offsets at the HfO 2 /SiO 2 /Ge interface with and without PDA are found to be 2.24 (2.69) and 2.48 (2.45) eV, respectively. These results indicate that in situ PEALD SiO 2 may be a promising interfacial control layer for the realization of high-quality Ge-based transistor devices. Moreover, it can be demonstrated that PEALD is a much more powerful technology for ultrathin interfacial control layer deposition than MOCVD.

Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

PubMed Central

Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

2016-01-01

The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer. PMID:26861833

Effects of vacuum rapid thermal annealing on the electrical characteristics of amorphous indium gallium zinc oxide thin films

NASA Astrophysics Data System (ADS)

Lee, Hyun-Woo; Cho, Won-Ju

2018-01-01

We investigated the effects of vacuum rapid thermal annealing (RTA) on the electrical characteristics of amorphous indium gallium zinc oxide (a-IGZO) thin films. The a-IGZO films deposited by radiofrequency sputtering were subjected to vacuum annealing under various temperature and pressure conditions with the RTA system. The carrier concentration was evaluated by Hall measurement; the electron concentration of the a-IGZO film increased and the resistivity decreased as the RTA temperature increased under vacuum conditions. In a-IGZO thin-film transistors (TFTs) with a bottom-gate top-contact structure, the threshold voltage decreased and the leakage current increased as the vacuum RTA temperature increased. As the annealing pressure decreased, the threshold voltage decreased, and the leakage current increased. X-ray photoelectron spectroscopy indicated changes in the lattice oxygen and oxygen vacancies of the a-IGZO films after vacuum RTA. At higher annealing temperatures, the lattice oxygen decreased and oxygen vacancies increased, which suggests that oxygen was diffused out in a reduced pressure atmosphere. The formation of oxygen vacancies increased the electron concentration, which consequently increased the conductivity of the a-IGZO films and reduced the threshold voltage of the TFTs. The results showed that the oxygen vacancies and electron concentrations of the a-IGZO thin films changed with the vacuum RTA conditions and that high-temperature RTA treatment at low pressure converted the IGZO thin film to a conductor.

Electrical properties of pseudo-single-crystalline Ge films grown by Au-induced layer exchange crystallization at 250 °C

NASA Astrophysics Data System (ADS)

Higashi, H.; Kudo, K.; Yamamoto, K.; Yamada, S.; Kanashima, T.; Tsunoda, I.; Nakashima, H.; Hamaya, K.

2018-06-01

We study the electrical properties of pseudo-single-crystalline Ge (PSC-Ge) films grown by a Au-induced layer exchange crystallization method at 250 °C. By inserting the SiNx layer between PSC-Ge and SiO2, we initiatively suppress the influence of the Ge/SiO2 interfacial defective layers, which have been reported in our previous works, on the electrical properties of the PSC-Ge layers. As a result, we can detect the influence of the ionized Au+ donors on the temperature-dependent hole concentration and Hall mobility. To further examine their electrical properties in detail, we also fabricate p-thin-film transistors (TFTs) with the PSC-Ge layer. Although the off-state leakage currents are suppressed by inserting the SiNx layer, the value of on/off ratio remains poor (<102). Even after the post-annealing at 400 °C for the TFTs, the on/off ratio is still poor (˜102) because of the gate-induced drain leakage current although a nominal field effect mobility is enhanced up to ˜25 cm2/V s. Considering these features, we conclude that the Au contaminations into the PSC-Ge layer can affect the electrical properties and device performances despite a low-growth temperature of 250 °C. To achieve further high-performance p-TFTs, we have to suppress the Au contaminations into PSC-Ge during the Au-induced crystallization growth.

Channel doping concentration and cell program state dependence on random telegraph noise spatial and statistical distribution in 30 nm NAND flash memory

NASA Astrophysics Data System (ADS)

Tomita, Toshihiro; Miyaji, Kousuke

2015-04-01

The dependence of spatial and statistical distribution of random telegraph noise (RTN) in a 30 nm NAND flash memory on channel doping concentration NA and cell program state Vth is comprehensively investigated using three-dimensional Monte Carlo device simulation considering random dopant fluctuation (RDF). It is found that single trap RTN amplitude ΔVth is larger at the center of the channel region in the NAND flash memory, which is closer to the jellium (uniform) doping results since NA is relatively low to suppress junction leakage current. In addition, ΔVth peak at the center of the channel decreases in the higher Vth state due to the current concentration at the shallow trench isolation (STI) edges induced by the high vertical electrical field through the fringing capacitance between the channel and control gate. In such cases, ΔVth distribution slope λ cannot be determined by only considering RDF and single trap.

Mechanism of high-fluence proton induced electrical degradation in AlGaN/GaN high-electron-mobility transistors

NASA Astrophysics Data System (ADS)

Lei, Zhifeng; Guo, Hongxia; Tang, Minghua; Peng, Chao; Zhang, Zhangang; Huang, Yun; En, Yunfei

2018-07-01

The effects of displacement damage induced by 3 and 6 MeV protons in AlGaN/GaN high-electron-mobility transistors (HEMTs) are investigated. For the 6 MeV protons at a dose of 5 × 1014 cm‑2, a 12% decrease in saturation current, a 3.8% decrease in the peak transconductance, a 0.3 V positive shift of the threshold voltage, and a three-to fourfold decrease in reverse gate leakage current are observed compared with the pre-irradiation values. The main degradation mechanism is considered to be the generation of deep trap states in the band gap, which remove electrons and reduce the carrier mobility in a two-dimensional electron gas (2DEG). Both the carrier removal rate and negatively charged trap density can be extracted, which shows that about 3500 proton injections lead to one carrier removal. Proton fluence and energy are found to be two key parameters that affect the degradation characteristics of irradiated GaN HEMTs.

Capacitorless 1T-DRAM on crystallized poly-Si TFT.

PubMed

Kim, Min Soo; Cho, Won Ju

2011-07-01

The single-transistor dynamic random-access memory (1T-DRAM) using a polycrystalline-silicon thin-film transistor (poly-Si TFT) was investigated. A 100-nm amorphous silicon thin film was deposited onto a 200-nm oxidized silicon wafer via low-pressure chemical vapor deposition (LPCVD), and the amorphous silicon layer was crystallized via eximer laser annealing (ELA) with a KrF source of 248 nm wavelength and 400 mJ/cm2 power. The fabricated capacitor less 1T-DRAM on the poly-Si TFT was evaluated via impact ionization and gate-induced drain leakage (GIDL) current programming. The device showed a clear memory margin between the "1" and "0" states, and as the channel length decreased, a floating body effect which induces a kink effect increases with high mobility. Furthermore, the GIDL current programming showed improved memory properties compared to the impact ionization method. Although the sensing margins and retention times in both program methods are commercially insufficient, it was confirmed the feasibility of the application of 1T-DRAM operation to TFTs.

Interface properties of SiO2/GaN structures formed by chemical vapor deposition with remote oxygen plasma mixed with Ar or He

NASA Astrophysics Data System (ADS)

Truyen, Nguyen Xuan; Taoka, Noriyuki; Ohta, Akio; Makihara, Katsunori; Yamada, Hisashi; Takahashi, Tokio; Ikeda, Mitsuhisa; Shimizu, Mitsuaki; Miyazaki, Seiichi

2018-06-01

The impacts of noble gas species (Ar and He) on the formation of a SiO2/GaN structure formed by a remote oxygen plasma-enhanced chemical vapor deposition (ROPE-CVD) method were systematically investigated. Atomic force microscopy revealed that ROPE-CVD with He leads to a smooth SiO2 surface compared with the case of Ar. We found that no obvious oxidations of the GaN surfaces after the SiO2 depositions with the both Ar and He cases were observed. The capacitance–voltage (C–V) curves of the GaN MOS capacitors formed by ROPE-CVD with the Ar and He dilutions show good interface properties with no hysteresis and good agreement with the ideal C–V curves even after post deposition annealing at 800 °C. Besides, we found that the current density–oxide electric field characteristics shows a gate leakage current for the Ar case lower than the He case.

Influence of thermal aging on AC leakage current in XLPE insulation

NASA Astrophysics Data System (ADS)

Geng, Pulong; Song, Jiancheng; Tian, Muqin; Lei, Zhipeng; Du, Yakun

2018-02-01

Cross-linked polyethylene (XLPE) has been widely used as cable insulation material because of its excellent dielectric properties, thermal stability and solvent resistance. To understand the influence of thermal aging on AC leakage current in XLPE insulation, all XLPE specimens were aged in oven in temperature range from 120 °C to 150 °C, and a series of tests were conducted on these XLPE specimens in different aging stages to measure the characteristic parameters, such as complex permittivity, leakage current and complex dielectric modulus. In the experiments, the effects of thermal aging, temperature and frequency on the AC leakage current in XLPE insulation were studied by analyzing complex dielectric constant and dielectric relaxation modulus spectrum, the change of relaxation peak and activation energy. It has been found that the active part of leakage current increases sharply with the increase of aging degree, and the test temperature and frequency have an influence on AC leakage current but the influence of test temperature is mainly reflected in the low frequency region. In addition, it has been shown by the experiments that the reactive part of leakage current exhibits a strong frequency dependent characteristic in the testing frequency range from 10-2 Hz to 105 Hz, but the influence of test temperature and thermal aging on it is relatively small.

Pentacene-based metal-insulator-semiconductor memory structures utilizing single walled carbon nanotubes as a nanofloating gate

NASA Astrophysics Data System (ADS)

Sleiman, A.; Rosamond, M. C.; Alba Martin, M.; Ayesh, A.; Al Ghaferi, A.; Gallant, A. J.; Mabrook, M. F.; Zeze, D. A.

2012-01-01

A pentacene-based organic metal-insulator-semiconductor memory device, utilizing single walled carbon nanotubes (SWCNTs) for charge storage is reported. SWCNTs were embedded, between SU8 and polymethylmethacrylate to achieve an efficient encapsulation. The devices exhibit capacitance-voltage clockwise hysteresis with a 6 V memory window at ± 30 V sweep voltage, attributed to charging and discharging of SWCNTs. As the applied gate voltage exceeds the SU8 breakdown voltage, charge leakage is induced in SU8 to allow more charges to be stored in the SWCNT nodes. The devices exhibited high storage density (˜9.15 × 1011 cm-2) and demonstrated 94% charge retention due to the superior encapsulation.

Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

NASA Astrophysics Data System (ADS)

Ashenafi, Emeshaw

Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse-with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on-ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.

Leakage current-induced effects in the silicon microstrip and gas electron multiplier readout chain and their compensation method

NASA Astrophysics Data System (ADS)

Zubrzycka, W.; Kasinski, K.

2018-04-01

Leakage current flowing into the charge sensitive amplifier (CSA) is a common issue in many radiation detection systems as it can increase overall system noise, shift a DC baseline or even lead a recording channel to instability. The commonly known leakage current contributor is a detector, however other system components like wires or an input protection circuit may become a serious problem. Compensation of the leakage current resulting from the electrostatic discharge (ESD) protection circuit by properly sizing its components is possible only for a narrow temperature range. Moreover, the leakage current from external sources can be significantly larger. Many applications, especially High Energy Physics (HEP) experiments, require a fast baseline restoration for high input hit rates by applying either a low-value feedback resistor or a high feedback resistance combined with a pulsed reset circuit. Leakage current flowing in the feedback in conjunction with a large feedback resistance supplied with a pulsed reset results in a significant voltage offset between the CSA input and output which can cause problems (e.g. fake hits or instability). This paper shows an issue referred to the leakage current of the ESD protection circuit flowing into the input amplifier. The following analysis and proposed solution is a result of the time and energy readout ASIC project realization for the Compressed Baryonic Matter (CBM) experiment at FAIR (Facility for Antiproton and Ion Research) in Darmstadt, Germany. This chip is purposed to work with microstrip and gaseous detectors, with high average input pulses frequencies (250 kHit/s per channel) and the possibility to process input charge of both polarities. We present measurements of the test structure fabricated in UMC 180 nm technology and propose a solution addressing leakage current related issues. This work combines the leakage current compensation capabilities at the CSA level with high, controllable value of the amplifier feedback resistor independent of the leakage current level and polarity. The simulation results of the double, switchable, Krummenacher circuit-based feedback application in the CSA with a pulsed reset functionality are presented.

Atomic Layer Deposition of HfO2 and Si Nitride on Ge Substrates

NASA Astrophysics Data System (ADS)

Zhu, Shiyang; Nakajima, Anri

2007-12-01

Hafnium oxide (HfO2) thin films were deposited on Ge substrates at 300 °C using atomic layer deposition (ALD) with tetrakis(diethylamino)hafnium (termed as TDEAH) as a precursor and water as an oxidant. The deposition rate was estimated to be 0.09 nm/cycle and the deposited HfO2 films have a smooth surface and an almost stoichiometric composition, indicating that the growth follows a layer-by-layer kinetics, similarly to that on Si substrates. Si nitride thin films were also deposited on Ge by ALD using SiCl4 as a precursor and NH3 as an oxidant. Si nitride has a smaller deposition rate of about 0.055 nm/cycle and a larger gate leakage current than HfO2 deposited on Ge by ALD.

Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

PubMed Central

Pavunny, Shojan P.; Scott, James F.; Katiyar, Ram S.

2014-01-01

A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k) of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS) specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS), bipolar (Bi) and BiCMOS chips applications, is presented in this review article. PMID:28788589

Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

NASA Astrophysics Data System (ADS)

Imamoto, Takuya; Ma, Yitao; Muraguchi, Masakazu; Endoh, Tetsuo

2015-04-01

In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 µA/µm for n-type 149 µA/µm for p-type), low off-leakage current (28.1 pA/µm for n-type and 79.6 pA/µm for p-type), and excellent on-off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (L\\text{gate}WS\\text{Id}/I\\text{d}2 of 10-13-10-11 µm2/Hz for n-type and 10-12-10-10 µm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

Synthesis, integration, and characterization of metal oxide films as alternative gate dielectric materials

NASA Astrophysics Data System (ADS)

Lin, You-Sheng

ZrO2 and HfO2 were investigated in this study to replace SiO2 as the potential gate dielectric materials in metal-oxide-semiconductor field effect transistors. ZrO2 and HfO2 films were deposited on p-type Si (100) wafers by an atomic layer chemical vapor deposition (ALCVD) process using zirconium (IV) t-butoxide and hafnium (IV) t-butoxide as the metal precursors, respectively. Oxygen was used alternatively with these metal alkoxide precursors into the reactor with purging and evacuation in between. The as-deposited ZrO2 and HfO2 films were stoichiometric and uniform based on X-ray photoemission spectroscopy and ellipsometry measurements. X-ray diffraction analysis indicated that the deposited films were amorphous, however, the high-resolution transmission electron microscopy showed an interfacial layer formation on the silicon substrate. Time-of-flight secondary ion mass spectrometry and medium energy ion scattering analysis showed significant intermixing between metal oxides and Si, indicating the formation of metal silicates, which were confirmed by their chemical etching resistance in HF solutions. The thermal stability of ZrO2 and HfO2 thin films on silicon was examined by monitoring their decomposition temperatures in ultra-high vacuum, using in-situ synchrotron radiation ultra-violet photoemission spectroscopy. The as-deposited ZrO2 and HfO2 thin films were thermally stable up to 880°C and 950°C in vacuum, respectively. The highest achieveable dielectric constants of as-deposited ZrO 2 and HfO2 were 21 and 24, respectively, which were slightly lower than the reported dielectric constants of bulk ZrO2 and HfO 2. These slight reductions in dielectric constants were attributed to the formation of the interfacial metal silicate layers. Very small hysteresis and interface state density were observed for both metal oxide films. Their leakage currents were a few orders of magnitude lower than that of SiO 2 at the same equivalent oxide thickness. NMOSFETs were also fabricated with the as-deposited metal oxide films, and reasonable ID-V D and IG-VG results were obtained. The electron mobilities were high from devices built using a plasma etching process to pattern the metal oxide films. However, they can be degraded if an HF wet etching process was used due to the large contact resistences. Upon oxygen annealing, the formation of SiOx at the interface improved the thermal stability of the as-deposited metal oxide films, however, lower overall dielectric constant and higher leakage current were observed. Upon ammonia annealing, the formation of SiOxNy improved not only the thermal stability but also reduced the leakage current. However, the overall dielectric constant of the film was still reduced due to the formation of the additional interfacial layer.

SLD-MOSCNT: A new MOSCNT with step-linear doping profile in the source and drain regions

NASA Astrophysics Data System (ADS)

Tahne, Behrooz Abdi; Naderi, Ali

2017-01-01

In this paper, a new structure, step-linear doping MOSCNT (SLD-MOSCNT), is proposed to improve the performance of basic MOSCNTs. The basic structure suffers from band to band tunneling (BTBT). We show that using SLD profile for source and drain regions increases the horizontal distance between valence and conduction bands at gate to source/drain junction which reduces BTBT probability. SLD performance is compared with other similar structures which have recently been proposed to reduce BTBT such as MOSCNT with lightly-doped drain and source (LDDS), and with double-light doping in source and drain regions (DLD). The obtained results using a nonequilibrium Green’s function (NEGF) method show that the SLD-MOSCNT has the lowest leakage current, power consumption and delay time, and the highest current ratio and voltage gain. The ambipolar conduction in the proposed structure is very low and can be neglected. In addition, these structures can improve short-channel effects. Also, the investigation of cutoff frequency of the different structures shows that the SLD has the highest cutoff frequency. Device performance has been investigated for gate length from 8 to 20 nm which demonstrates all discussions regarding the superiority of the proposed structure are also valid for different channel lengths. This improvement is more significant especially for channel length less than 12 nm. Therefore, the SLD can be considered as a candidate to be used in the applications with high speed and low power consumption.

Dual-Gate p-GaN Gate High Electron Mobility Transistors for Steep Subthreshold Slope.

PubMed

Bae, Jong-Ho; Lee, Jong-Ho

2016-05-01

A steep subthreshold slope characteristic is achieved through p-GaN gate HEMT with dual-gate structure. Obtained subthreshold slope is less than 120 μV/dec. Based on the measured and simulated data obtained from single-gate device, breakdown of parasitic floating-base bipolar transistor and floating gate charged with holes are responsible to increase abruptly in drain current. In the dual-gate device, on-current degrades with high temperature but subthreshold slope is not changed. To observe the switching speed of dual-gate device and transient response of drain current are measured. According to the transient responses of drain current, switching speed of the dual-gate device is about 10(-5) sec.

Simulation of leakage current measurement on medical devices using helmholtz coil configuration with different current flow

NASA Astrophysics Data System (ADS)

Sutanto, E.; Chandra, F.; Dinata, R.

2017-05-01

Leakage current measurement which can follow IEC standard for medical device is one of many challenges to be answered. The IEC 60601-1 has defined that the limit for a leakage current for Medical Device can be as low as 10 µA and as high as 500 µA, depending on which type of contact (applied part) connected to the patient. Most people are using ELCB (Earth-leakage circuit breaker) for safety purpose as this is the most common and available safety device in market. One type of ELCB devices is RCD (Residual Current Device) and this RCD type can measure the leakage current directly. This work will show the possibility on how Helmholtz Coil Configuration can be made to be like the RCD. The possibility is explored by comparing the magnetic field formula from each device, then it proceeds with a simulation using software EJS (Easy Java Simulation). The simulation will make sure the concept of magnetic field current cancellation follows the RCD concept. Finally, the possibility of increasing the measurement’s sensitivity is also analyzed. The sensitivity is needed to see the possibility on reaching the minimum leakage current limit defined by IEC, 0.01mA.

Finite Element Analysis of Film Stack Architecture for Complementary Metal-Oxide-Semiconductor Image Sensors.

PubMed

Wu, Kuo-Tsai; Hwang, Sheng-Jye; Lee, Huei-Huang

2017-05-02

Image sensors are the core components of computer, communication, and consumer electronic products. Complementary metal oxide semiconductor (CMOS) image sensors have become the mainstay of image-sensing developments, but are prone to leakage current. In this study, we simulate the CMOS image sensor (CIS) film stacking process by finite element analysis. To elucidate the relationship between the leakage current and stack architecture, we compare the simulated and measured leakage currents in the elements. Based on the analysis results, we further improve the performance by optimizing the architecture of the film stacks or changing the thin-film material. The material parameters are then corrected to improve the accuracy of the simulation results. The simulated and experimental results confirm a positive correlation between measured leakage current and stress. This trend is attributed to the structural defects induced by high stress, which generate leakage. Using this relationship, we can change the structure of the thin-film stack to reduce the leakage current and thereby improve the component life and reliability of the CIS components.

Finite Element Analysis of Film Stack Architecture for Complementary Metal-Oxide–Semiconductor Image Sensors

PubMed Central

Wu, Kuo-Tsai; Hwang, Sheng-Jye; Lee, Huei-Huang

2017-01-01

Image sensors are the core components of computer, communication, and consumer electronic products. Complementary metal oxide semiconductor (CMOS) image sensors have become the mainstay of image-sensing developments, but are prone to leakage current. In this study, we simulate the CMOS image sensor (CIS) film stacking process by finite element analysis. To elucidate the relationship between the leakage current and stack architecture, we compare the simulated and measured leakage currents in the elements. Based on the analysis results, we further improve the performance by optimizing the architecture of the film stacks or changing the thin-film material. The material parameters are then corrected to improve the accuracy of the simulation results. The simulated and experimental results confirm a positive correlation between measured leakage current and stress. This trend is attributed to the structural defects induced by high stress, which generate leakage. Using this relationship, we can change the structure of the thin-film stack to reduce the leakage current and thereby improve the component life and reliability of the CIS components. PMID:28468324

Post-deposition-annealing effect on current conduction in Al2O3 films formed by atomic layer deposition with H2O oxidant

NASA Astrophysics Data System (ADS)

Hiraiwa, Atsushi; Matsumura, Daisuke; Okubo, Satoshi; Kawarada, Hiroshi

2017-02-01

Atomic-layer-deposition (ALD) Al2O3 films are promising as gate insulators of non-Si semiconductor devices. Although they allow relatively small leakage currents just after deposition, ALD Al2O3 films formed at low temperatures are subject to high temperature during fabrication or operation of devices. Therefore, the effect of post-deposition annealing (PDA) on the properties of Al2O3 films is investigated in this study. ALD Al2O3 films formed using H2O oxidant at low temperatures are compacted by PDA, but their mass density and dielectric constant remain approximately unchanged or slightly decrease owing to the desorption of methyl groups contained in the films as impurities. In accordance with these results, the wet etching rate of Al2O3 films is not much reduced by PDA. The conduction current in ALD Al2O3 films formed on Si is reduced by PDA and becomes smaller than that in films formed at the same ALD temperatures as those of PDA. The conduction current for PDA temperatures above 250 °C, however, increases and, accordingly, spoils the merit of low-temperature ALD. Therefore, given that the dielectric constant of annealed films remains low, high-temperature ALD is practically more significant than applying PDA to low-temperature ALD Al2O3 films from the viewpoint of leakage current under the same thermal budget. Space-charge-controlled field emission analysis revealed that, at the aforementioned threshold temperature, PDA abruptly increases the Al2O3/SiO2 interfacial dipoles and simultaneously reduces the amount of the positive charge near the interface. The so-called negative-charge buildup by PDA might be caused by this decrease in the positive charge.

Electrical and band structural analyses of Ti1-x Al x O y films grown by atomic layer deposition on p-type GaAs

NASA Astrophysics Data System (ADS)

An, Youngseo; Mahata, Chandreswar; Lee, Changmin; Choi, Sungho; Byun, Young-Chul; Kang, Yu-Seon; Lee, Taeyoon; Kim, Jiyoung; Cho, Mann-Ho; Kim, Hyoungsub

2015-10-01

Amorphous Ti1-x Al x O y films in the Ti-oxide-rich regime (x  <  0.5) were deposited on p-type GaAs via atomic layer deposition with titanium isopropoxide, trimethylaluminum, and H2O precursor chemistry. The electrical properties and energy band alignments were examined for the resulting materials with their underlying substrates, and significant frequency dispersion was observed in the accumulation region of the Ti-oxide-rich Ti1-x Al x O y films. Although a further reduction in the frequency dispersion and leakage current (under gate electron injection) could be somewhat achieved through a greater addition of Al-oxide in the Ti1-x Al x O y film, the simultaneous decrease in the dielectric constant proved problematic in finding an optimal composition for application as a gate dielectric on GaAs. The spectroscopic band alignment measurements of the Ti-oxide-rich Ti1-x Al x O y films indicated that the band gaps had a rather slow increase with the addition of Al-oxide, which was primarily compensated for by an increase in the valance band offset, while a nearly-constant conduction band offset with a negative electron barrier height was maintained.

A Passive EMI Filter with Access to the Ungrounded Motor Neutral Line-Its Effect on Eliminating Leakage Current from the Inverter Heat Sink-

NASA Astrophysics Data System (ADS)

Doumoto, Takafumi; Akagi, Hirofumi

This paper deals with a leakage current flowing out of the heat sink of a voltage-source PWM inverter. The heat-sink leakage current is caused by a steep change in the common-mode voltage produced by the inverter. It flows through parasitic capacitors between the heat sink and power semiconductor devices when no EMI filter is connected. Experimental results reveal that the heat-sink leakage current flows not into the supply side, but into the motor side. These understandings succeed in describing an equivalent common-mode circuit taking the parasitic capacitors into account. The authors have proposed a passive EMI filter that is unique in access to the ungrounded motor neutral line. It is discussed from this equivalent circuit that the passive EMI filter is effective in preventing the leakage current from flowing. Moreover, installation of another small-sized common-mode inductor at the ac side of the diode rectifier prevents the leakage current from flowing into the supply side. Experimental results obtained from a 200-V, 3.7-kW laboratory system confirm the effectiveness and viability of the EMI filter.

Multifunctional Hybrid Multilayer Gate Dielectrics with Tunable Surface Energy for Ultralow-Power Organic and Amorphous Oxide Thin-Film Transistors.

PubMed

Byun, Hye-Ran; You, Eun-Ah; Ha, Young-Geun

2017-03-01

For large-area, printable, and flexible electronic applications using advanced semiconductors, novel dielectric materials with excellent capacitance, insulating property, thermal stability, and mechanical flexibility need to be developed to achieve high-performance, ultralow-voltage operation of thin-film transistors (TFTs). In this work, we first report on the facile fabrication of multifunctional hybrid multilayer gate dielectrics with tunable surface energy via a low-temperature solution-process to produce ultralow-voltage organic and amorphous oxide TFTs. The hybrid multilayer dielectric materials are constructed by iteratively stacking bifunctional phosphonic acid-based self-assembled monolayers combined with ultrathin high-k oxide layers. The nanoscopic thickness-controllable hybrid dielectrics exhibit the superior capacitance (up to 970 nF/cm 2 ), insulating property (leakage current densities <10 -7 A/cm 2 ), and thermal stability (up to 300 °C) as well as smooth surfaces (root-mean-square roughness <0.35 nm). In addition, the surface energy of the hybrid multilayer dielectrics are easily changed by switching between mono- and bifunctional phosphonic acid-based self-assembled monolayers for compatible fabrication with both organic and amorphous oxide semiconductors. Consequently, the hybrid multilayer dielectrics integrated into TFTs reveal their excellent dielectric functions to achieve high-performance, ultralow-voltage operation (< ± 2 V) for both organic and amorphous oxide TFTs. Because of the easily tunable surface energy, the multifunctional hybrid multilayer dielectrics can also be adapted for various organic and inorganic semiconductors, and metal gates in other device configurations, thus allowing diverse advanced electronic applications including ultralow-power and large-area electronic devices.

Hafnium silicate and hafnium silicon oxynitride gate dielectrics for strained Si_xGe_1-x: Interface stability

NASA Astrophysics Data System (ADS)

Addepalli, Swarna; Sivasubramani, Prasanna; El-Bouanani, Mohamed; Kim, Moon; Gnade, Bruce; Wallace, Robert

2003-03-01

Strained Si_xGe_1-x layers have gained considerable attention due to hole mobility enhancement, and ease of integration with Si-based CMOS technology. The deposition of stable high-κ dielectrics [1] such as hafnium silicate and hafnium silicon oxynitride in direct contact with SiGe would simultaneously improve the capacitance of the gate stack and lower the leakage current for high performance SiGe devices. However, the oxidation of the Si_xGe_1-x substrate either during dielectric deposition or post-deposition processing would degrade device performance due to the thermodynamic instability of germanium oxide [2,3]. Results from XPS, HR-TEM, and C-V, and I-V analyses after various annealing treatments will be presented for hafnium silicate and hafnium silicon oxynitride films deposited on strained Si_xGe_1-x(100), and correlated with dielectric-Si_xGe_1-x(100) interface stability. Implications to the introduction of these oxides as viable gate dielectric candidates for SiGe-based CMOS technology will be discussed. This work is supported by DARPA through SPAWAR Grant No. N66001-00-1-8928, and the Texas Advanced Technology Program. References: [1] G. D. Wilk, R. M. Wallace and J. M. Anthony, Journal of Applied Physics, 89, 5243 (2001) [2] W. S. Liu, J .S. Chen, M.-A. Nicolet, V. Arbet-Engels, K. L. Wang, Journal of Applied Physics, 72, 4444 (1992), and, Applied Physics Letters, 62, 3321 (1993) [3] W. S. Liu, M. -A. Nicolet, H. -H. Park, B. -H. Koak, J. -W. Lee, Journal of Applied Physics, 78, 2631 (1995)

Correlation between dislocations and leakage current of p-n diodes on a free-standing GaN substrate

NASA Astrophysics Data System (ADS)

Usami, Shigeyoshi; Ando, Yuto; Tanaka, Atsushi; Nagamatsu, Kentaro; Deki, Manato; Kushimoto, Maki; Nitta, Shugo; Honda, Yoshio; Amano, Hiroshi; Sugawara, Yoshihiro; Yao, Yong-Zhao; Ishikawa, Yukari

2018-04-01

Dislocations that cause a reverse leakage current in vertical p-n diodes on a GaN free-standing substrate were investigated. Under a high reverse bias, dot-like leakage spots were observed using an emission microscope. Subsequent cathodoluminescence (CL) observations revealed that the leakage spots coincided with part of the CL dark spots, indicating that some types of dislocation cause reverse leakage. When etch pits were formed on the dislocations by KOH etching, three sizes of etch pits were obtained (large, medium, and small). Among these etch pits, only the medium pits coincided with leakage spots. Additionally, transmission electron microscopy observations revealed that pure screw dislocations are present under the leakage spots. The results revealed that 1c pure screw dislocations are related to the reverse leakage in vertical p-n diodes.

Initial leakage current paths in the vertical-type GaN-on-GaN Schottky barrier diodes

NASA Astrophysics Data System (ADS)

Sang, Liwen; Ren, Bing; Sumiya, Masatomo; Liao, Meiyong; Koide, Yasuo; Tanaka, Atsushi; Cho, Yujin; Harada, Yoshitomo; Nabatame, Toshihide; Sekiguchi, Takashi; Usami, Shigeyoshi; Honda, Yoshio; Amano, Hiroshi

2017-09-01

Electrical characteristics of leakage current paths in vertical-type n-GaN Schottky barrier diodes (SBDs) on free-standing GaN substrates are investigated by using photon emission microscopy (PEM). The PEM mapping shows that the initial failure of the SBD devices at low voltages is due to the leakage current paths from polygonal pits in the GaN epilayers. It is observed that these polygonal pits originate from carbon impurity accumulation to the dislocations with a screw-type component by microstructure analysis. For the SBD without polygonal pits, no initial failure is observed and the first leakage appeals at the edge of electrodes as a result of electric field concentration. The mechanism of leakage at pits is explained in terms of trap assisted tunneling through fitting current-voltage characteristics.

Comparison of gate and drain current detection of hydrogen at room temperature with AlGaN /GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Wang, Hung-Ta; Kang, B. S.; Ren, F.; Fitch, R. C.; Gillespie, J. K.; Moser, N.; Jessen, G.; Jenkins, T.; Dettmer, R.; Via, D.; Crespo, A.; Gila, B. P.; Abernathy, C. R.; Pearton, S. J.

2005-10-01

Pt-gated AlGaN /GaN high electron mobility transistors can be used as room-temperature hydrogen gas sensors at hydrogen concentrations as low as 100ppm. A comparison of the changes in drain and gate current-voltage (I-V) characteristics with the introduction of 500ppm H2 into the measurement ambient shows that monitoring the change in drain-source current provides a wider gate voltage operation range for maximum detection sensitivity and higher total current change than measuring the change in gate current. However, over a narrow gate voltage range, the relative sensitivity of detection by monitoring the gate current changes is up to an order of magnitude larger than that of drain-source current changes. In both cases, the changes are fully reversible in <2-3min at 25°C upon removal of the hydrogen from the ambient.

Al203 thin films on Silicon and Germanium substrates for CMOS and flash memory applications

NASA Astrophysics Data System (ADS)

Gopalan, Sundararaman; Dutta, Shibesh; Ramesh, Sivaramakrishnan; Prathapan, Ragesh; Sreehari G., S.

2017-07-01

As scaling of device dimensions has continued, it has become necessary to replace traditional SiO2 with high dielectric constant materials in the conventional CMOS devices. In addition, use of metal gate electrodes and Germanium substrates may have to be used in order to address leakage and mobility issues. Al2O3 is one of the potential candidates both for CMOS and as a blocking dielectric for Flash memory applications owing to its low leakage. In this study, the effects of sputtering conditions and post-deposition annealing conditions on the electrical and reliability characteristics of MOS capacitors using Al2O3 films on Si and Ge substrates with Aluminium gate electrodes have been presented. It was observed that higher sputtering power resulted in larger flat-band voltage (Vfb) shifts, more hysteresis, higher interface state density (Dit) and a poorer reliability. Wit was also found that while a short duration high temperature annealing improves film characteristics, a long duration anneal even at 800C was found to be detrimental to MOS characteristics. Finally, the electronic conduction mechanism in Al2O3 films was also studied. It was observed that the conduction mechanism varied depending on the annealing condition, thickness of film and electric field.

Transport mechanism of reverse surface leakage current in AlGaN/GaN high-electron mobility transistor with SiN passivation

NASA Astrophysics Data System (ADS)

Zheng, Xue-Feng; Fan, Shuang; Chen, Yong-He; Kang, Di; Zhang, Jian-Kun; Wang, Chong; Mo, Jiang-Hui; Li, Liang; Ma, Xiao-Hua; Zhang, Jin-Cheng; Hao, Yue

2015-02-01

The transport mechanism of reverse surface leakage current in the AlGaN/GaN high-electron mobility transistor (HEMT) becomes one of the most important reliability issues with the downscaling of feature size. In this paper, the research results show that the reverse surface leakage current in AlGaN/GaN HEMT with SiN passivation increases with the enhancement of temperature in the range from 298 K to 423 K. Three possible transport mechanisms are proposed and examined to explain the generation of reverse surface leakage current. By comparing the experimental data with the numerical transport models, it is found that neither Fowler-Nordheim tunneling nor Frenkel-Poole emission can describe the transport of reverse surface leakage current. However, good agreement is found between the experimental data and the two-dimensional variable range hopping (2D-VRH) model. Therefore, it is concluded that the reverse surface leakage current is dominated by the electron hopping through the surface states at the barrier layer. Moreover, the activation energy of surface leakage current is extracted, which is around 0.083 eV. Finally, the SiN passivated HEMT with a high Al composition and a thin AlGaN barrier layer is also studied. It is observed that 2D-VRH still dominates the reverse surface leakage current and the activation energy is around 0.10 eV, which demonstrates that the alteration of the AlGaN barrier layer does not affect the transport mechanism of reverse surface leakage current in this paper. Project supported by the National Natural Science Foundation of China (Grant Nos. 61334002, 61106106, and 61474091), the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory, China (Grant No. ZHD201206), the New Experiment Development Funds for Xidian University, China (Grant No. SY1213), the 111 Project, China (Grant No. B12026), the Scientific Research Foundation for the Returned Overseas Chinese Scholars, State Education Ministry, China, and the Fundamental Research Funds for the Central Universities, China (Grant No. K5051325002).

Conversion efficiency of an energy harvester based on resonant tunneling through quantum dots with heat leakage.

PubMed

Kano, Shinya; Fujii, Minoru

2017-03-03

We study the conversion efficiency of an energy harvester based on resonant tunneling through quantum dots with heat leakage. Heat leakage current from a hot electrode to a cold electrode is taken into account in the analysis of the harvester operation. Modeling of electrical output indicates that a maximum heat leakage current is not negligible because it is larger than that of the heat current harvested into electrical power. A reduction of heat leakage is required in this energy harvester in order to obtain efficient heat-to-electrical conversion. Multiple energy levels of a quantum dot can increase the output power of the harvester. Heavily doped colloidal semiconductor quantum dots are a possible candidate for a quantum-dot monolayer in the energy harvester to reduce heat leakage, scaling down device size, and increasing electrical output via multiple discrete energy levels.

Impact of process parameters on the structural and electrical properties of metal/PZT/Al2O3/silicon gate stack for non-volatile memory applications

NASA Astrophysics Data System (ADS)

Singh, Prashant; Jha, Rajesh Kumar; Singh, Rajat Kumar; Singh, B. R.

2018-02-01

In this paper, we present the structural and electrical properties of the Al2O3 buffer layer on non-volatile memory behavior using Metal/PZT/Al2O3/Silicon structures. Metal/PZT/Silicon and Metal/Al2O3/Silicon structures were also fabricated and characterized to obtain capacitance and leakage current parameters. Lead zirconate titanate (PZT::35:65) and Al2O3 films were deposited by sputtering on the silicon substrate. Memory window, PUND, endurance, breakdown voltage, effective charges, flat-band voltage and leakage current density parameters were measured and the effects of process parameters on the structural and electrical characteristics were investigated. X-ray data show dominant (110) tetragonal phase of the PZT film, which crystallizes at 500 °C. The sputtered Al2O3 film annealed at different temperatures show dominant (312) orientation and amorphous nature at 425 °C. Multiple angle laser ellipsometric analysis reveals the temperature dependence of PZT film refractive index and extinction coefficient. Electrical characterization shows the maximum memory window of 3.9 V and breakdown voltage of 25 V for the Metal/Ferroelectric/Silicon (MFeS) structures annealed at 500 °C. With 10 nm Al2O3 layer in the Metal/Ferroelectric/Insulator/Silicon (MFeIS) structure, the memory window and breakdown voltage was improved to 7.21 and 35 V, respectively. Such structures show high endurance with no significant reduction polarization charge for upto 2.2 × 109 iteration cycles.

Characterization of metal-ferroelectric-insulator-semiconductor structures based on ferroelectric Langmuir-Blodgett polyvinylidene fluoride copolymer films for nondestructive random access memory applications

NASA Astrophysics Data System (ADS)

Reece, Timothy James

Ferroelectric field effect transistors (FeFETs) have attracted much attention recently because of their ability to combine high speed, low power consumption, and fast nondestructive readout with the potential for high density nonvolatile memory. The polarization of the ferroelectric is used to switch the channel at the silicon surface between states of high and low conductance. Among the ferroelectric thin films used in FET devices; the ferroelectric copolymer of Polyvinylidene fluoride, PVDF (C2H2F 2), with trifluoroethylene, TrFE (C2HF3), has distinct advantages, including low dielectric constant, low processing temperature, low cost and compatibility with organic semiconductors. By employing the Langmuir-Blodgett technique, films as thin as 1.8 nm can be deposited, reducing the operating voltage. An MFIS structure consisting of aluminum, 170 nm P(VDF-TrFE), 100 nm silicon oxide and n-type silicon exhibited low leakage current (˜1x10 -8 A/cm2), a large memory window (4.2 V) and operated at 35 Volts. The operating voltage was lowered through use of high k insulators like cerium oxide. A sample consisting of 25 nm P(VDF-TrFE), 30 nm cerium oxide and p-type silicon exhibited a 1.9 V window with 7 Volt gate amplitude. The leakage current in this case was considerably higher (1x10 -6 A/cm2). The characterization, modeling, and fabrication of metal-ferroelectricinsulator semiconductor (MFIS) structures based on these films are discussed.

InGaAs/InAlAs single photon avalanche diode for 1550 nm photons.

PubMed

Meng, Xiao; Xie, Shiyu; Zhou, Xinxin; Calandri, Niccolò; Sanzaro, Mirko; Tosi, Alberto; Tan, Chee Hing; Ng, Jo Shien

2016-03-01

A single photon avalanche diode (SPAD) with an InGaAs absorption region, and an InAlAs avalanche region was designed and demonstrated to detect 1550 nm wavelength photons. The characterization included leakage current, dark count rate and single photon detection efficiency as functions of temperature from 210 to 294 K. The SPAD exhibited good temperature stability, with breakdown voltage dependence of approximately 45 mV K(-1). Operating at 210 K and in a gated mode, the SPAD achieved a photon detection probability of 26% at 1550 nm with a dark count rate of 1 × 10(8) Hz. The time response of the SPAD showed decreasing timing jitter (full width at half maximum) with increasing overbias voltage, with 70 ps being the smallest timing jitter measured.

InGaAs/InAlAs single photon avalanche diode for 1550 nm photons

PubMed Central

Xie, Shiyu; Zhou, Xinxin; Calandri, Niccolò; Sanzaro, Mirko; Tosi, Alberto; Tan, Chee Hing; Ng, Jo Shien

2016-01-01

A single photon avalanche diode (SPAD) with an InGaAs absorption region, and an InAlAs avalanche region was designed and demonstrated to detect 1550 nm wavelength photons. The characterization included leakage current, dark count rate and single photon detection efficiency as functions of temperature from 210 to 294 K. The SPAD exhibited good temperature stability, with breakdown voltage dependence of approximately 45 mV K−1. Operating at 210 K and in a gated mode, the SPAD achieved a photon detection probability of 26% at 1550 nm with a dark count rate of 1 × 108 Hz. The time response of the SPAD showed decreasing timing jitter (full width at half maximum) with increasing overbias voltage, with 70 ps being the smallest timing jitter measured. PMID:27069647

Improved interfacial and electrical properties of atomic layer deposition HfO2 films on Ge with La2O3 passivation

NASA Astrophysics Data System (ADS)

Li, Xue-Fei; Liu, Xiao-Jie; Cao, Yan-Qiang; Li, Ai-Dong; Li, Hui; Wu, Di

2013-01-01

We report the characteristics of HfO2 films deposited on Ge substrates with and without La2O3 passivation at 250 °C by atomic layer deposition (ALD) using La[N(SiMe3)2]3 and Hf[N(CH3)(C2H5)]4 as the precursors. The HfO2 is observed to form defective HfGeOx at its interface during 500 °C postdeposition annealing. The insertion of an ultrathin La2O3 interfacial passivation layer effectively prevents the Ge outdiffusion and improves interfacial and electrical properties. Capacitance equivalent thickness (CET) of 1.35 nm with leakage current density JA of 8.3 × 10-4 A/cm2 at Vg = 1 V is achieved for the HfO2/La2O3 gate stacks on Ge substrates.

A CMOS matrix for extracting MOSFET parameters before and after irradiation

NASA Technical Reports Server (NTRS)

Blaes, B. R.; Buehler, M. G.; Lin, Y.-S.; Hicks, K. A.

1988-01-01

An addressable matrix of 16 n- and 16 p-MOSFETs was designed to extract the dc MOSFET parameters for all dc gate bias conditions before and after irradiation. The matrix contains four sets of MOSFETs, each with four different geometries that can be biased independently. Thus the worst-case bias scenarios can be determined. The MOSFET matrix was fabricated at a silicon foundry using a radiation-soft CMOS p-well LOCOS process. Co-60 irradiation results for the n-MOSFETs showed a threshold-voltage shift of -3 mV/krad(Si), whereas the p-MOSFETs showed a shift of 21 mV/krad(Si). The worst-case threshold-voltage shift occurred for the n-MOSFETs, with a gate bias of 5 V during the anneal. For the p-MOSFETs, biasing did not affect the shift in the threshold voltage. A parasitic MOSFET dominated the leakage of the n-MOSFET biased with 5 V on the gate during irradiation. Co-60 test results for other parameters are also presented.

FELERION: a new approach for leakage power reduction

NASA Astrophysics Data System (ADS)

R, Anjana; Somkuwar, Ajay

2014-12-01

The circuit proposed in this paper simultaneously reduces the sub threshold leakage power and saves the state of art aspect of the logic circuits. Sleep transistors and PMOS-only logic are used to further reduce the leakage power. Sleep transistors are used as the keepers to reduce the sub threshold leakage current providing the low resistance path to the output. PMOS-only logic is used between the pull up and pull down devices to mitigate the leakage power further. Our proposed fast efficient leakage reduction circuit not only reduces the leakage current but also reduces the power dissipation. Power and delay are analyzed at the 32 nm BSIM4 model for a chain of four inverters, NAND, NOR and ISCAS-85 c17 benchmark circuits using DSCH3 and the Microwind tool. The simulation results reveal that our proposed approach mitigates leakage power by 90%-94% as compared to the conventional approach.

Investigation of mercury thruster isolators. [service life

NASA Technical Reports Server (NTRS)

Mantenieks, M. A.

1973-01-01

Mercury ion thruster isolator lifetime tests were performed using different isolator materials and geometries. Tests were performed with and without the flow of mercury through the isolators in an oil diffusion pumped vacuum facility and cryogenically pumped bell jar. The onset of leakage current in isolators tested occurred in time intervals ranging from a few hours to many hundreds of hours. In all cases, surface contamination was responsible for the onset of leakage current and subsequent isolator failure. Rate of increase of leakage current and the leakage current level increased approximately exponentially with isolator temperature. Careful attention to shielding techniques and the elimination of sources of metal oxides appear to have eliminated isolator failures as a thruster life limiting mechanism.

Self-compensating design for reduction of timing and leakage sensitivity to systematic pattern dependent variation

NASA Astrophysics Data System (ADS)

Gupta, Puneet; Kahng, Andrew B.; Kim, Youngmin; Sylvester, Dennis

2006-03-01

Focus is one of the major sources of linewidth variation. CD variation caused by defocus is largely systematic after the layout is finished. In particular, dense lines "smile" through focus while isolated lines "frown" in typical Bossung plots. This well-defined systematic behavior of focus-dependent CD variation allows us to develop a self-compensating design methodology. In this work, we propose a novel design methodology that allows explicit compensation of focus-dependent CD variation, either within a cell (self-compensated cells) or across cells in a critical path (self-compensated design). By creating iso and dense variants for each library cell, we can achieve designs that are more robust to focus variation. Optimization with a mixture of iso and dense cell variants is possible both for area and leakage power, with the latter providing an interesting complement to existing leakage reduction techniques such as dual-Vth. We implement both heuristic and Mixed-Integer Linear Programming (MILP) solution methods to address this optimization, and experimentally compare their results. Our results indicate that designing with a self-compensated cell library incurs ~12% area penalty and ~6% leakage increase over original layouts while compensating for focus-dependent CD variation (i.e., the design meets timing constraints across a large range of focus variation). We observe ~27% area penalty and ~7% leakage increase at the worst-case defocus condition using only single-pitch cells. The area penalty of circuits after using either the heuristic or MILP optimization approach is reduced to ~3% while maintaining timing. We also apply our optimizations to leakage, which traditionally shows very large variability due to its exponential relationship with gate CD. We conclude that a mixed iso/dense library combined with a sensitivity-based optimization approach yields much better area/timing/leakage tradeoffs than using a self-compensated cell library alone. Self-compensated design shows an average of 25% leakage reduction at the worst defocus condition for the benchmark designs that we have studied.

Highly flexible SRAM cells based on novel tri-independent-gate FinFET

NASA Astrophysics Data System (ADS)

Liu, Chengsheng; Zheng, Fanglin; Sun, Yabin; Li, Xiaojin; Shi, Yanling

2017-10-01

In this paper, a novel tri-independent-gate (TIG) FinFET is proposed for highly flexible SRAM cells design. To mitigate the read-write conflict, two kinds of SRAM cells based on TIG FinFETs are designed, and high tradeoff are obtained between read stability and speed. Both cells can offer multi read operations for frequency requirement with single voltage supply. In the first TIG FinFET SRAM cell, the strength of single-fin access transistor (TIG FinFET) can be flexibly adjusted by selecting five different modes to meet the needs of dynamic frequency design. Compared to the previous double-independent-gate (DIG) FinFET SRAM cell, 12.16% shorter read delay can be achieved with only 1.62% read stability decrement. As for the second TIG FinFET SRAM cell, pass-gate feedback technology is applied and double-fin TIG FinFETs are used as access transistors to solve the severe write-ability degradation. Three modes exist to flexibly adjust read speed and stability, and 68.2% larger write margin and 51.7% shorter write delay are achieved at only the expense of 26.2% increase in leakage power, with the same layout area as conventional FinFET SRAM cell.

Improving subthreshold swing to thermionic emission limit in carbon nanotube network film-based field-effect

NASA Astrophysics Data System (ADS)

Zhao, Chenyi; Zhong, Donglai; Qiu, Chenguang; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2018-01-01

In this letter, we explore the vertical scaling-down behavior of carbon nanotube (CNT) network film field-effect transistors (FETs) and show that by using a high-efficiency gate insulator, we can substantially improve the subthreshold swing (SS) and its uniformity. By using an HfO2 layer with a thickness of 7.3 nm as the gate insulator, we fabricated CNT network film FETs with a long channel (>2 μm) that exhibit an SS of approximately 60 mV/dec. The preferred thickness of HfO2 as the gate insulator in a CNT network FET is between 7 nm and 10 nm, simultaneously yielding an excellent SS (<80 mV/decade) and low gate leakage. However, because of the statistical fluctuations of the network CNT channel, the lateral scaling of CNT network film-based FETs is more difficult than that of conventional FETs. Experiments suggest that excellent SS is difficult to achieve statistically in CNT network film FETs with a small channel length (smaller than the mean length of the CNTs), which eventually limits the further scaling down of this kind of CNT FET to the sub-micrometer regime.

SENSITIVITY OF THE HOUSE PRESSURE TEST FOR DUCT LEAKAGE TO VARIATIONS IN THE DISTRIBUTION OF AIR LEAKAGE IN THE HOUSE ENVELOPE

DOE Office of Scientific and Technical Information (OSTI.GOV)

ANDREWS,J.W.

1998-12-01

The house pressure test for air leakage in ducts calculates the signed difference between the supply and return leakage from the response of the air pressure in the house to operation of the system fan. The currently accepted version of this calculation was based on particular assumptions about how the house envelope leakage is distributed between the walls, ceiling, and floor. This report generalizes the equation to account for an arbitrary distribution of envelope leakage. It concludes that the currently accepted equation is usually accurate to within {+-}5%, but in a small proportion of cases the results may diverge bymore » 50% or more.« less

Developing Low-Noise GaAs JFETs For Cryogenic Operation

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.

1995-01-01

Report discusses aspects of effort to develop low-noise, low-gate-leakage gallium arsenide-based junction field-effect transistors (JFETs) for operation at temperature of about 4 K as readout amplifiers and multiplexing devices for infrared-imaging devices. Transistors needed to replace silicon transistors, relatively noisy at 4 K. Report briefly discusses basic physical principles of JFETs and describes continuing process of optimization of designs of GaAs JFETs for cryogenic operation.

Lightning Pin Injection Testing on MOSFETS

NASA Technical Reports Server (NTRS)

Ely, Jay J.; Nguyen, Truong X.; Szatkowski, George N.; Koppen, Sandra V.; Mielnik, John J.; Vaughan, Roger K.; Wysocki, Philip F.; Celaya, Jose R.; Saha, Sankalita

2009-01-01

Lightning transients were pin-injected into metal-oxide-semiconductor field-effect transistors (MOSFETs) to induce fault modes. This report documents the test process and results, and provides a basis for subsequent lightning tests. MOSFETs may be present in DC-DC power supplies and electromechanical actuator circuits that may be used on board aircraft. Results show that unprotected MOSFET Gates are susceptible to failure, even when installed in systems in well-shielded and partial-shielded locations. MOSFET Drains and Sources are significantly less susceptible. Device impedance decreased (current increased) after every failure. Such a failure mode may lead to cascading failures, as the damaged MOSFET may allow excessive current to flow through other circuitry. Preliminary assessments on a MOSFET subjected to 20-stroke pin-injection testing demonstrate that Breakdown Voltage, Leakage Current and Threshold Voltage characteristics show damage, while the device continues to meet manufacturer performance specifications. The purpose of this research is to develop validated tools, technologies, and techniques for automated detection, diagnosis and prognosis that enable mitigation of adverse events during flight, such as from lightning transients; and to understand the interplay between lightning-induced surges and aging (i.e. humidity, vibration thermal stress, etc.) on component degradation.

High performance thin film transistor with ZnO channel layer deposited by DC magnetron sputtering.

PubMed

Moon, Yeon-Keon; Moon, Dae-Yong; Lee, Sang-Ho; Jeong, Chang-Oh; Park, Jong-Wan

2008-09-01

Research in large area electronics, especially for low-temperature plastic substrates, focuses commonly on limitations of the semiconductor in thin film transistors (TFTs), in particular its low mobility. ZnO is an emerging example of a semiconductor material for TFTs that can have high mobility, while a-Si and organic semiconductors have low mobility (<1 cm2/Vs). ZnO-based TFTs have achieved high mobility, along with low-voltage operation low off-state current, and low gate leakage current. In general, ZnO thin films for the channel layer of TFTs are deposited with RF magnetron sputtering methods. On the other hand, we studied ZnO thin films deposited with DC magnetron sputtering for the channel layer of TFTs. After analyzing the basic physical and chemical properties of ZnO thin films, we fabricated a TFT-unit cell using ZnO thin films for the channel layer. The field effect mobility (micro(sat)) of 1.8 cm2/Vs and threshold voltage (Vth) of -0.7 V were obtained.

Oxygen vacancy defect engineering using atomic layer deposited HfAlO{sub x} in multi-layered gate stack

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bhuyian, M. N., E-mail: mnb3@njit.edu; Misra, D.; Sengupta, R.

2016-05-02

This work evaluates the defects in high quality atomic layer deposited (ALD) HfAlO{sub x} with extremely low Al (<3% Al/(Al + Hf)) incorporation in the Hf based high-k dielectrics. The defect activation energy estimated by the high temperature current voltage measurement shows that the charged oxygen vacancies, V{sup +}/V{sup 2+}, are the primary source of defects in these dielectrics. When Al is added in HfO{sub 2}, the V{sup +} type defects with a defect activation energy of E{sub a} ∼ 0.2 eV modify to V{sup 2+} type to E{sub a} ∼ 0.1 eV with reference to the Si conduction band. When devices were stressedmore » in the gate injection mode for 1000 s, more V{sup +} type defects are generated and E{sub a} reverts back to ∼0.2 eV. Since Al has a less number of valence electrons than do Hf, the change in the co-ordination number due to Al incorporation seems to contribute to the defect level modifications. Additionally, the stress induced leakage current behavior observed at 20 °C and at 125 °C demonstrates that the addition of Al in HfO{sub 2} contributed to suppressed trap generation process. This further supports the defect engineering model as reduced flat-band voltage shifts were observed at 20 °C and at 125 °C.« less

Single-step controlled-NOT logic from any exchange interaction

NASA Astrophysics Data System (ADS)

Galiautdinov, Andrei

2007-11-01

A self-contained approach to studying the unitary evolution of coupled qubits is introduced, capable of addressing a variety of physical systems described by exchange Hamiltonians containing Rabi terms. The method automatically determines both the Weyl chamber steering trajectory and the accompanying local rotations. Particular attention is paid to the case of anisotropic exchange with tracking controls, which is solved analytically. It is shown that, if computational subspace is well isolated, any exchange interaction can always generate high fidelity, single-step controlled-NOT (CNOT) logic, provided that both qubits can be individually manipulated. The results are then applied to superconducting qubit architectures, for which several CNOT gate implementations are identified. The paper concludes with consideration of two CNOT gate designs having high efficiency and operating with no significant leakage to higher-lying noncomputational states.

Characterization and reliability of aluminum gallium nitride/gallium nitride high electron mobility transistors

NASA Astrophysics Data System (ADS)

Douglas, Erica Ann

Compound semiconductor devices, particularly those based on GaN, have found significant use in military and civilian systems for both microwave and optoelectronic applications. Future uses in ultra-high power radar systems will require the use of GaN transistors operated at very high voltages, currents and temperatures. GaN-based high electron mobility transistors (HEMTs) have proven power handling capability that overshadows all other wide band gap semiconductor devices for high frequency and high-power applications. Little conclusive research has been reported in order to determine the dominating degradation mechanisms of the devices that result in failure under standard operating conditions in the field. Therefore, it is imperative that further reliability testing be carried out to determine the failure mechanisms present in GaN HEMTs in order to improve device performance, and thus further the ability for future technologies to be developed. In order to obtain a better understanding of the true reliability of AlGaN/GaN HEMTs and determine the MTTF under standard operating conditions, it is crucial to investigate the interaction effects between thermal and electrical degradation. This research spans device characterization, device reliability, and device simulation in order to obtain an all-encompassing picture of the device physics. Initially, finite element thermal simulations were performed to investigate the effect of device design on self-heating under high power operation. This was then followed by a study of reliability of HEMTs and other tests structures during high power dc operation. Test structures without Schottky contacts showed high stability as compared to HEMTs, indicating that degradation of the gate is the reason for permanent device degradation. High reverse bias of the gate has been shown to induce the inverse piezoelectric effect, resulting in a sharp increase in gate leakage current due to crack formation. The introduction of elevated temperatures during high reverse gate bias indicated that device failure is due to the breakdown of an unintentional gate oxide. RF stress of AlGaN/GaN HEMTs showed comparable critical voltage breakdown regime as that of similar devices stressed under dc conditions. Though RF device characteristics showed stability up to a drain bias of 20 V, Schottky diode characteristics degraded substantially at all voltages investigated. Results from both dc and RF stress conditions, under several bias regimes, confirm that the primary root for stress induced degradation was due to the Schottky contact. (Full text of this dissertation may be available via the University of Florida Libraries web site. Please check http://www.uflib.ufl.edu/etd.html)

Degradation of Leakage Currents in Solid Tantalum Capacitors Under Steady-State Bias Conditions

NASA Technical Reports Server (NTRS)

Teverovsky, Alexander A.

2010-01-01

Degradation of leakage currents in various types of solid tantalum capacitors under steady-state bias conditions was investigated at temperatures from 105 oC to 170 oC and voltages up to two times the rated voltage. Variations of leakage currents with time under highly accelerated life testing (HALT) and annealing, thermally stimulated depolarization currents, and I-V characteristics were measured to understand the conduction mechanism and the reason for current degradation. During HALT the currents increase gradually up to three orders of magnitude in some cases, and then stabilize with time. This degradation is reversible and annealing can restore the initial levels of leakage currents. The results are attributed to migration of positively charged oxygen vacancies in tantalum pentoxide films that diminish the Schottky barrier at the MnO2/Ta2O5 interface and increase electron injection. A simple model allows for estimation of concentration and mobility of oxygen vacancies based on the level of current degradation.

Leakage characterization of top select transistor for program disturbance optimization in 3D NAND flash

NASA Astrophysics Data System (ADS)

Zhang, Yu; Jin, Lei; Jiang, Dandan; Zou, Xingqi; Zhao, Zhiguo; Gao, Jing; Zeng, Ming; Zhou, Wenbin; Tang, Zhaoyun; Huo, Zongliang

2018-03-01

In order to optimize program disturbance characteristics effectively, a characterization approach that measures top select transistor (TSG) leakage from bit-line is proposed to quantify TSG leakage under program inhibit condition in 3D NAND flash memory. Based on this approach, the effect of Vth modulation of two-cell TSG on leakage is evaluated. By checking the dependence of leakage and corresponding program disturbance on upper and lower TSG Vth, this approach is validated. The optimal Vth pattern with high upper TSG Vth and low lower TSG Vth has been suggested for low leakage current and high boosted channel potential. It is found that upper TSG plays dominant role in preventing drain induced barrier lowering (DIBL) leakage from boosted channel to bit-line, while lower TSG assists to further suppress TSG leakage by providing smooth potential drop from dummy WL to edge of TSG, consequently suppressing trap assisted band-to-band tunneling current (BTBT) between dummy WL and TSG.

Techniques for computing discharge at four Navigation Dams on the Illinois and Des Plaines Rivers in Illinois

USGS Publications Warehouse

Mades, Dean M.; Weiss, Linda S.; Gray, John R.

1991-01-01

Techniques for computing discharge are developed for Brandon Road Dam on the Des Plaines River and for Dresden Island, Marseilles, and Starved Rock Dams on the Illinois River. At Brandon Road Dam, streamflow is regulated by the operation of Tainter gates and headgates. At Dresden Island, Marseilles, and Starved Rock Dams, only Tainter gates are operated to regulate streamflow. The locks at all dams are equipped with culvert valves that are used to fill and empty the lock. The techniques facilitate determination of discharge at locations along the upper Illinois Waterway where no streamflow-gaging stations exist. The techniques are also useful for computing low flows when the water-surface slope between control structures on the river approaches zero and traditional methods of determining discharge based on slope are unsatisfactory. Two techniques can be used to compute discharge at the dams--gate ratings and tailwater ratings . A gate ratingdescribes the relation between discharge, gate opening, tailwater stage, and headwater stage. A tailwater rating describes the relation between tailwater stage and discharge. Gate ratings for Tainter gates at Dresden Island, Marseilles, and Starved Rock Dams are based on a total of 78 measurements of discharge that range from 569 to 86,400 cubic feet per second. Flood hydrographs developed from the gate ratings and Lockmaster records of gate opening and stage compare closely with streamflow records published for nearby streamflow-gaging stations. Additional measurements are needed to verify gate ratings for Tainter gates and headgates at Brandon Road Dam after the dam rehabilitation is completed. Extensive leakage past deteriorated headgates and sluice gates contributed to uncertainty in the ratings developed for this dam. A useful tailwater rating is developed for Marseilles Dam. Tailwater ratings for Dresden Island Dam and Starved Rock Dam are of limited use because of varying downstream channel-storage conditions. A tailwater rating could not be developed for Brandon Road Dam because its tailwater pool is substantially affected by the headwater pool of Dresden Island Dam.

Design optimization of high frequency transformer with controlled leakage inductance for current fed dual active bridge converter

NASA Astrophysics Data System (ADS)

Jung, Tae-Uk; Kim, Myung-Hwan; Yoo, Jin-Hyung

2018-05-01

Current fed dual active bridge converters for photovoltaic generation may typically require a given leakage or extra inductance in order to provide proper control of the currents. Therefore, the many researches have been focused on the leakage inductance control of high frequency transformer to integrate an extra inductor. In this paper, an asymmetric winding arrangement to get the controlled leakage inductance for the high frequency transformer is proposed to improve the efficiency of the current fed dual active bridge converter. In order to accurate analysis, a coupled electromagnetic analysis model of transformer connected with high frequency switching circuit is used. A design optimization procedure for high efficiency is also presented using design analysis model, and it is verified by the experimental result.

Performance and Stability Enhancement of In-Sn-Zn-O TFTs Using SiO2 Gate Dielectrics Grown by Low Temperature Atomic Layer Deposition.

PubMed

Sheng, Jiazhen; Han, Ju-Hwan; Choi, Wan-Ho; Park, Jozeph; Park, Jin-Seong

2017-12-13

Silicon dioxide (SiO 2 ) films were synthesized by plasma-enhanced atomic layer deposition (PEALD) using BTBAS [bis(tertiarybutylamino) silane] as the precursor and O 2 plasma as the reactant, at a temperature range from 50 to 200 °C. While dielectric constant values larger than 3.7 are obtained at all deposition temperatures, the leakage current levels are drastically reduced to below 10 -12 A at temperatures above 150 °C, which are similar to those obtained in thermally oxidized and PECVD grown SiO 2 . Thin film transistors (TFTs) based on In-Sn-Zn-O (ITZO) semiconductors were fabricated using thermal SiO 2 , PECVD SiO 2 , and PEALD SiO 2 grown at 150 °C as the gate dielectrics, and superior device performance and stability are observed in the last case. A linear field effect mobility of 68.5 cm 2 /(V s) and a net threshold voltage shift (ΔV th ) of approximately 1.2 V under positive bias stress (PBS) are obtained using the PEALD SiO 2 as the gate insulator. The relatively high concentration of hydrogen in the PEALD SiO 2 is suggested to induce a high carrier density in the ITZO layer deposited onto it, which results in enhanced charge transport properties. Also, it is most likely that the hydrogen atoms have passivated the electron traps related to interstitial oxygen defects, thus resulting in improved stability under PBS. Although the PECVD SiO 2 contains a hydrogen concentration similar to that of PEALD SiO 2 , its relatively large surface roughness appears to induce scattering effects and the generation of electron traps, which result in inferior device performance and stability.

InP electroluminescence as a tool to directly monitor carrier leakage in InGaAsP/InP buried heterostructure lasers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Stern, M.B.; Brody, E.; Sowell, B.

1987-12-15

Direct measurements of homojunction and heterojunction carrier leakage currents in InGaAsP/InP buried heterostructure lasers have been made by monitoring the electroluminescence (EL) at 0.96 ..mu..m in the InP confinement layers. These EL measurements show directly, for the first time, a correlation between homojunction leakage currents and the sublinearity in the 1.3-..mu..m light output-current characteristic. The observed decrease in the 0.96-..mu..m intensity with increasing p-dopant concentration is a direct confirmation that heterojunction leakage is reduced when the doping level in the p-InP confinement layer is increased.

Dual-gate polysilicon nanoribbon biosensors enable high sensitivity detection of proteins.

PubMed

Zeimpekis, I; Sun, K; Hu, C; Ditshego, N M J; Thomas, O; de Planque, M R R; Chong, H M H; Morgan, H; Ashburn, P

2016-04-22

We demonstrate the advantages of dual-gate polysilicon nanoribbon biosensors with a comprehensive evaluation of different measurement schemes for pH and protein sensing. In particular, we compare the detection of voltage and current changes when top- and bottom-gate bias is applied. Measurements of pH show that a large voltage shift of 491 mV pH(-1) is obtained in the subthreshold region when the top-gate is kept at a fixed potential and the bottom-gate is varied (voltage sweep). This is an improvement of 16 times over the 30 mV pH(-1) measured using a top-gate sweep with the bottom-gate at a fixed potential. A similar large voltage shift of 175 mV is obtained when the protein avidin is sensed using a bottom-gate sweep. This is an improvement of 20 times compared with the 8.8 mV achieved from a top-gate sweep. Current measurements using bottom-gate sweeps do not deliver the same signal amplification as when using bottom-gate sweeps to measure voltage shifts. Thus, for detecting a small signal change on protein binding, it is advantageous to employ a double-gate transistor and to measure a voltage shift using a bottom-gate sweep. For top-gate sweeps, the use of a dual-gate transistor enables the current sensitivity to be enhanced by applying a negative bias to the bottom-gate to reduce the carrier concentration in the nanoribbon. For pH measurements, the current sensitivity increases from 65% to 149% and for avidin sensing it increases from 1.4% to 2.5%.

Dual-gate polysilicon nanoribbon biosensors enable high sensitivity detection of proteins

NASA Astrophysics Data System (ADS)

Zeimpekis, I.; Sun, K.; Hu, C.; Ditshego, N. M. J.; Thomas, O.; de Planque, M. R. R.; Chong, H. M. H.; Morgan, H.; Ashburn, P.

2016-04-01

We demonstrate the advantages of dual-gate polysilicon nanoribbon biosensors with a comprehensive evaluation of different measurement schemes for pH and protein sensing. In particular, we compare the detection of voltage and current changes when top- and bottom-gate bias is applied. Measurements of pH show that a large voltage shift of 491 mV pH-1 is obtained in the subthreshold region when the top-gate is kept at a fixed potential and the bottom-gate is varied (voltage sweep). This is an improvement of 16 times over the 30 mV pH-1 measured using a top-gate sweep with the bottom-gate at a fixed potential. A similar large voltage shift of 175 mV is obtained when the protein avidin is sensed using a bottom-gate sweep. This is an improvement of 20 times compared with the 8.8 mV achieved from a top-gate sweep. Current measurements using bottom-gate sweeps do not deliver the same signal amplification as when using bottom-gate sweeps to measure voltage shifts. Thus, for detecting a small signal change on protein binding, it is advantageous to employ a double-gate transistor and to measure a voltage shift using a bottom-gate sweep. For top-gate sweeps, the use of a dual-gate transistor enables the current sensitivity to be enhanced by applying a negative bias to the bottom-gate to reduce the carrier concentration in the nanoribbon. For pH measurements, the current sensitivity increases from 65% to 149% and for avidin sensing it increases from 1.4% to 2.5%.

Determination of the Steady State Leakage Current in Structures with Ferroelectric Ceramic Films

NASA Astrophysics Data System (ADS)

Podgornyi, Yu. V.; Vorotilov, K. A.; Sigov, A. S.

2018-03-01

Steady state leakage currents have been investigated in capacitor structures with ferroelectric solgel films of lead zirconate titanate (PZT) formed on silicon substrates with a lower Pt electrode. It is established that Pt/PZT/Hg structures, regardless of the PZT film thickness, are characterized by the presence of a rectifying contact similar to p-n junction. The steady state leakage current in the forward direction increases with a decrease in the film thickness and is determined by the ferroelectric bulk conductivity.

Design, development, fabrication and delivery of register and multiplexer units. [CMOS monolithic chip development

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardi, T.

1978-01-01

Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated. The CMOS standard cell array technique was selected and implemented. Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation. One of the chip types, multiplexer register type 1, is fabricated on a 0.143 x 0.123 inch chip. It uses nine standard cell types for a total of 54 standard cells. This involves more than 350 transistors and has the functional equivalent of 111 gates. The second chip, multiplexer register type 2, is housed on a 0.12 x 0.12 inch die. It uses 13 standard cell types, for a total of 42 standard cells. It contains more than 300 transistors, the functional equivalent of 112 gates. All of the hermetically sealed units were initially screened for proper functional operation. The static leakage and the dynamic leakage were measured. Dynamic measurements were made and recorded. At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1. At 5 V these units shifted data at a 6.6 MHz rate. The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C.

21 CFR 870.2640 - Portable leakage current alarm.

Code of Federal Regulations, 2014 CFR

2014-04-01

... (CONTINUED) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Monitoring Devices § 870.2640 Portable... the electrical leakage current between any two points of an electrical system and to sound an alarm if...

21 CFR 870.2640 - Portable leakage current alarm.

Code of Federal Regulations, 2013 CFR

2013-04-01

... (CONTINUED) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Monitoring Devices § 870.2640 Portable... the electrical leakage current between any two points of an electrical system and to sound an alarm if...

21 CFR 870.2640 - Portable leakage current alarm.

Code of Federal Regulations, 2012 CFR

2012-04-01

... (CONTINUED) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Monitoring Devices § 870.2640 Portable... the electrical leakage current between any two points of an electrical system and to sound an alarm if...

Microscopic origin of gating current fluctuations in a potassium channel voltage sensor.

PubMed

Freites, J Alfredo; Schow, Eric V; White, Stephen H; Tobias, Douglas J

2012-06-06

Voltage-dependent ion channels open and close in response to changes in membrane electrical potential due to the motion of their voltage-sensing domains (VSDs). VSD charge displacements within the membrane electric field are observed in electrophysiology experiments as gating currents preceding ionic conduction. The elementary charge motions that give rise to the gating current cannot be observed directly, but appear as discrete current pulses that generate fluctuations in gating current measurements. Here we report direct observation of gating-charge displacements in an atomistic molecular dynamics simulation of the isolated VSD from the KvAP channel in a hydrated lipid bilayer on the timescale (10-μs) expected for elementary gating charge transitions. The results reveal that gating-charge displacements are associated with the water-catalyzed rearrangement of salt bridges between the S4 arginines and a set of conserved acidic side chains on the S1-S3 transmembrane segments in the hydrated interior of the VSD. Copyright © 2012 Biophysical Society. Published by Elsevier Inc. All rights reserved.

Current-voltage characteristics influenced by the nanochannel diameter and surface charge density in a fluidic field-effect-transistor.

PubMed

Singh, Kunwar Pal; Guo, Chunlei

2017-06-21

The nanochannel diameter and surface charge density have a significant impact on current-voltage characteristics in a nanofluidic transistor. We have simulated the effect of the channel diameter and surface charge density on current-voltage characteristics of a fluidic nanochannel with positive surface charge on its walls and a gate electrode on its surface. Anion depletion/enrichment leads to a decrease/increase in ion current with gate potential. The ion current tends to increase linearly with gate potential for narrow channels at high surface charge densities and narrow channels are more effective to control the ion current at high surface charge densities. The current-voltage characteristics are highly nonlinear for wide channels at low surface charge densities and they show different regions of current change with gate potential. The ion current decreases with gate potential after attaining a peak value for wide channels at low values of surface charge densities. At low surface charge densities, the ion current can be controlled by a narrow range of gate potentials for wide channels. The current change with source drain voltage shows ohmic, limiting and overlimiting regions.

Reduction of surface leakage current by surface passivation of CdZn Te and other materials using hyperthermal oxygen atoms

DOEpatents

Hoffbauer, Mark A.; Prettyman, Thomas H.

2001-01-01

Reduction of surface leakage current by surface passivation of Cd.sub.1-x Zn.sub.x Te and other materials using hyperthermal oxygen atoms. Surface effects are important in the performance of CdZnTe room-temperature radiation detectors used as spectrometers since the dark current is often dominated by surface leakage. A process using high-kinetic-energy, neutral oxygen atoms (.about.3 eV) to treat the surface of CdZnTe detectors at or near ambient temperatures is described. Improvements in detector performance include significantly reduced leakage current which results in lower detector noise and greater energy resolution for radiation measurements of gamma- and X-rays, thereby increasing the accuracy and sensitivity of measurements of radionuclides having complex gamma-ray spectra, including special nuclear materials.

Simultaneous gates in frequency-crowded multilevel systems using fast, robust, analytic control shapes

NASA Astrophysics Data System (ADS)

Theis, L. S.; Motzoi, F.; Wilhelm, F. K.

2016-01-01

We present a few-parameter ansatz for pulses to implement a broad set of simultaneous single-qubit rotations in frequency-crowded multilevel systems. Specifically, we consider a system of two qutrits whose working and leakage transitions suffer from spectral crowding (detuned by δ ). In order to achieve precise controllability, we make use of two driving fields (each having two quadratures) at two different tones to simultaneously apply arbitrary combinations of rotations about axes in the X -Y plane to both qubits. Expanding the waveforms in terms of Hanning windows, we show how analytic pulses containing smooth and composite-pulse features can easily achieve gate errors less than 10-4 and considerably outperform known adiabatic techniques. Moreover, we find a generalization of the WAHWAH (Weak AnHarmonicity With Average Hamiltonian) method by Schutjens et al. [R. Schutjens, F. A. Dagga, D. J. Egger, and F. K. Wilhelm, Phys. Rev. A 88, 052330 (2013)], 10.1103/PhysRevA.88.052330 that allows precise separate single-qubit rotations for all gate times beyond a quantum speed limit. We find in all cases a quantum speed limit slightly below 2 π /δ for the gate time and show that our pulses are robust against variations in system parameters and filtering due to transfer functions, making them suitable for experimental implementations.

Leakage Currents and Gas Generation in Advanced Wet Tantalum Capacitors

NASA Technical Reports Server (NTRS)

Teverovsky, Alexander

2015-01-01

Currently, military grade, established reliability wet tantalum capacitors are among the most reliable parts used for space applications. This has been achieved over the years by extensive testing and improvements in design and materials. However, a rapid insertion of new types of advanced, high volumetric efficiency capacitors in space systems without proper testing and analysis of degradation mechanisms might increase risks of failures. The specifics of leakage currents in wet electrolytic capacitors is that the conduction process is associated with electrolysis of electrolyte and gas generation resulting in building up of internal gas pressure in the parts. The risk associated with excessive leakage currents and increased pressure is greater for high value advanced wet tantalum capacitors, but it has not been properly evaluated yet. In this work, in Part I, leakages currents in various types of tantalum capacitors have been analyzed in a wide range of voltages, temperatures, and time under bias. Gas generation and the level of internal pressure have been calculated in Part II for different case sizes and different hermeticity leak rates to assess maximal allowable leakage currents. Effects related to electrolyte penetration to the glass seal area have been studied and the possibility of failures analyzed in Part III. Recommendations for screening and qualification to reduce risks of failures have been suggested.

Development of a Crosstalk Suppression Algorithm for KID Readout

NASA Astrophysics Data System (ADS)

Lee, Kyungmin; Ishitsuka, H.; Oguri, S.; Suzuki, J.; Tajima, O.; Tomita, N.; Won, Eunil; Yoshida, M.

2018-06-01

The GroundBIRD telescope aims to detect B-mode polarization of the cosmic microwave background radiation using the kinetic inductance detector array as a polarimeter. For the readout of the signal from detector array, we have developed a frequency division multiplexing readout system based on a digital down converter method. These techniques in general have the leakage problems caused by the crosstalks. The window function was applied in the field programmable gate arrays to mitigate the effect of these problems and tested it in algorithm level.

High Performance Crystalline Organic Transistors and Circuit

DTIC Science & Technology

2011-08-02

pentacene -based OFETs, low voltage operation is possible. 3 Figure 1: Device structure for a low voltage pentacene OFET using a ZrO2 gate...first SiO Z OPentacene Au Pentacene ZrO2 AuPd SiO2 4 film. Bilayer dielectrics exhibit lower defect-related leakage effects, as pinholes or...other defects in one layer may be isolated by the other layer. 350 Å of pentacene was thermally evaporated on the ZrO2 dielectric at a rate of 0.1 Å

Gate-driven pure spin current in graphene

NASA Astrophysics Data System (ADS)

Lin, Xiaoyang; Su, Li; Zhang, Youguang; Bournel, Arnaud; Zhang, Yue; Klein, Jacques-Olivier; Zhao, Weisheng; Fert, Albert

An important challenge of spin current based devices is to realize long-distance transport and efficient manipulation of pure spin current without frequent spin-charge conversions. Here, the mechanism of gate-driven pure spin current in graphene is presented. Such a mechanism relies on the electrical gating of conductivity and spin diffusion length in graphene. The gate-driven feature is adopted to realize the pure spin current demultiplexing operation, which enables gate-controllable distribution of the pure spin current into graphene branches. Compared with Elliot-Yafet spin relaxation mechanism, D'yakonov-Perel spin relaxation mechanism results in more appreciable demultiplexing performance, which also implies a feasible strategy to characterize the spin relaxation mechanisms. The unique feature of the pure spin current demultiplexing operation would pave a way for ultra-low power spin logic beyond CMOS. Supported by the NSFC (61627813, 51602013) and the 111 project (B16001).

Radiation damage in MOS integrated circuits, Part 1

NASA Technical Reports Server (NTRS)

Danchenko, V.

1971-01-01

Complementary and p-channel MOS integrated circuits made by four commercial manufacturers were investigated for sensitivity to radiation environment. The circuits were irradiated with 1.5 MeV electrons. The results are given for electrons and for the Co-60 gamma radiation equivalent. The data are presented in terms of shifts in the threshold potentials and changes in transconductances and leakages. Gate biases of -10V, +10V and zero volts were applied to individual MOS units during irradiation. It was found that, in most of circuits of complementary MOS technologies, noticable changes due to radiation appear first as increased leakage in n-channel MOSFETs somewhat before a total integrated dose 10 to the 12th power electrons/sg cm is reached. The inability of p-channel MOSFETs to turn on sets in at about 10 to the 13th power electrons/sq cm. Of the circuits tested, an RCA A-series circuit was the most radiation resistant sample.

Inrush Current Suppression Circuit and Method for Controlling When a Load May Be Fully Energized

NASA Technical Reports Server (NTRS)

Schwerman, Paul (Inventor)

2017-01-01

A circuit and method for controlling when a load may be fully energized includes directing electrical current through a current limiting resistor that has a first terminal connected to a source terminal of a field effect transistor (FET), and a second terminal connected to a drain terminal of the FET. The gate voltage magnitude on a gate terminal of the FET is varied, whereby current flow through the FET is increased while current flow through the current limiting resistor is simultaneously decreased. A determination is made as to when the gate voltage magnitude on the gate terminal is equal to or exceeds a predetermined reference voltage magnitude, and the load is enabled to be fully energized when the gate voltage magnitude is equal to or exceeds the predetermined reference voltage magnitude.

Coherent molecular transistor: control through variation of the gate wave function.

PubMed

Ernzerhof, Matthias

2014-03-21

In quantum interference transistors (QUITs), the current through the device is controlled by variation of the gate component of the wave function that interferes with the wave function component joining the source and the sink. Initially, mesoscopic QUITs have been studied and more recently, QUITs at the molecular scale have been proposed and implemented. Typically, in these devices the gate lead is subjected to externally adjustable physical parameters that permit interference control through modifications of the gate wave function. Here, we present an alternative model of a molecular QUIT in which the gate wave function is directly considered as a variable and the transistor operation is discussed in terms of this variable. This implies that we specify the gate current as well as the phase of the gate wave function component and calculate the resulting current through the source-sink channel. Thus, we extend on prior works that focus on the phase of the gate wave function component as a control parameter while having zero or certain discrete values of the current. We address a large class of systems, including finite graphene flakes, and obtain analytic solutions for how the gate wave function controls the transistor.

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

PubMed

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J

2016-06-09

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

Distribution of leakage currents in the cylindrical and conical sections of the magnetically insulated transmission line of the Angara-5-1 facility in experiments with wire arrays

DOE Office of Scientific and Technical Information (OSTI.GOV)

Grabovski, E. V.; Gribov, A. N.; Samokhin, A. A.

2016-08-15

Current leakages in the magnetically insulated transmission lines (MITL) impose restrictions on the transmission of electromagnetic pulses to the load in high-power electrophysical facilities. The multimodule Angara-5-1 facility with an output electric power of up to 6 TW is considered. In this work, the experimental and calculated profiles of leakage currents in two sections of the line are compared when the eight-module facility is loaded by a wire array. The azimuthal distribution of the current in the cylindrical section of the MITL is also considered.

An analysis of the temperature dependence of the gate current in complementary heterojunction field-effect transistors

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.; Fossum, Eric R.; Baier, Steven M.

1992-01-01

The temperature dependence of the gate current versus the gate voltage in complementary heterojunction field-effect transistors (CHFET's) is examined. An analysis indicates that the gate conduction is due to a combination of thermionic emission, thermionic-field emission, and conduction through a temperature-activated resistance. The thermionic-field emission is consistent with tunneling through the AlGaAs insulator. The activation energy of the resistance is consistent with the ionization energy associated with the DX center in the AlGaAs. Methods reducing the gate current are discussed.

Indium arsenide-on-SOI MOSFETs with extreme lattice mismatch

NASA Astrophysics Data System (ADS)

Wu, Bin

Both molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD) have been used to explore the growth of InAs on Si. Despite 11.6% lattice mismatch, planar InAs structures have been observed by scanning electron microscopy (SEM) when nucleating using MBE on patterned submicron Si-on-insulator (SOI) islands. Planar structures of size as large as 500 x 500 nm 2 and lines of width 200 nm and length a few microns have been observed. MOCVD growth of InAs also generates single grain structures on Si islands when the size is reduced to 100 x 100 nm2. By choosing SOI as the growth template, selective growth is enabled by MOCVD. Post-growth pattern-then-anneal process, in which MOCVD InAs is deposited onto unpatterned SOI followed with patterning and annealing of InAs-on-Si structure, is found to change the relative lattice parameters of encapsulated 17/5 nm InAs/Si island. Observed from transmission electron diffraction (TED) patterns, the lattice mismatch of 17/5 nm InAs/Si island reduces from 11.2 to 4.2% after being annealed at 800°C for 30 minutes. High-k Al2O3 dielectrics have been deposited by both electron-beam-enabled physical vapor deposition (PVD) and atomic layer deposition (ALD). Films from both techniques show leakage currents on the order of 10-9A/cm2, at ˜1 MV/cm electric field, breakdown field > ˜6 MV/cm, and dielectric constant > 6, comparable to those of reported ALD prior arts by Groner. The first MOSFETs with extreme lattice mismatch InAs-on-SOI channels using PVD Al2O3 as the gate dielectric are characterized. Channel recess was used to improve the gate control of the drain current.

DLTS Analysis and Interface Engineering of Solution Route Fabricated Zirconia Based MIS Devices Using Plasma Treatment

NASA Astrophysics Data System (ADS)

Kumar, Arvind; Mondal, Sandip; Koteswara Rao, K. S. R.

2018-02-01

In this work, we have fabricated low-temperature sol-gel spin-coated and oxygen (O2) plasma treated ZrO2 thin film-based metal-insulator-semiconductor devices. To understand the impact of plasma treatment on the Si/ZrO2 interface, deep level transient spectroscopy measurements were performed. It is reported that the interface state density ( D it) comes down to 7.1 × 1010 eV-1 cm-2 from 4 × 1011 eV-1 cm-2, after plasma treatment. The reduction in D it is around five times and can be attributed to the passivation of oxygen vacancies near the Si/ZrO2 interface, as they try to relocate near the interface. The energy level position ( E T) of interfacial traps is estimated to be 0.36 eV below the conduction band edge. The untreated ZrO2 film displayed poor leakage behavior due to the presence of several traps within the film and at the interface; O2 plasma treated films show improved leakage current density as they have been reduced from 5.4 × 10-8 A/cm2 to 1.98 × 10-9 A/cm2 for gate injection mode and 6.4 × 10-8 A/cm2 to 6.3 × 10-10 A/cm2 for substrate injection mode at 1 V. Hence, we suggest that plasma treatment might be useful in future device fabrication technology.

Investigation of interface property in Al/SiO2/ n-SiC structure with thin gate oxide by illumination

NASA Astrophysics Data System (ADS)

Chang, P. K.; Hwu, J. G.

2017-04-01

The reverse tunneling current of Al/SiO2/ n-SiC structure employing thin gate oxide is introduced to examine the interface property by illumination. The gate current at negative bias decreases under blue LED illumination, yet increases under UV lamp illumination. Light-induced electrons captured by interface states may be emitted after the light sources are off, leading to the recovery of gate currents. Based on transient characteristics of gate current, the extracted trap level is close to the light energy for blue LED, indicating that electron capture induced by lighting may result in the reduction of gate current. Furthermore, bidirectional C- V measurements exhibit a positive voltage shift caused by electron trapping under blue LED illumination, while a negative voltage shift is observed under UV lamp illumination. Distinct trapping and detrapping behaviors can be observed from variations in I- V and C- V curves utilizing different light sources for 4H-SiC MOS capacitors with thin insulators.

Local epitaxial growth of ZrO2 on Ge (100) substrates by atomic layer epitaxy

NASA Astrophysics Data System (ADS)

Kim, Hyoungsub; Chui, Chi On; Saraswat, Krishna C.; McIntyre, Paul C.

2003-09-01

High-k dielectric deposition processes for gate dielectric preparation on Si surfaces usually result in the unavoidable and uncontrolled formation of a thin interfacial oxide layer. Atomic layer deposition of ˜55-Å ZrO2 film on a Ge (100) substrate using ZrCl4 and H2O at 300 °C was found to produce local epitaxial growth [(001) Ge//(001) ZrO2 and [100] Ge//[100] ZrO2] without a distinct interfacial layer, unlike the situation observed when ZrO2 is deposited using the same method on Si. Relatively large lattice mismatch (˜10%) between ZrO2 and Ge produced a high areal density of interfacial misfit dislocations. Large hysteresis (>200 mV) and high frequency dispersion were observed in capacitance-voltage measurements due to the high density of interface states. However, a low leakage current density, comparable to values obtained on Si substrates, was observed with the same capacitance density regardless of the high defect density.

Effect of annealing temperature on microstructural evolution and electrical properties of sol-gel processed ZrO2/Si films

NASA Astrophysics Data System (ADS)

Hwang, Soo Min; Lee, Seung Muk; Park, Kyung; Lee, Myung Soo; Joo, Jinho; Lim, Jun Hyung; Kim, Hyoungsub; Yoon, Jae Jin; Kim, Young Dong

2011-01-01

High-permittivity (k) ZrO2/Si(100) films were fabricated by a sol-gel technique and the microstructural evolution with the annealing temperature (Ta) was correlated with the variation of their electrical performance. With increasing Ta, the ZrO2 films crystallized into a tetragonal (t) phase which was maintained until 700 °C at nanoscale thicknesses. Although the formation of the t-ZrO2 phase obviously enhanced the k value of the ZrO2 dielectric layer, the maximum capacitance in accumulation was decreased by the growth of a low-k interfacial layer (IL) between ZrO2 and Si with increasing Ta. On the other hand, the gate leakage current was remarkably depressed with increasing Ta probably due to the combined effects of the increased IL thickness, optical band gap of ZrO2, and density of ZrO2 and decreased remnant organic components.

High Electron Mobility SiGe/Si Transistor Structures on Sapphire Substrates

NASA Technical Reports Server (NTRS)

Alterovitz, Samuel A.; Mueller, Carl H.; Croke, Edward T.; Ponchak, George E.

2004-01-01

SiGe/Si n-type modulation doped field effect structures and transistors (n-MODFETs) have been fabricated on r-plane sapphire substrates. The structures were deposited using molecular beam epitaxy, and antimony dopants were incorporated via a delta doping process. Secondary ion mass spectroscopy (SIMS) indicates that the peak antimony concentration was approximately 4 x 10(exp 19) per cubic centimeter. At these two temperatures, the electron carrier densities were 1.6 and 1.33 x 10(exp 12) per square centimeter, thus demonstrating that carrier confinement was excellent. Shubnikov-de Haas oscillations were observed at 0.25 K, thus confirming the two-dimensional nature of the carriers. Transistors, with gate lengths varying from 1 micron to 5 microns, were fabricated using these structures and dc characterization was performed at room temperature. The saturated drain current region extended over a wide source-to-drain voltage (V (sub DS)) range, with V (sub DS) knee voltages of approximately 0.5 V and increased leakage starting at voltages slightly higher than 4 V.

Photo-electronic current transport in back-gated graphene transistor

NASA Astrophysics Data System (ADS)

Srivastava, Ashok; Chen, Xinlu; Pradhan, Aswini K.

2017-04-01

In this work, we have studied photo-electronic current transport in a back-gated graphene field-effect transistor. Under the light illumination, band bending at the metal/graphene interface develops a built-in potential which generates photonic current at varying back-gate biases. A typical MOSFET type back-gated transistor structure uses a monolayer graphene as the channel layer formed over the silicon dioxide/silicon substrate. It is shown that the photo-electronic current consists of current contributions from photovoltaic, photo-thermoelectric and photo-bolometric effects. A maximum external responsivity close to 0.0009A/W is achieved at 30μW laser power source and 633nm wavelength.

Temperature-dependent leakage current behavior of epitaxial Bi0.5Na0.5TiO3-based thin films made by pulsed laser deposition

NASA Astrophysics Data System (ADS)

Hejazi, M. M.; Safari, A.

2011-11-01

This paper discusses the electrical conduction mechanisms in a 0.88 Bi0.5Na0.5TiO3-0.08 Bi0.5K0.5TiO3-0.04 BaTiO3 thin film in the temperature range of 200-350 K. The film was deposited on a SrRuO3/SrTiO3 substrate by pulsed laser deposition technique. At all measurement temperatures, the leakage current behavior of the film matched well with the Lampert's triangle bounded by three straight lines of different slopes. The relative location of the triangle sides varied with temperature due to its effect on the density of charge carriers and un-filled traps. At low electric fields, the ohmic conduction governed the leakage mechanism. The calculated activation energy of the trap is 0.19 eV implying the presence of shallow traps in the film. With increasing the applied field, an abrupt increase in the leakage current was observed. This was attributed to a trap-filling process by the injected carriers. At sufficiently high electric fields, the leakage current obeyed the Child's trap-free square law suggesting the space charge limited current was the dominant mechanism.

H-terminated diamond field effect transistor with ferroelectric gate insulator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Karaya, Ryota; Furuichi, Hiroki; Nakajima, Takashi

2016-06-13

An H-terminated diamond field-effect-transistor (FET) with a ferroelectric vinylidene fluoride (VDF)-trifluoroethylene (TrFE) copolymer gate insulator was fabricated. The VDF-TrFE film was deposited on the H-terminated diamond by the spin-coating method and low-temperature annealing was performed to suppress processing damage to the H-terminated diamond surface channel layer. The fabricated FET structure showed the typical properties of depletion-type p-channel FET and showed clear saturation of the drain current with a maximum value of 50 mA/mm. The drain current versus gate voltage curves of the proposed FET showed clockwise hysteresis loops due to the ferroelectricity of the VDF-TrFE gate insulator, and the memory windowmore » width was 19 V, when the gate voltage was swept from 20 to −20 V. The maximum on/off current ratio and the linear mobility were 10{sup 8} and 398 cm{sup 2}/V s, respectively. In addition, we modulated the drain current of the fabricated FET structure via the remnant polarization of the VDF-TrFE gate and obtained an on/off current ratio of 10{sup 3} without applying a DC gate voltage.« less

Gate-Driven Pure Spin Current in Graphene

NASA Astrophysics Data System (ADS)

Lin, Xiaoyang; Su, Li; Si, Zhizhong; Zhang, Youguang; Bournel, Arnaud; Zhang, Yue; Klein, Jacques-Olivier; Fert, Albert; Zhao, Weisheng

2017-09-01

The manipulation of spin current is a promising solution for low-power devices beyond CMOS. However, conventional methods, such as spin-transfer torque or spin-orbit torque for magnetic tunnel junctions, suffer from large power consumption due to frequent spin-charge conversions. An important challenge is, thus, to realize long-distance transport of pure spin current, together with efficient manipulation. Here, the mechanism of gate-driven pure spin current in graphene is presented. Such a mechanism relies on the electrical gating of carrier-density-dependent conductivity and spin-diffusion length in graphene. The gate-driven feature is adopted to realize the pure spin-current demultiplexing operation, which enables gate-controllable distribution of the pure spin current into graphene branches. Compared with the Elliott-Yafet spin-relaxation mechanism, the D'yakonov-Perel spin-relaxation mechanism results in more appreciable demultiplexing performance. The feature of the pure spin-current demultiplexing operation will allow a number of logic functions to be cascaded without spin-charge conversions and open a route for future ultra-low-power devices.

Analysis and modeling of leakage current sensor under pulsating direct current

NASA Astrophysics Data System (ADS)

Li, Kui; Dai, Yihua; Wang, Yao; Niu, Feng; Chen, Zhao; Huang, Shaopo

2017-05-01

In this paper, the transformation characteristics of current sensor under pulsating DC leakage current is investigated. The mathematical model of current sensor is proposed to accurately describe the secondary side current and excitation current. The transformation process of current sensor is illustrated in details and the transformation error is analyzed from multi aspects. A simulation model is built and a sensor prototype is designed to conduct comparative evaluation, and both simulation and experimental results are presented to verify the correctness of theoretical analysis.

Apparatus for detecting leakage of liquid sodium

DOEpatents

Himeno, Yoshiaki

1978-01-01

An apparatus for detecting the leakage of liquid sodium includes a cable-like sensor adapted to be secured to a wall of piping or other equipment having sodium on the opposite side of the wall, and the sensor includes a core wire electrically connected to the wall through a leak current detector and a power source. An accidental leakage of the liquid sodium causes the corrosion of a metallic layer and an insulative layer of the sensor by products resulted from a reaction of sodium with water or oxygen in the atmospheric air so as to decrease the resistance between the core wire and the wall. Thus, the leakage is detected as an increase in the leaking electrical current. The apparatus is especially adapted for use in detecting the leakage of liquid sodium from sodium-conveying pipes or equipment in a fast breeder reactor.

Hafnium oxide films for application as gate dielectrics

NASA Astrophysics Data System (ADS)

Hsu, Shuo-Lin

The deposition and characterization of HfO2 films for potential application as a high-kappa gate dielectric in MOS devices has been investigated. DC magnetron reactive sputtering was utilized to prepare the HfO2 films. Structural, chemical, and electrical analyses were performed to characterize the various physical, chemical and electrical properties of the sputtered HfO2 films. The sputtered HfO2 films were annealed to simulate the dopant activation process used in semiconductor processing, and to study the thermal stability of the high-kappa, films. The changes in the film properties due to the annealing are also discussed in this work. Glancing angle XRD was used to analyse the atomic scale structure of the films. The as deposited films exhibit an amorphous, regardless of the film thickness. During post-deposition annealing, the thicker films crystallized at lower temperature (< 600°C), and ultra-thin (5.8 nm) film crystallized at higher temperature (600--720°C). The crystalline phase which formed depended on the thickness of the films. The low temperature phase (monoclinic) formed in the 10--20 nm annealed films, and high temperature phase (tetragonal) formed in the ultra-thin annealed HfO2 film. TEM cross-section studies of as deposited samples show that an interfacial layer (< 1nm) exists between HfO2/Si for all film thicknesses. The interfacial layer grows thicker during heat treatment, and grows more rapidly when grain boundaries are present. XPS surface analysis shows the as deposited films are fully oxidized with an excess of oxygen. Interfacial chemistry analysis indicated that the interfacial layer is a silicon-rich silicate layer, which tends to transform to silica-like layer during heat treatment. I-V measurements show the leakage current density of the Al/as deposited-HfO 2/Si MOS diode is of the order of 10-3 A/cm 2, two orders of magnitude lower than that of a ZrO2 film with similar physical thickness. Carrier transport is dominated by Schottky emission at lower electric fields, and by Frenkel-Poole emission in the higher electric field region. After annealing, the leakage current density decreases significantly as the structure remains amorphous structure. It is suggested that this decrease is assorted with the densification and defect healing which accures when the porous as-deposited amorphous structure is annealed. The leakage current density increases of the HfO2 layer crystallizes on annealing, which is attributed to the presence of grain boundaries. C-V measurements of the as deposited film shows typical C-V characteristics, with negligible hystersis, a small flat band voltage shift, but great frequency dispersion. The relative permittivity of HfO2/interfacial layer stack obtained from the capacitance at accumulation is 15, which corresponds to an EOT (equivalent oxide thickness) = 1.66 nm. After annealing, the frequency dispersion is greatly enhanced, and the C-V curve is shifted toward the negative voltage. Reliability tests show that the HfO2 films which remain amorphous after annealing possess superior resistance to constant voltage stress and ambient aging. This study concluded that the sputtered HfO 2 films exhibit an amorphous as deposited. Postdeposition annealing alters the crystallinity, interfacial properties, and electrical characteristics. The HfO2 films which remain amorphous structure after annealing possess the best electrical properties.

Analysis of Co-Tunneling Current in Fullerene Single-Electron Transistor

NASA Astrophysics Data System (ADS)

KhademHosseini, Vahideh; Dideban, Daryoosh; Ahmadi, MohammadTaghi; Ismail, Razali

2018-05-01

Single-electron transistors (SETs) are nano devices which can be used in low-power electronic systems. They operate based on coulomb blockade effect. This phenomenon controls single-electron tunneling and it switches the current in SET. On the other hand, co-tunneling process increases leakage current, so it reduces main current and reliability of SET. Due to co-tunneling phenomenon, main characteristics of fullerene SET with multiple islands are modelled in this research. Its performance is compared with silicon SET and consequently, research result reports that fullerene SET has lower leakage current and higher reliability than silicon counterpart. Based on the presented model, lower co-tunneling current is achieved by selection of fullerene as SET island material which leads to smaller value of the leakage current. Moreover, island length and the number of islands can affect on co-tunneling and then they tune the current flow in SET.

Gating currents from Kv7 channels carrying neuronal hyperexcitability mutations in the voltage-sensing domain.

PubMed

Miceli, Francesco; Vargas, Ernesto; Bezanilla, Francisco; Taglialatela, Maurizio

2012-03-21

Changes in voltage-dependent gating represent a common pathogenetic mechanism for genetically inherited channelopathies, such as benign familial neonatal seizures or peripheral nerve hyperexcitability caused by mutations in neuronal K(v)7.2 channels. Mutation-induced changes in channel voltage dependence are most often inferred from macroscopic current measurements, a technique unable to provide a detailed assessment of the structural rearrangements underlying channel gating behavior; by contrast, gating currents directly measure voltage-sensor displacement during voltage-dependent gating. In this work, we describe macroscopic and gating current measurements, together with molecular modeling and molecular-dynamics simulations, from channels carrying mutations responsible for benign familial neonatal seizures and/or peripheral nerve hyperexcitability; K(v)7.4 channels, highly related to K(v)7.2 channels both functionally and structurally, were used for these experiments. The data obtained showed that mutations affecting charged residues located in the more distal portion of S(4) decrease the stability of the open state and the active voltage-sensing domain configuration but do not directly participate in voltage sensing, whereas mutations affecting a residue (R4) located more proximally in S(4) caused activation of gating-pore currents at depolarized potentials. These results reveal that distinct molecular mechanisms underlie the altered gating behavior of channels carrying disease-causing mutations at different voltage-sensing domain locations, thereby expanding our current view of the pathogenesis of neuronal hyperexcitability diseases. Copyright © 2012 Biophysical Society. Published by Elsevier Inc. All rights reserved.

Complex oxide thin films for microelectronics

NASA Astrophysics Data System (ADS)

Suvorova, Natalya

The rapid scaling of the device dimensions, namely in metal oxide semiconductor field effect transistor (MOSFET), is reaching its fundamental limit which includes the increase in allowable leakage current due to direct tunneling with decrease of physical thickness of SiO2 gate dielectric. The significantly higher relative dielectric constant (in the range 9--25) of the gate dielectric beyond the 3.9 value of silicon dioxide will allow increasing the physical thickness. Among the choices for the high dielectric constant (K) materials for future generation MOSFET application, barium strontium titanate (BST) and strontium titanate (STO) possess one of the highest attainable K values making them the promising candidates for alternative gate oxide. However, the gate stack engineering does not imply the simple replacement of the SiO2 with the new dielectric. Several requirements should be met for successful integration of a new material. The major one is a production of high level of interface states (Dit) compared to that of SiO 2 on Si. An insertion of a thin SiO2 layer prior the growth of high-K thin film is a simple solution that helps to limit reaction with Si substrate and attains a high quality interface. However, the combination of two thin films reduces the overall K of the dielectric stack. An optimization of the SiO2 underlayer in order to maintain the interface quality yet minimize the effect on K is the focus of this work. The results from our study are presented with emphasis on the key process parameters that improve the dielectric film stack. For in-situ growth characterization of BST and STO films sputter deposited on thermally oxidized Si substrates spectroscopic ellipsometry in combination with time of flight ion scattering and recoil spectrometry have been employed. Studies of material properties have been complemented with analytical electron microscopy. To evaluate the interface quality the electrical characterization has been employed using capacitance-voltage and conductance-voltage measurements. Special attention was given to the extraction of static dielectric constant of BST and STO from the multiple film stack. The K value was found to be sensitive to the input parameters such as dielectric constant and thickness of interface layers.

Comparison of the Standard of Air Leakage in Current Metal Duct Systems in the World

NASA Astrophysics Data System (ADS)

Di, Yuhui; Wang, Jiqian; Feng, Lu; Li, Xingwu; Hu, Chunlin; Shi, Junshe; Xu, Qingsong; Qiao, Leilei

2018-01-01

Based on the requirements of air leakage of metal ducts in Chinese design standards, technical measures and construction standards, this paper compares the development history, the classification of air pressure levels and the air tightness levels of air leakage standards of current Chinese and international metal ducts, sums up the differences, finds shortage by investigating the design and construction status and access to information, and makes recommendations, hoping to help the majority of engineering and technical personnel.

Analysis techniques of charging damage studied on three different high-current ion implanters

NASA Astrophysics Data System (ADS)

Felch, S. B.; Larson, L. A.; Current, M. I.; Lindsey, D. W.

1989-02-01

One of the Greater Silicon Valley Implant Users' Group's recent activities has been to sponsor a round-robin on charging damage, where identical wafers were implanted on three different state-of-the-art, high-current ion implanters. The devices studied were thin-dielectric (250 Å SiO2), polysilicon-gate MOS capacitors isolated by thick field oxide. The three implanters involved were the Varian/Extrion 160XP, the Eaton/Nova 10-80, and the Applied Materials PI9000. Each implanter vendor was given 48 wafers to implant with 100 keV As+ ions at a dose of 1 × 1016 cm-2. Parameters that were varied include the beam current, electron flood gun current, and chamber pressure. The charge-to-breakdown, breakdown voltage, and leakage current of several devices before anneal have been measured. The results from these tests were inconclusive as to the physical mechanism of charging and as to the effectiveness of techniques to reduce its impact on devices. However, the methodology of this study is discussed in detail to aid in the planning of future experiments. Authors' industrial affiliations: S.B. Felch, Varian Research Center, 611 Hansen Way, Palo Alto, CA 94303, USA; L.A. Larson, National Semiconductor Corp., P.O. Box 58090, Santa Clara, CA 95052-8090, USA; M.I. Current, Applied Materials, 3050 Bowers Ave., Santa Clara, CA 95054, USA; D.W. Lindsey, Eaton/NOVA, 931 Benicia Ave, Sunnyvale, CA 94086, USA.

Charge trapping and current-conduction mechanisms of metal-oxide-semiconductor capacitors with La xTa y dual-doped HfON dielectrics

NASA Astrophysics Data System (ADS)

Cheng, Chin-Lung; Horng, Jeng-Haur; Chang-Liao, Kuei-Shu; Jeng, Jin-Tsong; Tsai, Hung-Yang

2010-10-01

Charge trapping and related current-conduction mechanisms in metal-oxide-semiconductor (MOS) capacitors with La xTa y dual-doped HfON dielectrics have been investigated under various post-deposition annealing (PDA). The results indicate that by La xTa y incorporation into HfON dielectric enhances electrical and reliability characteristics, including equivalent-oxide-thickness (EOT), stress-induced leakage current (SILC), and trap energy level. The mechanisms related to larger positive charge generation in the gate dielectric bulk can be attributed to La xTa y dual-doped HfON dielectric. The results of C- V measurement indicate that more negative charges are induced with increasing PDA temperature for the La xTa y dual-doped HfON dielectric. The charge current transport mechanisms through various dielectrics have been analyzed with current-voltage ( I- V) measurements under various temperatures. The current-conduction mechanisms of HfLaTaON dielectric at the low-, medium-, and high-electrical fields were dominated by Schottky emission (SE), Frenkel-Poole emission (F-P), and Fowler-Nordheim (F-N), respectively. A low trap energy level ( Φ trap) involved in Frenkel-Pool conduction in an HfLaTaON dielectric was estimated to be around 0.142 eV. Although a larger amount of positive charges generated in the HfLaTaON dielectric was obtained, the Φ trap of these positive charges in the HfLaTaON dielectric are shallow compared with HfON dielectric.

Spider toxin inhibits gating pore currents underlying periodic paralysis.

PubMed

Männikkö, Roope; Shenkarev, Zakhar O; Thor, Michael G; Berkut, Antonina A; Myshkin, Mikhail Yu; Paramonov, Alexander S; Kulbatskii, Dmitrii S; Kuzmin, Dmitry A; Sampedro Castañeda, Marisol; King, Louise; Wilson, Emma R; Lyukmanova, Ekaterina N; Kirpichnikov, Mikhail P; Schorge, Stephanie; Bosmans, Frank; Hanna, Michael G; Kullmann, Dimitri M; Vassilevski, Alexander A

2018-04-24

Gating pore currents through the voltage-sensing domains (VSDs) of the skeletal muscle voltage-gated sodium channel Na V 1.4 underlie hypokalemic periodic paralysis (HypoPP) type 2. Gating modifier toxins target ion channels by modifying the function of the VSDs. We tested the hypothesis that these toxins could function as blockers of the pathogenic gating pore currents. We report that a crab spider toxin Hm-3 from Heriaeus melloteei can inhibit gating pore currents due to mutations affecting the second arginine residue in the S4 helix of VSD-I that we have found in patients with HypoPP and describe here. NMR studies show that Hm-3 partitions into micelles through a hydrophobic cluster formed by aromatic residues and reveal complex formation with VSD-I through electrostatic and hydrophobic interactions with the S3b helix and the S3-S4 extracellular loop. Our data identify VSD-I as a specific binding site for neurotoxins on sodium channels. Gating modifier toxins may constitute useful hits for the treatment of HypoPP. Copyright © 2018 the Author(s). Published by PNAS.

Performance comparison of single and dual metal dielectrically modulated TFETs for the application of label free biosensor

NASA Astrophysics Data System (ADS)

Verma, Madhulika; Sharma, Dheeraj; Pandey, Sunil; Nigam, Kaushal; Kondekar, P. N.

2017-01-01

In this work, we perform a comparative analysis between single and dual metal dielectrically modulated tunnel field-effect transistors (DMTFETs) for the application of label free biosensor. For this purpose, two different gate material with work-function as ϕM 1 and ϕM 2 are used in short-gate DMTFET, where ϕM 1 represents the work-function of gate M1 near to the drain end, while ϕM 2 denotes the work-function of gate M2 near to the source end. A nanogap cavity in the gate dielectric is formed by removing the selected portion of gate oxide for sensing the biomolecules. To investigate the sensitivity of these biosensors, dielectric constant and charge density within the cavity region are considered as governing parameters. The work-function of gate M2 is optimized and considered less than M1 to achieve abruptness at the source/channel junction, which results in better tunneling and improved ON-state current. The ATLAS device simulations show that dual metal SG-DMTFETs attains higher ON-state current and drain current sensitivity as compared to its counterpart device. Finally, a dual metal short-gate (DSG) biosensor is compared with the single metal short-gate (SG), single metal full-gate (FG), and dual metal full-gate (DFG) biosensors to analyse structurally enhanced conjugation effect on gate-channel coupling.

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

NASA Astrophysics Data System (ADS)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-low-power applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.

TEM studies of III-V MOSFETs for ultimate CMOS

NASA Astrophysics Data System (ADS)

Longo, Paolo

Over the past half-century electronic industry has enormously grown changing the way people live their lives. Such growth has been driven by the miniaturisation and development of the transistors which are the main components in an integrated circuit (IC) commonly referred as a chip. Until today electronic industry has been based on the use of Si and its native oxide SiO2 in transistors. However, the performance limit of conventional Si based transistors is rapidly being approached and alternatives will soon be required. One of the proposed alternatives is GaAs. n-type GaAs has a mobility 5 times higher than Si. This makes it a suitable candidate for MOSFETs devices. So far, GaAs has not been used for practical MOSFETs because of the difficulties of making a good dielectric oxide layer in terms of leakage current and unpinned Fermi Level. Using processes pioneered by Passlack et al, dielectric gate stacks consisting of a template layer of amorphous Ga2O3 followed by amorphous GdGaO have been grown on GaAs substrates. Careful deposition of Ga2O3 can leave the Fermi Level unpinned. The introduction of Gd is important in order to decrease the leakage of current. The electrical properties of the Ga2O3/Gd[x]Ga[0.4-x]O[0.6] dielectric stack are related to the Gd concentration and the quality of the GaAs/Ga2O3 interface. Over the past years in a unique partnership several research groups from the Physics and the Electronic and Electrical engineering Department have collaboratively worked for the realisation and development of such new generation of GaAs based transistors using the technology described above. The properties of such devices depend on structures at the nanoscale which is only few atoms across. Thus the characterization using the transmission electron microscope (TEM) becomes essential. In this project TEM has been used to study several MBE grown III-V semiconductor nanostructures. In particular most of the thesis is focussed on the chemical characterisation of the GaAs/Ga2O3/GGO dielectric gate stack, mainly using electron energy loss spectroscopy (EELS) and high-resolution scanning Transmission electron microscopy (STEM) imaging. As said above the quality of such interfaces affects the properties of the whole device. Hence the results presented herein represent an important feedback for the realisation of world performance GaAs devices.

Hydrophobicity and leakage current statistics of polymeric insulators long-term exposed to coastal contamination

DOE Office of Scientific and Technical Information (OSTI.GOV)

Soerqvist, T.; Vlastos, A.E.

1996-12-31

The hydrophobicity of polymeric insulators is crucial for their performance. This paper reports the hydrophobicity and the peak leakage current statistics of one porcelain, two ethylene-propylene-diene monomer (EPDM) and four silicone rubber (SIR) commercially available insulators. The insulators have been energized with 130 kV rms phase-to-ground AC voltage under identical outdoor conditions for more than seven years. The results presented show that under wet and polluted conditions the hydrophilic EPDM rubber insulators develop high leakage currents and substantial arcing. During a typical salt-storm the arcing amplitude of the EPDM rubber insulators is at least twice as high as that ofmore » the porcelain insulator. The SIR insulators, on the other hand, preserve a high degree of hydrophobicity after more than seven years in service and maintain very low leakage currents. However, the results show that during heavy salt contaminated conditions a highly stressed SIR insulator can temporarily lose its hydrophobicity and thereby develop considerable surface arcing.« less

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

PubMed

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Effect of Compressive Stresses on Leakage Currents in Microchip Tantalum Capacitors

NASA Technical Reports Server (NTRS)

Teverovsky, Alexander

2012-01-01

Microchip tantalum capacitors are manufactured using new technologies that allow for production of small size capacitors (down to EIA case size 0402) with volumetric efficiency much greater than for regular chip capacitors. Due to a small size of the parts and leadless design they might be more sensitive to mechanical stresses that develop after soldering onto printed wiring boards (PWB) compared to standard chip capacitors. In this work, the effect of compressive stresses on leakage currents in capacitors has been investigated in the range of stresses up to 200 MPa. Significant, up to three orders of magnitude, variations of currents were observed after the stress exceeds a certain critical level that varied from 10 MPa to 180 MPa for capacitors used in this study. A stress-induced generation of electron traps in tantalum pentoxide dielectric is suggested to explain reversible variations of leakage currents in tantalum capacitors. Thermo-mechanical characteristics of microchip capacitors have been studied to estimate the level of stresses caused by assembly onto PWB and assess the risk of stress-related degradation and failures. Keywords: tantalum capacitors, leakage current, soldering, reliability, mechanical stress.

21 CFR 870.2640 - Portable leakage current alarm.

Code of Federal Regulations, 2011 CFR

2011-04-01

... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Portable leakage current alarm. 870.2640 Section 870.2640 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Monitoring Devices § 870.2640 Portable...

21 CFR 870.2640 - Portable leakage current alarm.

Code of Federal Regulations, 2010 CFR

2010-04-01

... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Portable leakage current alarm. 870.2640 Section 870.2640 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Monitoring Devices § 870.2640 Portable...

Al{sub 2}O{sub 3}/GeO{sub x} gate stack on germanium substrate fabricated by in situ cycling ozone oxidation method

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Xu; Zeng, Zhen-Hua; Microwave Device and IC Department, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029

2014-09-01

Al{sub 2}O{sub 3}/GeO{sub x}/Ge gate stack fabricated by an in situ cycling ozone oxidation (COO) method in the atomic layer deposition (ALD) system at low temperature is systematically investigated. Excellent electrical characteristics such as minimum interface trap density as low as 1.9 × 10{sup 11 }cm{sup −2 }eV{sup −1} have been obtained by COO treatment. The impact of COO treatment against the band alignment of Al{sub 2}O{sub 3} with respect to Ge is studied by x-ray photoelectron spectroscopy (XPS) and spectroscopic ellipsometry (SE). Based on both XPS and SE studies, the origin of gate leakage in the ALD-Al{sub 2}O{sub 3} is attributed to themore » sub-gap states, which may be correlated to the OH-related groups in Al{sub 2}O{sub 3} network. It is demonstrated that the COO method is effective in repairing the OH-related defects in high-k dielectrics as well as forming superior high-k/Ge interface for high performance Ge MOS devices.« less

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer

PubMed Central

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J.

2016-01-01

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack. PMID:27279454

Printed Circuit Board Surface Finish and Effects of Chloride Contamination, Electric Field, and Humidity on Corrosion Reliability

NASA Astrophysics Data System (ADS)

Conseil-Gudla, Hélène; Jellesen, Morten S.; Ambat, Rajan

2017-02-01

Corrosion reliability is a serious issue today for electronic devices, components, and printed circuit boards (PCBs) due to factors such as miniaturization, globalized manufacturing practices which can lead to process-related residues, and global usage effects such as bias voltage and unpredictable user environments. The investigation reported in this paper focuses on understanding the synergistic effect of such parameters, namely contamination, humidity, PCB surface finish, pitch distance, and potential bias on leakage current under different humidity levels, and electrochemical migration probability under condensing conditions. Leakage currents were measured on interdigitated comb test patterns with three different types of surface finish typically used in the electronics industry, namely gold, copper, and tin. Susceptibility to electrochemical migration was studied under droplet conditions. The level of base leakage current (BLC) was similar for the different surface finishes and NaCl contamination levels up to relative humidity (RH) of 65%. A significant increase in leakage current was found for comb patterns contaminated with NaCl above 70% to 75% RH, close to the deliquescent RH of NaCl. Droplet tests on Cu comb patterns with varying pitch size showed that the initial BLC before dendrite formation increased with increasing NaCl contamination level, whereas electrochemical migration and the frequency of dendrite formation increased with bias voltage. The effect of different surface finishes on leakage current under humid conditions was not very prominent.

The Random Telegraph Signal Behavior of Intermittently Stuck Bits in SDRAMs

NASA Astrophysics Data System (ADS)

Chugg, Andrew Michael; Burnell, Andrew J.; Duncan, Peter H.; Parker, Sarah; Ward, Jonathan J.

2009-12-01

This paper reports behavior analogous to the Random Telegraph Signal (RTS) seen in the leakage currents from radiation induced hot pixels in Charge Coupled Devices (CCDs), but in the context of stuck bits in Synchronous Dynamic Random Access Memories (SDRAMs). Our analysis suggests that pseudo-random sticking and unsticking of the SDRAM bits is due to thermally induced fluctuations in leakage current through displacement damage complexes in depletion regions that were created by high-energy neutron and proton interactions. It is shown that the number of observed stuck bits increases exponentially with temperature, due to the general increase in the leakage currents through the damage centers with temperature. Nevertheless, some stuck bits are seen to pseudo-randomly stick and unstick in the context of a continuously rising trend of temperature, thus demonstrating that their damage centers can exist in multiple widely spaced, discrete levels of leakage current, which is highly consistent with RTS. This implies that these intermittently stuck bits (ISBs) are a displacement damage phenomenon and are unrelated to microdose issues, which is confirmed by the observation that they also occur in unbiased irradiation. Finally, we note that observed variations in the periodicity of the sticking and unsticking behavior on several timescales is most readily explained by multiple leakage current pathways through displacement damage complexes spontaneously and independently opening and closing under the influence of thermal vibrations.

Universality of Non-Ohmic Shunt Leakage in Thin-Film Solar Cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dongaonkar, S.; Servaites, J.D.; Ford, G.M.

2010-01-01

We compare the dark current-voltage (IV) characteristics of three different thin-film solar cell types: hydrogenated amorphous silicon (a-Si:H) p-i-n cells, organic bulk heterojunction (BHJ) cells, and Cu(In,Ga)Se 2 (CIGS) cells. All three device types exhibit a significant shunt leakage current at low forward bias (V<~0.4) and reverse bias, which cannot be explained by the classical solar cell diode model. This parasitic shunt current exhibits non-Ohmic behavior, as opposed to the traditional constant shunt resistance model for photovoltaics. We show here that this shunt leakage (I sh) , across all three solar cell types considered, is characterized by the following commonmore » phenomenological features: (a) voltage symmetry about V=0 , (b) nonlinear (power law) voltage dependence, and (c) extremely weak temperature dependence. Based on this analysis, we provide a simple method of subtracting this shunt current component from the measured data and discuss its implications on dark IV parameter extraction. We propose a space charge limited (SCL) current model for capturing all these features of the shunt leakage in a consistent framework and discuss possible physical origin of the parasitic paths responsible for this shunt current mechanism.« less

Trapped-ion quantum logic gates based on oscillating magnetic fields.

PubMed

Ospelkaus, C; Langer, C E; Amini, J M; Brown, K R; Leibfried, D; Wineland, D J

2008-08-29

Oscillating magnetic fields and field gradients can be used to implement single-qubit rotations and entangling multiqubit quantum gates for trapped-ion quantum information processing (QIP). With fields generated by currents in microfabricated surface-electrode traps, it should be possible to achieve gate speeds that are comparable to those of optically induced gates for realistic distances between the ion crystal and the electrode surface. Magnetic-field-mediated gates have the potential to significantly reduce the overhead in laser-beam control and motional-state initialization compared to current QIP experiments with trapped ions and will eliminate spontaneous scattering, a fundamental source of decoherence in laser-mediated gates.

Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement

NASA Astrophysics Data System (ADS)

Raad, Bhagwan Ram; Nigam, Kaushal; Sharma, Dheeraj; Kondekar, P. N.

2016-06-01

This script features a study of bandgap, gate material work function and gate dielectric engineering for enhancement of DC and Analog/RF performance, reduction in the hot carriers effect (HCEs) and drain induced barrier lowering (DIBL) for better device reliability. In this concern, the use of band gap and gate material work function engineering improves the device performance in terms of the ON-state current and suppressed ambipolar behaviour with maintaining the low OFF-state current. With these advantages, the use of gate material work function engineering imposes restriction on the high frequency performance due to increment in the parasitic capacitances and also introduces the hot carrier effects. Hence, the gate dielectric engineering with bandgap and gate material work function engineering are used in this paper to overcome the cons of the gate material work function engineering by obtaining a superior performance in terms of the current driving capability, ambipolar conduction, HCEs, DIBL and high frequency parameters of the device for ultra-low power applications. Finally, the optimization of length for different work function is performed to get the best out of this.

Module Hipot and ground continuity test results

NASA Technical Reports Server (NTRS)

Griffith, J. S.

1984-01-01

Hipot (high voltage potential) and module frame continuity tests of solar energy conversion modules intended for deployment into large arrays are discussed. The purpose of the tests is to reveal potentially hazardous voltage conditions in installed modules, and leakage currents that may result in loss of power or cause ground fault system problems, i.e., current leakage potential and leakage voltage distribution. The tests show a combined failure rate of 36% (69% when environmental testing is included). These failure rates are believed easily corrected by greater care in fabrication.

AlGaN/GaN-on-Si monolithic power-switching device with integrated gate current booster

NASA Astrophysics Data System (ADS)

Han, Sang-Woo; Jo, Min-Gi; Kim, Hyungtak; Cho, Chun-Hyung; Cha, Ho-Young

2017-08-01

This study investigates the effects of a monolithic gate current booster integrated with an AlGaN/GaN-on-Si power-switching device. The integrated gate current booster was implemented by a single-stage inverter topology consisting of a recessed normally-off AlGaN/GaN MOS-HFET and a mesa resistor. The monolithically integrated gate current booster in a switching FET eliminated the parasitic elements caused by external interconnection and enabled fast switching operation. The gate charging and discharging currents were boosted by the integrated inverter, which significantly reduced both rise and fall times: the rise time was reduced from 626 to 41.26 ns, while the fall time was reduced from 554 to 42.19 ns by the single-stage inverter. When the packaged monolithic power chip was tested under 1 MHz hard-switching operation with VDD = 200 V, the switching loss was found to have been drastically reduced, from 5.27 to 0.55 W.

Effects of negative gate-bias stress on the performance of solution-processed zinc-oxide transistors

NASA Astrophysics Data System (ADS)

Kim, Dongwook; Lee, Woo-Sub; Shin, Hyunji; Choi, Jong Sun; Zhang, Xue; Park, Jaehoon; Hwang, Jaeeun; Kim, Hongdoo; Bae, Jin-Hyuk

2014-08-01

We studied the effects of negative gate-bias stress on the electrical characteristics of top-contact zinc-oxide (ZnO) thin-film transistors (TFTs), which were fabricated by spin coating a ZnO solution onto a silicon-nitride gate dielectric layer. The negative gate-bias stress caused characteristic degradations in the on-state currents and the field-effect mobility of the fabricated ZnO TFTs. Additionally, a decrease in the off-state currents and a positive shift in the threshold voltage occurred with increasing stress time. These results indicate that the negative gate-bias stress caused an injection of electrons into the gate dielectric, thereby deteriorating the TFT's performance.

Dual amplitude pulse generator for radiation detectors

DOEpatents

Hoggan, Jerry M.; Kynaston, Ronnie L.; Johnson, Larry O.

2001-01-01

A pulsing circuit for producing an output signal having a high amplitude pulse and a low amplitude pulse may comprise a current source for providing a high current signal and a low current signal. A gate circuit connected to the current source includes a trigger signal input that is responsive to a first trigger signal and a second trigger signal. The first trigger signal causes the gate circuit to connect the high current signal to a pulse output terminal whereas the second trigger signal causes the gate circuit to connect the low current signal to the pulse output terminal.

Effect of Mechanical Stresses on Characteristics of Chip Tantalum Capacitors

NASA Technical Reports Server (NTRS)

Teverovsky, Alexander A.

2007-01-01

The effect of compressive mechanical stresses on chip solid tantalum capacitors is investigated by monitoring characteristics of different part types under axial and hydrostatic stresses. Depending on part types, an exponential increase of leakage currents was observed when stresses exceeded 10 MPa to 40 MPa. For the first time, reversible variations of leakage currents (up to two orders of magnitude) with stress have been demonstrated. Mechanical stresses did not cause significant changes of AC characteristics of the capacitors, whereas breakdown voltages measured during the surge current testing decreased substantially indicating an increased probability of failures of stressed capacitors in low impedance applications. Variations of leakage currents are explained by a combination of two mechanisms: stress-induced scintillations and stress-induced generation of electron traps in the tantalum pentoxide dielectric.

Availability and Distribution of Base Flow in Lower Honokohau Stream, Island of Maui

USGS Publications Warehouse

Fontaine, Richard A.

2003-01-01

Honokohau Stream is one of the few perennial streams in the Lahaina District of West Maui. Current Honokohau water-use practices often lead to conflicts among water users, which are most evident during periods of base flow. To better manage the resource, data are needed that describe the availability and distribution of base flow in lower Honokohau Stream and how base flow is affected by streamflow diversion and return-flow practices. Flow-duration discharges for percentiles ranging from 50 to 95 percent were estimated at 13 locations on lower Honokohau Stream using data from a variety of sources. These sources included (1) available U.S. Geological Survey discharge data, (2) published summaries of Maui Land & Pineapple Company, Inc. diversion and water development-tunnel data, (3) seepage run and low-flow partial-record discharge measurements made for this study, and (4) current (2003) water diversion and return-flow practices. These flow-duration estimates provide a detailed characterization of the distribution and availability of base flow in lower Honokohau Stream. Estimates of base-flow statistics indicate the significant effect of Honokohau Ditch diversions on flow in the stream. Eighty-six percent of the total flow upstream from the ditch is diverted from the stream. Immediately downstream from the diversion dam there is no flow in the stream 91.2 percent of the time, except for minor leakage through the dam. Flow releases at the Taro Gate, from Honokohau Ditch back into the stream, are inconsistent and were found to be less than the target release of 1.55 cubic feet per second on 9 of the 10 days on which measurements were made. Previous estimates of base-flow availability downstream from the Taro Gate release range from 2.32 to 4.6 cubic feet per second (1.5 to 3.0 million gallons per day). At the two principal sites where water is currently being diverted for agricultural use in the valley (MacDonald's and Chun's Dams), base flows of 2.32 cubic feet per second (1.5 million gallons per day) are available more than 95 percent of the time at MacDonald's Dam and 80 percent of the time at Chun's Dam. Base flows of 4.6 cubic feet per second (3.0 million gallons per day) are available 65 and 56 percent of the time, respectively. A base-flow water-accounting model was developed to estimate how flow-duration discharges for 13 sites on Honokohau Stream would change in response to a variety of flow release and diversion practices. A sample application of the model indicates that there is a 1 to 1 relation between changes in flow release rates at the Taro Gate and base flow upstream from MacDonald's Dam. At Chun's Dam the relation between Taro Gate releases and base flow varies with flow-duration percentiles. At the 95th and 60th percentiles, differences in base flow at Chun's Dam would equal about 50 and 90 percent of the change at the Taro Gate.

Fabrication and characteristics of MOSFET protein chip for detection of ribosomal protein.

PubMed

Park, Keun-Yong; Kim, Min-Suk; Choi, Sie-Young

2005-04-15

A metal oxide silicon field effect transistor (MOSFET) protein chip for the easy detection of protein was fabricated and its characteristics were investigated. Generally, the drain current of the MOSFET is varied by the gate potential. It is expected that the formation of an antibody-antigen complex on the gate of MOSFET would lead to a detectable change in the charge distribution and thus, directly modulate the drain current of MOSFET. As such, the drain current of the MOSFET protein chip can be varied by ribosomal proteins absorbed by the self-assembled monolayer (SAM) immobilized on the gate (Au) surface, as ribosomal protein has positive charge, and these current variations then used as the response of the protein chip. The gate of MOSFET protein chip is not directly biased by an external voltage source, so called open gate or floating gate MOSFET, but rather chemically modified by immobilized molecular receptors called self-assembled monolayer (SAM). In our experiments, the current variation in the proposed protein chip was about 8% with a protein concentration of 0.7 mM. As the protein concentration increased, the drain current also gradually increased. In addition, there were some drift of the drain current in the device. It is considered that these drift might be caused by the drift from the MOSFET itself or protein absorption procedures that are relied on the facile attachment of thiol (-S) ligands to the gate (Au) surface. We verified the formation of SAM on the gold surface and the absorption of protein through the surface plasmon resonance (SPR) measurement.

A universal steady state I-V relationship for membrane current

NASA Technical Reports Server (NTRS)

Chernyak, Y. B.; Cohen, R. J. (Principal Investigator)

1995-01-01

A purely electrical mechanism for the gating of membrane ionic channel gives rise to a simple I-V relationship for membrane current. Our approach is based on the known presence of gating charge, which is an established property of the membrane channel gating. The gating charge is systematically treated as a polarization of the channel protein which varies with the external electric field and modifies the effective potential through which the ions migrate in the channel. Two polarization effects have been considered: 1) the up or down shift of the whole potential function, and 2) the change in the effective electric field inside the channel which is due to familiar effect of the effective reduction of the electric field inside a dielectric body because of the presence of surface charges on its surface. Both effects are linear in the channel polarization. The ionic current is described by a steady state solution of the Nernst-Planck equation with the potential directly controlled by the gating charge system. The solution describes reasonably well the steady state and peak-current I-V relationships for different channels, and when applied adiabatically, explains the time lag between the gating charge current and the rise of the ionic current. The approach developed can be useful as an effective way to model the ionic currents in axons, cardiac cells and other excitable tissues.

Structural Modification of Organic Thin-Film Transistors for Photosensor Application

NASA Astrophysics Data System (ADS)

Jeong, Hyeon Seok; Bae, Jin-Hyuk; Lee, Hyeonju; Ndikumana, Joel; Park, Jaehoon

2018-05-01

We investigated the light response characteristics of bottom-gate/top-contact organic TFTs fabricated using pentacene and polystyrene as an organic semiconductor and a polymeric insulator, respectively. The pentacene TFT with overlaps (50 μm) between the source and gate electrodes as well as between the drain and gate electrodes exhibited negligible hysteresis in its transfer characteristics upon reversal of the gate voltage sweep direction. When the TFTs were structurally modified to produce an underlap structure between the source and gate electrodes, clockwise hysteresis and a drain-current decrease were observed, which were further augmented by increasing the gate underlap (from 30 μm to 50 μm and 70 μm). Herein, these results are explained in terms of space charge formation and accumulation capacitance reduction. Importantly, we found that space charges formed under the source electrode contributed to the drain currents via light irradiation through the underlap region. Under constant bias conditions, the TFTs with gate underlap structures thus exhibited on-state drain current changes in response to light signals. In our study, an optimal photosensitivity exceeding 11 was achieved by the TFT with a 30 μm gate underlap. Consequently, we suggest that gate underlap structure modification is a viable means of implementing light responsiveness in organic TFTs.

The role of localized junction leakage in the temperature-dependent laser-beam-induced current spectra for HgCdTe infrared focal plane array photodiodes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Feng, A. L.; Li, G., E-mail: liguang1971@ahu.edu.cn, E-mail: xschen@mail.sitp.ac.cn; He, G.

2013-11-07

We have performed the study on the dependence of laser beam induced current (LBIC) spectra on the temperature for the vacancy-doped molecular beam epitaxy grown Hg{sub 1−x}Cd{sub x}Te (x = 0.31) photodiodes by both experiment and numerical simulations. It is found that the measured LBIC signal has different distributions for different temperature extents. The LBIC profile tends to be more asymmetric with increasing temperature below 170 K. But the LBIC profile becomes more symmetric with increasing temperature above 170 K. Based on a localized leakage model, it is indicated that the localized junction leakage can lead to asymmetric LBIC signal, in good agreement withmore » the experimental data. The reason is that the trap-assisted tunneling current is the dominant leakage current at the cryogenic temperature below 170 K while the diffusion current component becomes dominant above the temperature of 170 K. The results are helpful for us to better clarify the mechanism of the dependence of LBIC spectra on temperature for the applications of HgCdTe infrared photodiodes.« less

Bottom-up and top-down fabrication of nanowire-based electronic devices: In situ doping of vapor liquid solid grown silicon nanowires and etch-dependent leakage current in InGaAs tunnel junctions

NASA Astrophysics Data System (ADS)

Kuo, Meng-Wei

Semiconductor nanowires are important components in future nanoelectronic and optoelectronic device applications. These nanowires can be fabricated using either bottom-up or top-down methods. While bottom-up techniques can achieve higher aspect ratio at reduced dimension without having surface and sub-surface damage, uniform doping distributions with abrupt junction profiles are less challenging for top-down methods. In this dissertation, nanowires fabricated by both methods were systematically investigated to understand: (1) the in situ incorporation of boron (B) dopants in Si nanowires grown by the bottom-up vapor-liquid-solid (VLS) technique, and (2) the impact of plasma-induced etch damage on InGaAs p +-i-n+ nanowire junctions for tunnel field-effect transistors (TFETs) applications. In Chapter 2 and 3, the in situ incorporation of B in Si nanowires grown using silane (SiH4) or silicon tetrachloride (SiCl4) as the Si precursor and trimethylboron (TMB) as the p-type dopant source is investigated by I-V measurements of individual nanowires. The results from measurements using a global-back-gated test structure reveal nonuniform B doping profiles on nanowires grown from SiH4, which is due to simultaneous incorporation of B from nanowire surface and the catalyst during VLS growth. In contrast, a uniform B doping profile in both the axial and radial directions is achieved for TMBdoped Si nanowires grown using SiCl4 at high substrate temperatures. In Chapter 4, the I-V characteristics of wet- and dry-etched InGaAs p+-i-n+ junctions with different mesa geometries, orientations, and perimeter-to-area ratios are compared to evaluate the impact of the dry etch process on the junction leakage current properties. Different post-dry etch treatments, including wet etching and thermal annealing, are performed and the effectiveness of each is assessed by temperaturedependent I-V measurements. As compared to wet-etched control devices, dry-etched junctions have a significantly higher leakage current and a current kink in the reverse bias regime, which is likely due to additional trap states created by plasma-induced damage during the Cl2/Ar/H2 mesa isolation step. These states extend more than 60 nm from the mesa surface and can only be partially passivated after a thermal anneal at 350°C for 20 minutes. The evolution of the electrical properties with post-dry etch treatments indicates that the shallow and deep-level trap states resulting from ion-induced point defects, arsenic vacancies and hydrogen-dopant complexes are the primary cause of degradation in the electrical properties of the dry-etched junctions.

Preparation and properties of sol-gel derived PZT thin films for decoupling capacitor applications

NASA Astrophysics Data System (ADS)

Schwartz, R. W.; Dimos, D.; Lockwood, S. J.; Torres, V. M.

The use of ceramic thin films as decoupling capacitors offers the possibility of capacitor integration within the integrated circuit (IC) package and, potentially, directly onto the IC itself. Since these configurations minimize series inductance, higher operational speeds are possible. In the present study, the authors have investigated the dielectric and leakage characteristics of sol-gel PZT films. For compositions near the morphotropic phase boundary, dielectric constants of 1000, and loss tangents of about 0.02, are observed. The current-voltage behavior of the capacitors is characterized by a non-linear response, and significant asymmetry in both the leakage and breakdown characteristics as a function of bias sign is observed. Breakdown fields for PZT 53/47 thin films are typically approximately 800 kV/cm at 25 C. The authors have also studied the effects of La and Nb dopant additions and alternate firing strategies on film leakage characteristics. Donor doping at 2 - 5 mol % lowers leakage currents by a factor of 10(exp 3). For films prepared by a multilayering approach, firing each layer to crystallization results in leakage currents that are a factor of 10(exp 2) lower than films prepared by the standard process.

Integrating Partial Polarization into a Metal-Ferroelectric-Semiconductor Field Effect Transistor Model

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

1999-01-01

The ferroelectric channel in a Metal-Ferroelectric-Semiconductor Field Effect Transistor (MFSFET) can partially change its polarization when the gate voltage near the polarization threshold voltage. This causes the MFSFET Drain current to change with repeated pulses of the same gate voltage near the polarization threshold voltage. A previously developed model [11, based on the Fermi-Dirac function, assumed that for a given gate voltage and channel polarization, a sin-le Drain current value would be generated. A study has been done to characterize the effects of partial polarization on the Drain current of a MFSFET. These effects have been described mathematically and these equations have been incorporated into a more comprehensive mathematical model of the MFSFET. The model takes into account the hysteresis nature of the MFSFET and the time dependent decay as well as the effects of partial polarization. This model defines the Drain current based on calculating the degree of polarization from previous gate pulses, the present Gate voltage, and the amount of time since the last Gate volta-e pulse.

A precision analogue integrator system for heavy current measurement in MFDC resistance spot welding

NASA Astrophysics Data System (ADS)

Xia, Yu-Jun; Zhang, Zhong-Dian; Xia, Zhen-Xin; Zhu, Shi-Liang; Zhang, Rui

2016-02-01

In order to control and monitor the quality of middle frequency direct current (MFDC) resistance spot welding (RSW), precision measurement of the welding current up to 100 kA is required, for which Rogowski coils are the only viable current transducers at present. Thus, a highly accurate analogue integrator is the key to restoring the converted signals collected from the Rogowski coils. Previous studies emphasised that the integration drift is a major factor that influences the performance of analogue integrators, but capacitive leakage error also has a significant impact on the result, especially in long-time pulse integration. In this article, new methods of measuring and compensating capacitive leakage error are proposed to fabricate a precision analogue integrator system for MFDC RSW. A voltage holding test is carried out to measure the integration error caused by capacitive leakage, and an original integrator with a feedback adder is designed to compensate capacitive leakage error in real time. The experimental results and statistical analysis show that the new analogue integrator system could constrain both drift and capacitive leakage error, of which the effect is robust to different voltage levels of output signals. The total integration error is limited within  ±0.09 mV s-1 0.005% s-1 or full scale at a 95% confidence level, which makes it possible to achieve the precision measurement of the welding current of MFDC RSW with Rogowski coils of 0.1% accuracy class.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Peng, Yong; Yao, Manwen, E-mail: yaomw@tongji.edu.cn; Chen, Jianwen

The electrical characteristics of SrTiO{sub 3}/Al{sub 2}O{sub 3} (160 nm up/90 nm down) laminated film capacitors using the sol-gel process have been investigated. SrTiO{sub 3} is a promising and extensively studied high-K dielectric material, but its leakage current property is poor. SrTiO{sub 3}/Al{sub 2}O{sub 3} laminated films can effectively suppress the demerits of pure SrTiO{sub 3} films under low electric field, but the leakage current value reaches to 0.1 A/cm{sup 2} at higher electric field (>160 MV/m). In this study, a new approach was applied to reduce the leakage current and improve the dielectric strength of SrTiO{sub 3}/Al{sub 2}O{sub 3} laminated films. Compared tomore » laminated films with Au top electrodes, dielectric strength of laminated films with Al top electrodes improves from 205 MV/m to 322 MV/m, simultaneously the leakage current maintains the same order of magnitude (10{sup −4} A/cm{sup 2}) until the breakdown occurs. The above electrical characteristics are attributed to the anodic oxidation reaction in origin, which can repair the defects of laminated films at higher electric field. The anodic oxidation reactions have been confirmed by the corresponding XPS measurement and the cross sectional HRTEM analysis. This work provides a new approach to fabricate dielectrics with high dielectric strength and low leakage current.« less

Impact of electrocardiogram-gated multi-slice computed tomography-based aortic annular measurement in the evaluation of paravalvular leakage following transcatheter aortic valve replacement: the efficacy of the OverSized AortiC Annular ratio (OSACA ratio) in TAVR.

PubMed

Maeda, Koichi; Kuratani, Toru; Torikai, Kei; Shimamura, Kazuo; Mizote, Isamu; Ichibori, Yasuhiro; Takeda, Yasuharu; Daimon, Takashi; Nakatani, Satoshi; Nanto, Shinsuke; Sawa, Yoshiki

2013-07-01

Even mild paravalvular leakage (PVL) after transcatheter aortic valve replacement (TAVR) is associated with increased late mortality. Electrocardiogram-gated multi-slice computed tomography (MSCT) enables detailed aortic annulus assessment. We describe the impact of MSCT for PVL following TAVR. Congruence between the prosthesis and annulus diameters affects PVL; therefore, we calculated the OverSized AortiC Annular ratio (OSACA ratio) and OSACA (transesophageal echocardiography, TEE) ratio as prosthesis diameter/annulus diameter on MSCT or TEE, respectively, and compared their relationship with PVL ≤ trace following TAVR. Of 36 consecutive patients undergoing TAVR (Group A), the occurrence of PVL ≤ trace (33.3%) was significantly related to the OSACA ratio (p = 0.00020). In receiver-operating characteristics analysis, the cutoff value of 1.03 for the OSACA ratio had the highest sum of sensitivity (75.0%) and specificity (91.7%; AUC = 0.87) with significantly higher discriminatory performance for PVL as compared to the OSACA (TEE) ratio (AUC = 0.69, p = 0.028). In nine consecutive patients (Group B) undergoing TAVR based on guidelines formulated from our experience with Group A, PVL ≤ trace was significantly more frequent (88.9%) than that in Group A (p = 0.0060). The OSACA ratio has a significantly higher discriminatory performance for PVL ≤ trace than the OSACA (TEE) ratio, and aortic annular measurement from MSCT is more accurate than that from TEE. © 2013 Wiley Periodicals, Inc.

The Value of Changing Position in the Detection of CSF Leakage in Spontaneous Intracranial Hypotension Using Tc-99m DTPA Scintigraphy: Two Case Reports.

PubMed

Lu, Yu Yu; Wang, Hsin Yi; Lin, Ying; Lin, Wan Yu

2012-09-01

Radionuclide Cisternography (RNC) is of potential value in pointing out the sites of cerebrospinal fluid (CSF) leakage in patients with spontaneous intracranial hypotension (SIH). In the current report, we present two patients who underwent RNC for suspected CSF leakage. Both patients underwent magnetic resonance imaging (MRI) and RNC for evaluation. We describe a simple method to increase the detection ability of RNC for CSF leakage in patients with SIH.

Using provenance of terrigenous sediment to reconstruct the Agulhas Leakage during the Early and Late Pleistocene

NASA Astrophysics Data System (ADS)

Pearson, B.; Franzese, A. M.

2017-12-01

The Agulhas Current, the strongest western boundary current in the southern hemisphere, is uniquely characterized by its strong retroflection. The current carries water southward from the Indian Ocean toward the cape of South Africa, before turning back on itself. At this point of retroflection, some of the current's flow escapes into the southern Atlantic Ocean. This transfer of water from the Indian Ocean to Atlantic Ocean makes up the Agulhas Leakage. The Leakage occurs in a series of eddies and rings located in the Cape Basin south of the African continent. Scientific literature demonstrates that relatively buoyant leakage water has been a determining factor varying strength of the Atlantic Meridional Ocean Current (AMOC), during glacial-interglacial cycles. It has been demonstrated that radiogenic isotope, major, and trace element concentrations serve as a proxy for terrigenous sediment provenance in the Agulhas region. Current understanding is that terrigenous sediment provenance is older during warmer periods of deposition. This corresponds to more input from southeastern African end members, and thus a stronger Agulhas Current, during warming periods in the paleoclimate record. Conversely, younger terrigenous sediment deposited during colder periods, such as the Last Glacial Maximum, suggests a weaker Agulhas Current, and less Agulhas Leakage. In 2016, on the International Ocean Discovery Program Expedition 361, sediment cores were drilled at 6 sites in the Greater Agulhas region. A major goal of the expedition was to expand knowledge of the relation between changes in the Agulhas System and changes in paleoclimate, southern African climate, and AMOC. We analyzed sediment from Expedition 361 Site U1479 (35°03.53'S; 17°24.06'E; 2615 mbsl) located where the Agulhas Leakage occurs. We measured Argon, strontium isotope ratios, ɛNd, trace and major element concentrations on the <2 micron clay fraction. Preliminary results foretell promising findings. For instance, for the Early Pleistocene ( 1.3 - 1.5 Ma), K-Ar model ages correlate with shipboard measurements of natural gamma radiation, which show approximate 41 kyr periodicity.

Electrical overstress in AlGaN/GaN HEMTs: study of degradation processes

NASA Astrophysics Data System (ADS)

Kuzmík, J.; Pogany, D.; Gornik, E.; Javorka, P.; Kordoš, P.

2004-02-01

We study degradation mechanisms in 50 μm gate width/0.45 μm length AlGaN/GaN HEMTs after electrical overstresses. One hundred nanosecond long rectangular current pulses are applied on the drain contact keeping either both of the source and gate grounded or the source grounded and gate floating. Source-drain pulsed I- V characteristics show similar shape for both connections. After the HEMT undergoes the source-drain breakdown, a negative differential resistance region transits into a low voltage/high current region. Changes in the Schottky contact dc I- V characteristics and in the source and drain ohmic contacts are investigated as a function of the current stress level and are related to the HEMT dc performance. Catastrophic HEMT degradation was observed after Istress=1.65 A in case of the 'gate floating' connection due to ohmic contacts burnout. In case of the 'gate grounded' connection, Istress=0.45 A was sufficient for the gate failure showing a high gate susceptibility to overstress. Backside transient interferometric mapping technique experiment reveals a current filament formation under both HEMT stress connections. Infrared camera observations lead to conclusion that the filament formation together with a consequent high-density electron flow is responsible for a dark spot formation and gradual ohmic contact degradation.

Enhancement of minority carrier injection in ambipolar carbon nanotube transistors using double-gate structures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Bongjun; Liang, Kelly; Dodabalapur, Ananth, E-mail: ananth.dodabalapur@engr.utexas.edu

We show that double-gate ambipolar thin-film transistors can be operated to enhance minority carrier injection. The two gate potentials need to be significantly different for enhanced injection to be observed. This enhancement is highly beneficial in devices such as light-emitting transistors where balanced electron and hole injections lead to optimal performance. With ambipolar single-walled carbon nanotube semiconductors, we demonstrate that higher ambipolar currents are attained at lower source-drain voltages, which is desired for portable electronic applications, by employing double-gate structures. In addition, when the two gates are held at the same potential, the expected advantages of the double-gate transistors suchmore » as enhanced on-current are also observed.« less

5.8kV SiC PiN Diode for Switching of High-Efficiency Inductive Pulsed Plasma Thruster Circuits

NASA Technical Reports Server (NTRS)

Toftul, Alexandra; Polzin, Kurt A.; Hudgins, Jerry L.

2014-01-01

Inductive Pulsed Plasma Thruster (IPPT) pulse circuits, such as those needed to operate the Pulsed Inductive Thruster (PIT), are required to quickly switch capacitor banks operating at a period of µs while conducting current at levels on the order of at least 10 kA. [1,2] For all iterations of the PIT to date, spark gaps have been used to discharge the capacitor bank through an inductive coil. Recent availability of fast, high-power solid state switching devices makes it possible to consider the use of semiconductor switches in modern IPPTs. In addition, novel pre-ionization schemes have led to a reduction in discharge energy per pulse for electric thrusters of this type, relaxing the switching requirements for these thrusters. [3,4] Solid state switches offer the advantage of greater controllability and reliability, as well as decreased drive circuit dimensions and mass relative to spark gap switches. The use of solid state devices such as Integrated Gate Bipolar Transistors (IGBTs), Gate Turn-off Thyristors (GTOs) and Silicon-Controlled Rectifiers (SCRs) often involves the use of power diodes. These semiconductor devices may be connected antiparallel to the switch for protection from reverse current, or used to reduce power loss in a circuit by clamping off current ringing. In each case, higher circuit efficiency may be achieved by using a diode that is able to transition, or 'switch,' from the forward conducting state ('on' state) to the reverse blocking state ('off' state) in the shortest amount of time, thereby minimizing current ringing and switching losses. Silicon Carbide (SiC) PiN diodes offer significant advantages to conventional fast-switching Silicon (Si) diodes for high power and fast switching applications. A wider band gap results in a breakdown voltage 10 times that of Si, so that a SiC device may have a thinner drift region for a given blocking voltage. [5] This leads to smaller, lighter devices for high voltage applications, as well as reduced forward conduction losses, faster reverse recovery time (faster turn-off), and lower-magnitude reverse recovery current. In addition, SiC devices have lower leakage current as compared to their Si counterparts, and a high thermal conductivity, potentially allowing the former to operate at higher temperatures with a smaller, lighter heatsink (or no heatsink at all).

Mechanism of a-IGZO TFT device deterioration—illumination light wavelength and substrate temperature effects

NASA Astrophysics Data System (ADS)

Chen, Te-Chih; Kuo, Yue; Chang, Ting-Chang; Chen, Min-Chen; Chen, Hua-Mao

2017-10-01

Device characteristics changes in an a-IGZO thin film transistor under light illumination and at raised temperature have been investigated. Light exposure causes a large leakage current, which is more obvious with an increase in the illumination energy, power and the temperature. The increase in the leakage current is due to the trap assisted photon excitation process that generates electron-hole pairs and the mechanism is enhanced with the additional thermal energy. The leakage current comes from the source side because holes generated in the process drift to the source side and therefore lower the barrier height. The above mechanism has been further verified with experiments of drain bias induced shifts in the threshold voltage and the subthreshold slope.

The effect of guard ring on leakage current and spectroscopic performance of TlBr planar detectors

NASA Astrophysics Data System (ADS)

Kargar, Alireza; Kim, Hadong; Cirignano, Leonard; Shah, Kanai

2014-09-01

Four thallium bromide planar detectors were fabricated from materials grown at RMD Inc. The TlBr samples were prepared to investigate the effect of guard ring on device gamma-ray spectroscopy performance, and to investigate the leakage current through surface and bulk. The devices' active area in planar configuration were 4.4 × 4.4 × 1.0 mm3. In this report, the detector fabrication process is described and the resulting energy spectra are discussed. It is shown that the guard ring improves device spectroscopic performance by shielding the sensing electrode from the surface leakage current, and by making the electric filed more uniform in the active region of the device.

Process monitoring using automatic physical measurement based on electrical and physical variability analysis

NASA Astrophysics Data System (ADS)

Shauly, Eitan N.; Levi, Shimon; Schwarzband, Ishai; Adan, Ofer; Latinsky, Sergey

2015-04-01

A fully automated silicon-based methodology for systematic analysis of electrical features is shown. The system was developed for process monitoring and electrical variability reduction. A mapping step was created by dedicated structures such as static-random-access-memory (SRAM) array or standard cell library, or by using a simple design rule checking run-set. The resulting database was then used as an input for choosing locations for critical dimension scanning electron microscope images and for specific layout parameter extraction then was input to SPICE compact modeling simulation. Based on the experimental data, we identified two items that must be checked and monitored using the method described here: transistor's sensitivity to the distance between the poly end cap and edge of active area (AA) due to AA rounding, and SRAM leakage due to a too close N-well to P-well. Based on this example, for process monitoring and variability analyses, we extensively used this method to analyze transistor gates having different shapes. In addition, analysis for a large area of high density standard cell library was done. Another set of monitoring focused on a high density SRAM array is also presented. These examples provided information on the poly and AA layers, using transistor parameters such as leakage current and drive current. We successfully define "robust" and "less-robust" transistor configurations included in the library and identified unsymmetrical transistors in the SRAM bit-cells. These data were compared to data extracted from the same devices at the end of the line. Another set of analyses was done to samples after Cu M1 etch. Process monitoring information on M1 enclosed contact was extracted based on contact resistance as a feedback. Guidelines for the optimal M1 space for different layout configurations were also extracted. All these data showed the successful in-field implementation of our methodology as a useful process monitoring method.

Independent gate control of injected and detected spin currents in CVD graphene nonlocal spin valves

NASA Astrophysics Data System (ADS)

Anugrah, Yoska; Hu, Jiaxi; Stecklein, Gordon; Crowell, Paul A.; Koester, Steven J.

2018-01-01

Graphene is an ideal material for spintronic devices due to its low spin-orbit coupling and high mobility. One of the most important potential applications of graphene spintronics is for use in neuromorphic computing systems, where the tunable spin resistance of graphene can be used to apply analog weighting factors. A key capability needed to achieve spin-based neuromorphic computing systems is to achieve distinct regions of control, where injected and detected spin currents can be tuned independently. Here, we demonstrate the ability to achieve such independent control using a graphene spin valve geometry where the injector and detector regions are modulated by two separate bottom gate electrodes. The spin transport parameters and their dependence on each gate voltage are extracted from Hanle precession measurements. From this analysis, local spin transport parameters and their dependence on the local gate voltage are found, which provide a basis for a spatially-resolved spin resistance network that simulates the device. The data and model are used to calculate the spin currents flowing into, through, and out of the graphene channel. We show that the spin current flowing through the graphene channel can be modulated by 30% using one gate and that the spin current absorbed by the detector can be modulated by 50% using the other gate. This result demonstrates that spin currents can be controlled by locally tuning the spin resistance of graphene. The integration of chemical vapor deposition (CVD) grown graphene with local gates allows for the implementation of large-scale integrated spin-based circuits.

Compact universal logic gates realized using quantization of current in nanodevices.

PubMed

Zhang, Wancheng; Wu, Nan-Jian; Yang, Fuhua

2007-12-12

This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.

High voltage and current, gate assisted, turn-off thyristor development

NASA Technical Reports Server (NTRS)

Nowalk, T. P.; Brewster, J. B.; Kao, Y. C.

1972-01-01

An improved high speed power switch with unique turn-off capability was developed. This gate assisted turn-off thyristor (GATT) was rated 1000 volts and 100 amperes with turn-off times of 2 microseconds. Fifty units were delivered for evaluation. In addition, test circuits designed to relate to the series inverter application were built and demonstrated. In the course of this work it was determined that the basic device design is adequate to meet the static characteristics and dynamic turn-off specification. It was further determined that the turn-on specification is critically dependent on the gate drive circuit due to the distributive nature of the cathode-gate geometry. Future work should emphasize design modifications which reduce the gate current required for fast turn-on, thereby opening the way to higher power (current) devices.

Conformational changes in the M2 muscarinic receptor induced by membrane voltage and agonist binding

PubMed Central

Navarro-Polanco, Ricardo A; Galindo, Eloy G Moreno; Ferrer-Villada, Tania; Arias, Marcelo; Rigby, J Ryan; Sánchez-Chapula, José A; Tristani-Firouzi, Martin

2011-01-01

Abstract The ability to sense transmembrane voltage is a central feature of many membrane proteins, most notably voltage-gated ion channels. Gating current measurements provide valuable information on protein conformational changes induced by voltage. The recent observation that muscarinic G-protein-coupled receptors (GPCRs) generate gating currents confirms their intrinsic capacity to sense the membrane electrical field. Here, we studied the effect of voltage on agonist activation of M2 muscarinic receptors (M2R) in atrial myocytes and how agonist binding alters M2R gating currents. Membrane depolarization decreased the potency of acetylcholine (ACh), but increased the potency and efficacy of pilocarpine (Pilo), as measured by ACh-activated K+ current, IKACh. Voltage-induced conformational changes in M2R were modified in a ligand-selective manner: ACh reduced gating charge displacement while Pilo increased the amount of charge displaced. Thus, these ligands manifest opposite voltage-dependent IKACh modulation and exert opposite effects on M2R gating charge displacement. Finally, mutations in the putative ligand binding site perturbed the movement of the M2R voltage sensor. Our data suggest that changes in voltage induce conformational changes in the ligand binding site that alter the agonist–receptor interaction in a ligand-dependent manner. Voltage-dependent GPCR modulation has important implications for cellular signalling in excitable tissues. Gating current measurement allows for the tracking of subtle conformational changes in the receptor that accompany agonist binding and changes in membrane voltage. PMID:21282291

Scaling behavior of fully spin-coated TFT

NASA Astrophysics Data System (ADS)

Mondal, Sandip; Kumar, Arvind; Rao, K. S. R. Koteswara; Venkataraman, V.

2017-05-01

We studied channel scaling behavior of fully spin coated, low temperature solution processed thin film transistor (TFT) fabricated on p++ - Si (˜1021 cm-3) as bottom gate. The solution processed, spin coated 40 nm thick amorphous Indium Gallium Zinc Oxide (a-IGZO) and 50 nm thick amorphous zirconium di-oxide (a-ZrO2) has been used as channel and low leakage dielectric at 350°C respectively. The channel scaling effect of the TFT with different width/length ratio (W/L= 2.5, 5 and 15) for same channel length (L = 10 μm) has been demonstrated. The lowest threshold voltage (Vth) is 6.25 V for the W/L=50/10. The maximum field effect mobility (μFE) has been found to be 0.123 cm2/Vs from W/L of 50/10 with the drain to source voltage (VD) of 10V and 20V gate to source voltage (VG). We also demonstrated that there is no contact resistance effect on the mobility of the fully sol-gel spin coated TFT.

Systematic review of methods to predict and detect anastomotic leakage in colorectal surgery.

PubMed

Hirst, N A; Tiernan, J P; Millner, P A; Jayne, D G

2014-02-01

Anastomotic leakage is a serious complication of gastrointestinal surgery resulting in increased morbidity and mortality, poor function and predisposing to cancer recurrence. Earlier diagnosis and intervention can minimize systemic complications but is hindered by current diagnostic methods that are non-specific and often uninformative. The purpose of this paper is to review current developments in the field and to identify strategies for early detection and treatment of anastomotic leakage. A systematic literature search was performed using the MEDLINE, Embase, PubMed and Cochrane Library databases. Search terms included 'anastomosis' and 'leak' and 'diagnosis' or 'detection' and 'gastrointestinal' or 'colorectal'. Papers concentrating on the diagnosis of gastrointestinal anastomotic leak were identified and further searches were performed by cross-referencing. Computerized tomography CT scanning and water-soluble contrast studies are the current preferred techniques for diagnosing anastomotic leakage but suffer from variable sensitivity and specificity, have logistical constraints and may delay timely intervention. Intra-operative endoscopy and imaging may offer certain advantages, but the ability to predict anastomotic leakage is unproven. Newer techniques involve measurement of biomarkers for anastomotic leakage and have the potential advantage of providing cheap real-time monitoring for postoperative complications. Current diagnostic tests often fail to diagnose anastomotic leak at an early stage that enables timely intervention and minimizes serious morbidity and mortality. Emerging technologies, based on detection of local biomarkers, have achieved proof of concept status but require further evaluation to determine whether they translate into improved patient outcomes. Further research is needed to address this important, yet relatively unrecognized, area of unmet clinical need. Colorectal Disease © 2013 The Association of Coloproctology of Great Britain and Ireland.