Ultrashort Channel Length Black Phosphorus Field-Effect Transistors.

PubMed

Miao, Jinshui; Zhang, Suoming; Cai, Le; Scherr, Martin; Wang, Chuan

2015-09-22

This paper reports high-performance top-gated black phosphorus (BP) field-effect transistors with channel lengths down to 20 nm fabricated using a facile angle evaporation process. By controlling the evaporation angle, the channel length of the transistors can be reproducibly controlled to be anywhere between 20 and 70 nm. The as-fabricated 20 nm top-gated BP transistors exhibit respectable on-state current (174 μA/μm) and transconductance (70 μS/μm) at a VDS of 0.1 V. Due to the use of two-dimensional BP as the channel material, the transistors exhibit relatively small short channel effects, preserving a decent on-off current ratio of 10(2) even at an extremely small channel length of 20 nm. Additionally, unlike the unencapsulated BP devices, which are known to be chemically unstable in ambient conditions, the top-gated BP transistors passivated by the Al2O3 gate dielectric layer remain stable without noticeable degradation in device performance after being stored in ambient conditions for more than 1 week. This work demonstrates the great promise of atomically thin BP for applications in ultimately scaled transistors.

Submicron Silicon MOSFET

NASA Technical Reports Server (NTRS)

Daud, T.

1986-01-01

Process for making metal-oxide/semiconductor field-effect transistors (MOSFET's) results in gate-channel lengths of only few hundred angstroms about 100 times as small as state-of-the-art devices. Gates must be shortened to develop faster MOSFET's; proposed fabrication process used to study effects of size reduction in MOS devices and eventually to build practical threedimensional structures.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Choi, Hyun-Sik; Jeon, Sanghun, E-mail: jeonsh@korea.ac.kr

Upon light exposure, an indium-zinc-oxide (IZO) thin-film transistor (TFT) presents higher photoconductivity by several orders of magnitude at the negative gate bias region. Among various device geometrical factors, scaling down the channel length of the photo-transistor results in an anomalous increase in photoconductivity. To probe the origin of this high photoconductivity in short-channel device, we measured transient current, current–voltage, and capacitance–voltage characteristics of IZO–TFTs with various channel lengths and widths before and after illumination. Under the illumination, the equilibrium potential region which lies far from front interface exists only in short-channel devices, forming the un-depleted conducting back channel. This regionmore » plays an important role in carrier transport under the illumination, leading to high photoconductivity in short-channel devices. Photon exposure coupled with gate-modulated band bending for short-channel devices leads to the accumulation of V{sub o}{sup ++} at the front channel and screening negative gate bias, thereby generating high current flow in the un-depleted back-channel region.« less

Reconfigurable ultra-thin film GDNMOS device for ESD protection in 28 nm FD-SOI technology

NASA Astrophysics Data System (ADS)

Athanasiou, Sotirios; Legrand, Charles-Alexandre; Cristoloveanu, Sorin; Galy, Philippe

2017-02-01

We propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fabricated with 28 nm UTBB FD-SOI high-k metal gate technology. By modifying the combination of the diode and transistor gate stacks, the robustness of the device is optimized, achieving a maximum breakdown voltage (VBR) of 4.9 V. In addition, modifications of the gate length modulate the trigger voltage (Vt1) with a minimum value of 3.5 V. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation. A lower doping of the base enhances the bipolar gain, leading to thyristor behavior. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior.

Study on effective MOSFET channel length extracted from gate capacitance

NASA Astrophysics Data System (ADS)

Tsuji, Katsuhiro; Terada, Kazuo; Fujisaka, Hisato

2018-01-01

The effective channel length (L GCM) of metal-oxide-semiconductor field-effect transistors (MOSFETs) is extracted from the gate capacitances of actual-size MOSFETs, which are measured by charge-injection-induced-error-free charge-based capacitance measurement (CIEF CBCM). To accurately evaluate the capacitances between the gate and the channel of test MOSFETs, the parasitic capacitances are removed by using test MOSFETs having various channel sizes and a source/drain reference device. A strong linear relationship between the gate-channel capacitance and the design channel length is obtained, from which L GCM is extracted. It is found that L GCM is slightly less than the effective channel length (L CRM) extracted from the measured MOSFET drain current. The reason for this is discussed, and it is found that the capacitance between the gate electrode and the source and drain regions affects this extraction.

Intermodulation distortion and linearity performance assessment of 50-nm gate length L-DUMGAC MOSFET for RFIC design

NASA Astrophysics Data System (ADS)

Chaujar, Rishu; Kaur, Ravneet; Saxena, Manoj; Gupta, Mridula; Gupta, R. S.

2008-08-01

The distortion and linearity behaviour of MOSFETs is imperative for low-noise applications and RFICs design. In this paper, an extensive study on the RF-distortion and linearity behaviour of Laterally Amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET is performed and the influence of technology variations such as gate length, negative junction depth (NJD), substrate bias, drain bias and gate material workfunction is explored using ATLAS device simulator. Simulation results reveal that L-DUMGAC MOSFET significantly enhances the linearity and intermodulation distortion performance in terms of figure of merit (FOM) metrics: V, V, IIP3, IMD3 and higher order transconductance coefficients: gm1, gm2, gm3, proving its efficacy for RFIC design. The work, thus, optimize the device's bias point for RFICs with higher efficiency and better linearity performance.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Technical Reports Server (NTRS)

Sewell, James S.; Bozada, Christopher A.

1994-01-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Astrophysics Data System (ADS)

Sewell, James S.; Bozada, Christopher A.

1994-02-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

AC signal characterization for optimization of a CMOS single-electron pump

NASA Astrophysics Data System (ADS)

Murray, Roy; Perron, Justin K.; Stewart, M. D., Jr.; Zimmerman, Neil M.

2018-02-01

Pumping single electrons at a set rate is being widely pursued as an electrical current standard. Semiconductor charge pumps have been pursued in a variety of modes, including single gate ratchet, a variety of 2-gate ratchet pumps, and 2-gate turnstiles. Whether pumping with one or two AC signals, lower error rates can result from better knowledge of the properties of the AC signal at the device. In this work, we operated a CMOS single-electron pump with a 2-gate ratchet style measurement and used the results to characterize and optimize our two AC signals. Fitting this data at various frequencies revealed both a difference in signal path length and attenuation between our two AC lines. Using this data, we corrected for the difference in signal path length and attenuation by applying an offset in both the phase and the amplitude at the signal generator. Operating the device as a turnstile while using the optimized parameters determined from the 2-gate ratchet measurement led to much flatter, more robust charge pumping plateaus. This method was useful in tuning our device up for optimal charge pumping, and may prove useful to the semiconductor quantum dot community to determine signal attenuation and path differences at the device.

Improved Performance of h-BN Encapsulated Double Gate Graphene Nanomesh Field Effect Transistor for Short Channel Length

NASA Astrophysics Data System (ADS)

Tiwari, Durgesh Laxman; Sivasankaran, K.

This paper presents improved performance of Double Gate Graphene Nanomesh Field Effect Transistor (DG-GNMFET) with h-BN as substrate and gate oxide material. The DC characteristics of 0.95μm and 5nm channel length devices are studied for SiO2 and h-BN substrate and oxide material. For analyzing the ballistic behavior of electron for 5nm channel length, von Neumann boundary condition is considered near source and drain contact region. The simulated results show improved saturation current for h-BN encapsulated structure with two times higher on current value (0.375 for SiO2 and 0.621 for h-BN) as compared to SiO2 encapsulated structure. The obtained result shows h-BN to be a better substrate and oxide material for graphene electronics with improved device characteristics.

Analysis of DC and analog/RF performance on Cyl-GAA-TFET using distinct device geometry

NASA Astrophysics Data System (ADS)

Vishvakarma, S. K.; Beohar, Ankur; Vijayvargiya, Vikas; Trivedi, Priyal

2017-07-01

In this paper, analysis of DC and analog/RF performance on cylindrical gate-all-around tunnel field-effect transistor (TFET) has been made using distinct device geometry. Firstly, performance parameters of GAA-TFET are analyzed in terms of drain current, gate capacitances, transconductance, source-drain conductance at different radii and channel length. Furthermore, we also produce the geometrical analysis towards the optimized investigation of radio frequency parameters like cut-off frequency, maximum oscillation frequency and gain bandwidth product using a 3D technology computer-aided design ATLAS. Due to band-to-band tunneling based current mechanism unlike MOSFET, gate-bias dependence values as primary parameters of TFET differ. We also analyze that the maximum current occurs when radii of Si is around 8 nm due to high gate controllability over channel with reduced fringing effects and also there is no change in the current of TFET on varying its length from 100 to 40 nm. However current starts to increase when channel length is further reduced for 40 to 30 nm. Both of these trades-offs affect the RF performance of the device. Project supported by the Council of Scientific and Industrial Research (CSIR) Funded Research Project, Grant No. 22/0651/14/EMR-II, Government of India.

Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement

NASA Astrophysics Data System (ADS)

Raad, Bhagwan Ram; Nigam, Kaushal; Sharma, Dheeraj; Kondekar, P. N.

2016-06-01

This script features a study of bandgap, gate material work function and gate dielectric engineering for enhancement of DC and Analog/RF performance, reduction in the hot carriers effect (HCEs) and drain induced barrier lowering (DIBL) for better device reliability. In this concern, the use of band gap and gate material work function engineering improves the device performance in terms of the ON-state current and suppressed ambipolar behaviour with maintaining the low OFF-state current. With these advantages, the use of gate material work function engineering imposes restriction on the high frequency performance due to increment in the parasitic capacitances and also introduces the hot carrier effects. Hence, the gate dielectric engineering with bandgap and gate material work function engineering are used in this paper to overcome the cons of the gate material work function engineering by obtaining a superior performance in terms of the current driving capability, ambipolar conduction, HCEs, DIBL and high frequency parameters of the device for ultra-low power applications. Finally, the optimization of length for different work function is performed to get the best out of this.

Local gate control in carbon nanotube quantum devices

NASA Astrophysics Data System (ADS)

Biercuk, Michael Jordan

This thesis presents transport measurements of carbon nanotube electronic devices operated in the quantum regime. Nanotubes are contacted by source and drain electrodes, and multiple lithographically-patterned electrostatic gates are aligned to each device. Transport measurements of device conductance or current as a function of local gate voltages reveal that local gates couple primarily to the proximal section of the nanotube, hence providing spatially localized control over carrier density along the nanotube length. Further, using several different techniques we are able to produce local depletion regions along the length of a tube. This phenomenon is explored in detail for different contact metals to the nanotube. We utilize local gating techniques to study multiple quantum dots in carbon nanotubes produced both by naturally occurring defects, and by the controlled application of voltages to depletion gates. We study double quantum dots in detail, where transport measurements reveal honeycomb charge stability diagrams. We extract values of energy-level spacings, capacitances, and interaction energies for this system, and demonstrate independent control over all relevant tunneling rates. We report rf-reflectometry measurements of gate-defined carbon nanotube quantum dots with integrated charge sensors. Aluminum rf-SETs are electrostatically coupled to carbon nanotube devices and detect single electron charging phenomena in the Coulomb blockade regime. Simultaneous correlated measurements of single electron charging are made using reflected rf power from the nanotube itself and from the rf-SET on microsecond time scales. We map charge stability diagrams for the nanotube quantum dot via charge sensing, observing Coulomb charging diamonds beyond the first order. Conductance measurements of carbon nanotubes containing gated local depletion regions exhibit plateaus as a function of gate voltage, spaced by approximately 1e2/h, the quantum of conductance for a single (non-degenerate) mode. Plateau structure is investigated as a function of bias voltage, temperature, and magnetic field. We speculate on the origin of this surprising quantization, which appears to lack band and spin degeneracy.

T-gate geometric (solution for submicrometer gate length) HEMT: Physical analysis, modeling and implementation as parasitic elements and its usage as dual gate for variable gain amplifiers

NASA Astrophysics Data System (ADS)

Gupta, Ritesh; Rathi, Servin; Kaur, Ravneet; Gupta, Mridula; Gupta, R. S.

2009-03-01

In order to achieve superior RF performance, short gate length is required for the compound semiconductor field effect transistors, but the limitation in lithography for submicrometer gate lengths leads to the formation of various metal-insulator geometries like T-gate [Sandeep R. Bahl, Jesus A. del Alamo, Physics of breakdown in InAlAs/ n +-InGaAs heterostructure field-effect transistors, IEEE Trans. Electron Devices 41 (12) (1994) 2268-2275]. These geometries are the combination of various Metal-Semiconductor (MS)/Metal-Air-Semiconductor (MAS) contacts. Moreover, field plates [S. Karmalkar, M.S. Shur, G. Simin, M. Asif Khan, Field-plate engineering for HFETs, IEEE Trans. Electron Devices 52 (2005) 2534-2540] are also being fabricated these days, mainly at the drain end ( Γ-gate) having Metal-Insulator-Semiconductor (MIS) instead of MAS contact with the intention of increasing the breakdown voltage of the device. To realize the effect of upper gate electrode in the T-gate structure and field plates, an analytical model has been proposed in the present article by dividing the whole structure into MS/MIS contact regions, applying current continuity among them and solving iteratively. The model proposed for Metal-Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) [R. Gupta, S.K. Aggarwal, M. Gupta, R.S. Gupta, Analytical model for metal insulator semiconductor high electron mobility transistor (MISHEMT) for its high frequency and high power applications, J. Semicond. Technol. Sci. 6 (3) (2006) 189-198], is equally applicable to High Electron Mobility Transistors (HEMT) and has been used to formulate this model. In this paper, various structures and geometries have been compared to anticipate the need of T-gate modeling. The effect of MIS contacts has been implemented as parasitic resistance and capacitance and has also been studied to control the middle conventional gate as in dual gate technology by applying separate voltages across it. The results obtained using the proposed analytical scheme has been compared with simulated and experimental results, to prove the validity of our model.

Multi-Subband Ensemble Monte Carlo simulations of scaled GAA MOSFETs

NASA Astrophysics Data System (ADS)

Donetti, L.; Sampedro, C.; Ruiz, F. G.; Godoy, A.; Gamiz, F.

2018-05-01

We developed a Multi-Subband Ensemble Monte Carlo simulator for non-planar devices, taking into account two-dimensional quantum confinement. It couples self-consistently the solution of the 3D Poisson equation, the 2D Schrödinger equation, and the 1D Boltzmann transport equation with the Ensemble Monte Carlo method. This simulator was employed to study MOS devices based on ultra-scaled Gate-All-Around Si nanowires with diameters in the range from 4 nm to 8 nm with gate length from 8 nm to 14 nm. We studied the output and transfer characteristics, interpreting the behavior in the sub-threshold region and in the ON state in terms of the spatial charge distribution and the mobility computed with the same simulator. We analyzed the results, highlighting the contribution of different valleys and subbands and the effect of the gate bias on the energy and velocity profiles. Finally the scaling behavior was studied, showing that only the devices with D = 4nm maintain a good control of the short channel effects down to the gate length of 8nm .

DC and analog/RF performance optimisation of source pocket dual work function TFET

NASA Astrophysics Data System (ADS)

Raad, Bhagwan Ram; Sharma, Dheeraj; Kondekar, Pravin; Nigam, Kaushal; Baronia, Sagar

2017-12-01

We investigate a systematic study of source pocket tunnel field-effect transistor (SP TFET) with dual work function of single gate material by using uniform and Gaussian doping profile in the drain region for ultra-low power high frequency high speed applications. For this, a n+ doped region is created near the source/channel junction to decrease the depletion width results in improvement of ON-state current. However, the dual work function of the double gate is used for enhancement of the device performance in terms of DC and analog/RF parameters. Further, to improve the high frequency performance of the device, Gaussian doping profile is considered in the drain region with different characteristic lengths which decreases the gate to drain capacitance and leads to drastic improvement in analog/RF figures of merit. Furthermore, the optimisation is performed with different concentrations for uniform and Gaussian drain doping profile and for various sectional length of lower work function of the gate electrode. Finally, the effect of temperature variation on the device performance is demonstrated.

Non-Volatile High Speed & Low Power Charge Trapping Devices

NASA Astrophysics Data System (ADS)

Kim, Moon Kyung; Tiwari, Sandip

2007-06-01

We report the operational characteristics of ultra-small-scaled SONOS (below 50 nm gate width and length) and SiO2/SiO2 structural devices with 0.5 um gate width and length where trapping occurs in a very narrow region. The experimental work summarizes the memory characteristics of retention time, endurance cycles, and speed in SONOS and SiO2/SiO2 structures. Silicon nitride has many defects to hold electrons as charge storage media in SONOS memory. Defects are also incorporated during growth and deposition in device processing. Our experiments show that the interface between two oxides, one grown and one deposited, provides a remarkable media for electron storage with a smaller gate stack and thus lower operating voltage. The exponential dependence of the time on the voltage is reflected in the characteristic energy. It is ˜0.44 eV for the write process and ˜0.47 eV for the erase process in SiO2/SiO2 structural device which is somewhat more efficient than those of SONOS structure memory.

The prospects of transition metal dichalcogenides for ultimately scaled CMOS

NASA Astrophysics Data System (ADS)

Thiele, S.; Kinberger, W.; Granzner, R.; Fiori, G.; Schwierz, F.

2018-05-01

MOSFET gate length scaling has been a main source of progress in digital electronics for decades. Today, researchers still spend considerable efforts on reducing the gate length and on developing ultimately scaled MOSFETs, thereby exploring both new device architectures and alternative channel materials beyond Silicon such as two-dimensional TMDs (transition metal dichalcogenide). On the other hand, the envisaged scaling scenario for the next 15 years has undergone a significant change recently. While the 2013 ITRS edition required a continuation of aggressive gate length scaling for at least another 15 years, the 2015 edition of the ITRS suggests a deceleration and eventually a levelling off of gate length scaling and puts more emphasis on alternative options such as pitch scaling to keep Moore's Law alive. In the present paper, future CMOS scaling is discussed in the light of emerging two-dimensional MOSFET channel, in particular two-dimensional TMDs. To this end, the scaling scenarios of the 2013 and 2015 ITRS editions are considered and the scaling potential of TMD MOSFETs is investigated by means of quantum-mechanical device simulations. It is shown that for ultimately scaled MOSFETs as required in the 2013 ITRS, the heavy carrier effective masses of the Mo- and W-based TMDs are beneficial for the suppression of direct source-drain tunneling, while to meet the significantly relaxed scaling targets of the 2016 ITRS heavy-effective-mass channels are not needed.

High-k dielectric Al2O3 nanowire and nanoplate field effect sensors for improved pH sensing

PubMed Central

Reddy, Bobby; Dorvel, Brian R.; Go, Jonghyun; Nair, Pradeep R.; Elibol, Oguz H.; Credo, Grace M.; Daniels, Jonathan S.; Chow, Edmond K. C.; Su, Xing; Varma, Madoo; Alam, Muhammad A.

2011-01-01

Over the last decade, field-effect transistors (FETs) with nanoscale dimensions have emerged as possible label-free biological and chemical sensors capable of highly sensitive detection of various entities and processes. While significant progress has been made towards improving their sensitivity, much is yet to be explored in the study of various critical parameters, such as the choice of a sensing dielectric, the choice of applied front and back gate biases, the design of the device dimensions, and many others. In this work, we present a process to fabricate nanowire and nanoplate FETs with Al2O3 gate dielectrics and we compare these devices with FETs with SiO2 gate dielectrics. The use of a high-k dielectric such as Al2O3 allows for the physical thickness of the gate dielectric to be thicker without losing sensitivity to charge, which then reduces leakage currents and results in devices that are highly robust in fluid. This optimized process results in devices stable for up to 8 h in fluidic environments. Using pH sensing as a benchmark, we show the importance of optimizing the device bias, particularly the back gate bias which modulates the effective channel thickness. We also demonstrate that devices with Al2O3 gate dielectrics exhibit superior sensitivity to pH when compared to devices with SiO2 gate dielectrics. Finally, we show that when the effective electrical silicon channel thickness is on the order of the Debye length, device response to pH is virtually independent of device width. These silicon FET sensors could become integral components of future silicon based Lab on Chip systems. PMID:21203849

High-frequency graphene voltage amplifier.

PubMed

Han, Shu-Jen; Jenkins, Keith A; Valdes Garcia, Alberto; Franklin, Aaron D; Bol, Ageeth A; Haensch, Wilfried

2011-09-14

While graphene transistors have proven capable of delivering gigahertz-range cutoff frequencies, applying the devices to RF circuits has been largely hindered by the lack of current saturation in the zero band gap graphene. Herein, the first high-frequency voltage amplifier is demonstrated using large-area chemical vapor deposition grown graphene. The graphene field-effect transistor (GFET) has a 6-finger gate design with gate length of 500 nm. The graphene common-source amplifier exhibits ∼5 dB low frequency gain with the 3 dB bandwidth greater than 6 GHz. This first AC voltage gain demonstration of a GFET is attributed to the clear current saturation in the device, which is enabled by an ultrathin gate dielectric (4 nm HfO(2)) of the embedded gate structures. The device also shows extrinsic transconductance of 1.2 mS/μm at 1 V drain bias, the highest for graphene FETs using large-scale graphene reported to date.

Impact of SiNx capping on the formation of source/drain contact for In-Ga-Zn-O thin film transistor with self-aligned gate

NASA Astrophysics Data System (ADS)

Oh, Himchan; Pi, Jae-Eun; Hwang, Chi-Sun; Kwon, Oh-Sang

2017-12-01

Self-aligned gate structures are preferred for faster operation and scaling down of thin film transistors by reducing the overlapped region between source/drain and gate electrodes. Doping on source/drain regions is essential to fabricate such a self-aligned gate thin film transistor. For oxide semiconductors such as In-Ga-Zn-O, SiNx capping readily increases their carrier concentration. We report that the SiNx deposition temperature and thickness significantly affect the device properties, including threshold voltage, field effect mobility, and contact resistance. The reason for these variations in device characteristics mainly comes from the extension of the doped region to the gated area after the SiNx capping step. Analyses on capacitance-voltage and transfer length characteristics support this idea.

Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

NASA Astrophysics Data System (ADS)

Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

2018-04-01

In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

Using the Secondary Electrons (SE) of scanning electron microscope with NIST`s MONSEL-II program to obtain improved linewidth measurements and slope angles of line edges on a MMIC GaAs device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sartore, R.G.

1996-12-31

In the evaluation of GaAs devices from the MMIC (Monolithic Microwave Integrated Circuits) program for Army applications, there was a requirement to obtain accurate linewidth measurements on the nominal 0.5 micrometer gate lengths used to fabricate these devices. Preliminary measurements indicated a significant variation (typically 10% to 30% but could be more) in the critical dimensional measurements of the gate length, gate to source distance and gate to drain distance. Passivation introduced a margin of error, which was removed by plasma etching. Additionally, the high aspect ratio (4-5) of the thick gold (Au) conductors also introduced measurement difficulties. The finalmore » measurements were performed were performed after the thick gold conductor was removed and only the barrier metal remained, which was approximately 250 nanometer thick platinum on GaAs substrate. The thickness was measured using the penetration voltage method. Linescan of the secondary electron signal as it scans across the gate is shown in Figure 1. This linescan is an average of 5 linescans in the immediate vicinity to reduce noise levels. A SEM image of the area is shown in Figure 2. To obtain a rough estimate of the slopes of the gate lines at the edges, the sample was tilted to 75 degrees and the image in Figure 3 was obtained. From this figure a rough estimate of the sloped edges, using a protractor, was obtained, approximately 27 degrees, +/-5 degrees.« less

Junctionless tri-gate InGaAs MOSFETs

NASA Astrophysics Data System (ADS)

Zota, Cezar B.; Borg, Mattias; Wernersson, Lars-Erik; Lind, Erik

2017-12-01

We demonstrate and characterize junctionless tri-gate InGaAs MOSFETs, fabricated using a simplified process with gate lengths down to L g = 25 nm at a nanowire dimension of 7 × 16 nm2. These devices use a single 7-nm-thick In0.80Ga0.20As (N D = 1 × 1019 cm-3) layer as both channel and contacts. The devices show SSsat = 76 mV/dec, peak g m = 1.6 mS/µm and I ON = 160 µA/µm (at I OFF = 100 nA/µm and V DD = 0.5 V), the latter which is the highest reported value for a junctionless FET. We also show that device performance is mainly limited by high parasitic access resistance due to the narrow and thin contact layer.

Characteristics of III-V Semiconductor Devices at High Temperature

NASA Technical Reports Server (NTRS)

Simons, Rainee N.; Young, Paul G.; Taub, Susan R.; Alterovitz, Samuel A.

1994-01-01

This paper presents the development of III-V based pseudomorphic high electron mobility transistors (PHEMT's) designed to operate over the temperature range 77 to 473 K (-196 to 200 C). These devices have a pseudomorphic undoped InGaAs channel that is sandwiched between an AlGaAs spacer and a buffer layer; gate widths of 200, 400, 1600, and 3200 micrometers; and a gate length of 2 micrometers. Measurements were performed at both room temperature and 473 K (200 C) and show that the drain current decreases by 30 percent and the gate current increases to about 9 microns A (at a reverse bias of -1.5 V) at the higher temperature. These devices have a maximum DC power dissipation of about 4.5 W and a breakdown voltage of about 16 V.

Experimental studies of MOS inversion and accumulation layers: Quantum mechanical effects and mobility

NASA Astrophysics Data System (ADS)

Chindalore, Gowrishankar L.

The development of fast, multi-functional, and energy efficient integrated circuits, is made possible by aggressively scaling the gate lengths of the MOS devices into the sub-quarter micron regime. However, with the increasing cost of fabrication, there is a strong need for the development of reliable and accurate device simulation capabilities. The development of the theoretical models for simulators is guided by extensive experimental data, which enable an experimental verification of the models, and lead to a better understanding of the underlying physics. This dissertation presents the methodology and the results for one such experimental effort, where two important physical effects in the inversion layer and the accumulation layer of a MOS device, namely, the quantum mechanical (QM) effects and the carrier mobility are investigated. Accordingly, this dissertation has been divided into two parts, with the first part discussing the increase in the threshold voltage and the accumulation electrical oxide thickness due to QM effects. The second part discusses the methodology and the experimental results for the extraction of the majority carrier mobilities in the accumulation layers of a MOSFET. The continued scaling of the MOS gate length requires decreased gate oxide thickness (tox) and increased channel doping (NB) in order to improve device performance while suppressing the short- channel effects. The combination of the two result in large enough transverse electric fields to cause significant quantization of the carriers in the potential well at the Si/SiO2 interface. Hence, compared to the classical calculations (where the QM effects are ignored), the QM effects are found to lead to an increase in the experimental threshold voltage by approximately 100mV, and an overestimation of the physical oxide thickness by approximately 3-4A, in MOSFET devices with a gate oxide thickness and the doping level anticipated for technologies with sub-quarter micron gate lengths. Thus, the experimental results indicate the need for using accurate QM models for simulating sub-quarter micron devices. Carrier mobility is a fundamental semiconductor device transport parameter that has been extensively characterized for both electrons and holes in the silicon bulk and MOS inversion layers. Accumulation layer mobility (μacc) has become increasingly important as the MOS devices have scaled to deep submicron gate lengths, and much effort has been required to achieve increased drive current. However, very little experimental data has been reported for carrier mobility in the MOS accumulation layers (Sun80, Man89). Hence, in this research work, the accumulation layer mobilities were extracted using buried-channel MOSFETs for both the electrons and holes, and for a wide range of doping levels at temperatures ranging from 25C to 150C. The experimental μacc is found to be greater than the corresponding bulk and the inversion layer mobilities, at low to moderate effective fields. However, at very high effective fields, where phonon and surface roughness scattering are dominant, the mobility behavior is found to be very similar to that of the inversion carriers. The extensive set of experimental data will enable the development of accurate local accumulation mobility models for inclusion in 2-D device simulators.

Effect of strained Ge-based NMOSFETs with Ge0.93Si0.07 stressors on device layout

NASA Astrophysics Data System (ADS)

Hsu, Hung-Wen; Lee, Chang-Chun

2017-12-01

This research proposes a germanium (Ge)-based n-channel MOSFET with Ge0.93Si0.07 S/D stressor. A simulation technique is utilized to understand the layout effect of shallow trench isolation (STI) length, gate width, dummy active of diffusion (OD) length, and extended poly width on stress distribution in a channel region. Stress distribution in a channel region was simulated by ANSYS software based on finite element analysis. Furthermore, carrier mobility gain was evaluated by a second-order piezoresistance model. The piezoresistance coefficient of Ge nMOSFET varies from that of Si nMOSFET. The piezoresistance coefficient shows that longitudinal and transverse stresses are the dominant factors affecting the change in electron mobility in the channel region. For Ge-based nMOSFET, longitudinal stress tends to be tensile, whereas transverse stress tends to be compressive. Stress along channel length becomes more tensile when STI length decreases. By contrast, stress along the channel width becomes more compressive when gate width or extended poly width decreases. Electron mobility in Ge-based nMOSFET could be enhanced under the aforementioned conditions. The enhanced electron mobility becomes more significant as the device combines with a contact etching stop layer stressor. Moreover, the mobility can be improved by changing the STI length, gate width, dummy OD length, or extended poly width. This investigation systematically analyzed the relationship between layout factor and stress distribution.

Label Free Detection of Biomolecules Using Charge-Plasma-Based Gate Underlap Dielectric Modulated Junctionless TFET

NASA Astrophysics Data System (ADS)

Wadhwa, Girish; Raj, Balwinder

2018-05-01

Nanoscale devices are emerging as a platform for detecting biomolecules. Various issues were observed during the fabrication process such as random dopant fluctuation and thermal budget. To reduce these issues charge-plasma-based concept is introduced. This paper proposes the implementation of charge-plasma-based gate underlap dielectric modulated junctionless tunnel field effect transistor (DM-JLTFET) for the revelation of biomolecule immobilized in the open cavity gate channel region. In this p+ source and n+ drain regions are introduced by employing different work function over the intrinsic silicon. Also dual material gate architecture is implemented to reduce short channel effect without abandoning any other device characteristic. The sensitivity of biosensor is studied for both the neutral and charge-neutral biomolecules. The effect of device parameters such as channel thickness, cavity length and cavity thickness on drain current have been analyzed through simulations. This paper investigates the performance of charge-plasma-based gate underlap DM-JLTFET for biomolecule sensing applications while varying dielectric constant, charge density at different biasing conditions.

Investigation of Short Channel Effects on Device Performance for 60nm NMOS Transistor

NASA Astrophysics Data System (ADS)

Chinnappan, U.; Sanudin, R.

2017-08-01

In the aggressively scaled complementary metal oxide semiconductor (CMOS) devices, shallower p-n junctions and low sheet resistances are essential for short-channel effect (SCE) control and high device performance. The SCE are attributed to two physical phenomena that are the limitation imposed on electron drift characteristics in channel and the modification of the threshold voltage (Vth) due to the shortening channel length. The decrement of Vth with decrement in gate length is a well-known attribute in SCE known as “threshold voltage roll-off’. In this research, the Technology Computer Aided Design (TCAD) was used to model the SCE phenomenon effect on 60nm n-type metal oxide semiconductor (NMOS) transistor. There are three parameters being investigated, which are the oxide thickness (Tox), gate length (L), acceptor concentration (Na). The simulation data were used to visualise the effect of SCE on the 60nm NMOS transistor. Simulation data suggest that all three parameters have significant effect on Vth, and hence on the transistor performance. It is concluded that there is a trade-off among these three parameters to obtain an optimized transistor performance.

Electro-optical graphene plasmonic logic gates.

PubMed

Ooi, Kelvin J A; Chu, Hong Son; Bai, Ping; Ang, Lay Kee

2014-03-15

The versatile control of graphene's plasmonic modes via an external gate-voltage inspires us to design efficient electro-optical graphene plasmonic logic gates at the midinfrared wavelengths. We show that these devices are superior to the conventional optical logic gates because the former possess cut-off states and interferometric effects. Moreover, the designed six basic logic gates (i.e., NOR/AND, NAND/OR, XNOR/XOR) achieved not only ultracompact size lengths of less than λ/28 with respect to the operating wavelength of 10 μm, but also a minimum extinction ratio as high as 15 dB. These graphene plasmonic logic gates are potential building blocks for future nanoscale midinfrared photonic integrated circuits.

Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices

NASA Astrophysics Data System (ADS)

Yu, Jie; Chen, Kun-ji; Ma, Zhong-yuan; Zhang, Xin-xin; Jiang, Xiao-fan; Wu, Yang-qing; Huang, Xin-fan; Oda, Shunri

2016-09-01

Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V/1 ms, which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8 × 1011/cm2) of Si-NCs. The program/erase (P/E) speed characteristics are almost independent of gate widths and lengths. However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. Furthermore, the data retention characteristic is also independent of the gate area. Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration. Project supported by the State Key Development Program for Basic Research of China (Grant No. 2010CB934402) and the National Natural Science Foundation of China (Grant Nos. 11374153, 61571221, and 61071008).

High performance multi-finger MOSFET on SOI for RF amplifiers

NASA Astrophysics Data System (ADS)

Adhikari, M. Singh; Singh, Y.

2017-10-01

In this paper, we propose structural modifications in the conventional planar metal-oxide-semiconductor field-effect transistor (MOSFET) on silicon-on-insulator by utilizing trenches in the epitaxial layer. The proposed multi-finger MOSFET (MF-MOSFET) has dual vertical-gates placed in separate trenches to form multiple channels in the p-base which carry the drain current in parallel. The proposed device uses TaN as gate electrode and SiO2 as gate dielectric. Simultaneous conduction of multiple channels enhances the drain current (ID) and provides higher transconductance (gm) leading to significant improvement in cut-off frequency (ft). Two-dimensional simulations are performed to evaluate and compare the performance of the MF-MOSFET with the conventional MOSFET. At a gate length of 60 nm, the proposed device provides 4 times higher ID, 3 times improvement in gm and 1.25 times increase in ft with better control over the short channel effects as compared with the conventional device.

Lateral energy band profile modulation in tunnel field effect transistors based on gate structure engineering

NASA Astrophysics Data System (ADS)

Cui, Ning; Liang, Renrong; Wang, Jing; Xu, Jun

2012-06-01

Choosing novel materials and structures is important for enhancing the on-state current in tunnel field-effect transistors (TFETs). In this paper, we reveal that the on-state performance of TFETs is mainly determined by the energy band profile of the channel. According to this interpretation, we present a new concept of energy band profile modulation (BPM) achieved with gate structure engineering. It is believed that this approach can be used to suppress the ambipolar effect. Based on this method, a Si TFET device with a symmetrical tri-material-gate (TMG) structure is proposed. Two-dimensional numerical simulations demonstrated that the special band profile in this device can boost on-state performance, and it also suppresses the off-state current induced by the ambipolar effect. These unique advantages are maintained over a wide range of gate lengths and supply voltages. The BPM concept can serve as a guideline for improving the performance of nanoscale TFET devices.

Efficient III-Nitride MIS-HEMT devices with high-κ gate dielectric for high-power switching boost converter circuits

NASA Astrophysics Data System (ADS)

Mohanbabu, A.; Mohankumar, N.; Godwin Raj, D.; Sarkar, Partha; Saha, Samar K.

2017-03-01

The paper reports the results of a systematic theoretical study on efficient recessed-gate, double-heterostructure, and normally-OFF metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs), HfAlOx/AlGaN on Al2O3 substrate. In device architecture, a thin AlGaN layer is used in the AlGaN graded barrier MIS-HEMTs that offers an excellent enhancement-mode device operation with threshold voltage higher than 5.3 V and drain current above 0.64 A/mm along with high on-current/off-current ratio over 107 and subthreshold slope less than 73 mV/dec. In addition, a high OFF-state breakdown voltage of 1200 V is achieved for a device with a gate-to-drain distance and field-plate length of 15 μm and 5.3 μm, respectively at a drain current of 1 mA/mm with a zero gate bias, and the substrate grounded. The numerical device simulation results show that in comparison to a conventional AlGaN/GaN MIS-HEMT of similar design, a graded barrier MIS-HEMT device exhibits a better interface property, remarkable suppression of leakage current, and a significant improvement of breakdown voltage for HfAlOx gate dielectric. Finally, the benefit of HfAlOx graded-barrier AlGaN MIS-HEMTs based switching devices is evaluated on an ultra-low-loss converter circuit.

Top-gated chemical vapor deposition grown graphene transistors with current saturation.

PubMed

Bai, Jingwei; Liao, Lei; Zhou, Hailong; Cheng, Rui; Liu, Lixin; Huang, Yu; Duan, Xiangfeng

2011-06-08

Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.

High Sensitive pH Sensor Based on AlInN/GaN Heterostructure Transistor.

PubMed

Dong, Yan; Son, Dong-Hyeok; Dai, Quan; Lee, Jun-Hyeok; Won, Chul-Ho; Kim, Jeong-Gil; Chen, Dunjun; Lee, Jung-Hee; Lu, Hai; Zhang, Rong; Zheng, Youdou

2018-04-24

The AlInN/GaN high-electron-mobility-transistor (HEMT) indicates better performances compared with the traditional AlGaN/GaN HEMTs. The present work investigated the pH sensor functionality of an analogous HEMT AlInN/GaN device with an open gate. It was shown that the Al 0.83 In 0.17 N/GaN device demonstrates excellent pH sense functionality in aqueous solutions, exhibiting higher sensitivity (−30.83 μA/pH for AlInN/GaN and −4.6 μA/pH for AlGaN/GaN) and a faster response time, lower degradation and good stability with respect to the AlGaN/GaN device, which is attributed to higher two-dimensional electron gas (2DEG) density and a thinner barrier layer in Al 0.83 In 0.17 N/GaN owning to lattice matching. On the other hand, the open gate geometry was found to affect the pH sensitivity obviously. Properly increasing the width and shortening the length of the open gate area could enhance the sensitivity. However, when the open gate width is too larger or too small, the pH sensitivity would be suppressed conversely. Designing an optimal ratio of the width to the length is important for achieving high sensitivity. This work suggests that the AlInN/GaN-based 2DEG carrier modulated devices would be good candidates for high-performance pH sensors and other related applications.

Two dimensional analytical model for a reconfigurable field effect transistor

NASA Astrophysics Data System (ADS)

Ranjith, R.; Jayachandran, Remya; Suja, K. J.; Komaragiri, Rama S.

2018-02-01

This paper presents two-dimensional potential and current models for a reconfigurable field effect transistor (RFET). Two potential models which describe subthreshold and above-threshold channel potentials are developed by solving two-dimensional (2D) Poisson's equation. In the first potential model, 2D Poisson's equation is solved by considering constant/zero charge density in the channel region of the device to get the subthreshold potential characteristics. In the second model, accumulation charge density is considered to get above-threshold potential characteristics of the device. The proposed models are applicable for the device having lightly doped or intrinsic channel. While obtaining the mathematical model, whole body area is divided into two regions: gated region and un-gated region. The analytical models are compared with technology computer-aided design (TCAD) simulation results and are in complete agreement for different lengths of the gated regions as well as at various supply voltage levels.

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

NASA Astrophysics Data System (ADS)

Liaw, Yue-Gie; Chen, Chii-Wen; Liao, Wen-Shiang; Wang, Mu-Chun; Zou, Xuecheng

2018-05-01

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of Id-Vg characteristics, threshold voltage (Vt), and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance (RSD), channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance (Gm) and drive current.

Gate-Driven Pure Spin Current in Graphene

NASA Astrophysics Data System (ADS)

Lin, Xiaoyang; Su, Li; Si, Zhizhong; Zhang, Youguang; Bournel, Arnaud; Zhang, Yue; Klein, Jacques-Olivier; Fert, Albert; Zhao, Weisheng

2017-09-01

The manipulation of spin current is a promising solution for low-power devices beyond CMOS. However, conventional methods, such as spin-transfer torque or spin-orbit torque for magnetic tunnel junctions, suffer from large power consumption due to frequent spin-charge conversions. An important challenge is, thus, to realize long-distance transport of pure spin current, together with efficient manipulation. Here, the mechanism of gate-driven pure spin current in graphene is presented. Such a mechanism relies on the electrical gating of carrier-density-dependent conductivity and spin-diffusion length in graphene. The gate-driven feature is adopted to realize the pure spin-current demultiplexing operation, which enables gate-controllable distribution of the pure spin current into graphene branches. Compared with the Elliott-Yafet spin-relaxation mechanism, the D'yakonov-Perel spin-relaxation mechanism results in more appreciable demultiplexing performance. The feature of the pure spin-current demultiplexing operation will allow a number of logic functions to be cascaded without spin-charge conversions and open a route for future ultra-low-power devices.

Advanced investigation of two-phase charge-coupled devices

NASA Technical Reports Server (NTRS)

Kosonocky, W. F.; Carnes, J. E.

1973-01-01

The performance of experimental two phase, charge-coupled shift registers constructed using polysilicon gates overlapped by aluminum gates was studied. Shift registers with 64, 128, and 500 stages were built and operated. Devices were operated at the maximum clock frequency of 20 MHz. Loss per transfer of less than .0001 was demonstrated for fat zero operation. The effect upon transfer efficiency of various structural and materials parameters was investigated including substrate orientation, resistivity, and conductivity type; channel width and channel length; and method of channel confinement. Operation of the devices with and without fat zero was studied as well as operation in the complete charge transfer mode and the bias charge, or bucket brigade mode.

Material Synthesis and Device Aspects of Monolayer Tungsten Diselenide.

PubMed

Yao, Zihan; Liu, Jialun; Xu, Kai; Chow, Edmond K C; Zhu, Wenjuan

2018-03-27

In this paper, we investigate the synthesis of WSe 2 by chemical vapor deposition and study the current transport and device scaling of monolayer WSe 2 . We found that the device characteristics of the back-gated WSe 2 transistors with thick oxides are very sensitive to the applied drain bias, especially for transistors in the sub-micrometer regime. The threshold voltage, subthreshold swing, and extracted field-effect mobility vary with the applied drain bias. The output characteristics in the long-channel transistors show ohmic-like behavior, while that in the short-channel transistors show Schottky-like behavior. Our investigation reveals that these phenomena are caused by the drain-induced barrier lowering (short-channel effect). For back-gated WSe 2 transistors with 280 nm oxide, the short-channel effect appears when the channel length is shorter than 0.4 µm. This extremely long electrostatic scaling length is due to the thick back-gate oxides. In addition, we also found that the hydrogen flow rate and the amount of WO 3 precursor play an important role in the morphology of the WSe 2 . The hole mobility of the monolayer WSe 2 is limited by Columbic scattering below 250 K, while it is limited by phonon scattering above 250 K. These findings are very important for the synthesis of WSe 2 and accurate characterization of the electronic devices based on 2D materials.

The GaN trench gate MOSFET with floating islands: High breakdown voltage and improved BFOM

NASA Astrophysics Data System (ADS)

Shen, Lingyan; Müller, Stephan; Cheng, Xinhong; Zhang, Dongliang; Zheng, Li; Xu, Dawei; Yu, Yuehui; Meissner, Elke; Erlbacher, Tobias

2018-02-01

A novel GaN trench gate (TG) MOSFET with P-type floating islands (FLI) in drift region, which can suppress the electric field peak at bottom of gate trench during the blocking state and prevent premature breakdown in gate oxide, is proposed and investigated by TCAD simulations. The influence of thickness, position, doping concentration and length of the FLI on breakdown voltage (BV) and specific on-resistance (Ron_sp) is studied, providing useful guidelines for design of this new type of device. Using optimized parameters for the FLI, GaN FLI TG-MOSFET obtains a BV as high as 2464 V with a Ron_sp of 3.0 mΩ cm2. Compared to the conventional GaN TG-MOSFET with the same structure parameters, the Baliga figure of merit (BFOM) is enhanced by 150%, getting closer to theoretical limit for GaN devices.

Toward spin-based Magneto Logic Gate in Graphene

NASA Astrophysics Data System (ADS)

Wen, Hua; Dery, Hanan; Amamou, Walid; Zhu, Tiancong; Lin, Zhisheng; Shi, Jing; Zutic, Igor; Krivorotov, Ilya; Sham, Lu; Kawakami, Roland

Graphene has emerged as a leading candidate for spintronic applications due to its long spin diffusion length at room temperature. A universal magnetologic gate (MLG) based on spin transport in graphene has been recently proposed as the building block of a logic circuit which could replace the current CMOS technology. This MLG has five ferromagnetic electrodes contacting a graphene channel and can be considered as two three-terminal XOR logic gates. Here we demonstrate this XOR logic gate operation in such a device. This was achieved by systematically tuning the injection current bias to balance the spin polarization efficiency of the two inputs, and offset voltage in the detection circuit to obtain binary outputs. The output is a current which corresponds to different logic states: zero current is logic `0', and nonzero current is logic `1'. We find improved performance could be achieved by reducing device size and optimizing the contacts.

Indium gallium arsenide microwave power transistors

NASA Technical Reports Server (NTRS)

Johnson, Gregory A.; Kapoor, Vik J.; Shokrani, Mohsen; Messick, Louis J.; Nguyen, Richard

1991-01-01

Depletion-mode InGaAs microwave power MISFETs with 1-micron gate lengths and up to 1-mm gate widths have been fabricated using an ion-implantation process. The devices employed a plasma-deposited silicon/silicon dioxide gate insulator. The dc I-V characteristics and RF power performance at 9.7 GHz are presented. The output power, power-added efficiency, and power gain as a function of input power are reported. An output power of 1.07 W with a corresponding power gain and power-added efficiency of 4.3 dB and 38 percent, respectively, was obtained. The large-gate-width devices provided over twice the previously reported output power for InGaAs MISFETs at X-band. In addition, output power stability within 1.2 percent over 24 h of continuous operation was achieved. In addition, a drain current drift of 4 percent over 10,000 sec was obtained.

Asymmetric underlap spacer layer enabled nanoscale double gate MOSFETs for design of ultra-wideband cascode amplifiers

NASA Astrophysics Data System (ADS)

Roy, Debapriya; Biswas, Abhijit

2017-10-01

Using extensive numerical analysis we investigate effects of asymmetric sidewall spacers on various device parameters of 20-nm double gate MOSFETs associated with analog/RF applications. Our studies show that the device with underlap drain-side spacer length LED of 10 nm and source-side spacer length LES of 5 nm shows improvement in terms of the peak value of transconductance efficiency, voltage gain Av, unity-gain cut-off frequency fT and maximum frequency of oscillations fMAX by 8.6%, 51.7%, 5% and 10.3%, respectively compared to the symmetric 5 nm underlap spacer device with HfO2 spacer of dielectric constant k = 22. Additionally, a higher spacer dielectric constant increases the peak Av while decreasing both peak fT and fMAX. The detailed physical insight is exploited to design a cascode amplifier which yields an ultra-wide gain bandwidth of 2.48 THz at LED = 10 nm with a SiO2 spacer.

Monte Carlo simulations of spin transport in a strained nanoscale InGaAs field effect transistor

NASA Astrophysics Data System (ADS)

Thorpe, B.; Kalna, K.; Langbein, F. C.; Schirmer, S.

2017-12-01

Spin-based logic devices could operate at a very high speed with a very low energy consumption and hold significant promise for quantum information processing and metrology. We develop a spintronic device simulator by combining an in-house developed, experimentally verified, ensemble self-consistent Monte Carlo device simulator with spin transport based on a Bloch equation model and a spin-orbit interaction Hamiltonian accounting for Dresselhaus and Rashba couplings. It is employed to simulate a spin field effect transistor operating under externally applied voltages on a gate and a drain. In particular, we simulate electron spin transport in a 25 nm gate length In0.7Ga0.3As metal-oxide-semiconductor field-effect transistor with a CMOS compatible architecture. We observe a non-uniform decay of the net magnetization between the source and the gate and a magnetization recovery effect due to spin refocusing induced by a high electric field between the gate and the drain. We demonstrate a coherent control of the polarization vector of the drain current via the source-drain and gate voltages, and show that the magnetization of the drain current can be increased twofold by the strain induced into the channel.

Voltage tunable plasmon propagation in dual gated bilayer graphene

NASA Astrophysics Data System (ADS)

Farzaneh, Seyed M.; Rakheja, Shaloo

2017-10-01

In this paper, we theoretically investigate plasmon propagation characteristics in AB and AA stacked bilayer graphene (BLG) in the presence of energy asymmetry due to an electrostatic field oriented perpendicularly to the plane of the graphene sheet. We first derive the optical conductivity of BLG using the Kubo formalism incorporating energy asymmetry and finite electron scattering. All results are obtained for room temperature (300 K) operation. By solving Maxwell's equations in a dual gate device setup, we obtain the wavevector of propagating plasmon modes in the transverse electric (TE) and transverse magnetic (TM) directions at terahertz frequencies. The plasmon wavevector allows us to compare the compression factor, propagation length, and the mode confinement of TE and TM plasmon modes in bilayer and monolayer graphene sheets and also to study the impact of material parameters on plasmon characteristics. Our results show that the energy asymmetry can be harnessed to increase the propagation length of TM plasmons in BLG. AA stacked BLG shows a larger increase in the propagation length than AB stacked BLG; conversely, it is very insensitive to the Fermi level variations. Additionally, the dual gate structure allows independent modulation of the energy asymmetry and the Fermi level in BLG, which is advantageous for reconfiguring plasmon characteristics post device fabrication.

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors with atomic layer deposited Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Lin, H. C.; Yang, T.; Sharifi, H.; Kim, S. K.; Xuan, Y.; Shen, T.; Mohammadi, S.; Ye, P. D.

2007-11-01

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with ex situ atomic-layer-deposited Al2O3 as gate dielectrics are studied. Maximum drain currents of 211 and 263mA/mm are obtained for 1μm gate-length Al2O3 MOS-HEMTs with 3 and 6nm thick gate oxide, respectively. C-V characteristic shows negligible hysteresis and frequency dispersion. The gate leakage current density of the MOS-HEMTs is 3-5 orders of magnitude lower than the conventional HEMTs under similar bias conditions. The drain current on-off ratio of MOS-HEMTs is ˜3×103 with a subthreshold swing of 90mV/decade. A maximum cutoff frequency (fT) of 27.3GHz and maximum oscillation frequency (fmax) of 39.9GHz and an effective channel mobility of 4250cm2/Vs are measured for the 1μm gate-length Al2O3 MOS-HEMT with 6nm gate oxide. Hooge's constant measured by low frequency noise spectral density characterization is 3.7×10-5 for the same device.

Design and analysis of 30 nm T-gate InAlN/GaN HEMT with AlGaN back-barrier for high power microwave applications

NASA Astrophysics Data System (ADS)

Murugapandiyan, P.; Ravimaran, S.; William, J.; Meenakshi Sundaram, K.

2017-11-01

In this article, we present the DC and microwave characteristics of a novel 30 nm T-gate InAlN/AlN/GaN HEMT with AlGaN back-barrier. The device structure is simulated by using Synopsys Sentaurus TCAD Drift-Diffusion transport model at room temperature. The device features are heavily doped (n++ GaN) source/drain regions with Si3N4 passivated device surface for reducing the contact resistances and gate capacitances of the device, which uplift the microwave characteristics of the HEMTs. 30 nm gate length D-mode (E-mode) HEMT exhibited a peak drain current density Idmax of 2.3 (2.42) A/mm, transconductance gm of 1.24(1.65) S/mm, current gain cut-off frequency ft of 262 (246) GHz, power gain cut-off frequency fmax of 246(290) GHz and the three terminal off-state breakdown voltage VBR of 40(38) V. The preeminent microwave characteristics with the higher breakdown voltage of the proposed GaN-based HEMT are the expected to be the most optimistic applicant for future high power millimeter wave applications.

Top-gate pentacene-based organic field-effect transistor with amorphous rubrene gate insulator

NASA Astrophysics Data System (ADS)

Hiroki, Mizuha; Maeda, Yasutaka; Ohmi, Shun-ichiro

2018-02-01

The scaling of organic field-effect transistors (OFETs) is necessary for high-density integration and for this, OFETs with a top-gate configuration are required. There have been several reports of damageless lithography processes for organic semiconductor or insulator layers. However, it is still difficult to fabricate scaled OFETs with a top-gate configuration. In this study, the lift-off process and the device characteristics of the OFETs with a top-gate configuration utilizing an amorphous (α) rubrene gate insulator were investigated. We have confirmed that α-rubrene shows an insulating property, and its extracted linear mobility was 2.5 × 10-2 cm2/(V·s). The gate length and width were 10 and 60 µm, respectively. From these results, the OFET with a top-gate configuration utilizing an α-rubrene gate insulator is promising for the high-density integration of scaled OFETs.

A high-performance channel engineered charge-plasma-based MOSFET with high-κ spacer

NASA Astrophysics Data System (ADS)

Shan, Chan; Wang, Ying; Luo, Xin; Bao, Meng-tian; Yu, Cheng-hao; Cao, Fei

2017-12-01

In this paper, the performance of graded channel double-gate MOSFET (GC-DGFET) that utilizes the charge-plasma concept and a high-κ spacer is investigated through 2-D device simulations. The results demonstrate that GC-DGFET with high-κ spacer can effectively improve the ON-state driving current (ION) and reduce the OFF-leakage current (IOFF). We find that reduction of the initial energy barrier between the source and channel is the origin of this ION enhancement. The reason for the IOFF reduction is identified to be the extension of the effective channel length owing to the fringing field via high-κ spacers. Consequently, these devices offer enhanced performance by reducing the total gate-to-gate capacitance (Cgg) and decreasing the intrinsic delay (τ).

Recessed Slant Gate AlGaN/GaN High Electron Mobility Transistors with 20.9 W/mm at 10 GHz

NASA Astrophysics Data System (ADS)

Pei, Yi; Chu, Rongming; Fichtenbaum, Nicholas A.; Chen, Zhen; Brown, David; Shen, Likun; Keller, Stacia; DenBaars, Steven P.; Mishra, Umesh K.

2007-12-01

A recessed slant gate processing has been used in AlGaN/GaN high electron mobility transistors (HEMTs) to mitigate the electric field, minimize the dispersion and increase the breakdown voltage. More than one order of magnitude of decrease in gate leakage has been observed by recessing the slant gate. For a 0.65 μm gate-length device, an extrinsic fT of 18 GHz and extrinsic fMAX of 52 GHz at a drain bias of 25 V were achieved. At 10 GHz, a state-of-the-art power density of 20.9 W/mm, with a power-added efficiency (PAE) of 40% at a drain bias of 83 V, was demonstrated.

Ultraclean single, double, and triple carbon nanotube quantum dots with recessed Re bottom gates

NASA Astrophysics Data System (ADS)

Jung, Minkyung; Schindele, Jens; Nau, Stefan; Weiss, Markus; Baumgartner, Andreas; Schoenenberger, Christian

2014-03-01

Ultraclean carbon nanotubes (CNTs) that are free from disorder provide a promising platform to manipulate single electron or hole spins for quantum information. Here, we demonstrate that ultraclean single, double, and triple quantum dots (QDs) can be formed reliably in a CNT by a straightforward fabrication technique. The QDs are electrostatically defined in the CNT by closely spaced metallic bottom gates deposited in trenches in Silicon dioxide by sputter deposition of Re. The carbon nanotubes are then grown by chemical vapor deposition (CVD) across the trenches and contacted using conventional electron beam lithography. The devices exhibit reproducibly the characteristics of ultraclean QDs behavior even after the subsequent electron beam lithography and chemical processing steps. We demonstrate the high quality using CNT devices with two narrow bottom gates and one global back gate. Tunable by the gate voltages, the device can be operated in four different regimes: i) fully p-type with ballistic transport between the outermost contacts (over a length of 700 nm), ii) clean n-type single QD behavior where a QD can be induced by either the left or the right bottom gate, iii) n-type double QD and iv) triple bipolar QD where the middle QD has opposite doping (p-type). Research at Basel is supported by the NCCR-Nano, NCCR-QIST, ERC project QUEST, and FP7 project SE2ND.

Graphene field effect transistor without an energy gap.

PubMed

Jang, Min Seok; Kim, Hyungjun; Son, Young-Woo; Atwater, Harry A; Goddard, William A

2013-05-28

Graphene is a room temperature ballistic electron conductor and also a very good thermal conductor. Thus, it has been regarded as an ideal material for postsilicon electronic applications. A major complication is that the relativistic massless electrons in pristine graphene exhibit unimpeded Klein tunneling penetration through gate potential barriers. Thus, previous efforts to realize a field effect transistor for logic applications have assumed that introduction of a band gap in graphene is a prerequisite. Unfortunately, extrinsic treatments designed to open a band gap seriously degrade device quality, yielding very low mobility and uncontrolled on/off current ratios. To solve this dilemma, we propose a gating mechanism that leads to a hundredfold enhancement in on/off transmittance ratio for normally incident electrons without any band gap engineering. Thus, our saw-shaped geometry gate potential (in place of the conventional bar-shaped geometry) leads to switching to an off state while retaining the ultrahigh electron mobility in the on state. In particular, we report that an on/off transmittance ratio of 130 is achievable for a sawtooth gate with a gate length of 80 nm. Our switching mechanism demonstrates that intrinsic graphene can be used in designing logic devices without serious alteration of the conventional field effect transistor architecture. This suggests a new variable for the optimization of the graphene-based device--geometry of the gate electrode.

Experimental determination of the impact of polysilicon LER on sub-100-nm transistor performance

NASA Astrophysics Data System (ADS)

Patterson, Kyle; Sturtevant, John L.; Alvis, John R.; Benavides, Nancy; Bonser, Douglas; Cave, Nigel; Nelson-Thomas, Carla; Taylor, William D.; Turnquest, Karen L.

2001-08-01

Photoresist line edge roughness (LER) has long been feared as a potential limitation to the application of various patterning technologies to actual devices. While this concern seems reasonable, experimental verification has proved elusive and thus LER specifications are typically without solid parametric rationale. We report here the transistor device performance impact of deliberate variations of polysilicon gate LER. LER magnitude was attenuated by more than a factor of 5 by altering the photoresist type and thickness, substrate reflectivity, masking approach, and etch process. The polysilicon gate LER for nominally 70 - 150 nm devices was quantified using digital image processing of SEM images, and compared to gate leakage and drive current for variable length and width transistors. With such comparisons, realistic LER specifications can be made for a given transistor. It was found that subtle cosmetic LER differences are often not discernable electrically, thus providing hope that LER will not limit transistor performance as the industry migrates to sub-100 nm patterning.

Design and Performance Analysis of Depletion-Mode InSb Quantum-Well Field-Effect Transistor for Logic Applications

NASA Astrophysics Data System (ADS)

Islam, R.; Uddin, M. M.; Hossain, M. Mofazzal; Matin, M. A.

The design of a 1μm gate length depletion-mode InSb quantum-well field-effect transistor (QWFET) with a 10nm-thick Al2O3 gate dielectric has been optimized using a quantum corrected self-consistent Schrödinger-Poisson (QCSP) and two-dimensional drift-diffusion model. The model predicts a very high electron mobility of 4.42m2V-1s-1 at Vg=0V, a small pinch off gate voltage (Vp) of -0.25V, a maximum extrinsic transconductance (gm) of ˜4.85mS/μm and a drain current density of more than 3.34mA/μm. A short-circuit current-gain cut-off frequency (fT) of 374GHz and a maximum oscillation frequency (fmax) of 645GHz are predicted for the device. These characteristics make the device a potential candidate for low power, high-speed logic electronic device applications.

A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

NASA Astrophysics Data System (ADS)

Priya, Anjali; Mishra, Ram Awadh

2016-04-01

In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.

Characteristics of enhanced-mode AlGaN/GaN MIS HEMTs for millimeter wave applications

NASA Astrophysics Data System (ADS)

Lee, Jong-Min; Ahn, Ho-Kyun; Jung, Hyun-Wook; Shin, Min Jeong; Lim, Jong-Won

2017-09-01

In this paper, an enhanced-mode (E-mode) AlGaN/GaN high electron mobility transistor (HEMT) was developed by using 4-inch GaN HEMT process. We designed and fabricated Emode HEMTs and characterized device performance. To estimate the possibility of application for millimeter wave applications, we focused on the high frequency performance and power characteristics. To shift the threshold voltage of HEMTs we applied the Al2O3 insulator to the gate structure and adopted the gate recess technique. To increase the frequency performance the e-beam lithography technique was used to define the 0.15 um gate length. To evaluate the dc and high frequency performance, electrical characterization was performed. The threshold voltage was measured to be positive value by linear extrapolation from the transfer curve. The device leakage current is comparable to that of the depletion mode device. The current gain cut-off frequency and the maximum oscillation frequency of the E-mode device with a total gate width of 150 um were 55 GHz and 168 GHz, respectively. To confirm the power performance for mm-wave applications the load-pull test was performed. The measured power density of 2.32 W/mm was achieved at frequencies of 28 and 30 GHz.

An AlGaN/GaN high-electron-mobility transistor with an AlN sub-buffer layer

NASA Astrophysics Data System (ADS)

Shealy, J. R.; Kaper, V.; Tilak, V.; Prunty, T.; Smart, J. A.; Green, B.; Eastman, L. F.

2002-04-01

The AlGaN/GaN high-electron-mobility transistor requires a thermally conducting, semi-insulating substrate to achieve the best possible microwave performance. The semi-insulating SiC substrate is currently the best choice for this device technology; however, fringing fields which penetrate the GaN buffer layer at pinch-off introduce significant substrate conduction at modest drain bias if channel electrons are not well confined to the nitride structure. The addition of an insulating AlN sub-buffer on the semi-insulating SiC substrate suppresses this parasitic conduction, which results in dramatic improvements in the AlGaN/GaN transistor performance. A pronounced reduction in both the gate-lag and the gate-leakage current are observed for structures with the AlN sub-buffer layer. These structures operate up to 50 V drain bias under drive, corresponding to a peak voltage of 80 V, for a 0.30 µm gate length device. The devices have achieved high-efficiency operation at 10 GHz (>70% power-added efficiency in class AB mode at 15 V drain bias) and the highest output power density observed thus far (11.2 W mm-1). Large-periphery devices (1.5 mm gate width) deliver 10 W (continuous wave) of maximum saturated output power at 10 GHz. The growth, processing, and performance of these devices are briefly reviewed.

An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models

NASA Astrophysics Data System (ADS)

Pereira, A. S. N.; de Streel, G.; Planes, N.; Haond, M.; Giacomini, R.; Flandre, D.; Kilchytska, V.

2017-02-01

The Drain Induced Barrier Lowering (DIBL) behavior in Ultra-Thin Body and Buried oxide (UTBB) transistors is investigated in details in the temperature range up to 150 °C, for the first time to the best of our knowledge. The analysis is based on experimental data, physical device simulation, compact model (SPICE) simulation and previously published models. Contrary to MASTAR prediction, experiments reveal DIBL increase with temperature. Physical device simulations of different thin-film fully-depleted (FD) devices outline the generality of such behavior. SPICE simulations, with UTSOI DK2.4 model, only partially adhere to experimental trends. Several analytic models available in the literature are assessed for DIBL vs. temperature prediction. Although being the closest to experiments, Fasarakis' model overestimates DIBL(T) dependence for shortest devices and underestimates it for upsized gate lengths frequently used in ultra-low-voltage (ULV) applications. This model is improved in our work, by introducing a temperature-dependent inversion charge at threshold. The improved model shows very good agreement with experimental data, with high gain in precision for the gate lengths under test.

Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET.

PubMed

Dutta, Sangya; Kumar, Vinay; Shukla, Aditya; Mohapatra, Nihar R; Ganguly, Udayan

2017-08-15

Neuro-biology inspired Spiking Neural Network (SNN) enables efficient learning and recognition tasks. To achieve a large scale network akin to biology, a power and area efficient electronic neuron is essential. Earlier, we had demonstrated an LIF neuron by a novel 4-terminal impact ionization based n+/p/n+ with an extended gate (gated-INPN) device by physics simulation. Excellent improvement in area and power compared to conventional analog circuit implementations was observed. In this paper, we propose and experimentally demonstrate a compact conventional 3-terminal partially depleted (PD) SOI- MOSFET (100 nm gate length) to replace the 4-terminal gated-INPN device. Impact ionization (II) induced floating body effect in SOI-MOSFET is used to capture LIF neuron behavior to demonstrate spiking frequency dependence on input. MHz operation enables attractive hardware acceleration compared to biology. Overall, conventional PD-SOI-CMOS technology enables very-large-scale-integration (VLSI) which is essential for biology scale (~10 11 neuron based) large neural networks.

Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around

NASA Astrophysics Data System (ADS)

Guerfi, Youssouf; Larrieu, Guilhem

2016-04-01

Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires' suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-scale process of GAA vertical silicon nanowire (VNW) MOSFETs is presented. A top-down approach is adopted for the realization of VNWs with an optimum reproducibility followed by thin layer engineering at nanoscale. Good overall electrical performances were obtained, with excellent electrostatic behavior (a subthreshold slope (SS) of 95 mV/dec and a drain induced barrier lowering (DIBL) of 25 mV/V) for a 15-nm gate length. Finally, a first demonstration of dual integration of n-type and p-type VNW transistors for the realization of CMOS inverter is proposed.

Current conduction in junction gate field effect transistors. Ph.D. Thesis

NASA Technical Reports Server (NTRS)

Kim, C.

1970-01-01

The internal physical mechanism that governs the current conduction in junction-gate field effect transistors is studied. A numerical method of analyzing the devices with different length-to-width ratios and doping profiles is developed. This method takes into account the two dimensional character of the electric field and the field dependent mobility. Application of the method to various device models shows that the channel width and the carrier concentration in the conductive channel decrease with increasing drain-to-source voltage for conventional devices. It also shows larger differential drain conductances for shorter devices when the drift velocity is not saturated. The interaction of the source and the drain gives the carrier accumulation in the channel which leads to the space-charge-limited current flow. The important parameters for the space-charge-limited current flow are found to be the L/L sub DE ratio and the crossover voltage.

High performance InP JFETs grown by MOCVD using tertiarybutylphosphine

NASA Astrophysics Data System (ADS)

Hashemi, M. M.; Shealy, J. B.; Corvini, P. J.; Denbaars, S. P.; Mishra, U. K.

1994-02-01

Indium phosphide channel junction field effect transistors were fabricated by metalorganic chemical vapor deposition using tertiarybulylphosphine (TBP) as the alternative source for phosphine. At growth temperatures of 600°C, InP with specular surface morphology and mobilities as high as 61000 cm2/V s at 77Khas been achieved using trimethylindium and TBP. To improve device isolation, pinch-off characteristics, and output transconductance, we employ a high resistivity (1 × 108 Ω-cm) semi-insulating InP buffer layer using ferrocene as the Fe-dopant. Devices with gate lengths of 1 urn exhibit very high extrinsic transconductance of 130 mS/mm, gate-drain breakdown voltage exceeding 20 V, maximum current density of >450 mA/mm with record high fT and fmax of 15 GHz and 35 GHz, respectively. These results indicate: that InP JFETs are promising electronic devices for microwave power amplification, and that TBP is capable of device quality materials.

A theoretical approach to study the optical sensitivity of a MESFET

NASA Astrophysics Data System (ADS)

Dutta, Sutanu

2018-05-01

A theoretical model to study the optical sensitivity of a metal-semiconductor field effect transistor has been proposed for a relatively high drain field. An analytical expression of drain current of the device has been derived for a MESFET under optical illumination considering field dependent mobility of electrons across the channel. The variation of drain current with and without optical illumination has been studied with drain and gate voltages. The optical sensitivity of the drain current has been studied for different biasing conditions and gate lengths. In addition, the shift in threshold voltage of a MESFET under optical illumination is determined and optical sensitivity of the device in terms of its threshold voltage has been studied.

Electrical Characteristics of Organic Field Effect Transistor Formed by Gas Treatment of High-k Al2O3 at Low Temperature

NASA Astrophysics Data System (ADS)

Lee, Sunwoo; Yoon, Seungki; Park, In-Sung; Ahn, Jinho

2009-04-01

We studied the electrical characteristics of an organic field effect transistor (OFET) formed by the hydrogen (H2) and nitrogen (N2) mixed gas treatment of a gate dielectric layer. We also investigated how device mobility is related to the length and width variations of the channel. Aluminum oxide (Al2O3) was used as the gate dielectric layer. After the treatment, the mobility and subthreshold swing were observed to be significantly improved by the decreased hole carrier localization at the interfacial layer between the gate oxide and pentacene channel layers. H2 gas plays an important role in removing the defects of the gate oxide layer at temperatures below 100 °C.

Scaling effects of a graphene field effect transistor for radiation detection

NASA Astrophysics Data System (ADS)

Shollar, Zachary Frank

Radiation detectors based on graphene is a burgeoning research topic within the immense field of graphene research. Although papers continue to parse out their mysteries, the devices remain simplistic and small. New fabrication techniques have allowed for millimeter scale and larger monolayer graphene sheets to be grown with increasingly better quality. It is the goal of this thesis to investigate the scaling effects of millimeter scale graphene for radiation detection purposes. To this end, chemical vapor deposition grown monolayer graphene was purchased and transferred to Si/SiO2 substrates. The devices were patterned into simple rectangular strips varying in size from 3000 x 500 mum, 600 x 100 mum, 300 x 50 mum, and 60 x 11 mum. Four metal contacts were patterned onto each strip for electrical characterization. Two probe resistance measurements were performed on all four sizes, at three different lengths along the graphene. Using the field effect, the graphene resistance response was measured at 0 V back-gate voltage to obtain graphene resistivity on SiO2, which showed an increase in resistivity as the graphene strip size increased. Further, the response was measured for varying back-gate sweep ranges and speeds. This lead to the conclusion that strong p-doping was inherent in the graphene strips, as evidenced by charge neutral points located above +50 V. Strong hysteresis observed in those tests alluded to trapped charge having a major effect on voltage sweeps. Mobility values for the graphene strips were extracted from the back-gate voltage sweeps and fixed gate voltage stabilization curves. Mobility values overall were less than 400 cm2 V-1 s-1, and showed a modest increase in mobility as graphene length increased. Lastly, the largest graphene strip had a light response and radiation response measured. Light response showed a dependence on gate voltage magnitude that favored positive gate voltages, on an n-type Silicon substrate. A saturation effect above +15 V seemed apparent with a resistance increase of only 0.61% +/- 0.062% for +15 V to 0.69% +/- 0.097% for the +50 V back-gate. Response of the largest graphene strip size to forward facing alpha irradiation showed a modest 0.32% +/- 0.082% increase in response, for a -15 V back- gate. Overall, millimeter scale graphene field effect devices showed a light and radiation response, proving their viability. However, results showed fabricated samples had numerous defects and were far from pristine. Fabrication of pristine graphene strips at millimeter scales is of concern. Further work into large scale GFET patterning, testing at more length and width dimensions, and further investigating metal contact and carrier transport in millimeter scales is needed.

Review on analog/radio frequency performance of advanced silicon MOSFETs

NASA Astrophysics Data System (ADS)

Passi, Vikram; Raskin, Jean-Pierre

2017-12-01

Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of drain-induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.

Slowing DNA Translocation in a Nanofluidic Field-Effect Transistor.

PubMed

Liu, Yifan; Yobas, Levent

2016-04-26

Here, we present an experimental demonstration of slowing DNA translocation across a nanochannel by modulating the channel surface charge through an externally applied gate bias. The experiments were performed on a nanofluidic field-effect transistor, which is a monolithic integrated platform featuring a 50 nm-diameter in-plane alumina nanocapillary whose entire length is surrounded by a gate electrode. The field-effect transistor behavior was validated on the gating of ionic conductance and protein transport. The gating of DNA translocation was subsequently studied by measuring discrete current dips associated with single λ-DNA translocation events under a source-to-drain bias of 1 V. The translocation speeds under various gate bias conditions were extracted by fitting event histograms of the measured translocation time to the first passage time distributions obtained from a simple 1D biased diffusion model. A positive gate bias was observed to slow the translocation of single λ-DNA chains markedly; the translocation speed was reduced by an order of magnitude from 18.4 mm/s obtained under a floating gate down to 1.33 mm/s under a positive gate bias of 9 V. Therefore, a dynamic and flexible regulation of the DNA translocation speed, which is vital for single-molecule sequencing, can be achieved on this device by simply tuning the gate bias. The device is realized in a conventional semiconductor microfabrication process without the requirement of advanced lithography, and can be potentially further developed into a compact electronic single-molecule sequencer.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mamaluy, Denis; Gao, Xujiao; Tierney, Brian David

We created a highly efficient, universal 3D quant um transport simulator. We demonstrated that the simulator scales linearly - both with the problem size (N) and number of CPUs, which presents an important break-through in the field of computational nanoelectronics. It allowed us, for the first time, to accurately simulate and optim ize a large number of realistic nanodevices in a much shorter time, when compared to other methods/codes such as RGF[%7EN 2.333 ]/KNIT, KWANT, and QTBM[%7EN 3 ]/NEMO5. In order to determine the best-in-class for different beyond-CMOS paradigms, we performed rigorous device optimization for high-performance logic devices at 6-,more » 5- and 4-nm gate lengths. We have discovered that there exists a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs). We have found that, at room temperatures, all FETs, irre spective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths.« less

Performance evaluation of bottom gate ZnO based thin film transistors with different W/L ratios for UV sensing

NASA Astrophysics Data System (ADS)

Varma, Tarun; Periasamy, C.; Boolchandani, Dharmendar

2018-02-01

In this paper, we report the simulation, fabrication and characterisation of UV photo-detectors with bottom gate ZnO Thin Film Transistors (TFTs), grown on silicon at room temperature using RF magnetron sputtering process. The static performance of these detectors have been explored by varying the channel lengths (6 μm and 12 μm). The fabricated devices show low leakage currents with threshold voltages of 1.18 & 2.33 V, sub-threshold swings of 13.5 & 12.8 V/dec for channel lengths of 6 μm and 12 μm TFT, respectively. They also exhibit superior electrical characteristics with an ON-OFF ratio of the order of 3. The detector was also tested for device stability, with the transfer characteristics of the TFTs, which got deteriorated mainly by the negative bias-stress. The TFTs were further tested for UV detector applications and found to exhibit good photo-response.

Distributed multiport memory architecture

NASA Technical Reports Server (NTRS)

Kohl, W. H. (Inventor)

1983-01-01

A multiport memory architecture is diclosed for each of a plurality of task centers connected to a command and data bus. Each task center, includes a memory and a plurality of devices which request direct memory access as needed. The memory includes an internal data bus and an internal address bus to which the devices are connected, and direct timing and control logic comprised of a 10-state ring counter for allocating memory devices by enabling AND gates connected to the request signal lines of the devices. The outputs of AND gates connected to the same device are combined by OR gates to form an acknowledgement signal that enables the devices to address the memory during the next clock period. The length of the ring counter may be effectively lengthened to any multiple of ten to allow for more direct memory access intervals in one repetitive sequence. One device is a network bus adapter which serially shifts onto the command and data bus, a data word (8 bits plus control and parity bits) during the next ten direct memory access intervals after it has been granted access. The NBA is therefore allocated only one access in every ten intervals, which is a predetermined interval for all centers. The ring counters of all centers are periodically synchronized by DMA SYNC signal to assure that all NBAs be able to function in synchronism for data transfer from one center to another.

A two-dimensional (2D) analytical subthreshold swing and transconductance model of underlap dual-material double-gate (DMDG) MOSFET for analog/RF applications

NASA Astrophysics Data System (ADS)

Narendar, Vadthiya; Rai, Saurabh; Tiwari, Siddharth; Mishra, R. A.

2016-12-01

The double-gate (DG) metal-oxide-semiconductor field effect transistors (MOSFETs) are the choice of technology in sub -100 nm regime of leading microelectronics industry. To enhance the analog and RF performance of DG MOSFET, an underlap dual-material (DM) DG MOSFET device structure has been considered because, it has the advantages of both underlap as well as that of dual-material gate (DMG). A 2D analytical surface potential, subthreshold current, subthreshold swing as well as transconductance modelling of underlap DMDG MOSFET has been done by solving the Poisson's equation. It has also been found that, numerically simulated data approves the analytically modelled data with commendable accuracy. As underlap length (Lun) increases, a substantial reduction of subthreshold current due to enhanced gate control over channel regime is observed. DMG structure facilitates to improve the average velocity of carriers which leads to superior drive current of the device. The underlap DMDG MOSFET device structure demonstrates an ameliorated subthreshold characteristic. The analog figure of merits (FOMs) such as transconductance (gm), transconductance generation factor (TGF), output conductance (gd), early voltage (VEA), intrinsic gain (AV) and RF FOMs namely cut-off frequency (fT), gain frequency product (GFP), transconductance frequency product (TFP) and gain transconductance frequency product (GTFP) have been evaluated. The aforesaid analysis revels that, the device is best suited for communication related Analog/RF applications.

Improved scatterer property estimates from ultrasound backscatter for small gate lengths using a gate-edge correction factor

NASA Astrophysics Data System (ADS)

Oelze, Michael L.; O'Brien, William D.

2004-11-01

Backscattered rf signals used to construct conventional ultrasound B-mode images contain frequency-dependent information that can be examined through the backscattered power spectrum. The backscattered power spectrum is found by taking the magnitude squared of the Fourier transform of a gated time segment corresponding to a region in the scattering volume. When a time segment is gated, the edges of the gated regions change the frequency content of the backscattered power spectrum due to truncating of the waveform. Tapered windows, like the Hanning window, and longer gate lengths reduce the relative contribution of the gate-edge effects. A new gate-edge correction factor was developed that partially accounted for the edge effects. The gate-edge correction factor gave more accurate estimates of scatterer properties at small gate lengths compared to conventional windowing functions. The gate-edge correction factor gave estimates of scatterer properties within 5% of actual values at very small gate lengths (less than 5 spatial pulse lengths) in both simulations and from measurements on glass-bead phantoms. While the gate-edge correction factor gave higher accuracy of estimates at smaller gate lengths, the precision of estimates was not improved at small gate lengths over conventional windowing functions. .

Design Architecture of field-effect transistor with back gate electrode for biosensor application

NASA Astrophysics Data System (ADS)

Fathil, M. F. M.; Arshad, M. K. Md.; Hashim, U.; Ruslinda, A. R.; Gopinath, Subash C. B.; M. Nuzaihan M., N.; Ayub, R. M.; Adzhri, R.; Zaki, M.; Azman, A. H.

2016-07-01

This paper presents the preparation method of photolithography chrome mask design used in fabrication process of field-effect transistor with back gate biasing based biosensor. Initially, the chrome masks are designed by studying the process flow of the biosensor fabrication, followed by drawing of the actual chrome mask using the AutoCAD software. The overall width and length of the device is optimized at 16 mm and 16 mm, respectively. Fabrication processes of the biosensor required five chrome masks, which included source and drain formation mask, the back gate area formation mask, electrode formation mask, front gate area formation mask, and passivation area formation mask. The complete chrome masks design will be sent for chrome mask fabrication and for future use in biosensor fabrication.

High kappa Dielectrics on InGaAs and GaN - Growth, Interfacial Structural Studies, and Surface Fermi Level Unpinning

DTIC Science & Technology

2011-04-20

ALD-Al2O3 and in-situ MBE-Al2O3/ Ga2O3 (Gd2O3) [GGO] as the gate dielectrics. The advances of the InGaAs MOSFETs achieved will enable future CMOS...and GaN MOSFETs:  High-performance self-aligned inversion-channel In0.53Ga0.47As and In0.75Ga0.25As MOSFET’s with Al2O3/ Ga2O3 (Gd2O3) as gate... Ga2O3 (Gd2O3) as gate dielectrics Key accomplishments in devices of 1m gate length: High drain current of 1.23 mA/m High transcoductance of 714

Fabrication of 80-nm T-gate high indium In0.7Ga0.3As/In0.6Ga0.4As composite channels mHEMT on GaAs substrate with simple technological process

NASA Astrophysics Data System (ADS)

Xian, Ji; Xiaodong, Zhang; Weihua, Kang; Zhili, Zhang; Jiahui, Zhou; Wenjun, Xu; Qi, Li; Gongli, Xiao; Zhijun, Yin; Yong, Cai; Baoshun, Zhang; Haiou, Li

2016-02-01

An 80-nm gate length metamorphic high electron mobility transistor (mHEMT) on a GaAs substrate with high indium composite compound-channels In0.7Ga0.3 As/In0.6Ga0.4 As and an optimized grade buffer scheme is presented. High 2-DEG Hall mobility values of 10200 cm2/(V·s) and a sheet density of 3.5 × 1012 cm-2 at 300 K have been achieved. The device's T-shaped gate was made by utilizing a simple three layers electron beam resist, instead of employing a passivation layer for the T-share gate, which is beneficial to decreasing parasitic capacitance and parasitic resistance of the gate and simplifying the device manufacturing process. The ohmic contact resistance Rc is 0.2 ω·mm when using the same metal system with the gate (Pt/Ti/Pt/Au), which reduces the manufacturing cycle of the device. The mHEMT device demonstrates excellent DC and RF characteristics. The peak extrinsic transconductance of 1.1 S/mm and the maximum drain current density of 0.86 A/mm are obtained. The unity current gain cut-off frequency (fT) and the maximum oscillation frequency (fmax) are 246 and 301 GHz, respectively. Project supported by the Key Laboratory of Nano-Devices and Applications, Nano-Fabrication Facility of SINANO, Chinese Academy of Sciences, the National Natural Science Foundation of China (Nos. 61274077, 61474031, 61464003), the Guangxi Natural Science Foundation (Nos. 2013GXNSFGA019003, 2013GXNSFAA019335), the National Basic Research Program of China (Nos. 2011CBA00605, 2010CB327501), the Project (No. 9140C140101140C14069), and the Innovation Project of GUET Graduate Education (Nos. GDYCSZ201448, GDYCSZ201449, YJCXS201529).

Gate-driven pure spin current in graphene

NASA Astrophysics Data System (ADS)

Lin, Xiaoyang; Su, Li; Zhang, Youguang; Bournel, Arnaud; Zhang, Yue; Klein, Jacques-Olivier; Zhao, Weisheng; Fert, Albert

An important challenge of spin current based devices is to realize long-distance transport and efficient manipulation of pure spin current without frequent spin-charge conversions. Here, the mechanism of gate-driven pure spin current in graphene is presented. Such a mechanism relies on the electrical gating of conductivity and spin diffusion length in graphene. The gate-driven feature is adopted to realize the pure spin current demultiplexing operation, which enables gate-controllable distribution of the pure spin current into graphene branches. Compared with Elliot-Yafet spin relaxation mechanism, D'yakonov-Perel spin relaxation mechanism results in more appreciable demultiplexing performance, which also implies a feasible strategy to characterize the spin relaxation mechanisms. The unique feature of the pure spin current demultiplexing operation would pave a way for ultra-low power spin logic beyond CMOS. Supported by the NSFC (61627813, 51602013) and the 111 project (B16001).

Design architecture of double spiral interdigitated electrode with back gate electrode for biosensor application

NASA Astrophysics Data System (ADS)

Fathil, M. F. M.; Arshad, M. K. Md.; Hashim, U.; Ruslinda, A. R.; Gopinath, Subash C. B.; M. Nuzaihan M., N.; Ayub, R. M.; Adzhri, R.; Zaki, M.; Azman, A. H.

2016-07-01

This paper presents the preparation method of photolithography chrome mask design used in fabrication process of double spiral interdigitated electrode with back gate biasing based biosensor. By learning the fabrication process flow of the biosensor, the chrome masks are designed through drawing using the AutoCAD software. The overall width and length of the device is optimized at 7.0 mm and 10.0 mm, respectively. Fabrication processes of the biosensor required three chrome masks, which included back gate opening, spiral IDE formation, and passivation area formation. The complete chrome masks design will be sent for chrome mask fabrication and for future use in biosensor fabrication.

Development of a Self Aligned CMOS Process for Flash Lamp Annealed Polycrystalline Silicon TFTs

NASA Astrophysics Data System (ADS)

Bischoff, Paul

The emerging active matrix liquid crystal (AMLCD) display market requires a high performing semiconductor material to meet rising standards of operation. Currently amorphous silicon (a-Si) dominates the market but it does not have the required mobility for it to be used in AMLCD manufacturing. Other materials have been developed including crystallizing a-Si into poly-silicon. A new approach to crystallization through the use of flash lamp annealing (FLA) decreases manufacturing time and greatly improves carrier mobility. Previous work on FLA silicon for the use in CMOS transistors revealed significant lateral dopant diffusion into the channel greatly increasing the minimum channel length required for a working device. This was further confounded by the gate overlap due to misalignment during lithography patterning steps. Through the use of furnace dopant activation instead of FLA dopant activation and a self aligned gate the minimum size transistor can be greatly reduced. A new lithography mask and process flow were developed for the furnace annealing and self aligned gate. Fabrication of the self aligned devices resulted in oxidation of the Molybdenum self aligned gate. Further development is needed to successfully manufacture these devices. Non-self aligned transistors were made simultaneously with self aligned devices and used the furnace activation. These devices showed an increase in sheet resistance from 250 O to 800 O and lower mobility from 380 to 40.2 V/cm2s. The lower mobility can be contributed to an increase in implanted trap density indicating furnace annealing is an inferior activation method over FLA. The minimum transistor size however was reduced from 20 to 5 mum. With improvements in the self aligned process high performing small devices can be manufactured.

Tunable SnSe2 /WSe2 Heterostructure Tunneling Field Effect Transistor.

PubMed

Yan, Xiao; Liu, Chunsen; Li, Chao; Bao, Wenzhong; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2017-09-01

The burgeoning 2D semiconductors can maintain excellent device electrostatics with an ultranarrow channel length and can realize tunneling by electrostatic gating to avoid deprivation of band-edge sharpness resulting from chemical doping, which make them perfect candidates for tunneling field effect transistors. Here this study presents SnSe 2 /WSe 2 van der Waals heterostructures with SnSe 2 as the p-layer and WSe 2 as the n-layer. The energy band alignment changes from a staggered gap band offset (type-II) to a broken gap (type-III) when changing the negative back-gate voltage to positive, resulting in the device operating as a rectifier diode (rectification ratio ~10 4 ) or an n-type tunneling field effect transistor, respectively. A steep average subthreshold swing of 80 mV dec -1 for exceeding two decades of drain current with a minimum of 37 mV dec -1 at room temperature is observed, and an evident trend toward negative differential resistance is also accomplished for the tunneling field effect transistor due to the high gate efficiency of 0.36 for single gate devices. The I ON /I OFF ratio of the transfer characteristics is >10 6 , accompanying a high ON current >10 -5 A. This work presents original phenomena of multilayer 2D van der Waals heterostructures which can be applied to low-power consumption devices. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Ballistic interference in ultraclean suspended monolayer graphene

NASA Astrophysics Data System (ADS)

Schonenberger, Christian; Rickhaus, Peter; Maurand, Romain; Makk, Peter; Hess, Samuel; Tovari, Endre; Weiss, Markus; Liu, Ming-Hao; Richter, Klaus

2014-03-01

We have developed a versatile technology that allows to suspend graphene and complement it with arbitrary bottom and top-gate structures. Using current annealing we demonstrate exceptional high mobililties in monolayer graphene approaching 100 m2/Vs. These suspended devices are ballistic over micrometer length scales and display intriguing interference patterns in the electrical con-ductance when different gate potentials are applied. Specifically we will discuss different types of Fabry-Perot resonances that appear in different gate voltage regimes of ballistic pn devices. We will go beyond our recent publication and also show electric transport measurements in magnetic field, where intriguing features appear in the intermediate field range in between the low-field Klein-tunneling regime and the quantum Hall regime. We observe a large number of non-dispersing states which might be due to so-called snake states confined to the pn interface. We will also discuss first results on electron guiding in ultraclean monolayer graphene. We acknowledge funding from the Swiss NFS and the EC.

Electrical properties of AlGaN/GaN HEMTs in stretchable geometries

NASA Astrophysics Data System (ADS)

Tompkins, R. P.; Mahaboob, I.; Shahedipour-Sandvik, F.; Lazarus, N.

2017-10-01

Many biological materials are naturally soft and stretchable, far more so than crystalline semiconductors. Creating systems that can be placed directly on a surface such as human skin has required new approaches in electronic device design and materials, a field known as stretchable electronics. One common method for fabricating a highly brittle semiconductor device able to survive tens of percent strain is to incorporate stress relief structures ('waves'). Although the mechanical advantages of this approach are well known, the effects on the electrical behavior of a device such as a transistor compared to a more traditional geometry have not been studied. Here, AlGaN/GaN high electron mobility transistors (HEMTs) grown on rigid sapphire substrates were fabricated in a common wavy geometry, a sinusoid, with dimensions similar to those used in stretchable electronics. The study analyzes control parameters available to the designer including gate location along the sinusoid, angle the source-drain contacts make with the gate, as well as variation of the gate length at the peak of the sinusoid. Common electrical parameters such as saturation current density, threshold voltage, and transconductance were compared between the sinusoidal and conventional straight geometries and results found to fall to within experimental uncertainty, suggesting shifting to a stretchable geometry is possible without appreciably degrading semiconductor device performance.

Control of short-channel effects in InAlN/GaN high-electron mobility transistors using graded AlGaN buffer

NASA Astrophysics Data System (ADS)

Han, Tiecheng; Zhao, Hongdong; Peng, Xiaocan; Li, Yuhai

2018-04-01

A graded AlGaN buffer is designed to realize the p-type buffer by inducing polarization-doping holes. Based on the two-dimensional device simulator, the effect of the graded AlGaN buffer on the direct-current (DC) and radio-frequency (RF) performance of short-gate InAlN/GaN high-electron mobility transistors (HEMTs) are investigated, theoretically. Compared to standard HEMT, an enhancement of electron confinement and a good control of short-channel effect (SCEs) are demonstrated in the graded AlGaN buffer HEMT. Accordingly, the pinched-off behavior and the ability of gate modulation are significantly improved. And, no serious SCEs are observed in the graded AlGaN buffer HEMT with an aspect ratio (LG/tch) of about 6.7, much lower than that of the standard HEMT (LG/tch = 13). In addition, for a 70-nm gate length, a peak current gain cutoff frequency (fT) of 171 GHz and power gain cutoff frequency (fmax) of 191 GHz are obtained in the grade buffer HEMT, which are higher than those of the standard one with the same gate length.

Noise characterization of enhancement-mode AlGaN graded barrier MIS-HEMT devices

NASA Astrophysics Data System (ADS)

Mohanbabu, A.; Saravana Kumar, R.; Mohankumar, N.

2017-12-01

This paper reports a systematic theoretical study on the microwave noise performance of graded AlGaN/GaN metal-insulator semiconductor high-electron mobility transistors (MIS-HEMTs) built on an Al2O3 substrate. The HfAlOx/AlGaN/GaN MIS-HEMT devices designed for this study show an outstanding small signal analog/RF and noise performance. The results on 1 μm gate length device show an enhancement mode operation with threshold voltage, VT = + 5.3 V, low drain leakage current, Ids,LL in the order of 1 × 10-9 A/mm along with high current gain cut-off frequency, fT of 17 GHz and maximum oscillation frequency fmax of 47 GHz at Vds = 10 V. The device Isbnd V and low-frequency noise estimation of the gate and drain noise spectral density and their correlation are evaluated using a Green's function method under different biasing conditions. The devices show a minimum noise figure (NFmin) of 1.053 dB in combination with equivalent noise resistance (Rn) of 23 Ω at 17 GHz, at Vgs = 6 V and Vds = 5 V which is relatively low and is suitable for broad-band low-noise amplifiers. This study shows that the graded AlGaN MIS-HEMT with HfAlOX gate insulator is appropriate for application requiring high-power and low-noise.

Study of G-S/D underlap for enhanced analog performance and RF/circuit analysis of UTB InAs-OI-Si MOSFET using NQS small signal model

NASA Astrophysics Data System (ADS)

Maity, Subir Kumar; Pandit, Soumya

2017-01-01

InGaAs (and its variant) appears to be a promising channel material for high-performance, low-power scaled CMOS applications due to its excellent carrier transport properties. However, MOS transistors made of this suffer from poor electrostatic integrity. In this work, we consider an underlap ultra thin body (UTB) InAs-on-Insulator n-channel MOS transistor, and study the effect of varying the gate-source/drain (G-S/D) underlap length on the analog performance of the device with the help of technology computer-aided design (TCAD) simulation, calibrated with Schrodinger-Poisson solver and experimental results. The underlap technique improves the gate electrostatic integrity which in turn improves the analog performance. We develop a non-quasi-static (NQS) small signal equivalent circuit model of the device which is used for study of the RF performance. With increase of the underlap length, the unity gain cut-off frequency degrades and the maximum oscillation frequency improves beyond a certain value of the underlap length. We further study the gain-frequency response of a common source amplifier using the NQS model, through SPICE simulation and observe that the voltage gain and the gain bandwidth improves.

Coaxially gated in-wire thin-film transistors made by template assembly.

PubMed

Kovtyukhova, Nina I; Kelley, Brian K; Mallouk, Thomas E

2004-10-13

Nanowire field effect transistors were prepared by a wet chemical template replication method using anodic aluminum oxide membranes. The membrane pores were first lined with a thin SiO2 layer by the surface sol-gel method. Au, CdS (or CdSe), and Au wire segments were then sequentially electrodeposited within the pores, and the resulting nanowires were released by dissolution of the membrane. Electrofluidic alignment of these nanowires between source and drain leads and evaporation of gold over the central CdS (CdSe) stripe affords a "wrap-around gate" structure. At VDS = -2 V, the Au/CdS/Au devices had an ON/OFF current ratio of 103, a threshold voltage of 2.4 V, and a subthreshold slope of 2.2 V/decade. A 3-fold decrease in the subthreshold slope relative to that of planar nanocrystalline CdSe devices can be attributed to coaxial gating. The control of dimensions afforded by template synthesis should make it possible to reduce the gate dielectric thickness, channel length, and diameter of the semiconductor segment to sublithographic dimensions while retaining the simplicity of the wet chemical synthetic method.

Nanometer-scale oxide thin film transistor with potential for high-density image sensor applications.

PubMed

Jeon, Sanghun; Park, Sungho; Song, Ihun; Hur, Ji-Hyun; Park, Jaechul; Kim, Hojung; Kim, Sunil; Kim, Sangwook; Yin, Huaxiang; Chung, U-In; Lee, Eunha; Kim, Changjung

2011-01-01

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al₂O₃/SiO₂) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.

1/F Noise in Indium Phosphide Transistors

DTIC Science & Technology

1992-04-01

Zn/5 nm Au. The gate length and width were 1 Pm and 400 gm, respectively. The device was annealed at 375"C in argon for 1 minute to simultaneously...evaporation, defined by lift-off, and annealed at 375°C for 10 minutes. The gate region was recessed until a source-drain current of 35 mA was obtained...considerations for the signal Sn V,2/R, at the network input from the amplifier output show that vo2 4RoR,, s - 4 nR 2 = So •Mo. (6) 4Ro (Ro + R,) 2

Extended Characterization of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

NASA Technical Reports Server (NTRS)

Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2013-01-01

Collected data for both common-source and common-gate amplifiers is presented in this paper. Characterizations of the two amplifier circuits using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed with wider input frequency ranges and varying device sizes compared to earlier characterizations. The effects of the ferroelectric layer's capacitance and variation load, quiescent point, or input signal on each circuit are discussed. Comparisons between the MFSFET and MOSFET circuit operation and performance are discussed at length as well as applications and advantages for the MFSFETs.

Overcoming the drawback of lower sense margin in tunnel FET based dynamic memory along with enhanced charge retention and scalability

NASA Astrophysics Data System (ADS)

Navlakha, Nupur; Kranti, Abhinav

2017-11-01

The work reports on the use of a planar tri-gate tunnel field effect transistor (TFET) to operate as dynamic memory at 85 °C with an enhanced sense margin (SM). Two symmetric gates (G1) aligned to the source at a partial region of intrinsic film result into better electrostatic control that regulates the read mechanism based on band-to-band tunneling, while the other gate (G2), positioned adjacent to the first front gate is responsible for charge storage and sustenance. The proposed architecture results in an enhanced SM of ˜1.2 μA μm-1 along with a longer retention time (RT) of ˜1.8 s at 85 °C, for a total length of 600 nm. The double gate architecture towards the source increases the tunneling current and also reduces short channel effects, enhancing SM and scalability, thereby overcoming the critical bottleneck faced by TFET based dynamic memories. The work also discusses the impact of overlap/underlap and interface charges on the performance of TFET based dynamic memory. Insights into device operation demonstrate that the choice of appropriate architecture and biases not only limit the trade-off between SM and RT, but also result in improved scalability with drain voltage and total length being scaled down to 0.8 V and 115 nm, respectively.

Deep-submicron Graphene Field-Effect Transistors with State-of-Art fmax

PubMed Central

Lyu, Hongming; Lu, Qi; Liu, Jinbiao; Wu, Xiaoming; Zhang, Jinyu; Li, Junfeng; Niu, Jiebin; Yu, Zhiping; Wu, Huaqiang; Qian, He

2016-01-01

In order to conquer the short-channel effects that limit conventional ultra-scale semiconductor devices, two-dimensional materials, as an option of ultimate thin channels, receive wide attention. Graphene, in particular, bears great expectations because of its supreme carrier mobility and saturation velocity. However, its main disadvantage, the lack of bandgap, has not been satisfactorily solved. As a result, maximum oscillation frequency (fmax) which indicates transistors’ power amplification ability has been disappointing. Here, we present submicron field-effect transistors with specially designed low-resistance gate and excellent source/drain contact, and therefore significantly improved fmax. The fabrication was assisted by the advanced 8-inch CMOS back-end-of-line technology. A 200-nm-gate-length GFET achieves fT/fmax = 35.4/50 GHz. All GFET samples with gate lengths ranging from 200 nm to 400 nm possess fmax 31–41% higher than fT, closely resembling Si n-channel MOSFETs at comparable technology nodes. These results re-strengthen the promise of graphene field-effect transistors in next generation semiconductor electronics. PMID:27775009

Two-Dimensional Quantum Model of a Nanotransistor

NASA Technical Reports Server (NTRS)

Govindan, T. R.; Biegel, B.; Svizhenko, A.; Anantram, M. P.

2009-01-01

A mathematical model, and software to implement the model, have been devised to enable numerical simulation of the transport of electric charge in, and the resulting electrical performance characteristics of, a nanotransistor [in particular, a metal oxide/semiconductor field-effect transistor (MOSFET) having a channel length of the order of tens of nanometers] in which the overall device geometry, including the doping profiles and the injection of charge from the source, gate, and drain contacts, are approximated as being two-dimensional. The model and software constitute a computational framework for quantitatively exploring such device-physics issues as those of source-drain and gate leakage currents, drain-induced barrier lowering, and threshold voltage shift due to quantization. The model and software can also be used as means of studying the accuracy of quantum corrections to other semiclassical models.

Intelligent Gate Drive for Fast Switching and Crosstalk Suppression of SiC Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Zheyu; Dix, Jeffery; Wang, Fei Fred

This study presents an intelligent gate drive for silicon carbide (SiC) devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control gate voltages and gate loop impedances of both devices in a phase-leg configuration during different switching transients. Compared to conventional gate drives, the proposed circuit has the capability of accelerating the switching speed of the phase-leg power devices and suppressing the crosstalk to below device limits. Based on Wolfspeed 1200-V SiCmore » MOSFETs, the test results demonstrate the effectiveness of this intelligent gate drive under varying operating conditions. More importantly, the proposed intelligent gate assist circuitry is embedded into a gate drive integrated circuit, offering a simple, compact, and reliable solution for end-users to maximize benefits of SiC devices in actual power electronics applications.« less

Intelligent Gate Drive for Fast Switching and Crosstalk Suppression of SiC Devices

DOE PAGES

Zhang, Zheyu; Dix, Jeffery; Wang, Fei Fred; ...

2017-01-19

This study presents an intelligent gate drive for silicon carbide (SiC) devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control gate voltages and gate loop impedances of both devices in a phase-leg configuration during different switching transients. Compared to conventional gate drives, the proposed circuit has the capability of accelerating the switching speed of the phase-leg power devices and suppressing the crosstalk to below device limits. Based on Wolfspeed 1200-V SiCmore » MOSFETs, the test results demonstrate the effectiveness of this intelligent gate drive under varying operating conditions. More importantly, the proposed intelligent gate assist circuitry is embedded into a gate drive integrated circuit, offering a simple, compact, and reliable solution for end-users to maximize benefits of SiC devices in actual power electronics applications.« less

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

DOE Office of Scientific and Technical Information (OSTI.GOV)

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on > 1 μA at V d = -1 V) and highmore » I on /I off ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.« less

Experimental and theoretical studies of Sub-THz detection using strained-Si FETs

NASA Astrophysics Data System (ADS)

Delgado Notario, J. A.; Javadi, E.; Clericò, V.; Fobelets, K.; Otsuji, T.; Diez, E.; Velázquez-Pérez, J. E.; Meziani, Y. M.

2017-10-01

We report on experimental and theoretical studies of nanoscale gate-lengths strained Silicon MODFETs as room temperature non resonant detectors. Devices were excited at room temperature by an electronic source at 150 and 300 GHz to characterize their sub-THz response. The maximum of the photovoltaic response was obtained when the FET gate was biased at a value close to the threshold voltage. Simulations based on a bi-dimensional hydrodynamic model for the charge transport coupled to a Poisson equation solver were performed by using Synopsys TCAD. A charge boundary condition for the floating drain contact was implemented to obtain the photovoltaic response. Results from numerical simulations are in agreement with experimental ones. To understand the coupling between terahertz radiation and devices, the devices were rotated at different angles under excitation at both sub-terahertz frequencies and their response measured. Both NEP (Noise Equivalent Power) and Responsivity were calculated from measurements. To demonstrate their utility, devices were used as sensors in a terahertz imaging system for inspection of hidden objects at both frequencies.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

DOE PAGES

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; ...

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on > 1 μA at V d = -1 V) and highmore » I on /I off ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.« less

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons.

PubMed

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; Shi, Wu; Lee, Kyunghoon; Wu, Shuang; Yong Choi, Byung; Braganza, Rohit; Lear, Jordan; Kau, Nicholas; Choi, Wonwoo; Chen, Chen; Pedramrazi, Zahra; Dumslaff, Tim; Narita, Akimitsu; Feng, Xinliang; Müllen, Klaus; Fischer, Felix; Zettl, Alex; Ruffieux, Pascal; Yablonovitch, Eli; Crommie, Michael; Fasel, Roman; Bokor, Jeffrey

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch  ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on  > 1 μA at V d  = -1 V) and high I on /I off  ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.Graphene nanoribbons show promise for high-performance field-effect transistors, however they often suffer from short lengths and wide band gaps. Here, the authors use a bottom-up synthesis approach to fabricate 9- and 13-atom wide ribbons, enabling short-channel transistors with 10 5 on-off current ratio.

30 nm T-gate enhancement-mode InAlN/AlN/GaN HEMT on SiC substrates for future high power RF applications

NASA Astrophysics Data System (ADS)

Murugapandiyan, P.; Ravimaran, S.; William, J.

2017-08-01

The DC and RF performance of 30 nm gate length enhancement mode (E-mode) InAlN/AlN/GaN high electron mobility transistor (HEMT) on SiC substrate with heavily doped source and drain region have been investigated using the Synopsys TCAD tool. The proposed device has the features of a recessed T-gate structure, InGaN back barrier and Al2O3 passivated device surface. The proposed HEMT exhibits a maximum drain current density of 2.1 A/mm, transconductance {g}{{m}} of 1050 mS/mm, current gain cut-off frequency {f}{{t}} of 350 GHz and power gain cut-off frequency {f}\\max of 340 GHz. At room temperature the measured carrier mobility (μ), sheet charge carrier density ({n}{{s}}) and breakdown voltage are 1580 cm2/(V \\cdot s), 1.9× {10}13 {{cm}}-2, and 10.7 V respectively. The superlatives of the proposed HEMTs are bewitching competitor or future sub-millimeter wave high power RF VLSI circuit applications.

Single-fabrication-step Ge nanosphere/SiO2/SiGe heterostructures: a key enabler for realizing Ge MOS devices

NASA Astrophysics Data System (ADS)

Liao, P. H.; Peng, K. P.; Lin, H. C.; George, T.; Li, P. W.

2018-05-01

We report channel and strain engineering of self-organized, gate-stacking heterostructures comprising Ge-nanosphere gate/SiO2/SiGe-channels. An exquisitely-controlled dynamic balance between the concentrations of oxygen, Si, and Ge interstitials was effectively exploited to simultaneously create these heterostructures in a single oxidation step. Process-controlled tunability of the channel length (5–95 nm diameters for the Ge-nanospheres), gate oxide thickness (2.5–4.8 nm), as well as crystal orientation, chemical composition and strain engineering of the SiGe-channel was achieved. Single-crystalline (100) Si1‑x Ge x shells with Ge content as high as x = 0.85 and with a compressive strain of 3%, as well as (110) Si1‑x Ge x shells with Ge content of x = 0.35 and corresponding compressive strain of 1.5% were achieved. For each crystal orientation, our high Ge-content, highly-stressed SiGe shells feature a high degree of crystallinity and thus, provide a core ‘building block’ required for the fabrication of Ge-based MOS devices.

Single-fabrication-step Ge nanosphere/SiO2/SiGe heterostructures: a key enabler for realizing Ge MOS devices.

PubMed

Liao, P H; Peng, K P; Lin, H C; George, T; Li, P W

2018-05-18

We report channel and strain engineering of self-organized, gate-stacking heterostructures comprising Ge-nanosphere gate/SiO 2 /SiGe-channels. An exquisitely-controlled dynamic balance between the concentrations of oxygen, Si, and Ge interstitials was effectively exploited to simultaneously create these heterostructures in a single oxidation step. Process-controlled tunability of the channel length (5-95 nm diameters for the Ge-nanospheres), gate oxide thickness (2.5-4.8 nm), as well as crystal orientation, chemical composition and strain engineering of the SiGe-channel was achieved. Single-crystalline (100) Si 1-x Ge x shells with Ge content as high as x = 0.85 and with a compressive strain of 3%, as well as (110) Si 1-x Ge x shells with Ge content of x = 0.35 and corresponding compressive strain of 1.5% were achieved. For each crystal orientation, our high Ge-content, highly-stressed SiGe shells feature a high degree of crystallinity and thus, provide a core 'building block' required for the fabrication of Ge-based MOS devices.

Quasi-free-standing bilayer epitaxial graphene field-effect transistors on 4H-SiC (0001) substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yu, C.; Li, J.; Song, X. B.

2016-01-04

Quasi-free-standing epitaxial graphene grown on wide band gap semiconductor SiC demonstrates high carrier mobility and good material uniformity, which make it promising for graphene-based electronic devices. In this work, quasi-free-standing bilayer epitaxial graphene is prepared and its transistors with gate lengths of 100 nm and 200 nm are fabricated and characterized. The 100 nm gate length graphene transistor shows improved DC and RF performances including a maximum current density I{sub ds} of 4.2 A/mm, and a peak transconductance g{sub m} of 2880 mS/mm. Intrinsic current-gain cutoff frequency f{sub T} of 407 GHz is obtained. The exciting DC and RF performances obtained in the quasi-free-standingmore » bilayer epitaxial graphene transistor show the great application potential of this material system.« less

The fundamental downscaling limit of field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mamaluy, Denis, E-mail: mamaluy@sandia.gov; Gao, Xujiao

2015-05-11

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increasemore » in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.« less

The fundamental downscaling limit of field effect transistors

DOE PAGES

Mamaluy, Denis; Gao, Xujiao

2015-05-12

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increasemore » in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.« less

Computer aided design of monolithic microwave and millimeter wave integrated circuits and subsystems

NASA Astrophysics Data System (ADS)

Ku, Walter H.

1987-08-01

This interim technical report presents results of research on the computer aided design of monolithic microwave and millimeter wave integrated circuits and subsystems. A specific objective is to extend the state-of-the-art of the Computer Aided Design (CAD) of the monolithic microwave and millimeter wave integrated circuits (MIMIC). In this reporting period, we have derived a new model for the high electron mobility transistor (HEMT) based on a nonlinear charge control formulation which takes into consideration the variation of the 2DEG distance offset from the heterointerface as a function of bias. Pseudomorphic InGaAs/GaAs HEMT devices have been successfully fabricated at UCSD. For a 1 micron gate length, a maximum transconductance of 320 mS/mm was obtained. In cooperation with TRW, devices with 0.15 micron and 0.25 micron gate lengths have been successfully fabricated and tested. New results on the design of ultra-wideband distributed amplifiers using 0.15 micron pseudomorphic InGaAs/GaAs HEMT's have also been obtained. In addition, two-dimensional models of the submicron MESFET's, HEMT's and HBT's are currently being developed for the CRAY X-MP/48 supercomputer. Preliminary results obtained are also presented in this report.

Fringing field effects in negative capacitance field-effect transistors with a ferroelectric gate insulator

NASA Astrophysics Data System (ADS)

Hattori, Junichi; Fukuda, Koichi; Ikegami, Tsutomu; Ota, Hiroyuki; Migita, Shinji; Asai, Hidehiro; Toriumi, Akira

2018-04-01

We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal-oxide-semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.

Interface trap of p-type gate integrated AlGaN/GaN heterostructure field effect transistors

NASA Astrophysics Data System (ADS)

Kim, Kyu Sang

2017-09-01

In this work, the impact of trap states at the p-(Al)GaN/AlGaN interface has been investigated for the normally-off mode p-(Al)GaN/AlGaN/GaN heterostructure field-effect transistors (HFETs) by means of frequency dependent conductance. From the current-voltage (I-V) measurement, it was found that the p-AlGaN gate integrated device has higher drain current and lower gate leakage current compared to the p-GaN gate integrated device. We obtained the interface trap density and the characteristic time constant for the p-type gate integrated HFETs under the forward gate voltage of up to 6 V. As a result, the interface trap density (characteristic time constant) of the p-GaN gate device was lower (longer) than that of the p-AlGaN. Furthermore, it was analyzed that the trap state energy level of the p-GaN gate device was located at the shallow level relative to the p-AlGaN gate device, which accounts for different gate leakage current of each devices.

Dual-Gate p-GaN Gate High Electron Mobility Transistors for Steep Subthreshold Slope.

PubMed

Bae, Jong-Ho; Lee, Jong-Ho

2016-05-01

A steep subthreshold slope characteristic is achieved through p-GaN gate HEMT with dual-gate structure. Obtained subthreshold slope is less than 120 μV/dec. Based on the measured and simulated data obtained from single-gate device, breakdown of parasitic floating-base bipolar transistor and floating gate charged with holes are responsible to increase abruptly in drain current. In the dual-gate device, on-current degrades with high temperature but subthreshold slope is not changed. To observe the switching speed of dual-gate device and transient response of drain current are measured. According to the transient responses of drain current, switching speed of the dual-gate device is about 10(-5) sec.

Proposal for a graphene-based all-spin logic gate

NASA Astrophysics Data System (ADS)

Su, Li; Zhao, Weisheng; Zhang, Yue; Querlioz, Damien; Zhang, Youguang; Klein, Jacques-Olivier; Dollfus, Philippe; Bournel, Arnaud

2015-02-01

In this work, we present a graphene-based all-spin logic gate (G-ASLG) that integrates the functionalities of perpendicular anisotropy magnetic tunnel junctions (p-MTJs) with spin transport in graphene-channel. It provides an ideal integration of logic and memory. The input and output states are defined as the relative magnetization between free layer and fixed layer of p-MTJs. They can be probed by the tunnel magnetoresistance and controlled by spin transfer torque effect. Using lateral non-local spin valve, the spin information is transmitted by the spin-current interaction through graphene channels. By using a physics-based spin current compact model, the operation of G-ASLG is demonstrated and its performance is analyzed. It allows us to evaluate the influence of parameters, such as spin injection efficiency, spin diffusion length, contact area, the device length, and their interdependence, and to optimize the energy and dynamic performance. Compared to other beyond-CMOS solutions, longer spin information transport length (˜μm), higher data throughput, faster computing speed (˜ns), and lower power consumption (˜μA) can be expected from the G-ASLG.

Comparative analysis of full-gate and short-gate dielectric modulated electrically doped Tunnel-FET based biosensors

NASA Astrophysics Data System (ADS)

Sharma, Dheeraj; Singh, Deepika; Pandey, Sunil; Yadav, Shivendra; Kondekar, P. N.

2017-11-01

In this work, we have done a comprehensive study between full-gate and short-gate dielectrically modulated (DM) electrically doped tunnel field-effect transistor (SGDM-EDTFET) based biosensors of equivalent dimensions. However, in both the structures, dielectric constant and charge density are considered as a sensing parameter for sensing the charged and non-charged biomolecules in the given solution. In SGDM-EDTFET architecture, the reduction in gate length results a significant improvement in the tunneling current due to occurrence of strong coupling between gate and channel region which ensures higher drain current sensitivity for detection of the biomolecules. Moreover, the sensitivity of dual metal SGDM-EDTFET is compared with the single metal SGDM-EDTFET to analyze the better sensing capability of both the devices for the biosensor application. Further, the effect of sensing parameter i.e., ON-current (ION), and ION/IOFF ratio is analysed for dual metal SGDM-EDTFET in comparison with dual metal SGDM-EDFET. From the comparison, it is found that dual metal SGDM-EDTFET based biosensor attains relatively better sensitivity and can be utilized as a suitable candidate for biosensing applications.

Radiation Effects On Emerging Electronic Materials And Devices

DTIC Science & Technology

2010-01-17

RADIATION EFFECTS ON EMERGING ELECTRONIC MATERIALS AND DEVICES FINAL PERFORMANCE REPORT PREPARED FOR: Kitt Reinhardt AFOSR/NE 875 N...and the other with metal gates and a high-K gate dielectric. These devices were programmed using both back-gate pulse and gate induced drain leakage... metal gate process GIDL method Fig. 1. Sensing margin as a function of total ionizing dose for nMOS 1T-DRAM cells programmed by back-gate pulse and

Fabrication and characterization of tensile In0.3Al0.7As barrier and compressive In0.7Ga0.3As channel pHEMTs having extremely low gate leakage for low-noise applications

NASA Astrophysics Data System (ADS)

Packeer, F.; Mohamad Isa, M.; Mat Jubadi, W.; Ian, K. W.; Missous, M.

2013-07-01

This study focuses on the area of the epitaxial design, fabrication and characterization of a 1 µm gate-length InP-based pseudomorphic high electron mobility transistor (pHEMT) using InGaAs-InAlAs material systems. The advanced epitaxial layer design incorporates a highly strained aluminum-rich Schottky contact barrier, an indium-rich channel and a double delta-doped structure, which significantly improves upon the conventional low-noise pHEMT which suffers from high gate current leakage and low breakdown voltage. The outstanding achievements of the new design approach are 99% less gate current leakage and a 73% increase in breakdown voltage, compared with the conventional design. Furthermore, no degradation in RF performance is observed in terms of the cut-off frequency in this new highly tensile strained design. The remarkable performance of this advanced pHEMT design facilitates the implementation of outstanding low-noise devices.

Transport properties of silicon complementary-metal-oxide semiconductor quantum well field-effect transistors

NASA Astrophysics Data System (ADS)

Naquin, Clint Alan

Introducing explicit quantum transport into silicon (Si) transistors in a manner compatible with industrial fabrication has proven challenging, yet has the potential to transform the performance horizons of large scale integrated Si devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors fabricated using industrial silicon complementary MOS processing. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (VG) spacing between NDTCs. The VG spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background. A folding amplifier frequency multiplier circuit using a single QW NMOS transistor to generate a folded current-voltage transfer function via a NDTC was demonstrated. Time domain data shows frequency doubling in the kHz range at room temperature, and Fourier analysis confirms that the output is dominated by the second harmonic of the input. De-embedding the circuit response characteristics from parasitic cable and contact impedances suggests that in the absence of parasitics the doubling bandwidth could be as high as 10 GHz in a monolithic integrated circuit, limited by the transresistance magnitude of the QW NMOS. This is the first example of a QW device fabricated by mainstream Si CMOS technology being used in a circuit application and establishes the feasibility of scalable CMOS circuits that exploit explicit quantum transport. Ongoing quantum transport simulations based off of the spatial dopant distribution suggests a quasi-parabolic potential profile. Energy spacings between resonant transmission states are not consistent with experimental data, suggesting that either the assumed transport model is incomplete, or scattering mechanisms significantly mix the quasi-bound states and broaden the energy spacings.

Multiplexed charge-locking device for large arrays of quantum devices

NASA Astrophysics Data System (ADS)

Puddy, R. K.; Smith, L. W.; Al-Taie, H.; Chong, C. H.; Farrer, I.; Griffiths, J. P.; Ritchie, D. A.; Kelly, M. J.; Pepper, M.; Smith, C. G.

2015-10-01

We present a method of forming and controlling large arrays of gate-defined quantum devices. The method uses an on-chip, multiplexed charge-locking system and helps to overcome the restraints imposed by the number of wires available in cryostat measurement systems. The device architecture that we describe here utilises a multiplexer-type scheme to lock charge onto gate electrodes. The design allows access to and control of gates whose total number exceeds that of the available electrical contacts and enables the formation, modulation and measurement of large arrays of quantum devices. We fabricate such devices on n-type GaAs/AlGaAs substrates and investigate the stability of the charge locked on to the gates. Proof-of-concept is shown by measurement of the Coulomb blockade peaks of a single quantum dot formed by a floating gate in the device. The floating gate is seen to drift by approximately one Coulomb oscillation per hour.

Graphene-Based Liquid-Gated Field Effect Transistor for Biosensing: Theory and Experiments

PubMed Central

Reiner-Rozman, Ciril; Larisika, Melanie; Nowak, Christoph; Knoll, Wolfgang

2015-01-01

We present an experimental and theoretical characterization for reduced Graphene-Oxide (rGO) based FETs used for biosensing applications. The presented approach shows a complete result analysis and theoretically predictable electrical properties. The formulation was tested for the analysis of the device performance in the liquid gate mode of operation with variation of the ionic strength and pH-values of the electrolytes in contact with the FET. The dependence on the Debye length was confirmed experimentally and theoretically, utilizing the Debye length as a working parameter and thus defining the limits of applicability for the presented rGO-FETs. Furthermore, the FETs were tested for the sensing of biomolecules (bovine serum albumin (BSA) as reference) binding to gate-immobilized anti-BSA antibodies and analyzed using the Langmuir binding theory for the description of the equilibrium surface coverage as a function of the bulk (analyte) concentration. The obtained binding coefficients for BSA are found to be same as in results from literature, hence confirming the applicability of the devices. The FETs used in the experiments were fabricated using wet-chemically synthesized graphene, displaying high electron and hole mobility (μ) and provide the strong sensitivity also for low potential changes (by change of pH, ion concentration, or molecule adsorption). The binding coefficient for BSA-anti-BSA interaction shows a behavior corresponding to the Langmuir adsorption theory with a Limit of Detection (LOD) in the picomolar concentration range. The presented approach shows high reproducibility and sensitivity and a good agreement of the experimental results with the calculated data. PMID:25791463

Depletion-mode vertical Ga2O3 trench MOSFETs fabricated using Ga2O3 homoepitaxial films grown by halide vapor phase epitaxy

NASA Astrophysics Data System (ADS)

Sasaki, Kohei; Thieu, Quang Tu; Wakimoto, Daiki; Koishikawa, Yuki; Kuramata, Akito; Yamakoshi, Shigenobu

2017-12-01

We developed depletion-mode vertical Ga2O3 trench metal-oxide-semiconductor field-effect transistors by using n+ contact and n- drift layers. These epilayers were grown on an n+ (001) Ga2O3 single-crystal substrate by halide vapor phase epitaxy. Cu and HfO2 were used for the gate metal and dielectric film, respectively. The mesa width and gate length were approximately 2 and 1 µm, respectively. The devices showed good DC characteristics, with a specific on-resistance of 3.7 mΩ cm2 and clear current modulation. An on-off ratio of approximately 103 was obtained.

Ion/Ioff ratio enhancement and scalability of gate-all-around nanowire negative-capacitance FET with ferroelectric HfO2

NASA Astrophysics Data System (ADS)

Jang, Kyungmin; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2017-10-01

We have investigated the energy efficiency and scalability of ferroelectric HfO2 (FE:HfO2)-based negative-capacitance field-effect-transistor (NCFET) with gate-all-around (GAA) nanowire (NW) channel structure. Analytic simulation is conducted to characterize NW-NCFET by varying NW diameter and/or thickness of gate insulator as device structural parameters. Due to the negative-capacitance effect and GAA NW channel structure, NW-NCFET is found to have 5× higher Ion/Ioff ratio than classical NW-MOSFET and 2× higher than double-gate (DG) NCFET, which results in wider design window for high Ion/Ioff ratio. To analyze these obtained results from the viewpoint of the device scalability, we have considered constraints regarding very limited device structural spaces to fit by the gate insulator and NW channel for aggresively scaled gate length (Lg) and/or very tight NW pitch. NW-NCFET still has design point with very thinned gate insulator and/or narrowed NW. Therefore, FE:HfO2-based NW-NCFET is applicable to the aggressively scaled technology node of sub-10 nm Lg and to the very tight NW integration of sub-30 nm NW pitch for beyond 7 nm technology. From 2011 to 2014, he engaged in developing high-speed optical transceiver module as an alternative military service in Republic of Korea. His research interest includes the development of steep slope MOSFETs for high energy-efficient operation and ferroelectric HfO2-based semiconductor devices, and fabrication of nanostructured devices. He joined the IBM T.J. Watson Research Center, Yorktown Heights, NY, in 2010, where he worked on advanced CMOS technologies such as FinFET, nanowire FET, SiGe channel and III-V channel. He was also engaged in launching 14 nm SOI FinFET and RMG technology development. Since 2014, he has been an Associate Professor in Institute of Industrial Science, University of Tokyo, Tokyo, Japan, where he has been working on ultralow power transistor and memory technology. Dr. Kobayashi is a member of IEEE and the Japan Society of Applied Physics. Dr. Hiramoto is a fellow of Japan Society of Applied Physics and a member of IEEE and IEICE. He served as the General Chair of Silicon Nanoelectronics Workshop in 2003 and the Program Chair in 1997, 1999, and 2001. He was on Committee of IEDM from 2003 to 2009. He was the Program Chair of Symposium on VLSI Technology in 2013 and was the General Chair in 2015. He is the Program Chair of International Conference on Solid-State Devices and Materials (SSDM) in 2016.

Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length

NASA Astrophysics Data System (ADS)

Jain, Neeraj; Raj, Balwinder

2017-12-01

Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects (SCEs), leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SOI FinFET is one of the best multigate structures that has gained importance in all electronic design automation (EDA) industries due to its improved short channel effects (SCEs), because of its more effective gate-controlling capabilities. In this paper, our aim is to explore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evaluated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope (SS), ON current (I on), OFF current (I off) and I on/I off ratio. The potential benefits of SOI FinFET at drain-to-source voltage, V DS = 0.05 V and V DS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain (A V), output conductance (g d), trans-conductance (g m), gate capacitance (C gg), and cut-off frequency (f T = g m/2πC gg) with spacer region variations.

Design Optimization of Ge/GaAs-Based Heterojunction Gate-All-Around (GAA) Arch-Shaped Tunneling Field-Effect Transistor (A-TFET).

PubMed

Seo, Jae Hwa; Yoon, Young Jun; Kang, In Man

2018-09-01

The Ge/GaAs-based heterojunction gate-all-around (GAA) arch-shaped tunneling field-effect transistor (A-TFET) have been designed and optimized using technology computer-aided design (TCAD) simulations. In our previous work, the silicon-based A-TFET was designed and demonstrated. However, to progress the electrical characteristics of A-TFET, the III-V compound heterojunction structures which has enhanced electrical properties must be adopted. Thus, the germanium with gallium arsenide (Ge/GaAs) is considered as key materials of A-TFET. The proposed device has a Ge-based p-doped source, GaAs-based i-doped channel and GaAs-based n-doped drain. Due to the critical issues of device performances, the doping concentration of source and channel region (Dsource, Dchannel), height of source region (Hsource) and epitaxially grown thickness of channel (tepi) was selected as design optimization variables of Ge/GaAs-based GAA A-TFET. The DC characteristics such as on-state current (ion), off-state current (ioff), subthreshold-swing (S) were of extracted and analyzed. Finally, the proposed device has a gate length (LG) of 90 nm, Dsource 5 × 1019 cm-3, Dchannel of 1018 cm-3, tepi of 4 nm, Hsource of 90 nm, R of 10 nm and demonstrate an ion of 2 mA/μm, S of 12.9 mV/dec.

Self-aligned gated field emission devices using single carbon nanofiber cathodes

NASA Astrophysics Data System (ADS)

Guillorn, M. A.; Melechko, A. V.; Merkulov, V. I.; Hensley, D. K.; Simpson, M. L.; Lowndes, D. H.

2002-11-01

We report on the fabrication and operation of integrated gated field emission devices using single vertically aligned carbon nanofiber (VACNF) cathodes where the gate aperture has been formed using a self-aligned technique based on chemical mechanical polishing. We find that this method for producing gated cathode devices easily achieves structures with gate apertures on the order of 2 mum that show good concentric alignment to the VACNF emitter. The operation of these devices was explored and field emission characteristics that fit well to the Fowler-Nordheim model of emission was demonstrated.

Modeling and simulation of enhancement mode p-GaN Gate AlGaN/GaN HEMT for RF circuit switch applications

NASA Astrophysics Data System (ADS)

Panda, D. K.; Lenka, T. R.

2017-06-01

An enhancement mode p-GaN gate AlGaN/GaN HEMT is proposed and a physics based virtual source charge model with Landauer approach for electron transport has been developed using Verilog-A and simulated using Cadence Spectre, in order to predict device characteristics such as threshold voltage, drain current and gate capacitance. The drain current model incorporates important physical effects such as velocity saturation, short channel effects like DIBL (drain induced barrier lowering), channel length modulation (CLM), and mobility degradation due to self-heating. The predicted I d-V ds, I d-V gs, and C-V characteristics show an excellent agreement with the experimental data for both drain current and capacitance which validate the model. The developed model was then utilized to design and simulate a single-pole single-throw (SPST) RF switch.

New MBE buffer for micron- and quarter-micron-gateGaAs MESFETs

NASA Technical Reports Server (NTRS)

1988-01-01

A new buffer layer has been developed that eliminates backgating in GaAs MESFETs and substantially reduces short-channel effects in GaAs MESFETs with 0.27-micron-long gates. The new buffer is grown by molecular beam epitaxy (MBE) at a substrate temperature of 200 C using Ga and As sub 4 beam fluxes. The buffer is crystalline, highly resistive, optically inactive, and can be overgrown with high quality GaAs. GaAs MESFETs with a gate length of 0.27 microns that incorporate the new buffer show improved dc and RF properties in comparison with a similar MESFET with a thin undoped GaAs buffer. To demonstrate the backgating performance improvement afforded by the new buffer, MESFETs were fabricated using a number of different buffer layers and structures. A schematic cross section of the MESFET structure used in this study is shown. The measured gate length, gate width, and source-drain spacing of this device are 2,98, and 5.5 microns, respectively. An ohmic contact, isolated from the MESFET by mesa etching, served as the sidegate. The MESFETs were fabricated in MBE n-GaAs layers grown on the new buffer and also in MBE n-GaAs layers grown on buffer layers of undoped GaAs, AlGaAs, and GaAs/AlGaAs superlattices. All the buffer layers were grown by MBE and are 2 microns thick. The active layer is doped to approximately 2 x 10 to the 17th/cu cm with silicon and is 0.3 microns thick.

ZnO-based multiple channel and multiple gate FinMOSFETs

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Huang, Hung-Lin; Tseng, Chun-Yen; Lee, Hsin-Ying

2016-02-01

In recent years, zinc oxide (ZnO)-based metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted much attention, because ZnO-based semiconductors possess several advantages, including large exciton binding energy, nontoxicity, biocompatibility, low material cost, and wide direct bandgap. Moreover, the ZnO-based MOSFET is one of most potential devices, due to the applications in microwave power amplifiers, logic circuits, large scale integrated circuits, and logic swing. In this study, to enhance the performances of the ZnO-based MOSFETs, the ZnObased multiple channel and multiple gate structured FinMOSFETs were fabricated using the simple laser interference photolithography method and the self-aligned photolithography method. The multiple channel structure possessed the additional sidewall depletion width control ability to improve the channel controllability, because the multiple channel sidewall portions were surrounded by the gate electrode. Furthermore, the multiple gate structure had a shorter distance between source and gate and a shorter gate length between two gates to enhance the gate operating performances. Besides, the shorter distance between source and gate could enhance the electron velocity in the channel fin structure of the multiple gate structure. In this work, ninety one channels and four gates were used in the FinMOSFETs. Consequently, the drain-source saturation current (IDSS) and maximum transconductance (gm) of the ZnO-based multiple channel and multiple gate structured FinFETs operated at a drain-source voltage (VDS) of 10 V and a gate-source voltage (VGS) of 0 V were respectively improved from 11.5 mA/mm to 13.7 mA/mm and from 4.1 mS/mm to 6.9 mS/mm in comparison with that of the conventional ZnO-based single channel and single gate MOSFETs.

Simulation and parametric analysis of graphene p-n junctions with two rectangular top gates and a single back gate

NASA Astrophysics Data System (ADS)

Nikiforidis, Ioannis; Karafyllidis, Ioannis G.; Dimitrakis, Panagiotis

2018-02-01

Graphene p-n junctions could be the building blocks of future nanoelectronic circuits. While the conductance modulation of graphene p-n junctions formed in devices with one bottom and one top gate have received much attention, there is comparatively little work done on devices with two top gates. Here, we employ tight-bind Hamiltonians and non-equilibrium Green function method to compute in a systematic way the dependence of the conductance of graphene p-n junctions, formed in a device with two top gates, on the device parameters. We present our results in a compact and systematic way, so that the effect of each parameter is clearly shown. Our results show that the device conductance can be effectively modulated, and that graphene devices with two top gates may be used as basic elements in future carbon-based nanoelectronic circuits.

Field effect transistor and method of construction thereof

NASA Technical Reports Server (NTRS)

Fletner, W. R. (Inventor)

1978-01-01

A field effect transistor is constructed by placing a semi-conductor layer on an insulating substrate so that the gate region is separated from source and drain regions. The gate electrode and gate region of the layer are of generally reduced length, the gate region being of greatest length on its surface closest to the gate electrode. This is accomplished by initially creating a relatively large gate region of one polarity, and then reversing the polarity of a central portion of this gate region by ion bombardment, thus achieving a narrower final gate region of the stated configuration.

Thermally activated hysteresis in high quality graphene/h-BN devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cadore, A. R., E-mail: alissoncadore@gmail.com, E-mail: lccampos@fisica.ufmg.br; Mania, E.; Lacerda, R. G.

2016-06-06

We report on gate hysteresis of resistance in high quality graphene/hexagonal boron nitride (h-BN) devices. We observe a thermally activated hysteretic behavior in resistance as a function of the applied gate voltage at temperatures above 375 K. In order to investigate the origin of the hysteretic phenomenon, we compare graphene/h-BN heterostructure devices with SiO{sub 2}/Si back gate electrodes to devices with graphite back gate electrodes. The gate hysteretic behavior of the resistance is present only in devices with an h-BN/SiO{sub 2} interface and is dependent on the orientation of the applied gate electric field and sweep rate. We describe a phenomenologicalmore » model which captures all of our findings based on charges trapped at the h-BN/SiO{sub 2} interface. Such hysteretic behavior in graphene resistance must be considered in high temperature applications for graphene devices and may open new routes for applications in digital electronics and memory devices.« less

An electrically reconfigurable logic gate intrinsically enabled by spin-orbit materials.

PubMed

Kazemi, Mohammad

2017-11-10

The spin degree of freedom in magnetic devices has been discussed widely for computing, since it could significantly reduce energy dissipation, might enable beyond Von Neumann computing, and could have applications in quantum computing. For spin-based computing to become widespread, however, energy efficient logic gates comprising as few devices as possible are required. Considerable recent progress has been reported in this area. However, proposals for spin-based logic either require ancillary charge-based devices and circuits in each individual gate or adopt principals underlying charge-based computing by employing ancillary spin-based devices, which largely negates possible advantages. Here, we show that spin-orbit materials possess an intrinsic basis for the execution of logic operations. We present a spin-orbit logic gate that performs a universal logic operation utilizing the minimum possible number of devices, that is, the essential devices required for representing the logic operands. Also, whereas the previous proposals for spin-based logic require extra devices in each individual gate to provide reconfigurability, the proposed gate is 'electrically' reconfigurable at run-time simply by setting the amplitude of the clock pulse applied to the gate. We demonstrate, analytically and numerically with experimentally benchmarked models, that the gate performs logic operations and simultaneously stores the result, realizing the 'stateful' spin-based logic scalable to ultralow energy dissipation.

Study on the electrical degradation of AlGaN/GaN MIS-HEMTs induced by residual stress of SiNx passivation

NASA Astrophysics Data System (ADS)

Bai, Zhiyuan; Du, Jiangfeng; Liu, Yong; Xin, Qi; Liu, Yang; Yu, Qi

2017-07-01

In this paper, we report a new phenomenon in C-V measurement of different gate length MIS-HEMTs, which can be associated with traps character of the AlGaN/GaN interface. The analysis of DC measurement, frequency dependent capacitance-voltage measurements and simulation show that the stress from passivation layer may induce a decrease of drain output current Ids, an increase of on-resistance, serious nonlinearity of transconductance gm, and a new peak of C-V curve. The value of the peak is reduced to zero while the gate length and measure frequency are increasing to 21 μm and 1 MHz, respectively. By using conductance method, the SiNx/GaN interface traps with energy level of EC-0.42 eV to EC-0.45 eV and density of 3.2 × 1012 ∼ 5.0 × 1012 eV-1 cm-2 is obtained after passivation. According to the experimental and simulation results, formation of the acceptor-like traps with concentration of 3 × 1011 cm-2 and energy level of EC-0.37 eV under the gate on AlGaN barrier side of AlGaN/GaN interface is the main reason for the degradation after the passivation. He is currently an Associate Professor with State Key Laboratory of Electronic Thin Films and Integrated Devices, School of Microelectronics and Solid-State Electronics, UESTC. He is the author of over 30 peer-reviewed journal papers and more than 20 conference papers. He has also hold over 20 patents. His research interests include Gallium Nitride based high-voltage power switching devices, microwave and millimeter-wave power devices and integrated technologies. Dr. Yu was a recipient of the prestigious Award of Science and Technology of China

Hydrodynamic electronic fluid instability in GaAs MESFETs at terahertz frequencies

NASA Astrophysics Data System (ADS)

Li, Kang; Hao, Yue; Jin, Xiaoqi; Lu, Wu

2018-01-01

III-V compound semiconductor field effect transistors (FETs) are potential candidates as solid state THz emitters and detectors due to plasma wave instability in these devices. Using a 2D hydrodynamic model, here we present the numerical studies of electron fluid instability in a FET structure. The model is implemented in a GaAs MESFET structure with a gate length of 0.2 µm as a testbed by taking into account the non-equilibrium transport and multi-valley non-parabolicity energy bands. The results show that the electronic density instability in the channel can produce stable periodic oscillations at THz frequencies. Along with stable oscillations, negative differential resistance in output characteristics is observed. The THz emission energy density increases monotonically with the drain bias. The emission frequency of electron density oscillations can be tuned by both gate and drain biases. The results suggest that III-V FETs can be a kind of versatile THz devices with good tunability on both radiative power and emission frequency.

Impact of strain on electronic and transport properties of 6 nm hydrogenated germanane nano-ribbon channel double gate field effect transistor

NASA Astrophysics Data System (ADS)

Meher Abhinav, E.; Sundararaj, Anuraj; Gopalakrishnan, Chandrasekaran; Kasmir Raja, S. V.; Chokhra, Saurabh

2017-11-01

In this work, chair like fully hydrogenated germanane (CGeH) nano-ribbon 6 nm short channel double gate field effect transistor (DG-FET) has been modeled and the impact of strain on the I-V characteristics of CGeH channel has been examined. The bond lengths, binding and formation energies of various hydrogenated geometries of buckled germanane channel were calculated using local density approximation (LDA) with Perdew-Zunger (PZ) and generalized gradient approximation (GGA) with Perdew Burke Ernzerhof (PBE) parameterization. From four various geometries, chair like structure is found to be more stable compared to boat like obtuse, stiruup structure and table like structure. The bandgap versus width, bandgap versus strain characteristics and I-V characteristics had been analyzed at room temperature using density functional theory (DFT). Using self consistent calculation it was observed that the electronic properties of nano-ribbon is independent of length and band structure, but dependent on edge type, strain [Uni-axial (ɛ xx ), bi-axial (ɛ xx   =  ɛ yy )] and width of the ribbon. The strain engineered hydrogenated germanane (GeH) showed wide direct bandgap (2.3 eV) which could help to build low noise electronic devices that operates at high frequencies. The observed bi-axial compression has high impact on the device transport characteristics with peak to valley ratio (PVR) of 2.14 and 380% increase in peak current compared to pristine CGeH device. The observed strain in CGeH DG-FET could facilitate in designing novel multiple-logic memory devices due to multiple negative differential resistance (NDR) regions.

Impact of gate geometry on ionic liquid gated ionotronic systems

DOE PAGES

Wong, Anthony T.; Noh, Joo Hyon; Pudasaini, Pushpa Raj; ...

2017-01-23

Ionic liquid electrolytes are gaining widespread application as a gate dielectric used to control ion transport in functional materials. This letter systematically examines the important influence that device geometry in standard “side gate” 3-terminal geometries plays in device performance of a well-known oxygen ion conductor. We show that the most influential component of device design is the ratio between the area of the gate electrode and the active channel, while the spacing between these components and their individual shapes has a negligible contribution. Finally, these findings provide much needed guidance in device design intended for ionotronic gating with ionic liquids.

Dual Input AND Gate Fabricated From a Single Channel Poly (3-Hexylthiophene) Thin Film Field Effect Transistor

NASA Technical Reports Server (NTRS)

Pinto, N. J.; Perez, R.; Mueller, C. H.; Theofylaktos, N.; Miranda, F. A.

2006-01-01

A regio-regular poly (3-hexylthiophene) (RRP3HT) thin film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. This device demonstrates AND logic functionality. The device functionality was controlled by applying either 0 or -10 V to each of the gate electrodes. When -10 V was simultaneously applied to both gates, the device was conductive (ON), while any other combination of gate voltages rendered the device resistive (OFF). The p-type carrier charge mobility was about 5x10(exp -4) per square centimeter per V-sec. The low mobility is attributed to the sharp contours of the RRP3HT film due to substrate non-planarity. A significant advantage of this architecture is that AND logic devices with multiple inputs can be fabricated using a single RRP3HT channel with multiple gates.

Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance

NASA Astrophysics Data System (ADS)

Tayal, Shubham; Nandi, Ashutosh

2018-06-01

This paper for the first time investigates the effect of temperature variation on analog/RF performance of SiO2 as well as high-K gate dielectric based junctionless silicon nanotube FET (JL-SiNTFET). It is observed that the change in temperature does not variate the analog/RF performance of junctionless silicon nanotube FET by substantial amount. By increasing the temperature from 77 K to 400 K, the deterioration in intrinsic dc gain (AV) is marginal that is only ∼3 dB. Furthermore, the variation in cut-off frequency (fT), maximum oscillation frequency (fMAX), and gain-frequency product (GFP) with temperature is also minimal in JLSiNT-FET. More so, the same trend is observed even at scaled gate length (Lg = 15 nm). Furthermore, we have observed that the use of high-K gate dielectric deteriorates the analog/RF performance of JLSiNT-FET. However, the use of high-K gate dielectric negligibly changes the effect of temperature variation on analog/RF performance of JLSINT-FET device.

Limits on silicon nanoelectronics for terascale integration.

PubMed

Meindl, J D; Chen, Q; Davis, J A

2001-09-14

Throughout the past four decades, silicon semiconductor technology has advanced at exponential rates in both performance and productivity. Concerns have been raised, however, that the limits of silicon technology may soon be reached. Analysis of fundamental, material, device, circuit, and system limits reveals that silicon technology has an enormous remaining potential to achieve terascale integration (TSI) of more than 1 trillion transistors per chip. Such massive-scale integration is feasible assuming the development and economical mass production of double-gate metal-oxide-semiconductor field effect transistors with gate oxide thickness of about 1 nanometer, silicon channel thickness of about 3 nanometers, and channel length of about 10 nanometers. The development of interconnecting wires for these transistors presents a major challenge to the achievement of nanoelectronics for TSI.

Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates

NASA Astrophysics Data System (ADS)

Chappanda, K. N.; Ilyas, S.; Younis, M. I.

2018-05-01

Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5  ×  1012 oscillations.

Optical NAND gate

DOEpatents

Skogen, Erik J [Albuquerque, NM; Raring, James [Goleta, CA; Tauke-Pedretti, Anna [Albuquerque, NM

2011-08-09

An optical NAND gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator and a photodetector. One pair of the optical waveguide devices is electrically connected in parallel to operate as an optical AND gate; and the other pair of the optical waveguide devices is connected in series to operate as an optical NOT gate (i.e. an optical inverter). The optical NAND gate utilizes two digital optical inputs and a continuous light input to provide a NAND function output. The optical NAND gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

Breaking Through the Multi-Mesa-Channel Width Limited of Normally Off GaN HEMTs Through Modulation of the Via-Hole-Length.

PubMed

Chien, Cheng-Yen; Wu, Wen-Hsin; You, Yao-Hong; Lin, Jun-Huei; Lee, Chia-Yu; Hsu, Wen-Ching; Kuan, Chieh-Hsiung; Lin, Ray-Ming

2017-12-01

We present new normally off GaN high-electron-mobility transistors (HEMTs) that overcome the typical limitations in multi-mesa-channel (MMC) width through modulation of the via-hole-length to regulate the charge neutrality screen effect. We have prepared enhancement-mode (E-mode) GaN HEMTs having widths of up to 300 nm, based on an enhanced surface pinning effect. E-mode GaN HEMTs having MMC structures and widths as well as via-hole-lengths of 100 nm/2 μm and 300 nm/6 μm, respectively, exhibited positive threshold voltages (V th ) of 0.79 and 0.46 V, respectively. The on-resistances of the MMC and via-hole-length structures were lower than those of typical tri-gate nanoribbon GaN HEMTs. In addition, the devices not only achieved the E-mode but also improved the power performance of the GaN HEMTs and effectively mitigated the device thermal effect. We controlled the via-hole-length sidewall surface pinning effect to obtain the E-mode GaN HEMTs. Our findings suggest that via-hole-length normally off GaN HEMTs have great potential for use in next-generation power electronics.

Extraction of mobility and Degradation coefficients in double gate junctionless transistors

NASA Astrophysics Data System (ADS)

Bhuvaneshwari, Y. V.; Kranti, Abhinav

2017-12-01

In this work, we use the modified McLarty function to understand and extract accumulation (μ acc) and bulk (μ bulk) mobility in Double Gate (DG) Junctionless (JL) MOSFETs over a wide range of doping concentration (N d) and temperature range (250 K to 520 K). The approach enables the estimation of mobility and its attenuation factors (θ 1 and θ 2) by a single method. The extracted results indicate that μ acc can reach higher values than μ bulk due to the screening effect. Results also show that θ 2 extracted in the accumulation regime of JL transistors exhibit relatively low values in comparison to inversion and accumulation mode devices. It is shown that the attenuation factor (θ 1) in JL devices designed with higher N d (≥1019 cm-3) is mainly affected by series resistance (R sd) whereas, in inversion mode (IM) and Accumulation mode (AM) devices, θ 1 factor is governed by both the intrinsic mobility reduction factor (θ 10) and R sd. Additionally, the impact of variation in oxide thickness (T ox), gate length (L g), N d and temperature on θ 1 and θ 2 has been investigated for JL transistor. The weak dependence of μ bulk and μ acc on temperature shows the prevalence of coulomb scattering over phonon scattering for heavily doped JL transistors. The work provides insights into different modes of operation, extraction of mobility and attenuation factors which will be useful for the development of compact models for JL transistors.

Proposal of ultra-compact NAND/NOR/XNOR all-optical logic gates based on a nonlinear 3x1 multimode interference

NASA Astrophysics Data System (ADS)

Tajaldini, Mehdi; Mat Jafri, M. Z.

2014-05-01

We present a highly miniaturized multimode interference (MMI) coupler based on nonlinear modal propagation analysis (NMPA) method as a novel design method and potential application for optical NAND, NOR and XNOR logic gates for Boolean logic signal processing devices. Crystalline polydiacetylene is used to allow the appearances of nonlinear effects in low input intensities and ultra- short length to control the MMI coupler as an active device to access light switching due to its high nonlinear susceptibility. We consider a 10x33 μm2 MMI structure with three inputs and one output. Notably, the access facets are single-mode waveguides with sub-micron width. The center input contributes to control the induced light propagation in MMI by intensity variation whereas others could be launched by particular intensity when they are ON and 0 in OFF. Output intensity is analyzed in various sets of inputs to show the capability of Boolean logic gates, the contrast between ON and OFF is calculated on mentioned gates to present the efficiency. Good operation in low intensity and highly miniaturized MMI coupler is observed. Furthermore, nonlinear effects could be realized through the modal interferences. The issue of high insertion loss is addressed with a 3×3 upgraded coupler. Furthermore, the main significant aspect of this paper is simulating an MMI coupler that is launched by three nonlinear inputs, simultaneously, whereas last presents have never studied more than one input in nonlinear regimes.

Silicon-compatible high-hole-mobility transistor with an undoped germanium channel for low-power application

NASA Astrophysics Data System (ADS)

Cho, Seongjae; Man Kang, In; Rok Kim, Kyung; Park, Byung-Gook; Harris, James S.

2013-11-01

In this work, Ge-based high-hole-mobility transistor with Si compatibility is designed, and its performance is evaluated. A 2-dimensional hole gas is effectively constructed by a AlGaAs/Ge/Si heterojunction with a sufficiently large valence band offset. Moreover, an intrinsic Ge channel is exploited so that high hole mobility is preserved without dopant scattering. Effects of design parameters such as gate length, Ge channel thickness, and aluminum fraction in the barrier material on device characteristics are thoroughly investigated through device simulations. A high on-current above 30 μA/μm along with a low subthreshold swing was obtained from an optimized planar device for low-power applications.

Hetero-Material Gate Doping-Less Tunnel FET and Its Misalignment Effects on Analog/RF Parameters

NASA Astrophysics Data System (ADS)

Anand, Sunny; Sarin, R. K.

2018-03-01

In this paper, with the use of a hetero-material gate technique, a tunnel field-effect transistor (TFET) subject to charge plasma technique is proposed, named as hetero-material gate doping-less tunnel FET (HMG-DLTFET) and a brief study has been done on the effects due to misalignment of the bottom gate towards drain (GMAD) and towards source (GMAS). The proposed devices provide better performance as the drive current increased by three times as compared to conventional doping-less TFET (DLTFET). The results are then analyzed and compared with conventional doped hetero-material gate double-gate tunnel FET (HMG-DGTFET). The analog/radiofrequency (RF) performance has been studied for both devices and comparative analysis has been done for different parameters such as drain current (I D), transconductance (g m), output conductance (g d), total gate capacitance (C gg) and cutoff frequency (f T). Both devices performed similarly in different misalignment configurations. When the bottom gate is perfectly aligned, the best performance is observed for both devices, but the doping-less device gives slightly more freedom for fabrication engineers as the amount of tolerance for HMG-DLTFET is better than that of HMG-DGTFET.

Contact resistance and overlapping capacitance in flexible sub-micron long oxide thin-film transistors for above 100 MHz operation

NASA Astrophysics Data System (ADS)

Münzenrieder, Niko; Salvatore, Giovanni A.; Petti, Luisa; Zysset, Christoph; Büthe, Lars; Vogt, Christian; Cantarella, Giuseppe; Tröster, Gerhard

2014-12-01

In recent years new forms of electronic devices such as electronic papers, flexible displays, epidermal sensors, and smart textiles have become reality. Thin-film transistors (TFTs) are the basic blocks of the circuits used in such devices and need to operate above 100 MHz to efficiently treat signals in RF systems and address pixels in high resolution displays. Beyond the choice of the semiconductor, i.e., silicon, graphene, organics, or amorphous oxides, the junctionless nature of TFTs and its geometry imply some limitations which become evident and important in devices with scaled channel length. Furthermore, the mechanical instability of flexible substrates limits the feature size of flexible TFTs. Contact resistance and overlapping capacitance are two parasitic effects which limit the transit frequency of transistors. They are often considered independent, while a deeper analysis of TFTs geometry imposes to handle them together; in fact, they both depend on the overlapping length (LOV) between source/drain and the gate contacts. Here, we conduct a quantitative analysis based on a large number of flexible ultra-scaled IGZO TFTs. Devices with three different values of overlap length and channel length down to 0.5 μm are fabricated to experimentally investigate the scaling behavior of the transit frequency. Contact resistance and overlapping capacitance depend in opposite ways on LOV. These findings establish routes for the optimization of the dimension of source/drain contact pads and suggest design guidelines to achieve megahertz operation in flexible IGZO TFTs and circuits.

Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

NASA Astrophysics Data System (ADS)

An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

2016-11-01

Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ravindran, P; Wui Ann, W; Lim, Y

Purpose: In general, the linear accelerator is gated using respiratory signal obtained by way of external sensors to account for the breathing motion during radiotherapy. One of the commonly used gating devices is the Varian RPM device. Calypso system that uses electromagnetic tracking of implanted or surface transponders could also be used for gating. The aim of this study is to compare the gating efficiency of RPM device and the calypso system by phantom studies. Methods: An ArcCheck insert was used as the phantom with a Gafchromic film placed in its holder. The ArcCheck insert was placed on a Motionmore » Sim platform and moved in the longitudinal direction simulating a respiratory motion with a period of 5 seconds and amplitude of ±6mm. The Gafchromic film was exposed to a 2 × 2cm{sup 2} field, i) with the phantom static, ii) phantom moving but ungated iii) gated with gating window of 2mm and 3mm. This was repeated with Calypso system using surface transponders with the same gating window. The Gafchromic films were read with an EPSON 11000 flatbed scanner and analysed with ‘Medphysto’ software. Results: The full width at half maximum (FWHM) as measured with film at the level of the film holder was 1.65cm when the phantom was static. FWHM measured with phantom moving and without gating was 1.16 cm and penumbra was 7 mm (80–20%) on both sides. When the beam was gated with 2 mm gating window the FWHM was 1.8 cm with RPM device and 1.9 cm with Calypso. Similarly, when the beam was gated with 3 mm window, the FWHM was 1.9cm with RPM device and 2cm with Calypso. Conclusion: This work suggests that the gating efficiency of RPM device is better than that of the Calypso with surface transponder, with reference to the latency in gating.« less

Electrolyte-gated transistors based on conducting polymer nanowire junction arrays.

PubMed

Alam, Maksudul M; Wang, Jun; Guo, Yaoyao; Lee, Stephanie P; Tseng, Hsian-Rong

2005-07-07

In this study, we describe the electrolyte gating and doping effects of transistors based on conducting polymer nanowire electrode junction arrays in buffered aqueous media. Conducting polymer nanowires including polyaniline, polypyrrole, and poly(ethylenedioxythiophene) were investigated. In the presence of a positive gate bias, the device exhibits a large on/off current ratio of 978 for polyaniline nanowire-based transistors; these values vary according to the acidity of the gate medium. We attribute these efficient electrolyte gating and doping effects to the electrochemically fabricated nanostructures of conducting polymer nanowires. This study demonstrates that two-terminal devices can be easily converted into three-terminal transistors by simply immersing the device into an electrolyte solution along with a gate electrode. Here, the field-induced modulation can be applied for signal amplification to enhance the device performance.

Highly tunable local gate controlled complementary graphene device performing as inverter and voltage controlled resistor.

PubMed

Kim, Wonjae; Riikonen, Juha; Li, Changfeng; Chen, Ya; Lipsanen, Harri

2013-10-04

Using single-layer CVD graphene, a complementary field effect transistor (FET) device is fabricated on the top of separated back-gates. The local back-gate control of the transistors, which operate with low bias at room temperature, enables highly tunable device characteristics due to separate control over electrostatic doping of the channels. Local back-gating allows control of the doping level independently of the supply voltage, which enables device operation with very low VDD. Controllable characteristics also allow the compensation of variation in the unintentional doping typically observed in CVD graphene. Moreover, both p-n and n-p configurations of FETs can be achieved by electrostatic doping using the local back-gate. Therefore, the device operation can also be switched from inverter to voltage controlled resistor, opening new possibilities in using graphene in logic circuitry.

Concentric-electrode organic electrochemical transistors: case study for selective hydrazine sensing

NASA Astrophysics Data System (ADS)

Pecqueur, S.; Lenfant, S.; Guérin, D.; Alibart, F.; Vuillaume, D.

2017-12-01

We report on hydrazine-sensing organic electrochemical transistors (OECTs) with a design consisting in concentric annular electrodes. The design engineering of these OECTs was motivated by the great potential of using OECT sensing arrays in fields such as bioelectronics. In this work, PEDOT:PSS-based OECTs have been studied as aqueous sensors, specifically sensitive to the lethal hydrazine molecule. These amperometric sensors have many relevant features for the development of hydrazine sensors, such as a sensitivity down to 10-5 M of hydrazine in water, an order of magnitude higher selectivity for hydrazine than for 9 other water soluble common analytes, the capability to recover entirely its base signal after water flushing and a very low voltage operation. The specificity for hydrazine to be sensed by our OECTs is caused by its catalytic oxidation at the gate electrode and enables increasing the output current modulation of the devices. This has permitted the device-geometry study of the whole series of 80 micrometric OECT devices with sub-20-nm PEDOT:PSS layers, channel lengths down to 1 μm and a specific device geometry of coplanar and concentric electrodes. The numerous geometries unravel new aspects of the OECT mechanisms governing the electrochemical sensing behaviours of the device, more particularly the effect of the contacts which are inherent at the micro-scale. By lowering the device cross-talking, micrometric gate-integrated radial OECTs shall contribute to the diminishing of the readout invasiveness and therefore promotes further the development of OECT biosensors.

A static induction device manufactured by silicon direct bonding

NASA Astrophysics Data System (ADS)

Chen, Xin'an; Liu, Su; Huang, Qing'an

2004-07-01

It is always a key problem how to improve the gate-source breakdown voltage (VGK) of static induction devices during manufacturing. By using a silicon direct bonding process to replace the high resistivity epitaxy process, a bonding buried gate structure is formed, which is different from an epitaxy buried gate structure. The new structure can improve the gate-source breakdown voltage from the process and the structure. It is shown that the bonding buried gate structure is a promising structure, that can improve the VGK and other performances of devices, by manufacture of a static induction thyristor.

Performance improvement of doped TFET by using plasma formation concept

NASA Astrophysics Data System (ADS)

Soni, Deepak; Sharma, Dheeraj; Yadav, Shivendra; Aslam, Mohd.; Sharma, Neeraj

2018-01-01

Formation of abrupt doping profile at tunneling junction for the nanoscale tunnel field effect transistor (TFET) is a critical issue for attaining improved electrical behaviour. The realization of abrupt doping profile is more difficult in the case of physically doped TFETs due to material solubility limit. In this concern, we propose a novel design of TFET. For this, P+ (source)-I (channel)-N (drain) type structure has been considered, wherein a metal electrode is deposited over the source region. In addition to this, a negative voltage is applied to the source electrode (SE). It induces the surface plasma layer of holes in the source region, which is responsible for steepness in the bands at source/channel junction and provides the advantage of higher doping in source region without any addition of the physical impurity. The proposed modification is helpful for achieving steeper band bending at the source/channel interface, which enables higher tunneling generation rate of charge carriers at this interface and overcomes the issue of low ON-state current. Thus, the proposed device shows the increment of 2 decades in drain current and 252 mV reduction in threshold voltage compared with conventional device. The optimization of spacer length (LSG) between source/gate (LSG) and applied negative voltage (Vpg) over source electrode have been performed to obtain optimum drain current and threshold voltage (Vth). Further, for the suppression of ambipolar current, drain region is kept lightly doped, which reduces the ambipolar current up to level of Off state current. Moreover, in the proposed device gate electrode is underlapped for improving RF performance. It also reduces gate to drain capacitances (Cgd) and increases cut-off-frequency (fT), fmax, GBP, TFP. In addition to these, linearity analysis has been performed to validate the applicability of the device.

The four-gate transistor

NASA Technical Reports Server (NTRS)

Mojarradi, M. M.; Cristoveanu, S.; Allibert, F.; France, G.; Blalock, B.; Durfrene, B.

2002-01-01

The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

Comparative influence study of gate-formation structuring on Al0.22Ga0.78As/In0.16Ga0.84As/Al0.22Ga0.78As double heterojunction high electron mobility transistors

NASA Astrophysics Data System (ADS)

Hsu, M. K.; Chiu, S. Y.; Wu, C. H.; Guo, D. F.; Lour, W. S.

2008-12-01

Pseudomorphic Al0.22Ga0.78As/In0.16Ga0.84As/Al0.22Ga0.78As double heterojunction high electron mobility transistors (DH-HEMTs) fabricated with different gate-formation structures of a single-recess gate (SRG), a double-recess gate (DRG) and a field-plate gate (FPG) were comparatively investigated. FPG devices show the best breakdown characteristics among these devices due to great reduction in the peak electric field between the drain and gate electrodes. The measured gate-drain breakdown voltages defined at a 1 mA mm-1 reverse gate-drain current density were -15.3, -19.1 and -26.0 V for SRG, DRG and FPG devices, respectively. No significant differences in their room-temperature common-source current-voltage characteristics were observed. However, FPG devices exhibit threshold voltages being the least sensitive to temperature. Threshold voltages as a function of temperature indicate a threshold-voltage variation as low as -0.97 mV K-1 for FPG devices. According to the 2.4 GHz load-pull power measurement at VDS = 3.0 V and VGS = -0.5 V, the saturated output power (POUT), power gain (GP) and maximum power-added efficiency (PAE) were 10.3 dBm/13.2 dB/36.6%, 11.2 dBm/13.1 dB/39.7% and 13.06 dBm/12.8 dB/47.3%, respectively, for SRG, DRG and FPG devices with a pi-gate in class AB operation. When the FPG device is biased at a VDS of 10 V, the saturated power density is more than 600 mW mm-1.

EduGATE - basic examples for educative purpose using the GATE simulation platform.

PubMed

Pietrzyk, Uwe; Zakhnini, Abdelhamid; Axer, Markus; Sauerzapf, Sophie; Benoit, Didier; Gaens, Michaela

2013-02-01

EduGATE is a collection of basic examples to introduce students to the fundamental physical aspects of medical imaging devices. It is based on the GATE platform, which has received a wide acceptance in the field of simulating medical imaging devices including SPECT, PET, CT and also applications in radiation therapy. GATE can be configured by commands, which are, for the sake of simplicity, listed in a collection of one or more macro files to set up phantoms, multiple types of sources, detection device, and acquisition parameters. The aim of the EduGATE is to use all these helpful features of GATE to provide insights into the physics of medical imaging by means of a collection of very basic and simple GATE macros in connection with analysis programs based on ROOT, a framework for data processing. A graphical user interface to define a configuration is also included. Copyright © 2012. Published by Elsevier GmbH.

Leakage effects in n-GaAs MESFET with n-GaAs buffer layer

NASA Technical Reports Server (NTRS)

Wang, Y. C.; Bahrami, M.

1983-01-01

Whereas improvement of the interface between the active layer and the buffer layer has been demonstrated, the leakage effects can be important if the buffer layer resistivity is not sufficiently high and/or the buffer layer thickness is not sufficiently small. It was found that two buffer leakage currents exist from the channel under the gate to the source and from drain to the channel in addition to the buffer leakage resistance between drain and source. It is shown that for a 1 micron gate-length n-GaAs MESFET, if the buffer layer resistivity is 12 OHM-CM and the buffer layer thickness h is 2 microns, the performance of the device degrades drastically. It is suggested that h should be below 2 microns.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

PubMed Central

Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

2016-01-01

An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated. PMID:26839036

Large-Area CVD-Grown Sub-2 V ReS2 Transistors and Logic Gates.

PubMed

Dathbun, Ajjiporn; Kim, Youngchan; Kim, Seongchan; Yoo, Youngjae; Kang, Moon Sung; Lee, Changgu; Cho, Jeong Ho

2017-05-10

We demonstrated the fabrication of large-area ReS 2 transistors and logic gates composed of a chemical vapor deposition (CVD)-grown multilayer ReS 2 semiconductor channel and graphene electrodes. Single-layer graphene was used as the source/drain and coplanar gate electrodes. An ion gel with an ultrahigh capacitance effectively gated the ReS 2 channel at a low voltage, below 2 V, through a coplanar gate. The contact resistance of the ion gel-gated ReS 2 transistors with graphene electrodes decreased dramatically compared with the SiO 2 -devices prepared with Cr electrodes. The resulting transistors exhibited good device performances, including a maximum electron mobility of 0.9 cm 2 /(V s) and an on/off current ratio exceeding 10 4 . NMOS logic devices, such as NOT, NAND, and NOR gates, were assembled using the resulting transistors as a proof of concept demonstration of the applicability of the devices to complex logic circuits. The large-area synthesis of ReS 2 semiconductors and graphene electrodes and their applications in logic devices open up new opportunities for realizing future flexible electronics based on 2D nanomaterials.

Dynamic Observation of Brain-Like Learning in a Ferroelectric Synapse Device

NASA Astrophysics Data System (ADS)

Nishitani, Yu; Kaneko, Yukihiro; Ueda, Michihito; Fujii, Eiji; Tsujimura, Ayumu

2013-04-01

A brain-like learning function was implemented in an electronic synapse device using a ferroelectric-gate field effect transistor (FeFET). The FeFET was a bottom-gate type FET with a ZnO channel and a ferroelectric Pb(Zr,Ti)O3 (PZT) gate insulator. The synaptic weight, which is represented by the channel conductance of the FeFET, is updated by applying a gate voltage through a change in the ferroelectric polarization in the PZT. A learning function based on the symmetric spike-timing dependent synaptic plasticity was implemented in the synapse device using the multilevel weight update by applying a pulse gate voltage. The dynamic weighting and learning behavior in the synapse device was observed as a change in the membrane potential in a spiking neuron circuit.

3D gate-all-around bandgap-engineered SONOS flash memory in vertical silicon pillar with metal gate

NASA Astrophysics Data System (ADS)

Oh, Jae-Sub; Yang, Seong-Dong; Lee, Sang-Youl; Kim, Young-Su; Kang, Min-Ho; Lim, Sung-Kyu; Lee, Hi-Deok; Lee, Ga-Won

2013-08-01

In this paper, a gate-all-around bandgap-engineered silicon-oxide-nitride-oxide-silicon device with a vertical silicon pillar structure and a Ti metal gate are demonstrated for a potential solution to overcome the scaling-down of flash memory device. The devices were fabricated using CMOS-compatible technology and exhibited well-behaved memory characteristics in terms of the program/erase window, retention, and endurance properties. Moreover, the integration of the Ti metal gate demonstrated a significant improvement in the erase characteristics due to the efficient suppression of the electron back tunneling through the blocking oxide.

Analysis of source/drain engineered 22nm FDSOI using high-k spacers

NASA Astrophysics Data System (ADS)

Malviya, Abhishek Kumar; Chauhan, R. K.

2018-04-01

While looking at the current classical scaling of devices there are lots of short channel effects come into consideration. In this paper, a novel device structure is proposed that is an improved structure of Modified Source(MS) FDSOI in terms of better electrical performance, on current and reduced off state leakage current with a higher Ion/Ioff ratio that helps in fast switching of low power nano electronic devices. Proposed structure has Modified drain and source regions with two different type to doping profile at 22nm gate length. In the upper part of engineered region (MD and MS) the doping concentration is kept high and less in the lower region. The purpose was to achieve low parasitic capacitance in source and drain region by reducing doping concentration [1].

Terahertz amplification in RTD-gated HEMTs with a grating-gate wave coupling topology

NASA Astrophysics Data System (ADS)

Condori Quispe, Hugo O.; Encomendero-Risco, Jimy J.; Xing, Huili Grace; Sensale-Rodriguez, Berardi

2016-08-01

We theoretically analyze the operation of a terahertz amplifier consisting of a resonant-tunneling-diode gated high-electron-mobility transistor (RTD-gated HEMT) in a grating-gate topology. In these devices, the key element enabling substantial power gain is the efficient coupling of terahertz waves into and out of plasmons in the RTD-gated HEMT channel, i.e., the gain medium, via the grating-gate itself, part of the active device, rather than by an external antenna structure as discussed in previous works, therefore potentially enabling terahertz amplification with associated power gains >40 dB.

Terahertz amplification in RTD-gated HEMTs with a grating-gate wave coupling topology

DOE Office of Scientific and Technical Information (OSTI.GOV)

Condori Quispe, Hugo O.; Sensale-Rodriguez, Berardi; Encomendero-Risco, Jimy J.

2016-08-08

We theoretically analyze the operation of a terahertz amplifier consisting of a resonant-tunneling-diode gated high-electron-mobility transistor (RTD-gated HEMT) in a grating-gate topology. In these devices, the key element enabling substantial power gain is the efficient coupling of terahertz waves into and out of plasmons in the RTD-gated HEMT channel, i.e., the gain medium, via the grating-gate itself, part of the active device, rather than by an external antenna structure as discussed in previous works, therefore potentially enabling terahertz amplification with associated power gains >40 dB.

Dual-gate GaAs FET switches

NASA Astrophysics Data System (ADS)

Vorhaus, J. L.; Fabian, W.; Ng, P. B.; Tajima, Y.

1981-02-01

A set of multi-pole, multi-throw switch devices consisting of dual-gate GaAs FET's is described. Included are single-pole, single-throw (SPST), double-pole, double-throw (DPDT), and single-pole four-throw (SP4T) switches. Device fabrication and measurement techniques are discussed. The device models for these switches were based on an equivalent circuit of a dual-gate FET. The devices were found to have substantial gain in X-band and low Ku-band.

Monolithic integration of a MOSFET with a MEMS device

DOEpatents

Bennett, Reid; Draper, Bruce

2003-01-01

An integrated microelectromechanical system comprises at least one MOSFET interconnected to at least one MEMS device on a common substrate. A method for integrating the MOSFET with the MEMS device comprises fabricating the MOSFET and MEMS device monolithically on the common substrate. Conveniently, the gate insulator, gate electrode, and electrical contacts for the gate, source, and drain can be formed simultaneously with the MEMS device structure, thereby eliminating many process steps and materials. In particular, the gate electrode and electrical contacts of the MOSFET and the structural layers of the MEMS device can be doped polysilicon. Dopant diffusion from the electrical contacts is used to form the source and drain regions of the MOSFET. The thermal diffusion step for forming the source and drain of the MOSFET can comprise one or more of the thermal anneal steps to relieve stress in the structural layers of the MEMS device.

Air-gating and chemical-gating in transistors and sensing devices made from hollow TiO2 semiconductor nanotubes

NASA Astrophysics Data System (ADS)

Alivov, Yahya; Funke, Hans; Nagpal, Prashant

2015-07-01

Rapid miniaturization of electronic devices down to the nanoscale, according to Moore’s law, has led to some undesirable effects like high leakage current in transistors, which can offset additional benefits from scaling down. Development of three-dimensional transistors, by spatial extension in the third dimension, has allowed higher contact area with a gate electrode and better control over conductivity in the semiconductor channel. However, these devices do not utilize the large surface area and interfaces for new electronic functionality. Here, we demonstrate air gating and chemical gating in hollow semiconductor nanotube devices and highlight the potential for development of novel transistors that can be modulated using channel bias, gate voltage, chemical composition, and concentration. Using chemical gating, we reversibly altered the conductivity of nanoscaled semiconductor nanotubes (10-500 nm TiO2 nanotubes) by six orders of magnitude, with a tunable rectification factor (ON/OFF ratio) ranging from 1-106. While demonstrated air- and chemical-gating speeds were slow here (˜seconds) due to the mechanical-evacuation rate and size of our chamber, the small nanoscale volume of these hollow semiconductors can enable much higher switching speeds, limited by the rate of adsorption/desorption of molecules at semiconductor interfaces. These chemical-gating effects are completely reversible, additive between different chemical compositions, and can enable semiconductor nanoelectronic devices for ‘chemical transistors’, ‘chemical diodes’, and very high-efficiency sensing applications.

On-chip surface modified nanostructured ZnO as functional pH sensors

NASA Astrophysics Data System (ADS)

Zhang, Qing; Liu, Wenpeng; Sun, Chongling; Zhang, Hao; Pang, Wei; Zhang, Daihua; Duan, Xuexin

2015-09-01

Zinc oxide (ZnO) nanostructures are promising candidates as electronic components for biological and chemical applications. In this study, ZnO ultra-fine nanowire (NW) and nanoflake (NF) hybrid structures have been prepared by Au-assisted chemical vapor deposition (CVD) under ambient pressure. Their surface morphology, lattice structures, and crystal orientation were investigated by scanning electron microscopy (SEM), x-ray diffraction (XRD), and transmission electron microscopy (TEM). Two types of ZnO nanostructures were successfully integrated as gate electrodes in extended-gate field-effect transistors (EGFETs). Due to the amphoteric properties of ZnO, such devices function as pH sensors. We found that the ultra-fine NWs, which were more than 50 μm in length and less than 100 nm in diameter, performed better in the pH sensing process than NW-NF hybrid structures because of their higher surface-to-volume ratio, considering the Nernst equation and the Gouy-Chapman-Stern model. Furthermore, the surface coating of (3-Aminopropyl)triethoxysilane (APTES) protects ZnO nanostructures in both acidic and alkaline environments, thus enhancing the device stability and extending its pH sensing dynamic range.

ALD Al2O3 passivation of Lg = 100 nm metamorphic InAlAs/InGaAs HEMTs with Si-doped Schottky layers on GaAs substrates

NASA Astrophysics Data System (ADS)

Sun, Bing; Chang, Hudong; Wang, Shengkai; Niu, Jiebin; Liu, Honggang

2017-12-01

In0.52Al0.48As/In0.7Ga0.3As metamorphic high-electron-mobility transistors (mHEMTs) on GaAs substrates have been demonstrated. The devices feature an epitaxial structure with Si-doped InP/In0.52Al0.48As Schottky layers, together with an atomic layer deposition (ALD) Al2O3 passivation process. In comparison to the GaAs mHEMTs with plasma enhanced chemical vapor deposition (PECVD) SiN passivation, the devices with ALD Al2O3 passivation exhibit more than one order of magnitude lower gate leakage current (Jg) and much lower contact resistance (RC) and specific contact resistivity (ρC). 100-nm gate length (Lg) In0.52Al0.48As/In0.7Ga0.3As mHEMTs with Si-doped InP/In0.52Al0.48As Schottky layers and ALD Al2O3 passivation exhibit excellent DC and RF characteristics, such as a maximum oscillation frequency (fmax) of 388.2 GHz.

Performance limits of tunnel transistors based on mono-layer transition-metal dichalcogenides

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jiang, Xiang-Wei, E-mail: xwjiang@semi.ac.cn; Li, Shu-Shen; Synergetic Innovation Center of Quantum Information and Quantum Physics, University of Science and Technology of China, Hefei, Anhui 230026

2014-05-12

Performance limits of tunnel field-effect transistors based on mono-layer transition metal dichalcogenides are investigated through numerical quantum mechanical simulations. The atomic mono-layer nature of the devices results in a much smaller natural length λ, leading to much larger electric field inside the tunneling diodes. As a result, the inter-band tunneling currents are found to be very high as long as ultra-thin high-k gate dielectric is possible. The highest on-state driving current is found to be close to 600 μA/μm at V{sub g} = V{sub d} = 0.5 V when 2 nm thin HfO{sub 2} layer is used for gate dielectric, outperforming most of the conventional semiconductor tunnelmore » transistors. In the five simulated transition-metal dichalcogenides, mono-layer WSe{sub 2} based tunnel field-effect transistor shows the best potential. Deep analysis reveals that there is plenty room to further enhance the device performance by either geometry, alloy, or strain engineering on these mono-layer materials.« less

Dynamic Wavelength-Tunable Photodetector Using Subwavelength Graphene Field-Effect Transistors

DOE PAGES

Léonard, François; Spataru, Catalin D.; Goldflam, Michael; ...

2017-04-04

The holy grail of photodetector technology is dynamic wavelength tunability. Because of its atomic thickness and unique properties, graphene opens up new paradigms to realize this concept, but so far this has been elusive experimentally. We employ detailed quantum transport modeling of photocurrent in graphene field-effect transistors (including realistic electromagnetic fields) to show that wavelength tunability is possible by dynamically changing the gate voltage. We also reveal the phenomena that govern the behavior of this type of device and show significant departure from the simple expectations based on vertical transitions. We find strong focusing of the electromagnetic fields at themore » contact edges over the same length scale as the band-bending. Both of these spatially-varying potentials lead to an enhancement of non-vertical optical transitions, which dominate even in the absence of phonon or impurity scattering. Furthermore, we show that the vanishing density of states near the Dirac point leads to contact blocking and a gate-dependent modulation of the photocurrent. Several of the effects discussed here should be applicable to a broad range of one- and two-dimensional materials and devices.« less

Dynamic Wavelength-Tunable Photodetector Using Subwavelength Graphene Field-Effect Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Léonard, François; Spataru, Catalin D.; Goldflam, Michael

The holy grail of photodetector technology is dynamic wavelength tunability. Because of its atomic thickness and unique properties, graphene opens up new paradigms to realize this concept, but so far this has been elusive experimentally. We employ detailed quantum transport modeling of photocurrent in graphene field-effect transistors (including realistic electromagnetic fields) to show that wavelength tunability is possible by dynamically changing the gate voltage. We also reveal the phenomena that govern the behavior of this type of device and show significant departure from the simple expectations based on vertical transitions. We find strong focusing of the electromagnetic fields at themore » contact edges over the same length scale as the band-bending. Both of these spatially-varying potentials lead to an enhancement of non-vertical optical transitions, which dominate even in the absence of phonon or impurity scattering. Furthermore, we show that the vanishing density of states near the Dirac point leads to contact blocking and a gate-dependent modulation of the photocurrent. Several of the effects discussed here should be applicable to a broad range of one- and two-dimensional materials and devices.« less

Lithium ion intercalation in thin crystals of hexagonal TaSe2 gated by a polymer electrolyte

NASA Astrophysics Data System (ADS)

Wu, Yueshen; Lian, Hailong; He, Jiaming; Liu, Jinyu; Wang, Shun; Xing, Hui; Mao, Zhiqiang; Liu, Ying

2018-01-01

Ionic liquid gating has been used to modify the properties of layered transition metal dichalcogenides (TMDCs), including two-dimensional (2D) crystals of TMDCs used extensively recently in the device work, which has led to observations of properties not seen in the bulk. The main effect comes from the electrostatic gating due to the strong electric field at the interface. In addition, ionic liquid gating also leads to ion intercalation when the ion size of the gate electrolyte is small compared to the interlayer spacing of TMDCs. However, the microscopic processes of ion intercalation have rarely been explored in layered TMDCs. Here, we employed a technique combining photolithography device fabrication and electrical transport measurements on the thin crystals of hexagonal TaSe2 using multiple channel devices gated by a polymer electrolyte LiClO4/Polyethylene oxide (PEO). The gate voltage and time dependent source-drain resistances of these thin crystals were used to obtain information on the intercalation process, the effect of ion intercalation, and the correlation between the ion occupation of allowed interstitial sites and the device characteristics. We found a gate voltage controlled modulation of the charge density waves and a scattering rate of charge carriers. Our work suggests that ion intercalation can be a useful tool for layered materials engineering and 2D crystal device design.

Theoretical investigation of performance of armchair graphene nanoribbon field effect transistors

NASA Astrophysics Data System (ADS)

Hur, Ji-Hyun; Kim, Deok-Kee

2018-05-01

In this paper, we theoretically investigate the highest possible expected performance for graphene nanoribbon field effect transistors (GNRFETs) for a wide range of operation voltages and device structure parameters, such as the width of the graphene nanoribbon and gate length. We formulated a self-consistent, non-equilibrium Green’s function method in conjunction with the Poisson equation and modeled the operation of nanometer sized GNRFETs, of which GNR channels have finite bandgaps so that the GNRFET can operate as a switch. We propose a metric for competing with the current silicon CMOS high performance or low power devices and explain that this can vary greatly depending on the GNRFET structure parameters.

Theoretical investigation of performance of armchair graphene nanoribbon field effect transistors.

PubMed

Hur, Ji-Hyun; Kim, Deok-Kee

2018-05-04

In this paper, we theoretically investigate the highest possible expected performance for graphene nanoribbon field effect transistors (GNRFETs) for a wide range of operation voltages and device structure parameters, such as the width of the graphene nanoribbon and gate length. We formulated a self-consistent, non-equilibrium Green's function method in conjunction with the Poisson equation and modeled the operation of nanometer sized GNRFETs, of which GNR channels have finite bandgaps so that the GNRFET can operate as a switch. We propose a metric for competing with the current silicon CMOS high performance or low power devices and explain that this can vary greatly depending on the GNRFET structure parameters.

Analysis of a Memory Device Failure

NASA Technical Reports Server (NTRS)

Nicolas, David P.; Devaney, John; Gores, Mark; Dicken, Howard

1998-01-01

The recent failure of a vintage memory device presented a unique challenge to failure analysts. Normally device layouts, fabrication parameters and other technical information were available to assist the analyst in the analysis. However, this device was out of production for many years and the manufacturer was no longer in business, so the information was not available. To further complicate this analysis, the package leads were all but removed making additional electrical testing difficult. Under these conditions, new and innovative methods were used to analyze the failure. The external visual exam, radiography, PIND, and leak testing were performed with nominal results. Since electrical testing was precluded by the short lead lengths, the device was delidded to expose the internal structures for microscopic examination. No failure mechanism was identified. The available electrical data suggested an ESD or low level EOS type mechanism which left no visible surface damage. Due to parallel electrical paths, electrical probing on the chip failed to locate the failure site. Two non-destructive Scanning Electron Microscopy techniques, CIVA (Charge Induced Voltage Alteration) and EBIC (Electron Beam Induced Current), and a liquid crystal decoration technique which detects localized heating were employed to aid in the analysis. CIVA and EBIC isolated two faults in the input circuitry, and the liquid crystal technique further localized two hot spots in regions on two input gates. Removal of the glassivation and metallization revealed multiple failure sites located in the gate oxide of two input transistors suggesting machine (testing) induced damage.

Radiation hardening of MOS devices by boron. [for stabilizing gate threshold potential of field effect device

NASA Technical Reports Server (NTRS)

Danchenko, V. (Inventor)

1974-01-01

A technique is described for radiation hardening of MOS devices and specifically for stabilizing the gate threshold potential at room temperature of a radiation subjected MOS field-effect device with a semiconductor substrate, an insulating layer of oxide on the substrate, and a gate electrode disposed on the insulating layer. The boron is introduced within a layer of the oxide of about 100 A-300 A thickness immediately adjacent the semiconductor-insulator interface. The concentration of boron in the oxide layer is preferably maintained on the order of 10 to the 18th power atoms/cu cm. The technique serves to reduce and substantially annihilate radiation induced positive gate charge accumulations.

Impact of gate engineering in enhancement mode n++GaN/InAlN/AlN/GaN HEMTs

NASA Astrophysics Data System (ADS)

Adak, Sarosij; Swain, Sanjit Kumar; Rahaman, Hafizur; Sarkar, Chandan Kumar

2016-12-01

This paper illustrate the effect of gate material engineering on the performance of enhancement mode n++GaN/InAlN/AlN/GaN high electron mobility transistors (HEMTs). A comparative analysis of key device parameters is discussed for the Triple Material Gate (TMG), Dual Material Gate (DMG) and the Single Material Gate (SMG) structure HEMTs by considering the same device dimensions. The simulation results shows that an significant improvement is noticed in the key analysis parameters such as drain current (Id), transconductance (gm), cut off frequency (fT), RF current gain, maximum cut off frequency (fmax) and RF power gain of the gate material engineered devices with respect to SMG normally off n++GaN/InAlN/AlN/GaN HEMTs. This improvement is due to the existence of the perceivable step in the surface potential along the channel which successfully screens the drain potential variation in the source side of the channel for the gate engineering devices. The analysis suggested that the proposed TMG and DMG engineered structure enhancement mode n++GaN/InAlN/AlN/GaN HEMTs can be considered as a potential device for future high speed, microwave and digital application.

Improvement in top-gate MoS2 transistor performance due to high quality backside Al2O3 layer

NASA Astrophysics Data System (ADS)

Bolshakov, Pavel; Zhao, Peng; Azcatl, Angelica; Hurley, Paul K.; Wallace, Robert M.; Young, Chadwin D.

2017-07-01

A high quality Al2O3 layer is developed to achieve high performance in top-gate MoS2 transistors. Compared with top-gate MoS2 field effect transistors on a SiO2 layer, the intrinsic mobility and subthreshold slope were greatly improved in high-k backside layer devices. A forming gas anneal is found to enhance device performance due to a reduction in the charge trap density of the backside dielectric. The major improvements in device performance are ascribed to the forming gas anneal and the high-k dielectric screening effect of the backside Al2O3 layer. Top-gate devices built upon these stacks exhibit a near-ideal subthreshold slope of ˜69 mV/dec and a high Y-Function extracted intrinsic carrier mobility (μo) of 145 cm2/V.s, indicating a positive influence on top-gate device performance even without any backside bias.

A novel hetero-material gate-underlap electrically doped TFET for improving DC/RF and ambipolar behaviour

NASA Astrophysics Data System (ADS)

Yadav, Shivendra; Sharma, Dheeraj; Chandan, Bandi Venkata; Aslam, Mohd; Soni, Deepak; Sharma, Neeraj

2018-05-01

In this article, the impact of gate-underlap with hetero material (low band gap) has been investigated in terms of DC and Analog/RF parameters by proposed device named as hetero material gate-underlap electrically doped TFET (HM-GUL-ED-TFET). Gate-underlap resolves the problem of ambipolarity, gate leakage current (Ig) and slightly improves the gate to drain capacitance, but DC performance is almost unaffected. Further, the use of low band gap material (Si0.5 Ge) in proposed device causes a drastic improvement in the DC as well as RF figures of merit. We have investigated the Si0.5 Ge as a suitable candidate among different low band gap materials. In addition, the sensitivity of gate-underlap in terms of gate to drain inversion and parasitic capacitances has been studied for HM-GUL-ED-TFET. Further, relatively it is observed that gate-underlap is a better way than drain-underlap in the proposed structure to improve Analog/RF performances without degrading the DC parameters of device. Additionally, hetero-junction alignment analysis has been done for fabrication feasibility.

Investigation of injection molding of orthogonal fluidic connector for microfluidic devices

NASA Astrophysics Data System (ADS)

Xu, Zheng; Cao, Dong; Zhao, Wei; Song, Man-cang; Liu, Jun-shan

2017-02-01

Orthogonal fluidic connections are essential for developing multilayered microfluidic devices. At present, most orthogonal connectors are realized by a horizontal channel and a vertical channel in different plates. Therefore, some extra alignment and adhesion processes for precise plate assembly are required. In this paper, the method of injection molding is proposed to make a one-body-type orthogonal connector in a single plastic plate. The connector was composed of a cantilevered tube and the other in the substrate. An injection mold was developed in which a side core-pulling mechanism and an ejection mechanism of push-pipes were combined to form the mold for an orthogonal connector. Both the type and the location of gate were optimized for the mold. The results showed that the fan gate in the middle position of the plate was the most suitable in term of both defect control and practicability. The effect of melt temperature was numerically investigated and then verified experimentally. With the optimized parameters, the relative length and the relative wall thickness of a cantilevered tube in the plastic part can reach 98.89% and 99.80%, respectively. Furthermore, using the plastic part as a cover plate, a three-layer plastic microfluidic device was conveniently fabricated for electrochemical detection.

Fabrication of one-transistor-capacitor structure of nonvolatile TFT ferroelectric RAM devices using Ba(Zr0.1Ti0.9)O3 gated oxide film.

PubMed

Yang, Cheng-Fu; Chen, Kai-Huang; Chen, Ying-Chung; Chang, Ting-Chang

2007-09-01

In this study, the Ba(Zr0.1Ti0.9)O3 (BZ1T9) thin films have been well deposited on the Pt/Ti/SiO2/Si substrate. The optimum radio frequency (RF) deposition parameters are developed, and the BZ1T9 thin films deposition at the optimum parameters have the maximum capacitance and dielectric constant of 4.4 nF and 190. As the applied voltage is increased to 8 V, the remnant polarization and coercive field of BZ1T9 thin films are about 4.5 microC/cm2 and 80 kV/cm. The counterclockwise current hysteresis and memory window of n-channel thin-film transistor property are observed, and that can be used to indicate the switching of ferroelectric polarization of BZ1T9 thin films. One-transistor-capacitor (1TC) structure of BZ1T9 ferroelectric random access memory device using bottom-gate amorphous silicon thin-film transistor was desirable because of the smaller size and better sensitivity. The BZ1T9 ferroelectric RAM devices with channel width = 40 microm and channel length = 8 microm has been successfully fabricated and the ID-VG transfer characteristics also are investigated in this study.

A quantum wave based compact modeling approach for the current in ultra-short DG MOSFETs suitable for rapid multi-scale simulations

NASA Astrophysics Data System (ADS)

Hosenfeld, Fabian; Horst, Fabian; Iñíguez, Benjamín; Lime, François; Kloes, Alexander

2017-11-01

Source-to-drain (SD) tunneling decreases the device performance in MOSFETs falling below the 10 nm channel length. Modeling quantum mechanical effects including SD tunneling has gained more importance specially for compact model developers. The non-equilibrium Green's function (NEGF) has become a state-of-the-art method for nano-scaled device simulation in the past years. In the sense of a multi-scale simulation approach it is necessary to bridge the gap between compact models with their fast and efficient calculation of the device current, and numerical device models which consider quantum effects of nano-scaled devices. In this work, an NEGF based analytical model for nano-scaled double-gate (DG) MOSFETs is introduced. The model consists of a closed-form potential solution of a classical compact model and a 1D NEGF formalism for calculating the device current, taking into account quantum mechanical effects. The potential calculation omits the iterative coupling and allows the straightforward current calculation. The model is based on a ballistic NEGF approach whereby backscattering effects are considered as second order effect in a closed-form. The accuracy and scalability of the non-iterative DG MOSFET model is inspected in comparison with numerical NanoMOS TCAD data for various channel lengths. With the help of this model investigations on short-channel and temperature effects are performed.

Physics. Creating and probing electron whispering-gallery modes in graphene.

PubMed

Zhao, Yue; Wyrick, Jonathan; Natterer, Fabian D; Rodriguez-Nieva, Joaquin F; Lewandowski, Cyprian; Watanabe, Kenji; Taniguchi, Takashi; Levitov, Leonid S; Zhitenev, Nikolai B; Stroscio, Joseph A

2015-05-08

The design of high-finesse resonant cavities for electronic waves faces challenges due to short electron coherence lengths in solids. Complementing previous approaches to confine electronic waves by carefully positioned adatoms at clean metallic surfaces, we demonstrate an approach inspired by the peculiar acoustic phenomena in whispering galleries. Taking advantage of graphene's gate-tunable light-like carriers, we create whispering-gallery mode (WGM) resonators defined by circular pn junctions, induced by a scanning tunneling probe. We can tune the resonator size and the carrier concentration under the probe in a back-gated graphene device over a wide range. The WGM-type confinement and associated resonances are a new addition to the quantum electron-optics toolbox, paving the way to develop electronic lenses and resonators. Copyright © 2015, American Association for the Advancement of Science.

Electrothermal DC characterization of GaN on Si MOS-HEMTs

NASA Astrophysics Data System (ADS)

Rodríguez, R.; González, B.; García, J.; Núñez, A.

2017-11-01

DC characteristics of AlGaN/GaN on Si single finger MOS-HEMTs, for different gate geometries, have been measured and numerically simulated with substrate temperatures up to 150 °C. Defect density, depending on gate width, and thermal resistance, depending additionally on temperature, are extracted from transfer characteristics displacement and the AC output conductance method, respectively, and modeled for numerical simulations with Atlas. The thermal conductivity degradation in thin films is also included for accurate simulation of the heating response. With an appropriate methodology, the internal model parameters for temperature dependencies have been established. The numerical simulations show a relative error lower than 4.6% overall, for drain current and channel temperature behavior, and account for the measured device temperature decrease with the channel length increase as well as with the channel width reduction, for a set bias.

Comparative study of CAVET with dielectric and p-GaN gate and Mg ion-implanted current blocking layer

NASA Astrophysics Data System (ADS)

Mandal, Saptarshi; Agarwal, Anchal; Ahmadi, Elaheh; Mahadeva Bhat, K.; Laurent, Matthew A.; Keller, Stacia; Chowdhury, Srabanti

2017-08-01

In this work, a study of two different types of current aperture vertical electron transistor (CAVET) with ion-implanted blocking layer are presented. The device fabrication and performance limitation of a CAVET with a dielectric gate is discussed, and the breakdown limiting structure is evaluated using on-wafer test structures. The gate dielectric limited the device breakdown to 50V, while the blocking layer was able to withstand over 400V. To improve the device performance, an alternative CAVET structure with a p-GaN gate instead of dielectric is designed and realized. The pGaN gated CAVET structure increased the breakdown voltage to over 400V. Measurement of test structures on the wafer showed the breakdown was limited by the blocking layer instead of the gate p-n junction.

Impact of gate work-function on memory characteristics in Al2O3/HfOx/Al2O3/graphene charge-trap memory devices

NASA Astrophysics Data System (ADS)

Lee, Sejoon; Song, Emil B.; Kim, Sungmin; Seo, David H.; Seo, Sunae; Won Kang, Tae; Wang, Kang L.

2012-01-01

Graphene-based non-volatile memory devices composed of a single-layer graphene channel and an Al2O3/HfOx/Al2O3 charge-storage layer exhibit memory functionality. The impact of the gate material's work-function (Φ) on the memory characteristics is investigated using different types of metals [Ti (ΦTi = 4.3 eV) and Ni (ΦNi = 5.2 eV)]. The ambipolar carrier conduction of graphene results in an enlargement of memory window (ΔVM), which is ˜4.5 V for the Ti-gate device and ˜9.1 V for the Ni-gate device. The increase in ΔVM is attributed to the change in the flat-band condition and the suppression of electron back-injection within the gate stack.

Front and backside processed thin film electronic devices

DOEpatents

Evans, Paul G [Madison, WI; Lagally, Max G [Madison, WI; Ma, Zhenqiang [Middleton, WI; Yuan, Hao-Chih [Lakewood, CO; Wang, Guogong [Madison, WI; Eriksson, Mark A [Madison, WI

2012-01-03

This invention provides thin film devices that have been processed on their front- and backside. The devices include an active layer that is sufficiently thin to be mechanically flexible. Examples of the devices include back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Leakage current conduction in metal gate junctionless nanowire transistors

NASA Astrophysics Data System (ADS)

Oproglidis, T. A.; Karatsori, T. A.; Barraud, S.; Ghibaudo, G.; Dimitriadis, C. A.

2017-05-01

In this paper, the experimental off-state drain leakage current behavior is systematically explored in n- and p-channel junctionless nanowire transistors with HfSiON/TiN/p+-polysilicon gate stack. The analysis of the drain leakage current is based on experimental data of the gate leakage current. It has been shown that the off-state drain leakage current in n-channel devices is negligible, whereas in p-channel devices it is significant and dramatically increases with drain voltage. The overall results indicate that the off-state drain leakage current in p-channel devices is mainly due to trap-assisted Fowler-Nordheim tunneling of electrons through the gate oxide of electrons from the metal gate to the silicon layer near the drain region.

Error-Transparent Quantum Gates for Small Logical Qubit Architectures

NASA Astrophysics Data System (ADS)

Kapit, Eliot

2018-02-01

One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016), 10.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both. The effective logical gate error rate in these models displays superlinear error reduction with linear increases in single qubit lifetime, proving that passive error correction is capable of increasing gate fidelity. Using a standard phenomenological noise model for superconducting qubits, we demonstrate a realistic, universal one- and two-qubit gate set for the VSLQ, with error rates an order of magnitude lower than those for same-duration operations on single qubits or pairs of qubits. These developments further suggest that incorporating small logical qubits into a measurement based code could substantially improve code performance.

Open-Gated pH Sensor Fabricated on an Undoped-AlGaN/GaN HEMT Structure

PubMed Central

Abidin, Mastura Shafinaz Zainal; Hashim, Abdul Manaf; Sharifabad, Maneea Eizadi; Rahman, Shaharin Fadzli Abd; Sadoh, Taizoh

2011-01-01

The sensing responses in aqueous solution of an open-gated pH sensor fabricated on an AlGaN/GaN high-electron-mobility-transistor (HEMT) structure are investigated. Under air-exposed ambient conditions, the open-gated undoped AlGaN/GaN HEMT only shows the presence of a linear current region. This seems to show that very low Fermi level pinning by surface states exists in the undoped AlGaN/GaN sample. In aqueous solution, typical current-voltage (I-V) characteristics with reasonably good gate controllability are observed, showing that the potential of the AlGaN surface at the open-gated area is effectively controlled via aqueous solution by the Ag/AgCl gate electrode. The open-gated undoped AlGaN/GaN HEMT structure is capable of distinguishing pH level in aqueous electrolytes and exhibits linear sensitivity, where high sensitivity of 1.9 mA/pH or 3.88 mA/mm/pH at drain-source voltage, VDS = 5 V is obtained. Due to the large leakage current where it increases with the negative gate voltage, Nernstian like sensitivity cannot be determined as commonly reported in the literature. This large leakage current may be caused by the technical factors rather than any characteristics of the devices. Surprisingly, although there are some imperfections in the device preparation and measurement, the fabricated devices work very well in distinguishing the pH levels. Suppression of current leakage by improving the device preparation is likely needed to improve the device performance. The fabricated device is expected to be suitable for pH sensing applications. PMID:22163786

Operation and biasing for single device equivalent to CMOS

DOEpatents

Welch, James D.

2001-01-01

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

Porous Diblock Copolymer Thin Films in High-Performance Semiconductor Microelectronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Black, C.T.

2011-02-01

The engine fueling more than 40 years of performance improvements in semiconductor integrated circuits (ICs) has been industry's ability to pattern circuit elements at ever-higher resolution and with ever-greater precision. Steady advances in photolithography - the process wherein ultraviolet light chemically changes a photosensitive polymer resist material in order to create a latent image - have resulted in scaling of minimum printed feature sizes from tens of microns during the 1980s to sub-50 nanometer transistor gate lengths in today's state-of-the-art ICs. The history of semiconductor technology scaling as well as future technology requirements is documented in the International Technology Roadmapmore » for Semiconductors (ITRS). The progression of the semiconductor industry to the realm of nanometer-scale sizes has brought enormous challenges to device and circuit fabrication, rendering performance improvements by conventional scaling alone increasingly difficult. Most often this discussion is couched in terms of field effect transistor (FET) feature sizes such as the gate length or gate oxide thickness, however these challenges extend to many other aspects of the IC, including interconnect dimensions and pitch, device packing density, power consumption, and heat dissipation. The ITRS Technology Roadmap forecasts a difficult set of scientific and engineering challenges with no presently-known solutions. The primary focus of this chapter is the research performed at IBM on diblock copolymer films composed of polystyrene (PS) and poly(methyl-methacrylate) (PMMA) (PS-b-PMMA) with total molecular weights M{sub n} in the range of {approx}60K (g/mol) and polydispersities (PD) of {approx}1.1. These materials self assemble to form patterns having feature sizes in the range of 15-20nm. PS-b-PMMA was selected as a self-assembling patterning material due to its compatibility with the semiconductor microelectronics manufacturing infrastructure, as well as the significant body of existing research on understanding its material properties.« less

Volumetric measurement of human red blood cells by MOSFET-based microfluidic gate.

PubMed

Guo, Jinhong; Ai, Ye; Cheng, Yuanbing; Li, Chang Ming; Kang, Yuejun; Wang, Zhiming

2015-08-01

In this paper, we present a MOSFET-based (metal oxide semiconductor field-effect transistor) microfluidic gate to characterize the translocation of red blood cells (RBCs) through a gate. In the microfluidic system, the bias voltage modulated by the particles or biological cells is connected to the gate of MOSFET. The particles or cells can be detected by monitoring the MOSFET drain current instead of DC/AC-gating method across the electronic gate. Polystyrene particles with various standard sizes are utilized to calibrate the proposed device. Furthermore, RBCs from both adults and newborn blood sample are used to characterize the performance of the device in distinguishing the two types of RBCs. As compared to conventional DC/AC current modulation method, the proposed device demonstrates a higher sensitivity and is capable of being a promising platform for bioassay analysis. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Spin Transport in Nondegenerate Si with a Spin MOSFET Structure at Room Temperature

NASA Astrophysics Data System (ADS)

Sasaki, Tomoyuki; Ando, Yuichiro; Kameno, Makoto; Tahara, Takayuki; Koike, Hayato; Oikawa, Tohru; Suzuki, Toshio; Shiraishi, Masashi

2014-09-01

Spin transport in nondegenerate semiconductors is expected to pave the way to the creation of spin transistors, spin logic devices, and reconfigurable logic circuits, because room-temperature (RT) spin transport in Si has already been achieved. However, RT spin transport has been limited to degenerate Si, which makes it difficult to produce spin-based signals because a gate electric field cannot be used to manipulate such signals. Here, we report the experimental demonstration of spin transport in nondegenerate Si with a spin metal-oxide-semiconductor field-effect transistor (MOSFET) structure. We successfully observe the modulation of the Hanle-type spin-precession signals, which is a characteristic spin dynamics in nondegenerate semiconductors. We obtain long spin transport of more than 20 μm and spin rotation greater than 4π at RT. We also observe gate-induced modulation of spin-transport signals at RT. The modulation of the spin diffusion length as a function of a gate voltage is successfully observed, which we attribute to the Elliott-Yafet spin relaxation mechanism. These achievements are expected to lead to the creation of practical Si-based spin MOSFETs.

Influence of gate width on gate-channel carrier mobility in AlGaN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Yang, Ming; Ji, Qizheng; Gao, Zhiliang; Zhang, Shufeng; Lin, Zhaojun; Yuan, Yafei; Song, Bo; Mei, Gaofeng; Lu, Ziwei; He, Jihao

2017-11-01

For the fabricated AlGaN/GaN heterostructure field-effect transistors (HFETs) with different gate widths, the gate-channel carrier mobility is experimentally obtained from the measured current-voltage and capacitance-voltage curves. Under each gate voltage, the mobility gets lower with gate width increasing. Analysis shows that the phenomenon results from the polarization Coulomb field (PCF) scattering, which originates from the irregularly distributed polarization charges at the AlGaN/GaN interface. The device with a larger gate width is with a larger PCF scattering potential and a stronger PCF scattering intensity. As a function of gate width, PCF scattering potential shows a same trend with the mobility variation. And the theoretically calculated mobility values fits well with the experimentally obtained values. Varying gate widths will be a new perspective for the improvement of device characteristics by modulating the gate-channel carrier mobility.

Extraction of the gate capacitance coupling coefficient in floating gate non-volatile memories: Statistical study of the effect of mismatching between floating gate memory and reference transistor in dummy cell extraction methods

NASA Astrophysics Data System (ADS)

Rafhay, Quentin; Beug, M. Florian; Duane, Russell

2007-04-01

This paper presents an experimental comparison of dummy cell extraction methods of the gate capacitance coupling coefficient for floating gate non-volatile memory structures from different geometries and technologies. These results show the significant influence of mismatching floating gate devices and reference transistors on the extraction of the gate capacitance coupling coefficient. In addition, it demonstrates the accuracy of the new bulk bias dummy cell extraction method and the importance of the β function, introduced recently in [Duane R, Beug F, Mathewson A. Novel capacitance coupling coefficient measurement methodology for floating gate non-volatile memory devices. IEEE Electr Dev Lett 2005;26(7):507-9], to determine matching pairs of floating gate memory and reference transistor.

Thick layered semiconductor devices with water top-gates: High on-off ratio field-effect transistors and aqueous sensors.

PubMed

Huang, Yuan; Sutter, Eli; Wu, Liangmei; Xu, Hong; Bao, Lihong; Gao, Hong-Jun; Zhou, Xingjiang; Sutter, Peter

2018-06-21

Layered semiconductors show promise as channel materials for field-effect transistors (FETs). Usually, such devices incorporate solid back or top gate dielectrics. Here, we explore de-ionized (DI) water as a solution top gate for field-effect switching of layered semiconductors including SnS2, MoS2, and black phosphorus. The DI water gate is easily fabricated, can sustain rapid bias changes, and its efficient coupling to layered materials provides high on-off current ratios, near-ideal sub-threshold swing, and enhanced short-channel behavior even for FETs with thick, bulk-like channels where such control is difficult to realize with conventional back-gating. Screening by the high-k solution gate eliminates hysteresis due to surface and interface trap states and substantially enhances the field-effect mobility. The onset of water electrolysis sets the ultimate limit to DI water gating at large negative gate bias. Measurements in this regime show promise for aqueous sensing, demonstrated here by the amperometric detection of glucose in aqueous solution. DI water gating of layered semiconductors can be harnessed in research on novel materials and devices, and it may with further development find broad applications in microelectronics and sensing.

Reconfigurable Diodes Based on Vertical WSe2 Transistors with van der Waals Bonded Contacts.

PubMed

Avsar, Ahmet; Marinov, Kolyo; Marin, Enrique Gonzalez; Iannaccone, Giuseppe; Watanabe, Kenji; Taniguchi, Takashi; Fiori, Gianluca; Kis, Andras

2018-05-01

New device concepts can increase the functionality of scaled electronic devices, with reconfigurable diodes allowing the design of more compact logic gates being one of the examples. In recent years, there has been significant interest in creating reconfigurable diodes based on ultrathin transition metal dichalcogenide crystals due to their unique combination of gate-tunable charge carriers, high mobility, and sizeable band gap. Thanks to their large surface areas, these devices are constructed under planar geometry and the device characteristics are controlled by electrostatic gating through rather complex two independent local gates or ionic-liquid gating. In this work, similar reconfigurable diode action is demonstrated in a WSe 2 transistor by only utilizing van der Waals bonded graphene and Co/h-BN contacts. Toward this, first the charge injection efficiencies into WSe 2 by graphene and Co/h-BN contacts are characterized. While Co/h-BN contact results in nearly Schottky-barrier-free charge injection, graphene/WSe 2 interface has an average barrier height of ≈80 meV. By taking the advantage of the electrostatic transparency of graphene and the different work-function values of graphene and Co/h-BN, vertical devices are constructed where different gate-tunable diode actions are demonstrated. This architecture reveals the opportunities for exploring new device concepts. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Design and fabrication of high-performance diamond triple-gate field-effect transistors

PubMed Central

Liu, Jiangwei; Ohsato, Hirotaka; Wang, Xi; Liao, Meiyong; Koide, Yasuo

2016-01-01

The lack of large-area single-crystal diamond wafers has led us to downscale diamond electronic devices. Here, we design and fabricate a hydrogenated diamond (H-diamond) triple-gate metal-oxide-semiconductor field-effect transistor (MOSFET) to extend device downscaling and increase device output current. The device’s electrical properties are compared with those of planar-type MOSFETs, which are fabricated simultaneously on the same substrate. The triple-gate MOSFET’s output current (174.2 mA mm−1) is much higher than that of the planar-type device (45.2 mA mm−1), and the on/off ratio and subthreshold swing are more than 108 and as low as 110 mV dec−1, respectively. The fabrication of these H-diamond triple-gate MOSFETs will drive diamond electronic device development forward towards practical applications. PMID:27708372

Semiconductor systems utilizing materials that form rectifying junctions in both N and P-type doping regions, whether metallurgically or field induced, and methods of use

DOEpatents

Welch, James D.

2000-01-01

Disclosed are semiconductor systems, such as integrated circuits utilizing Schotky barrier and/or diffused junction technology, which semiconductor systems incorporate material(s) that form rectifying junctions in both metallurgically and/or field induced N and P-type doping regions, and methods of their use. Disclosed are Schottky barrier based inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems and which can be operated as modulators, N and P-channel MOSFETS and CMOS formed therefrom, and (MOS) gate voltage controlled rectification direction and gate voltage controlled switching devices, and use of such material(s) to block parasitic current flow pathways. Simple demonstrative five mask fabrication procedures for inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

W-band six-port network analyzer for two-port characterization of millimeter wave transistors

NASA Technical Reports Server (NTRS)

Moeller, Karl J.; Schaffner, James H.; Fetterman, Harold R.

1989-01-01

A W-band (75-100 GHz) six-port junction network analyzer was constructed from commercially available descrete waveguide components and was used for the direct two-port S-parameter measurement of active three-terminal devices. A comparison between the six-port and a down-converter-type frequency extender for a conventional network analyzer revealed the superior performance of the six-port. The application of the six-port to characterize a 0.1-micron gate-length HEMT at W-band is described, and representative results are presented.

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

NASA Astrophysics Data System (ADS)

Maheran, A. H. Afifah; Menon, P. S.; Ahmad, I.; Shaari, S.; Faizah, Z. A. Noor

2015-04-01

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (ILEAK) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO2) and tungsten silicide (WSix). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum ILEAK where the maximum predicted ILEAK value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/µm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device's leakage current. The absolute process parameters combination results in ILEAK mean value of 3.96821 nA/µm where is far lower than the predicted value.

Evaluation of biasing and protection circuitry components for cryogenic MMIC low-noise amplifiers

NASA Astrophysics Data System (ADS)

Lamb, James W.

2014-05-01

Millimeter-wave integrated circuits with gate lengths as short as 35 nm are demonstrating extremely low-noise performance, especially when cooled to cryogenic temperatures. These operate at low voltages and are susceptible to damage from electrostatic discharge and improper biasing, as well as being sensitive to low-level interference. Designing a protection circuit for low voltages and temperatures is challenging because there is very little data available on components that may be suitable. Extensive testing at low temperatures yielded a set of components and a circuit topology that demonstrates the required level of protection for critical MMICs and similar devices. We present a circuit that provides robust protection for low voltage devices from room temperature down to 4 K.

Two-dimensional numerical model for the high electron mobility transistor

NASA Astrophysics Data System (ADS)

Loret, Dany

1987-11-01

A two-dimensional numerical drift-diffusion model for the High Electron Mobility Transistor (HEMT) is presented. Special attention is paid to the modeling of the current flow over the heterojunction. A finite difference scheme is used to solve the equations, and a variable mesh spacing was implemented to cope with the strong variations of functions near the heterojunction. Simulation results are compared to experimental data for a 0.7 μm gate length device. Small-signal transconductances and cut-off frequency obtained from the 2-D model agree well with the experimental values from S-parameter measurements. It is shown that the numerical models give good insight into device behaviour, including important parasitic effects such as electron injection into the bulk GaAs.

Method and system for reducing device performance degradation of organic devices

DOEpatents

Teague, Lucile C.

2014-09-02

Methods and systems for reducing the deleterious effects of gate bias stress on the drain current of an organic device, such as an organic thin film transistor, are provided. In a particular aspect, the organic layer of an organic device is illuminated with light having characteristics selected to reduce the gate bias voltage effects on the drain current of the organic device. For instance, the wavelength and intensity of the light are selected to provide a desired recovery of drain current of the organic device. If the characteristics of the light are appropriately matched to the organic device, recovery of the deleterious effects caused by gate bias voltage stress effects on the drain current of the organic device can be achieved. In a particular aspect, the organic device is selectively illuminated with light to operate the organic device in multiple modes of operation.

Indium-gallium-zinc-oxide thin-film transistor with a planar split dual-gate structure

NASA Astrophysics Data System (ADS)

Liu, Yu-Rong; Liu, Jie; Song, Jia-Qi; Lai, Pui-To; Yao, Ruo-He

2017-12-01

An amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) with a planar split dual gate (PSDG) structure has been proposed, fabricated and characterized. Experimental results indicate that the two independent gates can provide dynamical control of device characteristics such as threshold voltage, sub-threshold swing, off-state current and saturation current. The transconductance extracted from the output characteristics of the device increases from 4.0 × 10-6S to 1.6 × 10-5S for a change of control gate voltage from -2 V to 2 V, and thus the device could be used in a variable-gain amplifier. A significant advantage of the PSDG structure is its flexibility in controlling the device performance according to the need of practical applications.

Realization of Minimum and Maximum Gate Function in Ta2O5-based Memristive Devices

NASA Astrophysics Data System (ADS)

Breuer, Thomas; Nielen, Lutz; Roesgen, Bernd; Waser, Rainer; Rana, Vikas; Linn, Eike

2016-04-01

Redox-based resistive switching devices (ReRAM) are considered key enablers for future non-volatile memory and logic applications. Functionally enhanced ReRAM devices could enable new hardware concepts, e.g. logic-in-memory or neuromorphic applications. In this work, we demonstrate the implementation of ReRAM-based fuzzy logic gates using Ta2O5 devices to enable analogous Minimum and Maximum operations. The realized gates consist of two anti-serially connected ReRAM cells offering two inputs and one output. The cells offer an endurance up to 106 cycles. By means of exemplary input signals, each gate functionality is verified and signal constraints are highlighted. This realization could improve the efficiency of analogous processing tasks such as sorting networks in the future.

Gate protective device for SOS array

NASA Technical Reports Server (NTRS)

Meyer, J. E., Jr.; Scott, J. H.

1972-01-01

Protective gate device consisting of alternating heavily doped n(+) and p(+) diffusions eliminates breakdown voltages in silicon oxide on sapphire arrays caused by electrostatic discharge from person or equipment. Diffusions are easily produced during normal double epitaxial processing. Devices with nine layers had 27-volt breakdown.

Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11,000 cm(2)/V·s.

PubMed

Smith, Casey; Qaisi, Ramy; Liu, Zhihong; Yu, Qingkai; Hussain, Muhammad Mustafa

2013-07-23

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11,000 cm(2)/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low tox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance.

Monolithically integrated Si gate-controlled light-emitting device: science and properties

NASA Astrophysics Data System (ADS)

Xu, Kaikai

2018-02-01

The motivation of this study is to develop a p-n junction based light emitting device, in which the light emission is conventionally realized using reverse current driving, by voltage driving. By introducing an additional terminal of insulated gate for voltage driving, a novel three-terminal Si light emitting device is described where both the light intensity and spatial light pattern of the device are controlled by the gate voltage. The proposed light emitting device employs injection-enhanced Si in avalanche mode where electric field confinement occurs in the corner of a reverse-biased p+n junction. It is found that, depending on the bias conditions, the light intensity is either a linear or a quadratic function of the applied gate voltage or the reverse-bias. Since the light emission is based on the avalanching mode, the Si light emitting device offers the potential for very large scale integration-compatible light emitters for inter- or intra-chip signal transmission and contactless functional testing of wafers.

Low electron mobility of field-effect transistor determined by modulated magnetoresistance

NASA Astrophysics Data System (ADS)

Tauk, R.; Łusakowski, J.; Knap, W.; Tiberj, A.; Bougrioua, Z.; Azize, M.; Lorenzini, P.; Sakowicz, M.; Karpierz, K.; Fenouillet-Beranger, C.; Cassé, M.; Gallon, C.; Boeuf, F.; Skotnicki, T.

2007-11-01

Room temperature magnetotransport experiments were carried out on field-effect transistors in magnetic fields up to 10 T. It is shown that measurements of the transistor magnetoresistance and its first derivative with respect to the gate voltage allow the derivation of the electron mobility in the gated part of the transistor channel, while the access/contact resistances and the transistor gate length need not be known. We demonstrate the potential of this method using GaN and Si field-effect transistors and discuss its importance for mobility measurements in transistors with nanometer gate length.

Nanogranular SiO2 proton gated silicon layer transistor mimicking biological synapses

NASA Astrophysics Data System (ADS)

Liu, M. J.; Huang, G. S.; Feng, P.; Guo, Q. L.; Shao, F.; Tian, Z. A.; Li, G. J.; Wan, Q.; Mei, Y. F.

2016-06-01

Silicon on insulator (SOI)-based transistors gated by nanogranular SiO2 proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

Inversion channel diamond metal-oxide-semiconductor field-effect transistor with normally off characteristics.

PubMed

Matsumoto, Tsubasa; Kato, Hiromitsu; Oyama, Kazuhiro; Makino, Toshiharu; Ogura, Masahiko; Takeuchi, Daisuke; Inokuma, Takao; Tokuda, Norio; Yamasaki, Satoshi

2016-08-22

We fabricated inversion channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with normally off characteristics. At present, Si MOSFETs and insulated gate bipolar transistors (IGBTs) with inversion channels are widely used because of their high controllability of electric power and high tolerance. Although a diamond semiconductor is considered to be a material with a strong potential for application in next-generation power devices, diamond MOSFETs with an inversion channel have not yet been reported. We precisely controlled the MOS interface for diamond by wet annealing and fabricated p-channel and planar-type MOSFETs with phosphorus-doped n-type body on diamond (111) substrate. The gate oxide of Al2O3 was deposited onto the n-type diamond body by atomic layer deposition at 300 °C. The drain current was controlled by the negative gate voltage, indicating that an inversion channel with a p-type character was formed at a high-quality n-type diamond body/Al2O3 interface. The maximum drain current density and the field-effect mobility of a diamond MOSFET with a gate electrode length of 5 μm were 1.6 mA/mm and 8.0 cm(2)/Vs, respectively, at room temperature.

A novel low temperature soft reflow process for the fabrication of deep-submicron (<0.35 μm) T-gate pseudomorphic high electron mobility transistor structures

NASA Astrophysics Data System (ADS)

Ian, Ka Wa; Exarchos, Michael; Missous, Mohamed

2013-02-01

We report a new and simple low temperature soft reflow process using solvent vapour. The combination of this soft reflow and conventional i-line lithography enables low cost, highly efficient fabrication at the deep-submicron scale. Compared to the conventional thermal reflow process, the key benefits of the new soft reflow process are its low temperature operation (<50 °C), greater shrinkage of the structure size (up to 75%) and better controllability. Gate openings reflowed from 1 μm to 250 nm have been routinely and reproducibly achieved by utilizing the saturation characteristics of the process. The feasibility of this soft reflow process is demonstrated in the fabrication of a 350 nm T-gate pseudomorphic high electron mobility transistor. By shrinking the gate length by a factor of three (from a 1 μm initial opening), the output current is improved by 60% (500 mA mm-1 from 300 mA mm-1) and fT and fMAX are increased to 70 GHz (from 20 GHz) and 120 GHz (from 40 GHz) respectively. The proposed soft reflow could potentially be applied on other compatible substrates such as polymer based material for organic or thin film devices, potentially leading to many new possible applications.

MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

NASA Astrophysics Data System (ADS)

Riggert, C.; Ziegler, M.; Schroeder, D.; Krautschneider, W. H.; Kohlstedt, H.

2014-10-01

Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit.

Integrated all-optical programmable logic array based on semiconductor optical amplifiers.

PubMed

Dong, Wenchan; Huang, Zhuyang; Hou, Jie; Santos, Rui; Zhang, Xinliang

2018-05-01

The all-optical programmable logic array (PLA) is one of the most important optical complex logic devices that can implement combinational logic functions. In this Letter, we propose and experimentally demonstrate an integrated all-optical PLA at the operation speed of 40 Gb/s. The PLA mainly consists of a delay interferometer (DI) and semiconductor optical amplifiers (SOAs) of different lengths. The DI is used to pre-code the input signals and improve the reconfigurability of the scheme. The longer SOAs are nonlinear media for generating canonical logic units (CLUs) using four-wave mixing. The shorter SOAs are used to select the appropriate CLUs by changing the working states; then reconfigurable logic functions can be output directly. The results show that all the CLUs are realized successfully, and the optical signal-to-noise ratios are above 22 dB. The exclusive NOR gate and exclusive OR gate are experimentally demonstrated based on output CLUs.

Debye screening in single-molecule carbon nanotube field-effect sensors.

PubMed

Sorgenfrei, Sebastian; Chiu, Chien-Yang; Johnston, Matthew; Nuckolls, Colin; Shepard, Kenneth L

2011-09-14

Point-functionalized carbon nanotube field-effect transistors can serve as highly sensitive detectors for biomolecules. With a probe molecule covalently bound to a defect in the nanotube sidewall, two-level random telegraph noise (RTN) in the conductance of the device is observed as a result of a charged target biomolecule binding and unbinding at the defect site. Charge in proximity to the defect modulates the potential (and transmission) of the conductance-limiting barrier created by the defect. In this Letter, we study how these single-molecule electronic sensors are affected by ionic screening. Both charge in proximity to the defect site and buffer concentration are found to affect RTN amplitude in a manner that follows from simple Debye length considerations. RTN amplitude is also dependent on the potential of the electrolyte gate as applied to the reference electrode; at high enough gate potentials, the target DNA is completely repelled and RTN is suppressed.

Study of the enhancement-mode AlGaN/GaN high electron mobility transistor with split floating gates

NASA Astrophysics Data System (ADS)

Wang, Hui; Wang, Ning; Jiang, Ling-Li; Zhao, Hai-Yue; Lin, Xin-Peng; Yu, Hong-Yu

2017-11-01

In this work, the charge storage based split floating gates (FGs) enhancement mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs) are studied. The simulation results reveal that under certain density of two dimensional electron gas, the variation tendency of the threshold voltage (Vth) with the variation of the blocking dielectric thickness depends on the FG charge density. It is found that when the length sum and isolating spacing sum of the FGs both remain unchanged, the Vth shall decrease with the increasing FGs number but maintaining the device as E-mode. It is also reported that for the FGs HEMT, the failure of a FG will lead to the decrease of Vth as well as the increase of drain current, and the failure probability can be improved significantly with the increase of FGs number.

Solution processed molecular floating gate for flexible flash memories

NASA Astrophysics Data System (ADS)

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

2013-10-01

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices.

Solution processed molecular floating gate for flexible flash memories

PubMed Central

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

2013-01-01

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices. PMID:24172758

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-02-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-05-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

Perspective analysis of tri gate germanium tunneling field-effect transistor with dopant segregation region at source/drain

NASA Astrophysics Data System (ADS)

Liu, Liang-kui; Shi, Cheng; Zhang, Yi-bo; Sun, Lei

2017-04-01

A tri gate Ge-based tunneling field-effect transistor (TFET) has been numerically studied with technology computer aided design (TCAD) tools. Dopant segregated Schottky source/drain is applied to the device structure design (DS-TFET). The characteristics of the DS-TFET are compared and analyzed comprehensively. It is found that the performance of n-channel tri gate DS-TFET with a positive bias is insensitive to the dopant concentration and barrier height at n-type drain, and that the dopant concentration and barrier height at a p-type source considerably affect the device performance. The domination of electron current in the entire BTBT current of this device accounts for this phenomenon and the tri-gate DS-TFET is proved to have a higher performance than its dual-gate counterpart.

14 CFR 25.145 - Longitudinal control.

Code of Federal Regulations, 2010 CFR

2010-01-01

... complete retraction of the high lift devices from any position is begun during steady, straight, level...) If gated high-lift device control positions are provided, paragraph (c) of this section applies to retractions of the high-lift devices from any position from the maximum landing position to the first gated...

A two-dimensional analytical modeling for channel potential and threshold voltage of short channel triple material symmetrical gate Stack (TMGS) DG-MOSFET

NASA Astrophysics Data System (ADS)

Tripathi, Shweta

2016-10-01

In the present work, a two-dimensional (2D) analytical framework of triple material symmetrical gate stack (TMGS) DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS™ device simulator to affirm and formalize the proposed device structure.

Scaling of Device Variability and Subthreshold Swing in Ballistic Carbon Nanotube Transistors

NASA Astrophysics Data System (ADS)

Cao, Qing; Tersoff, Jerry; Han, Shu-Jen; Penumatcha, Ashish V.

2015-08-01

In field-effect transistors, the inherent randomness of dopants and other charges is a major cause of device-to-device variability. For a quasi-one-dimensional device such as carbon nanotube transistors, even a single charge can drastically change the performance, making this a critical issue for their adoption as a practical technology. Here we calculate the effect of the random charges at the gate-oxide surface in ballistic carbon nanotube transistors, finding good agreement with the variability statistics in recent experiments. A combination of experimental and simulation results further reveals that these random charges are also a major factor limiting the subthreshold swing for nanotube transistors fabricated on thin gate dielectrics. We then establish that the scaling of the nanotube device uniformity with the gate dielectric, fixed-charge density, and device dimension is qualitatively different from conventional silicon transistors, reflecting the very different device physics of a ballistic transistor with a quasi-one-dimensional channel. The combination of gate-oxide scaling and improved control of fixed-charge density should provide the uniformity needed for large-scale integration of such novel one-dimensional transistors even at extremely scaled device dimensions.

Fabrication of quantum dots in undoped Si/Si 0.8Ge 0.2 heterostructures using a single metal-gate layer

DOE PAGES

Lu, T. M.; Gamble, J. K.; Muller, R. P.; ...

2016-08-01

Enhancement-mode Si/SiGe electron quantum dots have been pursued extensively by many groups for their potential in quantum computing. Most of the reported dot designs utilize multiple metal-gate layers and use Si/SiGe heterostructures with Ge concentration close to 30%. Here, we report the fabrication and low-temperature characterization of quantum dots in the Si/Si 0.8Ge 0.2 heterostructures using only one metal-gate layer. We find that the threshold voltage of a channel narrower than 1 μm increases as the width decreases. The higher threshold can be attributed to the combination of quantum confinement and disorder. We also find that the lower Ge ratiomore » used here leads to a narrower operational gate bias range. The higher threshold combined with the limited gate bias range constrains the device design of lithographic quantum dots. We incorporate such considerations in our device design and demonstrate a quantum dot that can be tuned from a single dot to a double dot. Furthermore, the device uses only a single metal-gate layer, greatly simplifying device design and fabrication.« less

Effects of structure and oxygen flow rate on the photo-response of amorphous IGZO-based photodetector devices

NASA Astrophysics Data System (ADS)

Jang, Jun Tae; Ko, Daehyun; Choi, Sungju; Kang, Hara; Kim, Jae-Young; Yu, Hye Ri; Ahn, Geumho; Jung, Haesun; Rhee, Jihyun; Lee, Heesung; Choi, Sung-Jin; Kim, Dong Myong; Kim, Dae Hwan

2018-02-01

In this study, we investigated how the structure and oxygen flow rate (OFR) during the sputter-deposition affects the photo-responses of amorphous indium-gallium-zinc-oxide (a-IGZO)-based photodetector devices. As the result of comparing three types of device structures with one another, which are a global Schottky diode, local Schottky diode, and thin-film transistor (TFT), the IGZO TFT with the gate pulse technique suppressing the persistent photoconductivity (PPC) is the most promising photodetector in terms of a high photo-sensitivity and uniform sensing characteristic. In order to analyze the IGZO TFT-based photodetectors more quantitatively, the time-evolution of sub-gap density-of-states (DOS) was directly observed under photo-illumination and consecutively during the PPC-compensating period with applying the gate pulse. It shows that the increased ionized oxygen vacancy (VO2+) defects under photo-illumination was fully recovered by the positive gate pulse and even overcompensated by additional electron trapping. Based on experimentally extracted sub-gap DOS, the origin on PPC was successfully decomposed into the hole trapping and the VO ionization. Although the VO ionization is enhanced in lower OFR (O-poor) device, the PPC becomes more severe in high OFR (O-rich) device because the hole trapping dominates the PPC in IGZO TFT under photo-illumination rather than the VO ionization and more abundant holes are trapped into gate insulator and/or interface in O-rich TFTs. Similarly, the electron trapping during the PPC-compensating period with applying the positive gate pulse becomes more prominent in O-rich TFTs. It is attributed to more hole/electron traps in the gate insulator and/or interface, which is associated with oxygen interstitials, or originates from the ion bombardment-related lower quality gate oxide in O-rich devices.

Electronic spin transport in gate-tunable black phosphorus spin valves

NASA Astrophysics Data System (ADS)

Liu, Jiawei; Avsar, Ahmet; Tan, Jun You; Oezyilmaz, Barbaros

High charge mobility, the electric field effect and small spin-orbit coupling make semiconducting black phosphorus (BP) a promising material for spintronics device applications requiring long spin distance spin communication with all rectification and amplification actions. Towards this, we study the all electrical spin injection, transport and detection under non-local spin valve geometry in fully encapsulated ultra-thin BP devices. We observe spin relaxation times as high as 4 ns, with spin relaxation lengths exceeding 6 μm. These values are an order of magnitude higher than what have been measured in typical graphene spin valve devices. Moreover, the spin transport depends strongly on charge carrier concentration and can be manipulated in a spin transistor-like manner by controlling electric field. This behaviour persists even at room temperature. Finally, we will show that similar to its electrical and optical properties, spin transport property is also strongly anisotropic.

Engineering modular and orthogonal genetic logic gates for robust digital-like synthetic biology.

PubMed

Wang, Baojun; Kitney, Richard I; Joly, Nicolas; Buck, Martin

2011-10-18

Modular and orthogonal genetic logic gates are essential for building robust biologically based digital devices to customize cell signalling in synthetic biology. Here we constructed an orthogonal AND gate in Escherichia coli using a novel hetero-regulation module from Pseudomonas syringae. The device comprises two co-activating genes hrpR and hrpS controlled by separate promoter inputs, and a σ(54)-dependent hrpL promoter driving the output. The hrpL promoter is activated only when both genes are expressed, generating digital-like AND integration behaviour. The AND gate is demonstrated to be modular by applying new regulated promoters to the inputs, and connecting the output to a NOT gate module to produce a combinatorial NAND gate. The circuits were assembled using a parts-based engineering approach of quantitative characterization, modelling, followed by construction and testing. The results show that new genetic logic devices can be engineered predictably from novel native orthogonal biological control elements using quantitatively in-context characterized parts. © 2011 Macmillan Publishers Limited. All rights reserved.

Fabrication and characterization of heterojunction transistors

NASA Astrophysics Data System (ADS)

Lo, Chien-Fong

2011-12-01

Submircon emitter finger high-speed double heterojunction InAlAs/InGaAsSb/InGaAs bipolar transistors (DHBTs) and a variety of nitride high electron mobility transistors (HEMTs) including AlGaN/GaN, InAlN/GaN, and AlN/GaN were fabricated and characterized. DHBT structures were grown by solid source molecular beam epitaxy (SSMBE) on Fe-doped semiinsulating InP substrates and nitride HEMTs were grown with a metal organic chemical vapor deposition (MOCVD) system on sapphire or SiC substrates. AlN/GaN HEMTs were grown with a RF-VMBE on sapphire substrates. Ultra low base contact resistance of 3.7 x 10-7 ohm-cm2 after 1 min 250¢XC thermal treatment on noval InGaAsSb base of DHBTs was achieved and a long-term thermal stability of base metallization was studied. Regarding small scale DHBT fabrication, tri-layer system was introduced to improve the resolution for submicron emitter patterning and help to pile up a thicker emitter metal stack; guard-ring technique was applied around the emitter periphery in order to preserve the current gain at small emitter dimensions. Ultra low turn-on voltage and high current gain can be realized with InGaAsSb-base DHBTs as compared to the conventional InGaAs-base DHBTs. A peak current gain cutoff frequency (fT) of 268 GHz and power gain cutoff frequency (fmax) of 485 GHz were achieved. GaN-based HEMTs herein were fabricated with gate lengths from 400 nm to 1im, and were deposited Ti/Al/Ni/Au as their Ohmic contact metallization. Effects of the Ohmic contact annealing for lattice-matched InAlN/GaN HEMTs with and without a thin GaN cap layer were exhibited and their optimal annealing temperature were obtained. A maximum drain current of 1.3 A/mm and an extrinsic transconductance of 366 mS/mm were demonstrated for InAlN/GaN HEMTs with the shortest gate length. A unity-gain cutoff frequency (fT) of 69 GHz and a maximum frequency of oscillation (fmax) of 80 GHz for InAlN/GaN HEMTs were extracted from measured scattering parameters. Passivation is one of the most important parts in device processing for preventing degradation from various environmental conditions and promising a better device performance. Simply, ozone treatment of AlN on AlN/GaN heterostructures produced effective aluminum oxide surface passivation and chemical resistance to the AZ positive photoresist developer used for subsequent device fabrication. Metal oxide semiconductor diode-like gate current-voltage characteristics and minimal drain current degradation during gate pulse measurements were observed. With an additional oxygen plasma treatment on the gate area prior to the gate metal deposition, enhancement-mode AlN/GaN HEMTs were realized. In addition, for AlGaN/GaN HEMTs in high electrical field applications, a high-dielectric-strength SiNx passivation over an optimum thickness was needed to suppress surface flashover during a high voltage or high power operation. An excellent isolation blocking voltage of 900 V with a leakage current at 1 muA/mm was obtained across a nitrogen-implanted isolation-gap of 10 mum between two Ohmic pads. The radiation hardness of HBTs and HEMTs is one of the critical factors that need to be established for military, space, and nuclear industry applications. The effects of proton radiation on the dc performance of InAlAs/InGaAsSb/InGaAs HBTs and AlN/GaN HEMTs were investigated. Both of these devices showed a remarkable resistance to high energy protoninduced degradation and appeared very promising for terrestrial or space-borne applications. The proton-irradiated devices with a dose of 2 x 1011 cm-2 (estimated to be equivalent to more than 40 years of exposure in low-earth orbit) showed only small changes in dc transfer characteristics, threshold voltage shift, and gate-lag with a high frequency pulse on the gate of the HEMTs and showed small changes in junction ideality factor, generation recombination leakage current, and output conductance for the HBTs. The effect the gate metallization on the nitride HEMT reliability was also examined. By replacing the conventional Ni/Au gate metallization with Pt/Ti/Au, the critical voltage for degradation of AlGaN/GaN HEMTs during off-state biasing stress was significantly improved from -55 V to over larger than -100 V. Besides the irradiation or high voltage stresses, the effects of ambient on the Pt-gated HEMT sensor for gas sensing application were also explored. For the hydrogen sensing, the sensitivity decreased proportional to the relative humidity but the presence of humidity dramatically improved the sensor recovery characteristics after exposure to the hydrogen ambient.

Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors

NASA Astrophysics Data System (ADS)

Simoen, Eddy; Gaillardin, Marc; Paillet, Philippe; Reed, Robert A.; Schrimpf, Ron D.; Alles, Michael L.; El-Mamouni, Farah; Fleetwood, Daniel M.; Griffoni, Alessio; Claeys, Cor

2013-06-01

The aim of this review paper is to describe in a comprehensive manner the current understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and FinFET CMOS technologies. Total Ionizing Dose (TID) response, heavy-ion microdose effects and single-event effects (SEEs) will be discussed. It is shown that a very high TID tolerance can be achieved by narrow-fin SOI FinFET architectures, while bulk FinFETs may exhibit similar TID response to the planar devices. Due to the vertical nature of FinFETs, a specific heavy-ion response can be obtained, whereby the angle of incidence becomes highly important with respect to the vertical sidewall gates. With respect to SEE, the buried oxide in the SOI FinFETs suppresses the diffusion tails from the charge collection in the substrate compared to the planar bulk FinFET devices. Channel lengths and fin widths are now comparable to, or smaller than the dimensions of the region affected by the single ionizing ions or lasers used in testing. This gives rise to a high degree of sensitivity to individual device parameters and source-drain shunting during ion-beam or laser-beam SEE testing. Simulations are used to illuminate the mechanisms observed in radiation testing and the progress and needs for the numerical modeling/simulation of the radiation response of advanced SOI and FinFET transistors are highlighted.

Design and performance of a respiratory amplitude gating device for PET/CT imaging

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chang Guoping; Chang Tingting; Clark, John W. Jr.

2010-04-15

Purpose: Recently, the authors proposed a free-breathing amplitude gating (FBAG) technique for PET/CT scanners. The implementation of this technique required specialized hardware and software components that were specifically designed to interface with commercial respiratory gating devices to generate the necessary triggers required for the FBAG technique. The objective of this technical note is to introduce an in-house device that integrates all the necessary hardware and software components as well as tracks the patient's respiratory motion to realize amplitude gating on PET/CT scanners. Methods: The in-house device is composed of a piezoelectric transducer coupled to a data-acquisition system in order tomore » monitor the respiratory waveform. A LABVIEW program was designed to control the data-acquisition device and inject triggers into the PET list stream whenever the detected respiratory amplitude crossed a predetermined amplitude range. A timer was also programmed to stop the scan when the accumulated time within the selected amplitude range reached a user-set interval. This device was tested using a volunteer and a phantom study. Results: The results from the volunteer and phantom studies showed that the in-house device can detect similar respiratory signals as commercially available respiratory gating systems and is able to generate the necessary triggers to suppress respiratory motion artifacts. Conclusions: The proposed in-house device can be used to implement the FBAG technique in current PET/CT scanners.« less

Motion-gated acquisition for in vivo optical imaging

PubMed Central

Gioux, Sylvain; Ashitate, Yoshitomo; Hutteman, Merlijn; Frangioni, John V.

2009-01-01

Wide-field continuous wave fluorescence imaging, fluorescence lifetime imaging, frequency domain photon migration, and spatially modulated imaging have the potential to provide quantitative measurements in vivo. However, most of these techniques have not yet been successfully translated to the clinic due to challenging environmental constraints. In many circumstances, cardiac and respiratory motion greatly impair image quality and∕or quantitative processing. To address this fundamental problem, we have developed a low-cost, field-programmable gate array–based, hardware-only gating device that delivers a phase-locked acquisition window of arbitrary delay and width that is derived from an unlimited number of pseudo-periodic and nonperiodic input signals. All device features can be controlled manually or via USB serial commands. The working range of the device spans the extremes of mouse electrocardiogram (1000 beats per minute) to human respiration (4 breaths per minute), with timing resolution ⩽0.06%, and jitter ⩽0.008%, of the input signal period. We demonstrate the performance of the gating device, including dramatic improvements in quantitative measurements, in vitro using a motion simulator and in vivo using near-infrared fluorescence angiography of beating pig heart. This gating device should help to enable the clinical translation of promising new optical imaging technologies. PMID:20059276

Gallium arsenide processing for gate array logic

NASA Technical Reports Server (NTRS)

Cole, Eric D.

1989-01-01

The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

Detection beyond Debye's length with an electrolyte-gated organic field-effect transistor.

PubMed

Palazzo, Gerardo; De Tullio, Donato; Magliulo, Maria; Mallardi, Antonia; Intranuovo, Francesca; Mulla, Mohammad Yusuf; Favia, Pietro; Vikholm-Lundin, Inger; Torsi, Luisa

2015-02-04

Electrolyte-gated organic field-effect transistors are successfully used as biosensors to detect binding events occurring at distances from the transistor electronic channel that are much larger than the Debye length in highly concentrated solutions. The sensing mechanism is mainly capacitive and is due to the formation of Donnan's equilibria within the protein layer, leading to an extra capacitance (CDON) in series to the gating system. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Operation of a gated field emitter using an individual carbon nanofiber cathode

NASA Astrophysics Data System (ADS)

Guillorn, M. A.; Melechko, A. V.; Merkulov, V. I.; Ellis, E. D.; Britton, C. L.; Simpson, M. L.; Lowndes, D. H.; Baylor, L. R.

2001-11-01

We report on the operation of an integrated gated cathode device using a single vertically aligned carbon nanofiber as the field emission element. This device is capable of operation in a moderate vacuum for extended periods of time without experiencing a degradation of performance. Less than 1% of the total emitted current is collected by the gate electrode, indicating that the emitted electron beam is highly collimated. As a consequence, this device is ideal for applications that require well-focused electron emission from a microscale structure.

On the physical operation and optimization of the p-GaN gate in normally-off GaN HEMT devices

NASA Astrophysics Data System (ADS)

Efthymiou, L.; Longobardi, G.; Camuso, G.; Chien, T.; Chen, M.; Udrea, F.

2017-03-01

In this study, an investigation is undertaken to determine the effect of gate design parameters on the on-state characteristics (threshold voltage and gate turn-on voltage) of pGaN/AlGaN/GaN high electron mobility transistors (HEMTs). Design parameters considered are pGaN doping and gate metal work function. The analysis considers the effects of variations on these parameters using a TCAD model matched with experimental results. A better understanding of the underlying physics governing the operation of these devices is achieved with a view to enable better optimization of such gate designs.

Cryogenic on-chip multiplexer for the study of quantum transport in 256 split-gate devices

NASA Astrophysics Data System (ADS)

Al-Taie, H.; Smith, L. W.; Xu, B.; See, P.; Griffiths, J. P.; Beere, H. E.; Jones, G. A. C.; Ritchie, D. A.; Kelly, M. J.; Smith, C. G.

2013-06-01

We present a multiplexing scheme for the measurement of large numbers of mesoscopic devices in cryogenic systems. The multiplexer is used to contact an array of 256 split gates on a GaAs/AlGaAs heterostructure, in which each split gate can be measured individually. The low-temperature conductance of split-gate devices is governed by quantum mechanics, leading to the appearance of conductance plateaux at intervals of 2e2/h. A fabrication-limited yield of 94% is achieved for the array, and a "quantum yield" is also defined, to account for disorder affecting the quantum behaviour of the devices. The quantum yield rose from 55% to 86% after illuminating the sample, explained by the corresponding increase in carrier density and mobility of the two-dimensional electron gas. The multiplexer is a scalable architecture, and can be extended to other forms of mesoscopic devices. It overcomes previous limits on the number of devices that can be fabricated on a single chip due to the number of electrical contacts available, without the need to alter existing experimental set ups.

An intelligent 1:2 demultiplexer as an intracellular theranostic device based on DNA/Ag cluster-gated nanovehicles

NASA Astrophysics Data System (ADS)

Ran, Xiang; Wang, Zhenzhen; Ju, Enguo; Pu, Fang; Song, Yanqiu; Ren, Jinsong; Qu, Xiaogang

2018-02-01

The logic device demultiplexer can convey a single input signal into one of multiple output channels. The choice of the output channel is controlled by a selector. Several molecules and biomolecules have been used to mimic the function of a demultiplexer. However, the practical application of logic devices still remains a big challenge. Herein, we design and construct an intelligent 1:2 demultiplexer as a theranostic device based on azobenzene (azo)-modified and DNA/Ag cluster-gated nanovehicles. The configuration of azo and the conformation of the DNA ensemble can be regulated by light irradiation and pH, respectively. The demultiplexer which uses light as the input and acid as the selector can emit red fluorescence or a release drug under different conditions. Depending on different cells, the intelligent logic device can select the mode of cellular imaging in healthy cells or tumor therapy in tumor cells. The study incorporates the logic gate with the theranostic device, paving the way for tangible applications of logic gates in the future.

An intelligent 1:2 demultiplexer as an intracellular theranostic device based on DNA/Ag cluster-gated nanovehicles.

PubMed

Ran, Xiang; Wang, Zhenzhen; Ju, Enguo; Pu, Fang; Song, Yanqiu; Ren, Jinsong; Qu, Xiaogang

2018-02-09

The logic device demultiplexer can convey a single input signal into one of multiple output channels. The choice of the output channel is controlled by a selector. Several molecules and biomolecules have been used to mimic the function of a demultiplexer. However, the practical application of logic devices still remains a big challenge. Herein, we design and construct an intelligent 1:2 demultiplexer as a theranostic device based on azobenzene (azo)-modified and DNA/Ag cluster-gated nanovehicles. The configuration of azo and the conformation of the DNA ensemble can be regulated by light irradiation and pH, respectively. The demultiplexer which uses light as the input and acid as the selector can emit red fluorescence or a release drug under different conditions. Depending on different cells, the intelligent logic device can select the mode of cellular imaging in healthy cells or tumor therapy in tumor cells. The study incorporates the logic gate with the theranostic device, paving the way for tangible applications of logic gates in the future.

Reversible logic gates based on enzyme-biocatalyzed reactions and realized in flow cells: a modular approach.

PubMed

Fratto, Brian E; Katz, Evgeny

2015-05-18

Reversible logic gates, such as the double Feynman gate, Toffoli gate and Peres gate, with 3-input/3-output channels are realized using reactions biocatalyzed with enzymes and performed in flow systems. The flow devices are constructed using a modular approach, where each flow cell is modified with one enzyme that biocatalyzes one chemical reaction. The multi-step processes mimicking the reversible logic gates are organized by combining the biocatalytic cells in different networks. This work emphasizes logical but not physical reversibility of the constructed systems. Their advantages and disadvantages are discussed and potential use in biosensing systems, rather than in computing devices, is suggested. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Synthesizing Biomolecule-based Boolean Logic Gates

PubMed Central

Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

2012-01-01

One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications. PMID:23526588

Synthesizing biomolecule-based Boolean logic gates.

PubMed

Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

2013-02-15

One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, and hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications.

Evaluation of Anisotropic Biaxial Stress Induced Around Trench Gate of Si Power Transistor Using Water-Immersion Raman Spectroscopy

NASA Astrophysics Data System (ADS)

Suzuki, Takahiro; Yokogawa, Ryo; Oasa, Kohei; Nishiwaki, Tatsuya; Hamamoto, Takeshi; Ogura, Atsushi

2018-05-01

The trench gate structure is one of the promising techniques to reduce on-state resistance (R on) for silicon power devices, such as insulated gate bipolar transistors and power metal-oxide-semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the R on of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.

Using quantum process tomography to characterize decoherence in an analog electronic device

NASA Astrophysics Data System (ADS)

Ostrove, Corey; La Cour, Brian; Lanham, Andrew; Ott, Granville

The mathematical structure of a universal gate-based quantum computer can be emulated faithfully on a classical electronic device using analog signals to represent a multi-qubit state. We describe a prototype device capable of performing a programmable sequence of single-qubit and controlled two-qubit gate operations on a pair of voltage signals representing the real and imaginary parts of a two-qubit quantum state. Analog filters and true-RMS voltage measurements are used to perform unitary and measurement gate operations. We characterize the degradation of the represented quantum state with successive gate operations by formally performing quantum process tomography to estimate the equivalent decoherence channel. Experimental measurements indicate that the performance of the device may be accurately modeled as an equivalent quantum operation closely resembling a depolarizing channel with a fidelity of over 99%. This work was supported by the Office of Naval Research under Grant No. N00014-14-1-0323.

Flexible, polymer gated, AC-driven organic electroluminescence devices

NASA Astrophysics Data System (ADS)

Xu, Junwei; Carroll, David L.

2017-08-01

Comparing rigid inorganic layer, polymeric semiconducting gate layer exhibits superior flexibility as well as efficient carrier manipulation in high frequency AC cycles. Mechanism of the carrier manipulation at the gate in forward and reversed bias of AC cycle is studied. The flexible PET-based AC-OEL device with poly[(9,9-bis(3'-((N,N-dimethyl)-Nethylammonium)- propyl)-2,7-fluorene)-alt-2,7-(9,9-dioctylfluorene)] (PFN-Br) gate shows a stable electroluminescent performance in frequency sweep with a color rendering index (CRI) over 81 at 2800K color temperature.

Optical XOR gate

DOEpatents

Vawter, G. Allen

2013-11-12

An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

Optical NOR gate

DOEpatents

Skogen, Erik J [Albuquerque, NM; Tauke-Pedretti, Anna [Albuquerque, NM

2011-09-06

An optical NOR gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical NOR gate utilizes two digital optical inputs and a continuous light input to provide a NOR function digital optical output. The optical NOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

Device and material characterization and analytic modeling of amorphous silicon thin film transistors

NASA Astrophysics Data System (ADS)

Slade, Holly Claudia

Hydrogenated amorphous silicon thin film transistors (TFTs) are now well-established as switching elements for a variety of applications in the lucrative electronics market, such as active matrix liquid crystal displays, two-dimensional imagers, and position-sensitive radiation detectors. These applications necessitate the development of accurate characterization and simulation tools. The main goal of this work is the development of a semi- empirical, analytical model for the DC and AC operation of an amorphous silicon TFT for use in a manufacturing facility to improve yield and maintain process control. The model is physically-based, in order that the parameters scale with gate length and can be easily related back to the material and device properties. To accomplish this, extensive experimental data and 2D simulations are used to observe and quantify non- crystalline effects in the TFTs. In particular, due to the disorder in the amorphous network, localized energy states exist throughout the band gap and affect all regimes of TFT operation. These localized states trap most of the free charge, causing a gate-bias-dependent field effect mobility above threshold, a power-law dependence of the current on gate bias below threshold, very low leakage currents, and severe frequency dispersion of the TFT gate capacitance. Additional investigations of TFT instabilities reveal the importance of changes in the density of states and/or back channel conduction due to bias and thermal stress. In the above threshold regime, the model is similar to the crystalline MOSFET model, considering the drift component of free charge. This approach uses the field effect mobility to take into account the trap states and must utilize the correct definition of threshold voltage. In the below threshold regime, the density of deep states is taken into account. The leakage current is modeled empirically, and the parameters are temperature dependent to 150oC. The capacitance of the TFT can be modeled using a transmission line model, which is implemented using a small signal circuit with access resistors in series with the source and drain capacitances. This correctly reproduces the frequency dispersion in the TFT. Automatic parameter extraction routines are provided and are used to test the robustness of the model on a variety of devices from different research laboratories. The results demonstrate excellent agreement, showing that the model is suitable for device design, scaling, and implementation in the manufacturing process.

Direct observation of trapped charges under field-plate in p-GaN gate AlGaN/GaN high electron mobility transistors by electric field-induced optical second-harmonic generation

NASA Astrophysics Data System (ADS)

Katsuno, Takashi; Manaka, Takaaki; Soejima, Narumasa; Iwamoto, Mitsumasa

2017-02-01

Trapped charges underneath the field-plate (FP) in a p-gallium nitride (GaN) gate AlGaN/ GaN high electron mobility transistor device were visualized by using electric field-induced optical second-harmonic generation imaging. Second-harmonic (SH) signals in the off-state of the device with FP indicated that the electric field decreased at the p-GaN gate edge and concentrated at the FP edge. Nevertheless, SH signals originating from trapped charges were slightly observed at the p-GaN gate edge and were not observed at the FP edge in the on-state. Compared with the device without FP, reduction of trapped charges at the p-GaN gate edge of the device with FP is attributed to attenuation of the electric field with the aid of the FP. Negligible trapped charges at the FP edge is owing to lower trap density of the SiO2/AlGaN interface at the FP edge compared with that of the SiO2/p-GaN sidewall interface at the p-GaN gate edge and attenuated electric field by the thickness of the SiO2 passivation layer on the AlGaN surface.

In2O3 nanowire based field effect transistor for biological sensors.

NASA Astrophysics Data System (ADS)

Zeng, Zhongming; Wang, Kai; Zhou, Weilie

2008-03-01

Semiconductor nanowires (NWs) are attracting considerable attention due to their nanoscale dimensions and enormous surface-to-volume ratios. Many applications have been demonstrated in toxic gas, protein, small molecule and viruses sensing because of their superior sensing performances. Indium oxide (In2O3) NWs have been successfully applied for toxic gas and small organic molecule sensing. In our experiment, In2O3 NWs based field effect transistors (FET) are fabricated for virus (Ricin) detections. Single-crystalline In2O3 NWs with diameters around 100 nm were synthesized by the thermal evaporation. The nanodevice based on In2O3 NWs bridges the source/drain electrodes with a channel length of ˜5 μm. Basic transport properties of devices were measured before biological detection. The I-V curves with the gate voltage Vg=0 shows good ohmic contact and the resistance is about 10 Mφ. The back-gate effect on the conductivity showed that In2O3 NW is working as n-type channel with obvious back-gate effect, which is much stronger than the reported results. The nanodevices used as virus detection will be also discussed.

Ionic liquid gating on atomic layer deposition passivated GaN: Ultra-high electron density induced high drain current and low contact resistance

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhou, Hong; Du, Yuchen; Ye, Peide D., E-mail: yep@purdue.edu

2016-05-16

Herein, we report on achieving ultra-high electron density (exceeding 10{sup 14 }cm{sup −2}) in a GaN bulk material device by ionic liquid gating, through the application of atomic layer deposition (ALD) of Al{sub 2}O{sub 3} to passivate the GaN surface. Output characteristics demonstrate a maximum drain current of 1.47 A/mm, the highest reported among all bulk GaN field-effect transistors, with an on/off ratio of 10{sup 5} at room temperature. An ultra-high electron density exceeding 10{sup 14 }cm{sup −2} accumulated at the surface is confirmed via Hall-effect measurement and transfer length measurement. In addition to the ultra-high electron density, we also observe a reductionmore » of the contact resistance due to the narrowing of the Schottky barrier width on the contacts. Taking advantage of the ALD surface passivation and ionic liquid gating technique, this work provides a route to study the field-effect and carrier transport properties of conventional semiconductors in unprecedented ultra-high charge density regions.« less

Effect of gate skirts on pedestrian behavior at highway-rail grade crossings

DOT National Transportation Integrated Search

2013-12-31

The Federal Railroad Administration was interested in evaluating one type of pedestrian safety device, commonly known as gate skirts, that consists of a secondary horizontal hanging gate under the existing pedestrian gate to better block access to th...

Bio-fabrication of nanomesh channels of single-walled carbon nanotubes for locally gated field-effect transistors

NASA Astrophysics Data System (ADS)

Byeon, Hye-Hyeon; Lee, Woo Chul; Kim, Wonbin; Kim, Seong Keun; Kim, Woong; Yi, Hyunjung

2017-01-01

Single-walled carbon nanotubes (SWNTs) are one of the promising electronic components for nanoscale electronic devices such as field-effect transistors (FETs) owing to their excellent device characteristics such as high conductivity, high carrier mobility and mechanical flexibility. Localized gating gemometry of FETs enables individual addressing of active channels and allows for better electrostatics via thinner dielectric layer of high k-value. For localized gating of SWNTs, it becomes critical to define SWNTs of controlled nanostructures and functionality onto desired locations in high precision. Here, we demonstrate that a biologically templated approach in combination of microfabrication processes can successfully produce a nanostructured channels of SWNTs for localized active devices such as local bottom-gated FETs. A large-scale nanostructured network, nanomesh, of SWNTs were assembled in solution using an M13 phage with strong binding affinity toward SWNTs and micrometer-scale nanomesh channels were defined using negative photolithography and plasma-etching processes. The bio-fabrication approach produced local bottom-gated FETs with remarkably controllable nanostructures and successfully enabled semiconducting behavior out of unsorted SWNTs. In addition, the localized gating scheme enhanced the device performances such as operation voltage and I on/I off ratio. We believe that our approach provides a useful and integrative method for fabricating electronic devices out of nanoscale electronic materials for applications in which tunable electrical properties, mechanical flexibility, ambient stability, and chemical stability are of crucial importance.

3D modeling of dual-gate FinFET.

PubMed

Mil'shtein, Samson; Devarakonda, Lalitha; Zanchi, Brian; Palma, John

2012-11-13

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at Vg1 >Vg2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.

3D modeling of dual-gate FinFET

NASA Astrophysics Data System (ADS)

Mil'shtein, Samson; Devarakonda, Lalitha; Zanchi, Brian; Palma, John

2012-11-01

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at V g1 > V g2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.

Extended-gate organic field-effect transistor for the detection of histamine in water

NASA Astrophysics Data System (ADS)

Minamiki, Tsukuru; Minami, Tsuyoshi; Yokoyama, Daisuke; Fukuda, Kenjiro; Kumaki, Daisuke; Tokito, Shizuo

2015-04-01

As part of our ongoing research program to develop health care sensors based on organic field-effect transistor (OFET) devices, we have attempted to detect histamine using an extended-gate OFET. Histamine is found in spoiled or decayed fish, and causes foodborne illness known as scombroid food poisoning. The new OFET device possesses an extended gate functionalized by carboxyalkanethiol that can interact with histamine. As a result, we have succeeded in detecting histamine in water through a shift in OFET threshold voltage. This result indicates the potential utility of the designed OFET devices in food freshness sensing.

A simple device for respiratory gating for the MRI of laboratory animals.

PubMed

Burdett, N G; Carpenter, T A; Hall, L D

1993-01-01

Respiratory motion must be overcome if MRI of the abdomen, even at the lowest resolution, is to be performed satisfactorily. A simple and reliable respiratory gating device, based on the interruption of an infrared (IR) optical beam is described. This device has the advantage that gating is based on the position of the chest as opposed to its velocity, and that it can be used without degrading the radiofrequency isolation of a Faraday cage. Its use in animal MRI is illustrated by high resolution (200 microns) images of in vivo rat liver and kidney.

SLD-MOSCNT: A new MOSCNT with step-linear doping profile in the source and drain regions

NASA Astrophysics Data System (ADS)

Tahne, Behrooz Abdi; Naderi, Ali

2017-01-01

In this paper, a new structure, step-linear doping MOSCNT (SLD-MOSCNT), is proposed to improve the performance of basic MOSCNTs. The basic structure suffers from band to band tunneling (BTBT). We show that using SLD profile for source and drain regions increases the horizontal distance between valence and conduction bands at gate to source/drain junction which reduces BTBT probability. SLD performance is compared with other similar structures which have recently been proposed to reduce BTBT such as MOSCNT with lightly-doped drain and source (LDDS), and with double-light doping in source and drain regions (DLD). The obtained results using a nonequilibrium Green’s function (NEGF) method show that the SLD-MOSCNT has the lowest leakage current, power consumption and delay time, and the highest current ratio and voltage gain. The ambipolar conduction in the proposed structure is very low and can be neglected. In addition, these structures can improve short-channel effects. Also, the investigation of cutoff frequency of the different structures shows that the SLD has the highest cutoff frequency. Device performance has been investigated for gate length from 8 to 20 nm which demonstrates all discussions regarding the superiority of the proposed structure are also valid for different channel lengths. This improvement is more significant especially for channel length less than 12 nm. Therefore, the SLD can be considered as a candidate to be used in the applications with high speed and low power consumption.

Design consideration of δ-doping channels for high-performance n + - GaAs / p + -InGaP/n-GaAs camel-gate field effect transistors

NASA Astrophysics Data System (ADS)

Tsai, Jung-Hui; Chen, Jeng-Shyan; Chu, Yu-Jui

2005-01-01

The influence of δ-doping channels on the performance of n +-GaAs/p +-InGaP/n-GaAs camel-gate field effect transistors is investigated by theoretical analysis and experimental results. The depleted pn junction of the camel gate and the existence of considerable conduction band discontinuity at the InGaP/GaAs heterojunction enhance the potential barrier height and the forward gate voltage. As the concentration-thickness products of the n-GaAs layer and δ-doping layer are fixed, the higher δ-doping device exhibits a higher potential barrier height, a larger drain current, and a broader gate voltage swing, whereas the transconductance is somewhat lower. For a n +=5.5×10 12 cm -2δ-doping device, the experimental result exhibits a maximum transconductance of 240 mS/mm and a gate voltage swing of 3.5 V. Consequently, the studied devices provide a good potential for large signal and linear circuit applications.

Use of a hard mask for formation of gate and dielectric via nanofilament field emission devices

DOEpatents

Morse, Jeffrey D.; Contolini, Robert J.

2001-01-01

A process for fabricating a nanofilament field emission device in which a via in a dielectric layer is self-aligned to gate metal via structure located on top of the dielectric layer. By the use of a hard mask layer located on top of the gate metal layer, inert to the etch chemistry for the gate metal layer, and in which a via is formed by the pattern from etched nuclear tracks in a trackable material, a via is formed by the hard mask will eliminate any erosion of the gate metal layer during the dielectric via etch. Also, the hard mask layer will protect the gate metal layer while the gate structure is etched back from the edge of the dielectric via, if such is desired. This method provides more tolerance for the electroplating of a nanofilament in the dielectric via and sharpening of the nanofilament.

High-frequency electromechanical resonators based on thin GaTe

NASA Astrophysics Data System (ADS)

Chitara, Basant; Ya'akobovitz, Assaf

2017-10-01

Gallium telluride (GaTe) is a layered material, which exhibits a direct bandgap (˜1.65 eV) regardless of its thickness and therefore holds great potential for integration as a core element in stretchable optomechanical and optoelectronic devices. Here, we characterize and demonstrate the elastic properties and electromechanical resonators of suspended thin GaTe nanodrums. We used atomic force microscopy to extract the Young’s modulus of GaTe (average value ˜39 GPa) and to predict the resonance frequencies of suspended GaTe nanodrums of various geometries. Electromechanical resonators fabricated from suspended GaTe revealed fundamental resonance frequencies in the range of 10-25 MHz, which closely match predicted values. Therefore, this study paves the way for creating a new generation of GaTe based nanoelectromechanical devices with a direct bandgap vibrating element, which can serve as optomechanical sensors and actuators.

System and Method for Scan Range Gating

NASA Technical Reports Server (NTRS)

Lindemann, Scott (Inventor); Zuk, David M. (Inventor)

2017-01-01

A system for scanning light to define a range gated signal includes a pulsed coherent light source that directs light into the atmosphere, a light gathering instrument that receives the light modified by atmospheric backscatter and transfers the light onto an image plane, a scanner that scans collimated light from the image plane to form a range gated signal from the light modified by atmospheric backscatter, a control circuit that coordinates timing of a scan rate of the scanner and a pulse rate of the pulsed coherent light source so that the range gated signal is formed according to a desired range gate, an optical device onto which an image of the range gated signal is scanned, and an interferometer to which the image of the range gated signal is directed by the optical device. The interferometer is configured to modify the image according to a desired analysis.

Ads' click-through rates predicting based on gated recurrent unit neural networks

NASA Astrophysics Data System (ADS)

Chen, Qiaohong; Guo, Zixuan; Dong, Wen; Jin, Lingzi

2018-05-01

In order to improve the effect of online advertising and to increase the revenue of advertising, the gated recurrent unit neural networks(GRU) model is used as the ads' click through rates(CTR) predicting. Combined with the characteristics of gated unit structure and the unique of time sequence in data, using BPTT algorithm to train the model. Furthermore, by optimizing the step length algorithm of the gated unit recurrent neural networks, making the model reach optimal point better and faster in less iterative rounds. The experiment results show that the model based on the gated recurrent unit neural networks and its optimization of step length algorithm has the better effect on the ads' CTR predicting, which helps advertisers, media and audience achieve a win-win and mutually beneficial situation in Three-Side Game.

A manufacturable process integration approach for graphene devices

NASA Astrophysics Data System (ADS)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Technical Note: Evaluation of the latency and the beam characteristics of a respiratory gating system using an Elekta linear accelerator and a respiratory indicator device, Abches.

PubMed

Saito, Masahide; Sano, Naoki; Ueda, Koji; Shibata, Yuki; Kuriyama, Kengo; Komiyama, Takafumi; Marino, Kan; Aoki, Shinichi; Onishi, Hiroshi

2018-01-01

To evaluate the basic performance of a respiratory gating system using an Elekta linac and an Abches respiratory-monitoring device. The gating system was comprised of an Elekta Synergy linac equipped with a Response TM gating interface module and an Abches respiratory-monitoring device. The latencies from a reference respiratory signal to the resulting Abches gating output signal and the resulting monitor-ion-chamber output signal were measured. Then, the flatness and symmetry of the gated beams were measured using a two-dimensional ionization chamber array for fixed and arc beams, respectively. Furthermore, the beam quality, TPR 20,10 , and the output of the fixed gated beams were also measured using a Farmer chamber. Each of the beam characteristics was compared with each of those for nongated irradiation. The full latencies at beam-on and beam-off for 6-MV gated beams were 336.4 ± 23.4 ms and 87.6 ± 7.1 ms, respectively. The differences in flatness between the gated and nongated beams were within 0.91% and 0.87% for the gun-target and left-right directions, respectively. In the same manner, the beam symmetries were within 0.68% and 0.82%, respectively. The percentage differences in beam quality and beam output were below 1% for a beam-on time range of 1.1-7 s. The latency of the Elekta gating system combined with Abches was found to be acceptable using our measurement method. Furthermore, we demonstrated that the beam characteristics of the gating system using our respiratory indicator were comparable with the nongated beams for a single-arc gated beam delivery. © 2017 American Association of Physicists in Medicine.

Gate line edge roughness amplitude and frequency variation effects on intra die MOS device characteristics

NASA Astrophysics Data System (ADS)

Hamadeh, Emad; Gunther, Norman G.; Niemann, Darrell; Rahman, Mahmud

2006-06-01

Random fluctuations in fabrication process outcomes such as gate line edge roughness (LER) give rise to corresponding fluctuations in scaled down MOS device characteristics. A thermodynamic-variational model is presented to study the effects of LER on threshold voltage and capacitance of sub-50 nm MOS devices. Conceptually, we treat the geometric definition of the MOS devices on a die as consisting of a collection of gates. In turn, each of these gates has an area, A, and a perimeter, P, defined by nominally straight lines subject to random process outcomes producing roughness. We treat roughness as being deviations from straightness consisting of both transverse amplitude and longitudinal wavelength each having lognormal distribution. We obtain closed-form expressions for variance of threshold voltage ( Vth), and device capacitance ( C) at Onset of Strong Inversion (OSI) for a small device. Using our variational model, we characterized the device electrical properties such as σ and σC in terms of the statistical parameters of the roughness amplitude and spatial frequency, i.e., inverse roughness wavelength. We then verified our model with numerical analysis of Vth roll-off for small devices and σ due to dopant fluctuation. Our model was also benchmarked against TCAD of σ as a function of LER. We then extended our analysis to predict variations in σ and σC versus average LER spatial frequency and amplitude, and oxide-thickness. Given the intuitive expectation that LER of very short wavelengths must also have small amplitude, we have investigated the case in which the amplitude mean is inversely related to the frequency mean. We compare with the situation in which amplitude and frequency mean are unrelated. Given also that the gate perimeter may consist of different LER signature for each side, we have extended our analysis to the case when the LER statistical difference between gate sides is moderate, as well as when it is significantly large.

Resonant tunneling device with two-dimensional quantum well emitter and base layers

DOEpatents

Simmons, J.A.; Sherwin, M.E.; Drummond, T.J.; Weckwerth, M.V.

1998-10-20

A double electron layer tunneling device is presented. Electrons tunnel from a two dimensional emitter layer to a two dimensional tunneling layer and continue traveling to a collector at a lower voltage. The emitter layer is interrupted by an isolation etch, a depletion gate, or an ion implant to prevent electrons from traveling from the source along the emitter to the drain. The collector is similarly interrupted by a backgate, an isolation etch, or an ion implant. When the device is used as a transistor, a control gate is added to control the allowed energy states of the emitter layer. The tunnel gate may be recessed to change the operating range of the device and allow for integrated complementary devices. Methods of forming the device are also set forth, utilizing epoxy-bond and stop etch (EBASE), pre-growth implantation of the backgate or post-growth implantation. 43 figs.

Resonant tunneling device with two-dimensional quantum well emitter and base layers

DOEpatents

Simmons, Jerry A.; Sherwin, Marc E.; Drummond, Timothy J.; Weckwerth, Mark V.

1998-01-01

A double electron layer tunneling device is presented. Electrons tunnel from a two dimensional emitter layer to a two dimensional tunneling layer and continue traveling to a collector at a lower voltage. The emitter layer is interrupted by an isolation etch, a depletion gate, or an ion implant to prevent electrons from traveling from the source along the emitter to the drain. The collector is similarly interrupted by a backgate, an isolation etch, or an ion implant. When the device is used as a transistor, a control gate is added to control the allowed energy states of the emitter layer. The tunnel gate may be recessed to change the operating range of the device and allow for integrated complementary devices. Methods of forming the device are also set forth, utilizing epoxy-bond and stop etch (EBASE), pre-growth implantation of the backgate or post-growth implantation.

Experimental verification of electrostatic boundary conditions in gate-patterned quantum devices

NASA Astrophysics Data System (ADS)

Hou, H.; Chung, Y.; Rughoobur, G.; Hsiao, T. K.; Nasir, A.; Flewitt, A. J.; Griffiths, J. P.; Farrer, I.; Ritchie, D. A.; Ford, C. J. B.

2018-06-01

In a model of a gate-patterned quantum device, it is important to choose the correct electrostatic boundary conditions (BCs) in order to match experiment. In this study, we model gated-patterned devices in doped and undoped GaAs heterostructures for a variety of BCs. The best match is obtained for an unconstrained surface between the gates, with a dielectric region above it and a frozen layer of surface charge, together with a very deep back boundary. Experimentally, we find a  ∼0.2 V offset in pinch-off characteristics of 1D channels in a doped heterostructure before and after etching off a ZnO overlayer, as predicted by the model. Also, we observe a clear quantised current driven by a surface acoustic wave through a lateral induced n-i-n junction in an undoped heterostructure. In the model, the ability to pump electrons in this type of device is highly sensitive to the back BC. Using the improved boundary conditions, it is straightforward to model quantum devices quite accurately using standard software.

Quantum gate-set tomography

NASA Astrophysics Data System (ADS)

Blume-Kohout, Robin

2014-03-01

Quantum information technology is built on (1) physical qubits and (2) precise, accurate quantum logic gates that transform their states. Developing quantum logic gates requires good characterization - both in the development phase, where we need to identify a device's flaws so as to fix them, and in the production phase, where we need to make sure that the device works within specs and predict residual error rates and types. This task falls to quantum state and process tomography. But until recently, protocols for tomography relied on a pre-existing and perfectly calibrated reference frame comprising the measurements (and, for process tomography, input states) used to characterize the device. In practice, these measurements are neither independent nor perfectly known - they are usually implemented via exactly the same gates that we are trying to characterize! In the past year, several partial solutions to this self-consistency problem have been proposed. I will present a framework (gate set tomography, or GST) that addresses and resolves this problem, by self-consistently characterizing an entire set of quantum logic gates on a black-box quantum device. In particular, it contains an explicit closed-form protocol for linear-inversion gate set tomography (LGST), which is immune to both calibration error and technical pathologies like local maxima of the likelihood (which plagued earlier methods). GST also demonstrates significant (multiple orders of magnitude) improvements in efficiency over standard tomography by using data derived from long sequences of gates (much like randomized benchmarking). GST has now been applied to qubit devices in multiple technologies. I will present and discuss results of GST experiments in technologies including a single trapped-ion qubit and a silicon quantum dot qubit. Sandia National Laboratories is a multiprogram laboratory operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL850.

SNW 2000 Proceedings. Oxide Thickness Variation Induced Threshold Voltage Fluctuations in Decanano MOSFETs: a 3D Density Gradient Simulation Study

NASA Technical Reports Server (NTRS)

Asenov, Asen; Kaya, S.; Davies, J. H.; Saini, S.

2000-01-01

We use the density gradient (DG) simulation approach to study, in 3D, the effect of local oxide thickness fluctuations on the threshold voltage of decanano MOSFETs in a statistical manner. A description of the reconstruction procedure for the random 2D surfaces representing the 'atomistic' Si-SiO2 interface variations is presented. The procedure is based on power spectrum synthesis in the Fourier domain and can include either Gaussian or exponential spectra. The simulations show that threshold voltage variations induced by oxide thickness fluctuation become significant when the gate length of the devices become comparable to the correlation length of the fluctuations. The extent of quantum corrections in the simulations with respect to the classical case and the dependence of threshold variations on the oxide thickness are examined.

Modeling of Nano-Scale Transistors and Memory Devices for Low Power Applications

NASA Astrophysics Data System (ADS)

Cao, Xi

As the featuring size of transistors scaled down to sub-20 nm, the continuous scaling of power has become one of the main challenges of the semiconductor industry. The power issue is raised by the barely scalable supply voltage and a limitation on the subthreshold swing (SS) of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, self-consistent quantum transport device simulators are developed to examine the nanoscale transistors based on black phosphorus (BP) materials. The scaling limit of double-gated BP MOSFETs is assessed. To reduce the SS below the thermionic limit for ultra-steep switching, tunnel FETs (TFETs) and vertical ballistic impact ionization FETs based on BP and its heterojunctions are investigated. Furthermore, the ferroelectric tunneling junction (FTJ) is modeled and examined for potential low power memory applications. For BP MOSFETs, the device physics at the ultimate scaling limit are examined. The performance of monolayer BP MOSFETs is projected to sub-10 nm and compared with the International Technology Roadmap for Semiconductors (ITRS) requirements. And the interplay of quantum mechanical effects and the highly anisotropic bandstructure of BP at this scale is investigated. By choice of layer number and crystalline direction, BP materials can offer a range of bandgap and effective mass values, which is attractive for TFET applications. Therefore, scaling behaviors of BP TFETs near and below the 10 nm scale are studied. The gate oxide thickness scaling and the effect of high-k dielectric are compared between the TFETs and the MOSFETs. For the TFETs with the gate lengths beyond 10 nm and at the sub-10 nm scale, the direct-source-to-drain tunneling issues are evaluated, and different strategies to achieve ultra-steep switching are specified. In a sub-10 nm graphene-BP-graphene heterojunction transistor, the sharp turnon behavior was observed, under a small source-drain bias of 0.1 V. The fast switch is attributed to a ballistic energy-dependent impact ionization mechanism. A device model is developed, which shows agreement with experiment results. The model is applied to explore the gate oxide scaling behavior and the effect of graphene doping, and to optimize the device for low power applications. Finally, to keep the integrity of the computing system, the FTJ is studied for its possible use as a low power memory device. A compact model for FTJ, dealing with both static and dynamic behaviors, is developed and compared with experimental data. The write energy consumed by the memory cell, comprising one transistor and one FTJ, is estimated by applying the compact model to circuit simulation. And a way to reduce the write energy is suggested.

Tuning the metal-insulator crossover and magnetism in SrRuO 3 by ionic gating

DOE PAGES

Yi, Hee Taek; Gao, Bin; Xie, Wei; ...

2014-10-13

Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. We report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO 3. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90–250 K and 70–100 K,more » respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.« less

Tuning the metal-insulator crossover and magnetism in SrRuO₃ by ionic gating.

PubMed

Yi, Hee Taek; Gao, Bin; Xie, Wei; Cheong, Sang-Wook; Podzorov, Vitaly

2014-10-13

Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. Here we report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO₃. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90-250 K and 70-100 K, respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.

Improved performance of nanoscale junctionless tunnel field-effect transistor based on gate engineering approach

NASA Astrophysics Data System (ADS)

Molaei Imen Abadi, Rouzbeh; Sedigh Ziabari, Seyed Ali

2016-11-01

In this paper, a first qualitative study on the performance characteristics of dual-work function gate junctionless TFET (DWG-JLTFET) on the basis of energy band profile modulation is investigated. A dual-work function gate technique is used in a JLTFET in order to create a downward band bending on the source side similar to PNPN structure. Compared with the single-work function gate junctionless TFET (SWG-JLTFET), the numerical simulation results demonstrated that the DWG-JLTFET simultaneously optimizes the ON-state current, the OFF-state leakage current, and the threshold voltage and also improves average subthreshold slope. It is illustrated that if appropriate work functions are selected for the gate materials on the source side and the drain side, the JLTFET exhibits a considerably improved performance. Furthermore, the optimization design of the tunnel gate length ( L Tun) for the proposed DWG-JLTFET is studied. All the simulations are done in Silvaco TCAD for a channel length of 20 nm using the nonlocal band-to-band tunneling (BTBT) model.

Direct extraction of electron parameters from magnetoconductance analysis in mesoscopic ring array structures

NASA Astrophysics Data System (ADS)

Sawada, A.; Faniel, S.; Mineshige, S.; Kawabata, S.; Saito, K.; Kobayashi, K.; Sekine, Y.; Sugiyama, H.; Koga, T.

2018-05-01

We report an approach for examining electron properties using information about the shape and size of a nanostructure as a measurement reference. This approach quantifies the spin precession angles per unit length directly by considering the time-reversal interferences on chaotic return trajectories within mesoscopic ring arrays (MRAs). Experimentally, we fabricated MRAs using nanolithography in InGaAs quantum wells which had a gate-controllable spin-orbit interaction (SOI). As a result, we observed an Onsager symmetry related to relativistic magnetic fields, which provided us with indispensable information for the semiclassical billiard ball simulation. Our simulations, developed based on the real-space formalism of the weak localization/antilocalization effect including the degree of freedom for electronic spin, reproduced the experimental magnetoconductivity (MC) curves with high fidelity. The values of five distinct electron parameters (Fermi wavelength, spin precession angles per unit length for two different SOIs, impurity scattering length, and phase coherence length) were thereby extracted from a single MC curve. The methodology developed here is applicable to wide ranges of nanomaterials and devices, providing a diagnostic tool for exotic properties of two-dimensional electron systems.

Performance analysis of junction-less double Gate n-p-n impact ionization MOS transistor (JLDG n-IMOS)

NASA Astrophysics Data System (ADS)

Chauhan, Manvendra Singh; Chauhan, R. K.

2018-04-01

This paper demonstrates a Junction-less Double Gate n-p-n Impact ionization MOS transistor (JLDG n-IMOS) on a very light doped p-type silicon body. Device structure proposed in the paper is based on charge plasma concept. There is no metallurgical junctions in the proposed device and does not need any impurity doping to create the drain and source regions. Due to doping-less nature, the fabrication process is simple for JLDG n-IMOS. The double gate engineering in proposed device leads to reduction in avalanche breakdown via impact ionization, generating large number of carriers in drain-body junction, resulting high ION current, small IOFF current and great improvement in ION/IOFF ratio. The simulation and examination of the proposed device have been performed on ATLAS device simulatorsoftware.

Design, processing, and testing of lsi arrays for space station

NASA Technical Reports Server (NTRS)

Lile, W. R.; Hollingsworth, R. J.

1972-01-01

The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.

Top and Split Gating Control of the Electrical Characteristics of a Two-dimensional Electron Gas in a LaAlO3/SrTiO3 Perovskite

NASA Astrophysics Data System (ADS)

Kwak, Yongsu; Song, Jonghyun; Kim, Jihwan; Kim, Jinhee

2018-04-01

A top gate field effect transistor was fabricated using polymethyl methacrylate (PMMA) as a gate insulator on a LaAlO3 (LAO)/SrTiO3 (STO) hetero-interface. It showed n-type behavior, and a depletion mode was observed at low temperature. The electronic properties of the 2-dimensional electron gas at the LAO/STO hetero-interface were not changed by covering LAO with PMMA following the Au top gate electrode. A split gate device was also fabricated to construct depletion mode by using a narrow constriction between the LAO/STO conduction interface. The depletion mode, as well as superconducting critical current, could be controlled by applying a split gate voltage. Noticeably, the superconducting critical current tended to decrease with decreasing the split gate voltage and finally became zero. These results indicate that a weak-linked Josephson junction can be constructed and destroyed by split gating. This observation opens the possibility of gate-voltage-adjustable quantum devices.

Gate tunable parallel double quantum dots in InAs double-nanowire devices

NASA Astrophysics Data System (ADS)

Baba, S.; Matsuo, S.; Kamata, H.; Deacon, R. S.; Oiwa, A.; Li, K.; Jeppesen, S.; Samuelson, L.; Xu, H. Q.; Tarucha, S.

2017-12-01

We report fabrication and characterization of InAs nanowire devices with two closely placed parallel nanowires. The fabrication process we develop includes selective deposition of the nanowires with micron scale alignment onto predefined finger bottom gates using a polymer transfer technique. By tuning the double nanowire with the finger bottom gates, we observed the formation of parallel double quantum dots with one quantum dot in each nanowire bound by the normal metal contact edges. We report the gate tunability of the charge states in individual dots as well as the inter-dot electrostatic coupling. In addition, we fabricate a device with separate normal metal contacts and a common superconducting contact to the two parallel wires and confirm the dot formation in each wire from comparison of the transport properties and a superconducting proximity gap feature for the respective wires. With the fabrication techniques established in this study, devices can be realized for more advanced experiments on Cooper-pair splitting, generation of Parafermions, and so on.

Analytical Modeling of Triple-Metal Hetero-Dielectric DG SON TFET

NASA Astrophysics Data System (ADS)

Mahajan, Aman; Dash, Dinesh Kumar; Banerjee, Pritha; Sarkar, Subir Kumar

2018-02-01

In this paper, a 2-D analytical model of triple-metal hetero-dielectric DG TFET is presented by combining the concepts of triple material gate engineering and hetero-dielectric engineering. Three metals with different work functions are used as both front- and back gate electrodes to modulate the barrier at source/channel and channel/drain interface. In addition to this, front gate dielectric consists of high-K HfO2 at source end and low-K SiO2 at drain side, whereas back gate dielectric is replaced by air to further improve the ON current of the device. Surface potential and electric field of the proposed device are formulated solving 2-D Poisson's equation and Young's approximation. Based on this electric field expression, tunneling current is obtained by using Kane's model. Several device parameters are varied to examine the behavior of the proposed device. The analytical model is validated with TCAD simulation results for proving the accuracy of our proposed model.

Realization of Molecular-Based Transistors.

PubMed

Richter, Shachar; Mentovich, Elad; Elnathan, Roey

2018-06-06

Molecular-based devices are widely considered as significant candidates to play a role in the next generation of "post-complementary metal-oxide-semiconductor" devices. In this context, molecular-based transistors: molecular junctions that can be electrically gated-are of particular interest as they allow new modes of operation. The properties of molecular transistors composed of a single- or multimolecule assemblies, focusing on their practicality as real-world devices, concerning industry demands and its roadmap are compared. Also, the capability of the gate electrode to modulate the molecular transistor characteristics efficiently is addressed, showing that electrical gating can be easily facilitated in single molecular transistors and that gating of transistor composed of molecular assemblies is possible if the device is formed vertically. It is concluded that while the single-molecular transistor exhibits better performance on the lab-scale, its realization faces signifacant challenges when compared to those faced by transistors composed of a multimolecule assembly. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Terahertz signal detection in a short gate length field-effect transistor with a two-dimensional electron gas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vostokov, N. V., E-mail: vostokov@ipm.sci-nnov.ru; Shashkin, V. I.

2015-11-28

We consider the problem of non-resonant detection of terahertz signals in a short gate length field-effect transistor having a two-dimensional electron channel with zero external bias between the source and the drain. The channel resistance, gate-channel capacitance, and quadratic nonlinearity parameter of the transistor during detection as a function of the gate bias voltage are studied. Characteristics of detection of the transistor connected in an antenna with real impedance are analyzed. The consideration is based on both a simple one-dimensional model of the transistor and allowance for the two-dimensional distribution of the electric field in the transistor structure. The resultsmore » given by the different models are discussed.« less

Integrated-optics heralded controlled-NOT gate for polarization-encoded qubits

NASA Astrophysics Data System (ADS)

Zeuner, Jonas; Sharma, Aditya N.; Tillmann, Max; Heilmann, René; Gräfe, Markus; Moqanaki, Amir; Szameit, Alexander; Walther, Philip

2018-03-01

Recent progress in integrated-optics technology has made photonics a promising platform for quantum networks and quantum computation protocols. Integrated optical circuits are characterized by small device footprints and unrivalled intrinsic interferometric stability. Here, we take advantage of femtosecond-laser-written waveguides' ability to process polarization-encoded qubits and present an implementation of a heralded controlled-NOT gate on chip. We evaluate the gate performance in the computational basis and a superposition basis, showing that the gate can create polarization entanglement between two photons. Transmission through the integrated device is optimized using thermally expanded core fibers and adiabatically reduced mode-field diameters at the waveguide facets. This demonstration underlines the feasibility of integrated quantum gates for all-optical quantum networks and quantum repeaters.

Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

NASA Astrophysics Data System (ADS)

Park, C. H.; Im, Seongil; Yun, Jungheum; Lee, Gun Hwan; Lee, Byoung H.; Sung, Myung M.

2009-11-01

We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgOx and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgOx gate operates under low voltage write-erase (WR-ER) pulse of ±20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of ±70 V for WR and ER states. Both devices stably operated under visible illuminations.

Static and Turn-on Switching Characteristics of 4H-Silicon Carbide SITs to 200 deg C

NASA Technical Reports Server (NTRS)

Niedra, Janis M.; Schwarze, Gene E.

2005-01-01

Test results are presented for normally-off 4H-SiC Static Induction Transistors (SITs) intended for power switching and are among the first normally-off such devices realized in SiC. At zero gate bias, the gate p-n junction depletion layers extend far enough into the conduction channel to cut off the channel. Application of forward gate bias narrows the depletion regions, opening up the channel to conduction by majority carriers. In the present devices, narrow vertical channels get pinched by depletion regions from opposite sides. Since the material is SiC, the devices are usable at temperatures above 150 C. Static curve and pulse mode switching observations were done at selected temperatures up to 200 C on a device with average static characteristics from a batch of similar devices. Gate and drain currents were limited to about 400 mA and 3.5 A, respectively. The drain voltage was limited to roughly 300 V, which is conservative for this 600 V rated device. At 23 C, 1 kW, or even more, could be pulse mode switched in 65 ns (10 to 90 percent) into a 100 load. But at 200 C, the switching capability is greatly reduced in large part by the excessive gate current required. Severe collapse of the saturated drain-to-source current was observed at 200 C. The relation of this property to channel mobility is reviewed.

Self aligned hysteresis free carbon nanotube field-effect transistors

NASA Astrophysics Data System (ADS)

Shlafman, M.; Tabachnik, T.; Shtempluk, O.; Razin, A.; Kochetkov, V.; Yaish, Y. E.

2016-04-01

Hysteresis phenomenon in the transfer characteristics of carbon nanotube field effect transistor (CNT FET) is being considered as the main obstacle for successful realization of electronic devices based on CNTs. In this study, we prepare four kinds of CNTFETs and explore their hysteretic behavior. Two kinds of devices comprise on-surface CNTs (type I) and suspended CNTs (type II) with thin insulating layer underneath and a single global gate which modulates the CNT conductance. The third and fourth types (types III and IV) consist of suspended CNT over a metallic local gate underneath, where for type IV the local gate was patterned self aligned with the source and drain electrodes. The first two types of devices, i.e., type I and II, exhibit substantial hysteresis which increases with scanning range and sweeping time. Under high vacuum conditions and moderate electric fields ( |E |>4 ×106 V /cm ), the hysteresis for on-surface devices cannot be eliminated, as opposed to suspended devices. Interestingly, type IV devices exhibit no hysteresis at all at ambient conditions, and from the different roles which the global and local gates play for the four types of devices, we could learn about the hysteresis mechanism of this system. We believe that these self aligned hysteresis free FETs will enable the realization of different electronic devices and sensors based on CNTs.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

PubMed

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2

NASA Astrophysics Data System (ADS)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-01

Top-gated and bottom-gated transistors with multilayer MoS2 channel fully encapsulated by stacked Al2O3/HfO2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on–off current ratio of 108, high field-effect mobility of 102 cm2 V‑1 s‑1, and low subthreshold swing of 93 mV dec–1. Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10‑3–10‑2 V MV–1 cm–1 after 6 MV cm‑1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS2 channel fully encapsulated by stacked Al2O3/HfO2 is a promising way to fabricate high-performance ML MoS2 field-effect transistors for practical electron device applications.

GaN HEMTs with p-GaN gate: field- and time-dependent degradation

NASA Astrophysics Data System (ADS)

Meneghesso, G.; Meneghini, M.; Rossetto, I.; Canato, E.; Bartholomeus, J.; De Santi, C.; Trivellin, N.; Zanoni, E.

2017-02-01

GaN-HEMTs with p-GaN gate have recently demonstrated to be excellent normally-off devices for application in power conversion systems, thanks to the high and robust threshold voltage (VTH>1 V), the high breakdown voltage, and the low dynamic Ron increase. For this reason, studying the stability and reliability of these devices under high stress conditions is of high importance. This paper reports on our most recent results on the field- and time-dependent degradation of GaN-HEMTs with p-GaN gate submitted to stress with positive gate bias. Based on combined step-stress experiments, constant voltage stress and electroluminescence testing we demonstrated that: (i) when submitted to high/positive gate stress, the transistors may show a negative threshold voltage shift, that is ascribed to the injection of holes from the gate metal towards the p-GaN/AlGaN interface; (ii) in a step-stress experiment, the analyzed commercial devices fail at gate voltages higher than 9-10 V, due to the extremely high electric field over the p-GaN/AlGaN stack; (iii) constant voltage stress tests indicate that the failure is also time-dependent and Weibull distributed. The several processes that can explain the time-dependent failure are discussed in the following.

Experimental Demonstration of xor Operation in Graphene Magnetologic Gates at Room Temperature

NASA Astrophysics Data System (ADS)

Wen, Hua; Dery, Hanan; Amamou, Walid; Zhu, Tiancong; Lin, Zhisheng; Shi, Jing; Žutić, Igor; Krivorotov, Ilya; Sham, L. J.; Kawakami, Roland K.

2016-04-01

We report the experimental demonstration of a magnetologic gate built on graphene at room temperature. This magnetologic gate consists of three ferromagnetic electrodes contacting a single-layer graphene spin channel and relies on spin injection and spin transport in the graphene. We utilize electrical bias tuning of spin injection to balance the inputs and achieve "exclusive or" (xor) logic operation. Furthermore, a simulation of the device performance shows that substantial improvement towards spintronic applications can be achieved by optimizing the device parameters such as the device dimensions. This advance holds promise as a basic building block for spin-based information processing.

First-principles study of the variation of electron transport in a single molecular junction with the length of the molecular wire

NASA Astrophysics Data System (ADS)

Pal, Partha Pratim; Pati, Ranjit

2010-07-01

We report a first-principles study of quantum transport in a prototype two-terminal device consisting of a molecular nanowire acting as an inter-connect between two gold electrodes. The wire is composed of a series of bicyclo[1.1.1]pentane (BCP) cage-units. The length of the wire (L) is increased by sequentially increasing the number of BCP cage units in the wire from 1 to 3. A two terminal model device is made out of each of the three wires. A parameter free, nonequilibrium Green’s function approach, in which the bias effect is explicitly included within a many body framework, is used to calculate the current-voltage characteristics of each of the devices. In the low bias regime that is considered in our study, the molecular devices are found to exhibit Ohmic behavior with resistances of 0.12, 1.4, and 6.5μΩ for the wires containing one, two, and three cages respectively. Thus the conductance value, Gc , which is the reciprocal of resistance, decreases as e-βL with a decay constant (β) of 0.59Å-1 . This observed variation of conductance with the length of the wire is in excellent agreement with the earlier reported exponential decay feature of the electron transfer rate predicted from the electron transfer coupling matrix values obtained using the two-state Marcus-Hush model and the Koopman’s theorem approximation. The downright suppression of the computed electrical current for a bias up to 0.4 V in the longest wire can be exploited in designing a three terminal molecular transistor; this molecular wire could potentially be used as a throttle to avoid leakage gate current.

Vacuum field-effect transistor with a deep submicron channel fabricated by electro-forming

NASA Astrophysics Data System (ADS)

Wang, Xiao; Shen, Zhihua; Wu, Shengli; Zhang, Jintao

2017-06-01

Vacuum field-effect transistors (VFETs) with channel lengths down to 500 nm (i.e., the deep submicron scale) were fabricated with the mature technology of the surface conduction electron emitter fabrication process in our former experiments. The vacuum channel of this new VFET was generated by using the electro-forming process. During electro-forming, the joule heat cracks the conductive film and then generates the submicron scale gap that serves as the vacuum channel. The gap separates the conductive film into two plane-to-plane electrodes, which serve as a source (cathode) electrode and a drain (anode) electrode of the VFET, respectively. Experimental results reveal that the fabricated device demonstrates a clear triode behavior of the gate modulation. Fowler-Nordheim theory was used to analyze the electron emission mechanism and operating principle of the device.

Controllable transport of a skyrmion in a ferromagnetic narrow channel with voltage-controlled magnetic anisotropy

NASA Astrophysics Data System (ADS)

Wang, Junlin; Xia, Jing; Zhang, Xichao; Zhao, G. P.; Ye, Lei; Wu, Jing; Xu, Yongbing; Zhao, Weisheng; Zou, Zhigang; Zhou, Yan

2018-05-01

Magnetic skyrmions have potential applications in next-generation spintronic devices with ultralow energy consumption. In this work, the current-driven skyrmion motion in a narrow ferromagnetic nanotrack with voltage-controlled magnetic anisotropy (VCMA) is studied numerically. By utilizing the VCMA effect, the transport of skyrmion can be unidirectional in the nanotrack, leading to a one-way information channel. The trajectory of the skyrmion can also be modulated by periodically located VCMA gates, which protects the skyrmion from destruction by touching the track edge. In addition, the location of the skyrmion can be controlled by adjusting the driving pulse length in the presence of the VCMA effect. Our results provide guidelines for practical realization of the skyrmion-based information channel, diode, and skyrmion-based electronic devices such as racetrack memory.

Surface plasmon polaritons in a topological insulator embedded in an optical cavity

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, L. L., E-mail: lllihfcas@foxmail.com; Xu, W., E-mail: wenxu-issp@aliyun.com; Department of Physics, Yunnan University, Kunming 650091

Very recently, the surface plasmons in a topological insulator (TI) have been experimentally observed by exciting these collective modes with polarized light [P. Di Pietro, M. Ortolani, O. Limaj, A. Di Gaspare, V. Giliberti, F. Giorgianni, M. Brahlek, N. Bansal, N. Koirala, S. Oh, P. Calvani, and S. Lupi, Nat. Nanotechnol. 8, 556 (2013)]. Motivated by this experimental work, here we present a theoretical study on the surface plasmon polaritons (SPPs) induced by plasmon-photon interactions in a TI thin film embedded in an optical cavity. It is found that the frequencies of SPP modes are within the terahertz (THz) bandwidthmore » and can be tuned effectively by adjusting the surface electron density and/or the optical cavity length. Since the surface electron density can be well controlled by the gate-voltage applied perpendicular to the TI surface, our theoretical results indicate that gated TI thin films may have potential applications in the electrically tunable THz plasmonic devices.« less

Surface plasmon polaritons in a topological insulator embedded in an optical cavity

NASA Astrophysics Data System (ADS)

Li, L. L.; Xu, W.

2014-03-01

Very recently, the surface plasmons in a topological insulator (TI) have been experimentally observed by exciting these collective modes with polarized light [P. Di Pietro, M. Ortolani, O. Limaj, A. Di Gaspare, V. Giliberti, F. Giorgianni, M. Brahlek, N. Bansal, N. Koirala, S. Oh, P. Calvani, and S. Lupi, Nat. Nanotechnol. 8, 556 (2013)]. Motivated by this experimental work, here we present a theoretical study on the surface plasmon polaritons (SPPs) induced by plasmon-photon interactions in a TI thin film embedded in an optical cavity. It is found that the frequencies of SPP modes are within the terahertz (THz) bandwidth and can be tuned effectively by adjusting the surface electron density and/or the optical cavity length. Since the surface electron density can be well controlled by the gate-voltage applied perpendicular to the TI surface, our theoretical results indicate that gated TI thin films may have potential applications in the electrically tunable THz plasmonic devices.

Surface code architecture for donors and dots in silicon with imprecise and nonuniform qubit couplings

DOE PAGES

Pica, G.; Lovett, B. W.; Bhatt, R. N.; ...

2016-01-14

A scaled quantum computer with donor spins in silicon would benefit from a viable semiconductor framework and a strong inherent decoupling of the qubits from the noisy environment. Coupling neighboring spins via the natural exchange interaction according to current designs requires gate control structures with extremely small length scales. In this work, we present a silicon architecture where bismuth donors with long coherence times are coupled to electrons that can shuttle between adjacent quantum dots, thus relaxing the pitch requirements and allowing space between donors for classical control devices. An adiabatic SWAP operation within each donor/dot pair solves the scalabilitymore » issues intrinsic to exchange-based two-qubit gates, as it does not rely on subnanometer precision in donor placement and is robust against noise in the control fields. In conclusion, we use this SWAP together with well established global microwave Rabi pulses and parallel electron shuttling to construct a surface code that needs minimal, feasible local control.« less

Improved performance of graphene transistors by strain engineering.

PubMed

Nguyen, V Hung; Nguyen, Huy-Viet; Dollfus, P

2014-04-25

By means of numerical simulation, in this work we study the effects of uniaxial strain on the transport properties of strained graphene heterojunctions and explore the possibility of achieving good performance of graphene transistors using these hetero-channels. It is shown that a finite conduction gap can open in the strain junctions due to strain-induced deformation of the graphene bandstructure. These hetero-channels are then demonstrated to significantly improve the operation of graphene field-effect transistors (FETs). In particular, the ON/OFF current ratio can reach a value of over 10(5). In graphene normal FETs, the transconductance, although reduced compared to the case of unstrained devices, is still high, while good saturation of current can be obtained. This results in a high voltage gain and a high transition frequency of a few hundreds of GHz for a gate length of 80 nm. In graphene tunneling FETs, subthreshold swings lower than 30 mV /dec, strong nonlinear effects such as gate-controllable negative differential conductance, and current rectification are observed.

A type of all-optical logic gate based on graphene surface plasmon polaritons

NASA Astrophysics Data System (ADS)

Wu, Xiaoting; Tian, Jinping; Yang, Rongcao

2017-11-01

In this paper, a novel type of all-optical logic device based on graphene surface plasmon polaritons (GSP) is proposed. By utilizing linear interference between the GSP waves propagating in the different channels, this new structure can realize six different basic logic gates including OR, XOR, NOT, AND, NOR, and NAND. The state of ;ON/OFF; of each input channel can be well controlled by tuning the optical conductivity of graphene sheets, which can be further controlled by changing the external gate voltage. This type of logic gate is compact in geometrical sizes and is a potential block in the integration of nanophotonic devices.

Quasi-classical modeling of molecular quantum-dot cellular automata multidriver gates

NASA Astrophysics Data System (ADS)

Rahimi, Ehsan; Nejad, Shahram Mohammad

2012-05-01

Molecular quantum-dot cellular automata (mQCA) has received considerable attention in nanoscience. Unlike the current-based molecular switches, where the digital data is represented by the on/off states of the switches, in mQCA devices, binary information is encoded in charge configuration within molecular redox centers. The mQCA paradigm allows high device density and ultra-low power consumption. Digital mQCA gates are the building blocks of circuits in this paradigm. Design and analysis of these gates require quantum chemical calculations, which are demanding in computer time and memory. Therefore, developing simple models to probe mQCA gates is of paramount importance. We derive a semi-classical model to study the steady-state output polarization of mQCA multidriver gates, directly from the two-state approximation in electron transfer theory. The accuracy and validity of this model are analyzed using full quantum chemistry calculations. A complete set of logic gates, including inverters and minority voters, are implemented to provide an appropriate test bench in the two-dot mQCA regime. We also briefly discuss how the QCADesigner tool could find its application in simulation of mQCA devices.

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Impact of device engineering on analog/RF performances of tunnel field effect transistors

NASA Astrophysics Data System (ADS)

Vijayvargiya, V.; Reniwal, B. S.; Singh, P.; Vishvakarma, S. K.

2017-06-01

The tunnel field effect transistor (TFET) and its analog/RF performance is being aggressively studied at device architecture level for low power SoC design. Therefore, in this paper we have investigated the influence of the gate-drain underlap (UL) and different dielectric materials for the spacer and gate oxide on DG-TFET (double gate TFET) and its analog/RF performance for low power applications. Here, it is found that the drive current behavior in DG-TFET with a UL feature while implementing dielectric material for the spacer is different in comparison to that of DG-FET. Further, hetero gate dielectric-based DG-TFET (HGDG-TFET) is more resistive against drain-induced barrier lowering (DIBL) as compared to DG-TFET with high-k (HK) gate dielectric. Along with that, as compared to DG-FET, this paper also analyses the attributes of UL and dielectric material on analog/RF performance of DG-TFET in terms of transconductance (gm ), transconductance generation factor (TGF), capacitance, intrinsic resistance (Rdcr), cut-off frequency (F T), and maximum oscillation frequency (F max). The LK spacer-based HGDG-TFET with a gate-drain UL has the potential to improve the RF performance of device.

Gate engineered heterostructure junctionless TFET with Gaussian doping profile for ambipolar suppression and electrical performance improvement

NASA Astrophysics Data System (ADS)

Aghandeh, Hadi; Sedigh Ziabari, Seyed Ali

2017-11-01

This study investigates a junctionless tunnel field-effect transistor with a dual material gate and a heterostructure channel/source interface (DMG-H-JLTFET). We find that using the heterostructure interface improves device behavior by reducing the tunneling barrier width at the channel/source interface. Simultaneously, the dual material gate structure decreases ambipolar current by increasing the tunneling barrier width at the drain/channel interface. The performance of the device is analyzed based on the energy band diagram at on, off, and ambipolar states. Numerical simulations demonstrate improvements in ION, IOFF, ION/IOFF, subthreshold slope (SS), transconductance and cut-off frequency and suppressed ambipolar behavior. Next, the workfunction optimization of dual material gate is studied. It is found that if appropriate workfunctions are selected for tunnel and auxiliary gates, the JLTFET exhibits considerably improved performance. We then study the influence of Gaussian doping distribution at the drain and the channel on the ambipolar performance of the device and find that a Gaussian doping profile and a dual material gate structure remarkably reduce ambipolar current. Gaussian doped DMG-H-JLTFET, also exhibits enhanced IOFF, ION/IOFF, SS and a low threshold voltage without degrading IOFF.

Performance characteristics of a nanoscale double-gate reconfigurable array

NASA Astrophysics Data System (ADS)

Beckett, Paul

2008-12-01

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

Gate-Sensing the Potential Landscape of a GaAs Two-Dimensional Electron Gas

NASA Astrophysics Data System (ADS)

Croot, Xanthe; Mahoney, Alice; Pauka, Sebastian; Colless, James; Reilly, David; Watson, John; Fallahi, Saeed; Gardner, Geoff; Manfra, Michael; Lu, Hong; Gossard, Arthur

In situ dispersive gate sensors hold potential as a means of enabling the scalable readout of quantum dot arrays. Sensitive to quantum capacitance, dispersive sensors have been used to detect inter- and intra-dot transitions in GaAs double quantum dots, and can distinguish the spin states of singlet triplet qubits. In addition, the gate-sensing technique is likely of value in probing the physics of Majorana zero modes in nanowire devices. Beyond the readout signatures associated with charge and spin configurations of qubits, gate-sensing is sensitive to trapped charge in the potential landscape. Here, we report gate-sensing signals arising from tunnelling of electrons between puddles of trapped charge in a GaAs 2DEG. We examine these signals in a family of different devices with varying mobilities, and as a function of temperature and bias. Implications for qubit readout using the gate-sensing technique are discussed.

GATE AND VACUUM FLUSHING OF SEWER SEDIMENT: LABORATORY TESTING

EPA Science Inventory

The objective of this study was to test the performance of a traditional gate-flushing device and a newly-designed vacuum-flushing device in removing sediment from combined sewers and CSO storage tanks. A laboratory hydraulic flume was used to simulate a reach of sewer or storag...

Irradiation of MOS-FET devices to provide desired logic functions

NASA Technical Reports Server (NTRS)

Danchenko, V.; Schaefer, D. H.

1972-01-01

Gamma, X-ray, electron, or other radiation is used to shift threshold potentials of MOS devices on logic circuits. Before irradiation MOS gates to be shifted are biased positive and other gates are grounded to substrate. Threshold lasts 10 years. Thermal annealing brings circuit back to original configuration.

SEWER SEDIMENT GATE AND VACUUM FLUSHING TANKS: LABORATORY FLUME STUDIES

EPA Science Inventory

The objective of this study was to test the performance of a traditional gate-flushing device and a newly designed vacuum-flushing device in removing sediments from combined sewers and CSO storage tanks. A laboratory hydraulic flune was used to simulate a reach of sewer or storag...

Energy-band engineering for tunable memory characteristics through controlled doping of reduced graphene oxide.

PubMed

Han, Su-Ting; Zhou, Ye; Yang, Qing Dan; Zhou, Li; Huang, Long-Biao; Yan, Yan; Lee, Chun-Sing; Roy, Vellaisamy A L

2014-02-25

Tunable memory characteristics are used in multioperational mode circuits where memory cells with various functionalities are needed in one combined device. It is always a challenge to obtain control over threshold voltage for multimode operation. On this regard, we use a strategy of shifting the work function of reduced graphene oxide (rGO) in a controlled manner through doping gold chloride (AuCl3) and obtained a gradient increase of rGO work function. By inserting doped rGO as floating gate, a controlled threshold voltage (Vth) shift has been achieved in both p- and n-type low voltage flexible memory devices with large memory window (up to 4 times for p-type and 8 times for n-type memory devices) in comparison with pristine rGO floating gate memory devices. By proper energy band engineering, we demonstrated a flexible floating gate memory device with larger memory window and controlled threshold voltage shifts.

Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

DOE PAGES

Leng, X.; Bozovic, I.; Bollinger, A. T.

2016-08-10

Epitaxial indium tin oxide films have been grown on both LaAlO 3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers amore » pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices.« less

Fabrication of arrayed Si nanowire-based nano-floating gate memory devices on flexible plastics.

PubMed

Yoon, Changjoon; Jeon, Youngin; Yun, Junggwon; Kim, Sangsig

2012-01-01

Arrayed Si nanowire (NW)-based nano-floating gate memory (NFGM) devices with Pt nanoparticles (NPs) embedded in Al2O3 gate layers are successfully constructed on flexible plastics by top-down approaches. Ten arrayed Si NW-based NFGM devices are positioned on the first level. Cross-linked poly-4-vinylphenol (PVP) layers are spin-coated on them as isolation layers between the first and second level, and another ten devices are stacked on the cross-linked PVP isolation layers. The electrical characteristics of the representative Si NW-based NFGM devices on the first and second levels exhibit threshold voltage shifts, indicating the trapping and detrapping of electrons in their NPs nodes. They have an average threshold voltage shift of 2.5 V with good retention times of more than 5 x 10(4) s. Moreover, most of the devices successfully retain their electrical characteristics after about one thousand bending cycles. These well-arrayed and stacked Si NW-based NFGM devices demonstrate the potential of nanowire-based devices for large-scale integration.

33 CFR 401.48 - Turning basins.

Code of Federal Regulations, 2011 CFR

2011-07-01

.... 1—Opposite Brossard. (b) Turning Basin No. 2—Between Lock 7 and the Guard Gate Cut for vessels up to... vessels up to 107 m in overall length. (b) Turning Basin No. 2—Between Lock 7 and the Guard Gate Cut for...). (d) Turning Basin No. 4—North of Lock No. 8 for vessels up to 170 m in overall length. (e) For...

33 CFR 401.48 - Turning basins.

Code of Federal Regulations, 2010 CFR

2010-07-01

.... 1—Opposite Brossard. (b) Turning Basin No. 2—Between Lock 7 and the Guard Gate Cut for vessels up to... vessels up to 107 m in overall length. (b) Turning Basin No. 2—Between Lock 7 and the Guard Gate Cut for...). (d) Turning Basin No. 4—North of Lock No. 8 for vessels up to 170 m in overall length. (e) For...

Technical Note: High temporal resolution characterization of gating response time.

PubMed

Wiersma, Rodney D; McCabe, Bradley P; Belcher, Andrew H; Jensen, Patrick J; Smith, Brett; Aydogan, Bulent

2016-06-01

Low temporal latency between a gating ON/OFF signal and the LINAC beam ON/OFF during respiratory gating is critical for patient safety. Here the authors describe a novel method to precisely measure gating lag times at high temporal resolutions. A respiratory gating simulator with an oscillating platform was modified to include a linear potentiometer for position measurement. A photon diode was placed at linear accelerator isocenter for beam output measurement. The output signals of the potentiometer and diode were recorded simultaneously at 2500 Hz with an analog to digital converter for four different commercial respiratory gating systems. The ON and OFF of the beam signal were located and compared to the expected gating window for both phase and position based gating and the temporal lag times extracted. For phase based gating, a real-time position management (RPM) infrared marker tracking system with a single camera and a RPM system with a stereoscopic camera were measured to have mean gate ON/OFF lag times of 98/90 and 86/44 ms, respectively. For position based gating, an AlignRT 3D surface system and a Calypso magnetic fiducial tracking system were measured to have mean gate ON/OFF lag times of 356/529 and 209/60 ms, respectively. Temporal resolution of the method was high enough to allow characterization of individual gate cycles and was primary limited by the sampling speed of the data recording device. Significant variation of mean gate ON/OFF lag time was found between different gating systems. For certain gating devices, individual gating cycle lag times can vary significantly.

Technical Note: High temporal resolution characterization of gating response time

PubMed Central

Wiersma, Rodney D.; McCabe, Bradley P.; Belcher, Andrew H.; Jensen, Patrick J.; Smith, Brett; Aydogan, Bulent

2016-01-01

Purpose: Low temporal latency between a gating ON/OFF signal and the LINAC beam ON/OFF during respiratory gating is critical for patient safety. Here the authors describe a novel method to precisely measure gating lag times at high temporal resolutions. Methods: A respiratory gating simulator with an oscillating platform was modified to include a linear potentiometer for position measurement. A photon diode was placed at linear accelerator isocenter for beam output measurement. The output signals of the potentiometer and diode were recorded simultaneously at 2500 Hz with an analog to digital converter for four different commercial respiratory gating systems. The ON and OFF of the beam signal were located and compared to the expected gating window for both phase and position based gating and the temporal lag times extracted. Results: For phase based gating, a real-time position management (RPM) infrared marker tracking system with a single camera and a RPM system with a stereoscopic camera were measured to have mean gate ON/OFF lag times of 98/90 and 86/44 ms, respectively. For position based gating, an AlignRT 3D surface system and a Calypso magnetic fiducial tracking system were measured to have mean gate ON/OFF lag times of 356/529 and 209/60 ms, respectively. Conclusions: Temporal resolution of the method was high enough to allow characterization of individual gate cycles and was primary limited by the sampling speed of the data recording device. Significant variation of mean gate ON/OFF lag time was found between different gating systems. For certain gating devices, individual gating cycle lag times can vary significantly. PMID:27277028

Digital gate pulse generator for cycloconverter control

DOEpatents

Klein, Frederick F.; Mutone, Gioacchino A.

1989-01-01

The present invention provides a digital gate pulse generator which controls the output of a cycloconverter used for electrical power conversion applications by determining the timing and delivery of the firing pulses to the switching devices in the cycloconverter. Previous gate pulse generators have been built with largely analog or discrete digital circuitry which require many precision components and periodic adjustment. The gate pulse generator of the present invention utilizes digital techniques and a predetermined series of values to develop the necessary timing signals for firing the switching device. Each timing signal is compared with a reference signal to determine the exact firing time. The present invention is significantly more compact than previous gate pulse generators, responds quickly to changes in the output demand and requires only one precision component and no adjustments.

Double gate impact ionization MOS transistor: Proposal and investigation

NASA Astrophysics Data System (ADS)

Yang, Zhaonian; Zhang, Yue; Yang, Yuan; Yu, Ningmei

2017-02-01

In this paper, a double gate impact ionization MOS (DG-IMOS) transistor with improved performance is proposed and investigated by TCAD simulation. In the proposed design, a second gate is introduced in a conventional impact ionization MOS (IMOS) transistor that lengthens the equivalent channel length and suppresses the band-to-band tunneling. The OFF-state leakage current is reduced by over four orders of magnitude. At the ON-state, the second gate is negatively biased in order to enhance the electric field in the intrinsic region. As a result, the operating voltage does not increase with the increase in the channel length. The simulation result verifies that the proposed DG-IMOS achieves a better switching characteristic than the conventional is achieved. Lastly, the application of the DG-IMOS is discussed theoretically.

Performance analysis of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor

NASA Astrophysics Data System (ADS)

Ahish, S.; Sharma, Dheeraj; Vasantha, M. H.; Kumar, Y. B. N.

2017-03-01

In this paper, analog/RF performance of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor (HJTFET) has been explored. A highly doped n+ layer is placed at the Source-Channel junction in order to improve the horizontal electric field component and thus, improve the realiability of the device. The analog performance of the device is analysed by extracting current-voltage characteristics, transcondutance (gm), gate-to-drain capacitance (Cgd) and gate-to-source capacitance (Cgs). Further, RF performance of the device is evaluated by obtaining cut-off frequency (fT) and Gain Bandwidth (GBW) product. ION /IOFF ratio equal to ≈ 109, subthreshold slope of 27 mV/dec, maximum fT of 2.1 THz and maximum GBW of 484 GHz were achieved. Also, the impact of temperature variation on the linearity performance of the device has been investigated. Furthermore, the circuit level performance of the device is performed by implementing a Common Source (CS) amplifier; maximum gain of 31.11 dB and 3-dB cut-off frequency equal to 91.2 GHz were achieved for load resistance (RL) = 17.5 KΩ.

Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities

PubMed Central

Jung, Han Sae; Tsai, Hsin-Zon; Wong, Dillon; Germany, Chad; Kahn, Salman; Kim, Youngkyou; Aikawa, Andrew S.; Desai, Dhruv K.; Rodgers, Griffin F.; Bradley, Aaron J.; Velasco, Jairo; Watanabe, Kenji; Taniguchi, Takashi; Wang, Feng; Zettl, Alex; Crommie, Michael F.

2015-01-01

Owing to its relativistic low-energy charge carriers, the interaction between graphene and various impurities leads to a wealth of new physics and degrees of freedom to control electronic devices. In particular, the behavior of graphene’s charge carriers in response to potentials from charged Coulomb impurities is predicted to differ significantly from that of most materials. Scanning tunneling microscopy (STM) and scanning tunneling spectroscopy (STS) can provide detailed information on both the spatial and energy dependence of graphene's electronic structure in the presence of a charged impurity. The design of a hybrid impurity-graphene device, fabricated using controlled deposition of impurities onto a back-gated graphene surface, has enabled several novel methods for controllably tuning graphene’s electronic properties.1-8 Electrostatic gating enables control of the charge carrier density in graphene and the ability to reversibly tune the charge2 and/or molecular5 states of an impurity. This paper outlines the process of fabricating a gate-tunable graphene device decorated with individual Coulomb impurities for combined STM/STS studies.2-5 These studies provide valuable insights into the underlying physics, as well as signposts for designing hybrid graphene devices. PMID:26273961

Novel conformal organic antireflective coatings for advanced I-line lithography

NASA Astrophysics Data System (ADS)

Deshpande, Shreeram V.; Nowak, Kelly A.; Fowler, Shelly; Williams, Paul; Arjona, Mikko

2001-08-01

Flash memory chips are playing a critical role in semiconductor devices due to increased popularity of hand held electronic communication devices such as cell phones and PDAs (personal Digital Assistants). Flash memory offers two primary advantages in semiconductor devices. First, it offers flexibility of in-circuit programming capability to reduce the loss from programming errors and to significantly reduce commercialization time to market for new devices. Second, flash memory has a double density memory capability through stacked gate structures which increases the memory capability and thus saves significantly on chip real estate. However, due to stacked gate structures the requirements for manufacturing of flash memory devices are significantly different from traditional memory devices. Stacked gate structures also offer unique challenges to lithographic patterning materials such as Bottom Anti-Reflective Coating (BARC) compositions used to achieve CD control and to minimize standing wave effect in photolithography. To be applicable in flash memory manufacturing a BARC should form a conformal coating on high topography of stacked gate features as well as provide the normal anti-reflection properties for CD control. In this paper we report on a new highly conformal advanced i-line BARC for use in design and manufacture of flash memory devices. Conformal BARCs being significantly thinner in trenches than the planarizing BARCs offer the advantage of reducing BARC overetch and thus minimizing resist thickness loss.

Gate-Controlled BP-WSe2 Heterojunction Diode for Logic Rectifiers and Logic Optoelectronics.

PubMed

Li, Dong; Wang, Biao; Chen, Mingyuan; Zhou, Jun; Zhang, Zengxing

2017-06-01

p-n junctions play an important role in modern semiconductor electronics and optoelectronics, and field-effect transistors are often used for logic circuits. Here, gate-controlled logic rectifiers and logic optoelectronic devices based on stacked black phosphorus (BP) and tungsten diselenide (WSe 2 ) heterojunctions are reported. The gate-tunable ambipolar charge carriers in BP and WSe 2 enable a flexible, dynamic, and wide modulation on the heterojunctions as isotype (p-p and n-n) and anisotype (p-n) diodes, which exhibit disparate rectifying and photovoltaic properties. Based on such characteristics, it is demonstrated that BP-WSe 2 heterojunction diodes can be developed for high-performance logic rectifiers and logic optoelectronic devices. Logic optoelectronic devices can convert a light signal to an electric one by applied gate voltages. This work should be helpful to expand the applications of 2D crystals. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Formation of nanofilament field emission devices

DOEpatents

Morse, Jeffrey D.; Contolini, Robert J.; Musket, Ronald G.; Bernhardt, Anthony F.

2000-01-01

A process for fabricating a nanofilament field emission device. The process enables the formation of high aspect ratio, electroplated nanofilament structure devices for field emission displays wherein a via is formed in a dielectric layer and is self-aligned to a via in the gate metal structure on top of the dielectric layer. The desired diameter of the via in the dielectric layer is on the order of 50-200 nm, with an aspect ratio of 5-10. In one embodiment, after forming the via in the dielectric layer, the gate metal is passivated, after which a plating enhancement layer is deposited in the bottom of the via, where necessary. The nanofilament is then electroplated in the via, followed by removal of the gate passification layer, etch back of the dielectric, and sharpening of the nanofilament. A hard mask layer may be deposited on top of the gate metal and removed following electroplating of the nanofilament.

Trap-mediated electronic transport properties of gate-tunable pentacene/MoS2 p-n heterojunction diodes

PubMed Central

Kim, Jae-Keun; Cho, Kyungjune; Kim, Tae-Young; Pak, Jinsu; Jang, Jingon; Song, Younggul; Kim, Youngrok; Choi, Barbara Yuri; Chung, Seungjun; Hong, Woong-Ki; Lee, Takhee

2016-01-01

We investigated the trap-mediated electronic transport properties of pentacene/molybdenum disulphide (MoS2) p-n heterojunction devices. We observed that the hybrid p-n heterojunctions were gate-tunable and were strongly affected by trap-assisted tunnelling through the van der Waals gap at the heterojunction interfaces between MoS2 and pentacene. The pentacene/MoS2 p-n heterojunction diodes had gate-tunable high ideality factor, which resulted from trap-mediated conduction nature of devices. From the temperature-variable current-voltage measurement, a space-charge-limited conduction and a variable range hopping conduction at a low temperature were suggested as the gate-tunable charge transport characteristics of these hybrid p-n heterojunctions. Our study provides a better understanding of the trap-mediated electronic transport properties in organic/2-dimensional material hybrid heterojunction devices. PMID:27829663

Trap-mediated electronic transport properties of gate-tunable pentacene/MoS2 p-n heterojunction diodes

NASA Astrophysics Data System (ADS)

Kim, Jae-Keun; Cho, Kyungjune; Kim, Tae-Young; Pak, Jinsu; Jang, Jingon; Song, Younggul; Kim, Youngrok; Choi, Barbara Yuri; Chung, Seungjun; Hong, Woong-Ki; Lee, Takhee

2016-11-01

We investigated the trap-mediated electronic transport properties of pentacene/molybdenum disulphide (MoS2) p-n heterojunction devices. We observed that the hybrid p-n heterojunctions were gate-tunable and were strongly affected by trap-assisted tunnelling through the van der Waals gap at the heterojunction interfaces between MoS2 and pentacene. The pentacene/MoS2 p-n heterojunction diodes had gate-tunable high ideality factor, which resulted from trap-mediated conduction nature of devices. From the temperature-variable current-voltage measurement, a space-charge-limited conduction and a variable range hopping conduction at a low temperature were suggested as the gate-tunable charge transport characteristics of these hybrid p-n heterojunctions. Our study provides a better understanding of the trap-mediated electronic transport properties in organic/2-dimensional material hybrid heterojunction devices.

Trap-mediated electronic transport properties of gate-tunable pentacene/MoS2 p-n heterojunction diodes.

PubMed

Kim, Jae-Keun; Cho, Kyungjune; Kim, Tae-Young; Pak, Jinsu; Jang, Jingon; Song, Younggul; Kim, Youngrok; Choi, Barbara Yuri; Chung, Seungjun; Hong, Woong-Ki; Lee, Takhee

2016-11-10

We investigated the trap-mediated electronic transport properties of pentacene/molybdenum disulphide (MoS 2 ) p-n heterojunction devices. We observed that the hybrid p-n heterojunctions were gate-tunable and were strongly affected by trap-assisted tunnelling through the van der Waals gap at the heterojunction interfaces between MoS 2 and pentacene. The pentacene/MoS 2 p-n heterojunction diodes had gate-tunable high ideality factor, which resulted from trap-mediated conduction nature of devices. From the temperature-variable current-voltage measurement, a space-charge-limited conduction and a variable range hopping conduction at a low temperature were suggested as the gate-tunable charge transport characteristics of these hybrid p-n heterojunctions. Our study provides a better understanding of the trap-mediated electronic transport properties in organic/2-dimensional material hybrid heterojunction devices.

Correlation between ambient air and continuous bending stress for the electrical reliability of flexible pentacene-based thin-film transistors

NASA Astrophysics Data System (ADS)

Fan, Ching-Lin; Lin, Wei-Chun; Peng, Han-Hsing; Lin, Yu-Zuo; Huang, Bohr-Ran

2015-01-01

This study investigated how continuous bending stress affects the electrical characteristics of pentacene-based organic thin-film transistors (OTFTs) with poly(4-vinylphenol) (PVP) gate insulator in a vacuum and in ambient air. In tension mode, the strain direction of the fabricated devices was perpendicular to the device channel length. The OTFT devices that were bent in a vacuum exhibited a decreased on current because of cracking in the pentacene channel layer, which can obstruct the transport of charge carriers and deteriorate the on current of the OTFTs. The OTFT devices that were bent in ambient air exhibited a slightly decreased on current and considerably increased off current and subthreshold swing (SS). It was assumed that air moisture passed through the pentacene cracks into the interface between the PVP and pentacene layer, thereby yielding an increase in polar moisture traps, and leading to an increase in the conductivity of the pentacene, thus yielding a slightly decreased on current and considerably increased off current and SS.

Effect of active-layer composition and structure on device performance of coplanar top-gate amorphous oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Yue, Lan; Meng, Fanxin; Chen, Jiarong

2018-01-01

The thin-film transistors (TFTs) with amorphous aluminum-indium-zinc-oxide (a-AIZO) active layer were prepared by dip coating method. The dependence of properties of TFTs on the active-layer composition and structure was investigated. The results indicate that Al atoms acted as a carrier suppressor in IZO films. Meanwhile, it was found that the on/off current ratio (I on/off) of TFT was improved by embedding a high-resistivity AIZO layer between the low-resistivity AIZO layer and gate insulator. The improvement in I on/off was attributed to the decrease in off-state current of double-active-layer TFT due to an increase in the active-layer resistance and the contact resistance between active layer and source/drain electrode. Moreover, on-state current and threshold voltage (V th) can be mainly controlled through thickness and Al content of the low-resistivity AIZO layer. In addition, the saturation mobility (μ sat) of TFTs was improved with reducing the size of channel width or/and length, which was attributed to the decrease in trap states in the semiconductor and at the semiconductor/gate-insulator interface with the smaller channel width or/and shorter channel length. Thus, we can demonstrate excellent TFTs via the design of active-layer composition and structure by utilizing a low cost solution-processed method. The resulting TFT, operating in enhancement mode, has a high μ sat of 14.16 cm2 V-1 s-1, a small SS of 0.40 V/decade, a close-to-zero V th of 0.50 V, and I on/off of more than 105.

Special Component Designs for Differential-Amplifier MMICs

NASA Technical Reports Server (NTRS)

Kangaslahti, Pekka

2010-01-01

Special designs of two types of electronic components transistors and transmission lines have been conceived to optimize the performances of these components as parts of waveguide-embedded differential-amplifier monolithic microwave integrated circuits (MMICs) of the type described in the immediately preceding article. These designs address the following two issues, the combination of which is unique to these particular MMICs: Each MMIC includes a differential double-strip transmission line that typically has an impedance between 60 and 100 W. However, for purposes of matching of impedances, transmission lines having lower impedances are also needed. The transistors in each MMIC are, more specifically, one or more pair(s) of InP-based high-electron-mobility transistors (HEMTs). Heretofore, it has been common practice to fabricate each such pair as a single device configured in the side-to-side electrode sequence source/gate/drain/gate/source. This configuration enables low-inductance source grounding from the sides of the device. However, this configuration is not suitable for differential operation, in which it is necessary to drive the gates differentially and to feed the output from the drain electrodes differentially. The special transmission-line design provides for three conductors, instead of two, in places where lower impedance is needed. The third conductor is a metal strip placed underneath the differential double-strip transmission line. The third conductor increases the capacitance per unit length of the transmission line by such an amount as to reduce the impedance to between 5 and 15 W. In the special HEMT-pair design, the side-to-side electrode sequence is changed to drain/gate/source/gate/ drain. In addition, the size of the source is reduced significantly, relative to corresponding sizes in prior designs. This reduction is justified by the fact that, by virtue of the differential configuration, the device has an internal virtual ground, and therefore there is no need for a low-resistance contact between the source and the radio-frequency circuitry. The source contact is needed only for DC biasing. These designs were implemented in a single-stage-amplifier MMIC. In a test at a frequency of 305 GHz, the amplifier embedded in a waveguide exhibited a gain of 0 dB; after correcting for the loss in the waveguide, the amplifier was found to afford a gain of 0.9 dB. In a test at 220 GHz, the overall gain of the amplifier- and-waveguide assembly was found to be 3.5 dB.

Experimental phase diagram of zero-bias conductance peaks in superconductor/semiconductor nanowire devices

PubMed Central

Chen, Jun; Yu, Peng; Stenger, John; Hocevar, Moïra; Car, Diana; Plissard, Sébastien R.; Bakkers, Erik P. A. M.; Stanescu, Tudor D.; Frolov, Sergey M.

2017-01-01

Topological superconductivity is an exotic state of matter characterized by spinless p-wave Cooper pairing of electrons and by Majorana zero modes at the edges. The first signature of topological superconductivity is a robust zero-bias peak in tunneling conductance. We perform tunneling experiments on semiconductor nanowires (InSb) coupled to superconductors (NbTiN) and establish the zero-bias peak phase in the space of gate voltage and external magnetic field. Our findings are consistent with calculations for a finite-length topological nanowire and provide means for Majorana manipulation as required for braiding and topological quantum bits. PMID:28913432

Coherent molecular transistor: control through variation of the gate wave function.

PubMed

Ernzerhof, Matthias

2014-03-21

In quantum interference transistors (QUITs), the current through the device is controlled by variation of the gate component of the wave function that interferes with the wave function component joining the source and the sink. Initially, mesoscopic QUITs have been studied and more recently, QUITs at the molecular scale have been proposed and implemented. Typically, in these devices the gate lead is subjected to externally adjustable physical parameters that permit interference control through modifications of the gate wave function. Here, we present an alternative model of a molecular QUIT in which the gate wave function is directly considered as a variable and the transistor operation is discussed in terms of this variable. This implies that we specify the gate current as well as the phase of the gate wave function component and calculate the resulting current through the source-sink channel. Thus, we extend on prior works that focus on the phase of the gate wave function component as a control parameter while having zero or certain discrete values of the current. We address a large class of systems, including finite graphene flakes, and obtain analytic solutions for how the gate wave function controls the transistor.

Performance comparison of single and dual metal dielectrically modulated TFETs for the application of label free biosensor

NASA Astrophysics Data System (ADS)

Verma, Madhulika; Sharma, Dheeraj; Pandey, Sunil; Nigam, Kaushal; Kondekar, P. N.

2017-01-01

In this work, we perform a comparative analysis between single and dual metal dielectrically modulated tunnel field-effect transistors (DMTFETs) for the application of label free biosensor. For this purpose, two different gate material with work-function as ϕM 1 and ϕM 2 are used in short-gate DMTFET, where ϕM 1 represents the work-function of gate M1 near to the drain end, while ϕM 2 denotes the work-function of gate M2 near to the source end. A nanogap cavity in the gate dielectric is formed by removing the selected portion of gate oxide for sensing the biomolecules. To investigate the sensitivity of these biosensors, dielectric constant and charge density within the cavity region are considered as governing parameters. The work-function of gate M2 is optimized and considered less than M1 to achieve abruptness at the source/channel junction, which results in better tunneling and improved ON-state current. The ATLAS device simulations show that dual metal SG-DMTFETs attains higher ON-state current and drain current sensitivity as compared to its counterpart device. Finally, a dual metal short-gate (DSG) biosensor is compared with the single metal short-gate (SG), single metal full-gate (FG), and dual metal full-gate (DFG) biosensors to analyse structurally enhanced conjugation effect on gate-channel coupling.

Orientation selectivity in a multi-gated organic electrochemical transistor

NASA Astrophysics Data System (ADS)

Gkoupidenis, Paschalis; Koutsouras, Dimitrios A.; Lonjaret, Thomas; Fairfield, Jessamyn A.; Malliaras, George G.

2016-06-01

Neuromorphic devices offer promising computational paradigms that transcend the limitations of conventional technologies. A prominent example, inspired by the workings of the brain, is spatiotemporal information processing. Here we demonstrate orientation selectivity, a spatiotemporal processing function of the visual cortex, using a poly(3,4ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) organic electrochemical transistor with multiple gates. Spatially distributed inputs on a gate electrode array are found to correlate with the output of the transistor, leading to the ability to discriminate between different stimuli orientations. The demonstration of spatiotemporal processing in an organic electronic device paves the way for neuromorphic devices with new form factors and a facile interface with biology.

Design of a Ferroelectric Programmable Logic Gate Array

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

2003-01-01

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

Anomalous single-electron transfer in common-gate quadruple-dot single-electron devices with asymmetric junction capacitances

NASA Astrophysics Data System (ADS)

Imai, Shigeru; Ito, Masato

2018-06-01

In this paper, anomalous single-electron transfer in common-gate quadruple-dot turnstile devices with asymmetric junction capacitances is revealed. That is, the islands have the same total number of excess electrons at high and low gate voltages of the swing that transfers a single electron. In another situation, two electrons enter the islands from the source and two electrons leave the islands for the source and drain during a gate voltage swing cycle. First, stability diagrams of the turnstile devices are presented. Then, sequences of single-electron tunneling events by gate voltage swings are investigated, which demonstrate the above-mentioned anomalous single-electron transfer between the source and the drain. The anomalous single-electron transfer can be understood by regarding the four islands as “three virtual islands and a virtual source or drain electrode of a virtual triple-dot device”. The anomalous behaviors of the four islands are explained by the normal behavior of the virtual islands transferring a single electron and the behavior of the virtual electrode.

Dual-gated MoS2/WSe2 van der Waals tunnel diodes and transistors.

PubMed

Roy, Tania; Tosun, Mahmut; Cao, Xi; Fang, Hui; Lien, Der-Hsien; Zhao, Peida; Chen, Yu-Ze; Chueh, Yu-Lun; Guo, Jing; Javey, Ali

2015-02-24

Two-dimensional layered semiconductors present a promising material platform for band-to-band-tunneling devices given their homogeneous band edge steepness due to their atomically flat thickness. Here, we experimentally demonstrate interlayer band-to-band tunneling in vertical MoS2/WSe2 van der Waals (vdW) heterostructures using a dual-gate device architecture. The electric potential and carrier concentration of MoS2 and WSe2 layers are independently controlled by the two symmetric gates. The same device can be gate modulated to behave as either an Esaki diode with negative differential resistance, a backward diode with large reverse bias tunneling current, or a forward rectifying diode with low reverse bias current. Notably, a high gate coupling efficiency of ∼80% is obtained for tuning the interlayer band alignments, arising from weak electrostatic screening by the atomically thin layers. This work presents an advance in the fundamental understanding of the interlayer coupling and electron tunneling in semiconductor vdW heterostructures with important implications toward the design of atomically thin tunnel transistors.

Near-IR squaraine dye–loaded gated periodic mesoporous organosilica for photo-oxidation of phenol in a continuous-flow device

PubMed Central

Borah, Parijat; Sreejith, Sivaramapanicker; Anees, Palapuravan; Menon, Nishanth Venugopal; Kang, Yuejun; Ajayaghosh, Ayyappanpillai; Zhao, Yanli

2015-01-01

Periodic mesoporous organosilica (PMO) has been widely used for the fabrication of a variety of catalytically active materials. We report the preparation of novel photo-responsive PMO with azobenzene-gated pores. Upon activation, the azobenzene gate undergoes trans-cis isomerization, which allows an unsymmetrical near-infrared squaraine dye (Sq) to enter into the pores. The gate closure by cis-trans isomerization of the azobenzene unit leads to the safe loading of the monomeric dye inside the pores. The dye-loaded and azobenzene-gated PMO (Sq-azo@PMO) exhibits excellent generation of reactive oxygen species upon excitation at 664 nm, which can be effectively used for the oxidation of phenol into benzoquinone in aqueous solution. Furthermore, Sq-azo@PMO as the catalyst was placed inside a custom-built, continuous-flow device to carry out the photo-oxidation of phenol to benzoquinone in the presence of 664-nm light. By using the device, about 23% production of benzoquinone with 100% selectivity was achieved. The current research presents a prototype of transforming heterogeneous catalysts toward practical use. PMID:26601266

Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance

NASA Astrophysics Data System (ADS)

Yadav, Dharmendra Singh; Verma, Abhishek; Sharma, Dheeraj; Tirkey, Sukeshni; Raad, Bhagwan Ram

2017-11-01

Tunnel-field-effect-transistor (TFET) has emerged as one of the most prominent devices to replace conventional MOSFET due to its ability to provide sub-threshold slope below 60 mV/decade (SS ≤ 60 mV/decade) and low leakage current. Despite this, TFETs suffer from ambipolar behavior, lower ON-state current, and poor RF performance. To address these issues, we have introduced drain and gate work function engineering with hetero gate dielectric for the first time in charge plasma based doping-less TFET (DL TFET). In this, the usage of dual work functionality over the drain region significantly reduces the ambipolar behavior of the device by varying the energy barrier at drain/channel interface. Whereas, the presence of dual work function at the gate terminal increases the ON-state current (ION). The combined effect of dual work function at the gate and drain electrode results in the increment of ON-state current (ION) and decrement of ambipolar conduction (Iambi) respectively. Furthermore, the incorporation of hetero gate dielectric along with dual work functionality at the drain and gate electrode provides an overall improvement in the performance of the device in terms of reduction in ambipolarity, threshold voltage and sub-threshold slope along with improved ON-state current and high frequency figures of merit.

Thermoelectric Power in Bilayer Graphene Device with Ionic Liquid Gating.

PubMed

Chien, Yung-Yu; Yuan, Hongtao; Wang, Chang-Ran; Lee, Wei-Li

2016-02-08

The quest for materials showing large thermoelectric power has long been one of the important subjects in material science and technology. Such materials have great potential for thermoelectric cooling and also high figure of merit ZT thermoelectric applications. We have fabricated bilayer graphene devices with ionic-liquid gating in order to tune its band gap via application of a perpendicular electric field on a bilayer graphene. By keeping the Fermi level at charge neutral point during the cool-down, we found that the charge puddles effect can be greatly reduced and thus largely improve the transport properties at low T in graphene-based devices using ionic liquid gating. At (Vig, Vbg) = (-1 V, +23 V), a band gap of about 36.6 ± 3 meV forms, and a nearly 40% enhancement of thermoelectric power at T = 120 K is clearly observed. Our works demonstrate the feasibility of band gap tuning in a bilayer graphene using ionic liquid gating. We also remark on the significant influence of the charge puddles effect in ionic-liquid-based devices.

Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

PubMed Central

Long, Rathnait D.; McIntyre, Paul C.

2012-01-01

The literature on polar Gallium Nitride (GaN) surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS) devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

Meeting critical gate linewidth control needs at the 65 nm node

NASA Astrophysics Data System (ADS)

Mahorowala, Arpan; Halle, Scott; Gabor, Allen; Chu, William; Barberet, Alexandra; Samuels, Donald; Abdo, Amr; Tsou, Len; Yan, Wendy; Iseda, Seiji; Patel, Kaushal; Dirahoui, Bachir; Nomura, Asuka; Ahsan, Ishtiaq; Azam, Faisal; Berg, Gary; Brendler, Andrew; Zimmerman, Jeffrey; Faure, Tom

2006-03-01

With the nominal gate length at the 65 nm node being only 35 nm, controlling the critical dimension (CD) in polysilicon to within a few nanometers is essential to achieve a competitive power-to-performance ratio. Gate linewidths must be controlled, not only at the chip level so that the chip performs as the circuit designers and device engineers had intended, but also at the wafer level so that more chips with the optimum power-to-performance ratio are manufactured. Achieving tight across-chip linewidth variation (ACLV) and chip mean variation (CMV) is possible only if the mask-making, lithography, and etching processes are all controlled to very tight specifications. This paper identifies the various ACLV and CMV components, describes their root causes, and discusses a methodology to quantify them. For example, the site-to-site ACLV component is divided into systematic and random sub-components. The systematic component of the variation is attributed in part to pattern density variation across the field, and variation in exposure dose across the slit. The paper demonstrates our team's success in achieving the tight gate CD tolerances required for 65 nm technology. Certain key challenges faced, and methods employed to overcome them are described. For instance, the use of dose-compensation strategies to correct the small but systematic CD variations measured across the wafer, is described. Finally, the impact of immersion lithography on both ACLV and CMV is briefly discussed.

Ultrathin strain-gated field effect transistor based on In-doped ZnO nanobelts

NASA Astrophysics Data System (ADS)

Zhang, Zheng; Du, Junli; Li, Bing; Zhang, Shuhao; Hong, Mengyu; Zhang, Xiaomei; Liao, Qingliang; Zhang, Yue

2017-08-01

In this work, we fabricated a strain-gated piezoelectric transistor based on single In-doped ZnO nanobelt with ±(0001) top/bottom polar surfaces. In the vertical structured transistor, the Pt tip of the AFM and Au film are used as source and drain electrode. The electrical transport performance of the transistor is gated by compressive strains. The working mechanism is attributed to the Schottky barrier height changed under the coupling effect of piezoresistive and piezoelectric. Uniquely, the transistor turns off under the compressive stress of 806 nN. The strain-gated transistor is likely to have important applications in high resolution mapping device and MEMS devices.

A 2D analytical cylindrical gate tunnel FET (CG-TFET) model: impact of shortest tunneling distance

NASA Astrophysics Data System (ADS)

Dash, S.; Mishra, G. P.

2015-09-01

A 2D analytical tunnel field-effect transistor (FET) potential model with cylindrical gate (CG-TFET) based on the solution of Laplace’s equation is proposed. The band-to-band tunneling (BTBT) current is derived by the help of lateral electric field and the shortest tunneling distance. However, the analysis is extended to obtain the subthreshold swing (SS) and transfer characteristics of the device. The dependency of drain current, SS and transconductance on gate voltage and shortest tunneling distance is discussed. Also, the effect of scaling the gate oxide thickness and the cylindrical body diameter on the electrical parameters of the device is analyzed.

Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

NASA Astrophysics Data System (ADS)

Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin; Chi, Li-Feng; Wang, Sui-Dong

2015-03-01

Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

2-D modeling and analysis of short-channel behavior of a front high- K gate stack triple-material gate SB SON MOSFET

NASA Astrophysics Data System (ADS)

Banerjee, Pritha; Kumari, Tripty; Sarkar, Subir Kumar

2018-02-01

This paper presents the 2-D analytical modeling of a front high- K gate stack triple-material gate Schottky Barrier Silicon-On-Nothing MOSFET. Using the two-dimensional Poisson's equation and considering the popular parabolic potential approximation, expression for surface potential as well as the electric field has been considered. In addition, the response of the proposed device towards aggressive downscaling, that is, its extent of immunity towards the different short-channel effects, has also been considered in this work. The analytical results obtained have been validated using the simulated results obtained using ATLAS, a two-dimensional device simulator from SILVACO.

Design and simulation of a novel 1400 V-4000 V enhancement mode buried gate GaN HEMT for power applications

NASA Astrophysics Data System (ADS)

Faramehr, Soroush; Kalna, Karol; Igić, Petar

2014-11-01

A novel enhancement mode structure, a buried gate gallium nitride (GaN) high electron mobility transistor (HEMT) with a breakdown voltage (BV) of 1400 V-4000 V for a source-to-drain spacing (LSD) of 6 μm-32 μm, is investigated using simulations by Silvaco Atlas. The simulations are based on meticulous calibration of a conventional lateral 1 μm gate length GaN HEMT with a source-to-drain spacing of 6 μm against its experimental transfer characteristics and BV. The specific on-resistance RS for the new power transistor with the source-to-drain spacing of 6 μm showing BV = 1400 V and the source-to-drain spacing of 8 μm showing BV = 1800 V is found to be 2.3 mΩ · cm2 and 3.5 mΩ · cm2, respectively. Further improvement up to BV = 4000 V can be achieved by increasing the source-to-drain spacing to 32 μm with the specific on-resistance of RS = 35.5 mΩ · cm2. The leakage current in the proposed devices stays in the range of ˜5 × 10-9 mA mm-1.

Development of two-framing camera with large format and ultrahigh speed

NASA Astrophysics Data System (ADS)

Jiang, Xiaoguo; Wang, Yuan; Wang, Yi

2012-10-01

High-speed imaging facility is important and necessary for the formation of time-resolved measurement system with multi-framing capability. The framing camera which satisfies the demands of both high speed and large format needs to be specially developed in the ultrahigh speed research field. A two-framing camera system with high sensitivity and time-resolution has been developed and used for the diagnosis of electron beam parameters of Dragon-I linear induction accelerator (LIA). The camera system, which adopts the principle of light beam splitting in the image space behind the lens with long focus length, mainly consists of lens-coupled gated image intensifier, CCD camera and high-speed shutter trigger device based on the programmable integrated circuit. The fastest gating time is about 3 ns, and the interval time between the two frames can be adjusted discretely at the step of 0.5 ns. Both the gating time and the interval time can be tuned to the maximum value of about 1 s independently. Two images with the size of 1024×1024 for each can be captured simultaneously in our developed camera. Besides, this camera system possesses a good linearity, uniform spatial response and an equivalent background illumination as low as 5 electrons/pix/sec, which fully meets the measurement requirements of Dragon-I LIA.

Low-frequency noise in AlN/AlGaN/GaN metal-insulator-semiconductor devices: A comparison with Schottky devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Le, Son Phuong; Nguyen, Tuan Quy; Shih, Hong-An

2014-08-07

We have systematically investigated low-frequency noise (LFN) in AlN/AlGaN/GaN metal-insulator-semiconductor (MIS) devices, where the AlN gate insulator layer was sputtering-deposited on the AlGaN surface, in comparison with LFN in AlGaN/GaN Schottky devices. By measuring LFN in ungated two-terminal devices and heterojunction field-effect transistors (HFETs), we extracted LFN characteristics in the intrinsic gated region of the HFETs. Although there is a bias regime of the Schottky-HFETs in which LFN is dominated by the gate leakage current, LFN in the MIS-HFETs is always dominated by only the channel current. Analyzing the channel-current-dominated LFN, we obtained Hooge parameters α for the gated regionmore » as a function of the sheet electron concentration n{sub s} under the gate. In a regime of small n{sub s}, both the MIS- and Schottky-HFETs exhibit α∝n{sub s}{sup −1}. On the other hand, in a middle n{sub s} regime of the MIS-HFETs, α decreases rapidly like n{sub s}{sup −ξ} with ξ ∼ 2-3, which is not observed for the Schottky-HFETs. In addition, we observe strong increase in α∝n{sub s}{sup 3} in a large n{sub s} regime for both the MIS- and Schottky-HFETs.« less

Technical Note: High temporal resolution characterization of gating response time

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wiersma, Rodney D., E-mail: rwiersma@uchicago.edu; McCabe, Bradley P.; Belcher, Andrew H.

2016-06-15

Purpose: Low temporal latency between a gating ON/OFF signal and the LINAC beam ON/OFF during respiratory gating is critical for patient safety. Here the authors describe a novel method to precisely measure gating lag times at high temporal resolutions. Methods: A respiratory gating simulator with an oscillating platform was modified to include a linear potentiometer for position measurement. A photon diode was placed at linear accelerator isocenter for beam output measurement. The output signals of the potentiometer and diode were recorded simultaneously at 2500 Hz with an analog to digital converter for four different commercial respiratory gating systems. The ONmore » and OFF of the beam signal were located and compared to the expected gating window for both phase and position based gating and the temporal lag times extracted. Results: For phase based gating, a real-time position management (RPM) infrared marker tracking system with a single camera and a RPM system with a stereoscopic camera were measured to have mean gate ON/OFF lag times of 98/90 and 86/44 ms, respectively. For position based gating, an AlignRT 3D surface system and a Calypso magnetic fiducial tracking system were measured to have mean gate ON/OFF lag times of 356/529 and 209/60 ms, respectively. Conclusions: Temporal resolution of the method was high enough to allow characterization of individual gate cycles and was primary limited by the sampling speed of the data recording device. Significant variation of mean gate ON/OFF lag time was found between different gating systems. For certain gating devices, individual gating cycle lag times can vary significantly.« less

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maheran, A. H. Afifah; Menon, P. S.; Shaari, S.

2015-04-24

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (I{sub LEAK}) onmore » PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO{sub 2}) and tungsten silicide (WSi{sub x}). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum I{sub LEAK} where the maximum predicted I{sub LEAK} value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/µm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device’s leakage current. The absolute process parameters combination results in I{sub LEAK} mean value of 3.96821 nA/µm where is far lower than the predicted value.« less

Area efficient layout design of CMOS circuit for high-density ICs

NASA Astrophysics Data System (ADS)

Mishra, Vimal Kumar; Chauhan, R. K.

2018-01-01

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher Ion to Ioff ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.

High voltage and current, gate assisted, turn-off thyristor development

NASA Technical Reports Server (NTRS)

Nowalk, T. P.; Brewster, J. B.; Kao, Y. C.

1972-01-01

An improved high speed power switch with unique turn-off capability was developed. This gate assisted turn-off thyristor (GATT) was rated 1000 volts and 100 amperes with turn-off times of 2 microseconds. Fifty units were delivered for evaluation. In addition, test circuits designed to relate to the series inverter application were built and demonstrated. In the course of this work it was determined that the basic device design is adequate to meet the static characteristics and dynamic turn-off specification. It was further determined that the turn-on specification is critically dependent on the gate drive circuit due to the distributive nature of the cathode-gate geometry. Future work should emphasize design modifications which reduce the gate current required for fast turn-on, thereby opening the way to higher power (current) devices.

Highly sensitive glucose sensors based on enzyme-modified whole-graphene solution-gated transistors

NASA Astrophysics Data System (ADS)

Zhang, Meng; Liao, Caizhi; Mak, Chun Hin; You, Peng; Mak, Chee Leung; Yan, Feng

2015-02-01

Noninvasive glucose detections are convenient techniques for the diagnosis of diabetes mellitus, which require high performance glucose sensors. However, conventional electrochemical glucose sensors are not sensitive enough for these applications. Here, highly sensitive glucose sensors are successfully realized based on whole-graphene solution-gated transistors with the graphene gate electrodes modified with an enzyme glucose oxidase. The sensitivity of the devices is dramatically improved by co-modifying the graphene gates with Pt nanoparticles due to the enhanced electrocatalytic activity of the electrodes. The sensing mechanism is attributed to the reaction of H2O2 generated by the oxidation of glucose near the gate. The optimized glucose sensors show the detection limits down to 0.5 μM and good selectivity, which are sensitive enough for non-invasive glucose detections in body fluids. The devices show the transconductances two orders of magnitude higher than that of a conventional silicon field effect transistor, which is the main reason for their high sensitivity. Moreover, the devices can be conveniently fabricated with low cost. Therefore, the whole-graphene solution-gated transistors are a high-performance sensing platform for not only glucose detections but also many other types of biosensors that may find practical applications in the near future.

Programmable Schottky Junctions Based on Ferroelectric Gated MoS2 Transistors

NASA Astrophysics Data System (ADS)

Xiao, Zhiyong; Song, Jingfeng; Drcharme, Stephen; Hong, Xia

We report a programmable Schottky junction based on MoS2 field effect transistors with a SiO2 back gate and a ferroelectric copolymer poly(vinylidene-fluoride-trifluorethylene) (PVDF) top gate. We fabricated mechanically exfoliated single layer MoS2 flakes into two point devices via e-beam lithography, and deposited on the top of the devices ~20 nm PVDF thin films. The polarization of the PVDF layer is controlled locally by conducting atomic force microscopy. The devices exhibit linear ID-VD characteristics when the ferroelectric gate is uniformly polarized in one direction. We then polarized the gate into two domains with opposite polarization directions, and observed that the ID-VD characteristics of the MoS2 channel can be modulated between linear and rectified behaviors depending on the back gate voltage. The nonlinear ID-VD relation emerges when half of the channel is in the semiconductor phase while the other half is in the metallic phase, and it can be well described by the thermionic emission model with a Schottky barrier of ~0.5 eV. The Schottky junction can be erased by re-write the entire channel in the uniform polarization state. Our study facilitates the development of programmable, multifunctional nanoelectronics based on layered 2D TMDs..

Highly sensitive glucose sensors based on enzyme-modified whole-graphene solution-gated transistors

PubMed Central

Zhang, Meng; Liao, Caizhi; Mak, Chun Hin; You, Peng; Mak, Chee Leung; Yan, Feng

2015-01-01

Noninvasive glucose detections are convenient techniques for the diagnosis of diabetes mellitus, which require high performance glucose sensors. However, conventional electrochemical glucose sensors are not sensitive enough for these applications. Here, highly sensitive glucose sensors are successfully realized based on whole-graphene solution-gated transistors with the graphene gate electrodes modified with an enzyme glucose oxidase. The sensitivity of the devices is dramatically improved by co-modifying the graphene gates with Pt nanoparticles due to the enhanced electrocatalytic activity of the electrodes. The sensing mechanism is attributed to the reaction of H2O2 generated by the oxidation of glucose near the gate. The optimized glucose sensors show the detection limits down to 0.5 μM and good selectivity, which are sensitive enough for non-invasive glucose detections in body fluids. The devices show the transconductances two orders of magnitude higher than that of a conventional silicon field effect transistor, which is the main reason for their high sensitivity. Moreover, the devices can be conveniently fabricated with low cost. Therefore, the whole-graphene solution-gated transistors are a high-performance sensing platform for not only glucose detections but also many other types of biosensors that may find practical applications in the near future. PMID:25655666

Analysis of stability improvement in ZnO thin film transistor with dual-gate structure under negative bias stress

NASA Astrophysics Data System (ADS)

Yun, Ho-Jin; Kim, Young-Su; Jeong, Kwang-Seok; Kim, Yu-Mi; Yang, Seung-dong; Lee, Hi-Deok; Lee, Ga-Won

2014-01-01

In this study, we fabricated dual-gate zinc oxide thin film transistors (ZnO TFTs) without additional processes and analyzed their stability characteristics under a negative gate bias stress (NBS) by comparison with conventional bottom-gate structures. The dual-gate device shows superior electrical parameters, such as subthreshold swing (SS) and on/off current ratio. NBS of VGS = -20 V with VDS = 0 was applied, resulting in a negative threshold voltage (Vth) shift. After applying stress for 1000 s, the Vth shift is 0.60 V in a dual-gate ZnO TFT, while the Vth shift is 2.52 V in a bottom-gate ZnO TFT. The stress immunity of the dual-gate device is caused by the change in field distribution in the ZnO channel by adding another gate as the technology computer aided design (TCAD) simulation shows. Additionally, in flicker noise analysis, a lower noise level with a different mechanism is observed in the dual-gate structure. This can be explained by the top side of the ZnO film having a larger crystal and fewer grain boundaries than the bottom side, which is revealed by the enhanced SS and XRD results. Therefore, the improved stability of the dual-gate ZnO TFT is greatly related to the E-field cancellation effect and crystal quality of the ZnO film.

Carbon nanotube and graphene device modeling and simulation

NASA Astrophysics Data System (ADS)

Yoon, Young Ki

The performance of the semiconductors has been improved and the price has gone down for decades. It has been continuously scaled down in size year by year, and now it encounters the fundamental scaling limit. We, therefore, should prepare a new era beyond the conventional semiconductor technologies. One of the most promising devices is possible by carbon nanotube (CNT) or graphene nanoribbon (GNR) in terms of its excellent charge transport properties. Their fundamental material properties and device physics are totally different to those of the conventional devices. In this nano-regime, more sophisticated device modeling and simulation are really needed to elucidate nano-device operation and to save our resources from errors. The numerical simulation works in this dissertation will provide novel view points on the emerging devices. In this dissertation, CNT and GNR devices are numerically studied. The first part of this work is on CNT devices, and a common structure of CNT device has CNT channel, metal source and drain contacts, and gate electrode. We investigate the strain, geometry, and scattering effects on the device performance of CNT field-effect transistors (FETs). It is shown that even a small amount of strain can result in a large effect on the performance of CNTFETs due to the variation of the bandgap and band-structure-limited velocity. A type of strain which produces a larger bandgap results in increased Schottky barrier (SB) height and decreased band-structure-limited velocity, and hence a smaller minimum leakage current, smaller on current, larger maximum achievable Ion/Ioff, and larger intrinsic delay. We also examine geometry effect of partial gate CNTFETs. In the growth process of vertical CNT, underlap between the gate and the bottom electrode is advantageous for transistor operation because it suppresses ambipolar conduction of SBFETs. Both n-type and p-type transistor operations with balanced performance metrics can be achieved on a single partial gate FET by using proper bias schemes. The effect of phonon scattering on the intrinsic delay and cut-off frequency of Schottky barrier CNTFETs is also examined. Carriers are mostly scattered by optical and zone boundary phonons beyond the beginning of the channel. The scattering has a small direct effect on the DC on current of the CNTFET, but it results in significant decrease of intrinsic cut-off frequency and increase of intrinsic delay. Semiconducting CNT is useful for the channel in CNTFETs, whereas metallic CNT can be used as an electrode. If a porous CNT film is used as a source electrode, vertical thin-film transistors (TFTs) can be constructed. Vertical organic FET (OFET) shows clear transistor switching behavior allowing orders of magnitude modulation of the source-drain current even in the presence of electrostatic screening by the source electrode. The channel length should be carefully engineered due to the trade-off between device characteristics in the subthreshold and above-threshold regions. The second subject is device simulations of GNRFETs. Even though GNR is also graphene-based quasi-1D nanostructure like CNT, the differences in shape, boundary condition, and existence of edges and dangling bonds make it operate in a different way. Atomistic 3D simulation study of the performance of GNR SBFETs is presented. The impacts of non-idealities on device performance have been investigated. The edges of GNR, which do not exist in CNT, can be advantages or disadvantages. If an appropriate control by different edge atoms is possible, it would be definitely positive. Totally new electronic band structure is obtained by different edge-termination atoms. In addition, only a fraction of impurity atom can also much affect on the material properties of GNR. In order to perform device simulations of non-uniform GNR devices, multiscale simulation scheme can be used in non-equilibrium Green's function (NEGF) formalism and density-functional method.

Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers

NASA Astrophysics Data System (ADS)

Xu, Huifang; Dai, Yuehua

2017-02-01

A two-dimensional analytical model of double-gate (DG) tunneling field-effect transistors (TFETs) with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile, the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate, and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results. Project supported by the National Natural Science Foundation of China (No. 61376106), the University Natural Science Research Key Project of Anhui Province (No. KJ2016A169), and the Introduced Talents Project of Anhui Science and Technology University.

Scan direction induced charging dynamics and the application for detection of gate to S/D shorts in logic devices

NASA Astrophysics Data System (ADS)

Lei, Ming; Tian, Qing; Wu, Kevin; Zhao, Yan

2016-03-01

Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

Dependence of the 0.7 anomaly on the curvature of the potential barrier in quantum wires

NASA Astrophysics Data System (ADS)

Smith, L. W.; Al-Taie, H.; Lesage, A. A. J.; Sfigakis, F.; See, P.; Griffiths, J. P.; Beere, H. E.; Jones, G. A. C.; Ritchie, D. A.; Hamilton, A. R.; Kelly, M. J.; Smith, C. G.

2015-06-01

Ninety-eight one-dimensional channels defined using split gates fabricated on a GaAs/AlGaAs heterostructure are measured during one cooldown at 1.4 K. The devices are arranged in an array on a single chip and are individually addressed using a multiplexing technique. The anomalous conductance feature known as the "0.7 structure" is studied using statistical techniques. The ensemble of data shows that the 0.7 anomaly becomes more pronounced and occurs at lower values as the curvature of the potential barrier in the transport direction decreases. This corresponds to an increase in the effective length of the device. The 0.7 anomaly is not strongly influenced by other properties of the conductance related to density. The curvature of the potential barrier appears to be the primary factor governing the shape of the 0.7 structure at a given T and B .

Quantum transport properties of carbon nanotube field-effect transistors with electron-phonon coupling

NASA Astrophysics Data System (ADS)

Ishii, Hiroyuki; Kobayashi, Nobuhiko; Hirose, Kenji

2007-11-01

We investigated the electron-phonon coupling effects on the electronic transport properties of metallic (5,5)- and semiconducting (10,0)-carbon nanotube devices. We calculated the conductance and mobility of the carbon nanotubes with micron-order lengths at room temperature, using the time-dependent wave-packet approach based on the Kubo-Greenwood formula within a tight-binding approximation. We investigated the scattering effects of both longitudinal acoustic and optical phonon modes on the transport properties. The electron-optical phonon coupling decreases the conductance around the Fermi energy for the metallic carbon nanotubes, while the conductance of semiconductor nanotubes is decreased around the band edges by the acoustic phonons. Furthermore, we studied the Schottky-barrier effects on the mobility of the semiconducting carbon nanotube field-effect transistors for various gate voltages. We clarified how the electron mobilities of the devices are changed by the acoustic phonon.

Kink effect in ultrathin FDSOI MOSFETs

NASA Astrophysics Data System (ADS)

Park, H. J.; Bawedin, M.; Choi, H. G.; Cristoloveanu, S.

2018-05-01

Systematic experiments demonstrate the presence of the kink effect even in FDSOI MOSFETs. The back-gate bias controls the kink effect via the formation of a back accumulation channel. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (<10 nm) and/or very short transistors (L < 50 nm), the kink is totally absent as a consequence of super-coupling effect. For the first time, thanks to the availability of body contacts, the body potential is probed to evidence the impact of majority carrier accumulation and drain pulse duration on the kink effect onset. He is currently working toward the Ph.D. degree in FDSOI device characterization and simulation at a laboratory of IMEP-lahc, Université Grenoble Alpes, Minatec, Grenoble, France. His research interests include residual floating body effects, electrical characterization, and device simulation for ultra FDSOI MOSFETs.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET.

PubMed

Tan, Michael Loong Peng; Lentaris, Georgios; Amaratunga Aj, Gehan

2012-08-19

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.

Reliability study of refractory gate gallium arsenide MESFETS

NASA Technical Reports Server (NTRS)

Yin, J. C. W.; Portnoy, W. M.

1981-01-01

Refractory gate MESFET's were fabricated as an alternative to aluminum gate devices, which have been found to be unreliable as RF power amplifiers. In order to determine the reliability of the new structures, statistics of failure and information about mechanisms of failure in refractory gate MESFET's are given. Test transistors were stressed under conditions of high temperature and forward gate current to enhance failure. Results of work at 150 C and 275 C are reported.

Reliability study of refractory gate gallium arsenide MESFETS

NASA Astrophysics Data System (ADS)

Yin, J. C. W.; Portnoy, W. M.

Refractory gate MESFET's were fabricated as an alternative to aluminum gate devices, which have been found to be unreliable as RF power amplifiers. In order to determine the reliability of the new structures, statistics of failure and information about mechanisms of failure in refractory gate MESFET's are given. Test transistors were stressed under conditions of high temperature and forward gate current to enhance failure. Results of work at 150 C and 275 C are reported.

Variations of Contact Resistance in Dual-Gated Monolayer Molybdenum Disulfide Transistors Depending on Gate Bias Selection

NASA Astrophysics Data System (ADS)

Tran, P. X.

2017-06-01

Monolayer molybdenum disulfide (MoS2) is considered an alternative two-dimensional material for high performance ultra-thin field-effect transistors. MoS2 is a triple atomic layer with a direct 1.8 eV bandgap. Bulk MoS2 has an additional indirect bandgap of 1.2 eV, which leads to high current on/off ratio around 108. Flakes of MoS2 can be obtained by mechanical exfoliation or grown by chemical vapor deposition. Intrinsic cut-off frequency of multilayer MoS2 transistor has reached 42 GHz. Chemical doping of MoS2 is challenging and results in reduction of contact resistance. This paper focuses on modeling of dual-gated monolayer MoS2 transistors with effective mobility of carriers varying from 0.6 cm2/V s to 750 cm2/V s. In agreement with experimental data, the model demonstrates that in back-gate bias devices, the contact resistance decreases almost exponentially with increasing gate bias, whereas in top-gate bias devices, the contact resistance stays invariant when varying gate bias.

Thermal Simulation of a Silicon Carbide (SiC) Insulated-Gate Bipolar Transistor (IGBT) in Continuous Switching Mode

DTIC Science & Technology

operation in a DC-DC power converter switching at a frequency of up to 15 kHz. Calculations also estimated the effect of solder layers on temperature in the device....Thermal simulations were used to calculate temperatures in a silicon carbide (SiC) Insulated -Gate Bipolar Transistor (IGBT),simulating device

Front and backside processed thin film electronic devices

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2010-10-12

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Simultaneous control of thermoelectric properties in p- and n-type materials by electric double-layer gating: New design for thermoelectric device

NASA Astrophysics Data System (ADS)

Takayanagi, Ryohei; Fujii, Takenori; Asamitsu, Atsushi

2015-05-01

We report a novel design of a thermoelectric device that can control the thermoelectric properties of p- and n-type materials simultaneously by electric double-layer gating. Here, p-type Cu2O and n-type ZnO were used as the positive and negative electrodes of the electric double-layer capacitor structure. When a gate voltage was applied between the two electrodes, holes and electrons accumulated on the surfaces of Cu2O and ZnO, respectively. The thermopower was measured by applying a thermal gradient along the accumulated layer on the electrodes. We demonstrate here that the accumulated layers worked as a p-n pair of the thermoelectric device.

2. CLOSEUP OF SOUTH FACADE OF UPPER FALLS GATE HOUSE, ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

2. CLOSEUP OF SOUTH FACADE OF UPPER FALLS GATE HOUSE, SHOWING TRASH RACKS, REMOVABLE STEEL DOORS, TRASH RAKE STRUCTURE, AND DERRICK, WINCH AND CABLE GATE LIFTING DEVICE, LOOKING SOUTH/SOUTHWEST. - Washington Water Power Spokane River Upper Falls Hydroelectric Development, Gate House, Spokane River, approximately 0.5 mile northeast of intersection of Spokane Falls Boulevard & Post Street, Spokane, Spokane County, WA

Construction of a fuzzy and Boolean logic gates based on DNA.

PubMed

Zadegan, Reza M; Jepsen, Mette D E; Hildebrandt, Lasse L; Birkedal, Victoria; Kjems, Jørgen

2015-04-17

Logic gates are devices that can perform logical operations by transforming a set of inputs into a predictable single detectable output. The hybridization properties, structure, and function of nucleic acids can be used to make DNA-based logic gates. These devices are important modules in molecular computing and biosensing. The ideal logic gate system should provide a wide selection of logical operations, and be integrable in multiple copies into more complex structures. Here we show the successful construction of a small DNA-based logic gate complex that produces fluorescent outputs corresponding to the operation of the six Boolean logic gates AND, NAND, OR, NOR, XOR, and XNOR. The logic gate complex is shown to work also when implemented in a three-dimensional DNA origami box structure, where it controlled the position of the lid in a closed or open position. Implementation of multiple microRNA sensitive DNA locks on one DNA origami box structure enabled fuzzy logical operation that allows biosensing of complex molecular signals. Integrating logic gates with DNA origami systems opens a vast avenue to applications in the fields of nanomedicine for diagnostics and therapeutics. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

An “ohmic-first” self-terminating gate-recess technique for normally-off Al2O3/GaN MOSFET

NASA Astrophysics Data System (ADS)

Wang, Hongyue; Wang, Jinyan; Li, Mengjun; He, Yandong; Wang, Maojun; Yu, Min; Wu, Wengang; Zhou, Yang; Dai, Gang

2018-04-01

In this article, an ohmic-first AlGaN/GaN self-terminating gate-recess etching technique was demonstrated where ohmic contact formation is ahead of gate-recess-etching/gate-dielectric-deposition (GRE/GDD) process. The ohmic contact exhibits few degradations after the self-terminating gate-recess process. Besides, when comparing with that using the conventional fabrication process, the fabricated device using the ohmic-first fabrication process shows a better gate dielectric quality in terms of more than 3 orders lower forward gate leakage current, more than twice higher reverse breakdown voltage as well as better stability. Based on this proposed technique, the normally-off Al2O3/GaN MOSFET exhibits a threshold voltage (V th) of ˜1.8 V, a maximum drain current of ˜328 mA/mm, a forward gate leakage current of ˜10-6 A/mm and an off-state breakdown voltage of 218 V at room temperature. Meanwhile, high temperature characteristics of the device was also evaluated and small variations (˜7.6%) of the threshold voltage was confirmed up to 300 °C.

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers

PubMed Central

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Abstract Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlOx), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers. PMID:28634499

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers.

PubMed

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

High-voltage lateral double-implanted MOSFETs implemented on high-purity semi-insulating 4H-SiC substrates with gate field plates

NASA Astrophysics Data System (ADS)

Seok, Ogyun; Kim, Hyoung Woo; Moon, Jeong Hyun; Lee, Hyun-Su; Bahng, Wook

2018-06-01

Lateral double-implanted MOSFETs (LDIMOSFETs) fabricated on on-axis high-purity semi-insulating (HPSI) 4H-SiC substrates with gate field plates have been demonstrated for the enhancement of reverse blocking capability. The effects of gate field plate on LDIMOSFET were analyzed by simulation and experimental methods. The electric field concentration at the gate edge was successfully suppressed by a gate field plate. A high breakdown voltage of 934 V and a figure of merit of 14.6 MW/cm2 were achieved at L FP of 2 µm and L drift of 15 µm, while those of the conventional device without a gate field plate were 744 V and 13.3 MW/cm2, respectively. Also, the fabricated device shows stable blocking characteristics at a high temperature of 250 °C. The drain leakage was increased by only 22% at 250 °C compared with that at room temperature.

Experimental evidence of mobility enhancement in short-channel ultra-thin body double-gate MOSFETs by magnetoresistance technique

NASA Astrophysics Data System (ADS)

Chaisantikulwat, W.; Mouis, M.; Ghibaudo, G.; Cristoloveanu, S.; Widiez, J.; Vinet, M.; Deleonibus, S.

2007-11-01

Double-gate transistor with ultra-thin body (UTB) has proved to offer advantages over bulk device for high-speed, low-power applications. There is thus a strong need to obtain an accurate understanding of carrier transport and mobility in such device. In this work, we report for the first time an experimental evidence of mobility enhancement in UTB double-gate (DG) MOSFETs using magnetoresistance mobility extraction technique. Mobility in planar DG transistor operating in single- and double-gate mode is compared. The influence of different scattering mechanisms in the channel is also investigated by obtaining mobility values at low temperatures. The results show a clear mobility improvement in double-gate mode compared to single-gate mode mobility at the same inversion charge density. This is explained by the role of volume inversion in ultra-thin body transistor operating in DG mode. Volume inversion is found to be especially beneficial in terms of mobility gain at low-inversion densities.

N-Channel field-effect transistors with floating gates for extracellular recordings.

PubMed

Meyburg, Sven; Goryll, Michael; Moers, Jürgen; Ingebrandt, Sven; Böcker-Meffert, Simone; Lüth, Hans; Offenhäusser, Andreas

2006-01-15

A field-effect transistor (FET) for recording extracellular signals from electrogenic cells is presented. The so-called floating gate architecture combines a complementary metal oxide semiconductor (CMOS)-type n-channel transistor with an independent sensing area. This concept allows the transistor and sensing area to be optimised separately. The devices are robust and can be reused several times. The noise level of the devices was smaller than of comparable non-metallised gate FETs. In addition to the usual drift of FET devices, we observed a long-term drift that has to be controlled for future long-term measurements. The device performance for extracellular signal recording was tested using embryonic rat cardiac myocytes cultured on fibronectin-coated chips. The extracellular cell signals were recorded before and after the addition of the cardioactive isoproterenol. The signal shapes of the measured action potentials were comparable to the non-metallised gate FETs previously used in similar experiments. The fabrication of the devices involved the process steps of standard CMOS that were necessary to create n-channel transistors. The implementation of a complete CMOS process would facilitate the integration of the logical circuits necessary for signal pre-processing on a chip, which is a prerequisite for a greater number of sensor spots in future layouts.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, S.; Dhar, A., E-mail: adhar@phy.iitkgp.ernet.in

Highlights: • Alternative to chemically crosslinking of PMMA to achieve low leakage in provided. • Effect of LiF in reducing gate leakage through the OFET device is studied. • Effect of gate leakage on transistor performance has been investigated. • Low voltage operable and low temperature processed n-channel OFETs were fabricated. - Abstract: We report low temperature processed, low voltage operable n-channel organic field effect transistors (OFETs) using N,N′-Dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C{sub 8}) organic semiconductor and poly(methylmethacrylate) (PMMA)/lithium fluoride (LiF) bilayer gate dielectric. We have studied the role of LiF buffer dielectric in effectively reducing the gate leakage through the device andmore » thus obtaining superior performance in contrast to the single layer PMMA dielectric devices. The bilayer OFET devices had a low threshold voltage (V{sub t}) of the order of 5.3 V. The typical values of saturation electron mobility (μ{sub s}), on/off ratio and inverse sub-threshold slope (S) for the range of devices made were estimated to be 2.8 × 10{sup −3} cm{sup 2}/V s, 385, and 3.8 V/decade respectively. Our work thus provides a potential substitution for much complicated process of chemically crosslinking PMMA to achieve low leakage, high capacitance, and thus low operating voltage OFETs.« less

Highly Stable, Dual-Gated MoS2 Transistors Encapsulated by Hexagonal Boron Nitride with Gate-Controllable Contact, Resistance, and Threshold Voltage.

PubMed

Lee, Gwan-Hyoung; Cui, Xu; Kim, Young Duck; Arefe, Ghidewon; Zhang, Xian; Lee, Chul-Ho; Ye, Fan; Watanabe, Kenji; Taniguchi, Takashi; Kim, Philip; Hone, James

2015-07-28

Emerging two-dimensional (2D) semiconductors such as molybdenum disulfide (MoS2) have been intensively studied because of their novel properties for advanced electronics and optoelectronics. However, 2D materials are by nature sensitive to environmental influences, such as temperature, humidity, adsorbates, and trapped charges in neighboring dielectrics. Therefore, it is crucial to develop device architectures that provide both high performance and long-term stability. Here we report high performance of dual-gated van der Waals (vdW) heterostructure devices in which MoS2 layers are fully encapsulated by hexagonal boron nitride (hBN) and contacts are formed using graphene. The hBN-encapsulation provides excellent protection from environmental factors, resulting in highly stable device performance, even at elevated temperatures. Our measurements also reveal high-quality electrical contacts and reduced hysteresis, leading to high two-terminal carrier mobility (33-151 cm(2) V(-1) s(-1)) and low subthreshold swing (80 mV/dec) at room temperature. Furthermore, adjustment of graphene Fermi level and use of dual gates enable us to separately control contact resistance and threshold voltage. This novel vdW heterostructure device opens up a new way toward fabrication of stable, high-performance devices based on 2D materials.

Solution processed flexible organic thin film back-gated transistors based on polyimide dielectric films

NASA Astrophysics Data System (ADS)

Park, Janghoon; Min, Yoonki; Lee, Dongjin

2018-04-01

An organic thin film back-gated transistor (OBGT) was fabricated and characterized. The gate electrode was printed on the back side of substrate, and the dielectric layer was omitted by substituting the dielectric layer with the polyimide (PI) film substrate. Roll-to-roll (R2R) gravure printing, doctor blading, and drop casting methods were used to fabricate the OBGT. The printed OBGT device shows better performance compared with an OTFT device based on dielectric layer of BaTiO3. Additionally, a calendering process enhanced the performance by a factor of 3 to 7 (mobility: 0.016 cm2/V.s, on/off ratio: 9.17×103). A bending test was conducted to confirm the flexibility and durability of the OBGT device. The results show the fabricated device endures 20000-cyclic motions. The realized OBGT device was successfully fabricated and working, which is meaningful for production engineering from the viewpoint of process development.

Sulfuric acid and hydrogen peroxide surface passivation effects on AlGaN/GaN high electron mobility transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zaidi, Z. H., E-mail: zaffar.zaidi@sheffield.ac.uk; Lee, K. B.; Qian, H.

2014-12-28

In this work, we have compared SiN{sub x} passivation, hydrogen peroxide, and sulfuric acid treatment on AlGaN/GaN HEMTs surface after full device fabrication on Si substrate. Both the chemical treatments resulted in the suppression of device pinch-off gate leakage current below 1 μA/mm, which is much lower than that for SiN{sub x} passivation. The greatest suppression over the range of devices is observed with the sulfuric acid treatment. The device on/off current ratio is improved (from 10{sup 4}–10{sup 5} to 10{sup 7}) and a reduction in the device sub-threshold (S.S.) slope (from ∼215 to 90 mV/decade) is achieved. The sulfuric acid ismore » believed to work by oxidizing the surface which has a strong passivating effect on the gate leakage current. The interface trap charge density (D{sub it}) is reduced (from 4.86 to 0.90 × 10{sup 12 }cm{sup −2} eV{sup −1}), calculated from the change in the device S.S. The gate surface leakage current mechanism is explained by combined Mott hopping conduction and Poole Frenkel models for both untreated and sulfuric acid treated devices. Combining the sulfuric acid treatment underneath the gate with the SiN{sub x} passivation after full device fabrication results in the reduction of D{sub it} and improves the surface related current collapse.« less

Polysilicon Gate Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations in Sub-100 nm MOSFET's with Ultrathin Gate Oxide

NASA Technical Reports Server (NTRS)

Asenov, Asen; Saini, Subhash

2000-01-01

In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFET's with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3-D) "atomistic" simulation technique described else-where. MOSFET's with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled-in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide-thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect or the polysilicon grain boundaries on the threshold voltage variation are also presented.

High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric

PubMed Central

Fujii, Mami N.; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

2015-01-01

The use of indium–gallium–zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic–inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic–inorganic hybrid devices. PMID:26677773

High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric.

PubMed

Fujii, Mami N; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

2015-12-18

The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices.

Temperature-gated thermal rectifier for active heat flow control.

PubMed

Zhu, Jia; Hippalgaonkar, Kedar; Shen, Sheng; Wang, Kevin; Abate, Yohannes; Lee, Sangwook; Wu, Junqiao; Yin, Xiaobo; Majumdar, Arun; Zhang, Xiang

2014-08-13

Active heat flow control is essential for broad applications of heating, cooling, and energy conversion. Like electronic devices developed for the control of electric power, it is very desirable to develop advanced all-thermal solid-state devices that actively control heat flow without consuming other forms of energy. Here we demonstrate temperature-gated thermal rectification using vanadium dioxide beams in which the environmental temperature actively modulates asymmetric heat flow. In this three terminal device, there are two switchable states, which can be regulated by global heating. In the "Rectifier" state, we observe up to 28% thermal rectification. In the "Resistor" state, the thermal rectification is significantly suppressed (<1%). To the best of our knowledge, this is the first demonstration of solid-state active-thermal devices with a large rectification in the Rectifier state. This temperature-gated rectifier can have substantial implications ranging from autonomous thermal management of heating and cooling systems to efficient thermal energy conversion and storage.

Photon-triggered nanowire transistors

NASA Astrophysics Data System (ADS)

Kim, Jungkil; Lee, Hoo-Cheol; Kim, Kyoung-Ho; Hwang, Min-Soo; Park, Jin-Sung; Lee, Jung Min; So, Jae-Pil; Choi, Jae-Hyuck; Kwon, Soon-Hong; Barrelet, Carl J.; Park, Hong-Gyu

2017-10-01

Photon-triggered electronic circuits have been a long-standing goal of photonics. Recent demonstrations include either all-optical transistors in which photons control other photons or phototransistors with the gate response tuned or enhanced by photons. However, only a few studies report on devices in which electronic currents are optically switched and amplified without an electrical gate. Here we show photon-triggered nanowire (NW) transistors, photon-triggered NW logic gates and a single NW photodetection system. NWs are synthesized with long crystalline silicon (CSi) segments connected by short porous silicon (PSi) segments. In a fabricated device, the electrical contacts on both ends of the NW are connected to a single PSi segment in the middle. Exposing the PSi segment to light triggers a current in the NW with a high on/off ratio of >8 × 106. A device that contains two PSi segments along the NW can be triggered using two independent optical input signals. Using localized pump lasers, we demonstrate photon-triggered logic gates including AND, OR and NAND gates. A photon-triggered NW transistor of diameter 25 nm with a single 100 nm PSi segment requires less than 300 pW of power. Furthermore, we take advantage of the high photosensitivity and fabricate a submicrometre-resolution photodetection system. Photon-triggered transistors offer a new venue towards multifunctional device applications such as programmable logic elements and ultrasensitive photodetectors.

Photon-triggered nanowire transistors.

PubMed

Kim, Jungkil; Lee, Hoo-Cheol; Kim, Kyoung-Ho; Hwang, Min-Soo; Park, Jin-Sung; Lee, Jung Min; So, Jae-Pil; Choi, Jae-Hyuck; Kwon, Soon-Hong; Barrelet, Carl J; Park, Hong-Gyu

2017-10-01

Photon-triggered electronic circuits have been a long-standing goal of photonics. Recent demonstrations include either all-optical transistors in which photons control other photons or phototransistors with the gate response tuned or enhanced by photons. However, only a few studies report on devices in which electronic currents are optically switched and amplified without an electrical gate. Here we show photon-triggered nanowire (NW) transistors, photon-triggered NW logic gates and a single NW photodetection system. NWs are synthesized with long crystalline silicon (CSi) segments connected by short porous silicon (PSi) segments. In a fabricated device, the electrical contacts on both ends of the NW are connected to a single PSi segment in the middle. Exposing the PSi segment to light triggers a current in the NW with a high on/off ratio of >8 × 10 6 . A device that contains two PSi segments along the NW can be triggered using two independent optical input signals. Using localized pump lasers, we demonstrate photon-triggered logic gates including AND, OR and NAND gates. A photon-triggered NW transistor of diameter 25 nm with a single 100 nm PSi segment requires less than 300 pW of power. Furthermore, we take advantage of the high photosensitivity and fabricate a submicrometre-resolution photodetection system. Photon-triggered transistors offer a new venue towards multifunctional device applications such as programmable logic elements and ultrasensitive photodetectors.

Nano Peltier cooling device from geometric effects using a single graphene nanoribbon

NASA Astrophysics Data System (ADS)

Li, Wan-Ju; Yao, Dao-Xin; Carlson, Erica

2012-02-01

Based on the phenomenon of curvature-induced doping in graphene we propose a class of Peltier cooling devices, produced by geometrical effects, without gating. We show how a graphene nanoribbon laid on an array of curved nano cylinders can be used to create a targeted cooling device. Using theoretical calculations and experimental inputs, we predict that the cooling power of such a device can approach 1kW/cm^2, on par with the best known techniques using standard lithography methods. The structure proposed here helps pave the way toward designing graphene electronics which use geometry rather than gating to control devices.

Analysis and optimization of RC delay in vertical nanoplate FET

NASA Astrophysics Data System (ADS)

Woo, Changbeom; Ko, Kyul; Kim, Jongsu; Kim, Minsoo; Kang, Myounggon; Shin, Hyungcheol

2017-10-01

In this paper, we have analyzed short channel effects (SCEs) and RC delay with Vertical nanoplate FET (VNFET) using 3-D Technology computer-aided design (TCAD) simulation. The device is based on International Technology Road-map for Semiconductor (ITRS) 2013 recommendations, and it has initially gate length (LG) of 12.2 nm, channel thickness (Tch) of 4 nm, and spacer length (LSD) of 6 nm. To obtain improved performance by reducing RC delay, each dimension is adjusted (LG = 12.2 nm, Tch = 6 nm, LSD = 11.9 nm). It has each characteristic in this dimension (Ion/Ioff = 1.64 × 105, Subthreshold swing (S.S.) = 73 mV/dec, Drain-induced barrier lowering (DIBL) = 60 mV/V, and RC delay = 0.214 ps). Furthermore, with long shallow trench isolation (STI) length and thick insulator thickness (Ti), we can reduce RC delay from 0.214 ps to 0.163 ps. It is about a 23.8% reduction. Without decreasing drain current, there is a reduction of RC delay as reducing outer fringing capacitance (Cof). Finally, when source/drain spacer length is set to be different, we have verified RC delay to be optimum.

Evaluation of the irising effect of a slow-gating intensified charge-coupled device on laser-induced incandescence measurements of soot

NASA Astrophysics Data System (ADS)

Shaddix, Christopher R.; Williams, Timothy C.

2009-03-01

Intensified charge-coupled devices (ICCDs) are used extensively in many scientific and engineering environments to image weak or temporally short optical events. To optimize the quantum efficiency of light collection, many of these devices are chosen to have characteristic intensifier gate times that are relatively slow, on the order of tens of nanoseconds. For many measurements associated with nanosecond laser sources, such as scattering-based diagnostics and most laser-induced fluorescence applications, the signals rise and decay sufficiently fast during and after the laser pulse that the intensifier gate may be set to close after the cessation of the signal and still effectively reject interferences associated with longer time scales. However, the relatively long time scale and complex temporal response of laser-induced incandescence (LII) of nanometer-sized particles (such as soot) offer a difficult challenge to the use of slow-gating ICCDs for quantitative measurements. In this paper, ultraviolet Rayleigh scattering imaging is used to quantify the irising effect of a slow-gating scientific ICCD camera, and an analysis is conducted of LII image data collected with this camera as a function of intensifier gate width. The results demonstrate that relatively prompt LII detection, generally desirable to minimize the influences of particle size and local gas pressure and temperature on measurements of the soot volume fraction, is strongly influenced by the irising effect of slow-gating ICCDs.

Origin of threshold voltage fluctuation caused by ion implantation to source and drain extensions of silicon-on-insulator triple-gate fin-type field-effect transistors using three-dimensional process and device simulations

NASA Astrophysics Data System (ADS)

Tsutsumi, Toshiyuki

2018-06-01

The threshold voltage (V th) fluctuation induced by ion implantation (I/I) in the source and drain extensions (SDEs) of a silicon-on-insulator (SOI) triple-gate (Tri-Gate) fin-type field-effect transistor (FinFET) was analyzed by both three-dimensional (3D) process and device simulations collaboratively. The origin of the V th fluctuation induced by the SDE I/I is basically a variation of a bottleneck barrier height (BBH) due to implanted arsenic (As+) ions. In particular, a very low and broad V th distribution in the saturation region is due to percolative conduction in addition to the BBH variation. Moreover, it is surprisingly found that the V th fluctuation is mostly characterized by the BBH of only a top surface center line of a Si fin of the device. Our collaborative approach by 3D process and device simulations is dispensable for the accurate investigation of variability-tolerant devices. The obtained results are beneficial for the research and development of such future devices.

Effects of consecutive irradiation and bias temperature stress in p-channel power vertical double-diffused metal oxide semiconductor transistors

NASA Astrophysics Data System (ADS)

Davidović, Vojkan; Danković, Danijel; Ilić, Aleksandar; Manić, Ivica; Golubović, Snežana; Djorić-Veljković, Snežana; Prijić, Zoran; Prijić, Aneta; Stojadinović, Ninoslav

2018-04-01

The mechanisms responsible for the effects of consecutive irradiation and negative bias temperature (NBT) stress in p-channel power vertical double-diffused MOS (VDMOS) transistors are presented in this paper. The investigation was performed in order to clarify the mechanisms responsible for the effects of specific kind of stress in devices previously subjected to the other kind of stress. In addition, it may help in assessing the behaviour of devices subjected to simultaneous irradiation and NBT stressing. It is shown that irradiation of previously NBT stressed devices leads to additional build-up of oxide trapped charge and interface traps, while NBT stress effects in previously irradiated devices depend on gate bias applied during irradiation and on the total dose received. In the cases of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress leads to slight further device degradation. On the other hand, in the cases of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress may have a positive role, as it actually anneals a part of radiation-induced degradation.

Rectification of graphene self-switching diodes: First-principles study

NASA Astrophysics Data System (ADS)

Ghaziasadi, Hassan; Jamasb, Shahriar; Nayebi, Payman; Fouladian, Majid

2018-05-01

The first principles calculations based on self-consistent charge density functional tight-binding have performed to investigate the electrical properties and rectification behavior of the graphene self-switching diodes (GSSD). The devices contained two structures called CG-GSSD and DG-GSSD which have metallic or semiconductor gates depending on their side gates have a single or double hydrogen edge functionalized. We have relaxed the devices and calculated I-V curves, transmission spectrums and maximum rectification ratios. We found that the DG-MSM devices are more favorable and more stable. Also, the DG-MSM devices have better maximum rectification ratios and current. Moreover, by changing the side gates widths and behaviors from semiconductor to metal, the threshold voltages under forward bias changed from +1.2 V to +0.3 V. Also, the maximum currents are obtained from 1.12 μA to 10.50 μA. Finally, the MSM and SSS type of all devices have minimum and maximum values of voltage threshold and maximum rectification ratios, but the 769-DG devices don't obey this rule.

13. DETAIL VIEW, OF TAINTER GATE PIER, SHOWING RECESSES FOR ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

13. DETAIL VIEW, OF TAINTER GATE PIER, SHOWING RECESSES FOR EMERGENCY BULKHEADS AND DOGGING DEVICES, LOOKING SOUTHEAST (DOWN FACE). UPSTREAM FACE OF TAINTER GATE IS VISIBLE IN UPPER RIGHT CORNER - Upper Mississippi River 9-Foot Channel Project, Lock & Dam 26R, Alton, Madison County, IL

Analyzing Single-Event Gate Ruptures In Power MOSFET's

NASA Technical Reports Server (NTRS)

Zoutendyk, John A.

1993-01-01

Susceptibilities of power metal-oxide/semiconductor field-effect transistors (MOSFET's) to single-event gate ruptures analyzed by exposing devices to beams of energetic bromine ions while applying appropriate bias voltages to source, gate, and drain terminals and measuring current flowing into or out of each terminal.

A radar vehicle detection system for four-quadrant gate warning systems and blocked crossing detection.

DOT National Transportation Integrated Search

2012-12-01

The Wavetronix Matrix Radar was adapted for use at four-quadrant gate railroad crossings for the purpose of influencing exit gate behavior upon the detection of vehicles, as an alternative to buried inductive loops. Two radar devices were utilized, o...

A 4H Silicon Carbide Gate Buffer for Integrated Power Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ericson, N; Frank, S; Britton, C

2014-02-01

A gate buffer fabricated in a 2-mu m 4H silicon carbide (SiC) process is presented. The circuit is composed of an input buffer stage with a push-pull output stage, and is fabricated using enhancement mode N-channel FETs in a process optimized for SiC power switching devices. Simulation and measurement results of the fabricated gate buffer are presented and compared for operation at various voltage supply levels, with a capacitive load of 2 nF. Details of the design including layout specifics, simulation results, and directions for future improvement of this buffer are presented. In addition, plans for its incorporation into anmore » isolated high-side/low-side gate-driver architecture, fully integrated with power switching devices in a SiC process, are briefly discussed. This letter represents the first reported MOSFET-based gate buffer fabricated in 4H SiC.« less

Multi-valued logic gates based on ballistic transport in quantum point contacts.

PubMed

Seo, M; Hong, C; Lee, S-Y; Choi, H K; Kim, N; Chung, Y; Umansky, V; Mahalu, D

2014-01-22

Multi-valued logic gates, which can handle quaternary numbers as inputs, are developed by exploiting the ballistic transport properties of quantum point contacts in series. The principle of a logic gate that finds the minimum of two quaternary number inputs is demonstrated. The device is scalable to allow multiple inputs, which makes it possible to find the minimum of multiple inputs in a single gate operation. Also, the principle of a half-adder for quaternary number inputs is demonstrated. First, an adder that adds up two quaternary numbers and outputs the sum of inputs is demonstrated. Second, a device to express the sum of the adder into two quaternary digits [Carry (first digit) and Sum (second digit)] is demonstrated. All the logic gates presented in this paper can in principle be extended to allow decimal number inputs with high quality QPCs.

Integrated photonic quantum gates for polarization qubits.

PubMed

Crespi, Andrea; Ramponi, Roberta; Osellame, Roberto; Sansoni, Linda; Bongioanni, Irene; Sciarrino, Fabio; Vallone, Giuseppe; Mataloni, Paolo

2011-11-29

The ability to manipulate quantum states of light by integrated devices may open new perspectives both for fundamental tests of quantum mechanics and for novel technological applications. However, the technology for handling polarization-encoded qubits, the most commonly adopted approach, is still missing in quantum optical circuits. Here we demonstrate the first integrated photonic controlled-NOT (CNOT) gate for polarization-encoded qubits. This result has been enabled by the integration, based on femtosecond laser waveguide writing, of partially polarizing beam splitters on a glass chip. We characterize the logical truth table of the quantum gate demonstrating its high fidelity to the expected one. In addition, we show the ability of this gate to transform separable states into entangled ones and vice versa. Finally, the full accessibility of our device is exploited to carry out a complete characterization of the CNOT gate through a quantum process tomography.

Gate bias stress stability under light irradiation for indium zinc oxide thin-film transistors based on anodic aluminium oxide gate dielectrics

NASA Astrophysics Data System (ADS)

Li, Min; Lan, Linfeng; Xu, Miao; Wang, Lei; Xu, Hua; Luo, Dongxiang; Zou, Jianhua; Tao, Hong; Yao, Rihui; Peng, Junbiao

2011-11-01

Thin-film transistors (TFTs) using indium zinc oxide as the active layer and anodic aluminium oxide (Al2O3) as the gate dielectric layer were fabricated. The device showed an electron mobility of as high as 10.1 cm2 V-1 s-1, an on/off current ratio of as high as ~108, and a turn-on voltage (Von) of only -0.5 V. Furthermore, this kind of TFTs was very stable under positive bias illumination stress. However, when the device experienced negative bias illumination stress, the threshold voltage shifted to the positive direction. It was found that the instability under negative bias illumination stress (NBIS) was due to the electrons from the Al gate trapping into the Al2O3 dielectric when exposed to the illuminated light. Using a stacked structure of Al2O3/SiO2 dielectrics, the device became more stable under NBIS.

Reversible control of doping in graphene-on-SiO2 by cooling under gate-voltage

NASA Astrophysics Data System (ADS)

Singh, Anil Kumar; Gupta, Anjan Kumar

2017-11-01

The electronic properties of graphene can be modulated by various doping techniques other than back-gate, but most such methods are not easily reversible and also lead to mobility reduction. Here, we report on the reversible control of doping in graphene by cooling under back-gate-voltage. The observed variation in hysteresis in our devices with the temperature and interface preparation method is attributed to the variation in the density of redox species, namely, H2O and O2, at the graphene/SiO2 interface, and their diffusion. With careful interface preparation, we have been able to make devices with negligible hysteresis at room temperature and by exploiting hysteresis at high temperatures, we get a wide, but reversible tunability of interface charge density and graphene doping, by cooling to room temperature under gate-voltage. Such reversible control of graphene doping by manipulating the interface defect charge density can help in making new data storage devices using graphene.

Fabry-Pérot Interference in Gapped Bilayer Graphene with Broken Anti-Klein Tunneling

NASA Astrophysics Data System (ADS)

Varlet, Anastasia; Liu, Ming-Hao; Krueckl, Viktor; Bischoff, Dominik; Simonet, Pauline; Watanabe, Kenji; Taniguchi, Takashi; Richter, Klaus; Ensslin, Klaus; Ihn, Thomas

2014-09-01

We report the experimental observation of Fabry-Pérot interference in the conductance of a gate-defined cavity in a dual-gated bilayer graphene device. The high quality of the bilayer graphene flake, combined with the device's electrical robustness provided by the encapsulation between two hexagonal boron nitride layers, allows us to observe ballistic phase-coherent transport through a 1-μm-long cavity. We confirm the origin of the observed interference pattern by comparing to tight-binding calculations accounting for the gate-tunable band gap. The good agreement between experiment and theory, free of tuning parameters, further verifies that a gap opens in our device. The gap is shown to destroy the perfect reflection for electrons traversing the barrier with normal incidence (anti-Klein tunneling). The broken anti-Klein tunneling implies that the Berry phase, which is found to vary with the gate voltages, is always involved in the Fabry-Pérot oscillations regardless of the magnetic field, in sharp contrast with single-layer graphene.

Quasi-Two-Dimensional h-BN/β-Ga2O3 Heterostructure Metal-Insulator-Semiconductor Field-Effect Transistor.

PubMed

Kim, Janghyuk; Mastro, Michael A; Tadjer, Marko J; Kim, Jihyun

2017-06-28

β-gallium oxide (β-Ga 2 O 3 ) and hexagonal boron nitride (h-BN) heterostructure-based quasi-two-dimensional metal-insulator-semiconductor field-effect transistors (MISFETs) were demonstrated by integrating mechanical exfoliation of (quasi)-two-dimensional materials with a dry transfer process, wherein nanothin flakes of β-Ga 2 O 3 and h-BN were utilized as the channel and gate dielectric, respectively, of the MISFET. The h-BN dielectric, which has an extraordinarily flat and clean surface, provides a minimal density of charged impurities on the interface between β-Ga 2 O 3 and h-BN, resulting in superior device performances (maximum transconductance, on/off ratio, subthreshold swing, and threshold voltage) compared to those of the conventional back-gated configurations. Also, double-gating of the fabricated device was demonstrated by biasing both top and bottom gates, achieving the modulation of the threshold voltage. This heterostructured wide-band-gap nanodevice shows a new route toward stable and high-power nanoelectronic devices.

Research and development on advanced silicon carbide thin film growth techniques and fabrication of high power and microwave frequency silicon carbide-based device structures

NASA Astrophysics Data System (ADS)

Davis, Robert F.

1990-12-01

The RF operation of MESFETs and bipolar transistors fabricated from both alpha- and beta-SiC have been modeled. The results show that SiC has considerable promise for producing microwave power MESFETs with RF output power capability greater (approx. 4 times) than can be obtained with any of the commonly used semiconductors (e.g., GaAs), this due to the high breakdown field of SiC that allows high bias voltage to be applied. These device modeling efforts have been used as a guide to design a new MESFET mask set with a aS micron gate length and reduced gate pad area. For the first time, positive gain was observed for a SiC transistor at microwave frequencies. The highest values for Ft and Fmax were 2.9 GHz and 1.9 GHz, respectively. The highest current and power gains observed at 1.0 GHz were 8.5 dB and 7 db, respectively. Avalanche characteristics for a 6H-SiC IMPATT were observed for the first time. Heteroepitaxial growth of Ti on (0001) 6H-SiC has been achieved at room and elevated temperatures. Current voltage measurements display shifts toward ohmic behavior after annealing at 400 C. Molecular beam epitaxy equipment has been designed and commissioned.

Effect of Dielectric Interface on the Performance of MoS2 Transistors.

PubMed

Li, Xuefei; Xiong, Xiong; Li, Tiaoyang; Li, Sichao; Zhang, Zhenfeng; Wu, Yanqing

2017-12-27

Because of their wide bandgap and ultrathin body properties, two-dimensional materials are currently being pursued for next-generation electronic and optoelectronic applications. Although there have been increasing numbers of studies on improving the performance of MoS 2 field-effect transistors (FETs) using various methods, the dielectric interface, which plays a decisive role in determining the mobility, interface traps, and thermal transport of MoS 2 FETs, has not been well explored and understood. In this article, we present a comprehensive experimental study on the effect of high-k dielectrics on the performance of few-layer MoS 2 FETs from 300 to 4.3 K. Results show that Al 2 O 3 /HfO 2 could boost the mobility and drain current. Meanwhile, MoS 2 transistors with Al 2 O 3 /HfO 2 demonstrate a 2× reduction in oxide trap density compared to that of the devices with the conventional SiO 2 substrate. Also, we observe a negative differential resistance effect on the device with 1 μm-channel length when using conventional SiO 2 as the gate dielectric due to self-heating, and this is effectively eliminated by using the Al 2 O 3 /HfO 2 gate dielectric. This dielectric engineering provides a highly viable route to realizing high-performance transition metal dichalcogenide-based FETs.

Time-Gating Processes in Intra-Cavity Mode-Locking Devices Like Saturable Absorbers and Kerr Cells

NASA Technical Reports Server (NTRS)

Prasad, Narasimha; Roychoudhuri, Chandrasekhar

2010-01-01

Photons are non-interacting entities. Light beams do not interfere by themselves. Light beams constituting different laser modes (frequencies) are not capable of re-arranging their energies from extended time-domain to ultra-short time-domain by themselves without the aid of light-matter interactions with suitable intra-cavity devices. In this paper we will discuss the time-gating properties of intra-cavity "mode-locking" devices that actually help generate a regular train of high energy wave packets.

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO₂ Gate Dielectrics by CF₄ Plasma Treatment.

PubMed

Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

2018-05-17

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO₂ gate insulator and CF₄ plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO₂ gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm²/V∙s (without treatment) to 54.6 cm²/V∙s (with CF₄ plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO₂ gate dielectric has also been improved by the CF₄ plasma treatment. By applying the CF₄ plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device's immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF₄ plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO₂ gate dielectric, but also enhances the device's reliability.

MOSFET-BJT hybrid mode of the gated lateral bipolar junction transistor for C-reactive protein detection.

PubMed

Yuan, Heng; Kwon, Hyurk-Choon; Yeom, Se-Hyuk; Kwon, Dae-Hyuk; Kang, Shin-Won

2011-10-15

In this study, we propose a novel biosensor based on a gated lateral bipolar junction transistor (BJT) for biomaterial detection. The gated lateral BJT can function as both a BJT and a metal-oxide-semiconductor field-effect transistor (MOSFET) with both the emitter and source, and the collector and drain, coupled. C-reactive protein (CRP), which is an important disease marker in clinical examinations, can be detected using the proposed device. In the MOSFET-BJT hybrid mode, the sensitivity, selectivity, and reproducibility of the gated lateral BJT for biosensors were evaluated in this study. According to the results, in the MOSFET-BJT hybrid mode, the gated lateral BJT shows good selectivity and reproducibility. Changes in the emitter (source) current of the device for CRP antigen detection were approximately 0.65, 0.72, and 0.80 μA/decade at base currents of -50, -30, and -10 μA, respectively. The proposed device has significant application in the detection of certain biomaterials that require a dilution process using a common biosensor, such as a MOSFET-based biosensor. Copyright © 2011 Elsevier B.V. All rights reserved.

Formation of p-n-p junction with ionic liquid gate in graphene

DOE Office of Scientific and Technical Information (OSTI.GOV)

He, Xin; Tang, Ning, E-mail: ntang@pku.edu.cn, E-mail: geweikun@mail.tsinghua.edu.cn, E-mail: bshen@pku.edu.cn; Duan, Junxi

2014-04-07

Ionic liquid gating is a technique which is much more efficient than solid gating to tune carrier density. To observe the electronic properties of such a highly doped graphene device, a top gate made of ionic liquid has been used. By sweeping both the top and back gate voltage, a p-n-p junction has been created. The mechanism of forming the p-n-p junction has been discussed. Tuning the carrier density by ionic liquid gate can be an efficient method to be used in flexible electronics.

ESD protection design for advanced CMOS

NASA Astrophysics Data System (ADS)

Huang, Jin B.; Wang, Gewen

2001-10-01

ESD effects in integrated circuits have become a major concern as today's technologies shrink to sub-micron/deep- sub-micron dimensions. The thinner gate oxide and shallower junction depth used in the advanced technologies make them very vulnerable to ESD damages. The advanced techniques like silicidation and STI (shallow trench insulation) used for improving other device performances make ESD design even more challenging. For non-silicided technologies, a certain DCGS (drain contact to gate edge spacing) is needed to achieve ESD hardness for nMOS output drivers and nMOS protection transistors. The typical DCGS values are 4-5um and 2-3um for 0.5um and 0.25um CMOS, respectively. The silicidation reduces the ballast resistance provided by DCGS with at least a factor of 10. As a result, scaling of the ESD performance with device width is lost and even zero ESD performance is reported for standard silicided devices. The device level ESD design is focused in this paper, which includes GGNMOS (gate grounded NMOS) and GCNMOS (gate coupled NMOS). The device level ESD testing including TLP (transmission line pulse) is given. Several ESD issues caused by advanced technologies have been pointed out. The possible solutions have been developed and summarized including silicide blocking, process optimization, back-end ballasting, and new protection scheme, dummy gate/n-well resistor ballsting, etc. Some of them require process cost increase, and others provide novel, compact, and simple design but involving royalty/IP (intellectual property) issue. Circuit level ESD design and layout design considerations are covered. The top-level ESD protection strategies are also given.

Tuning on-off current ratio and field-effect mobility in a MoS(2)-graphene heterostructure via Schottky barrier modulation.

PubMed

Shih, Chih-Jen; Wang, Qing Hua; Son, Youngwoo; Jin, Zhong; Blankschtein, Daniel; Strano, Michael S

2014-06-24

Field-effect transistor (FET) devices composed of a MoS2-graphene heterostructure can combine the advantages of high carrier mobility in graphene with the permanent band gap of MoS2 for digital applications. Herein, we investigate the electron transfer, photoluminescence, and gate-controlled carrier transport in such a heterostructure. We show that the junction is a Schottky barrier, whose height can be artificially controlled by gating or doping graphene. When the applied gate voltage (or the doping level) is zero, the photoexcited electron-hole pairs in monolayer MoS2 can be split by the heterojunction, significantly reducing the photoluminescence. By applying negative gate voltage (or p-doping) in graphene, the interlayer impedance formed between MoS2 and graphene exhibits an 100-fold increase. For the first time, we show that the gate-controlled interlayer Schottky impedance can be utilized to modulate carrier transport in graphene, significantly depleting the hole transport, but preserving the electron transport. Accordingly, we demonstrate a new type of FET device, which enables a controllable transition from NMOS digital to bipolar characteristics. In the NMOS digital regime, we report a very high room temperature on/off current ratio (ION/IOFF ∼ 36) in comparison to graphene-based FET devices without sacrificing the field-effect electron mobilities in graphene. By engineering the source/drain contact area, we further estimate that a higher value of ION/IOFF up to 100 can be obtained in the device architecture considered. The device architecture presented here may enable semiconducting behavior in graphene for digital and analogue electronics.

Influence of hydropower dams on the composition of the suspended and riverbank sediments in the Danube.

PubMed

Klaver, Gerard; van Os, Bertil; Negrel, Philippe; Petelet-Giraud, Emmanuelle

2007-08-01

Large hydropower dams have major impacts on flow regime, sediment transport and the characteristics of water and sediment in downstream rivers. The Gabcikovo and Iron Gate dams divide the studied Danube transect (rkm 1895-795) into three parts. In the Gabcikovo Reservoir (length of 40km) only a part of the incoming suspended sediments were deposited. Contrary to this, in the much larger Iron Gate backwater zone and reservoir (length of 310km) all riverine suspended sediments were deposited within the reservoir. Subsequently, suspended sediments were transported by tributaries into the Iron Gate backwater zone. Here they were modified by fractional sedimentation before they transgressed downstream via the dams. Compared with undammed Danube sections, Iron Gate reservoir sediment and suspended matter showed higher clay contents and different K/Ga and Metal/Ga ratios. These findings emphasize the importance of reservoir-river sediment-fractionation.

Top-Contact Self-Aligned Printing for High-Performance Carbon Nanotube Thin-Film Transistors with Sub-Micron Channel Length.

PubMed

Cao, Xuan; Wu, Fanqi; Lau, Christian; Liu, Yihang; Liu, Qingzhou; Zhou, Chongwu

2017-02-28

Semiconducting single-wall carbon nanotubes are ideal semiconductors for printed thin-film transistors due to their excellent electrical performance and intrinsic printability with solution-based deposition. However, limited by resolution and registration accuracy of current printing techniques, previously reported fully printed nanotube transistors had rather long channel lengths (>20 μm) and consequently low current-drive capabilities (<0.2 μA/μm). Here we report fully inkjet printed nanotube transistors with dramatically enhanced on-state current density of ∼4.5 μA/μm by downscaling the devices to a sub-micron channel length with top-contact self-aligned printing and employing high-capacitance ion gel as the gate dielectric. Also, the printed transistors exhibited a high on/off ratio of ∼10 5 , low-voltage operation, and good mobility of ∼15.03 cm 2 V -1 s -1 . These advantageous features of our printed transistors are very promising for future high-definition printed displays and sensing systems, low-power consumer electronics, and large-scale integration of printed electronics.

Potentiometric Detection of Pathogens

DTIC Science & Technology

2012-01-01

nanosize organic electrode (conducting polymer top-layer) surface. This approach has then been changed to the gate modification in ion sensitive field...electrode (conducting polymer top-layer) surface. This approach has then been changed to the gate modification in ion sensitive field effect transistors, in...the conducting polymer top-layer, which makes the devices very functional and competitive. Secondly, the device development is discussed and finally

Progress towards a microwave-based high-fidelity Toffoli gate with superconducting qubits

NASA Astrophysics Data System (ADS)

Rigetti, Chad; Chow, Jerry; Corcoles, Antonio; Rozen, Jim; Keefe, George; Rothwell, Mary Beth; Rohrs, Jack; Borstelmann, Mark; Divincenzo, David; Ketchen, Mark; Steffen, Matthias

2011-03-01

We describe recent progress at IBM towards a microwave-based implementation of the Toffoli gate using three capacitively shunted flux qubits dispersively coupled to a resonator. We discuss the device architecture and the microwave protocol, along with expected limits to gate fidelity and scaling.

A SONOS device with a separated charge trapping layer for improvement of charge injection

NASA Astrophysics Data System (ADS)

Ahn, Jae-Hyuk; Moon, Dong-Il; Ko, Seung-Won; Kim, Chang-Hoon; Kim, Jee-Yeon; Kim, Moon-Seok; Seol, Myeong-Lok; Moon, Joon-Bae; Choi, Ji-Min; Oh, Jae-Sub; Choi, Sung-Jin; Choi, Yang-Kyu

2017-03-01

A charge trapping layer that is separated from the primary gate dielectric is implemented on a FinFET SONOS structure. By virtue of the reduced effective oxide thickness of the primary gate dielectric, a strong gate-to-channel coupling is obtained and thus short-channel effects in the proposed device are effectively suppressed. Moreover, a high program/erase speed and a large shift in the threshold voltage are achieved due to the improved charge injection by the reduced effective oxide thickness. The proposed structure has potential for use in high speed flash memory.

Gate bias stress in pentacene field-effect-transistors: Charge trapping in the dielectric or semiconductor

NASA Astrophysics Data System (ADS)

Häusermann, R.; Batlogg, B.

2011-08-01

Gate bias stress instability in organic field-effect transistors (OFETs) is a major conceptual and device issue. This effect manifests itself by an undesirable shift of the transfer characteristics and is associated with long term charge trapping. We study the role of the dielectric and the semiconductor separately by producing OFETs with the same semiconductor (pentacene) combined with different dielectrics (SiO2 and Cytop). We show that it is possible to fabricate devices which are immune to gate bias stress. For other material combinations, charge trapping occurs in the semiconductor alone or in the dielectric.

Correlation between border traps and exposed surface properties in gate recessed normally-off Al2O3/GaN MOSFET

NASA Astrophysics Data System (ADS)

Yin, Ruiyuan; Li, Yue; Sun, Yu; Wen, Cheng P.; Hao, Yilong; Wang, Maojun

2018-06-01

We report the effect of the gate recess process and the surface of as-etched GaN on the gate oxide quality and first reveal the correlation between border traps and exposed surface properties in normally-off Al2O3/GaN MOSFET. The inductively coupled plasma (ICP) dry etching gate recess with large damage presents a rough and active surface that is prone to form detrimental GaxO validated by atomic force microscopy and X-ray photoelectron spectroscopy. Lower drain current noise spectral density of the 1/f form and less dispersive ac transconductance are observed in GaN MOSFETs fabricated with oxygen assisted wet etching compared with devices based on ICP dry etching. One decade lower density of border traps is extracted in devices with wet etching according to the carrier number fluctuation model, which is consistent with the result from the ac transconductance method. Both methods show that the density of border traps is skewed towards the interface, indicating that GaxO is of higher trap density than the bulk gate oxide. GaxO located close to the interface is the major location of border traps. The damage-free oxidation assisted wet etching gate recess technique presents a relatively smooth and stable surface, resulting in lower border trap density, which would lead to better MOS channel quality and improved device reliability.

Noise-margin limitations on gallium-arsenide VLSI

NASA Technical Reports Server (NTRS)

Long, Stephen I.; Sundaram, Mani

1988-01-01

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

Graphene/Pentacene Barristor with Ion-Gel Gate Dielectric: Flexible Ambipolar Transistor with High Mobility and On/Off Ratio.

PubMed

Oh, Gwangtaek; Kim, Jin-Soo; Jeon, Ji Hoon; Won, EunA; Son, Jong Wan; Lee, Duk Hyun; Kim, Cheol Kyeom; Jang, Jingon; Lee, Takhee; Park, Bae Ho

2015-07-28

High-quality channel layer is required for next-generation flexible electronic devices. Graphene is a good candidate due to its high carrier mobility and unique ambipolar transport characteristics but typically shows a low on/off ratio caused by gapless band structure. Popularly investigated organic semiconductors, such as pentacene, suffer from poor carrier mobility. Here, we propose a graphene/pentacene channel layer with high-k ion-gel gate dielectric. The graphene/pentacene device shows both high on/off ratio and carrier mobility as well as excellent mechanical flexibility. Most importantly, it reveals ambipolar behaviors and related negative differential resistance, which are controlled by external bias. Therefore, our graphene/pentacene barristor with ion-gel gate dielectric can offer various flexible device applications with high performances.

A computational study of a novel graphene nanoribbon field effect transistor

NASA Astrophysics Data System (ADS)

Ghoreishi, Seyed Saleh; Yousefi, Reza

2017-04-01

In this paper, using gate structure engineering and modification of channel dopant profile, we propose a new double gate graphene nanoribbon field effect transistor (DG-GNRFET) mainly to suppress the band-to-band tunneling (BTBT) of carriers. In the new device, the intrinsic part of the channel is replaced by an intrinsic-lightly doped-intrinsic (I -N--I) configuration in a way that only the intrinsic parts are covered by the gate contact. Transport characteristics of the device are investigated theoretically using the nonequilibrium Green’s function (NEGF) formalism. Numerical simulations show that off-current, ambipolar behavior, on/off-current ratio and the switching characteristics such as intrinsic delay and power-delay product are improved. In addition, the new device demonstrates better sub-threshold swing and less drain-induced barrier lowering (DIBL).

Novel all-optical logic gate using an add/drop filter and intensity switch.

PubMed

Threepak, T; Mitatha, S; Yupapin, P P

2011-12-01

A novel design of all-optical logic device is proposed. An all-optical logic device system composes of an optical intensity switch and add/drop filter. The intensity switch is formed to switch signal by using the relationship between refraction angle and signal intensity. In operation, two input signals are coupled into one with some coupling loss and attenuation, in which the combination of add/drop with intensity switch produces the optical logic gate. The advantage is that the proposed device can operate the high speed logic function. Moreover, it uses low power consumption. Furthermore, by using the extremely small component, this design can be put into a single chip. Finally, we have successfully produced the all-optical logic gate that can generate the accurate AND and NOT operation results.

Electrical characteristics of silicon percolating nanonet-based field effect transistors in the presence of dispersion

NASA Astrophysics Data System (ADS)

Cazimajou, T.; Legallais, M.; Mouis, M.; Ternon, C.; Salem, B.; Ghibaudo, G.

2018-05-01

We studied the current-voltage characteristics of percolating networks of silicon nanowires (nanonets), operated in back-gated transistor mode, for future use as gas or biosensors. These devices featured P-type field-effect characteristics. It was found that a Lambert W function-based compact model could be used for parameter extraction of electrical parameters such as apparent low field mobility, threshold voltage and subthreshold slope ideality factor. Their variation with channel length and nanowire density was related to the change of conduction regime from direct source/drain connection by parallel nanowires to percolating channels. Experimental results could be related in part to an influence of the threshold voltage dispersion of individual nanowires.

Superconducting nanoribbon with a constriction: A quantum-confined Josephson junction

NASA Astrophysics Data System (ADS)

Flammia, L.; Zhang, L.-F.; Covaci, L.; Perali, A.; Milošević, M. V.

2018-04-01

Extended defects are known to strongly affect nanoscale superconductors. Here, we report the properties of superconducting nanoribbons with a constriction formed between two adjacent step edges by solving the Bogoliubov-de Gennes equations self-consistently in the regime where quantum confinement is important. Since the quantum resonances of the superconducting gap in the constricted area are different from the rest of the nanoribbon, such constriction forms a quantum-confined S-S'-S Josephson junction, with a broadly tunable performance depending on the length and width of the constriction with respect to the nanoribbon, and possible gating. These findings provide an intriguing approach to further tailor superconducting quantum devices where Josephson effect is of use.

Field-Effect Transistors Based on Networks of Highly Aligned, Chemically Synthesized N = 7 Armchair Graphene Nanoribbons.

PubMed

Passi, Vikram; Gahoi, Amit; Senkovskiy, Boris V; Haberer, Danny; Fischer, Felix R; Grüneis, Alexander; Lemme, Max C

2018-03-28

We report on the experimental demonstration and electrical characterization of N = 7 armchair graphene nanoribbon (7-AGNR) field effect transistors. The back-gated transistors are fabricated from atomically precise and highly aligned 7-AGNRs, synthesized with a bottom-up approach. The large area transfer process holds the promise of scalable device fabrication with atomically precise nanoribbons. The channels of the FETs are approximately 30 times longer than the average nanoribbon length of 30 nm to 40 nm. The density of the GNRs is high, so that transport can be assumed well-above the percolation threshold. The long channel transistors exhibit a maximum I ON / I OFF current ratio of 87.5.

Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure

PubMed Central

Khan, Z. N.; Ahmed, S.; Ali, M.

2016-01-01

Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application. PMID:27571412

Highly stable organic field-effect transistors with engineered gate dielectrics (Conference Presentation)

NASA Astrophysics Data System (ADS)

Kippelen, Bernard; Wang, Cheng-Yin; Fuentes-Hernandez, Canek; Yun, Minseong; Singh, Ankit K.; Dindar, Amir; Choi, Sangmoo; Graham, Samuel

2016-11-01

Organic field-effect transistors (OFETs) have the potential to lead to low-cost flexible displays, wearable electronics, and sensors. While recent efforts have focused greatly on improving the maximum charge mobility that can be achieved in such devices, studies about the stability and reliability of such high performance devices are relatively scarce. In this talk, we will discuss the results of recent studies aimed at improving the stability of OFETs under operation and their shelf lifetime. In particular, we will focus on device architectures where the gate dielectric is engineered to act simultaneously as an environmental barrier layer. In the past, our group had demonstrated solution-processed top-gate OFETs using TIPS-pentacene and PTAA blends as a semiconductor layer with a bilayer gate dielectric layer of CYTOP/Al2O3, where the oxide layer was fabricated by atomic layer deposition, ALD. Such devices displayed high operational stability with little degradation after 20,000 on/off scan cycles or continuous operation (24 h), and high environmental stability when kept in air for more than 2 years, with unchanged carrier mobility. Using this stable device geometry, simple circuits and sensors operating in aqueous conditions were demonstrated. However, the Al2O3 layer was found to degrade due to corrosion under prolonged exposure in aqueous solutions. In this talk, we will report on the use of a nanolaminate (NL) composed of Al2O3 and HfO2 by ALD to replace the Al2O3 single layer in the bilayer gate dielectric use in top-gate OFETs. Such OFETs were found to operate under harsh condition such as immersion in water at 95 °C. This work was funded by the Department of Energy (DOE) through the Bay Area Photovoltaics Consortium (BAPVC) under Award Number DE-EE0004946.

Quantum computing gates via optimal control

NASA Astrophysics Data System (ADS)

Atia, Yosi; Elias, Yuval; Mor, Tal; Weinstein, Yossi

2014-10-01

We demonstrate the use of optimal control to design two entropy-manipulating quantum gates which are more complex than the corresponding, commonly used, gates, such as CNOT and Toffoli (CCNOT): A two-qubit gate called polarization exchange (PE) and a three-qubit gate called polarization compression (COMP) were designed using GRAPE, an optimal control algorithm. Both gates were designed for a three-spin system. Our design provided efficient and robust nuclear magnetic resonance (NMR) radio frequency (RF) pulses for 13C2-trichloroethylene (TCE), our chosen three-spin system. We then experimentally applied these two quantum gates onto TCE at the NMR lab. Such design of these gates and others could be relevant for near-future applications of quantum computing devices.

A Calibration Method for Nanowire Biosensors to Suppress Device-to-device Variation

PubMed Central

Ishikawa, Fumiaki N.; Curreli, Marco; Chang, Hsiao-Kang; Chen, Po-Chiang; Zhang, Rui; Cote, Richard J.; Thompson, Mark E.; Zhou, Chongwu

2009-01-01

Nanowire/nanotube biosensors have stimulated significant interest; however the inevitable device-to-device variation in the biosensor performance remains a great challenge. We have developed an analytical method to calibrate nanowire biosensor responses that can suppress the device-to-device variation in sensing response significantly. The method is based on our discovery of a strong correlation between the biosensor gate dependence (dIds/dVg) and the absolute response (absolute change in current, ΔI). In2O3 nanowire based biosensors for streptavidin detection were used as the model system. Studying the liquid gate effect and ionic concentration dependence of strepavidin sensing indicates that electrostatic interaction is the dominant mechanism for sensing response. Based on this sensing mechanism and transistor physics, a linear correlation between the absolute sensor response (ΔI) and the gate dependence (dIds/dVg) is predicted and confirmed experimentally. Using this correlation, a calibration method was developed where the absolute response is divided by dIds/dVg for each device, and the calibrated responses from different devices behaved almost identically. Compared to the common normalization method (normalization of the conductance/resistance/current by the initial value), this calibration method was proved advantageous using a conventional transistor model. The method presented here substantially suppresses device-to-device variation, allowing the use of nanosensors in large arrays. PMID:19921812

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

NASA Astrophysics Data System (ADS)

Nedic, Stanko; Tea Chun, Young; Hong, Woong-Ki; Chu, Daping; Welland, Mark

2014-01-01

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ˜16.5 V, a high drain current on/off ratio of ˜105, a gate leakage current below ˜300 pA, and excellent retention characteristics for over 104 s.

Si/SiGe quadruple quantum dots with direct barrier gates

NASA Astrophysics Data System (ADS)

Ward, Daniel; Gamble, John; Foote, Ryan; Savage, Donald; Lagally, Max; Coppersmith, Susan; Eriksson, Mark

2014-03-01

We have fabricated a quadruple quantum dot in a Si/SiGe heterostructure with the aim of demonstrating a two-qubit quantum gate. This device makes use of direct barrier gates, in which individual gates are placed directly over the quantum dots and tunnel barriers. This design enables rational control of both energies and tunnel rates in coupled quantum dots. In this talk we discuss the design, fabrication, and initial characterization of the device. This work was supported in part by ARO (W911NF-12-0607), NSF (DMR-1206915), and the United States Department of Defense. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressly or implied, of the US Government.

A DNA Logic Gate Automaton for Detection of Rabies and Other Lyssaviruses.

PubMed

Vijayakumar, Pavithra; Macdonald, Joanne

2017-07-05

Immediate activation of biosensors is not always desirable, particularly if activation is due to non-specific interactions. Here we demonstrate the use of deoxyribozyme-based logic gate networks arranged into visual displays to precisely control activation of biosensors, and demonstrate a prototype molecular automaton able to discriminate between seven different genotypes of Lyssaviruses, including Rabies virus. The device uses novel mixed-base logic gates to enable detection of the large diversity of Lyssavirus sequence populations, while an ANDNOT logic gate prevents non-specific activation across genotypes. The resultant device provides a user-friendly digital-like, but molecule-powered, dot-matrix text output for unequivocal results read-out that is highly relevant for point of care applications. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Surface stoichiometry modification and improved DC/RF characteristics by plasma treated and annealed AlGaN/GaN HEMTs

NASA Astrophysics Data System (ADS)

Upadhyay, Bhanu B.; Takhar, Kuldeep; Jha, Jaya; Ganguly, Swaroop; Saha, Dipankar

2018-03-01

We demonstrate that N2 and O2 plasma treatment followed by rapid thermal annealing leads to surface stoichiometry modification in a AlGaN/GaN high electron mobility transistor. Both the source/drain access and gate regions respond positively improving the transistor characteristics albeit to different extents. Characterizations indicate that the surface show the characteristics of that of a higher band-gap material like AlxOy and GaxOy along with N-vacancy in the sub-surface region. The N-vacancy leads to an increased two-dimensional electron gas density. The formation of oxides lead to a reduced gate leakage current and surface passivation. The DC characteristics show increased transconductance, saturation drain current, ON/OFF current ratio, sub-threshold swing and lower ON resistance by a factor of 2.9, 2.0, 103.3 , 2.3, and 2.1, respectively. The RF characteristics show an increase in unity current gain frequency by a factor of 1.7 for a 500 nm channel length device.

Camel Gate Field Effect Transistors.

DTIC Science & Technology

1983-01-01

CAMFETs can be designed to yield relatively voltage independent transconductances, large for- * ward turn-on voltages, and large gate-drain breakdown...doping. The FATFET area is 4.6 x 10- 4 cm2. I.- . - . . - , - 36 80 * Camel Gate U_-- Eperimental 60 * -Theoretical % Schottky Gate ~--Experimental CL 4...in the design of other devices. Finally, a comparative study of the reliabil- ities of CAMFETs, JFETs, and MESFETs should be attempted. 43 VII

Quantum logic gates based on ballistic transport in graphene

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dragoman, Daniela; Academy of Romanian Scientists, Splaiul Independentei 54, 050094 Bucharest; Dragoman, Mircea, E-mail: mircea.dragoman@imt.ro

2016-03-07

The paper presents various configurations for the implementation of graphene-based Hadamard, C-phase, controlled-NOT, and Toffoli gates working at room temperature. These logic gates, essential for any quantum computing algorithm, involve ballistic graphene devices for qubit generation and processing and can be fabricated using existing nanolithographical techniques. All quantum gate configurations are based on the very large mean-free-paths of carriers in graphene at room temperature.

Dry dock gate stability modelling

NASA Astrophysics Data System (ADS)

Oktoberty; Widiyanto; Sasono, E. J.; Pramono, S.; Wandono, A. T.

2018-03-01

The development of marine transportation needs in Indonesia increasingly opens national shipyard business opportunities to provide shipbuilding services to the shipbuilding vessels. That emphasizes the stability of prime. The ship's decking door becomes an integral part of the efficient place and the specification of the use of the asset of its operational ease. This study aims to test the stability of Dry Dock gate with the length of 35.4 meters using Maxsurf and Hydromax in analyzing the calculation were in its assessment using interval per 500 mm length so that it can get detail data toward longitudinal and transverse such as studying Ship planning in general. The test result shows dry dock gate meets IMO standard with ballast construction containing 54% and 68% and using fix ballast can produce GMt 1,924 m, tide height 11,357m. The GMt value indicates dry dick gate can be stable and firmly erect at the base of the mouth dry dock. When empty ballast produces GMt 0.996 which means dry dock date is stable, but can easily be torn down. The condition can be used during dry dock gate treatment.

Mesoscopic Field-Effect-Induced Devices in Depleted Two-Dimensional Electron Systems

NASA Astrophysics Data System (ADS)

Bachsoliani, N.; Platonov, S.; Wieck, A. D.; Ludwig, S.

2017-12-01

Nanoelectronic devices embedded in the two-dimensional electron system (2DES) of a GaAs /(Al ,Ga )As heterostructure enable a large variety of applications ranging from fundamental research to high-speed transistors. Electrical circuits are thereby commonly defined by creating barriers for carriers by the selective depletion of a preexisting 2DES. We explore an alternative approach: we deplete the 2DES globally by applying a negative voltage to a global top gate and screen the electric field of the top gate only locally using nanoscale gates placed on the wafer surface between the plane of the 2DES and the top gate. Free carriers are located beneath the screen gates, and their properties can be controlled by means of geometry and applied voltages. This method promises considerable advantages for the definition of complex circuits by the electric-field effect, as it allows us to reduce the number of gates and simplify gate geometries. Examples are carrier systems with ring topology or large arrays of quantum dots. We present a first exploration of this method pursuing field effect, Hall effect, and Aharonov-Bohm measurements to study electrostatic, dynamic, and coherent properties.

Tunable nano Peltier cooling device from geometric effects using a single graphene nanoribbon

NASA Astrophysics Data System (ADS)

Li, Wan-Ju; Yao, Dao-Xin; Carlson, E. W.

2014-08-01

Based on the phenomenon of curvature-induced doping in graphene we propose a class of Peltier cooling devices, produced by geometrical effects, without gating. We show how a graphene nanoribbon laid on an array of curved nano cylinders can be used to create a targeted and tunable cooling device. Using two different approaches, the Nonequilibrium Green's Function (NEGF) method and experimental inputs, we predict that the cooling power of such a device can approach the order of kW/cm2, on par with the best known techniques using standard superlattice structures. The structure proposed here helps pave the way toward designing graphene electronics which use geometry rather than gating to control devices.

Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit

NASA Astrophysics Data System (ADS)

Al-Ameri, Talib; Georgiev, Vihar P.; Sadi, Toufik; Wang, Yijiao; Adamu-Lema, Fikru; Wang, Xingsheng; Amoroso, Salvatore M.; Towie, Ewan; Brown, Andrew; Asenov, Asen

2017-03-01

In this work we investigate the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future CMOS applications at the scaling limit. For the purpose of this paper, we created Si NWTs with two channel crystallographic orientations <1 1 0> and <1 0 0> and six different cross-section profiles. In the first part, we study the impact of quantum corrections on the gate capacitance and mobile charge in the channel. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic performance of the NWTs, is also investigated. The influence of the rotating of the NWTs cross-sectional geometry by 90° on charge distribution in the channel is also studied. We compare the correlation between the charge profile in the channel and cross-sectional dimension for circular transistor with four different cross-sections diameters: 5 nm, 6 nm, 7 nm and 8 nm. In the second part of this paper, we expand the computational study by including different gate lengths for some of the Si NWTs. As a result, we establish a correlation between the mobile charge distribution in the channel and the gate capacitance, drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All calculations are based on a quantum mechanical description of the mobile charge distribution in the channel. This description is based on the solution of the Schrödinger equation in NWT cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions.

Two-dimensional molybdenum disulphide nanosheet-covered metal nanoparticle array as a floating gate in multi-functional flash memories

NASA Astrophysics Data System (ADS)

Han, Su-Ting; Zhou, Ye; Chen, Bo; Zhou, Li; Yan, Yan; Zhang, Hua; Roy, V. A. L.

2015-10-01

Semiconducting two-dimensional materials appear to be excellent candidates for non-volatile memory applications. However, the limited controllability of charge trapping behaviors and the lack of multi-bit storage studies in two-dimensional based memory devices require further improvement for realistic applications. Here, we report a flash memory consisting of metal NPs-molybdenum disulphide (MoS2) as a floating gate by introducing a metal nanoparticle (NP) (Ag, Au, Pt) monolayer underneath the MoS2 nanosheets. Controlled charge trapping and long data retention have been achieved in a metal (Ag, Au, Pt) NPs-MoS2 floating gate flash memory. This controlled charge trapping is hypothesized to be attributed to band bending and a built-in electric field ξbi between the interface of the metal NPs and MoS2. The metal NPs-MoS2 floating gate flash memories were further proven to be multi-bit memory storage devices possessing a 3-bit storage capability and a good retention capability up to 104 s. We anticipate that these findings would provide scientific insight for the development of novel memory devices utilizing an atomically thin two-dimensional lattice structure.Semiconducting two-dimensional materials appear to be excellent candidates for non-volatile memory applications. However, the limited controllability of charge trapping behaviors and the lack of multi-bit storage studies in two-dimensional based memory devices require further improvement for realistic applications. Here, we report a flash memory consisting of metal NPs-molybdenum disulphide (MoS2) as a floating gate by introducing a metal nanoparticle (NP) (Ag, Au, Pt) monolayer underneath the MoS2 nanosheets. Controlled charge trapping and long data retention have been achieved in a metal (Ag, Au, Pt) NPs-MoS2 floating gate flash memory. This controlled charge trapping is hypothesized to be attributed to band bending and a built-in electric field ξbi between the interface of the metal NPs and MoS2. The metal NPs-MoS2 floating gate flash memories were further proven to be multi-bit memory storage devices possessing a 3-bit storage capability and a good retention capability up to 104 s. We anticipate that these findings would provide scientific insight for the development of novel memory devices utilizing an atomically thin two-dimensional lattice structure. Electronic supplementary information (ESI) available: Energy-dispersive X-ray spectroscopy (EDS) spectra of the metal NPs, SEM image of MoS2 on Au NPs, erasing operations of the metal NPs-MoS2 memory device, transfer characteristics of the standard FET devices and Ag NP devices under programming operation, tapping-mode AFM height image of the fabricated MoS2 film for pristine MoS2 flash memory, gate signals used for programming the Au NPs-MoS2 and Pt NPs-MoS2 flash memories, and data levels recorded for 100 sequential cycles. See DOI: 10.1039/c5nr05054e

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

NASA Astrophysics Data System (ADS)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

Multi-Dimensional Quantum Tunneling and Transport Using the Density-Gradient Model

NASA Technical Reports Server (NTRS)

Biegel, Bryan A.; Yu, Zhi-Ping; Ancona, Mario; Rafferty, Conor; Saini, Subhash (Technical Monitor)

1999-01-01

We show that quantum effects are likely to significantly degrade the performance of MOSFETs (metal oxide semiconductor field effect transistor) as these devices are scaled below 100 nm channel length and 2 nm oxide thickness over the next decade. A general and computationally efficient electronic device model including quantum effects would allow us to monitor and mitigate these effects. Full quantum models are too expensive in multi-dimensions. Using a general but efficient PDE solver called PROPHET, we implemented the density-gradient (DG) quantum correction to the industry-dominant classical drift-diffusion (DD) model. The DG model efficiently includes quantum carrier profile smoothing and tunneling in multi-dimensions and for any electronic device structure. We show that the DG model reduces DD model error from as much as 50% down to a few percent in comparison to thin oxide MOS capacitance measurements. We also show the first DG simulations of gate oxide tunneling and transverse current flow in ultra-scaled MOSFETs. The advantages of rapid model implementation using the PDE solver approach will be demonstrated, as well as the applicability of the DG model to any electronic device structure.

A MODFET dc model with improved pinchoff and saturation characteristics

NASA Astrophysics Data System (ADS)

Rohdin, Hans; Roblin, Patrick

1986-05-01

An improved analytical dc model for the MODFET is proposed which uses a new approximation of the two-dimensional electron gas concentration versus gate-to-channel voltage, a ratio which models both the subthreshold region and the gradual saturation of carriers due to the onset of AlGaAs charge modulation. A two-region Grebene-Ghandi model with a floating boundary is used for the channel. A maximum transconductance and a finite intrinsic output conductance in the saturated region are predicted, in agreement with experimental observations. The model is shown to approach the saturated velocity model in the limit of very short gate lengths, and to approach the classical gradual channel model in the limit of very long gate lengths.

A new DG nanoscale TFET based on MOSFETs by using source gate electrode: 2D simulation and an analytical potential model

NASA Astrophysics Data System (ADS)

Ramezani, Zeinab; Orouji, Ali A.

2017-08-01

This paper suggests and investigates a double-gate (DG) MOSFET, which emulates tunnel field effect transistors (M-TFET). We have combined this novel concept into a double-gate MOSFET, which behaves as a tunneling field effect transistor by work function engineering. In the proposed structure, in addition to the main gate, we utilize another gate over the source region with zero applied voltage and a proper work function to convert the source region from N+ to P+. We check the impact obtained by varying the source gate work function and source doping on the device parameters. The simulation results of the M-TFET indicate that it is a suitable case for a switching performance. Also, we present a two-dimensional analytic potential model of the proposed structure by solving the Poisson's equation in x and y directions and by derivatives from the potential profile; thus, the electric field is achieved. To validate our present model, we use the SILVACO ATLAS device simulator. The analytical results have been compared with it.

Bragg reflector based gate stack architecture for process integration of excimer laser annealing

NASA Astrophysics Data System (ADS)

Fortunato, G.; Mariucci, L.; Cuscunà, M.; Privitera, V.; La Magna, A.; Spinella, C.; Magrı, A.; Camalleri, M.; Salinas, D.; Simon, F.; Svensson, B.; Monakhov, E.

2006-12-01

An advanced gate stack structure, which incorporates a Bragg reflector, has been developed for the integration of excimer laser annealing into the power metal-oxide semiconductor (MOS) transistor fabrication process. This advanced gate structure effectively protects the gate stack from melting, thus solving the problem related to protrusion formation. By using this gate stack configuration, power MOS transistors were fabricated with improved electrical characteristics. The Bragg reflector based gate stack architecture can be applied to other device structures, such as scaled MOS transistors, thus extending the possibilities of process integration of excimer laser annealing.

Characterization and reliability of aluminum gallium nitride/gallium nitride high electron mobility transistors

NASA Astrophysics Data System (ADS)

Douglas, Erica Ann

Compound semiconductor devices, particularly those based on GaN, have found significant use in military and civilian systems for both microwave and optoelectronic applications. Future uses in ultra-high power radar systems will require the use of GaN transistors operated at very high voltages, currents and temperatures. GaN-based high electron mobility transistors (HEMTs) have proven power handling capability that overshadows all other wide band gap semiconductor devices for high frequency and high-power applications. Little conclusive research has been reported in order to determine the dominating degradation mechanisms of the devices that result in failure under standard operating conditions in the field. Therefore, it is imperative that further reliability testing be carried out to determine the failure mechanisms present in GaN HEMTs in order to improve device performance, and thus further the ability for future technologies to be developed. In order to obtain a better understanding of the true reliability of AlGaN/GaN HEMTs and determine the MTTF under standard operating conditions, it is crucial to investigate the interaction effects between thermal and electrical degradation. This research spans device characterization, device reliability, and device simulation in order to obtain an all-encompassing picture of the device physics. Initially, finite element thermal simulations were performed to investigate the effect of device design on self-heating under high power operation. This was then followed by a study of reliability of HEMTs and other tests structures during high power dc operation. Test structures without Schottky contacts showed high stability as compared to HEMTs, indicating that degradation of the gate is the reason for permanent device degradation. High reverse bias of the gate has been shown to induce the inverse piezoelectric effect, resulting in a sharp increase in gate leakage current due to crack formation. The introduction of elevated temperatures during high reverse gate bias indicated that device failure is due to the breakdown of an unintentional gate oxide. RF stress of AlGaN/GaN HEMTs showed comparable critical voltage breakdown regime as that of similar devices stressed under dc conditions. Though RF device characteristics showed stability up to a drain bias of 20 V, Schottky diode characteristics degraded substantially at all voltages investigated. Results from both dc and RF stress conditions, under several bias regimes, confirm that the primary root for stress induced degradation was due to the Schottky contact. (Full text of this dissertation may be available via the University of Florida Libraries web site. Please check http://www.uflib.ufl.edu/etd.html)

III-V/Ge MOS device technologies for low power integrated systems

NASA Astrophysics Data System (ADS)

Takagi, S.; Noguchi, M.; Kim, M.; Kim, S.-H.; Chang, C.-Y.; Yokoyama, M.; Nishi, K.; Zhang, R.; Ke, M.; Takenaka, M.

2016-11-01

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. The plasma post oxidation to form GeOx interfacial layers is a key gate stack technology for Ge CMOS. Also, direct wafer bonding of ultrathin body quantum well III-V-OI channels, combined with Tri-gate structures, realizes high performance III-V n-MOSFETs on Si. We also demonstrate planar-type InGaAs and Ge/strained SOI TFETs. The defect-less p+-n source junction formation with steep impurity profiles is a key for high performance TFET operation.

Logic Gates Made of N-Channel JFETs and Epitaxial Resistors

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2008-01-01

Prototype logic gates made of n-channel junction field-effect transistors (JFETs) and epitaxial resistors have been demonstrated, with a view toward eventual implementation of digital logic devices and systems in silicon carbide (SiC) integrated circuits (ICs). This development is intended to exploit the inherent ability of SiC electronic devices to function at temperatures from 300 to somewhat above 500 C and withstand large doses of ionizing radiation. SiC-based digital logic devices and systems could enable operation of sensors and robots in nuclear reactors, in jet engines, near hydrothermal vents, and in other environments that are so hot or radioactive as to cause conventional silicon electronic devices to fail. At present, current needs for digital processing at high temperatures exceed SiC integrated circuit production capabilities, which do not allow for highly integrated circuits. Only single to small number component production of depletion mode n-channel JFETs and epitaxial resistors on a single substrate is possible. As a consequence, the fine matching of components is impossible, resulting in rather large direct-current parameter distributions within a group of transistors typically spanning multiples of 5 to 10. Add to this the lack of p-channel devices to complement the n-channel FETs, the lack of precise dropping diodes, and the lack of enhancement mode devices at these elevated temperatures and the use of conventional direct coupled and buffered direct coupled logic gate design techniques is impossible. The presented logic gate design is tolerant of device parameter distributions and is not hampered by the lack of complementary devices or dropping diodes. In addition to n-channel JFETs, these gates include level-shifting and load resistors (see figure). Instead of relying on precise matching of parameters among individual JFETS, these designs rely on choosing the values of these resistors and of supply potentials so as to make the circuits perform the desired functions throughout the ranges over which the parameters of the JFETs are distributed. The supply rails V(sub dd) and V(sub ss) and the resistors R are chosen as functions of the distribution of direct-current operating parameters of the group of transistors used.

Excitonic AND Logic Gates on DNA Brick Nanobreadboards.

PubMed

Cannon, Brittany L; Kellis, Donald L; Davis, Paul H; Lee, Jeunghoon; Kuang, Wan; Hughes, William L; Graugnard, Elton; Yurke, Bernard; Knowlton, William B

2015-03-18

A promising application of DNA self-assembly is the fabrication of chromophore-based excitonic devices. DNA brick assembly is a compelling method for creating programmable nanobreadboards on which chromophores may be rapidly and easily repositioned to prototype new excitonic devices, optimize device operation, and induce reversible switching. Using DNA nanobreadboards, we have demonstrated each of these functions through the construction and operation of two different excitonic AND logic gates. The modularity and high chromophore density achievable via this brick-based approach provide a viable path toward developing information processing and storage systems.

Excitonic AND Logic Gates on DNA Brick Nanobreadboards

PubMed Central

2015-01-01

A promising application of DNA self-assembly is the fabrication of chromophore-based excitonic devices. DNA brick assembly is a compelling method for creating programmable nanobreadboards on which chromophores may be rapidly and easily repositioned to prototype new excitonic devices, optimize device operation, and induce reversible switching. Using DNA nanobreadboards, we have demonstrated each of these functions through the construction and operation of two different excitonic AND logic gates. The modularity and high chromophore density achievable via this brick-based approach provide a viable path toward developing information processing and storage systems. PMID:25839049

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Surface Engineering of Polycrystalline Silicon for Long-Term Mechanical Stress Endurance Enhancement in Flexible Low-Temperature Poly-Si Thin-Film Transistors.

PubMed

Chen, Bo-Wei; Chang, Ting-Chang; Chang, Kuan-Chang; Hung, Yu-Ju; Huang, Shin-Ping; Chen, Hua-Mao; Liao, Po-Yung; Lin, Yu-Ho; Huang, Hui-Chun; Chiang, Hsiao-Cheng; Yang, Chung-I; Zheng, Yu-Zhe; Chu, Ann-Kuo; Li, Hung-Wei; Tsai, Chih-Hung; Lu, Hsueh-Hsing; Wang, Terry Tai-Jui; Chang, Tsu-Chiang

2017-04-05

The surface morphology in polycrystalline silicon (poly-Si) film is an issue regardless of whether conventional excimer laser annealing (ELA) or the newer metal-induced lateral crystallization (MILC) process is used. This paper investigates the stress distribution while undergoing long-term mechanical stress and the influence of stress on electrical characteristics. Our simulated results show that the nonuniform stress in the gate insulator is more pronounced near the polysilicon/gate insulator edge and at the two sides of the polysilicon protrusion. This stress results in defects in the gate insulator and leads to a nonuniform degradation phenomenon, which affects both the performance and the reliability in thin-film transistors (TFTs). The degree of degradation is similar regardless of bending axis (channel-length axis, channel-width axis) or bending type (compression, tension), which means that the degradation is dominated by the protrusion effects. Furthermore, by utilizing long-term electrical bias stresses after undergoing long-tern bending stress, it is apparent that the carrier injection is severe in the subchannel region, which confirms that the influence of protrusions is crucial. To eliminate the influence of surface morphology in poly-Si, three kinds of laser energy density were used during crystallization to control the protrusion height. The device with the lowest protrusions demonstrates the smallest degradation after undergoing long-term bending.

Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation

NASA Astrophysics Data System (ADS)

Seema; Chauhan, Sudakar Singh

2018-05-01

In this paper, we demonstrate the double gate vertical tunnel field-effect transistor using homo/hetero dielectric buried oxide (HDB) to obtain the optimized device characteristics. In this concern, the existence of double gate, HDB and electrode work-function engineering enhances DC performance and Analog/RF performance. The use of electrostatic doping helps to achieve higher on-current owing to occurrence of higher tunneling generation rate of charge carriers at the source/epitaxial interface. Further, lightly doped drain region and high- k dielectric below channel and drain region are responsible to suppress the ambipolar current. Simulated results clarifies that proposed device have achieved the tremendous performance in terms of driving current capability, steeper subthreshold slope (SS), drain induced barrier lowering (DIBL), hot carrier effects (HCEs) and high frequency parameters for better device reliability.

A novel thin-film transistor with step gate-overlapped lightly doped drain and raised source/drain design

NASA Astrophysics Data System (ADS)

Chien, Feng-Tso; Chen, Jian-Liang; Chen, Chien-Ming; Chen, Chii-Wen; Cheng, Ching-Hwa; Chiu, Hsien-Chin

2017-11-01

In this paper, a novel step gate-overlapped lightly doped drain (GOLDD) with raised source/drain (RSD) structure (SGORSD) is proposed for TFT electronic device application. The new SGORSD structure could obtain a low electric field at channel near the drain side owing to a step GOLDD design. Compared to the conventional device, the SGORSD TFT exhibits a better kink effect and higher breakdown performance due to the reduced drain electric field (D-EF). In addition, the leakage current also can be suppressed. Moreover, the device stability, such as the threshold voltage shift and drain current degradation under a high gate bias, is improved by the design of SGORSD structure. Therefore, this novel step GOLDD structure can be a promising design to be used in active-matrix flat panel electronics.

I2 basal stacking fault as a degradation mechanism in reverse gate-biased AlGaN/GaN HEMTs

NASA Astrophysics Data System (ADS)

Lang, A. C.; Hart, J. L.; Wen, J. G.; Miller, D. J.; Meyer, D. J.; Taheri, M. L.

2016-09-01

Here, we present the observation of a bias-induced, degradation-enhancing defect process in plasma-assisted molecular beam epitaxy grown reverse gate-biased AlGaN/GaN high electron mobility transistors (HEMTs), which is compatible with the current theoretical framework of HEMT degradation. Specifically, we utilize both conventional transmission electron microscopy and aberration-corrected transmission electron microscopy to analyze microstructural changes in not only high strained regions in degraded AlGaN/GaN HEMTs but also the extended gate-drain access region. We find a complex defect structure containing an I2 basal stacking fault and offer a potential mechanism for device degradation based on this defect structure. This work supports the reality of multiple failure mechanisms during device operation and identifies a defect potentially involved with device degradation.

Variable N-type negative resistance in an injection-gated double-injection diode

NASA Technical Reports Server (NTRS)

Kapoor, A. K.; Henderson, H. T.

1981-01-01

Double-injection (DI) switching devices consist of p+ and n+ contacts (for hole and electron injection, respectively), separated by a near intrinsic semiconductor region containing deep traps. Under proper conditions, these devices exhibit S-type differential negative resistance (DNR) similar to silicon-controlled rectifiers. With the added influence of a p+ gate appropriately placed between the anode (p+) and cathode (n+), the current-voltage characteristic of the device has been manipulated for the first time to exhibit a variable N-type DNR. The anode current and the anode-to-cathode voltage levels at which this N-type DNR is observed can be varied by changing the gate-to-cathode bias. In essence, the classical S-type DI diode can be electronically transformed into an N-type diode. A first-order phenomenological model is proposed for the N-type DNR.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moghadam, Reza M.; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to low-power field-effect devices that can be used for logic or memory. Essential to realizing such field-effect devices is the development of ferroelectric metal-oxide-semiconductor (MOS) capacitors, in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel. Here we demonstrate that ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x= 0.7) that has been epitaxially grown on Ge. We find that themore » ferroelectric properties of SrZrxTi1-xO3 are exceptionally robust, as gate layers as thin as 5 nm give rise to hysteretic capacitance-voltage characteristics that are 2 V in width. The development of ferroelectric MOS capacitors with gate thicknesses that are technologically relevant opens a pathway to realize scalable ferroelectric field-effect devices.« less

Fabrication of a liquid-gated enzyme field effect device for sensitive glucose detection.

PubMed

Fathollahzadeh, M; Hosseini, M; Haghighi, B; Kolahdouz, M; Fathipour, M

2016-06-14

This study presents fabrication of a liquid-gated enzyme field effect device and its implementation as a glucose biosensor. The device consisted of four electrodes on a glass substrate with a channel functionalized by carboxylated multi-walled carbon nanotubes-polyaniline nanocomposite (MWCNTCOOH/PAn) and glucose oxidase. The resistance of functionalized channel increased with increasing the concentration of glucose when an electric field was applied to the liquid gate. The most effective and stable performance was obtained at the applied electric field of 100 mV. The device resistance, R, exhibited a linear relationship with the logarithm of glucose concentration in the range between 0.005 and 500 mM glucose. The detection limit (S/N = 3) for glucose was about 0.5 μM. Large effective area and good conductivity properties of MWCNTCOOH/PAn nanocomposite were the key features of the fabricated sensitive and stable glucose biosensor. Copyright © 2016 Elsevier B.V. All rights reserved.

High sensitivity measurement system for the direct-current, capacitance-voltage, and gate-drain low frequency noise characterization of field effect transistors.

PubMed

Giusi, G; Giordano, O; Scandurra, G; Rapisarda, M; Calvi, S; Ciofi, C

2016-04-01

Measurements of current fluctuations originating in electron devices have been largely used to understand the electrical properties of materials and ultimate device performances. In this work, we propose a high-sensitivity measurement setup topology suitable for the automatic and programmable Direct-Current (DC), Capacitance-Voltage (CV), and gate-drain low frequency noise characterization of field effect transistors at wafer level. Automatic and programmable operation is particularly useful when the device characteristics relax or degrade with time due to optical, bias, or temperature stress. The noise sensitivity of the proposed topology is in the order of fA/Hz(1/2), while DC performances are limited only by the source and measurement units used to bias the device under test. DC, CV, and NOISE measurements, down to 1 pA of DC gate and drain bias currents, in organic thin film transistors are reported to demonstrate system operation and performances.

High sensitivity measurement system for the direct-current, capacitance-voltage, and gate-drain low frequency noise characterization of field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Giusi, G.; Giordano, O.; Scandurra, G.

Measurements of current fluctuations originating in electron devices have been largely used to understand the electrical properties of materials and ultimate device performances. In this work, we propose a high-sensitivity measurement setup topology suitable for the automatic and programmable Direct-Current (DC), Capacitance-Voltage (CV), and gate-drain low frequency noise characterization of field effect transistors at wafer level. Automatic and programmable operation is particularly useful when the device characteristics relax or degrade with time due to optical, bias, or temperature stress. The noise sensitivity of the proposed topology is in the order of fA/Hz{sup 1/2}, while DC performances are limited only bymore » the source and measurement units used to bias the device under test. DC, CV, and NOISE measurements, down to 1 pA of DC gate and drain bias currents, in organic thin film transistors are reported to demonstrate system operation and performances.« less

Charge plasma technique based dopingless accumulation mode junctionless cylindrical surrounding gate MOSFET: analog performance improvement

NASA Astrophysics Data System (ADS)

Trivedi, Nitin; Kumar, Manoj; Haldar, Subhasis; Deswal, S. S.; Gupta, Mridula; Gupta, R. S.

2017-09-01

A charge plasma technique based dopingless (DL) accumulation mode (AM) junctionless (JL) cylindrical surrounding gate (CSG) MOSFET has been proposed and extensively investigated. Proposed device has no physical junction at source to channel and channel to drain interface. The complete silicon pillar has been considered as undoped. The high free electron density or induced N+ region is designed by keeping the work function of source/drain metal contacts lower than the work function of undoped silicon. Thus, its fabrication complexity is drastically reduced by curbing the requirement of high temperature doping techniques. The electrical/analog characteristics for the proposed device has been extensively investigated using the numerical simulation and are compared with conventional junctionless cylindrical surrounding gate (JL-CSG) MOSFET with identical dimensions. For the numerical simulation purpose ATLAS-3D device simulator is used. The results show that the proposed device is more short channel immune to conventional JL-CSG MOSFET and suitable for faster switching applications due to higher I ON/ I OFF ratio.

Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

PubMed

Choi, Woo Young; Lee, Hyun Kook

2016-01-01

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

Progress towards two double-dot qubits in Si/SiGe: quadruple quantum dots

NASA Astrophysics Data System (ADS)

Foote, Ryan H.; Ward, Daniel R.; Kim, Dohun; Thorgrimsson, Brandur; Smith, Luke; Savage, D. E.; Lagally, M. G.; Friesen, Mark; Coppersmith, S. N.; Eriksson, M. A.

We present the fabrication and electrical characterization of two types of gate-defined quadruple quantum dot devices formed in Si/SiGe heterostructures. We compare two designs, one which uses three layers of tightly overlapping gates and is similar to the work found in, and one which uses only two layers of gates and has significantly more open space between neighboring gates. We demonstrate charge-state conditional quantum oscillations in the more open device, we compare the tunability of both devices with each other, and we discuss the implications of these measurements on a path towards larger numbers of coupled quantum dot qubits. This work is supported in part by ARO (W911NF-12-1-0607), NSF (DMR-1206915, PHY-1104660), ONR (N00014-15-1-0029) and the Department of Defense. Development and maintenance of the growth facilities used for fabricating samples supported by DOE (DE-FG02-03ER46028). DK acknowledges support from the Korea Institute of Science and Technology Institutional Program (Project No. 2E26681). This research utilized facilities supported by the NSF (DMR-0832760, DMR-1121288).

rf Quantum Capacitance of the Topological Insulator Bi2Se3 in the Bulk Depleted Regime for Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Inhofer, A.; Duffy, J.; Boukhicha, M.; Bocquillon, E.; Palomo, J.; Watanabe, K.; Taniguchi, T.; Estève, I.; Berroir, J. M.; Fève, G.; Plaçais, B.; Assaf, B. A.

2018-02-01

A metal-dielectric topological-insulator capacitor device based on hexagonal-boron-nitrate- (h -BN) encapsulated CVD-grown Bi2Se3 is realized and investigated in the radio-frequency regime. The rf quantum capacitance and device resistance are extracted for frequencies as high as 10 GHz and studied as a function of the applied gate voltage. The superior quality h -BN gate dielectric combined with the optimized transport characteristics of CVD-grown Bi2Se3 (n ˜1018 cm-3 in 8 nm) on h -BN allow us to attain a bulk depleted regime by dielectric gating. A quantum-capacitance minimum and a linear variation of the capacitance with the chemical potential are observed revealing a Dirac regime. The topological surface state in proximity to the gate is seen to reach charge neutrality, but the bottom surface state remains charged and capacitively coupled to the top via the insulating bulk. Our work paves the way toward implementation of topological materials in rf devices.

Electroluminescence and other diagnostic techniques for the study of hot-electron effects in compound semiconductor devices

NASA Astrophysics Data System (ADS)

Zanoni, Enrico; Meneghesso, Gaudenzio; Menozzi, Roberto

2000-03-01

Hot electron in III-V FETs can be indirectly monitored by measuring the current coming out from the gate when the device is biased at high electric fields. This negative current is due to the collection of holes generated by impact ionization in the gate-to drain region. Electroluminescence represents a powerful tool in order to characterize not only hot electrons but also material properties. By using spatially resolved emission microscopy it is possible to show that the light due to cold electron/hole recombination is emitted between the gate and the source (low electric field region), while the contribution due to hot electrons is emitted between the gate and the drain (high electric field region). Deep-traps created in the device by hot carriers can be analysed by means of drain current deep level transient spectroscopy and by transconductance frequency dispersion. Cathodoluminescence, optical beam induced current, X-ray spectroscopy, electron energy loss spectroscopy in combination with a transmission electron microscopy are powerful tools in order to identify and localize surface modification following hot-electron stress tests.

Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

PubMed

Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

2017-10-11

The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

Combining a multi deposition multi annealing technique with a scavenging (Ti) to improve the high-k/metal gate stack performance for a gate-last process

NASA Astrophysics Data System (ADS)

ShuXiang, Zhang; Hong, Yang; Bo, Tang; Zhaoyun, Tang; Yefeng, Xu; Jing, Xu; Jiang, Yan

2014-10-01

ALD HfO2 films fabricated by a novel multi deposition multi annealing (MDMA) technique are investigated, we have included samples both with and without a Ti scavenging layer. As compared to the reference gate stack treated by conventional one-time deposition and annealing (D&A), devices receiving MDMA show a significant reduction in leakage current. Meanwhile, EOT growth is effectively controlled by the Ti scavenging layer. This improvement strongly correlates with the cycle number of D&A (while keeping the total annealing time and total dielectrics thickness the same). Transmission electron microscope and energy-dispersive X-ray spectroscopy analysis suggests that oxygen incorporation into both the high-k film and the interfacial layer is likely to be responsible for the improvement of the device. This novel MDMA is promising for the development of gate stack technology in a gate last integration scheme.

Highly reliable top-gated thin-film transistor memory with semiconducting, tunneling, charge-trapping, and blocking layers all of flexible polymers.

PubMed

Wang, Wei; Hwang, Sun Kak; Kim, Kang Lib; Lee, Ju Han; Cho, Suk Man; Park, Cheolmin

2015-05-27

The core components of a floating-gate organic thin-film transistor nonvolatile memory (OTFT-NVM) include the semiconducting channel layer, tunneling layer, floating-gate layer, and blocking layer, besides three terminal electrodes. In this study, we demonstrated OTFT-NVMs with all four constituent layers made of polymers based on consecutive spin-coating. Ambipolar charges injected and trapped in a polymer electret charge-controlling layer upon gate program and erase field successfully allowed for reliable bistable channel current levels at zero gate voltage. We have observed that the memory performance, in particular the reliability of a device, significantly depends upon the thickness of both blocking and tunneling layers, and with an optimized layer thickness and materials selection, our device exhibits a memory window of 15.4 V, on/off current ratio of 2 × 10(4), read and write endurance cycles over 100, and time-dependent data retention of 10(8) s, even when fabricated on a mechanically flexible plastic substrate.

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors.

PubMed

Chaure, Nandu B; Cammidge, Andrew N; Chambrier, Isabelle; Cook, Michael J; Cain, Markys G; Murphy, Craig E; Pal, Chandana; Ray, Asim K

2011-04-01

Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl) copper phthalocyanine (CuPc 6 ) were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs) in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO 2 ) as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS) resulted in values of 4×10 -2 cm 2 V -1 s -1 and 10 6 for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones.

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors

PubMed Central

Chaure, Nandu B; Cammidge, Andrew N; Chambrier, Isabelle; Cook, Michael J; Cain, Markys G; Murphy, Craig E; Pal, Chandana; Ray, Asim K

2011-01-01

Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl) copper phthalocyanine (CuPc6) were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs) in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO2) as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS) resulted in values of 4×10−2 cm2 V−1 s−1 and 106 for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones. PMID:27877383

AlGaN/GaN-on-Si monolithic power-switching device with integrated gate current booster

NASA Astrophysics Data System (ADS)

Han, Sang-Woo; Jo, Min-Gi; Kim, Hyungtak; Cho, Chun-Hyung; Cha, Ho-Young

2017-08-01

This study investigates the effects of a monolithic gate current booster integrated with an AlGaN/GaN-on-Si power-switching device. The integrated gate current booster was implemented by a single-stage inverter topology consisting of a recessed normally-off AlGaN/GaN MOS-HFET and a mesa resistor. The monolithically integrated gate current booster in a switching FET eliminated the parasitic elements caused by external interconnection and enabled fast switching operation. The gate charging and discharging currents were boosted by the integrated inverter, which significantly reduced both rise and fall times: the rise time was reduced from 626 to 41.26 ns, while the fall time was reduced from 554 to 42.19 ns by the single-stage inverter. When the packaged monolithic power chip was tested under 1 MHz hard-switching operation with VDD = 200 V, the switching loss was found to have been drastically reduced, from 5.27 to 0.55 W.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baart, T. A.; Vandersypen, L. M. K.; Kavli Institute of Nanoscience, Delft University of Technology, P.O. Box 5046, 2600 GA Delft

We report the computer-automated tuning of gate-defined semiconductor double quantum dots in GaAs heterostructures. We benchmark the algorithm by creating three double quantum dots inside a linear array of four quantum dots. The algorithm sets the correct gate voltages for all the gates to tune the double quantum dots into the single-electron regime. The algorithm only requires (1) prior knowledge of the gate design and (2) the pinch-off value of the single gate T that is shared by all the quantum dots. This work significantly alleviates the user effort required to tune multiple quantum dot devices.

Benchmarking gate-based quantum computers

NASA Astrophysics Data System (ADS)

Michielsen, Kristel; Nocon, Madita; Willsch, Dennis; Jin, Fengping; Lippert, Thomas; De Raedt, Hans

2017-11-01

With the advent of public access to small gate-based quantum processors, it becomes necessary to develop a benchmarking methodology such that independent researchers can validate the operation of these processors. We explore the usefulness of a number of simple quantum circuits as benchmarks for gate-based quantum computing devices and show that circuits performing identity operations are very simple, scalable and sensitive to gate errors and are therefore very well suited for this task. We illustrate the procedure by presenting benchmark results for the IBM Quantum Experience, a cloud-based platform for gate-based quantum computing.

Improved yields for MOST’s using ion implantation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Brockman, H. E.

1976-04-01

Conventionally diffused source and drain polysilicon gate MOST's commonly exhibit one type of fault, namely, that of polysilicon-to-diffusion short circuits. Investigations into the yields of large-area devices fabricated using ion-implanted sources and drains are compared with those of diffused structures. An improved technology for the chemical shaping of the polysilicon gates, which improves the yields for both types of devices, is also described. (AIP)

Ambipolar transport in CVD grown MoSe2 monolayer using an ionic liquid gel gate dielectric

NASA Astrophysics Data System (ADS)

Ortiz, Deliris N.; Ramos, Idalia; Pinto, Nicholas J.; Zhao, Meng-Qiang; Kumar, Vinayak; Johnson, A. T. Charlie

2018-03-01

CVD grown MoSe2 monolayers were electrically characterized at room temperature in a field effect transistor (FET) configuration using an ionic liquid (IL) as the gate dielectric. During the growth, instead of using MoO3 powder, ammonium heptamolybdate was used for better Mo control of the source and sodium cholate added for lager MoSe2 growth areas. In addition, a high specific capacitance (˜7 μF/cm2) IL was used as the gate dielectric to significantly reduce the operating voltage. The device exhibited ambipolar charge transport at low voltages with enhanced parameters during n- and p-FET operation. IL gating thins the Schottky barrier at the metal/semiconductor interface permitting efficient charge injection into the channel and reduces the effects of contact resistance on device performance. The large specific capacitance of the IL was also responsible for a much higher induced charge density compared to the standard SiO2 dielectric. The device was successfully tested as an inverter with a gain of ˜2. Using a common metal for contacts simplifies fabrication of this ambipolar device, and the possibility of radiative recombination of holes and electrons could further extend its use in low power optoelectronic applications.

Ka-band Ga-As FET noise receiver/device development

NASA Technical Reports Server (NTRS)

Schellenberg, J. M.; Feng, M.; Hackett, L. H.; Watkins, E. T.; Yamasaki, H.

1982-01-01

The development of technology for a 30 GHz low noise receiver utilizing GaAs FET devices exclusively is discussed. This program required single and dual-gate FET devices, low noise FET amplifiers, dual-gate FET mixers, and FET oscillators operating at Ka-band frequencies. A 0.25 micrometer gate FET device, developed with a minimum noise figure of 3.3 dB at 29 GHz and an associated gain of 7.4 dB, was used to fabricate a 3-stage amplifier with a minimum noise figure and associated gain of 4.4 dB and 17 dB, respectively. The 1-dB gain bandwidth of this amplifier extended from below 26.5 GHz to 30.5 GHz. A dual-gate mixer with a 2 dB conversion loss and a minimum noise figure of 10 dB at 29 GHz as well as a dielectric resonator stabilized FET oscillator at 25 GHz for the receiver L0. From these components, a hybrid microwave integrated circuit receiver was constructed which demonstrates a minimum single-side band noise figure of 4.6 dB at 29 GHz with a conversion gain of 17 dB. The output power at the 1-dB gain compression point was -5 dBm.

A magnetic phase-transition graphene transistor with tunable spin polarization

NASA Astrophysics Data System (ADS)

Vancsó, Péter; Hagymási, Imre; Tapasztó, Levente

2017-06-01

Graphene nanoribbons (GNRs) have been proposed as potential building blocks for field effect transistor (FET) devices due to their quantum confinement bandgap. Here, we propose a novel GNR device concept, enabling the control of both charge and spin signals, integrated within the simplest three-terminal device configuration. In a conventional FET device, a gate electrode is employed to tune the Fermi level of the system in and out of a static bandgap. By contrast, in the switching mechanism proposed here, the applied gate voltage can dynamically open and close an interaction gap, with only a minor shift of the Fermi level. Furthermore, the strong interplay of the band structure and edge spin configuration in zigzag ribbons enables such transistors to carry spin polarized current without employing an external magnetic field or ferromagnetic contacts. Using an experimentally validated theoretical model, we show that such transistors can switch at low voltages and high speed, and the spin polarization of the current can be tuned from 0% to 50% by using the same back gate electrode. Furthermore, such devices are expected to be robust against edge irregularities and can operate at room temperature. Controlling both charge and spin signal within the simplest FET device configuration could open up new routes in data processing with graphene based devices.

Nanoscale MOS devices: device parameter fluctuations and low-frequency noise (Invited Paper)

NASA Astrophysics Data System (ADS)

Wong, Hei; Iwai, Hiroshi; Liou, J. J.

2005-05-01

It is well-known in conventional MOS transistors that the low-frequency noise or flicker noise is mainly contributed by the trapping-detrapping events in the gate oxide and the mobility fluctuation in the surface channel. In nanoscale MOS transistors, the number of trapping-detrapping events becomes less important because of the large direct tunneling current through the ultrathin gate dielectric which reduces the probability of trapping-detrapping and the level of leakage current fluctuation. Other noise sources become more significant in nanoscale devices. The source and drain resistance noises have greater impact on the drain current noise. Significant contribution of the parasitic bipolar transistor noise in ultra-short channel and channel mobility fluctuation to the channel noise are observed. The channel mobility fluctuation in nanoscale devices could be due to the local composition fluctuation of the gate dielectric material which gives rise to the permittivity fluctuation along the channel and results in gigantic channel potential fluctuation. On the other hand, the statistical variations of the device parameters across the wafer would cause the noise measurements less accurate which will be a challenge for the applicability of analytical flicker noise model as a process or device evaluation tool for nanoscale devices. Some measures for circumventing these difficulties are proposed.

Two stage dual gate MESFET monolithic gain control amplifier for Ka-band

NASA Technical Reports Server (NTRS)

Sokolov, V.; Geddes, J.; Contolatis, A.

1987-01-01

A monolithic two stage gain control amplifier has been developed using submicron gate length dual gate MESFETs fabricated on ion implanted material. The amplifier has a gain of 12 dB at 30 GHz with a gain control range of over 30 dB. This ion implanted monolithic IC is readily integrable with other phased array receiver functions such as low noise amplifiers and phase shifters.