High Performance Transparent Transistor Memory Devices Using Nano-Floating Gate of Polymer/ZnO Nanocomposites

NASA Astrophysics Data System (ADS)

Shih, Chien-Chung; Lee, Wen-Ya; Chiu, Yu-Cheng; Hsu, Han-Wen; Chang, Hsuan-Chun; Liu, Cheng-Liang; Chen, Wen-Chang

2016-02-01

Nano-floating gate memory devices (NFGM) using metal nanoparticles (NPs) covered with an insulating polymer have been considered as a promising electronic device for the next-generation nonvolatile organic memory applications NPs. However, the transparency of the device with metal NPs is restricted to 60~70% due to the light absorption in the visible region caused by the surface plasmon resonance effects of metal NPs. To address this issue, we demonstrate a novel NFGM using the blends of hole-trapping poly (9-(4-vinylphenyl) carbazole) (PVPK) and electron-trapping ZnO NPs as the charge storage element. The memory devices exhibited a remarkably programmable memory window up to 60 V during the program/erase operations, which was attributed to the trapping/detrapping of charge carriers in ZnO NPs/PVPK composite. Furthermore, the devices showed the long-term retention time (>105 s) and WRER test (>200 cycles), indicating excellent electrical reliability and stability. Additionally, the fabricated transistor memory devices exhibited a relatively high transparency of 90% at the wavelength of 500 nm based on the spray-coated PEDOT:PSS as electrode, suggesting high potential for transparent organic electronic memory devices.

Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

NASA Astrophysics Data System (ADS)

Park, C. H.; Im, Seongil; Yun, Jungheum; Lee, Gun Hwan; Lee, Byoung H.; Sung, Myung M.

2009-11-01

We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgOx and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgOx gate operates under low voltage write-erase (WR-ER) pulse of ±20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of ±70 V for WR and ER states. Both devices stably operated under visible illuminations.

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement

PubMed Central

Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

2016-01-01

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates. PMID:26763827

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement.

PubMed

Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

2016-01-01

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates.

Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

NASA Astrophysics Data System (ADS)

Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin; Chi, Li-Feng; Wang, Sui-Dong

2015-03-01

Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

Synergistic High Charge-Storage Capacity for Multi-level Flexible Organic Flash Memory

NASA Astrophysics Data System (ADS)

Kang, Minji; Khim, Dongyoon; Park, Won-Tae; Kim, Jihong; Kim, Juhwan; Noh, Yong-Young; Baeg, Kang-Jun; Kim, Dong-Yu

2015-07-01

Electret and organic floating-gate memories are next-generation flash storage mediums for printed organic complementary circuits. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.

Synergistic High Charge-Storage Capacity for Multi-level Flexible Organic Flash Memory.

PubMed

Kang, Minji; Khim, Dongyoon; Park, Won-Tae; Kim, Jihong; Kim, Juhwan; Noh, Yong-Young; Baeg, Kang-Jun; Kim, Dong-Yu

2015-07-23

Electret and organic floating-gate memories are next-generation flash storage mediums for printed organic complementary circuits. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.

Reconfigurable Fault Tolerance for FPGAs

NASA Technical Reports Server (NTRS)

Shuler, Robert, Jr.

2010-01-01

The invention allows a field-programmable gate array (FPGA) or similar device to be efficiently reconfigured in whole or in part to provide higher capacity, non-redundant operation. The redundant device consists of functional units such as adders or multipliers, configuration memory for the functional units, a programmable routing method, configuration memory for the routing method, and various other features such as block RAM, I/O (random access memory, input/output) capability, dedicated carry logic, etc. The redundant device has three identical sets of functional units and routing resources and majority voters that correct errors. The configuration memory may or may not be redundant, depending on need. For example, SRAM-based FPGAs will need some type of radiation-tolerant configuration memory, or they will need triple-redundant configuration memory. Flash or anti-fuse devices will generally not need redundant configuration memory. Some means of loading and verifying the configuration memory is also required. These are all components of the pre-existing redundant FPGA. This innovation modifies the voter to accept a MODE input, which specifies whether ordinary voting is to occur, or if redundancy is to be split. Generally, additional routing resources will also be required to pass data between sections of the device created by splitting the redundancy. In redundancy mode, the voters produce an output corresponding to the two inputs that agree, in the usual fashion. In the split mode, the voters select just one input and convey this to the output, ignoring the other inputs. In a dual-redundant system (as opposed to triple-redundant), instead of a voter, there is some means to latch or gate a state update only when both inputs agree. In this case, the invention would require modification of the latch or gate so that it would operate normally in redundant mode, and would separately latch or gate the inputs in non-redundant mode.

Multi-bit dark state memory: Double quantum dot as an electronic quantum memory

NASA Astrophysics Data System (ADS)

Aharon, Eran; Pozner, Roni; Lifshitz, Efrat; Peskin, Uri

2016-12-01

Quantum dot clusters enable the creation of dark states which preserve electrons or holes in a coherent superposition of dot states for a long time. Various quantum logic devices can be envisioned to arise from the possibility of storing such trapped particles for future release on demand. In this work, we consider a double quantum dot memory device, which enables the preservation of a coherent state to be released as multiple classical bits. Our unique device architecture uses an external gating for storing (writing) the coherent state and for retrieving (reading) the classical bits, in addition to exploiting an internal gating effect for the preservation of the coherent state.

Pentacene-based metal-insulator-semiconductor memory structures utilizing single walled carbon nanotubes as a nanofloating gate

NASA Astrophysics Data System (ADS)

Sleiman, A.; Rosamond, M. C.; Alba Martin, M.; Ayesh, A.; Al Ghaferi, A.; Gallant, A. J.; Mabrook, M. F.; Zeze, D. A.

2012-01-01

A pentacene-based organic metal-insulator-semiconductor memory device, utilizing single walled carbon nanotubes (SWCNTs) for charge storage is reported. SWCNTs were embedded, between SU8 and polymethylmethacrylate to achieve an efficient encapsulation. The devices exhibit capacitance-voltage clockwise hysteresis with a 6 V memory window at ± 30 V sweep voltage, attributed to charging and discharging of SWCNTs. As the applied gate voltage exceeds the SU8 breakdown voltage, charge leakage is induced in SU8 to allow more charges to be stored in the SWCNT nodes. The devices exhibited high storage density (˜9.15 × 1011 cm-2) and demonstrated 94% charge retention due to the superior encapsulation.

Nonvolatile floating gate organic memory device based on pentacene/CdSe quantum dot heterojuction

NASA Astrophysics Data System (ADS)

Shin, Ik-Soo; Kim, Jung-Min; Jeun, Jun-Ho; Yoo, Seok-Hyun; Ge, Ziyi; Hong, Jong-In; Ho Bang, Jin; Kim, Yong-Sang

2012-04-01

An organic floating-gate memory device using CdSe quantum dots (QDs) as a charge-trapping element was fabricated. CdSe QDs were localized beneath a pentacene without any tunneling insulator, and the QD layer played a role as hole-trapping sites. The band bending formed at the junction between pentacene and QD layers inhibited back-injection of holes trapped in CdSe into pentacene, which appeared as a hysteretic capacitance-voltage response during the operation of the device. Nearly, 60% of trapped charge was sustained even after 104 s in programmed state, and this long retention time can be potentially useful in practical applications of non-volatile memory.

High-Performance Flexible Organic Nano-Floating Gate Memory Devices Functionalized with Cobalt Ferrite Nanoparticles.

PubMed

Jung, Ji Hyung; Kim, Sunghwan; Kim, Hyeonjung; Park, Jongnam; Oh, Joon Hak

2015-10-07

Nano-floating gate memory (NFGM) devices are transistor-type memory devices that use nanostructured materials as charge trap sites. They have recently attracted a great deal of attention due to their excellent performance, capability for multilevel programming, and suitability as platforms for integrated circuits. Herein, novel NFGM devices have been fabricated using semiconducting cobalt ferrite (CoFe2O4) nanoparticles (NPs) as charge trap sites and pentacene as a p-type semiconductor. Monodisperse CoFe2O4 NPs with different diameters have been synthesized by thermal decomposition and embedded in NFGM devices. The particle size effects on the memory performance have been investigated in terms of energy levels and particle-particle interactions. CoFe2O4 NP-based memory devices exhibit a large memory window (≈73.84 V), a high read current on/off ratio (read I(on)/I(off)) of ≈2.98 × 10(3), and excellent data retention. Fast switching behaviors are observed due to the exceptional charge trapping/release capability of CoFe2O4 NPs surrounded by the oleate layer, which acts as an alternative tunneling dielectric layer and simplifies the device fabrication process. Furthermore, the NFGM devices show excellent thermal stability, and flexible memory devices fabricated on plastic substrates exhibit remarkable mechanical and electrical stability. This study demonstrates a viable means of fabricating highly flexible, high-performance organic memory devices. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices

NASA Astrophysics Data System (ADS)

Yu, Jie; Chen, Kun-ji; Ma, Zhong-yuan; Zhang, Xin-xin; Jiang, Xiao-fan; Wu, Yang-qing; Huang, Xin-fan; Oda, Shunri

2016-09-01

Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V/1 ms, which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8 × 1011/cm2) of Si-NCs. The program/erase (P/E) speed characteristics are almost independent of gate widths and lengths. However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. Furthermore, the data retention characteristic is also independent of the gate area. Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration. Project supported by the State Key Development Program for Basic Research of China (Grant No. 2010CB934402) and the National Natural Science Foundation of China (Grant Nos. 11374153, 61571221, and 61071008).

Investing the effectiveness of retention performance in a non-volatile floating gate memory device with a core-shell structure of CdSe nanoparticles

NASA Astrophysics Data System (ADS)

Lee, Dong-Hoon; Kim, Jung-Min; Lim, Ki-Tae; Cho, Hyeong Jun; Bang, Jin Ho; Kim, Yong-Sang

2016-03-01

In this paper, we empirically investigate the retention performance of organic non-volatile floating gate memory devices with CdSe nanoparticles (NPs) as charge trapping elements. Core-structured CdSe NPs or core-shell-structured ZnS/CdSe NPs were mixed in PMMA and their performance in pentacene based device was compared. The NPs and self-organized thin tunneling PMMA inside the devices exhibited hysteresis by trapping hole during capacitance-voltage characterization. Despite of core-structured NPs showing a larger memory window, the retention time was too short to be adopted by an industry. By contrast core-shell structured NPs showed an improved retention time of >10000 seconds than core-structure NCs. Based on these results and the energy band structure, we propose the retention mechanism of each NPs. This investigation of retention performance provides a comparative and systematic study of the charging/discharging behaviors of NPs based memory devices. [Figure not available: see fulltext.

A Radiation-Tolerant, Low-Power Non-Volatile Memory Based on Silicon Nanocrystal Quantum Dots

NASA Technical Reports Server (NTRS)

Bell, L. D.; Boer, E. A.; Ostraat, M. L.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.; deBlauwe, J.; Green, M. L.

2001-01-01

Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO2 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled in program/erase threshold voltage swing was seen during 100,000 program and erase cycles. Additional near-term goals for this project include extensive testing for radiation hardness and the development of artificial layered tunnel barrier heterostructures which have the potential for large speed enhancements for read/write of nanocrystal memory elements, compared with conventional flash devices. Additional information is contained in the original extended abstract.

Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

NASA Astrophysics Data System (ADS)

Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

2018-04-01

In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

Non-Volatile High Speed & Low Power Charge Trapping Devices

NASA Astrophysics Data System (ADS)

Kim, Moon Kyung; Tiwari, Sandip

2007-06-01

We report the operational characteristics of ultra-small-scaled SONOS (below 50 nm gate width and length) and SiO2/SiO2 structural devices with 0.5 um gate width and length where trapping occurs in a very narrow region. The experimental work summarizes the memory characteristics of retention time, endurance cycles, and speed in SONOS and SiO2/SiO2 structures. Silicon nitride has many defects to hold electrons as charge storage media in SONOS memory. Defects are also incorporated during growth and deposition in device processing. Our experiments show that the interface between two oxides, one grown and one deposited, provides a remarkable media for electron storage with a smaller gate stack and thus lower operating voltage. The exponential dependence of the time on the voltage is reflected in the characteristic energy. It is ˜0.44 eV for the write process and ˜0.47 eV for the erase process in SiO2/SiO2 structural device which is somewhat more efficient than those of SONOS structure memory.

Technology breakthroughs in high performance metal-oxide-semiconductor devices for ultra-high density, low power non-volatile memory applications

NASA Astrophysics Data System (ADS)

Hong, Augustin Jinwoo

Non-volatile memory devices have attracted much attention because data can be retained without power consumption more than a decade. Therefore, non-volatile memory devices are essential to mobile electronic applications. Among state of the art non-volatile memory devices, NAND flash memory has earned the highest attention because of its ultra-high scalability and therefore its ultra-high storage capacity. However, human desire as well as market competition requires not only larger storage capacity but also lower power consumption for longer battery life time. One way to meet this human desire and extend the benefits of NAND flash memory is finding out new materials for storage layer inside the flash memory, which is called floating gate in the state of the art flash memory device. In this dissertation, we study new materials for the floating gate that can lower down the power consumption and increase the storage capacity at the same time. To this end, we employ various materials such as metal nanodot, metal thin film and graphene incorporating complementary-metal-oxide-semiconductor (CMOS) compatible processes. Experimental results show excellent memory effects at relatively low operating voltages. Detailed physics and analysis on experimental results are discussed. These new materials for data storage can be promising candidates for future non-volatile memory application beyond the state of the art flash technologies.

Memory and learning behaviors mimicked in nanogranular SiO2-based proton conductor gated oxide-based synaptic transistors

NASA Astrophysics Data System (ADS)

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2013-10-01

In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements.In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements. Electronic supplementary information (ESI) available. See DOI: 10.1039/c3nr02987e

Fabrication of arrayed Si nanowire-based nano-floating gate memory devices on flexible plastics.

PubMed

Yoon, Changjoon; Jeon, Youngin; Yun, Junggwon; Kim, Sangsig

2012-01-01

Arrayed Si nanowire (NW)-based nano-floating gate memory (NFGM) devices with Pt nanoparticles (NPs) embedded in Al2O3 gate layers are successfully constructed on flexible plastics by top-down approaches. Ten arrayed Si NW-based NFGM devices are positioned on the first level. Cross-linked poly-4-vinylphenol (PVP) layers are spin-coated on them as isolation layers between the first and second level, and another ten devices are stacked on the cross-linked PVP isolation layers. The electrical characteristics of the representative Si NW-based NFGM devices on the first and second levels exhibit threshold voltage shifts, indicating the trapping and detrapping of electrons in their NPs nodes. They have an average threshold voltage shift of 2.5 V with good retention times of more than 5 x 10(4) s. Moreover, most of the devices successfully retain their electrical characteristics after about one thousand bending cycles. These well-arrayed and stacked Si NW-based NFGM devices demonstrate the potential of nanowire-based devices for large-scale integration.

Thermally activated hysteresis in high quality graphene/h-BN devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cadore, A. R., E-mail: alissoncadore@gmail.com, E-mail: lccampos@fisica.ufmg.br; Mania, E.; Lacerda, R. G.

2016-06-06

We report on gate hysteresis of resistance in high quality graphene/hexagonal boron nitride (h-BN) devices. We observe a thermally activated hysteretic behavior in resistance as a function of the applied gate voltage at temperatures above 375 K. In order to investigate the origin of the hysteretic phenomenon, we compare graphene/h-BN heterostructure devices with SiO{sub 2}/Si back gate electrodes to devices with graphite back gate electrodes. The gate hysteretic behavior of the resistance is present only in devices with an h-BN/SiO{sub 2} interface and is dependent on the orientation of the applied gate electric field and sweep rate. We describe a phenomenologicalmore » model which captures all of our findings based on charges trapped at the h-BN/SiO{sub 2} interface. Such hysteretic behavior in graphene resistance must be considered in high temperature applications for graphene devices and may open new routes for applications in digital electronics and memory devices.« less

Ferroelectric FET for nonvolatile memory application with two-dimensional MoSe2 channels

NASA Astrophysics Data System (ADS)

Wang, Xudong; Liu, Chunsen; Chen, Yan; Wu, Guangjian; Yan, Xiao; Huang, Hai; Wang, Peng; Tian, Bobo; Hong, Zhenchen; Wang, Yutao; Sun, Shuo; Shen, Hong; Lin, Tie; Hu, Weida; Tang, Minghua; Zhou, Peng; Wang, Jianlu; Sun, Jinglan; Meng, Xiangjian; Chu, Junhao; Li, Zheng

2017-06-01

Graphene and other two-dimensional materials have received considerable attention regarding their potential applications in nano-electronics. Here, we report top-gate nonvolatile memory field-effect transistors (FETs) with different layers of MoSe2 nanosheets channel gated by ferroelectric film. The conventional gate dielectric of FETs was replaced by a ferroelectric thin film that provides a ferroelectric polarization electric field, and therefore defined as an Fe-FET where the poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) was used as the gate dielectric. Among the devices with MoSe2 channels of different thicknesses, the device with a single layer of MoSe2 exhibited a large hysteresis of electronic transport with an over 105 write/erase ratio, and displayed excellent retention and endurance performance. The possible mechanism of the device’s good properties was qualitatively analyzed using band theory. Additionally, a comprehensive study comparing the memory properties of MoSe2 channels of different thicknesses is presented. Increasing the numbers of MoSe2 layers was found to cause a reduced memory window. However, MoSe2 thickness of 5 nm yielded a write/erase ratio of more than 103. The results indicate that, based on a Fe-FET structure, the combination of two-dimensional semiconductors and organic ferroelectric gate dielectrics shows good promise for future applications in nonvolatile ferroelectric memory.

Fabrication of InGaZnO Nonvolatile Memory Devices at Low Temperature of 150 degrees C for Applications in Flexible Memory Displays and Transparency Coating on Plastic Substrates.

PubMed

Hanh, Nguyen Hong; Jang, Kyungsoo; Yi, Junsin

2016-05-01

We directly deposited amorphous InGaZnO (a-IGZO) nonvolatile memory (NVM) devices with oxynitride-oxide-dioxide (OOO) stack structures on plastic substrate by a DC pulsed magnetron sputtering and inductively coupled plasma chemical vapor deposition (ICPCVD) system, using a low-temperature of 150 degrees C. The fabricated bottom gate a-IGZO NVM devices have a wide memory window with a low operating voltage during programming and erasing, due to an effective control of the gate dielectrics. In addition, after ten years, the memory device retains a memory window of over 73%, with a programming duration of only 1 ms. Moreover, the a-IGZO films show high optical transmittance of over 85%, and good uniformity with a root mean square (RMS) roughness of 0.26 nm. This film is a promising candidate to achieve flexible displays and transparency on plastic substrates because of the possibility of low-temperature deposition, and the high transparent properties of a-IGZO films. These results demonstrate that the a-IGZO NVM devices obtained at low-temperature have a suitable programming and erasing efficiency for data storage under low-voltage conditions, in combination with excellent charge retention characteristics, and thus show great potential application in flexible memory displays.

Memory and Spin Injection Devices Involving Half Metals

DOE PAGES

Shaughnessy, M.; Snow, Ryan; Damewood, L.; ...

2011-01-01

We suggest memory and spin injection devices fabricated with half-metallic materials and based on the anomalous Hall effect. Schematic diagrams of the memory chips, in thin film and bulk crystal form, are presented. Spin injection devices made in thin film form are also suggested. These devices do not need any external magnetic field but make use of their own magnetization. Only a gate voltage is needed. The carriers are 100% spin polarized. Memory devices may potentially be smaller, faster, and less volatile than existing ones, and the injection devices may be much smaller and more efficient than existing spin injectionmore » devices.« less

Nonvolatile memory with graphene oxide as a charge storage node in nanowire field-effect transistors

NASA Astrophysics Data System (ADS)

Baek, David J.; Seol, Myeong-Lok; Choi, Sung-Jin; Moon, Dong-Il; Choi, Yang-Kyu

2012-02-01

Through the structural modification of a three-dimensional silicon nanowire field-effect transistor, i.e., a double-gate FinFET, a structural platform was developed which allowed for us to utilize graphene oxide (GO) as a charge trapping layer in a nonvolatile memory device. By creating a nanogap between the gate and the channel, GO was embedded after the complete device fabrication. By applying a proper gate voltage, charge trapping, and de-trapping within the GO was enabled and resulted in large threshold voltage shifts. The employment of GO with FinFET in our work suggests that graphitic materials can potentially play a significant role for future nanoelectronic applications.

Endurance degradation and lifetime model of p-channel floating gate flash memory device with 2T structure

NASA Astrophysics Data System (ADS)

Wei, Jiaxing; Liu, Siyang; Liu, Xiaoqiang; Sun, Weifeng; Liu, Yuwei; Liu, Xiaohong; Hou, Bo

2017-08-01

The endurance degradation mechanisms of p-channel floating gate flash memory device with two-transistor (2T) structure are investigated in detail in this work. With the help of charge pumping (CP) measurements and Sentaurus TCAD simulations, the damages in the drain overlap region along the tunnel oxide interface caused by band-to-band (BTB) tunneling programming and the damages in the channel region resulted from Fowler-Nordheim (FN) tunneling erasure are verified respectively. Furthermore, the lifetime model of endurance characteristic is extracted, which can extrapolate the endurance degradation tendency and predict the lifetime of the device.

Multilevel non-volatile data storage utilizing common current hysteresis of networked single walled carbon nanotubes

NASA Astrophysics Data System (ADS)

Hwang, Ihn; Wang, Wei; Hwang, Sun Kak; Cho, Sung Hwan; Kim, Kang Lib; Jeong, Beomjin; Huh, June; Park, Cheolmin

2016-05-01

The characteristic source-drain current hysteresis frequently observed in field-effect transistors with networked single walled carbon-nanotube (NSWNT) channels is problematic for the reliable switching and sensing performance of devices. But the two distinct current states of the hysteresis curve at a zero gate voltage can be useful for memory applications. In this work, we demonstrate a novel non-volatile transistor memory with solution-processed NSWNTs which are suitable for multilevel data programming and reading. A polymer passivation layer with a small amount of water employed on the top of the NSWNT channel serves as an efficient gate voltage dependent charge trapping and de-trapping site. A systematic investigation evidences that the water mixed in a polymer passivation solution is critical for reliable non-volatile memory operation. The optimized device is air-stable and temperature-resistive up to 80 °C and exhibits excellent non-volatile memory performance with an on/off current ratio greater than 104, a switching time less than 100 ms, data retention longer than 4000 s, and write/read endurance over 100 cycles. Furthermore, the gate voltage dependent charge injection mediated by water in the passivation layer allowed for multilevel operation of our memory in which 4 distinct current states were programmed repetitively and preserved over a long time period.The characteristic source-drain current hysteresis frequently observed in field-effect transistors with networked single walled carbon-nanotube (NSWNT) channels is problematic for the reliable switching and sensing performance of devices. But the two distinct current states of the hysteresis curve at a zero gate voltage can be useful for memory applications. In this work, we demonstrate a novel non-volatile transistor memory with solution-processed NSWNTs which are suitable for multilevel data programming and reading. A polymer passivation layer with a small amount of water employed on the top of the NSWNT channel serves as an efficient gate voltage dependent charge trapping and de-trapping site. A systematic investigation evidences that the water mixed in a polymer passivation solution is critical for reliable non-volatile memory operation. The optimized device is air-stable and temperature-resistive up to 80 °C and exhibits excellent non-volatile memory performance with an on/off current ratio greater than 104, a switching time less than 100 ms, data retention longer than 4000 s, and write/read endurance over 100 cycles. Furthermore, the gate voltage dependent charge injection mediated by water in the passivation layer allowed for multilevel operation of our memory in which 4 distinct current states were programmed repetitively and preserved over a long time period. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr00505e

Stretchable carbon nanotube charge-trap floating-gate memory and logic devices for wearable electronics.

PubMed

Son, Donghee; Koo, Ja Hoon; Song, Jun-Kyul; Kim, Jaemin; Lee, Mincheol; Shim, Hyung Joon; Park, Minjoon; Lee, Minbaek; Kim, Ji Hoon; Kim, Dae-Hyeong

2015-05-26

Electronics for wearable applications require soft, flexible, and stretchable materials and designs to overcome the mechanical mismatch between the human body and devices. A key requirement for such wearable electronics is reliable operation with high performance and robustness during various deformations induced by motions. Here, we present materials and device design strategies for the core elements of wearable electronics, such as transistors, charge-trap floating-gate memory units, and various logic gates, with stretchable form factors. The use of semiconducting carbon nanotube networks designed for integration with charge traps and ultrathin dielectric layers meets the performance requirements as well as reliability, proven by detailed material and electrical characterizations using statistics. Serpentine interconnections and neutral mechanical plane layouts further enhance the deformability required for skin-based systems. Repetitive stretching tests and studies in mechanics corroborate the validity of the current approaches.

Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

PubMed

Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

2015-03-04

Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

Wide memory window in graphene oxide charge storage nodes

NASA Astrophysics Data System (ADS)

Wang, Shuai; Pu, Jing; Chan, Daniel S. H.; Cho, Byung Jin; Loh, Kian Ping

2010-04-01

Solution-processable, isolated graphene oxide (GO) monolayers have been used as a charge trapping dielectric in TaN gate/Al2O3/isolated GO sheets/SiO2/p-Si memory device (TANOS). The TANOS type structure serves as memory device with the threshold voltage controlled by the amount of charge trapped in the GO sheet. Capacitance-Voltage hysteresis curves reveal a 7.5 V memory window using the sweep voltage of -5-14 V. Thermal reduction in the GO to graphene reduces the memory window to 1.4 V. The unique charge trapping properties of GO points to the potential applications in flexible organic memory devices.

Nanogranular SiO2 proton gated silicon layer transistor mimicking biological synapses

NASA Astrophysics Data System (ADS)

Liu, M. J.; Huang, G. S.; Feng, P.; Guo, Q. L.; Shao, F.; Tian, Z. A.; Li, G. J.; Wan, Q.; Mei, Y. F.

2016-06-01

Silicon on insulator (SOI)-based transistors gated by nanogranular SiO2 proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

Virtex-5QV Self Scrubber

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wojahn, Christopher K.

2015-10-20

This HDL code (hereafter referred to as "software") implements circuitry in Xilinx Virtex-5QV Field Programmable Gate Array (FPGA) hardware. This software allows the device to self-check the consistency of its own configuration memory for radiation-induced errors. The software then provides the capability to correct any single-bit errors detected in the memory using the device's inherent circuitry, or reload corrupted memory frames when larger errors occur that cannot be corrected with the device's built-in error correction and detection scheme.

Skyrmion-based multi-channel racetrack

NASA Astrophysics Data System (ADS)

Song, Chengkun; Jin, Chendong; Wang, Jinshuai; Xia, Haiyan; Wang, Jianbo; Liu, Qingfang

2017-11-01

Magnetic skyrmions are promising for the application of racetrack memories, logic gates, and other nano-devices, owing to their topologically protected stability, small size, and low driving current. In this work, we propose a skyrmion-based multi-channel racetrack memory where the skyrmion moves in the selected channel by applying voltage-controlled magnetic anisotropy gates. It is demonstrated numerically that a current-dependent skyrmion Hall effect can be restrained by the additional potential of the voltage-controlled region, and the skyrmion velocity and moving channel in the racetrack can be operated by tuning the voltage-controlled magnetic anisotropy, gate position, and current density. Our results offer a potential application of racetrack memory based on skyrmions.

Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations

NASA Astrophysics Data System (ADS)

Chambonneau, Maxime; Souiki-Figuigui, Sarra; Chiquet, Philippe; Della Marca, Vincenzo; Postel-Pellerin, Jérémy; Canet, Pierre; Portal, Jean-Michel; Grojo, David

2017-04-01

We demonstrate that infrared femtosecond laser pulses with intensity above the two-photon ionization threshold of crystalline silicon induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor transistor devices. With repeated irradiations of Flash memory cells, we show how the laser-produced free-electrons naturally redistribute on both sides of the tunnel oxide until the electric field of the transistor is suppressed. This ability enables us to determine in a nondestructive, rapid and contactless way the flat band and the neutral threshold voltages of the tested device. The physical mechanisms including nonlinear ionization, quantum tunneling of free-carriers, and flattening of the band diagram are discussed for interpreting the experiments. The possibility to control the carriers in memory transistors with ultrashort pulses holds promises for fast and remote device analyses (reliability, security, and defectivity) and for considerable developments in the growing field of ultrafast microelectronics.

Resonant tunneling based graphene quantum dot memristors.

PubMed

Pan, Xuan; Skafidas, Efstratios

2016-12-08

In this paper, we model two-terminal all graphene quantum dot (GQD) based resistor-type memory devices (memristors). The resistive switching is achieved by resonant electron tunneling. We show that parallel GQDs can be used to create multi-state memory circuits. The number of states can be optimised with additional voltage sources, whilst the noise margin for each state can be controlled by appropriately choosing the branch resistance. A three-terminal GQD device configuration is also studied. The addition of an isolated gate terminal can be used to add further or modify the states of the memory device. The proposed devices provide a promising route towards volatile memory devices utilizing only atomically thin two-dimensional graphene.

Dependence of Grain Size on the Performance of a Polysilicon Channel TFT for 3D NAND Flash Memory.

PubMed

Kim, Seung-Yoon; Park, Jong Kyung; Hwang, Wan Sik; Lee, Seung-Jun; Lee, Ki-Hong; Pyi, Seung Ho; Cho, Byung Jin

2016-05-01

We investigated the dependence of grain size on the performance of a polycrystalline silicon (poly-Si) channel TFT for application to 3D NAND Flash memory devices. It has been found that the device performance and memory characteristics are strongly affected by the grain size of the poly-Si channel. Higher on-state current, faster program speed, and poor endurance/reliability properties are observed when the poly-Si grain size is large. These are mainly attributed to the different local electric field induced by an oxide valley at the interface between the poly-Si channel and the gate oxide. In addition, the trap density at the gate oxide interface was successfully measured using a charge pumping method by the separation between the gate oxide interface traps and traps at the grain boundaries in the poly-Si channel. The poly-Si channel with larger grain size has lower interface trap density.

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

DOEpatents

Asaad, Sameh W.; Kapur, Mohit

2016-03-15

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

Floating-gate memory based on an organic metal-insulator-semiconductor capacitor

NASA Astrophysics Data System (ADS)

William, S.; Mabrook, M. F.; Taylor, D. M.

2009-08-01

A floating gate memory element is described which incorporates an evaporated gold film embedded in the gate dielectric of a metal-insulator-semiconductor capacitor based on poly(3-hexylthiophene). On exceeding a critical amplitude in the voltage sweep, hysteresis is observed in the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of the device. The anticlockwise hysteresis in C-V is consistent with strong electron trapping during the positive cycle but little hole trapping during the negative cycle. We argue that the clockwise hysteresis observed in the negative cycle of the I-V plot, arises from leakage of trapped holes through the underlying insulator to the control gate.

Random Telegraph Signal-Like Fluctuation Created by Fowler-Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

NASA Astrophysics Data System (ADS)

Kim, Heesang; Oh, Byoungchan; Kim, Kyungdo; Cha, Seon-Yong; Jeong, Jae-Goan; Hong, Sung-Joo; Lee, Jong-Ho; Park, Byung-Gook; Shin, Hyungcheol

2010-09-01

We generated traps inside gate oxide in gate-drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler-Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal-oxide-semiconductor field-effect transistors (MOSFETs).

Titanium-tungsten nanocrystals embedded in a SiO(2)/Al(2)O(3) gate dielectric stack for low-voltage operation in non-volatile memory.

PubMed

Yang, Shiqian; Wang, Qin; Zhang, Manhong; Long, Shibing; Liu, Jing; Liu, Ming

2010-06-18

Titanium-tungsten nanocrystals (NCs) were fabricated by a self-assembly rapid thermal annealing (RTA) process. Well isolated Ti(0.46)W(0.54) NCs were embedded in the gate dielectric stack of SiO(2)/Al(2)O(3). A metal-oxide-semiconductor (MOS) capacitor was fabricated to investigate its application in a non-volatile memory (NVM) device. It demonstrated a large memory window of 6.2 V in terms of flat-band voltage (V(FB)) shift under a dual-directional sweeping gate voltage of - 10 to 10 V. A 1.1 V V(FB) shift under a low dual-directional sweeping gate voltage of - 4 to 4 V was also observed. The retention characteristic of this MOS capacitor was demonstrated by a 0.5 V memory window after 10(4) s of elapsed time at room temperature. The endurance characteristic was demonstrated by a program/erase cycling test.

Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Shun; Gao, Xu, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn; Zhong, Ya-Nan

High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio andmore » good memory retention.« less

Artificial neuron synapse transistor based on silicon nanomembrane on plastic substrate

NASA Astrophysics Data System (ADS)

Liu, Minjie; Huang, Gaoshan; Feng, Ping; Guo, Qinglei; Shao, Feng; Tian, Ziao; Li, Gongjin; Wan, Qing; Mei, Yongfeng

2017-06-01

Silicon nanomembrane (SiNM) transistors gated by chitosan membrane were fabricated on plastic substrate to mimic synapse behaviors. The device has both a bottom proton gate (BG) and multiple side gates (SG). Electrical transfer properties of BG show hysteresis curves different from those of typical SiO2 gate dielectric. Synaptic behaviors and functions by linear accumulation and release of protons have been mimicked on this device: excitatory post-synaptic current (EPSC) and paired pulse facilitation behavior of biological synapses were mimicked and the paired-pulse facilitation index could be effectively tuned by the spike interval applied on the BG. Synaptic behaviors and functions, including short-term memory and long-term memory, were also experimentally demonstrated in BG mode. Meanwhile, spiking logic operation and logic modulation were realized in SG mode. Project supported by the National Natural Science Foundation of China (No. 51322201), the Specialized Research Fund for the Doctoral Program of Higher Education (No. 20120071110025), and Science and Technology Commission of Shanghai Municipality (No. 14JC1400200).

Fabrication and electrical characterization of a MOS memory device containing self-assembled metallic nanoparticles

NASA Astrophysics Data System (ADS)

Sargentis, Ch.; Giannakopoulos, K.; Travlos, A.; Tsamakis, D.

2007-04-01

Floating gate devices with nanoparticles embedded in dielectrics have recently attracted much attention due to the fact that these devices operate as non-volatile memories with high speed, high density and low power consumption. In this paper, memory devices containing gold (Au) nanoparticles have been fabricated using e-gun evaporation. The Au nanoparticles are deposited on a very thin SiO 2 layer and are then fully covered by a HfO 2 layer. The HfO 2 is a high- k dielectric and gives good scalability to the fabricated devices. We studied the effect of the deposition parameters to the size and the shape of the Au nanoparticles using capacitance-voltage and conductance-voltage measurements, we demonstrated that the fabricated device can indeed operate as a low-voltage memory device.

Synthesizing Biomolecule-based Boolean Logic Gates

PubMed Central

Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

2012-01-01

One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications. PMID:23526588

Synthesizing biomolecule-based Boolean logic gates.

PubMed

Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

2013-02-15

One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, and hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications.

Analogue spin-orbit torque device for artificial-neural-network-based associative memory operation

NASA Astrophysics Data System (ADS)

Borders, William A.; Akima, Hisanao; Fukami, Shunsuke; Moriya, Satoshi; Kurihara, Shouta; Horio, Yoshihiko; Sato, Shigeo; Ohno, Hideo

2017-01-01

We demonstrate associative memory operations reminiscent of the brain using nonvolatile spintronics devices. Antiferromagnet-ferromagnet bilayer-based Hall devices, which show analogue-like spin-orbit torque switching under zero magnetic fields and behave as artificial synapses, are used. An artificial neural network is used to associate memorized patterns from their noisy versions. We develop a network consisting of a field-programmable gate array and 36 spin-orbit torque devices. An effect of learning on associative memory operations is successfully confirmed for several 3 × 3-block patterns. A discussion on the present approach for realizing spintronics-based artificial intelligence is given.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Light-Gated Memristor with Integrated Logic and Memory Functions.

PubMed

Tan, Hongwei; Liu, Gang; Yang, Huali; Yi, Xiaohui; Pan, Liang; Shang, Jie; Long, Shibing; Liu, Ming; Wu, Yihong; Li, Run-Wei

2017-11-28

Memristive devices are able to store and process information, which offers several key advantages over the transistor-based architectures. However, most of the two-terminal memristive devices have fixed functions once made and cannot be reconfigured for other situations. Here, we propose and demonstrate a memristive device "memlogic" (memory logic) as a nonvolatile switch of logic operations integrated with memory function in a single light-gated memristor. Based on nonvolatile light-modulated memristive switching behavior, a single memlogic cell is able to achieve optical and electrical mixed basic Boolean logic of reconfigurable "AND", "OR", and "NOT" operations. Furthermore, the single memlogic cell is also capable of functioning as an optical adder and digital-to-analog converter. All the memlogic outputs are memristive for in situ data storage due to the nonvolatile resistive switching and persistent photoconductivity effects. Thus, as a memdevice, the memlogic has potential for not only simplifying the programmable logic circuits but also building memristive multifunctional optoelectronics.

A SONOS device with a separated charge trapping layer for improvement of charge injection

NASA Astrophysics Data System (ADS)

Ahn, Jae-Hyuk; Moon, Dong-Il; Ko, Seung-Won; Kim, Chang-Hoon; Kim, Jee-Yeon; Kim, Moon-Seok; Seol, Myeong-Lok; Moon, Joon-Bae; Choi, Ji-Min; Oh, Jae-Sub; Choi, Sung-Jin; Choi, Yang-Kyu

2017-03-01

A charge trapping layer that is separated from the primary gate dielectric is implemented on a FinFET SONOS structure. By virtue of the reduced effective oxide thickness of the primary gate dielectric, a strong gate-to-channel coupling is obtained and thus short-channel effects in the proposed device are effectively suppressed. Moreover, a high program/erase speed and a large shift in the threshold voltage are achieved due to the improved charge injection by the reduced effective oxide thickness. The proposed structure has potential for use in high speed flash memory.

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

NASA Astrophysics Data System (ADS)

Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

2018-06-01

The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

Low-voltage all-inorganic perovskite quantum dot transistor memory

NASA Astrophysics Data System (ADS)

Chen, Zhiliang; Zhang, Yating; Zhang, Heng; Yu, Yu; Song, Xiaoxian; Zhang, Haiting; Cao, Mingxuan; Che, Yongli; Jin, Lufan; Li, Yifan; Li, Qingyan; Dai, Haitao; Yang, Junbo; Yao, Jianquan

2018-05-01

An all-inorganic cesium lead halide quantum dot (QD) based Au nanoparticle (NP) floating-gate memory with a solution processed layer-by-layer method is demonstrated. Easy synthesis at room temperature and excellent stability make all-inorganic CsPbBr3 perovskite QDs suitable as a semiconductor layer in low voltage nonvolatile transistor memory. The bipolarity of QDs has both electrons and holes stored in the Au NP floating gate, resulting in bidirectional shifts of initial threshold voltage according to the applied programing and erasing pulses. Under low operation voltage (±5 V), the memory achieved a great memory window (˜2.4 V), long retention time (>105 s), and stable endurance properties after 200 cycles. So the proposed memory device based on CsPbBr3 perovskite QDs has a great potential in the flash memory market.

Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window

NASA Astrophysics Data System (ADS)

Kino, Hisashi; Fukushima, Takafumi; Tanaka, Tetsu

2018-04-01

Charge-trapping memory requires the increase of bit density per cell and a larger memory window for lower-power operation. A tunnel field-effect transistor (TFET) can achieve to increase the bit density per cell owing to its steep subthreshold slope. In addition, a TFET structure has an asymmetric structure, which is promising for achieving a larger memory window. A TFET with the N-type gate shows a higher electric field between the P-type source and the N-type gate edge than the conventional FET structure. This high electric field enables large amounts of charges to be injected into the charge storage layer. In this study, we fabricated silicon-oxide-nitride-oxide-semiconductor (SONOS) memory devices with the TFET structure and observed a steep subthreshold slope and a larger memory window.

Operation of a quantum dot in the finite-state machine mode: Single-electron dynamic memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Klymenko, M. V.; Klein, M.; Levine, R. D.

2016-07-14

A single electron dynamic memory is designed based on the non-equilibrium dynamics of charge states in electrostatically defined metallic quantum dots. Using the orthodox theory for computing the transfer rates and a master equation, we model the dynamical response of devices consisting of a charge sensor coupled to either a single and or a double quantum dot subjected to a pulsed gate voltage. We show that transition rates between charge states in metallic quantum dots are characterized by an asymmetry that can be controlled by the gate voltage. This effect is more pronounced when the switching between charge states correspondsmore » to a Markovian process involving electron transport through a chain of several quantum dots. By simulating the dynamics of electron transport we demonstrate that the quantum box operates as a finite-state machine that can be addressed by choosing suitable shapes and switching rates of the gate pulses. We further show that writing times in the ns range and retention memory times six orders of magnitude longer, in the ms range, can be achieved on the double quantum dot system using experimentally feasible parameters, thereby demonstrating that the device can operate as a dynamic single electron memory.« less

Recent Advances of Flexible Data Storage Devices Based on Organic Nanoscaled Materials.

PubMed

Zhou, Li; Mao, Jingyu; Ren, Yi; Han, Su-Ting; Roy, Vellaisamy A L; Zhou, Ye

2018-03-01

Following the trend of miniaturization as per Moore's law, and facing the strong demand of next-generation electronic devices that should be highly portable, wearable, transplantable, and lightweight, growing endeavors have been made to develop novel flexible data storage devices possessing nonvolatile ability, high-density storage, high-switching speed, and reliable endurance properties. Nonvolatile organic data storage devices including memory devices on the basis of floating-gate, charge-trapping, and ferroelectric architectures, as well as organic resistive memory are believed to be favorable candidates for future data storage applications. In this Review, typical information on device structure, memory characteristics, device operation mechanisms, mechanical properties, challenges, and recent progress of the above categories of flexible data storage devices based on organic nanoscaled materials is summarized. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Models for Total-Dose Radiation Effects in Non-Volatile Memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Campbell, Philip Montgomery; Wix, Steven D.

The objective of this work is to develop models to predict radiation effects in non- volatile memory: flash memory and ferroelectric RAM. In flash memory experiments have found that the internal high-voltage generators (charge pumps) are the most sensitive to radiation damage. Models are presented for radiation effects in charge pumps that demonstrate the experimental results. Floating gate models are developed for the memory cell in two types of flash memory devices by Intel and Samsung. These models utilize Fowler-Nordheim tunneling and hot electron injection to charge and erase the floating gate. Erase times are calculated from the models andmore » compared with experimental results for different radiation doses. FRAM is less sensitive to radiation than flash memory, but measurements show that above 100 Krad FRAM suffers from a large increase in leakage current. A model for this effect is developed which compares closely with the measurements.« less

Upsets in Erased Floating Gate Cells With High-Energy Protons

DOE PAGES

Gerardin, S.; Bagatin, M.; Paccagnella, A.; ...

2017-01-01

We discuss upsets in erased floating gate cells, due to large threshold voltage shifts, using statistical distributions collected on a large number of memory cells. The spread in the neutral threshold voltage appears to be too low to quantitatively explain the experimental observations in terms of simple charge loss, at least in SLC devices. The possibility that memories exposed to high energy protons and heavy ions exhibit negative charge transfer between programmed and erased cells is investigated, although the analysis does not provide conclusive support to this hypothesis.

MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

NASA Astrophysics Data System (ADS)

Riggert, C.; Ziegler, M.; Schroeder, D.; Krautschneider, W. H.; Kohlstedt, H.

2014-10-01

Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit.

Memory Device and Nanofabrication Techniques Using Electrically Configurable Materials

NASA Astrophysics Data System (ADS)

Ascenso Simões, Bruno

Development of novel nanofabrication techniques and single-walled carbon nanotubes field configurable transistor (SWCNT-FCT) memory devices using electrically configurable materials is presented. A novel lithographic technique, electric lithography (EL), that uses electric field for pattern generation has been demonstrated. It can be used for patterning of biomolecules on a polymer surface and patterning of resist as well. Using electrical resist composed of a polymer having Boc protected amine group and iodonium salt, Boc group on the surface of polymer was modified to free amine by applying an electric field. On the modified surface of the polymer, Streptavidin pattern was fabricated with a sub-micron scale. Also patterning of polymer resin composed of epoxy monomers and diaryl iodonium salt by EL has been demonstrated. Reaction mechanism for electric resist configuration is believed to be induced by an acid generation via electrochemical reduction in the resist. We show a novel field configurable transistor (FCT) based on single-walled carbon nanotube network field-effect transistors in which poly (ethylene glycol) crosslinked by electron-beam is incorporated into the gate. The device conductance can be configured to arbitrary states reversibly and repeatedly by applying external gate voltages. Raman spectroscopy revealed that evolution of the ratio of D- to G-band intensity in the SWCNTs of the FCT progressively increases as the device is configured to lower conductance states. Electron transport studies at low temperatures showed a strong temperature dependence of the resistance. Band gap widening of CNTs up to ˜ 4 eV has been observed by examining the differential conductance-gate voltage-bias voltage relationship. The switching mechanism of the FCT is attributed a structural transformation of CNTs via reversible hydrogenation and dehydrogenations induced by gate voltages, which tunes the CNT bandgap continuously and reversibly to non-volatile analog values. The CNT transistors with field tunable band gaps would facilitate field programmable circuits based on the self-organized CNTs, and might also lead to novel analog memory, neuromorphic, and photonic devices.

A nanocryotron comparator can connect single-flux-quantum circuits to conventional electronics

NASA Astrophysics Data System (ADS)

Zhao, Qing-Yuan; McCaughan, Adam N.; Dane, Andrew E.; Berggren, Karl K.; Ortlepp, Thomas

2017-04-01

Integration with conventional electronics offers a straightforward and economical approach to upgrading existing superconducting technologies, such as scaling up superconducting detectors into large arrays and combining single flux quantum (SFQ) digital circuits with semiconductor logic gates and memories. However, direct output signals from superconducting devices (e.g., Josephson junctions) are usually not compatible with the input requirements of conventional devices (e.g., transistors). Here, we demonstrate the use of a single three-terminal superconducting-nanowire device, called the nanocryotron (nTron), as a digital comparator to combine SFQ circuits with mature semiconductor circuits such as complementary metal oxide semiconductor (CMOS) circuits. Since SFQ circuits can digitize output signals from general superconducting devices and CMOS circuits can interface existing CMOS-compatible electronics, our results demonstrate the feasibility of a general architecture that uses an nTron as an interface to realize a ‘super-hybrid’ system consisting of superconducting detectors, superconducting quantum electronics, CMOS logic gates and memories, and other conventional electronics.

In-situ, In-Memory Stateful Vector Logic Operations based on Voltage Controlled Magnetic Anisotropy.

PubMed

Jaiswal, Akhilesh; Agrawal, Amogh; Roy, Kaushik

2018-04-10

Recently, the exponential increase in compute requirements demanded by emerging applications like artificial intelligence, Internet of things, etc. have rendered the state-of-art von-Neumann machines inefficient in terms of energy and throughput owing to the well-known von-Neumann bottleneck. A promising approach to mitigate the bottleneck is to do computations as close to the memory units as possible. One extreme possibility is to do in-situ Boolean logic computations by using stateful devices. Stateful devices are those that can act both as a compute engine and storage device, simultaneously. We propose such stateful, vector, in-memory operations using voltage controlled magnetic anisotropy (VCMA) effect in magnetic tunnel junctions (MTJ). Our proposal is based on the well known manufacturable 1-transistor - 1-MTJ bit-cell and does not require any modifications in the bit-cell circuit or the magnetic device. Instead, we leverage the very physics of the VCMA effect to enable stateful computations. Specifically, we exploit the voltage asymmetry of the VCMA effect to construct stateful IMP (implication) gate and use the precessional switching dynamics of the VCMA devices to propose a massively parallel NOT operation. Further, we show that other gates like AND, OR, NAND, NOR, NIMP (complement of implication) can be implemented using multi-cycle operations.

Optimization of pentacene double floating gate memories based on charge injection regulated by SAM functionalization

NASA Astrophysics Data System (ADS)

Li, S.; Guérin, D.; Lenfant, S.; Lmimouni, K.

2018-02-01

Pentacene based double nano-floating gate memories (NFGM) by using gold nanoparticles (Au NPs) and reduced graphene oxide (rGO) sheets as charge trapping layers are prepared and demonstrated. Particularly, the NFGM chemically treated by 2,3,4,5,6-pentafluorobenzenethiol (PFBT) self-assembled monolayers (SAM) exhibits excellent memory performances, including high mobility of 0.23 cm2V-1s-1, the large memory window of 51 V, and the stable retention property more than 108 s. Comparing the performances of NFGM without treating with PFBT SAM, the improving performances of the memory devices by SAM modification are explained by the increase of charge injection, which could be further investigated by XPS and UPS. In particular, the results highlight the utility of SAM modulations and controlling of charge transport in the development of organic transistor memories.

Ionic Liquid Gating Control of Spin Reorientation Transition and Switching of Perpendicular Magnetic Anisotropy.

PubMed

Zhao, Shishun; Wang, Lei; Zhou, Ziyao; Li, Chunlei; Dong, Guohua; Zhang, Le; Peng, Bin; Min, Tai; Hu, Zhongqiang; Ma, Jing; Ren, Wei; Ye, Zuo-Guang; Chen, Wei; Yu, Pu; Nan, Ce-Wen; Liu, Ming

2018-05-29

Electric field (E-field) modulation of perpendicular magnetic anisotropy (PMA) switching, in an energy-efficient manner, is of great potential to realize magnetoelectric (ME) memories and other ME devices. Voltage control of the spin-reorientation transition (SRT) that allows the magnetic moment rotating between the out-of-plane and the in-plane direction is thereby crucial. In this work, a remarkable magnetic anisotropy field change up to 1572 Oe is achieved under a small operation voltage of 4 V through ionic liquid (IL) gating control of SRT in Au/[DEME] + [TFSI] - /Pt/(Co/Pt) 2 /Ta capacitor heterostructures at room temperature, corresponding to a large ME coefficient of 378 Oe V -1 . As revealed by both ferromagnetic resonance measurements and magnetic domain evolution observation, the magnetization can be switched stably and reversibly between the out-of-plane and in-plane directions via IL gating. The key mechanism, revealed by the first-principles calculation, is that the IL gating process influences the interfacial spin-orbital coupling as well as net Rashba magnetic field between the Co and Pt layers, resulting in the modulation of the SRT and in-plane/out-of-plane magnetization switching. This work demonstrates a unique IL-gated PMA with large ME tunability and paves a way toward IL gating spintronic/electronic devices such as voltage tunable PMA memories. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Development of non-volatile semiconductor memory

NASA Technical Reports Server (NTRS)

Heikkila, W. W.

1979-01-01

A 256 word by 8-bit random access memory chip was developed utilizing p channel, metal gate metal-nitride-oxide-silicon (MNOS) technology; with operational characteristics of a 2.5 microsecond read cycle, a 6.0 microsecond write cycle, 800 milliwatts of power dissipation; and retention characteristics of 10 to the 8th power read cycles before data refresh and 5000 hours of no power retention. Design changes were implemented to reduce switching currents that caused parasitic bipolar transistors inherent in the MNOS structure to turn on. Final wafer runs exhibited acceptable yields for a die 250 mils on a side. Evaluation testing was performed on the device in order to determine the maturity of the device. A fixed gate breakdown mechanism was found when operated continuously at high temperature.

Nonvolatile gate effect in a ferroelectric-semiconductor quantum well.

PubMed

Stolichnov, Igor; Colla, Enrico; Setter, Nava; Wojciechowski, Tomasz; Janik, Elzbieta; Karczewski, Grzegorz

2006-12-15

Field effect transistors with ferroelectric gates would make ideal rewritable nonvolatile memories were it not for the severe problems in integrating the ferroelectric oxide directly on the semiconductor channel. We propose a powerful way to avoid these problems using a gate material that is ferroelectric and semiconducting simultaneously. First, ferroelectricity in semiconductor (Cd,Zn)Te films is proven and studied using modified piezoforce scanning probe microscopy. Then, a rewritable field effect device is demonstrated by local poling of the (Cd,Zn)Te layer of a (Cd,Zn)Te/CdTe quantum well, provoking a reversible, nonvolatile change in the resistance of the 2D electron gas. The results point to a potential new family of nanoscale one-transistor memories.

Computing with volatile memristors: an application of non-pinched hysteresis

NASA Astrophysics Data System (ADS)

Pershin, Y. V.; Shevchenko, S. N.

2017-02-01

The possibility of in-memory computing with volatile memristive devices, namely, memristors requiring a power source to sustain their memory, is demonstrated theoretically. We have adopted a hysteretic graphene-based field emission structure as a prototype of a volatile memristor, which is characterized by a non-pinched hysteresis loop. A memristive model of the structure is developed and used to simulate a polymorphic circuit implementing stateful logic gates, such as the material implication. Specific regions of parameter space realizing useful logic functions are identified. Our results are applicable to other realizations of volatile memory devices, such as certain NEMS switches.

Logic and memory concepts for all-magnetic computing based on transverse domain walls

NASA Astrophysics Data System (ADS)

Vandermeulen, J.; Van de Wiele, B.; Dupré, L.; Van Waeyenberge, B.

2015-06-01

We introduce a non-volatile digital logic and memory concept in which the binary data is stored in the transverse magnetic domain walls present in in-plane magnetized nanowires with sufficiently small cross sectional dimensions. We assign the digital bit to the two possible orientations of the transverse domain wall. Numerical proofs-of-concept are presented for a NOT-, AND- and OR-gate, a FAN-out as well as a reading and writing device. Contrary to the chirality based vortex domain wall logic gates introduced in Omari and Hayward (2014 Phys. Rev. Appl. 2 044001), the presented concepts remain applicable when miniaturized and are driven by electrical currents, making the technology compatible with the in-plane racetrack memory concept. The individual devices can be easily combined to logic networks working with clock speeds that scale linearly with decreasing design dimensions. This opens opportunities to an all-magnetic computing technology where the digital data is stored and processed under the same magnetic representation.

Logic gates realized by nonvolatile GeTe/Sb2Te3 super lattice phase-change memory with a magnetic field input

NASA Astrophysics Data System (ADS)

Lu, Bin; Cheng, Xiaomin; Feng, Jinlong; Guan, Xiawei; Miao, Xiangshui

2016-07-01

Nonvolatile memory devices or circuits that can implement both storage and calculation are a crucial requirement for the efficiency improvement of modern computer. In this work, we realize logic functions by using [GeTe/Sb2Te3]n super lattice phase change memory (PCM) cell in which higher threshold voltage is needed for phase change with a magnetic field applied. First, the [GeTe/Sb2Te3]n super lattice cells were fabricated and the R-V curve was measured. Then we designed the logic circuits with the super lattice PCM cell verified by HSPICE simulation and experiments. Seven basic logic functions are first demonstrated in this letter; then several multi-input logic gates are presented. The proposed logic devices offer the advantages of simple structures and low power consumption, indicating that the super lattice PCM has the potential in the future nonvolatile central processing unit design, facilitating the development of massive parallel computing architecture.

Nonvolatile memory thin film transistors using CdSe/ZnS quantum dot-poly(methyl methacrylate) composite layer formed by a two-step spin coating technique

NASA Astrophysics Data System (ADS)

Chen, Ying-Chih; Huang, Chun-Yuan; Yu, Hsin-Chieh; Su, Yan-Kuin

2012-08-01

The nonvolatile memory thin film transistors (TFTs) using a core/shell CdSe/ZnS quantum dot (QD)-poly(methyl methacrylate) (PMMA) composite layer as the floating gate have been demonstrated, with the device configuration of n+-Si gate/SiO2 insulator/QD-PMMA composite layer/pentacene channel/Au source-drain being proposed. To achieve the QD-PMMA composite layer, a two-step spin coating technique was used to successively deposit QD-PMMA composite and PMMA on the insulator. After the processes, the variation of crystal quality and surface morphology of the subsequent pentacene films characterized by x-ray diffraction spectra and atomic force microscopy was correlated to the two-step spin coating. The crystalline size of pentacene was improved from 147.9 to 165.2 Å, while the degree of structural disorder was decreased from 4.5% to 3.1% after the adoption of this technique. In pentacene-based TFTs, the improvement of the performance was also significant, besides the appearances of strong memory characteristics. The memory behaviors were attributed to the charge storage/discharge effect in QD-PMMA composite layer. Under the programming and erasing operations, programmable memory devices with the memory window (Δ Vth) = 23 V and long retention time were obtained.

Overcoming the drawback of lower sense margin in tunnel FET based dynamic memory along with enhanced charge retention and scalability

NASA Astrophysics Data System (ADS)

Navlakha, Nupur; Kranti, Abhinav

2017-11-01

The work reports on the use of a planar tri-gate tunnel field effect transistor (TFET) to operate as dynamic memory at 85 °C with an enhanced sense margin (SM). Two symmetric gates (G1) aligned to the source at a partial region of intrinsic film result into better electrostatic control that regulates the read mechanism based on band-to-band tunneling, while the other gate (G2), positioned adjacent to the first front gate is responsible for charge storage and sustenance. The proposed architecture results in an enhanced SM of ˜1.2 μA μm-1 along with a longer retention time (RT) of ˜1.8 s at 85 °C, for a total length of 600 nm. The double gate architecture towards the source increases the tunneling current and also reduces short channel effects, enhancing SM and scalability, thereby overcoming the critical bottleneck faced by TFET based dynamic memories. The work also discusses the impact of overlap/underlap and interface charges on the performance of TFET based dynamic memory. Insights into device operation demonstrate that the choice of appropriate architecture and biases not only limit the trade-off between SM and RT, but also result in improved scalability with drain voltage and total length being scaled down to 0.8 V and 115 nm, respectively.

Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Wei, E-mail: wwei99@jlu.edu.cn; Han, Jinhua; Ying, Jun

2014-09-22

Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm{sup 2}/V s. The unidirectional shift of turn-on voltage (V{sub on}) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (V{sub P}/V{sub E}) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered moleculemore » orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm{sup 2}/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the V{sub P}/V{sub E} of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional V{sub on} shift. As a result, an enlarged memory window of 28.6 V at the V{sub P}/V{sub E} of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.« less

Quasi-classical modeling of molecular quantum-dot cellular automata multidriver gates

NASA Astrophysics Data System (ADS)

Rahimi, Ehsan; Nejad, Shahram Mohammad

2012-05-01

Molecular quantum-dot cellular automata (mQCA) has received considerable attention in nanoscience. Unlike the current-based molecular switches, where the digital data is represented by the on/off states of the switches, in mQCA devices, binary information is encoded in charge configuration within molecular redox centers. The mQCA paradigm allows high device density and ultra-low power consumption. Digital mQCA gates are the building blocks of circuits in this paradigm. Design and analysis of these gates require quantum chemical calculations, which are demanding in computer time and memory. Therefore, developing simple models to probe mQCA gates is of paramount importance. We derive a semi-classical model to study the steady-state output polarization of mQCA multidriver gates, directly from the two-state approximation in electron transfer theory. The accuracy and validity of this model are analyzed using full quantum chemistry calculations. A complete set of logic gates, including inverters and minority voters, are implemented to provide an appropriate test bench in the two-dot mQCA regime. We also briefly discuss how the QCADesigner tool could find its application in simulation of mQCA devices.

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Light programmable organic transistor memory device based on hybrid dielectric

NASA Astrophysics Data System (ADS)

Ren, Xiaochen; Chan, Paddy K. L.

2013-09-01

We have fabricated the transistor memory devices based on SiO2 and polystyrene (PS) hybrid dielectric. The trap states densities with different semiconductors have been investigated and a maximum 160V memory window between programming and erasing is realized. For DNTT based transistor, the trapped electron density is limited by the number of mobile electrons in semiconductor. The charge transport mechanism is verified by light induced Vth shift effect. Furthermore, in order to meet the low operating power requirement of portable electronic devices, we fabricated the organic memory transistor based on AlOx/self-assembly monolayer (SAM)/PS hybrid dielectric, the effective capacitance of hybrid dielectric is 210 nF cm-2 and the transistor can reach saturation state at -3V gate bias. The memory window in transfer I-V curve is around 1V under +/-5V programming and erasing bias.

Nonvolatile infrared memory in MoS2/PbS van der Waals heterostructures

PubMed Central

Wen, Yao; Cai, Kaiming; Cheng, Ruiqing; Yin, Lei; Zhang, Yu; Li, Jie; Wang, Zhenxing; Wang, Feng; Wang, Fengmei; Shifa, Tofik Ahmed; Jiang, Chao; Yang, Hyunsoo

2018-01-01

Optoelectronic devices for information storage and processing are at the heart of optical communication technology due to their significant applications in optical recording and computing. The infrared radiations of 850, 1310, and 1550 nm with low energy dissipation in optical fibers are typical optical communication wavebands. However, optoelectronic devices that could convert and store the infrared data into electrical signals, thereby enabling optical data communications, have not yet been realized. We report an infrared memory device using MoS2/PbS van der Waals heterostructures, in which the infrared pulse intrigues a persistent resistance state that hardly relaxes within our experimental time scales (more than 104 s). The device fully retrieves the memory state even after powering off for 3 hours, indicating its potential for nonvolatile storage devices. Furthermore, the device presents a reconfigurable switch of 2000 stable cycles. Supported by a theoretical model with quantitative analysis, we propose that the optical memory and the electrical erasing phenomenon, respectively, originate from the localization of infrared-induced holes in PbS and gate voltage pulse-enhanced tunneling of electrons from MoS2 to PbS. The demonstrated MoS2 heterostructure–based memory devices open up an exciting field for optoelectronic infrared memory and programmable logic devices. PMID:29770356

Nonvolatile infrared memory in MoS2/PbS van der Waals heterostructures.

PubMed

Wang, Qisheng; Wen, Yao; Cai, Kaiming; Cheng, Ruiqing; Yin, Lei; Zhang, Yu; Li, Jie; Wang, Zhenxing; Wang, Feng; Wang, Fengmei; Shifa, Tofik Ahmed; Jiang, Chao; Yang, Hyunsoo; He, Jun

2018-04-01

Optoelectronic devices for information storage and processing are at the heart of optical communication technology due to their significant applications in optical recording and computing. The infrared radiations of 850, 1310, and 1550 nm with low energy dissipation in optical fibers are typical optical communication wavebands. However, optoelectronic devices that could convert and store the infrared data into electrical signals, thereby enabling optical data communications, have not yet been realized. We report an infrared memory device using MoS 2 /PbS van der Waals heterostructures, in which the infrared pulse intrigues a persistent resistance state that hardly relaxes within our experimental time scales (more than 10 4 s). The device fully retrieves the memory state even after powering off for 3 hours, indicating its potential for nonvolatile storage devices. Furthermore, the device presents a reconfigurable switch of 2000 stable cycles. Supported by a theoretical model with quantitative analysis, we propose that the optical memory and the electrical erasing phenomenon, respectively, originate from the localization of infrared-induced holes in PbS and gate voltage pulse-enhanced tunneling of electrons from MoS 2 to PbS. The demonstrated MoS 2 heterostructure-based memory devices open up an exciting field for optoelectronic infrared memory and programmable logic devices.

Synthesis of energy-efficient FSMs implemented in PLD circuits

NASA Astrophysics Data System (ADS)

Nawrot, Radosław; Kulisz, Józef; Kania, Dariusz

2017-11-01

The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous circuit. The experimental section reports a comparison of three methods of implementing sequential circuits in PLDs with respect to clock distribution: the classical fully synchronous structure, the structure exploiting the Enable Clock inputs of memory elements, and the structure using clock gating. The results show that the approach based on clock gating is the most efficient one, and it leads to significant reduction of dynamic power consumed by the FSM.

Extraction of sub-gap density of states via capacitance-voltage measurement for the erasing process in a TFT charge-trapping memory

NASA Astrophysics Data System (ADS)

Chiang, Yen-Chang; Hsiao, Yang-Hsuan; Li, Jeng-Ting; Chen, Jen-Sue

2018-02-01

Charge-trapping memories (CTMs) based on zinc tin oxide (ZTO) semiconductor thin-film transistors (TFTs) can be programmed by a positive gate voltage and erased by a negative gate voltage in conjunction with light illumination. To understand the mechanism involved, the sub-gap density of states associated with ionized oxygen vacancies in the ZTO active layer is extracted from optical response capacitance-voltage (C-V) measurements. The corresponding energy states of ionized oxygen vacancies are observed below the conduction band minimum at approximately 0.5-1.0 eV. From a comparison of the fitted oxygen vacancy concentration in the CTM-TFT after the light-bias erasing operation, it is found that the pristine-erased device contains more oxygen vacancies than the program-erased device because the trapped electrons in the programmed device are pulled into the active layer and neutralized by the oxygen vacancies that are present there.

Layer-by-layer charging in non-volatile memory devices using embedded sub-2 nm platinum nanoparticles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ramalingam, Balavinayagam; Zheng, Haisheng; Gangopadhyay, Shubhra, E-mail: gangopadhyays@missouri.edu

In this work, we demonstrate multi-level operation of a non-volatile memory metal oxide semiconductor capacitor by controlled layer-by-layer charging of platinum nanoparticle (PtNP) floating gate devices with defined gate voltage bias ranges. The device consists of two layers of ultra-fine, sub-2 nm PtNPs integrated between Al{sub 2}O{sub 3} tunneling and separation layers. PtNP size and interparticle distance were varied to control the particle self-capacitance and associated Coulomb charging energy. Likewise, the tunneling layer thicknesses were also varied to control electron tunneling to the first and second PtNP layers. The final device configuration with optimal charging behavior and multi-level programming was attainedmore » with a 3 nm Al{sub 2}O{sub 3} initial tunneling layer, initial PtNP layer with particle size 0.54 ± 0.12 nm and interparticle distance 4.65 ± 2.09 nm, 3 nm Al{sub 2}O{sub 3} layer to separate the PtNP layers, and second particle layer with 1.11 ± 0.28 nm PtNP size and interparticle distance 2.75 ± 1.05 nm. In this device, the memory window of the first PtNP layer saturated over a programming bias range of 7 V to 14 V, after which the second PtNP layer starts charging, exhibiting a multi-step memory window with layer-by-layer charging.« less

Graphene as a platform for novel nanoelectronic devices

NASA Astrophysics Data System (ADS)

Standley, Brian

Graphene's superlative electrical and mechanical properties, combined with its compatibility with existing planar silicon-based technology, make it an attractive platform for novel nanoelectronic devices. The development of two such devices is reported--a nonvolatile memory element exploiting the nanoscale graphene edge and a field-effect transistor using graphene for both the conducting channel and, in oxidized form, the gate dielectric. These experiments were enabled by custom software written to fully utilize both instrument-based and computer-based data acquisition hardware and provide a simple measurement automation system. Graphene break junctions were studied and found to exhibit switching behavior in response to an electric field. This switching allows the devices to act as nonvolatile memory elements which have demonstrated thousands of writing cycles and long retention times. A model for device operation is proposed based on the formation and breaking of carbon-atom chains that bridge the junctions. Information storage was demonstrated using the concept of rank coding, in which information is stored in the relative conductance of multiple graphene switches in a memory cell. The high mobility and two dimensional nature of graphene make it an attractive material for field-effect transistors. Another ultrathin layered materialmd graphene's insulating analogue, graphite oxidemd was studied as an alternative to bulk gate dielectric materials such as Al2O3 or HfO 2. Transistors were fabricated comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. Electron transport measurements reveal minimal leakage through the graphite oxide at room temperature. Its breakdown electric field was found to be comparable to SiO2, typically ˜1-3 x 108 V/m, while its dielectric constant is slightly higher, kappa ≈ 4.3. As nanoelectronics experiments and their associated instrumentation continue to grow in complexity the need for powerful data acquisition software has only increased. This role has traditionally been filled by semiconductor parameter analyzers or desktop computers running LabVIEW. Mezurit 2 represents a hybrid approach, providing basic virtual instruments which can be controlled in concert through a comprehensive scripting interface. Each virtual instrument's model of operation is described and an architectural overview is provided.

Operation mode switchable charge-trap memory based on few-layer MoS2

NASA Astrophysics Data System (ADS)

Hou, Xiang; Yan, Xiao; Liu, Chunsen; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2018-03-01

Ultrathin layered two-dimensional (2D) semiconductors like MoS2 and WSe2 have received a lot of attention because of their excellent electrical properties and potential applications in electronic devices. We demonstrate a charge-trap memory with two different tunable operation modes based on a few-layer MoS2 channel and an Al2O3/HfO2/Al2O3 charge storage stack. Our device shows excellent memory properties under the traditional three-terminal operation mode. More importantly, unlike conventional charge-trap devices, this device can also realize the memory performance with just two terminals (drain and source) because of the unique atomic crystal electrical characteristics. Under the two-terminal operation mode, the erase/program current ratio can reach up to 104 with a stable retention property. Our study indicates that the conventional charge-trap memory cell can also realize the memory performance without the gate terminal based on novel two dimensional materials, which is meaningful for low power consumption and high integration density applications.

Investigations on the effects of electrode materials on the device characteristics of ferroelectric memory thin film transistors fabricated on flexible substrates

NASA Astrophysics Data System (ADS)

Yang, Ji-Hee; Yun, Da-Jeong; Seo, Gi-Ho; Kim, Seong-Min; Yoon, Myung-Han; Yoon, Sung-Min

2018-03-01

For flexible memory device applications, we propose memory thin-film transistors using an organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] gate insulator and an amorphous In-Ga-Zn-O (a-IGZO) active channel. The effects of electrode materials and their deposition methods on the characteristics of memory devices exploiting the ferroelectric field effect were investigated for the proposed ferroelectric memory thin-film transistors (Fe-MTFTs) at flat and bending states. It was found that the plasma-induced sputtering deposition and mechanical brittleness of the indium-tin oxide (ITO) markedly degraded the ferroelectric-field-effect-driven memory window and bending characteristics of the Fe-MTFTs. The replacement of ITO electrodes with metal aluminum (Al) electrodes prepared by plasma-free thermal evaporation greatly enhanced the memory device characteristics even under bending conditions owing to their mechanical ductility. Furthermore, poly(3,4-ethylenedioxythiophene)-poly(styrene sulfonate) (PEDOT:PSS) was introduced to achieve robust bending performance under extreme mechanical stress. The Fe-MTFTs using PEDOT:PSS source/drain electrodes were successfully fabricated and showed the potential for use as flexible memory devices. The suitable choice of electrode materials employed for the Fe-MTFTs is concluded to be one of the most important control parameters for highly functional flexible Fe-MTFTs.

Redundant single event upset supression system

DOEpatents

Hoff, James R.

2006-04-04

CMOS transistors are configured to operate as either a redundant, SEU-tolerant, positive-logic, cross-coupled Nor Gate SR-flip flop or a redundant, SEU-tolerant, negative-logic, cross-coupled Nand Gate SR-flip flop. The register can operate as a memory, and further as a memory that can overcome the effects of radiation. As an SR-flip flop, the invention can be altered into any known type of latch or flip-flop by the application of external logic, thereby extending radiation tolerance to devices previously incapable of radiation tolerance. Numerous registers can be logically connected and replicated thereby being electronically configured to operate as a redundant circuit.

Ultrafast, superhigh gain visible-blind UV detector and optical logic gates based on nonpolar a-axial GaN nanowire

NASA Astrophysics Data System (ADS)

Wang, Xingfu; Zhang, Yong; Chen, Xinman; He, Miao; Liu, Chao; Yin, Yian; Zou, Xianshao; Li, Shuti

2014-09-01

Nonpolar a-axial GaN nanowire (NW) was first used to construct the MSM (metal-semiconductor-metal) symmetrical Schottky contact device for application as visible-blind ultraviolet (UV) detector. Without any surface or composition modifications, the fabricated device demonstrated a superior performance through a combination of its high sensitivity (up to 104 A W-1) and EQE value (up to 105), as well as ultrafast (<26 ms) response speed, which indicates that a balance between the photocurrent gain and the response speed has been achieved. Based on its excellent photoresponse performance, an optical logic AND gate and OR gate have been demonstrated for performing photo-electronic coupled logic devices by further integrating the fabricated GaN NW detectors, which logically convert optical signals to electrical signals in real time. These results indicate the possibility of using a nonpolar a-axial GaN NW not only as a high performance UV detector, but also as a stable optical logic device, both in light-wave communications and for future memory storage.Nonpolar a-axial GaN nanowire (NW) was first used to construct the MSM (metal-semiconductor-metal) symmetrical Schottky contact device for application as visible-blind ultraviolet (UV) detector. Without any surface or composition modifications, the fabricated device demonstrated a superior performance through a combination of its high sensitivity (up to 104 A W-1) and EQE value (up to 105), as well as ultrafast (<26 ms) response speed, which indicates that a balance between the photocurrent gain and the response speed has been achieved. Based on its excellent photoresponse performance, an optical logic AND gate and OR gate have been demonstrated for performing photo-electronic coupled logic devices by further integrating the fabricated GaN NW detectors, which logically convert optical signals to electrical signals in real time. These results indicate the possibility of using a nonpolar a-axial GaN NW not only as a high performance UV detector, but also as a stable optical logic device, both in light-wave communications and for future memory storage. Electronic supplementary information (ESI) available: Details of the EDS and SAED data, supplementary results of the UV detector, and the discussion of the transport properties of the MSM Schottky contact devices. See DOI: 10.1039/c4nr03581j

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moghadam, Reza M.; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to low-power field-effect devices that can be used for logic or memory. Essential to realizing such field-effect devices is the development of ferroelectric metal-oxide-semiconductor (MOS) capacitors, in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel. Here we demonstrate that ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x= 0.7) that has been epitaxially grown on Ge. We find that themore » ferroelectric properties of SrZrxTi1-xO3 are exceptionally robust, as gate layers as thin as 5 nm give rise to hysteretic capacitance-voltage characteristics that are 2 V in width. The development of ferroelectric MOS capacitors with gate thicknesses that are technologically relevant opens a pathway to realize scalable ferroelectric field-effect devices.« less

Reduced distribution of threshold voltage shift in double layer NiSi2 nanocrystals for nano-floating gate memory applications.

PubMed

Choi, Sungjin; Lee, Junhyuk; Kim, Donghyoun; Oh, Seulki; Song, Wangyu; Choi, Seonjun; Choi, Eunsuk; Lee, Seung-Beck

2011-12-01

We report on the fabrication and capacitance-voltage characteristics of double layer nickel-silicide nanocrystals with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. Compared with devices using SiO2 interlayer, the use of Si3N4 interlayer separation reduced the average size (4 nm) and distribution (+/- 2.5 nm) of NiSi2 nanocrystal (NC) charge traps by more than 50% and giving a two fold increase in NC density to 2.3 x 10(12) cm(-2). The increased density and reduced NC size distribution resulted in a significantly decrease in the distribution of the device C-V characteristics. For each program voltage, the distribution of the shift in the threshold voltage was reduced by more than 50% on average to less than 0.7 V demonstrating possible multi-level-cell operation.

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

NASA Astrophysics Data System (ADS)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

NASA Astrophysics Data System (ADS)

Jayanti, Srikant

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG in the form of PVD TaN was investigated along with high-k blocking dielectric. The material properties of TaN metal and high-k / low-k dielectric engineering were systematically studied. And the resulting memory structures exhibit excellent memory characteristics and scalability of the metal FG down to ˜1nm, which is promising in order to reduce the unwanted FG-FG interferences. In the later part of the study, the thermal stability of the combined stack was examined and various approaches to improve the stability and understand the cause of instability were explored. The performance of the high-k IPD metal FG memory structure was observed to degrade with higher annealing conditions and the deteriorated behavior was attributed to the leakage instability of the high-k /TaN capacitor. While the degradation is pronounced in both MIM and MIS capacitors, a higher leakage increment was seen in MIM, which was attributed to the higher degree of dielectric crystallization. In an attempt to improve the thermal stability, the trade-off in using amorphous interlayers to reduce the enhanced dielectric crystallization on metal was highlighted. Also, the effect of oxygen vacancies and grain growth on the dielectric leakage was studied through a multi-deposition-multi-anneal technique. Multi step deposition and annealing in a more electronegative ambient was observed to have a positive impact on the dielectric performance.

Design, processing, and testing of LSI arrays for space station

NASA Technical Reports Server (NTRS)

Schneider, W. C.

1974-01-01

At wafer probe, units of the TA6567 circuit, a beam leaded COS/MOS/SOS 256-bit RAM, were demonstrated to be functionally perfect. An aluminum gate current-sense version and a silicon-gate voltage-sense version of this memory were developed. Initial base line data for the beam lead SOS process using the TA5388 circuit show the stability of the dc device characteristics through the beam lead processing.

Modeling of Sonos Memory Cell Erase Cycle

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memories (NVSMS) have many advantages. These memories are electrically erasable programmable read-only memories (EEPROMs). They utilize low programming voltages, endure extended erase/write cycles, are inherently resistant to radiation, and are compatible with high-density scaled CMOS for low power, portable electronics. The SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. The SONOS floating gate charge and voltage, tunneling current, threshold voltage, and drain current were characterized during an erase cycle. Comparisons were made between the model predictions and experimental device data.

Organic transistor memory with a charge storage molecular double-floating-gate monolayer.

PubMed

Tseng, Chiao-Wei; Huang, Ding-Chi; Tao, Yu-Tai

2015-05-13

A flexible, low-voltage, and nonvolatile memory device was fabricated by implanting a functional monolayer on an aluminum oxide dielectric surface in a pentacene-based organic transistor. The monolayer-forming molecule contains a phosphonic acid group as the anchoring moiety and a charge-trapping core group flanked between two alkyl chain spacers as the charge trapping site. The memory characteristics strongly depend on the monolayer used due to the localized charge-trapping capability for different core groups, including the diacetylenic (DA) unit as the hole carrier trap, the naphthalenetetracarboxyldiimide (ND) unit as the electron carrier trap, and the one with both DA and ND units present, respectively. The device with the monolayer carrying both DA and ND groups has a larger memory window than that for the one containing DA only and a longer retention time than that for the one containing DA or ND only, giving a memory window of 1.4 V and a retention time around 10(9) s. This device with hybrid organic monolayer/inorganic dielectrics also exhibited rather stable device characteristics upon bending of the polymeric substrate.

Feasibility of self-structured current accessed bubble devices in spacecraft recording systems

NASA Technical Reports Server (NTRS)

Nelson, G. L.; Krahn, D. R.; Dean, R. H.; Paul, M. C.; Lo, D. S.; Amundsen, D. L.; Stein, G. A.

1985-01-01

The self-structured, current aperture approach to magnetic bubble memory is described. Key results include: (1) demonstration that self-structured bubbles (a lattice of strongly interacting bubbles) will slip by one another in a storage loop at spacings of 2.5 bubble diameters, (2) the ability of self-structured bubbles to move past international fabrication defects (missing apertures) in the propagation conductors (defeat tolerance), and (3) moving bubbles at mobility limited speeds. Milled barriers in the epitaxial garnet are discussed for containment of the bubble lattice. Experimental work on input/output tracks, storage loops, gates, generators, and magneto-resistive detectors for a prototype device are discussed. Potential final device architectures are described with modeling of power consumption, data rates, and access times. Appendices compare the self-structured bubble memory from the device and system perspectives with other non-volatile memory technologies.

Reduced electron back-injection in Al2O3/AlOx/Al2O3/graphene charge-trap memory devices

NASA Astrophysics Data System (ADS)

Lee, Sejoon; Song, Emil B.; Min Kim, Sung; Lee, Youngmin; Seo, David H.; Seo, Sunae; Wang, Kang L.

2012-12-01

A graphene charge-trap memory is devised using a single-layer graphene channel with an Al2O3/AlOx/Al2O3 oxide stack, where the ion-bombarded AlOx layer is intentionally added to create an abundance of charge-trap sites. The low dielectric constant of AlOx compared to Al2O3 reduces the potential drop in the control oxide Al2O3 and suppresses the electron back-injection from the gate to the charge-storage layer, allowing the memory window of the device to be further extended. This shows that the usage of a lower dielectric constant in the charge-storage layer compared to that of the control oxide layer improves the memory performance for graphene charge-trap memories.

Capacitance-voltage measurement in memory devices using ferroelectric polymer

NASA Astrophysics Data System (ADS)

Nguyen, Chien A.; Lee, Pooi See

2006-01-01

Application of thin polymer film as storing mean for non-volatile memory devices is investigated. Capacitance-voltage (C-V) measurement of metal-ferroelectric-metal device using ferroelectric copolymer P(VDF-TrFE) as dielectric layer shows stable 'butter-fly' curve. The two peaks in C-V measurement corresponding to the largest capacitance are coincidental at the coercive voltages that give rise to zero polarization in the polarization hysteresis measurement. By comparing data of C-V and P-E measurement, a correlation between two types of hysteresis is established in which it reveals simultaneous electrical processes occurring inside the device. These processes are caused by the response of irreversible and reversible polarization to the applied electric field that can be used to present a memory window. The memory effect of ferroelectric copolymer is further demonstrated for fabricating polymeric non-volatile memory devices using metal-ferroelectric-insulator-semiconductor structure (MFIS). By applying different sweeping voltages at the gate, bidirectional flat-band voltage shift is observed in the ferroelectric capacitor. The asymmetrical shift after negative sweeping is resulted from charge accumulation at the surface of Si substrate caused by the dipole direction in the polymer layer. The effect is reversed for positive voltage sweeping.

Protected quantum computing: interleaving gate operations with dynamical decoupling sequences.

PubMed

Zhang, Jingfu; Souza, Alexandre M; Brandao, Frederico Dias; Suter, Dieter

2014-02-07

Implementing precise operations on quantum systems is one of the biggest challenges for building quantum devices in a noisy environment. Dynamical decoupling attenuates the destructive effect of the environmental noise, but so far, it has been used primarily in the context of quantum memories. Here, we experimentally demonstrate a general scheme for combining dynamical decoupling with quantum logical gate operations using the example of an electron-spin qubit of a single nitrogen-vacancy center in diamond. We achieve process fidelities >98% for gate times that are 2 orders of magnitude longer than the unprotected dephasing time T2.

3-D Observation of dopant distribution at NAND flash memory floating gate using Atom probe tomography

NASA Astrophysics Data System (ADS)

Lee, Ji-hyun; Chae, Byeong-Kyu; Kim, Joong-Jeong; Lee, Sun Young; Park, Chan Gyung

2015-01-01

Dopant control becomes more difficult and critical as silicon devices become smaller. We observed the dopant distribution in a thermally annealed polysilicon gate using Transmission Electron Microscopy (TEM) and Atom probe tomography (APT). Phosphorus was doped at the silicon-nitride-diffusion-barrier-layer-covered polycrystalline silicon gate. Carbon also incorporated at the gate for the enhancement of operation uniformity. The impurity distribution was observed using atom probe tomography. The carbon atoms had segregated at grain boundaries and suppressed silicon grain growth. Phosphorus atoms, on the other hand, tended to pile-up at the interface. A 1-nm-thick diffusion barrier effectively blocked P atom out-diffusion. [Figure not available: see fulltext.

Graphene quantum dot (GQD)-induced photovoltaic and photoelectric memory elements in a pentacene/GQD field effect transistor as a probe of functional interface

NASA Astrophysics Data System (ADS)

Kim, Youngjun; Cho, Seongeun; Kim, Hyeran; Seo, Soonjoo; Lee, Hyun Uk; Lee, Jouhahn; Ko, Hyungduk; Chang, Mincheol; Park, Byoungnam

2017-09-01

Electric field-induced charge trapping and exciton dissociation were demonstrated at a penatcene/grapheme quantum dot (GQD) interface using a bottom contact bi-layer field effect transistor (FET) as an electrical nano-probe. Large threshold voltage shift in a pentacene/GQD FET in the dark arises from field-induced carrier trapping in the GQD layer or GQD-induced trap states at the pentacene/GQD interface. As the gate electric field increases, hysteresis characterized by the threshold voltage shift depending on the direction of the gate voltage scan becomes stronger due to carrier trapping associated with the presence of a GQD layer. Upon illumination, exciton dissociation and gate electric field-induced charge trapping simultaneously contribute to increase the threshold voltage window, which can potentially be exploited for photoelectric memory and/or photovoltaic devices through interface engineering.

Modeling of Nano-Scale Transistors and Memory Devices for Low Power Applications

NASA Astrophysics Data System (ADS)

Cao, Xi

As the featuring size of transistors scaled down to sub-20 nm, the continuous scaling of power has become one of the main challenges of the semiconductor industry. The power issue is raised by the barely scalable supply voltage and a limitation on the subthreshold swing (SS) of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, self-consistent quantum transport device simulators are developed to examine the nanoscale transistors based on black phosphorus (BP) materials. The scaling limit of double-gated BP MOSFETs is assessed. To reduce the SS below the thermionic limit for ultra-steep switching, tunnel FETs (TFETs) and vertical ballistic impact ionization FETs based on BP and its heterojunctions are investigated. Furthermore, the ferroelectric tunneling junction (FTJ) is modeled and examined for potential low power memory applications. For BP MOSFETs, the device physics at the ultimate scaling limit are examined. The performance of monolayer BP MOSFETs is projected to sub-10 nm and compared with the International Technology Roadmap for Semiconductors (ITRS) requirements. And the interplay of quantum mechanical effects and the highly anisotropic bandstructure of BP at this scale is investigated. By choice of layer number and crystalline direction, BP materials can offer a range of bandgap and effective mass values, which is attractive for TFET applications. Therefore, scaling behaviors of BP TFETs near and below the 10 nm scale are studied. The gate oxide thickness scaling and the effect of high-k dielectric are compared between the TFETs and the MOSFETs. For the TFETs with the gate lengths beyond 10 nm and at the sub-10 nm scale, the direct-source-to-drain tunneling issues are evaluated, and different strategies to achieve ultra-steep switching are specified. In a sub-10 nm graphene-BP-graphene heterojunction transistor, the sharp turnon behavior was observed, under a small source-drain bias of 0.1 V. The fast switch is attributed to a ballistic energy-dependent impact ionization mechanism. A device model is developed, which shows agreement with experiment results. The model is applied to explore the gate oxide scaling behavior and the effect of graphene doping, and to optimize the device for low power applications. Finally, to keep the integrity of the computing system, the FTJ is studied for its possible use as a low power memory device. A compact model for FTJ, dealing with both static and dynamic behaviors, is developed and compared with experimental data. The write energy consumed by the memory cell, comprising one transistor and one FTJ, is estimated by applying the compact model to circuit simulation. And a way to reduce the write energy is suggested.

A review of emerging non-volatile memory (NVM) technologies and applications

NASA Astrophysics Data System (ADS)

Chen, An

2016-11-01

This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

Memristive behavior in a junctionless flash memory cell

DOE Office of Scientific and Technical Information (OSTI.GOV)

Orak, Ikram; Department of Physics, Faculty of Science and Art, Bingöl University, 12000 Bingöl; Ürel, Mustafa

2015-06-08

We report charge storage based memristive operation of a junctionless thin film flash memory cell when it is operated as a two terminal device by grounding the gate. Unlike memristors based on nanoionics, the presented device mode, which we refer to as the flashristor mode, potentially allows greater control over the memristive properties, allowing rational design. The mode is demonstrated using a depletion type n-channel ZnO transistor grown by atomic layer deposition (ALD), with HfO{sub 2} as the tunnel dielectric, Al{sub 2}O{sub 3} as the control dielectric, and non-stoichiometric silicon nitride as the charge storage layer. The device exhibits themore » pinched hysteresis of a memristor and in the unoptimized device, R{sub off}/R{sub on} ratios of about 3 are presented with low operating voltages below 5 V. A simplified model predicts R{sub off}/R{sub on} ratios can be improved significantly by adjusting the native threshold voltage of the devices. The repeatability of the resistive switching is excellent and devices exhibit 10{sup 6 }s retention time, which can, in principle, be improved by engineering the gate stack and storage layer properties. The flashristor mode can find use in analog information processing applications, such as neuromorphic computing, where well-behaving and highly repeatable memristive properties are desirable.« less

Dual drain MOSFET detector for crosstie memory systems

NASA Astrophysics Data System (ADS)

Bluzer, N.

1985-03-01

This patent application, which discloses a circuit for detecting binary information in crosstie memory systems includes a dual drain MOSFET device having a single channel with a common source and an integrated, thin-film strip of magnetic material suitable for the storage and propagation of Bloch line-crosstie pairs acting as both a shift register and the device's gate. Current flowing through the device, in the absence of a magnetic field, is equally distributed to each drain; however, changing magnetic fields, normal to the plane of the device and generated by Bloch line-crosstie pairs in the strip, interact with the current such that a distribution imbalance exists and one drain or the other receives a disproportionate fraction of the current depending upon the direction of the magnetic field.

Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

NASA Astrophysics Data System (ADS)

Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

2018-05-01

Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

The floating-gate non-volatile semiconductor memory--from invention to the digital age.

PubMed

Sze, S M

2012-10-01

In the past 45 years (from 1967 to 2012), the non-volatile semiconductor memory (NVSM) has emerged from a floating-gate concept to the prime technology driver of the largest industry in the world-the electronics industry. In this paper, we briefly review the historical development of NVSM and project its future trends to the year 2020. In addition, we consider NVSM's wide-range of applications from the digital cellular phone to tablet computer to digital television. As the device dimension is scaled down to the deca-nanometer regime, we expect that many innovations will be made to meet the scaling challenges, and NVSM-inspired technology will continue to enrich and improve our lives for decades to come.

S-Band POSIX Device Drivers for RTEMS

NASA Technical Reports Server (NTRS)

Lux, James P.; Lang, Minh; Peters, Kenneth J.; Taylor, Gregory H.

2011-01-01

This is a set of POSIX device driver level abstractions in the RTEMS RTOS (Real-Time Executive for Multiprocessor Systems real-time operating system) to SBand radio hardware devices that have been instantiated in an FPGA (field-programmable gate array). These include A/D (analog-to-digital) sample capture, D/A (digital-to-analog) sample playback, PLL (phase-locked-loop) tuning, and PWM (pulse-width-modulation)-controlled gain. This software interfaces to Sband radio hardware in an attached Xilinx Virtex-2 FPGA. It uses plug-and-play device discovery to map memory to device IDs. Instead of interacting with hardware devices directly, using direct-memory mapped access at the application level, this driver provides an application programming interface (API) offering that easily uses standard POSIX function calls. This simplifies application programming, enables portability, and offers an additional level of protection to the hardware. There are three separate device drivers included in this package: sband_device (ADC capture and DAC playback), pll_device (RF front end PLL tuning), and pwm_device (RF front end AGC control).

Synthesis and electron storage characteristics of isolated silver nanodots on/embedded in Al 2O 3 gate dielectric

NASA Astrophysics Data System (ADS)

Wang, Q.; Song, Z. T.; Liu, W. L.; Lin, C. L.; Wang, T. H.

2004-05-01

Monolayer-isolated silver (Ag) nanodots with the average diameter down to 7 nm are synthesized on Al 2O 3/Si substrate by vacuum electron-beam evaporation followed by annealing at 400 °C in N 2 ambient. Metal-insulator-silicon (MIS) structures with Ag nanodots embedded in Al 2O 3 gate dielectric are fabricated. Clear electron storage effect with the flatband voltage shift of 1.3 eV is observed through capacitance-conductance and conductance-voltage measurements. Our results demonstrate the feasibility of applying Ag nanodots for nanocrystal floating-gate memory devices.

Materials and methods for the preparation of nanocomposites

DOEpatents

Talapin, Dmitri V.; Kovalenko, Maksym V.; Lee, Jong-Soo; Jiang, Chengyang

2016-05-24

Disclosed herein is an isolable colloidal particle comprising a nanoparticle and an inorganic capping agent bound to the surface of the nanoparticle, a solution of the same, a method for making the same from a biphasic solvent mixture, and the formation of structures and solids from the isolable colloidal particle. The process can yield photovoltaic cells, piezoelectric crystals, thermoelectric layers, optoelectronic layers, light emitting diodes, ferroelectric layers, thin film transistors, floating gate memory devices, imaging devices, phase change layers, and sensor devices.

Light-induced negative differential resistance in gate-controlled graphene-silicon photodiode

NASA Astrophysics Data System (ADS)

Liu, Wei; Guo, Hongwei; Li, Wei; Wan, Xia; Bodepudi, Srikrishna Chanakya; Shehzad, Khurram; Xu, Yang

2018-05-01

In this letter, we investigated light-induced negative differential resistance (L-NDR) effects in a hybrid photodiode formed by a graphene-silicon (GS) junction and a neighboring graphene-oxide-Si (GOS) capacitor. We observed two distinct L-NDR effects originating from the gate-dependent surface recombination and the potential-well-induced confinement of photo-carriers in the GOS region. We verified this by studying the gate-controlled GS diode, which can distinguish the photocurrent from the GS region with that from the GOS region (gate). A large peak-to-valley ratio of up to 12.1 has been obtained for the L-NDR due to gate-dependent surface recombination. Such strong L-NDR effect provides an opportunity to further engineer the optoelectronic properties of GS junctions along with exploring its potential applications in photodetectors, photo-memories, and position sensitive devices.

A High-Performance Optical Memory Array Based on Inhomogeneity of Organic Semiconductors.

PubMed

Pei, Ke; Ren, Xiaochen; Zhou, Zhiwen; Zhang, Zhichao; Ji, Xudong; Chan, Paddy Kwok Leung

2018-03-01

Organic optical memory devices keep attracting intensive interests for diverse optoelectronic applications including optical sensors and memories. Here, flexible nonvolatile optical memory devices are developed based on the bis[1]benzothieno[2,3-d;2',3'-d']naphtho[2,3-b;6,7-b']dithiophene (BBTNDT) organic field-effect transistors with charge trapping centers induced by the inhomogeneity (nanosprouts) of the organic thin film. The devices exhibit average mobility as high as 7.7 cm 2 V -1 s -1 , photoresponsivity of 433 A W -1 , and long retention time for more than 6 h with a current ratio larger than 10 6 . Compared with the standard floating gate memory transistors, the BBTNDT devices can reduce the fabrication complexity, cost, and time. Based on the reasonable performance of the single device on a rigid substrate, the optical memory transistor is further scaled up to a 16 × 16 active matrix array on a flexible substrate with operating voltage less than 3 V, and it is used to map out 2D optical images. The findings reveal the potentials of utilizing [1]benzothieno[3,2-b][1]benzothiophene (BTBT) derivatives as organic semiconductors for high-performance optical memory transistors with a facile structure. A detailed study on the charge trapping mechanism in the derivatives of BTBT materials is also provided, which is closely related to the nanosprouts formed inside the organic active layer. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Eliminating Overerase Behavior by Designing Energy Band in High-Speed Charge-Trap Memory Based on WSe2.

PubMed

Liu, Chunsen; Yan, Xiao; Wang, Jianlu; Ding, Shijin; Zhou, Peng; Zhang, David Wei

2017-05-01

Atomic crystal charge trap memory, as a new concept of nonvolatile memory, possesses an atomic level flatness interface, which makes them promising candidates for replacing conventional FLASH memory in the future. Here, a 2D material WSe 2 and a 3D Al 2 O 3 /HfO 2 /Al 2 O 3 charge-trap stack are combined to form a charge-trap memory device with a separation of control gate and memory stack. In this device, the charges are erased/written by built-in electric field, which significantly enhances the write speed to 1 µs. More importantly, owing to the elaborate design of the energy band structure, the memory only captures electrons with a large electron memory window over 20 V and trap selectivity about 13, both of them are the state-of-the-art values ever reported in FLASH memory based on 2D materials. Therefore, it is demonstrated that high-performance charge trap memory based on WSe 2 without the fatal overerase issue in conventional FLASH memory can be realized to practical application. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Design and simulation of nanoscale double-gate TFET/tunnel CNTFET

NASA Astrophysics Data System (ADS)

Bala, Shashi; Khosla, Mamta

2018-04-01

A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si), gallium arsenide (GaAs), alminium gallium arsenide (Al x Ga1‑x As) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are compared on the basis of inverse subthreshold slope (SS), I ON/I OFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the Al x Ga1‑x As based DG tunnel FET provides a better I ON/I OFF current ratio (2.51 × 106) as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.

Scan direction induced charging dynamics and the application for detection of gate to S/D shorts in logic devices

NASA Astrophysics Data System (ADS)

Lei, Ming; Tian, Qing; Wu, Kevin; Zhao, Yan

2016-03-01

Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

Investigation of impact of post-metallization annealing on reliability of 65 nm NOR floating-gate flash memories

NASA Astrophysics Data System (ADS)

Chiu, Shengfen; Xu, Yue; Ji, Xiaoli; Yan, Feng

2016-12-01

This paper investigates the impact of post-metallization annealing (PMA) in pure nitrogen ambient on the reliability of 65 nm NOR-type floating-gate flash memory devices. The experimental results show that, with PMA process, the cycling performance of flash cells, especially for the erasing speed is obviously degraded compared to that without PMA. It is found that the bulk oxide traps and tunnel oxide/Si interface traps are significantly increased with PMA treatment. The water/moisture residues left in the interlayer dielectric layers diffuse to tunnel oxide during PMA process is considered to be responsible for these traps generation, which further enhances the degradation of erase performance. Skipping PMA treatment is proposed to suppress the water diffusion effect on erase performance degradation of flash cells.

Materials and methods for the preparation of nanocomposites

DOEpatents

Nag, Angshuman; Talapin, Dmitri V.

2018-01-30

Disclosed herein is an isolable colloidal particle comprising a nanoparticle and an inorganic capping agent bound to the surface of the nanoparticle, a method for making the same in a biphasic solvent mixture, and the formation of structures and solids from the isolable colloidal particle. The process can yield photovoltaic cells, piezoelectric crystals, thermoelectric layers, optoelectronic layers, light emitting diodes, ferroelectric layers, thin film transistors, floating gate memory devices, phase change layers, and sensor devices.

Characteristics of Reduced Graphene Oxide Quantum Dots for a Flexible Memory Thin Film Transistor.

PubMed

Kim, Yo-Han; Lee, Eun Yeol; Lee, Hyun Ho; Seo, Tae Seok

2017-05-17

Reduced graphene oxide quantum dot (rGOQD) devices in formats of capacitor and thin film transistor (TFT) were demonstrated and examined as the first trial to achieve nonambipolar channel property. In addition, through a gold nanoparticle (Au NP) layer embedded between the rGOQD active channel and dielectric layer, memory capacitor and TFT performances were realized by capacitance-voltage (C-V) hysteresis and gate program, erase, and reprogram biases. First, capacitor structure of the rGOQD memory device was constructed to examine memory charging effect featured in hysteretic C-V behavior with a 30 nm dielectric layer of cross-linked poly(vinyl alcohol). For the intervening Au NP charging layer, self-assembled monolayer (SAM) formation of the Au NP was executed to utilize electrostatic interaction by a dip-coating process under ambient environments with a conformal fabrication uniformity. Second, the rGOQD memory TFT device was also constructed in the same format of the Au NPs SAMs on a flexible substrate. Characteristics of the rGOQD TFT output showed novel saturation curves unlike typical graphene-based TFTs. However, The rGOQD TFT device reveals relatively low on/off ratio of 10 1 and mobility of 5.005 cm 2 /V·s. For the memory capacitor, the flat-band voltage shift (ΔV FB ) was measured as 3.74 V for ±10 V sweep, and for the memory TFT, the threshold voltage shift (ΔV th ) by the Au NP charging was detected as 7.84 V. In summary, it was concluded that the rGOQD memory device could accomplish an ideal graphene-based memory performance, which could have provided a wide memory window and saturated output characteristics.

Hysteresis in the transfer characteristics of MoS2 transistors

NASA Astrophysics Data System (ADS)

Di Bartolomeo, Antonio; Genovese, Luca; Giubileo, Filippo; Iemmo, Laura; Luongo, Giuseppe; Foller, Tobias; Schleberger, Marika

2018-01-01

We investigate the origin of the hysteresis observed in the transfer characteristics of back-gated field-effect transistors with an exfoliated MoS2 channel. We find that the hysteresis is strongly enhanced by increasing either gate voltage, pressure, temperature or light intensity. Our measurements reveal a step-like behavior of the hysteresis around room temperature, which we explain as water-facilitated charge trapping at the MoS2/SiO2 interface. We conclude that intrinsic defects in MoS2, such as S vacancies, which result in effective positive charge trapping, play an important role, besides H2O and O2 adsorbates on the unpassivated device surface. We show that the bistability associated to the hysteresis can be exploited in memory devices.

Ferroelectric control of a Mott insulator

PubMed Central

Yamada, Hiroyuki; Marinova, Maya; Altuntas, Philippe; Crassous, Arnaud; Bégon-Lours, Laura; Fusil, Stéphane; Jacquet, Eric; Garcia, Vincent; Bouzehouane, Karim; Gloter, Alexandre; Villegas, Javier E.; Barthélémy, Agnès; Bibes, Manuel

2013-01-01

The electric field control of functional properties is an important goal in oxide-based electronics. To endow devices with memory, ferroelectric gating is interesting, but usually weak compared to volatile electrolyte gating. Here, we report a very large ferroelectric field-effect in perovskite heterostructures combining the Mott insulator CaMnO3 and the ferroelectric BiFeO3 in its “supertetragonal” phase. Upon polarization reversal of the BiFeO3 gate, the CaMnO3 channel resistance shows a fourfold variation around room temperature, and a tenfold change at ~200 K. This is accompanied by a carrier density modulation exceeding one order of magnitude. We have analyzed the results for various CaMnO3 thicknesses and explain them by the electrostatic doping of the CaMnO3 layer and the presence of a fixed dipole at the CaMnO3/BiFeO3 interface. Our results suggest the relevance of ferroelectric gates to control orbital- or spin-ordered phases, ubiquitous in Mott systems, and pave the way toward efficient Mott-tronics devices. PMID:24089020

Ferroelectric switching of poly(vinylidene difluoride-trifluoroethylene) in metal-ferroelectric-semiconductor non-volatile memories with an amorphous oxide semiconductor

NASA Astrophysics Data System (ADS)

Gelinck, G. H.; van Breemen, A. J. J. M.; Cobb, B.

2015-03-01

Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Mizubayashi, Wataru; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Masahara, Meishoku

2014-01-01

Three-dimensional (3D) fin-channel charge trapping (CT) flash memories with different gate materials of physical-vapor-deposited (PVD) titanium nitride (TiN) and n+-polycrystalline silicon (poly-Si) have successfully been fabricated by using (100)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. Electrical characteristics of the fabricated flash memories including statistical threshold voltage (Vt) variability, endurance, and data retention have been comparatively investigated. It was experimentally found that a larger memory window and a deeper erase are obtained in PVD-TiN-gated metal-oxide-nitride-oxide-silicon (MONOS)-type flash memories than in poly-Si-gated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type memories. The larger memory window and deeper erase of MONOS-type flash memories are contributed by the higher work function of the PVD-TiN metal gate than of the n+-poly-Si gate, which is effective for suppressing electron back tunneling during erase operation. It was also found that the initial Vt roll-off due to the short-channel effect (SCE) is directly related to the memory window roll-off when the gate length (Lg) is scaled down to 46 nm or less.

Light-erasable embedded charge-trapping memory based on MoS2 for system-on-panel applications

NASA Astrophysics Data System (ADS)

He, Long-Fei; Zhu, Hao; Xu, Jing; Liu, Hao; Nie, Xin-Ran; Chen, Lin; Sun, Qing-Qing; Xia, Yang; Wei Zhang, David

2017-11-01

The continuous scaling and challenges in device integrations in modern portable electronic products have aroused many scientific interests, and a great deal of effort has been made in seeking solutions towards a more microminiaturized package assembled with smaller and more powerful components. In this study, an embedded light-erasable charge-trapping memory with a high-k dielectric stack (Al2O3/HfO2/Al2O3) and an atomically thin MoS2 channel has been fabricated and fully characterized. The memory exhibits a sufficient memory window, fast programming and erasing (P/E) speed, and high On/Off current ratio up to 107. Less than 25% memory window degradation is observed after projected 10-year retention, and the device functions perfectly after 8000 P/E operation cycles. Furthermore, the programmed device can be fully erased by incident light without electrical assistance. Such excellent memory performance originates from the intrinsic properties of two-dimensional (2D) MoS2 and the engineered back-gate dielectric stack. Our integration of 2D semiconductors in the infrastructure of light-erasable charge-trapping memory is very promising for future system-on-panel applications like storage of metadata and flexible imaging arrays.

Controlling the layer localization of gapless states in bilayer graphene with a gate voltage

NASA Astrophysics Data System (ADS)

Jaskólski, W.; Pelc, M.; Bryant, Garnett W.; Chico, Leonor; Ayuela, A.

2018-04-01

Experiments in gated bilayer graphene with stacking domain walls present topological gapless states protected by no-valley mixing. Here we research these states under gate voltages using atomistic models, which allow us to elucidate their origin. We find that the gate potential controls the layer localization of the two states, which switches non-trivially between layers depending on the applied gate voltage magnitude. We also show how these bilayer gapless states arise from bands of single-layer graphene by analyzing the formation of carbon bonds between layers. Based on this analysis we provide a model Hamiltonian with analytical solutions, which explains the layer localization as a function of the ratio between the applied potential and interlayer hopping. Our results open a route for the manipulation of gapless states in electronic devices, analogous to the proposed writing and reading memories in topological insulators.

Anomalous annealing of floating gate errors due to heavy ion irradiation

NASA Astrophysics Data System (ADS)

Yin, Yanan; Liu, Jie; Sun, Youmei; Hou, Mingdong; Liu, Tianqi; Ye, Bing; Ji, Qinggang; Luo, Jie; Zhao, Peixiong

2018-03-01

Using the heavy ions provided by the Heavy Ion Research Facility in Lanzhou (HIRFL), the annealing of heavy-ion induced floating gate (FG) errors in 34 nm and 25 nm NAND Flash memories has been studied. The single event upset (SEU) cross section of FG and the evolution of the errors after irradiation depending on the ion linear energy transfer (LET) values, data pattern and feature size of the device are presented. Different rates of annealing for different ion LET and different pattern are observed in 34 nm and 25 nm memories. The variation of the percentage of different error patterns in 34 nm and 25 nm memories with annealing time shows that the annealing of FG errors induced by heavy-ion in memories will mainly take place in the cells directly hit under low LET ion exposure and other cells affected by heavy ions when the ion LET is higher. The influence of Multiple Cell Upsets (MCUs) on the annealing of FG errors is analyzed. MCUs with high error multiplicity which account for the majority of the errors can induce a large percentage of annealed errors.

Investigation of field induced trapping on floating gates

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1975-01-01

The development of a technology for building electrically alterable read only memories (EAROMs) or reprogrammable read only memories (RPROMs) using a single level metal gate p channel MOS process with all conventional processing steps is outlined. Nonvolatile storage of data is achieved by the use of charged floating gate electrodes. The floating gates are charged by avalanche injection of hot electrodes through gate oxide, and discharged by avalanche injection of hot holes through gate oxide. Three extra diffusion and patterning steps are all that is required to convert a standard p channel MOS process into a nonvolatile memory process. For identification, this nonvolatile memory technology was given the descriptive acronym DIFMOS which stands for Dual Injector, Floating gate MOS.

A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications

NASA Astrophysics Data System (ADS)

Liu, Chunsen; Yan, Xiao; Song, Xiongfei; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2018-05-01

As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 106 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

Analysis of a Memory Device Failure

NASA Technical Reports Server (NTRS)

Nicolas, David P.; Devaney, John; Gores, Mark; Dicken, Howard

1998-01-01

The recent failure of a vintage memory device presented a unique challenge to failure analysts. Normally device layouts, fabrication parameters and other technical information were available to assist the analyst in the analysis. However, this device was out of production for many years and the manufacturer was no longer in business, so the information was not available. To further complicate this analysis, the package leads were all but removed making additional electrical testing difficult. Under these conditions, new and innovative methods were used to analyze the failure. The external visual exam, radiography, PIND, and leak testing were performed with nominal results. Since electrical testing was precluded by the short lead lengths, the device was delidded to expose the internal structures for microscopic examination. No failure mechanism was identified. The available electrical data suggested an ESD or low level EOS type mechanism which left no visible surface damage. Due to parallel electrical paths, electrical probing on the chip failed to locate the failure site. Two non-destructive Scanning Electron Microscopy techniques, CIVA (Charge Induced Voltage Alteration) and EBIC (Electron Beam Induced Current), and a liquid crystal decoration technique which detects localized heating were employed to aid in the analysis. CIVA and EBIC isolated two faults in the input circuitry, and the liquid crystal technique further localized two hot spots in regions on two input gates. Removal of the glassivation and metallization revealed multiple failure sites located in the gate oxide of two input transistors suggesting machine (testing) induced damage.

Fabrication of one-transistor-capacitor structure of nonvolatile TFT ferroelectric RAM devices using Ba(Zr0.1Ti0.9)O3 gated oxide film.

PubMed

Yang, Cheng-Fu; Chen, Kai-Huang; Chen, Ying-Chung; Chang, Ting-Chang

2007-09-01

In this study, the Ba(Zr0.1Ti0.9)O3 (BZ1T9) thin films have been well deposited on the Pt/Ti/SiO2/Si substrate. The optimum radio frequency (RF) deposition parameters are developed, and the BZ1T9 thin films deposition at the optimum parameters have the maximum capacitance and dielectric constant of 4.4 nF and 190. As the applied voltage is increased to 8 V, the remnant polarization and coercive field of BZ1T9 thin films are about 4.5 microC/cm2 and 80 kV/cm. The counterclockwise current hysteresis and memory window of n-channel thin-film transistor property are observed, and that can be used to indicate the switching of ferroelectric polarization of BZ1T9 thin films. One-transistor-capacitor (1TC) structure of BZ1T9 ferroelectric random access memory device using bottom-gate amorphous silicon thin-film transistor was desirable because of the smaller size and better sensitivity. The BZ1T9 ferroelectric RAM devices with channel width = 40 microm and channel length = 8 microm has been successfully fabricated and the ID-VG transfer characteristics also are investigated in this study.

Memory operations in Au nanoparticle single-electron transistors with floating gate electrodes

NASA Astrophysics Data System (ADS)

Azuma, Yasuo; Sakamoto, Masanori; Teranishi, Toshiharu; Majima, Yutaka

2016-11-01

Floating gate memory operations are demonstrated in a single-electron transistor (SET) fabricated by a chemical assembly using the Au nanogap electrodes and the chemisorbed Au nanoparticles. By applying pulse voltages to the control gate, phase shifts were clearly and stably observed both in the Coulomb oscillations and in the Coulomb diamonds. Writing and erasing operations on the floating gate memory were reproducibly observed, and the charges on the floating gate electrodes were maintained for at least 12 h. By considering the capacitance of the floating gate electrode, the number of electrons in the floating gate electrode was estimated as 260. Owing to the stability of the fabricated SET, these writing and erasing operations on the floating gate memory can be applied to reconfigurable SET circuits fabricated by a chemically assembled technique.

Hot-Electron-Induced Device Degradation during Gate-Induced Drain Leakage Stress

NASA Astrophysics Data System (ADS)

Kim, Kwang-Soo; Han, Chang-Hoon; Lee, Jun-Ki; Kim, Dong-Soo; Kim, Hyong-Joon; Shin, Joong-Shik; Lee, Hea-Beoum; Choi, Byoung-Deog

2012-11-01

We studied the interface state generation and electron trapping by hot electrons under gate-induced drain leakage (GIDL) stress in p-type metal oxide semiconductor field-effect transistors (P-MOSFETs), which are used as the high-voltage core circuit of flash memory devices. When negative voltage was applied to a drain in the off-state, a GIDL current was generated, but when high voltage was applied to the drain, electrons had a high energy. The hot electrons produced the interface state and electron trapping. As a result, the threshold voltage shifted and the off-state leakage current (trap-assisted drain junction leakage current) increased. On the other hand, electron trapping mitigated the energy band bending near the drain and thus suppressed the GIDL current generation.

All optical programmable logic array (PLA)

NASA Astrophysics Data System (ADS)

Hiluf, Dawit

2018-03-01

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE PAGES

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.; ...

2015-08-12

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

PubMed Central

Pavunny, Shojan P.; Scott, James F.; Katiyar, Ram S.

2014-01-01

A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k) of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS) specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS), bipolar (Bi) and BiCMOS chips applications, is presented in this review article. PMID:28788589

Radiation Issues and Applications of Floating Gate Memories

NASA Technical Reports Server (NTRS)

Scheick, L. Z.; Nguyen, D. N.

2000-01-01

The radiation effects that affect various systems that comprise floating gate memories are presented. The wear-out degradation results of unirradiated flash memories are compared to irradiated flash memories. The procedure analyzes the failure to write and erase caused by wear-out and degradation of internal charge pump circuits. A method is described for characterizing the radiation effects of the floating gate itself. The rate dependence, stopping power dependence, SEU susceptibility and applications of floating gate in radiation environment are presented. The ramifications for dosimetry and cell failure are discussed as well as for the long term use aspects of non-volatile memories.

Memory in a fractional-order cardiomyocyte model alters properties of alternans and spontaneous activity

NASA Astrophysics Data System (ADS)

Comlekoglu, T.; Weinberg, S. H.

2017-09-01

Cardiac memory is the dependence of electrical activity on the prior history of one or more system state variables, including transmembrane potential (Vm), ionic current gating, and ion concentrations. While prior work has represented memory either phenomenologically or with biophysical detail, in this study, we consider an intermediate approach of a minimal three-variable cardiomyocyte model, modified with fractional-order dynamics, i.e., a differential equation of order between 0 and 1, to account for history-dependence. Memory is represented via both capacitive memory, due to fractional-order Vm dynamics, that arises due to non-ideal behavior of membrane capacitance; and ionic current gating memory, due to fractional-order gating variable dynamics, that arises due to gating history-dependence. We perform simulations for varying Vm and gating variable fractional-orders and pacing cycle length and measure action potential duration (APD) and incidence of alternans, loss of capture, and spontaneous activity. In the absence of ionic current gating memory, we find that capacitive memory, i.e., decreased Vm fractional-order, typically shortens APD, suppresses alternans, and decreases the minimum cycle length (MCL) for loss of capture. However, in the presence of ionic current gating memory, capacitive memory can prolong APD, promote alternans, and increase MCL. Further, we find that reduced Vm fractional order (typically less than 0.75) can drive phase 4 depolarizations that promote spontaneous activity. Collectively, our results demonstrate that memory reproduced by a fractional-order model can play a role in alternans formation and pacemaking, and in general, can greatly increase the range of electrophysiological characteristics exhibited by a minimal model.

Blanket Gate Would Address Blocks Of Memory

NASA Technical Reports Server (NTRS)

Lambe, John; Moopenn, Alexander; Thakoor, Anilkumar P.

1988-01-01

Circuit-chip area used more efficiently. Proposed gate structure selectively allows and restricts access to blocks of memory in electronic neural-type network. By breaking memory into independent blocks, gate greatly simplifies problem of reading from and writing to memory. Since blocks not used simultaneously, share operational amplifiers that prompt and read information stored in memory cells. Fewer operational amplifiers needed, and chip area occupied reduced correspondingly. Cost per bit drops as result.

Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

NASA Astrophysics Data System (ADS)

Park, Hyeonwoo; Teramoto, Akinobu; Kuroda, Rihito; Suwa, Tomoyuki; Sugawa, Shigetoshi

2018-04-01

Localized stress-induced leakage current (SILC) has become a major problem in the reliability of flash memories. To reduce it, clarifying the SILC mechanism is important, and statistical measurement and analysis have to be carried out. In this study, we applied an array test circuit that can measure the SILC distribution of more than 80,000 nMOSFETs with various gate areas at a high speed (within 80 s) and a high accuracy (on the 10-17 A current order). The results clarified that the distributions of localized SILC in different gate areas follow a universal distribution assuming the same SILC defect density distribution per unit area, and the current of localized SILC defects does not scale down with the gate area. Moreover, the distribution of SILC defect density and its dependence on the oxide field for measurement (E OX-Measure) were experimentally determined for fabricated devices.

A hybrid ferroelectric-flash memory cells

NASA Astrophysics Data System (ADS)

Park, Jae Hyo; Byun, Chang Woo; Seok, Ki Hwan; Kim, Hyung Yoon; Chae, Hee Jae; Lee, Sol Kyu; Son, Se Wan; Ahn, Donghwan; Joo, Seung Ki

2014-09-01

A ferroelectric-flash (F-flash) memory cells having a metal-ferroelectric-nitride-oxynitride-silicon structure are demonstrated, and the ferroelectric materials were perovskite-dominated Pb(Zr,Ti)O3 (PZT) crystallized by Pt gate electrode. The PZT thin-film as a blocking layer improves electrical and memorial performance where programming and erasing mechanism are different from the metal-ferroelectric-insulator-semiconductor device or the conventional silicon-oxide-nitride-oxide-silicon device. F-flash cells exhibit not only the excellent electrical transistor performance, having 442.7 cm2 V-1 s-1 of field-effect mobility, 190 mV dec-1 of substhreshold slope, and 8 × 105 on/off drain current ratio, but also a high reliable memory characteristics, having a large memory window (6.5 V), low-operating voltage (0 to -5 V), faster P/E switching speed (50/500 μs), long retention time (>10 years), and excellent fatigue P/E cycle (>105) due to the boosting effect, amplification effect, and energy band distortion of nitride from the large polarization. All these characteristics correspond to the best performances among conventional flash cells reported so far.

SRAM Based Re-programmable FPGA for Space Applications

NASA Technical Reports Server (NTRS)

Wang, J. J.; Sun, J. S.; Cronquist, B. E.; McCollum, J. L.; Speers, T. M.; Plants, W. C.; Katz, R. B.

1999-01-01

An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 micrometers CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I(sub CC)) measured indicates a device tolerance of approximately 50krad(Si).

Push the flash floating gate memories toward the future low energy application

NASA Astrophysics Data System (ADS)

Della Marca, V.; Just, G.; Regnier, A.; Ogier, J.-L.; Simola, R.; Niel, S.; Postel-Pellerin, J.; Lalande, F.; Masoero, L.; Molas, G.

2013-01-01

In this paper the energy consumption of flash floating gate cell, during a channel hot electron operation, is investigated. We characterize the device using different ramp and box pulses on control gate, to find the best solution to have low energy consumption and good cell performances. We use a new dynamic method to measure the drain current absorption in order to evaluate the impact of different bias conditions, and to study the cell behavior. The programming window and the energy consumption are considered as fundamental parameters. Using this dynamic technique, three zones of work are found; it is possible to optimize the drain voltage during the programming operation to minimize the energy consumption. Moreover, the cell's performances are improved using the CHISEL effect, with a reverse body bias. After the study concerning the programming pulses adjusting, we show the results obtained by increasing the channel doping dose parameter. Considering a channel hot electron programming operation, it is important to focus our attention on the bitline leakage consumption contribution. We measured it for the unselected bitline cells, and we show the effects of the lightly doped drain implantation energy on the leakage current. In this way the impact of gate induced drain leakage in band-to-band tunneling regime decreases, improving the cell's performances in a memory array.

MEMORIAL WALK WITH MEMORIALS, TOWARD ENTRANCE GATE. VIEW TO WEST. ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

MEMORIAL WALK WITH MEMORIALS, TOWARD ENTRANCE GATE. VIEW TO WEST. - Rock Island National Cemetery, Rock Island Arsenal, 0.25 mile north of southern tip of Rock Island, Rock Island, Rock Island County, IL

CMOS-compatible spintronic devices: a review

NASA Astrophysics Data System (ADS)

Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

2016-11-01

For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

Study Trapped Charge Distribution in P-Channel Silicon-Oxide-Nitride-Oxide-Silicon Memory Device Using Dynamic Programming Scheme

NASA Astrophysics Data System (ADS)

Li, Fu-Hai; Chiu, Yung-Yueh; Lee, Yen-Hui; Chang, Ru-Wei; Yang, Bo-Jun; Sun, Wein-Town; Lee, Eric; Kuo, Chao-Wei; Shirota, Riichiro

2013-04-01

In this study, we precisely investigate the charge distribution in SiN layer by dynamic programming of channel hot hole induced hot electron injection (CHHIHE) in p-channel silicon-oxide-nitride-oxide-silicon (SONOS) memory device. In the dynamic programming scheme, gate voltage is increased as a staircase with fixed step amplitude, which can prohibits the injection of holes in SiN layer. Three-dimensional device simulation is calibrated and is compared with the measured programming characteristics. It is found, for the first time, that the hot electron injection point quickly traverses from drain to source side synchronizing to the expansion of charged area in SiN layer. As a result, the injected charges quickly spread over on the almost whole channel area uniformly during a short programming period, which will afford large tolerance against lateral trapped charge diffusion by baking.

Improved charge trapping properties by embedded graphene oxide quantum-dots for flash memory application

NASA Astrophysics Data System (ADS)

Jia, Xinlei; Yan, Xiaobing; Wang, Hong; Yang, Tao; Zhou, Zhenyu; Zhao, Jianhui

2018-06-01

In this work, we have investigated two kinds of charge trapping memory devices with Pd/Al2O3/ZnO/SiO2/p-Si and Pd/Al2O3/ZnO/graphene oxide quantum-dots (GOQDs)/ZnO/SiO2/p-Si structure. Compared with the single ZnO sample, the memory window of the ZnO-GOQDs-ZnO sample reaches a larger value (more than doubled) of 2.7 V under the sweeping gate voltage ± 7 V, indicating a better charge storage capability and the significant charge trapping effects by embedding the GOQDs trapping layer. The ZnO-GOQDs-ZnO devices have better date retention properties with the high and low capacitances loss of ˜ 1.1 and ˜ 6.9%, respectively, as well as planar density of the trapped charges of 1.48 × 1012 cm- 2. It is proposed that the GOQDs play an important role in the outstanding memory characteristics due to the deep quantum potential wells and the discrete distribution of the GOQDs. The long date retention time might have resulted from the high potential barrier which suppressed both the back tunneling and the leakage current. Intercalating GOQDs in the memory device is a promising method to realize large memory window, low-power consumption and excellent retention properties.

Magnetoelectric domain wall dynamics and its implications for magnetoelectric memory

DOE PAGES

Belashchenko, K. D.; Tchernyshyov, O.; Kovalev, Alexey A.; ...

2016-03-30

Domain wall dynamics in a magnetoelectric antiferromagnet is analyzed, and its implications for magnetoelectric memory applications are discussed. Cr 2O 3 is used in the estimates of the materials parameters. It is found that the domain wall mobility has a maximum as a function of the electric field due to the gyrotropic coupling induced by it. In Cr 2O 3, the maximal mobility of 0.1 m/(s Oe) is reached at E≈0.06 V/nm. Fields of this order may be too weak to overcome the intrinsic depinning field, which is estimated for B-doped Cr 2O 3. These major drawbacks for device implementationmore » can be overcome by applying a small in-plane shear strain, which blocks the domain wall precession. Domain wall mobility of about 0.7 m/(s Oe) can then be achieved at E = 0.2 V/nm. Furthermore, a split-gate scheme is proposed for the domain-wall controlled bit element; its extension to multiple-gate linear arrays can offer advantages in memory density, programmability, and logic functionality.« less

Deposition and characterization of vanadium oxide based thin films for MOS device applications

NASA Astrophysics Data System (ADS)

Rakshit, Abhishek; Biswas, Debaleen; Chakraborty, Supratic

2018-04-01

Vanadium Oxide films are deposited on Si (100) substrate by reactive RF-sputtering of a pure Vanadium metallic target in an Argon-Oxygen plasma environment. The ratio of partial pressures of Argon to Oxygen in the sputtering-chamber is varied by controlling their respective flow rates and the resultant oxide films are obtained. MOS Capacitor based devices are then fabricated using the deposited oxide films. High frequency Capacitance-Voltage (C-V) and gate current-gate voltage (I-V) measurements reveal a significant dependence of electrical characteristics of the deposited films on their sputtering deposition parameters mainly, the relative content of Argon/Oxygen in the plasma chamber. A noteworthy change in the electrical properties is observed for the films deposited under higher relative oxygen content in the plasma atmosphere. Our results show that reactive sputtering serves as an indispensable deposition-setup for fabricating vanadium oxide based MOS devices tailor-made for Non-Volatile Memory (NVM) applications.

Mechanistic analysis of temperature-dependent current conduction through thin tunnel oxide in n+-polySi/SiO2/n+-Si structures

NASA Astrophysics Data System (ADS)

Samanta, Piyas

2017-09-01

We present a detailed investigation on temperature-dependent current conduction through thin tunnel oxides grown on degenerately doped n-type silicon (n+-Si) under positive bias ( VG ) on heavily doped n-type polycrystalline silicon (n+-polySi) gate in metal-oxide-semiconductor devices. The leakage current measured between 298 and 573 K and at oxide fields ranging from 6 to 10 MV/cm is primarily attributed to Poole-Frenkel (PF) emission of trapped electrons from the neutral electron traps located in the silicon dioxide (SiO2) band gap in addition to Fowler-Nordheim (FN) tunneling of electrons from n+-Si acting as the drain node in FLOating gate Tunnel OXide Electrically Erasable Programmable Read-Only Memory devices. Process-induced neutral electron traps are located at 0.18 eV and 0.9 eV below the SiO2 conduction band. Throughout the temperature range studied here, PF emission current IPF dominates FN electron tunneling current IFN at oxide electric fields Eox between 6 and 10 MV/cm. A physics based new analytical formula has been developed for FN tunneling of electrons from the accumulation layer of degenerate semiconductors at a wide range of temperatures incorporating the image force barrier rounding effect. FN tunneling has been formulated in the framework of Wentzel-Kramers-Brilloiun taking into account the correction factor due to abrupt variation of the energy barrier at the cathode/oxide interface. The effect of interfacial and near-interfacial trapped-oxide charges on FN tunneling has also been investigated in detail at positive VG . The mechanism of leakage current conduction through SiO2 films plays a crucial role in simulation of time-dependent dielectric breakdown of the memory devices and to precisely predict the normal operating field or applied floating gate (FG) voltage for lifetime projection of the devices. In addition, we present theoretical results showing the effect of drain doping concentration on the FG leakage current.

Gate-tunable memristive phenomena mediated by grain boundaries in single-layer MoS2

NASA Astrophysics Data System (ADS)

Sangwan, Vinod K.; Jariwala, Deep; Kim, In Soo; Chen, Kan-Sheng; Marks, Tobin J.; Lauhon, Lincoln J.; Hersam, Mark C.

2015-05-01

Continued progress in high-speed computing depends on breakthroughs in both materials synthesis and device architectures. The performance of logic and memory can be enhanced significantly by introducing a memristor, a two-terminal device with internal resistance that depends on the history of the external bias voltage. State-of-the-art memristors, based on metal-insulator-metal (MIM) structures with insulating oxides, such as TiO2, are limited by a lack of control over the filament formation and external control of the switching voltage. Here, we report a class of memristors based on grain boundaries (GBs) in single-layer MoS2 devices. Specifically, the resistance of GBs emerging from contacts can be easily and repeatedly modulated, with switching ratios up to ˜103 and a dynamic negative differential resistance (NDR). Furthermore, the atomically thin nature of MoS2 enables tuning of the set voltage by a third gate terminal in a field-effect geometry, which provides new functionality that is not observed in other known memristive devices.

Scalable ferroelectric MOS capacitors comprised of single crystalline SrZrxTi1-xO3 on Ge.

NASA Astrophysics Data System (ADS)

Moghadam, Reza; Xiao, Z.-Y.; Ahmadi-Majlan, K.; Grimley, E.; Ong, P. V.; Lebeau, J. M.; Chambers, S. A.; Hong, X.; Sushko, P.; Ngai, J. H.

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to field-effect devices that require very little power to operate, or that possess both logic and memory functionalities. The development of metal-oxide-semiconductor (MOS) capacitors in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel is essential in order to realize such field-effect devices. Here we demonstrate that scalable, ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x = 0.7) that has been epitaxially grown on Ge. Single crystalline SrZrxTi1-xO3 exhibits characteristics that are ideal for a ferroelectric gate material, namely, a type-I band offset with respect to Ge, large coercive fields and polarization that can be enhanced with electric field. The latter characteristic stems from the relaxor nature of SrZrxTi1-xO3. These properties enable MOS capacitors with 5 nm thick SrZrxTi1-xO3 layers to exhibit a nearly 2 V wide hysteretic window in the capacitance-voltage characteristics. The realization of ferroelectric MOS capacitors with technologically relevant gate thicknesses opens the pathway to practical field effect devices. NSF DMR 1508530.

Core-Shell Zn x Cd1- x Se/Zn y Cd1- y Se Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

NASA Astrophysics Data System (ADS)

Al-Amoody, Fuad; Suarez, Ernesto; Rodriguez, Angel; Heller, E.; Huang, Wenli; Jain, F.

2011-08-01

This paper presents a floating quantum dot (QD) gate nonvolatile memory device using high-energy-gap Zn y Cd1- y Se-cladded Zn x Cd1- x Se quantum dots ( y > x) with tunneling layers comprising nearly lattice-matched semiconductors (e.g., ZnS/ZnMgS) on Si channels. Also presented is the fabrication of an electroluminescent (EL) device with embedded cladded ZnCdSe quantum dots. These ZnCdSe quantum dots were embedded between indium tin oxide (ITO) on glass and a top Schottky metal electrode deposited on a thin CsF barrier. These QDs, which were nucleated in a photo-assisted microwave plasma (PMP) metalorganic chemical vapor deposition (MOCVD) reactor, were grown between the source and drain regions on a p-type silicon substrate of the nonvolatile memory device. The composition of QD cladding, which relates to the value of y in Zn y Cd1- y Se, was engineered by the intensity of ultraviolet light, which controlled the incorporation of zinc in ZnCdSe. The QD quality is comparable to those deposited by other methods. Characteristics and modeling of the II-VI quantum dots as well as two diverse types of devices are presented in this paper.

DIFMOS - A floating-gate electrically erasable nonvolatile semiconductor memory technology. [Dual Injector Floating-gate MOS

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1977-01-01

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.

Fredkin and Toffoli Gates Implemented in Oregonator Model of Belousov-Zhabotinsky Medium

NASA Astrophysics Data System (ADS)

Adamatzky, Andrew

A thin-layer Belousov-Zhabotinsky (BZ) medium is a powerful computing device capable for implementing logical circuits, memory, image processors, robot controllers, and neuromorphic architectures. We design the reversible logical gates — Fredkin gate and Toffoli gate — in a BZ medium network of excitable channels with subexcitable junctions. Local control of the BZ medium excitability is an important feature of the gates’ design. An excitable thin-layer BZ medium responds to a localized perturbation with omnidirectional target or spiral excitation waves. A subexcitable BZ medium responds to an asymmetric perturbation by producing traveling localized excitation wave-fragments similar to dissipative solitons. We employ interactions between excitation wave-fragments to perform the computation. We interpret the wave-fragments as values of Boolean variables. The presence of a wave-fragment at a given site of a circuit represents the logical truth, absence of the wave-fragment — logically false. Fredkin gate consists of ten excitable channels intersecting at 11 junctions, eight of which are subexcitable. Toffoli gate consists of six excitable channels intersecting at six junctions, four of which are subexcitable. The designs of the gates are verified using numerical integration of two-variable Oregonator equations.

Memcomputing with membrane memcapacitive systems

NASA Astrophysics Data System (ADS)

Pershin, Y. V.; Traversa, F. L.; Di Ventra, M.

2015-06-01

We show theoretically that networks of membrane memcapacitive systems—capacitors with memory made out of membrane materials—can be used to perform a complete set of logic gates in a massively parallel way by simply changing the external input amplitudes, but not the topology of the network. This polymorphism is an important characteristic of memcomputing (computing with memories) that closely reproduces one of the main features of the brain. A practical realization of these membrane memcapacitive systems, using, e.g., graphene or other 2D materials, would be a step forward towards a solid-state realization of memcomputing with passive devices.

Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

NASA Astrophysics Data System (ADS)

Okamoto, Shin-ichi; Maekawa, Kei-ichi; Kawashima, Yoshiyuki; Shiba, Kazutoshi; Sugiyama, Hideki; Inoue, Masao; Nishida, Akio

2015-04-01

High quality static random access memory (SRAM) for 40-nm embedded MONOS flash memory with split gate (SG-MONOS) was developed. Marginal failure, which results in threshold voltage/drain current tailing and outliers of SRAM transistors, occurs when using a conventional SRAM structure. These phenomena can be explained by not only gate depletion but also partial depletion and percolation path formation in the MOS channel. A stacked poly-Si gate structure can suppress these phenomena and achieve high quality SRAM without any defects in the 6σ level and with high affinity to the 40-nm SG-MONOS process was developed.

Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

NASA Astrophysics Data System (ADS)

Han, Jinhua; Wang, Wei; Ying, Jun; Xie, Wenfa

2014-01-01

An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized.

Body Doping Profile of Select Device to Minimize Program Disturbance in Three-Dimensional Stack NAND Flash Memory

NASA Astrophysics Data System (ADS)

Choe, Byeong-In; Park, Byung-Gook; Lee, Jong-Ho

2013-06-01

The program disturbance characteristic in the three-dimensional (3D) stack NAND flash was analyzed for the first time in terms of string select line (SSL) threshold voltage (Vth) and p-type body doping profile. From the edge word line (W/L) program disturbance, we can observe the boosted channel potential loss as a function of SSL Vth and body doping profile for SSL device. According to simulation work, a high Vth of the SSL device is required to suppress channel leakage during programming. When the body doping of the SSL device is high in the channel, there is a large band bending near the gate edge of the SSL adjacent to the edge W/L cell of boosted cell strings, which generates significantly electron-hole pairs. The generated electrons decreases the boosted channel potential, resulting in increase of program disturbance of the inhibit strings. Through optimization of the body doping profile of the SSL device, both channel leakage and the program disturbance are successfully suppressed for a highly reliable 3D stack NAND flash memory cell operation.

A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device

NASA Astrophysics Data System (ADS)

Szplet, R.; Kalisz, J.; Jachna, Z.

2009-02-01

We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizer's transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second.

Multifunctional graphene optoelectronic devices capable of detecting and storing photonic signals.

PubMed

Jang, Sukjae; Hwang, Euyheon; Lee, Youngbin; Lee, Seungwoo; Cho, Jeong Ho

2015-04-08

The advantages of graphene photodetectors were utilized to design a new multifunctional graphene optoelectronic device. Organic semiconductors, gold nanoparticles (AuNPs), and graphene were combined to fabricate a photodetecting device with a nonvolatile memory function for storing photonic signals. A pentacene organic semiconductor acted as a light absorption layer in the device and provided a high hole photocurrent to the graphene channel. The AuNPs, positioned between the tunneling and blocking dielectric layers, acted as both a charge trap layer and a plasmonic light scatterer, which enable storing of the information about the incident light. The proposed pentacene-graphene-AuNP hybrid photodetector not only performed well as a photodetector in the visible light range, it also was able to store the photonic signal in the form of persistent current. The good photodetection performance resulted from the plasmonics-enabled enhancement of the optical absorption and from the photogating mechanisms in the pentacene. The device provided a photoresponse that depended on the wavelength of incident light; therefore, the signal information (both the wavelength and intensity) of the incident light was effectively committed to memory. The simple process of applying a negative pulse gate voltage could then erase the programmed information. The proposed photodetector with the capacity to store a photonic signal in memory represents a significant step toward the use of graphene in optoelectronic devices.

FPGA cluster for high-performance AO real-time control system

NASA Astrophysics Data System (ADS)

Geng, Deli; Goodsell, Stephen J.; Basden, Alastair G.; Dipper, Nigel A.; Myers, Richard M.; Saunter, Chris D.

2006-06-01

Whilst the high throughput and low latency requirements for the next generation AO real-time control systems have posed a significant challenge to von Neumann architecture processor systems, the Field Programmable Gate Array (FPGA) has emerged as a long term solution with high performance on throughput and excellent predictability on latency. Moreover, FPGA devices have highly capable programmable interfacing, which lead to more highly integrated system. Nevertheless, a single FPGA is still not enough: multiple FPGA devices need to be clustered to perform the required subaperture processing and the reconstruction computation. In an AO real-time control system, the memory bandwidth is often the bottleneck of the system, simply because a vast amount of supporting data, e.g. pixel calibration maps and the reconstruction matrix, need to be accessed within a short period. The cluster, as a general computing architecture, has excellent scalability in processing throughput, memory bandwidth, memory capacity, and communication bandwidth. Problems, such as task distribution, node communication, system verification, are discussed.

Gating of memory encoding of time-delayed cross-frequency MEG networks revealed by graph filtration based on persistent homology

PubMed Central

Hahm, Jarang; Lee, Hyekyoung; Park, Hyojin; Kang, Eunjoo; Kim, Yu Kyeong; Chung, Chun Kee; Kang, Hyejin; Lee, Dong Soo

2017-01-01

To explain gating of memory encoding, magnetoencephalography (MEG) was analyzed over multi-regional network of negative correlations between alpha band power during cue (cue-alpha) and gamma band power during item presentation (item-gamma) in Remember (R) and No-remember (NR) condition. Persistent homology with graph filtration on alpha-gamma correlation disclosed topological invariants to explain memory gating. Instruction compliance (R-hits minus NR-hits) was significantly related to negative coupling between the left superior occipital (cue-alpha) and the left dorsolateral superior frontal gyri (item-gamma) on permutation test, where the coupling was stronger in R than NR. In good memory performers (R-hits minus false alarm), the coupling was stronger in R than NR between the right posterior cingulate (cue-alpha) and the left fusiform gyri (item-gamma). Gating of memory encoding was dictated by inter-regional negative alpha-gamma coupling. Our graph filtration over MEG network revealed these inter-regional time-delayed cross-frequency connectivity serve gating of memory encoding. PMID:28169281

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

NASA Astrophysics Data System (ADS)

Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

2009-08-01

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

Fault-Tolerant Sequencer Using FPGA-Based Logic Designs for Space Applications

DTIC Science & Technology

2013-12-01

Prototype Board SBU single bit upset SDK software development kit SDRAM synchronous dynamic random-access memory SEB single-event burnout ...current VHDL VHSIC hardware description language VHSIC very-high-speed integrated circuits VLSI very-large- scale integration VQFP very...transient pulse, called a single-event transient (SET), or even cause permanent damage to the device in the form of a burnout or gate rupture. The SEE

Al203 thin films on Silicon and Germanium substrates for CMOS and flash memory applications

NASA Astrophysics Data System (ADS)

Gopalan, Sundararaman; Dutta, Shibesh; Ramesh, Sivaramakrishnan; Prathapan, Ragesh; Sreehari G., S.

2017-07-01

As scaling of device dimensions has continued, it has become necessary to replace traditional SiO2 with high dielectric constant materials in the conventional CMOS devices. In addition, use of metal gate electrodes and Germanium substrates may have to be used in order to address leakage and mobility issues. Al2O3 is one of the potential candidates both for CMOS and as a blocking dielectric for Flash memory applications owing to its low leakage. In this study, the effects of sputtering conditions and post-deposition annealing conditions on the electrical and reliability characteristics of MOS capacitors using Al2O3 films on Si and Ge substrates with Aluminium gate electrodes have been presented. It was observed that higher sputtering power resulted in larger flat-band voltage (Vfb) shifts, more hysteresis, higher interface state density (Dit) and a poorer reliability. Wit was also found that while a short duration high temperature annealing improves film characteristics, a long duration anneal even at 800C was found to be detrimental to MOS characteristics. Finally, the electronic conduction mechanism in Al2O3 films was also studied. It was observed that the conduction mechanism varied depending on the annealing condition, thickness of film and electric field.

Nanocrystals embedded in hafnium dioxide-based dielectrics as charge storage nodes of nano-floating gate memory

NASA Astrophysics Data System (ADS)

Lee, Pui Fai

2007-12-01

Nanocrystals (NC) embedded in dielectrics have attracted a great deal of attention recently because they can potentially be applied in nonvolatile, high-speed, high-density and low-power memory devices. This device benefits from a relatively low operating voltage, high endurance, fast write-erase speeds and better immunity to soft errors. The nanocrystal materials suitable for such an application can be either metals or semiconductors. Recent studies have shown that high-k dielectrics, instead of SiO2 , for the tunneling layer in nanocrystal floating gate memory can improve the trade-off between data retention and program efficiency due to the unique band alignment of high-k dielectrics in the programming and retention modes. In this project, HfAlO has been selected as the high- k dielectric for the nanocrystal floating gate memory structure. The trilayer structure (HfAlO/Ge-NC/HfAlO) on Si was fabricated by PLD. Results revealed that relatively low substrate temperature and growth rate are favourable for the formation of smaller-size Ge nanocrystals. Effects of size/density of the Ge nanocrystal, the tunneling and control oxide layer thicknesses and the oxygen partial pressure during their growth on the charge storage and charge retention characteristics have also been studied. The island structure of the Ge nanocrystal suggests that the growth is based on the Volmer-Webber mode. The self-organized Ge nanocrystals so formed were uniform in size (5--20 nm diameter) and distribution with a density approaching 1012--1013cm-2. Flat-band voltage shift (DeltaVFB) of about 3.6 V and good retention property have been achieved. By varying aggregation distance, sputtering gas pressure and ionization power of the nanocluster source, nanoclusters of Ge with different sizes can be formed. The memory effect of the trilayer structure so formed with 10 nm Ge nanoclusters are manifested by the counter-clockwise hysteresis loop in the C-V curves and a maximum flat-band voltage shift of 5.0 V has been achieved. For comparison purposes, metal nanocrystals have also been investigated by utilizing both of the physical deposition methods as mentioned above. Silver (Ag) nanocrystals with size of 10--40 nm have been embedded in HfAlO matrix in the trilayer capacitor structure and a flat-band voltage shift of 2.0 V has been achieved.

Scalable fabrication of nanostructured devices on flexible substrates using additive driven self-assembly and nanoimprint lithography

NASA Astrophysics Data System (ADS)

Watkins, James

2013-03-01

Roll-to-roll (R2R) technologies provide routes for continuous production of flexible, nanostructured materials and devices with high throughput and low cost. We employ additive-driven self-assembly to produce well-ordered polymer/nanoparticle hybrid materials that can serve as active device layers, we use highly filled nanoparticle/polymer hybrids for applications that require tailored dielectric constant or refractive index, and we employ R2R nanoimprint lithography for device scale patterning. Specific examples include the fabrication of flexible floating gate memory and large area films for optical/EM management. Our newly constructed R2R processing facility includes a custom designed, precision R2R UV-assisted nanoimprint lithography (NIL) system and hybrid nanostructured materials coaters.

DefenseLink.mil - Special Report - Travels With Gates

Science.gov Websites

Force in Afghanistan to the NATO and partner-nation defense ministers here today.Story New Memorial Attends NATO Defense Ministers' Conference Gates Tours Netherlands American Cemetery and Memorial MEMORIAL DEDICATION - NATO officials dedicate a memorial to those who have lost their lives in alliance operations

Electrically programmable-erasable In-Ga-Zn-O thin-film transistor memory with atomic-layer-deposited Al{sub 2}O{sub 3}/Pt nanocrystals/Al{sub 2}O{sub 3} gate stack

DOE Office of Scientific and Technical Information (OSTI.GOV)

Qian, Shi-Bing; Zhang, Wen-Peng; Liu, Wen-Jun

Amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) memory is very promising for transparent and flexible system-on-panel displays; however, electrical erasability has always been a severe challenge for this memory. In this article, we demonstrated successfully an electrically programmable-erasable memory with atomic-layer-deposited Al{sub 2}O{sub 3}/Pt nanocrystals/Al{sub 2}O{sub 3} gate stack under a maximal processing temperature of 300 {sup o}C. As the programming voltage was enhanced from 14 to 19 V for a constant pulse of 0.2 ms, the threshold voltage shift increased significantly from 0.89 to 4.67 V. When the programmed device was subjected to an appropriate pulse under negative gatemore » bias, it could return to the original state with a superior erasing efficiency. The above phenomena could be attributed to Fowler-Nordheim tunnelling of electrons from the IGZO channel to the Pt nanocrystals during programming, and inverse tunnelling of the trapped electrons during erasing. In terms of 0.2-ms programming at 16 V and 350-ms erasing at −17 V, a large memory window of 3.03 V was achieved successfully. Furthermore, the memory exhibited stable repeated programming/erasing (P/E) characteristics and good data retention, i.e., for 2-ms programming at 14 V and 250-ms erasing at −14 V, a memory window of 2.08 V was still maintained after 10{sup 3} P/E cycles, and a memory window of 1.1 V was retained after 10{sup 5} s retention time.« less

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2005-01-01

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations.

PubMed

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-27

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

NASA Astrophysics Data System (ADS)

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-01

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

Investigation of multilayer WS2 flakes as charge trapping stack layers in non-volatile memories

NASA Astrophysics Data System (ADS)

Wang, Hong; Ren, Deliang; Lu, Chao; Yan, Xiaobing

2018-06-01

In this study, the non-volatile flash memory devices utilize tungsten sulfide flakes as the charge trapping stack layers were fabricated. The sandwiched structure of Pd/ZHO/WS2/ZHO/WS2/SiO2/Si manifests a memory window of 2.26 V and a high density of trapped charges 4.88 × 1012/cm2 under a ±5 V gate sweeping voltage. Moreover, the data retention results of as-fabricated non-volatile memories demonstrate that the high and low capacitance states are enhanced by 3.81% and 3.11%, respectively, after a measurement duration of 1.20 × 104 s. These remarkable achievements are probably attributed to the defects and band gap of WS2 flakes. Besides, the proposed memory fabrication is not only compatible with CMOS manufacturing processes but also gets rid of the high-temperature annealing process. Overall, this proposed non-volatile memory is highly attractive for low voltage, long data retention applications.

Multi-terminal memtransistors from polycrystalline monolayer molybdenum disulfide

NASA Astrophysics Data System (ADS)

Sangwan, Vinod K.; Lee, Hong-Sub; Bergeron, Hadallia; Balla, Itamar; Beck, Megan E.; Chen, Kan-Sheng; Hersam, Mark C.

2018-02-01

Memristors are two-terminal passive circuit elements that have been developed for use in non-volatile resistive random-access memory and may also be useful in neuromorphic computing. Memristors have higher endurance and faster read/write times than flash memory and can provide multi-bit data storage. However, although two-terminal memristors have demonstrated capacity for basic neural functions, synapses in the human brain outnumber neurons by more than a thousandfold, which implies that multi-terminal memristors are needed to perform complex functions such as heterosynaptic plasticity. Previous attempts to move beyond two-terminal memristors, such as the three-terminal Widrow-Hoff memristor and field-effect transistors with nanoionic gates or floating gates, did not achieve memristive switching in the transistor. Here we report the experimental realization of a multi-terminal hybrid memristor and transistor (that is, a memtransistor) using polycrystalline monolayer molybdenum disulfide (MoS2) in a scalable fabrication process. The two-dimensional MoS2 memtransistors show gate tunability in individual resistance states by four orders of magnitude, as well as large switching ratios, high cycling endurance and long-term retention of states. In addition to conventional neural learning behaviour of long-term potentiation/depression, six-terminal MoS2 memtransistors have gate-tunable heterosynaptic functionality, which is not achievable using two-terminal memristors. For example, the conductance between a pair of floating electrodes (pre- and post-synaptic neurons) is varied by a factor of about ten by applying voltage pulses to modulatory terminals. In situ scanning probe microscopy, cryogenic charge transport measurements and device modelling reveal that the bias-induced motion of MoS2 defects drives resistive switching by dynamically varying Schottky barrier heights. Overall, the seamless integration of a memristor and transistor into one multi-terminal device could enable complex neuromorphic learning and the study of the physics of defect kinetics in two-dimensional materials.

ENTRANCE GATE AND MEMORIAL AVENUE APPROACH, LOOKING INTO CEMETERY WITH ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

ENTRANCE GATE AND MEMORIAL AVENUE APPROACH, LOOKING INTO CEMETERY WITH ADMINISTRATION BUILDING IN BACKGROUND. VIEW TO NORTHWEST. - Mountain Home National Cemetery, Mountain Home, Washington County, TN

Logic computation in phase change materials by threshold and memory switching.

PubMed

Cassinerio, M; Ciocchini, N; Ielmini, D

2013-11-06

Memristors, namely hysteretic devices capable of changing their resistance in response to applied electrical stimuli, may provide new opportunities for future memory and computation, thanks to their scalable size, low switching energy and nonvolatile nature. We have developed a functionally complete set of logic functions including NOR, NAND and NOT gates, each utilizing a single phase-change memristor (PCM) where resistance switching is due to the phase transformation of an active chalcogenide material. The logic operations are enabled by the high functionality of nanoscale phase change, featuring voltage comparison, additive crystallization and pulse-induced amorphization. The nonvolatile nature of memristive states provides the basis for developing reconfigurable hybrid logic/memory circuits featuring low-power and high-speed switching. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Novel nano materials for high performance logic and memory devices

NASA Astrophysics Data System (ADS)

Das, Saptarshi

After decades of relentless progress, the silicon CMOS industry is approaching a stall in device performance for both logic and memory devices due to fundamental scaling limitations. In order to reinforce the accelerating pace, novel materials with unique properties are being proposed on an urgent basis. This list includes one dimensional nanotubes, quasi one dimensional nanowires, two dimensional atomistically thin layered materials like graphene, hexagonal boron nitride and the more recently the rich family of transition metal di-chalcogenides comprising of MoS2, WSe2, WS2 and many more for logic applications and organic and inorganic ferroelectrics, phase change materials and magnetic materials for memory applications. Only time will tell who will win, but exploring these novel materials allow us to revisit the fundamentals and strengthen our understanding which will ultimately be beneficial for high performance device design. While there has been growing interest in two-dimensional (2D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancies due to the lack of a complete picture of their performance potential. The fact that the 2-D layered semiconducting di-chalcogenides need to be connected to the "outside" world in order to capitalize on their ultimate potential immediately emphasizes the importance of a thorough understanding of the contacts. This thesis demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2D material can be harvested. A comprehensive experimental study on the dependence of carrier mobility on the layer thickness of back gated multilayer MoS 2 field effect transistors is also provided. A resistor network model that comprises of Thomas-Fermi charge screening and interlayer coupling is used to explain the non-monotonic trend in the extracted field effect mobility with the layer thickness. The non-monotonic trend suggests that in order to harvest the maximum potential of MoS2 for high performance device applications, a layer thickness in the range of 6-12 nm would be ideal. Finally using scandium contacts on 10nm thick exfoliated MoS2 flakes that are covered by a 15nm ALD grown Al2O3 film, record high mobility of 700cm2/Vs is achieved at room-temperature which is extremely encouraging for the design of high performance logic devices. The destructive nature of the readout process in Ferroelectric Random Access Memories (FeRAMs) is one of the major limiting factors for their wide scale commercialization. Utilizing Ferroelectric Field-Effect Transistor RAM (FeTRAM) instead solves the destructive read out problem, but at the expense of introducing crystalline ferroelectrics that are hard to integrate into CMOS. In order to address these challenges a novel, fully functional, CMOS compatible, One-Transistor-One-Transistor (1T1T) memory cell architecture using an organic ferroelectric -- PVDF-TrFE -- as the memory storage unit (gate oxide) and a silicon nanowire as the memory read out unit (channel material) is proposed and experimentally demonstrated. While evaluating the scaling potential of the above mentioned organic FeTRAM, it is found that the switching time and switching voltage of this organic copolymer PVDF-TrFE exhibits an unexpected scaling behavior as a function of the lateral device dimensions. The phenomenological theory, that explains this abnormal scaling trend, involves in-plane interchain and intrachain interaction of the copolymer - resulting in a power-law dependence of the switching field on the device area (ESW alpha ACH0.1) that is ultimately responsible for the decrease in the switching time and switching voltage. These findings are encouraging since they indicate that scaling the switching voltage and switching time without aggressively scaling the copolymer thickness occurs naturally while scaling the device area -- in this way ultimately improving the packing density and leading towards high performance memory devices.

Intelligent Gate Drive for Fast Switching and Crosstalk Suppression of SiC Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Zheyu; Dix, Jeffery; Wang, Fei Fred

This study presents an intelligent gate drive for silicon carbide (SiC) devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control gate voltages and gate loop impedances of both devices in a phase-leg configuration during different switching transients. Compared to conventional gate drives, the proposed circuit has the capability of accelerating the switching speed of the phase-leg power devices and suppressing the crosstalk to below device limits. Based on Wolfspeed 1200-V SiCmore » MOSFETs, the test results demonstrate the effectiveness of this intelligent gate drive under varying operating conditions. More importantly, the proposed intelligent gate assist circuitry is embedded into a gate drive integrated circuit, offering a simple, compact, and reliable solution for end-users to maximize benefits of SiC devices in actual power electronics applications.« less

Intelligent Gate Drive for Fast Switching and Crosstalk Suppression of SiC Devices

DOE PAGES

Zhang, Zheyu; Dix, Jeffery; Wang, Fei Fred; ...

2017-01-19

This study presents an intelligent gate drive for silicon carbide (SiC) devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control gate voltages and gate loop impedances of both devices in a phase-leg configuration during different switching transients. Compared to conventional gate drives, the proposed circuit has the capability of accelerating the switching speed of the phase-leg power devices and suppressing the crosstalk to below device limits. Based on Wolfspeed 1200-V SiCmore » MOSFETs, the test results demonstrate the effectiveness of this intelligent gate drive under varying operating conditions. More importantly, the proposed intelligent gate assist circuitry is embedded into a gate drive integrated circuit, offering a simple, compact, and reliable solution for end-users to maximize benefits of SiC devices in actual power electronics applications.« less

Nonvolatile memory with Co-SiO2 core-shell nanocrystals as charge storage nodes in floating gate

NASA Astrophysics Data System (ADS)

Liu, Hai; Ferrer, Domingo A.; Ferdousi, Fahmida; Banerjee, Sanjay K.

2009-11-01

In this letter, we reported nanocrystal floating gate memory with Co-SiO2 core-shell nanocrystal charge storage nodes. By using a water-in-oil microemulsion scheme, Co-SiO2 core-shell nanocrystals were synthesized and closely packed to achieve high density matrix in the floating gate without aggregation. The insulator shell also can help to increase the thermal stability of the nanocrystal metal core during the fabrication process to improve memory performance.

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

NASA Astrophysics Data System (ADS)

Jovanović, B.; Brum, R. M.; Torres, L.

2014-04-01

After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

Ion/Ioff ratio enhancement and scalability of gate-all-around nanowire negative-capacitance FET with ferroelectric HfO2

NASA Astrophysics Data System (ADS)

Jang, Kyungmin; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2017-10-01

We have investigated the energy efficiency and scalability of ferroelectric HfO2 (FE:HfO2)-based negative-capacitance field-effect-transistor (NCFET) with gate-all-around (GAA) nanowire (NW) channel structure. Analytic simulation is conducted to characterize NW-NCFET by varying NW diameter and/or thickness of gate insulator as device structural parameters. Due to the negative-capacitance effect and GAA NW channel structure, NW-NCFET is found to have 5× higher Ion/Ioff ratio than classical NW-MOSFET and 2× higher than double-gate (DG) NCFET, which results in wider design window for high Ion/Ioff ratio. To analyze these obtained results from the viewpoint of the device scalability, we have considered constraints regarding very limited device structural spaces to fit by the gate insulator and NW channel for aggresively scaled gate length (Lg) and/or very tight NW pitch. NW-NCFET still has design point with very thinned gate insulator and/or narrowed NW. Therefore, FE:HfO2-based NW-NCFET is applicable to the aggressively scaled technology node of sub-10 nm Lg and to the very tight NW integration of sub-30 nm NW pitch for beyond 7 nm technology. From 2011 to 2014, he engaged in developing high-speed optical transceiver module as an alternative military service in Republic of Korea. His research interest includes the development of steep slope MOSFETs for high energy-efficient operation and ferroelectric HfO2-based semiconductor devices, and fabrication of nanostructured devices. He joined the IBM T.J. Watson Research Center, Yorktown Heights, NY, in 2010, where he worked on advanced CMOS technologies such as FinFET, nanowire FET, SiGe channel and III-V channel. He was also engaged in launching 14 nm SOI FinFET and RMG technology development. Since 2014, he has been an Associate Professor in Institute of Industrial Science, University of Tokyo, Tokyo, Japan, where he has been working on ultralow power transistor and memory technology. Dr. Kobayashi is a member of IEEE and the Japan Society of Applied Physics. Dr. Hiramoto is a fellow of Japan Society of Applied Physics and a member of IEEE and IEICE. He served as the General Chair of Silicon Nanoelectronics Workshop in 2003 and the Program Chair in 1997, 1999, and 2001. He was on Committee of IEDM from 2003 to 2009. He was the Program Chair of Symposium on VLSI Technology in 2013 and was the General Chair in 2015. He is the Program Chair of International Conference on Solid-State Devices and Materials (SSDM) in 2016.

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2011-01-01

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

Investigation of multi-state charge-storage properties of redox-active organic molecules in silicon-molecular hybrid devices for DRAM and Flash applications

NASA Astrophysics Data System (ADS)

Gowda, Srivardhan Shivappa

Molecular electronics has recently spawned a considerable amount of interest with several molecules possessing charge-conduction and charge-storage properties proposed for use in electronic devices. Hybrid silicon-molecular technology has the promise of augmenting the current silicon technology and provide for a transitional path to future molecule-only technology. The focus of this dissertation work has been on developing a class of hybrid silicon-molecular electronic devices for DRAM and Flash memory applications utilizing redox-active molecules. This work exploits the ability of molecules to store charges with single-electron precision at room temperature. The hybrid devices are fabricated by forming self-assembled monolayers of redox-active molecules on Si and oxide (SiO2 and HfO2) surfaces via formation of covalent linkages. The molecules possess discrete quantum states from which electrons can tunnel to the Si substrate at discrete applied voltages (oxidation process, cell write), leaving behind a positively charged layer of molecules. The reduction (erase) process, which is the process of electrons tunneling back from Si to the molecules, neutralizes the positively charged molecular monolayer. Hybrid silicon-molecular capacitor test structures were electrically characterized with an electrolyte gate using cyclic voltammetry (CyV) and impedance spectroscopy (CV) techniques. The redox voltages, kinetics (write/erase speeds) and charge-retention characteristics were found to be strongly dependent on the Si doping type and densities, and ambient light. It was also determined that the redox energy states in the molecules communicate with the valence band of the Si substrate. This allows tuning of write and read states by modulating minority carriers in n- and p-Si substrates. Ultra-thin dielectric tunnel barriers (SiO2, HfO2) were placed between the molecules and the Si substrate to augment charge-retention for Flash memory applications. The redox response was studied as a function of tunnel oxide thickness, dielectric permittivity and energy barrier, and modified Butler-Volmer expressions were postulated to describe the redox kinetics. The speed vs. retention performance of the devices was improved via asymmetric layered tunnel barriers. The properties of molecules can be tailored by molecular design and synthetic chemistry. In this work, it was demonstrated that an alternate route to tune/enhance the properties of the hybrid device is to engineer the substrate (silicon) component. The molecules were attached to diode surfaces to tune redox voltages and improve charge-retention characteristics. N+ pockets embedded in P-Si well were utilized to obtain multiple states from a two-state molecule. The structure was also employed as a characterization tool in investigating the intrinsic properties of the molecules such as lateral conductivity within the monolayer. Redox molecules were also incorporated on an ultra thin gate-oxide of Si MOSFETs with the intent of studying the interaction of redox states with Si MOSFETs. The discrete molecular states were manifested in the drain current and threshold voltage characteristics of the device. This work demonstrates the multi-state modulation of Si-MOSFETs' drain current via redox-active molecular monolayers. Polymeric films of redox-active molecules were incorporated to improve the charge-density (ON/OFF ratio) and these structures may be employed for multi-state, low-voltage Flash memory applications. The most critical aspect of this research effort is to build a reliable and high density solid state memory technology. To this end, efforts were directed towards replacement of the electrolytic gate, which forms an extremely thin insulating double layer (˜10 nm) at the electrolyte-molecule interface, with a combination of an ultra-thin high-K dielectric layer and a metal gate. Several interesting observations were made in the research approaches towards integration and provided valuable insights into the electrolyte-redox systems. In summary, this work provides fundamental insights into the interaction of redox-energy states with silicon substrate and realistic approaches for exploiting the unique properties of the molecules that may enable solutions for nanoscale high density, low-voltage, long retention and multiple bit memory applications.

An Investigation of Quantum Dot Super Lattice Use in Nonvolatile Memory and Transistors

NASA Astrophysics Data System (ADS)

Mirdha, P.; Parthasarathy, B.; Kondo, J.; Chan, P.-Y.; Heller, E.; Jain, F. C.

2018-02-01

Site-specific self-assembled colloidal quantum dots (QDs) will deposit in two layers only on p-type substrate to form a QD superlattice (QDSL). The QDSL structure has been integrated into the floating gate of a nonvolatile memory component and has demonstrated promising results in multi-bit storage, ease of fabrication, and memory retention. Additionally, multi-valued logic devices and circuits have been created by using QDSL structures which demonstrated ternary and quaternary logic. With increasing use of site-specific self-assembled QDSLs, fundamental understanding of silicon and germanium QDSL charge storage capability, self-assembly on specific surfaces, uniform distribution, and mini-band formation has to be understood for successful implementation in devices. In this work, we investigate the differences in electron charge storage by building metal-oxide semiconductor (MOS) capacitors and using capacitance and voltage measurements to quantify the storage capabilities. The self-assembly process and distribution density of the QDSL is done by obtaining atomic force microscopy (AFM) results on line samples. Additionally, we present a summary of the theoretical density of states in each of the QDSLs.

Improved Reading Gate For Vertical-Bloch-Line Memory

NASA Technical Reports Server (NTRS)

Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

1994-01-01

Improved design for reading gate of vertical-Bloch-line magnetic-bubble memory increases reliability of discrimination between binary ones and zeros. Magnetic bubbles that signify binary "1" and "0" produced by applying sufficiently large chopping currents to memory stripes. Bubbles then propagated differentially in bubble sorter. Method of discriminating between ones and zeros more reliable.

Ambipolar nonvolatile memory based on a quantum-dot transistor with a nanoscale floating gate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Che, Yongli; Zhang, Yating, E-mail: yating@tju.edu.cn; Song, Xiaoxian

2016-07-04

Using only solution processing methods, we developed ambipolar quantum-dot (QD) transistor floating-gate memory (FGM) that uses Au nanoparticles as a floating gate. Because of the bipolarity of the active channel of PbSe QDs, the memory could easily trap holes or electrons in the floating gate by programming/erasing (P/E) operations, which could shift the threshold voltage both up and down. As a result, the memory exhibited good programmable memory characteristics: a large memory window (ΔV{sub th} ∼ 15 V) and a long retention time (>10{sup 5 }s). The magnitude of ΔV{sub th} depended on both P/E voltages and the bias voltage (V{sub DS}): ΔV{sub th}more » was a cubic function to V{sub P/E} and linearly depended on V{sub DS}. Therefore, this FGM based on a QD transistor is a promising alternative to its inorganic counterparts owing to its advantages of bipolarity, high mobility, low cost, and large-area production.« less

Radiation-Hardened Solid-State Drive

NASA Technical Reports Server (NTRS)

Sheldon, Douglas J.

2010-01-01

A method is provided for a radiationhardened (rad-hard) solid-state drive for space mission memory applications by combining rad-hard and commercial off-the-shelf (COTS) non-volatile memories (NVMs) into a hybrid architecture. The architecture is controlled by a rad-hard ASIC (application specific integrated circuit) or a FPGA (field programmable gate array). Specific error handling and data management protocols are developed for use in a rad-hard environment. The rad-hard memories are smaller in overall memory density, but are used to control and manage radiation-induced errors in the main, and much larger density, non-rad-hard COTS memory devices. Small amounts of rad-hard memory are used as error buffers and temporary caches for radiation-induced errors in the large COTS memories. The rad-hard ASIC/FPGA implements a variety of error-handling protocols to manage these radiation-induced errors. The large COTS memory is triplicated for protection, and CRC-based counters are calculated for sub-areas in each COTS NVM array. These counters are stored in the rad-hard non-volatile memory. Through monitoring, rewriting, regeneration, triplication, and long-term storage, radiation-induced errors in the large NV memory are managed. The rad-hard ASIC/FPGA also interfaces with the external computer buses.

Synaptic organic transistors with a vacuum-deposited charge-trapping nanosheet

NASA Astrophysics Data System (ADS)

Kim, Chang-Hyun; Sung, Sujin; Yoon, Myung-Han

2016-09-01

Organic neuromorphic devices hold great promise for unconventional signal processing and efficient human-machine interfaces. Herein, we propose novel synaptic organic transistors devised to overcome the traditional trade-off between channel conductance and memory performance. A vacuum-processed, nanoscale metallic interlayer provides an ultra-flat surface for a high-mobility molecular film as well as a desirable degree of charge trapping, allowing for low-temperature fabrication of uniform device arrays on plastic. The device architecture is implemented by widely available electronic materials in combination with conventional deposition methods. Therefore, our results are expected to generate broader interests in incorporation of organic electronics into large-area neuromorphic systems, with potential in gate-addressable complex logic circuits and transparent multifunctional interfaces receiving direct optical and cellular stimulation.

Field-Free Programmable Spin Logics via Chirality-Reversible Spin-Orbit Torque Switching.

PubMed

Wang, Xiao; Wan, Caihua; Kong, Wenjie; Zhang, Xuan; Xing, Yaowen; Fang, Chi; Tao, Bingshan; Yang, Wenlong; Huang, Li; Wu, Hao; Irfan, Muhammad; Han, Xiufeng

2018-06-21

Spin-orbit torque (SOT)-induced magnetization switching exhibits chirality (clockwise or counterclockwise), which offers the prospect of programmable spin-logic devices integrating nonvolatile spintronic memory cells with logic functions. Chirality is usually fixed by an applied or effective magnetic field in reported studies. Herein, utilizing an in-plane magnetic layer that is also switchable by SOT, the chirality of a perpendicular magnetic layer that is exchange-coupled with the in-plane layer can be reversed in a purely electrical way. In a single Hall bar device designed from this multilayer structure, three logic gates including AND, NAND, and NOT are reconfigured, which opens a gateway toward practical programmable spin-logic devices. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Material parameters from frequency dispersion simulation of floating gate memory with Ge nanocrystals in HfO2

NASA Astrophysics Data System (ADS)

Palade, C.; Lepadatu, A. M.; Slav, A.; Lazanu, S.; Teodorescu, V. S.; Stoica, T.; Ciurea, M. L.

2018-01-01

Trilayer memory capacitors with Ge nanocrystals (NCs) floating gate in HfO2 were obtained by magnetron sputtering deposition on p-type Si substrate followed by rapid thermal annealing at relatively low temperature of 600 °C. The frequency dispersion of capacitance and resistance was measured in accumulation regime of Al/HfO2 gate oxide/Ge NCs in HfO2 floating gate/HfO2 tunnel oxide/SiOx/p-Si/Al memory capacitors. For simulation of the frequency dispersion a complex circuit model was used considering an equivalent parallel RC circuit for each layer of the trilayer structure. A series resistance due to metallic contacts and Si substrate was necessary to be included in the model. A very good fit to the experimental data was obtained and the parameters of each layer in the memory capacitor, i.e. capacitances and resistances were determined and in turn the intrinsic material parameters, i.e. dielectric constants and resistivities of layers were evaluated. The results are very important for the study and optimization of the hysteresis behaviour of floating gate memories based on NCs embedded in oxide.

Interface trap of p-type gate integrated AlGaN/GaN heterostructure field effect transistors

NASA Astrophysics Data System (ADS)

Kim, Kyu Sang

2017-09-01

In this work, the impact of trap states at the p-(Al)GaN/AlGaN interface has been investigated for the normally-off mode p-(Al)GaN/AlGaN/GaN heterostructure field-effect transistors (HFETs) by means of frequency dependent conductance. From the current-voltage (I-V) measurement, it was found that the p-AlGaN gate integrated device has higher drain current and lower gate leakage current compared to the p-GaN gate integrated device. We obtained the interface trap density and the characteristic time constant for the p-type gate integrated HFETs under the forward gate voltage of up to 6 V. As a result, the interface trap density (characteristic time constant) of the p-GaN gate device was lower (longer) than that of the p-AlGaN. Furthermore, it was analyzed that the trap state energy level of the p-GaN gate device was located at the shallow level relative to the p-AlGaN gate device, which accounts for different gate leakage current of each devices.

Digital MOS integrated circuits

NASA Astrophysics Data System (ADS)

Elmasry, M. I.

MOS in digital circuit design is considered along with aspects of digital VLSI, taking into account a comparison of MOSFET logic circuits, 1-micrometer MOSFET VLSI technology, a generalized guide for MOSFET miniaturization, processing technologies, novel circuit structures for VLSI, and questions of circuit and system design for VLSI. MOS memory cells and circuits are discussed, giving attention to a survey of high-density dynamic RAM cell concepts, one-device cells for dynamic random-access memories, variable resistance polysilicon for high density CMOS Ram, high performance MOS EPROMs using a stacked-gate cell, and the optimization of the latching pulse for dynamic flip-flop sensors. Programmable logic arrays are considered along with digital signal processors, microprocessors, static RAMs, and dynamic RAMs.

Dual-Gate p-GaN Gate High Electron Mobility Transistors for Steep Subthreshold Slope.

PubMed

Bae, Jong-Ho; Lee, Jong-Ho

2016-05-01

A steep subthreshold slope characteristic is achieved through p-GaN gate HEMT with dual-gate structure. Obtained subthreshold slope is less than 120 μV/dec. Based on the measured and simulated data obtained from single-gate device, breakdown of parasitic floating-base bipolar transistor and floating gate charged with holes are responsible to increase abruptly in drain current. In the dual-gate device, on-current degrades with high temperature but subthreshold slope is not changed. To observe the switching speed of dual-gate device and transient response of drain current are measured. According to the transient responses of drain current, switching speed of the dual-gate device is about 10(-5) sec.

Floating gate memory with charge storage dots array formed by Dps protein modified with site-specific binding peptides

NASA Astrophysics Data System (ADS)

Kamitake, Hiroki; Uenuma, Mutsunori; Okamoto, Naofumi; Horita, Masahiro; Ishikawa, Yasuaki; Yamashita, Ichro; Uraoka, Yukiharu

2015-05-01

We report a nanodot (ND) floating gate memory (NFGM) with a high-density ND array formed by a biological nano process. We utilized two kinds of cage-shaped proteins displaying SiO2 binding peptide (minTBP-1) on their outer surfaces: ferritin and Dps, which accommodate cobalt oxide NDs in their cavities. The diameters of the cobalt NDs were regulated by the cavity sizes of the proteins. Because minTBP-1 is strongly adsorbed on the SiO2 surface, high-density cobalt oxide ND arrays were obtained by a simple spin coating process. The densities of cobalt oxide ND arrays based on ferritin and Dps were 6.8 × 1011 dots cm-2 and 1.2 × 1012 dots cm-2, respectively. After selective protein elimination and embedding in a metal-oxide-semiconductor (MOS) capacitor, the charge capacities of both ND arrays were evaluated by measuring their C-V characteristics. The MOS capacitor embedded with the Dps ND array showed a wider memory window than the device embedded with the ferritin ND array. Finally, we fabricated an NFGM with a high-density ND array based on Dps, and confirmed its competent writing/erasing characteristics and long retention time.

Surface-confined assemblies and polymers for molecular logic.

PubMed

de Ruiter, Graham; van der Boom, Milko E

2011-08-16

Stimuli responsive materials are capable of mimicking the operation characteristics of logic gates such as AND, OR, NOR, and even flip-flops. Since the development of molecular sensors and the introduction of the first AND gate in solution by de Silva in 1993, Molecular (Boolean) Logic and Computing (MBLC) has become increasingly popular. In this Account, we present recent research activities that focus on MBLC with electrochromic polymers and metal polypyridyl complexes on a solid support. Metal polypyridyl complexes act as useful sensors to a variety of analytes in solution (i.e., H(2)O, Fe(2+/3+), Cr(6+), NO(+)) and in the gas phase (NO(x) in air). This information transfer, whether the analyte is present, is based on the reversible redox chemistry of the metal complexes, which are stable up to 200 °C in air. The concurrent changes in the optical properties are nondestructive and fast. In such a setup, the input is directly related to the output and, therefore, can be represented by one-input logic gates. These input-output relationships are extendable for mimicking the diverse functions of essential molecular logic gates and circuits within a set of Boolean algebraic operations. Such a molecular approach towards Boolean logic has yielded a series of proof-of-concept devices: logic gates, multiplexers, half-adders, and flip-flop logic circuits. MBLC is a versatile and, potentially, a parallel approach to silicon circuits: assemblies of these molecular gates can perform a wide variety of logic tasks through reconfiguration of their inputs. Although these developments do not require a semiconductor blueprint, similar guidelines such as signal propagation, gate-to-gate communication, propagation delay, and combinatorial and sequential logic will play a critical role in allowing this field to mature. For instance, gate-to-gate communication by chemical wiring of the gates with metal ions as electron carriers results in the integration of stand-alone systems: the output of one gate is used as the input for another gate. Using the same setup, we were able to display both combinatorial and sequential logic. We have demonstrated MBLC by coupling electrochemical inputs with optical readout, which resulted in various logic architectures built on a redox-active, functionalized surface. Electrochemically operated sequential logic systems such as flip-flops, multivalued logic, and multistate memory could enhance computational power without increasing spatial requirements. Applying multivalued digits in data storage could exponentially increase memory capacity. Furthermore, we evaluate the pros and cons of MBLC and identify targets for future research in this Account. © 2011 American Chemical Society

GATE AND FLANKING FENCE AT ENTRANCE TO MEMORIAL WALK. VIEW ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

GATE AND FLANKING FENCE AT ENTRANCE TO MEMORIAL WALK. VIEW TO NORTHEAST. - Rock Island National Cemetery, Rock Island Arsenal, 0.25 mile north of southern tip of Rock Island, Rock Island, Rock Island County, IL

GETTYSBURG ADDRESS TABLET BESIDE ENTRANCE GATE AT MEMORIAL WALK. VIEW ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

GETTYSBURG ADDRESS TABLET BESIDE ENTRANCE GATE AT MEMORIAL WALK. VIEW TO EAST. - Rock Island National Cemetery, Rock Island Arsenal, 0.25 mile north of southern tip of Rock Island, Rock Island, Rock Island County, IL

Fabrication of Nano-Crossbar Resistive Switching Memory Based on the Copper-Tantalum Pentoxide-Platinum Device Structure

NASA Astrophysics Data System (ADS)

Olga Gneri, Paula; Jardim, Marcos

Resistive switching memory has been of interest lately not only for its simple metal-insulator-metal (MIM) structure but also for its promising ease of scalability an integration into current CMOS technologies like the Field Programmable Gate Arrays and other non-volatile memory applications. There are several resistive switching MIM combinations but under this scope of research, attention will be paid to the bipolar resistive switching characteristics and fabrication of Tantalum Pentaoxide sandwiched between platinum and copper. By changing the polarity of the voltage bias, this metal-insulator-metal (MIM) device can be switched between a high resistive state (OFF) and low resistive state (ON). The change in states is induced by an electrochemical metallization process, which causes a formation or dissolution of Cu metal filamentary paths in the Tantalum Pentaoxide insulator. There is very little thorough experimental information about the Cu-Ta 2O5-Pt switching characteristics when scaled to nanometer dimensions. In this light, the MIM structure was fabricated in a two-dimensional crossbar format. Also, with the limited available resources, a multi-spacer technique was formulated to localize the active device area in this MIM configuration to less than 20nm. This step is important in understanding the switching characteristics and reliability of this structure when scaled to nanometer dimensions.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhu, H. X.; Zhang, T.; Wang, R. X.

A nano-floating gate memory structure based on Ni nanocrystals (NCs) embedded HfO{sub x} film is deposited by means of radio-frequency magnetron sputtering. Microstructure investigations reveal that self-organized Ni-NCs with diameters of 4-8 nm are well dispersed in amorphous HfO{sub x} matrix. Pt/Ni-NCs embedded HfO{sub x}/Si/Ag capacitor structures exhibit voltage-dependent capacitance-voltage hysteresis, and a maximum flat-band voltage shift of 1.5 V, corresponding to a charge storage density of 6.0 × 10{sup 12} electrons/cm{sup 2}, is achieved. These capacitor memory cells exhibit good endurance characteristic up to 4 × 10{sup 4} cycles and excellent retention performance of 10{sup 5} s, fulfilling themore » requirements of next generation non-volatile memory devices. Schottky tunneling is proven to be responsible for electrons tunneling in these capacitors.« less

Voltage-controlled low-energy switching of nanomagnets through Ruderman-Kittel-Kasuya-Yosida interactions for magnetoelectric device applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ghosh, Bahniman, E-mail: bghosh@utexas.edu; Dey, Rik; Register, Leonard F.

2016-07-21

In this article, we consider through simulation low-energy switching of nanomagnets via electrostatically gated inter-magnet Ruderman-Kittel-Kasuya-Yosida (RKKY) interactions on the surface of three-dimensional topological insulators, for possible memory and nonvolatile logic applications. We model the possibility and dynamics of RKKY-based switching of one nanomagnet by coupling to one or more nanomagnets of set orientation. Potential applications to both memory and nonvolatile logic are illustrated. Sub-attojoule switching energies, far below conventional spin transfer torque (STT)-based memories and even below CMOS logic appear possible. Switching times on the order of a few nanoseconds, comparable to times for STT switching, are estimated formore » ferromagnetic nanomagnets, but the approach also appears compatible with the use of antiferromagnets which may allow for faster switching.« less

Charge storage and tunneling mechanism of Ni nanocrystals embedded HfOx film

NASA Astrophysics Data System (ADS)

Zhu, H. X.; Zhang, T.; Wang, R. X.; Zhang, Y. Y.; Li, L. T.; Qiu, X. Y.

2016-05-01

A nano-floating gate memory structure based on Ni nanocrystals (NCs) embedded HfOx film is deposited by means of radio-frequency magnetron sputtering. Microstructure investigations reveal that self-organized Ni-NCs with diameters of 4-8 nm are well dispersed in amorphous HfOx matrix. Pt/Ni-NCs embedded HfOx/Si/Ag capacitor structures exhibit voltage-dependent capacitance-voltage hysteresis, and a maximum flat-band voltage shift of 1.5 V, corresponding to a charge storage density of 6.0 × 1012 electrons/cm2, is achieved. These capacitor memory cells exhibit good endurance characteristic up to 4 × 104 cycles and excellent retention performance of 105 s, fulfilling the requirements of next generation non-volatile memory devices. Schottky tunneling is proven to be responsible for electrons tunneling in these capacitors.

Nanocrystal floating gate memory with solution-processed indium-zinc-tin-oxide channel and colloidal silver nanocrystals

NASA Astrophysics Data System (ADS)

Hu, Quanli; Ha, Sang-Hyub; Lee, Hyun Ho; Yoon, Tae-Sik

2011-12-01

A nanocrystal (NC) floating gate memory with solution-processed indium-zinc-tin-oxide (IZTO) channel and silver (Ag) NCs embedded in thin gate dielectric layer (SiO2(30 nm)/Al2O3(3 nm)) was fabricated. Both the IZTO channel and colloidal Ag NC layers were prepared by spin-coating and subsequent annealing, and dip-coating process, respectively. A threshold voltage shift up to ~0.9 V, corresponding to the electron density of 6.5 × 1011 cm-2, at gate pulsing <=10 V was achieved by the charging of high density NCs. These results present the successful non-volatile memory characteristics of an oxide-semiconductor transistor fabricated through solution processes.

DETAIL OF FENCE FLANKING GATE AT ENTRANCE TO MEMORIAL WALK. ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

DETAIL OF FENCE FLANKING GATE AT ENTRANCE TO MEMORIAL WALK. VIEW TO NORTHEAST. - Rock Island National Cemetery, Rock Island Arsenal, 0.25 mile north of southern tip of Rock Island, Rock Island, Rock Island County, IL

Radiation Effects On Emerging Electronic Materials And Devices

DTIC Science & Technology

2010-01-17

RADIATION EFFECTS ON EMERGING ELECTRONIC MATERIALS AND DEVICES FINAL PERFORMANCE REPORT PREPARED FOR: Kitt Reinhardt AFOSR/NE 875 N...and the other with metal gates and a high-K gate dielectric. These devices were programmed using both back-gate pulse and gate induced drain leakage... metal gate process GIDL method Fig. 1. Sensing margin as a function of total ionizing dose for nMOS 1T-DRAM cells programmed by back-gate pulse and

Redundancy Technology With A Focused Ion Beam

NASA Astrophysics Data System (ADS)

Komano, Haruki; Hashimoto, Kazuhiko; Takigawa, Tadahiro

1989-08-01

Fuse cutting with a focused ion beam to activate redundancy circuits is proposed. In order to verify its potential usefulness, experiments have been performed. Fuse-cutting time was evaluated using aluminum fuses with a thin passivation layer, which are difficult to cut by conventional laser-beam technology due to the material's high reflectivity. The fuse width and thickness were 2 and 0.8 μm, respectively. The fuse was cut in 5 seconds with a 30 keV focused ion beam of 0.3 A/cm2 current density. Since the fuses used in DRAMs will be smaller, their cutting time will become shorter by scanning an ion beam on narrower areas. Moreover, it can be shortened by increasing current density. Fuses for redundancy technology in 256 k CMOS SRAMs were cut with a focused ion beam. The operation of the memories was checked with a memory tester. It was confirmed that memories which had failure cells operated normally after focused-ion-beam fuse-cutting. Focused ion beam irradiation effects upon a device have been studied. When a 30 keV gallium focused ion beam was irradiated near the gate of MOSFETs, a threshold voltage shift was not observed at an ion dose of 0.3 C/cm2 which corresponded to the ion dose in cutting a fuse. However, when irradiated on the gate, a threshold voltage shift was observed at ion doses of more than 8 x 10-4 C/cm2. The voltage shift was caused by the charge of ions within the passivation layer. It is necessary at least not to irradiate a focused ion beam on a device in cutting fuses. It is concluded that the focused-ion-beam method will be advantageous for future redundancy technology application.

Sketched oxide single-electron transistor

NASA Astrophysics Data System (ADS)

Cheng, Guanglei; Siles, Pablo F.; Bi, Feng; Cen, Cheng; Bogorin, Daniela F.; Bark, Chung Wung; Folkman, Chad M.; Park, Jae-Wan; Eom, Chang-Beom; Medeiros-Ribeiro, Gilberto; Levy, Jeremy

2011-06-01

Devices that confine and process single electrons represent an important scaling limit of electronics. Such devices have been realized in a variety of materials and exhibit remarkable electronic, optical and spintronic properties. Here, we use an atomic force microscope tip to reversibly `sketch' single-electron transistors by controlling a metal-insulator transition at the interface of two oxides. In these devices, single electrons tunnel resonantly between source and drain electrodes through a conducting oxide island with a diameter of ~1.5 nm. We demonstrate control over the number of electrons on the island using bottom- and side-gate electrodes, and observe hysteresis in electron occupation that is attributed to ferroelectricity within the oxide heterostructure. These single-electron devices may find use as ultradense non-volatile memories, nanoscale hybrid piezoelectric and charge sensors, as well as building blocks in quantum information processing and simulation platforms.

Real-time field programmable gate array architecture for computer vision

NASA Astrophysics Data System (ADS)

Arias-Estrada, Miguel; Torres-Huitzil, Cesar

2001-01-01

This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low-level image processing. The field programmable gate array (FPGA)-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and it is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on dedicated very- large-scale-integrated devices to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real-time performance are discussed. Some results are presented and discussed.

Origins of Chaos in Autonomous Boolean Networks

NASA Astrophysics Data System (ADS)

Socolar, Joshua; Cavalcante, Hugo; Gauthier, Daniel; Zhang, Rui

2010-03-01

Networks with nodes consisting of ideal Boolean logic gates are known to display either steady states, periodic behavior, or an ultraviolet catastrophe where the number of logic-transition events circulating in the network per unit time grows as a power-law. In an experiment, non-ideal behavior of the logic gates prevents the ultraviolet catastrophe and may lead to deterministic chaos. We identify certain non-ideal features of real logic gates that enable chaos in experimental networks. We find that short-pulse rejection and the asymmetry between the logic states tends to engender periodic behavior. On the other hand, a memory effect termed ``degradation'' can generate chaos. Our results strongly suggest that deterministic chaos can be expected in a large class of experimental Boolean-like networks. Such devices may find application in a variety of technologies requiring fast complex waveforms or flat power spectra. The non-ideal effects identified here also have implications for the statistics of attractors in large complex networks.

1T1R Nonvolatile Memory with Al/TiO₂/Au and Sol-Gel-Processed Insulator for Barium Zirconate Nickelate Gate in Pentacene Thin Film Transistor.

PubMed

Lee, Ke-Jing; Chang, Yu-Chi; Lee, Cheng-Jung; Wang, Li-Wen; Wang, Yeong-Her

2017-12-09

A one-transistor and one-resistor (1T1R) architecture with a resistive random access memory (RRAM) cell connected to an organic thin-film transistor (OTFT) device is successfully demonstrated to avoid the cross-talk issues of only one RRAM cell. The OTFT device, which uses barium zirconate nickelate (BZN) as a dielectric layer, exhibits favorable electrical properties, such as a high field-effect mobility of 5 cm²/Vs, low threshold voltage of -1.1 V, and low leakage current of 10 -12 A, for a driver in the 1T1R operation scheme. The 1T1R architecture with a TiO₂-based RRAM cell connected with a BZN OTFT device indicates a low operation current (10 μA) and reliable data retention (over ten years). This favorable performance of the 1T1R device can be attributed to the additional barrier heights introduced by using Ni (II) acetylacetone as a substitute for acetylacetone, and the relatively low leakage current of a BZN dielectric layer. The proposed 1T1R device with low leakage current OTFT and excellent uniform resistance distribution of RRAM exhibits a good potential for use in practical low-power electronic applications.

Multiplexed charge-locking device for large arrays of quantum devices

NASA Astrophysics Data System (ADS)

Puddy, R. K.; Smith, L. W.; Al-Taie, H.; Chong, C. H.; Farrer, I.; Griffiths, J. P.; Ritchie, D. A.; Kelly, M. J.; Pepper, M.; Smith, C. G.

2015-10-01

We present a method of forming and controlling large arrays of gate-defined quantum devices. The method uses an on-chip, multiplexed charge-locking system and helps to overcome the restraints imposed by the number of wires available in cryostat measurement systems. The device architecture that we describe here utilises a multiplexer-type scheme to lock charge onto gate electrodes. The design allows access to and control of gates whose total number exceeds that of the available electrical contacts and enables the formation, modulation and measurement of large arrays of quantum devices. We fabricate such devices on n-type GaAs/AlGaAs substrates and investigate the stability of the charge locked on to the gates. Proof-of-concept is shown by measurement of the Coulomb blockade peaks of a single quantum dot formed by a floating gate in the device. The floating gate is seen to drift by approximately one Coulomb oscillation per hour.

Analysis of power gating in different hierarchical levels of 2MB cache, considering variation

NASA Astrophysics Data System (ADS)

Jafari, Mohsen; Imani, Mohsen; Fathipour, Morteza

2015-09-01

This article reintroduces power gating technique in different hierarchical levels of static random-access memory (SRAM) design including cell, row, bank and entire cache memory in 16 nm Fin field effect transistor. Different structures of SRAM cells such as 6T, 8T, 9T and 10T are used in design of 2MB cache memory. The power reduction of the entire cache memory employing cell-level optimisation is 99.7% with the expense of area and other stability overheads. The power saving of the cell-level optimisation is 3× (1.2×) higher than power gating in cache (bank) level due to its superior selectivity. The access delay times are allowed to increase by 4% in the same energy delay product to achieve the best power reduction for each supply voltages and optimisation levels. The results show the row-level power gating is the best for optimising the power of the entire cache with lowest drawbacks. Comparisons of cells show that the cells whose bodies have higher power consumption are the best candidates for power gating technique in row-level optimisation. The technique has the lowest percentage of saving in minimum energy point (MEP) of the design. The power gating also improves the variation of power in all structures by at least 70%.

Biophotonic logic devices based on quantum dots and temporally-staggered Förster energy transfer relays

NASA Astrophysics Data System (ADS)

Claussen, Jonathan C.; Algar, W. Russ; Hildebrandt, Niko; Susumu, Kimihiro; Ancona, Mario G.; Medintz, Igor L.

2013-11-01

Integrating photonic inputs/outputs into unimolecular logic devices can provide significantly increased functional complexity and the ability to expand the repertoire of available operations. Here, we build upon a system previously utilized for biosensing to assemble and prototype several increasingly sophisticated biophotonic logic devices that function based upon multistep Förster resonance energy transfer (FRET) relays. The core system combines a central semiconductor quantum dot (QD) nanoplatform with a long-lifetime Tb complex FRET donor and a near-IR organic fluorophore acceptor; the latter acts as two unique inputs for the QD-based device. The Tb complex allows for a form of temporal memory by providing unique access to a time-delayed modality as an alternate output which significantly increases the inherent computing options. Altering the device by controlling the configuration parameters with biologically based self-assembly provides input control while monitoring changes in emission output of all participants, in both a spectral and temporal-dependent manner, gives rise to two input, single output Boolean Logic operations including OR, AND, INHIBIT, XOR, NOR, NAND, along with the possibility of gate transitions. Incorporation of an enzymatic cleavage step provides for a set-reset function that can be implemented repeatedly with the same building blocks and is demonstrated with single input, single output YES and NOT gates. Potential applications for these devices are discussed in the context of their constituent parts and the richness of available signal.

Biophotonic logic devices based on quantum dots and temporally-staggered Förster energy transfer relays.

PubMed

Claussen, Jonathan C; Algar, W Russ; Hildebrandt, Niko; Susumu, Kimihiro; Ancona, Mario G; Medintz, Igor L

2013-12-21

Integrating photonic inputs/outputs into unimolecular logic devices can provide significantly increased functional complexity and the ability to expand the repertoire of available operations. Here, we build upon a system previously utilized for biosensing to assemble and prototype several increasingly sophisticated biophotonic logic devices that function based upon multistep Förster resonance energy transfer (FRET) relays. The core system combines a central semiconductor quantum dot (QD) nanoplatform with a long-lifetime Tb complex FRET donor and a near-IR organic fluorophore acceptor; the latter acts as two unique inputs for the QD-based device. The Tb complex allows for a form of temporal memory by providing unique access to a time-delayed modality as an alternate output which significantly increases the inherent computing options. Altering the device by controlling the configuration parameters with biologically based self-assembly provides input control while monitoring changes in emission output of all participants, in both a spectral and temporal-dependent manner, gives rise to two input, single output Boolean Logic operations including OR, AND, INHIBIT, XOR, NOR, NAND, along with the possibility of gate transitions. Incorporation of an enzymatic cleavage step provides for a set-reset function that can be implemented repeatedly with the same building blocks and is demonstrated with single input, single output YES and NOT gates. Potential applications for these devices are discussed in the context of their constituent parts and the richness of available signal.

Synaptic organic transistors with a vacuum-deposited charge-trapping nanosheet

PubMed Central

Kim, Chang-Hyun; Sung, Sujin; Yoon, Myung-Han

2016-01-01

Organic neuromorphic devices hold great promise for unconventional signal processing and efficient human-machine interfaces. Herein, we propose novel synaptic organic transistors devised to overcome the traditional trade-off between channel conductance and memory performance. A vacuum-processed, nanoscale metallic interlayer provides an ultra-flat surface for a high-mobility molecular film as well as a desirable degree of charge trapping, allowing for low-temperature fabrication of uniform device arrays on plastic. The device architecture is implemented by widely available electronic materials in combination with conventional deposition methods. Therefore, our results are expected to generate broader interests in incorporation of organic electronics into large-area neuromorphic systems, with potential in gate-addressable complex logic circuits and transparent multifunctional interfaces receiving direct optical and cellular stimulation. PMID:27645425

3D Printing of Living Responsive Materials and Devices.

PubMed

Liu, Xinyue; Yuk, Hyunwoo; Lin, Shaoting; Parada, German Alberto; Tang, Tzu-Chieh; Tham, Eléonore; de la Fuente-Nunez, Cesar; Lu, Timothy K; Zhao, Xuanhe

2018-01-01

3D printing has been intensively explored to fabricate customized structures of responsive materials including hydrogels, liquid-crystal elastomers, shape-memory polymers, and aqueous droplets. Herein, a new method and material system capable of 3D-printing hydrogel inks with programed bacterial cells as responsive components into large-scale (3 cm), high-resolution (30 μm) living materials, where the cells can communicate and process signals in a programmable manner, are reported. The design of 3D-printed living materials is guided by quantitative models that account for the responses of programed cells in printed microstructures of hydrogels. Novel living devices are further demonstrated, enabled by 3D printing of programed cells, including logic gates, spatiotemporally responsive patterning, and wearable devices. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

DOE-EPSCoR Final Report Period: September 1, 2008- August 31, 2016

DOE Office of Scientific and Technical Information (OSTI.GOV)

Katiyar, Ram; Gomez, M.; Morell, G.

In this project, multifunctional nanostructured spintronic and magnetoelectric materials were investigated by experimental and computational efforts for applications in energy efficient electronic systems that integrate functionalities and thus have the potential to enable a new generation of faster responding devices and increased integration densities. The team systematically investigated transition metal (TM)-doped ZnO nanostructures, silicide nanorods, magnetoelectric oxides, and ferroelectric/ferromagnetic heterostructures. In what follows, we report the progress made by researchers during the above period in developing and understanding of 1) Spintronics nanostructures; 2) Resistive switching phenomenon in oxides for memory devices; 3) Magnetoelectric multiferroics; 4) Novel high-k gate oxides formore » logic devices; 5) Two dimensional (2D) materials; and 6) Theoretical studies in the above fields.« less

Characterization and metrology implications of the 1997 NTRS

NASA Astrophysics Data System (ADS)

Class, W.; Wortman, J. J.

1998-11-01

In the Front-end (transistor forming) area of silicon CMOS device processing, several NTRS difficult challenges have been identified including; scaled and alternate gate dielectric materials, new DRAM dielectric materials, alternate gate materials, elevated contact structures, engineered channels, and large-area cost-effective silicon substrates. This paper deals with some of the characterization and metrology challenges facing the industry if it is to meet the projected needs identified in the NTRS. In the areas of gate and DRAM dielectric, scaling requires that existing material layers be thinned to maximize capacitance. For the current gate dielectric, SiO2 and its nitrided derivatives, direct tunneling will limit scaling to approximately 1.5nm for logic applications before power losses become unacceptable. Low power logic and memory applications may limit scaling to the 2.0-2.2nm range. Beyond these limits, dielectric materials having higher dielectric constant, will permit continued capacitance increases while allowing for the use of thicker dielectric layers, where tunneling may be minimized. In the near term silicon nitride is a promising SiO2 substitute material while in the longer term "high-k" materials such as tantalum pentoxide and barium strontium titanate (BST) will be required. For these latter materials, it is likely that a multilayer dielectric stack will be needed, consisting of an ultra-thin (1-2 atom layer) interfacial SiO2 layer and a high-k overlayer. Silicon wafer surface preparation control, as well as the control of composition, crystal structure, and thickness for such stacks pose significant characterization and metrology challenges. In addition to the need for new gate dielectric materials, new gate materials will be required to overcome the limitations of the current doped polysilicon gate materials. Such a change has broad ramifications on device electrical performance and manufacturing process robustness which again implies a broad range of new characterization and metrology requirements. Finally, the doped structure of the MOS transistor must scale to very small lateral and depth dimensions, and thermal budgets must be reduced to permit the retention of very abrupt highly doped drain and channel engineered structures. Eventually, the NTRS forecasts the need for an elevated contact structure. Here, there are significant challenges associated with three-dimensional dopant profiling, measurement of dopant activity in ultra-shallow device regions, as well as point defect metrology and characterization.

Self-aligned gated field emission devices using single carbon nanofiber cathodes

NASA Astrophysics Data System (ADS)

Guillorn, M. A.; Melechko, A. V.; Merkulov, V. I.; Hensley, D. K.; Simpson, M. L.; Lowndes, D. H.

2002-11-01

We report on the fabrication and operation of integrated gated field emission devices using single vertically aligned carbon nanofiber (VACNF) cathodes where the gate aperture has been formed using a self-aligned technique based on chemical mechanical polishing. We find that this method for producing gated cathode devices easily achieves structures with gate apertures on the order of 2 mum that show good concentric alignment to the VACNF emitter. The operation of these devices was explored and field emission characteristics that fit well to the Fowler-Nordheim model of emission was demonstrated.

A New Partial Reconfiguration-Based Fault-Injection System to Evaluate SEU Effects in SRAM-Based FPGAs

NASA Astrophysics Data System (ADS)

Sterpone, L.; Violante, M.

2007-08-01

Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in implementing complex system. Unfortunately, SRAM-based FPGAs are extremely sensitive to single event upsets (SEUs) induced by radiation particles. In order to successfully deploy safety- or mission-critical applications, designer need to validate the correctness of the obtained designs. In this paper we describe a system based on partial-reconfiguration for running fault-injection experiments within the configuration memory of SRAM-based FPGAs. The proposed fault-injection system uses the internal configuration capabilities that modern FPGAs offer in order to inject SEU within the configuration memory. Detailed experimental results show that the technique is orders of magnitude faster than previously proposed ones.

A Retina-Like Dual Band Organic Photosensor Array for Filter-Free Near-Infrared-to-Memory Operations.

PubMed

Wang, Hanlin; Liu, Hongtao; Zhao, Qiang; Ni, Zhenjie; Zou, Ye; Yang, Jie; Wang, Lifeng; Sun, Yanqiu; Guo, Yunlong; Hu, Wenping; Liu, Yunqi

2017-08-01

Human eyes use retina photoreceptor cells to absorb and distinguish photons from different wavelengths to construct an image. Mimicry of such a process and extension of its spectral response into the near-infrared (NIR) is indispensable for night surveillance, retinal prosthetics, and medical imaging applications. Currently, NIR organic photosensors demand optical filters to reduce visible interference, thus making filter-free and anti-visible NIR imaging a challenging task. To solve this limitation, a filter-free and conformal, retina-inspired NIR organic photosensor is presented. Featuring an integration of photosensing and floating-gate memory modules, the device possesses an acute color distinguishing capability. In general, the retina-like photosensor transduces NIR (850 nm) into nonvolatile memory and acts as a dynamic photoswitch under green light (550 nm). In doing this, a filter-free but color-distinguishing photosensor is demonstrated that selectively converts NIR optical signals into nonvolatile memory. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Interface engineering and reliability characteristics of hafnium dioxide with poly silicon gate and dual metal (ruthenium-tantalum alloy, ruthenium) gate electrode for beyond 65 nm technology

NASA Astrophysics Data System (ADS)

Kim, Young-Hee

Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is still necessary to understand what is intrinsic we can not change, or what is extrinsic one we can improve.

Controlling Working Memory Operations by Selective Gating: The Roles of Oscillations and Synchrony

PubMed Central

Dipoppa, Mario; Szwed, Marcin; Gutkin, Boris S.

2016-01-01

Working memory (WM) is a primary cognitive function that corresponds to the ability to update, stably maintain, and manipulate short-term memory (ST M) rapidly to perform ongoing cognitive tasks. A prevalent neural substrate of WM coding is persistent neural activity, the property of neurons to remain active after having been activated by a transient sensory stimulus. This persistent activity allows for online maintenance of memory as well as its active manipulation necessary for task performance. WM is tightly capacity limited. Therefore, selective gating of sensory and internally generated information is crucial for WM function. While the exact neural substrate of selective gating remains unclear, increasing evidence suggests that it might be controlled by modulating ongoing oscillatory brain activity. Here, we review experiments and models that linked selective gating, persistent activity, and brain oscillations, putting them in the more general mechanistic context of WM. We do so by defining several operations necessary for successful WM function and then discussing how such operations may be carried out by mechanisms suggested by computational models. We specifically show how oscillatory mechanisms may provide a rapid and flexible active gating mechanism for WM operations. PMID:28154616

Controlling Working Memory Operations by Selective Gating: The Roles of Oscillations and Synchrony.

PubMed

Dipoppa, Mario; Szwed, Marcin; Gutkin, Boris S

2016-01-01

Working memory (WM) is a primary cognitive function that corresponds to the ability to update, stably maintain, and manipulate short-term memory (ST M) rapidly to perform ongoing cognitive tasks. A prevalent neural substrate of WM coding is persistent neural activity , the property of neurons to remain active after having been activated by a transient sensory stimulus. This persistent activity allows for online maintenance of memory as well as its active manipulation necessary for task performance. WM is tightly capacity limited. Therefore, selective gating of sensory and internally generated information is crucial for WM function. While the exact neural substrate of selective gating remains unclear, increasing evidence suggests that it might be controlled by modulating ongoing oscillatory brain activity. Here, we review experiments and models that linked selective gating, persistent activity, and brain oscillations, putting them in the more general mechanistic context of WM. We do so by defining several operations necessary for successful WM function and then discussing how such operations may be carried out by mechanisms suggested by computational models. We specifically show how oscillatory mechanisms may provide a rapid and flexible active gating mechanism for WM operations.

Simulation and parametric analysis of graphene p-n junctions with two rectangular top gates and a single back gate

NASA Astrophysics Data System (ADS)

Nikiforidis, Ioannis; Karafyllidis, Ioannis G.; Dimitrakis, Panagiotis

2018-02-01

Graphene p-n junctions could be the building blocks of future nanoelectronic circuits. While the conductance modulation of graphene p-n junctions formed in devices with one bottom and one top gate have received much attention, there is comparatively little work done on devices with two top gates. Here, we employ tight-bind Hamiltonians and non-equilibrium Green function method to compute in a systematic way the dependence of the conductance of graphene p-n junctions, formed in a device with two top gates, on the device parameters. We present our results in a compact and systematic way, so that the effect of each parameter is clearly shown. Our results show that the device conductance can be effectively modulated, and that graphene devices with two top gates may be used as basic elements in future carbon-based nanoelectronic circuits.

Ferroelectric field-effect transistors based on solution-processed electrochemically exfoliated graphene

NASA Astrophysics Data System (ADS)

Heidler, Jonas; Yang, Sheng; Feng, Xinliang; Müllen, Klaus; Asadi, Kamal

2018-06-01

Memories based on graphene that could be mass produced using low-cost methods have not yet received much attention. Here we demonstrate graphene ferroelectric (dual-gate) field effect transistors. The graphene has been obtained using electrochemical exfoliation of graphite. Field-effect transistors are realized using a monolayer of graphene flakes deposited by the Langmuir-Blodgett protocol. Ferroelectric field effect transistor memories are realized using a random ferroelectric copolymer poly(vinylidenefluoride-co-trifluoroethylene) in a top gated geometry. The memory transistors reveal ambipolar behaviour with both electron and hole accumulation channels. We show that the non-ferroelectric bottom gate can be advantageously used to tune the on/off ratio.

Radiation-hardened optically reconfigurable gate array exploiting holographic memory characteristics

NASA Astrophysics Data System (ADS)

Seto, Daisaku; Watanabe, Minoru

2015-09-01

In this paper, we present a proposal for a radiation-hardened optically reconfigurable gate array (ORGA). The ORGA is a type of field programmable gate array (FPGA). The ORGA configuration can be executed by the exploitation of holographic memory characteristics even if 20% of the configuration data are damaged. Moreover, the optoelectronic technology enables the high-speed reconfiguration of the programmable gate array. Such a high-speed reconfiguration can increase the radiation tolerance of its programmable gate array to 9.3 × 104 times higher than that of current FPGAs. Through experimentation, this study clarified the configuration dependability using the impulse-noise emulation and high-speed configuration capabilities of the ORGA with corrupt configuration contexts. Moreover, the radiation tolerance of the programmable gate array was confirmed theoretically through probabilistic calculation.

Sketched Oxide Single-Electron Transistor

NASA Astrophysics Data System (ADS)

Cheng, Guanglei

2012-02-01

Devices that confine and process single electrons represent an important scaling limit of electronics. Such devices have been realized in a variety of materials and exhibit remarkable electronic, optical and spintronic properties. Here, we use an atomic force microscope tip to reversibly ``sketch'' single-electron transistors by controlling a metal-insulator transition at the interface of two oxides.ootnotetextCheng et al., Nature Nanotechnology 6, 343 (2011). In these devices, single electrons tunnel resonantly between source and drain electrodes through a conducting oxide island with a diameter of ˜1.5 nm. We demonstrate control over the number of electrons on the island using bottom- and side-gate electrodes, and observe hysteresis in electron occupation that is attributed to ferroelectricity within the oxide heterostructure. These single-electron devices may find use as ultradense non-volatile memories, nanoscale hybrid piezoelectric and charge sensors, as well as building blocks in quantum information processing and simulation platforms.

An attention-gating recurrent working memory architecture for emergent speech representation

NASA Astrophysics Data System (ADS)

Elshaw, Mark; Moore, Roger K.; Klein, Michael

2010-06-01

This paper describes an attention-gating recurrent self-organising map approach for emergent speech representation. Inspired by evidence from human cognitive processing, the architecture combines two main neural components. The first component, the attention-gating mechanism, uses actor-critic learning to perform selective attention towards speech. Through this selective attention approach, the attention-gating mechanism controls access to working memory processing. The second component, the recurrent self-organising map memory, develops a temporal-distributed representation of speech using phone-like structures. Representing speech in terms of phonetic features in an emergent self-organised fashion, according to research on child cognitive development, recreates the approach found in infants. Using this representational approach, in a fashion similar to infants, should improve the performance of automatic recognition systems through aiding speech segmentation and fast word learning.

Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong (Inventor); Herath, Jeffrey A. (Inventor)

2010-01-01

An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.

Configurable unitary transformations and linear logic gates using quantum memories.

PubMed

Campbell, G T; Pinel, O; Hosseini, M; Ralph, T C; Buchler, B C; Lam, P K

2014-08-08

We show that a set of optical memories can act as a configurable linear optical network operating on frequency-multiplexed optical states. Our protocol is applicable to any quantum memories that employ off-resonant Raman transitions to store optical information in atomic spins. In addition to the configurability, the protocol also offers favorable scaling with an increasing number of modes where N memories can be configured to implement arbitrary N-mode unitary operations during storage and readout. We demonstrate the versatility of this protocol by showing an example where cascaded memories are used to implement a conditional cz gate.

An electrically reconfigurable logic gate intrinsically enabled by spin-orbit materials.

PubMed

Kazemi, Mohammad

2017-11-10

The spin degree of freedom in magnetic devices has been discussed widely for computing, since it could significantly reduce energy dissipation, might enable beyond Von Neumann computing, and could have applications in quantum computing. For spin-based computing to become widespread, however, energy efficient logic gates comprising as few devices as possible are required. Considerable recent progress has been reported in this area. However, proposals for spin-based logic either require ancillary charge-based devices and circuits in each individual gate or adopt principals underlying charge-based computing by employing ancillary spin-based devices, which largely negates possible advantages. Here, we show that spin-orbit materials possess an intrinsic basis for the execution of logic operations. We present a spin-orbit logic gate that performs a universal logic operation utilizing the minimum possible number of devices, that is, the essential devices required for representing the logic operands. Also, whereas the previous proposals for spin-based logic require extra devices in each individual gate to provide reconfigurability, the proposed gate is 'electrically' reconfigurable at run-time simply by setting the amplitude of the clock pulse applied to the gate. We demonstrate, analytically and numerically with experimentally benchmarked models, that the gate performs logic operations and simultaneously stores the result, realizing the 'stateful' spin-based logic scalable to ultralow energy dissipation.

Cognitive mechanisms associated with auditory sensory gating

PubMed Central

Jones, L.A.; Hills, P.J.; Dick, K.M.; Jones, S.P.; Bright, P.

2016-01-01

Sensory gating is a neurophysiological measure of inhibition that is characterised by a reduction in the P50 event-related potential to a repeated identical stimulus. The objective of this work was to determine the cognitive mechanisms that relate to the neurological phenomenon of auditory sensory gating. Sixty participants underwent a battery of 10 cognitive tasks, including qualitatively different measures of attentional inhibition, working memory, and fluid intelligence. Participants additionally completed a paired-stimulus paradigm as a measure of auditory sensory gating. A correlational analysis revealed that several tasks correlated significantly with sensory gating. However once fluid intelligence and working memory were accounted for, only a measure of latent inhibition and accuracy scores on the continuous performance task showed significant sensitivity to sensory gating. We conclude that sensory gating reflects the identification of goal-irrelevant information at the encoding (input) stage and the subsequent ability to selectively attend to goal-relevant information based on that previous identification. PMID:26716891

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE PAGES

King, M. P.; Wu, X.; Eller, Manfred; ...

2016-12-07

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

King, M. P.; Wu, X.; Eller, Manfred

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2017-06-01

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

Computer vision camera with embedded FPGA processing

NASA Astrophysics Data System (ADS)

Lecerf, Antoine; Ouellet, Denis; Arias-Estrada, Miguel

2000-03-01

Traditional computer vision is based on a camera-computer system in which the image understanding algorithms are embedded in the computer. To circumvent the computational load of vision algorithms, low-level processing and imaging hardware can be integrated in a single compact module where a dedicated architecture is implemented. This paper presents a Computer Vision Camera based on an open architecture implemented in an FPGA. The system is targeted to real-time computer vision tasks where low level processing and feature extraction tasks can be implemented in the FPGA device. The camera integrates a CMOS image sensor, an FPGA device, two memory banks, and an embedded PC for communication and control tasks. The FPGA device is a medium size one equivalent to 25,000 logic gates. The device is connected to two high speed memory banks, an IS interface, and an imager interface. The camera can be accessed for architecture programming, data transfer, and control through an Ethernet link from a remote computer. A hardware architecture can be defined in a Hardware Description Language (like VHDL), simulated and synthesized into digital structures that can be programmed into the FPGA and tested on the camera. The architecture of a classical multi-scale edge detection algorithm based on a Laplacian of Gaussian convolution has been developed to show the capabilities of the system.

Learning to use working memory: a reinforcement learning gating model of rule acquisition in rats

PubMed Central

Lloyd, Kevin; Becker, Nadine; Jones, Matthew W.; Bogacz, Rafal

2012-01-01

Learning to form appropriate, task-relevant working memory representations is a complex process central to cognition. Gating models frame working memory as a collection of past observations and use reinforcement learning (RL) to solve the problem of when to update these observations. Investigation of how gating models relate to brain and behavior remains, however, at an early stage. The current study sought to explore the ability of simple RL gating models to replicate rule learning behavior in rats. Rats were trained in a maze-based spatial learning task that required animals to make trial-by-trial choices contingent upon their previous experience. Using an abstract version of this task, we tested the ability of two gating algorithms, one based on the Actor-Critic and the other on the State-Action-Reward-State-Action (SARSA) algorithm, to generate behavior consistent with the rats'. Both models produced rule-acquisition behavior consistent with the experimental data, though only the SARSA gating model mirrored faster learning following rule reversal. We also found that both gating models learned multiple strategies in solving the initial task, a property which highlights the multi-agent nature of such models and which is of importance in considering the neural basis of individual differences in behavior. PMID:23115551

Impact of gate geometry on ionic liquid gated ionotronic systems

DOE PAGES

Wong, Anthony T.; Noh, Joo Hyon; Pudasaini, Pushpa Raj; ...

2017-01-23

Ionic liquid electrolytes are gaining widespread application as a gate dielectric used to control ion transport in functional materials. This letter systematically examines the important influence that device geometry in standard “side gate” 3-terminal geometries plays in device performance of a well-known oxygen ion conductor. We show that the most influential component of device design is the ratio between the area of the gate electrode and the active channel, while the spacing between these components and their individual shapes has a negligible contribution. Finally, these findings provide much needed guidance in device design intended for ionotronic gating with ionic liquids.

Dual Input AND Gate Fabricated From a Single Channel Poly (3-Hexylthiophene) Thin Film Field Effect Transistor

NASA Technical Reports Server (NTRS)

Pinto, N. J.; Perez, R.; Mueller, C. H.; Theofylaktos, N.; Miranda, F. A.

2006-01-01

A regio-regular poly (3-hexylthiophene) (RRP3HT) thin film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. This device demonstrates AND logic functionality. The device functionality was controlled by applying either 0 or -10 V to each of the gate electrodes. When -10 V was simultaneously applied to both gates, the device was conductive (ON), while any other combination of gate voltages rendered the device resistive (OFF). The p-type carrier charge mobility was about 5x10(exp -4) per square centimeter per V-sec. The low mobility is attributed to the sharp contours of the RRP3HT film due to substrate non-planarity. A significant advantage of this architecture is that AND logic devices with multiple inputs can be fabricated using a single RRP3HT channel with multiple gates.

Remote hardware-reconfigurable robotic camera

NASA Astrophysics Data System (ADS)

Arias-Estrada, Miguel; Torres-Huitzil, Cesar; Maya-Rueda, Selene E.

2001-10-01

In this work, a camera with integrated image processing capabilities is discussed. The camera is based on an imager coupled to an FPGA device (Field Programmable Gate Array) which contains an architecture for real-time computer vision low-level processing. The architecture can be reprogrammed remotely for application specific purposes. The system is intended for rapid modification and adaptation for inspection and recognition applications, with the flexibility of hardware and software reprogrammability. FPGA reconfiguration allows the same ease of upgrade in hardware as a software upgrade process. The camera is composed of a digital imager coupled to an FPGA device, two memory banks, and a microcontroller. The microcontroller is used for communication tasks and FPGA programming. The system implements a software architecture to handle multiple FPGA architectures in the device, and the possibility to download a software/hardware object from the host computer into its internal context memory. System advantages are: small size, low power consumption, and a library of hardware/software functionalities that can be exchanged during run time. The system has been validated with an edge detection and a motion processing architecture, which will be presented in the paper. Applications targeted are in robotics, mobile robotics, and vision based quality control.

100-nm gate lithography for double-gate transistors

NASA Astrophysics Data System (ADS)

Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

2001-09-01

The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

1T1R Nonvolatile Memory with Al/TiO2/Au and Sol-Gel-Processed Insulator for Barium Zirconate Nickelate Gate in Pentacene Thin Film Transistor

PubMed Central

Lee, Ke-Jing; Chang, Yu-Chi; Lee, Cheng-Jung; Wang, Li-Wen; Wang, Yeong-Her

2017-01-01

A one-transistor and one-resistor (1T1R) architecture with a resistive random access memory (RRAM) cell connected to an organic thin-film transistor (OTFT) device is successfully demonstrated to avoid the cross-talk issues of only one RRAM cell. The OTFT device, which uses barium zirconate nickelate (BZN) as a dielectric layer, exhibits favorable electrical properties, such as a high field-effect mobility of 2.5 cm2/Vs, low threshold voltage of −2.8 V, and low leakage current of 10−12 A, for a driver in the 1T1R operation scheme. The 1T1R architecture with a TiO2-based RRAM cell connected with a BZN OTFT device indicates a low operation current (10 μA) and reliable data retention (over ten years). This favorable performance of the 1T1R device can be attributed to the additional barrier heights introduced by using Ni (II) acetylacetone as a substitute for acetylacetone, and the relatively low leakage current of a BZN dielectric layer. The proposed 1T1R device with low leakage current OTFT and excellent uniform resistance distribution of RRAM exhibits a good potential for use in practical low-power electronic applications. PMID:29232828

Auto- and hetero-associative memory using a 2-D optical logic gate

NASA Technical Reports Server (NTRS)

Chao, Tien-Hsin

1989-01-01

An optical associative memory system suitable for both auto- and hetero-associative recall is demonstrated. This system utilizes Hamming distance as the similarity measure between a binary input and a memory image with the aid of a two-dimensional optical EXCLUSIVE OR (XOR) gate and a parallel electronics comparator module. Based on the Hamming distance measurement, this optical associative memory performs a nearest neighbor search and the result is displayed in the output plane in real-time. This optical associative memory is fast and noniterative and produces no output spurious states as compared with that of the Hopfield neural network model.

Auto- and hetero-associative memory using a 2-D optical logic gate

NASA Astrophysics Data System (ADS)

Chao, Tien-Hsin

1989-06-01

An optical associative memory system suitable for both auto- and hetero-associative recall is demonstrated. This system utilizes Hamming distance as the similarity measure between a binary input and a memory image with the aid of a two-dimensional optical EXCLUSIVE OR (XOR) gate and a parallel electronics comparator module. Based on the Hamming distance measurement, this optical associative memory performs a nearest neighbor search and the result is displayed in the output plane in real-time. This optical associative memory is fast and noniterative and produces no output spurious states as compared with that of the Hopfield neural network model.

Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates

NASA Astrophysics Data System (ADS)

Chappanda, K. N.; Ilyas, S.; Younis, M. I.

2018-05-01

Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5  ×  1012 oscillations.

Are biochips the new wave

NASA Astrophysics Data System (ADS)

Bussert, J.

1982-06-01

The possibility of microchip synthesis from molecular configurations is considered. A bistable memory element concept is described which can be independently written on and read, and which consists of a chain of transition metal atoms, a bulging ligand connecting the transition metal atoms, and two types of ligand attached to the transition metal atoms. The molecular emulation of switches, memory and interfaces is presently being investigated independently, although simultaneous synthesis of entire architectures is the ultimate goal of research. Molecular circuitry, which could incorporate 10,000 more gates into an IC chip than chemical techniques, would be of greatest immediate importance in avionics and other portable military electronics devices for which minimum size and weight are valuable. Attention is given to a computer-controlled method for the synthesis of molecular computers.

Optical NAND gate

DOEpatents

Skogen, Erik J [Albuquerque, NM; Raring, James [Goleta, CA; Tauke-Pedretti, Anna [Albuquerque, NM

2011-08-09

An optical NAND gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator and a photodetector. One pair of the optical waveguide devices is electrically connected in parallel to operate as an optical AND gate; and the other pair of the optical waveguide devices is connected in series to operate as an optical NOT gate (i.e. an optical inverter). The optical NAND gate utilizes two digital optical inputs and a continuous light input to provide a NAND function output. The optical NAND gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

Electric bistability induced by incorporating self-assembled monolayers/aggregated clusters of azobenzene derivatives in pentacene-based thin-film transistors.

PubMed

Tseng, Chiao-Wei; Huang, Ding-Chi; Tao, Yu-Tai

2012-10-24

Composite films of pentacene and a series of azobenzene derivatives are prepared and used as the active channel material in top-contact, bottom-gate field-effect transistors. The transistors exhibit high field-effect mobility as well as large I-V hysteresis as a function of the gate bias history. The azobenzene moieties, incorporated either in the form of self-assembled monolayer or discrete multilayer clusters at the dielectric surface, result in electric bistability of the pentacene-based transistor either by photoexcitation or gate biasing. The direction of threshold voltage shifts, size of hysteresis, response time, and retention characteristics all strongly depend on the substituent on the benzene ring. The results show that introducing a monolayer of azobenzene moieties results in formation of charge carrier traps responsible for slower switching between the bistable states and longer retention time. With clusters of azobenzene moieties as the trap sites, the switching is faster but the retention is shorter. Detailed film structure analyses and correlation with the transistor/memory properties of these devices are provided.

All-optical XNOR/NOT logic gates and LATCH based on a reflective vertical cavity semiconductor saturable absorber.

PubMed

Pradhan, Rajib

2014-06-10

This work proposes a scheme of all-optical XNOR/NOT logic gates based on a reflective vertical cavity semiconductor (quantum wells, QWs) saturable absorber (VCSSA). In a semiconductor Fabry-Perot cavity operated with a low-intensity resonance wavelength, both intensity-dependent saturating phase-shift and thermal phase-shift occur, which are considered in the proposed logic operations. The VCSSA-based logics are possible using the saturable behavior of reflectivity under the typical operating conditions. The low-intensity saturable reflectivity is reported for all-optical logic operations where all possible nonlinear phase-shifts are ignored. Here, saturable absorption (SA) and the nonlinear phase-shift-based all-optical XNOR/NOT gates and one-bit memory or LATCH are proposed under new operating conditions. All operations are demonstrated for a VCSSA based on InGaAs/InP QWs. These types of SA-based logic devices can be comfortably used for a signal bit rate of about 10 GHz corresponding to the carrier recovery time of the semiconductor material.

Hetero-Material Gate Doping-Less Tunnel FET and Its Misalignment Effects on Analog/RF Parameters

NASA Astrophysics Data System (ADS)

Anand, Sunny; Sarin, R. K.

2018-03-01

In this paper, with the use of a hetero-material gate technique, a tunnel field-effect transistor (TFET) subject to charge plasma technique is proposed, named as hetero-material gate doping-less tunnel FET (HMG-DLTFET) and a brief study has been done on the effects due to misalignment of the bottom gate towards drain (GMAD) and towards source (GMAS). The proposed devices provide better performance as the drive current increased by three times as compared to conventional doping-less TFET (DLTFET). The results are then analyzed and compared with conventional doped hetero-material gate double-gate tunnel FET (HMG-DGTFET). The analog/radiofrequency (RF) performance has been studied for both devices and comparative analysis has been done for different parameters such as drain current (I D), transconductance (g m), output conductance (g d), total gate capacitance (C gg) and cutoff frequency (f T). Both devices performed similarly in different misalignment configurations. When the bottom gate is perfectly aligned, the best performance is observed for both devices, but the doping-less device gives slightly more freedom for fabrication engineers as the amount of tolerance for HMG-DLTFET is better than that of HMG-DGTFET.

Gate length variation effect on performance of gate-first self-aligned In₀.₅₃Ga₀.₄₇As MOSFET.

PubMed

Mohd Razip Wee, Mohd F; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y

2013-01-01

A multi-gate n-type In₀.₅₃Ga₀.₄₇As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm(2)/Vs are achieved for the gate length and width of 0.2 µm and 30 µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10(-8) A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared.

Gate Length Variation Effect on Performance of Gate-First Self-Aligned In0.53Ga0.47As MOSFET

PubMed Central

Mohd Razip Wee, Mohd F.; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y.

2013-01-01

A multi-gate n-type In0.53Ga0.47As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm2/Vs are achieved for the gate length and width of 0.2 µm and 30µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10−8 A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared. PMID:24367548

Asymmetric underlap optimization of sub-10nm finfets for realizing energy-efficient logic and robust memories

NASA Astrophysics Data System (ADS)

Akkala, Arun Goud

Leakage currents in CMOS transistors have risen dramatically with technology scaling leading to significant increase in standby power consumption. Among the various transistor candidates, the excellent short channel immunity of Silicon double gate FinFETs have made them the best contender for successful scaling to sub-10nm nodes. For sub-10nm FinFETs, new quantum mechanical leakage mechanisms such as direct source to drain tunneling (DSDT) of charge carriers through channel potential energy barrier arising due to proximity of source/drain regions coupled with the high transport direction electric field is expected to dominate overall leakage. To counter the effects of DSDT and worsening short channel effects and to maintain Ion/ Ioff, performance and power consumption at reasonable values, device optimization techniques are necessary for deeply scaled transistors. In this work, source/drain underlapping of FinFETs has been explored using quantum mechanical device simulations as a potentially promising method to lower DSDT while maintaining the Ion/ Ioff ratio at acceptable levels. By adopting a device/circuit/system level co-design approach, it is shown that asymmetric underlapping, where the drain side underlap is longer than the source side underlap, results in optimal energy efficiency for logic circuits in near-threshold as well as standard, super-threshold operating regimes. In addition, read/write conflict in 6T SRAMs and the degradation in cell noise margins due to the low supply voltage can be mitigated by using optimized asymmetric underlapped n-FinFETs for the access transistor, thereby leading to robust cache memories. When gate-workfunction tuning is possible, using asymmetric underlapped n-FinFETs for both access and pull-down devices in an SRAM bit cell can lead to high-speed and low-leakage caches. Further, it is shown that threshold voltage degradation in the presence of Hot Carrier Injection (HCI) is less severe in asymmetric underlap n-FinFETs. A lifetime projection is carried out assuming that HCI is the major degradation mechanism and it is shown that a 3.4x improvement in device lifetime is possible over symmetric underlapped n-FinFET.

Memory operation mechanism of fullerene-containing polymer memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nakajima, Anri, E-mail: anakajima@hiroshima-u.ac.jp; Fujii, Daiki

2015-03-09

The memory operation mechanism in fullerene-containing nanocomposite gate insulators was investigated while varying the kind of fullerene in a polymer gate insulator. It was cleared what kind of traps and which positions in the nanocomposite the injected electrons or holes are stored in. The reason for the difference in the easiness of programming was clarified taking the role of the charging energy of an injected electron into account. The dependence of the carrier dynamics on the kind of fullerene molecule was investigated. A nonuniform distribution of injected carriers occurred after application of a large magnitude programming voltage due to themore » width distribution of the polystyrene barrier between adjacent fullerene molecules. Through the investigations, we demonstrated a nanocomposite gate with fullerene molecules having excellent retention characteristics and a programming capability. This will lead to the realization of practical organic memories with fullerene-containing polymer nanocomposites.« less

Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

NASA Astrophysics Data System (ADS)

An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

2016-11-01

Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ravindran, P; Wui Ann, W; Lim, Y

Purpose: In general, the linear accelerator is gated using respiratory signal obtained by way of external sensors to account for the breathing motion during radiotherapy. One of the commonly used gating devices is the Varian RPM device. Calypso system that uses electromagnetic tracking of implanted or surface transponders could also be used for gating. The aim of this study is to compare the gating efficiency of RPM device and the calypso system by phantom studies. Methods: An ArcCheck insert was used as the phantom with a Gafchromic film placed in its holder. The ArcCheck insert was placed on a Motionmore » Sim platform and moved in the longitudinal direction simulating a respiratory motion with a period of 5 seconds and amplitude of ±6mm. The Gafchromic film was exposed to a 2 × 2cm{sup 2} field, i) with the phantom static, ii) phantom moving but ungated iii) gated with gating window of 2mm and 3mm. This was repeated with Calypso system using surface transponders with the same gating window. The Gafchromic films were read with an EPSON 11000 flatbed scanner and analysed with ‘Medphysto’ software. Results: The full width at half maximum (FWHM) as measured with film at the level of the film holder was 1.65cm when the phantom was static. FWHM measured with phantom moving and without gating was 1.16 cm and penumbra was 7 mm (80–20%) on both sides. When the beam was gated with 2 mm gating window the FWHM was 1.8 cm with RPM device and 1.9 cm with Calypso. Similarly, when the beam was gated with 3 mm window, the FWHM was 1.9cm with RPM device and 2cm with Calypso. Conclusion: This work suggests that the gating efficiency of RPM device is better than that of the Calypso with surface transponder, with reference to the latency in gating.« less

Electrolyte-gated transistors based on conducting polymer nanowire junction arrays.

PubMed

Alam, Maksudul M; Wang, Jun; Guo, Yaoyao; Lee, Stephanie P; Tseng, Hsian-Rong

2005-07-07

In this study, we describe the electrolyte gating and doping effects of transistors based on conducting polymer nanowire electrode junction arrays in buffered aqueous media. Conducting polymer nanowires including polyaniline, polypyrrole, and poly(ethylenedioxythiophene) were investigated. In the presence of a positive gate bias, the device exhibits a large on/off current ratio of 978 for polyaniline nanowire-based transistors; these values vary according to the acidity of the gate medium. We attribute these efficient electrolyte gating and doping effects to the electrochemically fabricated nanostructures of conducting polymer nanowires. This study demonstrates that two-terminal devices can be easily converted into three-terminal transistors by simply immersing the device into an electrolyte solution along with a gate electrode. Here, the field-induced modulation can be applied for signal amplification to enhance the device performance.

Magnetic gates and guides for superconducting vortices

DOE PAGES

Vlasko-Vlasov, V. K.; Colauto, F.; Buzdin, A. I.; ...

2017-04-04

Here, we image the motion of superconducting vortices in niobium film covered with a regular array of thin permalloy stripes. By altering the magnetization orientation in the stripes using a small in-plane magnetic field, we can tune the strength of interactions between vortices and the stripe edges, enabling acceleration or retardation of the superconducting vortices in the sample and consequently introducing strong tunable anisotropy into the vortex dynamics. We discuss our observations in terms of the attraction/repulsion between point magnetic charges carried by vortices and lines of magnetic charges at the stripe edges, and derive analytical formulas for the vortex-magneticmore » stripes coupling. Our approach demonstrates the analogy between the vortex motion regulated by the magnetic stripe array and electric carrier flow in gated semiconducting devices. Scaling down the geometrical features of the proposed design may enable controlled manipulation of single vortices, paving the way for Abrikosov vortex microcircuits and memories.« less

Magnetic gates and guides for superconducting vortices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vlasko-Vlasov, V. K.; Colauto, F.; Buzdin, A. I.

Here, we image the motion of superconducting vortices in niobium film covered with a regular array of thin permalloy stripes. By altering the magnetization orientation in the stripes using a small in-plane magnetic field, we can tune the strength of interactions between vortices and the stripe edges, enabling acceleration or retardation of the superconducting vortices in the sample and consequently introducing strong tunable anisotropy into the vortex dynamics. We discuss our observations in terms of the attraction/repulsion between point magnetic charges carried by vortices and lines of magnetic charges at the stripe edges, and derive analytical formulas for the vortex-magneticmore » stripes coupling. Our approach demonstrates the analogy between the vortex motion regulated by the magnetic stripe array and electric carrier flow in gated semiconducting devices. Scaling down the geometrical features of the proposed design may enable controlled manipulation of single vortices, paving the way for Abrikosov vortex microcircuits and memories.« less

Highly tunable local gate controlled complementary graphene device performing as inverter and voltage controlled resistor.

PubMed

Kim, Wonjae; Riikonen, Juha; Li, Changfeng; Chen, Ya; Lipsanen, Harri

2013-10-04

Using single-layer CVD graphene, a complementary field effect transistor (FET) device is fabricated on the top of separated back-gates. The local back-gate control of the transistors, which operate with low bias at room temperature, enables highly tunable device characteristics due to separate control over electrostatic doping of the channels. Local back-gating allows control of the doping level independently of the supply voltage, which enables device operation with very low VDD. Controllable characteristics also allow the compensation of variation in the unintentional doping typically observed in CVD graphene. Moreover, both p-n and n-p configurations of FETs can be achieved by electrostatic doping using the local back-gate. Therefore, the device operation can also be switched from inverter to voltage controlled resistor, opening new possibilities in using graphene in logic circuitry.

A static induction device manufactured by silicon direct bonding

NASA Astrophysics Data System (ADS)

Chen, Xin'an; Liu, Su; Huang, Qing'an

2004-07-01

It is always a key problem how to improve the gate-source breakdown voltage (VGK) of static induction devices during manufacturing. By using a silicon direct bonding process to replace the high resistivity epitaxy process, a bonding buried gate structure is formed, which is different from an epitaxy buried gate structure. The new structure can improve the gate-source breakdown voltage from the process and the structure. It is shown that the bonding buried gate structure is a promising structure, that can improve the VGK and other performances of devices, by manufacture of a static induction thyristor.

Nonvolatile Ferroelectric Memory Circuit Using Black Phosphorus Nanosheet-Based Field-Effect Transistors with P(VDF-TrFE) Polymer.

PubMed

Lee, Young Tack; Kwon, Hyeokjae; Kim, Jin Sung; Kim, Hong-Hee; Lee, Yun Jae; Lim, Jung Ah; Song, Yong-Won; Yi, Yeonjin; Choi, Won-Kook; Hwang, Do Kyung; Im, Seongil

2015-10-27

Two-dimensional van der Waals (2D vdWs) materials are a class of new materials that can provide important resources for future electronics and materials sciences due to their unique physical properties. Among 2D vdWs materials, black phosphorus (BP) has exhibited significant potential for use in electronic and optoelectronic applications because of its allotropic properties, high mobility, and direct and narrow band gap. Here, we demonstrate a few-layered BP-based nonvolatile memory transistor with a poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric top gate insulator. Experiments showed that our BP-based ferroelectric transistors operate satisfactorily at room temperature in ambient air and exhibit a clear memory window. Unlike conventional ambipolar BP transistors, our ferroelectric transistors showed only p-type characteristics due to the carbon-fluorine (C-F) dipole effect of the P(VDF-TrFE) layer, as well as the highest linear mobility value of 1159 cm(2) V(-1) s(-1) with a 10(3) on/off current ratio. For more advanced memory applications beyond unit memory devices, we implemented two memory inverter circuits, a resistive-load inverter circuit and a complementary inverter circuit, combined with an n-type molybdenum disulfide (MoS2) nanosheet. Our memory inverter circuits displayed a clear memory window of 15 V and memory output voltage efficiency of 95%.

The four-gate transistor

NASA Technical Reports Server (NTRS)

Mojarradi, M. M.; Cristoveanu, S.; Allibert, F.; France, G.; Blalock, B.; Durfrene, B.

2002-01-01

The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

Comparative influence study of gate-formation structuring on Al0.22Ga0.78As/In0.16Ga0.84As/Al0.22Ga0.78As double heterojunction high electron mobility transistors

NASA Astrophysics Data System (ADS)

Hsu, M. K.; Chiu, S. Y.; Wu, C. H.; Guo, D. F.; Lour, W. S.

2008-12-01

Pseudomorphic Al0.22Ga0.78As/In0.16Ga0.84As/Al0.22Ga0.78As double heterojunction high electron mobility transistors (DH-HEMTs) fabricated with different gate-formation structures of a single-recess gate (SRG), a double-recess gate (DRG) and a field-plate gate (FPG) were comparatively investigated. FPG devices show the best breakdown characteristics among these devices due to great reduction in the peak electric field between the drain and gate electrodes. The measured gate-drain breakdown voltages defined at a 1 mA mm-1 reverse gate-drain current density were -15.3, -19.1 and -26.0 V for SRG, DRG and FPG devices, respectively. No significant differences in their room-temperature common-source current-voltage characteristics were observed. However, FPG devices exhibit threshold voltages being the least sensitive to temperature. Threshold voltages as a function of temperature indicate a threshold-voltage variation as low as -0.97 mV K-1 for FPG devices. According to the 2.4 GHz load-pull power measurement at VDS = 3.0 V and VGS = -0.5 V, the saturated output power (POUT), power gain (GP) and maximum power-added efficiency (PAE) were 10.3 dBm/13.2 dB/36.6%, 11.2 dBm/13.1 dB/39.7% and 13.06 dBm/12.8 dB/47.3%, respectively, for SRG, DRG and FPG devices with a pi-gate in class AB operation. When the FPG device is biased at a VDS of 10 V, the saturated power density is more than 600 mW mm-1.

Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement

NASA Astrophysics Data System (ADS)

Raad, Bhagwan Ram; Nigam, Kaushal; Sharma, Dheeraj; Kondekar, P. N.

2016-06-01

This script features a study of bandgap, gate material work function and gate dielectric engineering for enhancement of DC and Analog/RF performance, reduction in the hot carriers effect (HCEs) and drain induced barrier lowering (DIBL) for better device reliability. In this concern, the use of band gap and gate material work function engineering improves the device performance in terms of the ON-state current and suppressed ambipolar behaviour with maintaining the low OFF-state current. With these advantages, the use of gate material work function engineering imposes restriction on the high frequency performance due to increment in the parasitic capacitances and also introduces the hot carrier effects. Hence, the gate dielectric engineering with bandgap and gate material work function engineering are used in this paper to overcome the cons of the gate material work function engineering by obtaining a superior performance in terms of the current driving capability, ambipolar conduction, HCEs, DIBL and high frequency parameters of the device for ultra-low power applications. Finally, the optimization of length for different work function is performed to get the best out of this.

Radiation Effects on Current Field Programmable Technologies

NASA Technical Reports Server (NTRS)

Katz, R.; LaBel, K.; Wang, J. J.; Cronquist, B.; Koga, R.; Penzin, S.; Swift, G.

1997-01-01

Manufacturers of field programmable gate arrays (FPGAS) take different technological and architectural approaches that directly affect radiation performance. Similar y technological and architectural features are used in related technologies such as programmable substrates and quick-turn application specific integrated circuits (ASICs). After analyzing current technologies and architectures and their radiation-effects implications, this paper includes extensive test data quantifying various devices total dose and single event susceptibilities, including performance degradation effects and temporary or permanent re-configuration faults. Test results will concentrate on recent technologies being used in space flight electronic systems and those being developed for use in the near term. This paper will provide the first extensive study of various configuration memories used in programmable devices. Radiation performance limits and their impacts will be discussed for each design. In addition, the interplay between device scaling, process, bias voltage, design, and architecture will be explored. Lastly, areas of ongoing research will be discussed.

Oxide-based materials by atomic layer deposition

NASA Astrophysics Data System (ADS)

Godlewski, Marek; Pietruszka, Rafał; Kaszewski, Jarosław; Witkowski, Bartłomiej S.; Gierałtowska, Sylwia; Wachnicki, Łukasz; Godlewski, Michał M.; Slonska, Anna; Gajewski, Zdzisław

2017-02-01

Thin films of wide band-gap oxides grown by Atomic Layer Deposition (ALD) are suitable for a range of applications. Some of these applications will be presented. First of all, ALD-grown high-k HfO2 is used as a gate oxide in the electronic devices. Moreover, ALD-grown oxides can be used in memory devices, in transparent transistors, or as elements of solar cells. Regarding photovoltaics (PV), ALD-grown thin films of Al2O3 are already used as anti-reflection layers. In addition, thin films of ZnO are tested as replacement of ITO in PV devices. New applications in organic photovoltaics, electronics and optoelectronics are also demonstrated Considering new applications, the same layers, as used in electronics, can also find applications in biology, medicine and in a food industry. This is because layers of high-k oxides show antibacterial activity, as discussed in this work.

In2Ga2ZnO7 oxide semiconductor based charge trap device for NAND flash memory.

PubMed

Hwang, Eun Suk; Kim, Jun Shik; Jeon, Seok Min; Lee, Seung Jun; Jang, Younjin; Cho, Deok-Yong; Hwang, Cheol Seong

2018-04-01

The programming characteristics of charge trap flash memory device adopting amorphous In 2 Ga 2 ZnO 7 (a-IGZO) oxide semiconductors as channel layer were evaluated. Metal-organic chemical vapor deposition (MOCVD) and RF-sputtering processes were used to grow a 45 nm thick a-IGZO layer on a 20 nm thick SiO 2 (blocking oxide)/p ++ -Si (control gate) substrate, where 3 nm thick atomic layer deposited Al 2 O 3 (tunneling oxide) and 5 nm thick low-pressure CVD Si 3 N 4 (charge trap) layers were intervened between the a-IGZO and substrate. Despite the identical stoichiometry and other physicochemical properties of the MOCVD and sputtered a-IGZO, a much faster programming speed of MOCVD a-IGZO was observed. A comparable amount of oxygen vacancies was found in both MOCVD and sputtered a-IGZO, confirmed by x-ray photoelectron spectroscopy and bias-illumination-instability test measurements. Ultraviolet photoelectron spectroscopy analysis revealed a higher Fermi level (E F ) of the MOCVD a-IGZO (∼0.3 eV) film than that of the sputtered a-IGZO, which could be ascribed to the higher hydrogen concentration in the MOCVD a-IGZO film. Since the programming in a flash memory device is governed by the tunneling of electrons from the channel to charge trapping layer, the faster programming performance could be the result of a higher E F of MOCVD a-IGZO.

In2Ga2ZnO7 oxide semiconductor based charge trap device for NAND flash memory

NASA Astrophysics Data System (ADS)

Hwang, Eun Suk; Kim, Jun Shik; Jeon, Seok Min; Lee, Seung Jun; Jang, Younjin; Cho, Deok-Yong; Hwang, Cheol Seong

2018-04-01

The programming characteristics of charge trap flash memory device adopting amorphous In2Ga2ZnO7 (a-IGZO) oxide semiconductors as channel layer were evaluated. Metal-organic chemical vapor deposition (MOCVD) and RF-sputtering processes were used to grow a 45 nm thick a-IGZO layer on a 20 nm thick SiO2 (blocking oxide)/p++-Si (control gate) substrate, where 3 nm thick atomic layer deposited Al2O3 (tunneling oxide) and 5 nm thick low-pressure CVD Si3N4 (charge trap) layers were intervened between the a-IGZO and substrate. Despite the identical stoichiometry and other physicochemical properties of the MOCVD and sputtered a-IGZO, a much faster programming speed of MOCVD a-IGZO was observed. A comparable amount of oxygen vacancies was found in both MOCVD and sputtered a-IGZO, confirmed by x-ray photoelectron spectroscopy and bias-illumination-instability test measurements. Ultraviolet photoelectron spectroscopy analysis revealed a higher Fermi level (E F) of the MOCVD a-IGZO (∼0.3 eV) film than that of the sputtered a-IGZO, which could be ascribed to the higher hydrogen concentration in the MOCVD a-IGZO film. Since the programming in a flash memory device is governed by the tunneling of electrons from the channel to charge trapping layer, the faster programming performance could be the result of a higher E F of MOCVD a-IGZO.

Rapid synthesis and decoration of reduced graphene oxide with gold nanoparticles by thermostable peptides for memory device and photothermal applications.

PubMed

Otari, Sachin V; Kumar, Manoj; Anwar, Muhammad Zahid; Thorat, Nanasaheb D; Patel, Sanjay K S; Lee, Dongjin; Lee, Jai Hyo; Lee, Jung-Kul; Kang, Yun Chan; Zhang, Liaoyuan

2017-09-08

This article presents novel, rapid, and environmentally benign synthesis method for one-step reduction and decoration of graphene oxide with gold nanoparticles (NAuNPs) by using thermostable antimicrobial nisin peptides to form a gold-nanoparticles-reduced graphene oxide (NAu-rGO) nanocomposite. The formed composite material was characterized by UV/Vis spectroscopy, X-ray diffraction, Raman spectroscopy, X-ray photoelectron spectroscopy, field emission scanning electron microscopy, and high-resolution transmission electron microscopy (HR-TEM). HR-TEM analysis revealed the formation of spherical AuNPs of 5-30 nm in size on reduced graphene oxide (rGO) nanosheets. A non-volatile-memory device was prepared based on a solution-processed ZnO thin-film transistor fabricated by inserting the NAu-rGO nanocomposite in the gate dielectric stack as a charge trapping medium. The transfer characteristic of the ZnO thin-film transistor memory device showed large clockwise hysteresis behaviour because of charge carrier trapping in the NAu-rGO nanocomposite. Under positive and negative bias conditions, clear positive and negative threshold voltage shifts occurred, which were attributed to charge carrier trapping and de-trapping in the ZnO/NAu-rGO/SiO 2 structure. Also, the photothermal effect of the NAu-rGO nanocomposites on MCF7 breast cancer cells caused inhibition of ~80% cells after irradiation with infrared light (0.5 W cm -2 ) for 5 min.

EduGATE - basic examples for educative purpose using the GATE simulation platform.

PubMed

Pietrzyk, Uwe; Zakhnini, Abdelhamid; Axer, Markus; Sauerzapf, Sophie; Benoit, Didier; Gaens, Michaela

2013-02-01

EduGATE is a collection of basic examples to introduce students to the fundamental physical aspects of medical imaging devices. It is based on the GATE platform, which has received a wide acceptance in the field of simulating medical imaging devices including SPECT, PET, CT and also applications in radiation therapy. GATE can be configured by commands, which are, for the sake of simplicity, listed in a collection of one or more macro files to set up phantoms, multiple types of sources, detection device, and acquisition parameters. The aim of the EduGATE is to use all these helpful features of GATE to provide insights into the physics of medical imaging by means of a collection of very basic and simple GATE macros in connection with analysis programs based on ROOT, a framework for data processing. A graphical user interface to define a configuration is also included. Copyright © 2012. Published by Elsevier GmbH.

Systems and methods for detecting a failure event in a field programmable gate array

NASA Technical Reports Server (NTRS)

Ng, Tak-Kwong (Inventor); Herath, Jeffrey A. (Inventor)

2009-01-01

An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.

Cobalt germanide nanostructure formation and memory characteristic enhancement in silicon oxide films

NASA Astrophysics Data System (ADS)

Joo, Beom Soo; Kim, Hyunseung; Jang, Seunghun; Han, Dongwoo; Han, Moonsup

2018-08-01

We investigated nano-floating gate memory having a charge trap layer (CTL) composed of cobalt germanide nanostructure (ns-CoGe). A tunneling oxide layer; a CTL containing Co, Ge, and Si; and a blocking oxide layer were sequentially deposited on a p-type silicon substrate by RF magnetron sputtering and low-pressure chemical vapor deposition. We optimized the CTL formation conditions by rapid thermal annealing at a somewhat low temperature (about 830 °C) by considering the differences in Gibbs free energy and chemical enthalpy among the components. To characterize the charge storage properties, capacitance-voltage (C-V) measurements were performed. Further, we used X-ray photoelectron spectroscopy for chemical analysis of the CTL. In this work, we not only report that the C-V measurement shows a remarkable opening of the memory window for the ns-CoGe compared with those of nanostructures composed of Co or Ge alone, but also clarify that the improvement in the memory characteristics originates in the nanostructure formation, which consists mainly of Co-Ge bonds. We expect ns-CoGe to be a strong candidate for fabrication of next-generation memory devices.

Ferroelectric memory based on molybdenum disulfide and ferroelectric hafnium oxide

NASA Astrophysics Data System (ADS)

Yap, Wui Chung; Jiang, Hao; Xia, Qiangfei; Zhu, Wenjuan

Recently, ferroelectric hafnium oxide (HfO2) was discovered as a new type of ferroelectric material with the advantages of high coercive field, excellent scalability (down to 2.5 nm), and good compatibility with CMOS processing. In this work, we demonstrate, for the first time, 2D ferroelectric memories with molybdenum disulfide (MoS2) as the channel material and aluminum doped HfO2 as the ferroelectric gate dielectric. A 16 nm thick layer of HfO2, doped with 5.26% aluminum, was deposited via atomic layer deposition (ALD), then subjected to rapid thermal annealing (RTA) at 1000 °C, and the polarization-voltage characteristics of the resulting metal-ferroelectric-metal (MFM) capacitors were measured, showing a remnant polarization of 0.6 μC/cm2. Ferroelectric memories with embedded ferroelectric hafnium oxide stacks and monolayer MoS2 were fabricated. The transfer characteristics after program and erase pulses revealed a clear ferroelectric memory window. In addition, endurance (up to 10,000 cycles) of the devices were tested and effects associated with ferroelectric materials, such as the wake-up effect and polarization fatigue, were observed. This research can potentially lead to advances of 2D materials in low-power logic and memory applications.

Channel doping concentration and cell program state dependence on random telegraph noise spatial and statistical distribution in 30 nm NAND flash memory

NASA Astrophysics Data System (ADS)

Tomita, Toshihiro; Miyaji, Kousuke

2015-04-01

The dependence of spatial and statistical distribution of random telegraph noise (RTN) in a 30 nm NAND flash memory on channel doping concentration NA and cell program state Vth is comprehensively investigated using three-dimensional Monte Carlo device simulation considering random dopant fluctuation (RDF). It is found that single trap RTN amplitude ΔVth is larger at the center of the channel region in the NAND flash memory, which is closer to the jellium (uniform) doping results since NA is relatively low to suppress junction leakage current. In addition, ΔVth peak at the center of the channel decreases in the higher Vth state due to the current concentration at the shallow trench isolation (STI) edges induced by the high vertical electrical field through the fringing capacitance between the channel and control gate. In such cases, ΔVth distribution slope λ cannot be determined by only considering RDF and single trap.

Capacitorless 1T-DRAM on crystallized poly-Si TFT.

PubMed

Kim, Min Soo; Cho, Won Ju

2011-07-01

The single-transistor dynamic random-access memory (1T-DRAM) using a polycrystalline-silicon thin-film transistor (poly-Si TFT) was investigated. A 100-nm amorphous silicon thin film was deposited onto a 200-nm oxidized silicon wafer via low-pressure chemical vapor deposition (LPCVD), and the amorphous silicon layer was crystallized via eximer laser annealing (ELA) with a KrF source of 248 nm wavelength and 400 mJ/cm2 power. The fabricated capacitor less 1T-DRAM on the poly-Si TFT was evaluated via impact ionization and gate-induced drain leakage (GIDL) current programming. The device showed a clear memory margin between the "1" and "0" states, and as the channel length decreased, a floating body effect which induces a kink effect increases with high mobility. Furthermore, the GIDL current programming showed improved memory properties compared to the impact ionization method. Although the sensing margins and retention times in both program methods are commercially insufficient, it was confirmed the feasibility of the application of 1T-DRAM operation to TFTs.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

PubMed Central

Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

2016-01-01

An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated. PMID:26839036

Large-Area CVD-Grown Sub-2 V ReS2 Transistors and Logic Gates.

PubMed

Dathbun, Ajjiporn; Kim, Youngchan; Kim, Seongchan; Yoo, Youngjae; Kang, Moon Sung; Lee, Changgu; Cho, Jeong Ho

2017-05-10

We demonstrated the fabrication of large-area ReS 2 transistors and logic gates composed of a chemical vapor deposition (CVD)-grown multilayer ReS 2 semiconductor channel and graphene electrodes. Single-layer graphene was used as the source/drain and coplanar gate electrodes. An ion gel with an ultrahigh capacitance effectively gated the ReS 2 channel at a low voltage, below 2 V, through a coplanar gate. The contact resistance of the ion gel-gated ReS 2 transistors with graphene electrodes decreased dramatically compared with the SiO 2 -devices prepared with Cr electrodes. The resulting transistors exhibited good device performances, including a maximum electron mobility of 0.9 cm 2 /(V s) and an on/off current ratio exceeding 10 4 . NMOS logic devices, such as NOT, NAND, and NOR gates, were assembled using the resulting transistors as a proof of concept demonstration of the applicability of the devices to complex logic circuits. The large-area synthesis of ReS 2 semiconductors and graphene electrodes and their applications in logic devices open up new opportunities for realizing future flexible electronics based on 2D nanomaterials.

Numerical model of a single nanocrystal devoted to the study of disordered nanocrystal floating gates of new flash memories

NASA Astrophysics Data System (ADS)

Leroy, Yann; Armeanu, Dumitru; Cordan, Anne-Sophie

2011-05-01

The improvement of our model concerning a single nanocrystal that belongs to a nanocrystal floating gate of a flash memory is presented. In order to extend the gate voltage range applicability of the model, the 3D continuum of states of either metallic or semiconducting electrodes is discretized into 2D subbands. Such an approach gives precise information about the mechanisms behind the charging or release processes of the nanocrystal. Then, the self-energy and screening effects of an electron within the nanocrystal are evaluated and introduced in the model. This enables a better determination of the operating point of the nanocrystal memory. The impact of those improvements on the charging or release time of the nanocrystal is discussed.

Performance Evaluation and Improvement of Ferroelectric Field-Effect Transistor Memory

NASA Astrophysics Data System (ADS)

Yu, Hyung Suk

Flash memory is reaching scaling limitations rapidly due to reduction of charge in floating gates, charge leakage and capacitive coupling between cells which cause threshold voltage fluctuations, short retention times, and interference. Many new memory technologies are being considered as alternatives to flash memory in an effort to overcome these limitations. Ferroelectric Field-Effect Transistor (FeFET) is one of the main emerging candidates because of its structural similarity to conventional FETs and fast switching speed. Nevertheless, the performance of FeFETs have not been systematically compared and analyzed against other competing technologies. In this work, we first benchmark the intrinsic performance of FeFETs and other memories by simulations in order to identify the strengths and weaknesses of FeFETs. To simulate realistic memory applications, we compare memories on an array structure. For the comparisons, we construct an accurate delay model and verify it by benchmarking against exact HSPICE simulations. Second, we propose an accurate model for FeFET memory window since the existing model has limitations. The existing model assumes symmetric operation voltages but it is not valid for the practical asymmetric operation voltages. In this modeling, we consider practical operation voltages and device dimensions. Also, we investigate realistic changes of memory window over time and retention time of FeFETs. Last, to improve memory window and subthreshold swing, we suggest nonplanar junctionless structures for FeFETs. Using the suggested structures, we study the dimensional dependences of crucial parameters like memory window and subthreshold swing and also analyze key interference mechanisms.

Dynamic Observation of Brain-Like Learning in a Ferroelectric Synapse Device

NASA Astrophysics Data System (ADS)

Nishitani, Yu; Kaneko, Yukihiro; Ueda, Michihito; Fujii, Eiji; Tsujimura, Ayumu

2013-04-01

A brain-like learning function was implemented in an electronic synapse device using a ferroelectric-gate field effect transistor (FeFET). The FeFET was a bottom-gate type FET with a ZnO channel and a ferroelectric Pb(Zr,Ti)O3 (PZT) gate insulator. The synaptic weight, which is represented by the channel conductance of the FeFET, is updated by applying a gate voltage through a change in the ferroelectric polarization in the PZT. A learning function based on the symmetric spike-timing dependent synaptic plasticity was implemented in the synapse device using the multilevel weight update by applying a pulse gate voltage. The dynamic weighting and learning behavior in the synapse device was observed as a change in the membrane potential in a spiking neuron circuit.

Direct growth of graphene-dielectric bi-layer structure on device substrates from Si-based polymer

NASA Astrophysics Data System (ADS)

Seo, Hong-Kyu; Kim, Kyunghun; Min, Sung-Yong; Lee, Yeongjun; Eon Park, Chan; Raj, Rishi; Lee, Tae-Woo

2017-06-01

To facilitate the utilization of graphene films in conventional semiconducting devices (e.g. transistors and memories) which includes an insulating layer such as gate dielectric, facile synthesis of bi-layers composed of a graphene film and an insulating layer by one-step thermal conversion will be very important. We demonstrate a simple, inexpensive, scalable and patternable process to synthesize graphene-dielectric bi-layer films from solution-processed polydimethylsiloxane (PDMS) under a Ni capping layer. This method fabricates graphene-dielectric bi-layer structure simultaneously directly on substrate by thermal conversion of PDMS without using additional graphene transfer and patterning process or formation of an expensive dielectric layer, which makes the device fabrication process much easier. The graphene-dielectric bi-layer on a conducting substrate was used in bottom-contact pentacene field-effect transistors that showed ohmic contact and small hysteresis. Our new method will provide a way to fabricate flexible electronic devices simply and inexpensively.

UVPROM dosimetry, microdosimetry and applications to SEU and extreme value theory

NASA Astrophysics Data System (ADS)

Scheick, Leif Zebediah

A new method is described for characterizing a device in terms of the statistical distribution of first failures. The method is based on the erasure of a commercial Ultra- Violet erasable Programmable Read Only Memory (UVPROM). The method of readout would be used on a spacecraft or in other restrictive radiation environments. The measurement of the charge remaining on the floating gate is used to determine absorbed dose. The method of determining dose does not require the detector to be destroyed or erased nor does it effect the ability for taking further measurements. This is compared to extreme value theory applied to the statistical distributions that apply to this device. This technique predicts the threshold of Single Event Effects (SEE), like anomalous changes in erasure time in programmable devices due to high microdose energy-deposition events. This technique also allows for advanced non-destructive, screening of a single microelectronic devices for predictable response in a stressful, i.e. radiation, environments.

Terahertz amplification in RTD-gated HEMTs with a grating-gate wave coupling topology

NASA Astrophysics Data System (ADS)

Condori Quispe, Hugo O.; Encomendero-Risco, Jimy J.; Xing, Huili Grace; Sensale-Rodriguez, Berardi

2016-08-01

We theoretically analyze the operation of a terahertz amplifier consisting of a resonant-tunneling-diode gated high-electron-mobility transistor (RTD-gated HEMT) in a grating-gate topology. In these devices, the key element enabling substantial power gain is the efficient coupling of terahertz waves into and out of plasmons in the RTD-gated HEMT channel, i.e., the gain medium, via the grating-gate itself, part of the active device, rather than by an external antenna structure as discussed in previous works, therefore potentially enabling terahertz amplification with associated power gains >40 dB.

Terahertz amplification in RTD-gated HEMTs with a grating-gate wave coupling topology

DOE Office of Scientific and Technical Information (OSTI.GOV)

Condori Quispe, Hugo O.; Sensale-Rodriguez, Berardi; Encomendero-Risco, Jimy J.

2016-08-08

We theoretically analyze the operation of a terahertz amplifier consisting of a resonant-tunneling-diode gated high-electron-mobility transistor (RTD-gated HEMT) in a grating-gate topology. In these devices, the key element enabling substantial power gain is the efficient coupling of terahertz waves into and out of plasmons in the RTD-gated HEMT channel, i.e., the gain medium, via the grating-gate itself, part of the active device, rather than by an external antenna structure as discussed in previous works, therefore potentially enabling terahertz amplification with associated power gains >40 dB.

Dual-gate GaAs FET switches

NASA Astrophysics Data System (ADS)

Vorhaus, J. L.; Fabian, W.; Ng, P. B.; Tajima, Y.

1981-02-01

A set of multi-pole, multi-throw switch devices consisting of dual-gate GaAs FET's is described. Included are single-pole, single-throw (SPST), double-pole, double-throw (DPDT), and single-pole four-throw (SP4T) switches. Device fabrication and measurement techniques are discussed. The device models for these switches were based on an equivalent circuit of a dual-gate FET. The devices were found to have substantial gain in X-band and low Ku-band.

Monolithic integration of a MOSFET with a MEMS device

DOEpatents

Bennett, Reid; Draper, Bruce

2003-01-01

An integrated microelectromechanical system comprises at least one MOSFET interconnected to at least one MEMS device on a common substrate. A method for integrating the MOSFET with the MEMS device comprises fabricating the MOSFET and MEMS device monolithically on the common substrate. Conveniently, the gate insulator, gate electrode, and electrical contacts for the gate, source, and drain can be formed simultaneously with the MEMS device structure, thereby eliminating many process steps and materials. In particular, the gate electrode and electrical contacts of the MOSFET and the structural layers of the MEMS device can be doped polysilicon. Dopant diffusion from the electrical contacts is used to form the source and drain regions of the MOSFET. The thermal diffusion step for forming the source and drain of the MOSFET can comprise one or more of the thermal anneal steps to relieve stress in the structural layers of the MEMS device.

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

High-k dielectric Al2O3 nanowire and nanoplate field effect sensors for improved pH sensing

PubMed Central

Reddy, Bobby; Dorvel, Brian R.; Go, Jonghyun; Nair, Pradeep R.; Elibol, Oguz H.; Credo, Grace M.; Daniels, Jonathan S.; Chow, Edmond K. C.; Su, Xing; Varma, Madoo; Alam, Muhammad A.

2011-01-01

Over the last decade, field-effect transistors (FETs) with nanoscale dimensions have emerged as possible label-free biological and chemical sensors capable of highly sensitive detection of various entities and processes. While significant progress has been made towards improving their sensitivity, much is yet to be explored in the study of various critical parameters, such as the choice of a sensing dielectric, the choice of applied front and back gate biases, the design of the device dimensions, and many others. In this work, we present a process to fabricate nanowire and nanoplate FETs with Al2O3 gate dielectrics and we compare these devices with FETs with SiO2 gate dielectrics. The use of a high-k dielectric such as Al2O3 allows for the physical thickness of the gate dielectric to be thicker without losing sensitivity to charge, which then reduces leakage currents and results in devices that are highly robust in fluid. This optimized process results in devices stable for up to 8 h in fluidic environments. Using pH sensing as a benchmark, we show the importance of optimizing the device bias, particularly the back gate bias which modulates the effective channel thickness. We also demonstrate that devices with Al2O3 gate dielectrics exhibit superior sensitivity to pH when compared to devices with SiO2 gate dielectrics. Finally, we show that when the effective electrical silicon channel thickness is on the order of the Debye length, device response to pH is virtually independent of device width. These silicon FET sensors could become integral components of future silicon based Lab on Chip systems. PMID:21203849

Air-gating and chemical-gating in transistors and sensing devices made from hollow TiO2 semiconductor nanotubes

NASA Astrophysics Data System (ADS)

Alivov, Yahya; Funke, Hans; Nagpal, Prashant

2015-07-01

Rapid miniaturization of electronic devices down to the nanoscale, according to Moore’s law, has led to some undesirable effects like high leakage current in transistors, which can offset additional benefits from scaling down. Development of three-dimensional transistors, by spatial extension in the third dimension, has allowed higher contact area with a gate electrode and better control over conductivity in the semiconductor channel. However, these devices do not utilize the large surface area and interfaces for new electronic functionality. Here, we demonstrate air gating and chemical gating in hollow semiconductor nanotube devices and highlight the potential for development of novel transistors that can be modulated using channel bias, gate voltage, chemical composition, and concentration. Using chemical gating, we reversibly altered the conductivity of nanoscaled semiconductor nanotubes (10-500 nm TiO2 nanotubes) by six orders of magnitude, with a tunable rectification factor (ON/OFF ratio) ranging from 1-106. While demonstrated air- and chemical-gating speeds were slow here (˜seconds) due to the mechanical-evacuation rate and size of our chamber, the small nanoscale volume of these hollow semiconductors can enable much higher switching speeds, limited by the rate of adsorption/desorption of molecules at semiconductor interfaces. These chemical-gating effects are completely reversible, additive between different chemical compositions, and can enable semiconductor nanoelectronic devices for ‘chemical transistors’, ‘chemical diodes’, and very high-efficiency sensing applications.

Thermally stable In0.7Ga0.3As/In0.52Al0.48As pHEMTs using thermally evaporated palladium gate metallization

NASA Astrophysics Data System (ADS)

Ian, Ka Wa; Zawawiand, Mohamad Adzhar Md; Missous, Mohamed

2014-03-01

This work described the fabrication and performances of strained channel In0.52Al0.47As/In0.7Ga0.3As/InP pHEMTs with thermally evaporated Pd/Ti/Au gate metallization. The electrical characteristics of these Pd-gate devices are studied to investigate the effects of changing the Pd metal thickness, annealing temperature and annealing time. Following annealing at 200 °C for 35 min, a 10 nm Pd-gate device displays a VTH of -0.25 V, which is significantly smaller compared to those with Ti/Au gate schemes showing VTH = -0.75 V. A 1 um gate length device exhibits an improved Gm of 580 mS mm-1 (from 500 mS mm-1), a high IDSmax of 400 mA mm-1 (from 330 mA mm-1) and good fT and fmax of 24.5 and 49 GHz commensurate with the 1 µm gate length. All these enhancements are attributed to the controllable gate sinking of Pd. The device shows no significant degradation even after annealing at 230 °C for more than 5 h, which implies that the reliability of these Pd-gate structures is excellent.

Effect of Split Gate Size on the Electrostatic Potential and 0.7 Anomaly within Quantum Wires on a Modulation-Doped GaAs /AlGaAs Heterostructure

NASA Astrophysics Data System (ADS)

Smith, L. W.; Al-Taie, H.; Lesage, A. A. J.; Thomas, K. J.; Sfigakis, F.; See, P.; Griffiths, J. P.; Farrer, I.; Jones, G. A. C.; Ritchie, D. A.; Kelly, M. J.; Smith, C. G.

2016-04-01

We study 95 split gates of different size on a single chip using a multiplexing technique. Each split gate defines a one-dimensional channel on a modulation-doped GaAs /AlGaAs heterostructure, through which the conductance is quantized. The yield of devices showing good quantization decreases rapidly as the length of the split gates increases. However, for the subset of devices showing good quantization, there is no correlation between the electrostatic length of the one-dimensional channel (estimated using a saddle-point model) and the gate length. The variation in electrostatic length and the one-dimensional subband spacing for devices of the same gate length exceeds the variation in the average values between devices of different lengths. There is a clear correlation between the curvature of the potential barrier in the transport direction and the strength of the "0.7 anomaly": the conductance value of the 0.7 anomaly reduces as the barrier curvature becomes shallower. These results highlight the key role of the electrostatic environment in one-dimensional systems. Even in devices with clean conductance plateaus, random fluctuations in the background potential are crucial in determining the potential landscape in the active device area such that nominally identical gate structures have different characteristics.

Flexible Peripheral Component Interconnect Input/Output Card

NASA Technical Reports Server (NTRS)

Bigelow, Kirk K.; Jerry, Albert L.; Baricio, Alisha G.; Cummings, Jon K.

2010-01-01

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

Quantum phase gate based on electromagnetically induced transparency in optical cavities

NASA Astrophysics Data System (ADS)

Borges, Halyne S.; Villas-Bôas, Celso J.

2016-11-01

We theoretically investigate the implementation of a quantum controlled-phase gate in a system constituted by a single atom inside an optical cavity, based on the electromagnetically induced transparency effect. First we show that a probe pulse can experience a π phase shift due to the presence or absence of a classical control field. Considering the interplay of the cavity-EIT effect and the quantum memory process, we demonstrated a controlled-phase gate between two single photons. To this end, first one needs to store a (control) photon in the ground atomic states. In the following, a second (target) photon must impinge on the atom-cavity system. Depending on the atomic state, this second photon will be either transmitted or reflected, acquiring different phase shifts. This protocol can then be easily extended to multiphoton systems, i.e., keeping the control photon stored, it may induce phase shifts in several single photons, thus enabling the generation of multipartite entangled states. We explore the relevant parameter space in the atom-cavity system that allows the implementation of quantum controlled-phase gates using the recent technologies. In particular, we have found a lower bound for the cooperativity of the atom-cavity system which enables the implementation of phase shift on single photons. The induced shift on the phase of a photonic qubit and the controlled-phase gate between single photons, combined with optical devices, enable one to perform universal quantum computation.

Lithium ion intercalation in thin crystals of hexagonal TaSe2 gated by a polymer electrolyte

NASA Astrophysics Data System (ADS)

Wu, Yueshen; Lian, Hailong; He, Jiaming; Liu, Jinyu; Wang, Shun; Xing, Hui; Mao, Zhiqiang; Liu, Ying

2018-01-01

Ionic liquid gating has been used to modify the properties of layered transition metal dichalcogenides (TMDCs), including two-dimensional (2D) crystals of TMDCs used extensively recently in the device work, which has led to observations of properties not seen in the bulk. The main effect comes from the electrostatic gating due to the strong electric field at the interface. In addition, ionic liquid gating also leads to ion intercalation when the ion size of the gate electrolyte is small compared to the interlayer spacing of TMDCs. However, the microscopic processes of ion intercalation have rarely been explored in layered TMDCs. Here, we employed a technique combining photolithography device fabrication and electrical transport measurements on the thin crystals of hexagonal TaSe2 using multiple channel devices gated by a polymer electrolyte LiClO4/Polyethylene oxide (PEO). The gate voltage and time dependent source-drain resistances of these thin crystals were used to obtain information on the intercalation process, the effect of ion intercalation, and the correlation between the ion occupation of allowed interstitial sites and the device characteristics. We found a gate voltage controlled modulation of the charge density waves and a scattering rate of charge carriers. Our work suggests that ion intercalation can be a useful tool for layered materials engineering and 2D crystal device design.

Fast quantum logic gates with trapped-ion qubits

NASA Astrophysics Data System (ADS)

Schäfer, V. M.; Ballance, C. J.; Thirumalai, K.; Stephenson, L. J.; Ballance, T. G.; Steane, A. M.; Lucas, D. M.

2018-03-01

Quantum bits (qubits) based on individual trapped atomic ions are a promising technology for building a quantum computer. The elementary operations necessary to do so have been achieved with the required precision for some error-correction schemes. However, the essential two-qubit logic gate that is used to generate quantum entanglement has hitherto always been performed in an adiabatic regime (in which the gate is slow compared with the characteristic motional frequencies of the ions in the trap), resulting in logic speeds of the order of 10 kilohertz. There have been numerous proposals of methods for performing gates faster than this natural ‘speed limit’ of the trap. Here we implement one such method, which uses amplitude-shaped laser pulses to drive the motion of the ions along trajectories designed so that the gate operation is insensitive to the optical phase of the pulses. This enables fast (megahertz-rate) quantum logic that is robust to fluctuations in the optical phase, which would otherwise be an important source of experimental error. We demonstrate entanglement generation for gate times as short as 480 nanoseconds—less than a single oscillation period of an ion in the trap and eight orders of magnitude shorter than the memory coherence time measured in similar calcium-43 hyperfine qubits. The power of the method is most evident at intermediate timescales, at which it yields a gate error more than ten times lower than can be attained using conventional techniques; for example, we achieve a 1.6-microsecond-duration gate with a fidelity of 99.8 per cent. Faster and higher-fidelity gates are possible at the cost of greater laser intensity. The method requires only a single amplitude-shaped pulse and one pair of beams derived from a continuous-wave laser. It offers the prospect of combining the unrivalled coherence properties, operation fidelities and optical connectivity of trapped-ion qubits with the submicrosecond logic speeds that are usually associated with solid-state devices.

Fast quantum logic gates with trapped-ion qubits.

PubMed

Schäfer, V M; Ballance, C J; Thirumalai, K; Stephenson, L J; Ballance, T G; Steane, A M; Lucas, D M

2018-02-28

Quantum bits (qubits) based on individual trapped atomic ions are a promising technology for building a quantum computer. The elementary operations necessary to do so have been achieved with the required precision for some error-correction schemes. However, the essential two-qubit logic gate that is used to generate quantum entanglement has hitherto always been performed in an adiabatic regime (in which the gate is slow compared with the characteristic motional frequencies of the ions in the trap), resulting in logic speeds of the order of 10 kilohertz. There have been numerous proposals of methods for performing gates faster than this natural 'speed limit' of the trap. Here we implement one such method, which uses amplitude-shaped laser pulses to drive the motion of the ions along trajectories designed so that the gate operation is insensitive to the optical phase of the pulses. This enables fast (megahertz-rate) quantum logic that is robust to fluctuations in the optical phase, which would otherwise be an important source of experimental error. We demonstrate entanglement generation for gate times as short as 480 nanoseconds-less than a single oscillation period of an ion in the trap and eight orders of magnitude shorter than the memory coherence time measured in similar calcium-43 hyperfine qubits. The power of the method is most evident at intermediate timescales, at which it yields a gate error more than ten times lower than can be attained using conventional techniques; for example, we achieve a 1.6-microsecond-duration gate with a fidelity of 99.8 per cent. Faster and higher-fidelity gates are possible at the cost of greater laser intensity. The method requires only a single amplitude-shaped pulse and one pair of beams derived from a continuous-wave laser. It offers the prospect of combining the unrivalled coherence properties, operation fidelities and optical connectivity of trapped-ion qubits with the submicrosecond logic speeds that are usually associated with solid-state devices.

Radiation hardening of MOS devices by boron. [for stabilizing gate threshold potential of field effect device

NASA Technical Reports Server (NTRS)

Danchenko, V. (Inventor)

1974-01-01

A technique is described for radiation hardening of MOS devices and specifically for stabilizing the gate threshold potential at room temperature of a radiation subjected MOS field-effect device with a semiconductor substrate, an insulating layer of oxide on the substrate, and a gate electrode disposed on the insulating layer. The boron is introduced within a layer of the oxide of about 100 A-300 A thickness immediately adjacent the semiconductor-insulator interface. The concentration of boron in the oxide layer is preferably maintained on the order of 10 to the 18th power atoms/cu cm. The technique serves to reduce and substantially annihilate radiation induced positive gate charge accumulations.

Impact of gate engineering in enhancement mode n++GaN/InAlN/AlN/GaN HEMTs

NASA Astrophysics Data System (ADS)

Adak, Sarosij; Swain, Sanjit Kumar; Rahaman, Hafizur; Sarkar, Chandan Kumar

2016-12-01

This paper illustrate the effect of gate material engineering on the performance of enhancement mode n++GaN/InAlN/AlN/GaN high electron mobility transistors (HEMTs). A comparative analysis of key device parameters is discussed for the Triple Material Gate (TMG), Dual Material Gate (DMG) and the Single Material Gate (SMG) structure HEMTs by considering the same device dimensions. The simulation results shows that an significant improvement is noticed in the key analysis parameters such as drain current (Id), transconductance (gm), cut off frequency (fT), RF current gain, maximum cut off frequency (fmax) and RF power gain of the gate material engineered devices with respect to SMG normally off n++GaN/InAlN/AlN/GaN HEMTs. This improvement is due to the existence of the perceivable step in the surface potential along the channel which successfully screens the drain potential variation in the source side of the channel for the gate engineering devices. The analysis suggested that the proposed TMG and DMG engineered structure enhancement mode n++GaN/InAlN/AlN/GaN HEMTs can be considered as a potential device for future high speed, microwave and digital application.

Formation of holographic memory for optically reconfigurable gate array by angle-multiplexing recording of multi-circuit information in liquid crystal composites

NASA Astrophysics Data System (ADS)

Ogiwara, Akifumi; Maekawa, Hikaru; Watanabe, Minoru; Moriwaki, Retsu

2014-02-01

A holographic polymer-dispersed liquid crystal (HPDLC) memory to record multi-context information for an optically reconfigurable gate array is formed by the angle-multiplexing recording using a successive laser exposure in liquid crystal (LC) composites. The laser illumination system is constructed using the half mirror and photomask written by the different configuration contexts placed on the motorized stages under the control of a personal computer. The fabricated holographic memory implements a precise reconstruction of configuration contexts corresponding to the various logical circuits such as OR circuit and NOR circuit by the laser illumination at different incident angle in the HPDLC memory.

Improvement in top-gate MoS2 transistor performance due to high quality backside Al2O3 layer

NASA Astrophysics Data System (ADS)

Bolshakov, Pavel; Zhao, Peng; Azcatl, Angelica; Hurley, Paul K.; Wallace, Robert M.; Young, Chadwin D.

2017-07-01

A high quality Al2O3 layer is developed to achieve high performance in top-gate MoS2 transistors. Compared with top-gate MoS2 field effect transistors on a SiO2 layer, the intrinsic mobility and subthreshold slope were greatly improved in high-k backside layer devices. A forming gas anneal is found to enhance device performance due to a reduction in the charge trap density of the backside dielectric. The major improvements in device performance are ascribed to the forming gas anneal and the high-k dielectric screening effect of the backside Al2O3 layer. Top-gate devices built upon these stacks exhibit a near-ideal subthreshold slope of ˜69 mV/dec and a high Y-Function extracted intrinsic carrier mobility (μo) of 145 cm2/V.s, indicating a positive influence on top-gate device performance even without any backside bias.

Neuromimetic Circuits with Synaptic Devices Based on Strongly Correlated Electron Systems

NASA Astrophysics Data System (ADS)

Ha, Sieu D.; Shi, Jian; Meroz, Yasmine; Mahadevan, L.; Ramanathan, Shriram

2014-12-01

Strongly correlated electron systems such as the rare-earth nickelates (R NiO3 , R denotes a rare-earth element) can exhibit synapselike continuous long-term potentiation and depression when gated with ionic liquids; exploiting the extreme sensitivity of coupled charge, spin, orbital, and lattice degrees of freedom to stoichiometry. We present experimental real-time, device-level classical conditioning and unlearning using nickelate-based synaptic devices in an electronic circuit compatible with both excitatory and inhibitory neurons. We establish a physical model for the device behavior based on electric-field-driven coupled ionic-electronic diffusion that can be utilized for design of more complex systems. We use the model to simulate a variety of associate and nonassociative learning mechanisms, as well as a feedforward recurrent network for storing memory. Our circuit intuitively parallels biological neural architectures, and it can be readily generalized to other forms of cellular learning and extinction. The simulation of neural function with electronic device analogs may provide insight into biological processes such as decision making, learning, and adaptation, while facilitating advanced parallel information processing in hardware.

A novel hetero-material gate-underlap electrically doped TFET for improving DC/RF and ambipolar behaviour

NASA Astrophysics Data System (ADS)

Yadav, Shivendra; Sharma, Dheeraj; Chandan, Bandi Venkata; Aslam, Mohd; Soni, Deepak; Sharma, Neeraj

2018-05-01

In this article, the impact of gate-underlap with hetero material (low band gap) has been investigated in terms of DC and Analog/RF parameters by proposed device named as hetero material gate-underlap electrically doped TFET (HM-GUL-ED-TFET). Gate-underlap resolves the problem of ambipolarity, gate leakage current (Ig) and slightly improves the gate to drain capacitance, but DC performance is almost unaffected. Further, the use of low band gap material (Si0.5 Ge) in proposed device causes a drastic improvement in the DC as well as RF figures of merit. We have investigated the Si0.5 Ge as a suitable candidate among different low band gap materials. In addition, the sensitivity of gate-underlap in terms of gate to drain inversion and parasitic capacitances has been studied for HM-GUL-ED-TFET. Further, relatively it is observed that gate-underlap is a better way than drain-underlap in the proposed structure to improve Analog/RF performances without degrading the DC parameters of device. Additionally, hetero-junction alignment analysis has been done for fabrication feasibility.

Highly conducting leakage-free electrolyte for SrCoOx-based non-volatile memory device

NASA Astrophysics Data System (ADS)

Katase, Takayoshi; Suzuki, Yuki; Ohta, Hiromichi

2017-10-01

The electrochemical switching of SrCoOx-based non-volatile memory with a thin-film-transistor structure was examined by using liquid-leakage-free electrolytes with different conductivities (σ) as the gate insulator. We first examined leakage-free water, which is incorporated in the amorphous (a-) 12CaO.7Al2O3 film with a nanoporous structure (Calcium Aluminate with Nanopore), but the electrochemical oxidation/reduction of the SrCoOx layer required the application of a high gate voltage (Vg) up to 20 V for a very long current-flowing-time (t) ˜40 min, primarily due to the low σ [2.0 × 10-8 S cm-1 at room temperature (RT)] of leakage-free water. We then controlled the σ of the leakage-free electrolyte, infiltrated in the a-NaxTaO3 film with a nanopillar array structure, from 8.0 × 10-8 S cm-1 to 2.5 × 10-6 S cm-1 at RT by changing the x = 0.01-1.0. As the result, the t, required for the metallization of the SrCoOx layer under small Vg = -3 V, becomes two orders of magnitude shorter with increase of the σ of the a-NaxTaO3 leakage-free electrolyte. These results indicate that the ion migration in the leakage-free electrolyte is the rate-determining step for the electrochemical switching, compared to the other electrochemical process, and the high σ of the leakage-free electrolyte is the key factor for the development of the non-volatile SrCoOx-based electro-magnetic phase switching device.

A 2D Material based Gate Tunable Memristive Device for Emulating Modulatory Input-dependent Hetero-synaptic Plasticity.

NASA Astrophysics Data System (ADS)

Yan, Xiaodong; Tian, He; Xie, Yujun; Kostelec, Andrew; Zhao, Huan; Cha, Judy J.; Tice, Jesse; Wang, Han

Modulatory input-dependent plasticity is a well-known type of hetero-synaptic response where the release of neuromodulators can alter the efficacy of neurotransmission in a nearby chemical synapse. Solid-state devices that can mimic such phenomenon are desirable for enhancing the functionality and reconfigurability of neuromorphic electronics. In this work, we demonstrated a tunable artificial synaptic device concept based on the properties of graphene and tin oxide that can mimic the modulatory input-dependent plasticity. By using graphene as the contact electrode, a third electrode terminal can be used to modulate the conductive filament formation in the vertical tin oxide based resistive memory device. The resulting synaptic characteristics of this device, in terms of the profile of synaptic weight change and the spike-timing-dependent-plasticity, is tunable with the bias at the modulating terminal. Furthermore, the synaptic response can be reconfigured between excitatory and inhibitory modes by this modulating bias. The operation mechanism of the device is studied with combined experimental and theoretical analysis. The device is attractive for application in neuromorphic electronics. This work is supported by ARO and NG-ION2 at USC.

Comparative study of CAVET with dielectric and p-GaN gate and Mg ion-implanted current blocking layer

NASA Astrophysics Data System (ADS)

Mandal, Saptarshi; Agarwal, Anchal; Ahmadi, Elaheh; Mahadeva Bhat, K.; Laurent, Matthew A.; Keller, Stacia; Chowdhury, Srabanti

2017-08-01

In this work, a study of two different types of current aperture vertical electron transistor (CAVET) with ion-implanted blocking layer are presented. The device fabrication and performance limitation of a CAVET with a dielectric gate is discussed, and the breakdown limiting structure is evaluated using on-wafer test structures. The gate dielectric limited the device breakdown to 50V, while the blocking layer was able to withstand over 400V. To improve the device performance, an alternative CAVET structure with a p-GaN gate instead of dielectric is designed and realized. The pGaN gated CAVET structure increased the breakdown voltage to over 400V. Measurement of test structures on the wafer showed the breakdown was limited by the blocking layer instead of the gate p-n junction.

Vertical bloch line memory

NASA Technical Reports Server (NTRS)

Katti, Romney R. (Inventor); Stadler, Henry L. (Inventor); Wu, Jiin-chuan (Inventor)

1995-01-01

A new read gate design for the vertical Bloch line (VBL) memory is disclosed which offers larger operating margin than the existing read gate designs. In the existing read gate designs, a current is applied to all the stripes. The stripes that contain a VBL pair are chopped, while the stripes that do not contain a VBL pair are not chopped. The information is then detected by inspecting the presence or absence of the bubble. The margin of the chopping current amplitude is very small, and sometimes non-existent. A new method of reading Vertical Bloch Line memory is also disclosed. Instead of using the wall chirality to separate the two binary states, the spatial deflection of the stripe head is used. Also disclosed herein is a compact memory which uses vertical Bloch line (VBL) memory technology for providing data storage. A three-dimensional arrangement in the form of stacks of VBL memory layers is used to achieve high volumetric storage density. High data transfer rate is achieved by operating all the layers in parallel. Using Hall effect sensing, and optical sensing via the Faraday effect to access the data from within the three-dimensional packages, an even higher data transfer rate can be achieved due to parallel operation within each layer.

Novelty modulates human striatal activation and prefrontal-striatal effective connectivity during working memory encoding.

PubMed

Geiger, Lena S; Moessnang, Carolin; Schäfer, Axel; Zang, Zhenxiang; Zangl, Maria; Cao, Hengyi; van Raalten, Tamar R; Meyer-Lindenberg, Andreas; Tost, Heike

2018-05-11

The functional role of the basal ganglia (BG) in the gating of suitable motor responses to the cortex is well established. Growing evidence supports an analogous role of the BG during working memory encoding, a task phase in which the "input-gating" of relevant materials (or filtering of irrelevant information) is an important mechanism supporting cognitive capacity and the updating of working memory buffers. One important aspect of stimulus relevance is the novelty of working memory items, a quality that is understudied with respect to its effects on corticostriatal function and connectivity. To this end, we used functional magnetic resonance imaging (fMRI) in 74 healthy volunteers performing an established Sternberg working memory task with different task phases (encoding vs. retrieval) and degrees of stimulus familiarity (novel vs. previously trained). Activation analyses demonstrated a highly significant engagement of the anterior striatum, in particular during the encoding of novel working memory items. Dynamic causal modeling (DCM) of corticostriatal circuit connectivity identified a selective positive modulatory influence of novelty encoding on the connection from the dorsolateral prefrontal cortex (DLPFC) to the anterior striatum. These data extend prior research by further underscoring the relevance of the BG for human cognitive function and provide a mechanistic account of the DLPFC as a plausible top-down regulatory element of striatal function that may facilitate the "input-gating" of novel working memory materials.

Front and backside processed thin film electronic devices

DOEpatents

Evans, Paul G [Madison, WI; Lagally, Max G [Madison, WI; Ma, Zhenqiang [Middleton, WI; Yuan, Hao-Chih [Lakewood, CO; Wang, Guogong [Madison, WI; Eriksson, Mark A [Madison, WI

2012-01-03

This invention provides thin film devices that have been processed on their front- and backside. The devices include an active layer that is sufficiently thin to be mechanically flexible. Examples of the devices include back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Reconfigurable ultra-thin film GDNMOS device for ESD protection in 28 nm FD-SOI technology

NASA Astrophysics Data System (ADS)

Athanasiou, Sotirios; Legrand, Charles-Alexandre; Cristoloveanu, Sorin; Galy, Philippe

2017-02-01

We propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fabricated with 28 nm UTBB FD-SOI high-k metal gate technology. By modifying the combination of the diode and transistor gate stacks, the robustness of the device is optimized, achieving a maximum breakdown voltage (VBR) of 4.9 V. In addition, modifications of the gate length modulate the trigger voltage (Vt1) with a minimum value of 3.5 V. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation. A lower doping of the base enhances the bipolar gain, leading to thyristor behavior. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior.

Leakage current conduction in metal gate junctionless nanowire transistors

NASA Astrophysics Data System (ADS)

Oproglidis, T. A.; Karatsori, T. A.; Barraud, S.; Ghibaudo, G.; Dimitriadis, C. A.

2017-05-01

In this paper, the experimental off-state drain leakage current behavior is systematically explored in n- and p-channel junctionless nanowire transistors with HfSiON/TiN/p+-polysilicon gate stack. The analysis of the drain leakage current is based on experimental data of the gate leakage current. It has been shown that the off-state drain leakage current in n-channel devices is negligible, whereas in p-channel devices it is significant and dramatically increases with drain voltage. The overall results indicate that the off-state drain leakage current in p-channel devices is mainly due to trap-assisted Fowler-Nordheim tunneling of electrons through the gate oxide of electrons from the metal gate to the silicon layer near the drain region.

Fault tolerance issues in nanoelectronics

NASA Astrophysics Data System (ADS)

Spagocci, S. M.

The astonishing success story of microelectronics cannot go on indefinitely. In fact, once devices reach the few-atom scale (nanoelectronics), transient quantum effects are expected to impair their behaviour. Fault tolerant techniques will then be required. The aim of this thesis is to investigate the problem of transient errors in nanoelectronic devices. Transient error rates for a selection of nanoelectronic gates, based upon quantum cellular automata and single electron devices, in which the electrostatic interaction between electrons is used to create Boolean circuits, are estimated. On the bases of such results, various fault tolerant solutions are proposed, for both logic and memory nanochips. As for logic chips, traditional techniques are found to be unsuitable. A new technique, in which the voting approach of triple modular redundancy (TMR) is extended by cascading TMR units composed of nanogate clusters, is proposed and generalised to other voting approaches. For memory chips, an error correcting code approach is found to be suitable. Various codes are considered and a lookup table approach is proposed for encoding and decoding. We are then able to give estimations for the redundancy level to be provided on nanochips, so as to make their mean time between failures acceptable. It is found that, for logic chips, space redundancies up to a few tens are required, if mean times between failures have to be of the order of a few years. Space redundancy can also be traded for time redundancy. As for memory chips, mean times between failures of the order of a few years are found to imply both space and time redundancies of the order of ten.

Auto and hetero-associative memory using a 2-D optical logic gate

NASA Technical Reports Server (NTRS)

Chao, Tien-Hsin (Inventor)

1992-01-01

An optical system for auto-associative and hetero-associative recall utilizing Hamming distance as the similarity measure between a binary input image vector V(sup k) and a binary image vector V(sup m) in a first memory array using an optical Exclusive-OR gate for multiplication of each of a plurality of different binary image vectors in memory by the input image vector. After integrating the light of each product V(sup k) x V(sup m), a shortest Hamming distance detection electronics module determines which product has the lowest light intensity and emits a signal that activates a light emitting diode to illuminate a corresponding image vector in a second memory array for display. That corresponding image vector is identical to the memory image vector V(sup m) in the first memory array for auto-associative recall or related to it, such as by name, for hetero-associative recall.

High-performance black phosphorus top-gate ferroelectric transistor for nonvolatile memory applications

NASA Astrophysics Data System (ADS)

Lee, Young Tack; Hwang, Do Kyung; Choi, Won Kook

2016-10-01

Two-dimensional (2D) van der Waals (vdW) atomic crystals have been extensively studied and significant progress has been made. The newest 2D vdW material, called black phosphorus (BP), has attracted considerable attention due to its unique physical properties, such as its being a singlecomponent material like graphene, and its having a high mobility and direct band gap. Here, we report on a high-performance BP nanosheet based ferroelectric field effect transistor (FeFET) with a poly(vinylidenefluoride-trifluoroethylene) top-gate insulator for a nonvolatile memory application. The BP FeFETs show the highest linear hole mobility of 563 cm2/Vs and a clear memory window of more than 15 V. For more advanced nonvolatile memory circuit applications, two different types of resistive-load and complementary ferroelectric memory inverters were implemented, which showed distinct memory on/off switching characteristics.

A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Bailey, Mark; Ho, Fat Duen

2004-01-01

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.

Photonic Potential of Haloarchaeal Pigment Bacteriorhodopsin for Future Electronics: A Review.

PubMed

Ashwini, Ravi; Vijayanand, S; Hemapriya, J

2017-08-01

Haloarchaea are known for its adaptation in extreme saline environment. Halophilic archaea produces carotenoid pigments and proton pumps to protect them from extremes of salinity. Bacteriorhodopsin (bR) is a light-driven proton pump that resides in the membrane of haloarchaea Halobacterium salinarum. The photocycle of Bacteriorhodopsin passes through several states from K to O, finally liberating ATP for host's survival. Extensive studies on Bacteriorhodopsin photocycle has provided in depth knowledge on their sequential mechanism of converting solar energy into chemical energy inside the cell. This ability of Bacteriorhodopsin to harvest sunlight has now been experimented to exploit the unexplored and extensively available solar energy in various biotechnological applications. Currently, bacteriorhodopsin finds its importance in dye-sensitized solar cell (DSSC), logic gates (integrated circuits, IC's), optical switching, optical memories, storage devices (random access memory, RAM), biosensors, electronic sensors and optical microcavities. This review deals with the optical and electrical applications of the purple pigment Bacteriorhodopsin.

Plasma Doping—Enabling Technology for High Dose Logic and Memory Applications

NASA Astrophysics Data System (ADS)

Miller, T.; Godet, L.; Papasouliotis, G. D.; Singh, V.

2008-11-01

As logic and memory device dimensions shrink with each generation, there are more high dose implants at lower energies. Examples include dual poly gate (also referred to as counter-doped poly), elevated source drain and contact plug implants. Plasma Doping technology throughput and dopant profile benefits at these ultra high dose and lower energy conditions have been well established [1,2,3]. For the first time a production-worthy plasma doping implanter, the VIISta PLAD tool, has been developed with unique architecture suited for precise and repeatable dopant placement. Critical elements of the architecture include pulsed DC wafer bias, closed-loop dosimetry and a uniform low energy, high density plasma source. In this paper key performance metrics such as dose uniformity, dose repeatability and dopant profile control will be presented that demonstrate the production-worthiness of the VIISta PLAD tool for several high dose applications.

Coherent all-optical control of ultracold atoms arrays in permanent magnetic traps.

PubMed

Abdelrahman, Ahmed; Mukai, Tetsuya; Häffner, Hartmut; Byrnes, Tim

2014-02-10

We propose a hybrid architecture for quantum information processing based on magnetically trapped ultracold atoms coupled via optical fields. The ultracold atoms, which can be either Bose-Einstein condensates or ensembles, are trapped in permanent magnetic traps and are placed in microcavities, connected by silica based waveguides on an atom chip structure. At each trapping center, the ultracold atoms form spin coherent states, serving as a quantum memory. An all-optical scheme is used to initialize, measure and perform a universal set of quantum gates on the single and two spin-coherent states where entanglement can be generated addressably between spatially separated trapped ultracold atoms. This allows for universal quantum operations on the spin coherent state quantum memories. We give detailed derivations of the composite cavity system mediated by a silica waveguide as well as the control scheme. Estimates for the necessary experimental conditions for a working hybrid device are given.

Error-Transparent Quantum Gates for Small Logical Qubit Architectures

NASA Astrophysics Data System (ADS)

Kapit, Eliot

2018-02-01

One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016), 10.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both. The effective logical gate error rate in these models displays superlinear error reduction with linear increases in single qubit lifetime, proving that passive error correction is capable of increasing gate fidelity. Using a standard phenomenological noise model for superconducting qubits, we demonstrate a realistic, universal one- and two-qubit gate set for the VSLQ, with error rates an order of magnitude lower than those for same-duration operations on single qubits or pairs of qubits. These developments further suggest that incorporating small logical qubits into a measurement based code could substantially improve code performance.

A Decoherence-Free Quantum Memory Using Trapped Ions

DTIC Science & Technology

2016-09-22

superpo- sitions. Robust quantum memories are there- fore essential to realizing the potential gains of quantum computing (3). However, inter- action of a...tolerant quantum logic (13, 14). These properties suggest that DFSs will be intrinsic to future quantum computing architectures. Logic gates on DFS...practi- cal quantum computing will in any case re- quire logic gates of a much higher fidelity than those used in this work. We therefore expect that, once

On the simple random-walk models of ion-channel gate dynamics reflecting long-term memory.

PubMed

Wawrzkiewicz, Agata; Pawelek, Krzysztof; Borys, Przemyslaw; Dworakowska, Beata; Grzywna, Zbigniew J

2012-06-01

Several approaches to ion-channel gating modelling have been proposed. Although many models describe the dwell-time distributions correctly, they are incapable of predicting and explaining the long-term correlations between the lengths of adjacent openings and closings of a channel. In this paper we propose two simple random-walk models of the gating dynamics of voltage and Ca(2+)-activated potassium channels which qualitatively reproduce the dwell-time distributions, and describe the experimentally observed long-term memory quite well. Biological interpretation of both models is presented. In particular, the origin of the correlations is associated with fluctuations of channel mass density. The long-term memory effect, as measured by Hurst R/S analysis of experimental single-channel patch-clamp recordings, is close to the behaviour predicted by our models. The flexibility of the models enables their use as templates for other types of ion channel.

Analysis of electrical characteristics and proposal of design guide for ultra-scaled nanoplate vertical FET and 6T-SRAM

NASA Astrophysics Data System (ADS)

Seo, Youngsoo; Kim, Shinkeun; Ko, Kyul; Woo, Changbeom; Kim, Minsoo; Lee, Jangkyu; Kang, Myounggon; Shin, Hyungcheol

2018-02-01

In this paper, electrical characteristics of gate-all-around (GAA) nanoplate (NP) vertical FET (VFET) were analyzed for single transistor and 6T-SRAM cell through 3D technology computer-aided design (TCAD) simulation. In VFET, gate and extension lengths are not limited by the area of device because theses lengths are vertically located. The height of NP is assumed in 40 nm considering device fabrication method (top-down approach). According to the sizes of devices, we analyzed the performances of device such as total resistance, capacitance, intrinsic gate delay, sub-threshold swing (S.S), drain-induced barrier lowering (DIBL) and static noise margin (SNM). As the gate length becomes larger, the resistance should be smaller because the total height of NP is fixed in 40 nm. Also, when the channel thickness becomes thicker, the total resistance becomes smaller since the sheet resistances of channel and extension become smaller and the contact resistance becomes smaller due to the increasing contact area. In addition, as the length of channel pitch increases, the parasitic capacitance comes to be larger due to the increasing area of gate-drain and gate-source. The performance of RC delay is best in the shortest gate length (12 nm), the thickest channel (6 nm) and the shortest channel pitch (17 nm) owing to the reduced resistance and parasitic capacitance. However, the other performances such as DIBL, S.S, on/off ratio and SNM are worst because the short channel effect is highest in this situation. Also, we investigated the performance of the multi-channel device. As the number of channels increases, the performance of device and the reliability of SRAM improve because of reduced contact resistance, increased gate dimension and multi-channel compensation effect.

Open-Gated pH Sensor Fabricated on an Undoped-AlGaN/GaN HEMT Structure

PubMed Central

Abidin, Mastura Shafinaz Zainal; Hashim, Abdul Manaf; Sharifabad, Maneea Eizadi; Rahman, Shaharin Fadzli Abd; Sadoh, Taizoh

2011-01-01

The sensing responses in aqueous solution of an open-gated pH sensor fabricated on an AlGaN/GaN high-electron-mobility-transistor (HEMT) structure are investigated. Under air-exposed ambient conditions, the open-gated undoped AlGaN/GaN HEMT only shows the presence of a linear current region. This seems to show that very low Fermi level pinning by surface states exists in the undoped AlGaN/GaN sample. In aqueous solution, typical current-voltage (I-V) characteristics with reasonably good gate controllability are observed, showing that the potential of the AlGaN surface at the open-gated area is effectively controlled via aqueous solution by the Ag/AgCl gate electrode. The open-gated undoped AlGaN/GaN HEMT structure is capable of distinguishing pH level in aqueous electrolytes and exhibits linear sensitivity, where high sensitivity of 1.9 mA/pH or 3.88 mA/mm/pH at drain-source voltage, VDS = 5 V is obtained. Due to the large leakage current where it increases with the negative gate voltage, Nernstian like sensitivity cannot be determined as commonly reported in the literature. This large leakage current may be caused by the technical factors rather than any characteristics of the devices. Surprisingly, although there are some imperfections in the device preparation and measurement, the fabricated devices work very well in distinguishing the pH levels. Suppression of current leakage by improving the device preparation is likely needed to improve the device performance. The fabricated device is expected to be suitable for pH sensing applications. PMID:22163786

Control and manipulation of antiferromagnetic skyrmions in racetrack

NASA Astrophysics Data System (ADS)

Xia, Haiyan; Jin, Chendong; Song, Chengkun; Wang, Jinshuai; Wang, Jianbo; Liu, Qingfang

2017-12-01

Controllable manipulations of magnetic skyrmions are essential for next-generation spintronic devices. Here, the duplication and merging of skyrmions, as well as logical AND and OR functions, are designed in antiferromagnetic (AFM) materials with a cusp or smooth Y-junction structures. The operational time are in the dozens of picoseconds, enabling ultrafast information processing. A key factor for the successful operation is the relatively complex Y-junction structures, where domain walls propagate through in a controlled manner, without significant risks of pinning, vanishing or unwanted depinning of existing domain walls, as well as the nucleation of new domain walls. The motions of a multi-bit, namely the motion of an AFM skyrmion-chain in racetrack, are also investigated. Those micromagnetic simulations may contribute to future AFM skyrmion-based spintronic devices, such as nanotrack memory, logic gates and other information processes.

Magnetic bilayer-skyrmions without skyrmion Hall effect

NASA Astrophysics Data System (ADS)

Zhang, Xichao; Zhou, Yan; Ezawa, Motohiko

2016-01-01

Magnetic skyrmions might be used as information carriers in future advanced memories, logic gates and computing devices. However, there exists an obstacle known as the skyrmion Hall effect (SkHE), that is, the skyrmion trajectories bend away from the driving current direction due to the Magnus force. Consequently, the skyrmions in constricted geometries may be destroyed by touching the sample edges. Here we theoretically propose that the SkHE can be suppressed in the antiferromagnetically exchange-coupled bilayer system, since the Magnus forces in the top and bottom layers are exactly cancelled. We show that such a pair of SkHE-free magnetic skyrmions can be nucleated and be driven by the current-induced torque. Our proposal provides a promising means to move magnetic skyrmions in a perfectly straight trajectory in ultra-dense devices with ultra-fast processing speed.

Controllable transport of a skyrmion in a ferromagnetic narrow channel with voltage-controlled magnetic anisotropy

NASA Astrophysics Data System (ADS)

Wang, Junlin; Xia, Jing; Zhang, Xichao; Zhao, G. P.; Ye, Lei; Wu, Jing; Xu, Yongbing; Zhao, Weisheng; Zou, Zhigang; Zhou, Yan

2018-05-01

Magnetic skyrmions have potential applications in next-generation spintronic devices with ultralow energy consumption. In this work, the current-driven skyrmion motion in a narrow ferromagnetic nanotrack with voltage-controlled magnetic anisotropy (VCMA) is studied numerically. By utilizing the VCMA effect, the transport of skyrmion can be unidirectional in the nanotrack, leading to a one-way information channel. The trajectory of the skyrmion can also be modulated by periodically located VCMA gates, which protects the skyrmion from destruction by touching the track edge. In addition, the location of the skyrmion can be controlled by adjusting the driving pulse length in the presence of the VCMA effect. Our results provide guidelines for practical realization of the skyrmion-based information channel, diode, and skyrmion-based electronic devices such as racetrack memory.

Operation and biasing for single device equivalent to CMOS

DOEpatents

Welch, James D.

2001-01-01

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

Volumetric measurement of human red blood cells by MOSFET-based microfluidic gate.

PubMed

Guo, Jinhong; Ai, Ye; Cheng, Yuanbing; Li, Chang Ming; Kang, Yuejun; Wang, Zhiming

2015-08-01

In this paper, we present a MOSFET-based (metal oxide semiconductor field-effect transistor) microfluidic gate to characterize the translocation of red blood cells (RBCs) through a gate. In the microfluidic system, the bias voltage modulated by the particles or biological cells is connected to the gate of MOSFET. The particles or cells can be detected by monitoring the MOSFET drain current instead of DC/AC-gating method across the electronic gate. Polystyrene particles with various standard sizes are utilized to calibrate the proposed device. Furthermore, RBCs from both adults and newborn blood sample are used to characterize the performance of the device in distinguishing the two types of RBCs. As compared to conventional DC/AC current modulation method, the proposed device demonstrates a higher sensitivity and is capable of being a promising platform for bioassay analysis. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Instantons in Self-Organizing Logic Gates

NASA Astrophysics Data System (ADS)

Bearden, Sean R. B.; Manukian, Haik; Traversa, Fabio L.; Di Ventra, Massimiliano

2018-03-01

Self-organizing logic is a recently suggested framework that allows the solution of Boolean truth tables "in reverse"; i.e., it is able to satisfy the logical proposition of gates regardless to which terminal(s) the truth value is assigned ("terminal-agnostic logic"). It can be realized if time nonlocality (memory) is present. A practical realization of self-organizing logic gates (SOLGs) can be done by combining circuit elements with and without memory. By employing one such realization, we show, numerically, that SOLGs exploit elementary instantons to reach equilibrium points. Instantons are classical trajectories of the nonlinear equations of motion describing SOLGs and connect topologically distinct critical points in the phase space. By linear analysis at those points, we show that these instantons connect the initial critical point of the dynamics, with at least one unstable direction, directly to the final fixed point. We also show that the memory content of these gates affects only the relaxation time to reach the logically consistent solution. Finally, we demonstrate, by solving the corresponding stochastic differential equations, that, since instantons connect critical points, noise and perturbations may change the instanton trajectory in the phase space but not the initial and final critical points. Therefore, even for extremely large noise levels, the gates self-organize to the correct solution. Our work provides a physical understanding of, and can serve as an inspiration for, models of bidirectional logic gates that are emerging as important tools in physics-inspired, unconventional computing.

Unified random access memory (URAM) by integration of a nanocrystal floating gate for nonvolatile memory and a partially depleted floating body for capacitorless 1T-DRAM

NASA Astrophysics Data System (ADS)

Ryu, Seong-Wan; Han, Jin-Woo; Kim, Chung-Jin; Kim, Sungho; Choi, Yang-Kyu

2009-03-01

This paper describes a unified memory (URAM) that utilizes a nanocrystal SOI MOSFET for multi-functional applications of both nonvolatile memory (NVM) and capacitorless 1T-DRAM. By using a discrete storage node (Ag nanocrystal) as the floating gate of the NVM, high defect immunity and 2-bit/cell operation were achieved. The embedded nanocrystal NVM also showed 1T-DRAM operation (program/erase time = 100 ns) characteristics, which were realized by storing holes in the floating body of the SOI MOSFET, without requiring an external capacitor. Three-bit/cell operation was accomplished for different applications - 2-bits for nonvolatility and 1-bit for fast operation.

Influence of gate width on gate-channel carrier mobility in AlGaN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Yang, Ming; Ji, Qizheng; Gao, Zhiliang; Zhang, Shufeng; Lin, Zhaojun; Yuan, Yafei; Song, Bo; Mei, Gaofeng; Lu, Ziwei; He, Jihao

2017-11-01

For the fabricated AlGaN/GaN heterostructure field-effect transistors (HFETs) with different gate widths, the gate-channel carrier mobility is experimentally obtained from the measured current-voltage and capacitance-voltage curves. Under each gate voltage, the mobility gets lower with gate width increasing. Analysis shows that the phenomenon results from the polarization Coulomb field (PCF) scattering, which originates from the irregularly distributed polarization charges at the AlGaN/GaN interface. The device with a larger gate width is with a larger PCF scattering potential and a stronger PCF scattering intensity. As a function of gate width, PCF scattering potential shows a same trend with the mobility variation. And the theoretically calculated mobility values fits well with the experimentally obtained values. Varying gate widths will be a new perspective for the improvement of device characteristics by modulating the gate-channel carrier mobility.

Thick layered semiconductor devices with water top-gates: High on-off ratio field-effect transistors and aqueous sensors.

PubMed

Huang, Yuan; Sutter, Eli; Wu, Liangmei; Xu, Hong; Bao, Lihong; Gao, Hong-Jun; Zhou, Xingjiang; Sutter, Peter

2018-06-21

Layered semiconductors show promise as channel materials for field-effect transistors (FETs). Usually, such devices incorporate solid back or top gate dielectrics. Here, we explore de-ionized (DI) water as a solution top gate for field-effect switching of layered semiconductors including SnS2, MoS2, and black phosphorus. The DI water gate is easily fabricated, can sustain rapid bias changes, and its efficient coupling to layered materials provides high on-off current ratios, near-ideal sub-threshold swing, and enhanced short-channel behavior even for FETs with thick, bulk-like channels where such control is difficult to realize with conventional back-gating. Screening by the high-k solution gate eliminates hysteresis due to surface and interface trap states and substantially enhances the field-effect mobility. The onset of water electrolysis sets the ultimate limit to DI water gating at large negative gate bias. Measurements in this regime show promise for aqueous sensing, demonstrated here by the amperometric detection of glucose in aqueous solution. DI water gating of layered semiconductors can be harnessed in research on novel materials and devices, and it may with further development find broad applications in microelectronics and sensing.

Two-dimensional non-volatile programmable p-n junctions

NASA Astrophysics Data System (ADS)

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M.; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe2/hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 104 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

Two-dimensional non-volatile programmable p-n junctions.

PubMed

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe 2 /hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 10 4 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

Reconfigurable Diodes Based on Vertical WSe2 Transistors with van der Waals Bonded Contacts.

PubMed

Avsar, Ahmet; Marinov, Kolyo; Marin, Enrique Gonzalez; Iannaccone, Giuseppe; Watanabe, Kenji; Taniguchi, Takashi; Fiori, Gianluca; Kis, Andras

2018-05-01

New device concepts can increase the functionality of scaled electronic devices, with reconfigurable diodes allowing the design of more compact logic gates being one of the examples. In recent years, there has been significant interest in creating reconfigurable diodes based on ultrathin transition metal dichalcogenide crystals due to their unique combination of gate-tunable charge carriers, high mobility, and sizeable band gap. Thanks to their large surface areas, these devices are constructed under planar geometry and the device characteristics are controlled by electrostatic gating through rather complex two independent local gates or ionic-liquid gating. In this work, similar reconfigurable diode action is demonstrated in a WSe 2 transistor by only utilizing van der Waals bonded graphene and Co/h-BN contacts. Toward this, first the charge injection efficiencies into WSe 2 by graphene and Co/h-BN contacts are characterized. While Co/h-BN contact results in nearly Schottky-barrier-free charge injection, graphene/WSe 2 interface has an average barrier height of ≈80 meV. By taking the advantage of the electrostatic transparency of graphene and the different work-function values of graphene and Co/h-BN, vertical devices are constructed where different gate-tunable diode actions are demonstrated. This architecture reveals the opportunities for exploring new device concepts. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Nanoscale Multigate TiN Metal Nanocrystal Memory Using High-k Blocking Dielectric and High-Work-Function Gate Electrode Integrated on Silcon-on-Insulator Substrate

NASA Astrophysics Data System (ADS)

Lu, Chi-Pei; Luo, Cheng-Kei; Tsui, Bing-Yue; Lin, Cha-Hsin; Tzeng, Pei-Jer; Wang, Ching-Chiun; Tsai, Ming-Jinn

2009-04-01

In this study, a charge-trapping-layer-engineered nanoscale n-channel trigate TiN nanocrystal nonvolatile memory was successfully fabricated on silicon-on-insulator (SOI) wafer. An Al2O3 high-k blocking dielectric layer and a P+ polycrystalline silicon gate electrode were used to obtain low operation voltage and suppress the back-side injection effect, respectively. TiN nanocrystals were formed by annealing TiN/Al2O3 nanolaminates deposited by an atomic layer deposition system. The memory characteristics of various samples with different TiN wetting layer thicknesses, post-deposition annealing times, and blocking oxide thicknesses were also investigated. The sample with a thicker wetting layer exhibited a much larger memory window than other samples owing to its larger nanocrystal size. Good retention with a mere 12% charge loss for up to 10 years and high endurance were also obtained. Furthermore, gate disturbance and read disturbance were measured with very small charge migrations after a 103 s stressing bias.

Roads towards fault-tolerant universal quantum computation

NASA Astrophysics Data System (ADS)

Campbell, Earl T.; Terhal, Barbara M.; Vuillot, Christophe

2017-09-01

A practical quantum computer must not merely store information, but also process it. To prevent errors introduced by noise from multiplying and spreading, a fault-tolerant computational architecture is required. Current experiments are taking the first steps toward noise-resilient logical qubits. But to convert these quantum devices from memories to processors, it is necessary to specify how a universal set of gates is performed on them. The leading proposals for doing so, such as magic-state distillation and colour-code techniques, have high resource demands. Alternative schemes, such as those that use high-dimensional quantum codes in a modular architecture, have potential benefits, but need to be explored further.

Roads towards fault-tolerant universal quantum computation.

PubMed

Campbell, Earl T; Terhal, Barbara M; Vuillot, Christophe

2017-09-13

A practical quantum computer must not merely store information, but also process it. To prevent errors introduced by noise from multiplying and spreading, a fault-tolerant computational architecture is required. Current experiments are taking the first steps toward noise-resilient logical qubits. But to convert these quantum devices from memories to processors, it is necessary to specify how a universal set of gates is performed on them. The leading proposals for doing so, such as magic-state distillation and colour-code techniques, have high resource demands. Alternative schemes, such as those that use high-dimensional quantum codes in a modular architecture, have potential benefits, but need to be explored further.

Design and fabrication of high-performance diamond triple-gate field-effect transistors

PubMed Central

Liu, Jiangwei; Ohsato, Hirotaka; Wang, Xi; Liao, Meiyong; Koide, Yasuo

2016-01-01

The lack of large-area single-crystal diamond wafers has led us to downscale diamond electronic devices. Here, we design and fabricate a hydrogenated diamond (H-diamond) triple-gate metal-oxide-semiconductor field-effect transistor (MOSFET) to extend device downscaling and increase device output current. The device’s electrical properties are compared with those of planar-type MOSFETs, which are fabricated simultaneously on the same substrate. The triple-gate MOSFET’s output current (174.2 mA mm−1) is much higher than that of the planar-type device (45.2 mA mm−1), and the on/off ratio and subthreshold swing are more than 108 and as low as 110 mV dec−1, respectively. The fabrication of these H-diamond triple-gate MOSFETs will drive diamond electronic device development forward towards practical applications. PMID:27708372

Semiconductor systems utilizing materials that form rectifying junctions in both N and P-type doping regions, whether metallurgically or field induced, and methods of use

DOEpatents

Welch, James D.

2000-01-01

Disclosed are semiconductor systems, such as integrated circuits utilizing Schotky barrier and/or diffused junction technology, which semiconductor systems incorporate material(s) that form rectifying junctions in both metallurgically and/or field induced N and P-type doping regions, and methods of their use. Disclosed are Schottky barrier based inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems and which can be operated as modulators, N and P-channel MOSFETS and CMOS formed therefrom, and (MOS) gate voltage controlled rectification direction and gate voltage controlled switching devices, and use of such material(s) to block parasitic current flow pathways. Simple demonstrative five mask fabrication procedures for inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

L1 track trigger for the CMS HL-LHC upgrade using AM chips and FPGAs

NASA Astrophysics Data System (ADS)

Fedi, Giacomo

2017-08-01

The increase of luminosity at the HL-LHC will require the introduction of tracker information in CMS's Level-1 trigger system to maintain an acceptable trigger rate when selecting interesting events, despite the order of magnitude increase in minimum bias interactions. To meet the latency requirements, dedicated hardware has to be used. This paper presents the results of tests of a prototype system (pattern recognition ezzanine) as core of pattern recognition and track fitting for the CMS experiment, combining the power of both associative memory custom ASICs and modern Field Programmable Gate Array (FPGA) devices. The mezzanine uses the latest available associative memory devices (AM06) and the most modern Xilinx Ultrascale FPGAs. The results of the test for a complete tower comprising about 0.5 million patterns is presented, using as simulated input events traversing the upgraded CMS detector. The paper shows the performance of the pattern matching, track finding and track fitting, along with the latency and processing time needed. The pT resolution over pT of the muons measured using the reconstruction algorithm is at the order of 1% in the range 3-100 GeV/c.

Method and system for reducing device performance degradation of organic devices

DOEpatents

Teague, Lucile C.

2014-09-02

Methods and systems for reducing the deleterious effects of gate bias stress on the drain current of an organic device, such as an organic thin film transistor, are provided. In a particular aspect, the organic layer of an organic device is illuminated with light having characteristics selected to reduce the gate bias voltage effects on the drain current of the organic device. For instance, the wavelength and intensity of the light are selected to provide a desired recovery of drain current of the organic device. If the characteristics of the light are appropriately matched to the organic device, recovery of the deleterious effects caused by gate bias voltage stress effects on the drain current of the organic device can be achieved. In a particular aspect, the organic device is selectively illuminated with light to operate the organic device in multiple modes of operation.

Indium-gallium-zinc-oxide thin-film transistor with a planar split dual-gate structure

NASA Astrophysics Data System (ADS)

Liu, Yu-Rong; Liu, Jie; Song, Jia-Qi; Lai, Pui-To; Yao, Ruo-He

2017-12-01

An amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) with a planar split dual gate (PSDG) structure has been proposed, fabricated and characterized. Experimental results indicate that the two independent gates can provide dynamical control of device characteristics such as threshold voltage, sub-threshold swing, off-state current and saturation current. The transconductance extracted from the output characteristics of the device increases from 4.0 × 10-6S to 1.6 × 10-5S for a change of control gate voltage from -2 V to 2 V, and thus the device could be used in a variable-gain amplifier. A significant advantage of the PSDG structure is its flexibility in controlling the device performance according to the need of practical applications.

Gate protective device for SOS array

NASA Technical Reports Server (NTRS)

Meyer, J. E., Jr.; Scott, J. H.

1972-01-01

Protective gate device consisting of alternating heavily doped n(+) and p(+) diffusions eliminates breakdown voltages in silicon oxide on sapphire arrays caused by electrostatic discharge from person or equipment. Diffusions are easily produced during normal double epitaxial processing. Devices with nine layers had 27-volt breakdown.

Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11,000 cm(2)/V·s.

PubMed

Smith, Casey; Qaisi, Ramy; Liu, Zhihong; Yu, Qingkai; Hussain, Muhammad Mustafa

2013-07-23

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11,000 cm(2)/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low tox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance.

Monolithically integrated Si gate-controlled light-emitting device: science and properties

NASA Astrophysics Data System (ADS)

Xu, Kaikai

2018-02-01

The motivation of this study is to develop a p-n junction based light emitting device, in which the light emission is conventionally realized using reverse current driving, by voltage driving. By introducing an additional terminal of insulated gate for voltage driving, a novel three-terminal Si light emitting device is described where both the light intensity and spatial light pattern of the device are controlled by the gate voltage. The proposed light emitting device employs injection-enhanced Si in avalanche mode where electric field confinement occurs in the corner of a reverse-biased p+n junction. It is found that, depending on the bias conditions, the light intensity is either a linear or a quadratic function of the applied gate voltage or the reverse-bias. Since the light emission is based on the avalanching mode, the Si light emitting device offers the potential for very large scale integration-compatible light emitters for inter- or intra-chip signal transmission and contactless functional testing of wafers.

Effect with high density nano dot type storage layer structure on 20 nm planar NAND flash memory characteristics

NASA Astrophysics Data System (ADS)

Sasaki, Takeshi; Muraguchi, Masakazu; Seo, Moon-Sik; Park, Sung-kye; Endoh, Tetsuo

2014-01-01

The merits, concerns and design principle for the future nano dot (ND) type NAND flash memory cell are clarified, by considering the effect of storage layer structure on NAND flash memory characteristics. The characteristics of the ND cell for a NAND flash memory in comparison with the floating gate type (FG) is comprehensively studied through the read, erase, program operation, and the cell to cell interference with device simulation. Although the degradation of the read throughput (0.7% reduction of the cell current) and slower program time (26% smaller programmed threshold voltage shift) with high density (10 × 1012 cm-2) ND NAND are still concerned, the suppress of the cell to cell interference with high density (10 × 1012 cm-2) plays the most important part for scaling and multi-level cell (MLC) operation in comparison with the FG NAND. From these results, the design knowledge is shown to require the control of the number of nano dots rather than the higher nano dot density, from the viewpoint of increasing its memory capacity by MLC operation and suppressing threshold voltage variability caused by the number of dots in the storage layer. Moreover, in order to increase its memory capacity, it is shown the tunnel oxide thickness with ND should be designed thicker (>3 nm) than conventional designed ND cell for programming/erasing with direct tunneling mechanism.

Fault handling schemes in electronic systems with specific application to radiation tolerance and VLSI design

NASA Technical Reports Server (NTRS)

Attia, John Okyere

1993-01-01

Naturally occurring space radiation particles can produce transient and permanent changes in the electrical properties of electronic devices and systems. In this work, the transient radiation effects on DRAM and CMOS SRAM were considered. In addition, the effect of total ionizing dose radiation of the switching times of CMOS logic gates were investigated. Effects of transient radiation on the column and cell of MOS dynamic memory cell was simulated using SPICE. It was found that the critical charge of the bitline was higher than that of the cell. In addition, the critical charge of the combined cell-bitline was found to be dependent on the gate voltage of the access transistor. In addition, the effect of total ionizing dose radiation on the switching times of CMOS logic gate was obtained. The results of this work indicate that, the rise time of CMOS logic gates increases, while the fall time decreases with an increase in total ionizing dose radiation. Also, by increasing the size of the P-channel transistor with respect to that of the N-channel transistor, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in total ionizing dose radiation. Furthermore, a method was developed for replacing polysilicon feedback resistance of SRAMs with a switched capacitor network. A switched capacitor SRAM was implemented using MOS Technology. The critical change of the switched capacitor SRAM has a very large critical charge. The results of this work indicate that switched capacitor SRAM is a viable alternative to SRAM with polysilicon feedback resistance.

Simulation of InGaAs subchannel DG-HEMTs for analogue/RF applications

NASA Astrophysics Data System (ADS)

Saravana Kumar, R.; Mohanbabu, A.; Mohankumar, N.; Godwin Raj, D.

2018-03-01

The paper reports on the influence of a barrier thickness and gate length on the various device parameters of double gate high electron mobility transistors (DG-HEMTs). The DC and RF performance of the device have been studied by varying the barrier thickness from 1 to 5 nm and gate length from 10 to 150 nm, respectively. As the gate length is reduced below 50 nm regime, the barrier thickness plays an important role in device performance. Scaling the gate length leads to higher transconductance and high frequency operations with the expense of poor short channel effects. The authors claim that the 30-nm gate length, mole fractions tuned In0.53Ga0.47As/In0.7Ga0.3As/In0.53Ga0.47As subchannel DG-HEMT with optimised device structure of 2 nm In0.48Al0.52As barrier layer show a peak gm of 3.09 mS/µm, VT of 0.29 V, ION/IOFF ratio of 2.24 × 105, subthreshold slope 73 mV/decade and drain induced barrier lowering 68 mV/V with fT and fmax of 776 and 905 GHz at Vds = 0.5 V is achieved. These superior performances are achieved by using double-gate architecture with reduced gate to channel distance.

A Component-Based FPGA Design Framework for Neuronal Ion Channel Dynamics Simulations

PubMed Central

Mak, Terrence S. T.; Rachmuth, Guy; Lam, Kai-Pui; Poon, Chi-Sang

2008-01-01

Neuron-machine interfaces such as dynamic clamp and brain-implantable neuroprosthetic devices require real-time simulations of neuronal ion channel dynamics. Field Programmable Gate Array (FPGA) has emerged as a high-speed digital platform ideal for such application-specific computations. We propose an efficient and flexible component-based FPGA design framework for neuronal ion channel dynamics simulations, which overcomes certain limitations of the recently proposed memory-based approach. A parallel processing strategy is used to minimize computational delay, and a hardware-efficient factoring approach for calculating exponential and division functions in neuronal ion channel models is used to conserve resource consumption. Performances of the various FPGA design approaches are compared theoretically and experimentally in corresponding implementations of the AMPA and NMDA synaptic ion channel models. Our results suggest that the component-based design framework provides a more memory economic solution as well as more efficient logic utilization for large word lengths, whereas the memory-based approach may be suitable for time-critical applications where a higher throughput rate is desired. PMID:17190033

Photo-assisted hysteresis of electronic transport for ZnO nanowire transistors

NASA Astrophysics Data System (ADS)

Du, Qianqian; Ye, Jiandong; Xu, Zhonghua; Zhu, Shunming; Tang, Kun; Gu, Shulin; Zheng, Youdou

2018-03-01

Recently, ZnO nanowire field effect transistors (FETs) have received renewed interest due to their extraordinary low dimensionality and high sensitivity to external chemical environments and illumination conditions. These prominent properties have promising potential in nanoscale chemical and photo-sensors. In this article, we have fabricated ZnO nanowire FETs and have found hysteresis behavior in their transfer characteristics. The mechanism and dynamics of the hysteresis phenomena have been investigated in detail by varying the sweeping rate and range of the gate bias with and without light irradiation. Significantly, light irradiation is of great importance on charge trapping by regulating adsorption and desorption of oxygen at the interface of ZnO/SiO2. Carriers excited by light irradiation can dramatically promote trapping/detrapping processes. With the assistance of light illumination, we have demonstrated a photon-assisted nonvolatile memory which employs the ZnO nanowire FET. The device exhibits reliable programming/erasing operations and a large on/off ratio. The proposed proto-type memory has thus provided a possible novel path for creating a memory functionality to other low-dimensional material systems.

Self-assembled oxide films with tailored nanoscale ionic and electronic channels for controlled resistive switching

NASA Astrophysics Data System (ADS)

Cho, Seungho; Yun, Chao; Tappertzhofen, Stefan; Kursumovic, Ahmed; Lee, Shinbuhm; Lu, Ping; Jia, Quanxi; Fan, Meng; Jian, Jie; Wang, Haiyan; Hofmann, Stephan; MacManus-Driscoll, Judith L.

2016-08-01

Resistive switches are non-volatile memory cells based on nano-ionic redox processes that offer energy efficient device architectures and open pathways to neuromorphics and cognitive computing. However, channel formation typically requires an irreversible, not well controlled electroforming process, giving difficulty to independently control ionic and electronic properties. The device performance is also limited by the incomplete understanding of the underlying mechanisms. Here, we report a novel memristive model material system based on self-assembled Sm-doped CeO2 and SrTiO3 films that allow the separate tailoring of nanoscale ionic and electronic channels at high density (~1012 inch-2). We systematically show that these devices allow precise engineering of the resistance states, thus enabling large on-off ratios and high reproducibility. The tunable structure presents an ideal platform to explore ionic and electronic mechanisms and we expect a wide potential impact also on other nascent technologies, ranging from ionic gating to micro-solid oxide fuel cells and neuromorphics.

Optical bistability for optical signal processing and computing

NASA Astrophysics Data System (ADS)

Peyghambarian, N.; Gibbs, H. M.

1985-02-01

Optical bistability (OB) is a phenomenon in which a nonlinear medium responds to an optical input beam by changing its transmission abruptly from one value to another. A 'nonlinear medium' is a medium in which the index of refraction depends on the incident light intensity. A device is said to be optically bistable if two stable output states exist for the same value of the input. Optically bistable devices can perform a number of logic functions related to optical memory, optical transistor, optical discriminator, optical limiter, optical oscillator, and optical gate. They also have the potential for subpicosecond switching, greatly exceeding the capability of electronics. This potential is one of several advantages of optical data processing over electronic processing. Other advantages are greater immunity to electromagnetic interference and crosstalk, and highly parallel processing capability. The present investigation is mainly concerned with all-optical etalon devices. The considered materials, include GaAs, ZnS and ZnSe, CuCl, InSb, InAs, and CdS.

A Content-Addressable Memory structure using quantum cells in nanotechnology with energy dissipation analysis

NASA Astrophysics Data System (ADS)

Sadoghifar, Ali; Heikalabad, Saeed Rasouli

2018-05-01

Quantum-dot cellular automata is one of the recent new technologies at the nanoscale that can be a suitable replacement for CMOS technology. The circuits constructed in QCA technology have desirable features such as low power consumption, high speed and small size. These features can be more distinct in memory structures. In this paper, we design a new structure for content addressable memory cell in QCA. For this purpose, first, a unique gate is introduced for mask operation in QCA and then this gate is used to improve the performance of CAM. These structures are evaluated with QCADesigner simulator.

Unifying Gate Synthesis and Magic State Distillation.

PubMed

Campbell, Earl T; Howard, Mark

2017-02-10

The leading paradigm for performing a computation on quantum memories can be encapsulated as distill-then-synthesize. Initially, one performs several rounds of distillation to create high-fidelity magic states that provide one good T gate, an essential quantum logic gate. Subsequently, gate synthesis intersperses many T gates with Clifford gates to realize a desired circuit. We introduce a unified framework that implements one round of distillation and multiquibit gate synthesis in a single step. Typically, our method uses the same number of T gates as conventional synthesis but with the added benefit of quadratic error suppression. Because of this, one less round of magic state distillation needs to be performed, leading to significant resource savings.

Device optimization and scaling properties of a gate-on-germanium source tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Chattopadhyay, Avik; Mallik, Abhijit; Omura, Yasuhisa

2015-06-01

A gate-on-germanium source (GoGeS) tunnel field-effect transistor (TFET) shows great promise for low-power (sub-0.5 V) applications. A detailed investigation, with the help of a numerical device simulator, on the effects of variation in different structural parameters of a GoGeS TFET on its electrical performance is reported in this paper. Structural parameters such as κ-value of the gate dielectric, length and κ-value of the spacer, and doping concentrations of both the substrate and source are considered. A low-κ symmetric spacer and a high-κ gate dielectric are found to yield better device performance. The substrate doping influences only the p-i-n leakage floor. The source doping is found to significantly affect performance parameters such as OFF-state current, ON-state current and subthreshold swing, in addition to a threshold voltage shift. Results of the investigation on the gate length scaling of such devices are also reported in this paper.

Power reduction by power gating in differential pair type spin-transfer-torque magnetic random access memories for low-power nonvolatile cache memories

NASA Astrophysics Data System (ADS)

Ohsawa, Takashi; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2014-01-01

Array operation currents in spin-transfer-torque magnetic random access memories (STT-MRAMs) that use four differential pair type magnetic tunnel junction (MTJ)-based memory cells (4T2MTJ, two 6T2MTJs and 8T2MTJ) are simulated and compared with that in SRAM. With L3 cache applications in mind, it is assumed that the memories are composed of 32 Mbyte capacity to be accessed in 64 byte in parallel. All the STT-MRAMs except for the 8T2MTJ one are designed with 32 bit fine-grained power gating scheme applied to eliminate static currents in the memory cells that are not accessed. The 8T2MTJ STT-MRAM, the cell’s design concept being not suitable for the fine-grained power gating, loads and saves 32 Mbyte data in 64 Mbyte unit per 1 Mbit sub-array in 2 × 103 cycles. It is shown that the array operation current of the 4T2MTJ STT-MRAM is 70 mA averaged in 15 ns write cycles at Vdd = 0.9 V. This is the smallest among the STT-MRAMs, about the half of the low standby power (LSTP) SRAM whose array operation current is totally dominated by the cells’ subthreshold leakage.

Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

NASA Astrophysics Data System (ADS)

Yamamoto, Shuu'ichirou; Shuto, Yusuke; Sugahara, Satoshi

2013-07-01

We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks. Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-02-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-05-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

2D Quantum Transport Modeling in Nanoscale MOSFETs

NASA Technical Reports Server (NTRS)

Svizhenko, Alexei; Anantram, M. P.; Govindan, T. R.; Biegel, Bryan

2001-01-01

With the onset of quantum confinement in the inversion layer in nanoscale MOSFETs, behavior of the resonant level inevitably determines all device characteristics. While most classical device simulators take quantization into account in some simplified manner, the important details of electrostatics are missing. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL, and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density- gradient and quantum-corrected MEDICI). We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions, oxide tunneling and phase-breaking scattering are treated on equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. Quantum simulations are focused on MIT 25, 50 and 90 nm "well- tempered" MOSFETs and compared to classical and quantum corrected models. The important feature of quantum model is smaller slope of Id-Vg curve and consequently higher threshold voltage. These results are quantitatively consistent with I D Schroedinger-Poisson calculations. The effect of gate length on gate-oxide leakage and sub-threshold current has been studied. The shorter gate length device has an order of magnitude smaller current at zero gate bias than the longer gate length device without a significant trade-off in on-current. This should be a device design consideration.

Perspective analysis of tri gate germanium tunneling field-effect transistor with dopant segregation region at source/drain

NASA Astrophysics Data System (ADS)

Liu, Liang-kui; Shi, Cheng; Zhang, Yi-bo; Sun, Lei

2017-04-01

A tri gate Ge-based tunneling field-effect transistor (TFET) has been numerically studied with technology computer aided design (TCAD) tools. Dopant segregated Schottky source/drain is applied to the device structure design (DS-TFET). The characteristics of the DS-TFET are compared and analyzed comprehensively. It is found that the performance of n-channel tri gate DS-TFET with a positive bias is insensitive to the dopant concentration and barrier height at n-type drain, and that the dopant concentration and barrier height at a p-type source considerably affect the device performance. The domination of electron current in the entire BTBT current of this device accounts for this phenomenon and the tri-gate DS-TFET is proved to have a higher performance than its dual-gate counterpart.

On Using the Volatile Mem-Capacitive Effect of TiO2 Resistive Random Access Memory to Mimic the Synaptic Forgetting Process

NASA Astrophysics Data System (ADS)

Sarkar, Biplab; Mills, Steven; Lee, Bongmook; Pitts, W. Shepherd; Misra, Veena; Franzon, Paul D.

2018-02-01

In this work, we report on mimicking the synaptic forgetting process using the volatile mem-capacitive effect of a resistive random access memory (RRAM). TiO2 dielectric, which is known to show volatile memory operations due to migration of inherent oxygen vacancies, was used to achieve the volatile mem-capacitive effect. By placing the volatile RRAM candidate along with SiO2 at the gate of a MOS capacitor, a volatile capacitance change resembling the forgetting nature of a human brain is demonstrated. Furthermore, the memory operation in the MOS capacitor does not require a current flow through the gate dielectric indicating the feasibility of obtaining low power memory operations. Thus, the mem-capacitive effect of volatile RRAM candidates can be attractive to the future neuromorphic systems for implementing the forgetting process of a human brain.

Quantitative Analysis of Charge Injection and Discharging of Si Nanocrystals and Arrays by Electrostatic Force Microscopy

NASA Technical Reports Server (NTRS)

Bell, L. D.; Boer, E.; Ostraat, M.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.

2000-01-01

NASA requirements for computing and memory for microspacecraft emphasize high density, low power, small size, and radiation hardness. The distributed nature of storage elements in nanocrystal floating-gate memories leads to intrinsic fault tolerance and radiation hardness. Conventional floating-gate non-volatile memories are more susceptible to radiation damage. Nanocrystal-based memories also offer the possibility of faster, lower power operation. In the pursuit of filling these requirements, the following tasks have been accomplished: (1) Si nanocrystal charging has been accomplished with conducting-tip AFM; (2) Both individual nanocrystals on an oxide surface and nanocrystals formed by implantation have been charged; (3) Discharging is consistent with tunneling through a field-lowered oxide barrier; (4) Modeling of the response of the AFM to trapped charge has allowed estimation of the quantity of trapped charge; and (5) Initial attempts to fabricate competitive nanocrystal non-volatile memories have been extremely successful.

14 CFR 25.145 - Longitudinal control.

Code of Federal Regulations, 2010 CFR

2010-01-01

... complete retraction of the high lift devices from any position is begun during steady, straight, level...) If gated high-lift device control positions are provided, paragraph (c) of this section applies to retractions of the high-lift devices from any position from the maximum landing position to the first gated...

A two-dimensional analytical modeling for channel potential and threshold voltage of short channel triple material symmetrical gate Stack (TMGS) DG-MOSFET

NASA Astrophysics Data System (ADS)

Tripathi, Shweta

2016-10-01

In the present work, a two-dimensional (2D) analytical framework of triple material symmetrical gate stack (TMGS) DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS™ device simulator to affirm and formalize the proposed device structure.

Scaling of Device Variability and Subthreshold Swing in Ballistic Carbon Nanotube Transistors

NASA Astrophysics Data System (ADS)

Cao, Qing; Tersoff, Jerry; Han, Shu-Jen; Penumatcha, Ashish V.

2015-08-01

In field-effect transistors, the inherent randomness of dopants and other charges is a major cause of device-to-device variability. For a quasi-one-dimensional device such as carbon nanotube transistors, even a single charge can drastically change the performance, making this a critical issue for their adoption as a practical technology. Here we calculate the effect of the random charges at the gate-oxide surface in ballistic carbon nanotube transistors, finding good agreement with the variability statistics in recent experiments. A combination of experimental and simulation results further reveals that these random charges are also a major factor limiting the subthreshold swing for nanotube transistors fabricated on thin gate dielectrics. We then establish that the scaling of the nanotube device uniformity with the gate dielectric, fixed-charge density, and device dimension is qualitatively different from conventional silicon transistors, reflecting the very different device physics of a ballistic transistor with a quasi-one-dimensional channel. The combination of gate-oxide scaling and improved control of fixed-charge density should provide the uniformity needed for large-scale integration of such novel one-dimensional transistors even at extremely scaled device dimensions.

Fabrication of quantum dots in undoped Si/Si 0.8Ge 0.2 heterostructures using a single metal-gate layer

DOE PAGES

Lu, T. M.; Gamble, J. K.; Muller, R. P.; ...

2016-08-01

Enhancement-mode Si/SiGe electron quantum dots have been pursued extensively by many groups for their potential in quantum computing. Most of the reported dot designs utilize multiple metal-gate layers and use Si/SiGe heterostructures with Ge concentration close to 30%. Here, we report the fabrication and low-temperature characterization of quantum dots in the Si/Si 0.8Ge 0.2 heterostructures using only one metal-gate layer. We find that the threshold voltage of a channel narrower than 1 μm increases as the width decreases. The higher threshold can be attributed to the combination of quantum confinement and disorder. We also find that the lower Ge ratiomore » used here leads to a narrower operational gate bias range. The higher threshold combined with the limited gate bias range constrains the device design of lithographic quantum dots. We incorporate such considerations in our device design and demonstrate a quantum dot that can be tuned from a single dot to a double dot. Furthermore, the device uses only a single metal-gate layer, greatly simplifying device design and fabrication.« less

Effects of structure and oxygen flow rate on the photo-response of amorphous IGZO-based photodetector devices

NASA Astrophysics Data System (ADS)

Jang, Jun Tae; Ko, Daehyun; Choi, Sungju; Kang, Hara; Kim, Jae-Young; Yu, Hye Ri; Ahn, Geumho; Jung, Haesun; Rhee, Jihyun; Lee, Heesung; Choi, Sung-Jin; Kim, Dong Myong; Kim, Dae Hwan

2018-02-01

In this study, we investigated how the structure and oxygen flow rate (OFR) during the sputter-deposition affects the photo-responses of amorphous indium-gallium-zinc-oxide (a-IGZO)-based photodetector devices. As the result of comparing three types of device structures with one another, which are a global Schottky diode, local Schottky diode, and thin-film transistor (TFT), the IGZO TFT with the gate pulse technique suppressing the persistent photoconductivity (PPC) is the most promising photodetector in terms of a high photo-sensitivity and uniform sensing characteristic. In order to analyze the IGZO TFT-based photodetectors more quantitatively, the time-evolution of sub-gap density-of-states (DOS) was directly observed under photo-illumination and consecutively during the PPC-compensating period with applying the gate pulse. It shows that the increased ionized oxygen vacancy (VO2+) defects under photo-illumination was fully recovered by the positive gate pulse and even overcompensated by additional electron trapping. Based on experimentally extracted sub-gap DOS, the origin on PPC was successfully decomposed into the hole trapping and the VO ionization. Although the VO ionization is enhanced in lower OFR (O-poor) device, the PPC becomes more severe in high OFR (O-rich) device because the hole trapping dominates the PPC in IGZO TFT under photo-illumination rather than the VO ionization and more abundant holes are trapped into gate insulator and/or interface in O-rich TFTs. Similarly, the electron trapping during the PPC-compensating period with applying the positive gate pulse becomes more prominent in O-rich TFTs. It is attributed to more hole/electron traps in the gate insulator and/or interface, which is associated with oxygen interstitials, or originates from the ion bombardment-related lower quality gate oxide in O-rich devices.

Engineering modular and orthogonal genetic logic gates for robust digital-like synthetic biology.

PubMed

Wang, Baojun; Kitney, Richard I; Joly, Nicolas; Buck, Martin

2011-10-18

Modular and orthogonal genetic logic gates are essential for building robust biologically based digital devices to customize cell signalling in synthetic biology. Here we constructed an orthogonal AND gate in Escherichia coli using a novel hetero-regulation module from Pseudomonas syringae. The device comprises two co-activating genes hrpR and hrpS controlled by separate promoter inputs, and a σ(54)-dependent hrpL promoter driving the output. The hrpL promoter is activated only when both genes are expressed, generating digital-like AND integration behaviour. The AND gate is demonstrated to be modular by applying new regulated promoters to the inputs, and connecting the output to a NOT gate module to produce a combinatorial NAND gate. The circuits were assembled using a parts-based engineering approach of quantitative characterization, modelling, followed by construction and testing. The results show that new genetic logic devices can be engineered predictably from novel native orthogonal biological control elements using quantitatively in-context characterized parts. © 2011 Macmillan Publishers Limited. All rights reserved.

Design and performance of a respiratory amplitude gating device for PET/CT imaging

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chang Guoping; Chang Tingting; Clark, John W. Jr.

2010-04-15

Purpose: Recently, the authors proposed a free-breathing amplitude gating (FBAG) technique for PET/CT scanners. The implementation of this technique required specialized hardware and software components that were specifically designed to interface with commercial respiratory gating devices to generate the necessary triggers required for the FBAG technique. The objective of this technical note is to introduce an in-house device that integrates all the necessary hardware and software components as well as tracks the patient's respiratory motion to realize amplitude gating on PET/CT scanners. Methods: The in-house device is composed of a piezoelectric transducer coupled to a data-acquisition system in order tomore » monitor the respiratory waveform. A LABVIEW program was designed to control the data-acquisition device and inject triggers into the PET list stream whenever the detected respiratory amplitude crossed a predetermined amplitude range. A timer was also programmed to stop the scan when the accumulated time within the selected amplitude range reached a user-set interval. This device was tested using a volunteer and a phantom study. Results: The results from the volunteer and phantom studies showed that the in-house device can detect similar respiratory signals as commercially available respiratory gating systems and is able to generate the necessary triggers to suppress respiratory motion artifacts. Conclusions: The proposed in-house device can be used to implement the FBAG technique in current PET/CT scanners.« less

Motion-gated acquisition for in vivo optical imaging

PubMed Central

Gioux, Sylvain; Ashitate, Yoshitomo; Hutteman, Merlijn; Frangioni, John V.

2009-01-01

Wide-field continuous wave fluorescence imaging, fluorescence lifetime imaging, frequency domain photon migration, and spatially modulated imaging have the potential to provide quantitative measurements in vivo. However, most of these techniques have not yet been successfully translated to the clinic due to challenging environmental constraints. In many circumstances, cardiac and respiratory motion greatly impair image quality and∕or quantitative processing. To address this fundamental problem, we have developed a low-cost, field-programmable gate array–based, hardware-only gating device that delivers a phase-locked acquisition window of arbitrary delay and width that is derived from an unlimited number of pseudo-periodic and nonperiodic input signals. All device features can be controlled manually or via USB serial commands. The working range of the device spans the extremes of mouse electrocardiogram (1000 beats per minute) to human respiration (4 breaths per minute), with timing resolution ⩽0.06%, and jitter ⩽0.008%, of the input signal period. We demonstrate the performance of the gating device, including dramatic improvements in quantitative measurements, in vitro using a motion simulator and in vivo using near-infrared fluorescence angiography of beating pig heart. This gating device should help to enable the clinical translation of promising new optical imaging technologies. PMID:20059276

Gallium arsenide processing for gate array logic

NASA Technical Reports Server (NTRS)

Cole, Eric D.

1989-01-01

The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

Interface engineering of semiconductor/dielectric heterojunctions toward functional organic thin-film transistors.

PubMed

Zhang, Hongtao; Guo, Xuefeng; Hui, Jingshu; Hu, Shuxin; Xu, Wei; Zhu, Daoben

2011-11-09

Interface modification is an effective and promising route for developing functional organic field-effect transistors (OFETs). In this context, however, researchers have not created a reliable method of functionalizing the interfaces existing in OFETs, although this has been crucial for the technological development of high-performance CMOS circuits. Here, we demonstrate a novel approach that enables us to reversibly photocontrol the carrier density at the interface by using photochromic spiropyran (SP) self-assembled monolayers (SAMs) sandwiched between active semiconductors and gate insulators. Reversible changes in dipole moment of SPs in SAMs triggered by lights with different wavelengths produce two distinct built-in electric fields on the OFET that can modulate the channel conductance and consequently threshold voltage values, thus leading to a low-cost noninvasive memory device. This concept of interface functionalization offers attractive new prospects for the development of organic electronic devices with tailored electronic and other properties.

Magneto-Ionic Control of Interfacial Magnetic Anisotorpy

NASA Astrophysics Data System (ADS)

Bauer, Uwe; Emori, Satoru; Beach, Geoffrey

2014-03-01

Voltage control of magnetism could bring about revolutionary new spintronic memory and logic devices. Here, we examine domain wall (DW) dynamics in ultrathin Co films and nanowires under the influence of a voltage applied across a gadolinium oxide gate dielectric that simultaneously acts as an oxygen ion conductor. We investigate two electrode configurations, one with a continuous gate dielectric and the other with a patterned gate dielectric which exhibits an open oxide edge right underneath the electrode perimeter. We demonstrate that the open oxide edge acts as a fast diffusion path for oxygen ions and allows voltage-induced switching of magnetic anisotropy at the nanoscale by modulating interfacial chemistry rather than charge density. At room temperature this effect is limited to the vicinity of the open oxide edge, but at a temperature of 100°C it allows complete control over magnetic anisotropy across the whole electrode area, due to higher oxygen ion mobility at elevated temperature. We then harness this novel ``magneto-ionic'' effect to create unprecedentedly strong voltage-induced anisotropy modifications of 3000 fJ/Vm and create electrically programmable DW traps with pinning strengths of 650 Oe, enough to bring to a standstill DWs travelling at speeds of at least 20 m/s. This work is supported by the National Science Foundation through grant ECCS-1128439.

Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II-VI Tunnel Insulators

NASA Astrophysics Data System (ADS)

Suarez, E.; Gogna, M.; Al-Amoody, F.; Karmakar, S.; Ayers, J.; Heller, E.; Jain, F.

2010-07-01

This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn0.95Mg0.05S/ZnS tunnel insulators. The GeO x -cladded Ge and SiO x -cladded Si quantum dots (QDs) are self-assembled site-specifically on the II-VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudomorphic II-VI stack serves both as a tunnel insulator and a high- κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si3N4 and SiO2 layers grown by plasma- enhanced chemical vapor deposition.

Operation of a gated field emitter using an individual carbon nanofiber cathode

NASA Astrophysics Data System (ADS)

Guillorn, M. A.; Melechko, A. V.; Merkulov, V. I.; Ellis, E. D.; Britton, C. L.; Simpson, M. L.; Lowndes, D. H.; Baylor, L. R.

2001-11-01

We report on the operation of an integrated gated cathode device using a single vertically aligned carbon nanofiber as the field emission element. This device is capable of operation in a moderate vacuum for extended periods of time without experiencing a degradation of performance. Less than 1% of the total emitted current is collected by the gate electrode, indicating that the emitted electron beam is highly collimated. As a consequence, this device is ideal for applications that require well-focused electron emission from a microscale structure.

Impact of Lateral Straggle on the Analog/RF Performance of Asymmetric Gate Stack Double Gate MOSFET

NASA Astrophysics Data System (ADS)

Sivaram, Gollamudi Sai; Chakraborty, Shramana; Das, Rahul; Dasgupta, Arpan; Kundu, Atanu; Sarkar, Chandan K.

2016-09-01

This paper presents a systematic comparative study of Analog and RF performances of an underlapped double gate (U-DG) NMOSFET with Gate Stack (GS) for varying straggle lengths. Asymmetric underlap devices (A-U-DG) have been proposed as one of the remedies for reducing Short Channel Effects (SCE's) with the underlap being present towards the source for sub 20 nm devices. However, the Source to Drain (S/D) implant lateral diffusion leads to a variation in the effective underlap length. This paper investigates the impact of variation of straggle length on the Analog and RF parameters of the device. The RF performance is analyzed by considering the intrinsic capacitances (Cgd, Cgs), intrinsic resistances (Rgd, Rgs), transport delay (τm), inductance (Lsd), cutoff frequency (fT), and the maximum frequency of oscillations (fmax). The circuit performance of the devices are also studied. It is seen that the Analog and RF performances of the devices are improved by optimizing the S/D lateral straggle.

Impact of strain on electronic and transport properties of 6 nm hydrogenated germanane nano-ribbon channel double gate field effect transistor

NASA Astrophysics Data System (ADS)

Meher Abhinav, E.; Sundararaj, Anuraj; Gopalakrishnan, Chandrasekaran; Kasmir Raja, S. V.; Chokhra, Saurabh

2017-11-01

In this work, chair like fully hydrogenated germanane (CGeH) nano-ribbon 6 nm short channel double gate field effect transistor (DG-FET) has been modeled and the impact of strain on the I-V characteristics of CGeH channel has been examined. The bond lengths, binding and formation energies of various hydrogenated geometries of buckled germanane channel were calculated using local density approximation (LDA) with Perdew-Zunger (PZ) and generalized gradient approximation (GGA) with Perdew Burke Ernzerhof (PBE) parameterization. From four various geometries, chair like structure is found to be more stable compared to boat like obtuse, stiruup structure and table like structure. The bandgap versus width, bandgap versus strain characteristics and I-V characteristics had been analyzed at room temperature using density functional theory (DFT). Using self consistent calculation it was observed that the electronic properties of nano-ribbon is independent of length and band structure, but dependent on edge type, strain [Uni-axial (ɛ xx ), bi-axial (ɛ xx   =  ɛ yy )] and width of the ribbon. The strain engineered hydrogenated germanane (GeH) showed wide direct bandgap (2.3 eV) which could help to build low noise electronic devices that operates at high frequencies. The observed bi-axial compression has high impact on the device transport characteristics with peak to valley ratio (PVR) of 2.14 and 380% increase in peak current compared to pristine CGeH device. The observed strain in CGeH DG-FET could facilitate in designing novel multiple-logic memory devices due to multiple negative differential resistance (NDR) regions.

On the physical operation and optimization of the p-GaN gate in normally-off GaN HEMT devices

NASA Astrophysics Data System (ADS)

Efthymiou, L.; Longobardi, G.; Camuso, G.; Chien, T.; Chen, M.; Udrea, F.

2017-03-01

In this study, an investigation is undertaken to determine the effect of gate design parameters on the on-state characteristics (threshold voltage and gate turn-on voltage) of pGaN/AlGaN/GaN high electron mobility transistors (HEMTs). Design parameters considered are pGaN doping and gate metal work function. The analysis considers the effects of variations on these parameters using a TCAD model matched with experimental results. A better understanding of the underlying physics governing the operation of these devices is achieved with a view to enable better optimization of such gate designs.

Development of Low Parasitic Light Sensitivity and Low Dark Current 2.8 μm Global Shutter Pixel †

PubMed Central

Yokoyama, Toshifumi; Tsutsui, Masafumi; Suzuki, Masakatsu; Nishi, Yoshiaki; Mizuno, Ikuo; Lahav, Assaf

2018-01-01

We developed a low parasitic light sensitivity (PLS) and low dark current 2.8 μm global shutter pixel. We propose a new inner lens design concept to realize both low PLS and high quantum efficiency (QE). 1/PLS is 7700 and QE is 62% at a wavelength of 530 nm. We also propose a new storage-gate based memory node for low dark current. P-type implants and negative gate biasing are introduced to suppress dark current at the surface of the memory node. This memory node structure shows the world smallest dark current of 9.5 e−/s at 60 °C. PMID:29370146

Development of Low Parasitic Light Sensitivity and Low Dark Current 2.8 μm Global Shutter Pixel.

PubMed

Yokoyama, Toshifumi; Tsutsui, Masafumi; Suzuki, Masakatsu; Nishi, Yoshiaki; Mizuno, Ikuo; Lahav, Assaf

2018-01-25

Abstract : We developed a low parasitic light sensitivity (PLS) and low dark current 2.8 μm global shutter pixel. We propose a new inner lens design concept to realize both low PLS and high quantum efficiency (QE). 1/PLS is 7700 and QE is 62% at a wavelength of 530 nm. We also propose a new storage-gate based memory node for low dark current. P-type implants and negative gate biasing are introduced to suppress dark current at the surface of the memory node. This memory node structure shows the world smallest dark current of 9.5 e - /s at 60 °C.

Cryogenic on-chip multiplexer for the study of quantum transport in 256 split-gate devices

NASA Astrophysics Data System (ADS)

Al-Taie, H.; Smith, L. W.; Xu, B.; See, P.; Griffiths, J. P.; Beere, H. E.; Jones, G. A. C.; Ritchie, D. A.; Kelly, M. J.; Smith, C. G.

2013-06-01

We present a multiplexing scheme for the measurement of large numbers of mesoscopic devices in cryogenic systems. The multiplexer is used to contact an array of 256 split gates on a GaAs/AlGaAs heterostructure, in which each split gate can be measured individually. The low-temperature conductance of split-gate devices is governed by quantum mechanics, leading to the appearance of conductance plateaux at intervals of 2e2/h. A fabrication-limited yield of 94% is achieved for the array, and a "quantum yield" is also defined, to account for disorder affecting the quantum behaviour of the devices. The quantum yield rose from 55% to 86% after illuminating the sample, explained by the corresponding increase in carrier density and mobility of the two-dimensional electron gas. The multiplexer is a scalable architecture, and can be extended to other forms of mesoscopic devices. It overcomes previous limits on the number of devices that can be fabricated on a single chip due to the number of electrical contacts available, without the need to alter existing experimental set ups.

An intelligent 1:2 demultiplexer as an intracellular theranostic device based on DNA/Ag cluster-gated nanovehicles

NASA Astrophysics Data System (ADS)

Ran, Xiang; Wang, Zhenzhen; Ju, Enguo; Pu, Fang; Song, Yanqiu; Ren, Jinsong; Qu, Xiaogang

2018-02-01

The logic device demultiplexer can convey a single input signal into one of multiple output channels. The choice of the output channel is controlled by a selector. Several molecules and biomolecules have been used to mimic the function of a demultiplexer. However, the practical application of logic devices still remains a big challenge. Herein, we design and construct an intelligent 1:2 demultiplexer as a theranostic device based on azobenzene (azo)-modified and DNA/Ag cluster-gated nanovehicles. The configuration of azo and the conformation of the DNA ensemble can be regulated by light irradiation and pH, respectively. The demultiplexer which uses light as the input and acid as the selector can emit red fluorescence or a release drug under different conditions. Depending on different cells, the intelligent logic device can select the mode of cellular imaging in healthy cells or tumor therapy in tumor cells. The study incorporates the logic gate with the theranostic device, paving the way for tangible applications of logic gates in the future.

An intelligent 1:2 demultiplexer as an intracellular theranostic device based on DNA/Ag cluster-gated nanovehicles.

PubMed

Ran, Xiang; Wang, Zhenzhen; Ju, Enguo; Pu, Fang; Song, Yanqiu; Ren, Jinsong; Qu, Xiaogang

2018-02-09

The logic device demultiplexer can convey a single input signal into one of multiple output channels. The choice of the output channel is controlled by a selector. Several molecules and biomolecules have been used to mimic the function of a demultiplexer. However, the practical application of logic devices still remains a big challenge. Herein, we design and construct an intelligent 1:2 demultiplexer as a theranostic device based on azobenzene (azo)-modified and DNA/Ag cluster-gated nanovehicles. The configuration of azo and the conformation of the DNA ensemble can be regulated by light irradiation and pH, respectively. The demultiplexer which uses light as the input and acid as the selector can emit red fluorescence or a release drug under different conditions. Depending on different cells, the intelligent logic device can select the mode of cellular imaging in healthy cells or tumor therapy in tumor cells. The study incorporates the logic gate with the theranostic device, paving the way for tangible applications of logic gates in the future.

Reversible logic gates based on enzyme-biocatalyzed reactions and realized in flow cells: a modular approach.

PubMed

Fratto, Brian E; Katz, Evgeny

2015-05-18

Reversible logic gates, such as the double Feynman gate, Toffoli gate and Peres gate, with 3-input/3-output channels are realized using reactions biocatalyzed with enzymes and performed in flow systems. The flow devices are constructed using a modular approach, where each flow cell is modified with one enzyme that biocatalyzes one chemical reaction. The multi-step processes mimicking the reversible logic gates are organized by combining the biocatalytic cells in different networks. This work emphasizes logical but not physical reversibility of the constructed systems. Their advantages and disadvantages are discussed and potential use in biosensing systems, rather than in computing devices, is suggested. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Evaluation of Anisotropic Biaxial Stress Induced Around Trench Gate of Si Power Transistor Using Water-Immersion Raman Spectroscopy

NASA Astrophysics Data System (ADS)

Suzuki, Takahiro; Yokogawa, Ryo; Oasa, Kohei; Nishiwaki, Tatsuya; Hamamoto, Takeshi; Ogura, Atsushi

2018-05-01

The trench gate structure is one of the promising techniques to reduce on-state resistance (R on) for silicon power devices, such as insulated gate bipolar transistors and power metal-oxide-semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the R on of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.

The Role of Working Memory Gating in Task Switching: A Procedural Version of the Reference-Back Paradigm

PubMed Central

Kessler, Yoav

2017-01-01

Models of working memory (WM) suggest that the contents of WM are separated from perceptual input by a gate, that enables shielding information against interference when closed, and allows for rapid updating when open. Recent work in the declarative WM domain provided evidence for this notion, demonstrating the behavioral cost of opening and closing the gate. The goal of the present work was to examine gating in procedural WM, namely in a task-switching experiment. In each trial, participants were presented with a digit and a task cue, indicating whether the required task was a parity or a magnitude decision. Critically, a colored frame around the stimulus indicated whether the task cue was relevant (attend trials), or whether it had to be ignored, and the previous task set should be applied regardless of the present cue (ignore trials). Switching between tasks, and between ignore and attend trials, was manipulated. The results of two experiments demonstrated that the cost of gate opening was eliminated in task switching trials, implying that both processes operate in parallel. PMID:29312095

Local gate control in carbon nanotube quantum devices

NASA Astrophysics Data System (ADS)

Biercuk, Michael Jordan

This thesis presents transport measurements of carbon nanotube electronic devices operated in the quantum regime. Nanotubes are contacted by source and drain electrodes, and multiple lithographically-patterned electrostatic gates are aligned to each device. Transport measurements of device conductance or current as a function of local gate voltages reveal that local gates couple primarily to the proximal section of the nanotube, hence providing spatially localized control over carrier density along the nanotube length. Further, using several different techniques we are able to produce local depletion regions along the length of a tube. This phenomenon is explored in detail for different contact metals to the nanotube. We utilize local gating techniques to study multiple quantum dots in carbon nanotubes produced both by naturally occurring defects, and by the controlled application of voltages to depletion gates. We study double quantum dots in detail, where transport measurements reveal honeycomb charge stability diagrams. We extract values of energy-level spacings, capacitances, and interaction energies for this system, and demonstrate independent control over all relevant tunneling rates. We report rf-reflectometry measurements of gate-defined carbon nanotube quantum dots with integrated charge sensors. Aluminum rf-SETs are electrostatically coupled to carbon nanotube devices and detect single electron charging phenomena in the Coulomb blockade regime. Simultaneous correlated measurements of single electron charging are made using reflected rf power from the nanotube itself and from the rf-SET on microsecond time scales. We map charge stability diagrams for the nanotube quantum dot via charge sensing, observing Coulomb charging diamonds beyond the first order. Conductance measurements of carbon nanotubes containing gated local depletion regions exhibit plateaus as a function of gate voltage, spaced by approximately 1e2/h, the quantum of conductance for a single (non-degenerate) mode. Plateau structure is investigated as a function of bias voltage, temperature, and magnetic field. We speculate on the origin of this surprising quantization, which appears to lack band and spin degeneracy.

Using quantum process tomography to characterize decoherence in an analog electronic device

NASA Astrophysics Data System (ADS)

Ostrove, Corey; La Cour, Brian; Lanham, Andrew; Ott, Granville

The mathematical structure of a universal gate-based quantum computer can be emulated faithfully on a classical electronic device using analog signals to represent a multi-qubit state. We describe a prototype device capable of performing a programmable sequence of single-qubit and controlled two-qubit gate operations on a pair of voltage signals representing the real and imaginary parts of a two-qubit quantum state. Analog filters and true-RMS voltage measurements are used to perform unitary and measurement gate operations. We characterize the degradation of the represented quantum state with successive gate operations by formally performing quantum process tomography to estimate the equivalent decoherence channel. Experimental measurements indicate that the performance of the device may be accurately modeled as an equivalent quantum operation closely resembling a depolarizing channel with a fidelity of over 99%. This work was supported by the Office of Naval Research under Grant No. N00014-14-1-0323.

Working memory accuracy for multiple targets is driven by reward expectation and stimulus contrast with different time-courses.

PubMed

Klink, P Christiaan; Jeurissen, Danique; Theeuwes, Jan; Denys, Damiaan; Roelfsema, Pieter R

2017-08-22

The richness of sensory input dictates that the brain must prioritize and select information for further processing and storage in working memory. Stimulus salience and reward expectations influence this prioritization but their relative contributions and underlying mechanisms are poorly understood. Here we investigate how the quality of working memory for multiple stimuli is determined by priority during encoding and later memory phases. Selective attention could, for instance, act as the primary gating mechanism when stimuli are still visible. Alternatively, observers might still be able to shift priorities across memories during maintenance or retrieval. To distinguish between these possibilities, we investigated how and when reward cues determine working memory accuracy and found that they were only effective during memory encoding. Previously learned, but currently non-predictive, color-reward associations had a similar influence, which gradually weakened without reinforcement. Finally, we show that bottom-up salience, manipulated through varying stimulus contrast, influences memory accuracy during encoding with a fundamentally different time-course than top-down reward cues. While reward-based effects required long stimulus presentation, the influence of contrast was strongest with brief presentations. Our results demonstrate how memory resources are distributed over memory targets and implicates selective attention as a main gating mechanism between sensory and memory systems.

2D Quantum Mechanical Study of Nanoscale MOSFETs

NASA Technical Reports Server (NTRS)

Svizhenko, Alexei; Anantram, M. P.; Govindan, T. R.; Biegel, B.; Kwak, Dochan (Technical Monitor)

2000-01-01

With the onset of quantum confinement in the inversion layer in nanoscale MOSFETs, behavior of the resonant level inevitably determines all device characteristics. While most classical device simulators take quantization into account in some simplified manner, the important details of electrostatics are missing. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL, and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density-gradient and quantum-corrected MEDICI). We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions and oxide tunneling are treated on an equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. We present the results of our simulations of MIT 25, 50 and 90 nm "well-tempered" MOSFETs and compare them to those of classical and quantum corrected models. The important feature of quantum model is smaller slope of Id-Vg curve and consequently higher threshold voltage. Surprisingly, the self-consistent potential profile shows lower injection barrier in the channel in quantum case. These results are qualitatively consistent with ID Schroedinger-Poisson calculations. The effect of gate length on gate-oxide leakage and subthreshold current has been studied. The shorter gate length device has an order of magnitude smaller current at zero gate bias than the longer gate length device without a significant trade-off in on-current. This should be a device design consideration.

Flexible, polymer gated, AC-driven organic electroluminescence devices

NASA Astrophysics Data System (ADS)

Xu, Junwei; Carroll, David L.

2017-08-01

Comparing rigid inorganic layer, polymeric semiconducting gate layer exhibits superior flexibility as well as efficient carrier manipulation in high frequency AC cycles. Mechanism of the carrier manipulation at the gate in forward and reversed bias of AC cycle is studied. The flexible PET-based AC-OEL device with poly[(9,9-bis(3'-((N,N-dimethyl)-Nethylammonium)- propyl)-2,7-fluorene)-alt-2,7-(9,9-dioctylfluorene)] (PFN-Br) gate shows a stable electroluminescent performance in frequency sweep with a color rendering index (CRI) over 81 at 2800K color temperature.

Optical XOR gate

DOEpatents

Vawter, G. Allen

2013-11-12

An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

Optical NOR gate

DOEpatents

Skogen, Erik J [Albuquerque, NM; Tauke-Pedretti, Anna [Albuquerque, NM

2011-09-06

An optical NOR gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical NOR gate utilizes two digital optical inputs and a continuous light input to provide a NOR function digital optical output. The optical NOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

Soft error rate simulation and initial design considerations of neutron intercepting silicon chip (NISC)

NASA Astrophysics Data System (ADS)

Celik, Cihangir

Advances in microelectronics result in sub-micrometer electronic technologies as predicted by Moore's Law, 1965, which states the number of transistors in a given space would double every two years. The most available memory architectures today have submicrometer transistor dimensions. The International Technology Roadmap for Semiconductors (ITRS), a continuation of Moore's Law, predicts that Dynamic Random Access Memory (DRAM) will have an average half pitch size of 50 nm and Microprocessor Units (MPU) will have an average gate length of 30 nm over the period of 2008-2012. Decreases in the dimensions satisfy the producer and consumer requirements of low power consumption, more data storage for a given space, faster clock speed, and portability of integrated circuits (IC), particularly memories. On the other hand, these properties also lead to a higher susceptibility of IC designs to temperature, magnetic interference, power supply, and environmental noise, and radiation. Radiation can directly or indirectly affect device operation. When a single energetic particle strikes a sensitive node in the micro-electronic device, it can cause a permanent or transient malfunction in the device. This behavior is called a Single Event Effect (SEE). SEEs are mostly transient errors that generate an electric pulse which alters the state of a logic node in the memory device without having a permanent effect on the functionality of the device. This is called a Single Event Upset (SEU) or Soft Error . Contrary to SEU, Single Event Latchup (SEL), Single Event Gate Rapture (SEGR), or Single Event Burnout (SEB) they have permanent effects on the device operation and a system reset or recovery is needed to return to proper operations. The rate at which a device or system encounters soft errors is defined as Soft Error Rate (SER). The semiconductor industry has been struggling with SEEs and is taking necessary measures in order to continue to improve system designs in nano-scale technologies. Prevention of SEEs has been studied and applied in the semiconductor industry by including radiation protection precautions in the system architecture or by using corrective algorithms in the system operation. Decreasing 10B content (20%of natural boron) in the natural boron of Borophosphosilicate glass (BPSG) layers that are conventionally used in the fabrication of semiconductor devices was one of the major radiation protection approaches for the system architecture. Neutron interaction in the BPSG layer was the origin of the SEEs because of the 10B (n,alpha) 7Li reaction products. Both of the particles produced have the capability of ionization in the silicon substrate region, whose thickness is comparable to the ranges of these particles. Using the soft error phenomenon in exactly the opposite manner of the semiconductor industry can provide a new neutron detection system based on the SERs in the semiconductor memories. By investigating the soft error mechanisms in the available semiconductor memories and enhancing the soft error occurrences in these devices, one can convert all memory using intelligent systems into portable, power efficient, directiondependent neutron detectors. The Neutron Intercepting Silicon Chip (NISC) project aims to achieve this goal by introducing 10B-enriched BPSG layers to the semiconductor memory architectures. This research addresses the development of a simulation tool, the NISC Soft Error Analysis Tool (NISCSAT), for soft error modeling and analysis in the semiconductor memories to provide basic design considerations for the NISC. NISCSAT performs particle transport and calculates the soft error probabilities, or SER, depending on energy depositions of the particles in a given memory node model of the NISC. Soft error measurements were performed with commercially available, off-the-shelf semiconductor memories and microprocessors to observe soft error variations with the neutron flux and memory supply voltage. Measurement results show that soft errors in the memories increase proportionally with the neutron flux, whereas they decrease with increasing the supply voltages. NISC design considerations include the effects of device scaling, 10B content in the BPSG layer, incoming neutron energy, and critical charge of the node for this dissertation. NISCSAT simulations were performed with various memory node models to account these effects. Device scaling simulations showed that any further increase in the thickness of the BPSG layer beyond 2 mum causes self-shielding of the incoming neutrons due to the BPSG layer and results in lower detection efficiencies. Moreover, if the BPSG layer is located more than 4 mum apart from the depletion region in the node, there are no soft errors in the node due to the fact that both of the reaction products have lower ranges in the silicon or any possible node layers. Calculation results regarding the critical charge indicated that the mean charge deposition of the reaction products in the sensitive volume of the node is about 15 fC. It is evident that the NISC design should have a memory architecture with a critical charge of 15 fC or less to obtain higher detection efficiencies. Moreover, the sensitive volume should be placed in close proximity to the BPSG layers so that its location would be within the range of alpha and 7Li particles. Results showed that the distance between the BPSG layer and the sensitive volume should be less than 2 mum to increase the detection efficiency of the NISC. Incoming neutron energy was also investigated by simulations and the results obtained from these simulations showed that NISC neutron detection efficiency is related with the neutron cross-sections of 10B (n,alpha) 7Li reaction, e.g., ratio of the thermal (0.0253 eV) to fast (2 MeV) neutron detection efficiencies is approximately equal to 8000:1. Environmental conditions and their effects on the NISC performance were also studied in this research. Cosmic rays were modeled and simulated via NISCSAT to investigate detection reliability of the NISC. Simulation results show that cosmic rays account for less than 2 % of the soft errors for the thermal neutron detection. On the other hand, fast neutron detection by the NISC, which already has a poor efficiency due to the low neutron cross-sections, becomes almost impossible at higher altitudes where the cosmic ray fluxes and their energies are higher. NISCSAT simulations regarding soft error dependency of the NISC for temperature and electromagnetic fields show that there are no significant effects in the NISC detection efficiency. Furthermore, the detection efficiency of the NISC decreases with both air humidity and use of moderators since the incoming neutrons scatter away before reaching the memory surface.

Retention of data in heat-damaged SIM cards and potential recovery methods.

PubMed

Jones, B J; Kenyon, A J

2008-05-02

Examination of various SIM cards and smart card devices indicates that data may be retained in SIM card memory structures even after heating to temperatures up to 450 degrees C, which the National Institute of Standards and Technology (NIST) has determined to be approximately the maximum average sustained temperature at desk height in a house fire. However, in many cases, and certainly for temperatures greater than 450 degrees C, the SIM card chip has suffered structural or mechanical damage that renders simple probing or rewiring ineffective. Nevertheless, this has not necessarily affected the data, which is stored as charge in floating gates, and alternative methods for directly accessing the stored charge may be applicable.

Radiation tolerant 1 micron CMOS technology

NASA Astrophysics Data System (ADS)

Crevel, P.; Rodde, K.

1991-03-01

Starting from a standard one micron Complementary Metal Oxide Semiconductor (CMOS) for high density, low power memory applications, the degree of radiation tolerance of the baseline process is evaluated. Implemented process modifications to improve latchup sensitivity under heavy ion irradiation as well as total dose effects without changing layout rules are described. By changing doping profiles in Metal Nitride Oxide Semiconductors (MNOS) and P-channel MOS (PMOS) device regions, it is possible to guarantee data sheet specification of a 64 K low power static RAM for total gamma dose up to 35 krad (Si) (and even higher values for the gate array family) without latch up for Linear Energy Transfer LET up to 115 MeV/(mg/cm squared).

The effect of split gate dimensions on the electrostatic potential and 0.7 anomaly within one-dimensional quantum wires on a modulation doped GaAs/AlGaAs heterostructure

NASA Astrophysics Data System (ADS)

Smith, L. W.; Al-Taie, H.; Lesage, A. A. J.; Thomas, K. J.; Sfigakis, F.; See, P.; Griffiths, J. P.; Farrer, I.; Jones, G. A. C.; Ritchie, D. A.; Kelly, M. J.; Smith, C. G.

We use a multiplexing scheme to measure the conductance properties of 95 split gates of 7 different gate dimensions fabricated on a GaAs/AlGaAs chip, in a single cool down. The number of devices for which conductance is accurately quantized reduces as the gate length increases. However, even the devices for which conductance is accurately quantized in units of 2e2 / h show no correlation between the length of electrostatic potential barrier in the channel and the gate length, using a saddle point model to estimate the barrier length. Further, the strength of coupling between the gates and the 1D channel does not increase with gate length beyond 0.7 μm. The background electrostatic profile appears as significant as the gate dimension in determining device behavior. We find a clear correlation between the curvature of the electrostatic barrier along the channel and the strength of the ``0.7 anomaly'' which identifies the electrostatic length of the channel as the principal factor governing the conductance of the 0.7 anomaly. Present address: Wisconsin Institute for Quantum Information, University of Wisconsin-Madison, Madison, WI.

Voltage-Dependent Charge Storage in Cladded Zn0.56Cd0.44Se Quantum Dot MOS Capacitors for Multibit Memory Applications

NASA Astrophysics Data System (ADS)

Khan, J.; Lingalugari, M.; Al-Amoody, F.; Jain, F.

2013-11-01

As conventional memories approach scaling limitations, new storage methods must be utilized to increase Si yield and produce higher on-chip memory density. Use of II-VI Zn0.56Cd0.44Se quantum dots (QDs) is compatible with epitaxial gate insulators such as ZnS-ZnMgS. Voltage-dependent charging effects in cladded Zn0.56Cd0.44Se QDs are presented in a conventional metal-oxide-semiconductor capacitor structure. Charge storage capabilities in Si and ZnMgS QDs have been reported by various researchers; this work is focused on II-VI material Zn0.56Cd0.44Se QDs nucleated using photoassisted microwave plasma metalorganic chemical vapor deposition. Using capacitance-voltage hysteresis characterization, the multistep charging and discharging capabilities of the QDs at room temperature are presented. Three charging states are presented within a 10 V charging voltage range. These characteristics exemplify discrete charge states in the QD layer, perfect for multibit, QD-functionalized high-density memory applications. Multiple charge states with low operating voltage provide device characteristics that can be used for multibit storage by allowing varying charges to be stored in a QD layer based on the applied "write" voltage.

Efficient III-Nitride MIS-HEMT devices with high-κ gate dielectric for high-power switching boost converter circuits

NASA Astrophysics Data System (ADS)

Mohanbabu, A.; Mohankumar, N.; Godwin Raj, D.; Sarkar, Partha; Saha, Samar K.

2017-03-01

The paper reports the results of a systematic theoretical study on efficient recessed-gate, double-heterostructure, and normally-OFF metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs), HfAlOx/AlGaN on Al2O3 substrate. In device architecture, a thin AlGaN layer is used in the AlGaN graded barrier MIS-HEMTs that offers an excellent enhancement-mode device operation with threshold voltage higher than 5.3 V and drain current above 0.64 A/mm along with high on-current/off-current ratio over 107 and subthreshold slope less than 73 mV/dec. In addition, a high OFF-state breakdown voltage of 1200 V is achieved for a device with a gate-to-drain distance and field-plate length of 15 μm and 5.3 μm, respectively at a drain current of 1 mA/mm with a zero gate bias, and the substrate grounded. The numerical device simulation results show that in comparison to a conventional AlGaN/GaN MIS-HEMT of similar design, a graded barrier MIS-HEMT device exhibits a better interface property, remarkable suppression of leakage current, and a significant improvement of breakdown voltage for HfAlOx gate dielectric. Finally, the benefit of HfAlOx graded-barrier AlGaN MIS-HEMTs based switching devices is evaluated on an ultra-low-loss converter circuit.

Reversible photo-chem-electrotriggered three-state luminescence switching based on core-shell nanostructures

NASA Astrophysics Data System (ADS)

Zhai, Yanling; Zhu, Zhijun; Zhu, Chengzhou; Zhu, Jinbo; Ren, Jiangtao; Wang, Erkang; Dong, Shaojun

2013-05-01

Reversible three-state fluorescence switches triggered by light, electricity and chemical inputs based on ``sponges'' of Pyronin Y-doped silica nanoparticles (PYDS) and polyoxometalate K14[Na(H2O)P5W30O110] (Na-POMs) core-shell nanostructures were realized. Under one or two signal inputs, the system exhibited distinct three-state interconvertible automaton, achieving reversible ``on'' and ``off'' luminescence switches via the related luminescence quenching effect. The features of the system correspond to the equivalent circuitry of an IMPLICATION logic gate performing the Boolean operation by using potential and chemical as inputs. Such a multi-chromic device with novel structure possesses several advantages, such as relative low operation voltage, large reproducibility and reversibility, apparent fluorescence contrast, and long-time stability, which make it a suitable candidate for nonvolatile memory devices. In addition, the current protocol for the hybrid film fabrication can be easily extended from the polyoxometalate and organic dyes to other novel nanostructures matched multifunctional stimulus-responsive species and fluorescence materials in the future.Reversible three-state fluorescence switches triggered by light, electricity and chemical inputs based on ``sponges'' of Pyronin Y-doped silica nanoparticles (PYDS) and polyoxometalate K14[Na(H2O)P5W30O110] (Na-POMs) core-shell nanostructures were realized. Under one or two signal inputs, the system exhibited distinct three-state interconvertible automaton, achieving reversible ``on'' and ``off'' luminescence switches via the related luminescence quenching effect. The features of the system correspond to the equivalent circuitry of an IMPLICATION logic gate performing the Boolean operation by using potential and chemical as inputs. Such a multi-chromic device with novel structure possesses several advantages, such as relative low operation voltage, large reproducibility and reversibility, apparent fluorescence contrast, and long-time stability, which make it a suitable candidate for nonvolatile memory devices. In addition, the current protocol for the hybrid film fabrication can be easily extended from the polyoxometalate and organic dyes to other novel nanostructures matched multifunctional stimulus-responsive species and fluorescence materials in the future. Electronic supplementary information (ESI) available: Experimental details and instrumentation; electrochemical, fluorescence and absorption spectra characterizations of hybrid films. See DOI: 10.1039/c3nr00254c

Direct observation of trapped charges under field-plate in p-GaN gate AlGaN/GaN high electron mobility transistors by electric field-induced optical second-harmonic generation

NASA Astrophysics Data System (ADS)

Katsuno, Takashi; Manaka, Takaaki; Soejima, Narumasa; Iwamoto, Mitsumasa

2017-02-01

Trapped charges underneath the field-plate (FP) in a p-gallium nitride (GaN) gate AlGaN/ GaN high electron mobility transistor device were visualized by using electric field-induced optical second-harmonic generation imaging. Second-harmonic (SH) signals in the off-state of the device with FP indicated that the electric field decreased at the p-GaN gate edge and concentrated at the FP edge. Nevertheless, SH signals originating from trapped charges were slightly observed at the p-GaN gate edge and were not observed at the FP edge in the on-state. Compared with the device without FP, reduction of trapped charges at the p-GaN gate edge of the device with FP is attributed to attenuation of the electric field with the aid of the FP. Negligible trapped charges at the FP edge is owing to lower trap density of the SiO2/AlGaN interface at the FP edge compared with that of the SiO2/p-GaN sidewall interface at the p-GaN gate edge and attenuated electric field by the thickness of the SiO2 passivation layer on the AlGaN surface.

Cyclic Nucleotide-Gated Channels, Calmodulin, Adenylyl Cyclase, and Calcium/Calmodulin-Dependent Protein Kinase II Are Required for Late, but Not Early, Long-Term Memory Formation in the Honeybee

ERIC Educational Resources Information Center

Matsumoto, Yukihisa; Sandoz, Jean-Christophe; Devaud, Jean-Marc; Lormant, Flore; Mizunami, Makoto; Giurfa, Martin

2014-01-01

Memory is a dynamic process that allows encoding, storage, and retrieval of information acquired through individual experience. In the honeybee "Apis mellifera," olfactory conditioning of the proboscis extension response (PER) has shown that besides short-term memory (STM) and mid-term memory (MTM), two phases of long-term memory (LTM)…

Effect of gate skirts on pedestrian behavior at highway-rail grade crossings

DOT National Transportation Integrated Search

2013-12-31

The Federal Railroad Administration was interested in evaluating one type of pedestrian safety device, commonly known as gate skirts, that consists of a secondary horizontal hanging gate under the existing pedestrian gate to better block access to th...

Bio-fabrication of nanomesh channels of single-walled carbon nanotubes for locally gated field-effect transistors

NASA Astrophysics Data System (ADS)

Byeon, Hye-Hyeon; Lee, Woo Chul; Kim, Wonbin; Kim, Seong Keun; Kim, Woong; Yi, Hyunjung

2017-01-01

Single-walled carbon nanotubes (SWNTs) are one of the promising electronic components for nanoscale electronic devices such as field-effect transistors (FETs) owing to their excellent device characteristics such as high conductivity, high carrier mobility and mechanical flexibility. Localized gating gemometry of FETs enables individual addressing of active channels and allows for better electrostatics via thinner dielectric layer of high k-value. For localized gating of SWNTs, it becomes critical to define SWNTs of controlled nanostructures and functionality onto desired locations in high precision. Here, we demonstrate that a biologically templated approach in combination of microfabrication processes can successfully produce a nanostructured channels of SWNTs for localized active devices such as local bottom-gated FETs. A large-scale nanostructured network, nanomesh, of SWNTs were assembled in solution using an M13 phage with strong binding affinity toward SWNTs and micrometer-scale nanomesh channels were defined using negative photolithography and plasma-etching processes. The bio-fabrication approach produced local bottom-gated FETs with remarkably controllable nanostructures and successfully enabled semiconducting behavior out of unsorted SWNTs. In addition, the localized gating scheme enhanced the device performances such as operation voltage and I on/I off ratio. We believe that our approach provides a useful and integrative method for fabricating electronic devices out of nanoscale electronic materials for applications in which tunable electrical properties, mechanical flexibility, ambient stability, and chemical stability are of crucial importance.

3D modeling of dual-gate FinFET.

PubMed

Mil'shtein, Samson; Devarakonda, Lalitha; Zanchi, Brian; Palma, John

2012-11-13

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at Vg1 >Vg2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.

3D modeling of dual-gate FinFET

NASA Astrophysics Data System (ADS)

Mil'shtein, Samson; Devarakonda, Lalitha; Zanchi, Brian; Palma, John

2012-11-01

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at V g1 > V g2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.

Extended-gate organic field-effect transistor for the detection of histamine in water

NASA Astrophysics Data System (ADS)

Minamiki, Tsukuru; Minami, Tsuyoshi; Yokoyama, Daisuke; Fukuda, Kenjiro; Kumaki, Daisuke; Tokito, Shizuo

2015-04-01

As part of our ongoing research program to develop health care sensors based on organic field-effect transistor (OFET) devices, we have attempted to detect histamine using an extended-gate OFET. Histamine is found in spoiled or decayed fish, and causes foodborne illness known as scombroid food poisoning. The new OFET device possesses an extended gate functionalized by carboxyalkanethiol that can interact with histamine. As a result, we have succeeded in detecting histamine in water through a shift in OFET threshold voltage. This result indicates the potential utility of the designed OFET devices in food freshness sensing.

A simple device for respiratory gating for the MRI of laboratory animals.

PubMed

Burdett, N G; Carpenter, T A; Hall, L D

1993-01-01

Respiratory motion must be overcome if MRI of the abdomen, even at the lowest resolution, is to be performed satisfactorily. A simple and reliable respiratory gating device, based on the interruption of an infrared (IR) optical beam is described. This device has the advantage that gating is based on the position of the chest as opposed to its velocity, and that it can be used without degrading the radiofrequency isolation of a Faraday cage. Its use in animal MRI is illustrated by high resolution (200 microns) images of in vivo rat liver and kidney.

Self-Aligned van der Waals Heterojunction Diodes and Transistors.

PubMed

Sangwan, Vinod K; Beck, Megan E; Henning, Alex; Luo, Jiajia; Bergeron, Hadallia; Kang, Junmo; Balla, Itamar; Inbar, Hadass; Lauhon, Lincoln J; Hersam, Mark C

2018-02-14

A general self-aligned fabrication scheme is reported here for a diverse class of electronic devices based on van der Waals materials and heterojunctions. In particular, self-alignment enables the fabrication of source-gated transistors in monolayer MoS 2 with near-ideal current saturation characteristics and channel lengths down to 135 nm. Furthermore, self-alignment of van der Waals p-n heterojunction diodes achieves complete electrostatic control of both the p-type and n-type constituent semiconductors in a dual-gated geometry, resulting in gate-tunable mean and variance of antiambipolar Gaussian characteristics. Through finite-element device simulations, the operating principles of source-gated transistors and dual-gated antiambipolar devices are elucidated, thus providing design rules for additional devices that employ self-aligned geometries. For example, the versatility of this scheme is demonstrated via contact-doped MoS 2 homojunction diodes and mixed-dimensional heterojunctions based on organic semiconductors. The scalability of this approach is also shown by fabricating self-aligned short-channel transistors with subdiffraction channel lengths in the range of 150-800 nm using photolithography on large-area MoS 2 films grown by chemical vapor deposition. Overall, this self-aligned fabrication method represents an important step toward the scalable integration of van der Waals heterojunction devices into more sophisticated circuits and systems.

Design consideration of δ-doping channels for high-performance n + - GaAs / p + -InGaP/n-GaAs camel-gate field effect transistors

NASA Astrophysics Data System (ADS)

Tsai, Jung-Hui; Chen, Jeng-Shyan; Chu, Yu-Jui

2005-01-01

The influence of δ-doping channels on the performance of n +-GaAs/p +-InGaP/n-GaAs camel-gate field effect transistors is investigated by theoretical analysis and experimental results. The depleted pn junction of the camel gate and the existence of considerable conduction band discontinuity at the InGaP/GaAs heterojunction enhance the potential barrier height and the forward gate voltage. As the concentration-thickness products of the n-GaAs layer and δ-doping layer are fixed, the higher δ-doping device exhibits a higher potential barrier height, a larger drain current, and a broader gate voltage swing, whereas the transconductance is somewhat lower. For a n +=5.5×10 12 cm -2δ-doping device, the experimental result exhibits a maximum transconductance of 240 mS/mm and a gate voltage swing of 3.5 V. Consequently, the studied devices provide a good potential for large signal and linear circuit applications.

Flexible integrated circuits and multifunctional electronics based on single atomic layers of MoS2 and graphene

NASA Astrophysics Data System (ADS)

Amani, Matin; Burke, Robert A.; Proie, Robert M.; Dubey, Madan

2015-03-01

Two-dimensional materials, such as graphene and its analogues, have been investigated by numerous researchers for high performance flexible and conformal electronic systems, because they offer the ultimate level of thickness scaling, atomically smooth surfaces and high crystalline quality. Here, we use layer-by-layer transfer of large area molybdenum disulphide (MoS2) and graphene grown by chemical vapor deposition (CVD) to demonstrate electronics on flexible polyimide (PI) substrates. On the same PI substrate, we are able to simultaneously fabricate MoS2 based logic, non-volatile memory cells with graphene floating gates, photo-detectors and MoS2 transistors with tunable source and drain contacts. We are also able to demonstrate that these flexible heterostructure devices have very high electronic performance, comparable to four point measurements taken on SiO2 substrates, with on/off ratios >107 and field effect mobilities as high as 16.4 cm2 V-1 s-1. Additionally, the heterojunctions show high optoelectronic sensitivity and were operated as photodetectors with responsivities over 30 A W-1. Through local gating of the individual graphene/MoS2 contacts, we are able to tune the contact resistance over the range of 322-1210 Ω mm for each contact, by modulating the graphene work function. This leads to devices with tunable and multifunctional performance that can be implemented in a conformable platform.

Flexible integrated circuits and multifunctional electronics based on single atomic layers of MoS2 and graphene.

PubMed

Amani, Matin; Burke, Robert A; Proie, Robert M; Dubey, Madan

2015-03-20

Two-dimensional materials, such as graphene and its analogues, have been investigated by numerous researchers for high performance flexible and conformal electronic systems, because they offer the ultimate level of thickness scaling, atomically smooth surfaces and high crystalline quality. Here, we use layer-by-layer transfer of large area molybdenum disulphide (MoS2) and graphene grown by chemical vapor deposition (CVD) to demonstrate electronics on flexible polyimide (PI) substrates. On the same PI substrate, we are able to simultaneously fabricate MoS2 based logic, non-volatile memory cells with graphene floating gates, photo-detectors and MoS2 transistors with tunable source and drain contacts. We are also able to demonstrate that these flexible heterostructure devices have very high electronic performance, comparable to four point measurements taken on SiO2 substrates, with on/off ratios >10(7) and field effect mobilities as high as 16.4 cm(2) V(-1) s(-1). Additionally, the heterojunctions show high optoelectronic sensitivity and were operated as photodetectors with responsivities over 30 A W(-1). Through local gating of the individual graphene/MoS2 contacts, we are able to tune the contact resistance over the range of 322-1210 Ω mm for each contact, by modulating the graphene work function. This leads to devices with tunable and multifunctional performance that can be implemented in a conformable platform.

Use of a hard mask for formation of gate and dielectric via nanofilament field emission devices

DOEpatents

Morse, Jeffrey D.; Contolini, Robert J.

2001-01-01

A process for fabricating a nanofilament field emission device in which a via in a dielectric layer is self-aligned to gate metal via structure located on top of the dielectric layer. By the use of a hard mask layer located on top of the gate metal layer, inert to the etch chemistry for the gate metal layer, and in which a via is formed by the pattern from etched nuclear tracks in a trackable material, a via is formed by the hard mask will eliminate any erosion of the gate metal layer during the dielectric via etch. Also, the hard mask layer will protect the gate metal layer while the gate structure is etched back from the edge of the dielectric via, if such is desired. This method provides more tolerance for the electroplating of a nanofilament in the dielectric via and sharpening of the nanofilament.

High-frequency electromechanical resonators based on thin GaTe

NASA Astrophysics Data System (ADS)

Chitara, Basant; Ya'akobovitz, Assaf

2017-10-01

Gallium telluride (GaTe) is a layered material, which exhibits a direct bandgap (˜1.65 eV) regardless of its thickness and therefore holds great potential for integration as a core element in stretchable optomechanical and optoelectronic devices. Here, we characterize and demonstrate the elastic properties and electromechanical resonators of suspended thin GaTe nanodrums. We used atomic force microscopy to extract the Young’s modulus of GaTe (average value ˜39 GPa) and to predict the resonance frequencies of suspended GaTe nanodrums of various geometries. Electromechanical resonators fabricated from suspended GaTe revealed fundamental resonance frequencies in the range of 10-25 MHz, which closely match predicted values. Therefore, this study paves the way for creating a new generation of GaTe based nanoelectromechanical devices with a direct bandgap vibrating element, which can serve as optomechanical sensors and actuators.

System and Method for Scan Range Gating

NASA Technical Reports Server (NTRS)

Lindemann, Scott (Inventor); Zuk, David M. (Inventor)

2017-01-01

A system for scanning light to define a range gated signal includes a pulsed coherent light source that directs light into the atmosphere, a light gathering instrument that receives the light modified by atmospheric backscatter and transfers the light onto an image plane, a scanner that scans collimated light from the image plane to form a range gated signal from the light modified by atmospheric backscatter, a control circuit that coordinates timing of a scan rate of the scanner and a pulse rate of the pulsed coherent light source so that the range gated signal is formed according to a desired range gate, an optical device onto which an image of the range gated signal is scanned, and an interferometer to which the image of the range gated signal is directed by the optical device. The interferometer is configured to modify the image according to a desired analysis.

A manufacturable process integration approach for graphene devices

NASA Astrophysics Data System (ADS)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Technical Note: Evaluation of the latency and the beam characteristics of a respiratory gating system using an Elekta linear accelerator and a respiratory indicator device, Abches.

PubMed

Saito, Masahide; Sano, Naoki; Ueda, Koji; Shibata, Yuki; Kuriyama, Kengo; Komiyama, Takafumi; Marino, Kan; Aoki, Shinichi; Onishi, Hiroshi

2018-01-01

To evaluate the basic performance of a respiratory gating system using an Elekta linac and an Abches respiratory-monitoring device. The gating system was comprised of an Elekta Synergy linac equipped with a Response TM gating interface module and an Abches respiratory-monitoring device. The latencies from a reference respiratory signal to the resulting Abches gating output signal and the resulting monitor-ion-chamber output signal were measured. Then, the flatness and symmetry of the gated beams were measured using a two-dimensional ionization chamber array for fixed and arc beams, respectively. Furthermore, the beam quality, TPR 20,10 , and the output of the fixed gated beams were also measured using a Farmer chamber. Each of the beam characteristics was compared with each of those for nongated irradiation. The full latencies at beam-on and beam-off for 6-MV gated beams were 336.4 ± 23.4 ms and 87.6 ± 7.1 ms, respectively. The differences in flatness between the gated and nongated beams were within 0.91% and 0.87% for the gun-target and left-right directions, respectively. In the same manner, the beam symmetries were within 0.68% and 0.82%, respectively. The percentage differences in beam quality and beam output were below 1% for a beam-on time range of 1.1-7 s. The latency of the Elekta gating system combined with Abches was found to be acceptable using our measurement method. Furthermore, we demonstrated that the beam characteristics of the gating system using our respiratory indicator were comparable with the nongated beams for a single-arc gated beam delivery. © 2017 American Association of Physicists in Medicine.

Gate line edge roughness amplitude and frequency variation effects on intra die MOS device characteristics

NASA Astrophysics Data System (ADS)

Hamadeh, Emad; Gunther, Norman G.; Niemann, Darrell; Rahman, Mahmud

2006-06-01

Random fluctuations in fabrication process outcomes such as gate line edge roughness (LER) give rise to corresponding fluctuations in scaled down MOS device characteristics. A thermodynamic-variational model is presented to study the effects of LER on threshold voltage and capacitance of sub-50 nm MOS devices. Conceptually, we treat the geometric definition of the MOS devices on a die as consisting of a collection of gates. In turn, each of these gates has an area, A, and a perimeter, P, defined by nominally straight lines subject to random process outcomes producing roughness. We treat roughness as being deviations from straightness consisting of both transverse amplitude and longitudinal wavelength each having lognormal distribution. We obtain closed-form expressions for variance of threshold voltage ( Vth), and device capacitance ( C) at Onset of Strong Inversion (OSI) for a small device. Using our variational model, we characterized the device electrical properties such as σ and σC in terms of the statistical parameters of the roughness amplitude and spatial frequency, i.e., inverse roughness wavelength. We then verified our model with numerical analysis of Vth roll-off for small devices and σ due to dopant fluctuation. Our model was also benchmarked against TCAD of σ as a function of LER. We then extended our analysis to predict variations in σ and σC versus average LER spatial frequency and amplitude, and oxide-thickness. Given the intuitive expectation that LER of very short wavelengths must also have small amplitude, we have investigated the case in which the amplitude mean is inversely related to the frequency mean. We compare with the situation in which amplitude and frequency mean are unrelated. Given also that the gate perimeter may consist of different LER signature for each side, we have extended our analysis to the case when the LER statistical difference between gate sides is moderate, as well as when it is significantly large.

One-dimensional array of gold nanoparticles fabricated using biotemplate and its application to fine FET

NASA Astrophysics Data System (ADS)

Ban, Takahiko; Uenuma, Mutsunori; Migita, Shinji; Okamoto, Naofumi; Ishikawa, Yasuaki; Uraoka, Yukiharu; Yamashita, Ichiro; Yamamoto, Shin-ichi

2018-06-01

By synthesizing AuS nanoparticles (NPs) with spherical shell protein (ferritin) and using a V-groove, a one-dimensional array of NPs was formed at the bottom of the V-groove. It has been reported that AuS NPs are converted to Au NPs by UV/ozone treatment. Floating gate memory (FGM) was fabricated by applying this one-dimensional array to V-grooved junctionless (JL) FETs, V-grooved nin-like-type FETs, and pip-like-type FETs, which are fine FETs. In JL-FETs, it is considered that conversion occurred because of good charge storage efficiency, and operation in the opposite direction to normal FGM operation was seen. In the nin-like and pip-like types devices, the same operation as in conventional FGM was shown, and the width of the memory window was about the same size as when one electron entered one NP. The one-dimensional arrangement of the metal NPs used in this study is considered to be applicable to various fields of nanotechnology.

Protein-Based Three-Dimensional Memories and Associative Processors

NASA Astrophysics Data System (ADS)

Birge, Robert

2008-03-01

The field of bioelectronics has benefited from the fact that nature has often solved problems of a similar nature to those which must be solved to create molecular electronic or photonic devices that operate with efficiency and reliability. Retinal proteins show great promise in bioelectronic devices because they operate with high efficiency (˜0.65%), high cyclicity (>10^7), operate over an extended wavelength range (360 -- 630 nm) and can convert light into changes in voltage, pH, absorption or refractive index. This talk will focus on a retinal protein called bacteriorhodopsin, the proton pump of the organism Halobacterium salinarum. Two memories based on this protein will be described. The first is an optical three-dimensional memory. This memory stores information using volume elements (voxels), and provides as much as a thousand-fold improvement in effective capacity over current technology. A unique branching reaction of a variant of bacteriorhodopsin is used to turn each protein into an optically addressed latched AND gate. Although three working prototypes have been developed, a number of cost/performance and architectural issues must be resolved prior to commercialization. The major issue is that the native protein provides a very inefficient branching reaction. Genetic engineering has improved performance by nearly 500-fold, but a further order of magnitude improvement is needed. Protein-based holographic associative memories will also be discussed. The human brain stores and retrieves information via association, and human intelligence is intimately connected to the nature and enormous capacity of this associative search and retrieval process. To a first order approximation, creativity can be viewed as the association of two seemingly disparate concepts to form a totally new construct. Thus, artificial intelligence requires large scale associative memories. Current computer hardware does not provide an optimal environment for creating artificial intelligence due to the serial nature of random access memories. Software cannot provide a satisfactory work-around that does not introduce unacceptable latency. Holographic associative memories provide a useful approach to large scale associative recall. Bacteriorhodopsin has long been recognized for its outstanding holographic properties, and when utilized in the Paek and Psaltis design, provides a high-speed real-time associative memory with variable thresholding and feedback. What remains is to make an associative memory capable of high-speed association and long-term data storage. The use of directed evolution to create a protein with the necessary unique properties will be discussed.

Novel organic semiconductors and a high capacitance gate dielectric for organic thin film transistors

NASA Astrophysics Data System (ADS)

Cai, Xiuyu

2007-12-01

Organic semiconductors are attracting more and more interest as a promising set of materials in the field of electronics research. This thesis focused on several new organic semiconductors and a novel high-kappa dielectric thin film (SrTiO3), which are two essential parts in Organic Thin Film Transistors (OTFTs). Structure and morphology of thin films of tricyanovinyl capped oligothiophenes were studied using atomic force microscopy and x-ray diffraction. Thin film transistors of one compound exhibited a reasonable electron mobility of 0.02 cm2/Vs. Temperature dependent measurements on the thin film transistor based on this compound revealed shallow trap states that were interpreted in terms of a multiple trap and release model. Moreover, inversion of the majority charge carrier type from electrons to holes was observed when the number of oligothiophene rings increased to six and ambipolar transport behavior was observed for tricyanovinyl sexithiophene. Another interesting organic semiconductor compound is the fluoalkylquarterthiophene, which showed ambipolar transport and large hysteresis in the transfer curve. Due to the bistable state at floating gate, the thin film transistor was exploited to study non-volatile floating gate memory effects. The temperature dependence of the retention time for this memory device revealed that the electron trapping was an activated process. Following the earlier work on hybrid acene-thiophene organic semiconductors, new compounds with similar structure were studied to reveal the mechanism of the air-stability exhibited by some compounds. They all formed highly crystalline thin films and showed reasonable device performances which are well correlated with the molecular structures, thin film microstructures, and solid state packing. The most air-stable compound had no observable degradation with exposure to air for 15 months. SrTiO3 was developed to be employed in OTFTs. Optimization of thin film growth was performed using reactive sputtering growth. Excellent SrTiO3 epitaixal thin film growth was revealed on conductive SrTiO 3:Nb substrates. A maximum charge carrier density of 1014 cm-2 was obtained based on pentacene and perylene diimide thin film transistors. Some new physical phenomena, such as step-like transfer characteristic curve and negative transconductance, were observed at such high field effect induced charge carrier density.

III-V HEMTs: low-noise devices for high-frequency applications

NASA Astrophysics Data System (ADS)

Mateos, Javier

2003-05-01

With the recent development of broadband and satellite communications, one of the main engines for the advance of modern Microelectronics is the fabrication of devices with increasing cutoff frequency and lowest possible level of noise. Even if heterojunction bipolar devices (HBTs) have reached a good frequency performance, the top end of high frequency low-noise applications is monopolized by unipolar devices, mainly HEMTs (High Electron Mobility Transistors). In particular, within the vast family of heterojunction devices, the best results ever reported in the W-band have been obtained with InP based HEMTs using the AlInAs/InGaAs material system, improving those of usual GaAs based pseudomorphic HEMTs. In field effect devices, the reduction of the gate length (Lg) up to the technological limit is the main way to achieve the maximum performances. But the design of the devices is not so simple, when reducing the gate length it is convenient to keep constant the aspect ratio (gate length over gate-to-channel distance) in order to limit short channel effects. This operation can lead to the appearance of other unwanted effects, like the depletion of the channel due to the surface potential or the tunneling of electrons from the channel to the gate. Therefore, in order to optimize the high frequency or the low-noise behavior of the devices (that usually can not be reached together) not only the gate-to-channel distance must be chosen carefully, but also many other technological parameters (both geometrical and electrical): composition of materials, width of the device, length, depth and position of the recess, thickness and doping of the different layers, etc. Historically, these parameters have been optimized by classical simulation techniques or, when such simulations are not physically applicable, by the expensive 'test and error' procedure. With the use of computer simulation, the design optimization can be made in a short time and with no money spent. However, classical modelling of electronic devices meets important difficulties when dealing with advanced transistors, mainly due to their small size, and the Monte Carlo technique appears as the only possible choice

Resonant tunneling device with two-dimensional quantum well emitter and base layers

DOEpatents

Simmons, J.A.; Sherwin, M.E.; Drummond, T.J.; Weckwerth, M.V.

1998-10-20

A double electron layer tunneling device is presented. Electrons tunnel from a two dimensional emitter layer to a two dimensional tunneling layer and continue traveling to a collector at a lower voltage. The emitter layer is interrupted by an isolation etch, a depletion gate, or an ion implant to prevent electrons from traveling from the source along the emitter to the drain. The collector is similarly interrupted by a backgate, an isolation etch, or an ion implant. When the device is used as a transistor, a control gate is added to control the allowed energy states of the emitter layer. The tunnel gate may be recessed to change the operating range of the device and allow for integrated complementary devices. Methods of forming the device are also set forth, utilizing epoxy-bond and stop etch (EBASE), pre-growth implantation of the backgate or post-growth implantation. 43 figs.

Resonant tunneling device with two-dimensional quantum well emitter and base layers

DOEpatents

Simmons, Jerry A.; Sherwin, Marc E.; Drummond, Timothy J.; Weckwerth, Mark V.

1998-01-01

A double electron layer tunneling device is presented. Electrons tunnel from a two dimensional emitter layer to a two dimensional tunneling layer and continue traveling to a collector at a lower voltage. The emitter layer is interrupted by an isolation etch, a depletion gate, or an ion implant to prevent electrons from traveling from the source along the emitter to the drain. The collector is similarly interrupted by a backgate, an isolation etch, or an ion implant. When the device is used as a transistor, a control gate is added to control the allowed energy states of the emitter layer. The tunnel gate may be recessed to change the operating range of the device and allow for integrated complementary devices. Methods of forming the device are also set forth, utilizing epoxy-bond and stop etch (EBASE), pre-growth implantation of the backgate or post-growth implantation.

Ferroelectric transistors with monolayer molybdenum disulfide and ultra-thin aluminum-doped hafnium oxide

NASA Astrophysics Data System (ADS)

Yap, Wui Chung; Jiang, Hao; Liu, Jialun; Xia, Qiangfei; Zhu, Wenjuan

2017-07-01

In this letter, we demonstrate ferroelectric memory devices with monolayer molybdenum disulfide (MoS2) as the channel material and aluminum (Al)-doped hafnium oxide (HfO2) as the ferroelectric gate dielectric. Metal-ferroelectric-metal capacitors with 16 nm thick Al-doped HfO2 are fabricated, and a remnant polarization of 3 μC/cm2 under a program/erase voltage of 5 V is observed. The capability of potential 10 years data retention was estimated using extrapolation of the experimental data. Ferroelectric transistors based on embedded ferroelectric HfO2 and MoS2 grown by chemical vapor deposition are fabricated. Clockwise hysteresis is observed at low program/erase voltages due to slow bulk traps located near the 2D/dielectric interface, while counterclockwise hysteresis is observed at high program/erase voltages due to ferroelectric polarization. In addition, the endurances of the devices are tested, and the effects associated with ferroelectric materials, such as the wake-up effect and polarization fatigue, are observed. Reliable writing/reading in MoS2/Al-doped HfO2 ferroelectric transistors over 2 × 104 cycles is achieved. This research can potentially lead to advances of two-dimensional (2D) materials in low-power logic and memory applications.

Spintronics with multiferroics

NASA Astrophysics Data System (ADS)

Béa, H.; Gajek, M.; Bibes, M.; Barthélémy, A.

2008-10-01

In this paper, we review the recent research on the functionalization of multiferroics for spintronics applications. We focus more particularly on antiferromagnetic and ferroelectric BiFeO3 and its integration in several types of architectures. For instance, when used as a tunnel barrier, BiFeO3 allows the observation of a large tunnel magnetoresistance with Co and (La,Sr)MnO3 ferromagnetic electrodes. Also, its antiferromagnetic and magnetoelectric properties have been exploited to induce an exchange coupling with a ferromagnet. The mechanisms of such an exchange coupling open ways to electrically control magnetization and possibly the logic state of spintronics devices. We also discuss recent results concerning the use of ferromagnetic and ferroelectric (La,Bi)MnO3 as an active tunnel barrier in magnetic tunnel junctions with Au and (La,Sr)MnO3 electrodes. A four-resistance-state device has been obtained, with two states arising from a spin filtering effect due to the ferromagnetic character of the barrier and two resulting from the ferroelectric behavior of the (La,Bi)MnO3 ultrathin film. These results show that the additional degree of freedom provided by the ferroelectric polarization brings novel functionalities to spintronics, either as a extra order parameter for multiple-state memory elements, or as a handle for gate-controlled magnetic memories.

Experimental verification of electrostatic boundary conditions in gate-patterned quantum devices

NASA Astrophysics Data System (ADS)

Hou, H.; Chung, Y.; Rughoobur, G.; Hsiao, T. K.; Nasir, A.; Flewitt, A. J.; Griffiths, J. P.; Farrer, I.; Ritchie, D. A.; Ford, C. J. B.

2018-06-01

In a model of a gate-patterned quantum device, it is important to choose the correct electrostatic boundary conditions (BCs) in order to match experiment. In this study, we model gated-patterned devices in doped and undoped GaAs heterostructures for a variety of BCs. The best match is obtained for an unconstrained surface between the gates, with a dielectric region above it and a frozen layer of surface charge, together with a very deep back boundary. Experimentally, we find a  ∼0.2 V offset in pinch-off characteristics of 1D channels in a doped heterostructure before and after etching off a ZnO overlayer, as predicted by the model. Also, we observe a clear quantised current driven by a surface acoustic wave through a lateral induced n-i-n junction in an undoped heterostructure. In the model, the ability to pump electrons in this type of device is highly sensitive to the back BC. Using the improved boundary conditions, it is straightforward to model quantum devices quite accurately using standard software.

Electrical and ferroelectric properties of RF sputtered PZT/SBN on silicon for non-volatile memory applications

NASA Astrophysics Data System (ADS)

Singh, Prashant; Jha, Rajesh Kumar; Singh, Rajat Kumar; Singh, B. R.

2018-02-01

We report the integration of multilayer ferroelectric film deposited by RF magnetron sputtering and explore the electrical characteristics for its application as the gate of ferroelectric field effect transistor for non-volatile memories. PZT (Pb[Zr0.35Ti0.65]O3) and SBN (SrBi2Nb2O9) ferroelectric materials were selected for the stack fabrication due to their large polarization and fatigue free properties respectively. Electrical characterization has been carried out to obtain memory window, leakage current density, PUND and endurance characteristics. Fabricated multilayer ferroelectric film capacitor structure shows large memory window of 17.73 V and leakage current density of the order 10-6 A cm-2 for the voltage sweep of -30 to +30 V. This multilayer gate stack of PZT/SBN shows promising endurance property with no degradation in the remnant polarization for the read/write iteration cycles upto 108.

Control of Turing patterns and their usage as sensors, memory arrays, and logic gates

NASA Astrophysics Data System (ADS)

Muzika, František; Schreiber, Igor

2013-10-01

We study a model system of three diffusively coupled reaction cells arranged in a linear array that display Turing patterns with special focus on the case of equal coupling strength for all components. As a suitable model reaction we consider a two-variable core model of glycolysis. Using numerical continuation and bifurcation techniques we analyze the dependence of the system's steady states on varying rate coefficient of the recycling step while the coupling coefficients of the inhibitor and activator are fixed and set at the ratios 100:1, 1:1, and 4:5. We show that stable Turing patterns occur at all three ratios but, as expected, spontaneous transition from the spatially uniform steady state to the spatially nonuniform Turing patterns occurs only in the first case. The other two cases possess multiple Turing patterns, which are stabilized by secondary bifurcations and coexist with stable uniform periodic oscillations. For the 1:1 ratio we examine modular spatiotemporal perturbations, which allow for controllable switching between the uniform oscillations and various Turing patterns. Such modular perturbations are then used to construct chemical computing devices utilizing the multiple Turing patterns. By classifying various responses we propose: (a) a single-input resettable sensor capable of reading certain value of concentration, (b) two-input and three-input memory arrays capable of storing logic information, (c) three-input, three-output logic gates performing combinations of logical functions OR, XOR, AND, and NAND.

Electrical Characteristics of WSi2 Nanocrystal Capacitors with Barrier-Engineered High-k Tunnel Layers

NASA Astrophysics Data System (ADS)

Lee, Hyo Jun; Lee, Dong Uk; Kim, Eun Kyu; You, Hee-Wook; Cho, Won-Ju

2011-06-01

Nanocrystal-floating gate capacitors with WSi2 nanocrystals and high-k tunnel layers were fabricated to improve the electrical properties such as retention, programming/erasing speed, and endurance. The WSi2 nanocrystals were distributed uniformly between the tunnel and control gate oxide layers. The electrical performance of the tunnel barrier with the SiO2/HfO2/Al2O3 (2/1/3 nm) (OHA) tunnel layer appeared to be better than that with the Al2O3/HfO2/Al2O3 (2/1/3 nm) (AHA) tunnel layer. When ΔVFB is about 1 V after applying voltage at ±8 V, the programming/erasing speeds of AHA and OHA tunnel layers are 300 ms and 500 µs, respectively. In particular, the device with WSi2 nanocrystals and the OHA tunnel barrier showed a large memory window of about 7.76 V when the voltage swept from 10 to -10 V, and it was maintained at about 2.77 V after 104 cycles.

Proposal for a graphene-based all-spin logic gate

NASA Astrophysics Data System (ADS)

Su, Li; Zhao, Weisheng; Zhang, Yue; Querlioz, Damien; Zhang, Youguang; Klein, Jacques-Olivier; Dollfus, Philippe; Bournel, Arnaud

2015-02-01

In this work, we present a graphene-based all-spin logic gate (G-ASLG) that integrates the functionalities of perpendicular anisotropy magnetic tunnel junctions (p-MTJs) with spin transport in graphene-channel. It provides an ideal integration of logic and memory. The input and output states are defined as the relative magnetization between free layer and fixed layer of p-MTJs. They can be probed by the tunnel magnetoresistance and controlled by spin transfer torque effect. Using lateral non-local spin valve, the spin information is transmitted by the spin-current interaction through graphene channels. By using a physics-based spin current compact model, the operation of G-ASLG is demonstrated and its performance is analyzed. It allows us to evaluate the influence of parameters, such as spin injection efficiency, spin diffusion length, contact area, the device length, and their interdependence, and to optimize the energy and dynamic performance. Compared to other beyond-CMOS solutions, longer spin information transport length (˜μm), higher data throughput, faster computing speed (˜ns), and lower power consumption (˜μA) can be expected from the G-ASLG.

Quantum gate-set tomography

NASA Astrophysics Data System (ADS)

Blume-Kohout, Robin

2014-03-01

Quantum information technology is built on (1) physical qubits and (2) precise, accurate quantum logic gates that transform their states. Developing quantum logic gates requires good characterization - both in the development phase, where we need to identify a device's flaws so as to fix them, and in the production phase, where we need to make sure that the device works within specs and predict residual error rates and types. This task falls to quantum state and process tomography. But until recently, protocols for tomography relied on a pre-existing and perfectly calibrated reference frame comprising the measurements (and, for process tomography, input states) used to characterize the device. In practice, these measurements are neither independent nor perfectly known - they are usually implemented via exactly the same gates that we are trying to characterize! In the past year, several partial solutions to this self-consistency problem have been proposed. I will present a framework (gate set tomography, or GST) that addresses and resolves this problem, by self-consistently characterizing an entire set of quantum logic gates on a black-box quantum device. In particular, it contains an explicit closed-form protocol for linear-inversion gate set tomography (LGST), which is immune to both calibration error and technical pathologies like local maxima of the likelihood (which plagued earlier methods). GST also demonstrates significant (multiple orders of magnitude) improvements in efficiency over standard tomography by using data derived from long sequences of gates (much like randomized benchmarking). GST has now been applied to qubit devices in multiple technologies. I will present and discuss results of GST experiments in technologies including a single trapped-ion qubit and a silicon quantum dot qubit. Sandia National Laboratories is a multiprogram laboratory operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL850.

A memory efficient implementation scheme of Gauss error function in a Laguerre-Volterra network for neuroprosthetic devices

NASA Astrophysics Data System (ADS)

Li, Will X. Y.; Cui, Ke; Zhang, Wei

2017-04-01

Cognitive neural prosthesis is a manmade device which can be used to restore or compensate for lost human cognitive modalities. The generalized Laguerre-Volterra (GLV) network serves as a robust mathematical underpinning for the development of such prosthetic instrument. In this paper, a hardware implementation scheme of Gauss error function for the GLV network targeting reconfigurable platforms is reported. Numerical approximations are formulated which transform the computation of nonelementary function into combinational operations of elementary functions, and memory-intensive look-up table (LUT) based approaches can therefore be circumvented. The computational precision can be made adjustable with the utilization of an error compensation scheme, which is proposed based on the experimental observation of the mathematical characteristics of the error trajectory. The precision can be further customizable by exploiting the run-time characteristics of the reconfigurable system. Compared to the polynomial expansion based implementation scheme, the utilization of slice LUTs, occupied slices, and DSP48E1s on a Xilinx XC6VLX240T field-programmable gate array has decreased by 94.2%, 94.1%, and 90.0%, respectively. While compared to the look-up table based scheme, 1.0 ×1017 bits of storage can be spared under the maximum allowable error of 1.0 ×10-3 . The proposed implementation scheme can be employed in the study of large-scale neural ensemble activity and in the design and development of neural prosthetic device.

Attention Gating in Short-Term Visual Memory.

ERIC Educational Resources Information Center

Reeves, Adam; Sperling, George

1986-01-01

An experiment is conducted showing that an attention shift to a stream of numerals presented in rapid serial visual presentation mode produces not a total loss, but a systematic distortion of order. An attention gating model (AGM) is developed from a more general attention model. (Author/LMO)

Tuning the metal-insulator crossover and magnetism in SrRuO 3 by ionic gating

DOE PAGES

Yi, Hee Taek; Gao, Bin; Xie, Wei; ...

2014-10-13

Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. We report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO 3. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90–250 K and 70–100 K,more » respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.« less

Tuning the metal-insulator crossover and magnetism in SrRuO₃ by ionic gating.

PubMed

Yi, Hee Taek; Gao, Bin; Xie, Wei; Cheong, Sang-Wook; Podzorov, Vitaly

2014-10-13

Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. Here we report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO₃. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90-250 K and 70-100 K, respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.

Performance analysis of junction-less double Gate n-p-n impact ionization MOS transistor (JLDG n-IMOS)

NASA Astrophysics Data System (ADS)

Chauhan, Manvendra Singh; Chauhan, R. K.

2018-04-01

This paper demonstrates a Junction-less Double Gate n-p-n Impact ionization MOS transistor (JLDG n-IMOS) on a very light doped p-type silicon body. Device structure proposed in the paper is based on charge plasma concept. There is no metallurgical junctions in the proposed device and does not need any impurity doping to create the drain and source regions. Due to doping-less nature, the fabrication process is simple for JLDG n-IMOS. The double gate engineering in proposed device leads to reduction in avalanche breakdown via impact ionization, generating large number of carriers in drain-body junction, resulting high ION current, small IOFF current and great improvement in ION/IOFF ratio. The simulation and examination of the proposed device have been performed on ATLAS device simulatorsoftware.

Top and Split Gating Control of the Electrical Characteristics of a Two-dimensional Electron Gas in a LaAlO3/SrTiO3 Perovskite

NASA Astrophysics Data System (ADS)

Kwak, Yongsu; Song, Jonghyun; Kim, Jihwan; Kim, Jinhee

2018-04-01

A top gate field effect transistor was fabricated using polymethyl methacrylate (PMMA) as a gate insulator on a LaAlO3 (LAO)/SrTiO3 (STO) hetero-interface. It showed n-type behavior, and a depletion mode was observed at low temperature. The electronic properties of the 2-dimensional electron gas at the LAO/STO hetero-interface were not changed by covering LAO with PMMA following the Au top gate electrode. A split gate device was also fabricated to construct depletion mode by using a narrow constriction between the LAO/STO conduction interface. The depletion mode, as well as superconducting critical current, could be controlled by applying a split gate voltage. Noticeably, the superconducting critical current tended to decrease with decreasing the split gate voltage and finally became zero. These results indicate that a weak-linked Josephson junction can be constructed and destroyed by split gating. This observation opens the possibility of gate-voltage-adjustable quantum devices.

Gate tunable parallel double quantum dots in InAs double-nanowire devices

NASA Astrophysics Data System (ADS)

Baba, S.; Matsuo, S.; Kamata, H.; Deacon, R. S.; Oiwa, A.; Li, K.; Jeppesen, S.; Samuelson, L.; Xu, H. Q.; Tarucha, S.

2017-12-01

We report fabrication and characterization of InAs nanowire devices with two closely placed parallel nanowires. The fabrication process we develop includes selective deposition of the nanowires with micron scale alignment onto predefined finger bottom gates using a polymer transfer technique. By tuning the double nanowire with the finger bottom gates, we observed the formation of parallel double quantum dots with one quantum dot in each nanowire bound by the normal metal contact edges. We report the gate tunability of the charge states in individual dots as well as the inter-dot electrostatic coupling. In addition, we fabricate a device with separate normal metal contacts and a common superconducting contact to the two parallel wires and confirm the dot formation in each wire from comparison of the transport properties and a superconducting proximity gap feature for the respective wires. With the fabrication techniques established in this study, devices can be realized for more advanced experiments on Cooper-pair splitting, generation of Parafermions, and so on.

Analytical Modeling of Triple-Metal Hetero-Dielectric DG SON TFET

NASA Astrophysics Data System (ADS)

Mahajan, Aman; Dash, Dinesh Kumar; Banerjee, Pritha; Sarkar, Subir Kumar

2018-02-01

In this paper, a 2-D analytical model of triple-metal hetero-dielectric DG TFET is presented by combining the concepts of triple material gate engineering and hetero-dielectric engineering. Three metals with different work functions are used as both front- and back gate electrodes to modulate the barrier at source/channel and channel/drain interface. In addition to this, front gate dielectric consists of high-K HfO2 at source end and low-K SiO2 at drain side, whereas back gate dielectric is replaced by air to further improve the ON current of the device. Surface potential and electric field of the proposed device are formulated solving 2-D Poisson's equation and Young's approximation. Based on this electric field expression, tunneling current is obtained by using Kane's model. Several device parameters are varied to examine the behavior of the proposed device. The analytical model is validated with TCAD simulation results for proving the accuracy of our proposed model.

Realization of Molecular-Based Transistors.

PubMed

Richter, Shachar; Mentovich, Elad; Elnathan, Roey

2018-06-06

Molecular-based devices are widely considered as significant candidates to play a role in the next generation of "post-complementary metal-oxide-semiconductor" devices. In this context, molecular-based transistors: molecular junctions that can be electrically gated-are of particular interest as they allow new modes of operation. The properties of molecular transistors composed of a single- or multimolecule assemblies, focusing on their practicality as real-world devices, concerning industry demands and its roadmap are compared. Also, the capability of the gate electrode to modulate the molecular transistor characteristics efficiently is addressed, showing that electrical gating can be easily facilitated in single molecular transistors and that gating of transistor composed of molecular assemblies is possible if the device is formed vertically. It is concluded that while the single-molecular transistor exhibits better performance on the lab-scale, its realization faces signifacant challenges when compared to those faced by transistors composed of a multimolecule assembly. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Integrated-optics heralded controlled-NOT gate for polarization-encoded qubits

NASA Astrophysics Data System (ADS)

Zeuner, Jonas; Sharma, Aditya N.; Tillmann, Max; Heilmann, René; Gräfe, Markus; Moqanaki, Amir; Szameit, Alexander; Walther, Philip

2018-03-01

Recent progress in integrated-optics technology has made photonics a promising platform for quantum networks and quantum computation protocols. Integrated optical circuits are characterized by small device footprints and unrivalled intrinsic interferometric stability. Here, we take advantage of femtosecond-laser-written waveguides' ability to process polarization-encoded qubits and present an implementation of a heralded controlled-NOT gate on chip. We evaluate the gate performance in the computational basis and a superposition basis, showing that the gate can create polarization entanglement between two photons. Transmission through the integrated device is optimized using thermally expanded core fibers and adiabatically reduced mode-field diameters at the waveguide facets. This demonstration underlines the feasibility of integrated quantum gates for all-optical quantum networks and quantum repeaters.

Self-assembled oxide films with tailored nanoscale ionic and electronic channels for controlled resistive switching

DOE PAGES

Cho, Seungho; Yun, Chao; Tappertzhofen, Stefan; ...

2016-08-05

Resistive switches are non-volatile memory cells based on nano-ionic redox processes that offer energy efficient device architectures and open pathways to neuromorphics and cognitive computing. However, channel formation typically requires an irreversible, not well controlled electroforming process, giving difficulty to independently control ionic and electronic properties. The device performance is also limited by the incomplete understanding of the underlying mechanisms. Here, we report a novel memristive model material system based on self-assembled Sm-doped CeO 2 and SrTiO 3 films that allow the separate tailoring of nanoscale ionic and electronic channels at high density (~10 12 inch –2). Here, we systematicallymore » show that these devices allow precise engineering of the resistance states, thus enabling large on–off ratios and high reproducibility. The tunable structure presents an ideal platform to explore ionic and electronic mechanisms and we expect a wide potential impact also on other nascent technologies, ranging from ionic gating to micro-solid oxide fuel cells and neuromorphics.« less

NSC 800, 8-bit CMOS microprocessor

NASA Technical Reports Server (NTRS)

Suszko, S. F.

1984-01-01

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

State memory in solution gated epitaxial graphene

NASA Astrophysics Data System (ADS)

Butko, A. V.; Butko, V. Y.; Lebedev, S. P.; Lebedev, A. A.; Davydov, V. Y.; Smirnov, A. N.; Eliseyev, I. A.; Dunaevskiy, M. S.; Kumzerov, Y. A.

2018-06-01

We studied electrical transport in transistors fabricated on a surface of high quality epitaxial graphene with density of defects as low as 5·1010 cm-2 and observed quasistatic hysteresis with a time constant in a scale of hours. This constant is in a few orders of magnitude greater than the constant previously reported in CVD graphene. The hysteresis observed here can be described as a shift of ∼+2V of the Dirac point measured during a gate voltage increase from the position of the Dirac point measured during a gate voltage decrease. This hysteresis can be characterized as a nonvolatile quasistatic state memory effect in which the state of the gated graphene is determined by its initial state prior to entering the hysteretic region. Due to this effect the difference in resistance of the gated graphene measured in the hysteretic region at the same applied voltages can be as high as 70%. The observed effect can be explained by assuming that charge carriers in graphene and oppositely charged molecular ions from the solution form quasistable interfacial complexes at the graphene interface. These complexes likely preserve the initial state by preventing charge carriers in graphene from discharging in the hysteretic region.

Static and Turn-on Switching Characteristics of 4H-Silicon Carbide SITs to 200 deg C

NASA Technical Reports Server (NTRS)

Niedra, Janis M.; Schwarze, Gene E.

2005-01-01

Test results are presented for normally-off 4H-SiC Static Induction Transistors (SITs) intended for power switching and are among the first normally-off such devices realized in SiC. At zero gate bias, the gate p-n junction depletion layers extend far enough into the conduction channel to cut off the channel. Application of forward gate bias narrows the depletion regions, opening up the channel to conduction by majority carriers. In the present devices, narrow vertical channels get pinched by depletion regions from opposite sides. Since the material is SiC, the devices are usable at temperatures above 150 C. Static curve and pulse mode switching observations were done at selected temperatures up to 200 C on a device with average static characteristics from a batch of similar devices. Gate and drain currents were limited to about 400 mA and 3.5 A, respectively. The drain voltage was limited to roughly 300 V, which is conservative for this 600 V rated device. At 23 C, 1 kW, or even more, could be pulse mode switched in 65 ns (10 to 90 percent) into a 100 load. But at 200 C, the switching capability is greatly reduced in large part by the excessive gate current required. Severe collapse of the saturated drain-to-source current was observed at 200 C. The relation of this property to channel mobility is reviewed.

Self aligned hysteresis free carbon nanotube field-effect transistors

NASA Astrophysics Data System (ADS)

Shlafman, M.; Tabachnik, T.; Shtempluk, O.; Razin, A.; Kochetkov, V.; Yaish, Y. E.

2016-04-01

Hysteresis phenomenon in the transfer characteristics of carbon nanotube field effect transistor (CNT FET) is being considered as the main obstacle for successful realization of electronic devices based on CNTs. In this study, we prepare four kinds of CNTFETs and explore their hysteretic behavior. Two kinds of devices comprise on-surface CNTs (type I) and suspended CNTs (type II) with thin insulating layer underneath and a single global gate which modulates the CNT conductance. The third and fourth types (types III and IV) consist of suspended CNT over a metallic local gate underneath, where for type IV the local gate was patterned self aligned with the source and drain electrodes. The first two types of devices, i.e., type I and II, exhibit substantial hysteresis which increases with scanning range and sweeping time. Under high vacuum conditions and moderate electric fields ( |E |>4 ×106 V /cm ), the hysteresis for on-surface devices cannot be eliminated, as opposed to suspended devices. Interestingly, type IV devices exhibit no hysteresis at all at ambient conditions, and from the different roles which the global and local gates play for the four types of devices, we could learn about the hysteresis mechanism of this system. We believe that these self aligned hysteresis free FETs will enable the realization of different electronic devices and sensors based on CNTs.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

PubMed

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2

NASA Astrophysics Data System (ADS)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-01

Top-gated and bottom-gated transistors with multilayer MoS2 channel fully encapsulated by stacked Al2O3/HfO2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on–off current ratio of 108, high field-effect mobility of 102 cm2 V‑1 s‑1, and low subthreshold swing of 93 mV dec–1. Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10‑3–10‑2 V MV–1 cm–1 after 6 MV cm‑1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS2 channel fully encapsulated by stacked Al2O3/HfO2 is a promising way to fabricate high-performance ML MoS2 field-effect transistors for practical electron device applications.

GaN HEMTs with p-GaN gate: field- and time-dependent degradation

NASA Astrophysics Data System (ADS)

Meneghesso, G.; Meneghini, M.; Rossetto, I.; Canato, E.; Bartholomeus, J.; De Santi, C.; Trivellin, N.; Zanoni, E.

2017-02-01

GaN-HEMTs with p-GaN gate have recently demonstrated to be excellent normally-off devices for application in power conversion systems, thanks to the high and robust threshold voltage (VTH>1 V), the high breakdown voltage, and the low dynamic Ron increase. For this reason, studying the stability and reliability of these devices under high stress conditions is of high importance. This paper reports on our most recent results on the field- and time-dependent degradation of GaN-HEMTs with p-GaN gate submitted to stress with positive gate bias. Based on combined step-stress experiments, constant voltage stress and electroluminescence testing we demonstrated that: (i) when submitted to high/positive gate stress, the transistors may show a negative threshold voltage shift, that is ascribed to the injection of holes from the gate metal towards the p-GaN/AlGaN interface; (ii) in a step-stress experiment, the analyzed commercial devices fail at gate voltages higher than 9-10 V, due to the extremely high electric field over the p-GaN/AlGaN stack; (iii) constant voltage stress tests indicate that the failure is also time-dependent and Weibull distributed. The several processes that can explain the time-dependent failure are discussed in the following.

Experimental Demonstration of xor Operation in Graphene Magnetologic Gates at Room Temperature

NASA Astrophysics Data System (ADS)

Wen, Hua; Dery, Hanan; Amamou, Walid; Zhu, Tiancong; Lin, Zhisheng; Shi, Jing; Žutić, Igor; Krivorotov, Ilya; Sham, L. J.; Kawakami, Roland K.

2016-04-01

We report the experimental demonstration of a magnetologic gate built on graphene at room temperature. This magnetologic gate consists of three ferromagnetic electrodes contacting a single-layer graphene spin channel and relies on spin injection and spin transport in the graphene. We utilize electrical bias tuning of spin injection to balance the inputs and achieve "exclusive or" (xor) logic operation. Furthermore, a simulation of the device performance shows that substantial improvement towards spintronic applications can be achieved by optimizing the device parameters such as the device dimensions. This advance holds promise as a basic building block for spin-based information processing.

Model dynamics for quantum computing

NASA Astrophysics Data System (ADS)

Tabakin, Frank

2017-08-01

A model master equation suitable for quantum computing dynamics is presented. In an ideal quantum computer (QC), a system of qubits evolves in time unitarily and, by virtue of their entanglement, interfere quantum mechanically to solve otherwise intractable problems. In the real situation, a QC is subject to decoherence and attenuation effects due to interaction with an environment and with possible short-term random disturbances and gate deficiencies. The stability of a QC under such attacks is a key issue for the development of realistic devices. We assume that the influence of the environment can be incorporated by a master equation that includes unitary evolution with gates, supplemented by a Lindblad term. Lindblad operators of various types are explored; namely, steady, pulsed, gate friction, and measurement operators. In the master equation, we use the Lindblad term to describe short time intrusions by random Lindblad pulses. The phenomenological master equation is then extended to include a nonlinear Beretta term that describes the evolution of a closed system with increasing entropy. An external Bath environment is stipulated by a fixed temperature in two different ways. Here we explore the case of a simple one-qubit system in preparation for generalization to multi-qubit, qutrit and hybrid qubit-qutrit systems. This model master equation can be used to test the stability of memory and the efficacy of quantum gates. The properties of such hybrid master equations are explored, with emphasis on the role of thermal equilibrium and entropy constraints. Several significant properties of time-dependent qubit evolution are revealed by this simple study.

Poly-4-vinylphenol (PVP) and Poly(melamine-co-formaldehyde) (PMF)-Based Atomic Switching Device and Its Application to Logic Gate Circuits with Low Operating Voltage.

PubMed

Kang, Dong-Ho; Choi, Woo-Young; Woo, Hyunsuk; Jang, Sungkyu; Park, Hyung-Youl; Shim, Jaewoo; Choi, Jae-Woong; Kim, Sungho; Jeon, Sanghun; Lee, Sungjoo; Park, Jin-Hong

2017-08-16

In this study, we demonstrate a high-performance solid polymer electrolyte (SPE) atomic switching device with low SET/RESET voltages (0.25 and -0.5 V, respectively), high on/off-current ratio (10 5 ), excellent cyclic endurance (>10 3 ), and long retention time (>10 4 s), where poly-4-vinylphenol (PVP)/poly(melamine-co-formaldehyde) (PMF) is used as an SPE layer. To accomplish these excellent device performance parameters, we reduce the off-current level of the PVP/PMF atomic switching device by improving the electrical insulating property of the PVP/PMF electrolyte through adjustment of the number of cross-linked chains. We then apply a titanium buffer layer to the PVP/PMF switching device for further improvement of bipolar switching behavior and device stability. In addition, we first implement SPE atomic switch-based logic AND and OR circuits with low operating voltages below 2 V by integrating 5 × 5 arrays of PVP/PMF switching devices on the flexible substrate. In particular, this low operating voltage of our logic circuits was much lower than that (>5 V) of the circuits configured by polymer resistive random access memory. This research successfully presents the feasibility of PVP/PMF atomic switches for flexible integrated circuits for next-generation electronic applications.

The Role of Anterior Nuclei of the Thalamus: A Subcortical Gate in Memory Processing: An Intracerebral Recording Study.

PubMed

Štillová, Klára; Jurák, Pavel; Chládek, Jan; Chrastina, Jan; Halámek, Josef; Bočková, Martina; Goldemundová, Sabina; Říha, Ivo; Rektor, Ivan

2015-01-01

To study the involvement of the anterior nuclei of the thalamus (ANT) as compared to the involvement of the hippocampus in the processes of encoding and recognition during visual and verbal memory tasks. We studied intracerebral recordings in patients with pharmacoresistent epilepsy who underwent deep brain stimulation (DBS) of the ANT with depth electrodes implanted bilaterally in the ANT and compared the results with epilepsy surgery candidates with depth electrodes implanted bilaterally in the hippocampus. We recorded the event-related potentials (ERPs) elicited by the visual and verbal memory encoding and recognition tasks. P300-like potentials were recorded in the hippocampus by visual and verbal memory encoding and recognition tasks and in the ANT by the visual encoding and visual and verbal recognition tasks. No significant ERPs were recorded during the verbal encoding task in the ANT. In the visual and verbal recognition tasks, the P300-like potentials in the ANT preceded the P300-like potentials in the hippocampus. The ANT is a structure in the memory pathway that processes memory information before the hippocampus. We suggest that the ANT has a specific role in memory processes, especially memory recognition, and that memory disturbance should be considered in patients with ANT-DBS and in patients with ANT lesions. ANT is well positioned to serve as a subcortical gate for memory processing in cortical structures.

Low latency and persistent data storage

DOEpatents

Fitch, Blake G; Franceschini, Michele M; Jagmohan, Ashish; Takken, Todd E

2014-02-18

Persistent data storage is provided by a method that includes receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.

Adult forebrain NMDA receptors gate social motivation and social memory.

PubMed

Jacobs, Stephanie; Tsien, Joe Z

2017-02-01

Motivation to engage in social interaction is critical to ensure normal social behaviors, whereas dysregulation in social motivation can contribute to psychiatric diseases such as schizophrenia, autism, social anxiety disorders and post-traumatic stress disorder (PTSD). While dopamine is well known to regulate motivation, its downstream targets are poorly understood. Given the fact that the dopamine 1 (D1) receptors are often physically coupled with the NMDA receptors, we hypothesize that the NMDA receptor activity in the adult forebrain principal neurons are crucial not only for learning and memory, but also for the proper gating of social motivation. Here, we tested this hypothesis by examining sociability and social memory in inducible forebrain-specific NR1 knockout mice. These mice are ideal for exploring the role of the NR1 subunit in social behavior because the NR1 subunit can be selectively knocked out after the critical developmental period, in which NR1 is required for normal development. We found that the inducible deletion of the NMDA receptors prior to behavioral assays impaired, not only object and social recognition memory tests, but also resulted in profound deficits in social motivation. Mice with ablated NR1 subunits in the forebrain demonstrated significant decreases in sociability compared to their wild type counterparts. These results suggest that in addition to its crucial role in learning and memory, the NMDA receptors in the adult forebrain principal neurons gate social motivation, independent of neuronal development. Copyright © 2016 Elsevier Inc. All rights reserved.

A type of all-optical logic gate based on graphene surface plasmon polaritons

NASA Astrophysics Data System (ADS)

Wu, Xiaoting; Tian, Jinping; Yang, Rongcao

2017-11-01

In this paper, a novel type of all-optical logic device based on graphene surface plasmon polaritons (GSP) is proposed. By utilizing linear interference between the GSP waves propagating in the different channels, this new structure can realize six different basic logic gates including OR, XOR, NOT, AND, NOR, and NAND. The state of ;ON/OFF; of each input channel can be well controlled by tuning the optical conductivity of graphene sheets, which can be further controlled by changing the external gate voltage. This type of logic gate is compact in geometrical sizes and is a potential block in the integration of nanophotonic devices.

Impact of device engineering on analog/RF performances of tunnel field effect transistors

NASA Astrophysics Data System (ADS)

Vijayvargiya, V.; Reniwal, B. S.; Singh, P.; Vishvakarma, S. K.

2017-06-01

The tunnel field effect transistor (TFET) and its analog/RF performance is being aggressively studied at device architecture level for low power SoC design. Therefore, in this paper we have investigated the influence of the gate-drain underlap (UL) and different dielectric materials for the spacer and gate oxide on DG-TFET (double gate TFET) and its analog/RF performance for low power applications. Here, it is found that the drive current behavior in DG-TFET with a UL feature while implementing dielectric material for the spacer is different in comparison to that of DG-FET. Further, hetero gate dielectric-based DG-TFET (HGDG-TFET) is more resistive against drain-induced barrier lowering (DIBL) as compared to DG-TFET with high-k (HK) gate dielectric. Along with that, as compared to DG-FET, this paper also analyses the attributes of UL and dielectric material on analog/RF performance of DG-TFET in terms of transconductance (gm ), transconductance generation factor (TGF), capacitance, intrinsic resistance (Rdcr), cut-off frequency (F T), and maximum oscillation frequency (F max). The LK spacer-based HGDG-TFET with a gate-drain UL has the potential to improve the RF performance of device.

Gate engineered heterostructure junctionless TFET with Gaussian doping profile for ambipolar suppression and electrical performance improvement

NASA Astrophysics Data System (ADS)

Aghandeh, Hadi; Sedigh Ziabari, Seyed Ali

2017-11-01

This study investigates a junctionless tunnel field-effect transistor with a dual material gate and a heterostructure channel/source interface (DMG-H-JLTFET). We find that using the heterostructure interface improves device behavior by reducing the tunneling barrier width at the channel/source interface. Simultaneously, the dual material gate structure decreases ambipolar current by increasing the tunneling barrier width at the drain/channel interface. The performance of the device is analyzed based on the energy band diagram at on, off, and ambipolar states. Numerical simulations demonstrate improvements in ION, IOFF, ION/IOFF, subthreshold slope (SS), transconductance and cut-off frequency and suppressed ambipolar behavior. Next, the workfunction optimization of dual material gate is studied. It is found that if appropriate workfunctions are selected for tunnel and auxiliary gates, the JLTFET exhibits considerably improved performance. We then study the influence of Gaussian doping distribution at the drain and the channel on the ambipolar performance of the device and find that a Gaussian doping profile and a dual material gate structure remarkably reduce ambipolar current. Gaussian doped DMG-H-JLTFET, also exhibits enhanced IOFF, ION/IOFF, SS and a low threshold voltage without degrading IOFF.

Comparisons of single event vulnerability of GaAs SRAMS

NASA Astrophysics Data System (ADS)

Weatherford, T. R.; Hauser, J. R.; Diehl, S. E.

1986-12-01

A GaAs MESFET/JFET model incorporated into SPICE has been used to accurately describe C-EJFET, E/D MESFET and D MESFET/resistor GaAs memory technologies. These cells have been evaluated for critical charges due to gate-to-drain and drain-to-source charge collection. Low gate-to-drain critical charges limit conventional GaAs SRAM soft error rates to approximately 1E-6 errors/bit-day. SEU hardening approaches including decoupling resistors, diodes, and FETs have been investigated. Results predict GaAs RAM cell critical charges can be increased to over 0.1 pC. Soft error rates in such hardened memories may approach 1E-7 errors/bit-day without significantly reducing memory speed. Tradeoffs between hardening level, performance and fabrication complexity are discussed.

Performance characteristics of a nanoscale double-gate reconfigurable array

NASA Astrophysics Data System (ADS)

Beckett, Paul

2008-12-01

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

Gate-Sensing the Potential Landscape of a GaAs Two-Dimensional Electron Gas

NASA Astrophysics Data System (ADS)

Croot, Xanthe; Mahoney, Alice; Pauka, Sebastian; Colless, James; Reilly, David; Watson, John; Fallahi, Saeed; Gardner, Geoff; Manfra, Michael; Lu, Hong; Gossard, Arthur

In situ dispersive gate sensors hold potential as a means of enabling the scalable readout of quantum dot arrays. Sensitive to quantum capacitance, dispersive sensors have been used to detect inter- and intra-dot transitions in GaAs double quantum dots, and can distinguish the spin states of singlet triplet qubits. In addition, the gate-sensing technique is likely of value in probing the physics of Majorana zero modes in nanowire devices. Beyond the readout signatures associated with charge and spin configurations of qubits, gate-sensing is sensitive to trapped charge in the potential landscape. Here, we report gate-sensing signals arising from tunnelling of electrons between puddles of trapped charge in a GaAs 2DEG. We examine these signals in a family of different devices with varying mobilities, and as a function of temperature and bias. Implications for qubit readout using the gate-sensing technique are discussed.

GATE AND VACUUM FLUSHING OF SEWER SEDIMENT: LABORATORY TESTING

EPA Science Inventory

The objective of this study was to test the performance of a traditional gate-flushing device and a newly-designed vacuum-flushing device in removing sediment from combined sewers and CSO storage tanks. A laboratory hydraulic flume was used to simulate a reach of sewer or storag...

Irradiation of MOS-FET devices to provide desired logic functions

NASA Technical Reports Server (NTRS)

Danchenko, V.; Schaefer, D. H.

1972-01-01

Gamma, X-ray, electron, or other radiation is used to shift threshold potentials of MOS devices on logic circuits. Before irradiation MOS gates to be shifted are biased positive and other gates are grounded to substrate. Threshold lasts 10 years. Thermal annealing brings circuit back to original configuration.

SEWER SEDIMENT GATE AND VACUUM FLUSHING TANKS: LABORATORY FLUME STUDIES

EPA Science Inventory

The objective of this study was to test the performance of a traditional gate-flushing device and a newly designed vacuum-flushing device in removing sediments from combined sewers and CSO storage tanks. A laboratory hydraulic flune was used to simulate a reach of sewer or storag...

Development of InSb charge-coupled infrared imaging devices: Linear imager

NASA Technical Reports Server (NTRS)

Phillips, J. D.

1976-01-01

The following results were accomplished in the development of charge coupled infrared imaging devices: (1) a four-phase overlapping gate with 9 transfers (2-bits) and 1.0-mil gate lengths was successfully operated, (2) the measured transfer efficiency of 0.975 for this device is in excellent agreement with predictions for the reduced gate length device, (3) mask revisions of the channel stop metal on the 8582 mask have been carried out with the result being a large increase in the dc yield of the tested devices, (4) partial optical sensitivity to chopped blackbody radiation was observed for an 8582 9-bit imager, (5) analytical consideration of the modulation transfer function degradation caused by transfer inefficiency in the CCD registers was presented, and (6) for larger array lengths or for the insertion of isolated bits between sensors, improvements in InSb fabrication technology with corresponding decrease in the interface state density are required.

Study of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) transistor including source drain depletion length: Model for sub-threshold behavior

NASA Astrophysics Data System (ADS)

Kumari, Vandana; Kumar, Ayush; Saxena, Manoj; Gupta, Mridula

2018-01-01

The sub-threshold model formulation of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) FET including source/drain depletion length is reported in the present work under the assumption that the ungated regions are fully depleted. To provide deeper insight into the device performance, the impact of gaussian straggle, channel length, oxide and channel thickness and high-k gate dielectric has been studied using extensive TCAD device simulation.

Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

DOE PAGES

Leng, X.; Bozovic, I.; Bollinger, A. T.

2016-08-10

Epitaxial indium tin oxide films have been grown on both LaAlO 3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers amore » pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices.« less

Technical Note: High temporal resolution characterization of gating response time.

PubMed

Wiersma, Rodney D; McCabe, Bradley P; Belcher, Andrew H; Jensen, Patrick J; Smith, Brett; Aydogan, Bulent

2016-06-01

Low temporal latency between a gating ON/OFF signal and the LINAC beam ON/OFF during respiratory gating is critical for patient safety. Here the authors describe a novel method to precisely measure gating lag times at high temporal resolutions. A respiratory gating simulator with an oscillating platform was modified to include a linear potentiometer for position measurement. A photon diode was placed at linear accelerator isocenter for beam output measurement. The output signals of the potentiometer and diode were recorded simultaneously at 2500 Hz with an analog to digital converter for four different commercial respiratory gating systems. The ON and OFF of the beam signal were located and compared to the expected gating window for both phase and position based gating and the temporal lag times extracted. For phase based gating, a real-time position management (RPM) infrared marker tracking system with a single camera and a RPM system with a stereoscopic camera were measured to have mean gate ON/OFF lag times of 98/90 and 86/44 ms, respectively. For position based gating, an AlignRT 3D surface system and a Calypso magnetic fiducial tracking system were measured to have mean gate ON/OFF lag times of 356/529 and 209/60 ms, respectively. Temporal resolution of the method was high enough to allow characterization of individual gate cycles and was primary limited by the sampling speed of the data recording device. Significant variation of mean gate ON/OFF lag time was found between different gating systems. For certain gating devices, individual gating cycle lag times can vary significantly.

Technical Note: High temporal resolution characterization of gating response time

PubMed Central

Wiersma, Rodney D.; McCabe, Bradley P.; Belcher, Andrew H.; Jensen, Patrick J.; Smith, Brett; Aydogan, Bulent

2016-01-01

Purpose: Low temporal latency between a gating ON/OFF signal and the LINAC beam ON/OFF during respiratory gating is critical for patient safety. Here the authors describe a novel method to precisely measure gating lag times at high temporal resolutions. Methods: A respiratory gating simulator with an oscillating platform was modified to include a linear potentiometer for position measurement. A photon diode was placed at linear accelerator isocenter for beam output measurement. The output signals of the potentiometer and diode were recorded simultaneously at 2500 Hz with an analog to digital converter for four different commercial respiratory gating systems. The ON and OFF of the beam signal were located and compared to the expected gating window for both phase and position based gating and the temporal lag times extracted. Results: For phase based gating, a real-time position management (RPM) infrared marker tracking system with a single camera and a RPM system with a stereoscopic camera were measured to have mean gate ON/OFF lag times of 98/90 and 86/44 ms, respectively. For position based gating, an AlignRT 3D surface system and a Calypso magnetic fiducial tracking system were measured to have mean gate ON/OFF lag times of 356/529 and 209/60 ms, respectively. Conclusions: Temporal resolution of the method was high enough to allow characterization of individual gate cycles and was primary limited by the sampling speed of the data recording device. Significant variation of mean gate ON/OFF lag time was found between different gating systems. For certain gating devices, individual gating cycle lag times can vary significantly. PMID:27277028

Simulating the room-temperature dynamic motion of a ferromagnetic vortex in a bistable potential

NASA Astrophysics Data System (ADS)

Haber, E.; Badea, R.; Berezovsky, J.

2018-05-01

The ability to precisely and reliably control the dynamics of ferromagnetic (FM) vortices could lead to novel nonvolatile memory devices and logic gates. Intrinsic and fabricated defects in the FM material can pin vortices and complicate the dynamics. Here, we simulated switching a vortex between bistable pinning sites using magnetic field pulses. The dynamic motion was modeled with the Thiele equation for a massless, rigid vortex subject to room-temperature thermal noise. The dynamics were explored both when the system was at zero temperature and at room-temperature. The probability of switching for different pulses was calculated, and the major features are explained using the basins of attraction map of the two pinning sites.

Digital gate pulse generator for cycloconverter control

DOEpatents

Klein, Frederick F.; Mutone, Gioacchino A.

1989-01-01

The present invention provides a digital gate pulse generator which controls the output of a cycloconverter used for electrical power conversion applications by determining the timing and delivery of the firing pulses to the switching devices in the cycloconverter. Previous gate pulse generators have been built with largely analog or discrete digital circuitry which require many precision components and periodic adjustment. The gate pulse generator of the present invention utilizes digital techniques and a predetermined series of values to develop the necessary timing signals for firing the switching device. Each timing signal is compared with a reference signal to determine the exact firing time. The present invention is significantly more compact than previous gate pulse generators, responds quickly to changes in the output demand and requires only one precision component and no adjustments.

Low latency and persistent data storage

DOEpatents

Fitch, Blake G; Franceschini, Michele M; Jagmohan, Ashish; Takken, Todd

2014-11-04

Persistent data storage is provided by a computer program product that includes computer program code configured for receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.

Performance analysis of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor

NASA Astrophysics Data System (ADS)

Ahish, S.; Sharma, Dheeraj; Vasantha, M. H.; Kumar, Y. B. N.

2017-03-01

In this paper, analog/RF performance of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor (HJTFET) has been explored. A highly doped n+ layer is placed at the Source-Channel junction in order to improve the horizontal electric field component and thus, improve the realiability of the device. The analog performance of the device is analysed by extracting current-voltage characteristics, transcondutance (gm), gate-to-drain capacitance (Cgd) and gate-to-source capacitance (Cgs). Further, RF performance of the device is evaluated by obtaining cut-off frequency (fT) and Gain Bandwidth (GBW) product. ION /IOFF ratio equal to ≈ 109, subthreshold slope of 27 mV/dec, maximum fT of 2.1 THz and maximum GBW of 484 GHz were achieved. Also, the impact of temperature variation on the linearity performance of the device has been investigated. Furthermore, the circuit level performance of the device is performed by implementing a Common Source (CS) amplifier; maximum gain of 31.11 dB and 3-dB cut-off frequency equal to 91.2 GHz were achieved for load resistance (RL) = 17.5 KΩ.

Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities

PubMed Central

Jung, Han Sae; Tsai, Hsin-Zon; Wong, Dillon; Germany, Chad; Kahn, Salman; Kim, Youngkyou; Aikawa, Andrew S.; Desai, Dhruv K.; Rodgers, Griffin F.; Bradley, Aaron J.; Velasco, Jairo; Watanabe, Kenji; Taniguchi, Takashi; Wang, Feng; Zettl, Alex; Crommie, Michael F.

2015-01-01

Owing to its relativistic low-energy charge carriers, the interaction between graphene and various impurities leads to a wealth of new physics and degrees of freedom to control electronic devices. In particular, the behavior of graphene’s charge carriers in response to potentials from charged Coulomb impurities is predicted to differ significantly from that of most materials. Scanning tunneling microscopy (STM) and scanning tunneling spectroscopy (STS) can provide detailed information on both the spatial and energy dependence of graphene's electronic structure in the presence of a charged impurity. The design of a hybrid impurity-graphene device, fabricated using controlled deposition of impurities onto a back-gated graphene surface, has enabled several novel methods for controllably tuning graphene’s electronic properties.1-8 Electrostatic gating enables control of the charge carrier density in graphene and the ability to reversibly tune the charge2 and/or molecular5 states of an impurity. This paper outlines the process of fabricating a gate-tunable graphene device decorated with individual Coulomb impurities for combined STM/STS studies.2-5 These studies provide valuable insights into the underlying physics, as well as signposts for designing hybrid graphene devices. PMID:26273961

Gate-Controlled BP-WSe2 Heterojunction Diode for Logic Rectifiers and Logic Optoelectronics.

PubMed

Li, Dong; Wang, Biao; Chen, Mingyuan; Zhou, Jun; Zhang, Zengxing

2017-06-01

p-n junctions play an important role in modern semiconductor electronics and optoelectronics, and field-effect transistors are often used for logic circuits. Here, gate-controlled logic rectifiers and logic optoelectronic devices based on stacked black phosphorus (BP) and tungsten diselenide (WSe 2 ) heterojunctions are reported. The gate-tunable ambipolar charge carriers in BP and WSe 2 enable a flexible, dynamic, and wide modulation on the heterojunctions as isotype (p-p and n-n) and anisotype (p-n) diodes, which exhibit disparate rectifying and photovoltaic properties. Based on such characteristics, it is demonstrated that BP-WSe 2 heterojunction diodes can be developed for high-performance logic rectifiers and logic optoelectronic devices. Logic optoelectronic devices can convert a light signal to an electric one by applied gate voltages. This work should be helpful to expand the applications of 2D crystals. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Formation of nanofilament field emission devices

DOEpatents

Morse, Jeffrey D.; Contolini, Robert J.; Musket, Ronald G.; Bernhardt, Anthony F.

2000-01-01

A process for fabricating a nanofilament field emission device. The process enables the formation of high aspect ratio, electroplated nanofilament structure devices for field emission displays wherein a via is formed in a dielectric layer and is self-aligned to a via in the gate metal structure on top of the dielectric layer. The desired diameter of the via in the dielectric layer is on the order of 50-200 nm, with an aspect ratio of 5-10. In one embodiment, after forming the via in the dielectric layer, the gate metal is passivated, after which a plating enhancement layer is deposited in the bottom of the via, where necessary. The nanofilament is then electroplated in the via, followed by removal of the gate passification layer, etch back of the dielectric, and sharpening of the nanofilament. A hard mask layer may be deposited on top of the gate metal and removed following electroplating of the nanofilament.

High-frequency graphene voltage amplifier.

PubMed

Han, Shu-Jen; Jenkins, Keith A; Valdes Garcia, Alberto; Franklin, Aaron D; Bol, Ageeth A; Haensch, Wilfried

2011-09-14

While graphene transistors have proven capable of delivering gigahertz-range cutoff frequencies, applying the devices to RF circuits has been largely hindered by the lack of current saturation in the zero band gap graphene. Herein, the first high-frequency voltage amplifier is demonstrated using large-area chemical vapor deposition grown graphene. The graphene field-effect transistor (GFET) has a 6-finger gate design with gate length of 500 nm. The graphene common-source amplifier exhibits ∼5 dB low frequency gain with the 3 dB bandwidth greater than 6 GHz. This first AC voltage gain demonstration of a GFET is attributed to the clear current saturation in the device, which is enabled by an ultrathin gate dielectric (4 nm HfO(2)) of the embedded gate structures. The device also shows extrinsic transconductance of 1.2 mS/μm at 1 V drain bias, the highest for graphene FETs using large-scale graphene reported to date.

Trap-mediated electronic transport properties of gate-tunable pentacene/MoS2 p-n heterojunction diodes

PubMed Central

Kim, Jae-Keun; Cho, Kyungjune; Kim, Tae-Young; Pak, Jinsu; Jang, Jingon; Song, Younggul; Kim, Youngrok; Choi, Barbara Yuri; Chung, Seungjun; Hong, Woong-Ki; Lee, Takhee

2016-01-01

We investigated the trap-mediated electronic transport properties of pentacene/molybdenum disulphide (MoS2) p-n heterojunction devices. We observed that the hybrid p-n heterojunctions were gate-tunable and were strongly affected by trap-assisted tunnelling through the van der Waals gap at the heterojunction interfaces between MoS2 and pentacene. The pentacene/MoS2 p-n heterojunction diodes had gate-tunable high ideality factor, which resulted from trap-mediated conduction nature of devices. From the temperature-variable current-voltage measurement, a space-charge-limited conduction and a variable range hopping conduction at a low temperature were suggested as the gate-tunable charge transport characteristics of these hybrid p-n heterojunctions. Our study provides a better understanding of the trap-mediated electronic transport properties in organic/2-dimensional material hybrid heterojunction devices. PMID:27829663

Trap-mediated electronic transport properties of gate-tunable pentacene/MoS2 p-n heterojunction diodes

NASA Astrophysics Data System (ADS)

Kim, Jae-Keun; Cho, Kyungjune; Kim, Tae-Young; Pak, Jinsu; Jang, Jingon; Song, Younggul; Kim, Youngrok; Choi, Barbara Yuri; Chung, Seungjun; Hong, Woong-Ki; Lee, Takhee

2016-11-01

We investigated the trap-mediated electronic transport properties of pentacene/molybdenum disulphide (MoS2) p-n heterojunction devices. We observed that the hybrid p-n heterojunctions were gate-tunable and were strongly affected by trap-assisted tunnelling through the van der Waals gap at the heterojunction interfaces between MoS2 and pentacene. The pentacene/MoS2 p-n heterojunction diodes had gate-tunable high ideality factor, which resulted from trap-mediated conduction nature of devices. From the temperature-variable current-voltage measurement, a space-charge-limited conduction and a variable range hopping conduction at a low temperature were suggested as the gate-tunable charge transport characteristics of these hybrid p-n heterojunctions. Our study provides a better understanding of the trap-mediated electronic transport properties in organic/2-dimensional material hybrid heterojunction devices.

Trap-mediated electronic transport properties of gate-tunable pentacene/MoS2 p-n heterojunction diodes.

PubMed

Kim, Jae-Keun; Cho, Kyungjune; Kim, Tae-Young; Pak, Jinsu; Jang, Jingon; Song, Younggul; Kim, Youngrok; Choi, Barbara Yuri; Chung, Seungjun; Hong, Woong-Ki; Lee, Takhee

2016-11-10

We investigated the trap-mediated electronic transport properties of pentacene/molybdenum disulphide (MoS 2 ) p-n heterojunction devices. We observed that the hybrid p-n heterojunctions were gate-tunable and were strongly affected by trap-assisted tunnelling through the van der Waals gap at the heterojunction interfaces between MoS 2 and pentacene. The pentacene/MoS 2 p-n heterojunction diodes had gate-tunable high ideality factor, which resulted from trap-mediated conduction nature of devices. From the temperature-variable current-voltage measurement, a space-charge-limited conduction and a variable range hopping conduction at a low temperature were suggested as the gate-tunable charge transport characteristics of these hybrid p-n heterojunctions. Our study provides a better understanding of the trap-mediated electronic transport properties in organic/2-dimensional material hybrid heterojunction devices.