Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors with atomic layer deposited Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Lin, H. C.; Yang, T.; Sharifi, H.; Kim, S. K.; Xuan, Y.; Shen, T.; Mohammadi, S.; Ye, P. D.

2007-11-01

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with ex situ atomic-layer-deposited Al2O3 as gate dielectrics are studied. Maximum drain currents of 211 and 263mA/mm are obtained for 1μm gate-length Al2O3 MOS-HEMTs with 3 and 6nm thick gate oxide, respectively. C-V characteristic shows negligible hysteresis and frequency dispersion. The gate leakage current density of the MOS-HEMTs is 3-5 orders of magnitude lower than the conventional HEMTs under similar bias conditions. The drain current on-off ratio of MOS-HEMTs is ˜3×103 with a subthreshold swing of 90mV/decade. A maximum cutoff frequency (fT) of 27.3GHz and maximum oscillation frequency (fmax) of 39.9GHz and an effective channel mobility of 4250cm2/Vs are measured for the 1μm gate-length Al2O3 MOS-HEMT with 6nm gate oxide. Hooge's constant measured by low frequency noise spectral density characterization is 3.7×10-5 for the same device.

TiN/Al2O3/ZnO gate stack engineering for top-gate thin film transistors by combination of post oxidation and annealing

NASA Astrophysics Data System (ADS)

Kato, Kimihiko; Matsui, Hiroaki; Tabata, Hitoshi; Takenaka, Mitsuru; Takagi, Shinichi

2018-04-01

Control of fabrication processes for a gate stack structure with a ZnO thin channel layer and an Al2O3 gate insulator has been examined for enhancing the performance of a top-gate ZnO thin film transistor (TFT). The Al2O3/ZnO interface and the ZnO layer are defective just after the Al2O3 layer formation by atomic layer deposition. Post treatments such as plasma oxidation, annealing after the Al2O3 deposition, and gate metal formation (PMA) are promising to improve the interfacial and channel layer qualities drastically. Post-plasma oxidation effectively reduces the interfacial defect density and eliminates Fermi level pinning at the Al2O3/ZnO interface, which is essential for improving the cut-off of the drain current of TFTs. A thermal effect of post-Al2O3 deposition annealing at 350 °C can improve the crystalline quality of the ZnO layer, enhancing the mobility. On the other hand, impacts of post-Al2O3 deposition annealing and PMA need to be optimized because the annealing can also accompany the increase in the shallow-level defect density and the resulting electron concentration, in addition to the reduction in the deep-level defect density. The development of the interfacial control technique has realized the excellent TFT performance with a large ON/OFF ratio, steep subthreshold characteristics, and high field-effect mobility.

Novel Dry-Type Glucose Sensor Based on a Metal-Oxide-Semiconductor Capacitor Structure with Horseradish Peroxidase + Glucose Oxidase Catalyzing Layer

NASA Astrophysics Data System (ADS)

Lin, Jing-Jenn; Wu, You-Lin; Hsu, Po-Yen

2007-10-01

In this paper, we present a novel dry-type glucose sensor based on a metal-oxide-semiconductor capacitor (MOSC) structure using SiO2 as a gate dielectric in conjunction with a horseradish peroxidase (HRP) + glucose oxidase (GOD) catalyzing layer. The tested glucose solution was dropped directly onto the window opened on the SiO2 layer, with a coating of HRP + GOD catalyzing layer on top of the gate dielectric. From the capacitance-voltage (C-V) characteristics of the sensor, we found that the glucose solution can induce an inversion layer on the silicon surface causing a gate leakage current flowing along the SiO2 surface. The gate current changes Δ I before and after the drop of glucose solution exhibits a near-linear relationship with increasing glucose concentration. The Δ I sensitivity is about 1.76 nA cm-2 M-1, and the current is quite stable 20 min after the drop of the glucose solution is tested.

Enhancing the pH sensitivity by laterally synergic modulation in dual-gate electric-double-layer transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Ning; Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201; Hui Liu, Yang

2015-02-16

The sensitivity of a standard ion-sensitive field-effect transistor is limited to be 59.2 mV/pH (Nernst limit) at room temperature. Here, a concept based on laterally synergic electric-double-layer (EDL) modulation is proposed in order to overcome the Nernst limit. Indium-zinc-oxide EDL transistors with two laterally coupled gates are fabricated, and the synergic modulation behaviors of the two asymmetric gates are investigated. A high sensitivity of ∼168 mV/pH is realized in the dual-gate operation mode. Laterally synergic modulation in oxide-based EDL transistors is interesting for high-performance bio-chemical sensors.

Chemical gating of epitaxial graphene through ultrathin oxide layers.

PubMed

Larciprete, Rosanna; Lacovig, Paolo; Orlando, Fabrizio; Dalmiglio, Matteo; Omiciuolo, Luca; Baraldi, Alessandro; Lizzit, Silvano

2015-08-07

We achieved a controllable chemical gating of epitaxial graphene grown on metal substrates by exploiting the electrostatic polarization of ultrathin SiO2 layers synthesized below it. Intercalated oxygen diffusing through the SiO2 layer modifies the metal-oxide work function and hole dopes graphene. The graphene/oxide/metal heterostructure behaves as a gated plane capacitor with the in situ grown SiO2 layer acting as a homogeneous dielectric spacer, whose high capacity allows the Fermi level of graphene to be shifted by a few hundreds of meV when the oxygen coverage at the metal substrate is of the order of 0.5 monolayers. The hole doping can be finely tuned by controlling the amount of interfacial oxygen, as well as by adjusting the thickness of the oxide layer. After complete thermal desorption of oxygen the intrinsic doping of SiO2 supported graphene is evaluated in the absence of contaminants and adventitious adsorbates. The demonstration that the charge state of graphene can be changed by chemically modifying the buried oxide/metal interface hints at the possibility of tuning the level and sign of doping by the use of other intercalants capable of diffusing through the ultrathin porous dielectric and reach the interface with the metal.

A SONOS device with a separated charge trapping layer for improvement of charge injection

NASA Astrophysics Data System (ADS)

Ahn, Jae-Hyuk; Moon, Dong-Il; Ko, Seung-Won; Kim, Chang-Hoon; Kim, Jee-Yeon; Kim, Moon-Seok; Seol, Myeong-Lok; Moon, Joon-Bae; Choi, Ji-Min; Oh, Jae-Sub; Choi, Sung-Jin; Choi, Yang-Kyu

2017-03-01

A charge trapping layer that is separated from the primary gate dielectric is implemented on a FinFET SONOS structure. By virtue of the reduced effective oxide thickness of the primary gate dielectric, a strong gate-to-channel coupling is obtained and thus short-channel effects in the proposed device are effectively suppressed. Moreover, a high program/erase speed and a large shift in the threshold voltage are achieved due to the improved charge injection by the reduced effective oxide thickness. The proposed structure has potential for use in high speed flash memory.

Solvothermal synthesis of gallium-indium-zinc-oxide nanoparticles for electrolyte-gated transistors.

PubMed

Santos, Lídia; Nunes, Daniela; Calmeiro, Tomás; Branquinho, Rita; Salgueiro, Daniela; Barquinha, Pedro; Pereira, Luís; Martins, Rodrigo; Fortunato, Elvira

2015-01-14

Solution-processed field-effect transistors are strategic building blocks when considering low-cost sustainable flexible electronics. Nevertheless, some challenges (e.g., processing temperature, reliability, reproducibility in large areas, and cost effectiveness) are requirements that must be surpassed in order to achieve high-performance transistors. The present work reports electrolyte-gated transistors using as channel layer gallium-indium-zinc-oxide nanoparticles produced by solvothermal synthesis combined with a solid-state electrolyte based on aqueous dispersions of vinyl acetate stabilized with cellulose derivatives, acrylic acid ester in styrene and lithium perchlorate. The devices fabricated using this approach display a ION/IOFF up to 1 × 10(6), threshold voltage (VTh) of 0.3-1.9 V, and mobility up to 1 cm(2)/(V s), as a function of gallium-indium-zinc-oxide ink formulation and two different annealing temperatures. These results validates the usage of electrolyte-gated transistors as a viable and promising alternative for nanoparticle based semiconductor devices as the electrolyte improves the interface and promotes a more efficient step coverage of the channel layer, reducing the operating voltage when compared with conventional dielectrics gating. Moreover, it is shown that by controlling the applied gate potential, the operation mechanism of the electrolyte-gated transistors can be modified from electric double layer to electrochemical doping.

Material parameters from frequency dispersion simulation of floating gate memory with Ge nanocrystals in HfO2

NASA Astrophysics Data System (ADS)

Palade, C.; Lepadatu, A. M.; Slav, A.; Lazanu, S.; Teodorescu, V. S.; Stoica, T.; Ciurea, M. L.

2018-01-01

Trilayer memory capacitors with Ge nanocrystals (NCs) floating gate in HfO2 were obtained by magnetron sputtering deposition on p-type Si substrate followed by rapid thermal annealing at relatively low temperature of 600 °C. The frequency dispersion of capacitance and resistance was measured in accumulation regime of Al/HfO2 gate oxide/Ge NCs in HfO2 floating gate/HfO2 tunnel oxide/SiOx/p-Si/Al memory capacitors. For simulation of the frequency dispersion a complex circuit model was used considering an equivalent parallel RC circuit for each layer of the trilayer structure. A series resistance due to metallic contacts and Si substrate was necessary to be included in the model. A very good fit to the experimental data was obtained and the parameters of each layer in the memory capacitor, i.e. capacitances and resistances were determined and in turn the intrinsic material parameters, i.e. dielectric constants and resistivities of layers were evaluated. The results are very important for the study and optimization of the hysteresis behaviour of floating gate memories based on NCs embedded in oxide.

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices.

PubMed

Black, Jennifer M; Come, Jeremy; Bi, Sheng; Zhu, Mengyang; Zhao, Wei; Wong, Anthony T; Noh, Joo Hyon; Pudasaini, Pushpa R; Zhang, Pengfei; Okatan, Mahmut Baris; Dai, Sheng; Kalinin, Sergei V; Rack, Philip D; Ward, Thomas Zac; Feng, Guang; Balke, Nina

2017-11-22

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal-insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment and theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices

DOE PAGES

Black, Jennifer M.; Come, Jeremy; Bi, Sheng; ...

2017-10-24

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal–insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment andmore » theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.« less

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Black, Jennifer M.; Come, Jeremy; Bi, Sheng

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal–insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment andmore » theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.« less

Direct current performance and current collapse in AlGaN/GaN insulated gate high-electron mobility transistors on Si (1 1 1) substrate with very thin SiO2 gate dielectric

NASA Astrophysics Data System (ADS)

Lachab, M.; Sultana, M.; Fatima, H.; Adivarahan, V.; Fareed, Q.; Khan, M. A.

2012-12-01

This work reports on the dc performance of AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) grown on Si (1 1 1) substrate and the study of current dispersion in these devices using various widely adopted methods. The MOSHEMTs were fabricated using a very thin (4.2 nm) SiO2 film as the gate insulator and were subsequently passivated with about 30 nm thick Si3N4 layer. For devices with 2.5 µm long gates and a 4 µm drain-to-source spacing, the maximum saturation drain current density was 822 mA mm-1 at + 4 V gate bias and the peak external transconductance was ˜100 mS mm-1. Furthermore, the oxide layer successfully suppressed the drain and gate leakage currents with the subthreshold current and the gate diode current levels exceeding by more than three orders of magnitude the levels found in their Schottky gate counterparts. Capacitance-voltage and dynamic current-voltage measurements were carried out to assess the oxide quality as well as the devices’ surface properties after passivation. The efficacy of each of these characterization techniques to probe the presence of interface traps and oxide charge in the nitride-based transistors is also discussed.

Gate bias stress stability under light irradiation for indium zinc oxide thin-film transistors based on anodic aluminium oxide gate dielectrics

NASA Astrophysics Data System (ADS)

Li, Min; Lan, Linfeng; Xu, Miao; Wang, Lei; Xu, Hua; Luo, Dongxiang; Zou, Jianhua; Tao, Hong; Yao, Rihui; Peng, Junbiao

2011-11-01

Thin-film transistors (TFTs) using indium zinc oxide as the active layer and anodic aluminium oxide (Al2O3) as the gate dielectric layer were fabricated. The device showed an electron mobility of as high as 10.1 cm2 V-1 s-1, an on/off current ratio of as high as ~108, and a turn-on voltage (Von) of only -0.5 V. Furthermore, this kind of TFTs was very stable under positive bias illumination stress. However, when the device experienced negative bias illumination stress, the threshold voltage shifted to the positive direction. It was found that the instability under negative bias illumination stress (NBIS) was due to the electrons from the Al gate trapping into the Al2O3 dielectric when exposed to the illuminated light. Using a stacked structure of Al2O3/SiO2 dielectrics, the device became more stable under NBIS.

Nanocomposites of polyimide and mixed oxide nanoparticles for high performance nanohybrid gate dielectrics in flexible thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Ju Hyun; Hwang, Byeong-Ung; Kim, Do-Il; Kim, Jin Soo; Seol, Young Gug; Kim, Tae Woong; Lee, Nae-Eung

2017-05-01

Organic gate dielectrics in thin film transistors (TFTs) for flexible display have advantages of high flexibility yet have the disadvantage of low dielectric constant (low- k). To supplement low- k characteristics of organic gate dielectrics, an organic/inorganic nanocomposite insulator loaded with high- k inorganic oxide nanoparticles (NPs) has been investigated but high loading of high- k NPs in polymer matrix is essential. Herein, compositing of over-coated polyimide (PI) on self-assembled (SA) layer of mixed HfO2 and ZrO2 NPs as inorganic fillers was used to make dielectric constant higher and leakage characteristics lower. A flexible TFT with lower the threshold voltage and high current on/off ratio could be fabricated by using the hybrid gate dielectric structure of the nanocomposite with SA layer of mixed NPs on ultrathin atomic-layer deposited Al2O3. [Figure not available: see fulltext.

Frequency-Stable Ionic-Type Hybrid Gate Dielectrics for High Mobility Solution-Processed Metal-Oxide Thin-Film Transistors

PubMed Central

Heo, Jae Sang; Choi, Seungbeom; Jo, Jeong-Wan; Kang, Jingu; Park, Ho-Hyun; Kim, Yong-Hoon; Park, Sung Kyu

2017-01-01

In this paper, we demonstrate high mobility solution-processed metal-oxide thin-film transistors (TFTs) by using a high-frequency-stable ionic-type hybrid gate dielectric (HGD). The HGD gate dielectric, a blend of sol-gel aluminum oxide (AlOx) and poly(4-vinylphenol) (PVP), exhibited high dielectric constant (ε~8.15) and high-frequency-stable characteristics (1 MHz). Using the ionic-type HGD as a gate dielectric layer, an minimal electron-double-layer (EDL) can be formed at the gate dielectric/InOx interface, enhancing the field-effect mobility of the TFTs. Particularly, using the ionic-type HGD gate dielectrics annealed at 350 °C, InOx TFTs having an average field-effect mobility of 16.1 cm2/Vs were achieved (maximum mobility of 24 cm2/Vs). Furthermore, the ionic-type HGD gate dielectrics can be processed at a low temperature of 150 °C, which may enable their applications in low-thermal-budget plastic and elastomeric substrates. In addition, we systematically studied the operational stability of the InOx TFTs using the HGD gate dielectric, and it was observed that the HGD gate dielectric effectively suppressed the negative threshold voltage shift during the negative-illumination-bias stress possibly owing to the recombination of hole carriers injected in the gate dielectric with the negatively charged ionic species in the HGD gate dielectric. PMID:28772972

Transport Properties of Anatase-TiO2 Polycrystalline-Thin-Film Field-Effect Transistors with Electrolyte Gate Layers

NASA Astrophysics Data System (ADS)

Horita, Ryohei; Ohtani, Kyosuke; Kai, Takahiro; Murao, Yusuke; Nishida, Hiroya; Toya, Taku; Seo, Kentaro; Sakai, Mio; Okuda, Tetsuji

2013-11-01

We have fabricated anatase-TiO2 polycrystalline-thin-film field-effect transistors (FETs) with poly(vinyl alcohol) (PVA), ion-liquid (IL), and ion-gel (IG) gate layers, and have tried to improve the response to gate voltage by varying the concentration of mobile ions in these electrolyte gate layers. The increase in the concentration of mobile ions by doping NaOH into the PVA gate layer or reducing the gelator in the IG gate layer markedly increases the drain-source current and reduces the driving gate voltage, which show that the mobile ions in the PVA, IL, and IG gate layers cause the formation of electric double layers (EDLs), which act as nanogap capacitors. In these TiO2-EDL-FETs, the slow formation of EDLs and the oxidation reaction at the interface between the surface of the TiO2 film and the electrolytes cause unideal FET properties. In the optimized IL and IG TiO2-EDL-FETs, the driving gate voltage is less than 1 V and the ON/OFF ratios of the transfer characteristics are about 1×104 at RT, and the nearly metallic state is realized at the interface purely by applying a gate voltage.

An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement

NASA Astrophysics Data System (ADS)

Ye, Fan; Xiaorong, Luo; Kun, Zhou; Yuanhang, Fan; Yongheng, Jiang; Qi, Wang; Pei, Wang; Yinchun, Luo; Bo, Zhang

2014-03-01

A low specific on-resistance (Ron,sp) SOI NBL TLDMOS (silicon-on-insulator trench LDMOS with an N buried layer) is proposed. It has three features: a thin N buried layer (NBL) on the interface of the SOI layer/buried oxide (BOX) layer, an oxide trench in the drift region, and a trench gate extended to the BOX layer. First, on the on-state, the electron accumulation layer forms beside the extended trench gate; the accumulation layer and the highly doping NBL constitute an L-shaped low-resistance conduction path, which sharply decreases the Ron,sp. Second, in the y-direction, the BOX's electric field (E-field) strength is increased to 154 V/μm from 48 V/μm of the SOI Trench Gate LDMOS (SOI TG LDMOS) owing to the high doping NBL. Third, the oxide trench increases the lateral E-field strength due to the lower permittivity of oxide than that of Si and strengthens the multiple-directional depletion effect. Fourth, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Therefore, the SOI NBL TLDMOS structure not only increases the breakdown voltage (BV), but also reduces the cell pitch and Ron,sp. Compared with the TG LDMOS, the NBL TLDMOS improves the BV by 105% at the same cell pitch of 6 μm, and decreases the Ron,sp by 80% at the same BV.

High-performance a-IGZO thin-film transistor with conductive indium-tin-oxide buried layer

NASA Astrophysics Data System (ADS)

Ahn, Min-Ju; Cho, Won-Ju

2017-10-01

In this study, we fabricated top-contact top-gate (TCTG) structure of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with a thin buried conductive indium-tin oxide (ITO) layer. The electrical performance of a-IGZO TFTs was improved by inserting an ITO buried layer under the IGZO channel. Also, the effect of the buried layer's length on the electrical characteristics of a-IGZO TFTs was investigated. The electrical performance of the transistors improved with increasing the buried layer's length: a large on/off current ratio of 1.1×107, a high field-effect mobility of 35.6 cm2/Vs, a small subthreshold slope of 116.1 mV/dec, and a low interface trap density of 4.2×1011 cm-2eV-1 were obtained. The buried layer a-IGZO TFTs exhibited enhanced transistor performance and excellent stability against the gate bias stress.

Improvement of Self-Heating of Indium Gallium Zinc Aluminum Oxide Thin-Film Transistors Using Al2O3 Barrier Layer

NASA Astrophysics Data System (ADS)

Jian, Li-Yi; Lee, Hsin-Ying; Lin, Yung-Hao; Lee, Ching-Ting

2018-02-01

To study the self-heating effect, aluminum oxide (Al2O3) barrier layers of various thicknesses have been inserted between the channel layer and insulator layer in bottom-gate-type indium gallium zinc aluminum oxide (IGZAO) thin-film transistors (TFTs). Each IGZAO channel layer was deposited on indium tin oxide (ITO)-coated glass substrate by using a magnetron radiofrequency cosputtering system with dual targets composed of indium gallium zinc oxide (IGZO) and Al. The 3 s orbital of Al cation provided an extra transport pathway and widened the conduction-band bottom, thus increasing the electron mobility of the IGZAO films. The Al-O bonds were able to sustain the oxygen stability of the IGZAO films. The self-heating behavior of the resulting IGZAO TFTs was studied by Hall measurements on the IGZAO films as well as the electrical performance of the IGZAO TFTs with Al2O3 barrier layers of various thicknesses at different temperatures. IGZAO TFTs with 50-nm-thick Al2O3 barrier layer were stressed by positive gate bias stress (PGBS, at gate-source voltage V GS = 5 V and drain-source voltage V DS = 0 V); at V GS = 5 V and V DS = 10 V, the threshold voltage shifts were 0.04 V and 0.2 V, respectively, much smaller than for the other IGZAO TFTs without Al2O3 barrier layer, which shifted by 0.2 V and 1.0 V when stressed under the same conditions.

Comparative study on nitridation and oxidation plasma interface treatment for AlGaN/GaN MIS-HEMTs with AlN gate dielectric

NASA Astrophysics Data System (ADS)

Zhu, Jie-Jie; Ma, Xiao-Hua; Hou, Bin; Chen, Li-Xiang; Zhu, Qing; Hao, Yue

2017-02-01

This paper demonstrated the comparative study on interface engineering of AlN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) by using plasma interface pre-treatment in various ambient gases. The 15 nm AlN gate dielectric grown by plasma-enhanced atomic layer deposition significantly suppressed the gate leakage current by about two orders of magnitude and increased the peak field-effect mobility by more than 50%. NH3/N2 nitridation plasma treatment (NPT) was used to remove the 3 nm poor-quality interfacial oxide layer and N2O/N2 oxidation plasma treatment (OPT) to improve the quality of interfacial layer, both resulting in improved dielectric/barrier interface quality, positive threshold voltage (V th) shift larger than 0.9 V, and negligible dispersion. In comparison, however, NPT led to further decrease in interface charges by 3.38 × 1012 cm-2 and an extra positive V th shift of 1.3 V. Analysis with fat field-effect transistors showed that NPT resulted in better sub-threshold characteristics and transconductance linearity for MIS-HEMTs compared with OPT. The comparative study suggested that direct removing the poor interfacial oxide layer by nitridation plasma was superior to improving the quality of interfacial layer by oxidation plasma for the interface engineering of GaN-based MIS-HEMTs.

Electrical level of defects in single-layer two-dimensional TiO2

NASA Astrophysics Data System (ADS)

Song, X. F.; Hu, L. F.; Li, D. H.; Chen, L.; Sun, Q. Q.; Zhou, P.; Zhang, D. W.

2015-11-01

The remarkable properties of graphene and transition metal dichalcogenides (TMDCs) have attracted increasing attention on two-dimensional materials, but the gate oxide, one of the key components of two-dimensional electronic devices, has rarely reported. We found the single-layer oxide can be used as the two dimensional gate oxide in 2D electronic structure, such as TiO2. However, the electrical performance is seriously influenced by the defects existing in the single-layer oxide. In this paper, a nondestructive and noncontact solution based on spectroscopic ellipsometry has been used to detect the defect states and energy level of single-layer TiO2 films. By fitting the Lorentz oscillator model, the results indicate the exact position of defect energy levels depends on the estimated band gap and the charge state of the point defects of TiO2.

Short-Term Synaptic Plasticity Regulation in Solution-Gated Indium-Gallium-Zinc-Oxide Electric-Double-Layer Transistors.

PubMed

Wan, Chang Jin; Liu, Yang Hui; Zhu, Li Qiang; Feng, Ping; Shi, Yi; Wan, Qing

2016-04-20

In the biological nervous system, synaptic plasticity regulation is based on the modulation of ionic fluxes, and such regulation was regarded as the fundamental mechanism underlying memory and learning. Inspired by such biological strategies, indium-gallium-zinc-oxide (IGZO) electric-double-layer (EDL) transistors gated by aqueous solutions were proposed for synaptic behavior emulations. Short-term synaptic plasticity, such as paired-pulse facilitation, high-pass filtering, and orientation tuning, was experimentally emulated in these EDL transistors. Most importantly, we found that such short-term synaptic plasticity can be effectively regulated by alcohol (ethyl alcohol) and salt (potassium chloride) additives. Our results suggest that solution gated oxide-based EDL transistors could act as the platforms for short-term synaptic plasticity emulation.

Influence of high energy electron irradiation on the characteristics of polysilicon thin film transistors

NASA Astrophysics Data System (ADS)

Aleksandrova, P. V.; Gueorguiev, V. K.; Ivanov, Tz. E.; Kaschieva, S.

2006-08-01

The influence of high energy electron (23 MeV) irradiation on the electrical characteristics of p-channel polysilicon thin film transistors (PSTFTs) was studied. The channel 220 nm thick LPCVD (low pressure chemical vapor deposition) deposited polysilicon layer was phosphorus doped by ion implantation. A 45 nm thick, thermally grown, SiO2 layer served as gate dielectric. A self-alignment technology for boron doping of the source and drain regions was used. 200 nm thick polysilicon film was deposited as a gate electrode. The obtained p-channel PSTFTs were irradiated with different high energy electron doses. Leakage currents through the gate oxide and transfer characteristics of the transistors were measured. A software model describing the field enhancement and the non-uniform current distribution at textured polysilicon/oxide interface was developed. In order to assess the irradiation-stimulated changes of gate oxide parameters the gate oxide tunneling conduction and transistor characteristics were studied. At MeV dose of 6×1013 el/cm2, a negligible degradation of the transistor properties was found. A significant deterioration of the electrical properties of PSTFTs at MeV irradiation dose of 3×1014 el/cm2 was observed.

Room-Temperature-Processed Flexible Amorphous InGaZnO Thin Film Transistor.

PubMed

Xiao, Xiang; Zhang, Letao; Shao, Yang; Zhou, Xiaoliang; He, Hongyu; Zhang, Shengdong

2017-12-13

A room-temperature flexible amorphous indium-gallium-zinc oxide thin film transistor (a-IGZO TFT) technology is developed on plastic substrates, in which both the gate dielectric and passivation layers of the TFTs are formed by an anodic oxidation (anodization) technique. While the gate dielectric Al 2 O 3 is grown with a conventional anodization on an Al:Nd gate electrode, the channel passivation layer Al 2 O 3 is formed using a localized anodization technique. The anodized Al 2 O 3 passivation layer shows a superior passivation effect to that of PECVD SiO 2 . The room-temperature-processed flexible a-IGZO TFT exhibits a field-effect mobility of 7.5 cm 2 /V·s, a subthreshold swing of 0.44 V/dec, an on-off ratio of 3.1 × 10 8 , and an acceptable gate-bias stability with threshold voltage shifts of 2.65 and -1.09 V under positive gate-bias stress and negative gate-bias stress, respectively. Bending and fatigue tests confirm that the flexible a-IGZO TFT also has a good mechanical reliability, with electrical performances remaining consistent up to a strain of 0.76% as well as after 1200 cycles of fatigue testing.

P-type field effect transistor based on Na-doped BaSnO3

NASA Astrophysics Data System (ADS)

Jang, Yeaju; Hong, Sungyun; Park, Jisung; Char, Kookrin

We fabricated field effect transistors (FET) based on the p-type Na-doped BaSnO3 (BNSO) channel layer. The properties of epitaxial BNSO channel layer were controlled by the doping rate. In order to modulate the p-type FET, we used amorphous HfOx and epitaxial BaHfO3 (BHO) gate oxides, both of which have high dielectric constants. HfOx was deposited by atomic-layer-deposition and BHO was epitaxially grown by pulsed laser deposition. The pulsed laser deposited SrRuO3 (SRO) was used as the source and the drain contacts. Indium-tin oxide and La-doped BaSnO3 were used as the gate electrodes on top of the HfOx and the BHO gate oxides, respectively. We will analyze and present the performances of the BNSO field effect transistor such as the IDS-VDS, the IDS-VGS, the Ion/Ioff ratio, and the field effect mobility. Samsung Science and Technology Foundation.

Preparation of gallium nitride surfaces for atomic layer deposition of aluminum oxide

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kerr, A. J.; Department of Chemistry and Biochemistry, University of California, San Diego, La Jolla, California 92093; Chagarov, E.

2014-09-14

A combined wet and dry cleaning process for GaN(0001) has been investigated with XPS and DFT-MD modeling to determine the molecular-level mechanisms for cleaning and the subsequent nucleation of gate oxide atomic layer deposition (ALD). In situ XPS studies show that for the wet sulfur treatment on GaN(0001), sulfur desorbs at room temperature in vacuum prior to gate oxide deposition. Angle resolved depth profiling XPS post-ALD deposition shows that the a-Al{sub 2}O{sub 3} gate oxide bonds directly to the GaN substrate leaving both the gallium surface atoms and the oxide interfacial atoms with XPS chemical shifts consistent with bulk-like charge.more » These results are in agreement with DFT calculations that predict the oxide/GaN(0001) interface will have bulk-like charges and a low density of band gap states. This passivation is consistent with the oxide restoring the surface gallium atoms to tetrahedral bonding by eliminating the gallium empty dangling bonds on bulk terminated GaN(0001)« less

Oxide-based synaptic transistors gated by solution-processed gelatin electrolytes

NASA Astrophysics Data System (ADS)

He, Yinke; Sun, Jia; Qian, Chuan; Kong, Ling-An; Gou, Guangyang; Li, Hongjian

2017-04-01

In human brain, a large number of neurons are connected via synapses. Simulation of the synaptic behaviors using electronic devices is the most important step for neuromorphic systems. In this paper, proton conducting gelatin electrolyte-gated oxide field-effect transistors (FETs) were used for emulating synaptic functions, in which the gate electrode is regarded as pre-synaptic neuron and the channel layer as the post-synaptic neuron. In analogy to the biological synapse, a potential spike can be applied at the gate electrode and trigger ionic motion in the gelatin electrolyte, which in turn generates excitatory post-synaptic current (EPSC) in the channel layer. Basic synaptic behaviors including spike time-dependent EPSC, paired-pulse facilitation (PPF), self-adaptation, and frequency-dependent synaptic transmission were successfully mimicked. Such ionic/electronic hybrid devices are beneficial for synaptic electronics and brain-inspired neuromorphic systems.

Effects of negative gate-bias stress on the performance of solution-processed zinc-oxide transistors

NASA Astrophysics Data System (ADS)

Kim, Dongwook; Lee, Woo-Sub; Shin, Hyunji; Choi, Jong Sun; Zhang, Xue; Park, Jaehoon; Hwang, Jaeeun; Kim, Hongdoo; Bae, Jin-Hyuk

2014-08-01

We studied the effects of negative gate-bias stress on the electrical characteristics of top-contact zinc-oxide (ZnO) thin-film transistors (TFTs), which were fabricated by spin coating a ZnO solution onto a silicon-nitride gate dielectric layer. The negative gate-bias stress caused characteristic degradations in the on-state currents and the field-effect mobility of the fabricated ZnO TFTs. Additionally, a decrease in the off-state currents and a positive shift in the threshold voltage occurred with increasing stress time. These results indicate that the negative gate-bias stress caused an injection of electrons into the gate dielectric, thereby deteriorating the TFT's performance.

Nano-scale zirconia and hafnia dielectrics grown by atomic layer deposition: Crystallinity, interface structures and electrical properties

NASA Astrophysics Data System (ADS)

Kim, Hyoungsub

With the continued scaling of transistors, leakage current densities across the SiO2 gate dielectric have increased enormously through direct tunneling. Presently, metal oxides having higher dielectric constants than SiO2 are being investigated to reduce the leakage current by increasing the physical thickness of the dielectric. Many possible techniques exist for depositing high-kappa gate dielectrics. Atomic layer deposition (ALD) has drawn attention as a method for preparing ultrathin metal oxide layers with excellent electrical characteristics and near-perfect film conformality due to the layer-by-layer nature of the deposition mechanism. For this research, an ALD system using ZrCl4/HfCl4 and H2O was built and optimized. The microstructural and electrical properties of ALD-ZrO2 and HfO2 grown on SiO2/Si substrates were investigated and compared using various characterization tools. In particular, the crystallization kinetics of amorphous ALD-HfO2 films were studied using in-situ annealing experiments in a TEM. The effect of crystallization on the electrical properties of ALD-HfO 2 was also investigated using various in-situ and ex-situ post-deposition anneals. Our results revealed that crystallization had little effect on the magnitude of the gate leakage current or on the conduction mechanisms. Building upon the results for each metal oxide separately, more advanced investigations were made. Several nanolaminate structures using ZrO2 and HfO2 with different sequences and layer thicknesses were characterized. The effects of the starting microstructure on the microstructural evolution of nanolaminate stacks were studied. Additionally, a promising new approach for engineering the thickness of the SiO2-based interface layer between the metal oxide and silicon substrate after deposition of the metal oxide layer was suggested. Through experimental measurements and thermodynamic analysis, it is shown that a Ti overlayer, which exhibits a high oxygen solubility, can effectively getter oxygen from the interface layer, thus decomposing SiO2 and reducing the interface layer thickness in a controllable fashion. As one of several possible applications, ALD-ZrO2 and HfO 2 gate dielectric films were deposited on Ge (001) substrates with different surface passivations. After extensive characterization using various microstructural, electrical, and chemical analyses, excellent MOS electrical properties of high-kappa gate dielectrics on Ge were successfully demonstrated with optimized surface nitridation of the Ge substrates.

High-Mobility 6,13-Bis(triisopropylsilylethynyl) Pentacene Transistors Using Solution-Processed Polysilsesquioxane Gate Dielectric Layers.

PubMed

Matsuda, Yu; Nakahara, Yoshio; Michiura, Daisuke; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) is a low-temperature curable polymer that is compatible with low-cost plastic substrates. We cured PSQ gate dielectric layers by irradiation with ultraviolet light at ~60 °C, and used them for 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) thin film transistors (TFTs). The fabricated TFTs have shown the maximum and average hole mobility of 1.3 and 0.78 ± 0.3 cm2V-1s-1, which are comparable to those of the previously reported transistors using single-crystalline TIPS-pentacene micro-ribbons for their active layers and thermally oxidized SiO2 for their gate dielectric layers. Itis therefore demonstrated that PSQ is a promising polymer gate dielectric material for low-cost organic TFTs.

Radiation hardening of metal-oxide semi-conductor (MOS) devices by boron

NASA Technical Reports Server (NTRS)

Danchenko, V.

1974-01-01

Technique using boron effectively protects metal-oxide semiconductor devices from ionizing radiation without using shielding materials. Boron is introduced into insulating gate oxide layer at semiconductor-insulator interface.

Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors

NASA Astrophysics Data System (ADS)

Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

2016-04-01

In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade-1 and 3.62 × 1011 eV-1 cm-2, respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

Polysilicon Gate Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations in Sub-100 nm MOSFET's with Ultrathin Gate Oxide

NASA Technical Reports Server (NTRS)

Asenov, Asen; Saini, Subhash

2000-01-01

In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFET's with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3-D) "atomistic" simulation technique described else-where. MOSFET's with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled-in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide-thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect or the polysilicon grain boundaries on the threshold voltage variation are also presented.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Duan, Guo Xing; Hatchtel, Jordan; Shen, Xiao

Here, we investigate negative-bias temperature instabilities in SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics. The activation energies we measured for interface-trap charge buildup during negative-bias temperature stress were lower for SiGe channel pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si capping layers than for conventional Si channel pMOSFETs with SiO 2 gate dielectrics. Electron energy loss spectroscopy and scanning transmission electron microscopy images demonstrate that Ge atoms can diffuse from the SiGe layer into the Si capping layer, which is adjacent to the SiO 2/HfO 2 gate dielectric. Density functional calculations show that these Ge atoms reduce themore » strength of nearby Si-H bonds and that Ge-H bond energies are still lower, thereby reducing the activation energy for interface-trap generation for the SiGe devices. Moreover, activation energies for oxide-trap charge buildup during negative-bias temperature stress are similarly small for SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si pMOSFETs with SiO 2 gate dielectrics, suggesting that, in both cases, the oxide-trap charge buildup likely is rate-limited by hole tunneling into the near-interfacial SiO 2.« less

Effect of high-pressure H{sub 2}O treatment on elimination of interfacial GeO{sub X} layer between ZrO{sub 2} and Ge stack

DOE Office of Scientific and Technical Information (OSTI.GOV)

Huang, Chen-Shuo; Liu, Po-Tsun

2011-08-22

This investigation demonstrates the effect of high-pressure H{sub 2}O treatment on the elimination of the interfacial germanium suboxide (GeO{sub X}) layer between ZrO{sub 2} and Ge. The formation of GeO{sub X} interlayer increases the gate-leakage current and worsen the controllability of the gate during deposition or thermal cycles. X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy reveal that high-pressure H{sub 2}O treatment eliminates the interfacial GeO{sub X} layer. The physical mechanism involves the oxidation of non-oxidized Zr with H{sub 2}O and the reduction of GeO{sub X} by H{sub 2}. Treatment with H{sub 2}O reduces the gate-leakage current of a ZrO{submore » 2}/Ge capacitor by a factor of 1000.« less

Interface Engineering for Atomic Layer Deposited Alumina Gate Dielectric on SiGe Substrates.

PubMed

Zhang, Liangliang; Guo, Yuzheng; Hassan, Vinayak Vishwanath; Tang, Kechao; Foad, Majeed A; Woicik, Joseph C; Pianetta, Piero; Robertson, John; McIntyre, Paul C

2016-07-27

Optimization of the interface between high-k dielectrics and SiGe substrates is a challenging topic due to the complexity arising from the coexistence of Si and Ge interfacial oxides. Defective high-k/SiGe interfaces limit future applications of SiGe as a channel material for electronic devices. In this paper, we identify the surface layer structure of as-received SiGe and Al2O3/SiGe structures based on soft and hard X-ray photoelectron spectroscopy. As-received SiGe substrates have native SiOx/GeOx surface layers, where the GeOx-rich layer is beneath a SiOx-rich surface. Silicon oxide regrows on the SiGe surface during Al2O3 atomic layer deposition, and both SiOx and GeOx regrow during forming gas anneal in the presence of a Pt gate metal. The resulting mixed SiOx-GeOx interface layer causes large interface trap densities (Dit) due to distorted Ge-O bonds across the interface. In contrast, we observe that oxygen-scavenging Al top gates decompose the underlying SiOx/GeOx, in a selective fashion, leaving an ultrathin SiOx interfacial layer that exhibits dramatically reduced Dit.

Characteristics of high-k gate dielectric formed by the oxidation of sputtered Hf/Zr/Hf thin films on the Si substrate

NASA Astrophysics Data System (ADS)

Kim, H. D.; Roh, Y.; Lee, J. E.; Kang, H.-B.; Yang, C.-W.; Lee, N.-E.

2004-07-01

We have investigated the effects of high temperature annealing on the physical and electrical properties of multilayered high-k gate oxide [HfSixOy/HfO2/intermixed-layer(IL)/ZrO2/intermixed-layer(IL)/HfO2] in metal-oxide-semiconductor device. The multilayered high-k films were formed after oxidizing the Hf/Zr/Hf films deposited directly on the Si substrate. The subsequent N2 annealing at high temperature (>= 700 °C) not only results in the polycrystallization of the multilayered high-k films, but also causes the diffusion of Zr. The latter transforms the HfSixOy/HfO2/IL/ZrO2/IL/HfO2 film into the Zr-doped HfO2 film, and improves electrical properties in general. However, the thin SiOx interfacial layer starts to form if annealing temperature increases over 700 °C, deteriorating the equivalent oxide thickness. .

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fakhri, M.; Theisen, M.; Behrendt, A.

Top gated metal-oxide thin-film transistors (TFTs) provide two benefits compared to their conventional bottom-gate counterparts: (i) The gate dielectric may concomitantly serve as encapsulation layer for the TFT channel. (ii) Damage of the dielectric due to high-energetic particles during channel deposition can be avoided. In our work, the top-gate dielectric is prepared by ozone based atomic layer deposition at low temperatures. For ultra-low gas permeation rates, we introduce nano-laminates of Al{sub 2}O{sub 3}/ZrO{sub 2} as dielectrics. The resulting TFTs show a superior environmental stability even at elevated temperatures. Their outstanding stability vs. bias stress is benchmarked against bottom-gate devices withmore » encapsulation.« less

Electrical properties of solution processed highly transparent ZnO TFT with organic gate dielectric

NASA Astrophysics Data System (ADS)

Pandya, Nirav C.; Joshi, Nikhil G.; Trivedi, U. N.; Joshi, U. S.

2013-02-01

All oxide thin film transistors (TFT) with zinc oxide active layer were fabricated by chemical solution deposition (CSD) using aqueous solutions on glass substrate. Thin film transistors (TFTs) with amorphous zinc oxide as channel layers and poly-vinyl alcohol as dielectric layers were fabricated at low temperatures by chemical solution deposition (CSD). Atomic force microscopy (AFM) confirmed nano grain size with fairly smooth surface topography. Very small leakage currents were achieved in the transfer curves, while soft saturation was observed in the output current voltage (I-V) characteristics of the device. Optical transmission of better than 87% in the visible region was estimated, which is better than the organic gate insulator based ZnO TFTs reported so far. Our results offer lot of promise to TFT based display and optoelectronics.

Ferroelectric HfZrOx-based MoS2 negative capacitance transistor with ITO capping layers for steep-slope device application

NASA Astrophysics Data System (ADS)

Xu, Jing; Jiang, Shu-Ye; Zhang, Min; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

2018-03-01

A negative capacitance field-effect transistor (NCFET) built with hafnium-based oxide is one of the most promising candidates for low power-density devices due to the extremely steep subthreshold swing (SS) and high on-state current induced by incorporating the ferroelectric material in the gate stack. Here, we demonstrated a two-dimensional (2D) back-gate NCFET with the integration of ferroelectric HfZrOx in the gate stack and few-layer MoS2 as the channel. Instead of using the conventional TiN capping metal to form ferroelectricity in HfZrOx, the NCFET was fabricated on a thickness-optimized Al2O3/indium tin oxide (ITO)/HfZrOx/ITO/SiO2/Si stack, in which the two ITO layers sandwiching the HfZrOx film acted as the control back gate and ferroelectric gate, respectively. The thickness of each layer in the stack was engineered for distinguishable optical identification of the exfoliated 2D flakes on the surface. The NCFET exhibited small off-state current and steep switching behavior with minimum SS as low as 47 mV/dec. Such a steep-slope transistor is compatible with the standard CMOS fabrication process and is very attractive for 2D logic and sensor applications and future energy-efficient nanoelectronic devices with scaling power supply.

Large-Scale Precise Printing of Ultrathin Sol-Gel Oxide Dielectrics for Directly Patterned Solution-Processed Metal Oxide Transistor Arrays.

PubMed

Lee, Won-June; Park, Won-Tae; Park, Sungjun; Sung, Sujin; Noh, Yong-Young; Yoon, Myung-Han

2015-09-09

Ultrathin and dense metal oxide gate di-electric layers are reported by a simple printing of AlOx and HfOx sol-gel precursors. Large-area printed indium gallium zinc oxide (IGZO) thin-film transistor arrays, which exhibit mobilities >5 cm(2) V(-1) s(-1) and gate leakage current of 10(-9) A cm(-2) at a very low operation voltage of 2 V, are demonstrated by continuous simple bar-coated processes. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Electrofluidic gating of a chemically reactive surface.

PubMed

Jiang, Zhijun; Stein, Derek

2010-06-01

We consider the influence of an electric field applied normal to the electric double layer at a chemically reactive surface. Our goal is to elucidate how surface chemistry affects the potential for field-effect control over micro- and nanofluidic systems, which we call electrofluidic gating. The charging of a metal-oxide-electrolyte (MOE) capacitor is first modeled analytically. We apply the Poisson-Boltzmann description of the double layer and impose chemical equilibrium between the ionizable surface groups and the solution at the solid-liquid interface. The chemically reactive surface is predicted to behave as a buffer, regulating the charge in the double layer by either protonating or deprotonating in response to the applied field. We present the dependence of the charge density and the electrochemical potential of the double layer on the applied field, the density, and the dissociation constants of ionizable surface groups and the ionic strength and the pH of the electrolyte. We simulate the responses of SiO(2) and Al(2)O(3), two widely used oxide insulators with different surface chemistries. We also consider the limits to electrofluidic gating imposed by the nonlinear behavior of the double layer and the dielectric strength of oxide materials, which were measured for SiO(2) and Al(2)O(3) films in MOE configurations. Our results clarify the response of chemically reactive surfaces to applied fields, which is crucial to understanding electrofluidic effects in real devices.

Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

NASA Astrophysics Data System (ADS)

Park, C. H.; Im, Seongil; Yun, Jungheum; Lee, Gun Hwan; Lee, Byoung H.; Sung, Myung M.

2009-11-01

We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgOx and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgOx gate operates under low voltage write-erase (WR-ER) pulse of ±20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of ±70 V for WR and ER states. Both devices stably operated under visible illuminations.

Effect of dual-dielectric hydrogen-diffusion barrier layers on the performance of low-temperature processed transparent InGaZnO thin-film transistors

NASA Astrophysics Data System (ADS)

Tari, Alireza; Wong, William S.

2018-02-01

Dual-dielectric SiOx/SiNx thin-film layers were used as back-channel and gate-dielectric barrier layers for bottom-gate InGaZnO (IGZO) thin-film transistors (TFTs). The concentration profiles of hydrogen, indium, gallium, and zinc oxide were analyzed using secondary-ion mass spectroscopy characterization. By implementing an effective H-diffusion barrier, the hydrogen concentration and the creation of H-induced oxygen deficiency (H-Vo complex) defects during the processing of passivated flexible IGZO TFTs were minimized. A bilayer back-channel passivation layer, consisting of electron-beam deposited SiOx on plasma-enhanced chemical vapor-deposition (PECVD) SiNx films, effectively protected the TFT active region from plasma damage and minimized changes in the chemical composition of the semiconductor layer. A dual-dielectric PECVD SiOx/PECVD SiNx gate-dielectric, using SiOx as a barrier layer, also effectively prevented out-diffusion of hydrogen atoms from the PECVD SiNx-gate dielectric to the IGZO channel layer during the device fabrication.

Effects of Energy Relaxation via Quantum Coupling Among Three-Dimensional Motion on the Tunneling Current of Graphene Field-Effect Transistors.

PubMed

Mao, Ling-Feng; Ning, Huansheng; Li, Xijun

2015-12-01

We report theoretical study of the effects of energy relaxation on the tunneling current through the oxide layer of a two-dimensional graphene field-effect transistor. In the channel, when three-dimensional electron thermal motion is considered in the Schrödinger equation, the gate leakage current at a given oxide field largely increases with the channel electric field, electron mobility, and energy relaxation time of electrons. Such an increase can be especially significant when the channel electric field is larger than 1 kV/cm. Numerical calculations show that the relative increment of the tunneling current through the gate oxide will decrease with increasing the thickness of oxide layer when the oxide is a few nanometers thick. This highlights that energy relaxation effect needs to be considered in modeling graphene transistors.

Multibit Polycristalline Silicon-Oxide-Silicon Nitride-Oxide-Silicon Memory Cells with High Density Designed Utilizing a Separated Control Gate

NASA Astrophysics Data System (ADS)

Rok Kim, Kyeong; You, Joo Hyung; Dal Kwack, Kae; Kim, Tae Whan

2010-10-01

Unique multibit NAND polycrystalline silicon-oxide-silicon nitride-oxide-silicon (SONOS) memory cells utilizing a separated control gate (SCG) were designed to increase memory density. The proposed NAND SONOS memory device based on a SCG structure was operated as two bits, resulting in an increase in the storage density of the NVM devices in comparison with conventional single-bit memories. The electrical properties of the SONOS memory cells with a SCG were investigated to clarify the charging effects in the SONOS memory cells. When the program voltage was supplied to each gate of the NAND SONOS flash memory cells, the electrons were trapped in the nitride region of the oxide-nitride-oxide layer under the gate to supply the program voltage. The electrons were accumulated without affecting the other gate during the programming operation, indicating the absence of cross-talk between two trap charge regions. It is expected that the inference effect will be suppressed by the lower program voltage than the program voltage of the conventional NAND flash memory. The simulation results indicate that the proposed unique NAND SONOS memory cells with a SCG can be used to increase memory density.

Gate protective device for SOS array

NASA Technical Reports Server (NTRS)

Meyer, J. E., Jr.; Scott, J. H.

1972-01-01

Protective gate device consisting of alternating heavily doped n(+) and p(+) diffusions eliminates breakdown voltages in silicon oxide on sapphire arrays caused by electrostatic discharge from person or equipment. Diffusions are easily produced during normal double epitaxial processing. Devices with nine layers had 27-volt breakdown.

Impact of metal gates on remote phonon scattering in titanium nitride/hafnium dioxide n-channel metal-oxide-semiconductor field effect transistors-low temperature electron mobility study

NASA Astrophysics Data System (ADS)

Maitra, Kingsuk; Frank, Martin M.; Narayanan, Vijay; Misra, Veena; Cartier, Eduard A.

2007-12-01

We report low temperature (40-300 K) electron mobility measurements on aggressively scaled [equivalent oxide thickness (EOT)=1 nm] n-channel metal-oxide-semiconductor field effect transistors (nMOSFETs) with HfO2 gate dielectrics and metal gate electrodes (TiN). A comparison is made with conventional nMOSFETs containing HfO2 with polycrystalline Si (poly-Si) gate electrodes. No substantial change in the temperature acceleration factor is observed when poly-Si is replaced with a metal gate, showing that soft optical phonons are not significantly screened by metal gates. A qualitative argument based on an analogy between remote phonon scattering and high-resolution electron energy-loss spectroscopy (HREELS) is provided to explain the underlying physics of the observed phenomenon. It is also shown that soft optical phonon scattering is strongly damped by thin SiO2 interface layers, such that room temperature electron mobility values at EOT=1 nm become competitive with values measured in nMOSFETs with SiON gate dielectrics used in current high performance processors.

Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

NASA Astrophysics Data System (ADS)

Wan, Chang Jin; Zhu, Li Qiang; Wan, Xiang; Shi, Yi; Wan, Qing

2016-01-01

The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors.

Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wan, Chang Jin; Wan, Qing, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn; Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201

The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors.

Advanced detectors and signal processing for bubble memories

NASA Technical Reports Server (NTRS)

Kryder, M. H.; Rasky, P. H. L.; Greve, D. W.

1985-01-01

The feasibility of combining silicon and magnetic bubble technologies is demonstrated. Results of bubble film annealing indicate that a low temperature silicon on garnet technology is the most likely one to succeed commercially. Annealing ambients are also shown to have a major effect on the magnetic properties of bubble films. Functional MOSFETs were fabricated on bubble films coated with thick (approximately 1 micron) SiO2 layers. The two main problems with these silicon on garnet MOSFETs are low electron mobilities and large gate leakage currents. Results indicate that the laser recrystallized silicon and gate oxide (SiO2) layers are contaminated. The data suggest that part of the contaminating ions originate in the sputtered oxide spacer layer and part originates in the bubble film itself. A diffusion barrier, such as silicon nitride, placed between the bubble film and the silicon layer should eliminate the contamination induced problem.

Lanthanide-based oxides and silicates for high-kappa gate dielectric applications

NASA Astrophysics Data System (ADS)

Jur, Jesse Stephen

The ability to improve performance of the high-end metal oxide semiconductor field effect transistor (MOSFET) is highly reliant on the dimensional scaling of such a device. In scaling, a decrease in dielectric thickness results in high current leakage between the electrode and the substrate by way of direct tunneling through the gate dielectric. Observation of a high leakage current when the standard gate dielectric, SiO2, is decreased below a thickness of 1.5 nm requires engineering of a replacement dielectric that is much more scalable. This high-kappa dielectric allows for a physically thicker oxide, reducing leakage current. Integration of select lanthanide-based oxides and silicates, in particular lanthanum oxide and silicate, into MOS gate stack devices is examined. The quality of the high-kappa dielectrics is monitored electrically to determine properties such as equivalent oxide thickness, leakage current density and defect densities. In addition, analytical characterization of the dielectric and the gate stack is provided to examine the materialistic significance to the change of the electrical properties of the devices. In this work, lanthanum oxide films have been deposited by thermal evaporation on to a pre-grown chemical oxide layer on silicon. It is observed that the SiO2 interfacial layer can be consumed by a low-temperature reaction with lanthanum oxide to produce a high-quality silicate. This is opposed to depositing lanthanum oxide directly on silicon, which can possibly favor silicide formation. The importance of oxygen regulation in the surrounding environment of the La2O3-SiO2 reaction-anneal is observed. By controlling the oxygen available during the reaction, SiO2 growth can be limited to achieve high stoichiometric ratios of La2O 3 to SiO2. As a result, MOS devices with an equivalent oxide thickness (EOT) of 5 A and a leakage current density of 5.0 A/cm 2 are attained. This data equals the best value achieved in this field and is a substantial improvement over SiO(N) dielectrics, allowing for increased device scaling. High-temperature processing, consistent with the source/drain activation anneal in MOSFET processing, is performed on lanthanum-silicate based MOS devices with Ta or TaN gate electrodes and a W metal capping layer. The thermal limit of Ta is observed to be less than 800°C, resulting in a phase transformation that can result in uncontrolled shifting of the MOS device flat-band voltage. TaN is observed to be more thermally stable (up to 1000°C) and results in an increase in the capacitance density suggesting that it impedes oxygen reaction with silicon to produce SiO2. It is later observed that a W metal capping layer can serve as a high-oxygen source, which results in an increased interfacial SiO2 formation. By limiting the oxygen content in the W capping layer and by utilizing a thermally stable TaN gate electrode, control over the electrical properties of the MOS device is acquired. To determine the stability of amorphous lanthanum-silicate in contact with investigated by means of back-side secondary ion mass spectroscopy profiling. The results are the first reported data showing that the lanthanum incorporated in the silica matrix doe not diffuse into the silicon substrate after high temperature processing. The decrease in the device effective work function (φM,eff ) observed in these samples is examined in detail. First, as a La 2O3 capping layer on HfSiO(N), the shift yields ideal-φ M,eff values for nMOSFET deices (4.0 eV) that were previously inaccessible. Other lanthanide oxides (Dy, Ho and Yb) used as capping layers show similar effects. It is also shown that tuning of φM,eff can be realized by controlling the extent of lanthanide-silicate formation. This research, conducted in conjunction with SEMATECH and the SRC, represents a significant technological advancement in realizing 45 and sub-45 nm MOSFET device nodes.

High-contrast terahertz wave modulation by gated graphene enhanced by extraordinary transmission through ring apertures.

PubMed

Gao, Weilu; Shu, Jie; Reichel, Kimberly; Nickel, Daniel V; He, Xiaowei; Shi, Gang; Vajtai, Robert; Ajayan, Pulickel M; Kono, Junichiro; Mittleman, Daniel M; Xu, Qianfan

2014-03-12

Gate-controllable transmission of terahertz (THz) radiation makes graphene a promising material for making high-speed THz wave modulators. However, to date, graphene-based THz modulators have exhibited only small on/off ratios due to small THz absorption in single-layer graphene. Here we demonstrate a ∼50% amplitude modulation of THz waves with gated single-layer graphene by the use of extraordinary transmission through metallic ring apertures placed right above the graphene layer. The extraordinary transmission induced ∼7 times near-filed enhancement of THz absorption in graphene. These results promise complementary metal-oxide-semiconductor compatible THz modulators with tailored operation frequencies, large on/off ratios, and high speeds, ideal for applications in THz communications, imaging, and sensing.

Control of magnetism by electrical charge doping or redox reactions in a surface-oxidized Co thin film with a solid-state capacitor structure

NASA Astrophysics Data System (ADS)

Hirai, T.; Koyama, T.; Chiba, D.

2018-03-01

We have investigated the electric field (EF) effect on magnetism in a Co thin film with a naturally oxidized surface. The EF was applied to the oxidized Co surface through a gate insulator layer made of HfO2, which was formed using atomic layer deposition (ALD). The efficiency of the EF effect on the magnetic anisotropy in the sample with the HfO2 layer deposited at the appropriate temperature for the ALD process was relatively large compared to the previously reported values with an unoxidized Co film. The coercivity promptly and reversibly followed the variation in gate voltage. The modulation of the channel resistance was at most ˜0.02%. In contrast, a dramatic change in the magnetic properties including the large change in the saturation magnetic moment and a much larger EF-induced modulation of the channel resistance (˜10%) were observed in the sample with a HfO2 layer deposited at a temperature far below the appropriate temperature range. The response of these properties to the gate voltage was very slow, suggesting that a redox reaction dominated the EF effect on the magnetism in this sample. The frequency response for the capacitive properties was examined to discuss the difference in the mechanism of the EF effect observed here.

Investigation of short-circuit failure mechanisms of SiC MOSFETs by varying DC bus voltage

NASA Astrophysics Data System (ADS)

Namai, Masaki; An, Junjie; Yano, Hiroshi; Iwamuro, Noriyuki

2018-07-01

In this study, the experimental evaluation and numerical analysis of short-circuit mechanisms of 1200 V SiC planar and trench MOSFETs were conducted at various DC bus voltages from 400 to 800 V. Investigation of the impact of DC bus voltage on short-circuit capability yielded results that are extremely useful for many existing power electronics applications. Three failure mechanisms were identified in this study: thermal runaway, MOS channel current following device turn-off, and rupture of the gate oxide layer (gate oxide layer damage). The SiC MOSFETs experienced lattice temperatures exceeding 1000 K during the short-circuit transient; as Si insulated gate bipolar transistors (IGBTs) are not typically subject to such temperatures, the MOSFETs experienced distinct failure modes, and the mode experienced was significantly influenced by the DC bus voltage. In conclusion, suggestions regarding the SiC MOSFET design and operation methods that would enhance device robustness are proposed.

Metal-oxide thin-film transistor-based pH sensor with a silver nanowire top gate electrode

NASA Astrophysics Data System (ADS)

Yoo, Tae-Hee; Sang, Byoung-In; Wang, Byung-Yong; Lim, Dae-Soon; Kang, Hyun Wook; Choi, Won Kook; Lee, Young Tack; Oh, Young-Jei; Hwang, Do Kyung

2016-04-01

Amorphous InGaZnO (IGZO) metal-oxide-semiconductor thin-film transistors (TFTs) are one of the most promising technologies to replace amorphous and polycrystalline Si TFTs. Recently, TFT-based sensing platforms have been gaining significant interests. Here, we report on IGZO transistor-based pH sensors in aqueous medium. In order to achieve stable operation in aqueous environment and enhance sensitivity, we used Al2O3 grown by using atomic layer deposition (ALD) and a porous Ag nanowire (NW) mesh as the top gate dielectric and electrode layers, respectively. Such devices with a Ag NW mesh at the top gate electrode rapidly respond to the pH of solutions by shifting the turn-on voltage. Furthermore, the output voltage signals induced by the voltage shifts can be directly extracted by implantation of a resistive load inverter.

Junctionless Thin-Film Transistors Gated by an H₃PO₄-Incorporated Chitosan Proton Conductor.

PubMed

Liu, Huixuan; Xun, Damao

2018-04-01

We fabricated an H3PO4-incorporated chitosan proton conductor film that exhibited the electric double layer effect and showed a high specific capacitance of 4.42 μF/cm2. Transparent indium tin oxide thin-film transistors gated by H3PO4-incorporated chitosan films were fabricated by sputtering through a shadow mask. The operating voltage was as low as 1.2 V because of the high specific capacitance of the H3PO4-incorporated chitosan dielectrics. The junctionless transparent indium tin oxide thin film transistors exhibited good performance, including an estimated current on/off ratio and field-effect mobility of 1.2 × 106 and 6.63 cm2V-1s-1, respectively. These low-voltage thin-film electric-double-layer transistors gated by H3PO4-incorporated chitosan are promising for next generation battery-powered "see-through" portable sensors.

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE PAGES

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.; ...

2014-10-15

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Bi-layer channel structure-based oxide thin-film transistors consisting of ZnO and Al-doped ZnO with different Al compositions and stacking sequences

NASA Astrophysics Data System (ADS)

Cho, Sung Woon; Yun, Myeong Gu; Ahn, Cheol Hyoun; Kim, So Hee; Cho, Hyung Koun

2015-03-01

Zinc oxide (ZnO)-based bi-layers, consisting of ZnO and Al-doped ZnO (AZO) layers grown by atomic layer deposition, were utilized as the channels of oxide thin-film transistors (TFTs). Thin AZO layers (5 nm) with different Al compositions (5 and 14 at. %) were deposited on top of and beneath the ZnO layers in a bi-layer channel structure. All of the bi-layer channel TFTs that included the AZO layers showed enhanced stability (Δ V Th ≤ 3.2 V) under a positive bias stress compared to the ZnO single-layer channel TFT (Δ V Th = 4.0 V). However, the AZO/ZnO bi-layer channel TFTs with an AZO interlayer between the gate dielectric and the ZnO showed a degraded field effect mobility (0.3 cm2/V·s for 5 at. % and 1.8 cm2/V·s for 14 at. %) compared to the ZnO single-layer channel TFT (5.5 cm2/V·s) due to increased scattering caused by Al-related impurities near the gate dielectric/channel interface. In contrast, the ZnO/AZO bi-layer channel TFTs with an AZO layer on top of the ZnO layer exhibited an improved field effect mobility (7.8 cm2/V·s for 14 at. %) and better stability. [Figure not available: see fulltext.

Multi-oxide active layer deposition using Applied Materials Pivot array coater for high-mobility metal oxide TFT

NASA Astrophysics Data System (ADS)

Park, Hyun Chan; Scheer, Evelyn; Witting, Karin; Hanika, Markus; Bender, Marcus; Hsu, Hao Chien; Yim, Dong Kil

2015-11-01

By controlling a thin indium tin oxide (ITO), indium zinc oxide interface layer between gate insulator and indium gallium zinc oxide (IGZO), the thin-film transistor (TFT) performance can reach higher mobility as conventional IGZO as well as superior stability. For large-area display application, Applied Materials static PVD array coater (Applied Materials GmbH & Co. KG, Alzenau, Germany) using rotary targets has been developed to enable uniform thin layer deposition in display industry. Unique magnet motion parameter optimization in Pivot sputtering coater is shown to provide very uniform thin ITO layer to reach TFT performance with high mobility, not only on small scale, but also on Gen8.5 (2500 × 2200 mm glass size) production system.

Low-Temperature-Processed Zinc Oxide Thin-Film Transistors Fabricated by Plasma-Assisted Atomic Layer Deposition

NASA Astrophysics Data System (ADS)

Kawamura, Yumi; Tani, Mai; Hattori, Nozomu; Miyatake, Naomasa; Horita, Masahiro; Ishikawa, Yasuaki; Uraoka, Yukiharu

2012-02-01

We investigated zinc oxide (ZnO) thin films prepared by plasma assisted atomic layer deposition (PA-ALD), and thin-film transistors (TFTs) with the ALD ZnO channel layer for application to next-generation displays. We deposited the ZnO channel layer by PA-ALD at 100 or 300 °C, and fabricated TFTs. The transfer characteristic of the 300 °C-deposited ZnO TFT exhibited high mobility (5.7 cm2 V-1 s-1), although the threshold voltage largely shifted toward the negative (-16 V). Furthermore, we deposited Al2O3 thin film as a gate insulator by PA-ALD at 100 °C for the low-temperature TFT fabrication process. In the case of ZnO TFTs with the Al2O3 gate insulator, the shift of the threshold voltage improved (-0.1 V). This improvement of the negative shift seems to be due to the negative charges of the Al2O3 film deposited by PA-ALD. On the basis of the experimental results, we confirmed that the threshold voltage of ZnO TFTs is controlled by PA-ALD for the deposition of the gate insulator.

MOSFET Electric-Charge Sensor

NASA Technical Reports Server (NTRS)

Robinson, Paul A., Jr.

1988-01-01

Charged-particle probe compact and consumes little power. Proposed modification enables metal oxide/semiconductor field-effect transistor (MOSFET) to act as detector of static electric charges or energetic charged particles. Thickened gate insulation acts as control structure. During measurements metal gate allowed to "float" to potential of charge accumulated in insulation. Stack of modified MOSFET'S constitutes detector of energetic charged particles. Each gate "floats" to potential induced by charged-particle beam penetrating its layer.

Using Ultrathin Parylene Films as an Organic Gate Insulator in Nanowire Field-Effect Transistors.

PubMed

Gluschke, J G; Seidl, J; Lyttleton, R W; Carrad, D J; Cochrane, J W; Lehmann, S; Samuelson, L; Micolich, A P

2018-06-27

We report the development of nanowire field-effect transistors featuring an ultrathin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally coated nanowires, which we used to produce functional Ω-gate and gate-all-around structures. These give subthreshold swings as low as 140 mV/dec and on/off ratios exceeding 10 3 at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically treated nanowire surfaces, a feature generally not possible with oxides produced by atomic layer deposition due to the surface "self-cleaning" effect. Our results highlight the potential for parylene as an alternative ultrathin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylene's well-established biocompatible properties.

Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

PubMed Central

Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M.; Avila-García, Alejandro; Vazquez-Acosta, E. N.; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

2010-01-01

Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

A study on the high temperature-dependence of the electrical properties in a solution-deposited zinc-tin-oxide thin-film transistor operated in the saturation region

NASA Astrophysics Data System (ADS)

Yu, Kyeong Min; Bae, Byung Seong; Jung, Myunghee; Yun, Eui-Jung

2016-06-01

We investigate the effects of high temperatures in the range of 292 - 393 K on the electrical properties of solution-processed amorphous zinc-tin-oxide (a-ZTO) thin-film transistors (TFTs) operated in the saturation region. The fabricated a-ZTO TFTs have a non-patterned bottom gate and top contact structure, and they use a heavily-doped Si wafer and SiO2 as a gate electrode and a gate insulator layer, respectively. In a-ZTO TFTs, the trap release energy ( E TR ) was deduced by using Maxwell-Boltzmann statistics. The decreasing E TR toward zero with increasing gate voltage (the density of trap states ( n s )) in the a-ZTO active layer can be attributed to a shift of the Fermi level toward the mobility edge with increasing gate voltage. The TFTs with low gate voltage (low n s ) exhibit multiple trap and release characteristics and show thermally-activated behavior. In TFTs with a high gate voltage (high n s ), however, we observe decreasing mobility and conductivity with increasing temperature at temperatures ranging from 303 to 363 K. This confirms that the E TR can drop to zero, indicating a shift of the Fermi level beyond the mobility edge. Hence, the mobility edge is detected at the cusp between thermally-activated transport and band transport.

Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

PubMed Central

Long, Rathnait D.; McIntyre, Paul C.

2012-01-01

The literature on polar Gallium Nitride (GaN) surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS) devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

Direct protein detection with a nano-interdigitated array gate MOSFET.

PubMed

Tang, Xiaohui; Jonas, Alain M; Nysten, Bernard; Demoustier-Champagne, Sophie; Blondeau, Franoise; Prévot, Pierre-Paul; Pampin, Rémi; Godfroid, Edmond; Iñiguez, Benjamin; Colinge, Jean-Pierre; Raskin, Jean-Pierre; Flandre, Denis; Bayot, Vincent

2009-08-15

A new protein sensor is demonstrated by replacing the gate of a metal oxide semiconductor field effect transistor (MOSFET) with a nano-interdigitated array (nIDA). The sensor is able to detect the binding reaction of a typical antibody Ixodes ricinus immunosuppressor (anti-Iris) protein at a concentration lower than 1 ng/ml. The sensor exhibits a high selectivity and reproducible specific detection. We provide a simple model that describes the behavior of the sensor and explains the origin of its high sensitivity. The simulated and experimental results indicate that the drain current of nIDA-gate MOSFET sensor is significantly increased with the successive binding of the thiol layer, Iris and anti-Iris protein layers. It is found that the sensor detection limit can be improved by well optimizing the geometrical parameters of nIDA-gate MOSFET. This nanobiosensor, with real-time and label-free capabilities, can easily be used for the detection of other proteins, DNA, virus and cancer markers. Moreover, an on-chip associated electronics nearby the sensor can be integrated since its fabrication is compatible with complementary metal oxide semiconductor (CMOS) technology.

Development of III-V p-MOSFETs with high-kappa gate stack for future CMOS applications

NASA Astrophysics Data System (ADS)

Nagaiah, Padmaja

As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, non-silicon materials and new device architectures are gradually being introduced to improve Si integrated circuit performance and continue transistor scaling. Recently, the replacement of SiO2 with a high-k material (HfO2) as gate dielectric has essentially removed one of the biggest advantages of Si as channel material. As a result, alternate high mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. III-V materials in particular have become of great interest as channel materials, owing to their superior electron transport properties. However, there are several critical challenges that need to be addressed before III-V based CMOS can replace Si CMOS technology. Some of these challenges include development of a high quality, thermally stable gate dielectric/III-V interface, and improvement in III-V p-channel hole mobility to complement the n-channel mobility, low source/drain resistance and integration onto Si substrate. In this thesis, we would be addressing the first two issues i.e. the development high performance III-V p-channels and obtaining high quality III-V/high-k interface. We start with using the device architecture of the already established InGaAs n-channels as a baseline to understand the effect of remote scattering from the high-k oxide and oxide/semiconductor interface on channel transport properties such as electron mobility and channel electron concentration. Temperature dependent Hall electron mobility measurements were performed to separate various scattering induced mobility limiting factors. Dependence of channel mobility on proximity of the channel to the oxide interface, oxide thickness, annealing conditions are discussed. The results from this work will be used in the design of the p-channel MOSFETs. Following this, InxGa1-xAs (x>0.53) is chosen as channel material for developing p-channel MOSFETs. Band engineering, strain induced valence band splitting and quantum confinement is used to improve channel hole mobility. Experimental results on the Hall hole mobility is presented for InxGa1-xAs channels with varying In content, thickness of the quantum well and temperature. Then, high mobility InxGa 1-xAs heterostructure thus obtained are integrated with in-situ deposited high-k gate oxide required for high performance p-MOSFET and discuss the challenges associated with the gated structure and draw conclusions on this material system. Antimonide based channel materials such as GaSb and InxGa 1-xSb are explored for III-V based p-MOSFETs in last two chapters. Options for Sb based strained QW channels to obtain maximum hole mobility by varying the strain, channel and barrier material, thickness of the layers etc. is discussed followed by the growth of these Sb channels on GaAs and InP substrates using molecular beam epitaxy. The physical properties of the structures such as the heterostructure quality, alloy content and surface roughness are examined via TEM, XRD and AFM. Following this, electrical measurement results on Hall hole mobility is presented. The effect of strain, alloy content, temperature and thickness on channel mobility and concentration is reported. Development of GaSb n- and p-MOS capacitor structures with in-situ deposited HfO2 gate oxide dielectric using in-situ deposited amorphous Si (a-Si) interface passivation layer (IPL) to improve the interface quality of high-k oxide and (In)GaSb surface is presented. In-situ deposited gate oxides such as Al2O3 and combination oxide of Al 2O3 and HfO2 with and without the a-Si IPL are also explored as alternate gate dielectrics. Subsequently, MOS capacitor structures using buried InGaSb QWs are demonstrated. Development of an inversion type bulk GaSb with implanted source-drain contacts and in-situ deposited gate oxide HfO2 gate oxide is discussed. The merits of biaxial compressive strain is demonstrated on strained surface and buried channel In0.36 Ga0.64Sb QW MOSFETs with thin top barrier and in-situ deposited a-Si IPL and high-k HfO2 as well as combination Al 2O3+HfO2 gate stacks and ex-situ atomic layer deposited (ALD) combination gate oxide and with thin 2 nm InAs surface passivation layer is presented. Finally, summary of the salient results from the different chapters is provided with recommendations for future research.

High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

PubMed

Jaehnike, Felix; Pham, Duy Vu; Anselmann, Ralf; Bock, Claudia; Kunze, Ulrich

2015-07-01

A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications.

Passivation of oxide traps and interface states in GaAs metal-oxide-semiconductor capacitor by LaTaON passivation layer and fluorine incorporation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, L. N.; Choi, H. W.; Lai, P. T., E-mail: laip@eee.hku.hk

2015-11-23

GaAs metal-oxide-semiconductor capacitor with TaYON/LaTaON gate-oxide stack and fluorine-plasma treatment is fabricated and compared with its counterparts without the LaTaON passivation interlayer or the fluorine treatment. Experimental results show that the sample exhibits better characteristics: low interface-state density (8 × 10{sup 11 }cm{sup −2}/eV), small flatband voltage (0.69 V), good capacitance-voltage behavior, small frequency dispersion, and small gate leakage current (6.35 × 10{sup −6} A/cm{sup 2} at V{sub fb} + 1 V). These should be attributed to the suppressed growth of unstable Ga and As oxides on the GaAs surface during gate-oxide annealing by the LaTaON interlayer and fluorine incorporation, and the passivating effects of fluorine atoms on the acceptor-likemore » interface and near-interface traps.« less

Pronounced photogating effect in atomically thin WSe2 with a self-limiting surface oxide layer

NASA Astrophysics Data System (ADS)

Yamamoto, Mahito; Ueno, Keiji; Tsukagoshi, Kazuhito

2018-04-01

The photogating effect is a photocurrent generation mechanism that leads to marked responsivity in two-dimensional (2D) semiconductor-based devices. A key step to promote the photogating effect in a 2D semiconductor is to integrate it with a high density of charge traps. Here, we show that self-limiting surface oxides on atomically thin WSe2 can serve as effective electron traps to facilitate p-type photogating. By examining the gate-bias-induced threshold voltage shift of a p-type transistor based on single-layer WSe2 with surface oxide, the electron trap density and the trap rate of the oxide are determined to be >1012 cm-2 and >1010 cm-2 s-1, respectively. White-light illumination on an oxide-covered 4-layer WSe2 transistor leads to the generation of photocurrent, the magnitude of which increases with the hole mobility. During illumination, the photocurrent evolves on a timescale of seconds, and a portion of the current persists even after illumination. These observations indicate that the photogenerated electrons are trapped deeply in the surface oxide and effectively gate the underlying WSe2. Owing to the pronounced photogating effect, the responsivity of the oxide-covered WSe2 transistor is observed to exceed 3000 A/W at an incident optical power of 1.1 nW, suggesting the effectiveness of surface oxidation in facilitating the photogating effect in 2D semiconductors.

Experimental studies of MOS inversion and accumulation layers: Quantum mechanical effects and mobility

NASA Astrophysics Data System (ADS)

Chindalore, Gowrishankar L.

The development of fast, multi-functional, and energy efficient integrated circuits, is made possible by aggressively scaling the gate lengths of the MOS devices into the sub-quarter micron regime. However, with the increasing cost of fabrication, there is a strong need for the development of reliable and accurate device simulation capabilities. The development of the theoretical models for simulators is guided by extensive experimental data, which enable an experimental verification of the models, and lead to a better understanding of the underlying physics. This dissertation presents the methodology and the results for one such experimental effort, where two important physical effects in the inversion layer and the accumulation layer of a MOS device, namely, the quantum mechanical (QM) effects and the carrier mobility are investigated. Accordingly, this dissertation has been divided into two parts, with the first part discussing the increase in the threshold voltage and the accumulation electrical oxide thickness due to QM effects. The second part discusses the methodology and the experimental results for the extraction of the majority carrier mobilities in the accumulation layers of a MOSFET. The continued scaling of the MOS gate length requires decreased gate oxide thickness (tox) and increased channel doping (NB) in order to improve device performance while suppressing the short- channel effects. The combination of the two result in large enough transverse electric fields to cause significant quantization of the carriers in the potential well at the Si/SiO2 interface. Hence, compared to the classical calculations (where the QM effects are ignored), the QM effects are found to lead to an increase in the experimental threshold voltage by approximately 100mV, and an overestimation of the physical oxide thickness by approximately 3-4A, in MOSFET devices with a gate oxide thickness and the doping level anticipated for technologies with sub-quarter micron gate lengths. Thus, the experimental results indicate the need for using accurate QM models for simulating sub-quarter micron devices. Carrier mobility is a fundamental semiconductor device transport parameter that has been extensively characterized for both electrons and holes in the silicon bulk and MOS inversion layers. Accumulation layer mobility (μacc) has become increasingly important as the MOS devices have scaled to deep submicron gate lengths, and much effort has been required to achieve increased drive current. However, very little experimental data has been reported for carrier mobility in the MOS accumulation layers (Sun80, Man89). Hence, in this research work, the accumulation layer mobilities were extracted using buried-channel MOSFETs for both the electrons and holes, and for a wide range of doping levels at temperatures ranging from 25C to 150C. The experimental μacc is found to be greater than the corresponding bulk and the inversion layer mobilities, at low to moderate effective fields. However, at very high effective fields, where phonon and surface roughness scattering are dominant, the mobility behavior is found to be very similar to that of the inversion carriers. The extensive set of experimental data will enable the development of accurate local accumulation mobility models for inclusion in 2-D device simulators.

Adhesion layer for etching of tracks in nuclear trackable materials

DOEpatents

Morse, Jeffrey D.; Contolini, Robert J.

2001-01-01

A method for forming nuclear tracks having a width on the order of 100-200 nm in nuclear trackable materials, such as polycarbonate (LEXAN) without causing delamination of the LEXAN. The method utilizes an adhesion film having a inert oxide which allows the track to be sufficiently widened to >200 nm without delamination of the nuclear trackable materials. The adhesion film may be composed of a metal such as Cr, Ni, Au, Pt, or Ti, or composed of a dielectric having a stable surface, such as silicon dioxide (SiO.sub.2), silicon nitride (SiN.sub.x), and aluminum oxide (AlO). The adhesion film can either be deposited on top of the gate metal layer, or if the properties of the adhesion film are adequate, it can be used as the gate layer. Deposition of the adhesion film is achieved by standard techniques, such as sputtering or evaporation.

Polycrystalline silicon thin-film transistors fabricated by Joule-heating-induced crystallization

NASA Astrophysics Data System (ADS)

Hong, Won-Eui; Ro, Jae-Sang

2015-01-01

Joule-heating-induced crystallization (JIC) of amorphous silicon (a-Si) films is carried out by applying an electric pulse to a conductive layer located beneath or above the films. Crystallization occurs across the whole substrate surface within few tens of microseconds. Arc instability, however, is observed during crystallization, and is attributed to dielectric breakdown in the conductor/insulator/transformed polycrystalline silicon (poly-Si) sandwich structures at high temperatures during electrical pulsing for crystallization. In this study, we devised a method for the crystallization of a-Si films while preventing arc generation; this method consisted of pre-patterning an a-Si active layer into islands and then depositing a gate oxide and gate electrode. Electric pulsing was then applied to the gate electrode formed using a Mo layer. The Mo layer was used as a Joule-heat source for the crystallization of pre-patterned active islands of a-Si films. JIC-processed poly-Si thin-film transistors (TFTs) were fabricated successfully, and the proposed method was found to be compatible with the standard processing of coplanar top-gate poly-Si TFTs.

Low voltage-driven oxide phototransistors with fast recovery, high signal-to-noise ratio, and high responsivity fabricated via a simple defect-generating process

PubMed Central

Yun, Myeong Gu; Kim, Ye Kyun; Ahn, Cheol Hyoun; Cho, Sung Woon; Kang, Won Jun; Cho, Hyung Koun; Kim, Yong-Hoon

2016-01-01

We have demonstrated that photo-thin film transistors (photo-TFTs) fabricated via a simple defect-generating process could achieve fast recovery, a high signal to noise (S/N) ratio, and high sensitivity. The photo-TFTs are inverted-staggered bottom-gate type indium-gallium-zinc-oxide (IGZO) TFTs fabricated using atomic layer deposition (ALD)-derived Al2O3 gate insulators. The surfaces of the Al2O3 gate insulators are damaged by ion bombardment during the deposition of the IGZO channel layers by sputtering and the damage results in the hysteresis behavior of the photo-TFTs. The hysteresis loops broaden as the deposition power density increases. This implies that we can easily control the amount of the interface trap sites and/or trap sites in the gate insulator near the interface. The photo-TFTs with large hysteresis-related defects have high S/N ratio and fast recovery in spite of the low operation voltages including a drain voltage of 1 V, positive gate bias pulse voltage of 3 V, and gate voltage pulse width of 3 V (0 to 3 V). In addition, through the hysteresis-related defect-generating process, we have achieved a high responsivity since the bulk defects that can be photo-excited and eject electrons also increase with increasing deposition power density. PMID:27553518

Nonvolatile memory with graphene oxide as a charge storage node in nanowire field-effect transistors

NASA Astrophysics Data System (ADS)

Baek, David J.; Seol, Myeong-Lok; Choi, Sung-Jin; Moon, Dong-Il; Choi, Yang-Kyu

2012-02-01

Through the structural modification of a three-dimensional silicon nanowire field-effect transistor, i.e., a double-gate FinFET, a structural platform was developed which allowed for us to utilize graphene oxide (GO) as a charge trapping layer in a nonvolatile memory device. By creating a nanogap between the gate and the channel, GO was embedded after the complete device fabrication. By applying a proper gate voltage, charge trapping, and de-trapping within the GO was enabled and resulted in large threshold voltage shifts. The employment of GO with FinFET in our work suggests that graphitic materials can potentially play a significant role for future nanoelectronic applications.

Single layer of Ge quantum dots in HfO2 for floating gate memory capacitors.

PubMed

Lepadatu, A M; Palade, C; Slav, A; Maraloiu, A V; Lazanu, S; Stoica, T; Logofatu, C; Teodorescu, V S; Ciurea, M L

2017-04-28

High performance trilayer memory capacitors with a floating gate of a single layer of Ge quantum dots (QDs) in HfO 2 were fabricated using magnetron sputtering followed by rapid thermal annealing (RTA). The layer sequence of the capacitors is gate HfO 2 /floating gate of single layer of Ge QDs in HfO 2 /tunnel HfO 2 /p-Si wafers. Both Ge and HfO 2 are nanostructured by RTA at moderate temperatures of 600-700 °C. By nanostructuring at 600 °C, the formation of a single layer of well separated Ge QDs with diameters of 2-3 nm at a density of 4-5 × 10 15 m -2 is achieved in the floating gate (intermediate layer). The Ge QDs inside the intermediate layer are arranged in a single layer and are separated from each other by HfO 2 nanocrystals (NCs) about 8 nm in diameter with a tetragonal/orthorhombic structure. The Ge QDs in the single layer are located at the crossing of the HfO 2 NCs boundaries. In the intermediate layer, besides Ge QDs, a part of the Ge atoms is segregated by RTA at the HfO 2 NCs boundaries, while another part of the Ge atoms is present inside the HfO 2 lattice stabilizing the tetragonal/orthorhombic structure. The fabricated capacitors show a memory window of 3.8 ± 0.5 V and a capacitance-time characteristic with 14% capacitance decay in the first 3000-4000 s followed by a very slow capacitance decrease extrapolated to 50% after 10 years. This high performance is mainly due to the floating gate of a single layer of well separated Ge QDs in HfO 2 , distanced from the Si substrate by the tunnel oxide layer with a precise thickness.

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

PubMed

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J

2016-06-09

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

Oxide-based materials by atomic layer deposition

NASA Astrophysics Data System (ADS)

Godlewski, Marek; Pietruszka, Rafał; Kaszewski, Jarosław; Witkowski, Bartłomiej S.; Gierałtowska, Sylwia; Wachnicki, Łukasz; Godlewski, Michał M.; Slonska, Anna; Gajewski, Zdzisław

2017-02-01

Thin films of wide band-gap oxides grown by Atomic Layer Deposition (ALD) are suitable for a range of applications. Some of these applications will be presented. First of all, ALD-grown high-k HfO2 is used as a gate oxide in the electronic devices. Moreover, ALD-grown oxides can be used in memory devices, in transparent transistors, or as elements of solar cells. Regarding photovoltaics (PV), ALD-grown thin films of Al2O3 are already used as anti-reflection layers. In addition, thin films of ZnO are tested as replacement of ITO in PV devices. New applications in organic photovoltaics, electronics and optoelectronics are also demonstrated Considering new applications, the same layers, as used in electronics, can also find applications in biology, medicine and in a food industry. This is because layers of high-k oxides show antibacterial activity, as discussed in this work.

AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors using Sc2O3 as the gate oxide and surface passivation

NASA Astrophysics Data System (ADS)

Mehandru, R.; Luo, B.; Kim, J.; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Gotthold, D.; Birkhahn, R.; Peres, B.; Fitch, R.; Gillespie, J.; Jenkins, T.; Sewell, J.; Via, D.; Crespo, A.

2003-04-01

We demonstrated that Sc2O3 thin films deposited by plasma-assisted molecular-beam epitaxy can be used simultaneously as a gate oxide and as a surface passivation layer on AlGaN/GaN high electron mobility transistors (HEMTs). The maximum drain source current, IDS, reaches a value of over 0.8 A/mm and is ˜40% higher on Sc2O3/AlGaN/GaN transistors relative to conventional HEMTs fabricated on the same wafer. The metal-oxide-semiconductor HEMTs (MOS-HEMTs) threshold voltage is in good agreement with the theoretical value, indicating that Sc2O3 retains a low surface state density on the AlGaN/GaN structures and effectively eliminates the collapse in drain current seen in unpassivated devices. The MOS-HEMTs can be modulated to +6 V of gate voltage. In particular, Sc2O3 is a very promising candidate as a gate dielectric and surface passivant because it is more stable on GaN than is MgO.

Enhanced two dimensional electron gas transport characteristics in Al2O3/AlInN/GaN metal-oxide-semiconductor high-electron-mobility transistors on Si substrate

NASA Astrophysics Data System (ADS)

Freedsman, J. J.; Watanabe, A.; Urayama, Y.; Egawa, T.

2015-09-01

The authors report on Al2O3/Al0.85In0.15N/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor (MOS-HEMT) on Si fabricated by using atomic layer deposited Al2O3 as gate insulator and passivation layer. The MOS-HEMT with the gate length of 2 μm exhibits excellent direct-current (dc) characteristics with a drain current maximum of 1270 mA/mm at a gate bias of 3 V and an off-state breakdown voltage of 180 V for a gate-drain spacing of 4 μm. Also, the 1 μm-gate MOS-HEMT shows good radio-frequency (rf) response such as current gain and maximum oscillation cut-off frequencies of 10 and 34 GHz, respectively. The capacitance-voltage characteristics at 1 MHz revealed significant increase in two-dimensional electron gas (2DEG) density for the MOS-HEMT compared to conventional Schottky barrier HEMTs. Analyses using drain-source conductivity measurements showed improvements in 2DEG transport characteristics for the MOS-HEMT. The enhancements in dc and rf performances of the Al2O3/Al0.85In0.15N/GaN MOS-HEMT are attributed to the improvements in 2DEG characteristics.

Ambipolar transport of silver nanoparticles decorated graphene oxide field effect transistors

NASA Astrophysics Data System (ADS)

Sarkar, Kalyan Jyoti; Sarkar, K.; Pal, B.; Kumar, Aparabal; Das, Anish; Banerji, P.

2018-05-01

In this article, we report ambipolar field effect transistor (FET) by using graphene oxide (GO) as a gate dielectric material for silver nanoparticles (AgNPs) decorated GO channel layer. GO was synthesized by Hummers' method. The AgNPs were prepared via photochemical reduction of silver nitrate solution by using monoethanolamine as a reducing agent. Morphological properties of channel layer were characterized by Field Effect Scanning Electron Microscopy (FESEM). Fourier Transform Infrared Spectroscopy (FTIR) was carried out to characterize GO thin film. For device fabrication gold (Au) was deposited as source-drain contact and aluminum (Al) was taken as bottom contact. Electrical measurements were performed by back gate configuration. Ambipolar transport behavior was explained from transfer characteristics. A maximum electron mobiliy of 6.65 cm2/Vs and a hole mobility of 2.46 cm2/Vs were extracted from the transfer characteristics. These results suggest that GO is a potential candidate as a gate dielectric material for thin film transistor applications and also provides new insights in GO based research.

Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chun, Minkyu; Um, Jae Gwang; Park, Min Sang

We report the abnormal behavior of the threshold voltage (V{sub TH}) shift under positive bias Temperature stress (PBTS) and negative bias temperature stress (NBTS) at top/bottom gate in dual gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). It is found that the PBTS at top gate shows negative transfer shift and NBTS shows positive transfer shift for both top and bottom gate sweep. The shift of bottom/top gate sweep is dominated by top gate bias (V{sub TG}), while bottom gate bias (V{sub BG}) is less effect than V{sub TG}. The X-ray photoelectron spectroscopy (XPS) depth profile provides the evidence of Inmore » metal diffusion to the top SiO{sub 2}/a-IGZO and also the existence of large amount of In{sup +} under positive top gate bias around top interfaces, thus negative transfer shift is observed. On the other hand, the formation of OH{sup −} at top interfaces under the stress of negative top gate bias shows negative transfer shift. The domination of V{sub TG} both on bottom/top gate sweep after PBTS/NBTS is obviously occurred due to thin active layer.« less

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium-gallium-zinc oxide gate stack.

PubMed

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-20

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium-gallium-zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>10 4 ). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium–gallium–zinc oxide gate stack

NASA Astrophysics Data System (ADS)

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-01

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium–gallium–zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>104). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vanheusden, K.; Warren, W.L.; Devine, R.A.B.

It is shown how mobile H{sup +} ions can be generated thermally inside the oxide layer of Si/SiO{sub 2}/Si structures. The technique involves only standard silicon processing steps: the nonvolatile field effect transistor (NVFET) is based on a standard MOSFET with thermally grown SiO{sub 2} capped with a poly-silicon layer. The capped thermal oxide receives an anneal at {approximately}1100 C that enables the incorporation of the mobile protons into the gate oxide. The introduction of the protons is achieved by a subsequent 500-800 C anneal in a hydrogen-containing ambient, such as forming gas (N{sub 2}:H{sub 2} 95:5). The mobile protonsmore » are stable and entrapped inside the oxide layer, and unlike alkali ions, their space-charge distribution can be controlled and rapidly rearranged at room temperature by an applied electric field. Using this principle, a standard MOS transistor can be converted into a nonvolatile memory transistor that can be switched between normally on and normally off. Switching speed, retention, endurance, and radiation tolerance data are presented showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as the floating gate technologies (e.g. Flash memory).« less

INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Quantum-Mechanical Study on Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Hu, Guang-Xi; Wang, Ling-Li; Liu, Ran; Tang, Ting-Ao; Qiu, Zhi-Jun

2010-10-01

As the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) scales into the nanometer regime, quantum mechanical effects are becoming more and more significant. In this work, a model for the surrounding-gate (SG) nMOSFET is developed. The Schrödinger equation is solved analytically. Some of the solutions are verified via results obtained from simulations. It is found that the percentage of the electrons with lighter conductivity mass increases as the silicon body radius decreases, or as the gate voltage reduces, or as the temperature decreases. The centroid of inversion-layer is driven away from the silicon-oxide interface towards the silicon body, therefore the carriers will suffer less scattering from the interface and the electrons effective mobility of the SG nMOSFETs will be enhanced.

Designing 4H-SiC P-shielding trench gate MOSFET to optimize on-off electrical characteristics

NASA Astrophysics Data System (ADS)

Kyoung, Sinsu; Hong, Young-sung; Lee, Myung-hwan; Nam, Tae-jin

2018-02-01

In order to enhance specific on-resistance (Ron,sp), the trench gate structure was also introduced into 4H-SiC MOSFET as Si MOSFET. But the 4H-SiC trench gate has worse off-state characteristics than the Si trench gate due to the incomplete gate oxidation process (Šimonka et al., 2017). In order to overcome this problem, P-shielding trench gate MOSFET (TMOS) was proposed and researched in previous studies. But P-shielding has to be designed with minimum design rule in order to protect gate oxide effectively. P-shielding TMOS also has the drawback of on-state characteristics degradation corresponding to off state improvement for minimum design rule. Therefore optimized design is needed to satisfy both on and off characteristics. In this paper, the design parameters were analyzed and optimized so that the 4H-SiC P-shielding TMOS satisfies both on and off characteristics. Design limitations were proposed such that P-shielding is able to defend the gate oxide. The P-shielding layer should have the proper junction depth and concentration to defend the electric field to gate oxide during the off-state. However, overmuch P-shielding junction depth disturbs the on-state current flow, a problem which can be solved by increasing the trench depth. As trench depth increases, however, the breakdown voltage decreases. Therefore, trench depth should be designed with due consideration for on-off characteristics. For this, design conditions and modeling were proposed which allow P-shielding to operate without degradation of on-state characteristics. Based on this proposed model, the 1200 V 4H-SiC P-shielding trench gate MOSFET was designed and optimized.

Effect of active-layer composition and structure on device performance of coplanar top-gate amorphous oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Yue, Lan; Meng, Fanxin; Chen, Jiarong

2018-01-01

The thin-film transistors (TFTs) with amorphous aluminum-indium-zinc-oxide (a-AIZO) active layer were prepared by dip coating method. The dependence of properties of TFTs on the active-layer composition and structure was investigated. The results indicate that Al atoms acted as a carrier suppressor in IZO films. Meanwhile, it was found that the on/off current ratio (I on/off) of TFT was improved by embedding a high-resistivity AIZO layer between the low-resistivity AIZO layer and gate insulator. The improvement in I on/off was attributed to the decrease in off-state current of double-active-layer TFT due to an increase in the active-layer resistance and the contact resistance between active layer and source/drain electrode. Moreover, on-state current and threshold voltage (V th) can be mainly controlled through thickness and Al content of the low-resistivity AIZO layer. In addition, the saturation mobility (μ sat) of TFTs was improved with reducing the size of channel width or/and length, which was attributed to the decrease in trap states in the semiconductor and at the semiconductor/gate-insulator interface with the smaller channel width or/and shorter channel length. Thus, we can demonstrate excellent TFTs via the design of active-layer composition and structure by utilizing a low cost solution-processed method. The resulting TFT, operating in enhancement mode, has a high μ sat of 14.16 cm2 V-1 s-1, a small SS of 0.40 V/decade, a close-to-zero V th of 0.50 V, and I on/off of more than 105.

Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

PubMed Central

Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

2016-01-01

The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer. PMID:26861833

Nanogranular SiO2 proton gated silicon layer transistor mimicking biological synapses

NASA Astrophysics Data System (ADS)

Liu, M. J.; Huang, G. S.; Feng, P.; Guo, Q. L.; Shao, F.; Tian, Z. A.; Li, G. J.; Wan, Q.; Mei, Y. F.

2016-06-01

Silicon on insulator (SOI)-based transistors gated by nanogranular SiO2 proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

Lithium ion intercalation in thin crystals of hexagonal TaSe2 gated by a polymer electrolyte

NASA Astrophysics Data System (ADS)

Wu, Yueshen; Lian, Hailong; He, Jiaming; Liu, Jinyu; Wang, Shun; Xing, Hui; Mao, Zhiqiang; Liu, Ying

2018-01-01

Ionic liquid gating has been used to modify the properties of layered transition metal dichalcogenides (TMDCs), including two-dimensional (2D) crystals of TMDCs used extensively recently in the device work, which has led to observations of properties not seen in the bulk. The main effect comes from the electrostatic gating due to the strong electric field at the interface. In addition, ionic liquid gating also leads to ion intercalation when the ion size of the gate electrolyte is small compared to the interlayer spacing of TMDCs. However, the microscopic processes of ion intercalation have rarely been explored in layered TMDCs. Here, we employed a technique combining photolithography device fabrication and electrical transport measurements on the thin crystals of hexagonal TaSe2 using multiple channel devices gated by a polymer electrolyte LiClO4/Polyethylene oxide (PEO). The gate voltage and time dependent source-drain resistances of these thin crystals were used to obtain information on the intercalation process, the effect of ion intercalation, and the correlation between the ion occupation of allowed interstitial sites and the device characteristics. We found a gate voltage controlled modulation of the charge density waves and a scattering rate of charge carriers. Our work suggests that ion intercalation can be a useful tool for layered materials engineering and 2D crystal device design.

Highly scaled equivalent oxide thickness of 0.66 nm for TiN/HfO2/GaSb MOS capacitors by using plasma-enhanced atomic layer deposition

NASA Astrophysics Data System (ADS)

Tsai, Ming-Li; Wang, Shin-Yuan; Chien, Chao-Hsin

2017-08-01

Through in situ hydrogen plasma treatment (HPT) and plasma-enhanced atomic-layer-deposited TiN (PEALD-TiN) layer capping, we successfully fabricated TiN/HfO2/GaSb metal-oxide-semiconductor capacitors with an ultrathin equivalent oxide thickness of 0.66 nm and a low density of states of approximately 2 × 1012 cm-2 eV-1 near the valence band edge. After in situ HPT, a native oxide-free surface was obtained through efficient etching. Moreover, the use of the in situ PEALD-TiN layer precluded high-κ dielectric damage that would have been caused by conventional sputtering, thereby yielding a superior high-κ dielectric and low gate leakage current.

Improving pH sensitivity by field-induced charge regulation in flexible biopolymer electrolyte gated oxide transistors

NASA Astrophysics Data System (ADS)

Liu, Ning; Gan, Lu; Liu, Yu; Gui, Weijun; Li, Wei; Zhang, Xiaohang

2017-10-01

Electrical manipulation of charged ions in electrolyte-gated transistors is crucial for enhancing the electric-double-layer (EDL) gating effect, thereby improving their sensing abilities. Here, indium-zinc-oxide (IZO) based thin-film-transistors (TFTs) are fabricated on flexible plastic substrate. Acid doped chitosan-based biopolymer electrolyte is used as the gate dielectric, exhibiting an extremely high EDL capacitance. By regulating the dynamic EDL charging process with special gate potential profiles, the EDL gating effect of the chitosan-gated TFT is enhanced, and then resulting in higher pH sensitivities. An extremely high sensitivity of ∼57.8 mV/pH close to Nernst limit is achieved when the gate bias of the TFT sensor sweeps at a rate of 10 mV/s. Additionally, an enhanced sensitivity of 2630% in terms of current variation with pH range from 11 to 3 is realized when the device is operated in the ion depletion mode with a negative gate bias of -0.7 V. Robust ionic modulation is demonstrated in such chitosan-gated sensors. Efficiently driving the charged ions in the chitosan-gated IZO-TFT provides a new route for ultrasensitive, low voltage, and low-cost biochemical sensing technologies.

Naphthalenetetracarboxylic diimide layer-based transistors with nanometer oxide and side chain dielectrics operating below one volt.

PubMed

Jung, Byung Jun; Martinez Hardigree, Josue F; Dhar, Bal Mukund; Dawidczyk, Thomas J; Sun, Jia; See, Kevin Cua; Katz, Howard E

2011-04-26

We designed a new naphthalenetetracarboxylic diimide (NTCDI) semiconductor molecule with long fluoroalkylbenzyl side chains. The side chains, 1.2 nm long, not only aid in self-assembly and kinetically stabilize injected electrons but also act as part of the gate dielectric in field-effect transistors. On Si substrates coated only with the 2 nm thick native oxide, NTCDI semiconductor films were deposited with thicknesses from 17 to 120 nm. Top contact Au electrodes were deposited as sources and drains. The devices showed good transistor characteristics in air with 0.1-1 μA of drain current at 0.5 V of V(G) and V(DS) and W/L of 10-20, even though channel width (250 μm) is over 1000 times the distance (20 nm) between gate and drain electrodes. The extracted capacitance-times-mobility product, an expression of the sheet transconductance, can exceed 100 nS V(-1), 2 orders of magnitude higher than typical organic transistors. The vertical low-frequency capacitance with gate voltage applied in the accumulation regime reached as high as 650 nF/cm(2), matching the harmonic sum of capacitances of the native oxide and one side chain and indicating that some gate-induced carriers in such devices are distributed among all of the NTCDI core layers, although the preponderance of the carriers are still near the gate electrode. Besides demonstrating and analyzing thickness-dependent NTCDI-based transistor behavior, we also showed <1 V detection of dinitrotoluene vapor by such transistors.

Anomalous positive flatband voltage shifts in metal gate stacks containing rare-earth oxide capping layers

NASA Astrophysics Data System (ADS)

Caraveo-Frescas, J. A.; Hedhili, M. N.; Wang, H.; Schwingenschlögl, U.; Alshareef, H. N.

2012-03-01

It is shown that the well-known negative flatband voltage (VFB) shift, induced by rare-earth oxide capping in metal gate stacks, can be completely reversed in the absence of the silicon overlayer. Using TaN metal gates and Gd2O3-doped dielectric, we measure a ˜350 mV negative shift with the Si overlayer present and a ˜110 mV positive shift with the Si overlayer removed. This effect is correlated to a positive change in the average electrostatic potential at the TaN/dielectric interface which originates from an interfacial dipole. The dipole is created by the replacement of interfacial oxygen atoms in the HfO2 lattice with nitrogen atoms from TaN.

Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tari, Alireza, E-mail: atari@uwaterloo.ca; Lee, Czang-Ho; Wong, William S.

Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer intomore » the IGZO and resulted in higher resistivity films.« less

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer

PubMed Central

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J.

2016-01-01

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack. PMID:27279454

Reliability Characterization of Digital Microcircuits - Investigation of an In-Process Oxide Reliability Screening Method

DTIC Science & Technology

1993-04-01

CLASSIFICATION 18. SECURITY CLASSIFICATION 19. SECURIlY CLASSIFICATION 20. UMITATION OF ABSTRACT OF REPORT OF THIS PAGE OF ABSTRACT UNCLASSIFIED UNCLASSIFIED...with the silicon underneath, growing a thin nitride layer. This layer of Si 3 N 4 , if not completely removed, will retard oxidation in the area...C. Shatas, K. C. Saraswat and J. D. Meindl, "Interfacial and Breakdown Characteristics of MOS Devices with Rapidly Grown Ultrathin SiO Gate

Pseudo-diode based on protonic/electronic hybrid oxide transistor

NASA Astrophysics Data System (ADS)

Fu, Yang Ming; Liu, Yang Hui; Zhu, Li Qiang; Xiao, Hui; Song, An Ran

2018-01-01

Current rectification behavior has been proved to be essential in modern electronics. Here, a pseudo-diode is proposed based on protonic/electronic hybrid indium-gallium-zinc oxide electric-double-layer (EDL) transistor. The oxide EDL transistors are fabricated by using phosphorous silicate glass (PSG) based proton conducting electrolyte as gate dielectric. A diode operation mode is established on the transistor, originating from field configurable proton fluxes within the PSG electrolyte. Current rectification ratios have been modulated to values ranged between ˜4 and ˜50 000 with gate electrode biased at voltages ranged between -0.7 V and 0.1 V. Interestingly, the proposed pseudo-diode also exhibits field reconfigurable threshold voltages. When the gate is biased at -0.5 V and 0.3 V, threshold voltages are set to ˜-1.3 V and -0.55 V, respectively. The proposed pseudo-diode may find potential applications in brain-inspired platforms and low-power portable systems.

All-Aluminum Thin Film Transistor Fabrication at Room Temperature.

PubMed

Yao, Rihui; Zheng, Zeke; Zeng, Yong; Liu, Xianzhe; Ning, Honglong; Hu, Shiben; Tao, Ruiqiang; Chen, Jianqiu; Cai, Wei; Xu, Miao; Wang, Lei; Lan, Linfeng; Peng, Junbiao

2017-02-23

Bottom-gate all-aluminum thin film transistors with multi conductor/insulator nanometer heterojunction were investigated in this article. Alumina (Al₂O₃) insulating layer was deposited on the surface of aluminum doping zinc oxide (AZO) conductive layer, as one AZO/Al₂O₃ heterojunction unit. The measurements of transmittance electronic microscopy (TEM) and X-ray reflectivity (XRR) revealed the smooth interfaces between ~2.2-nm-thick Al₂O₃ layers and ~2.7-nm-thick AZO layers. The devices were entirely composited by aluminiferous materials, that is, their gate and source/drain electrodes were respectively fabricated by aluminum neodymium alloy (Al:Nd) and pure Al, with Al₂O₃/AZO multilayered channel and AlO x :Nd gate dielectric layer. As a result, the all-aluminum TFT with two Al₂O₃/AZO heterojunction units exhibited a mobility of 2.47 cm²/V·s and an I on / I off ratio of 10⁶. All processes were carried out at room temperature, which created new possibilities for green displays industry by allowing for the devices fabricated on plastic-like substrates or papers, mainly using no toxic/rare materials.

Nanoscale Multigate TiN Metal Nanocrystal Memory Using High-k Blocking Dielectric and High-Work-Function Gate Electrode Integrated on Silcon-on-Insulator Substrate

NASA Astrophysics Data System (ADS)

Lu, Chi-Pei; Luo, Cheng-Kei; Tsui, Bing-Yue; Lin, Cha-Hsin; Tzeng, Pei-Jer; Wang, Ching-Chiun; Tsai, Ming-Jinn

2009-04-01

In this study, a charge-trapping-layer-engineered nanoscale n-channel trigate TiN nanocrystal nonvolatile memory was successfully fabricated on silicon-on-insulator (SOI) wafer. An Al2O3 high-k blocking dielectric layer and a P+ polycrystalline silicon gate electrode were used to obtain low operation voltage and suppress the back-side injection effect, respectively. TiN nanocrystals were formed by annealing TiN/Al2O3 nanolaminates deposited by an atomic layer deposition system. The memory characteristics of various samples with different TiN wetting layer thicknesses, post-deposition annealing times, and blocking oxide thicknesses were also investigated. The sample with a thicker wetting layer exhibited a much larger memory window than other samples owing to its larger nanocrystal size. Good retention with a mere 12% charge loss for up to 10 years and high endurance were also obtained. Furthermore, gate disturbance and read disturbance were measured with very small charge migrations after a 103 s stressing bias.

Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for AdvancedCMOS Devices

PubMed Central

Suzuki, Masamichi

2012-01-01

A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3) high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT) of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al) atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process. PMID:28817057

Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure

PubMed Central

Khan, Z. N.; Ahmed, S.; Ali, M.

2016-01-01

Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application. PMID:27571412

Thin Film Complementary Metal Oxide Semiconductor (CMOS) Device Using a Single-Step Deposition of the Channel Layer

PubMed Central

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wang, Zhenwei; Hedhili, M. N.; Wang, Q. X.; Alshareef, H. N.

2014-01-01

We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n- and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350°C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications. PMID:24728223

Optimization of a Solution-Processed SiO2 Gate Insulator by Plasma Treatment for Zinc Oxide Thin Film Transistors.

PubMed

Jeong, Yesul; Pearson, Christopher; Kim, Hyun-Gwan; Park, Man-Young; Kim, Hongdoo; Do, Lee-Mi; Petty, Michael C

2016-01-27

We report on the optimization of the plasma treatment conditions for a solution-processed silicon dioxide gate insulator for application in zinc oxide thin film transistors (TFTs). The SiO2 layer was formed by spin coating a perhydropolysilazane (PHPS) precursor. This thin film was subsequently thermally annealed, followed by exposure to an oxygen plasma, to form an insulating (leakage current density of ∼10(-7) A/cm(2)) SiO2 layer. Optimized ZnO TFTs (40 W plasma treatment of the gate insulator for 10 s) possessed a carrier mobility of 3.2 cm(2)/(V s), an on/off ratio of ∼10(7), a threshold voltage of -1.3 V, and a subthreshold swing of 0.2 V/decade. In addition, long-term exposure (150 min) of the pre-annealed PHPS to the oxygen plasma enabled the maximum processing temperature to be reduced from 180 to 150 °C. The resulting ZnO TFT exhibited a carrier mobility of 1.3 cm(2)/(V s) and on/off ratio of ∼10(7).

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Cimang, E-mail: cimang@adam.t.u-tokyo.ac.jp; Lee, Choong Hyun; Nishimura, Tomonori

We investigated yttrium scandate (YScO{sub 3}) as an alternative high-permittivity (k) dielectric thin film for Ge gate stack formation. Significant enhancement of k-value is reported in YScO{sub 3} comparing to both of its binary compounds, Y{sub 2}O{sub 3} and Sc{sub 2}O{sub 3}, without any cost of interface properties. It suggests a feasible approach to a design of promising high-k dielectrics for Ge gate stack, namely, the formation of high-k ternary oxide out of two medium-k binary oxides. Aggressive scaling of equivalent oxide thickness (EOT) with promising interface properties is presented by using YScO{sub 3} as high-k dielectric and yttrium-doped GeO{submore » 2} (Y-GeO{sub 2}) as interfacial layer, for a demonstration of high-k gate stack on Ge. In addition, we demonstrate Ge n-MOSFET performance showing the peak electron mobility over 1000 cm{sup 2}/V s in sub-nm EOT region by YScO{sub 3}/Y-GeO{sub 2}/Ge gate stack.« less

Reduced electron back-injection in Al2O3/AlOx/Al2O3/graphene charge-trap memory devices

NASA Astrophysics Data System (ADS)

Lee, Sejoon; Song, Emil B.; Min Kim, Sung; Lee, Youngmin; Seo, David H.; Seo, Sunae; Wang, Kang L.

2012-12-01

A graphene charge-trap memory is devised using a single-layer graphene channel with an Al2O3/AlOx/Al2O3 oxide stack, where the ion-bombarded AlOx layer is intentionally added to create an abundance of charge-trap sites. The low dielectric constant of AlOx compared to Al2O3 reduces the potential drop in the control oxide Al2O3 and suppresses the electron back-injection from the gate to the charge-storage layer, allowing the memory window of the device to be further extended. This shows that the usage of a lower dielectric constant in the charge-storage layer compared to that of the control oxide layer improves the memory performance for graphene charge-trap memories.

Leakage current conduction in metal gate junctionless nanowire transistors

NASA Astrophysics Data System (ADS)

Oproglidis, T. A.; Karatsori, T. A.; Barraud, S.; Ghibaudo, G.; Dimitriadis, C. A.

2017-05-01

In this paper, the experimental off-state drain leakage current behavior is systematically explored in n- and p-channel junctionless nanowire transistors with HfSiON/TiN/p+-polysilicon gate stack. The analysis of the drain leakage current is based on experimental data of the gate leakage current. It has been shown that the off-state drain leakage current in n-channel devices is negligible, whereas in p-channel devices it is significant and dramatically increases with drain voltage. The overall results indicate that the off-state drain leakage current in p-channel devices is mainly due to trap-assisted Fowler-Nordheim tunneling of electrons through the gate oxide of electrons from the metal gate to the silicon layer near the drain region.

Response Of A MOSFET To A Cosmic Ray

NASA Technical Reports Server (NTRS)

Benumof, Reuben; Zoutendyk, John A.

1988-01-01

Theoretical paper discusses response of enhancement-mode metal oxide/semiconductor field-effect transistor to cosmic-ray ion that passes perpendicularly through gate-oxide layers. Even if ion causes no permanent damage, temporary increase of electrical conductivity along track of ion large enough and long enough to cause change in logic state in logic circuit containing MOSFET.

Highly stable organic field-effect transistors with engineered gate dielectrics (Conference Presentation)

NASA Astrophysics Data System (ADS)

Kippelen, Bernard; Wang, Cheng-Yin; Fuentes-Hernandez, Canek; Yun, Minseong; Singh, Ankit K.; Dindar, Amir; Choi, Sangmoo; Graham, Samuel

2016-11-01

Organic field-effect transistors (OFETs) have the potential to lead to low-cost flexible displays, wearable electronics, and sensors. While recent efforts have focused greatly on improving the maximum charge mobility that can be achieved in such devices, studies about the stability and reliability of such high performance devices are relatively scarce. In this talk, we will discuss the results of recent studies aimed at improving the stability of OFETs under operation and their shelf lifetime. In particular, we will focus on device architectures where the gate dielectric is engineered to act simultaneously as an environmental barrier layer. In the past, our group had demonstrated solution-processed top-gate OFETs using TIPS-pentacene and PTAA blends as a semiconductor layer with a bilayer gate dielectric layer of CYTOP/Al2O3, where the oxide layer was fabricated by atomic layer deposition, ALD. Such devices displayed high operational stability with little degradation after 20,000 on/off scan cycles or continuous operation (24 h), and high environmental stability when kept in air for more than 2 years, with unchanged carrier mobility. Using this stable device geometry, simple circuits and sensors operating in aqueous conditions were demonstrated. However, the Al2O3 layer was found to degrade due to corrosion under prolonged exposure in aqueous solutions. In this talk, we will report on the use of a nanolaminate (NL) composed of Al2O3 and HfO2 by ALD to replace the Al2O3 single layer in the bilayer gate dielectric use in top-gate OFETs. Such OFETs were found to operate under harsh condition such as immersion in water at 95 °C. This work was funded by the Department of Energy (DOE) through the Bay Area Photovoltaics Consortium (BAPVC) under Award Number DE-EE0004946.

Remote N2 plasma treatment to deposit ultrathin high-k dielectric as tunneling contact layer for single-layer MoS2 MOSFET

NASA Astrophysics Data System (ADS)

Qian, Qingkai; Zhang, Zhaofu; Hua, Mengyuan; Wei, Jin; Lei, Jiacheng; Chen, Kevin J.

2017-12-01

Remote N2 plasma treatment is explored as a surface functionalization technique to deposit ultrathin high-k dielectric on single-layer MoS2. The ultrathin dielectric is used as a tunneling contact layer, which also serves as an interfacial layer below the gate region for fabricating top-gate MoS2 metal-oxide-semiconductor field-effect transistors (MOSFETs). The fabricated devices exhibited small hysteresis and mobility as high as 14 cm2·V-1·s-1. The contact resistance was significantly reduced, which resulted in the increase of drain current from 20 to 56 µA/µm. The contact resistance reduction can be attributed to the alleviated metal-MoS2 interface reaction and the preserved conductivity of MoS2 below the source/drain metal contact.

Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

PubMed

Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

2015-03-04

Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

High-Resolution Inkjet-Printed Oxide Thin-Film Transistors with a Self-Aligned Fine Channel Bank Structure.

PubMed

Zhang, Qing; Shao, Shuangshuang; Chen, Zheng; Pecunia, Vincenzo; Xia, Kai; Zhao, Jianwen; Cui, Zheng

2018-05-09

A self-aligned inkjet printing process has been developed to construct small channel metal oxide (a-IGZO) thin-film transistors (TFTs) with independent bottom gates on transparent glass substrates. Poly(methylsilsesquioxane) was used to pattern hydrophobic banks on the transparent substrate instead of commonly used self-assembled octadecyltrichlorosilane. Photolithographic exposure from backside using bottom-gate electrodes as mask formed hydrophilic channel areas for the TFTs. IGZO ink was selectively deposited by an inkjet printer in the hydrophilic channel region and confined by the hydrophobic bank structure, resulting in the precise deposition of semiconductor layers just above the gate electrodes. Inkjet-printed IGZO TFTs with independent gate electrodes of 10 μm width have been demonstrated, avoiding completely printed channel beyond the broad of the gate electrodes. The TFTs showed on/off ratios of 10 8 , maximum mobility of 3.3 cm 2 V -1 s -1 , negligible hysteresis, and good uniformity. This method is conductive to minimizing the area of printed TFTs so as to the development of high-resolution printing displays.

Amorphous indium-gallium-zinc-oxide thin-film transistors using organic-inorganic hybrid films deposited by low-temperature plasma-enhanced chemical vapor deposition for all dielectric layers

NASA Astrophysics Data System (ADS)

Hsu, Chao-Jui; Chang, Ching-Hsiang; Chang, Kuei-Ming; Wu, Chung-Chih

2017-01-01

We investigated the deposition of high-performance organic-inorganic hybrid dielectric films by low-temperature (close to room temperature) inductively coupled plasma chemical vapor deposition (ICP-CVD) with hexamethyldisiloxane (HMDSO)/O2 precursor gas. The hybrid films exhibited low leakage currents and high breakdown fields, suitable for thin-film transistor (TFT) applications. They were successfully integrated into the gate insulator, the etch-stop layer, and the passivation layer for bottom-gate staggered amorphous In-Ga-Zn-O (a-IGZO) TFTs having the etch-stop configuration. With the double-active-layer configuration having a buffer a-IGZO back-channel layer grown in oxygen-rich atmosphere for better immunity against plasma damage, the etch-stop-type bottom-gate staggered a-IGZO TFTs with good TFT characteristics were successfully demonstrated. The TFTs showed good field-effect mobility (μFE), threshold voltage (V th), subthreshold swing (SS), and on/off ratio (I on/off) of 7.5 cm2 V-1 s-1, 2.38 V, 0.38 V/decade, and 2.2 × 108, respectively, manifesting their usefulness for a-IGZO TFTs.

All-Aluminum Thin Film Transistor Fabrication at Room Temperature

PubMed Central

Yao, Rihui; Zheng, Zeke; Zeng, Yong; Liu, Xianzhe; Ning, Honglong; Hu, Shiben; Tao, Ruiqiang; Chen, Jianqiu; Cai, Wei; Xu, Miao; Wang, Lei; Lan, Linfeng; Peng, Junbiao

2017-01-01

Bottom-gate all-aluminum thin film transistors with multi conductor/insulator nanometer heterojunction were investigated in this article. Alumina (Al2O3) insulating layer was deposited on the surface of aluminum doping zinc oxide (AZO) conductive layer, as one AZO/Al2O3 heterojunction unit. The measurements of transmittance electronic microscopy (TEM) and X-ray reflectivity (XRR) revealed the smooth interfaces between ~2.2-nm-thick Al2O3 layers and ~2.7-nm-thick AZO layers. The devices were entirely composited by aluminiferous materials, that is, their gate and source/drain electrodes were respectively fabricated by aluminum neodymium alloy (Al:Nd) and pure Al, with Al2O3/AZO multilayered channel and AlOx:Nd gate dielectric layer. As a result, the all-aluminum TFT with two Al2O3/AZO heterojunction units exhibited a mobility of 2.47 cm2/V·s and an Ion/Ioff ratio of 106. All processes were carried out at room temperature, which created new possibilities for green displays industry by allowing for the devices fabricated on plastic-like substrates or papers, mainly using no toxic/rare materials. PMID:28772579

Improved interfacial and electrical properties of GaAs metal-oxide-semiconductor capacitors with HfTiON as gate dielectric and TaON as passivation interlayer

NASA Astrophysics Data System (ADS)

Wang, L. S.; Xu, J. P.; Zhu, S. Y.; Huang, Y.; Lai, P. T.

2013-08-01

The interfacial and electrical properties of sputtered HfTiON on sulfur-passivated GaAs with or without TaON as interfacial passivation layer (IPL) are investigated. Experimental results show that the GaAs metal-oxide-semiconductor capacitor with HfTiON/TaON stacked gate dielectric annealed at 600 °C exhibits low interface-state density (1.0 × 1012 cm-2 eV-1), small gate leakage current (7.3 × 10-5 A cm-2 at Vg = Vfb + 1 V), small capacitance equivalent thickness (1.65 nm), and large equivalent dielectric constant (26.2). The involved mechanisms lie in the fact that the TaON IPL can effectively block the diffusions of Hf, Ti, and O towards GaAs surface and suppress the formation of interfacial As-As bonds, Ga-/As-oxides, thus unpinning the Femi level at the TaON/GaAs interface and improving the interface quality and electrical properties of the device.

Technologies for suppressing charge-traps in novel p-channel Field-MOSFET with thick gate oxide

NASA Astrophysics Data System (ADS)

Miyoshi, Tomoyuki; Oshima, Takayuki; Noguchi, Junji

2015-05-01

High voltage laterally diffused MOS (LDMOS) FETs are widely used in analog applications. A Field-MOSFET with a thick gate oxide is one of the best ways of achieving a simpler design and smaller circuit footprint for high-voltage analog circuits. This paper focuses on an approach to improving the reliability of p-channel Field-MOSFETs. By introducing a fluorine implantation process and terminating fluorine at the LOCOS bird’s beak, the gate oxide breakdown voltage could be raised to 350 V at a high-slew rate and the negative bias temperature instability (NBTI) shift could be kept to within 15% over a product’s lifetime. By controlling the amount of charge in the insulating layer through improving the interlayer dielectric (ILD) deposition processes, a higher BVDSS of 370 V and 10-year tolerability of 300 V were obtained with an assisted reduced surface electric field (RESURF) effect. These techniques can supply an efficient solution for ensuring reliable high-performance applications.

An Ultrathin Single Crystalline Relaxor Ferroelectric Integrated on a High Mobility Semiconductor.

PubMed

Moghadam, Reza M; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar; Grimley, Everett D; Bowden, Mark; Ong, Phuong-Vu; Chambers, Scott A; Lebeau, James M; Hong, Xia; Sushko, Peter V; Ngai, Joseph H

2017-10-11

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, the integration of gate materials that enable nonvolatile or hysteretic functionality in field-effect transistors could lead to device technologies that consume less power or allow for novel modalities in computing. Here we present electrical characterization of ultrathin single crystalline SrZr x Ti 1-x O 3 (x = 0.7) films epitaxially grown on a high mobility semiconductor, Ge. Epitaxial films of SrZr x Ti 1-x O 3 exhibit relaxor behavior, characterized by a hysteretic polarization that can modulate the surface potential of Ge. We find that gate layers as thin as 5 nm corresponding to an equivalent-oxide thickness of just 1.0 nm exhibit a ∼2 V hysteretic window in the capacitance-voltage characteristics. The development of hysteretic metal-oxide-semiconductor capacitors with nanoscale gate thicknesses opens new vistas for nanoelectronic devices.

Asymmetrical field emitter

DOEpatents

Fleming, J.G.; Smith, B.K.

1995-10-10

A method is disclosed for providing a field emitter with an asymmetrical emitter structure having a very sharp tip in close proximity to its gate. One preferred embodiment of the present invention includes an asymmetrical emitter and a gate. The emitter having a tip and a side is coupled to a substrate. The gate is connected to a step in the substrate. The step has a top surface and a side wall that is substantially parallel to the side of the emitter. The tip of the emitter is in close proximity to the gate. The emitter is at an emitter potential, and the gate is at a gate potential such that with the two potentials at appropriate values, electrons are emitted from the emitter. In one embodiment, the gate is separated from the emitter by an oxide layer, and the emitter is etched anisotropically to form its tip and its asymmetrical structure. 17 figs.

Extended-gate-type IGZO electric-double-layer TFT immunosensor with high sensitivity and low operation voltage

NASA Astrophysics Data System (ADS)

Liang, Lingyan; Zhang, Shengnan; Wu, Weihua; Zhu, Liqiang; Xiao, Hui; Liu, Yanghui; Zhang, Hongliang; Javaid, Kashif; Cao, Hongtao

2016-10-01

An immunosensor is proposed based on the indium-gallium-zinc-oxide (IGZO) electric-double-layer thin-film transistor (EDL TFT) with a separating extended gate. The IGZO EDL TFT has a field-effect mobility of 24.5 cm2 V-1 s-1 and an operation voltage less than 1.5 V. The sensors exhibit the linear current response to label-free target immune molecule in the concentrations ranging from 1.6 to 368 × 10-15 g/ml with a detection limit of 1.6 × 10-15 g/ml (0.01 fM) under an ultralow operation voltage of 0.5 V. The IGZO TFT component demonstrates a consecutive assay stability and recyclability due to the unique structure with the separating extended gate. With the excellent electrical properties and the potential for plug-in-card-type multifunctional sensing, extended-gate-type IGZO EDL TFTs can be promising candidates for the development of a label-free biosensor for public health applications.

Atomic Layer Deposition of HfO2 and Si Nitride on Ge Substrates

NASA Astrophysics Data System (ADS)

Zhu, Shiyang; Nakajima, Anri

2007-12-01

Hafnium oxide (HfO2) thin films were deposited on Ge substrates at 300 °C using atomic layer deposition (ALD) with tetrakis(diethylamino)hafnium (termed as TDEAH) as a precursor and water as an oxidant. The deposition rate was estimated to be 0.09 nm/cycle and the deposited HfO2 films have a smooth surface and an almost stoichiometric composition, indicating that the growth follows a layer-by-layer kinetics, similarly to that on Si substrates. Si nitride thin films were also deposited on Ge by ALD using SiCl4 as a precursor and NH3 as an oxidant. Si nitride has a smaller deposition rate of about 0.055 nm/cycle and a larger gate leakage current than HfO2 deposited on Ge by ALD.

Real-time detection of mercury ions in water using a reduced graphene oxide/DNA field-effect transistor with assistance of a passivation layer

DOE PAGES

Chang, Jingbo; Zhou, Guihua; Gao, Xianfeng; ...

2015-08-01

Field-effect transistor (FET) sensors based on reduced graphene oxide (rGO) for detecting chemical species provide a number of distinct advantages, such as ultrasensitivity, label-free, and real-time response. However, without a passivation layer, channel materials directly exposed to an ionic solution could generate multiple signals from ionic conduction through the solution droplet, doping effect, and gating effect. Therefore, a method that provides a passivation layer on the surface of rGO without degrading device performance will significantly improve device sensitivity, in which the conductivity changes solely with the gating effect. In this work, we report rGO FET sensor devices with Hg 2+-dependentmore » DNA as a probe and the use of an Al 2O 3 layer to separate analytes from conducting channel materials. The device shows good electronic stability, excellent lower detection limit (1 nM), and high sensitivity for real-time detection of Hg 2+ in an underwater environment. Our work shows that optimization of an rGO FET structure can provide significant performance enhancement and profound fundamental understanding for the sensor mechanism.« less

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2017-06-01

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

Investigation of impact of post-metallization annealing on reliability of 65 nm NOR floating-gate flash memories

NASA Astrophysics Data System (ADS)

Chiu, Shengfen; Xu, Yue; Ji, Xiaoli; Yan, Feng

2016-12-01

This paper investigates the impact of post-metallization annealing (PMA) in pure nitrogen ambient on the reliability of 65 nm NOR-type floating-gate flash memory devices. The experimental results show that, with PMA process, the cycling performance of flash cells, especially for the erasing speed is obviously degraded compared to that without PMA. It is found that the bulk oxide traps and tunnel oxide/Si interface traps are significantly increased with PMA treatment. The water/moisture residues left in the interlayer dielectric layers diffuse to tunnel oxide during PMA process is considered to be responsible for these traps generation, which further enhances the degradation of erase performance. Skipping PMA treatment is proposed to suppress the water diffusion effect on erase performance degradation of flash cells.

Field effect transistor with HfO2/Parylene-C bilayer hybrid gate insulator

NASA Astrophysics Data System (ADS)

Kumar, Neeraj; Kito, Ai; Inoue, Isao

2015-03-01

We have investigated the electric field control of the carrier density and the mobility at the surface of SrTiO3, a well known transition-metal oxide, in a field effect transistor (FET) geometry. We have used a Parylene-C (8 nm)/HfO2 (20 nm) double-layer gate insulator (GI), which can be a potential candidate for a solid state GI for the future Mott FETs. So far, only examples of the Mott FET used liquid electrolyte or ferroelectric oxides for the GI. However, possible electrochemical reaction at the interface causes damage to the surface of the Mott insulator. Thus, an alternative GI has been highly desired. We observed that even an ultra thin Parylene-C layer is effective for keeping the channel surface clean and free from oxygen vacancies. The 8 nm Parylene-C film has a relatively low resistance and consequentially its capacitance does not dominate the total capacitance of the Parylene-C/HfO2 GI. The breakdown gate voltage at 300 K is usually more than 10 V (~ 3.4 MV/cm). At gate voltage of 3 V the carrier density measured by the Hall effect is about 3 ×1013 cm-2, competent to cause the Mott transition. Moreover, the field effect mobility reaches in the range of 10 cm2/Vs indicating the Parylene-C passivated surface is actually very clean.

Electrical and band structural analyses of Ti1-x Al x O y films grown by atomic layer deposition on p-type GaAs

NASA Astrophysics Data System (ADS)

An, Youngseo; Mahata, Chandreswar; Lee, Changmin; Choi, Sungho; Byun, Young-Chul; Kang, Yu-Seon; Lee, Taeyoon; Kim, Jiyoung; Cho, Mann-Ho; Kim, Hyoungsub

2015-10-01

Amorphous Ti1-x Al x O y films in the Ti-oxide-rich regime (x  <  0.5) were deposited on p-type GaAs via atomic layer deposition with titanium isopropoxide, trimethylaluminum, and H2O precursor chemistry. The electrical properties and energy band alignments were examined for the resulting materials with their underlying substrates, and significant frequency dispersion was observed in the accumulation region of the Ti-oxide-rich Ti1-x Al x O y films. Although a further reduction in the frequency dispersion and leakage current (under gate electron injection) could be somewhat achieved through a greater addition of Al-oxide in the Ti1-x Al x O y film, the simultaneous decrease in the dielectric constant proved problematic in finding an optimal composition for application as a gate dielectric on GaAs. The spectroscopic band alignment measurements of the Ti-oxide-rich Ti1-x Al x O y films indicated that the band gaps had a rather slow increase with the addition of Al-oxide, which was primarily compensated for by an increase in the valance band offset, while a nearly-constant conduction band offset with a negative electron barrier height was maintained.

Gate-Induced Interfacial Superconductivity in 1T-SnSe2.

PubMed

Zeng, Junwen; Liu, Erfu; Fu, Yajun; Chen, Zhuoyu; Pan, Chen; Wang, Chenyu; Wang, Miao; Wang, Yaojia; Xu, Kang; Cai, Songhua; Yan, Xingxu; Wang, Yu; Liu, Xiaowei; Wang, Peng; Liang, Shi-Jun; Cui, Yi; Hwang, Harold Y; Yuan, Hongtao; Miao, Feng

2018-02-14

Layered metal chalcogenide materials provide a versatile platform to investigate emergent phenomena and two-dimensional (2D) superconductivity at/near the atomically thin limit. In particular, gate-induced interfacial superconductivity realized by the use of an electric-double-layer transistor (EDLT) has greatly extended the capability to electrically induce superconductivity in oxides, nitrides, and transition metal chalcogenides and enable one to explore new physics, such as the Ising pairing mechanism. Exploiting gate-induced superconductivity in various materials can provide us with additional platforms to understand emergent interfacial superconductivity. Here, we report the discovery of gate-induced 2D superconductivity in layered 1T-SnSe 2 , a typical member of the main-group metal dichalcogenide (MDC) family, using an EDLT gating geometry. A superconducting transition temperature T c ≈ 3.9 K was demonstrated at the EDL interface. The 2D nature of the superconductivity therein was further confirmed based on (1) a 2D Tinkham description of the angle-dependent upper critical field B c2 , (2) the existence of a quantum creep state as well as a large ratio of the coherence length to the thickness of superconductivity. Interestingly, the in-plane B c2 approaching zero temperature was found to be 2-3 times higher than the Pauli limit, which might be related to an electric field-modulated spin-orbit interaction. Such results provide a new perspective to expand the material matrix available for gate-induced 2D superconductivity and the fundamental understanding of interfacial superconductivity.

Demonstration of large field effect in topological insulator films via a high-κ back gate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, C. Y.; Lin, H. Y.; Yang, S. R.

2016-05-16

The spintronics applications long anticipated for topological insulators (TIs) has been hampered due to the presence of high density intrinsic defects in the bulk states. In this work we demonstrate the back-gating effect on TIs by integrating Bi{sub 2}Se{sub 3} films 6–10 quintuple layer (QL) thick with amorphous high-κ oxides of Al{sub 2}O{sub 3} and Y{sub 2}O{sub 3}. Large gating effect of tuning the Fermi level E{sub F} to very close to the band gap was observed, with an applied bias of an order of magnitude smaller than those of the SiO{sub 2} back gate, and the modulation of filmmore » resistance can reach as high as 1200%. The dependence of the gating effect on the TI film thickness was investigated, and ΔN{sub 2D}/ΔV{sub g} varies with TI film thickness as ∼t{sup −0.75}. To enhance the gating effect, a Y{sub 2}O{sub 3} layer thickness 4 nm was inserted into Al{sub 2}O{sub 3} gate stack to increase the total κ value to 13.2. A 1.4 times stronger gating effect is observed, and the increment of induced carrier numbers is in good agreement with additional charges accumulated in the higher κ oxides. Moreover, we have reduced the intrinsic carrier concentration in the TI film by doping Te to Bi{sub 2}Se{sub 3} to form Bi{sub 2}Te{sub x}Se{sub 1−x}. The observation of a mixed state of ambipolar field that both electrons and holes are present indicates that we have tuned the E{sub F} very close to the Dirac Point. These results have demonstrated that our capability of gating TIs with high-κ back gate to pave the way to spin devices of tunable E{sub F} for dissipationless spintronics based on well-established semiconductor technology.« less

Control of Ga-oxide interlayer growth and Ga diffusion in SiO2/GaN stacks for high-quality GaN-based metal-oxide-semiconductor devices with improved gate dielectric reliability

NASA Astrophysics Data System (ADS)

Yamada, Takahiro; Watanabe, Kenta; Nozaki, Mikito; Yamada, Hisashi; Takahashi, Tokio; Shimizu, Mitsuaki; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-01-01

A simple and feasible method for fabricating high-quality and highly reliable GaN-based metal-oxide-semiconductor (MOS) devices was developed. The direct chemical vapor deposition of SiO2 films on GaN substrates forming Ga-oxide interlayers was carried out to fabricate SiO2/GaO x /GaN stacked structures. Although well-behaved hysteresis-free GaN-MOS capacitors with extremely low interface state densities below 1010 cm-2 eV-1 were obtained by postdeposition annealing, Ga diffusion into overlying SiO2 layers severely degraded the dielectric breakdown characteristics. However, this problem was found to be solved by rapid thermal processing, leading to the superior performance of the GaN-MOS devices in terms of interface quality, insulating property, and gate dielectric reliability.

Electrical hysteresis in p-GaN metal-oxide-semiconductor capacitor with atomic-layer-deposited Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Zhang, Kexiong; Liao, Meiyong; Imura, Masataka; Nabatame, Toshihide; Ohi, Akihiko; Sumiya, Masatomo; Koide, Yasuo; Sang, Liwen

2016-12-01

The electrical hysteresis in current-voltage (I-V) and capacitance-voltage characteristics was observed in an atomic-layer-deposited Al2O3/p-GaN metal-oxide-semiconductor capacitor (PMOSCAP). The absolute minimum leakage currents of the PMOSCAP for forward and backward I-V scans occurred not at 0 V but at -4.4 and +4.4 V, respectively. A negative flat-band voltage shift of 5.5 V was acquired with a capacitance step from +4.4 to +6.1 V during the forward scan. Mg surface accumulation on p-GaN was demonstrated to induce an Mg-Ga-Al-O oxidized layer with a trap density on the order of 1013 cm-2. The electrical hysteresis is attributed to the hole trapping and detrapping process in the traps of the Mg-Ga-Al-O layer via the Poole-Frenkel mechanism.

A compact quantum correction model for symmetric double gate metal-oxide-semiconductor field-effect transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cho, Edward Namkyu; Shin, Yong Hyeon; Yun, Ilgu, E-mail: iyun@yonsei.ac.kr

2014-11-07

A compact quantum correction model for a symmetric double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated. The compact quantum correction model is proposed from the concepts of the threshold voltage shift (ΔV{sub TH}{sup QM}) and the gate capacitance (C{sub g}) degradation. First of all, ΔV{sub TH}{sup QM} induced by quantum mechanical (QM) effects is modeled. The C{sub g} degradation is then modeled by introducing the inversion layer centroid. With ΔV{sub TH}{sup QM} and the C{sub g} degradation, the QM effects are implemented in previously reported classical model and a comparison between the proposed quantum correction model and numerical simulationmore » results is presented. Based on the results, the proposed quantum correction model can be applicable to the compact model of DG MOSFET.« less

Nonvolatile MoS2 field effect transistors directly gated by single crystalline epitaxial ferroelectric

NASA Astrophysics Data System (ADS)

Lu, Zhongyuan; Serrao, Claudy; Khan, Asif Islam; You, Long; Wong, Justin C.; Ye, Yu; Zhu, Hanyu; Zhang, Xiang; Salahuddin, Sayeef

2017-07-01

We demonstrate non-volatile, n-type, back-gated, MoS2 transistors, placed directly on an epitaxial grown, single crystalline, PbZr0.2Ti0.8O3 (PZT) ferroelectric. The transistors show decent ON current (19 μA/μm), high on-off ratio (107), and a subthreshold swing of (SS ˜ 92 mV/dec) with a 100 nm thick PZT layer as the back gate oxide. Importantly, the ferroelectric polarization can directly control the channel charge, showing a clear anti-clockwise hysteresis. We have self-consistently confirmed the switching of the ferroelectric and corresponding change in channel current from a direct time-dependent measurement. Our results demonstrate that it is possible to obtain transistor operation directly on polar surfaces, and therefore, it should be possible to integrate 2D electronics with single crystalline functional oxides.

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

PubMed

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

Study Trapped Charge Distribution in P-Channel Silicon-Oxide-Nitride-Oxide-Silicon Memory Device Using Dynamic Programming Scheme

NASA Astrophysics Data System (ADS)

Li, Fu-Hai; Chiu, Yung-Yueh; Lee, Yen-Hui; Chang, Ru-Wei; Yang, Bo-Jun; Sun, Wein-Town; Lee, Eric; Kuo, Chao-Wei; Shirota, Riichiro

2013-04-01

In this study, we precisely investigate the charge distribution in SiN layer by dynamic programming of channel hot hole induced hot electron injection (CHHIHE) in p-channel silicon-oxide-nitride-oxide-silicon (SONOS) memory device. In the dynamic programming scheme, gate voltage is increased as a staircase with fixed step amplitude, which can prohibits the injection of holes in SiN layer. Three-dimensional device simulation is calibrated and is compared with the measured programming characteristics. It is found, for the first time, that the hot electron injection point quickly traverses from drain to source side synchronizing to the expansion of charged area in SiN layer. As a result, the injected charges quickly spread over on the almost whole channel area uniformly during a short programming period, which will afford large tolerance against lateral trapped charge diffusion by baking.

Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs

NASA Astrophysics Data System (ADS)

Dentoni Litta, E.; Hellström, P.-E.; Östling, M.

2015-06-01

High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.

Influence of the charge trap density distribution in a gate insulator on the positive-bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Eungtaek; Kim, Choong-Ki; Lee, Myung Keun

We investigated the positive-bias stress (PBS) instability of thin film transistors (TFTs) composed of different types of first-gate insulators, which serve as a protection layer of the active surface. Two different deposition methods, i.e., the thermal atomic layer deposition (THALD) and plasma-enhanced ALD (PEALD) of Al{sub 2}O{sub 3}, were applied for the deposition of the first GI. When THALD was used to deposit the GI, amorphous indium-gallium-zinc oxide (a-IGZO) TFTs showed superior stability characteristics under PBS. For example, the threshold voltage shift (ΔV{sub th}) was 0 V even after a PBS time (t{sub stress}) of 3000 s under a gate voltage (V{submore » G}) condition of 5 V (with an electrical field of 1.25 MV/cm). On the other hand, when the first GI was deposited by PEALD, the ΔV{sub th} value of a-IGZO TFTs was 0.82 V after undergoing an identical amount of PBS. In order to interpret the disparate ΔV{sub th} values resulting from PBS quantitatively, the average oxide charge trap density (N{sub T}) in the GI and its spatial distribution were investigated through low-frequency noise characterizations. A higher N{sub T} resulted during in the PEALD type GI than in the THALD case. Specifically, the PEALD process on a-IGZO layer surface led to an increasing trend of N{sub T} near the GI/a-IGZO interface compared to bulk GI owing to oxygen plasma damage on the a-IGZO surface.« less

Solution-processed nanoparticle super-float-gated organic field-effect transistor as un-cooled ultraviolet and infrared photon counter.

PubMed

Yuan, Yongbo; Dong, Qingfeng; Yang, Bin; Guo, Fawen; Zhang, Qi; Han, Ming; Huang, Jinsong

2013-01-01

High sensitivity photodetectors in ultraviolet (UV) and infrared (IR) range have broad civilian and military applications. Here we report on an un-cooled solution-processed UV-IR photon counter based on modified organic field-effect transistors. This type of UV detectors have light absorbing zinc oxide nanoparticles (NPs) sandwiched between two gate dielectric layers as a floating gate. The photon-generated charges on the floating gate cause high resistance regions in the transistor channel and tune the source-drain output current. This "super-float-gating" mechanism enables very high sensitivity photodetectors with a minimum detectable ultraviolet light intensity of 2.6 photons/μm(2)s at room temperature as well as photon counting capability. Based on same mechansim, infrared photodetectors with lead sulfide NPs as light absorbing materials have also been demonstrated.

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

NASA Astrophysics Data System (ADS)

Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

2018-06-01

The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

Trilayer TMDC Heterostructures for MOSFETs and Nanobiosensors

NASA Astrophysics Data System (ADS)

Datta, Kanak; Shadman, Abir; Rahman, Ehsanur; Khosru, Quazi D. M.

2017-02-01

Two dimensional materials such as transition metal dichalcogenides (TMDC) and their bi-layer/tri-layer heterostructures have become the focus of intense research and investigation in recent years due to their promising applications in electronics and optoelectronics. In this work, we have explored device level performance of trilayer TMDC heterostructure (MoS2/MX2/MoS2; M = Mo or, W and X = S or, Se) metal oxide semiconductor field effect transistors (MOSFETs) in the quantum ballistic regime. Our simulation shows that device `on' current can be improved by inserting a WS2 monolayer between two MoS2 monolayers. Application of biaxial tensile strain reveals a reduction in drain current which can be attributed to the lowering of carrier effective mass with increased tensile strain. In addition, it is found that gate underlap geometry improves electrostatic device performance by improving sub-threshold swing. However, increase in channel resistance reduces drain current. Besides exploring the prospect of these materials in device performance, novel trilayer TMDC heterostructure double gate field effect transistors (FETs) are proposed for sensing Nano biomolecules as well as for pH sensing. Bottom gate operation ensures these FETs operating beyond Nernst limit of 59 mV/pH. Simulation results found in this work reveal that scaling of bottom gate oxide results in better sensitivity while top oxide scaling exhibits an opposite trend. It is also found that, for identical operating conditions, proposed TMDC FET pH sensors show super-Nernst sensitivity indicating these materials as potential candidates in implementing such sensor. Besides pH sensing, all these materials show high sensitivity in the sub-threshold region as a channel material in nanobiosensor while MoS2/WS2/MoS2 FET shows the least sensitivity among them.

Crystalline ZrTiO{sub 4} gated p-metal–oxide–semiconductor field effect transistors with sub-nm equivalent oxide thickness featuring good electrical characteristics and reliability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Chao-Yi; Hsieh, Ching-Heng; Lee, Ching-Wei

2015-02-02

ZrTiO{sub 4} crystallized in orthorhombic (o-) phase was stacked with an amorphous Yb{sub 2}O{sub 3} interfacial layer as the gate dielectric for Si-based p-MOSFETs. With thermal annealing after gate electrode, the gate stack with equivalent oxide thickness (EOT) of 0.82 nm achieves high dielectric quality by showing a low interface trap density (D{sub it}) of 2.75 × 10{sup 11 }cm{sup −2}eV{sup −1} near the midgap and low oxide traps. Crystallization of ZrTiO{sub 4} and post metal annealing are also proven to introduce very limited amount of metal induced gap states or interfacial dipole. The p-MOSFETs exhibit good sub-threshold swing of 75 mV/dec which is ascribedmore » to the low D{sub it} value and small EOT. Owing to the Y{sub 2}O{sub 3} interfacial layer and smooth interface with Si substrate that, respectively, suppress phonon and surface roughness scattering, the p-MOSFETs also display high hole mobility of 49 cm{sup 2}/V-s at 1 MV/cm. In addition, I{sub on}/I{sub off} ratio larger than 10{sup 6} is also observed. From the reliability evaluation by negative bias temperature instability test, after stressing with an electric field of −10 MV/cm at 85 °C for 1000 s, satisfactory threshold voltage shift of 12 mV and sub-threshold swing degradation of 3% were obtained. With these promising characteristics, the Yb{sub 2}O{sub 3}/o-ZrTiO{sub 4} gate stack holds the great potential for next-generation electronics.« less

Self-Assembled Films of Dendrimers and Metallophthalocyanines as FET-Based Glucose Biosensors

PubMed Central

Vieira, Nirton C.S.; Figueiredo, Alessandra; de Queiroz, Alvaro A.A.; Zucolotto, Valtencir; Guimarães, Francisco E.G.

2011-01-01

Separative extended gate field effect transistor (SEGFET) type devices have been used as an ion sensor or biosensor as an alternative to traditional ion sensitive field effect transistors (ISFETs) due to their robustness, ease of fabrication, low cost and possibility of FET isolation from the chemical environment. The layer-by-layer technique allows the combination of different materials with suitable properties for enzyme immobilization on simple platforms such as the extended gate of SEGFET devices enabling the fabrication of biosensors. Here, glucose biosensors based on dendrimers and metallophthalocyanines (MPcs) in the form of layer-by-layer (LbL) films, assembled on indium tin oxide (ITO) as separative extended gate material, has been produced. NH3+ groups in the dendrimer allow electrostatic interactions or covalent bonds with the enzyme (glucose oxidase). Relevant parameters such as optimum pH, buffer concentration and presence of serum bovine albumin (BSA) in the immobilization process were analyzed. The relationship between the output voltage and glucose concentration shows that upon detection of a specific analyte, the sub-products of the enzymatic reaction change the pH locally, affecting the output signal of the FET transducer. In addition, dendritic layers offer a nanoporous environment, which may be permeable to H+ ions, improving the sensibility as modified electrodes for glucose biosensing. PMID:22163704

Low-temperature sol-gel oxide TFT with a fluoropolymer dielectric to enhance the effective mobility at low operation voltage

NASA Astrophysics Data System (ADS)

Yu, Shang-Yu; Wang, Kuan-Hsun; Zan, Hsiao-Wen; Soppera, Olivier

2017-06-01

In this article, we propose a solution-processed high-performance amorphous indium-zinc oxide (a-IZO) thin-film transistor (TFT) gated with a fluoropolymer dielectric. Compared with a conventional IZO TFT with a silicon nitride dielectric, a fluoropolymer dielectric effectively reduces the operation voltage to less than 3 V and greatly increases the effective mobility 40-fold. We suggest that the dipole layer formed at the dielectric surface facilitates electron accumulation and induces the electric double-layer effect. The dipole-induced hysteresis effect is also investigated.

Chemical vapor deposited monolayer MoS2 top-gate MOSFET with atomic-layer-deposited ZrO2 as gate dielectric

NASA Astrophysics Data System (ADS)

Hu, Yaoqiao; Jiang, Huaxing; Lau, Kei May; Li, Qiang

2018-04-01

For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec-1, and a field-effect electron mobility of 12.1 cm2 V-1 s-1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm-1 at V DS = 5 V. The gate leakage current is below 10-2 A cm-2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm-1 is obtained. Gate hysteresis and frequency-dependent capacitance-voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ˜3 × 1012 cm-2 eV-1.

Low voltage operation of IGZO thin film transistors enabled by ultrathin Al2O3 gate dielectric

NASA Astrophysics Data System (ADS)

Ma, Pengfei; Du, Lulu; Wang, Yiming; Jiang, Ran; Xin, Qian; Li, Yuxiang; Song, Aimin

2018-01-01

An ultrathin, 5 nm, Al2O3 film grown by atomic-layer deposition was used as a gate dielectric for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The Al2O3 layer showed a low surface roughness of 0.15 nm, a low leakage current, and a high breakdown voltage of 6 V. In particular, a very high gate capacitance of 720 nF/cm2 was achieved, making it possible for the a-IGZO TFTs to not only operate at a low voltage of 1 V but also exhibit desirable properties including a low threshold voltage of 0.3 V, a small subthreshold swing of 100 mV/decade, and a high on/off current ratio of 1.2 × 107. Furthermore, even under an ultralow operation voltage of 0.6 V, well-behaved transistor characteristics were still observed with an on/off ratio as high as 3 × 106. The electron transport through the Al2O3 layer has also been analyzed, indicating the Fowler-Nordheim tunneling mechanism.

Achieving high carrier mobility exceeding 70 cm2/Vs in amorphous zinc tin oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Kim, Sang Tae; Shin, Yeonwoo; Yun, Pil Sang; Bae, Jong Uk; Chung, In Jae; Jeong, Jae Kyeong

2017-09-01

This paper proposes a new defect engineering concept for low-cost In- and Ga-free zinc tin oxide (ZTO) thin-film transistors (TFTs). This concept is comprised of capping ZTO films with tantalum (Ta) and a subsequent modest thermal annealing treatment at 200 °C. The Ta-capped ZTO TFTs exhibited a remarkably high carrier mobility of 70.8 cm2/Vs, low subthreshold gate swing of 0.18 V/decade, threshold voltage of -1.3 V, and excellent ION/OFF ratio of 2 × 108. The improvement (> two-fold) in the carrier mobility compared to the uncapped ZTO TFT can be attributed to the effective reduction of the number of adverse tailing trap states, such as hydroxyl groups or oxygen interstitial defects, which stems from the scavenging effect of the Ta capping layer on the ZTO channel layer. Furthermore, the Ta-capped ZTO TFTs showed excellent positive and negative gate bias stress stabilities. [Figure not available: see fulltext.

Effect of organic buffer layer in the electrical properties of amorphous-indium gallium zinc oxide thin film transistor.

PubMed

Wang, Jian-Xun; Hyung, Gun Woo; Li, Zhao-Hui; Son, Sung-Yong; Kwon, Sang Jik; Kim, Young Kwan; Cho, Eou Sik

2012-07-01

In this research, we reported on the fabrication of top-contact amorphous-indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with an organic buffer layer between inorganic gate dielectric and active layer in order to improve the electrical properties of devices. By inserting an organic buffer layer, it was possible to make an affirmation of the improvements in the electrical characteristics of a-IGZO TFTs such as subthreshold slope (SS), on/off current ratio (I(ON/OFF)), off-state current, and saturation field-effect mobility (muFE). The a-IGZO TFTs with the cross-linked polyvinyl alcohol (c-PVA) buffer layer exhibited the pronounced improvements of the muFE (17.4 cm2/Vs), SS (0.9 V/decade), and I(ON/OFF) (8.9 x 10(6)).

Selective UV–O3 treatment for indium zinc oxide thin film transistors with solution-based multiple active layer

NASA Astrophysics Data System (ADS)

Kim, Yu-Jung; Jeong, Jun-Kyo; Park, Jung-Hyun; Jeong, Byung-Jun; Lee, Hi-Deok; Lee, Ga-Won

2018-06-01

In this study, a method to control the electrical performance of solution-based indium zinc oxide (IZO) thin film transistors (TFTs) is proposed by ultraviolet–ozone (UV–O3) treatment on the selective layer during multiple IZO active layer depositions. The IZO film is composed of triple layers formed by spin coating and UV–O3 treatment only on the first layer or last layer. The IZO films are compared by X-ray photoelectron spectroscopy, and the results show that the atomic ratio of oxygen vacancy (VO) increases in the UV–O3 treatment on the first layer, while it decreases on last layer. The device characteristics of the bottom gated structure are also improved in the UV–O3 treatment on the first layer. This indicates that the selective UV–O3 treatment in a multi-stacking active layer is an effective method to optimize TFT properties by controlling the amount of VO in the IZO interface and surface independently.

Inversion channel diamond metal-oxide-semiconductor field-effect transistor with normally off characteristics.

PubMed

Matsumoto, Tsubasa; Kato, Hiromitsu; Oyama, Kazuhiro; Makino, Toshiharu; Ogura, Masahiko; Takeuchi, Daisuke; Inokuma, Takao; Tokuda, Norio; Yamasaki, Satoshi

2016-08-22

We fabricated inversion channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with normally off characteristics. At present, Si MOSFETs and insulated gate bipolar transistors (IGBTs) with inversion channels are widely used because of their high controllability of electric power and high tolerance. Although a diamond semiconductor is considered to be a material with a strong potential for application in next-generation power devices, diamond MOSFETs with an inversion channel have not yet been reported. We precisely controlled the MOS interface for diamond by wet annealing and fabricated p-channel and planar-type MOSFETs with phosphorus-doped n-type body on diamond (111) substrate. The gate oxide of Al2O3 was deposited onto the n-type diamond body by atomic layer deposition at 300 °C. The drain current was controlled by the negative gate voltage, indicating that an inversion channel with a p-type character was formed at a high-quality n-type diamond body/Al2O3 interface. The maximum drain current density and the field-effect mobility of a diamond MOSFET with a gate electrode length of 5 μm were 1.6 mA/mm and 8.0 cm(2)/Vs, respectively, at room temperature.

Nanoindentation investigation of HfO2 and Al2O3 films grown by atomic layer deposition

Treesearch

K. Tapily; Joseph E. Jakes; D. S. Stone; P. Shrestha; D. Gu; H. Baumgart; A. A. Elmustafa

2008-01-01

The challenges of reducing gate leakage current and dielectric breakdown beyond the 45 nm technology node have shifted engineers’ attention from the traditional and proven dielectric SiO2 to materials of higher dielectric constant also known as high-k materials such as hafnium oxide (HfO2) and aluminum oxide (Al2O3). These high-k materials are projected to...

Electron Transporting Semiconductor Dielectric Intramolecular

DTIC Science & Technology

2012-04-27

gate dielectric, and the capacitance times mobility was 80 nS/V (10x typical pentacene /oxide), stable to heating to 70 °C in air. Remarkably...oxide/ Pentacene Bilayer Transistors: High Mobility n-Channel, Ambipolar and Nonvolatile Devices” Adv. Funct. Mater. 18, 1832-1839 (2008) Sun, J...case of layered OSC OFETs. This proposal is somewhat different from a model by deLeeuw for amorphous OFETs13 in which carriers would be locally

In operando evidence of deoxygenation in ionic liquid gating of YBa2Cu3O7-X

PubMed Central

Perez-Muñoz, Ana M.; Schio, Pedro; Poloni, Roberta; Fernandez-Martinez, Alejandro; Rivera-Calzada, Alberto; Salas-Colera, Eduardo; Kinney, Joseph; Leon, Carlos; Santamaria, Jacobo; Garcia-Barriocanal, Javier; Goldman, Allen M.

2017-01-01

Field-effect experiments on cuprates using ionic liquids have enabled the exploration of their rich phase diagrams [Leng X, et al. (2011) Phys Rev Lett 107(2):027001]. Conventional understanding of the electrostatic doping is in terms of modifications of the charge density to screen the electric field generated at the double layer. However, it has been recently reported that the suppression of the metal to insulator transition induced in VO2 by ionic liquid gating is due to oxygen vacancy formation rather than to electrostatic doping [Jeong J, et al. (2013) Science 339(6126):1402–1405]. These results underscore the debate on the true nature, electrostatic vs. electrochemical, of the doping of cuprates with ionic liquids. Here, we address the doping mechanism of the high-temperature superconductor YBa2Cu3O7-X (YBCO) by simultaneous ionic liquid gating and X-ray absorption experiments. Pronounced spectral changes are observed at the Cu K-edge concomitant with the superconductor-to-insulator transition, evidencing modification of the Cu coordination resulting from the deoxygenation of the CuO chains, as confirmed by first-principles density functional theory (DFT) simulations. Beyond providing evidence of the importance of chemical doping in electric double-layer (EDL) gating experiments with superconducting cuprates, our work shows that interfacing correlated oxides with ionic liquids enables a delicate control of oxygen content, paving the way to novel electrochemical concepts in future oxide electronics. PMID:28028236

In operando evidence of deoxygenation in ionic liquid gating of YBa2Cu3O7-X.

PubMed

Perez-Muñoz, Ana M; Schio, Pedro; Poloni, Roberta; Fernandez-Martinez, Alejandro; Rivera-Calzada, Alberto; Cezar, Julio C; Salas-Colera, Eduardo; Castro, German R; Kinney, Joseph; Leon, Carlos; Santamaria, Jacobo; Garcia-Barriocanal, Javier; Goldman, Allen M

2017-01-10

Field-effect experiments on cuprates using ionic liquids have enabled the exploration of their rich phase diagrams [Leng X, et al. (2011) Phys Rev Lett 107(2):027001]. Conventional understanding of the electrostatic doping is in terms of modifications of the charge density to screen the electric field generated at the double layer. However, it has been recently reported that the suppression of the metal to insulator transition induced in VO 2 by ionic liquid gating is due to oxygen vacancy formation rather than to electrostatic doping [Jeong J, et al. (2013) Science 339(6126):1402-1405]. These results underscore the debate on the true nature, electrostatic vs. electrochemical, of the doping of cuprates with ionic liquids. Here, we address the doping mechanism of the high-temperature superconductor YBa 2 Cu 3 O 7-X (YBCO) by simultaneous ionic liquid gating and X-ray absorption experiments. Pronounced spectral changes are observed at the Cu K-edge concomitant with the superconductor-to-insulator transition, evidencing modification of the Cu coordination resulting from the deoxygenation of the CuO chains, as confirmed by first-principles density functional theory (DFT) simulations. Beyond providing evidence of the importance of chemical doping in electric double-layer (EDL) gating experiments with superconducting cuprates, our work shows that interfacing correlated oxides with ionic liquids enables a delicate control of oxygen content, paving the way to novel electrochemical concepts in future oxide electronics.

Atomic layer deposited TaCy metal gates: Impact on microstructure, electrical properties, and work function on HfO2 high-k dielectrics

NASA Astrophysics Data System (ADS)

Triyoso, D. H.; Gregory, R.; Schaeffer, J. K.; Werho, D.; Li, D.; Marcus, S.; Wilk, G. D.

2007-11-01

TaCy has been reported to have the appropriate work function for negative metal-oxide semiconductor metal in high-k metal-oxide field-effect transistors. As device size continues to shrink, a conformal deposition for metal gate electrodes is needed. In this work, we report on the development and characterization of a novel TaCy process by atomic layer deposition (ALD). Detailed physical properties of TaCy films are studied using ellipsometry, a four-point probe, Rutherford backscattering spectrometry (RBS), x-ray photoelectron spectroscopy (XPS), and x-ray diffraction (XRD). RBS and XPS analysis indicate that TaCy films are near-stoichiometric, nitrogen free, and have low oxygen impurities. Powder XRD spectra showed that ALD films have a cubic microstructure. XPS carbon bonding studies revealed that little or no glassy carbon is present in the bulk of the film. Excellent electrical properties are obtained using ALD TaCy as a metal gate electrode. Well-behaved capacitance-voltage characteristics with ALD HfO2 gate dielectrics are demonstrated for TaCy thicknesses of 50, 100, and 250 Å. A low fixed charge (˜2-4×10-11 cm-2) is observed for all ALD HfO2/ALD TaCy devices. Increasing the thickness of ALD TaCy results in a decrease in work function (4.77 to 4.54 eV) and lower threshold voltages.

Synergistic approach to high-performance oxide thin film transistors using a bilayer channel architecture.

PubMed

Yu, Xinge; Zhou, Nanjia; Smith, Jeremy; Lin, Hui; Stallings, Katie; Yu, Junsheng; Marks, Tobin J; Facchetti, Antonio

2013-08-28

We report here a bilayer metal oxide thin film transistor concept (bMO TFT) where the channel has the structure: dielectric/semiconducting indium oxide (In2O3) layer/semiconducting indium gallium oxide (IGO) layer. Both semiconducting layers are grown from solution via a low-temperature combustion process. The TFT mobilities of bottom-gate/top-contact bMO TFTs processed at T = 250 °C are ~5tmex larger (~2.6 cm(2)/(V s)) than those of single-layer IGO TFTs (~0.5 cm(2)/(V s)), reaching values comparable to single-layer combustion-processed In2O3 TFTs (~3.2 cm(2)/(V s)). More importantly, and unlike single-layer In2O3 TFTs, the threshold voltage of the bMO TFTs is ~0.0 V, and the current on/off ratio is significantly enhanced to ~1 × 10(8) (vs ~1 × 10(4) for In2O3). The microstructure and morphology of the In2O3/IGO bilayers are analyzed by X-ray diffraction, atomic force microscopy, X-ray photoelectron spectroscopy, and transmission electron microscopy, revealing the polycrystalline nature of the In2O3 layer and the amorphous nature of the IGO layer. This work demonstrates that solution-processed metal oxides can be implemented in bilayer TFT architectures with significantly enhanced performance.

A manufacturable process integration approach for graphene devices

NASA Astrophysics Data System (ADS)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Anomalous Coulomb oscillation in crossed carbon nanotubes

NASA Astrophysics Data System (ADS)

Baek, Seung Jae; Lee, Dongsu; Park, Seung Joo; Park, Yung Woo; Svensson, Johannes; Jonson, Mats; Campbell, Eleanor E. B.

2008-03-01

Single-walled carbon nanotube (SWCNT) crossed junctions separated by an insulating layer were fabricated to investigate the double quantum dot modulated by a single gate (DQD-sG). Anomalous Coulomb oscillations were observed on the lower CNT at low temperature, where the behavior was interpreted by the concept of a double quantum dot (DQD) system http://scitation.aip.org/getabs/servlet/GetabsServlet?prog=normal&id =APPLAB000089000023233107000001&idtype=cvips&gifs=yes [1]. To understand it more clearly, we have intentionally fabricated crossed CNTs without oxide layer in between. The observed anomalous Coulomb oscillations indicate that the contact resistance between the two tubes becomes a potential barrier splitting the initial single QD into the DQD, and the back-gate modulates the energy levels of the DQD.

100-nm gate lithography for double-gate transistors

NASA Astrophysics Data System (ADS)

Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

2001-09-01

The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

Electrical Characteristics of WSi2 Nanocrystal Capacitors with Barrier-Engineered High-k Tunnel Layers

NASA Astrophysics Data System (ADS)

Lee, Hyo Jun; Lee, Dong Uk; Kim, Eun Kyu; You, Hee-Wook; Cho, Won-Ju

2011-06-01

Nanocrystal-floating gate capacitors with WSi2 nanocrystals and high-k tunnel layers were fabricated to improve the electrical properties such as retention, programming/erasing speed, and endurance. The WSi2 nanocrystals were distributed uniformly between the tunnel and control gate oxide layers. The electrical performance of the tunnel barrier with the SiO2/HfO2/Al2O3 (2/1/3 nm) (OHA) tunnel layer appeared to be better than that with the Al2O3/HfO2/Al2O3 (2/1/3 nm) (AHA) tunnel layer. When ΔVFB is about 1 V after applying voltage at ±8 V, the programming/erasing speeds of AHA and OHA tunnel layers are 300 ms and 500 µs, respectively. In particular, the device with WSi2 nanocrystals and the OHA tunnel barrier showed a large memory window of about 7.76 V when the voltage swept from 10 to -10 V, and it was maintained at about 2.77 V after 104 cycles.

Implementation of atomic layer deposition-based AlON gate dielectrics in AlGaN/GaN MOS structure and its physical and electrical properties

NASA Astrophysics Data System (ADS)

Nozaki, Mikito; Watanabe, Kenta; Yamada, Takahiro; Shih, Hong-An; Nakazawa, Satoshi; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

Alumina incorporating nitrogen (aluminum oxynitride; AlON) for immunity against charge injection was grown on a AlGaN/GaN substrate through the repeated atomic layer deposition (ALD) of AlN layers and in situ oxidation in ozone (O3) ambient under optimized conditions. The nitrogen distribution was uniform in the depth direction, the composition was controllable over a wide range (0.5–32%), and the thickness could be precisely controlled. Physical analysis based on synchrotron radiation X-ray photoelectron spectroscopy (SR-XPS) revealed that harmful intermixing at the insulator/AlGaN interface causing Ga out-diffusion in the gate stack was effectively suppressed by this method. AlON/AlGaN/GaN MOS capacitors were fabricated, and they had excellent electrical properties and immunity against electrical stressing as a result of the improved interface stability.

Photo-induced persistent inversion of germanium in a 200-nm-deep surface region.

PubMed

Prokscha, T; Chow, K H; Stilp, E; Suter, A; Luetkens, H; Morenzoni, E; Nieuwenhuys, G J; Salman, Z; Scheuermann, R

2013-01-01

The controlled manipulation of the charge carrier concentration in nanometer thin layers is the basis of current semiconductor technology and of fundamental importance for device applications. Here we show that it is possible to induce a persistent inversion from n- to p-type in a 200-nm-thick surface layer of a germanium wafer by illumination with white and blue light. We induce the inversion with a half-life of ~12 hours at a temperature of 220 K which disappears above 280 K. The photo-induced inversion is absent for a sample with a 20-nm-thick gold capping layer providing a Schottky barrier at the interface. This indicates that charge accumulation at the surface is essential to explain the observed inversion. The contactless change of carrier concentration is potentially interesting for device applications in opto-electronics where the gate electrode and gate oxide could be replaced by the semiconductor surface.

Diamond field effect transistors with a high-dielectric constant Ta2O5 as gate material

NASA Astrophysics Data System (ADS)

Liu, J.-W.; Liao, M.-Y.; Imura, M.; Watanabe, E.; Oosato, H.; Koide, Y.

2014-06-01

A Ta2O5/Al2O3 bilayer gate oxide with a high-dielectric constant (high-k) has been successfully applied to a hydrogenated-diamond (H-diamond) metal-insulator-semiconductor field effect transistor (MISFET). The Ta2O5 layer is prepared by a sputtering-deposition (SD) technique on the Al2O3 buffer layer fabricated by an atomic layer deposition (ALD) technique. The ALD-Al2O3 plays an important role to eliminate plasma damage for the H-diamond surface during SD-Ta2O5 deposition. The dielectric constants of the SD-Ta2O5/ALD-Al2O3 bilayer and single SD-Ta2O5 are as large as 12.7 and 16.5, respectively. The k value of the single SD-Ta2O5 in this study is in good agreement with that of the SD-Ta2O5 on oxygen-terminated diamond. The capacitance-voltage characteristic suggests low interfacial trapped charge density for the SD-Ta2O5/ALD-Al2O3/H-diamond MIS diode. The MISFET with a gate length of 4 µm has a drain current maximum and an extrinsic transconductance of -97.7 mA mm-1 (normalized by gate width) and 31.0 ± 0.1 mS mm-1, respectively. The effective mobility in the H-diamond channel layer is found to be 70.1 ± 0.5 cm2 V-1 s-1.

Effect of Al-diffusion-induced positive flatband voltage shift on the electrical characteristics of Al-incorporated high-k metal-oxide-semiconductor field-effective transistor

NASA Astrophysics Data System (ADS)

Wang, Wenwu; Akiyama, Koji; Mizubayashi, Wataru; Nabatame, Toshihide; Ota, Hiroyuki; Toriumi, Akira

2009-03-01

We systematically studied what effect Al diffusion from high-k dielectrics had on the flatband voltage (Vfb) of Al-incorporated high-k gate stacks. An anomalous positive shift fin Vfb with the decreasing equivalent oxide thickness (EOT) of high-k gate stacks is reported. As the SiO2 interfacial layer is aggressively thinned in Al-incorporated HfxAl1-xOy gate stacks with a metal-gate electrode, the Vfb first lies on the well known linear Vfb-EOT plot and deviates toward the positive-voltage direction (Vfb roll-up), followed by shifting toward negative voltage (Vfb roll-off). We demonstrated that the Vfb roll-up behavior remarkably decreases the threshold voltage (Vth) of p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs), and does not cause severe degradation in the characteristics of hole mobility. The Vfb roll-up behavior, which is independent of gate materials but strongly dependent on high-k dielectrics, was ascribed to variations in fixed charges near the SiO2/Si interface, which are caused by Al diffusion from HfxAl1-xOy through SiO2 to the SiO2/Si interface. These results indicate that anomalous positive shift in Vfb, i.e., Vfb roll-up, should be taken into consideration in quantitatively adjusting Vfb in thin EOT regions and that it could be used to further tune Vth in p-MOSFETs.

Atomic layer deposited oxide films as protective interface layers for integrated graphene transfer

NASA Astrophysics Data System (ADS)

Cabrero-Vilatela, A.; Alexander-Webber, J. A.; Sagade, A. A.; Aria, A. I.; Braeuninger-Weimer, P.; Martin, M.-B.; Weatherup, R. S.; Hofmann, S.

2017-12-01

The transfer of chemical vapour deposited graphene from its parent growth catalyst has become a bottleneck for many of its emerging applications. The sacrificial polymer layers that are typically deposited onto graphene for mechanical support during transfer are challenging to remove completely and hence leave graphene and subsequent device interfaces contaminated. Here, we report on the use of atomic layer deposited (ALD) oxide films as protective interface and support layers during graphene transfer. The method avoids any direct contact of the graphene with polymers and through the use of thicker ALD layers (≥100 nm), polymers can be eliminated from the transfer-process altogether. The ALD film can be kept as a functional device layer, facilitating integrated device manufacturing. We demonstrate back-gated field effect devices based on single-layer graphene transferred with a protective Al2O3 film onto SiO2 that show significantly reduced charge trap and residual carrier densities. We critically discuss the advantages and challenges of processing graphene/ALD bilayer structures.

A Low Temperature, Solution-Processed Poly(4-vinylphenol), YO(x) Nanoparticle Composite/Polysilazane Bi-Layer Gate Insulator for ZnO Thin Film Transistor.

PubMed

Shin, Hyeonwoo; Kang, Chan-Mo; Chae, Hyunsik; Kim, Hyun-Gwan; Baek, Kyu-Ha; Choi, Hyoung Jin; Park, Man-Young; Do, Lee-Mi; Lee, Changhee

2016-03-01

Low temperature, solution-processed metal oxide thin film transistors (MEOTFTs) have been widely investigated for application in low-cost, transparent, and flexible electronics. To enlarge the application area, solution-processed gate insulators (GI) have been investigated in recent years. We investigated the effects of the organic/inorganic bi-layer GI to ZnO thin film transistors (TFTs). PVP, YO(x) nanoparticle composite, and polysilazane bi-layer showed low leakage current (-10(-8) A/cm2 in 2 MV), which are applicable in low temperature processed MEOTFTs. Polysilazane was used as an interlayer between ZnO and PVP, YO(x) nanoparticle composite as a good charge transport interface with ZnO. By applying the PVP, YO(x), nanoparticle composite/polysilazane bi-layer structure to ZnO TFTs, we successfully suppressed the off current (I(off)) to -10(-11) and fabricated good MEOTFTs in 180 degrees C.

Gate length variation effect on performance of gate-first self-aligned In₀.₅₃Ga₀.₄₇As MOSFET.

PubMed

Mohd Razip Wee, Mohd F; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y

2013-01-01

A multi-gate n-type In₀.₅₃Ga₀.₄₇As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm(2)/Vs are achieved for the gate length and width of 0.2 µm and 30 µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10(-8) A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared.

Gate Length Variation Effect on Performance of Gate-First Self-Aligned In0.53Ga0.47As MOSFET

PubMed Central

Mohd Razip Wee, Mohd F.; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y.

2013-01-01

A multi-gate n-type In0.53Ga0.47As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm2/Vs are achieved for the gate length and width of 0.2 µm and 30µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10−8 A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared. PMID:24367548

GaN-Based High Temperature and Radiation-Hard Electronics for Harsh Environments

NASA Technical Reports Server (NTRS)

Son, Kyung-ah; Liao, Anna; Lung, Gerald; Gallegos, Manuel; Hatakeh, Toshiro; Harris, Richard D.; Scheick, Leif Z.; Smythe, William D.

2010-01-01

We develop novel GaN-based high temperature and radiation-hard electronics to realize data acquisition electronics and transmitters suitable for operations in harsh planetary environments. In this paper, we discuss our research on metal-oxide-semiconductor (MOS) transistors that are targeted for 500 (sup o)C operation and >2 Mrad radiation hardness. For the target device performance, we develop Schottky-free AlGaN/GaN MOS transistors, where a gate electrode is processed in a MOS layout using an Al2O3 gate dielectric layer....

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE PAGES

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.; ...

2015-08-12

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

Epitaxial pentacene films grown on the surface of ion-beam-processed gate dielectric layer

NASA Astrophysics Data System (ADS)

Chou, W. Y.; Kuo, C. W.; Cheng, H. L.; Mai, Y. S.; Tang, F. C.; Lin, S. T.; Yeh, C. Y.; Horng, J. B.; Chia, C. T.; Liao, C. C.; Shu, D. Y.

2006-06-01

The following research describes the process of fabrication of pentacene films with submicron thickness, deposited by thermal evaporation in high vacuum. The films were fabricated with the aforementioned conditions and their characteristics were analyzed using x-ray diffraction, scanning electron microscopy, polarized Raman spectroscopy, and photoluminescence. Organic thin-film transistors (OTFTs) were fabricated on an indium tin oxide coated glass substrate, using an active layer of ordered pentacene molecules, which were grown at room temperature. Pentacene film was aligned using the ion-beam aligned method, which is typically employed to align liquid crystals. Electrical measurements taken on a thin-film transistor indicated an increase in the saturation current by a factor of 15. Pentacene-based OTFTs with argon ion-beam-processed gate dielectric layers of silicon dioxide, in which the direction of the ion beam was perpendicular to the current flow, exhibited a mobility that was up to an order of magnitude greater than that of the controlled device without ion-beam process; current on/off ratios of approximately 106 were obtained. Polarized Raman spectroscopy investigation indicated that the surface of the gate dielectric layer, treated with argon ion beam, enhanced the intermolecular coupling of pentacene molecules. The study also proposes the explanation for the mechanism of carrier transportation in pentacene films.

A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under positive gate bias stress

DOE Office of Scientific and Technical Information (OSTI.GOV)

Niang, K. M.; Flewitt, A. J., E-mail: ajf@eng.cam.ac.uk; Barquinha, P. M. C.

Thin film transistors (TFTs) employing an amorphous indium gallium zinc oxide (a-IGZO) channel layer exhibit a positive shift in the threshold voltage under the application of positive gate bias stress (PBS). The time and temperature dependence of the threshold voltage shift was measured and analysed using the thermalization energy concept. The peak energy barrier to defect conversion is extracted to be 0.75 eV and the attempt-to-escape frequency is extracted to be 10{sup 7} s{sup −1}. These values are in remarkable agreement with measurements in a-IGZO TFTs under negative gate bias illumination stress (NBIS) reported recently (Flewitt and Powell, J. Appl. Phys.more » 115, 134501 (2014)). This suggests that the same physical process is responsible for both PBS and NBIS, and supports the oxygen vacancy defect migration model that the authors have previously proposed.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moghadam, Reza M.; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to low-power field-effect devices that can be used for logic or memory. Essential to realizing such field-effect devices is the development of ferroelectric metal-oxide-semiconductor (MOS) capacitors, in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel. Here we demonstrate that ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x= 0.7) that has been epitaxially grown on Ge. We find that themore » ferroelectric properties of SrZrxTi1-xO3 are exceptionally robust, as gate layers as thin as 5 nm give rise to hysteretic capacitance-voltage characteristics that are 2 V in width. The development of ferroelectric MOS capacitors with gate thicknesses that are technologically relevant opens a pathway to realize scalable ferroelectric field-effect devices.« less

Atomic-layer-deposited Al2O3 and HfO2 on InAlAs: A comparative study of interfacial and electrical characteristics

NASA Astrophysics Data System (ADS)

Wu, Li-Fan; Zhang, Yu-Ming; Lv, Hong-Liang; Zhang, Yi-Men

2016-10-01

Al2O3 and HfO2 thin films are separately deposited on n-type InAlAs epitaxial layers by using atomic layer deposition (ALD). The interfacial properties are revealed by angle-resolved x-ray photoelectron spectroscopy (AR-XPS). It is demonstrated that the Al2O3 layer can reduce interfacial oxidation and trap charge formation. The gate leakage current densities are 1.37 × 10-6 A/cm2 and 3.22 × 10-6 A/cm2 at +1 V for the Al2O3/InAlAs and HfO2/InAlAs MOS capacitors respectively. Compared with the HfO2/InAlAs metal-oxide-semiconductor (MOS) capacitor, the Al2O3/InAlAs MOS capacitor exhibits good electrical properties in reducing gate leakage current, narrowing down the hysteresis loop, shrinking stretch-out of the C-V characteristics, and significantly reducing the oxide trapped charge (Q ot) value and the interface state density (D it). Project supported by the National Basic Research Program of China (Grant No. 2010CB327505), the Advanced Research Foundation of China (Grant No. 914xxx803-051xxx111), the National Defense Advance Research Project, China (Grant No. 513xxxxx306), the National Natural Science Foundation of China (Grant No. 51302215), the Scientific Research Program Funded by Shaanxi Provincial Education Department, China (Grant No. 14JK1656), and the Science and Technology Project of Shaanxi Province, China (Grant No. 2016KRM029).

C-H surface diamond field effect transistors for high temperature (400 °C) and high voltage (500 V) operation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kawarada, H., E-mail: kawarada@waseda.jp; Institute of Nano-Science and Nano-Engineering, Waseda University, Shinjuku, Tokyo 169-8555; Kagami Memorial Laboratory for Material Science and Technology, Waseda University, Shinjuku, Tokyo 169-0051

2014-07-07

By forming a highly stable Al{sub 2}O{sub 3} gate oxide on a C-H bonded channel of diamond, high-temperature, and high-voltage metal-oxide-semiconductor field-effect transistor (MOSFET) has been realized. From room temperature to 400 °C (673 K), the variation of maximum drain-current is within 30% at a given gate bias. The maximum breakdown voltage (V{sub B}) of the MOSFET without a field plate is 600 V at a gate-drain distance (L{sub GD}) of 7 μm. We fabricated some MOSFETs for which V{sub B}/L{sub GD} > 100 V/μm. These values are comparable to those of lateral SiC or GaN FETs. The Al{sub 2}O{sub 3} was deposited on the C-Hmore » surface by atomic layer deposition (ALD) at 450 °C using H{sub 2}O as an oxidant. The ALD at relatively high temperature results in stable p-type conduction and FET operation at 400 °C in vacuum. The drain current density and transconductance normalized by the gate width are almost constant from room temperature to 400 °C in vacuum and are about 10 times higher than those of boron-doped diamond FETs.« less

Use of a hard mask for formation of gate and dielectric via nanofilament field emission devices

DOEpatents

Morse, Jeffrey D.; Contolini, Robert J.

2001-01-01

A process for fabricating a nanofilament field emission device in which a via in a dielectric layer is self-aligned to gate metal via structure located on top of the dielectric layer. By the use of a hard mask layer located on top of the gate metal layer, inert to the etch chemistry for the gate metal layer, and in which a via is formed by the pattern from etched nuclear tracks in a trackable material, a via is formed by the hard mask will eliminate any erosion of the gate metal layer during the dielectric via etch. Also, the hard mask layer will protect the gate metal layer while the gate structure is etched back from the edge of the dielectric via, if such is desired. This method provides more tolerance for the electroplating of a nanofilament in the dielectric via and sharpening of the nanofilament.

Field-effect P-N junction

DOEpatents

Regan, William; Zettl, Alexander

2015-05-05

This disclosure provides systems, methods, and apparatus related to field-effect p-n junctions. In one aspect, a device includes an ohmic contact, a semiconductor layer disposed on the ohmic contact, at least one rectifying contact disposed on the semiconductor layer, a gate including a layer disposed on the at least one rectifying contact and the semiconductor layer and a gate contact disposed on the layer. A lateral width of the rectifying contact is less than a semiconductor depletion width of the semiconductor layer. The gate contact is electrically connected to the ohmic contact to create a self-gating feedback loop that is configured to maintain a gate electric field of the gate.

A Survey of Solid-State Microwave Power Devices

DTIC Science & Technology

1977-04-29

from the channel by a thin oxide layer (insulated gate FET or IGFET), it may be a diffused junction at the top of the channel (junction FET or JFET...greater than 100 GHz. YIG-tuned units are finding increasing use as extremely stable sources, whereas varactor tuning is used where tuning speed is

Transport measurements on monolayer and few-layer WSe2

NASA Astrophysics Data System (ADS)

Palomaki, Tauno; Zhao, Wenjin; Finney, Joe; Fei, Zaiyao; Nguyen, Paul; McKay, Frank; Cobden, David

The behavior of the electrical contacts often dominates transport measurements in mono and few-layer transition metal dichalcogenide (TMD) devices. Creating good contacts for some TMDs is particularly challenging since the fabrication procedure should prevent the TMD from oxidizing or chemically interacting with the contacts. In this talk, we discuss our progress on creating mono and few-layer WSe2 devices with both good electrical contacts and minimal effects from the substrate, polymer contamination, oxidation and other chemistry. For example, we have developed a technique for encapsulating metallic contacts and WSe2 flakes together in hexagonal boron nitride with multiple gates to separate and control the contributions from the channel and the Schottky barriers at the contacts. Research supported in part by Samsung GRO grant US 040814

Nonvolatile gate effect in a ferroelectric-semiconductor quantum well.

PubMed

Stolichnov, Igor; Colla, Enrico; Setter, Nava; Wojciechowski, Tomasz; Janik, Elzbieta; Karczewski, Grzegorz

2006-12-15

Field effect transistors with ferroelectric gates would make ideal rewritable nonvolatile memories were it not for the severe problems in integrating the ferroelectric oxide directly on the semiconductor channel. We propose a powerful way to avoid these problems using a gate material that is ferroelectric and semiconducting simultaneously. First, ferroelectricity in semiconductor (Cd,Zn)Te films is proven and studied using modified piezoforce scanning probe microscopy. Then, a rewritable field effect device is demonstrated by local poling of the (Cd,Zn)Te layer of a (Cd,Zn)Te/CdTe quantum well, provoking a reversible, nonvolatile change in the resistance of the 2D electron gas. The results point to a potential new family of nanoscale one-transistor memories.

Highly improved photo-induced bias stability of sandwiched triple layer structure in sol-gel processed fluorine-doped indium zinc oxide thin film transistor

NASA Astrophysics Data System (ADS)

Kim, Dongha; Park, Hyungjin; Bae, Byeong-Soo

2016-03-01

In order to improve the reliability of TFT, an Al2O3 insulating layer is inserted between active fluorine doped indium zinc oxide (IZO:F) thin films to form a sandwiched triple layer. All the thin films were fabricated via low-cost sol-gel process. Due to its large energy bandgap and high bonding energy with oxygen atoms, the Al2O3 layer acts as a photo-induced positive charge blocking layer that effectively blocks the migration of both holes and V o2+ toward the interface between the gate insulator and the semiconductor. The inserted Al2O3 triple layer exhibits a noticeably low turn on voltage shift of -0.7 V under NBIS as well as the good TFT performance with a mobility of 10.9 cm2/V ṡ s. We anticipate that this approach can be used to solve the stability issues such as NBIS, which is caused by inescapable oxygen vacancies.

Reconfigurable and non-volatile vertical magnetic logic gates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Butler, J., E-mail: jbutl001@ucr.edu; Lee, B.; Shachar, M.

2014-04-28

In this paper, we discuss the concept and prototype fabrication of reconfigurable and non-volatile vertical magnetic logic gates. These gates consist of two input layers and a RESET layer. The RESET layer allows the structure to be used as either an AND or an OR gate, depending on its magnetization state. To prove this concept, the gates were fabricated using a multi-layered patterned magnetic media, in which three magnetic layers are stacked and exchange-decoupled via non-magnetic interlayers. We demonstrate the functionality of these logic gates by conducting atomic force microscopy and magnetic force microscopy (MFM) analysis of the multi-layered patternedmore » magnetic media. The logic gates operation mechanism and fabrication feasibility are both validated by the MFM imaging results.« less

Large current modulation and tunneling magnetoresistance change by a side-gate electric field in a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor.

PubMed

Kanaki, Toshiki; Yamasaki, Hiroki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

2018-05-08

A vertical spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) is a promising low-power device for the post scaling era. Here, using a ferromagnetic-semiconductor GaMnAs-based vertical spin MOSFET with a GaAs channel layer, we demonstrate a large drain-source current I DS modulation by a gate-source voltage V GS with a modulation ratio up to 130%, which is the largest value that has ever been reported for vertical spin field-effect transistors thus far. We find that the electric field effect on indirect tunneling via defect states in the GaAs channel layer is responsible for the large I DS modulation. This device shows a tunneling magnetoresistance (TMR) ratio up to ~7%, which is larger than that of the planar-type spin MOSFETs, indicating that I DS can be controlled by the magnetization configuration. Furthermore, we find that the TMR ratio can be modulated by V GS . This result mainly originates from the electric field modulation of the magnetic anisotropy of the GaMnAs ferromagnetic electrodes as well as the potential modulation of the nonmagnetic semiconductor GaAs channel layer. Our findings provide important progress towards high-performance vertical spin MOSFETs.

Complex oxide thin films for microelectronics

NASA Astrophysics Data System (ADS)

Suvorova, Natalya

The rapid scaling of the device dimensions, namely in metal oxide semiconductor field effect transistor (MOSFET), is reaching its fundamental limit which includes the increase in allowable leakage current due to direct tunneling with decrease of physical thickness of SiO2 gate dielectric. The significantly higher relative dielectric constant (in the range 9--25) of the gate dielectric beyond the 3.9 value of silicon dioxide will allow increasing the physical thickness. Among the choices for the high dielectric constant (K) materials for future generation MOSFET application, barium strontium titanate (BST) and strontium titanate (STO) possess one of the highest attainable K values making them the promising candidates for alternative gate oxide. However, the gate stack engineering does not imply the simple replacement of the SiO2 with the new dielectric. Several requirements should be met for successful integration of a new material. The major one is a production of high level of interface states (Dit) compared to that of SiO 2 on Si. An insertion of a thin SiO2 layer prior the growth of high-K thin film is a simple solution that helps to limit reaction with Si substrate and attains a high quality interface. However, the combination of two thin films reduces the overall K of the dielectric stack. An optimization of the SiO2 underlayer in order to maintain the interface quality yet minimize the effect on K is the focus of this work. The results from our study are presented with emphasis on the key process parameters that improve the dielectric film stack. For in-situ growth characterization of BST and STO films sputter deposited on thermally oxidized Si substrates spectroscopic ellipsometry in combination with time of flight ion scattering and recoil spectrometry have been employed. Studies of material properties have been complemented with analytical electron microscopy. To evaluate the interface quality the electrical characterization has been employed using capacitance-voltage and conductance-voltage measurements. Special attention was given to the extraction of static dielectric constant of BST and STO from the multiple film stack. The K value was found to be sensitive to the input parameters such as dielectric constant and thickness of interface layers.

Mechanical writing of n-type conductive layers on the SrTiO3 surface in nanoscale

PubMed Central

Wang, Yuhang; Zhao, Kehan; Shi, Xiaolan; Li, Geng; Xie, Guanlin; Lai, Xubo; Ni, Jun; Zhang, Liuwan

2015-01-01

The fabrication and control of the conductive surface and interface on insulating SrTiO3 bulk provide a pathway for oxide electronics. The controllable manipulation of local doping concentration in semiconductors is an important step for nano-electronics. Here we show that conductive patterns can be written on bare SrTiO3 surface by controllable doping in nanoscale using the mechanical interactions of atomic force microscopy tip without applying external electric field. The conductivity of the layer is n-type, oxygen sensitive, and can be effectively tuned by the gate voltage. Hence, our findings have potential applications in oxide nano-circuits and oxygen sensors. PMID:26042679

DOE Office of Scientific and Technical Information (OSTI.GOV)

Park, J.; Ahn, Y.; Tilka, J. A.

Disorder in the potential-energy landscape presents a major obstacle to the more rapid development of semiconductor quantum device technologies. We report a large-magnitude source of disorder, beyond commonly considered unintentional background doping or fixed charge in oxide layers: nanoscale strain fields induced by residual stresses in nanopatterned metal gates. Quantitative analysis of synchrotron coherent hard x-ray nanobeam diffraction patterns reveals gate-induced curvature and strains up to 0.03% in a buried Si quantum well within a Si/SiGe heterostructure. Furthermore, electrode stress presents both challenges to the design of devices and opportunities associated with the lateral manipulation of electronic energy levels.

Improving off-state leakage characteristics for high voltage AlGaN/GaN-HFETs on Si substrates

NASA Astrophysics Data System (ADS)

Moon, Sung-Woon; Twynam, John; Lee, Jongsub; Seo, Deokwon; Jung, Sungdal; Choi, Hong Goo; Shim, Heejae; Yim, Jeong Soon; Roh, Sungwon D.

2014-06-01

We present a reliable process and design technique for realizing high voltage AlGaN/GaN hetero-junction field effect transistors (HFETs) on Si substrates with very low and stable off-state leakage current characteristics. In this work, we have investigated the effects of the surface passivation layer, prepared by low pressure chemical vapor deposition (LPCVD) of silicon nitride (SiNx), and gate bus isolation design on the off-state leakage characteristics of metal-oxide-semiconductor (MOS) gate structure-based GaN HFETs. The surface passivated devices with gate bus isolation fully surrounding the source and drain regions showed extremely low off-state leakage currents of less than 20 nA/mm at 600 V, with very small variation. These techniques were successfully applied to high-current devices with 80-mm gate width, yielding excellent off-state leakage characteristics within a drain voltage range 0-700 V.

Fabrication of Ta2O5/GeNx gate insulator stack for Ge metal-insulator-semiconductor structures by electron-cyclotron-resonance plasma nitridation and sputtering deposition techniques

NASA Astrophysics Data System (ADS)

Otani, Yohei; Itayama, Yasuhiro; Tanaka, Takuo; Fukuda, Yukio; Toyota, Hiroshi; Ono, Toshiro; Mitsui, Minoru; Nakagawa, Kiyokazu

2007-04-01

The authors have fabricated germanium (Ge) metal-insulator-semiconductor (MIS) structures with a 7-nm-thick tantalum pentaoxide (Ta2O5)/2-nm-thick germanium nitride (GeNx) gate insulator stack by electron-cyclotron-resonance plasma nitridation and sputtering deposition. They found that pure GeNx ultrathin layers can be formed by the direct plasma nitridation of the Ge surface without substrate heating. X-ray photoelectron spectroscopy revealed no oxidation of the GeNx layer after the Ta2O5 sputtering deposition. The fabricated MIS capacitor with a capacitance equivalent thickness of 4.3nm showed excellent leakage current characteristics. The interface trap density obtained by the modified conductance method was 4×1011cm-2eV-1 at the midgap.

Gate-Variable Mid-Infrared Optical Transitions in a (Bi1-xSbx)2Te3 Topological Insulator.

PubMed

Whitney, William S; Brar, Victor W; Ou, Yunbo; Shao, Yinming; Davoyan, Artur R; Basov, D N; He, Ke; Xue, Qi-Kun; Atwater, Harry A

2017-01-11

We report mid-infrared spectroscopy measurements of ultrathin, electrostatically gated (Bi 1-x Sb x ) 2 Te 3 topological insulator films in which we observe several percent modulation of transmittance and reflectance as gating shifts the Fermi level. Infrared transmittance measurements of gated films were enabled by use of an epitaxial lift-off method for large-area transfer of topological insulator films from infrared-absorbing SrTiO 3 growth substrates to thermal oxidized silicon substrates. We combine these optical experiments with transport measurements and angle-resolved photoemission spectroscopy to identify the observed spectral modulation as a gate-driven transfer of spectral weight between both bulk and 2D topological surface channels and interband and intraband channels. We develop a model for the complex permittivity of gated (Bi 1-x Sb x ) 2 Te 3 and find a good match to our experimental data. These results open the path for layered topological insulator materials as a new candidate for tunable, ultrathin infrared optics and highlight the possibility of switching topological optoelectronic phenomena between bulk and spin-polarized surface regimes.

Utilizing self-assembled-monolayer-based gate dielectrics to fabricate molybdenum disulfide field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kawanago, Takamasa, E-mail: kawanago.t.ab@m.titech.ac.jp; Oda, Shunri

In this study, we apply self-assembled-monolayer (SAM)-based gate dielectrics to the fabrication of molybdenum disulfide (MoS{sub 2}) field-effect transistors. A simple fabrication process involving the selective formation of a SAM on metal oxides in conjunction with the dry transfer of MoS{sub 2} flakes was established. A subthreshold slope (SS) of 69 mV/dec and no hysteresis were demonstrated with the ultrathin SAM-based gate dielectrics accompanied by a low gate leakage current. The small SS and no hysteresis indicate the superior interfacial properties of the MoS{sub 2}/SAM structure. Cross-sectional transmission electron microscopy revealed a sharp and abrupt interface of the MoS{sub 2}/SAM structure.more » The SAM-based gate dielectrics are found to be applicable to the fabrication of low-voltage MoS{sub 2} field-effect transistors and can also be extended to various layered semiconductor materials. This study opens up intriguing possibilities of SAM-based gate dielectrics in functional electronic devices.« less

Self-Healing Polymer Dielectric for a High Capacitance Gate Insulator.

PubMed

Ko, Jieun; Kim, Young-Jae; Kim, Youn Sang

2016-09-14

Self-healing materials are required for development of various flexible electronic devices to repair cracks and ruptures caused by repetitive bending or folding. Specifically, a self-healing dielectric layer has huge potential to achieve healing electronics without mechanical breakdown in flexible operations. Here, we developed a high performance self-healing dielectric layer with an ionic liquid and catechol-functionalized polymer which exhibited a self-healing ability for both bulk and film states under mild self-healing conditions at 55 °C for 30 min. Due to the sufficient ion mobility of the ionic liquid in the polymer matrix, it had a high capacitance value above 1 μF/cm(2) at 20 Hz. Moreover, zinc oxide (ZnO) thin-film transistors (TFTs) with a self-healing dielectric layer exhibited a high field-effect mobility of 16.1 ± 3.07 cm(2) V(-1) s(-1) at a gate bias of 3 V. Even after repetitive self-healing of the dielectric layer from mechanical breaking, the electrical performance of the TFTs was well-maintained.

Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window

NASA Astrophysics Data System (ADS)

Kino, Hisashi; Fukushima, Takafumi; Tanaka, Tetsu

2018-04-01

Charge-trapping memory requires the increase of bit density per cell and a larger memory window for lower-power operation. A tunnel field-effect transistor (TFET) can achieve to increase the bit density per cell owing to its steep subthreshold slope. In addition, a TFET structure has an asymmetric structure, which is promising for achieving a larger memory window. A TFET with the N-type gate shows a higher electric field between the P-type source and the N-type gate edge than the conventional FET structure. This high electric field enables large amounts of charges to be injected into the charge storage layer. In this study, we fabricated silicon-oxide-nitride-oxide-semiconductor (SONOS) memory devices with the TFET structure and observed a steep subthreshold slope and a larger memory window.

High quality HfO{sub 2}/p-GaSb(001) metal-oxide-semiconductor capacitors with 0.8 nm equivalent oxide thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Barth, Michael; Datta, Suman, E-mail: sdatta@engr.psu.edu; Bruce Rayner, G.

2014-12-01

We investigate in-situ cleaning of GaSb surfaces and its effect on the electrical performance of p-type GaSb metal-oxide-semiconductor capacitor (MOSCAP) using a remote hydrogen plasma. Ultrathin HfO{sub 2} films grown by atomic layer deposition were used as a high permittivity gate dielectric. Compared to conventional ex-situ chemical cleaning methods, the in-situ GaSb surface treatment resulted in a drastic improvement in the impedance characteristics of the MOSCAPs, directly evidencing a much lower interface trap density and enhanced Fermi level movement efficiency. We demonstrate that by using a combination of ex-situ and in-situ surface cleaning steps, aggressively scaled HfO{sub 2}/p-GaSb MOSCAP structuresmore » with a low equivalent oxide thickness of 0.8 nm and efficient gate modulation of the surface potential are achieved, allowing to push the Fermi level far away from the valence band edge high up into the band gap of GaSb.« less

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

NASA Astrophysics Data System (ADS)

Held, Martin; Schießl, Stefan P.; Miehler, Dominik; Gannott, Florentina; Zaumseil, Jana

2015-08-01

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfOx) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100-300 nF/cm2) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfOx dielectrics.

Real-time photoelectron spectroscopy study of the oxidation reaction kinetics on p-type and n-type Si (001) surfaces

NASA Astrophysics Data System (ADS)

Yu, Zhou

Silicon oxides thermally grown on Si surface are the core gate materials of metal-oxide-semiconductor field effect transistor (MOSFET). This thin oxide layer insulates the gate terminals and the transistors substrate which make MOSFET has certain advantages over those conventional junctions, such as field-effect transistor (FET) and junction field effect transistor (JFET). With an oxide insulating layer, MOSFET is able to sustain higher input impedance and the corresponding gate leakage current can be minimized. Today, though the oxidation process on Si substrate is popular in industry, there are still some uncertainties about its oxidation kinetics. On a path to clarify and modeling the oxidation kinetics, a study of initial oxidation kinetics on Si (001) surface has attracted attentions due to having a relatively low surface electron density and few adsorption channels compared with other Si surface direction. Based on previous studies, there are two oxidation models of Si (001) that extensively accepted, which are dual oxide species mode and autocatalytic reaction model. These models suggest the oxidation kinetics on Si (001) mainly relies on the metastable oxygen atom on the surface and the kinetic is temperature dependent. Professor Yuji Takakuwa's group, Surface Physics laboratory, Institute of Multidisciplinary Research for Advanced Materials, Tohoku University, observed surface strain existed during the oxidation kinetics on Si (001) and this is the first time that strain was discovered during Si oxidation. Therefore, it is necessary to explain where the strain comes from since none of previous model research included the surface strain (defects generation) into considerations. Moreover, recent developing of complementary metal-oxide-semiconductor (CMOS) requires a simultaneous oxidation process on p- and n-type Si substrate. However, none of those previous models included the dopant factor into the oxidation kinetic modeling. All of these points that further work is necessary to update and modify the traditional Si (001) oxidation models that had been accepted for several decades. To update and complement the Si (001) oxidation kinetics, an understanding of the temperature and dopant factor during initial oxidation kinetics on Si (001) is our first step. In this study, real-time photoelectron spectroscopy is applied to characterize the oxidized (001) surface and surface information was collected by ultraviolet photoelectron spectroscopy technique. By analyzing parameters such as O 2p spectra uptake, change of work function and the surface state in respect of p- and n- type Si (001) substrate under different temperature, the oxygen adsorption structure and the dopant factor can be determined. In this study, experiments with temperature gradients on p-type Si (001) were conducted and this aims to clarify the temperature dependent characteristic of Si (001) surface oxidation. A comparison of the O 2p uptake, change of work function and surface state between p-and n-type Si (001) is made under a normal temperature and these provides with the data to explain how the dopant factor impacts the oxygen adsorption structure on the surface. In the future, the study of the oxygen adsorption structure will lead to an explanation of the surface strain that discovered; therefore, fundamental of the initial oxidation on Si (001) would be updated and complemented, which would contribute to the future gate technology in MOSFET and CMOS.

Characterisation of Nd2O3 thick gate dielectric for silicon

NASA Astrophysics Data System (ADS)

Dakhel, A. A.

2004-03-01

Thin neodymium films were prepared by the reactive synthesis method on Si (P) substrates to form MOS devices. The oxide films were characterised by UV absorption spectroscopy, X-ray fluorescence (EDXRF) and X-ray diffraction (XRD). The ac conductance and capacitance of the devices were studied as a function of frequency in the range 100 Hz-100 kHz, of temperature in the range 293-473 K and of gate voltage. It was proved that a suitable formalism to explain the frequency dependence of the ac conductivity and capacitance of the insulator is controlled by a universal power law based on the relaxation processes of the hopping or tunnelling of the current carriers between equilibrium sites. The temperature dependence of the ac conductance at the accumulation state shows a small activation energy of about 0.07 eV for a MOS device with amorphous neodymium oxide. The temperature dependence of the accumulation capacitance for a MOS structure with crystalline neodymium oxide shows a maximum at about 390 K; such a maximum was not observed for the structure with amorphous neodymium oxide. The method of capacitance-gate voltage (C-Vg) measurements was used to investigate the effect of annealing in air and in vacuum on the surface density of states (Nss) at the insulator/semiconductor (I/S) interface. It was concluded that the density of surface states in the mid-gap increases by about five times while the density of the trapped charges in the oxide layer decreases by about eight times when the oxide crystallises into a polycrystalline structure.

Germanium MOS capacitors grown on Silicon using low temperature RF-PECVD

NASA Astrophysics Data System (ADS)

Dushaq, Ghada; Rasras, Mahmoud; Nayfeh, Ammar

2017-10-01

In this paper, Ge metal-oxide-semiconductor capacitors (MOSCAPs) are fabricated on Si using a low temperature two-step deposition technique by radio frequency plasma enhanced chemical vapor deposition. The MOSCAP gate stack consists of atomic layer deposition of Al2O3 as the gate oxide and a Ti/Al metal gate electrode. The electrical characteristics of 9 nm Al2O3/i-Ge/Si MOSCAPs exhibit an n-type (p-channel) behavior and normal high frequency C-V responses. In addition to CV measurements, the gate leakage versus the applied voltage is measured and discussed. Moreover, the electrical behavior is discussed in terms of the material and interface quality. The Ge/high-k interface trap density versus the surface potential is extracted using the most commonly used methods in detemining the interface traps based on the capacitance-voltage (C-V) curves. The discussion included the Dit calculation from the conductance method, the high-low frequency (Castagné-Vapaille) method, and the Terman (high-frequency) method. Furthermore, the origins of the discrepancies in the interface trap densities determined from the different methods are discussed. The study of the post annealed Ge layers at different temperatures in H2 and N2 gas ambient revealed an improved electrical and transport properties of the films treated at T  <  600 °C. Also, samples annealed at  <550 °C show the lowest threading dislocation density of ~1  ×  106 cm-2. The low temperature processing of Ge/Si demonstrates a great potential for p-channel transistor applications in a monolithically integrated CMOS platform.

Hot-electron-induced hydrogen redistribution and defect generation in metal-oxide-semiconductor capacitors

NASA Astrophysics Data System (ADS)

Buchanan, D. A.; Marwick, A. D.; Dimaria, D. J.; Dori, L.

1994-09-01

Redistribution of hydrogen caused by hot-electron injection has been studied by hydrogen depth profiling with N-15 nuclear reaction analysis and electrical methods. Internal photoemission and Fowler-Nordheim injection were used for electron injection into large Al-gate and polysilicon-gate capacitors, respectively. A hydrogen-rich layer (about 10(exp 15) atoms/sq cm) observed at the Al/SiO2 interface was found to serve as the source of hydrogen during the hot-electron stress. A small fraction of the hydrogen released from this layer was found to be retrapped near the Si/SiO2 interface for large electron fluences in the Al-gate samples. Within the limit of detectability, about 10(exp 14)/sq cm, no hydrogen was measured using nuclear reaction analysis in the polysilicon-gate samples. The buildup of hydrogen at the Si/SiO2 interface exhibits a threshold at about 1 MV/cm, consistent with the threshold for electron heating in SiO2. In the 'wet' SiO2 films with purposely introduced excess hydrogen, the rate of hydrogen buildup at the Si/SiO2 interface is found to be significantly greater than that found in the 'dry' films. During electron injection, hydrogen redistribution was also confirmed via the deactivation of boron dopant in the silicon substrate. The generation rates of interface states, neutral electron traps, and anomalous positive charge are found to increase with increasing hydrogen buildup in the substrate and the initial hydrogen concentration in the film. It is concluded that the generation of defects is preceded by the hot-electron-induced release and transport of atomic hydrogen and it is the chemical reaction of this species within the metal-oxide-semiconductor structure that generates the electrically active defects.

Polymer-electrolyte-gated nanowire synaptic transistors for neuromorphic applications

NASA Astrophysics Data System (ADS)

Zou, Can; Sun, Jia; Gou, Guangyang; Kong, Ling-An; Qian, Chuan; Dai, Guozhang; Yang, Junliang; Guo, Guang-hua

2017-09-01

Polymer-electrolytes are formed by dissolving a salt in polymer instead of water, the conducting mechanism involves the segmental motion-assisted diffusion of ion in the polymer matrix. Here, we report on the fabrication of tin oxide (SnO2) nanowire synaptic transistors using polymer-electrolyte gating. A thin layer of poly(ethylene oxide) and lithium perchlorate (PEO/LiClO4) was deposited on top of the devices, which was used to boost device performances. A voltage spike applied on the in-plane gate attracts ions toward the polymer-electrolyte/SnO2 nanowire interface and the ions are gradually returned after the pulse is removed, which can induce a dynamic excitatory postsynaptic current in the nanowire channel. The SnO2 synaptic transistors exhibit the behavior of short-term plasticity like the paired-pulse facilitation and self-adaptation, which is related to the electric double-effect regulation. In addition, the synaptic logic functions and the logical function transformation are also discussed. Such single SnO2 nanowire-based synaptic transistors are of great importance for future neuromorphic devices.

Large-area, continuous and high electrical performances of bilayer to few layers MoS2 fabricated by RF sputtering via post-deposition annealing method

PubMed Central

Hussain, Sajjad; Singh, Jai; Vikraman, Dhanasekaran; Singh, Arun Kumar; Iqbal, Muhammad Zahir; Khan, Muhammad Farooq; Kumar, Pushpendra; Choi, Dong-Chul; Song, Wooseok; An, Ki-Seok; Eom, Jonghwa; Lee, Wan-Gyu; Jung, Jongwan

2016-01-01

We report a simple and mass-scalable approach for thin MoS2 films via RF sputtering combined with the post-deposition annealing process. We have prepared as-sputtered film using a MoS2 target in the sputtering system. The as-sputtered film was subjected to post-deposition annealing to improve crystalline quality at 700 °C in a sulfur and argon environment. The analysis confirmed the growth of continuous bilayer to few-layer MoS2 film. The mobility value of ~29 cm2/Vs and current on/off ratio on the order of ~104 were obtained for bilayer MoS2. The mobility increased up to ~173–181 cm2/Vs, respectively, for few-layer MoS2. The mobility of our bilayer MoS2 FETs is larger than any previously reported values of single to bilayer MoS2 grown on SiO2/Si substrate with a SiO2 gate oxide. Moreover, our few-layer MoS2 FETs exhibited the highest mobility value ever reported for any MoS2 FETs with a SiO2 gate oxide. It is presumed that the high mobility behavior of our film could be attributed to low charged impurities of our film and dielectric screening effect by an interfacial MoOxSiy layer. The combined preparation route of RF sputtering and post-deposition annealing process opens up the novel possibility of mass and batch production of MoS2 film. PMID:27492282

Effect of Gallium Doping on the Characteristic Properties of Polycrystalline Cadmium Telluride Thin Film

NASA Astrophysics Data System (ADS)

Ojo, A. A.; Dharmadasa, I. M.

2017-08-01

Ga-doped CdTe polycrystalline thin films were successfully electrodeposited on glass/fluorine doped tin oxide substrates from aqueous electrolytes containing cadmium nitrate (Cd(NO3)2·4H2O) and tellurium oxide (TeO2). The effects of different Ga-doping concentrations on the CdTe:Ga coupled with different post-growth treatments were studied by analysing the structural, optical, morphological and electronic properties of the deposited layers using x-ray diffraction (XRD), ultraviolet-visible spectrophotometry, scanning electron microscopy, photoelectrochemical cell measurement and direct-current conductivity test respectively. XRD results show diminishing (111)C CdTe peak above 20 ppm Ga-doping and the appearance of (301)M GaTe diffraction above 50 ppm Ga-doping indicating the formation of two phases; CdTe and GaTe. Although, reductions in the absorption edge slopes were observed above 20 ppm Ga-doping for the as-deposited CdTe:Ga layer, no obvious influence on the energy gap of CdTe films with Ga-doping were detected. Morphologically, reductions in grain size were observed at 50 ppm Ga-doping and above with high pinhole density within the layer. For the as-deposited CdTe:Ga layers, conduction type change from n- to p- were observed at 50 ppm, while the n-type conductivity were retained after post-growth treatment. Highest conductivity was observed at 20 ppm Ga-doping of CdTe. These results are systematically reported in this paper.

Thickness engineering of atomic layer deposited Al2O3 films to suppress interfacial reaction and diffusion of Ni/Au gate metal in AlGaN/GaN HEMTs up to 600 °C in air

NASA Astrophysics Data System (ADS)

Suria, Ateeq J.; Yalamarthy, Ananth Saran; Heuser, Thomas A.; Bruefach, Alexandra; Chapin, Caitlin A.; So, Hongyun; Senesky, Debbie G.

2017-06-01

In this paper, we describe the use of 50 nm atomic layer deposited (ALD) Al2O3 to suppress the interfacial reaction and inter-diffusion between the gate metal and semiconductor interface, to extend the operation limit up to 600 °C in air. Suppression of diffusion is verified through Auger electron spectroscopy (AES) depth profiling and X-ray diffraction (XRD) and is further supported with electrical characterization. An ALD Al2O3 thin film (10 nm and 50 nm), which functions as a dielectric layer, was inserted between the gate metal (Ni/Au) and heterostructure-based semiconductor material (AlGaN/GaN) to form a metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). This extended the 50 nm ALD Al2O3 MIS-HEMT (50-MIS) current-voltage (Ids-Vds) and gate leakage (Ig,leakage) characteristics up to 600 °C. Both, the 10 nm ALD Al2O3 MIS-HEMT (10-MIS) and HEMT, failed above 350 °C, as evidenced by a sudden increase of approximately 50 times and 5.3 × 106 times in Ig,leakage, respectively. AES on the HEMT revealed the formation of a Ni-Au alloy and Ni present in the active region. Additionally, XRD showed existence of metal gallides in the HEMT. The 50-MIS enables the operation of AlGaN/GaN based electronics in oxidizing high-temperature environments, by suppressing interfacial reaction and inter-diffusion of the gate metal with the semiconductor.

Electrical characteristics and thermal stability of n+ polycrystalline- Si/ZrO2/SiO2/Si metal-oxide-semiconductor capacitors

NASA Astrophysics Data System (ADS)

Lim, Kwan-Yong; Park, Dae-Gyu; Cho, Heung-Jae; Kim, Joong-Jung; Yang, Jun-Mo; Ii, Choi-Sang; Yeo, In-Seok; Park, Jin Won

2002-01-01

We have investigated the thermal stability of n+ polycrystalline-Si(poly-Si)/ZrO2(50-140 Å)/SiO2(7 Å)/p-Si metal-oxide-semiconductor (MOS) capacitors via electrical and material characterization. The ZrO2 gate dielectric was prepared by atomic layer chemical vapor deposition using ZrCl4 and H2O vapor. Capacitance-voltage hysteresis as small as ˜12 mV with the flatband voltage of -0.5 V and the interface trap density of ˜5×1010cm-2 eV-1 were attained with activation anneal at 750 °C. A high level of gate leakage current was observed at the activation temperatures over 750 °C and attributed to the interfacial reaction of poly-Si and ZrO2 during the poly-Si deposition and the following high temperature anneal. Because of this, the ZrO2 gate dielectric is incompatible with the conventional poly-Si gate process. In the MOS capacitors having a smaller active area (<50×50 μm2), fortunately, the electrical degradation by further severe silicidation does not occur up to an 800 °C anneal in N2 for 30 min.

Highly Mobile Two-Dimensional Electron Gases with a Strong Gating Effect at the Amorphous LaAlO3/KTaO3 Interface.

PubMed

Zhang, Hui; Zhang, Hongrui; Yan, Xi; Zhang, Xuejing; Zhang, Qinghua; Zhang, Jing; Han, Furong; Gu, Lin; Liu, Banggui; Chen, Yuansha; Shen, Baogen; Sun, Jirong

2017-10-18

Two-dimensional electron gas (2DEG) at the perovskite oxide interface exhibits a lot of exotic properties, presenting a promising platform for the exploration of emergent phenomena. While most of the previous works focused on SrTiO 3 -based 2DEG, here we report on the fabrication of high-quality 2DEGs by growing an amorphous LaAlO 3 layer on a (001)-orientated KTaO 3 substrate, which is a 5d metal oxide with a polar surface, at a high temperature that is usually adopted for crystalline LaAlO 3 . Metallic 2DEGs with a Hall mobility as high as ∼2150 cm 2 /(V s) and a sheet carrier density as low as 2 × 10 12 cm -2 are obtained. For the first time, the gating effect on the transport process is studied, and its influence on spin relaxation and inelastic and elastic scattering is determined. Remarkably, the spin relaxation time can be strongly tuned by a back gate. It is reduced by a factor of ∼69 while the gate voltage is swept from -25 to +100 V. The mechanism that dominates the spin relaxation is elucidated.

Properties of slow traps of ALD Al{sub 2}O{sub 3}/GeO{sub x}/Ge nMOSFETs with plasma post oxidation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ke, M., E-mail: kiramn@mosfet.t.u-tokyo.ac.jp; Yu, X.; Chang, C.

2016-07-18

The realization of Ge gate stacks with a small amount of slow trap density as well as thin equivalent oxide thickness and low interface state density (D{sub it}) is a crucial issue for Ge CMOS. In this study, we examine the properties of slow traps, particularly the location of slow traps, of Al{sub 2}O{sub 3}/GeO{sub x}/n-Ge and HfO{sub 2}/Al{sub 2}O{sub 3}/GeO{sub x}/n-Ge MOS interfaces with changing the process and structural parameters, formed by atomic layer deposition (ALD) of Al{sub 2}O{sub 3} and HfO{sub 2}/Al{sub 2}O{sub 3} combined with plasma post oxidation. It is found that the slow traps can locatemore » in the GeO{sub x} interfacial layer, not in the ALD Al{sub 2}O{sub 3} layer. Furthermore, we study the time dependence of channel currents in the Ge n-MOSFETs with 5-nm-thick Al{sub 2}O{sub 3}/GeO{sub x}/Ge gate stacks, with changing the thickness of GeO{sub x}, in order to further clarify the position of slow traps. The time dependence of the current drift and the effective time constant of slow traps do not change among the MOSFETs with the different thickness GeO{sub x}, demonstrating that the slow traps mainly exist near the interfaces between Ge and GeO{sub x}.« less

Large Area CVD MoS2 RF transistors with GHz performance

NASA Astrophysics Data System (ADS)

Nagavalli Yogeesh, Maruthi; Sanne, Atresh; Park, Saungeun; Akinwade, Deji; Banerjee, Sanjay

Molybdenum disulfide (MoS2) is a 2D semiconductor in the family of transition metal dichalcogenides (TMDs). Its single layer direct bandgap of 1.8 eV allows for high ION/IOFF metal-oxide semiconducting field-effect transistors (FETs). More relevant for radio frequency (RF) wireless applications, theoretical studies predict MoS2 to have saturation velocities, vsat >3×106 cm/s. Facilitated by cm-scale CVD MoS2, here we design and fabricate both top-gated and embedded gate short channel MoS2 RF transistors, and provide a systematic comparison of channel length scaling, extrinsic doping from oxygen-deficient dielectrics, and a gate-first gate-last process flow. The intrinsic fT (fmax) obtained from the embedded gate transistors shows 3X (2X) improvement over top-gated CVD MoS2 RF FETs, and the largest high-field saturation velocity, vsat = 1.88 ×106 cm/s, in MoS2 reported so far. The gate-first approach, offers enhancement mode operation, ION/IOFF ratio of 10, 8< and the highest reported transconductance (gm) of 70 μS/ μm. By manipulating the interfacial oxygen vacancies in atomic layer deposited (ALD) HfO2-x we are able to achieve 2X current density over stoichiometric Al2O3. We demonstrate a common-source (CS) amplifier with voltage gain of 14 dB and an active frequency mixer with conversion gain of -15 dB. Our results of gigahertz frequency performance as well as analog circuit operation show that large area CVD MoS2 may be suitable for industrial-scale electronic applications.

Electrode-stress-induced nanoscale disorder in Si quantum electronic devices

DOE PAGES

Park, J.; Ahn, Y.; Tilka, J. A.; ...

2016-06-20

Disorder in the potential-energy landscape presents a major obstacle to the more rapid development of semiconductor quantum device technologies. We report a large-magnitude source of disorder, beyond commonly considered unintentional background doping or fixed charge in oxide layers: nanoscale strain fields induced by residual stresses in nanopatterned metal gates. Quantitative analysis of synchrotron coherent hard x-ray nanobeam diffraction patterns reveals gate-induced curvature and strains up to 0.03% in a buried Si quantum well within a Si/SiGe heterostructure. Furthermore, electrode stress presents both challenges to the design of devices and opportunities associated with the lateral manipulation of electronic energy levels.

Layer-by-layer charging in non-volatile memory devices using embedded sub-2 nm platinum nanoparticles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ramalingam, Balavinayagam; Zheng, Haisheng; Gangopadhyay, Shubhra, E-mail: gangopadhyays@missouri.edu

In this work, we demonstrate multi-level operation of a non-volatile memory metal oxide semiconductor capacitor by controlled layer-by-layer charging of platinum nanoparticle (PtNP) floating gate devices with defined gate voltage bias ranges. The device consists of two layers of ultra-fine, sub-2 nm PtNPs integrated between Al{sub 2}O{sub 3} tunneling and separation layers. PtNP size and interparticle distance were varied to control the particle self-capacitance and associated Coulomb charging energy. Likewise, the tunneling layer thicknesses were also varied to control electron tunneling to the first and second PtNP layers. The final device configuration with optimal charging behavior and multi-level programming was attainedmore » with a 3 nm Al{sub 2}O{sub 3} initial tunneling layer, initial PtNP layer with particle size 0.54 ± 0.12 nm and interparticle distance 4.65 ± 2.09 nm, 3 nm Al{sub 2}O{sub 3} layer to separate the PtNP layers, and second particle layer with 1.11 ± 0.28 nm PtNP size and interparticle distance 2.75 ± 1.05 nm. In this device, the memory window of the first PtNP layer saturated over a programming bias range of 7 V to 14 V, after which the second PtNP layer starts charging, exhibiting a multi-step memory window with layer-by-layer charging.« less

Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation

NASA Astrophysics Data System (ADS)

Nogueira, Gabriel Leonardo; da Silva Ozório, Maiza; da Silva, Marcelo Marques; Morais, Rogério Miranda; Alves, Neri

2018-05-01

We report a process for performing the middle electrode for a vertical field effect transistor (VOFET) by the evaporation of a tin (Sn) layer. Bare aluminum oxide (Al2O3), obtained by anodization, and Al2O3 covered with a polymethylmethacrylate (PMMA) layer were used as the gate dielectric. We measured the electrical resistance of Sn while the evaporation was carried out to find the best condition to prepare the middle electrode, that is, good lateral conduction associated with openings that give permeability to the electric field in a vertical direction. This process showed that 55 nm Sn thick is suitable for use in a VOFET, being easier to achieve optimal thickness when the Sn is evaporated onto PMMA than onto bare Al2O3. The addition of a PMMA layer on the Al2O3 surface modifies the morphology of the Sn layer, resulting in a lowering of the threshold voltage. The values of threshold voltage and electric field, VTH = - 8 V and ETH = 354.5 MV/m respectively, were calculated using an Al2O3 film 20 nm thick covered with a 14 nm PMMA layer as gate dielectric, while for bare Al2O3 these values were VTH = - 10 V and ETH = 500 MV/m.

XPS-XRF hybrid metrology enabling FDSOI process

NASA Astrophysics Data System (ADS)

Hossain, Mainul; Subramanian, Ganesh; Triyoso, Dina; Wahl, Jeremy; Mcardle, Timothy; Vaid, Alok; Bello, A. F.; Lee, Wei Ti; Klare, Mark; Kwan, Michael; Pois, Heath; Wang, Ying; Larson, Tom

2016-03-01

Planar fully-depleted silicon-on-insulator (FDSOI) technology potentially offers comparable transistor performance as FinFETs. pFET FDOSI devices are based on a silicon germanium (cSiGe) layer on top of a buried oxide (BOX). Ndoped interfacial layer (IL), high-k (HfO2) layer and the metal gate stacks are then successively built on top of the SiGe layer. In-line metrology is critical in precisely monitoring the thickness and composition of the gate stack and associated underlying layers in order to achieve desired process control. However, any single in-line metrology technique is insufficient to obtain the thickness of IL, high-k, cSiGe layers in addition to Ge% and N-dose in one single measurement. A hybrid approach is therefore needed that combines the capabilities of more than one measurement technique to extract multiple parameters in a given film stack. This paper will discuss the approaches, challenges, and results associated with the first-in-industry implementation of XPS-XRF hybrid metrology for simultaneous detection of high-k thickness, IL thickness, N-dose, cSiGe thickness and %Ge, all in one signal measurement on a FDSOI substrate in a manufacturing fab. Strong correlation to electrical data for one or more of these measured parameters will also be presented, establishing the reliability of this technique.

2D Quantum Transport Modeling in Nanoscale MOSFETs

NASA Technical Reports Server (NTRS)

Svizhenko, Alexei; Anantram, M. P.; Govindan, T. R.; Biegel, Bryan

2001-01-01

With the onset of quantum confinement in the inversion layer in nanoscale MOSFETs, behavior of the resonant level inevitably determines all device characteristics. While most classical device simulators take quantization into account in some simplified manner, the important details of electrostatics are missing. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL, and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density- gradient and quantum-corrected MEDICI). We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions, oxide tunneling and phase-breaking scattering are treated on equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. Quantum simulations are focused on MIT 25, 50 and 90 nm "well- tempered" MOSFETs and compared to classical and quantum corrected models. The important feature of quantum model is smaller slope of Id-Vg curve and consequently higher threshold voltage. These results are quantitatively consistent with I D Schroedinger-Poisson calculations. The effect of gate length on gate-oxide leakage and sub-threshold current has been studied. The shorter gate length device has an order of magnitude smaller current at zero gate bias than the longer gate length device without a significant trade-off in on-current. This should be a device design consideration.

Method for disclosing invisible physical properties in metal-ferroelectric-insulator-semiconductor gate stacks

NASA Astrophysics Data System (ADS)

Sakai, Shigeki; Zhang, Wei; Takahashi, Mitsue

2017-04-01

In metal-ferroelectric-insulator-semiconductor gate stacks of ferroelectric-gate field effect transistors (FeFETs), it is impossible to directly obtain curves of polarization versus electric field (P f-E f) in the ferroelectric layer. The P f-E f behavior is not simple, i.e. the P f-E f curves are hysteretic and nonlinear, and the hysteresis curve width depends on the electric field scan amplitude. Unless the P f-E f relation is known, the field E f strength cannot be solved when the voltage is applied between the gate meal and the semiconductor substrate, and thus P f-E f cannot be obtained after all. In this paper, the method for disclosing the relationships among the polarization peak-to-peak amplitude (2P mm_av), the electric field peak-to-peak amplitude (2E mm_av), and the memory window (E w) in units of the electric field is presented. To get P mm_av versus E mm_av, FeFETs with different ferroelectric-layer thicknesses should be prepared. Knowing such essential physical parameters is helpful and in many cases enough to quantitatively understand the behavior of FeFETs. The method is applied to three groups. The first one consists of SrBi2Ta2O9-based FeFETs. The second and third ones consist of Ca x Sr1-x Bi2Ta2O9-based FeFETs made by two kinds of annealing. The method can clearly differentiate the characters of the three groups. By applying the method, ferroelectric relationships among P mm_av, E mm_av, and E w are well classified in the three groups according to the difference of the material kinds and the annealing conditions. The method also evaluates equivalent oxide thickness (EOT) of a dual layer of a deposited high-k insulator and a thermally-grown SiO2-like interfacial layer (IL). The IL thickness calculated by the method is consistent with cross-sectional image of the FeFETs observed by a transmission electron microscope. The method successfully discloses individual characteristics of the ferroelectric and the insulator layers hidden in the gate stack of a FeFET.

Highly improved photo-induced bias stability of sandwiched triple layer structure in sol-gel processed fluorine-doped indium zinc oxide thin film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Dongha; Park, Hyungjin; Bae, Byeong-Soo, E-mail: bsbae@kaist.ac.kr

In order to improve the reliability of TFT, an Al{sub 2}O{sub 3} insulating layer is inserted between active fluorine doped indium zinc oxide (IZO:F) thin films to form a sandwiched triple layer. All the thin films were fabricated via low-cost sol-gel process. Due to its large energy bandgap and high bonding energy with oxygen atoms, the Al{sub 2}O{sub 3} layer acts as a photo-induced positive charge blocking layer that effectively blocks the migration of both holes and V {sub o}{sup 2+} toward the interface between the gate insulator and the semiconductor. The inserted Al{sub 2}O{sub 3} triple layer exhibits amore » noticeably low turn on voltage shift of −0.7 V under NBIS as well as the good TFT performance with a mobility of 10.9 cm{sup 2}/V ⋅ s. We anticipate that this approach can be used to solve the stability issues such as NBIS, which is caused by inescapable oxygen vacancies.« less

Fabrication of Stretchable Organic-Inorganic Hybrid Thin-Film Transistors on Polyimide Stiff-Island Structures.

PubMed

Jung, Soon-Won; Koo, Jae Bon; Park, Chan Woo; Na, Bock Soon; Oh, Ji-Young; Lee, Sang Seok

2015-10-01

In this study, stretchable organic-inorganic hybrid thin-film transistors (TFTs) are fabricated on a polyimide (PI) stiff-island/elastomer substrate using blends of poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] and poly(methyl methacrylate) (PMMA) and oxide semiconductor In-Ga-Zn-O as the gate dielectric and semiconducting layer, respectively. Carrier mobility, Ion/Ioff ratio, and subthreshold swing (SS) values of 6.1 cm2 V(-1) s(-1), 10(7), and 0.2 V/decade, respectively, were achieved. For the hybrid TFTs, the endurable maximum strain without degradation of electrical properties was approximately 49%. These results correspond to those obtained in the first study on fabrication of stretchable hybrid-type TFTs on elastomer substrate using an organic gate insulator and oxide semiconducting active channel structure, thus indicating the feasibility of a promising device for stretchable electronic systems.

Defect generation in amorphous-indium-gallium-zinc-oxide thin-film transistors by positive bias stress at elevated temperature

DOE Office of Scientific and Technical Information (OSTI.GOV)

Um, Jae Gwang; Mativenga, Mallory; Jang, Jin, E-mail: jjang@khu.ac.kr

2014-04-07

We report on the generation and characterization of a hump in the transfer characteristics of amorphous indium gallium zinc-oxide thin-film transistors by positive bias temperature stress. The hump depends strongly on the gate bias stress at 100 °C. Due to the hump, the positive shift of the transfer characteristic in deep depletion is always smaller that in accumulation. Since, the latter shift is twice the former, with very good correlation, we conclude that the effect is due to creation of a double acceptor, likely to be a cation vacancy. Our results indicate that these defects are located near the gate insulator/activemore » layer interface, rather than in the bulk. Migration of donor defects from the interface towards the bulk may also occur under PBST at 100 °C.« less

Thermal oxidation of Si/SiGe heterostructures for use in quantum dot qubits

NASA Astrophysics Data System (ADS)

Neyens, Samuel F.; Foote, Ryan H.; Knapp, T. J.; McJunkin, Thomas; Savage, D. E.; Lagally, M. G.; Coppersmith, S. N.; Eriksson, M. A.

Here we demonstrate dry thermal oxidation of a Si/SiGe heterostructure at 700°C and use a Hall bar device to measure the mobility after oxidation to be 43,000 cm2V-1s-1 at a carrier density of 4.1 ×1011 cm-2. Surprisingly, we find no significant reduction in mobility compared with an Al2O3 device made with atomic layer deposition on the same heterostructure, indicating thermal oxidation can be used to process Si/SiGe quantum dot devices. This result provides a path for investigating improvements to the gate oxide in Si/SiGe qubit devices, whose performance is believed to be limited by charge noise in the oxide layer. This work was supported in part by ARO (W911NF-12-0607) and NSF (DMR-1206915 and PHY-1104660). Development and maintenance of the growth facilities used for fabricating samples is supported by DOE (DE-FG02-03ER46028). This research utilized NSF-supported shared facilities at the University of Wisconsin-Madison.

Oxygen and carbon dioxide sensing

NASA Technical Reports Server (NTRS)

Ren, Fan (Inventor); Pearton, Stephen John (Inventor)

2012-01-01

A high electron mobility transistor (HEMT) capable of performing as a CO.sub.2 or O.sub.2 sensor is disclosed, hi one implementation, a polymer solar cell can be connected to the HEMT for use in an infrared detection system. In a second implementation, a selective recognition layer can be provided on a gate region of the HEMT. For carbon dioxide sensing, the selective recognition layer can be, in one example, PEI/starch. For oxygen sensing, the selective recognition layer can be, in one example, indium zinc oxide (IZO). In one application, the HEMTs can be used for the detection of carbon dioxide and oxygen in exhaled breath or blood.

The Development of III-V Semiconductor MOSFETs for Future CMOS Applications

NASA Astrophysics Data System (ADS)

Greene, Andrew M.

Alternative channel materials with superior transport properties over conventional strained silicon are required for supply voltage scaling in low power complementary metal-oxide-semiconductor (CMOS) integrated circuits. Group III-V compound semiconductor systems offer a potential solution due to their high carrier mobility, low carrier effective mass and large injection velocity. The enhancement in transistor drive current at a lower overdrive voltage allows for the scaling of supply voltage while maintaining high switching performance. This thesis focuses on overcoming several material and processing challenges associated with III-V semiconductor development including a low thermal processing budget, high interface trap state density (Dit), low resistance source/drain contacts and growth on lattice mismatched substrates. Non-planar In0.53Ga0.47As FinFETs were developed using both "gate-first" and "gate-last" fabrication methods for n-channel MOSFETs. Electron beam lithography and anisotropic plasma etching processes were optimized to create highly scaled fins with near vertical sidewalls. Plasma damage was removed using a wet etch process and improvements in gate efficiency were characterized on MOS capacitor structures. A two-step, selective removal of the pre-grown n+ contact layer was developed for "gate-last" recess etching. The final In0.53Ga 0.47As FinFET devices demonstrated an ION = 70 mA/mm, I ON/IOFF ratio = 15,700 and sub-threshold swing = 210 mV/dec. Bulk GaSb and strained In0.36Ga0.64Sb quantum well (QW) heterostructures were developed for p-channel MOSFETs. Dit was reduced to 2 - 3 x 1012 cm-2eV-1 using an InAs surface layer, (NH4)2S passivation and atomic layer deposition (ALD) of Al2O3. A self-aligned "gate-first" In0.36Ga0.64Sb MOSFET fabrication process was invented using a "T-shaped" electron beam resist patterning stack and intermetallic source/drain contacts. Ni contacts annealed at 300°C demonstrated an ION = 166 mA/mm, ION/IOFF ratio = 1,500 and sub-threshold swing = 340 mV/dec. Split C-V measurements were used to extract an effective channel mobility of muh* = 300 cm2/Vs at Ns = 2 x 1012 cm -2. "Gate-last" MOSFETs grown with an epitaxial p + contact layer were fabricated using selective gate-recess etching techniques. A parasitic "n-channel" limited ION/I OFF ratio and sub-threshold swing, most likely due to effects from the InAs surface layer.

Low temperature growth and electrical characterization of insulators for GaAs MISFETS

NASA Technical Reports Server (NTRS)

Borrego, J. M.; Ghandhi, S. K.

1981-01-01

Progress in the low temperature growth of oxides and layers on GaAs and the detailed electrical characterization of these oxides is reported. A plasma anodization system was designed, assembled, and put into operation. A measurement system was assembled for determining capacitance and conductance as a function of gate voltage for frequencies in the range from 1 Hz to 1 MHz. Initial measurements were carried out in Si-SiO2 capacitors in order to test the system and in GaAs MIS capacitors abricated using liquid anodization.

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.

2013-11-25

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Voltage controlled spintronic devices for logic applications

DOEpatents

You, Chun-Yeol; Bader, Samuel D.

2001-01-01

A reprogrammable logic gate comprising first and second voltage-controlled rotation transistors. Each transistor comprises three ferromagnetic layers with a spacer and insulating layer between the first and second ferromagnetic layers and an additional insulating layer between the second and third ferromagnetic layers. The third ferromagnetic layer of each transistor is connected to each other, and a constant external voltage source is applied to the second ferromagnetic layer of the first transistor. As input voltages are applied to the first ferromagnetic layer of each transistor, the relative directions of magnetization of the ferromagnetic layers and the magnitude of the external voltage determines the output voltage of the gate. By altering these parameters, the logic gate is capable of behaving as AND, OR, NAND, or NOR gates.

Multifunctional Hybrid Multilayer Gate Dielectrics with Tunable Surface Energy for Ultralow-Power Organic and Amorphous Oxide Thin-Film Transistors.

PubMed

Byun, Hye-Ran; You, Eun-Ah; Ha, Young-Geun

2017-03-01

For large-area, printable, and flexible electronic applications using advanced semiconductors, novel dielectric materials with excellent capacitance, insulating property, thermal stability, and mechanical flexibility need to be developed to achieve high-performance, ultralow-voltage operation of thin-film transistors (TFTs). In this work, we first report on the facile fabrication of multifunctional hybrid multilayer gate dielectrics with tunable surface energy via a low-temperature solution-process to produce ultralow-voltage organic and amorphous oxide TFTs. The hybrid multilayer dielectric materials are constructed by iteratively stacking bifunctional phosphonic acid-based self-assembled monolayers combined with ultrathin high-k oxide layers. The nanoscopic thickness-controllable hybrid dielectrics exhibit the superior capacitance (up to 970 nF/cm 2 ), insulating property (leakage current densities <10 -7 A/cm 2 ), and thermal stability (up to 300 °C) as well as smooth surfaces (root-mean-square roughness <0.35 nm). In addition, the surface energy of the hybrid multilayer dielectrics are easily changed by switching between mono- and bifunctional phosphonic acid-based self-assembled monolayers for compatible fabrication with both organic and amorphous oxide semiconductors. Consequently, the hybrid multilayer dielectrics integrated into TFTs reveal their excellent dielectric functions to achieve high-performance, ultralow-voltage operation (< ± 2 V) for both organic and amorphous oxide TFTs. Because of the easily tunable surface energy, the multifunctional hybrid multilayer dielectrics can also be adapted for various organic and inorganic semiconductors, and metal gates in other device configurations, thus allowing diverse advanced electronic applications including ultralow-power and large-area electronic devices.

Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al{sub 2}O{sub 3} gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Aoki, Takeshi, E-mail: aokit@sc.sumitomo-chem.co.jp; Fukuhara, Noboru; Osada, Takenori

2015-08-15

This paper presents a compressive study on the fabrication and optimization of GaAs metal–oxide–semiconductor (MOS) structures comprising a Al{sub 2}O{sub 3} gate oxide, deposited via atomic layer deposition (ALD), with an AlN interfacial passivation layer prepared in situ via metal–organic chemical vapor deposition (MOCVD). The established protocol afforded self-limiting growth of Al{sub 2}O{sub 3} in the atmospheric MOCVD reactor. Consequently, this enabled successive growth of MOCVD-formed AlN and ALD-formed Al{sub 2}O{sub 3} layers on the GaAs substrate. The effects of AlN thickness, post-deposition anneal (PDA) conditions, and crystal orientation of the GaAs substrate on the electrical properties of the resultingmore » MOS capacitors were investigated. Thin AlN passivation layers afforded incorporation of optimum amounts of nitrogen, leading to good capacitance–voltage (C–V) characteristics with reduced frequency dispersion. In contrast, excessively thick AlN passivation layers degraded the interface, thereby increasing the interfacial density of states (D{sub it}) near the midgap and reducing the conduction band offset. To further improve the interface with the thin AlN passivation layers, the PDA conditions were optimized. Using wet nitrogen at 600 °C was effective to reduce D{sub it} to below 2 × 10{sup 12} cm{sup −2} eV{sup −1}. Using a (111)A substrate was also effective in reducing the frequency dispersion of accumulation capacitance, thus suggesting the suppression of traps in GaAs located near the dielectric/GaAs interface. The current findings suggest that using an atmosphere ALD process with in situ AlN passivation using the current MOCVD system could be an efficient solution to improving GaAs MOS interfaces.« less

High performance multi-finger MOSFET on SOI for RF amplifiers

NASA Astrophysics Data System (ADS)

Adhikari, M. Singh; Singh, Y.

2017-10-01

In this paper, we propose structural modifications in the conventional planar metal-oxide-semiconductor field-effect transistor (MOSFET) on silicon-on-insulator by utilizing trenches in the epitaxial layer. The proposed multi-finger MOSFET (MF-MOSFET) has dual vertical-gates placed in separate trenches to form multiple channels in the p-base which carry the drain current in parallel. The proposed device uses TaN as gate electrode and SiO2 as gate dielectric. Simultaneous conduction of multiple channels enhances the drain current (ID) and provides higher transconductance (gm) leading to significant improvement in cut-off frequency (ft). Two-dimensional simulations are performed to evaluate and compare the performance of the MF-MOSFET with the conventional MOSFET. At a gate length of 60 nm, the proposed device provides 4 times higher ID, 3 times improvement in gm and 1.25 times increase in ft with better control over the short channel effects as compared with the conventional device.

Review of recent progresses on flexible oxide semiconductor thin film transistors based on atomic layer deposition processes

NASA Astrophysics Data System (ADS)

Sheng, Jiazhen; Han, Ki-Lim; Hong, TaeHyun; Choi, Wan-Ho; Park, Jin-Seong

2018-01-01

The current article is a review of recent progress and major trends in the field of flexible oxide thin film transistors (TFTs), fabricating with atomic layer deposition (ALD) processes. The ALD process offers accurate controlling of film thickness and composition as well as ability of achieving excellent uniformity over large areas at relatively low temperatures. First, an introduction is provided on what is the definition of ALD, the difference among other vacuum deposition techniques, and the brief key factors of ALD on flexible devices. Second, considering functional layers in flexible oxide TFT, the ALD process on polymer substrates may improve device performances such as mobility and stability, adopting as buffer layers over the polymer substrate, gate insulators, and active layers. Third, this review consists of the evaluation methods of flexible oxide TFTs under various mechanical stress conditions. The bending radius and repetition cycles are mostly considering for conventional flexible devices. It summarizes how the device has been degraded/changed under various stress types (directions). The last part of this review suggests a potential of each ALD film, including the releasing stress, the optimization of TFT structure, and the enhancement of device performance. Thus, the functional ALD layers in flexible oxide TFTs offer great possibilities regarding anti-mechanical stress films, along with flexible display and information storage application fields. Project supported by the National Research Foundation of Korea (NRF) (No. NRF-2017R1D1A1B03034035), the Ministry of Trade, Industry & Energy (No. #10051403), and the Korea Semiconductor Research Consortium.

Highly reliable top-gated thin-film transistor memory with semiconducting, tunneling, charge-trapping, and blocking layers all of flexible polymers.

PubMed

Wang, Wei; Hwang, Sun Kak; Kim, Kang Lib; Lee, Ju Han; Cho, Suk Man; Park, Cheolmin

2015-05-27

The core components of a floating-gate organic thin-film transistor nonvolatile memory (OTFT-NVM) include the semiconducting channel layer, tunneling layer, floating-gate layer, and blocking layer, besides three terminal electrodes. In this study, we demonstrated OTFT-NVMs with all four constituent layers made of polymers based on consecutive spin-coating. Ambipolar charges injected and trapped in a polymer electret charge-controlling layer upon gate program and erase field successfully allowed for reliable bistable channel current levels at zero gate voltage. We have observed that the memory performance, in particular the reliability of a device, significantly depends upon the thickness of both blocking and tunneling layers, and with an optimized layer thickness and materials selection, our device exhibits a memory window of 15.4 V, on/off current ratio of 2 × 10(4), read and write endurance cycles over 100, and time-dependent data retention of 10(8) s, even when fabricated on a mechanically flexible plastic substrate.

Thick layered semiconductor devices with water top-gates: High on-off ratio field-effect transistors and aqueous sensors.

PubMed

Huang, Yuan; Sutter, Eli; Wu, Liangmei; Xu, Hong; Bao, Lihong; Gao, Hong-Jun; Zhou, Xingjiang; Sutter, Peter

2018-06-21

Layered semiconductors show promise as channel materials for field-effect transistors (FETs). Usually, such devices incorporate solid back or top gate dielectrics. Here, we explore de-ionized (DI) water as a solution top gate for field-effect switching of layered semiconductors including SnS2, MoS2, and black phosphorus. The DI water gate is easily fabricated, can sustain rapid bias changes, and its efficient coupling to layered materials provides high on-off current ratios, near-ideal sub-threshold swing, and enhanced short-channel behavior even for FETs with thick, bulk-like channels where such control is difficult to realize with conventional back-gating. Screening by the high-k solution gate eliminates hysteresis due to surface and interface trap states and substantially enhances the field-effect mobility. The onset of water electrolysis sets the ultimate limit to DI water gating at large negative gate bias. Measurements in this regime show promise for aqueous sensing, demonstrated here by the amperometric detection of glucose in aqueous solution. DI water gating of layered semiconductors can be harnessed in research on novel materials and devices, and it may with further development find broad applications in microelectronics and sensing.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states atmore » the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Seo, Jooyeok; Lee, Chulyeon; Han, Hyemi

We report a tactile touch sensor based on a planar liquid crystal-gated-organic field-effect transistor (LC-g-OFET) structure. The LC-g-OFET touch sensors were fabricated by forming the 10 μm thick LC layer (4-cyano-4{sup ′}-pentylbiphenyl - 5CB) on top of the 50 nm thick channel layer (poly(3-hexylthiophene) - P3HT) that is coated on the in-plane aligned drain/source/gate electrodes (indium-tin oxide - ITO). As an external physical stimulation to examine the tactile touch performance, a weak nitrogen flow (83.3 μl/s) was employed to stimulate the LC layer of the touch device. The LC-g-OFET device exhibited p-type transistor characteristics with a hole mobility of 1.5more » cm{sup 2}/Vs, but no sensing current by the nitrogen flow touch was measured at sufficiently high drain (V{sub D}) and gate (V{sub G}) voltages. However, a clear sensing current signal was detected at lower voltages, which was quite sensitive to the combination of V{sub D} and V{sub G}. The best voltage combination was V{sub D} = −0.2 V and V{sub G} = −1 V for the highest ratio of signal currents to base currents (i.e., signal-to-noise ratio). The change in the LC alignment upon the nitrogen flow touch was assigned as the mechanism for the present LC-g-OFET touch sensors.« less

Electrical Properties of Ultrathin Hf-Ti-O Higher k Gate Dielectric Films and Their Application in ETSOI MOSFET.

PubMed

Xiong, Yuhua; Chen, Xiaoqiang; Wei, Feng; Du, Jun; Zhao, Hongbin; Tang, Zhaoyun; Tang, Bo; Wang, Wenwu; Yan, Jiang

2016-12-01

Ultrathin Hf-Ti-O higher k gate dielectric films (~2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) ~9.4%, low equivalent gate oxide thickness (EOT) of ~0.69 nm and acceptable gate leakage current density of 0.61 A/cm 2 @ (V fb  - 1)V could be obtained. The conduction mechanism through the gate dielectric is dominated by the F-N tunneling in the gate voltage range of -0.5 to -2 V. Under the same physical thickness and process flow, lower EOT and higher I on /I off ratio could be obtained while using Hf-Ti-O as gate dielectric compared with HfO 2 . With Hf-Ti-O as gate dielectric, two ETSOI PMOSFETs with gate width/gate length (W/L) of 0.5 μm/25 nm and 3 μm/40 nm show good performances such as high I on , I on /I off ratio in the magnitude of 10 5 , and peak transconductance, as well as suitable threshold voltage (-0.3~-0.2 V). Particularly, ETSOI PMOSFETs show superior short-channel control capacity with DIBL <82 mV/V and subthreshold swing <70 mV/decade.

Improvement of Ion/Ioff for h-BN encapsulated bilayer graphene by graphite local back gate electrode

NASA Astrophysics Data System (ADS)

Uwanno, Teerayut; Taniguchi, Takashi; Watanabe, Kenji; Nagashio, Kosuke

The critical issue for bilayer graphene (BLG) devices is low Ion/Ioff even at the band gap of 0.3eV. Band gap in BLG can be formed by creating potential difference between the two layers of BLG. This can be done by applying external electric field perpendicularly to BLG to induce different carrier densities in the two layers. Due to such origin, the spatial uniformity of band gap in the channel is quite sensitive to charge inhomogeneity in BLG. In order to apply electric field of 3V/nm to open the maximum band gap of 0.3eV, high- k gate stack has been utilized so far. However, oxide dielectrics usually have large charge inhomogeneity causing in-plane potential fluctuation in BLG channel. Due to surface flatness and small charge inhomogeneity, h-BN has been used as dielectrics to achieve high quality graphene devices, however, Ion/Iofffor BLG/ h-BN heterostuctures has not been reported yet. In this study, we used graphite as local back gate electrode to BLG encapsulated with h-BN. This resulted in much higher Ion/Ioff, indicating the importance of screening of charge inhomogeneity from SiO2 substrate surface by local graphite back gate electrode. This research was partly supported by JSPS Core-to-Core Program, A. Advanced Research Networks.

Al{sub 2}O{sub 3}/GeO{sub x} gate stack on germanium substrate fabricated by in situ cycling ozone oxidation method

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Xu; Zeng, Zhen-Hua; Microwave Device and IC Department, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029

2014-09-01

Al{sub 2}O{sub 3}/GeO{sub x}/Ge gate stack fabricated by an in situ cycling ozone oxidation (COO) method in the atomic layer deposition (ALD) system at low temperature is systematically investigated. Excellent electrical characteristics such as minimum interface trap density as low as 1.9 × 10{sup 11 }cm{sup −2 }eV{sup −1} have been obtained by COO treatment. The impact of COO treatment against the band alignment of Al{sub 2}O{sub 3} with respect to Ge is studied by x-ray photoelectron spectroscopy (XPS) and spectroscopic ellipsometry (SE). Based on both XPS and SE studies, the origin of gate leakage in the ALD-Al{sub 2}O{sub 3} is attributed to themore » sub-gap states, which may be correlated to the OH-related groups in Al{sub 2}O{sub 3} network. It is demonstrated that the COO method is effective in repairing the OH-related defects in high-k dielectrics as well as forming superior high-k/Ge interface for high performance Ge MOS devices.« less

pH sensing characteristics and biosensing application of solution-gated reduced graphene oxide field-effect transistors.

PubMed

Sohn, Il-Yung; Kim, Duck-Jin; Jung, Jin-Heak; Yoon, Ok Ja; Thanh, Tien Nguyen; Quang, Trung Tran; Lee, Nae-Eung

2013-07-15

Solution-gated reduced graphene oxide field-effect transistors (R-GO FETs) were investigated for pH sensing and biochemical sensing applications. A channel of a networked R-GO film formed by self-assembly was incorporated as a sensing layer into a solution-gated FET structure for pH sensing and the detection of acetylcholine (Ach), which is a neurotransmitter in the nerve system, through enzymatic reactions. The fabricated R-GO FET was sensitive to protons (H(+)) with a pH sensitivity of 29 mV/pH in terms of the shift of the charge neutrality point (CNP), which is attributed to changes in the surface potential caused by the interaction of protons with OH surface functional groups present on the R-GO surface. The R-GO FET immobilized with acetylcholinesterase (AchE) was used to detect Ach in the concentration range of 0.1-10mM by sensing protons generated during the enzymatic reactions. The results indicate that R-GO FETs provide the capability to detect protons, demonstrating their applicability as a biosensing device for enzymatic reactions. Copyright © 2013 Elsevier B.V. All rights reserved.

Impacts of oxidants in atomic layer deposition method on Al2O3/GaN interface properties

NASA Astrophysics Data System (ADS)

Taoka, Noriyuki; Kubo, Toshiharu; Yamada, Toshikazu; Egawa, Takashi; Shimizu, Mitsuaki

2018-01-01

The electrical interface properties of GaN metal-oxide-semiconductor (MOS) capacitors with an Al2O3 gate insulator formed by atomic layer deposition method using three kinds of oxidants were investigated by the capacitance-voltage technique, Terman method, and conductance method. We found that O3 and the alternate supply of H2O and O3 (AS-HO) are effective for reducing the interface trap density (D it) at the energy range of 0.15 to 0.30 eV taking from the conduction band minimum. On the other hand, we found that surface potential fluctuation (σs) induced by interface charges for the AS-HO oxidant is much larger than that for a Si MOS capacitor with a SiO2 layer formed by chemical vapor deposition despite the small D it values for the AS-HO oxidant compared with the Si MOS capacitor. This means that the total charged center density including the fixed charge density, charged slow trap density, and charged interface trap density for the GaN MOS capacitor is higher than that for the Si MOS capacitor. Therefore, σs has to be reduced to improve the performances and reliability of GaN devices with the Al2O3/GaN interfaces.

Directed-Assembly of Carbon Nanotubes on Soft Substrates for Flexible Biosensor Array

NASA Astrophysics Data System (ADS)

Lee, Hyoung Woo; Koh, Juntae; Lee, Byung Yang; Kim, Tae Hyun; Lee, Joohyung; Hong, Seunghun; Yi, Mihye; Jhon, Young Min

2009-03-01

We developed a method to selectively assemble and align carbon nanotubes (CNTs) on soft substrates for flexible biosensors. In this strategy, thin oxide layer was deposited on soft substrates via low temperature plasma enhanced chemical vapor deposition, and linker-free assembly process was applied onto the oxide surface where the assembly of carbon nanotubes was guided by methyl-terminated molecular patterns on the oxide surface. The electrical characterization of the fabricated CNT devices exhibited typical p-type gating effect and 1/f noise behavior. The bare oxide regions near CNTs were functionalized with glutamate oxidase to fabricate selective biosensors to detect two forms of glutamate substances existing in different situations: L-glutamic acid, a neuro-transmitting material, and monosodium glutamate, a food additive.

Single crystal functional oxides on silicon

PubMed Central

Bakaul, Saidur Rahman; Serrao, Claudy Rayan; Lee, Michelle; Yeung, Chun Wing; Sarker, Asis; Hsu, Shang-Lin; Yadav, Ajay Kumar; Dedon, Liv; You, Long; Khan, Asif Islam; Clarkson, James David; Hu, Chenming; Ramesh, Ramamoorthy; Salahuddin, Sayeef

2016-01-01

Single-crystalline thin films of complex oxides show a rich variety of functional properties such as ferroelectricity, piezoelectricity, ferro and antiferromagnetism and so on that have the potential for completely new electronic applications. Direct synthesis of such oxides on silicon remains challenging because of the fundamental crystal chemistry and mechanical incompatibility of dissimilar interfaces. Here we report integration of thin (down to one unit cell) single crystalline, complex oxide films onto silicon substrates, by epitaxial transfer at room temperature. In a field-effect transistor using a transferred lead zirconate titanate layer as the gate insulator, we demonstrate direct reversible control of the semiconductor channel charge with polarization state. These results represent the realization of long pursued but yet to be demonstrated single-crystal functional oxides on-demand on silicon. PMID:26853112

Depletion-mode vertical Ga2O3 trench MOSFETs fabricated using Ga2O3 homoepitaxial films grown by halide vapor phase epitaxy

NASA Astrophysics Data System (ADS)

Sasaki, Kohei; Thieu, Quang Tu; Wakimoto, Daiki; Koishikawa, Yuki; Kuramata, Akito; Yamakoshi, Shigenobu

2017-12-01

We developed depletion-mode vertical Ga2O3 trench metal-oxide-semiconductor field-effect transistors by using n+ contact and n- drift layers. These epilayers were grown on an n+ (001) Ga2O3 single-crystal substrate by halide vapor phase epitaxy. Cu and HfO2 were used for the gate metal and dielectric film, respectively. The mesa width and gate length were approximately 2 and 1 µm, respectively. The devices showed good DC characteristics, with a specific on-resistance of 3.7 mΩ cm2 and clear current modulation. An on-off ratio of approximately 103 was obtained.

Bias temperature instability in tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Mizubayashi, Wataru; Mori, Takahiro; Fukuda, Koichi; Ishikawa, Yuki; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Liu, Yongxun; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Matsukawa, Takashi; Masahara, Meishoku; Endo, Kazuhiko

2017-04-01

We systematically investigated the bias temperature instability (BTI) of tunnel field-effect transistors (TFETs). The positive BTI and negative BTI mechanisms in TFETs are the same as those in metal-oxide-semiconductor FETs (MOSFETs). In TFETs, although traps are generated in high-k gate dielectrics by the bias stress and/or the interface state is degraded at the interfacial layer/channel interface, the threshold voltage (V th) shift due to BTI degradation is caused by the traps and/or the degradation of the interface state locating the band-to-band tunneling (BTBT) region near the source/gate edge. The BTI lifetime in n- and p-type TFETs is improved by applying a drain bias corresponding to the operation conditions.

2D Quantum Mechanical Study of Nanoscale MOSFETs

NASA Technical Reports Server (NTRS)

Svizhenko, Alexei; Anantram, M. P.; Govindan, T. R.; Biegel, B.; Kwak, Dochan (Technical Monitor)

2000-01-01

With the onset of quantum confinement in the inversion layer in nanoscale MOSFETs, behavior of the resonant level inevitably determines all device characteristics. While most classical device simulators take quantization into account in some simplified manner, the important details of electrostatics are missing. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL, and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density-gradient and quantum-corrected MEDICI). We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions and oxide tunneling are treated on an equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. We present the results of our simulations of MIT 25, 50 and 90 nm "well-tempered" MOSFETs and compare them to those of classical and quantum corrected models. The important feature of quantum model is smaller slope of Id-Vg curve and consequently higher threshold voltage. Surprisingly, the self-consistent potential profile shows lower injection barrier in the channel in quantum case. These results are qualitatively consistent with ID Schroedinger-Poisson calculations. The effect of gate length on gate-oxide leakage and subthreshold current has been studied. The shorter gate length device has an order of magnitude smaller current at zero gate bias than the longer gate length device without a significant trade-off in on-current. This should be a device design consideration.

Role of Oxygen in Ionic Liquid Gating on Two-Dimensional Cr2Ge2Te6: A Non-oxide Material.

PubMed

Chen, Yangyang; Xing, Wenyu; Wang, Xirui; Shen, Bowen; Yuan, Wei; Su, Tang; Ma, Yang; Yao, Yunyan; Zhong, Jiangnan; Yun, Yu; Xie, X C; Jia, Shuang; Han, Wei

2018-01-10

Ionic liquid gating can markedly modulate a material's carrier density so as to induce metallization, superconductivity, and quantum phase transitions. One of the main issues is whether the mechanism of ionic liquid gating is an electrostatic field effect or an electrochemical effect, especially for oxide materials. Recent observation of the suppression of the ionic liquid gate-induced metallization in the presence of oxygen for oxide materials suggests the electrochemical effect. However, in more general scenarios, the role of oxygen in the ionic liquid gating effect is still unclear. Here, we perform ionic liquid gating experiments on a non-oxide material: two-dimensional ferromagnetic Cr 2 Ge 2 Te 6 . Our results demonstrate that despite the large increase of the gate leakage current in the presence of oxygen, the oxygen does not affect the ionic liquid gating effect on  the channel resistance of Cr 2 Ge 2 Te 6 devices (<5% difference), which suggests the electrostatic field effect as the mechanism on non-oxide materials. Moreover, our results show that ionic liquid gating is more effective on the modulation of the channel resistances compared to the back gating across the 300 nm thick SiO 2 .

Mechanistic analysis of temperature-dependent current conduction through thin tunnel oxide in n+-polySi/SiO2/n+-Si structures

NASA Astrophysics Data System (ADS)

Samanta, Piyas

2017-09-01

We present a detailed investigation on temperature-dependent current conduction through thin tunnel oxides grown on degenerately doped n-type silicon (n+-Si) under positive bias ( VG ) on heavily doped n-type polycrystalline silicon (n+-polySi) gate in metal-oxide-semiconductor devices. The leakage current measured between 298 and 573 K and at oxide fields ranging from 6 to 10 MV/cm is primarily attributed to Poole-Frenkel (PF) emission of trapped electrons from the neutral electron traps located in the silicon dioxide (SiO2) band gap in addition to Fowler-Nordheim (FN) tunneling of electrons from n+-Si acting as the drain node in FLOating gate Tunnel OXide Electrically Erasable Programmable Read-Only Memory devices. Process-induced neutral electron traps are located at 0.18 eV and 0.9 eV below the SiO2 conduction band. Throughout the temperature range studied here, PF emission current IPF dominates FN electron tunneling current IFN at oxide electric fields Eox between 6 and 10 MV/cm. A physics based new analytical formula has been developed for FN tunneling of electrons from the accumulation layer of degenerate semiconductors at a wide range of temperatures incorporating the image force barrier rounding effect. FN tunneling has been formulated in the framework of Wentzel-Kramers-Brilloiun taking into account the correction factor due to abrupt variation of the energy barrier at the cathode/oxide interface. The effect of interfacial and near-interfacial trapped-oxide charges on FN tunneling has also been investigated in detail at positive VG . The mechanism of leakage current conduction through SiO2 films plays a crucial role in simulation of time-dependent dielectric breakdown of the memory devices and to precisely predict the normal operating field or applied floating gate (FG) voltage for lifetime projection of the devices. In addition, we present theoretical results showing the effect of drain doping concentration on the FG leakage current.

37 CFR 211.4 - Registration of claims of protection in mask works.

Code of Federal Regulations, 2010 CFR

2010-07-01

... adding metal-connection layers to unpersonalized gate arrays may separately register the entire unpersonalized gate array and the custom metallization layers. Applicants seeking to register separately entire unpersonalized gate arrays or custom metallization layers should make the nature of their claim clear at Space 8...

Effect of mesa structure formation on the electrical properties of zinc oxide thin film transistors.

PubMed

Singh, Shaivalini; Chakrabarti, P

2014-05-01

ZnO based bottom-gate thin film transistor (TFT) with SiO2 as insulating layer has been fabricated with two different structures. The effect of formation of mesa structure on the electrical characteristics of the TFTs has been studied. The formation of mesa structure of ZnO channel region can definitely result in better control over channel region and enhance value of channel mobility of ZnO TFT. As a result, by fabricating a mesa structured TFT, a better value of mobility and on-state current are achieved at low voltages. A typical saturation current of 1.85 x 10(-7) A under a gate bias of 50 V is obtained for non mesa structure TFT while for mesa structured TFT saturation current of 5 x 10(-5) A can be obtained at comparatively very low gate bias of 6.4 V.

AlN and Al oxy-nitride gate dielectrics for reliable gate stacks on Ge and InGaAs channels

DOE Office of Scientific and Technical Information (OSTI.GOV)

Guo, Y.; Li, H.; Robertson, J.

2016-05-28

AlN and Al oxy-nitride dielectric layers are proposed instead of Al{sub 2}O{sub 3} as a component of the gate dielectric stacks on higher mobility channels in metal oxide field effect transistors to improve their positive bias stress instability reliability. It is calculated that the gap states of nitrogen vacancies in AlN lie further away in energy from the semiconductor band gap than those of oxygen vacancies in Al{sub 2}O{sub 3}, and thus AlN might be less susceptible to charge trapping and have a better reliability performance. The unfavourable defect energy level distribution in amorphous Al{sub 2}O{sub 3} is attributed tomore » its larger coordination disorder compared to the more symmetrically bonded AlN. Al oxy-nitride is also predicted to have less tendency for charge trapping.« less

Controlling the layer localization of gapless states in bilayer graphene with a gate voltage

NASA Astrophysics Data System (ADS)

Jaskólski, W.; Pelc, M.; Bryant, Garnett W.; Chico, Leonor; Ayuela, A.

2018-04-01

Experiments in gated bilayer graphene with stacking domain walls present topological gapless states protected by no-valley mixing. Here we research these states under gate voltages using atomistic models, which allow us to elucidate their origin. We find that the gate potential controls the layer localization of the two states, which switches non-trivially between layers depending on the applied gate voltage magnitude. We also show how these bilayer gapless states arise from bands of single-layer graphene by analyzing the formation of carbon bonds between layers. Based on this analysis we provide a model Hamiltonian with analytical solutions, which explains the layer localization as a function of the ratio between the applied potential and interlayer hopping. Our results open a route for the manipulation of gapless states in electronic devices, analogous to the proposed writing and reading memories in topological insulators.

Comparative study of CAVET with dielectric and p-GaN gate and Mg ion-implanted current blocking layer

NASA Astrophysics Data System (ADS)

Mandal, Saptarshi; Agarwal, Anchal; Ahmadi, Elaheh; Mahadeva Bhat, K.; Laurent, Matthew A.; Keller, Stacia; Chowdhury, Srabanti

2017-08-01

In this work, a study of two different types of current aperture vertical electron transistor (CAVET) with ion-implanted blocking layer are presented. The device fabrication and performance limitation of a CAVET with a dielectric gate is discussed, and the breakdown limiting structure is evaluated using on-wafer test structures. The gate dielectric limited the device breakdown to 50V, while the blocking layer was able to withstand over 400V. To improve the device performance, an alternative CAVET structure with a p-GaN gate instead of dielectric is designed and realized. The pGaN gated CAVET structure increased the breakdown voltage to over 400V. Measurement of test structures on the wafer showed the breakdown was limited by the blocking layer instead of the gate p-n junction.

Impact of post metal annealing on gate work function engineering for advanced MOS applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, S. Sachin, E-mail: ssachikl995@yahoo.in; Prasad, Amitesh; Sinha, Amrita

2016-05-06

Ultra thin HfO{sub 2} high-k gate dielectric has been deposited directly on strained Si{sub 0.81}Ge{sub 0.19} by Atomic Layer Deposition (ALD) technique. The influence of different types of metal gate electrodes (Al, Au, Pt) on electrical characteristics of Metal-Oxide-Semiconductor capacitors has been studied. Our results show that the electrical characteristics of MOS device are highly dependent on the gate electrodes used. The dependency of electrical characteristics on post metal annealing was studied in detail. The measured flat band (V{sub fb}) and hysteresis (ΔV{sub fb}) from high frequency C-V characteristics were used to study the pre-existing traps in the dielectric. Impactmore » of PMA on interface state density (D{sub it}), border trap density (N{sub bt}) and oxide trap density (Q{sub f/q}) of high-k gate stack were also examined for all the devices. The N{sub bt} and frequency dispersion significantly reduces to ~2.77x1010 cm{sup −2} and ~11.34 % respectively in case of Al electrode with a Dit value of ~4x10{sup 12} eV{sup −1}cm{sup −2} after PMA (350°C) in N{sub 2}, suggesting an improvement in device performance while Pt electrode shows a much less value of ΔVfb (~0.02 V) and Dit (~3.44x10{sup 12} eV{sup −1}cm{sup −2}) after PMA.« less

Synthesis and Characterization of the 2-Dimensional Transition Metal Dichalcogenides

NASA Astrophysics Data System (ADS)

Browning, Robert

In the last 50 years, the semiconductor industry has been scaling the silicon transistor to achieve faster devices, lower power consumption, and improve device performance. Transistor gate dimensions have become so small that short channel effects and gate leakage have become a significant problem. To address these issues, performance enhancement techniques such as strained silicon are used to improve mobility, while new high-k gate dielectric materials replace silicon oxide to reduce gate leakage. At some point the fundamental limit of silicon will be reached and the semiconductor industry will need to find an alternate solution. The advent of graphene led to the discovery of other layered materials such as the transition metal dichalcogenides. These materials have a layered structure similar to graphene and therefore possess some of the same qualities, but unlike graphene, these materials possess sizeable bandgaps between 1-2 eV making them useful for digital electronic applications. Since initially discovered, most of the research on these films has been from mechanically exfoliated flakes, which are easily produced due to the weak van der Waals force binding the layers together. For these materials to be considered for use in mainstream semiconductor technology, methods need to be explored to grow these films uniformly over a large area. In this research, atomic layer deposition (ALD) was employed as the growth technique used to produce large area uniform thin films of several different transition metal dichalcogenides. By optimizing the ALD growth parameters, it is possible to grow high quality films a few to several monolayers thick over a large area with good uniformity. This has been demonstrated and verified using several physical analytical tests such as Raman spectroscopy, photoluminescence, x-ray photoelectron spectroscopy, x-ray diffraction, transmission electron spectroscopy, and scanning electron microscopy, which show that these films possess the same qualities as those of the mechanically exfoliated films. Back-gated field effect transistors were created and electrical characterization was performed to determine if ALD grown films possess the same electronic properties as films produced from other methods. The tests revealed that the ALD grown films have high field effect mobility and high current on/off ratios. The WSe2 films also exhibited ambipolar electrical behavior making them a possible candidate for complementary metal-oxide semiconductor (CMOS) technology. Ab-initio density functional theory calculations were performed and compared to experimental properties of MoS2 and WSe2 films, which show that the ALD films grown in this research match theoretical predictions. The transconductance measurements from the WSe2 devices used, matched very well with the theoretical calculations, bridging the gap between experimental data and theoretical predictions. Based upon this research, ALD growth of TMD films proves to be a viable alternative for silicon based digital electronics.

Dopant distributions in n-MOSFET structure observed by atom probe tomography.

PubMed

Inoue, K; Yano, F; Nishida, A; Takamizawa, H; Tsunomura, T; Nagai, Y; Hasegawa, M

2009-11-01

The dopant distributions in an n-type metal-oxide-semiconductor field effect transistor (MOSFET) structure were analyzed by atom probe tomography. The dopant distributions of As, P, and B atoms in a MOSFET structure (gate, gate oxide, channel, source/drain extension, and halo) were obtained. P atoms were segregated at the interface between the poly-Si gate and the gate oxide, and on the grain boundaries of the poly-Si gate, which had an elongated grain structure along the gate height direction. The concentration of B atoms was enriched near the edge of the source/drain extension where the As atoms were implanted.

In2Ga2ZnO7 oxide semiconductor based charge trap device for NAND flash memory.

PubMed

Hwang, Eun Suk; Kim, Jun Shik; Jeon, Seok Min; Lee, Seung Jun; Jang, Younjin; Cho, Deok-Yong; Hwang, Cheol Seong

2018-04-01

The programming characteristics of charge trap flash memory device adopting amorphous In 2 Ga 2 ZnO 7 (a-IGZO) oxide semiconductors as channel layer were evaluated. Metal-organic chemical vapor deposition (MOCVD) and RF-sputtering processes were used to grow a 45 nm thick a-IGZO layer on a 20 nm thick SiO 2 (blocking oxide)/p ++ -Si (control gate) substrate, where 3 nm thick atomic layer deposited Al 2 O 3 (tunneling oxide) and 5 nm thick low-pressure CVD Si 3 N 4 (charge trap) layers were intervened between the a-IGZO and substrate. Despite the identical stoichiometry and other physicochemical properties of the MOCVD and sputtered a-IGZO, a much faster programming speed of MOCVD a-IGZO was observed. A comparable amount of oxygen vacancies was found in both MOCVD and sputtered a-IGZO, confirmed by x-ray photoelectron spectroscopy and bias-illumination-instability test measurements. Ultraviolet photoelectron spectroscopy analysis revealed a higher Fermi level (E F ) of the MOCVD a-IGZO (∼0.3 eV) film than that of the sputtered a-IGZO, which could be ascribed to the higher hydrogen concentration in the MOCVD a-IGZO film. Since the programming in a flash memory device is governed by the tunneling of electrons from the channel to charge trapping layer, the faster programming performance could be the result of a higher E F of MOCVD a-IGZO.

In2Ga2ZnO7 oxide semiconductor based charge trap device for NAND flash memory

NASA Astrophysics Data System (ADS)

Hwang, Eun Suk; Kim, Jun Shik; Jeon, Seok Min; Lee, Seung Jun; Jang, Younjin; Cho, Deok-Yong; Hwang, Cheol Seong

2018-04-01

The programming characteristics of charge trap flash memory device adopting amorphous In2Ga2ZnO7 (a-IGZO) oxide semiconductors as channel layer were evaluated. Metal-organic chemical vapor deposition (MOCVD) and RF-sputtering processes were used to grow a 45 nm thick a-IGZO layer on a 20 nm thick SiO2 (blocking oxide)/p++-Si (control gate) substrate, where 3 nm thick atomic layer deposited Al2O3 (tunneling oxide) and 5 nm thick low-pressure CVD Si3N4 (charge trap) layers were intervened between the a-IGZO and substrate. Despite the identical stoichiometry and other physicochemical properties of the MOCVD and sputtered a-IGZO, a much faster programming speed of MOCVD a-IGZO was observed. A comparable amount of oxygen vacancies was found in both MOCVD and sputtered a-IGZO, confirmed by x-ray photoelectron spectroscopy and bias-illumination-instability test measurements. Ultraviolet photoelectron spectroscopy analysis revealed a higher Fermi level (E F) of the MOCVD a-IGZO (∼0.3 eV) film than that of the sputtered a-IGZO, which could be ascribed to the higher hydrogen concentration in the MOCVD a-IGZO film. Since the programming in a flash memory device is governed by the tunneling of electrons from the channel to charge trapping layer, the faster programming performance could be the result of a higher E F of MOCVD a-IGZO.

Field effect transistor and method of construction thereof

NASA Technical Reports Server (NTRS)

Fletner, W. R. (Inventor)

1978-01-01

A field effect transistor is constructed by placing a semi-conductor layer on an insulating substrate so that the gate region is separated from source and drain regions. The gate electrode and gate region of the layer are of generally reduced length, the gate region being of greatest length on its surface closest to the gate electrode. This is accomplished by initially creating a relatively large gate region of one polarity, and then reversing the polarity of a central portion of this gate region by ion bombardment, thus achieving a narrower final gate region of the stated configuration.

Few-layer nanoplates of Bi 2 Se 3 and Bi 2 Te 3 with highly tunable chemical potential.

PubMed

Kong, Desheng; Dang, Wenhui; Cha, Judy J; Li, Hui; Meister, Stefan; Peng, Hailin; Liu, Zhongfan; Cui, Yi

2010-06-09

A topological insulator (TI) represents an unconventional quantum phase of matter with insulating bulk band gap and metallic surface states. Recent theoretical calculations and photoemission spectroscopy measurements show that group V-VI materials Bi(2)Se(3), Bi(2)Te(3), and Sb(2)Te(3) are TIs with a single Dirac cone on the surface. These materials have anisotropic, layered structures, in which five atomic layers are covalently bonded to form a quintuple layer, and quintuple layers interact weakly through van der Waals interaction to form the crystal. A few quintuple layers of these materials are predicted to exhibit interesting surface properties. Different from our previous nanoribbon study, here we report the synthesis and characterizations of ultrathin Bi(2)Te(3) and Bi(2)Se(3) nanoplates with thickness down to 3 nm (3 quintuple layers), via catalyst-free vapor-solid (VS) growth mechanism. Optical images reveal thickness-dependent color and contrast for nanoplates grown on oxidized silicon (300 nm SiO(2)/Si). As a new member of TI nanomaterials, ultrathin TI nanoplates have an extremely large surface-to-volume ratio and can be electrically gated more effectively than the bulk form, potentially enhancing surface state effects in transport measurements. Low-temperature transport measurements of a single nanoplate device, with a high-k dielectric top gate, show decrease in carrier concentration by several times and large tuning of chemical potential.

Extraction of sub-gap density of states via capacitance-voltage measurement for the erasing process in a TFT charge-trapping memory

NASA Astrophysics Data System (ADS)

Chiang, Yen-Chang; Hsiao, Yang-Hsuan; Li, Jeng-Ting; Chen, Jen-Sue

2018-02-01

Charge-trapping memories (CTMs) based on zinc tin oxide (ZTO) semiconductor thin-film transistors (TFTs) can be programmed by a positive gate voltage and erased by a negative gate voltage in conjunction with light illumination. To understand the mechanism involved, the sub-gap density of states associated with ionized oxygen vacancies in the ZTO active layer is extracted from optical response capacitance-voltage (C-V) measurements. The corresponding energy states of ionized oxygen vacancies are observed below the conduction band minimum at approximately 0.5-1.0 eV. From a comparison of the fitted oxygen vacancy concentration in the CTM-TFT after the light-bias erasing operation, it is found that the pristine-erased device contains more oxygen vacancies than the program-erased device because the trapped electrons in the programmed device are pulled into the active layer and neutralized by the oxygen vacancies that are present there.

Bio-sorbable, liquid electrolyte gated thin-film transistor based on a solution-processed zinc oxide layer.

PubMed

Singh, Mandeep; Palazzo, Gerardo; Romanazzi, Giuseppe; Suranna, Gian Paolo; Ditaranto, Nicoletta; Di Franco, Cinzia; Santacroce, Maria Vittoria; Mulla, Mohammad Yusuf; Magliulo, Maria; Manoli, Kyriaki; Torsi, Luisa

2014-01-01

Among the metal oxide semiconductors, ZnO has been widely investigated as a channel material in thin-film transistors (TFTs) due to its excellent electrical properties, optical transparency and simple fabrication via solution-processed techniques. Herein, we report a solution-processable ZnO-based thin-film transistor gated through a liquid electrolyte with an ionic strength comparable to that of a physiological fluid. The surface morphology and chemical composition of the ZnO films upon exposure to water and phosphate-buffered saline (PBS) are discussed in terms of the operation stability and electrical performance of the ZnO TFT devices. The improved device characteristics upon exposure to PBS are associated with the enhancement of the oxygen vacancies in the ZnO lattice due to Na(+) doping. Moreover, the dissolution kinetics of the ZnO thin film in a liquid electrolyte opens the possible applicability of these devices as an active element in "transient" implantable systems.

Random Telegraph Signal-Like Fluctuation Created by Fowler-Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

NASA Astrophysics Data System (ADS)

Kim, Heesang; Oh, Byoungchan; Kim, Kyungdo; Cha, Seon-Yong; Jeong, Jae-Goan; Hong, Sung-Joo; Lee, Jong-Ho; Park, Byung-Gook; Shin, Hyungcheol

2010-09-01

We generated traps inside gate oxide in gate-drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler-Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal-oxide-semiconductor field-effect transistors (MOSFETs).

Carbon nanotube-based three-dimensional monolithic optoelectronic integrated system

NASA Astrophysics Data System (ADS)

Liu, Yang; Wang, Sheng; Liu, Huaping; Peng, Lian-Mao

2017-06-01

Single material-based monolithic optoelectronic integration with complementary metal oxide semiconductor-compatible signal processing circuits is one of the most pursued approaches in the post-Moore era to realize rapid data communication and functional diversification in a limited three-dimensional space. Here, we report an electrically driven carbon nanotube-based on-chip three-dimensional optoelectronic integrated circuit. We demonstrate that photovoltaic receivers, electrically driven transmitters and on-chip electronic circuits can all be fabricated using carbon nanotubes via a complementary metal oxide semiconductor-compatible low-temperature process, providing a seamless integration platform for realizing monolithic three-dimensional optoelectronic integrated circuits with diversified functionality such as the heterogeneous AND gates. These circuits can be vertically scaled down to sub-30 nm and operates in photovoltaic mode at room temperature. Parallel optical communication between functional layers, for example, bottom-layer digital circuits and top-layer memory, has been demonstrated by mapping data using a 2 × 2 transmitter/receiver array, which could be extended as the next generation energy-efficient signal processing paradigm.

Directed assembly of carbon nanotubes on soft substrates for use as a flexible biosensor array.

PubMed

Koh, Juntae; Yi, Mihye; Yang Lee, Byung; Kim, Tae Hyun; Lee, Joohyung; Jhon, Young Min; Hong, Seunghun

2008-12-17

We have developed a method to selectively assemble and align carbon nanotubes (CNTs) on soft substrates for use as flexible biosensors. In this strategy, a thin oxide layer was deposited on soft substrates via low temperature plasma enhanced chemical vapor deposition, and a linker-free assembly process was applied on the oxide surface where the assembly of carbon nanotubes was guided by methyl-terminated molecular patterns on the oxide surface. The electrical characterization of the fabricated CNT devices exhibited a typical p-type gating effect and 1/f noise behavior. The bare oxide regions near CNTs were functionalized with glutamate oxidase to fabricate selective biosensors to detect two forms of glutamate substances existing in different situations: L-glutamic acid, a neurotransmitting material, and monosodium glutamate, a food additive.

Interface passivation and trap reduction via hydrogen fluoride for molybdenum disulfide on silicon oxide back-gate transistors

NASA Astrophysics Data System (ADS)

Hu, Yaoqiao; San Yip, Pak; Tang, Chak Wah; Lau, Kei May; Li, Qiang

2018-04-01

Layered semiconductor molybdenum disulfide (MoS2) has recently emerged as a promising material for flexible electronic and optoelectronic devices because of its finite bandgap and high degree of gate control. Here, we report a hydrogen fluoride (HF) passivation technique for improving the carrier mobility and interface quality of chemical vapor deposited monolayer MoS2 on a SiO2/Si substrate. After passivation, the fabricated MoS2 back-gate transistors demonstrate a more than double improvement in average electron mobility, a reduced gate hysteresis gap of 3 V, and a low interface trapped charge density of ˜5.8 × 1011 cm-2. The improvements are attributed to the satisfied interface dangling bonds, thus a reduction of interface trap states and trapped charges. Surface x-ray photoelectron spectroscopy analysis and first-principles simulation were performed to verify the HF passivation effect. The results here highlight the necessity of a MoS2/dielectric passivation strategy and provides a viable route for enhancing the performance of MoS2 nano-electronic devices.

Detection of prostate-specific antigen with biomolecule-gated AlGaN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Li, Jia-dong; Cheng, Jun-jie; Miao, Bin; Wei, Xiao-wei; Xie, Jie; Zhang, Jin-cheng; Zhang, Zhi-qiang; Wu, Dong-min

2014-07-01

In order to improve the sensitivity of AlGaN/GaN high electron mobility transistor (HEMT) biosensors, a simple biomolecule-gated AlGaN/GaN HEMT structure was designed and successfully fabricated for prostate specific antigen (PSA) detection. UV/ozone was used to oxidize the GaN surface and then a 3-aminopropyl trimethoxysilane (APTES) self-assembled monolayer was bound to the sensing region. This monolayer serves as a binding layer for attachment of the prostate specific antibody (anti-PSA). The biomolecule-gated AlGaN/GaN HEMT sensor shows a rapid and sensitive response when the target prostate-specific antigen in buffer solution was added to the antibody-immobilized sensing area. The current change showed a logarithm relationship against the PSA concentration from 0.1 pg/ml to 0.993 ng/ml. The sensitivity of 0.215% is determined for 0.1 pg/ml PSA solution. The above experimental result of the biomolecule-gated AlGaN/GaN HEMT biosensor suggested that this biosensor might be a useful tool for prostate cancer screening.

Ferroelectric control of a Mott insulator

PubMed Central

Yamada, Hiroyuki; Marinova, Maya; Altuntas, Philippe; Crassous, Arnaud; Bégon-Lours, Laura; Fusil, Stéphane; Jacquet, Eric; Garcia, Vincent; Bouzehouane, Karim; Gloter, Alexandre; Villegas, Javier E.; Barthélémy, Agnès; Bibes, Manuel

2013-01-01

The electric field control of functional properties is an important goal in oxide-based electronics. To endow devices with memory, ferroelectric gating is interesting, but usually weak compared to volatile electrolyte gating. Here, we report a very large ferroelectric field-effect in perovskite heterostructures combining the Mott insulator CaMnO3 and the ferroelectric BiFeO3 in its “supertetragonal” phase. Upon polarization reversal of the BiFeO3 gate, the CaMnO3 channel resistance shows a fourfold variation around room temperature, and a tenfold change at ~200 K. This is accompanied by a carrier density modulation exceeding one order of magnitude. We have analyzed the results for various CaMnO3 thicknesses and explain them by the electrostatic doping of the CaMnO3 layer and the presence of a fixed dipole at the CaMnO3/BiFeO3 interface. Our results suggest the relevance of ferroelectric gates to control orbital- or spin-ordered phases, ubiquitous in Mott systems, and pave the way toward efficient Mott-tronics devices. PMID:24089020

Effect of atomic-arrangement matching on La{sub 2}O{sub 3}/Ge heterostructures for epitaxial high-k-gate-stacks

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kanashima, T., E-mail: kanashima@ee.es.osaka-u.ac.jp; Zenitaka, M.; Kajihara, Y.

2015-12-14

We demonstrate a high-quality La{sub 2}O{sub 3} layer on germanium (Ge) as an epitaxial high-k-gate-insulator, where there is an atomic-arrangement matching condition between La{sub 2}O{sub 3}(001) and Ge(111). Structural analyses reveal that (001)-oriented La{sub 2}O{sub 3} layers were grown epitaxially only when we used Ge(111) despite low growth temperatures less than 300 °C. The permittivity (k) of the La{sub 2}O{sub 3} layer is roughly estimated to be ∼19 from capacitance-voltage (C-V) analyses in Au/La{sub 2}O{sub 3}/Ge structures after post-metallization-annealing treatments, although the C-V curve indicates the presence of carrier traps near the interface. By using X-ray photoelectron spectroscopy analyses, we findmore » that only Ge–O–La bonds are formed at the interface, and the thickness of the equivalent interfacial Ge oxide layer is much smaller than that of GeO{sub 2} monolayer. We discuss a model of the interfacial structure between La{sub 2}O{sub 3} and Ge(111) and comment on the C-V characteristics.« less

Electrical characterization of amorphous Al2O3 dielectric films on n-type 4H-SiC

NASA Astrophysics Data System (ADS)

Khosa, R. Y.; Thorsteinsson, E. B.; Winters, M.; Rorsman, N.; Karhu, R.; Hassan, J.; Sveinbjörnsson, E. Ö.

2018-02-01

We report on the electrical properties of Al2O3 films grown on 4H-SiC by successive thermal oxidation of thin Al layers at low temperatures (200°C - 300°C). MOS capacitors made using these films contain lower density of interface traps, are more immune to electron injection and exhibit higher breakdown field (5MV/cm) than Al2O3 films grown by atomic layer deposition (ALD) or rapid thermal processing (RTP). Furthermore, the interface state density is significantly lower than in MOS capacitors with nitrided thermal silicon dioxide, grown in N2O, serving as the gate dielectric. Deposition of an additional SiO2 film on the top of the Al2O3 layer increases the breakdown voltage of the MOS capacitors while maintaining low density of interface traps. We examine the origin of negative charges frequently encountered in Al2O3 films grown on SiC and find that these charges consist of trapped electrons which can be released from the Al2O3 layer by depletion bias stress and ultraviolet light exposure. This electron trapping needs to be reduced if Al2O3 is to be used as a gate dielectric in SiC MOS technology.

Near-zero hysteresis and near-ideal subthreshold swing in h-BN encapsulated single-layer MoS2 field-effect transistors

NASA Astrophysics Data System (ADS)

Vu, Quoc An; Fan, Sidi; Hyup Lee, Sang; Joo, Min-Kyu; Jong Yu, Woo; Lee, Young Hee

2018-07-01

While two-dimensional (2D) van der Waals (vdW) layered materials are promising channel materials for wearable electronics and energy-efficient field-effect transistors (FETs), large hysteresis and large subthreshold swing induced by either dangling bonds at gate oxide dielectrics and/or trap molecules in bubbles at vdW interface are a serious drawback, hampering implementation of the 2D-material based FETs in real electronics. Here, we report a monolayer MoS2 FET with near-zero hysteresis reaching 0.15% of the sweeping range of the gate bias, a record-value observed so far in 2D FETs. This was realized by squeezing the MoS2 channel between top h-BN layer and bottom h-BN gate dielectrics and further removing the trap molecules in bubbles at the vdW interfaces via post-annealing. By segregating the bubbles out to the edge of the channel, we also obtain excellent switching characteristics with a minimum subthreshold swing of 63 mV/dec, an average subthreshold slope of 69 mV/dec for a current range of four orders of magnitude at room temperature, and a high on/off current ratio of 108 at a small operating voltage (<1 V). Such a near-zero hysteresis and a near-ideal subthreshold limit originate from the reduced trap density of ~5.2  ×  109 cm‑2 eV‑1, a thousand times smaller than previously reported values.

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

NASA Astrophysics Data System (ADS)

Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

2009-08-01

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

Fabrication of 4H-SiC n-channel IGBTs with ultra high blocking voltage

NASA Astrophysics Data System (ADS)

Yang, Xiaolei; Tao, Yonghong; Yang, Tongtong; Huang, Runhua; Song, Bai

2018-03-01

Owing to the conductivity modulation of silicon carbide (SiC) bipolar devices, n-channel insulated gate bipolar transistors (n-IGBTs) have a significant advantage over metal oxide semiconductor field effect transistors (MOSFETs) in ultra high voltage (UHV) applications. In this paper, backside grinding and laser annealing process were carried out to fabricate 4H-SiC n-IGBTs. The thickness of a drift layer was 120 μm, which was designed for a blocking voltage of 13 kV. The n-IGBTs carried a collector current density of 24 A/cm2 at a power dissipation of 300 W/cm2 when the gate voltage was 20 V, with a differential specific on-resistance of 140 mΩ·cm2.

Innovative Ge Quantum Dot Functional Sensing and Metrology Devices

DTIC Science & Technology

2017-08-21

information latency and power consumption . In contrast, optical interconnects have shown tremendous promise for replacing electrical wires thanks to...single oxidation step of Si0.85Ge0.15 nano-pillars patterned over a buffer layer of Si3N4 on top of the n-Si substrate. During the high- temperature ...exquisitely-controlled dynamic balance between the fluxes of oxygen and silicon interstitials. Results and Discussion: 1. Self-organized, gate

Impact of La{sub 2}O{sub 3} interfacial layers on InGaAs metal-oxide-semiconductor interface properties in Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs gate stacks deposited by atomic-layer-deposition

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chang, C.-Y., E-mail: cychang@mosfet.t.u-tokyo.ac.jp; Takenaka, M.; Takagi, S.

We examine the electrical properties of atomic layer deposition (ALD) La{sub 2}O{sub 3}/InGaAs and Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs metal-oxide-semiconductor (MOS) capacitors. It is found that the thick ALD La{sub 2}O{sub 3}/InGaAs interface provides low interface state density (D{sub it}) with the minimum value of ∼3 × 10{sup 11} cm{sup −2} eV{sup −1}, which is attributable to the excellent La{sub 2}O{sub 3} passivation effect for InGaAs surfaces. It is observed, on the other hand, that there are a large amount of slow traps and border traps in La{sub 2}O{sub 3}. In order to simultaneously satisfy low D{sub it} and small hysteresis, the effectivenessmore » of Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs gate stacks with ultrathin La{sub 2}O{sub 3} interfacial layers is in addition evaluated. The reduction of the La{sub 2}O{sub 3} thickness to 0.4 nm in Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs gate stacks leads to the decrease in hysteresis. On the other hand, D{sub it} of the Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs interfaces becomes higher than that of the La{sub 2}O{sub 3}/InGaAs ones, attributable to the diffusion of Al{sub 2}O{sub 3} through La{sub 2}O{sub 3} into InGaAs and resulting modification of the La{sub 2}O{sub 3}/InGaAs interface structure. As a result of the effective passivation effect of La{sub 2}O{sub 3} on InGaAs, however, the Al{sub 2}O{sub 3}/10 cycle (0.4 nm) La{sub 2}O{sub 3}/InGaAs gate stacks can realize still lower D{sub it} with maintaining small hysteresis and low leakage current than the conventional Al{sub 2}O{sub 3}/InGaAs MOS interfaces.« less

Nanometer-scale oxide thin film transistor with potential for high-density image sensor applications.

PubMed

Jeon, Sanghun; Park, Sungho; Song, Ihun; Hur, Ji-Hyun; Park, Jaechul; Kim, Hojung; Kim, Sunil; Kim, Sangwook; Yin, Huaxiang; Chung, U-In; Lee, Eunha; Kim, Changjung

2011-01-01

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al₂O₃/SiO₂) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.

Materials science, integration, and performance characterization of high-dielectric constant thin film based devices

NASA Astrophysics Data System (ADS)

Fan, Wei

To overcome the oxidation and diffusion problems encountered during Copper integration with oxide thin film-based devices, TiAl/Cu/Ta heterostructure has been first developed in this study. Investigation on the oxidation and diffusion resistance of the laminate structure showed high electrical conductance and excellent thermal stability in oxygen environment. Two amorphous oxide layers that were formed on both sides of the TiAl barrier after heating in oxygen have been revealed as the structure that effectively prevents oxygen penetration and protects the integrity of underlying Cu layer. Polycrystalline (BaxSr1-x)TiO3 (BST) thin films were subsequently deposited on the Cu-based bottom electrode by RF magnetron sputtering to investigate the interaction between the oxide and Cu layers. The thickness of the interfacial layer and interface roughness play critical roles in the optimization of the electrical performance of the BST capacitors using Cu-based electrode. It was determined that BST deposition at moderate temperature followed by rapid thermal annealing in pure oxygen yields BST/Cu capacitors with good electrical properties for application to high frequency devices. The knowledge obtained on the study of barrier properties of TiAl inspired a continuous research on the materials science issues related to the application of the hybrid TiAlOx, as high-k gate dielectric in MOSFET devices. Novel fabrication process such as deposition of ultra-thin TiAl alloy layer followed by oxidation with atomic oxygen has been established in this study. Stoichiometric amorphous TiAlOx layers, exhibiting only Ti4+ and Al3+ states, were produced with a large variation of oxidation temperature (700°C to room temperature). The interfacial SiOx formation between TiAlOx and Si was substantially inhibited by the use of the low temperature oxidation process. Electrical characterization revealed a large permittivity of 30 and an improved band structure for the produced TiAlOx layers, compared with pure TiO2. A modified 3-element model was adopted to extract the true C-V behavior of the TiAlOx-based MOS capacitor. Extremely small equivalent oxide thickness (EOT) less than 0.5 nm with dielectric leakage 4˜5 magnitude lower than that for SiO2 has been achieved on TiAlOx layer as a result of its excellent dielectric properties.

Formation of nanofilament field emission devices

DOEpatents

Morse, Jeffrey D.; Contolini, Robert J.; Musket, Ronald G.; Bernhardt, Anthony F.

2000-01-01

A process for fabricating a nanofilament field emission device. The process enables the formation of high aspect ratio, electroplated nanofilament structure devices for field emission displays wherein a via is formed in a dielectric layer and is self-aligned to a via in the gate metal structure on top of the dielectric layer. The desired diameter of the via in the dielectric layer is on the order of 50-200 nm, with an aspect ratio of 5-10. In one embodiment, after forming the via in the dielectric layer, the gate metal is passivated, after which a plating enhancement layer is deposited in the bottom of the via, where necessary. The nanofilament is then electroplated in the via, followed by removal of the gate passification layer, etch back of the dielectric, and sharpening of the nanofilament. A hard mask layer may be deposited on top of the gate metal and removed following electroplating of the nanofilament.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-01

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

PubMed

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-17

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

A transparent electrochromic metal-insulator switching device with three-terminal transistor geometry

NASA Astrophysics Data System (ADS)

Katase, Takayoshi; Onozato, Takaki; Hirono, Misako; Mizuno, Taku; Ohta, Hiromichi

2016-05-01

Proton and hydroxyl ion play an essential role for tuning functionality of oxides because their electronic state can be controlled by modifying oxygen off-stoichiometry and/or protonation. Tungsten trioxide (WO3), a well-known electrochromic (EC) material for smart window, is a wide bandgap insulator, whereas it becomes a metallic conductor HxWO3 by protonation. Although one can utilize electrochromism together with metal-insulator (MI) switching for one device, such EC-MI switching cannot be utilized in current EC devices because of their two-terminal structure with parallel-plate configuration. Here we demonstrate a transparent EC-MI switchable device with three-terminal TFT-type structure using amorphous (a-) WO3 channel layer, which was fabricated on glass substrate at room temperature. We used water-infiltrated nano-porous glass, CAN (calcium aluminate with nano-pores), as a liquid-leakage-free solid gate insulator. At virgin state, the device was fully transparent in the visible-light region. For positive gate voltage, the active channel became dark blue, and electrical resistivity of the a-WO3 layer drastically decreased with protonation. For negative gate voltage, deprotonation occurred and the active channel returned to transparent insulator. Good cycleability of the present transparent EC-MI switching device would have potential for the development of advanced smart windows.

Novel H+-Ion Sensor Based on a Gated Lateral BJT Pair

PubMed Central

Yuan, Heng; Zhang, Jixing; Cao, Chuangui; Zhang, Gangyuan; Zhang, Shaoda

2015-01-01

An H+-ion sensor based on a gated lateral bipolar junction transistor (BJT) pair that can operate without the classical reference electrode is proposed. The device is a special type of ion-sensitive field-effect transistor (ISFET). Classical ISFETs have the advantage of miniaturization, but  they are difficult to fabricate by a single fabrication process because of the bulky and brittle reference electrode materials. Moreover, the reference electrodes need to be separated from the sensor device in some cases. The proposed device is composed of two gated lateral BJT components, one of which had a silicide layer while the other was without the layer. The two components were operated under the metal-oxide semiconductor field-effect transistor (MOSFET)-BJT hybrid mode, which can be controlled by emitter voltage and base current. Buffer solutions with different pH values were used as the sensing targets to verify the characteristics of the proposed device. Owing to their different sensitivities, both components could simultaneously detect the H+-ion concentration and function as a reference to each other. Per the experimental results, the sensitivity of the proposed device was found to be approximately 0.175 μA/pH. This experiment demonstrates enormous potential to lower the cost of the ISFET-based sensor technology. PMID:26703625

Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

NASA Astrophysics Data System (ADS)

An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

2016-11-01

Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

Cobalt germanide nanostructure formation and memory characteristic enhancement in silicon oxide films

NASA Astrophysics Data System (ADS)

Joo, Beom Soo; Kim, Hyunseung; Jang, Seunghun; Han, Dongwoo; Han, Moonsup

2018-08-01

We investigated nano-floating gate memory having a charge trap layer (CTL) composed of cobalt germanide nanostructure (ns-CoGe). A tunneling oxide layer; a CTL containing Co, Ge, and Si; and a blocking oxide layer were sequentially deposited on a p-type silicon substrate by RF magnetron sputtering and low-pressure chemical vapor deposition. We optimized the CTL formation conditions by rapid thermal annealing at a somewhat low temperature (about 830 °C) by considering the differences in Gibbs free energy and chemical enthalpy among the components. To characterize the charge storage properties, capacitance-voltage (C-V) measurements were performed. Further, we used X-ray photoelectron spectroscopy for chemical analysis of the CTL. In this work, we not only report that the C-V measurement shows a remarkable opening of the memory window for the ns-CoGe compared with those of nanostructures composed of Co or Ge alone, but also clarify that the improvement in the memory characteristics originates in the nanostructure formation, which consists mainly of Co-Ge bonds. We expect ns-CoGe to be a strong candidate for fabrication of next-generation memory devices.

Flexible Proton-Gated Oxide Synaptic Transistors on Si Membrane.

PubMed

Zhu, Li Qiang; Wan, Chang Jin; Gao, Ping Qi; Liu, Yang Hui; Xiao, Hui; Ye, Ji Chun; Wan, Qing

2016-08-24

Ion-conducting materials have received considerable attention for their applications in fuel cells, electrochemical devices, and sensors. Here, flexible indium zinc oxide (InZnO) synaptic transistors with multiple presynaptic inputs gated by proton-conducting phosphorosilicate glass-based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton-gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton-gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multigates coupled flexible proton-gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing.

3D gate-all-around bandgap-engineered SONOS flash memory in vertical silicon pillar with metal gate

NASA Astrophysics Data System (ADS)

Oh, Jae-Sub; Yang, Seong-Dong; Lee, Sang-Youl; Kim, Young-Su; Kang, Min-Ho; Lim, Sung-Kyu; Lee, Hi-Deok; Lee, Ga-Won

2013-08-01

In this paper, a gate-all-around bandgap-engineered silicon-oxide-nitride-oxide-silicon device with a vertical silicon pillar structure and a Ti metal gate are demonstrated for a potential solution to overcome the scaling-down of flash memory device. The devices were fabricated using CMOS-compatible technology and exhibited well-behaved memory characteristics in terms of the program/erase window, retention, and endurance properties. Moreover, the integration of the Ti metal gate demonstrated a significant improvement in the erase characteristics due to the efficient suppression of the electron back tunneling through the blocking oxide.

Positron annihilation studies in the field induced depletion regions of metal-oxide-semiconductor structures

NASA Astrophysics Data System (ADS)

Asoka-Kumar, P.; Leung, T. C.; Lynn, K. G.; Nielsen, B.; Forcier, M. P.; Weinberg, Z. A.; Rubloff, G. W.

1992-06-01

The centroid shifts of positron annihilation spectra are reported from the depletion regions of metal-oxide-semiconductor (MOS) capacitors at room temperature and at 35 K. The centroid shift measurement can be explained using the variation of the electric field strength and depletion layer thickness as a function of the applied gate bias. An estimate for the relevant MOS quantities is obtained by fitting the centroid shift versus beam energy data with a steady-state diffusion-annihilation equation and a derivative-gaussian positron implantation profile. Inadequacy of the present analysis scheme is evident from the derived quantities and alternate methods are required for better predictions.

Improvement in top-gate MoS2 transistor performance due to high quality backside Al2O3 layer

NASA Astrophysics Data System (ADS)

Bolshakov, Pavel; Zhao, Peng; Azcatl, Angelica; Hurley, Paul K.; Wallace, Robert M.; Young, Chadwin D.

2017-07-01

A high quality Al2O3 layer is developed to achieve high performance in top-gate MoS2 transistors. Compared with top-gate MoS2 field effect transistors on a SiO2 layer, the intrinsic mobility and subthreshold slope were greatly improved in high-k backside layer devices. A forming gas anneal is found to enhance device performance due to a reduction in the charge trap density of the backside dielectric. The major improvements in device performance are ascribed to the forming gas anneal and the high-k dielectric screening effect of the backside Al2O3 layer. Top-gate devices built upon these stacks exhibit a near-ideal subthreshold slope of ˜69 mV/dec and a high Y-Function extracted intrinsic carrier mobility (μo) of 145 cm2/V.s, indicating a positive influence on top-gate device performance even without any backside bias.

Fabrication and Characteristics of High Mobility InSnZnO Thin Film Transistors.

PubMed

Choi, Pyungho; Lee, Junki; Park, Hyoungsun; Baek, Dohyun; Lee, Jaehyeong; Yi, Junsin; Kim, Sangsoo; Choi, Byoungdeog

2016-05-01

In this paper, we describe the fabrication of thin film transistors (TFTs) with amorphous indium-tin-zinc-oxide (ITZO) as the active material. A transparent ITZO channel layer was formed under an optimized oxygen partial pressure (OPP (%) = O2/(Ar + O2)) and subsequent annealing process. The electrical properties exhibited by this device include field-effect mobility (μ(eff)), sub-threshold swing (SS), and on/off current ratio (I(ON/OFF)) values of 28.97 cm2/V x s, 0.2 V/decade, and 2.64 x 10(7), respectively. The average transmittance values for each OPP condition in the visible range were greater than 80%. The positive gate bias stress resulted in a positive threshold voltage (V(th)) shift in the transfer curves and degraded the parameters μ(eff) and SS. These phenomena originated from electron trapping from the ITZO channel layer into the oxide/ITZO interface trap sites.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Won Lee, Sang; Suh, Dongseok, E-mail: energy.suh@skku.edu; Department of Energy Science and Department of Physics, Sungkyunkwan University, Suwon 440-746

A prior requirement of any developed transistor for practical use is the stability test. Random network carbon nanotube-thin film transistor (CNT-TFT) was fabricated on SiO{sub 2}/Si. Gate bias stress stability was investigated with various passivation layers of HfO{sub 2} and Al{sub 2}O{sub 3}. Compared to the threshold voltage shift without passivation layer, the measured values in the presence of passivation layers were reduced independent of gate bias polarity except HfO{sub 2} under positive gate bias stress (PGBS). Al{sub 2}O{sub 3} capping layer was found to be the best passivation layer to prevent ambient gas adsorption, while gas adsorption on HfO{submore » 2} layer was unavoidable, inducing surface charges to increase threshold voltage shift in particular for PGBS. This high performance in the gate bias stress test of CNT-TFT even superior to that of amorphous silicon opens potential applications to active TFT industry for soft electronics.« less

Nano-textured high sensitivity ion sensitive field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hajmirzaheydarali, M.; Sadeghipari, M.; Akbari, M.

2016-02-07

Nano-textured gate engineered ion sensitive field effect transistors (ISFETs), suitable for high sensitivity pH sensors, have been realized. Utilizing a mask-less deep reactive ion etching results in ultra-fine poly-Si features on the gate of ISFET devices where spacing of the order of 10 nm and less is achieved. Incorporation of these nano-sized features on the gate is responsible for high sensitivities up to 400 mV/pH in contrast to conventional planar structures. The fabrication process for this transistor is inexpensive, and it is fully compatible with standard complementary metal oxide semiconductor fabrication procedure. A theoretical modeling has also been presented to predict themore » extension of the diffuse layer into the electrolyte solution for highly featured structures and to correlate this extension with the high sensitivity of the device. The observed ultra-fine features by means of scanning electron microscopy and transmission electron microscopy tools corroborate the theoretical prediction.« less

Characterizing Radio Emission From Extensive Air Showers with the SLAC-T510 Experiment, with Applications to ANITA

NASA Astrophysics Data System (ADS)

McGuire, Felicia Ann

Essential to metal-oxide-semiconductor field-effect transistor (MOSFET) scaling is the reduction of the supply voltage to mitigate the power consumption and corresponding heat dissipation. Conventional dielectric materials are subject to the thermal limit imposed by the Boltzmann factor in the subthreshold swing, which places an absolute minimum on the supply voltage required to modulate the current. Furthermore, as technology approaches the 5 nm node, electrostatic control of a silicon channel becomes exceedingly difficult, regardless of the gating technique. This notion of "the end of silicon scaling" has rapidly increased research into more scalable channel materials as well as new methods of transistor operation. Among the many promising options are two-dimensional (2D) FETs and negative capacitance (NC) FETs. 2D-FETs make use of atomically thin semiconducting channels that have enabled demonstrated scalability beyond what silicon can offer. NC-FETs demonstrate an effective negative capacitance arising from the integration of a ferroelectric into the transistor gate stack, allowing sub-60 mV/dec switching. While both of these devices provide significant advantages, neither can accomplish the ultimate goal of a FET that is both low-voltage and scalable. However, an appropriate fusion of the 2D-FET and NC-FET into a 2D NC-FET has the potential of enabling a steep-switching device that is dimensionally scalable beyond the 5 nm technology node. In this work, the motivation for and operation of 2D NC-FETs is presented. Experimental realization of 2D NC-FETs using 2D transition metal dichalcogenide molybdenum disulfide (MoS2) as the channel is shown with two different ferroelectric materials: 1) a solution-processed, polymeric poly(vinylidene difluoride trifluoroethylene) ferroelectric and 2) an atomic layer deposition (ALD) grown hafnium zirconium oxide (HfZrO2) ferroelectric. Each ferroelectric was integrated into the gate stack of a 2D-FET having either a top-gate (polymeric ferroelectric) or bottom-gate (HfZrO2 ferroelectric) configuration. HfZrO 2 devices with metallic interfacial layers (between ferroelectric and dielectric) and thinner ferroelectric layers were found to reduce both the hysteresis and the threshold voltage. Detailed characterization of the devices was performed and, most significantly, the 2D NC-FETs with HfZrO2 reproducibly yielded subthreshold swings well below the thermal limit with over more than four orders of magnitude in drain current modulation. HfZrO 2 devices without metallic interfacial layers were utilized to explore the impact of ferroelectric thickness, dielectric thickness, and dielectric composition on device performance. The impact of an interfacial metallic layer on the device operation was investigated in devices with HfZrO2 and shown to be crucial at enabling sub-60 mV/dec switching and large internal voltage gains. The significance of dielectric material choice on device performance was explored and found to be a critical factor in 2D NC-FET transistor operation. These successful results pave the way for future integration of this new device structure into existing technology markets.

Leakage current conduction and reliability assessment of passivating thin silicon dioxide films on n-4H-SiC

NASA Astrophysics Data System (ADS)

Samanta, Piyas; Mandal, Krishna C.

2016-09-01

We have analyzed the mechanisms of leakage current conduction in passivating silicon dioxide (SiO2) films grown on (0 0 0 1) silicon (Si) face of n-type 4H-SiC (silicon carbide). It was observed that the experimentally measured gate current density in metal-oxide-silicon carbide (MOSiC) structures under positive gate bias at an oxide field Eox above 5 MV/cm is comprised of Fowler-Nordheim (FN) tunneling of electrons from the accumulated n-4H-SiC and Poole-Frenkel (PF) emission of trapped electrons from the localized neutral traps in the SiO2 gap, IFN and IPF, respectively at temperatures between 27 and 200 °C. In MOSiC structures, PF mechanism dominates FN tunneling of electrons from the accumulation layer of n-4H-SiC due to high density (up to 1013 cm-2) of carbon-related acceptor-like traps located at about 2.5 eV below the SiO2 conduction band (CB). These current conduction mechanisms were taken into account in studying hole injection/trapping into 10 nm-thick tunnel oxide on the Si face of 4H-SiC during electron injection from n-4H-SiC under high-field electrical stress with positive bias on the heavily doped n-type polysilicon (n+-polySi) gate at a wide range of temperatures between 27 and 200 °C. Holes were generated in the n+-polySi anode material by the hot-electrons during their transport through thin oxide films at oxide electric fields Eox from 5.6 to 8.0 MV/cm (prior to the intrinsic oxide breakdown field). Time-to-breakdown tBD of the gate dielectric was found to follow reciprocal field (1/E) model irrespective of stress temperatures. Despite the significant amount of process-induced interfacial electron traps contributing to a large amount of leakage current via PF emission in thermally grown SiO2 on the Si-face of n-4H-SiC, MOSiC devices having a 10 nm-thick SiO2 film can be safely used in 5 V TTL logic circuits over a period of 10 years.

Integrated field emission array for ion desorption

DOEpatents

Resnick, Paul J; Hertz, Kristin L.; Holland, Christopher; Chichester, David

2016-08-23

An integrated field emission array for ion desorption includes an electrically conductive substrate; a dielectric layer lying over the electrically conductive substrate comprising a plurality of laterally separated cavities extending through the dielectric layer; a like plurality of conically-shaped emitter tips on posts, each emitter tip/post disposed concentrically within a laterally separated cavity and electrically contacting the substrate; and a gate electrode structure lying over the dielectric layer, including a like plurality of circular gate apertures, each gate aperture disposed concentrically above an emitter tip/post to provide a like plurality of annular gate electrodes and wherein the lower edge of each annular gate electrode proximate the like emitter tip/post is rounded. Also disclosed herein are methods for fabricating an integrated field emission array.

Integrated field emission array for ion desorption

DOEpatents

Resnick, Paul J; Hertz, Kristin L; Holland, Christopher; Chichester, David; Schwoebel, Paul

2013-09-17

An integrated field emission array for ion desorption includes an electrically conductive substrate; a dielectric layer lying over the electrically conductive substrate comprising a plurality of laterally separated cavities extending through the dielectric layer; a like plurality of conically-shaped emitter tips on posts, each emitter tip/post disposed concentrically within a laterally separated cavity and electrically contacting the substrate; and a gate electrode structure lying over the dielectric layer, including a like plurality of circular gate apertures, each gate aperture disposed concentrically above an emitter tip/post to provide a like plurality of annular gate electrodes and wherein the lower edge of each annular gate electrode proximate the like emitter tip/post is rounded. Also disclosed herein are methods for fabricating an integrated field emission array.

A fabrication guide for planar silicon quantum dot heterostructures

NASA Astrophysics Data System (ADS)

Spruijtenburg, Paul C.; Amitonov, Sergey V.; van der Wiel, Wilfred G.; Zwanenburg, Floris A.

2018-04-01

We describe important considerations to create top-down fabricated planar quantum dots in silicon, often not discussed in detail in literature. The subtle interplay between intrinsic material properties, interfaces and fabrication processes plays a crucial role in the formation of electrostatically defined quantum dots. Processes such as oxidation, physical vapor deposition and atomic-layer deposition must be tailored in order to prevent unwanted side effects such as defects, disorder and dewetting. In two directly related manuscripts written in parallel we use techniques described in this work to create depletion-mode quantum dots in intrinsic silicon, and low-disorder silicon quantum dots defined with palladium gates. While we discuss three different planar gate structures, the general principles also apply to 0D and 1D systems, such as self-assembled islands and nanowires.

ZnO thin-film transistors with a polymeric gate insulator built on a polyethersulfone substrate

NASA Astrophysics Data System (ADS)

Hyung, Gun Woo; Park, Jaehoon; Koo, Ja Ryong; Choi, Kyung Min; Kwon, Sang Jik; Cho, Eou Sik; Kim, Yong Seog; Kim, Young Kwan

2012-03-01

Zinc oxide (ZnO) thin-film transistors (TFTs) with a cross-linked poly(vinyl alcohol) (c-PVA) insulator are fabricated on a polyethersulfone substrate. The ZnO film, formed by atomic layer deposition, shows a polycrystalline hexagonal structure with a band gap energy of about 3.37 eV. The fabricated ZnO TFT exhibits a field-effect mobility of 0.38 cm2/Vs and a threshold voltage of 0.2 V. The hysteresis of the device is mainly caused by trapped electrons at the c-PVA/ZnO interface, whereas the positive threshold voltage shift occurs as a consequence of constant positive gate bias stress after 5000 s due to an electron injection from the ZnO film into the c-PVA insulator.

Tuning the metal-insulator crossover and magnetism in SrRuO 3 by ionic gating

DOE PAGES

Yi, Hee Taek; Gao, Bin; Xie, Wei; ...

2014-10-13

Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. We report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO 3. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90–250 K and 70–100 K,more » respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.« less

Tuning the metal-insulator crossover and magnetism in SrRuO₃ by ionic gating.

PubMed

Yi, Hee Taek; Gao, Bin; Xie, Wei; Cheong, Sang-Wook; Podzorov, Vitaly

2014-10-13

Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. Here we report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO₃. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90-250 K and 70-100 K, respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.

Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

NASA Astrophysics Data System (ADS)

Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

2018-04-01

In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

Understanding the Structure of High-K Gate Oxides - Oral Presentation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Miranda, Andre

2015-08-25

Hafnium Oxide (HfO 2) amorphous thin films are being used as gate oxides in transistors because of their high dielectric constant (κ) over Silicon Dioxide. The present study looks to find the atomic structure of HfO 2 thin films which hasn’t been done with the technique of this study. In this study, two HfO 2 samples were studied. One sample was made with thermal atomic layer deposition (ALD) on top of a Chromium and Gold layer on a silicon wafer. The second sample was made with plasma ALD on top of a Chromium and Gold layer on a Silicon wafer.more » Both films were deposited at a thickness of 50nm. To obtain atomic structure information, Grazing Incidence X-ray diffraction (GIXRD) was carried out on the HfO 2 samples. Because of this, absorption, footprint, polarization, and dead time corrections were applied to the scattering intensity data collected. The scattering curves displayed a difference in structure between the ALD processes. The plasma ALD sample showed the broad peak characteristic of an amorphous structure whereas the thermal ALD sample showed an amorphous structure with characteristics of crystalline materials. This appears to suggest that the thermal process results in a mostly amorphous material with crystallites within. Further, the scattering intensity data was used to calculate a pair distribution function (PDF) to show more atomic structure. The PDF showed atom distances in the plasma ALD sample had structure up to 10 Å, while the thermal ALD sample showed the same structure below 10 Å. This structure that shows up below 10 Å matches the bond distances of HfO 2 published in literature. The PDF for the thermal ALD sample also showed peaks up to 20 Å, suggesting repeating atomic spacing outside the HfO 2 molecule in the sample. This appears to suggest that there is some crystalline structure within the thermal ALD sample.« less

Oxidative Modulation of Voltage-Gated Potassium Channels

PubMed Central

Sahoo, Nirakar; Hoshi, Toshinori

2014-01-01

Abstract Significance: Voltage-gated K+ channels are a large family of K+-selective ion channel protein complexes that open on membrane depolarization. These K+ channels are expressed in diverse tissues and their function is vital for numerous physiological processes, in particular of neurons and muscle cells. Potentially reversible oxidative regulation of voltage-gated K+ channels by reactive species such as reactive oxygen species (ROS) represents a contributing mechanism of normal cellular plasticity and may play important roles in diverse pathologies including neurodegenerative diseases. Recent Advances: Studies using various protocols of oxidative modification, site-directed mutagenesis, and structural and kinetic modeling provide a broader phenomenology and emerging mechanistic insights. Critical Issues: Physicochemical mechanisms of the functional consequences of oxidative modifications of voltage-gated K+ channels are only beginning to be revealed. In vivo documentation of oxidative modifications of specific amino-acid residues of various voltage-gated K+ channel proteins, including the target specificity issue, is largely absent. Future Directions: High-resolution chemical and proteomic analysis of ion channel proteins with respect to oxidative modification combined with ongoing studies on channel structure and function will provide a better understanding of how the function of voltage-gated K+ channels is tuned by ROS and the corresponding reducing enzymes to meet cellular needs. Antioxid. Redox Signal. 21, 933–952. PMID:24040918

Device performance of in situ steam generated gate dielectric nitrided by remote plasma nitridation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Al-Shareef, H. N.; Karamcheti, A.; Luo, T. Y.

2001-06-11

In situ steam generated (ISSG) oxides have recently attracted interest for use as gate dielectrics because of their demonstrated reliability improvement over oxides formed by dry oxidation. [G. Minor, G. Xing, H. S. Joo, E. Sanchez, Y. Yokota, C. Chen, D. Lopes, and A. Balakrishna, Electrochem. Soc. Symp. Proc. 99-10, 3 (1999); T. Y. Luo, H. N. Al-Shareef, G. A. Brown, M. Laughery, V. Watt, A. Karamcheti, M. D. Jackson, and H. R. Huff, Proc. SPIE 4181, 220 (2000).] We show in this letter that nitridation of ISSG oxide using a remote plasma decreases the gate leakage current of ISSGmore » oxide by an order of magnitude without significantly degrading transistor performance. In particular, it is shown that the peak normalized transconductance of n-channel devices with an ISSG oxide gate dielectric decreases by only 4% and the normalized drive current by only 3% after remote plasma nitridation (RPN). In addition, it is shown that the reliability of the ISSG oxide exhibits only a small degradation after RPN. These observations suggest that the ISSG/RPN process holds promise for gate dielectric applications. {copyright} 2001 American Institute of Physics.« less

Hafnium silicate and hafnium silicon oxynitride gate dielectrics for strained Si_xGe_1-x: Interface stability

NASA Astrophysics Data System (ADS)

Addepalli, Swarna; Sivasubramani, Prasanna; El-Bouanani, Mohamed; Kim, Moon; Gnade, Bruce; Wallace, Robert

2003-03-01

Strained Si_xGe_1-x layers have gained considerable attention due to hole mobility enhancement, and ease of integration with Si-based CMOS technology. The deposition of stable high-κ dielectrics [1] such as hafnium silicate and hafnium silicon oxynitride in direct contact with SiGe would simultaneously improve the capacitance of the gate stack and lower the leakage current for high performance SiGe devices. However, the oxidation of the Si_xGe_1-x substrate either during dielectric deposition or post-deposition processing would degrade device performance due to the thermodynamic instability of germanium oxide [2,3]. Results from XPS, HR-TEM, and C-V, and I-V analyses after various annealing treatments will be presented for hafnium silicate and hafnium silicon oxynitride films deposited on strained Si_xGe_1-x(100), and correlated with dielectric-Si_xGe_1-x(100) interface stability. Implications to the introduction of these oxides as viable gate dielectric candidates for SiGe-based CMOS technology will be discussed. This work is supported by DARPA through SPAWAR Grant No. N66001-00-1-8928, and the Texas Advanced Technology Program. References: [1] G. D. Wilk, R. M. Wallace and J. M. Anthony, Journal of Applied Physics, 89, 5243 (2001) [2] W. S. Liu, J .S. Chen, M.-A. Nicolet, V. Arbet-Engels, K. L. Wang, Journal of Applied Physics, 72, 4444 (1992), and, Applied Physics Letters, 62, 3321 (1993) [3] W. S. Liu, M. -A. Nicolet, H. -H. Park, B. -H. Koak, J. -W. Lee, Journal of Applied Physics, 78, 2631 (1995)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ahn, Cheol Hyoun; Hee Kim, So; Gu Yun, Myeong

In this study, we proposed the artificially designed channel structure in oxide thin-film transistors (TFTs) called a “step-composition gradient channel.” We demonstrated Al step-composition gradient Al-Zn-O (AZO) channel structures consisting of three AZO layers with different Al contents. The effects of stacking sequence in the step-composition gradient channel on performance and electrical stability of bottom-gate TFT devices were investigated with two channels of inverse stacking order (ascending/descending step-composition). The TFT with ascending step-composition channel structure (5 → 10 → 14 at. % Al composition) showed relatively negative threshold voltage (−3.7 V) and good instability characteristics with a reduced threshold voltage shift (Δmore » 1.4 V), which was related to the alignment of the conduction band off-set within the channel layer depending on the Al contents. Finally, the reduced Al composition in the initial layer of ascending step-composition channel resulted in the best field effect mobility of 4.5 cm{sup 2}/V s. We presented a unique active layer of the “step-composition gradient channel” in the oxide TFTs and explained the mechanism of adequate channel design.« less

Multi-Dimensional Quantum Effect Simulation Using a Density-Gradient Model and Script-Level Programming Techniques

NASA Technical Reports Server (NTRS)

Rafferty, Connor S.; Biegel, Bryan A.; Yu, Zhi-Ping; Ancona, Mario G.; Bude, J.; Dutton, Robert W.; Saini, Subhash (Technical Monitor)

1998-01-01

A density-gradient (DG) model is used to calculate quantum-mechanical corrections to classical carrier transport in MOS (Metal Oxide Semiconductor) inversion/accumulation layers. The model is compared to measured data and to a fully self-consistent coupled Schrodinger and Poisson equation (SCSP) solver. Good agreement is demonstrated for MOS capacitors with gate oxide as thin as 21 A. It is then applied to study carrier distribution in ultra short MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) with surface roughness. This work represents the first implementation of the DG formulation on multidimensional unstructured meshes. It was enabled by a powerful scripting approach which provides an easy-to-use and flexible framework for solving the fourth-order PDEs (Partial Differential Equation) of the DG model.

Low-Damage Sputter Deposition on Graphene

NASA Astrophysics Data System (ADS)

Chen, Ching-Tzu; Casu, Emanuele; Gajek, Marcin; Raoux, Simone

2013-03-01

Despite its versatility and prevalence in the microelectronics industry, sputter deposition has seen very limited applications for graphene-based electronics. We have systematically investigated the sputtering induced graphene defects and identified the reflected high-energy neutrals of the sputtering gas as the primary cause of damage. In this talk, we introduce a novel sputtering technique that is shown to dramatically reduce bombardment of the fast neutrals and improve the structural integrity of the underlying graphene layer. We also demonstrate that sputter deposition and in-situ oxidation of 1 nm Al film at elevated temperatures yields homogeneous, fully covered oxide films with r.m.s. roughness much less than 1 monolayer, which shows the potential of using such technique for gate oxides, tunnel barriers, and multilayer fabrication in a wide range of graphene devices.

Improvement of the GaSb/Al2O3 interface using a thin InAs surface layer

NASA Astrophysics Data System (ADS)

Greene, Andrew; Madisetti, Shailesh; Nagaiah, Padmaja; Yakimov, Michael; Tokranov, Vadim; Moore, Richard; Oktyabrsky, Serge

2012-12-01

The highly reactive GaSb surface was passivated with a thin InAs layer to limit interface trap state density (Dit) at the III-V/high-k oxide interface. This InAs surface was subjected to various cleaning processes to effectively reduce native oxides before atomic layer deposition (ALD). Ammonium sulfide pre-cleaning and trimethylaluminum/water ALD were used in conjunction to provide a clean interface and annealing in forming gas (FG) at 350 °C resulted in an optimized fabrication for n-GaSb/InAs/high-k gate stacks. Interface trap density, Dit ≈ 2-3 × 1012 cm-2eV-1 resided near the n-GaSb conductance band which was extracted and compared with three different methods. Conductance-voltage-frequency plots showed efficient Fermi level movement and a sub-threshold slope of 200 mV/dec. A composite high-k oxide process was also developed using ALD of Al2O3 and HfO2 resulting in a Dit ≈ 6-7 × 1012 cm-2eV-1. Subjecting these samples to a higher (450 °C) processing temperature results in increased oxidation and a thermally unstable interface. p-GaSb displayed very fast minority carrier generation/recombination likely due to a high density of bulk traps in GaSb.

Coaxially gated in-wire thin-film transistors made by template assembly.

PubMed

Kovtyukhova, Nina I; Kelley, Brian K; Mallouk, Thomas E

2004-10-13

Nanowire field effect transistors were prepared by a wet chemical template replication method using anodic aluminum oxide membranes. The membrane pores were first lined with a thin SiO2 layer by the surface sol-gel method. Au, CdS (or CdSe), and Au wire segments were then sequentially electrodeposited within the pores, and the resulting nanowires were released by dissolution of the membrane. Electrofluidic alignment of these nanowires between source and drain leads and evaporation of gold over the central CdS (CdSe) stripe affords a "wrap-around gate" structure. At VDS = -2 V, the Au/CdS/Au devices had an ON/OFF current ratio of 103, a threshold voltage of 2.4 V, and a subthreshold slope of 2.2 V/decade. A 3-fold decrease in the subthreshold slope relative to that of planar nanocrystalline CdSe devices can be attributed to coaxial gating. The control of dimensions afforded by template synthesis should make it possible to reduce the gate dielectric thickness, channel length, and diameter of the semiconductor segment to sublithographic dimensions while retaining the simplicity of the wet chemical synthetic method.

Low-voltage organic electronics based on a gate-tunable injection barrier in vertical graphene-organic semiconductor heterostructures.

PubMed

Hlaing, Htay; Kim, Chang-Hyun; Carta, Fabio; Nam, Chang-Yong; Barton, Rob A; Petrone, Nicholas; Hone, James; Kymissis, Ioannis

2015-01-14

The vertical integration of graphene with inorganic semiconductors, oxide semiconductors, and newly emerging layered materials has recently been demonstrated as a promising route toward novel electronic and optoelectronic devices. Here, we report organic thin film transistors based on vertical heterojunctions of graphene and organic semiconductors. In these thin heterostructure devices, current modulation is accomplished by tuning of the injection barriers at the semiconductor/graphene interface with the application of a gate voltage. N-channel devices fabricated with a thin layer of C60 show a room temperature on/off ratio >10(4) and current density of up to 44 mAcm(-2). Because of the ultrashort channel intrinsic to the vertical structure, the device is fully operational at a driving voltage of 200 mV. A complementary p-channel device is also investigated, and a logic inverter based on two complementary transistors is demonstrated. The vertical integration of graphene with organic semiconductors via simple, scalable, and low-temperature fabrication processes opens up new opportunities to realize flexible, transparent organic electronic, and optoelectronic devices.

Correlation of film morphology and defect content with the charge-carrier transport in thin-film transistors based on ZnO nanoparticles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Polster, S.; Jank, M. P. M.; Frey, L.

2016-01-14

The correlation of defect content and film morphology with the charge-carrier transport in field-effect devices based on zinc oxide nanoparticles was investigated. Changes in the defect content and the morphology were realized by annealing and sintering of the nanoparticle thin films. Temperature-dependent electrical measurements reveal that the carrier transport is thermally activated for both the unsintered and sintered thin films. Reduced energetic barrier heights between the particles have been determined after sintering. Additionally, the energetic barrier heights between the particles can be reduced by increasing the drain-to-source voltage and the gate-to-source voltage. The changes in the barrier height are discussedmore » with respect to information obtained by scanning electron microscopy and photoluminescence measurements. It is found that a reduction of surface states and a lower roughness at the interface between the particle layer and the gate dielectric lead to lower barrier heights. Both surface termination and layer morphology at the interface affect the barrier height and thus are the main criteria for mobility improvement and device optimization.« less

Gate-tunable memristive phenomena mediated by grain boundaries in single-layer MoS2

NASA Astrophysics Data System (ADS)

Sangwan, Vinod K.; Jariwala, Deep; Kim, In Soo; Chen, Kan-Sheng; Marks, Tobin J.; Lauhon, Lincoln J.; Hersam, Mark C.

2015-05-01

Continued progress in high-speed computing depends on breakthroughs in both materials synthesis and device architectures. The performance of logic and memory can be enhanced significantly by introducing a memristor, a two-terminal device with internal resistance that depends on the history of the external bias voltage. State-of-the-art memristors, based on metal-insulator-metal (MIM) structures with insulating oxides, such as TiO2, are limited by a lack of control over the filament formation and external control of the switching voltage. Here, we report a class of memristors based on grain boundaries (GBs) in single-layer MoS2 devices. Specifically, the resistance of GBs emerging from contacts can be easily and repeatedly modulated, with switching ratios up to ˜103 and a dynamic negative differential resistance (NDR). Furthermore, the atomically thin nature of MoS2 enables tuning of the set voltage by a third gate terminal in a field-effect geometry, which provides new functionality that is not observed in other known memristive devices.

Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

NASA Astrophysics Data System (ADS)

Han, Jinhua; Wang, Wei; Ying, Jun; Xie, Wenfa

2014-01-01

An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized.

Study of SiO2-Si and metal-oxide-semiconductor structures using positrons

NASA Astrophysics Data System (ADS)

Leung, T. C.; Asoka-Kumar, P.; Nielsen, B.; Lynn, K. G.

1993-01-01

Studies of SiO2-Si and metal-oxide-semiconductor (MOS) structures using positrons are summarized and a concise picture of the present understanding of positrons in these systems is provided. Positron annihilation line-shape S data are presented as a function of the positron incident energy, gate voltage, and annealing, and are described with a diffusion-annihilation equation for positrons. The data are compared with electrical measurements. Distinct annihilation characteristics were observed at the SiO2-Si interface and have been studied as a function of bias voltage and annealing conditions. The shift of the centroid (peak) of γ-ray energy distributions in the depletion region of the MOS structures was studied as a function of positron energy and gate voltage, and the shifts are explained by the corresponding variations in the strength of the electric field and thickness of the depletion layer. The potential role of the positron annihilation technique as a noncontact, nondestructive, and depth-sensitive characterization tool for the technologically important, deeply buried interface is shown.

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Mizubayashi, Wataru; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Masahara, Meishoku

2014-01-01

Three-dimensional (3D) fin-channel charge trapping (CT) flash memories with different gate materials of physical-vapor-deposited (PVD) titanium nitride (TiN) and n+-polycrystalline silicon (poly-Si) have successfully been fabricated by using (100)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. Electrical characteristics of the fabricated flash memories including statistical threshold voltage (Vt) variability, endurance, and data retention have been comparatively investigated. It was experimentally found that a larger memory window and a deeper erase are obtained in PVD-TiN-gated metal-oxide-nitride-oxide-silicon (MONOS)-type flash memories than in poly-Si-gated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type memories. The larger memory window and deeper erase of MONOS-type flash memories are contributed by the higher work function of the PVD-TiN metal gate than of the n+-poly-Si gate, which is effective for suppressing electron back tunneling during erase operation. It was also found that the initial Vt roll-off due to the short-channel effect (SCE) is directly related to the memory window roll-off when the gate length (Lg) is scaled down to 46 nm or less.

Investigation of field induced trapping on floating gates

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1975-01-01

The development of a technology for building electrically alterable read only memories (EAROMs) or reprogrammable read only memories (RPROMs) using a single level metal gate p channel MOS process with all conventional processing steps is outlined. Nonvolatile storage of data is achieved by the use of charged floating gate electrodes. The floating gates are charged by avalanche injection of hot electrodes through gate oxide, and discharged by avalanche injection of hot holes through gate oxide. Three extra diffusion and patterning steps are all that is required to convert a standard p channel MOS process into a nonvolatile memory process. For identification, this nonvolatile memory technology was given the descriptive acronym DIFMOS which stands for Dual Injector, Floating gate MOS.

Effect of atomic layer deposition temperature on current conduction in Al2O3 films formed using H2O oxidant

NASA Astrophysics Data System (ADS)

Hiraiwa, Atsushi; Matsumura, Daisuke; Kawarada, Hiroshi

2016-08-01

To develop high-performance, high-reliability gate insulation and surface passivation technologies for wide-bandgap semiconductor devices, the effect of atomic layer deposition (ALD) temperature on current conduction in Al2O3 films is investigated based on the recently proposed space-charge-controlled field emission model. Leakage current measurement shows that Al2O3 metal-insulator-semiconductor capacitors formed on the Si substrates underperform thermally grown SiO2 capacitors at the same average field. However, using equivalent oxide field as a more practical measure, the Al2O3 capacitors are found to outperform the SiO2 capacitors in the cases where the capacitors are negatively biased and the gate material is adequately selected to reduce virtual dipoles at the gate/Al2O3 interface. The Al2O3 electron affinity increases with the increasing ALD temperature, but the gate-side virtual dipoles are not affected. Therefore, the leakage current of negatively biased Al2O3 capacitors is approximately independent of the ALD temperature because of the compensation of the opposite effects of increased electron affinity and permittivity in Al2O3. By contrast, the substrate-side sheet of charge increases with increasing ALD temperature above 210 °C and hence enhances the current of positively biased Al2O3 capacitors more significantly at high temperatures. Additionally, an anomalous oscillatory shift of the current-voltage characteristics with ALD temperature was observed in positively biased capacitors formed by low-temperature (≤210 °C) ALD. This shift is caused by dipoles at the Al2O3/underlying SiO2 interface. Although they have a minimal positive-bias leakage current, the low-temperature-grown Al2O3 films cause the so-called blisters problem when heated above 400 °C. Therefore, because of the absence of blistering, a 450 °C ALD process is presently the most promising technology for growing high-reliability Al2O3 films.

Accurate characterization and understanding of interface trap density trends between atomic layer deposited dielectrics and AlGaN/GaN with bonding constraint theory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ramanan, Narayanan; Lee, Bongmook; Misra, Veena, E-mail: vmisra@ncsu.edu

2015-06-15

Many dielectrics have been proposed for the gate stack or passivation of AlGaN/GaN based metal oxide semiconductor heterojunction field effect transistors, to reduce gate leakage and current collapse, both for power and RF applications. Atomic Layer Deposition (ALD) is preferred for dielectric deposition as it provides uniform, conformal, and high quality films with precise monolayer control of film thickness. Identification of the optimum ALD dielectric for the gate stack or passivation requires a critical investigation of traps created at the dielectric/AlGaN interface. In this work, a pulsed-IV traps characterization method has been used for accurate characterization of interface traps withmore » a variety of ALD dielectrics. High-k dielectrics (HfO{sub 2}, HfAlO, and Al{sub 2}O{sub 3}) are found to host a high density of interface traps with AlGaN. In contrast, ALD SiO{sub 2} shows the lowest interface trap density (<2 × 10{sup 12 }cm{sup −2}) after annealing above 600 °C in N{sub 2} for 60 s. The trend in observed trap densities is subsequently explained with bonding constraint theory, which predicts a high density of interface traps due to a higher coordination state and bond strain in high-k dielectrics.« less

High temperature interface superconductivity

DOE PAGES

Gozar, A.; Bozovic, I.

2016-01-20

High-T c superconductivity at interfaces has a history of more than a couple of decades. In this review we focus our attention on copper-oxide based heterostructures and multi-layers. We first discuss the technique, atomic layer-by-layer molecular beam epitaxy (ALL-MBE) engineering, that enabled High-T c Interface Superconductivity (HT-IS), and the challenges associated with the realization of high quality interfaces. Then we turn our attention to the experiments which shed light on the structure and properties of interfacial layers, allowing comparison to those of single-phase films and bulk crystals. Both ‘passive’ hetero-structures as well as surface-induced effects by external gating are discussed.more » Here, we conclude by comparing HT-IS in cuprates and in other classes of materials, especially Fe-based superconductors, and by examining the grand challenges currently laying ahead for the field.« less

Characterizing the structure of topological insulator thin films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Richardella, Anthony; Kandala, Abhinav; Lee, Joon Sue

2015-08-01

We describe the characterization of structural defects that occur during molecular beam epitaxy of topological insulator thin films on commonly used substrates. Twinned domains are ubiquitous but can be reduced by growth on smooth InP (111)A substrates, depending on details of the oxide desorption. Even with a low density of twins, the lattice mismatch between (Bi, Sb){sub 2}Te{sub 3} and InP can cause tilts in the film with respect to the substrate. We also briefly discuss transport in simultaneously top and back electrically gated devices using SrTiO{sub 3} and the use of capping layers to protect topological insulator films frommore » oxidation and exposure.« less

Mixed protonic and electronic conductors hybrid oxide synaptic transistors

NASA Astrophysics Data System (ADS)

Fu, Yang Ming; Zhu, Li Qiang; Wen, Juan; Xiao, Hui; Liu, Rui

2017-05-01

Mixed ionic and electronic conductor hybrid devices have attracted widespread attention in the field of brain-inspired neuromorphic systems. Here, mixed protonic and electronic conductor (MPEC) hybrid indium-tungsten-oxide (IWO) synaptic transistors gated by nanogranular phosphorosilicate glass (PSG) based electrolytes were obtained. Unique field-configurable proton self-modulation behaviors were observed on the MPEC hybrid transistor with extremely strong interfacial electric-double-layer effects. Temporally coupled synaptic plasticities were demonstrated on the MPEC hybrid IWO synaptic transistor, including depolarization/hyperpolarization, synaptic facilitation and depression, facilitation-stead/depression-stead behaviors, spiking rate dependent plasticity, and high-pass/low-pass synaptic filtering behaviors. MPEC hybrid synaptic transistors may find potential applications in neuron-inspired platforms.

Solution-Processed Transistors Using Colloidal Nanocrystals with Composition-Matched Molecular "Solders": Approaching Single Crystal Mobility.

PubMed

Jang, Jaeyoung; Dolzhnikov, Dmitriy S; Liu, Wenyong; Nam, Sooji; Shim, Moonsub; Talapin, Dmitri V

2015-10-14

Crystalline silicon-based complementary metal-oxide-semiconductor transistors have become a dominant platform for today's electronics. For such devices, expensive and complicated vacuum processes are used in the preparation of active layers. This increases cost and restricts the scope of applications. Here, we demonstrate high-performance solution-processed CdSe nanocrystal (NC) field-effect transistors (FETs) that exhibit very high carrier mobilities (over 400 cm(2)/(V s)). This is comparable to the carrier mobilities of crystalline silicon-based transistors. Furthermore, our NC FETs exhibit high operational stability and MHz switching speeds. These NC FETs are prepared by spin coating colloidal solutions of CdSe NCs capped with molecular solders [Cd2Se3](2-) onto various oxide gate dielectrics followed by thermal annealing. We show that the nature of gate dielectrics plays an important role in soldered CdSe NC FETs. The capacitance of dielectrics and the NC electronic structure near gate dielectric affect the distribution of localized traps and trap filling, determining carrier mobility and operational stability of the NC FETs. We expand the application of the NC soldering process to core-shell NCs consisting of a III-V InAs core and a CdSe shell with composition-matched [Cd2Se3](2-) molecular solders. Soldering CdSe shells forms nanoheterostructured material that combines high electron mobility and near-IR photoresponse.

Three dimensional graphene transistor for ultra-sensitive pH sensing directly in biological media.

PubMed

Ameri, Shideh Kabiri; Singh, Pramod K; Sonkusale, Sameer R

2016-08-31

In this work, pH sensing directly in biological media using three dimensional liquid gated graphene transistors is presented. The sensor is made of suspended network of graphene coated all around with thin layer of hafnium oxide (HfO2), showing high sensitivity and sensing beyond the Debye-screening limit. The performance of the pH sensor is validated by measuring the pH of isotonic buffered, Dulbecco's phosphate buffered saline (DPBS) solution, and of blood serum derived from Sprague-Dawley rat. The pH sensor shows high sensitivity of 71 ± 7 mV/pH even in high ionic strength media with molarities as high as 289 ± 1 mM. High sensitivity of this device is owing to suspension of three dimensional graphene in electrolyte which provides all around liquid gating of graphene, leading to higher electrostatic coupling efficiency of electrolyte to the channel and higher gating control of transistor channel by ions in the electrolyte. Coating graphene with hafnium oxide film (HfO2) provides binding sites for hydrogen ions, which results in higher sensitivity and sensing beyond the Debye-screening limit. The 3D graphene transistor offers the possibility of real-time pH measurement in biological media without the need for desaltation or sample preparation. Copyright © 2016 Elsevier B.V. All rights reserved.

Scalable ferroelectric MOS capacitors comprised of single crystalline SrZrxTi1-xO3 on Ge.

NASA Astrophysics Data System (ADS)

Moghadam, Reza; Xiao, Z.-Y.; Ahmadi-Majlan, K.; Grimley, E.; Ong, P. V.; Lebeau, J. M.; Chambers, S. A.; Hong, X.; Sushko, P.; Ngai, J. H.

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to field-effect devices that require very little power to operate, or that possess both logic and memory functionalities. The development of metal-oxide-semiconductor (MOS) capacitors in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel is essential in order to realize such field-effect devices. Here we demonstrate that scalable, ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x = 0.7) that has been epitaxially grown on Ge. Single crystalline SrZrxTi1-xO3 exhibits characteristics that are ideal for a ferroelectric gate material, namely, a type-I band offset with respect to Ge, large coercive fields and polarization that can be enhanced with electric field. The latter characteristic stems from the relaxor nature of SrZrxTi1-xO3. These properties enable MOS capacitors with 5 nm thick SrZrxTi1-xO3 layers to exhibit a nearly 2 V wide hysteretic window in the capacitance-voltage characteristics. The realization of ferroelectric MOS capacitors with technologically relevant gate thicknesses opens the pathway to practical field effect devices. NSF DMR 1508530.

Epitaxial GeSn film formed by solid phase epitaxy and its application to Yb{sub 2}O{sub 3}-gated GeSn metal-oxide-semiconductor capacitors with sub-nm equivalent oxide thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Ching-Wei; Wu, Yung-Hsien; Hsieh, Ching-Heng

2014-11-17

Through the technique of solid phase epitaxy (SPE), an epitaxial Ge{sub 0.955}Sn{sub 0.045} film was formed on a Ge substrate by depositing an amorphous GeSn film followed by a rapid thermal annealing at 550 °C. A process that uses a SiO{sub 2} capping layer on the amorphous GeSn film during SPE was proposed and it prevents Sn precipitation from occurring while maintaining a smooth surface due to the reduced surface mobility of Sn atoms. The high-quality epitaxial GeSn film was observed to have single crystal structure, uniform thickness and composition, and tiny surface roughness with root mean square of 0.56 nm. Withmore » a SnO{sub x}-free surface, Yb{sub 2}O{sub 3}-gated GeSn metal-oxide-semiconductor (MOS) capacitors with equivalent oxide thickness (EOT) of 0.55 nm were developed. A small amount of traps inside the Yb{sub 2}O{sub 3} was verified by negligible hysteresis in capacitance measurement. Low leakage current of 0.4 A/cm{sup 2} at gate bias of flatband voltage (V{sub FB})-1 V suggests the high quality of the gate dielectric. In addition, the feasibility of using Yb{sub 2}O{sub 3} to well passivate GeSn surface was also evidenced by the small interface trap density (D{sub it}) of 4.02 × 10{sup 11} eV{sup −1} cm{sup −2}, which can be attributed to smooth GeSn surface and Yb{sub 2}O{sub 3} valency passivation. Both leakage current and D{sub it} performance outperform other passivation techniques at sub-nm EOT regime. The proposed epitaxial GeSn film along with Yb{sub 2}O{sub 3} dielectric paves an alternative way to enable high-performance GeSn MOS devices.« less

Electroluminescence color tuning between green and red from metal-oxide-semiconductor devices fabricated by spin-coating of rare-earth (terbium + europium) organic compounds on silicon

NASA Astrophysics Data System (ADS)

Matsuda, Toshihiro; Hattori, Fumihiro; Iwata, Hideyuki; Ohzone, Takashi

2018-04-01

Color tunable electroluminescence (EL) from metal-oxide-semiconductor devices with the rare-earth elements Tb and Eu is reported. Organic compound liquid sources of (Tb + Ba) and Eu with various Eu/Tb ratios from 0.001 to 0.4 were spin-coated on an n+-Si substrate and annealed to form an oxide insulator layer. The EL spectra had only peaks corresponding to the intrashell Tb3+/Eu3+ transitions in the spectral range from green to red, and the intensity ratio of the peaks was appropriately tuned using the appropriate Eu/Tb ratios in liquid sources. Consequently, the EL emission colors linearly changed from yellowish green to yellowish orange and eventually to reddish orange on the CIE chromaticity diagram. The gate current +I G current also affected the EL colors for the medium-Eu/Tb-ratio device. The structure of the surface insulator films analyzed by cross-sectional transmission electron microscopy (TEM), X-ray diffraction (XRD) analysis, and X-ray photoelectron spectroscopy (XPS) has four layers, namely, (Tb4O7 + Eu2O3), [Tb4O7 + Eu2O3 + (Tb/Eu/Ba)SiO x ], (Tb/Eu/Ba)SiO x , and SiO x -rich oxide. The EL mechanism proposed is that electrons injected from the Si substrate into the SiO x -rich oxide and Tb/Eu/Ba-silicate layers become hot electrons accelerated in a high electric field, and then these hot electrons excite Tb3+ and Eu3+ ions in the Tb4O7/Eu2O3 layers resulting in EL emission from Tb3+ and Eu3+ intrashell transitions.

Restorative effect of oxygen annealing on device performance in HfIZO thin-film transistors

NASA Astrophysics Data System (ADS)

Ha, Tae-Jun

2015-03-01

Metal-oxide based thin-film transistors (oxide-TFTs) are very promising for use in next generation electronics such as transparent displays requiring high switching and driving performance. In this study, we demonstrate an optimized process to secure excellent device performance with a favorable shift of the threshold voltage toward 0V in amorphous hafnium-indium-zinc-oxide (a-HfIZO) TFTs by using post-treatment with oxygen annealing. This enhancement results from the improved interfacial characteristics between gate dielectric and semiconductor layers due to the reduction in the density of interfacial states related to oxygen vacancies afforded by oxygen annealing. The device statistics confirm the improvement in the device-to-device and run-to-run uniformity. We also report on the photo-induced stability in such oxide-TFTs against long-term UV irradiation, which is significant for transparent displays.

ALD TiO x as a top-gate dielectric and passivation layer for InGaZnO115 ISFETs

NASA Astrophysics Data System (ADS)

Pavlidis, S.; Bayraktaroglu, B.; Leedy, K.; Henderson, W.; Vogel, E.; Brand, O.

2017-11-01

The suitability of atomic layer deposited (ALD) titanium oxide (TiO x ) as a top gate dielectric and passivation layer for indium gallium zinc oxide (InGaZnO115) ion sensitive field effect transistors (ISFETs) is investigated. TiO x is an attractive barrier material, but reports of its use for InGaZnO thin film transistor (TFT) passivation have been conflicting thus far. In this work, it is found that the passivated TFT’s behavior depends on the TiO x deposition temperature, affecting critical device characteristics such as threshold voltage, field-effect mobility and sub-threshold swing. An O2 annealing step is required to recover TFT performance post passivation. It is also observed that the positive bias stress response of the passivated TFTs improves compared the original bare device. Secondary ion mass spectroscopy excludes the effects of hydrogen doping and inter-diffusion as sources of the temperature-dependent performance change, therefore indicating that oxygen gettering induced by TiO x passivation is the likely source of oxygen vacancies and, consequently, carriers in the InGaZnO film. It is also shown that potentiometric sensing using ALD TiO x exhibits a near Nernstian response to pH change, as well as minimizes V TH drift in TiO x passivated InGaZnO TFTs immersed in an acidic liquid. These results add to the understanding of InGaZnO passivation effects and underscore the potential for low-temperature fabricated InGaZnO ISFETs to be used as high-performance mobile chemical sensors.

Differential-Mode Biosensor Using Dual Extended-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Choi, Jinhyeon; Lee, Hee Ho; Ahn, Jungil; Seo, Sang-Ho; Shin, Jang-Kyoo

2012-06-01

In this paper, we present a differential-mode biosensor using dual extended-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), which possesses the advantages of both the extended-gate structure and the differential-mode operation. The extended-gate MOSFET was fabricated using a 0.6 µm standard complementary metal oxide semiconductor (CMOS) process. The Au extended gate is the sensing gate on which biomolecules are immobilized, while the Pt extended gate is the dummy gate for use in the differential-mode detection circuit. The differential-mode operation offers many advantages such as insensitivity to the variation of temperature and light, as well as low noise. The outputs were measured using a semiconductor parameter analyzer in a phosphate buffered saline (PBS; pH 7.4) solution. A standard Ag/AgCl reference electrode was used to apply the gate bias. We measured the variation of output voltage with time, temperature, and light intensity. The bindings of self-assembled monolayer (SAM), streptavidin, and biotin caused a variation in the output voltage of the differential-mode detection circuit and this was confirmed by surface plasmon resonance (SPR) experiment. Biotin molecules could be detected up to a concentration of as low as 0.001 µg/ml.

Synthesis, integration, and characterization of metal oxide films as alternative gate dielectric materials

NASA Astrophysics Data System (ADS)

Lin, You-Sheng

ZrO2 and HfO2 were investigated in this study to replace SiO2 as the potential gate dielectric materials in metal-oxide-semiconductor field effect transistors. ZrO2 and HfO2 films were deposited on p-type Si (100) wafers by an atomic layer chemical vapor deposition (ALCVD) process using zirconium (IV) t-butoxide and hafnium (IV) t-butoxide as the metal precursors, respectively. Oxygen was used alternatively with these metal alkoxide precursors into the reactor with purging and evacuation in between. The as-deposited ZrO2 and HfO2 films were stoichiometric and uniform based on X-ray photoemission spectroscopy and ellipsometry measurements. X-ray diffraction analysis indicated that the deposited films were amorphous, however, the high-resolution transmission electron microscopy showed an interfacial layer formation on the silicon substrate. Time-of-flight secondary ion mass spectrometry and medium energy ion scattering analysis showed significant intermixing between metal oxides and Si, indicating the formation of metal silicates, which were confirmed by their chemical etching resistance in HF solutions. The thermal stability of ZrO2 and HfO2 thin films on silicon was examined by monitoring their decomposition temperatures in ultra-high vacuum, using in-situ synchrotron radiation ultra-violet photoemission spectroscopy. The as-deposited ZrO2 and HfO2 thin films were thermally stable up to 880°C and 950°C in vacuum, respectively. The highest achieveable dielectric constants of as-deposited ZrO 2 and HfO2 were 21 and 24, respectively, which were slightly lower than the reported dielectric constants of bulk ZrO2 and HfO 2. These slight reductions in dielectric constants were attributed to the formation of the interfacial metal silicate layers. Very small hysteresis and interface state density were observed for both metal oxide films. Their leakage currents were a few orders of magnitude lower than that of SiO 2 at the same equivalent oxide thickness. NMOSFETs were also fabricated with the as-deposited metal oxide films, and reasonable ID-V D and IG-VG results were obtained. The electron mobilities were high from devices built using a plasma etching process to pattern the metal oxide films. However, they can be degraded if an HF wet etching process was used due to the large contact resistences. Upon oxygen annealing, the formation of SiOx at the interface improved the thermal stability of the as-deposited metal oxide films, however, lower overall dielectric constant and higher leakage current were observed. Upon ammonia annealing, the formation of SiOxNy improved not only the thermal stability but also reduced the leakage current. However, the overall dielectric constant of the film was still reduced due to the formation of the additional interfacial layer.

Visible-light-induced instability in amorphous metal-oxide based TFTs for transparent electronics

NASA Astrophysics Data System (ADS)

Ha, Tae-Jun

2014-10-01

We investigate the origin of visible-light-induced instability in amorphous metal-oxide based thin film transistors (oxide-TFTs) for transparent electronics by exploring the shift in threshold voltage (Vth). A large hysteresis window in amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs possessing large optical band-gap (≈3 eV) was observed in a visible-light illuminated condition whereas no hysteresis window was shown in a dark measuring condition. We also report the instability caused by photo irradiation and prolonged gate bias stress in oxide-TFTs. Larger Vth shift was observed after photo-induced stress combined with a negative gate bias than the sum of that after only illumination stress and only negative gate bias stress. Such results can be explained by trapped charges at the interface of semiconductor/dielectric and/or in the gate dielectric which play a role in a screen effect on the electric field applied by gate voltage, for which we propose that the localized-states-assisted transitions by visible-light absorption can be responsible.

Off-line wafer level reliability control: unique measurement method to monitor the lifetime indicator of gate oxide validated within bipolar/CMOS/DMOS technology

NASA Astrophysics Data System (ADS)

Gagnard, Xavier; Bonnaud, Olivier

2000-08-01

We have recently published a paper on a new rapid method for the determination of the lifetime of the gate oxide involved in a Bipolar/CMOS/DMOS technology (BCD). Because this previous method was based on a current measurement with gate voltage as a parameter needing several stress voltages, it was applied only by lot sampling. Thus, we tried to find an indicator in order to monitor the gate oxide lifetime during the wafer level parametric test and involving only one measurement of the device on each wafer test cell. Using the Weibull law and Crook model, combined with our recent model, we have developed a new test method needing only one electrical measurement of MOS capacitor to monitor the quality of the gate oxide. Based also on a current measurement, the parameter is the lifetime indicator of the gate oxide. From the analysis of several wafers, we gave evidence of the possibility to detect a low performance wafer, which corresponds to the infantile failure on the Weibull plot. In order to insert this new method in the BCD parametric program, a parametric flowchart was established. This type of measurement is an important challenges, because the actual measurements, breakdown charge, Qbd, and breakdown electric field, Ebd, at parametric level and Ebd and interface states density, Dit during the process cannot guarantee the gate oxide lifetime all along fabrication process. This indicator measurement is the only one, which predicts the lifetime decrease.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-02-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-05-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors

PubMed Central

Fan, Ching-Lin; Shang, Ming-Chi; Wang, Shea-Jue; Hsia, Mao-Yuan; Lee, Win-Der; Huang, Bohr-Ran

2017-01-01

In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W). PMID:28773101

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors.

PubMed

Fan, Ching-Lin; Shang, Ming-Chi; Wang, Shea-Jue; Hsia, Mao-Yuan; Lee, Win-Der; Huang, Bohr-Ran

2017-07-03

In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W).

High-κ gate dielectrics: Current status and materials properties considerations

NASA Astrophysics Data System (ADS)

Wilk, G. D.; Wallace, R. M.; Anthony, J. M.

2001-05-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward successful integration into the expected processing conditions for future CMOS technologies, especially due to their tendency to form at interfaces with Si (e.g. silicates). These pseudobinary systems also thereby enable the use of other high-κ materials by serving as an interfacial high-κ layer. While work is ongoing, much research is still required, as it is clear that any material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Electron-beam irradiation-induced gate oxide degradation

NASA Astrophysics Data System (ADS)

Cho, Byung Jin; Chong, Pei Fen; Chor, Eng Fong; Joo, Moon Sig; Yeo, In Seok

2000-12-01

Gate oxide degradation induced by electron-beam irradiation has been studied. A large increase in the low-field excess leakage current was observed on irradiated oxides and this was very similar to electrical stress-induced leakage currents. Unlike conventional electrical stress-induced leakage currents, however, electron-beam induced leakage currents exhibit a power law relationship with fluency without any signs of saturation. It has also been found that the electron-beam neither accelerates nor initiates quasibreakdown of the ultrathin gate oxide. Therefore, the traps generated by electron-beam irradiation do not contribute to quasibreakdown, only to the leakage current.

Enhancement of thermal stability and water resistance in yttrium-doped GeO{sub 2}/Ge gate stack

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Cimang, E-mail: cimang@adam.t.u-tokyo.ac.jp; Hyun Lee, Choong; Zhang, Wenfeng

2014-03-03

We have systematically investigated the material and electrical properties of yttrium-doped GeO{sub 2} (Y-GeO{sub 2}) on Germanium (Ge). A significant improvement of both thermal stability and water resistance were demonstrated by Y-GeO{sub 2}/Ge stack, compared to that of pure GeO{sub 2}/Ge stack. The excellent electrical properties of Y-GeO{sub 2}/Ge stacks with low D{sub it} were presented as well as enhancement of dielectric constant in Y-GeO{sub 2} layer, which is beneficial for further equivalent oxide thickness scaling of Ge gate stack. The improvement of thermal stability and water resistance are discussed both in terms of the Gibbs free energy lowering andmore » network modification of Y-GeO{sub 2}.« less

Fabrication of quantum dots in undoped Si/Si 0.8Ge 0.2 heterostructures using a single metal-gate layer

DOE PAGES

Lu, T. M.; Gamble, J. K.; Muller, R. P.; ...

2016-08-01

Enhancement-mode Si/SiGe electron quantum dots have been pursued extensively by many groups for their potential in quantum computing. Most of the reported dot designs utilize multiple metal-gate layers and use Si/SiGe heterostructures with Ge concentration close to 30%. Here, we report the fabrication and low-temperature characterization of quantum dots in the Si/Si 0.8Ge 0.2 heterostructures using only one metal-gate layer. We find that the threshold voltage of a channel narrower than 1 μm increases as the width decreases. The higher threshold can be attributed to the combination of quantum confinement and disorder. We also find that the lower Ge ratiomore » used here leads to a narrower operational gate bias range. The higher threshold combined with the limited gate bias range constrains the device design of lithographic quantum dots. We incorporate such considerations in our device design and demonstrate a quantum dot that can be tuned from a single dot to a double dot. Furthermore, the device uses only a single metal-gate layer, greatly simplifying device design and fabrication.« less

Improved Mobility and Bias Stability of Thin Film Transistors Using the Double-Layer a-InGaZnO/a-InGaZnO:N Channel.

PubMed

Yu, H; Zhang, L; Li, X H; Xu, H Y; Liu, Y C

2016-04-01

The amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFTs) were demonstrated based on a double-layer channel structure, where the channel is composed of an ultrathin nitro-genated a-IGZO (a-IGZO:N) layer and an undoped a-IGZO layer. The double-layer channel device showed higher saturation mobility and lower threshold-voltage shift (5.74 cm2/Vs, 2.6 V) compared to its single-layer counterpart (0.17 cm2/Vs, 7.23 V). The improvement can be attributed to three aspects: (1) improved carrier transport properties of the channel by the a-IGZO:N layer with high carrier mobility and the a-IGZO layer with high carrier concentration, (2) reduced interfacial trap density between the active channel and the gate insulator, and (3) higher surface flatness of the double-layer channel. Our study reveals key insights into double-layer channel, involving selecting more suitable electrical property for back-channel layer and more suitable interface modification for active layer. Meanwhile, room temperature fabrication amorphous TFTs offer certain advantages on better flexibility and higher uniformity over a large area.

Near interface traps in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fiorenza, Patrick; La Magna, Antonino; Vivona, Marilena

This letter reports on the impact of gate oxide trapping states on the conduction mechanisms in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs). The phenomena were studied by gate current transient measurements, performed on n-channel MOSFETs operated in “gate-controlled-diode” configuration. The measurements revealed an anomalous non-steady conduction under negative bias (V{sub G} > |20 V|) through the SiO{sub 2}/4H-SiC interface. The phenomenon was explained by the coexistence of a electron variable range hopping and a hole Fowler-Nordheim (FN) tunnelling. A semi-empirical modified FN model with a time-depended electric field is used to estimate the near interface traps in the gate oxide (N{sub trap} ∼ 2 × 10{supmore » 11} cm{sup −2}).« less

DIFMOS - A floating-gate electrically erasable nonvolatile semiconductor memory technology. [Dual Injector Floating-gate MOS

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1977-01-01

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.

Fabrication of 4H-SiC lateral double implanted MOSFET on an on-axis semi-insulating substrate without using epi-layer

NASA Astrophysics Data System (ADS)

Kim, Hyoung Woo; Seok, Ogyun; Moon, Jeong Hyun; Bahng, Wook; Jo, Jungyol

2017-12-01

4H-SiC lateral double implanted metal-oxide-semiconductor field effect transistors (LDIMOSFET) were fabricated on on-axis semi-insulating SiC substrates without using an epi-layer. The LDIMOSFET adopted a current path layer (CPL), which was formed by ion-implantation. The CPL works as a drift region between gate and drain. By using on-axis semi-insulating substrate and optimized CPL parameters, breakdown voltage (BV) of 1093 V and specific on-resistance (R on,sp) of 89.8 mΩ·cm2 were obtained in devices with 20 µm long CPL. Experimentally extracted field-effect channel mobility was 21.7 cm2·V-1·s-1 and the figure-of-merit (BV2/R on,sp) was 13.3 MW/cm2.

The role of cleaning conditions and epitaxial layer structure on reliability of Sc 2O 3 and MgO passivation on AlGaN/GaN HEMTS

NASA Astrophysics Data System (ADS)

Luo, B.; Mehandru, R. M.; Kim, Jihyun; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Fitch, R. C.; Gillespie, J.; Dellmer, R.; Jenkins, T.; Sewell, J.; Via, D.; Crespo, A.

2002-12-01

The effect of layer structure (GaN versus AlGaN cap) and cleaning procedure prior to Sc 2O 3 or MgO deposition at 100 °C were examined for their effects on the long-term bias-stress stability of AlGaN/GaN high electron mobility transistors (HEMTs). Surface cleaning by itself was not sufficient to prevent current collapse in the devices. The forward and reverse gate leakage currents were decreased under most conditions upon deposition of the oxide passivation layers. After ≈13 h of bias-stressing, the MgO-passivated HEMTs retain ⩾90% their initial drain-source current. The Sc 2O 3-passivated devices retained ˜80% recovery of the current under the same conditions.

Simultaneous control of thermoelectric properties in p- and n-type materials by electric double-layer gating: New design for thermoelectric device

NASA Astrophysics Data System (ADS)

Takayanagi, Ryohei; Fujii, Takenori; Asamitsu, Atsushi

2015-05-01

We report a novel design of a thermoelectric device that can control the thermoelectric properties of p- and n-type materials simultaneously by electric double-layer gating. Here, p-type Cu2O and n-type ZnO were used as the positive and negative electrodes of the electric double-layer capacitor structure. When a gate voltage was applied between the two electrodes, holes and electrons accumulated on the surfaces of Cu2O and ZnO, respectively. The thermopower was measured by applying a thermal gradient along the accumulated layer on the electrodes. We demonstrate here that the accumulated layers worked as a p-n pair of the thermoelectric device.

High Mobility Thin Film Transistors Based on Amorphous Indium Zinc Tin Oxide

PubMed Central

Noviyana, Imas; Lestari, Annisa Dwi; Putri, Maryane; Won, Mi-Sook; Bae, Jong-Seong; Heo, Young-Woo; Lee, Hee Young

2017-01-01

Top-contact bottom-gate thin film transistors (TFTs) with zinc-rich indium zinc tin oxide (IZTO) active layer were prepared at room temperature by radio frequency magnetron sputtering. Sintered ceramic target was prepared and used for deposition from oxide powder mixture having the molar ratio of In2O3:ZnO:SnO2 = 2:5:1. Annealing treatment was carried out for as-deposited films at various temperatures to investigate its effect on TFT performances. It was found that annealing treatment at 350 °C for 30 min in air atmosphere yielded the best result, with the high field effect mobility value of 34 cm2/Vs and the minimum subthreshold swing value of 0.12 V/dec. All IZTO thin films were amorphous, even after annealing treatment of up to 350 °C. PMID:28773058

Room-temperature phosphorescence logic gates developed from nucleic acid functionalized carbon dots and graphene oxide

NASA Astrophysics Data System (ADS)

Gui, Rijun; Jin, Hui; Wang, Zonghua; Zhang, Feifei; Xia, Jianfei; Yang, Min; Bi, Sai; Xia, Yanzhi

2015-04-01

Room-temperature phosphorescence (RTP) logic gates were developed using capture ssDNA (cDNA) modified carbon dots and graphene oxide (GO). The experimental results suggested the feasibility of these developed RTP-based ``OR'', ``INHIBIT'' and ``OR-INHIBIT'' logic gate operations, using Hg2+, target ssDNA (tDNA) and doxorubicin (DOX) as inputs.Room-temperature phosphorescence (RTP) logic gates were developed using capture ssDNA (cDNA) modified carbon dots and graphene oxide (GO). The experimental results suggested the feasibility of these developed RTP-based ``OR'', ``INHIBIT'' and ``OR-INHIBIT'' logic gate operations, using Hg2+, target ssDNA (tDNA) and doxorubicin (DOX) as inputs. Electronic supplementary information (ESI) available: All experimental details, Part S1-3, Fig. S1-6 and Table S1. See DOI: 10.1039/c4nr07620f

Surface modification of a polyimide gate insulator with an yttrium oxide interlayer for aqueous-solution-processed ZnO thin-film transistors.

PubMed

Jang, Kwang-Suk; Wee, Duyoung; Kim, Yun Ho; Kim, Jinsoo; Ahn, Taek; Ka, Jae-Won; Yi, Mi Hye

2013-06-11

We report a simple approach to modify the surface of a polyimide gate insulator with an yttrium oxide interlayer for aqueous-solution-processed ZnO thin-film transistors. It is expected that the yttrium oxide interlayer will provide a surface that is more chemically compatible with the ZnO semiconductor than is bare polyimde. The field-effect mobility and the on/off current ratio of the ZnO TFT with the YOx/polyimide gate insulator were 0.456 cm(2)/V·s and 2.12 × 10(6), respectively, whereas the ZnO TFT with the polyimide gate insulator was inactive.

Performance and Stability Enhancement of In-Sn-Zn-O TFTs Using SiO2 Gate Dielectrics Grown by Low Temperature Atomic Layer Deposition.

PubMed

Sheng, Jiazhen; Han, Ju-Hwan; Choi, Wan-Ho; Park, Jozeph; Park, Jin-Seong

2017-12-13

Silicon dioxide (SiO 2 ) films were synthesized by plasma-enhanced atomic layer deposition (PEALD) using BTBAS [bis(tertiarybutylamino) silane] as the precursor and O 2 plasma as the reactant, at a temperature range from 50 to 200 °C. While dielectric constant values larger than 3.7 are obtained at all deposition temperatures, the leakage current levels are drastically reduced to below 10 -12 A at temperatures above 150 °C, which are similar to those obtained in thermally oxidized and PECVD grown SiO 2 . Thin film transistors (TFTs) based on In-Sn-Zn-O (ITZO) semiconductors were fabricated using thermal SiO 2 , PECVD SiO 2 , and PEALD SiO 2 grown at 150 °C as the gate dielectrics, and superior device performance and stability are observed in the last case. A linear field effect mobility of 68.5 cm 2 /(V s) and a net threshold voltage shift (ΔV th ) of approximately 1.2 V under positive bias stress (PBS) are obtained using the PEALD SiO 2 as the gate insulator. The relatively high concentration of hydrogen in the PEALD SiO 2 is suggested to induce a high carrier density in the ITZO layer deposited onto it, which results in enhanced charge transport properties. Also, it is most likely that the hydrogen atoms have passivated the electron traps related to interstitial oxygen defects, thus resulting in improved stability under PBS. Although the PECVD SiO 2 contains a hydrogen concentration similar to that of PEALD SiO 2 , its relatively large surface roughness appears to induce scattering effects and the generation of electron traps, which result in inferior device performance and stability.

Gate-Controllable Magneto-optic Kerr Effect in Layered Collinear Antiferromagnets

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sivadas, Nikhil; Okamoto, Satoshi; Xiao, Di

2016-12-23

In this paper, using symmetry arguments and a tight-binding model, we show that for layered collinear antiferromagnets, magneto-optic effects can be generated and manipulated by controlling crystal symmetries through a gate voltage. This provides a promising route for electric field manipulation of the magneto-optic effects without modifying the underlying magnetic structure. We further demonstrate the gate control of the magneto-optic Kerr effect (MOKE) in bilayer MnPSe 3 using first-principles calculations. Finally, the field-induced inversion symmetry breaking effect leads to gate-controllable MOKE, whose direction of rotation can be switched by the reversal of the gate voltage.

Three-State Quantum Dot Gate FETs Using ZnS-ZnMgS Lattice-Matched Gate Insulator on Silicon

NASA Astrophysics Data System (ADS)

Karmakar, Supriya; Suarez, Ernesto; Jain, Faquir C.

2011-08-01

This paper presents the three-state behavior of quantum dot gate field-effect transistors (FETs). GeO x -cladded Ge quantum dots (QDs) are site-specifically self-assembled over lattice-matched ZnS-ZnMgS high- κ gate insulator layers grown by metalorganic chemical vapor deposition (MOCVD) on silicon substrates. A model of three-state behavior manifested in the transfer characteristics due to the quantum dot gate is also presented. The model is based on the transfer of carriers from the inversion channel to two layers of cladded GeO x -Ge quantum dots.

Spin measurement in an undoped Si/SiGe double quantum dot incorporating a micromagnet

NASA Astrophysics Data System (ADS)

Wu, Xian; Ward, Daniel; Prance, Jonathan; Kim, Dohun; Shi, Zhan; Mohr, Robert; Gamble, John; Savage, Donald; Lagally, Max; Friesen, Mark; Coppersmith, Susan; Eriksson, Mark

2014-03-01

We present measurements on a double dot formed in an accumulation-mode undoped Si/SiGe heterostructure. The double dot incorporates a proximal micromagnet to generate a stable magnetic field difference between the quantum dots. The gate design incorporates two layers of gates, and the upper layer of gates is split into five different sections to decrease crosstalk between different gates. A novel pattern of the lower layer gates enhances the tunability of tunnel rates. We will describe our attempts to create a singlet-triplet qubit in this device. This work was supported in part by ARO(W911NF-12-0607), NSF(DMR-1206915), and the United States Department of Defense. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressly or implied, of the US Government. Now works at Lancaster University, UK.

III-V/Ge MOS device technologies for low power integrated systems

NASA Astrophysics Data System (ADS)

Takagi, S.; Noguchi, M.; Kim, M.; Kim, S.-H.; Chang, C.-Y.; Yokoyama, M.; Nishi, K.; Zhang, R.; Ke, M.; Takenaka, M.

2016-11-01

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. The plasma post oxidation to form GeOx interfacial layers is a key gate stack technology for Ge CMOS. Also, direct wafer bonding of ultrathin body quantum well III-V-OI channels, combined with Tri-gate structures, realizes high performance III-V n-MOSFETs on Si. We also demonstrate planar-type InGaAs and Ge/strained SOI TFETs. The defect-less p+-n source junction formation with steep impurity profiles is a key for high performance TFET operation.

Downscaling ferroelectric field effect transistors by using ferroelectric Si-doped HfO2

NASA Astrophysics Data System (ADS)

Martin, Dominik; Yurchuk, Ekaterina; Müller, Stefan; Müller, Johannes; Paul, Jan; Sundquist, Jonas; Slesazeck, Stefan; Schlösser, Till; van Bentum, Ralf; Trentzsch, Martin; Schröder, Uwe; Mikolajick, Thomas

2013-10-01

Throughout the 22 nm technology node HfO2 is established as a reliable gate dielectric in contemporary complementary metal oxide semiconductor (CMOS) technology. The working principle of ferroelectric field effect transistors FeFET has also been demonstrated for some time for dielectric materials like Pb[ZrxTi1-x]O3 and SrBi2Ta2O9. However, integrating these into contemporary downscaled CMOS technology nodes is not trivial due to the necessity of an extremely thick gate stack. Recent developments have shown HfO2 to have ferroelectric properties, given the proper doping. Moreover, these doped HfO2 thin films only require layer thicknesses similar to the ones already in use in CMOS technology. This work will show how the incorporation of Si induces ferroelectricity in HfO2 based capacitor structures and finally demonstrate non-volatile storage in nFeFETs down to a gate length of 100 nm. A memory window of 0.41 V can be retained after 20,000 switching cycles. Retention can be extrapolated to 10 years.

Effects of protein inter-layers on cell-diamond FET characteristics.

PubMed

Rezek, Bohuslav; Krátká, Marie; Kromka, Alexander; Kalbacova, Marie

2010-12-15

Diamond is recognized as an attractive material for merging solid-state and biological systems. The advantage of diamond field-effect transistors (FET) is that they are chemically resistant, bio-compatible, and can operate without gate oxides. Solution-gated FETs based on H-terminated nanocrystalline diamond films exhibiting surface conductivity are employed here for studying effects of fetal bovine serum (FBS) proteins and osteoblastic SAOS-2 cells on diamond electronic properties. FBS proteins adsorbed on the diamond FETs permanently decrease diamond conductivity as reflected by the -45 mV shift of the FET transfer characteristics. Cell cultivation for 2 days results in a further shift by another -78 mV. We attribute it to a change of diamond material properties rather than purely to the field-effect. Increase in gate leakage currents (by a factor of 4) indicates that the FBS proteins also decrease the diamond-electrolyte electronic barrier induced by C-H surface dipoles. We propose a model where the proteins replace ions in the very vicinity of the H-terminated diamond surface. Copyright © 2010 Elsevier B.V. All rights reserved.

Use of laser drilling in the manufacture of organic inverter circuits.

PubMed

Iba, Shingo; Kato, Yusaku; Sekitani, Tsuyoshi; Kawaguchi, Hiroshi; Sakurai, Takayasu; Someya, Takao

2006-01-01

Inverter circuits have been made by connecting two high-quality pentacene field-effect transistors. A uniform and pinhole-free 900 nm thick polyimide gate-insulating layer was formed on a flexible polyimide film with gold gate electrodes and partially removed by using a CO2 laser drilling machine to make via holes and contact holes. Subsequent evaporation of the gold layer results in good electrical connection with a gold gate layer underneath the gate-insulating layer. By optimization of the settings of the CO2 laser drilling machine, contact resistance can be reduced to as low as 3 ohms for 180 microm square electrodes. No degradation of the transport properties of the organic transistors was observed after the laser-drilling process. This study demonstrates the feasibility of using the laser drilling process for implementation of organic transistors in integrated circuits on flexible polymer films.

CCD imaging sensors

NASA Technical Reports Server (NTRS)

Janesick, James R. (Inventor); Elliott, Stythe T. (Inventor)

1989-01-01

A method for promoting quantum efficiency (QE) of a CCD imaging sensor for UV, far UV and low energy x-ray wavelengths by overthinning the back side beyond the interface between the substrate and the photosensitive semiconductor material, and flooding the back side with UV prior to using the sensor for imaging. This UV flooding promotes an accumulation layer of positive states in the oxide film over the thinned sensor to greatly increase QE for either frontside or backside illumination. A permanent or semipermanent image (analog information) may be stored in a frontside SiO.sub.2 layer over the photosensitive semiconductor material using implanted ions for a permanent storage and intense photon radiation for a semipermanent storage. To read out this stored information, the gate potential of the CCD is biased more negative than that used for normal imaging, and excess charge current thus produced through the oxide is integrated in the pixel wells for subsequent readout by charge transfer from well to well in the usual manner.

Flexible, polymer gated, AC-driven organic electroluminescence devices

NASA Astrophysics Data System (ADS)

Xu, Junwei; Carroll, David L.

2017-08-01

Comparing rigid inorganic layer, polymeric semiconducting gate layer exhibits superior flexibility as well as efficient carrier manipulation in high frequency AC cycles. Mechanism of the carrier manipulation at the gate in forward and reversed bias of AC cycle is studied. The flexible PET-based AC-OEL device with poly[(9,9-bis(3'-((N,N-dimethyl)-Nethylammonium)- propyl)-2,7-fluorene)-alt-2,7-(9,9-dioctylfluorene)] (PFN-Br) gate shows a stable electroluminescent performance in frequency sweep with a color rendering index (CRI) over 81 at 2800K color temperature.

Electrical characterization of 4H-SiC metal-oxide-semiconductor structure with Al2O3 stacking layers as dielectric

NASA Astrophysics Data System (ADS)

Chang, P. K.; Hwu, J. G.

2018-02-01

Interface defects and oxide bulk traps conventionally play important roles in the electrical performance of SiC MOS device. Introducing the Al2O3 stack grown by repeated anodization of Al films can notably lower the leakage current in comparison to the SiO2 structure, and enhance the minority carrier response at low frequency when the number of Al2O3 layers increase. In addition, the interface quality is not deteriorated by the stacking of Al2O3 layers because the stacked Al2O3 structure grown by anodization possesses good uniformity. In this work, the capacitance equivalent thickness (CET) of stacking Al2O3 will be up to 19.5 nm and the oxidation process can be carried out at room temperature. For the Al2O3 gate stack with CET 19.5 nm on n-SiC substrate, the leakage current at 2 V is 2.76 × 10-10 A/cm2, the interface trap density at the flatband voltage is 3.01 × 1011 eV-1 cm-2, and the effective breakdown field is 11.8 MV/cm. Frequency dispersion and breakdown characteristics may thus be improved as a result of the reduction in trap density. The Al2O3 stacking layers are capable of maintaining the leakage current as low as possible even after constant voltage stress test, which will further ameliorate reliability characteristics.

Improvement in the electrical performance and bias-stress stability of dual-active-layered silicon zinc oxide/zinc oxide thin-film transistor

NASA Astrophysics Data System (ADS)

Liu, Yu-Rong; Zhao, Gao-Wei; Lai, Pai-To; Yao, Ruo-He

2016-08-01

Si-doped zinc oxide (SZO) thin films are deposited by using a co-sputtering method, and used as the channel active layers of ZnO-based TFTs with single and dual active layer structures. The effects of silicon content on the optical transmittance of the SZO thin film and electrical properties of the SZO TFT are investigated. Moreover, the electrical performances and bias-stress stabilities of the single- and dual-active-layer TFTs are investigated and compared to reveal the effects of the Si doping and dual-active-layer structure. The average transmittances of all the SZO films are about 90% in the visible light region of 400 nm-800 nm, and the optical band gap of the SZO film gradually increases with increasing Si content. The Si-doping can effectively suppress the grain growth of ZnO, revealed by atomic force microscope analysis. Compared with that of the undoped ZnO TFT, the off-state current of the SZO TFT is reduced by more than two orders of magnitude and it is 1.5 × 10-12 A, and thus the on/off current ratio is increased by more than two orders of magnitude. In summary, the SZO/ZnO TFT with dual-active-layer structure exhibits a high on/off current ratio of 4.0 × 106 and superior stability under gate-bias and drain-bias stress. Projected supported by the National Natural Science Foundation of China (Grant Nos. 61076113 and 61274085), the Natural Science Foundation of Guangdong Province (Grant No. 2016A030313474), and the University Development Fund (Nanotechnology Research Institute, Grant No. 00600009) of the University of Hong Kong, China.

Permanent and Transient Radiation Effects on Thin-Oxide (200-A) MOS Transistors

DTIC Science & Technology

1976-06-01

n-channel technology using a SiO, gate-oxide thickness ol ’ 200 A and a %hallow phiosphorus diffusion of 0.5 pin on a 0.7-ohm)-cmn 8-doped > Si...substrate. The thickness of the sell-aligned it polysilicon gate was kept at 3500 A. The oxide was grown in dry 0, at a temperature ot 1000C, followed...semiconductor work function difference (equal to 0 V for the polysilicon gates’ studied here). The effect of the ionizing radiation is to introduce

Electron-beam-evaporated thin films of hafnium dioxide for fabricating electronic devices

DOE PAGES

Xiao, Zhigang; Kisslinger, Kim

2015-06-17

Thin films of hafnium dioxide (HfO 2) are widely used as the gate oxide in fabricating integrated circuits because of their high dielectric constants. In this paper, the authors report the growth of thin films of HfO 2 using e-beam evaporation, and the fabrication of complementary metal-oxide semiconductor (CMOS) integrated circuits using this HfO 2 thin film as the gate oxide. The authors analyzed the thin films using high-resolution transmission electron microscopy and electron diffraction, thereby demonstrating that the e-beam-evaporation-grown HfO 2 film has a polycrystalline structure and forms an excellent interface with silicon. Accordingly, we fabricated 31-stage CMOS ringmore » oscillator to test the quality of the HfO 2 thin film as the gate oxide, and obtained excellent rail-to-rail oscillation waveforms from it, denoting that the HfO 2 thin film functioned very well as the gate oxide.« less

Genetic programs constructed from layered logic gates in single cells

PubMed Central

Moon, Tae Seok; Lou, Chunbo; Tamsir, Alvin; Stanton, Brynne C.; Voigt, Christopher A.

2014-01-01

Genetic programs function to integrate environmental sensors, implement signal processing algorithms and control expression dynamics1. These programs consist of integrated genetic circuits that individually implement operations ranging from digital logic to dynamic circuits2–6, and they have been used in various cellular engineering applications, including the implementation of process control in metabolic networks and the coordination of spatial differentiation in artificial tissues. A key limitation is that the circuits are based on biochemical interactions occurring in the confined volume of the cell, so the size of programs has been limited to a few circuits1,7. Here we apply part mining and directed evolution to build a set of transcriptional AND gates in Escherichia coli. Each AND gate integrates two promoter inputs and controls one promoter output. This allows the gates to be layered by having the output promoter of an upstream circuit serve as the input promoter for a downstream circuit. Each gate consists of a transcription factor that requires a second chaperone protein to activate the output promoter. Multiple activator–chaperone pairs are identified from type III secretion pathways in different strains of bacteria. Directed evolution is applied to increase the dynamic range and orthogonality of the circuits. These gates are connected in different permutations to form programs, the largest of which is a 4-input AND gate that consists of 3 circuits that integrate 4 inducible systems, thus requiring 11 regulatory proteins. Measuring the performance of individual gates is sufficient to capture the behaviour of the complete program. Errors in the output due to delays (faults), a common problem for layered circuits, are not observed. This work demonstrates the successful layering of orthogonal logic gates, a design strategy that could enable the construction of large, integrated circuits in single cells. PMID:23041931

Charge injection from gate electrode by simultaneous stress of optical and electrical biases in HfInZnO amorphous oxide thin film transistor

NASA Astrophysics Data System (ADS)

Kwon, Dae Woong; Kim, Jang Hyun; Chang, Ji Soo; Kim, Sang Wan; Sun, Min-Chul; Kim, Garam; Kim, Hyun Woo; Park, Jae Chul; Song, Ihun; Kim, Chang Jung; Jung, U. In; Park, Byung-Gook

2010-11-01

A comprehensive study is done regarding stabilities under simultaneous stress of light and dc-bias in amorphous hafnium-indium-zinc-oxide thin film transistors. The positive threshold voltage (Vth) shift is observed after negative gate bias and light stress, and it is completely different from widely accepted phenomenon which explains that negative-bias stress results in Vth shift in the left direction by bias-induced hole-trapping. Gate current measurement is performed to explain the unusual positive Vth shift under simultaneous application of light and negative gate bias. As a result, it is clearly found that the positive Vth shift is derived from electron injection from gate electrode to gate insulator.

HfO2 Gate Dielectric on (NH4)2S Passivated (100) GaAs Grown by Atomic Layer Deposition

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, P.T.; /Stanford U., Materials Sci. Dept.; Sun, Y.

2007-09-28

The interface between hafnium oxide grown by atomic layer deposition and (100) GaAs treated with HCl cleaning and (NH{sub 4}){sub 2}S passivation has been characterized. Synchrotron radiation photoemission core level spectra indicated successful removal of the native oxides and formation of passivating sulfides on the GaAs surface. Layer-by-layer removal of the hafnia film revealed a small amount of As{sub 2}O{sub 3} formed at the interface during the dielectric deposition. Traces of arsenic and sulfur out-diffusion into the hafnia film were observed after a 450 C post-deposition anneal, and may be the origins for the electrically active defects. Transmission electron microscopymore » cross section images showed thicker HfO{sub 2} films for a given precursor exposure on S-treated GaAs versus the non-treated sample. In addition, the valence-band and the conduction-band offsets at the HfO{sub 2}/GaAs interface were deduced to be 3.18 eV and a range of 0.87-0.97 eV, respectively. It appears that HCl+(NH{sub 4})2{sub S} treatments provide a superior chemical passivation for GaAs and initial surface for ALD deposition.« less

A study of trap-limited conduction influenced by plasma damage on the source/drain regions of amorphous InGaZnO TFTs

NASA Astrophysics Data System (ADS)

Hsu, Chih-Chieh; Sun, Jhen-Kai; Wu, Chien-Hsun

2015-11-01

This study investigated electrical characteristics and stability variations of amorphous indium gallium zinc oxide thin film transistors (a-IGZO TFTs) with plasma damage on their source/drain (S/D) regions. The influence of the plasma damage on the TFT performance is absent as the channel length is 36-100 μm. When the channel length is decreased to 3-5 μm, the mobility (μ ) of the bottom gate TFT (BG TFT) with plasma damage is significantly degraded to 0.6 cm2 (V s)-1, which is much lower than 4.3 cm2 (V s)-1 of a damage-free BG TFT. We utilized the TFT passivation layer and the indium tin oxide (ITO), which was used as the pixel electrode material in the TFT backplane, to be the top gate insulator and top gate electrode of the defective BG TFT to obtain the defective dual-gate TFT. The mobility can be restored to 5.1 cm2 (V s)-1. Additional process steps are not required. Besides, this method is easily implemented and is fully compatible with TFT backplane fabrication process. The transfer curves, hysteresis characteristics, stabilities under constant voltage stress and constant current stress tests were measured to give evidences that the traps created by the plasma damage on the S/D regions indeed can affect electron transport. This trap-limited conduction can be improved by using the top gate. It was proven that the top gate was not for contributing an observably additional current. It was for inducing electrons to electrically passivate the plasma-induced defects near the back channel. Thus, the trapping/detrapping of the electrons transporting in the front channel can be reduced. The trap density near the Fermi level, hopping distance and hopping energy are 1.1  ×  1018 cm-3 eV-1, 162 Å, and 52 meV for the BG TFT with plasma damage on the S/D regions.

Planarized thick copper gate polycrystalline silicon thin film transistors for ultra-large AMOLED displays

NASA Astrophysics Data System (ADS)

Yun, Seung Jae; Lee, Yong Woo; Son, Se Wan; Byun, Chang Woo; Reddy, A. Mallikarjuna; Joo, Seung Ki

2012-08-01

A planarized thick copper (Cu) gate low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) is fabricated for ultra-large active-matrix organic light-emitting diode (AMOLED) displays. We introduce a damascene and chemical mechanical polishing process to embed a planarized Cu gate of 500 nm thickness into a trench and Si3N4/SiO2 multilayer gate insulator, to prevent the Cu gate from diffusing into the silicon (Si) layer at 550°C, and metal-induced lateral crystallization (MILC) technology to crystallize the amorphous Si layer. A poly-Si TFT with planarized thick Cu gate exhibits a field effect mobility of 5 cm2/Vs and a threshold voltage of -9 V, and a subthreshold swing (S) of 1.4 V/dec.

Intelligent layered nanoflare: "lab-on-a-nanoparticle" for multiple DNA logic gate operations and efficient intracellular delivery.

PubMed

Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

2014-08-07

DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a "lab-on-a-nanoparticle", the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.

Intelligent layered nanoflare: ``lab-on-a-nanoparticle'' for multiple DNA logic gate operations and efficient intracellular delivery

NASA Astrophysics Data System (ADS)

Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

2014-07-01

DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology. Electronic supplementary information (ESI) available: Additional figures (Table S1, Fig. S1-S5). See DOI: 10.1039/c4nr01676a

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

NASA Astrophysics Data System (ADS)

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-09-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec.

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

PubMed Central

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-01-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec. PMID:27641430

Electron mobility in the inversion layers of fully depleted SOI films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zaitseva, E. G., E-mail: ZaytsevaElza@yandex.ru; Naumova, O. V.; Fomin, B. I.

The dependences of the electron mobility μ{sub eff} in the inversion layers of fully depleted double–gate silicon-on-insulator (SOI) metal–oxide–semiconductor (MOS) transistors on the density N{sub e} of induced charge carriers and temperature T are investigated at different states of the SOI film (inversion–accumulation) from the side of one of the gates. It is shown that at a high density of induced charge carriers of N{sub e} > 6 × 10{sup 12} cm{sup –2} the μeff(T) dependences allow the components of mobility μ{sub eff} that are related to scattering at surface phonons and from the film/insulator surface roughness to be distinguished.more » The μ{sub eff}(N{sub e}) dependences can be approximated by the power functions μ{sub eff}(N{sub e}) ∝ N{sub e}{sup −n}. The exponents n in the dependences and the dominant mechanisms of scattering of electrons induced near the interface between the SOI film and buried oxide are determined for different N{sub e} ranges and film states from the surface side.« less

All diamond self-aligned thin film transistor

DOEpatents

Gerbi, Jennifer [Champaign, IL

2008-07-01

A substantially all diamond transistor with an electrically insulating substrate, an electrically conductive diamond layer on the substrate, and a source and a drain contact on the electrically conductive diamond layer. An electrically insulating diamond layer is in contact with the electrically conductive diamond layer, and a gate contact is on the electrically insulating diamond layer. The diamond layers may be homoepitaxial, polycrystalline, nanocrystalline or ultrananocrystalline in various combinations.A method of making a substantially all diamond self-aligned gate transistor is disclosed in which seeding and patterning can be avoided or minimized, if desired.

Single-electron-occupation metal-oxide-semiconductor quantum dots formed from efficient poly-silicon gate layout

DOE Office of Scientific and Technical Information (OSTI.GOV)

Carroll, Malcolm S.; rochette, sophie; Rudolph, Martin

We introduce a silicon metal-oxide-semiconductor quantum dot structure that achieves dot-reservoir tunnel coupling control without a dedicated barrier gate. The elementary structure consists of two accumulation gates separated spatially by a gap, one gate accumulating a reservoir and the other a quantum dot. Control of the tunnel rate between the dot and the reservoir across the gap is demonstrated in the single electron regime by varying the reservoir accumulation gate voltage while compensating with the dot accumulation gate voltage. The method is then applied to a quantum dot connected in series to source and drain reservoirs, enabling transport down tomore » the single electron regime. Finally, tuning of the valley splitting with the dot accumulation gate voltage is observed. This split accumulation gate structure creates silicon quantum dots of similar characteristics to other realizations but with less electrodes, in a single gate stack subtractive fabrication process that is fully compatible with silicon foundry manufacturing.« less

High Performance Amplifier Element Realization via MoS2/GaTe Heterostructures.

PubMed

Yan, Xiao; Zhang, David Wei; Liu, Chunsen; Bao, Wenzhong; Wang, Shuiyuan; Ding, Shijin; Zheng, Gengfeng; Zhou, Peng

2018-04-01

2D layered materials (2DLMs), together with their heterostructures, have been attracting tremendous research interest in recent years because of their unique physical and electrical properties. A variety of circuit elements have been made using mechanically exfoliated 2DLMs recently, including hard drives, detectors, sensors, and complementary metal oxide semiconductor field-effect transistors. However, 2DLM-based amplifier circuit elements are rarely studied. Here, the integration of 2DLMs with 3D bulk materials to fabricate vertical junction transistors with current amplification based on a MoS 2 /GaTe heterostructure is reported. Vertical junction transistors exhibit the typical current amplification characteristics of conventional bulk bipolar junction transistors while having good current transmission coefficients (α ∼ 0.95) and current gain coefficient (β ∼ 7) at room temperature. The devices provide new attractive prospects in the investigation of 2DLM-based integrated circuits based on amplifier circuits.

High Mobility Flexible Amorphous IGZO Thin-Film Transistors with a Low Thermal Budget Ultra-Violet Pulsed Light Process.

PubMed

Benwadih, M; Coppard, R; Bonrad, K; Klyszcz, A; Vuillaume, D

2016-12-21

Amorphous, sol-gel processed, indium gallium zinc oxide (IGZO) transistors on plastic substrate with a printable gate dielectric and an electron mobility of 4.5 cm 2 /(V s), as well as a mobility of 7 cm 2 /(V s) on solid substrate (Si/SiO 2 ) are reported. These performances are obtained using a low temperature pulsed light annealing technique. Ultraviolet (UV) pulsed light system is an innovative technique compared to conventional (furnace or hot-plate) annealing process that we successfully implemented on sol-gel IGZO thin film transistors (TFTs) made on plastic substrate. The photonic annealing treatment has been optimized to obtain IGZO TFTs with significant electrical properties. Organic gate dielectric layers deposited on this pulsed UV light annealed films have also been optimized. This technique is very promising for the development of amorphous IGZO TFTs on plastic substrates.

High mobility bottom gate InGaZnO thin film transistors with SiOx etch stopper

NASA Astrophysics Data System (ADS)

Kim, Minkyu; Jeong, Jong Han; Lee, Hun Jung; Ahn, Tae Kyung; Shin, Hyun Soo; Park, Jin-Seong; Jeong, Jae Kyeong; Mo, Yeon-Gon; Kim, Hye Dong

2007-05-01

The authors report on the fabrication of thin film transistors (TFTs), which use an amorphous indium gallium zinc oxide (a-IGZO) channel, by rf sputtering at room temperature and for which the channel length and width are patterned by photolithography and dry etching. To prevent plasma damage to the active channel, a 100-nm-thick SiOx layer deposited by plasma enhanced chemical vapor deposition was adopted as an etch stopper structure. The a-IGZO TFT (W /L=10μm/50μm) fabricated on glass exhibited a high field-effect mobility of 35.8cm2/Vs, a subthreshold gate swing value of 0.59V/decade, a thrseshold voltage of 5.9V, and an Ion/off ratio of 4.9×106, which is acceptable for use as the switching transistor of an active-matrix TFT backplane.

Optimization of pentacene double floating gate memories based on charge injection regulated by SAM functionalization

NASA Astrophysics Data System (ADS)

Li, S.; Guérin, D.; Lenfant, S.; Lmimouni, K.

2018-02-01

Pentacene based double nano-floating gate memories (NFGM) by using gold nanoparticles (Au NPs) and reduced graphene oxide (rGO) sheets as charge trapping layers are prepared and demonstrated. Particularly, the NFGM chemically treated by 2,3,4,5,6-pentafluorobenzenethiol (PFBT) self-assembled monolayers (SAM) exhibits excellent memory performances, including high mobility of 0.23 cm2V-1s-1, the large memory window of 51 V, and the stable retention property more than 108 s. Comparing the performances of NFGM without treating with PFBT SAM, the improving performances of the memory devices by SAM modification are explained by the increase of charge injection, which could be further investigated by XPS and UPS. In particular, the results highlight the utility of SAM modulations and controlling of charge transport in the development of organic transistor memories.

High Performance Amplifier Element Realization via MoS2/GaTe Heterostructures

PubMed Central

Yan, Xiao; Zhang, David Wei; Liu, Chunsen; Bao, Wenzhong; Wang, Shuiyuan; Ding, Shijin; Zheng, Gengfeng

2018-01-01

Abstract 2D layered materials (2DLMs), together with their heterostructures, have been attracting tremendous research interest in recent years because of their unique physical and electrical properties. A variety of circuit elements have been made using mechanically exfoliated 2DLMs recently, including hard drives, detectors, sensors, and complementary metal oxide semiconductor field‐effect transistors. However, 2DLM‐based amplifier circuit elements are rarely studied. Here, the integration of 2DLMs with 3D bulk materials to fabricate vertical junction transistors with current amplification based on a MoS2/GaTe heterostructure is reported. Vertical junction transistors exhibit the typical current amplification characteristics of conventional bulk bipolar junction transistors while having good current transmission coefficients (α ∼ 0.95) and current gain coefficient (β ∼ 7) at room temperature. The devices provide new attractive prospects in the investigation of 2DLM‐based integrated circuits based on amplifier circuits. PMID:29721428

Resonant tunneling device with two-dimensional quantum well emitter and base layers

DOEpatents

Simmons, J.A.; Sherwin, M.E.; Drummond, T.J.; Weckwerth, M.V.

1998-10-20

A double electron layer tunneling device is presented. Electrons tunnel from a two dimensional emitter layer to a two dimensional tunneling layer and continue traveling to a collector at a lower voltage. The emitter layer is interrupted by an isolation etch, a depletion gate, or an ion implant to prevent electrons from traveling from the source along the emitter to the drain. The collector is similarly interrupted by a backgate, an isolation etch, or an ion implant. When the device is used as a transistor, a control gate is added to control the allowed energy states of the emitter layer. The tunnel gate may be recessed to change the operating range of the device and allow for integrated complementary devices. Methods of forming the device are also set forth, utilizing epoxy-bond and stop etch (EBASE), pre-growth implantation of the backgate or post-growth implantation. 43 figs.

Resonant tunneling device with two-dimensional quantum well emitter and base layers

DOEpatents

Simmons, Jerry A.; Sherwin, Marc E.; Drummond, Timothy J.; Weckwerth, Mark V.

1998-01-01

A double electron layer tunneling device is presented. Electrons tunnel from a two dimensional emitter layer to a two dimensional tunneling layer and continue traveling to a collector at a lower voltage. The emitter layer is interrupted by an isolation etch, a depletion gate, or an ion implant to prevent electrons from traveling from the source along the emitter to the drain. The collector is similarly interrupted by a backgate, an isolation etch, or an ion implant. When the device is used as a transistor, a control gate is added to control the allowed energy states of the emitter layer. The tunnel gate may be recessed to change the operating range of the device and allow for integrated complementary devices. Methods of forming the device are also set forth, utilizing epoxy-bond and stop etch (EBASE), pre-growth implantation of the backgate or post-growth implantation.

Sensing small neurotransmitter-enzyme interaction with nanoporous gated ion-sensitive field effect transistors.

PubMed

Kisner, Alexandre; Stockmann, Regina; Jansen, Michael; Yegin, Ugur; Offenhäusser, Andreas; Kubota, Lauro Tatsuo; Mourzina, Yulia

2012-01-15

Ion-sensitive field effect transistors with gates having a high density of nanopores were fabricated and employed to sense the neurotransmitter dopamine with high selectivity and detectability at micromolar range. The nanoporous structure of the gates was produced by applying a relatively simple anodizing process, which yielded a porous alumina layer with pores exhibiting a mean diameter ranging from 20 to 35 nm. Gate-source voltages of the transistors demonstrated a pH-dependence that was linear over a wide range and could be understood as changes in surface charges during protonation and deprotonation. The large surface area provided by the pores allowed the physical immobilization of tyrosinase, which is an enzyme that oxidizes dopamine, on the gates of the transistors, and thus, changes the acid-base behavior on their surfaces. Concentration-dependent dopamine interacting with immobilized tyrosinase showed a linear dependence into a physiological range of interest for dopamine concentration in the changes of gate-source voltages. In comparison with previous approaches, a response time relatively fast for detecting dopamine was obtained. Additionally, selectivity assays for other neurotransmitters that are abundantly found in the brain were examined. These results demonstrate that the nanoporous structure of ion-sensitive field effect transistors can easily be used to immobilize specific enzyme that can readily and selectively detect small neurotransmitter molecule based on its acid-base interaction with the receptor. Therefore, it could serve as a technology platform for molecular studies of neurotransmitter-enzyme binding and drugs screening. Copyright © 2011 Elsevier B.V. All rights reserved.

Observations on the Presumed LET Dependence of SEGR

NASA Technical Reports Server (NTRS)

Selva, L.; Swift, G.; Taylor, W.; Edmonds, L.

1998-01-01

Single-event gate rupture (SEGR)in vertical power MOSFETs is induced by charge deposited in the epitaxial region (below the gate oxide) in concert with the weakening of the oxide, both are a result of the ion passage.

Fringing field effects in negative capacitance field-effect transistors with a ferroelectric gate insulator

NASA Astrophysics Data System (ADS)

Hattori, Junichi; Fukuda, Koichi; Ikegami, Tsutomu; Ota, Hiroyuki; Migita, Shinji; Asai, Hidehiro; Toriumi, Akira

2018-04-01

We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal-oxide-semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.

Potentiometric Detection of Pathogens

DTIC Science & Technology

2012-01-01

nanosize organic electrode (conducting polymer top-layer) surface. This approach has then been changed to the gate modification in ion sensitive field...electrode (conducting polymer top-layer) surface. This approach has then been changed to the gate modification in ion sensitive field effect transistors, in...the conducting polymer top-layer, which makes the devices very functional and competitive. Secondly, the device development is discussed and finally

Silicon-ion-implanted PMMA with nanostructured ultrathin layers for plastic electronics

NASA Astrophysics Data System (ADS)

Hadjichristov, G. B.; Ivanov, Tz E.; Marinov, Y. G.

2014-12-01

Being of interest for plastic electronics, ion-beam produced nanostructure, namely silicon ion (Si+) implanted polymethyl-methacrylate (PMMA) with ultrathin nanostructured dielectric (NSD) top layer and nanocomposite (NC) buried layer, is examined by electric measurements. In the proposed field-effect organic nanomaterial structure produced within the PMMA network by ion implantation with low energy (50 keV) Si+ at the fluence of 3.2 × 1016 cm-2 the gate NSD is ion-nanotracks-modified low-conductive surface layer, and the channel NC consists of carbon nanoclusters. In the studied ion-modified PMMA field-effect configuration, the gate NSD and the buried NC are formed as planar layers both with a thickness of about 80 nm. The NC channel of nano-clustered amorphous carbon (that is an organic semiconductor) provides a huge increase in the electrical conduction of the material in the subsurface region, but also modulates the electric field distribution in the drift region. The field effect via the gate NSD is analyzed. The most important performance parameters, such as the charge carrier field-effect mobility and amplification of this particular type of PMMA- based transconductance device with NC n-type channel and gate NSD top layer, are determined.

Ferroelectric memory based on molybdenum disulfide and ferroelectric hafnium oxide

NASA Astrophysics Data System (ADS)

Yap, Wui Chung; Jiang, Hao; Xia, Qiangfei; Zhu, Wenjuan

Recently, ferroelectric hafnium oxide (HfO2) was discovered as a new type of ferroelectric material with the advantages of high coercive field, excellent scalability (down to 2.5 nm), and good compatibility with CMOS processing. In this work, we demonstrate, for the first time, 2D ferroelectric memories with molybdenum disulfide (MoS2) as the channel material and aluminum doped HfO2 as the ferroelectric gate dielectric. A 16 nm thick layer of HfO2, doped with 5.26% aluminum, was deposited via atomic layer deposition (ALD), then subjected to rapid thermal annealing (RTA) at 1000 °C, and the polarization-voltage characteristics of the resulting metal-ferroelectric-metal (MFM) capacitors were measured, showing a remnant polarization of 0.6 μC/cm2. Ferroelectric memories with embedded ferroelectric hafnium oxide stacks and monolayer MoS2 were fabricated. The transfer characteristics after program and erase pulses revealed a clear ferroelectric memory window. In addition, endurance (up to 10,000 cycles) of the devices were tested and effects associated with ferroelectric materials, such as the wake-up effect and polarization fatigue, were observed. This research can potentially lead to advances of 2D materials in low-power logic and memory applications.

Metallorganic chemical vapor deposition and atomic layer deposition approaches for the growth of hafnium-based thin films from dialkylamide precursors for advanced CMOS gate stack applications

NASA Astrophysics Data System (ADS)

Consiglio, Steven P.

To continue the rapid progress of the semiconductor industry as described by Moore's Law, the feasibility of new material systems for front end of the line (FEOL) process technologies needs to be investigated, since the currently employed polysilicon/SiO2-based transistor system is reaching its fundamental scaling limits. Revolutionary breakthroughs in complementary-metal-oxide-semiconductor (CMOS) technology were recently announced by Intel Corporation and International Business Machines Corporation (IBM), with both organizations revealing significant progress in the implementation of hafnium-based high-k dielectrics along with metal gates. This announcement was heralded by Gordon Moore as "...the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s." Accordingly, the study described herein focuses on the growth of Hf-based dielectrics and Hf-based metal gates using chemical vapor-based deposition methods, specifically metallorganic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). A family of Hf source complexes that has received much attention recently due to their desirable properties for implementation in wafer scale manufacturing is the Hf dialkylamide precursors. These precursors are room temperature liquids and possess sufficient volatility and desirable decomposition characteristics for both MOCVD and ALD processing. Another benefit of using these sources is the existence of chemically compatible Si dialkylamide sources as co-precursors for use in Hf silicate growth. The first part of this study investigates properties of MOCVD-deposited HfO2 and HfSixOy using dimethylamido Hf and Si precursor sources using a customized MOCVD reactor. The second part of this study involves a study of wet and dry surface pre-treatments for ALD growth of HfO2 using tetrakis(ethylmethylamido)hafnium in a wafer scale manufacturing environment. The third part of this study is an investigation of the properties of conductive HfN grown via plasma-assisted atomic layer deposition (PA-ALD) using tetrakis(ethylmethylamido)hafnium on a modified commercially available wafer processing tool. Key properties of these materials for use as gate stack replacement materials are addressed and future directions for further characterization and novel material investigations are proposed.

Combining a multi deposition multi annealing technique with a scavenging (Ti) to improve the high-k/metal gate stack performance for a gate-last process

NASA Astrophysics Data System (ADS)

ShuXiang, Zhang; Hong, Yang; Bo, Tang; Zhaoyun, Tang; Yefeng, Xu; Jing, Xu; Jiang, Yan

2014-10-01

ALD HfO2 films fabricated by a novel multi deposition multi annealing (MDMA) technique are investigated, we have included samples both with and without a Ti scavenging layer. As compared to the reference gate stack treated by conventional one-time deposition and annealing (D&A), devices receiving MDMA show a significant reduction in leakage current. Meanwhile, EOT growth is effectively controlled by the Ti scavenging layer. This improvement strongly correlates with the cycle number of D&A (while keeping the total annealing time and total dielectrics thickness the same). Transmission electron microscope and energy-dispersive X-ray spectroscopy analysis suggests that oxygen incorporation into both the high-k film and the interfacial layer is likely to be responsible for the improvement of the device. This novel MDMA is promising for the development of gate stack technology in a gate last integration scheme.

Local epitaxial growth of ZrO2 on Ge (100) substrates by atomic layer epitaxy

NASA Astrophysics Data System (ADS)

Kim, Hyoungsub; Chui, Chi On; Saraswat, Krishna C.; McIntyre, Paul C.

2003-09-01

High-k dielectric deposition processes for gate dielectric preparation on Si surfaces usually result in the unavoidable and uncontrolled formation of a thin interfacial oxide layer. Atomic layer deposition of ˜55-Å ZrO2 film on a Ge (100) substrate using ZrCl4 and H2O at 300 °C was found to produce local epitaxial growth [(001) Ge//(001) ZrO2 and [100] Ge//[100] ZrO2] without a distinct interfacial layer, unlike the situation observed when ZrO2 is deposited using the same method on Si. Relatively large lattice mismatch (˜10%) between ZrO2 and Ge produced a high areal density of interfacial misfit dislocations. Large hysteresis (>200 mV) and high frequency dispersion were observed in capacitance-voltage measurements due to the high density of interface states. However, a low leakage current density, comparable to values obtained on Si substrates, was observed with the same capacitance density regardless of the high defect density.

New MBE buffer for micron- and quarter-micron-gateGaAs MESFETs

NASA Technical Reports Server (NTRS)

1988-01-01

A new buffer layer has been developed that eliminates backgating in GaAs MESFETs and substantially reduces short-channel effects in GaAs MESFETs with 0.27-micron-long gates. The new buffer is grown by molecular beam epitaxy (MBE) at a substrate temperature of 200 C using Ga and As sub 4 beam fluxes. The buffer is crystalline, highly resistive, optically inactive, and can be overgrown with high quality GaAs. GaAs MESFETs with a gate length of 0.27 microns that incorporate the new buffer show improved dc and RF properties in comparison with a similar MESFET with a thin undoped GaAs buffer. To demonstrate the backgating performance improvement afforded by the new buffer, MESFETs were fabricated using a number of different buffer layers and structures. A schematic cross section of the MESFET structure used in this study is shown. The measured gate length, gate width, and source-drain spacing of this device are 2,98, and 5.5 microns, respectively. An ohmic contact, isolated from the MESFET by mesa etching, served as the sidegate. The MESFETs were fabricated in MBE n-GaAs layers grown on the new buffer and also in MBE n-GaAs layers grown on buffer layers of undoped GaAs, AlGaAs, and GaAs/AlGaAs superlattices. All the buffer layers were grown by MBE and are 2 microns thick. The active layer is doped to approximately 2 x 10 to the 17th/cu cm with silicon and is 0.3 microns thick.

First-principles simulations of Graphene/Transition-metal-Dichalcogenides/Graphene Field-Effect Transistor

NASA Astrophysics Data System (ADS)

Li, Xiangguo; Wang, Yun-Peng; Zhang, X.-G.; Cheng, Hai-Ping

A prototype field-effect transistor (FET) with fascinating properties can be made by assembling graphene and two-dimensional insulating crystals into three-dimensional stacks with atomic layer precision. Transition metal dichalcogenides (TMDCs) such as WS2, MoS2 are good candidates for the atomically thin barrier between two layers of graphene in the vertical FET due to their sizable bandgaps. We investigate the electronic properties of the Graphene/TMDCs/Graphene sandwich structure using first-principles method. We find that the effective tunnel barrier height of the TMDC layers in contact with the graphene electrodes has a layer dependence and can be modulated by a gate voltage. Consequently a very high ON/OFF ratio can be achieved with appropriate number of TMDC layers and a suitable range of the gate voltage. The spin-orbit coupling in TMDC layers is also layer dependent but unaffected by the gate voltage. These properties can be important in future nanoelectronic device designs. DOE/BES-DE-FG02-02ER45995; NERSC.

Electron Doping of Ultrathin Black Phosphorus with Cu Adatoms.

PubMed

Koenig, Steven P; Doganov, Rostislav A; Seixas, Leandro; Carvalho, Alexandra; Tan, Jun You; Watanabe, Kenji; Taniguchi, Takashi; Yakovlev, Nikolai; Castro Neto, Antonio H; Özyilmaz, Barbaros

2016-04-13

Few-layer black phosphorus is a monatomic two-dimensional crystal with a direct band gap that has high carrier mobility for both holes and electrons. Similarly to other layered atomic crystals, like graphene or layered transition metal dichalcogenides, the transport behavior of few-layer black phosphorus is sensitive to surface impurities, adsorbates, and adatoms. Here we study the effect of Cu adatoms onto few-layer black phosphorus by characterizing few-layer black phosphorus field effect devices and by performing first-principles calculations. We find that the addition of Cu adatoms can be used to controllably n-dope few layer black phosphorus, thereby lowering the threshold voltage for n-type conduction without degrading the transport properties. We demonstrate a scalable 2D material-based complementary inverter which utilizes a boron nitride gate dielectric, a graphite gate, and a single bP crystal for both the p- and n-channels. The inverter operates at matched input and output voltages, exhibits a gain of 46, and does not require different contact metals or local electrostatic gating.

Enzyme-polyelectrolyte multilayer assemblies on reduced graphene oxide field-effect transistors for biosensing applications.

PubMed

Piccinini, Esteban; Bliem, Christina; Reiner-Rozman, Ciril; Battaglini, Fernando; Azzaroni, Omar; Knoll, Wolfgang

2017-06-15

We present the construction of layer-by-layer (LbL) assemblies of polyethylenimine and urease onto reduced-graphene-oxide based field-effect transistors (rGO FETs) for the detection of urea. This versatile biosensor platform simultaneously exploits the pH dependency of liquid-gated graphene-based transistors and the change in the local pH produced by the catalyzed hydrolysis of urea. The use of an interdigitated microchannel resulted in transistors displaying low noise, high pH sensitivity (20.3µA/pH) and transconductance values up to 800 µS. The modification of rGO FETs with a weak polyelectrolyte improved the pH response because of its transducing properties by electrostatic gating effects. In the presence of urea, the urease-modified rGO FETs showed a shift in the Dirac point due to the change in the local pH close to the graphene surface. Markedly, these devices operated at very low voltages (less than 500mV) and were able to monitor urea in the range of 1-1000µm, with a limit of detection (LOD) down to 1µm, fast response and good long-term stability. The urea-response of the transistors was enhanced by increasing the number of bilayers due to the increment of the enzyme surface coverage onto the channel. Moreover, quantification of the heavy metal Cu 2+ (with a LOD down to 10nM) was performed in aqueous solution by taking advantage of the urease specific inhibition. Copyright © 2016 The Authors. Published by Elsevier B.V. All rights reserved.

Effect of atomic layer deposition temperature on current conduction in Al{sub 2}O{sub 3} films formed using H{sub 2}O oxidant

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hiraiwa, Atsushi, E-mail: hiraiwa@aoni.waseda.jp, E-mail: qs4a-hriw@asahi-net.or.jp; Matsumura, Daisuke; Kawarada, Hiroshi, E-mail: kawarada@waseda.jp

To develop high-performance, high-reliability gate insulation and surface passivation technologies for wide-bandgap semiconductor devices, the effect of atomic layer deposition (ALD) temperature on current conduction in Al{sub 2}O{sub 3} films is investigated based on the recently proposed space-charge-controlled field emission model. Leakage current measurement shows that Al{sub 2}O{sub 3} metal-insulator-semiconductor capacitors formed on the Si substrates underperform thermally grown SiO{sub 2} capacitors at the same average field. However, using equivalent oxide field as a more practical measure, the Al{sub 2}O{sub 3} capacitors are found to outperform the SiO{sub 2} capacitors in the cases where the capacitors are negatively biased andmore » the gate material is adequately selected to reduce virtual dipoles at the gate/Al{sub 2}O{sub 3} interface. The Al{sub 2}O{sub 3} electron affinity increases with the increasing ALD temperature, but the gate-side virtual dipoles are not affected. Therefore, the leakage current of negatively biased Al{sub 2}O{sub 3} capacitors is approximately independent of the ALD temperature because of the compensation of the opposite effects of increased electron affinity and permittivity in Al{sub 2}O{sub 3}. By contrast, the substrate-side sheet of charge increases with increasing ALD temperature above 210 °C and hence enhances the current of positively biased Al{sub 2}O{sub 3} capacitors more significantly at high temperatures. Additionally, an anomalous oscillatory shift of the current-voltage characteristics with ALD temperature was observed in positively biased capacitors formed by low-temperature (≤210 °C) ALD. This shift is caused by dipoles at the Al{sub 2}O{sub 3}/underlying SiO{sub 2} interface. Although they have a minimal positive-bias leakage current, the low-temperature-grown Al{sub 2}O{sub 3} films cause the so-called blisters problem when heated above 400 °C. Therefore, because of the absence of blistering, a 450 °C ALD process is presently the most promising technology for growing high-reliability Al{sub 2}O{sub 3} films.« less

Comparative analysis of the effects of tantalum doping and annealing on atomic layer deposited (Ta2O5)x(Al2O3)1-x as potential gate dielectrics for GaN/AlxGa1-xN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Partida-Manzanera, T.; Roberts, J. W.; Bhat, T. N.; Zhang, Z.; Tan, H. R.; Dolmanan, S. B.; Sedghi, N.; Tripathy, S.; Potter, R. J.

2016-01-01

This paper describes a method to optimally combine wide band gap Al2O3 with high dielectric constant (high-κ) Ta2O5 for gate dielectric applications. (Ta2O5)x(Al2O3)1-x thin films deposited by thermal atomic layer deposition (ALD) on GaN-capped AlxGa1-xN/GaN high electron mobility transistor (HEMT) structures have been studied as a function of the Ta2O5 molar fraction. X-ray photoelectron spectroscopy shows that the bandgap of the oxide films linearly decreases from 6.5 eV for pure Al2O3 to 4.6 eV for pure Ta2O5. The dielectric constant calculated from capacitance-voltage measurements also increases linearly from 7.8 for Al2O3 up to 25.6 for Ta2O5. The effect of post-deposition annealing in N2 at 600 °C on the interfacial properties of undoped Al2O3 and Ta-doped (Ta2O5)0.12(Al2O3)0.88 films grown on GaN-HEMTs has been investigated. These conditions are analogous to the conditions used for source/drain contact formation in gate-first HEMT technology. A reduction of the Ga-O to Ga-N bond ratios at the oxide/HEMT interfaces is observed after annealing, which is attributed to a reduction of interstitial oxygen-related defects. As a result, the conduction band offsets (CBOs) of the Al2O3/GaN-HEMT and (Ta2O5)0.16(Al2O3)0.84/GaN-HEMT samples increased by ˜1.1 eV to 2.8 eV and 2.6 eV, respectively, which is advantageous for n-type HEMTs. The results demonstrate that ALD of Ta-doped Al2O3 can be used to control the properties of the gate dielectric, allowing the κ-value to be increased, while still maintaining a sufficient CBO to the GaN-HEMT structure for low leakage currents.

A low-frequency noise model with carrier generation-recombination process for pentacene organic thin-film transistor

NASA Astrophysics Data System (ADS)

Han, C. Y.; Qian, L. X.; Leung, C. H.; Che, C. M.; Lai, P. T.

2013-07-01

By including the generation-recombination process of charge carriers in conduction channel, a model for low-frequency noise in pentacene organic thin-film transistors (OTFTs) is proposed. In this model, the slope and magnitude of power spectral density for low-frequency noise are related to the traps in the gate dielectric and accumulation layer of the OTFT for the first time. The model can well fit the measured low-frequency noise data of pentacene OTFTs with HfO2 or HfLaO gate dielectric, which validates this model, thus providing an estimate on the densities of traps in the gate dielectric and accumulation layer. It is revealed that the traps in the accumulation layer are much more than those in the gate dielectric, and so dominate the low-frequency noise of pentacene OTFTs.

In-plane optical anisotropy of layered gallium telluride

DOE PAGES

Huang, Shengxi; Tatsumi, Yuki; Ling, Xi; ...

2016-08-16

Layered gallium telluride (GaTe) has attracted much attention recently, due to its extremely high photoresponsivity, short response time, and promising thermoelectric performance. Different from most commonly studied two-dimensional (2D) materials, GaTe has in-plane anisotropy and a low symmetry with the C 2h 3 space group. Investigating the in-plane optical anisotropy, including the electron–photon and electron–phonon interactions of GaTe is essential in realizing its applications in optoelectronics and thermoelectrics. In this work, the anisotropic light-matter interactions in the low-symmetry material GaTe are studied using anisotropic optical extinction and Raman spectroscopies as probes. Our polarized optical extinction spectroscopy reveals the weak anisotropymore » in optical extinction spectra for visible light of multilayer GaTe. Polarized Raman spectroscopy proves to be sensitive to the crystalline orientation of GaTe, and shows the intricate dependences of Raman anisotropy on flake thickness, photon and phonon energies. Such intricate dependences can be explained by theoretical analyses employing first-principles calculations and group theory. Furthermore, these studies are a crucial step toward the applications of GaTe especially in optoelectronics and thermoelectrics, and provide a general methodology for the study of the anisotropy of light-matter interactions in 2D layered materials with in-plane anisotropy.« less

Effect of Al gate on the electrical behaviour of Al-doped Ta2O5 stacks

NASA Astrophysics Data System (ADS)

Skeparovski, A.; Novkovski, N.; Atanassova, E.; Paskaleva, A.; Lazarov, V. K.

2011-06-01

The electrical behaviour of Al-doped Ta2O5 films on nitrided silicon and implemented in Al-gated MIS capacitors has been studied. The dopant was introduced into the Ta2O5 through its surface by deposing a thin Al layer on the top of Ta2O5 followed by an annealing process. The HRTEM images reveal that the initial double-layer structure of the stacks composed of doped Ta2O5 and interfacial SiON layer undergoes changes during the formation of the Al gate and transforms into a three-layer structure with an additional layer between the Al electrode and the doped Ta2O5. This layer, being a result of reaction between the Al gate and the Al-doped Ta2O5, affects the overall electrical properties of the stacks. Strong charge trapping/detrapping processes have been established in the vicinity of the doped Ta2O5/SiON interface resulting in a large C-V hysteresis effect. The charge trapping also influences the current conduction in the layers keeping the current density level rather low even at high electric fields (J < 10-6 A cm-2 at 7 MV cm-1). By employing a three-layer model of the stack, the permittivity of both, the Al-doped Ta2O5 and the additional layer, has been estimated and the corresponding conduction mechanisms identified.

Temperature-dependent degradation mechanisms of threshold voltage in La2O3-gated n-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Ming-Tsong; Hsu, De-Cheng; Juan, Pi-Chun; Wang, Y. L.; Lee, Joseph Ya-min

2010-09-01

Metal-oxide-semiconductor capacitors and n-channel metal-oxide-semiconductor field-effect transistors with La2O3 gate dielectric were fabricated. The positive bias temperature instability was studied. The degradation of threshold voltage (ΔVT) showed an exponential dependence on the stress time in the temperature range from 25 to 75 °C. The degradation of subthreshold slope (ΔS) and gate leakage (IG) with stress voltage was also measured. The degradation of VT is attributed to the oxide trap charges Qot. The extracted activation energy of 0.2 eV is related to a degradation dominated by the release of atomic hydrogen in La2O3 thin films.

Graphene as a platform for novel nanoelectronic devices

NASA Astrophysics Data System (ADS)

Standley, Brian

Graphene's superlative electrical and mechanical properties, combined with its compatibility with existing planar silicon-based technology, make it an attractive platform for novel nanoelectronic devices. The development of two such devices is reported--a nonvolatile memory element exploiting the nanoscale graphene edge and a field-effect transistor using graphene for both the conducting channel and, in oxidized form, the gate dielectric. These experiments were enabled by custom software written to fully utilize both instrument-based and computer-based data acquisition hardware and provide a simple measurement automation system. Graphene break junctions were studied and found to exhibit switching behavior in response to an electric field. This switching allows the devices to act as nonvolatile memory elements which have demonstrated thousands of writing cycles and long retention times. A model for device operation is proposed based on the formation and breaking of carbon-atom chains that bridge the junctions. Information storage was demonstrated using the concept of rank coding, in which information is stored in the relative conductance of multiple graphene switches in a memory cell. The high mobility and two dimensional nature of graphene make it an attractive material for field-effect transistors. Another ultrathin layered materialmd graphene's insulating analogue, graphite oxidemd was studied as an alternative to bulk gate dielectric materials such as Al2O3 or HfO 2. Transistors were fabricated comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. Electron transport measurements reveal minimal leakage through the graphite oxide at room temperature. Its breakdown electric field was found to be comparable to SiO2, typically ˜1-3 x 108 V/m, while its dielectric constant is slightly higher, kappa ≈ 4.3. As nanoelectronics experiments and their associated instrumentation continue to grow in complexity the need for powerful data acquisition software has only increased. This role has traditionally been filled by semiconductor parameter analyzers or desktop computers running LabVIEW. Mezurit 2 represents a hybrid approach, providing basic virtual instruments which can be controlled in concert through a comprehensive scripting interface. Each virtual instrument's model of operation is described and an architectural overview is provided.

Improved memory characteristics by NH3-nitrided GdO as charge storage layer for nonvolatile memory applications

NASA Astrophysics Data System (ADS)

Liu, L.; Xu, J. P.; Ji, F.; Chen, J. X.; Lai, P. T.

2012-07-01

Charge-trapping memory capacitor with nitrided gadolinium oxide (GdO) as charge storage layer (CSL) is fabricated, and the influence of post-deposition annealing in NH3 on its memory characteristics is investigated. Transmission electron microscopy, x-ray photoelectron spectroscopy, and x-ray diffraction are used to analyze the cross-section and interface quality, composition, and crystallinity of the stack gate dielectric, respectively. It is found that nitrogen incorporation can improve the memory window and achieve a good trade-off among the memory properties due to NH3-annealing-induced reasonable distribution profile of a large quantity of deep-level bulk traps created in the nitrided GdO film and reduction of shallow traps near the CSL/SiO2 interface.

Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

NASA Astrophysics Data System (ADS)

Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

2018-01-01

Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

Multiple and configurable optical logic systems based on layered double hydroxides and chromophore assemblies.

PubMed

Shi, Wenying; Fu, Yi; Li, Zhixiong; Wei, Min

2015-01-14

Multiple and configurable fluorescence logic gates were fabricated via self-assembly of layered double hydroxides and various chromophores. These logic gates were operated by observation of different emissions with the same excitation wavelength, which achieve YES, NOT, AND, INH and INHIBIT logic operations, respectively.

MOCVD of HfO2 and ZrO2 high-k gate dielectrics for InAlN/AlN/GaN MOS-HEMTs

NASA Astrophysics Data System (ADS)

Abermann, S.; Pozzovivo, G.; Kuzmik, J.; Strasser, G.; Pogany, D.; Carlin, J.-F.; Grandjean, N.; Bertagnolli, E.

2007-12-01

We apply metal organic chemical vapour deposition (MOCVD) of HfO2 and of ZrO2 from β-diketonate precursors to grow high-k gate dielectrics for InAlN/AlN/GaN metal oxide semiconductor (MOS)-high electron mobility transistors (HEMTs). High-k oxides of about 12 nm-14 nm are deposited for the MOS-HEMTs incorporating Ni/Au gates, whereas as a reference, Ni-contact-based 'conventional' Schottky-barrier (SB)-HEMTs are processed. The processed dielectrics decrease the gate current leakage of the HEMTs by about four orders of magnitude if compared with the SB-gated HEMTs and show superior device characteristics in terms of IDS and breakdown.

Artificial semiconductor/insulator superlattice channel structure for high-performance oxide thin-film transistors

PubMed Central

Ahn, Cheol Hyoun; Senthil, Karuppanan; Cho, Hyung Koun; Lee, Sang Yeol

2013-01-01

High-performance thin-film transistors (TFTs) are the fundamental building blocks in realizing the potential applications of the next-generation displays. Atomically controlled superlattice structures are expected to induce advanced electric and optical performance due to two-dimensional electron gas system, resulting in high-electron mobility transistors. Here, we have utilized a semiconductor/insulator superlattice channel structure comprising of ZnO/Al2O3 layers to realize high-performance TFTs. The TFT with ZnO (5 nm)/Al2O3 (3.6 nm) superlattice channel structure exhibited high field effect mobility of 27.8 cm2/Vs, and threshold voltage shift of only < 0.5 V under positive/negative gate bias stress test during 2 hours. These properties showed extremely improved TFT performance, compared to ZnO TFTs. The enhanced field effect mobility and stability obtained for the superlattice TFT devices were explained on the basis of layer-by-layer growth mode, improved crystalline nature of the channel layers, and passivation effect of Al2O3 layers. PMID:24061388

Photolithographically Patterned TiO2 Films for Electrolyte-Gated Transistors.

PubMed

Valitova, Irina; Kumar, Prajwal; Meng, Xiang; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2016-06-15

Metal oxides constitute a class of materials whose properties cover the entire range from insulators to semiconductors to metals. Most metal oxides are abundant and accessible at moderate cost. Metal oxides are widely investigated as channel materials in transistors, including electrolyte-gated transistors, where the charge carrier density can be modulated by orders of magnitude upon application of relatively low electrical bias (2 V). Electrolyte gating offers the opportunity to envisage new applications in flexible and printed electronics as well as to improve our current understanding of fundamental processes in electronic materials, e.g. insulator/metal transitions. In this work, we employ photolithographically patterned TiO2 films as channels for electrolyte-gated transistors. TiO2 stands out for its biocompatibility and wide use in sensing, electrochromics, photovoltaics and photocatalysis. We fabricated TiO2 electrolyte-gated transistors using an original unconventional parylene-based patterning technique. By using a combination of electrochemical and charge carrier transport measurements we demonstrated that patterning improves the performance of electrolyte-gated TiO2 transistors with respect to their unpatterned counterparts. Patterned electrolyte-gated (EG) TiO2 transistors show threshold voltages of about 0.9 V, ON/OFF ratios as high as 1 × 10(5), and electron mobility above 1 cm(2)/(V s).

Interfacial phenomena in high-kappa dielectrics

NASA Astrophysics Data System (ADS)

Mathew, Anoop

The introduction of novel high-kappa dielectric materials to replace the traditional SiO2 insulating layer in CMOS transistors is a watershed event in the history of transistor development. Further, replacement of the traditional highly-doped polycrystalline silicon gate electrode with a new set of materials for metal gates complicates the transition and introduces further integration challenges. A whole variety of new material surfaces and interfaces are thus introduced that merit close investigation to determine parameters for optimal device performance. Nitrogen is a key component that improves the performance of a variety of materials for the next generation of these CMOS transistors. Nitrogen is introduced into new gate dielectric materials such as hafnium silicates as well as in potential metal gate materials such as hafnium nitride. A photoemission study of the binding energies of the various atoms in these systems using photoemission reveals the nature of the atomic bonding. The current study compares hafnium silicates of various compositions which were thermally nitrided at different temperatures in ammonia, hafnium nitrides, and thin HfO2 films using photoelectron spectroscopy. A recurring theme that is explored is the competition between oxygen and nitrogen atoms in bonding with hafnium and other atoms. The N 1s photoemission peak is seen to have contributions from its bonding with hafnium, oxygen, and silicon atoms. The Hf 4f and O 1s spectra similarly exhibit signatures of their bonding environment with their neighboring atoms. Angle resolved photoemission and in-situ annealing/argon sputtering experiments are used to elucidate the nature of the bonding and its evolution with processing. A nondestructive profilitng of nitrogen distribution as a function of composition in nitrided hafnium silicates is also constructed using angle resolved photoemission as a function of the take-off angle. These results are corroborated with depth reconstruction obtained using medium energy ion scattering (MEIS). A comparison of samples nitrided at progressively increasing temperatures in an ammonia environment shows substitution of oxygen with nitrogen atoms and increasing penetration of nitrogen into the gate stack. Trends in the binding energy of the the as-prepared hafnium silicates suggest that they are non-phase separated, and the binding energy of the hafnium and silicon track the relative composition. Upon being subject to rapid thermal annealing, the samples are observed to show behavior consistent with phase separation. There is also the evidence of charges at the oxide/Si interface that modify the expected behavior of the shifts in binding energy. In another set of experiments, a one-cycle atomic layer deposition (ALD) growth reaction on the water terminated Si(100) -- (2x1) surface is shown to lead to successful nucleation, high metal oxide coverage, and an abrupt metal-oxide/silicon interface as confirmed by photoemission, reflection high energy electron diffraction (RHEED), and Rutherford back scattering (RBS) measurements. Photoemission results confirm the coordination states of the hafnium and oxygen atoms. A Hf 4f core level shift is observed and assigned to the presence of the Si-O-Hf bonding environment with the more electronegative Si atom inducing the binding energy shift. This Hf 4f shift is smaller than that reported previously for silicates because of the difference of the semiconductor bonding environment. The subspecies *(O)2HfCl2 and *OHfCl3 are seen to be the predominant intermediate species in these reactions and photoemission results provide corroborative evidence for their presence. Experiments indicate that the hydroxyl sites bound to Si(100) are active for adsorption. The abrupt interface could be useful for aggressive Effective Oxide Thickness (EOT) scaling.

Low temperature mobility in hafnium-oxide gated germanium p-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Beer, Chris; Whall, Terry; Parker, Evan; Leadley, David; De Jaeger, Brice; Nicholas, Gareth; Zimmerman, Paul; Meuris, Marc; Szostak, Slawomir; Gluszko, Grzegorz; Lukasiak, Lidia

2007-12-01

Effective mobility measurements have been made at 4.2K on high performance high-k gated germanium p-type metal-oxide-semiconductor field effect transistors with a range of Ge/gate dielectric interface state densities. The mobility is successfully modelled by assuming surface roughness and interface charge scattering at the SiO2 interlayer/Ge interface. The deduced interface charge density is approximately equal to the values obtained from the threshold voltage and subthreshold slope measurements on each device. A hydrogen anneal reduces both the interface state density and the surface root mean square roughness by 20%.

Scan direction induced charging dynamics and the application for detection of gate to S/D shorts in logic devices

NASA Astrophysics Data System (ADS)

Lei, Ming; Tian, Qing; Wu, Kevin; Zhao, Yan

2016-03-01

Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

Low-voltage electric-double-layer paper transistors gated by microporous SiO2 processed at room temperature

NASA Astrophysics Data System (ADS)

Sun, Jia; Wan, Qing; Lu, Aixia; Jiang, Jie

2009-11-01

Battery drivable low-voltage SnO2-based paper thin-film transistors with a near-zero threshold voltage (Vth=0.06 V) gated by microporous SiO2 dielectric with electric-double-layer (EDL) effect are fabricated at room temperature. The operating voltage is found to be as low as 1.5 V due to the huge gate specific capacitance (1.34 μF/cm2 at 40 Hz) related to EDL formation. The subthreshold gate voltage swing and current on/off ratio is found to be 82 mV/decade and 2.0×105, respectively. The electron field-effect mobility is estimated to be 47.3 cm2/V s based on the measured gate specific capacitance at 40 Hz.

High performance top-gated ferroelectric field effect transistors based on two-dimensional ZnO nanosheets

NASA Astrophysics Data System (ADS)

Tian, Hongzheng; Wang, Xudong; Zhu, Yuankun; Liao, Lei; Wang, Xianying; Wang, Jianlu; Hu, Weida

2017-01-01

High quality ultrathin two-dimensional zinc oxide (ZnO) nanosheets (NSs) are synthesized, and the ZnO NS ferroelectric field effect transistors (FeFETs) are demonstrated based on the P(VDF-TrFE) polymer film used as the top gate insulating layer. The ZnO NSs exhibit a maximum field effect mobility of 588.9 cm2/Vs and a large transconductance of 2.5 μS due to their high crystalline quality and ultrathin two-dimensional structure. The polarization property of the P(VDF-TrFE) film is studied, and a remnant polarization of >100 μC/cm2 is achieved with a P(VDF-TrFE) thickness of 300 nm. Because of the ultrahigh remnant polarization field generated in the P(VDF-TrFE) film, the FeFETs show a large memory window of 16.9 V and a high source-drain on/off current ratio of more than 107 at zero gate voltage and a source-drain bias of 0.1 V. Furthermore, a retention time of >3000 s of the polarization state is obtained, inspiring a promising candidate for applications in data storage with non-volatile features.

High fluence swift heavy ion structure modification of the SiO2/Si interface and gate insulator in 65 nm MOSFETs

NASA Astrophysics Data System (ADS)

Ma, Yao; Gao, Bo; Gong, Min; Willis, Maureen; Yang, Zhimei; Guan, Mingyue; Li, Yun

2017-04-01

In this work, a study of the structure modification, induced by high fluence swift heavy ion radiation, of the SiO2/Si structures and gate oxide interface in commercial 65 nm MOSFETs is performed. A key and novel point in this study is the specific use of the transmission electron microscopy (TEM) technique instead of the conventional atomic force microscope (AFM) or scanning electron microscope (SEM) techniques which are typically performed following the chemical etching of the sample to observe the changes in the structure. Using this method we show that after radiation, the appearance of a clearly visible thin layer between the SiO2 and Si is observed presenting as a variation in the TEM intensity at the interface of the two materials. Through measuring the EDX line scans we reveal that the Si:O ratio changed and that this change can be attributed to the migration of the Si towards interface after the Si-O bond is destroyed by the swift heavy ions. For the 65 nm MOSFET sample, the silicon substrate, the SiON insulator and the poly-silicon gate interfaces become blurred under the same irradiation conditions.

Control of Ambipolar Transport in SnO Thin-Film Transistors by Back-Channel Surface Passivation for High Performance Complementary-like Inverters.

PubMed

Luo, Hao; Liang, Lingyan; Cao, Hongtao; Dai, Mingzhi; Lu, Yicheng; Wang, Mei

2015-08-12

For ultrathin semiconductor channels, the surface and interface nature are vital and often dominate the bulk properties to govern the field-effect behaviors. High-performance thin-film transistors (TFTs) rely on the well-defined interface between the channel and gate dielectric, featuring negligible charge trap states and high-speed carrier transport with minimum carrier scattering characters. The passivation process on the back-channel surface of the bottom-gate TFTs is indispensable for suppressing the surface states and blocking the interactions between the semiconductor channel and the surrounding atmosphere. We report a dielectric layer for passivation of the back-channel surface of 20 nm thick tin monoxide (SnO) TFTs to achieve ambipolar operation and complementary metal oxide semiconductor (CMOS) like logic devices. This chemical passivation reduces the subgap states of the ultrathin channel, which offers an opportunity to facilitate the Fermi level shifting upward upon changing the polarity of the gate voltage. With the advent of n-type inversion along with the pristine p-type conduction, it is now possible to realize ambipolar operation using only one channel layer. The CMOS-like logic inverters based on ambipolar SnO TFTs were also demonstrated. Large inverter voltage gains (>100) in combination with wide noise margins are achieved due to high and balanced electron and hole mobilities. The passivation also improves the long-term stability of the devices. The ability to simultaneously achieve field-effect inversion, electrical stability, and logic function in those devices can open up possibilities for the conventional back-channel surface passivation in the CMOS-like electronics.

Dual-gated MoS2/WSe2 van der Waals tunnel diodes and transistors.

PubMed

Roy, Tania; Tosun, Mahmut; Cao, Xi; Fang, Hui; Lien, Der-Hsien; Zhao, Peida; Chen, Yu-Ze; Chueh, Yu-Lun; Guo, Jing; Javey, Ali

2015-02-24

Two-dimensional layered semiconductors present a promising material platform for band-to-band-tunneling devices given their homogeneous band edge steepness due to their atomically flat thickness. Here, we experimentally demonstrate interlayer band-to-band tunneling in vertical MoS2/WSe2 van der Waals (vdW) heterostructures using a dual-gate device architecture. The electric potential and carrier concentration of MoS2 and WSe2 layers are independently controlled by the two symmetric gates. The same device can be gate modulated to behave as either an Esaki diode with negative differential resistance, a backward diode with large reverse bias tunneling current, or a forward rectifying diode with low reverse bias current. Notably, a high gate coupling efficiency of ∼80% is obtained for tuning the interlayer band alignments, arising from weak electrostatic screening by the atomically thin layers. This work presents an advance in the fundamental understanding of the interlayer coupling and electron tunneling in semiconductor vdW heterostructures with important implications toward the design of atomically thin tunnel transistors.

Evolution of zirconyl-stearate Langmuir monolayers and the synthesized ZrO2 thin films with pH

NASA Astrophysics Data System (ADS)

Choudhary, Raveena; Sharma, Rajni; Brar, Loveleen K.

2018-04-01

ZrO2 thin films have a wide range of applications ranging from photonics, antireflection coatings, and resistive oxygen gas sensors, as a gate dielectric and in high temperature fuel cells. We have used the deposition of zirconyl stearate monolayers followed by their oxidation as a method for the synthesis of zirconium oxide thin films. The zirconyl stearate films have been studied and deposited for first time to the best of our knowledge. The Langmuir monolayers are studied using pressure-Area (π-A) isotherms and oscillatory barrier method. The morphology of the films for limited number of layers was studied with FE-SEM to determine the effect of pH on the final ZrO2 film. The 200 layer deposition films show pure monoclinic phase. The films have a band gap ˜6.0eV with a strong PL emission peak is at 490 nm and a weak peak is at 423 nm. So the films formed by this deposition method are suitable for luminescent applications

Positive Bias Instability of Bottom-Gate Zinc Oxide Thin-Film Transistors with a SiOx/SiNx-Stacked Gate Insulator

NASA Astrophysics Data System (ADS)

Furuta, Mamoru; Kamada, Yudai; Hiramatsu, Takahiro; Li, Chaoyang; Kimura, Mutsumi; Fujita, Shizuo; Hirao, Takashi

2011-03-01

The positive bias instabilities of the zinc oxide thin-film transistors (ZnO TFTs) with a SiOx/SiNx-stacked gate insulator have been investigated. The film quality of a gate insulator of SiOx, which forms an interface with the ZnO channel, was varied by changing the gas mixture ratio of SiH4/N2O/N2 during plasma-enhanced chemical vapor deposition. The positive bias stress endurance of ZnO TFT strongly depended on the deposition condition of the SiOx gate insulator. From the relaxations of the transfer curve shift after imposition of positive bias stress, transfer curves could not be recovered completely without any thermal annealing. A charge trapping in a gate insulator rather than that in bulk ZnO and its interface with a gate insulator is a dominant instability mechanism of ZnO TFTs under positive bias stress.

Influence of gate recess on the electronic characteristics of β-Ga2O3 MOSFETs

NASA Astrophysics Data System (ADS)

Lv, Yuanjie; Mo, Jianghui; Song, Xubo; He, Zezhao; Wang, Yuangang; Tan, Xin; Zhou, Xingye; Gu, Guodong; Guo, Hongyu; Feng, Zhihong

2018-05-01

Gallium oxide (Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with gate recess depths of 110 nm and 220 nm, respectively. The gate recess was formed by dry plasma etching with Cr metal as the mask. The fabricated devices with a 25-nm HfO2 gate dielectric both showed a low off-state drain current of about 1.8 × 10-10 A/mm. The effects of recess depth on the electronic characteristics of Ga2O3 MOSFETs were investigated. Upon increasing the recess depth from 110 nm to 220 nm, the saturated drain current decreased from 20.7 mA/mm to 2.6 mA/mm, while the threshold voltage moved increased to +3 V. Moreover, the breakdown voltage increased from 122 V to 190 V. This is mainly because the inverted-trapezoidal gate played the role of a gate-field plate, which suppressed the peak electric field close to the gate.

Bias stress instability of double-gate a-IGZO TFTs on polyimide substrate

NASA Astrophysics Data System (ADS)

Cho, Won-Ju; Ahn, Min-Ju

2017-09-01

In this study, flexible double-gate thin-film transistor (TFT)-based amorphous indium-galliumzinc- oxide (a-IGZO) was fabricated on a polyimide substrate. Double-gate operation with connected front and back gates was compared with a single-gate operation. As a result, the double-gate a- IGZO TFT exhibited enhanced electrical characteristics as well as improved long-term reliability. Under positive- and negative-bias temperature stress, the threshold voltage shift of the double-gate operation was much smaller than that of the single-gate operation.

Electron transporting water-gated thin film transistors

NASA Astrophysics Data System (ADS)

Al Naim, Abdullah; Grell, Martin

2012-10-01

We demonstrate an electron-transporting water-gated thin film transistor, using thermally converted precursor-route zinc-oxide (ZnO) intrinsic semiconductors with hexamethyldisilazene (HMDS) hydrophobic surface modification. Water gated HMDS-ZnO thin film transistors (TFT) display low threshold and high electron mobility. ZnO films constitute an attractive alternative to organic semiconductors for TFT transducers in sensor applications for waterborne analytes. Despite the use of an electrolyte as gate medium, the gate geometry (shape of gate electrode and distance between gate electrode and TFT channel) is relevant for optimum performance of water-gated TFTs.

Highly efficient gate-tunable photocurrent generation in vertical heterostructures of layered materials

PubMed Central

Yu, Woo Jong; Liu, Yuan; Zhou, Hailong; Yin, Anxiang; Li, Zheng; Huang, Yu

2014-01-01

Layered materials of graphene and MoS2, for example, have recently emerged as an exciting material system for future electronics and optoelectronics. Vertical integration of layered materials can enable the design of novel electronic and photonic devices. Here, we report highly efficient photocurrent generation from vertical heterostructures of layered materials. We show that vertically stacked graphene–MoS2–graphene and graphene–MoS2–metal junctions can be created with a broad junction area for efficient photon harvesting. The weak electrostatic screening effect of graphene allows the integration of single or dual gates under and/or above the vertical heterostructure to tune the band slope and photocurrent generation. We demonstrate that the amplitude and polarity of the photocurrent in the gated vertical heterostructures can be readily modulated by the electric field of an external gate to achieve a maximum external quantum efficiency of 55% and internal quantum efficiency up to 85%. Our study establishes a method to control photocarrier generation, separation and transport processes using an external electric field. PMID:24162001

High Performance 50 nm InAlAs/In0.75GaAs Metamorphic High Electron Mobility Transistors with Si3N4 Passivation on Thin InGaAs Layer

NASA Astrophysics Data System (ADS)

Yeon, Seongjin; Seo, Kwangseok

2008-04-01

We fabricated 50 nm InAlAs/InGaAs metamorphic high electron mobility transistors (HEMTs) with a very thin barrier. Through the reduction of the gate-channel distance (dGC) in the epitaxial structure, a channel aspect ratio (ARC) of over three was achieved when Lg was 50 nm. We inserted a thin InGaAs layer as a protective layer, and tested various gate structures to reduce surface problems induced by barrier shrinkage and to optimize the device characteristics. Through the optimization of the gate structure with the thin InGaAs layer, the fabricated 50 nm metamorphic HEMT exhibited high DC and RF characteristics, Gm of 1.5 S/mm, and fT of 490 GHz.

Step buffer layer of Al0.25Ga0.75N/Al0.08Ga0.92N on P-InAlN gate normally-off high electron mobility transistors

NASA Astrophysics Data System (ADS)

Shrestha, Niraj M.; Li, Yiming; Chang, E. Y.

2016-07-01

Normally-off AlGaN/GaN high electron mobility transistors (HEMTs) are indispensable devices for power electronics as they can greatly simplify circuit designs in a cost-effective way. In this work, the electrical characteristics of p-type InAlN gate normally-off AlGaN/GaN HEMTs with a step buffer layer of Al0.25Ga0.75N/Al0.1Ga0.9N is studied numerically. Our device simulation shows that a p-InAlN gate with a step buffer layer allows the transistor to possess normally-off behavior with high drain current and high breakdown voltage simultaneously. The gate modulation by the p-InAlN gate and the induced holes appearing beneath the gate at the GaN/Al0.25Ga0.75N interface is because a hole appearing in the p-InAlN layer can effectively vary the threshold voltage positively. The estimated threshold voltage of the normally-off HEMTs explored is 2.5 V at a drain bias of 25 V, which is 220% higher than the conventional p-AlGaN normally-off AlGaN/GaN gate injection transistor (GIT). Concurrently, the maximum current density of the explored HEMT at a drain bias of 10 V slightly decreases by about 7% (from 240 to 223 mA mm-1). At a drain bias of 15 V, the current density reached 263 mA mm-1. The explored structure is promising owing to tunable positive threshold voltage and the maintenance of similar current density; notably, its breakdown voltage significantly increases by 36% (from 800 V, GIT, to 1086 V). The engineering findings of this study indicate that novel p-InAlN for both the gate and the step buffer layer can feature a high threshold voltage, large current density and high operating voltage for advanced AlGaN/GaN HEMT devices.

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

NASA Astrophysics Data System (ADS)

Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

2013-06-01

In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

Effects of HfO2 encapsulation on electrical performances of few-layered MoS2 transistor with ALD HfO2 as back-gate dielectric.

PubMed

Xu, Jingping; Wen, Ming; Zhao, Xinyuan; Liu, Lu; Song, Xingjuan; Lai, Pui-To; Tang, Wing-Man

2018-08-24

The carrier mobility of MoS 2 transistors can be greatly improved by the screening role of high-k gate dielectric. In this work, atomic-layer deposited (ALD) HfO 2 annealed in NH 3 is used to replace SiO 2 as the gate dielectric to fabricate back-gated few-layered MoS 2 transistors, and good electrical properties are achieved with field-effect mobility (μ) of 19.1 cm 2 V -1 s -1 , subthreshold swing (SS) of 123.6 mV dec -1 and on/off ratio of 3.76 × 10 5 . Furthermore, enhanced device performance is obtained when the surface of the MoS 2 channel is coated by an ALD HfO 2 layer with different thicknesses (10, 15 and 20 nm), where the transistor with a 15 nm HfO 2 encapsulation layer exhibits the best overall electrical properties: μ = 42.1 cm 2 V -1 s -1 , SS = 87.9 mV dec -1 and on/off ratio of 2.72 × 10 6 . These improvements should be associated with the enhanced screening effect on charged-impurity scattering and protection from absorption of environmental gas molecules by the high-k encapsulation. The capacitance equivalent thickness of the back-gate dielectric (HfO 2 ) is only 6.58 nm, which is conducive to scaling of the MoS 2 transistors.

Pentacene-based low voltage organic field-effect transistors with anodized Ta2O5 gate dielectric

NASA Astrophysics Data System (ADS)

Jeong, Yeon Taek; Dodabalapur, Ananth

2007-11-01

Pentacene-based low voltage organic field-effect transistors were realized using an anodized Ta2O5 gate dielectric. The Ta2O5 gate dielectric layer with a surface roughness of 1.3Å was obtained by anodizing an e-beam evaporated Ta film. The device exhibited values of saturation mobility, threshold voltage, and Ion/Ioff ratio of 0.45cm2/Vs, 0.56V, and 7.5×101, respectively. The gate leakage current was reduced by more than 70% with a hexamethyldisilazane (HMDS) treatment on the Ta2O5 layer. The HMDS treatment also resulted in enhanced mobility values and a larger pentacene grain size.

Electric-field control of conductance in metal quantum point contacts by electric-double-layer gating

NASA Astrophysics Data System (ADS)

Shibata, K.; Yoshida, K.; Daiguji, K.; Sato, H.; , T., Ii; Hirakawa, K.

2017-10-01

An electric-field control of quantized conductance in metal (gold) quantum point contacts (QPCs) is demonstrated by adopting a liquid-gated electric-double-layer (EDL) transistor geometry. Atomic-scale gold QPCs were fabricated by applying the feedback-controlled electrical break junction method to the gold nanojunction. The electric conductance in gold QPCs shows quantized conductance plateaus and step-wise increase/decrease by the conductance quantum, G0 = 2e2/h, as EDL-gate voltage is swept, demonstrating a modulation of the conductance of gold QPCs by EDL gating. The electric-field control of conductance in metal QPCs may open a way for their application to local charge sensing at room temperature.

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

NASA Astrophysics Data System (ADS)

Hu, Ai-Bin; Xu, Qiu-Xia

2010-05-01

Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO2 (1 < x < 2). Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V · s) and 81.0 cm2/(V · s), respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.

Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Wei, E-mail: wwei99@jlu.edu.cn; Han, Jinhua; Ying, Jun

2014-09-22

Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm{sup 2}/V s. The unidirectional shift of turn-on voltage (V{sub on}) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (V{sub P}/V{sub E}) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered moleculemore » orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm{sup 2}/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the V{sub P}/V{sub E} of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional V{sub on} shift. As a result, an enlarged memory window of 28.6 V at the V{sub P}/V{sub E} of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.« less

Relationship between effective mobility and border traps associated with charge trapping in In0.7Ga0.3As MOSFETs with various high-κ stacks

NASA Astrophysics Data System (ADS)

Kwon, Hyuk-Min; Kim, Dae-Hyun; Kim, Tae-Woo

2018-03-01

The effective mobility and reliability characteristics of In0.7Ga0.3As quantum-well (QW) MOSFETs with various high-κ gate stacks and HEMTs with a Schottky gate under bias temperature instability (BTI) stress were investigated. The effective mobilities (μeff) of HEMTs, single-layer Al2O3, bilayer Al2O3 (0.6 nm)/HfO2 (2.0 nm), and Al2O3 (0.6 nm)/HfO2 (3.0 nm) were ˜9000, ˜6158, ˜4789, and ˜4447 cm2 V-1 s-1 at N inv = 1.5 × 1012/cm2, respectively. The maximum effective mobility of In0.7Ga0.3As channel MOSFETs was compared with that of In0.7Ga0.3As/In0.48Al0.52As HEMTs, which are interface and border trap-free FETs. The results showed that the effective channel mobility was sensitive to traps in high-κ dielectrics related to interface trap density and border traps in the oxide. The ΔV T degradation of the bilayer Al2O3/HfO2 under BTI stress was greater than that of a single Al2O3 layer because the HfO2 layer had a high density of oxygen vacancies which were related to border traps.

Structural and electrical properties of atomic layer deposited Al-doped ZrO2 films and of the interface with TaN electrode

NASA Astrophysics Data System (ADS)

Spiga, S.; Rao, R.; Lamagna, L.; Wiemer, C.; Congedo, G.; Lamperti, A.; Molle, A.; Fanciulli, M.; Palma, F.; Irrera, F.

2012-07-01

Al-doped ZrO2 (Al-ZrO2) films deposited by atomic layer deposition onto silicon substrates and the interface with the TaN metal gate are investigated. In particular, structural properties of as-grown and annealed films in the 6-26 nm thickness range, as well as leakage and capacitive behavior of metal-oxide-semiconductor stacks are characterized. As-deposited Al-ZrO2 films in the mentioned thickness range are amorphous and crystallize in the ZrO2 cubic phase after thermal treatment at 900 °C. Correspondingly, the dielectric constant (k) value increases from 20 ± 1 to 27 ± 2. The Al-ZrO2 layers exhibit uniform composition through the film thickness and are thermally stable on Si, whereas chemical reactions take place at the TaN/Al-ZrO2 interface. A transient capacitance technique is adopted for monitoring charge trapping and flat band instability at short and long time scales. The role of traps nearby the TaN/Al-ZrO2 interface is discussed and compared with other metal/high-k oxide films. Further, analytical modeling of the flat band voltage shift with a power-law dependence on time allows extracting features of bulk traps close to the silicon/oxide interface, which exhibit energy levels in the 1.4-1.9 eV range above the valence band of the Al-ZrO2.

Biologically sensitive field-effect transistors: from ISFETs to NanoFETs.

PubMed

Pachauri, Vivek; Ingebrandt, Sven

2016-06-30

Biologically sensitive field-effect transistors (BioFETs) are one of the most abundant classes of electronic sensors for biomolecular detection. Most of the time these sensors are realized as classical ion-sensitive field-effect transistors (ISFETs) having non-metallized gate dielectrics facing an electrolyte solution. In ISFETs, a semiconductor material is used as the active transducer element covered by a gate dielectric layer which is electronically sensitive to the (bio-)chemical changes that occur on its surface. This review will provide a brief overview of the history of ISFET biosensors with general operation concepts and sensing mechanisms. We also discuss silicon nanowire-based ISFETs (SiNW FETs) as the modern nanoscale version of classical ISFETs, as well as strategies to functionalize them with biologically sensitive layers. We include in our discussion other ISFET types based on nanomaterials such as carbon nanotubes, metal oxides and so on. The latest examples of highly sensitive label-free detection of deoxyribonucleic acid (DNA) molecules using SiNW FETs and single-cell recordings for drug screening and other applications of ISFETs will be highlighted. Finally, we suggest new device platforms and newly developed, miniaturized read-out tools with multichannel potentiometric and impedimetric measurement capabilities for future biomedical applications. © 2016 The Author(s). Published by Portland Press Limited on behalf of the Biochemical Society.

Biologically sensitive field-effect transistors: from ISFETs to NanoFETs

PubMed Central

Pachauri, Vivek

2016-01-01

Biologically sensitive field-effect transistors (BioFETs) are one of the most abundant classes of electronic sensors for biomolecular detection. Most of the time these sensors are realized as classical ion-sensitive field-effect transistors (ISFETs) having non-metallized gate dielectrics facing an electrolyte solution. In ISFETs, a semiconductor material is used as the active transducer element covered by a gate dielectric layer which is electronically sensitive to the (bio-)chemical changes that occur on its surface. This review will provide a brief overview of the history of ISFET biosensors with general operation concepts and sensing mechanisms. We also discuss silicon nanowire-based ISFETs (SiNW FETs) as the modern nanoscale version of classical ISFETs, as well as strategies to functionalize them with biologically sensitive layers. We include in our discussion other ISFET types based on nanomaterials such as carbon nanotubes, metal oxides and so on. The latest examples of highly sensitive label-free detection of deoxyribonucleic acid (DNA) molecules using SiNW FETs and single-cell recordings for drug screening and other applications of ISFETs will be highlighted. Finally, we suggest new device platforms and newly developed, miniaturized read-out tools with multichannel potentiometric and impedimetric measurement capabilities for future biomedical applications. PMID:27365038

Static Noise Margin Enhancement by Flex-Pass-Gate SRAM

NASA Astrophysics Data System (ADS)

O'Uchi, Shin-Ichi; Masahara, Meishoku; Sakamoto, Kunihiro; Endo, Kazuhiko; Liu, Yungxun; Matsukawa, Takashi; Sekigawa, Toshihiro; Koike, Hanpei; Suzuki, Eiichi

A Flex-Pass-Gate SRAM, i.e. a fin-type-field-effect-transistor- (FinFET-) based SRAM, is proposed to enhance noise margin during both read and write operations. In its cell, the flip-flop is composed of usual three-terminal- (3T-) FinFETs while pass gates are composed of four-terminal- (4T-) FinFETs. The 4T-FinFETs enable to adopt a dynamic threshold-voltage control in the pass gates. During a write operation, the threshold voltage of the pass gates is lowered to enhance the writing speed and stability. During the read operation, on the other hand, the threshold voltage is raised to enhance the static noise margin. An asymmetric-oxide 4T-FinFET is helpful to manage the leakage current through the pass gate. In this paper, a design strategy of the pass gate with an asymmetric gate oxide is considered, and a TCAD-based Monte Carlo simulation reveals that the Flex-Pass-Gate SRAM based on that design strategy is expected to be effective in half-pitch 32-nm technology for low-standby-power (LSTP) applications, even taking into account the variability in the device performance.

Stable indium oxide thin-film transistors with fast threshold voltage recovery

NASA Astrophysics Data System (ADS)

Vygranenko, Yuriy; Wang, Kai; Nathan, Arokia

2007-12-01

Stable thin-film transistors (TFTs) with semiconducting indium oxide channel and silicon dioxide gate dielectric were fabricated by reactive ion beam assisted evaporation and plasma-enhanced chemical vapor deposition. The field-effect mobility is 3.3cm2/Vs, along with an on/off current ratio of 106, and subthreshold slope of 0.5V/decade. When subject to long-term gate bias stress, the TFTs show fast recovery of the threshold voltage (VT) when relaxed without annealing, suggesting that charge trapping at the interface and/or in the bulk gate dielectric to be the dominant mechanism underlying VT instability. Device performance and stability make indium oxide TFTs promising for display applications.

Ferroelectric switching of poly(vinylidene difluoride-trifluoroethylene) in metal-ferroelectric-semiconductor non-volatile memories with an amorphous oxide semiconductor

NASA Astrophysics Data System (ADS)

Gelinck, G. H.; van Breemen, A. J. J. M.; Cobb, B.

2015-03-01

Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

Programmable Schottky Junctions Based on Ferroelectric Gated MoS2 Transistors

NASA Astrophysics Data System (ADS)

Xiao, Zhiyong; Song, Jingfeng; Drcharme, Stephen; Hong, Xia

We report a programmable Schottky junction based on MoS2 field effect transistors with a SiO2 back gate and a ferroelectric copolymer poly(vinylidene-fluoride-trifluorethylene) (PVDF) top gate. We fabricated mechanically exfoliated single layer MoS2 flakes into two point devices via e-beam lithography, and deposited on the top of the devices ~20 nm PVDF thin films. The polarization of the PVDF layer is controlled locally by conducting atomic force microscopy. The devices exhibit linear ID-VD characteristics when the ferroelectric gate is uniformly polarized in one direction. We then polarized the gate into two domains with opposite polarization directions, and observed that the ID-VD characteristics of the MoS2 channel can be modulated between linear and rectified behaviors depending on the back gate voltage. The nonlinear ID-VD relation emerges when half of the channel is in the semiconductor phase while the other half is in the metallic phase, and it can be well described by the thermionic emission model with a Schottky barrier of ~0.5 eV. The Schottky junction can be erased by re-write the entire channel in the uniform polarization state. Our study facilitates the development of programmable, multifunctional nanoelectronics based on layered 2D TMDs..

Three-Dimensional Flexible Complementary Metal-Oxide-Semiconductor Logic Circuits Based On Two-Layer Stacks of Single-Walled Carbon Nanotube Networks.

PubMed

Zhao, Yudan; Li, Qunqing; Xiao, Xiaoyang; Li, Guanhong; Jin, Yuanhao; Jiang, Kaili; Wang, Jiaping; Fan, Shoushan

2016-02-23

We have proposed and fabricated stable and repeatable, flexible, single-walled carbon nanotube (SWCNT) thin film transistor (TFT) complementary metal-oxide-semiconductor (CMOS) integrated circuits based on a three-dimensional (3D) structure. Two layers of SWCNT-TFT devices were stacked, where one layer served as n-type devices and the other one served as p-type devices. On the basis of this method, it is able to save at least half of the area required to construct an inverter and make large-scale and high-density integrated CMOS circuits easier to design and manufacture. The 3D flexible CMOS inverter gain can be as high as 40, and the total noise margin is more than 95%. Moreover, the input and output voltage of the inverter are exactly matched for cascading. 3D flexible CMOS NOR, NAND logic gates, and 15-stage ring oscillators were fabricated on PI substrates with high performance as well. Stable electrical properties of these circuits can be obtained with bending radii as small as 3.16 mm, which shows that such a 3D structure is a reliable architecture and suitable for carbon nanotube electrical applications in complex flexible and wearable electronic devices.

A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered Zr x Si1- x O2 Gate dielectric and improved electrical and hysteresis performance

NASA Astrophysics Data System (ADS)

Hung, Chien-Hsiung; Wang, Shui-Jinn; Liu, Pang-Yi; Wu, Chien-Hung; Wu, Nai-Sheng; Yan, Hao-Ping; Lin, Tseng-Hsing

2017-04-01

The use of co-sputtered zirconium silicon oxide (Zr x Si1- x O2) gate dielectrics to improve the gate controllability of amorphous indium gallium zinc oxide (α-IGZO) thin-film transistors (TFTs) through a room-temperature fabrication process is proposed and demonstrated. With the sputtering power of the SiO2 target in the range of 0-150 W and with that of the ZrO2 target kept at 100 W, a dielectric constant ranging from approximately 28.1 to 7.8 is obtained. The poly-structure formation immunity of the Zr x Si1- x O2 dielectrics, reduction of the interface trap density suppression, and gate leakage current are examined. Our experimental results reveal that the Zr0.85Si0.15O2 gate dielectric can lead to significantly improved TFT subthreshold swing performance (103 mV/dec) and field effect mobility (33.76 cm2 V-1 s-1).

Near-IR squaraine dye–loaded gated periodic mesoporous organosilica for photo-oxidation of phenol in a continuous-flow device

PubMed Central

Borah, Parijat; Sreejith, Sivaramapanicker; Anees, Palapuravan; Menon, Nishanth Venugopal; Kang, Yuejun; Ajayaghosh, Ayyappanpillai; Zhao, Yanli

2015-01-01

Periodic mesoporous organosilica (PMO) has been widely used for the fabrication of a variety of catalytically active materials. We report the preparation of novel photo-responsive PMO with azobenzene-gated pores. Upon activation, the azobenzene gate undergoes trans-cis isomerization, which allows an unsymmetrical near-infrared squaraine dye (Sq) to enter into the pores. The gate closure by cis-trans isomerization of the azobenzene unit leads to the safe loading of the monomeric dye inside the pores. The dye-loaded and azobenzene-gated PMO (Sq-azo@PMO) exhibits excellent generation of reactive oxygen species upon excitation at 664 nm, which can be effectively used for the oxidation of phenol into benzoquinone in aqueous solution. Furthermore, Sq-azo@PMO as the catalyst was placed inside a custom-built, continuous-flow device to carry out the photo-oxidation of phenol to benzoquinone in the presence of 664-nm light. By using the device, about 23% production of benzoquinone with 100% selectivity was achieved. The current research presents a prototype of transforming heterogeneous catalysts toward practical use. PMID:26601266

Design, fabrication, and evaluation of charge-coupled devices with aluminum-anodized-aluminum gates

NASA Technical Reports Server (NTRS)

Gassaway, J. D.; Causey, W. H., Jr.

1977-01-01

A 4-phase, 49 1/2 bit CCD shift register was designed and fabricated using two levels of aluminum metallization with anodic Al2O3 insulation separating the layers. Test circuitry was also designed and constructed. A numerical analysis of an MOS-RC transmission line was made and results are given to characterize performance for various conductivities. The electrical design of the CCD included a low-noise dual-gate input and a balanced floating diffusion output circuit. Metallization was accomplished both by low voltage DC sputtering and thermal evaporation. The audization was according to published procedures using a buffered tartaric acid bath. Approximately 20 wafers were processed with 50 complete chips per wafer. All devices failed by shorting between the metal levels at some point. Experimental procedures eliminated temperature effects from sintering and drying, anodic oxide thickness, edge effects, photoresist stripping procedures, and metallization techniques as the primary causes of failure. It was believed from a study of SEM images that protuberances (hillocks) grow up from the first level metal through the oxide either causing a direct short or producing a weak, highly stressed insulation point which fails at low voltage. The cause of these hillocks is unknown; however, they have been observed to grow during temperature excursions to 470 C.

Steep-slope hysteresis-free negative capacitance MoS2 transistors

NASA Astrophysics Data System (ADS)

Si, Mengwei; Su, Chun-Jung; Jiang, Chunsheng; Conrad, Nathan J.; Zhou, Hong; Maize, Kerry D.; Qiu, Gang; Wu, Chien-Ting; Shakouri, Ali; Alam, Muhammad A.; Ye, Peide D.

2018-01-01

The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV dec-1 at room temperature and therefore precludes lowering of the supply voltage and overall power consumption1,2. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier3. Meanwhile, two-dimensional semiconductors such as atomically thin transition-metal dichalcogenides, due to their low dielectric constant and ease of integration into a junctionless transistor topology, offer enhanced electrostatic control of the channel4-12. Here, we combine these two advantages and demonstrate a molybdenum disulfide (MoS2) two-dimensional steep-slope transistor with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack. This device exhibits excellent performance in both on and off states, with a maximum drain current of 510 μA μm-1 and a sub-thermionic subthreshold slope, and is essentially hysteresis-free. Negative differential resistance was observed at room temperature in the MoS2 negative-capacitance FETs as the result of negative capacitance due to the negative drain-induced barrier lowering. A high on-current-induced self-heating effect was also observed and studied.

Self-aligned top-gate amorphous indium zinc oxide thin-film transistors exceeding low-temperature poly-Si transistor performance.

PubMed

Park, Jae Chul; Lee, Ho-Nyeon; Im, Seongil

2013-08-14

Thin-film transistor (TFT) is a key component of active-matrix flat-panel displays (AMFPDs). These days, the low-temperature poly silicon (LTPS) TFTs are to match with advanced AMFPDs such as the active matrix organic light-emitting diode (AMOLED) display, because of their high mobility for fast pixel switching. However, the manufacturing process of LTPS TFT is quite complicated, costly, and scale-limited. Amorphous oxide semiconductor (AOS) TFT technology is another candidate, which is as simple as that of conventioanl amorphous (a)-Si TFTs in fabrication but provides much superior device performances to those of a-Si TFTs. Hence, various AOSs have been compared with LTPS for active channel layer of the advanced TFTs, but have always been found to be relatively inferior to LTPS. In the present work, we clear the persistent inferiority, innovating the device performaces of a-IZO TFT by adopting a self-aligned coplanar top-gate structure and modifying the surface of a-IZO material. Herein, we demonstrate a high-performance simple-processed a-IZO TFT with mobility of ∼157 cm(2) V(-1) s(-1), SS of ∼190 mV dec(-1), and good bias/photostabilities, which overall surpass the performances of high-cost LTPS TFTs.

Interaction of Black Phosphorus with Oxygen and Water

DOE PAGES

Huang, Yuan; Qiao, Jingsi; He, Kai; ...

2016-10-24

Black phosphorus (BP) has attracted significant interest as a monolayer or few-layer material with extraordinary electrical and optoelectronic properties. Chemical reactions with different ambient species, notably oxygen and water, are important as they govern key properties such as stability in air, electronic structure and charge transport, wetting by aqueous solutions, etc. Here, we report experiments combined with ab-initio calculations that address the effects of oxygen and water in contact with BP. Our results show that the reaction with oxygen is primarily responsible for changing properties of BP. Oxidation involving the dissociative chemisorption of O 2 causes the decomposition of BPmore » and continuously lowers the conductance of BP field-effect transistors (FETs). In contrast, BP is stable in contact with deaerated (i.e., O 2 depleted) water and the carrier mobility in BP FETs gated by H 2O increases significantly due to efficient dielectric screening of scattering centers by the high-k dielectric. Isotope labeling experiments, contact angle measurements and calculations show that the pristine BP surface is hydrophobic, but is turned progressively hydrophilic by oxidation. Lastly, our results open new avenues for exploring applications that require contact of BP with aqueous solutions including solution gating, electrochemistry, and solution-phase approaches for exfoliation, dispersion, and delivery of BP.« less

Reversible formation of ammonium persulfate/sulfuric acid graphite intercalation compounds and their peculiar Raman spectra.

PubMed

Dimiev, Ayrat M; Bachilo, Sergei M; Saito, Riichiro; Tour, James M

2012-09-25

Graphite intercalation compounds (GICs) can be considered stacks of individual doped graphene layers. Here we demonstrate a reversible formation of sulfuric acid-based GICs using ammonium persulfate as the chemical oxidizing agent. No covalent chemical oxidation leading to the formation of graphite oxide occurs, which inevitably happens when other compounds such as potassium permanganate are used to charge carbon layers. The resulting acid/persulfate-induced stage-1 and stage-2 GICs are characterized by suppression of the 2D band in the Raman spectra and by unusually strong enhancement of the G band. The G band is selectively enhanced at different doping levels with different excitations. These observations are in line with recent reports for chemically doped and gate-modulated graphene and support newly proposed theories of Raman processes. At the same time GICs have some advantageous differences over graphene, which are demonstrated in this report. Our experimental observations, along with earlier reported data, suggest that at high doping levels the G band cannot be used as the reference peak for normalizing Raman spectra, which is a commonly used practice today. A Fermi energy shift of 1.20-1.25 eV and ∼1.0 eV was estimated for the stage-1 and stage-2 GICs, respectively, from the Raman and optical spectroscopy data.

Changes in the distribution of type II transmembrane serine protease, TMPRSS2 and in paracellular permeability in IPEC-J2 cells exposed to oxidative stress.

PubMed

Paszti-Gere, Erzsebet; Barna, Reka Fanni; Kovago, Csaba; Szauder, Ipoly; Ujhelyi, Gabriella; Jakab, Csaba; Meggyesházi, Nóra; Szekacs, Andras

2015-04-01

The effect of oxidative stress on barrier integrity and localization of transmembrane serine proteinase 2 (TMPRSS2) were studied using porcine epithelial IPEC-J2 cells on membrane inserts. Increased paracellular permeability of FITC-dextran 4 kDa (fluorescence intensity 43,508 ± 2,391 versus 3,550 ± 759) and that of gentamicin (3.41 ± 0.06 % increase to controls) were measured parallel with the reduced transepithelial electrical resistance (23.3 ± 4.06 % decrease) of cell layers 6 h after 1 h 1 mM H2O2 treatment. The immunohistochemical localization of adherens junctional β-catenin was not affected by reactive oxygen species (ROS) up to 4 mM H2O2. Peroxide-triggered enhanced paracellular permeability of IPEC-J2 cell layer was accompanied by predominantly cytoplasmic occurrence of TMPRSS2 embedded in cell membrane under physiological conditions. These results support that ROS can influence paracellular gate opening via multifaceted mode of action without involvement of β-catenin redistribution in adherens junction. Altered distribution pattern of TMPRSS2 and relocalized transmembrane serine protease activity may contribute to weakening of epithelial barrier integrity under acute oxidative stress.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Ao; Liu, Guoxia, E-mail: gxliu@qdu.edu.cn, E-mail: fukaishan@yahoo.com; Zhu, Huihui

Solution-processed p-type oxide semiconductors have recently attracted increasing interests for the applications in low-cost optoelectronic devices and low-power consumption complementary metal-oxide-semiconductor circuits. In this work, p-type nickel oxide (NiO{sub x}) thin films were prepared using low-temperature solution process and integrated as the channel layer in thin-film transistors (TFTs). The electrical properties of NiO{sub x} TFTs, together with the characteristics of NiO{sub x} thin films, were systematically investigated as a function of annealing temperature. By introducing aqueous high-k aluminum oxide (Al{sub 2}O{sub 3}) gate dielectric, the electrical performance of NiO{sub x} TFT was improved significantly compared with those based on SiO{submore » 2} dielectric. Particularly, the hole mobility was found to be 60 times enhancement, quantitatively from 0.07 to 4.4 cm{sup 2}/V s, which is mainly beneficial from the high areal capacitance of the Al{sub 2}O{sub 3} dielectric and high-quality NiO{sub x}/Al{sub 2}O{sub 3} interface. This simple solution-based method for producing p-type oxide TFTs is promising for next-generation oxide-based electronic applications.« less

In-depth analysis and modelling of self-heating effects in nanometric DGMOSFETs

NASA Astrophysics Data System (ADS)

Roldán, J. B.; González, B.; Iñiguez, B.; Roldán, A. M.; Lázaro, A.; Cerdeira, A.

2013-01-01

Self-heating effects (SHEs) in nanometric symmetrical double-gate MOSFETs (DGMOSFETs) have been analysed. An equivalent thermal circuit for the transistors has been developed to characterise thermal effects, where the temperature and thickness dependency of the thermal conductivity of the silicon and oxide layers within the devices has been included. The equivalent thermal circuit is consistent with simulations using a commercial technology computer-aided design (TCAD) tool (Sentaurus by Synopsys). In addition, a model for DGMOSFETs has been developed where SHEs have been considered in detail, taking into account the temperature dependence of the low-field mobility, saturation velocity, and inversion charge. The model correctly reproduces Sentaurus simulation data for the typical bias range used in integrated circuits. Lattice temperatures predicted by simulation are coherently reproduced by the model for varying silicon layer geometry.

Field Effect Transistors Using Atomically Thin Layers of Copper Indium Selenide (CuInSe)

NASA Astrophysics Data System (ADS)

Patil, Prasanna; Ghosh, Sujoy; Wasala, Milinda; Lei, Sidong; Vajtai, Robert; Ajayan, Pulickel; Talapatra, Saikat

We will report fabrication of field-effect transistors (FETs) using few-layers of Copper Indium Selenide (CuInSe) flakes exfoliated from crystals grown using chemical vapor transport technique. Our transport measurements indicate n-type FET with electron mobility µ ~ 3 cm2 V-1 s-1 at room temperature when Silicon dioxide (SiO2) is used as a back gate. Mobility can be further increased significantly when ionic liquid 1-Butyl-3-methylimidazolium hexafluorophosphate (BMIM-PF6) is used as top gate. Similarly subthreshold swing can be further improved from 103 V/dec to 0.55 V/dec by using ionic liquid as a top gate. We also found ON/OFF ratio of ~ 102 for both top and back gate. Comparison between ionic liquid top gate and SiO2 back gate will be presented and discussed. This work is supported by the U.S. Army Research Office through a MURI Grant # W911NF-11-1-0362.

Suspended sub-50 nm vanadium dioxide membrane transistors: fabrication and ionic liquid gating studies

NASA Astrophysics Data System (ADS)

Sim, Jai S.; Zhou, You; Ramanathan, Shriram

2012-10-01

We demonstrate a robust lithographic patterning method to fabricate self-supported sub-50 nm VO2 membranes that undergo a phase transition. Utilizing such self-supported membranes, we directly observed a shift in the metal-insulator transition temperature arising from stress relaxation and consistent opening of the hysteresis. Electric double layer transistors were then fabricated with the membranes and compared to thin film devices. The ionic liquid allowed reversible modulation of channel resistance and distinguishing bulk processes from the surface effects. From the shift in the metal-insulator transition temperature, the carrier density doped through electrolyte gating is estimated to be 1 × 1020 cm-3. Hydrogen annealing studies showed little difference in resistivity between the film and the membrane indicating rapid diffusion of hydrogen in the vanadium oxide rutile lattice consistent with previous observations. The ability to fabricate electrically-wired, suspended VO2 ultra-thin membranes creates new opportunities to study mesoscopic size effects on phase transitions and may also be of interest in sensor devices.

Degradation of CMOS image sensors in deep-submicron technology due to γ-irradiation

NASA Astrophysics Data System (ADS)

Rao, Padmakumar R.; Wang, Xinyang; Theuwissen, Albert J. P.

2008-09-01

In this work, radiation induced damage mechanisms in deep submicron technology is resolved using finger gated-diodes (FGDs) as a radiation sensitive tool. It is found that these structures are simple yet efficient structures to resolve radiation induced damage in advanced CMOS processes. The degradation of the CMOS image sensors in deep-submicron technology due to γ-ray irradiation is studied by developing a model for the spectral response of the sensor and also by the dark-signal degradation as a function of STI (shallow-trench isolation) parameters. It is found that threshold shifts in the gate-oxide/silicon interface as well as minority carrier life-time variations in the silicon bulk are minimal. The top-layer material properties and the photodiode Si-SiO2 interface quality are degraded due to γ-ray irradiation. Results further suggest that p-well passivated structures are inevitable for radiation-hard designs. It was found that high electrical fields in submicron technologies pose a threat to high quality imaging in harsh environments.

A pH sensor with a double-gate silicon nanowire field-effect transistor

NASA Astrophysics Data System (ADS)

Ahn, Jae-Hyuk; Kim, Jee-Yeon; Seol, Myeong-Lok; Baek, David J.; Guo, Zheng; Kim, Chang-Hoon; Choi, Sung-Jin; Choi, Yang-Kyu

2013-02-01

A pH sensor composed of a double-gate silicon nanowire field-effect transistor (DG Si-NW FET) is demonstrated. The proposed DG Si-NW FET allows the independent addressing of the gate voltage and hence improves the sensing capability through an application of asymmetric gate voltage between the two gates. One gate is a driving gate which controls the current flow, and the other is a supporting gate which amplifies the shift of the threshold voltage, which is a sensing metric, and which arises from changes in the pH. The pH signal is also amplified through modulation of the gate oxide thickness.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gelinck, G. H., E-mail: Gerwin.Gelinck@tno.nl; Department of Applied Physics, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven; Breemen, A. J. J. M. van

Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

The Influence of Hafnium Doping on Density of States in Zinc Oxide Thin-Film Transistors Deposited via Atomic Layer Deposition.

PubMed

Ding, Xingwei; Qin, Cunping; Song, Jiantao; Zhang, Jianhua; Jiang, Xueyin; Zhang, Zhilin

2017-12-01

Thin-film transistors (TFTs) with atomic layer deposition (ALD) HfZnO (HZO) as channel layer and Al 2 O 3 as gate insulator were successfully fabricated. Compared with ZnO-TFT, the stability of HZO-TFT was obviously improved as Hf doping can suppress the generation of oxygen related defects. The transfer characteristics of TFTs at different temperatures were also investigated, and temperature stability enhancement was observed for the TFT with Hf doping. The density of states (DOS) was calculated based on the experimentally obtained E a , which can explain the experimental observation. A high-field effect mobility of 9.4 cm 2 /Vs, a suitable turn-on voltage of 0.26 V, a high on/off ratio of over 10 7 and a steep sub-threshold swing of 0.3 V/decade were obtained in HZO-TFT. The results showed that temperature stability enhancement in HfZnO thin-film transistors are attributed to the smaller DOS.

The Influence of Hafnium Doping on Density of States in Zinc Oxide Thin-Film Transistors Deposited via Atomic Layer Deposition

NASA Astrophysics Data System (ADS)

Ding, Xingwei; Qin, Cunping; Song, Jiantao; Zhang, Jianhua; Jiang, Xueyin; Zhang, Zhilin

2017-01-01

Thin-film transistors (TFTs) with atomic layer deposition (ALD) HfZnO (HZO) as channel layer and Al2O3 as gate insulator were successfully fabricated. Compared with ZnO-TFT, the stability of HZO-TFT was obviously improved as Hf doping can suppress the generation of oxygen related defects. The transfer characteristics of TFTs at different temperatures were also investigated, and temperature stability enhancement was observed for the TFT with Hf doping. The density of states (DOS) was calculated based on the experimentally obtained E a, which can explain the experimental observation. A high-field effect mobility of 9.4 cm2/Vs, a suitable turn-on voltage of 0.26 V, a high on/off ratio of over 107 and a steep sub-threshold swing of 0.3 V/decade were obtained in HZO-TFT. The results showed that temperature stability enhancement in HfZnO thin-film transistors are attributed to the smaller DOS.

Growth of IZO/IGZO dual-active-layer for low-voltage-drive and high-mobility thin film transistors based on an ALD grown Al2O3 gate insulator

NASA Astrophysics Data System (ADS)

Ding, Xingwei; Zhang, Hao; Ding, He; Zhang, Jianhua; Huang, Chuanxin; Shi, Weimin; Li, Jun; Jiang, Xueyin; Zhang, Zhilin

2014-12-01

We successfully integrated the high-performance oxide thin film transistors with novel IZO/IGZO dual-active-layers. The results showed that dual-active-layer (IZO/IGZO) TFTs, compared with single active layer IGZO TFTs and IZO TFTs, exhibited the excellent performances; specifically, a high field effect mobility of 14.4 cm2/Vs, a suitable threshold voltage of 0.8 V, a high on/off ratio of more than 107, a steep sub-threshold swing of 0.13 V/dec, and a substantially small threshold voltage shift of 0.51 V after temperature stress from 293 K to 353 K. In order to understand the superior performance, the density-of-states (DOS) were investigated based on the temperature-dependent transfer curves. The superior electric properties were attributed to the smaller DOS and higher carrier concentration. The proposed IZO/IGZO-TFT in this paper can be used as driving devices in the next-generation flat panel displays.

Assessment of pseudo-bilayer structures in the heterogate germanium electron-hole bilayer tunnel field-effect transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Padilla, J. L., E-mail: jose.padilladelatorre@epfl.ch; Alper, C.; Ionescu, A. M.

2015-06-29

We investigate the effect of pseudo-bilayer configurations at low operating voltages (≤0.5 V) in the heterogate germanium electron-hole bilayer tunnel field-effect transistor (HG-EHBTFET) compared to the traditional bilayer structures of EHBTFETs arising from semiclassical simulations where the inversion layers for electrons and holes featured very symmetric profiles with similar concentration levels at the ON-state. Pseudo-bilayer layouts are attained by inducing a certain asymmetry between the top and the bottom gates so that even though the hole inversion layer is formed at the bottom of the channel, the top gate voltage remains below the required value to trigger the formation of themore » inversion layer for electrons. Resulting benefits from this setup are improved electrostatic control on the channel, enhanced gate-to-gate efficiency, and higher I{sub ON} levels. Furthermore, pseudo-bilayer configurations alleviate the difficulties derived from confining very high opposite carrier concentrations in very thin structures.« less

Impact of gate work-function on memory characteristics in Al2O3/HfOx/Al2O3/graphene charge-trap memory devices

NASA Astrophysics Data System (ADS)

Lee, Sejoon; Song, Emil B.; Kim, Sungmin; Seo, David H.; Seo, Sunae; Won Kang, Tae; Wang, Kang L.

2012-01-01

Graphene-based non-volatile memory devices composed of a single-layer graphene channel and an Al2O3/HfOx/Al2O3 charge-storage layer exhibit memory functionality. The impact of the gate material's work-function (Φ) on the memory characteristics is investigated using different types of metals [Ti (ΦTi = 4.3 eV) and Ni (ΦNi = 5.2 eV)]. The ambipolar carrier conduction of graphene results in an enlargement of memory window (ΔVM), which is ˜4.5 V for the Ti-gate device and ˜9.1 V for the Ni-gate device. The increase in ΔVM is attributed to the change in the flat-band condition and the suppression of electron back-injection within the gate stack.

Effect of nanocomposite gate-dielectric properties on pentacene microstructure and field-effect transistor characteristics.

PubMed

Lee, Wen-Hsi; Wang, Chun-Chieh

2010-02-01

In this study, the effect of surface energy and roughness of the nanocomposite gate dielectric on pentacene morphology and electrical properties of pentacene OTFT are reported. Nanoparticles TiO2 were added in the polyimide matrix to form a nanocomposite which has a significantly different surface characteristic from polyimide, leading to a discrepancy in the structural properties of pentacene growth. A growth mode of pentacene deposited on the nanocomposite is proposed to explain successfully the effect of surface properties of nanocomposite gate dielectric such as surface energy and roughness on the pentacene morphology and electrical properties of OTFT. To obtain the lower surface energy and smoother surface of nanocomposite gate dielectric that is responsible for the desired crystalline, microstructure of pentacene and electrical properties of device, a bottom contact OTFT-pentacene deposited on the double-layer nanocomposite gate dielectric consisting of top smoothing layer of the neat polyimide and bottom layer of (PI+ nano-TiO2 particles) nanocomposite has been successfully demonstrated to exhibit very promising performance including high current on to off ratio of about 6 x 10(5), threshold voltage of -10 V and moderately high filed mobility of 0.15 cm2V(-1)s(-1).

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Controllable Edge Oxidation and Bubbling Exfoliation Enable the Fabrication of High Quality Water Dispersible Graphene

PubMed Central

Tian, Suyun; Sun, Jing; Yang, Siwei; He, Peng; Wang, Gang; Di, Zengfeng; Ding, Guqiao; Xie, Xiaoming; Jiang, Mianheng

2016-01-01

Despite significant progresses made on mass production of chemically exfoliated graphene, the quality, cost and environmental friendliness remain major challenges for its market penetration. Here, we present a fast and green exfoliation strategy for large scale production of high quality water dispersible few layer graphene through a controllable edge oxidation and localized gas bubbling process. Mild edge oxidation guarantees that the pristine sp2 lattice is largely intact and the edges are functionalized with hydrophilic groups, giving rise to high conductivity and good water dispersibility at the same time. The aqueous concentration can be as high as 5.0 mg mL−1, which is an order of magnitude higher than previously reports. The water soluble graphene can be directly spray-coated on various substrates, and the back-gated field effect transistor give hole and electron mobility of ~496 and ~676 cm2 V−1 s−1, respectively. These results achieved are expected to expedite various applications of graphene. PMID:27666869

Controllable Edge Oxidation and Bubbling Exfoliation Enable the Fabrication of High Quality Water Dispersible Graphene.

PubMed

Tian, Suyun; Sun, Jing; Yang, Siwei; He, Peng; Wang, Gang; Di, Zengfeng; Ding, Guqiao; Xie, Xiaoming; Jiang, Mianheng

2016-09-26

Despite significant progresses made on mass production of chemically exfoliated graphene, the quality, cost and environmental friendliness remain major challenges for its market penetration. Here, we present a fast and green exfoliation strategy for large scale production of high quality water dispersible few layer graphene through a controllable edge oxidation and localized gas bubbling process. Mild edge oxidation guarantees that the pristine sp 2 lattice is largely intact and the edges are functionalized with hydrophilic groups, giving rise to high conductivity and good water dispersibility at the same time. The aqueous concentration can be as high as 5.0 mg mL -1 , which is an order of magnitude higher than previously reports. The water soluble graphene can be directly spray-coated on various substrates, and the back-gated field effect transistor give hole and electron mobility of ~496 and ~676 cm 2 V -1 s -1 , respectively. These results achieved are expected to expedite various applications of graphene.

I-V curve hysteresis induced by gate-free charging of GaAs nanowires' surface oxide

NASA Astrophysics Data System (ADS)

Alekseev, P. A.; Geydt, P.; Dunaevskiy, M. S.; Lähderanta, E.; Haggrén, T.; Kakko, J.-P.; Lipsanen, H.

2017-09-01

The control of nanowire-based device performance requires knowledge about the transport of charge carriers and its limiting factors. We present the experimental and modeled results of a study of electrical properties of GaAs nanowires (NWs), considering their native oxide cover. Measurements of individual vertical NWs were performed by conductive atomic force microscopy (C-AFM). Experimental C-AFM observations with numerical simulations revealed the complex resistive behavior of NWs. A hysteresis of current-voltage characteristics of the p-doped NWs as-grown on substrates with different types of doping was registered. The emergence of hysteresis was explained by the trapping of majority carriers in the surface oxide layer near the reverse-biased barriers under the source-drain current. It was found that the accumulation of charge increases the current for highly doped p+-NWs on n+-substrates, while for moderately doped p-NWs on p+-substrates, charge accumulation decreases the current due to blocking of the conductive channel of NWs.

Thin-Film Transistors Fabricated Using Sputter Deposition of Zinc Oxide

NASA Astrophysics Data System (ADS)

Xiao, Nan

2013-01-01

Development of thin film transistors (TFTs) with conventional channel layer materials, such as amorphous silicon (a-Si) and polysilicon (poly-Si), has been extensively investigated. A-Si TFT currently serves the large flat panel industry; however advanced display products are demanding better TFT performance because of the associated low electron mobility of a-Si. This has motivated interest in semiconducting metal oxides, such as Zinc Oxide (ZnO), for TFT backplanes. This work involves the fabrication and characterization of TFTs using ZnO deposited by sputtering. An overview of the process details and results from recently fabricated TFTs following a full-factorial designed experiment will be presented. Material characterization and analysis of electrical results will be described. The investigated process variables were the gate dielectric and ZnO sputtering process parameters including power density and oxygen partial pressure. Electrical results showed clear differences in treatment combinations, with certain I-V characteristics demonstrating superior performance to preliminary work. A study of device stability will also be discussed.

Controllable Edge Oxidation and Bubbling Exfoliation Enable the Fabrication of High Quality Water Dispersible Graphene

NASA Astrophysics Data System (ADS)

Tian, Suyun; Sun, Jing; Yang, Siwei; He, Peng; Wang, Gang; di, Zengfeng; Ding, Guqiao; Xie, Xiaoming; Jiang, Mianheng

2016-09-01

Despite significant progresses made on mass production of chemically exfoliated graphene, the quality, cost and environmental friendliness remain major challenges for its market penetration. Here, we present a fast and green exfoliation strategy for large scale production of high quality water dispersible few layer graphene through a controllable edge oxidation and localized gas bubbling process. Mild edge oxidation guarantees that the pristine sp2 lattice is largely intact and the edges are functionalized with hydrophilic groups, giving rise to high conductivity and good water dispersibility at the same time. The aqueous concentration can be as high as 5.0 mg mL-1, which is an order of magnitude higher than previously reports. The water soluble graphene can be directly spray-coated on various substrates, and the back-gated field effect transistor give hole and electron mobility of ~496 and ~676 cm2 V-1 s-1, respectively. These results achieved are expected to expedite various applications of graphene.

CMOS Active-Pixel Image Sensor With Simple Floating Gates

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Investigation of interface property in Al/SiO2/ n-SiC structure with thin gate oxide by illumination

NASA Astrophysics Data System (ADS)

Chang, P. K.; Hwu, J. G.

2017-04-01

The reverse tunneling current of Al/SiO2/ n-SiC structure employing thin gate oxide is introduced to examine the interface property by illumination. The gate current at negative bias decreases under blue LED illumination, yet increases under UV lamp illumination. Light-induced electrons captured by interface states may be emitted after the light sources are off, leading to the recovery of gate currents. Based on transient characteristics of gate current, the extracted trap level is close to the light energy for blue LED, indicating that electron capture induced by lighting may result in the reduction of gate current. Furthermore, bidirectional C- V measurements exhibit a positive voltage shift caused by electron trapping under blue LED illumination, while a negative voltage shift is observed under UV lamp illumination. Distinct trapping and detrapping behaviors can be observed from variations in I- V and C- V curves utilizing different light sources for 4H-SiC MOS capacitors with thin insulators.

The electrical and interfacial properties of metal-high-k oxide-semiconductor field effect transistors with CeO2/HfO2 laminated gate dielectrics

NASA Astrophysics Data System (ADS)

Chang, Ingram Yin-ku; Chen, Chun-Heng; Chiu, Fu-Chien; Lee, Joseph Ya-min

2007-11-01

Metal-oxide-semiconductor field-effect transistors with CeO2/HfO2 laminated gate dielectrics were fabricated. The transistors have a subthreshold slope of 74.9mV/decade. The interfacial properties were measured using gated diodes. The surface state density Dit was 9.78×1011cm-2eV-1. The surface-recombination velocity (s0) and the minority carrier lifetime in the field-induced depletion region (τ0,FIJ) measured from the gated diode were about 6.11×103cm /s and 1.8×10-8s, respectively. The effective capture cross section of surface state (σs) extracted using the subthreshold-swing measurement and the gated diode was about 7.69×10-15cm2. The effective electron mobility of CeO2/HfO2 laminated gated transistors was determined to be 212cm2/Vs.

Characterization of a Common-Gate Amplifier Using Ferroelectric Transistors

NASA Technical Reports Server (NTRS)

Hunt, Mitchell; Sayyah, Rana; MacLeod, Todd C.; Ho, Fat D.

2011-01-01

In this paper, the empirical data collected through experiments performed using a FeFET in the common-gate amplifier circuit is presented. The FeFET common-gate amplifier was characterized by varying all parameters in the circuit, such as load resistance, biasing of the transistor, and input voltages. Due to the polarization of the ferroelectric layer, the particular behavior of the FeFET common-gate amplifier presents interesting results. Furthermore, the differences between a FeFET common-gate amplifier and a MOSFET common-gate amplifier are examined.

Mechanism of oxide thickness and temperature dependent current conduction in n+-polySi/SiO2/p-Si structures — a new analysis

NASA Astrophysics Data System (ADS)

Samanta, Piyas

2017-10-01

The conduction mechanism of gate leakage current through thermally grown silicon dioxide (SiO2) films on (100) p-type silicon has been investigated in detail under negative bias on the degenerately doped n-type polysilicon (n+-polySi) gate. The analysis utilizes the measured gate current density J G at high oxide fields E ox in 5.4 to 12 nm thick SiO2 films between 25 and 300 °C. The leakage current measured up to 300 °C was due to Fowler-Nordheim (FN) tunneling of electrons from the accumulated n +-polySi gate in conjunction with Poole Frenkel (PF) emission of trapped-electrons from the electron traps located at energy levels ranging from 0.6 to 1.12 eV (depending on the oxide thickness) below the SiO2 conduction band (CB). It was observed that PF emission current I PF dominates FN electron tunneling current I FN at oxide electric fields E ox between 6 and 10 MV/cm and throughout the temperature range studied here. Understanding of the mechanism of leakage current conduction through SiO2 films plays a crucial role in simulation of time-dependent dielectric breakdown (TDDB) of metaloxide-semiconductor (MOS) devices and to precisely predict the normal operating field or applied gate voltage for lifetime projection of the MOS integrated circuits.

Physical and electrical characterizations of AlGaN/GaN MOS gate stacks with AlGaN surface oxidation treatment

NASA Astrophysics Data System (ADS)

Yamada, Takahiro; Watanabe, Kenta; Nozaki, Mikito; Shih, Hong-An; Nakazawa, Satoshi; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

The impacts of inserting ultrathin oxides into insulator/AlGaN interfaces on their electrical properties were investigated to develop advanced AlGaN/GaN metal–oxide–semiconductor (MOS) gate stacks. For this purpose, the initial thermal oxidation of AlGaN surfaces in oxygen ambient was systematically studied by synchrotron radiation X-ray photoelectron spectroscopy (SR-XPS) and atomic force microscopy (AFM). Our physical characterizations revealed that, when compared with GaN surfaces, aluminum addition promotes the initial oxidation of AlGaN surfaces at temperatures of around 400 °C, followed by smaller grain growth above 850 °C. Electrical measurements of AlGaN/GaN MOS capacitors also showed that, although excessive oxidation treatment of AlGaN surfaces over around 700 °C has an adverse effect, interface passivation with the initial oxidation of the AlGaN surfaces at temperatures ranging from 400 to 500 °C was proven to be beneficial for fabricating high-quality AlGaN/GaN MOS gate stacks.

PVA:LiClO4: a robust, high Tg polymer electrolyte for adjustable ion gating of 2D materials

NASA Astrophysics Data System (ADS)

Kinder, Erich; Fullerton, Susan; CenterLow Energy Systems Technology Team

2015-03-01

Polymer electrolytes are an effective way to gate organic semiconductors and nanomaterials, such as nanotubes and 2D materials, by establishing an electrostatic double layer with large capacitance. Widely used solid electrolytes, such as those based on polyethylene oxide, have a glass transition temperature below room temperature. This permits relatively fast ion mobility at T = 23 °C, but requires a constant applied field to maintain a doping profile. Moreover, PEO-based electrolytes cannot withstand a variety of solvents, limiting its use. Here, we demonstrate a polymer electrolyte using polyvinyl alcohol (PVA) with Tg >23 °C, through which a doping profile can be defined by a potential applied when the polymer is heated above Tg, then ``locked-in'' by cooling the electrolyte to room temperature (

Near-thermal limit gating in heavily doped III-V semiconductor nanowires using polymer electrolytes

NASA Astrophysics Data System (ADS)

Ullah, A. R.; Carrad, D. J.; Krogstrup, P.; Nygârd, J.; Micolich, A. P.

2018-02-01

Doping is a common route to reducing nanowire transistor on-resistance but it has limits. A high doping level gives significant loss in gate performance and ultimately complete gate failure. We show that electrolyte gating remains effective even when the Be doping in our GaAs nanowires is so high that traditional metal-oxide gates fail. In this regime we obtain a combination of subthreshold swing and contact resistance that surpasses the best existing p -type nanowire metal-oxide semiconductor field-effect transistors (MOSFETs). Our subthreshold swing of 75 mV/dec is within 25 % of the room-temperature thermal limit and comparable with n -InP and n -GaAs nanowire MOSFETs. Our results open a new path to extending the performance and application of nanowire transistors, and motivate further work on improved solid electrolytes for nanoscale device applications.

Analyzing Single-Event Gate Ruptures In Power MOSFET's

NASA Technical Reports Server (NTRS)

Zoutendyk, John A.

1993-01-01

Susceptibilities of power metal-oxide/semiconductor field-effect transistors (MOSFET's) to single-event gate ruptures analyzed by exposing devices to beams of energetic bromine ions while applying appropriate bias voltages to source, gate, and drain terminals and measuring current flowing into or out of each terminal.

Ion Sensitive Transparent-Gate Transistor for Visible Cell Sensing.

PubMed

Sakata, Toshiya; Nishimura, Kotaro; Miyazawa, Yuuya; Saito, Akiko; Abe, Hiroyuki; Kajisa, Taira

2017-04-04

In this study, we developed an ion-sensitive transparent-gate transistor (IS-TGT) for visible cell sensing. The gate sensing surface of the IS-TGT is transparent in a solution because a transparent amorphous oxide semiconductor composed of amorphous In-Ga-Zn-oxide (a-IGZO) with a thin SiO 2 film gate that includes an indium tin oxide (ITO) film as the source and drain electrodes is utilized. The pH response of the IS-TGT was found to be about 56 mV/pH, indicating approximately Nernstian response. Moreover, the potential signals of the IS-TGT for sodium and potassium ions, which are usually included in biological environments, were evaluated. The optical and electrical properties of the IS-TGT enable cell functions to be monitored simultaneously with microscopic observation and electrical measurement. A platform based on the IS-TGT can be used as a simple and cost-effective plate-cell-sensing system based on thin-film fabrication technology in the research field of life science.

Comparative Study of HfTa-based gate-dielectric Ge metal-oxide-semiconductor capacitors with and without AlON interlayer

NASA Astrophysics Data System (ADS)

Xu, J. P.; Zhang, X. F.; Li, C. X.; Chan, C. L.; Lai, P. T.

2010-04-01

The electrical properties and high-field reliability of HfTa-based gate-dielectric metal-oxide-semiconductor (MOS) devices with and without AlON interlayer on Ge substrate are investigated. Experimental results show that the MOS capacitor with HfTaON/AlON stack gate dielectric exhibits low interface-state/oxide-charge densities, low gate leakage, small capacitance equivalent thickness (˜1.1 nm), and high dielectric constant (˜20). All of these should be attributed to the blocking role of the ultrathin AlON interlayer against interdiffusions of Ge, Hf, and Ta and penetration of O into the Ge substrate, with the latter effectively suppressing the unintentional formation of unstable poor-quality low- k GeO x and giving a superior AlON/Ge interface. Moreover, incorporation of N into both the interlayer and high- k dielectric further improves the device reliability under high-field stress through the formation of strong N-related bonds.

Electrically tunable coherent optical absorption in graphene with ion gel.

PubMed

Thareja, Vrinda; Kang, Ju-Hyung; Yuan, Hongtao; Milaninia, Kaveh M; Hwang, Harold Y; Cui, Yi; Kik, Pieter G; Brongersma, Mark L

2015-03-11

We demonstrate electrical control over coherent optical absorption in a graphene-based Salisbury screen consisting of a single layer of graphene placed in close proximity to a gold back reflector. The screen was designed to enhance light absorption at a target wavelength of 3.2 μm by using a 600 nm-thick, nonabsorbing silica spacer layer. An ionic gel layer placed on top of the screen was used to electrically gate the charge density in the graphene layer. Spectroscopic reflectance measurements were performed in situ as a function of gate bias. The changes in the reflectance spectra were analyzed using a Fresnel based transfer matrix model in which graphene was treated as an infinitesimally thin sheet with a conductivity given by the Kubo formula. The analysis reveals that a careful choice of the ionic gel layer thickness can lead to optical absorption enhancements of up to 5.5 times for the Salisbury screen compared to a suspended sheet of graphene. In addition to these absorption enhancements, we demonstrate very large electrically induced changes in the optical absorption of graphene of ∼3.3% per volt, the highest attained so far in a device that features an atomically thick active layer. This is attributable in part to the more effective gating achieved with the ion gel over the conventional dielectric back gates and partially by achieving a desirable coherent absorption effect linked to the presence of the thin ion gel that boosts the absorption by 40%.

Leakage effects in n-GaAs MESFET with n-GaAs buffer layer

NASA Technical Reports Server (NTRS)

Wang, Y. C.; Bahrami, M.

1983-01-01

Whereas improvement of the interface between the active layer and the buffer layer has been demonstrated, the leakage effects can be important if the buffer layer resistivity is not sufficiently high and/or the buffer layer thickness is not sufficiently small. It was found that two buffer leakage currents exist from the channel under the gate to the source and from drain to the channel in addition to the buffer leakage resistance between drain and source. It is shown that for a 1 micron gate-length n-GaAs MESFET, if the buffer layer resistivity is 12 OHM-CM and the buffer layer thickness h is 2 microns, the performance of the device degrades drastically. It is suggested that h should be below 2 microns.

Additive/Subtractive Manufacturing Research and Development in Europe

DTIC Science & Technology

2004-12-01

electronic gates and switches. The idea is to attach a gold nanoparticle to a redox gate (molecule) that undergoes reduction and oxidation reactions...This is used to synthesize mixed metal oxides such as CeO2, Ce:Zr, ZrO2, and Pr:Ce and produce them in nanoparticle form. The fourth project that was...on glass. Laser patterning is followed by heating to diffuse the oxide into the glass. MMSC has used the direct-write of conductors on polymer

Development and characterization of ultrathin hafnium titanates as high permittivity gate insulators

NASA Astrophysics Data System (ADS)

Li, Min

High permittivity or high-kappa materials are being developed for use as gate insulators for future ultrascaled metal oxide semiconductor field effect transistors (MOSFETs). Hafnium containing compounds are the leading candidates. Due to its moderate permittivity, however, it is difficult to achieve HfO2 gate structures with an EOT well below 1.0 nm. One approach to increase HfO2 permittivity is combining it with a very high-kappa material, such as TiO2. In this thesis, we systematically studied the electrical and physical characteristics of high-kappa hafnium titanates films as gate insulators. A series of HfxTi1-xO2 films with well-controlled composition were deposited using an MOCVD system. The physical properties of the films were analyzed using a variety of characterization techniques. X-ray micro diffraction indicates that the Ti-rich thin film is more immune to crystallization. TEM analysis showed that the thick stoichiometric HfTiO 4 film has an orthorhombic structure and large anisotropic grains. The C-V curves from the devices with the hafnium titanates films displayed relatively low hysteresis. In a certain composition range, the interfacial layer (IL) EOT and permittivity of HfxTi1-x O2 increases linearly with increasing Ti. The charge is negative for HfxTi1-xO2/IL and positive for Si/IL interface, and the magnitude increases as Hf increases. For ultra-thin films (less than 2 nm EOT), the leakage current increases with increasing HE Moreover, the Hf-rich sample has weaker temperature dependence of the current. In the MOSFET devices with the hafnium titanates films, normal transistor characteristics were observed, also electron mobility degradation. Next, we investigated the effects that different pre-deposition surface treatments, including HF dipping, NH3 surface nitridation, and HfO2 deposition, have on the electrical properties of hafnium titanates. Surface nitridation shows stronger effect than the thin HfO2 layer. The nitrided samples displayed a negative flat band voltage shift and larger hysteresis relative to the HF-dipped samples. The IL EOT reduction by mtridation increases with increasing HE Surface nitridation also induces extra charge, more considerable at the Si/IL interface. The leakage current is reduced in the Hf-rich samples with a nitride layer. Electron mobility degradation by surface nitridation was also observed.

Electrostatically Gated Graphene-Zinc Oxide Nanowire Heterojunction.

PubMed

You, Xueqiu; Pak, James Jungho

2015-03-01

This paper presents an electrostatically gated graphene-ZnO nanowire (NW) heterojunction for the purpose of device applications for the first time. A sub-nanometer-thick energy barrier width was formed between a monatomic graphene layer and electrochemically grown ZnO NWs. Because of the narrow energy barrier, electrons can tunnel through the barrier when a voltage is applied across the junction. A near-ohmic current-voltage (I-V) curve was obtained from the graphene-electrochemically grown ZnO NW heterojunction. This near-ohmic contact changed to asymmetric I-V Schottky contact when the samples were exposed to an oxygen environment. It is believed that the adsorbed oxygen atoms or molecules on the ZnO NW surface capture free electrons of the ZnO NWs, thereby creating a depletion region in the ZnO NWs. Consequentially, the electron concentration in the ZnO NWs is dramatically reduced, and the energy barrier width of the graphene-ZnO NW heterojunction increases greatly. This increased energy barrier width reduces the electron tunneling probability, resulting in a typical Schottky contact. By adjusting the back-gate voltage to control the graphene-ZnO NW Schottky energy barrier height, a large modulation on the junction current (on/off ratio of 10(3)) was achieved.

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

NASA Astrophysics Data System (ADS)

Nedic, Stanko; Tea Chun, Young; Hong, Woong-Ki; Chu, Daping; Welland, Mark

2014-01-01

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ˜16.5 V, a high drain current on/off ratio of ˜105, a gate leakage current below ˜300 pA, and excellent retention characteristics for over 104 s.

Fredkin and Toffoli Gates Implemented in Oregonator Model of Belousov-Zhabotinsky Medium

NASA Astrophysics Data System (ADS)

Adamatzky, Andrew

A thin-layer Belousov-Zhabotinsky (BZ) medium is a powerful computing device capable for implementing logical circuits, memory, image processors, robot controllers, and neuromorphic architectures. We design the reversible logical gates — Fredkin gate and Toffoli gate — in a BZ medium network of excitable channels with subexcitable junctions. Local control of the BZ medium excitability is an important feature of the gates’ design. An excitable thin-layer BZ medium responds to a localized perturbation with omnidirectional target or spiral excitation waves. A subexcitable BZ medium responds to an asymmetric perturbation by producing traveling localized excitation wave-fragments similar to dissipative solitons. We employ interactions between excitation wave-fragments to perform the computation. We interpret the wave-fragments as values of Boolean variables. The presence of a wave-fragment at a given site of a circuit represents the logical truth, absence of the wave-fragment — logically false. Fredkin gate consists of ten excitable channels intersecting at 11 junctions, eight of which are subexcitable. Toffoli gate consists of six excitable channels intersecting at six junctions, four of which are subexcitable. The designs of the gates are verified using numerical integration of two-variable Oregonator equations.

Inorganic proton conducting electrolyte coupled oxide-based dendritic transistors for synaptic electronics.

PubMed

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2014-05-07

Ionic/electronic hybrid devices with synaptic functions are considered to be the essential building blocks for neuromorphic systems and brain-inspired computing. Here, artificial synapses based on indium-zinc-oxide (IZO) transistors gated by nanogranular SiO2 proton-conducting electrolyte films are fabricated on glass substrates. Spike-timing dependent plasticity and paired-pulse facilitation are successfully mimicked in an individual bottom-gate transistor. Most importantly, dynamic logic and dendritic integration established by spatiotemporally correlated spikes are also mimicked in dendritic transistors with two in-plane gates as the presynaptic input terminals.